drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  54 };
  55
  56 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  57         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  58         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  59         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  60         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  61         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  62 };
  63
  64 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  65         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  66         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  67         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  68         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  69         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  70         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  71 };
  72
  73 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  74         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  75         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  76         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  77         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  78         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  80 };
  81
  82 static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are the same */
  83         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  84         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  85         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  86         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  87         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  88         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  89 };
  90
  91 /* IIR can theoretically queue up two events. Be paranoid. */
  92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
  93         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
  94         POSTING_READ(GEN8_##type##_IMR(which)); \
  95         I915_WRITE(GEN8_##type##_IER(which), 0); \
  96         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  97         POSTING_READ(GEN8_##type##_IIR(which)); \
  98         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  99         POSTING_READ(GEN8_##type##_IIR(which)); \
 100 } while (0)
 101
 102 #define GEN5_IRQ_RESET(type) do { \
 103         I915_WRITE(type##IMR, 0xffffffff); \
 104         POSTING_READ(type##IMR); \
 105         I915_WRITE(type##IER, 0); \
 106         I915_WRITE(type##IIR, 0xffffffff); \
 107         POSTING_READ(type##IIR); \
 108         I915_WRITE(type##IIR, 0xffffffff); \
 109         POSTING_READ(type##IIR); \
 110 } while (0)
 111
 112 /*
 113  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 114  */
 115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
 116         u32 val = I915_READ(reg); \
 117         if (val) { \
 118                 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
 119                      (reg), val); \
 120                 I915_WRITE((reg), 0xffffffff); \
 121                 POSTING_READ(reg); \
 122                 I915_WRITE((reg), 0xffffffff); \
 123                 POSTING_READ(reg); \
 124         } \
 125 } while (0)
 126
 127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 128         GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
 129         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 130         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 131         POSTING_READ(GEN8_##type##_IMR(which)); \
 132 } while (0)
 133
 134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 135         GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
 136         I915_WRITE(type##IER, (ier_val)); \
 137         I915_WRITE(type##IMR, (imr_val)); \
 138         POSTING_READ(type##IMR); \
 139 } while (0)
 140
 141 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 142
 143 /* For display hotplug interrupt */
 144 void
 145 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 146 {
 147         assert_spin_locked(&dev_priv->irq_lock);
 148
 149         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 150                 return;
 151
 152         if ((dev_priv->irq_mask & mask) != 0) {
 153                 dev_priv->irq_mask &= ~mask;
 154                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 155                 POSTING_READ(DEIMR);
 156         }
 157 }
 158
 159 void
 160 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 161 {
 162         assert_spin_locked(&dev_priv->irq_lock);
 163
 164         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 165                 return;
 166
 167         if ((dev_priv->irq_mask & mask) != mask) {
 168                 dev_priv->irq_mask |= mask;
 169                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 170                 POSTING_READ(DEIMR);
 171         }
 172 }
 173
 174 /**
 175  * ilk_update_gt_irq - update GTIMR
 176  * @dev_priv: driver private
 177  * @interrupt_mask: mask of interrupt bits to update
 178  * @enabled_irq_mask: mask of interrupt bits to enable
 179  */
 180 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 181                               uint32_t interrupt_mask,
 182                               uint32_t enabled_irq_mask)
 183 {
 184         assert_spin_locked(&dev_priv->irq_lock);
 185
 186         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 187
 188         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 189                 return;
 190
 191         dev_priv->gt_irq_mask &= ~interrupt_mask;
 192         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 193         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 194         POSTING_READ(GTIMR);
 195 }
 196
 197 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 198 {
 199         ilk_update_gt_irq(dev_priv, mask, mask);
 200 }
 201
 202 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 203 {
 204         ilk_update_gt_irq(dev_priv, mask, 0);
 205 }
 206
 207 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
 208 {
 209         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 210 }
 211
 212 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
 213 {
 214         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 215 }
 216
 217 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
 218 {
 219         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 220 }
 221
 222 /**
 223   * snb_update_pm_irq - update GEN6_PMIMR
 224   * @dev_priv: driver private
 225   * @interrupt_mask: mask of interrupt bits to update
 226   * @enabled_irq_mask: mask of interrupt bits to enable
 227   */
 228 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 229                               uint32_t interrupt_mask,
 230                               uint32_t enabled_irq_mask)
 231 {
 232         uint32_t new_val;
 233
 234         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 235
 236         assert_spin_locked(&dev_priv->irq_lock);
 237
 238         new_val = dev_priv->pm_irq_mask;
 239         new_val &= ~interrupt_mask;
 240         new_val |= (~enabled_irq_mask & interrupt_mask);
 241
 242         if (new_val != dev_priv->pm_irq_mask) {
 243                 dev_priv->pm_irq_mask = new_val;
 244                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
 245                 POSTING_READ(gen6_pm_imr(dev_priv));
 246         }
 247 }
 248
 249 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 250 {
 251         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 252                 return;
 253
 254         snb_update_pm_irq(dev_priv, mask, mask);
 255 }
 256
 257 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
 258                                   uint32_t mask)
 259 {
 260         snb_update_pm_irq(dev_priv, mask, 0);
 261 }
 262
 263 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 264 {
 265         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 266                 return;
 267
 268         __gen6_disable_pm_irq(dev_priv, mask);
 269 }
 270
 271 void gen6_reset_rps_interrupts(struct drm_device *dev)
 272 {
 273         struct drm_i915_private *dev_priv = dev->dev_private;
 274         uint32_t reg = gen6_pm_iir(dev_priv);
 275
 276         spin_lock_irq(&dev_priv->irq_lock);
 277         I915_WRITE(reg, dev_priv->pm_rps_events);
 278         I915_WRITE(reg, dev_priv->pm_rps_events);
 279         POSTING_READ(reg);
 280         spin_unlock_irq(&dev_priv->irq_lock);
 281 }
 282
 283 void gen6_enable_rps_interrupts(struct drm_device *dev)
 284 {
 285         struct drm_i915_private *dev_priv = dev->dev_private;
 286
 287         spin_lock_irq(&dev_priv->irq_lock);
 288
 289         WARN_ON(dev_priv->rps.pm_iir);
 290         WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 291         dev_priv->rps.interrupts_enabled = true;
 292         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
 293                                 dev_priv->pm_rps_events);
 294         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 295
 296         spin_unlock_irq(&dev_priv->irq_lock);
 297 }
 298
 299 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 300 {
 301         /*
 302          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
 303          * if GEN6_PM_UP_EI_EXPIRED is masked.
 304          *
 305          * TODO: verify if this can be reproduced on VLV,CHV.
 306          */
 307         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
 308                 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
 309
 310         if (INTEL_INFO(dev_priv)->gen >= 8)
 311                 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
 312
 313         return mask;
 314 }
 315
 316 void gen6_disable_rps_interrupts(struct drm_device *dev)
 317 {
 318         struct drm_i915_private *dev_priv = dev->dev_private;
 319
 320         spin_lock_irq(&dev_priv->irq_lock);
 321         dev_priv->rps.interrupts_enabled = false;
 322         spin_unlock_irq(&dev_priv->irq_lock);
 323
 324         cancel_work_sync(&dev_priv->rps.work);
 325
 326         spin_lock_irq(&dev_priv->irq_lock);
 327
 328         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
 329
 330         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 331         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
 332                                 ~dev_priv->pm_rps_events);
 333         I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
 334         I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
 335
 336         dev_priv->rps.pm_iir = 0;
 337
 338         spin_unlock_irq(&dev_priv->irq_lock);
 339 }
 340
 341 /**
 342  * ibx_display_interrupt_update - update SDEIMR
 343  * @dev_priv: driver private
 344  * @interrupt_mask: mask of interrupt bits to update
 345  * @enabled_irq_mask: mask of interrupt bits to enable
 346  */
 347 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 348                                   uint32_t interrupt_mask,
 349                                   uint32_t enabled_irq_mask)
 350 {
 351         uint32_t sdeimr = I915_READ(SDEIMR);
 352         sdeimr &= ~interrupt_mask;
 353         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 354
 355         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 356
 357         assert_spin_locked(&dev_priv->irq_lock);
 358
 359         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 360                 return;
 361
 362         I915_WRITE(SDEIMR, sdeimr);
 363         POSTING_READ(SDEIMR);
 364 }
 365
 366 static void
 367 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 368                        u32 enable_mask, u32 status_mask)
 369 {
 370         u32 reg = PIPESTAT(pipe);
 371         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 372
 373         assert_spin_locked(&dev_priv->irq_lock);
 374         WARN_ON(!intel_irqs_enabled(dev_priv));
 375
 376         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 377                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 378                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 379                       pipe_name(pipe), enable_mask, status_mask))
 380                 return;
 381
 382         if ((pipestat & enable_mask) == enable_mask)
 383                 return;
 384
 385         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 386
 387         /* Enable the interrupt, clear any pending status */
 388         pipestat |= enable_mask | status_mask;
 389         I915_WRITE(reg, pipestat);
 390         POSTING_READ(reg);
 391 }
 392
 393 static void
 394 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 395                         u32 enable_mask, u32 status_mask)
 396 {
 397         u32 reg = PIPESTAT(pipe);
 398         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 399
 400         assert_spin_locked(&dev_priv->irq_lock);
 401         WARN_ON(!intel_irqs_enabled(dev_priv));
 402
 403         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 404                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 405                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 406                       pipe_name(pipe), enable_mask, status_mask))
 407                 return;
 408
 409         if ((pipestat & enable_mask) == 0)
 410                 return;
 411
 412         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 413
 414         pipestat &= ~enable_mask;
 415         I915_WRITE(reg, pipestat);
 416         POSTING_READ(reg);
 417 }
 418
 419 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 420 {
 421         u32 enable_mask = status_mask << 16;
 422
 423         /*
 424          * On pipe A we don't support the PSR interrupt yet,
 425          * on pipe B and C the same bit MBZ.
 426          */
 427         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 428                 return 0;
 429         /*
 430          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 431          * A the same bit is for perf counters which we don't use either.
 432          */
 433         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 434                 return 0;
 435
 436         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 437                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 438                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 439         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 440                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 441         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 442                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 443
 444         return enable_mask;
 445 }
 446
 447 void
 448 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 449                      u32 status_mask)
 450 {
 451         u32 enable_mask;
 452
 453         if (IS_VALLEYVIEW(dev_priv->dev))
 454                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 455                                                            status_mask);
 456         else
 457                 enable_mask = status_mask << 16;
 458         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 459 }
 460
 461 void
 462 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 463                       u32 status_mask)
 464 {
 465         u32 enable_mask;
 466
 467         if (IS_VALLEYVIEW(dev_priv->dev))
 468                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 469                                                            status_mask);
 470         else
 471                 enable_mask = status_mask << 16;
 472         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 473 }
 474
 475 /**
 476  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 477  */
 478 static void i915_enable_asle_pipestat(struct drm_device *dev)
 479 {
 480         struct drm_i915_private *dev_priv = dev->dev_private;
 481
 482         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 483                 return;
 484
 485         spin_lock_irq(&dev_priv->irq_lock);
 486
 487         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 488         if (INTEL_INFO(dev)->gen >= 4)
 489                 i915_enable_pipestat(dev_priv, PIPE_A,
 490                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 491
 492         spin_unlock_irq(&dev_priv->irq_lock);
 493 }
 494
 495 /*
 496  * This timing diagram depicts the video signal in and
 497  * around the vertical blanking period.
 498  *
 499  * Assumptions about the fictitious mode used in this example:
 500  *  vblank_start >= 3
 501  *  vsync_start = vblank_start + 1
 502  *  vsync_end = vblank_start + 2
 503  *  vtotal = vblank_start + 3
 504  *
 505  *           start of vblank:
 506  *           latch double buffered registers
 507  *           increment frame counter (ctg+)
 508  *           generate start of vblank interrupt (gen4+)
 509  *           |
 510  *           |          frame start:
 511  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 512  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 513  *           |          |
 514  *           |          |  start of vsync:
 515  *           |          |  generate vsync interrupt
 516  *           |          |  |
 517  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 518  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 519  * ----va---> <-----------------vb--------------------> <--------va-------------
 520  *       |          |       <----vs----->                     |
 521  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 522  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 523  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 524  *       |          |                                         |
 525  *       last visible pixel                                   first visible pixel
 526  *                  |                                         increment frame counter (gen3/4)
 527  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 528  *
 529  * x  = horizontal active
 530  * _  = horizontal blanking
 531  * hs = horizontal sync
 532  * va = vertical active
 533  * vb = vertical blanking
 534  * vs = vertical sync
 535  * vbs = vblank_start (number)
 536  *
 537  * Summary:
 538  * - most events happen at the start of horizontal sync
 539  * - frame start happens at the start of horizontal blank, 1-4 lines
 540  *   (depending on PIPECONF settings) after the start of vblank
 541  * - gen3/4 pixel and frame counter are synchronized with the start
 542  *   of horizontal active on the first line of vertical active
 543  */
 544
 545 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 546 {
 547         /* Gen2 doesn't have a hardware frame counter */
 548         return 0;
 549 }
 550
 551 /* Called from drm generic code, passed a 'crtc', which
 552  * we use as a pipe index
 553  */
 554 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 555 {
 556         struct drm_i915_private *dev_priv = dev->dev_private;
 557         unsigned long high_frame;
 558         unsigned long low_frame;
 559         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 560         struct intel_crtc *intel_crtc =
 561                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 562         const struct drm_display_mode *mode =
 563                 &intel_crtc->config->base.adjusted_mode;
 564
 565         htotal = mode->crtc_htotal;
 566         hsync_start = mode->crtc_hsync_start;
 567         vbl_start = mode->crtc_vblank_start;
 568         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 569                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 570
 571         /* Convert to pixel count */
 572         vbl_start *= htotal;
 573
 574         /* Start of vblank event occurs at start of hsync */
 575         vbl_start -= htotal - hsync_start;
 576
 577         high_frame = PIPEFRAME(pipe);
 578         low_frame = PIPEFRAMEPIXEL(pipe);
 579
 580         /*
 581          * High & low register fields aren't synchronized, so make sure
 582          * we get a low value that's stable across two reads of the high
 583          * register.
 584          */
 585         do {
 586                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 587                 low   = I915_READ(low_frame);
 588                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 589         } while (high1 != high2);
 590
 591         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 592         pixel = low & PIPE_PIXEL_MASK;
 593         low >>= PIPE_FRAME_LOW_SHIFT;
 594
 595         /*
 596          * The frame counter increments at beginning of active.
 597          * Cook up a vblank counter by also checking the pixel
 598          * counter against vblank start.
 599          */
 600         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 601 }
 602
 603 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 604 {
 605         struct drm_i915_private *dev_priv = dev->dev_private;
 606         int reg = PIPE_FRMCOUNT_GM45(pipe);
 607
 608         return I915_READ(reg);
 609 }
 610
 611 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 612 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 613
 614 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 615 {
 616         struct drm_device *dev = crtc->base.dev;
 617         struct drm_i915_private *dev_priv = dev->dev_private;
 618         const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
 619         enum pipe pipe = crtc->pipe;
 620         int position, vtotal;
 621
 622         vtotal = mode->crtc_vtotal;
 623         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 624                 vtotal /= 2;
 625
 626         if (IS_GEN2(dev))
 627                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 628         else
 629                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 630
 631         /*
 632          * See update_scanline_offset() for the details on the
 633          * scanline_offset adjustment.
 634          */
 635         return (position + crtc->scanline_offset) % vtotal;
 636 }
 637
 638 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 639                                     unsigned int flags, int *vpos, int *hpos,
 640                                     ktime_t *stime, ktime_t *etime)
 641 {
 642         struct drm_i915_private *dev_priv = dev->dev_private;
 643         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 645         const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
 646         int position;
 647         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 648         bool in_vbl = true;
 649         int ret = 0;
 650         unsigned long irqflags;
 651
 652         if (!intel_crtc->active) {
 653                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 654                                  "pipe %c\n", pipe_name(pipe));
 655                 return 0;
 656         }
 657
 658         htotal = mode->crtc_htotal;
 659         hsync_start = mode->crtc_hsync_start;
 660         vtotal = mode->crtc_vtotal;
 661         vbl_start = mode->crtc_vblank_start;
 662         vbl_end = mode->crtc_vblank_end;
 663
 664         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 665                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 666                 vbl_end /= 2;
 667                 vtotal /= 2;
 668         }
 669
 670         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 671
 672         /*
 673          * Lock uncore.lock, as we will do multiple timing critical raw
 674          * register reads, potentially with preemption disabled, so the
 675          * following code must not block on uncore.lock.
 676          */
 677         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 678
 679         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 680
 681         /* Get optional system timestamp before query. */
 682         if (stime)
 683                 *stime = ktime_get();
 684
 685         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 686                 /* No obvious pixelcount register. Only query vertical
 687                  * scanout position from Display scan line register.
 688                  */
 689                 position = __intel_get_crtc_scanline(intel_crtc);
 690         } else {
 691                 /* Have access to pixelcount since start of frame.
 692                  * We can split this into vertical and horizontal
 693                  * scanout position.
 694                  */
 695                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 696
 697                 /* convert to pixel counts */
 698                 vbl_start *= htotal;
 699                 vbl_end *= htotal;
 700                 vtotal *= htotal;
 701
 702                 /*
 703                  * In interlaced modes, the pixel counter counts all pixels,
 704                  * so one field will have htotal more pixels. In order to avoid
 705                  * the reported position from jumping backwards when the pixel
 706                  * counter is beyond the length of the shorter field, just
 707                  * clamp the position the length of the shorter field. This
 708                  * matches how the scanline counter based position works since
 709                  * the scanline counter doesn't count the two half lines.
 710                  */
 711                 if (position >= vtotal)
 712                         position = vtotal - 1;
 713
 714                 /*
 715                  * Start of vblank interrupt is triggered at start of hsync,
 716                  * just prior to the first active line of vblank. However we
 717                  * consider lines to start at the leading edge of horizontal
 718                  * active. So, should we get here before we've crossed into
 719                  * the horizontal active of the first line in vblank, we would
 720                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 721                  * always add htotal-hsync_start to the current pixel position.
 722                  */
 723                 position = (position + htotal - hsync_start) % vtotal;
 724         }
 725
 726         /* Get optional system timestamp after query. */
 727         if (etime)
 728                 *etime = ktime_get();
 729
 730         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 731
 732         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 733
 734         in_vbl = position >= vbl_start && position < vbl_end;
 735
 736         /*
 737          * While in vblank, position will be negative
 738          * counting up towards 0 at vbl_end. And outside
 739          * vblank, position will be positive counting
 740          * up since vbl_end.
 741          */
 742         if (position >= vbl_start)
 743                 position -= vbl_end;
 744         else
 745                 position += vtotal - vbl_end;
 746
 747         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 748                 *vpos = position;
 749                 *hpos = 0;
 750         } else {
 751                 *vpos = position / htotal;
 752                 *hpos = position - (*vpos * htotal);
 753         }
 754
 755         /* In vblank? */
 756         if (in_vbl)
 757                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 758
 759         return ret;
 760 }
 761
 762 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 763 {
 764         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 765         unsigned long irqflags;
 766         int position;
 767
 768         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 769         position = __intel_get_crtc_scanline(crtc);
 770         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 771
 772         return position;
 773 }
 774
 775 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 776                               int *max_error,
 777                               struct timeval *vblank_time,
 778                               unsigned flags)
 779 {
 780         struct drm_crtc *crtc;
 781
 782         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 783                 DRM_ERROR("Invalid crtc %d\n", pipe);
 784                 return -EINVAL;
 785         }
 786
 787         /* Get drm_crtc to timestamp: */
 788         crtc = intel_get_crtc_for_pipe(dev, pipe);
 789         if (crtc == NULL) {
 790                 DRM_ERROR("Invalid crtc %d\n", pipe);
 791                 return -EINVAL;
 792         }
 793
 794         if (!crtc->state->enable) {
 795                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 796                 return -EBUSY;
 797         }
 798
 799         /* Helper routine in DRM core does all the work: */
 800         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 801                                                      vblank_time, flags,
 802                                                      crtc,
 803                                                      &to_intel_crtc(crtc)->config->base.adjusted_mode);
 804 }
 805
 806 static bool intel_hpd_irq_event(struct drm_device *dev,
 807                                 struct drm_connector *connector)
 808 {
 809         enum drm_connector_status old_status;
 810
 811         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 812         old_status = connector->status;
 813
 814         connector->status = connector->funcs->detect(connector, false);
 815         if (old_status == connector->status)
 816                 return false;
 817
 818         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 819                       connector->base.id,
 820                       connector->name,
 821                       drm_get_connector_status_name(old_status),
 822                       drm_get_connector_status_name(connector->status));
 823
 824         return true;
 825 }
 826
 827 static void i915_digport_work_func(struct work_struct *work)
 828 {
 829         struct drm_i915_private *dev_priv =
 830                 container_of(work, struct drm_i915_private, dig_port_work);
 831         u32 long_port_mask, short_port_mask;
 832         struct intel_digital_port *intel_dig_port;
 833         int i;
 834         u32 old_bits = 0;
 835
 836         spin_lock_irq(&dev_priv->irq_lock);
 837         long_port_mask = dev_priv->long_hpd_port_mask;
 838         dev_priv->long_hpd_port_mask = 0;
 839         short_port_mask = dev_priv->short_hpd_port_mask;
 840         dev_priv->short_hpd_port_mask = 0;
 841         spin_unlock_irq(&dev_priv->irq_lock);
 842
 843         for (i = 0; i < I915_MAX_PORTS; i++) {
 844                 bool valid = false;
 845                 bool long_hpd = false;
 846                 intel_dig_port = dev_priv->hpd_irq_port[i];
 847                 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
 848                         continue;
 849
 850                 if (long_port_mask & (1 << i))  {
 851                         valid = true;
 852                         long_hpd = true;
 853                 } else if (short_port_mask & (1 << i))
 854                         valid = true;
 855
 856                 if (valid) {
 857                         enum irqreturn ret;
 858
 859                         ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
 860                         if (ret == IRQ_NONE) {
 861                                 /* fall back to old school hpd */
 862                                 old_bits |= (1 << intel_dig_port->base.hpd_pin);
 863                         }
 864                 }
 865         }
 866
 867         if (old_bits) {
 868                 spin_lock_irq(&dev_priv->irq_lock);
 869                 dev_priv->hpd_event_bits |= old_bits;
 870                 spin_unlock_irq(&dev_priv->irq_lock);
 871                 schedule_work(&dev_priv->hotplug_work);
 872         }
 873 }
 874
 875 /*
 876  * Handle hotplug events outside the interrupt handler proper.
 877  */
 878 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 879
 880 static void i915_hotplug_work_func(struct work_struct *work)
 881 {
 882         struct drm_i915_private *dev_priv =
 883                 container_of(work, struct drm_i915_private, hotplug_work);
 884         struct drm_device *dev = dev_priv->dev;
 885         struct drm_mode_config *mode_config = &dev->mode_config;
 886         struct intel_connector *intel_connector;
 887         struct intel_encoder *intel_encoder;
 888         struct drm_connector *connector;
 889         bool hpd_disabled = false;
 890         bool changed = false;
 891         u32 hpd_event_bits;
 892
 893         mutex_lock(&mode_config->mutex);
 894         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 895
 896         spin_lock_irq(&dev_priv->irq_lock);
 897
 898         hpd_event_bits = dev_priv->hpd_event_bits;
 899         dev_priv->hpd_event_bits = 0;
 900         list_for_each_entry(connector, &mode_config->connector_list, head) {
 901                 intel_connector = to_intel_connector(connector);
 902                 if (!intel_connector->encoder)
 903                         continue;
 904                 intel_encoder = intel_connector->encoder;
 905                 if (intel_encoder->hpd_pin > HPD_NONE &&
 906                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 907                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 908                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 909                                  "switching from hotplug detection to polling\n",
 910                                 connector->name);
 911                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 912                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 913                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 914                         hpd_disabled = true;
 915                 }
 916                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 917                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 918                                       connector->name, intel_encoder->hpd_pin);
 919                 }
 920         }
 921          /* if there were no outputs to poll, poll was disabled,
 922           * therefore make sure it's enabled when disabling HPD on
 923           * some connectors */
 924         if (hpd_disabled) {
 925                 drm_kms_helper_poll_enable(dev);
 926                 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
 927                                  msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 928         }
 929
 930         spin_unlock_irq(&dev_priv->irq_lock);
 931
 932         list_for_each_entry(connector, &mode_config->connector_list, head) {
 933                 intel_connector = to_intel_connector(connector);
 934                 if (!intel_connector->encoder)
 935                         continue;
 936                 intel_encoder = intel_connector->encoder;
 937                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 938                         if (intel_encoder->hot_plug)
 939                                 intel_encoder->hot_plug(intel_encoder);
 940                         if (intel_hpd_irq_event(dev, connector))
 941                                 changed = true;
 942                 }
 943         }
 944         mutex_unlock(&mode_config->mutex);
 945
 946         if (changed)
 947                 drm_kms_helper_hotplug_event(dev);
 948 }
 949
 950 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 951 {
 952         struct drm_i915_private *dev_priv = dev->dev_private;
 953         u32 busy_up, busy_down, max_avg, min_avg;
 954         u8 new_delay;
 955
 956         spin_lock(&mchdev_lock);
 957
 958         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 959
 960         new_delay = dev_priv->ips.cur_delay;
 961
 962         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 963         busy_up = I915_READ(RCPREVBSYTUPAVG);
 964         busy_down = I915_READ(RCPREVBSYTDNAVG);
 965         max_avg = I915_READ(RCBMAXAVG);
 966         min_avg = I915_READ(RCBMINAVG);
 967
 968         /* Handle RCS change request from hw */
 969         if (busy_up > max_avg) {
 970                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 971                         new_delay = dev_priv->ips.cur_delay - 1;
 972                 if (new_delay < dev_priv->ips.max_delay)
 973                         new_delay = dev_priv->ips.max_delay;
 974         } else if (busy_down < min_avg) {
 975                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 976                         new_delay = dev_priv->ips.cur_delay + 1;
 977                 if (new_delay > dev_priv->ips.min_delay)
 978                         new_delay = dev_priv->ips.min_delay;
 979         }
 980
 981         if (ironlake_set_drps(dev, new_delay))
 982                 dev_priv->ips.cur_delay = new_delay;
 983
 984         spin_unlock(&mchdev_lock);
 985
 986         return;
 987 }
 988
 989 static void notify_ring(struct drm_device *dev,
 990                         struct intel_engine_cs *ring)
 991 {
 992         if (!intel_ring_initialized(ring))
 993                 return;
 994
 995         trace_i915_gem_request_notify(ring);
 996
 997         wake_up_all(&ring->irq_queue);
 998 }
 999
1000 static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
1001                             struct intel_rps_ei *rps_ei)
1002 {
1003         u32 cz_ts, cz_freq_khz;
1004         u32 render_count, media_count;
1005         u32 elapsed_render, elapsed_media, elapsed_time;
1006         u32 residency = 0;
1007
1008         cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1009         cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
1010
1011         render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1012         media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1013
1014         if (rps_ei->cz_clock == 0) {
1015                 rps_ei->cz_clock = cz_ts;
1016                 rps_ei->render_c0 = render_count;
1017                 rps_ei->media_c0 = media_count;
1018
1019                 return dev_priv->rps.cur_freq;
1020         }
1021
1022         elapsed_time = cz_ts - rps_ei->cz_clock;
1023         rps_ei->cz_clock = cz_ts;
1024
1025         elapsed_render = render_count - rps_ei->render_c0;
1026         rps_ei->render_c0 = render_count;
1027
1028         elapsed_media = media_count - rps_ei->media_c0;
1029         rps_ei->media_c0 = media_count;
1030
1031         /* Convert all the counters into common unit of milli sec */
1032         elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1033         elapsed_render /=  cz_freq_khz;
1034         elapsed_media /= cz_freq_khz;
1035
1036         /*
1037          * Calculate overall C0 residency percentage
1038          * only if elapsed time is non zero
1039          */
1040         if (elapsed_time) {
1041                 residency =
1042                         ((max(elapsed_render, elapsed_media) * 100)
1043                                 / elapsed_time);
1044         }
1045
1046         return residency;
1047 }
1048
1049 /**
1050  * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1051  * busy-ness calculated from C0 counters of render & media power wells
1052  * @dev_priv: DRM device private
1053  *
1054  */
1055 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1056 {
1057         u32 residency_C0_up = 0, residency_C0_down = 0;
1058         int new_delay, adj;
1059
1060         dev_priv->rps.ei_interrupt_count++;
1061
1062         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1063
1064
1065         if (dev_priv->rps.up_ei.cz_clock == 0) {
1066                 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1067                 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1068                 return dev_priv->rps.cur_freq;
1069         }
1070
1071
1072         /*
1073          * To down throttle, C0 residency should be less than down threshold
1074          * for continous EI intervals. So calculate down EI counters
1075          * once in VLV_INT_COUNT_FOR_DOWN_EI
1076          */
1077         if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1078
1079                 dev_priv->rps.ei_interrupt_count = 0;
1080
1081                 residency_C0_down = vlv_c0_residency(dev_priv,
1082                                                      &dev_priv->rps.down_ei);
1083         } else {
1084                 residency_C0_up = vlv_c0_residency(dev_priv,
1085                                                    &dev_priv->rps.up_ei);
1086         }
1087
1088         new_delay = dev_priv->rps.cur_freq;
1089
1090         adj = dev_priv->rps.last_adj;
1091         /* C0 residency is greater than UP threshold. Increase Frequency */
1092         if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1093                 if (adj > 0)
1094                         adj *= 2;
1095                 else
1096                         adj = 1;
1097
1098                 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1099                         new_delay = dev_priv->rps.cur_freq + adj;
1100
1101                 /*
1102                  * For better performance, jump directly
1103                  * to RPe if we're below it.
1104                  */
1105                 if (new_delay < dev_priv->rps.efficient_freq)
1106                         new_delay = dev_priv->rps.efficient_freq;
1107
1108         } else if (!dev_priv->rps.ei_interrupt_count &&
1109                         (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1110                 if (adj < 0)
1111                         adj *= 2;
1112                 else
1113                         adj = -1;
1114                 /*
1115                  * This means, C0 residency is less than down threshold over
1116                  * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1117                  */
1118                 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1119                         new_delay = dev_priv->rps.cur_freq + adj;
1120         }
1121
1122         return new_delay;
1123 }
1124
1125 static void gen6_pm_rps_work(struct work_struct *work)
1126 {
1127         struct drm_i915_private *dev_priv =
1128                 container_of(work, struct drm_i915_private, rps.work);
1129         u32 pm_iir;
1130         int new_delay, adj;
1131
1132         spin_lock_irq(&dev_priv->irq_lock);
1133         /* Speed up work cancelation during disabling rps interrupts. */
1134         if (!dev_priv->rps.interrupts_enabled) {
1135                 spin_unlock_irq(&dev_priv->irq_lock);
1136                 return;
1137         }
1138         pm_iir = dev_priv->rps.pm_iir;
1139         dev_priv->rps.pm_iir = 0;
1140         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1141         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1142         spin_unlock_irq(&dev_priv->irq_lock);
1143
1144         /* Make sure we didn't queue anything we're not going to process. */
1145         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1146
1147         if ((pm_iir & dev_priv->pm_rps_events) == 0)
1148                 return;
1149
1150         mutex_lock(&dev_priv->rps.hw_lock);
1151
1152         adj = dev_priv->rps.last_adj;
1153         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1154                 if (adj > 0)
1155                         adj *= 2;
1156                 else {
1157                         /* CHV needs even encode values */
1158                         adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1159                 }
1160                 new_delay = dev_priv->rps.cur_freq + adj;
1161
1162                 /*
1163                  * For better performance, jump directly
1164                  * to RPe if we're below it.
1165                  */
1166                 if (new_delay < dev_priv->rps.efficient_freq)
1167                         new_delay = dev_priv->rps.efficient_freq;
1168         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1169                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1170                         new_delay = dev_priv->rps.efficient_freq;
1171                 else
1172                         new_delay = dev_priv->rps.min_freq_softlimit;
1173                 adj = 0;
1174         } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1175                 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1176         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1177                 if (adj < 0)
1178                         adj *= 2;
1179                 else {
1180                         /* CHV needs even encode values */
1181                         adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1182                 }
1183                 new_delay = dev_priv->rps.cur_freq + adj;
1184         } else { /* unknown event */
1185                 new_delay = dev_priv->rps.cur_freq;
1186         }
1187
1188         /* sysfs frequency interfaces may have snuck in while servicing the
1189          * interrupt
1190          */
1191         new_delay = clamp_t(int, new_delay,
1192                             dev_priv->rps.min_freq_softlimit,
1193                             dev_priv->rps.max_freq_softlimit);
1194
1195         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1196
1197         intel_set_rps(dev_priv->dev, new_delay);
1198
1199         mutex_unlock(&dev_priv->rps.hw_lock);
1200 }
1201
1202
1203 /**
1204  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1205  * occurred.
1206  * @work: workqueue struct
1207  *
1208  * Doesn't actually do anything except notify userspace. As a consequence of
1209  * this event, userspace should try to remap the bad rows since statistically
1210  * it is likely the same row is more likely to go bad again.
1211  */
1212 static void ivybridge_parity_work(struct work_struct *work)
1213 {
1214         struct drm_i915_private *dev_priv =
1215                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1216         u32 error_status, row, bank, subbank;
1217         char *parity_event[6];
1218         uint32_t misccpctl;
1219         uint8_t slice = 0;
1220
1221         /* We must turn off DOP level clock gating to access the L3 registers.
1222          * In order to prevent a get/put style interface, acquire struct mutex
1223          * any time we access those registers.
1224          */
1225         mutex_lock(&dev_priv->dev->struct_mutex);
1226
1227         /* If we've screwed up tracking, just let the interrupt fire again */
1228         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1229                 goto out;
1230
1231         misccpctl = I915_READ(GEN7_MISCCPCTL);
1232         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1233         POSTING_READ(GEN7_MISCCPCTL);
1234
1235         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1236                 u32 reg;
1237
1238                 slice--;
1239                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1240                         break;
1241
1242                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1243
1244                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1245
1246                 error_status = I915_READ(reg);
1247                 row = GEN7_PARITY_ERROR_ROW(error_status);
1248                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1249                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1250
1251                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1252                 POSTING_READ(reg);
1253
1254                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1255                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1256                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1257                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1258                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1259                 parity_event[5] = NULL;
1260
1261                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1262                                    KOBJ_CHANGE, parity_event);
1263
1264                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1265                           slice, row, bank, subbank);
1266
1267                 kfree(parity_event[4]);
1268                 kfree(parity_event[3]);
1269                 kfree(parity_event[2]);
1270                 kfree(parity_event[1]);
1271         }
1272
1273         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1274
1275 out:
1276         WARN_ON(dev_priv->l3_parity.which_slice);
1277         spin_lock_irq(&dev_priv->irq_lock);
1278         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1279         spin_unlock_irq(&dev_priv->irq_lock);
1280
1281         mutex_unlock(&dev_priv->dev->struct_mutex);
1282 }
1283
1284 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1285 {
1286         struct drm_i915_private *dev_priv = dev->dev_private;
1287
1288         if (!HAS_L3_DPF(dev))
1289                 return;
1290
1291         spin_lock(&dev_priv->irq_lock);
1292         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1293         spin_unlock(&dev_priv->irq_lock);
1294
1295         iir &= GT_PARITY_ERROR(dev);
1296         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1297                 dev_priv->l3_parity.which_slice |= 1 << 1;
1298
1299         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1300                 dev_priv->l3_parity.which_slice |= 1 << 0;
1301
1302         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1303 }
1304
1305 static void ilk_gt_irq_handler(struct drm_device *dev,
1306                                struct drm_i915_private *dev_priv,
1307                                u32 gt_iir)
1308 {
1309         if (gt_iir &
1310             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1311                 notify_ring(dev, &dev_priv->ring[RCS]);
1312         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1313                 notify_ring(dev, &dev_priv->ring[VCS]);
1314 }
1315
1316 static void snb_gt_irq_handler(struct drm_device *dev,
1317                                struct drm_i915_private *dev_priv,
1318                                u32 gt_iir)
1319 {
1320
1321         if (gt_iir &
1322             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1323                 notify_ring(dev, &dev_priv->ring[RCS]);
1324         if (gt_iir & GT_BSD_USER_INTERRUPT)
1325                 notify_ring(dev, &dev_priv->ring[VCS]);
1326         if (gt_iir & GT_BLT_USER_INTERRUPT)
1327                 notify_ring(dev, &dev_priv->ring[BCS]);
1328
1329         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1330                       GT_BSD_CS_ERROR_INTERRUPT |
1331                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1332                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1333
1334         if (gt_iir & GT_PARITY_ERROR(dev))
1335                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1336 }
1337
1338 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1339                                        struct drm_i915_private *dev_priv,
1340                                        u32 master_ctl)
1341 {
1342         struct intel_engine_cs *ring;
1343         u32 rcs, bcs, vcs;
1344         uint32_t tmp = 0;
1345         irqreturn_t ret = IRQ_NONE;
1346
1347         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1348                 tmp = I915_READ(GEN8_GT_IIR(0));
1349                 if (tmp) {
1350                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1351                         ret = IRQ_HANDLED;
1352
1353                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1354                         ring = &dev_priv->ring[RCS];
1355                         if (rcs & GT_RENDER_USER_INTERRUPT)
1356                                 notify_ring(dev, ring);
1357                         if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1358                                 intel_lrc_irq_handler(ring);
1359
1360                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1361                         ring = &dev_priv->ring[BCS];
1362                         if (bcs & GT_RENDER_USER_INTERRUPT)
1363                                 notify_ring(dev, ring);
1364                         if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1365                                 intel_lrc_irq_handler(ring);
1366                 } else
1367                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1368         }
1369
1370         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1371                 tmp = I915_READ(GEN8_GT_IIR(1));
1372                 if (tmp) {
1373                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1374                         ret = IRQ_HANDLED;
1375
1376                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1377                         ring = &dev_priv->ring[VCS];
1378                         if (vcs & GT_RENDER_USER_INTERRUPT)
1379                                 notify_ring(dev, ring);
1380                         if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1381                                 intel_lrc_irq_handler(ring);
1382
1383                         vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1384                         ring = &dev_priv->ring[VCS2];
1385                         if (vcs & GT_RENDER_USER_INTERRUPT)
1386                                 notify_ring(dev, ring);
1387                         if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1388                                 intel_lrc_irq_handler(ring);
1389                 } else
1390                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1391         }
1392
1393         if (master_ctl & GEN8_GT_PM_IRQ) {
1394                 tmp = I915_READ(GEN8_GT_IIR(2));
1395                 if (tmp & dev_priv->pm_rps_events) {
1396                         I915_WRITE(GEN8_GT_IIR(2),
1397                                    tmp & dev_priv->pm_rps_events);
1398                         ret = IRQ_HANDLED;
1399                         gen6_rps_irq_handler(dev_priv, tmp);
1400                 } else
1401                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1402         }
1403
1404         if (master_ctl & GEN8_GT_VECS_IRQ) {
1405                 tmp = I915_READ(GEN8_GT_IIR(3));
1406                 if (tmp) {
1407                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1408                         ret = IRQ_HANDLED;
1409
1410                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1411                         ring = &dev_priv->ring[VECS];
1412                         if (vcs & GT_RENDER_USER_INTERRUPT)
1413                                 notify_ring(dev, ring);
1414                         if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1415                                 intel_lrc_irq_handler(ring);
1416                 } else
1417                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1418         }
1419
1420         return ret;
1421 }
1422
1423 #define HPD_STORM_DETECT_PERIOD 1000
1424 #define HPD_STORM_THRESHOLD 5
1425
1426 static int pch_port_to_hotplug_shift(enum port port)
1427 {
1428         switch (port) {
1429         case PORT_A:
1430         case PORT_E:
1431         default:
1432                 return -1;
1433         case PORT_B:
1434                 return 0;
1435         case PORT_C:
1436                 return 8;
1437         case PORT_D:
1438                 return 16;
1439         }
1440 }
1441
1442 static int i915_port_to_hotplug_shift(enum port port)
1443 {
1444         switch (port) {
1445         case PORT_A:
1446         case PORT_E:
1447         default:
1448                 return -1;
1449         case PORT_B:
1450                 return 17;
1451         case PORT_C:
1452                 return 19;
1453         case PORT_D:
1454                 return 21;
1455         }
1456 }
1457
1458 static inline enum port get_port_from_pin(enum hpd_pin pin)
1459 {
1460         switch (pin) {
1461         case HPD_PORT_B:
1462                 return PORT_B;
1463         case HPD_PORT_C:
1464                 return PORT_C;
1465         case HPD_PORT_D:
1466                 return PORT_D;
1467         default:
1468                 return PORT_A; /* no hpd */
1469         }
1470 }
1471
1472 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1473                                          u32 hotplug_trigger,
1474                                          u32 dig_hotplug_reg,
1475                                          const u32 hpd[HPD_NUM_PINS])
1476 {
1477         struct drm_i915_private *dev_priv = dev->dev_private;
1478         int i;
1479         enum port port;
1480         bool storm_detected = false;
1481         bool queue_dig = false, queue_hp = false;
1482         u32 dig_shift;
1483         u32 dig_port_mask = 0;
1484
1485         if (!hotplug_trigger)
1486                 return;
1487
1488         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1489                          hotplug_trigger, dig_hotplug_reg);
1490
1491         spin_lock(&dev_priv->irq_lock);
1492         for (i = 1; i < HPD_NUM_PINS; i++) {
1493                 if (!(hpd[i] & hotplug_trigger))
1494                         continue;
1495
1496                 port = get_port_from_pin(i);
1497                 if (port && dev_priv->hpd_irq_port[port]) {
1498                         bool long_hpd;
1499
1500                         if (HAS_PCH_SPLIT(dev)) {
1501                                 dig_shift = pch_port_to_hotplug_shift(port);
1502                                 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1503                         } else {
1504                                 dig_shift = i915_port_to_hotplug_shift(port);
1505                                 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1506                         }
1507
1508                         DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1509                                          port_name(port),
1510                                          long_hpd ? "long" : "short");
1511                         /* for long HPD pulses we want to have the digital queue happen,
1512                            but we still want HPD storm detection to function. */
1513                         if (long_hpd) {
1514                                 dev_priv->long_hpd_port_mask |= (1 << port);
1515                                 dig_port_mask |= hpd[i];
1516                         } else {
1517                                 /* for short HPD just trigger the digital queue */
1518                                 dev_priv->short_hpd_port_mask |= (1 << port);
1519                                 hotplug_trigger &= ~hpd[i];
1520                         }
1521                         queue_dig = true;
1522                 }
1523         }
1524
1525         for (i = 1; i < HPD_NUM_PINS; i++) {
1526                 if (hpd[i] & hotplug_trigger &&
1527                     dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1528                         /*
1529                          * On GMCH platforms the interrupt mask bits only
1530                          * prevent irq generation, not the setting of the
1531                          * hotplug bits itself. So only WARN about unexpected
1532                          * interrupts on saner platforms.
1533                          */
1534                         WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1535                                   "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1536                                   hotplug_trigger, i, hpd[i]);
1537
1538                         continue;
1539                 }
1540
1541                 if (!(hpd[i] & hotplug_trigger) ||
1542                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1543                         continue;
1544
1545                 if (!(dig_port_mask & hpd[i])) {
1546                         dev_priv->hpd_event_bits |= (1 << i);
1547                         queue_hp = true;
1548                 }
1549
1550                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1551                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1552                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1553                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1554                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1555                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1556                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1557                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1558                         dev_priv->hpd_event_bits &= ~(1 << i);
1559                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1560                         storm_detected = true;
1561                 } else {
1562                         dev_priv->hpd_stats[i].hpd_cnt++;
1563                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1564                                       dev_priv->hpd_stats[i].hpd_cnt);
1565                 }
1566         }
1567
1568         if (storm_detected)
1569                 dev_priv->display.hpd_irq_setup(dev);
1570         spin_unlock(&dev_priv->irq_lock);
1571
1572         /*
1573          * Our hotplug handler can grab modeset locks (by calling down into the
1574          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1575          * queue for otherwise the flush_work in the pageflip code will
1576          * deadlock.
1577          */
1578         if (queue_dig)
1579                 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1580         if (queue_hp)
1581                 schedule_work(&dev_priv->hotplug_work);
1582 }
1583
1584 static void gmbus_irq_handler(struct drm_device *dev)
1585 {
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587
1588         wake_up_all(&dev_priv->gmbus_wait_queue);
1589 }
1590
1591 static void dp_aux_irq_handler(struct drm_device *dev)
1592 {
1593         struct drm_i915_private *dev_priv = dev->dev_private;
1594
1595         wake_up_all(&dev_priv->gmbus_wait_queue);
1596 }
1597
1598 #if defined(CONFIG_DEBUG_FS)
1599 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1600                                          uint32_t crc0, uint32_t crc1,
1601                                          uint32_t crc2, uint32_t crc3,
1602                                          uint32_t crc4)
1603 {
1604         struct drm_i915_private *dev_priv = dev->dev_private;
1605         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1606         struct intel_pipe_crc_entry *entry;
1607         int head, tail;
1608
1609         spin_lock(&pipe_crc->lock);
1610
1611         if (!pipe_crc->entries) {
1612                 spin_unlock(&pipe_crc->lock);
1613                 DRM_DEBUG_KMS("spurious interrupt\n");
1614                 return;
1615         }
1616
1617         head = pipe_crc->head;
1618         tail = pipe_crc->tail;
1619
1620         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1621                 spin_unlock(&pipe_crc->lock);
1622                 DRM_ERROR("CRC buffer overflowing\n");
1623                 return;
1624         }
1625
1626         entry = &pipe_crc->entries[head];
1627
1628         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1629         entry->crc[0] = crc0;
1630         entry->crc[1] = crc1;
1631         entry->crc[2] = crc2;
1632         entry->crc[3] = crc3;
1633         entry->crc[4] = crc4;
1634
1635         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1636         pipe_crc->head = head;
1637
1638         spin_unlock(&pipe_crc->lock);
1639
1640         wake_up_interruptible(&pipe_crc->wq);
1641 }
1642 #else
1643 static inline void
1644 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1645                              uint32_t crc0, uint32_t crc1,
1646                              uint32_t crc2, uint32_t crc3,
1647                              uint32_t crc4) {}
1648 #endif
1649
1650
1651 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1652 {
1653         struct drm_i915_private *dev_priv = dev->dev_private;
1654
1655         display_pipe_crc_irq_handler(dev, pipe,
1656                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1657                                      0, 0, 0, 0);
1658 }
1659
1660 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1661 {
1662         struct drm_i915_private *dev_priv = dev->dev_private;
1663
1664         display_pipe_crc_irq_handler(dev, pipe,
1665                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1666                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1667                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1668                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1669                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1670 }
1671
1672 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1673 {
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675         uint32_t res1, res2;
1676
1677         if (INTEL_INFO(dev)->gen >= 3)
1678                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1679         else
1680                 res1 = 0;
1681
1682         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1683                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1684         else
1685                 res2 = 0;
1686
1687         display_pipe_crc_irq_handler(dev, pipe,
1688                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1689                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1690                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1691                                      res1, res2);
1692 }
1693
1694 /* The RPS events need forcewake, so we add them to a work queue and mask their
1695  * IMR bits until the work is done. Other interrupts can be processed without
1696  * the work queue. */
1697 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1698 {
1699         if (pm_iir & dev_priv->pm_rps_events) {
1700                 spin_lock(&dev_priv->irq_lock);
1701                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1702                 if (dev_priv->rps.interrupts_enabled) {
1703                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1704                         queue_work(dev_priv->wq, &dev_priv->rps.work);
1705                 }
1706                 spin_unlock(&dev_priv->irq_lock);
1707         }
1708
1709         if (INTEL_INFO(dev_priv)->gen >= 8)
1710                 return;
1711
1712         if (HAS_VEBOX(dev_priv->dev)) {
1713                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1714                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1715
1716                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1717                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1718         }
1719 }
1720
1721 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1722 {
1723         if (!drm_handle_vblank(dev, pipe))
1724                 return false;
1725
1726         return true;
1727 }
1728
1729 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1730 {
1731         struct drm_i915_private *dev_priv = dev->dev_private;
1732         u32 pipe_stats[I915_MAX_PIPES] = { };
1733         int pipe;
1734
1735         spin_lock(&dev_priv->irq_lock);
1736         for_each_pipe(dev_priv, pipe) {
1737                 int reg;
1738                 u32 mask, iir_bit = 0;
1739
1740                 /*
1741                  * PIPESTAT bits get signalled even when the interrupt is
1742                  * disabled with the mask bits, and some of the status bits do
1743                  * not generate interrupts at all (like the underrun bit). Hence
1744                  * we need to be careful that we only handle what we want to
1745                  * handle.
1746                  */
1747
1748                 /* fifo underruns are filterered in the underrun handler. */
1749                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1750
1751                 switch (pipe) {
1752                 case PIPE_A:
1753                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1754                         break;
1755                 case PIPE_B:
1756                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1757                         break;
1758                 case PIPE_C:
1759                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1760                         break;
1761                 }
1762                 if (iir & iir_bit)
1763                         mask |= dev_priv->pipestat_irq_mask[pipe];
1764
1765                 if (!mask)
1766                         continue;
1767
1768                 reg = PIPESTAT(pipe);
1769                 mask |= PIPESTAT_INT_ENABLE_MASK;
1770                 pipe_stats[pipe] = I915_READ(reg) & mask;
1771
1772                 /*
1773                  * Clear the PIPE*STAT regs before the IIR
1774                  */
1775                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1776                                         PIPESTAT_INT_STATUS_MASK))
1777                         I915_WRITE(reg, pipe_stats[pipe]);
1778         }
1779         spin_unlock(&dev_priv->irq_lock);
1780
1781         for_each_pipe(dev_priv, pipe) {
1782                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1783                     intel_pipe_handle_vblank(dev, pipe))
1784                         intel_check_page_flip(dev, pipe);
1785
1786                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1787                         intel_prepare_page_flip(dev, pipe);
1788                         intel_finish_page_flip(dev, pipe);
1789                 }
1790
1791                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1792                         i9xx_pipe_crc_irq_handler(dev, pipe);
1793
1794                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1795                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1796         }
1797
1798         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1799                 gmbus_irq_handler(dev);
1800 }
1801
1802 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1803 {
1804         struct drm_i915_private *dev_priv = dev->dev_private;
1805         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1806
1807         if (hotplug_status) {
1808                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1809                 /*
1810                  * Make sure hotplug status is cleared before we clear IIR, or else we
1811                  * may miss hotplug events.
1812                  */
1813                 POSTING_READ(PORT_HOTPLUG_STAT);
1814
1815                 if (IS_G4X(dev)) {
1816                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1817
1818                         intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1819                 } else {
1820                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1821
1822                         intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1823                 }
1824
1825                 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1826                     hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1827                         dp_aux_irq_handler(dev);
1828         }
1829 }
1830
1831 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1832 {
1833         struct drm_device *dev = arg;
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835         u32 iir, gt_iir, pm_iir;
1836         irqreturn_t ret = IRQ_NONE;
1837
1838         if (!intel_irqs_enabled(dev_priv))
1839                 return IRQ_NONE;
1840
1841         while (true) {
1842                 /* Find, clear, then process each source of interrupt */
1843
1844                 gt_iir = I915_READ(GTIIR);
1845                 if (gt_iir)
1846                         I915_WRITE(GTIIR, gt_iir);
1847
1848                 pm_iir = I915_READ(GEN6_PMIIR);
1849                 if (pm_iir)
1850                         I915_WRITE(GEN6_PMIIR, pm_iir);
1851
1852                 iir = I915_READ(VLV_IIR);
1853                 if (iir) {
1854                         /* Consume port before clearing IIR or we'll miss events */
1855                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
1856                                 i9xx_hpd_irq_handler(dev);
1857                         I915_WRITE(VLV_IIR, iir);
1858                 }
1859
1860                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1861                         goto out;
1862
1863                 ret = IRQ_HANDLED;
1864
1865                 if (gt_iir)
1866                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1867                 if (pm_iir)
1868                         gen6_rps_irq_handler(dev_priv, pm_iir);
1869                 /* Call regardless, as some status bits might not be
1870                  * signalled in iir */
1871                 valleyview_pipestat_irq_handler(dev, iir);
1872         }
1873
1874 out:
1875         return ret;
1876 }
1877
1878 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1879 {
1880         struct drm_device *dev = arg;
1881         struct drm_i915_private *dev_priv = dev->dev_private;
1882         u32 master_ctl, iir;
1883         irqreturn_t ret = IRQ_NONE;
1884
1885         if (!intel_irqs_enabled(dev_priv))
1886                 return IRQ_NONE;
1887
1888         for (;;) {
1889                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1890                 iir = I915_READ(VLV_IIR);
1891
1892                 if (master_ctl == 0 && iir == 0)
1893                         break;
1894
1895                 ret = IRQ_HANDLED;
1896
1897                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1898
1899                 /* Find, clear, then process each source of interrupt */
1900
1901                 if (iir) {
1902                         /* Consume port before clearing IIR or we'll miss events */
1903                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
1904                                 i9xx_hpd_irq_handler(dev);
1905                         I915_WRITE(VLV_IIR, iir);
1906                 }
1907
1908                 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1909
1910                 /* Call regardless, as some status bits might not be
1911                  * signalled in iir */
1912                 valleyview_pipestat_irq_handler(dev, iir);
1913
1914                 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1915                 POSTING_READ(GEN8_MASTER_IRQ);
1916         }
1917
1918         return ret;
1919 }
1920
1921 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1922 {
1923         struct drm_i915_private *dev_priv = dev->dev_private;
1924         int pipe;
1925         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1926         u32 dig_hotplug_reg;
1927
1928         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1929         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1930
1931         intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1932
1933         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1934                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1935                                SDE_AUDIO_POWER_SHIFT);
1936                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1937                                  port_name(port));
1938         }
1939
1940         if (pch_iir & SDE_AUX_MASK)
1941                 dp_aux_irq_handler(dev);
1942
1943         if (pch_iir & SDE_GMBUS)
1944                 gmbus_irq_handler(dev);
1945
1946         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1947                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1948
1949         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1950                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1951
1952         if (pch_iir & SDE_POISON)
1953                 DRM_ERROR("PCH poison interrupt\n");
1954
1955         if (pch_iir & SDE_FDI_MASK)
1956                 for_each_pipe(dev_priv, pipe)
1957                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1958                                          pipe_name(pipe),
1959                                          I915_READ(FDI_RX_IIR(pipe)));
1960
1961         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1962                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1963
1964         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1965                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1966
1967         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1968                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1969
1970         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1971                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1972 }
1973
1974 static void ivb_err_int_handler(struct drm_device *dev)
1975 {
1976         struct drm_i915_private *dev_priv = dev->dev_private;
1977         u32 err_int = I915_READ(GEN7_ERR_INT);
1978         enum pipe pipe;
1979
1980         if (err_int & ERR_INT_POISON)
1981                 DRM_ERROR("Poison interrupt\n");
1982
1983         for_each_pipe(dev_priv, pipe) {
1984                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1985                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1986
1987                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1988                         if (IS_IVYBRIDGE(dev))
1989                                 ivb_pipe_crc_irq_handler(dev, pipe);
1990                         else
1991                                 hsw_pipe_crc_irq_handler(dev, pipe);
1992                 }
1993         }
1994
1995         I915_WRITE(GEN7_ERR_INT, err_int);
1996 }
1997
1998 static void cpt_serr_int_handler(struct drm_device *dev)
1999 {
2000         struct drm_i915_private *dev_priv = dev->dev_private;
2001         u32 serr_int = I915_READ(SERR_INT);
2002
2003         if (serr_int & SERR_INT_POISON)
2004                 DRM_ERROR("PCH poison interrupt\n");
2005
2006         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2007                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2008
2009         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2010                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2011
2012         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2013                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2014
2015         I915_WRITE(SERR_INT, serr_int);
2016 }
2017
2018 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2019 {
2020         struct drm_i915_private *dev_priv = dev->dev_private;
2021         int pipe;
2022         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2023         u32 dig_hotplug_reg;
2024
2025         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2026         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2027
2028         intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2029
2030         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2031                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2032                                SDE_AUDIO_POWER_SHIFT_CPT);
2033                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2034                                  port_name(port));
2035         }
2036
2037         if (pch_iir & SDE_AUX_MASK_CPT)
2038                 dp_aux_irq_handler(dev);
2039
2040         if (pch_iir & SDE_GMBUS_CPT)
2041                 gmbus_irq_handler(dev);
2042
2043         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2044                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2045
2046         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2047                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2048
2049         if (pch_iir & SDE_FDI_MASK_CPT)
2050                 for_each_pipe(dev_priv, pipe)
2051                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2052                                          pipe_name(pipe),
2053                                          I915_READ(FDI_RX_IIR(pipe)));
2054
2055         if (pch_iir & SDE_ERROR_CPT)
2056                 cpt_serr_int_handler(dev);
2057 }
2058
2059 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2060 {
2061         struct drm_i915_private *dev_priv = dev->dev_private;
2062         enum pipe pipe;
2063
2064         if (de_iir & DE_AUX_CHANNEL_A)
2065                 dp_aux_irq_handler(dev);
2066
2067         if (de_iir & DE_GSE)
2068                 intel_opregion_asle_intr(dev);
2069
2070         if (de_iir & DE_POISON)
2071                 DRM_ERROR("Poison interrupt\n");
2072
2073         for_each_pipe(dev_priv, pipe) {
2074                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2075                     intel_pipe_handle_vblank(dev, pipe))
2076                         intel_check_page_flip(dev, pipe);
2077
2078                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2079                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2080
2081                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2082                         i9xx_pipe_crc_irq_handler(dev, pipe);
2083
2084                 /* plane/pipes map 1:1 on ilk+ */
2085                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2086                         intel_prepare_page_flip(dev, pipe);
2087                         intel_finish_page_flip_plane(dev, pipe);
2088                 }
2089         }
2090
2091         /* check event from PCH */
2092         if (de_iir & DE_PCH_EVENT) {
2093                 u32 pch_iir = I915_READ(SDEIIR);
2094
2095                 if (HAS_PCH_CPT(dev))
2096                         cpt_irq_handler(dev, pch_iir);
2097                 else
2098                         ibx_irq_handler(dev, pch_iir);
2099
2100                 /* should clear PCH hotplug event before clear CPU irq */
2101                 I915_WRITE(SDEIIR, pch_iir);
2102         }
2103
2104         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2105                 ironlake_rps_change_irq_handler(dev);
2106 }
2107
2108 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2109 {
2110         struct drm_i915_private *dev_priv = dev->dev_private;
2111         enum pipe pipe;
2112
2113         if (de_iir & DE_ERR_INT_IVB)
2114                 ivb_err_int_handler(dev);
2115
2116         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2117                 dp_aux_irq_handler(dev);
2118
2119         if (de_iir & DE_GSE_IVB)
2120                 intel_opregion_asle_intr(dev);
2121
2122         for_each_pipe(dev_priv, pipe) {
2123                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2124                     intel_pipe_handle_vblank(dev, pipe))
2125                         intel_check_page_flip(dev, pipe);
2126
2127                 /* plane/pipes map 1:1 on ilk+ */
2128                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2129                         intel_prepare_page_flip(dev, pipe);
2130                         intel_finish_page_flip_plane(dev, pipe);
2131                 }
2132         }
2133
2134         /* check event from PCH */
2135         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2136                 u32 pch_iir = I915_READ(SDEIIR);
2137
2138                 cpt_irq_handler(dev, pch_iir);
2139
2140                 /* clear PCH hotplug event before clear CPU irq */
2141                 I915_WRITE(SDEIIR, pch_iir);
2142         }
2143 }
2144
2145 /*
2146  * To handle irqs with the minimum potential races with fresh interrupts, we:
2147  * 1 - Disable Master Interrupt Control.
2148  * 2 - Find the source(s) of the interrupt.
2149  * 3 - Clear the Interrupt Identity bits (IIR).
2150  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2151  * 5 - Re-enable Master Interrupt Control.
2152  */
2153 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2154 {
2155         struct drm_device *dev = arg;
2156         struct drm_i915_private *dev_priv = dev->dev_private;
2157         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2158         irqreturn_t ret = IRQ_NONE;
2159
2160         if (!intel_irqs_enabled(dev_priv))
2161                 return IRQ_NONE;
2162
2163         /* We get interrupts on unclaimed registers, so check for this before we
2164          * do any I915_{READ,WRITE}. */
2165         intel_uncore_check_errors(dev);
2166
2167         /* disable master interrupt before clearing iir  */
2168         de_ier = I915_READ(DEIER);
2169         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2170         POSTING_READ(DEIER);
2171
2172         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2173          * interrupts will will be stored on its back queue, and then we'll be
2174          * able to process them after we restore SDEIER (as soon as we restore
2175          * it, we'll get an interrupt if SDEIIR still has something to process
2176          * due to its back queue). */
2177         if (!HAS_PCH_NOP(dev)) {
2178                 sde_ier = I915_READ(SDEIER);
2179                 I915_WRITE(SDEIER, 0);
2180                 POSTING_READ(SDEIER);
2181         }
2182
2183         /* Find, clear, then process each source of interrupt */
2184
2185         gt_iir = I915_READ(GTIIR);
2186         if (gt_iir) {
2187                 I915_WRITE(GTIIR, gt_iir);
2188                 ret = IRQ_HANDLED;
2189                 if (INTEL_INFO(dev)->gen >= 6)
2190                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
2191                 else
2192                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2193         }
2194
2195         de_iir = I915_READ(DEIIR);
2196         if (de_iir) {
2197                 I915_WRITE(DEIIR, de_iir);
2198                 ret = IRQ_HANDLED;
2199                 if (INTEL_INFO(dev)->gen >= 7)
2200                         ivb_display_irq_handler(dev, de_iir);
2201                 else
2202                         ilk_display_irq_handler(dev, de_iir);
2203         }
2204
2205         if (INTEL_INFO(dev)->gen >= 6) {
2206                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2207                 if (pm_iir) {
2208                         I915_WRITE(GEN6_PMIIR, pm_iir);
2209                         ret = IRQ_HANDLED;
2210                         gen6_rps_irq_handler(dev_priv, pm_iir);
2211                 }
2212         }
2213
2214         I915_WRITE(DEIER, de_ier);
2215         POSTING_READ(DEIER);
2216         if (!HAS_PCH_NOP(dev)) {
2217                 I915_WRITE(SDEIER, sde_ier);
2218                 POSTING_READ(SDEIER);
2219         }
2220
2221         return ret;
2222 }
2223
2224 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2225 {
2226         struct drm_device *dev = arg;
2227         struct drm_i915_private *dev_priv = dev->dev_private;
2228         u32 master_ctl;
2229         irqreturn_t ret = IRQ_NONE;
2230         uint32_t tmp = 0;
2231         enum pipe pipe;
2232         u32 aux_mask = GEN8_AUX_CHANNEL_A;
2233
2234         if (!intel_irqs_enabled(dev_priv))
2235                 return IRQ_NONE;
2236
2237         if (IS_GEN9(dev))
2238                 aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2239                         GEN9_AUX_CHANNEL_D;
2240
2241         master_ctl = I915_READ(GEN8_MASTER_IRQ);
2242         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2243         if (!master_ctl)
2244                 return IRQ_NONE;
2245
2246         I915_WRITE(GEN8_MASTER_IRQ, 0);
2247         POSTING_READ(GEN8_MASTER_IRQ);
2248
2249         /* Find, clear, then process each source of interrupt */
2250
2251         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2252
2253         if (master_ctl & GEN8_DE_MISC_IRQ) {
2254                 tmp = I915_READ(GEN8_DE_MISC_IIR);
2255                 if (tmp) {
2256                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2257                         ret = IRQ_HANDLED;
2258                         if (tmp & GEN8_DE_MISC_GSE)
2259                                 intel_opregion_asle_intr(dev);
2260                         else
2261                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2262                 }
2263                 else
2264                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2265         }
2266
2267         if (master_ctl & GEN8_DE_PORT_IRQ) {
2268                 tmp = I915_READ(GEN8_DE_PORT_IIR);
2269                 if (tmp) {
2270                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2271                         ret = IRQ_HANDLED;
2272
2273                         if (tmp & aux_mask)
2274                                 dp_aux_irq_handler(dev);
2275                         else
2276                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2277                 }
2278                 else
2279                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2280         }
2281
2282         for_each_pipe(dev_priv, pipe) {
2283                 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2284
2285                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2286                         continue;
2287
2288                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2289                 if (pipe_iir) {
2290                         ret = IRQ_HANDLED;
2291                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2292
2293                         if (pipe_iir & GEN8_PIPE_VBLANK &&
2294                             intel_pipe_handle_vblank(dev, pipe))
2295                                 intel_check_page_flip(dev, pipe);
2296
2297                         if (IS_GEN9(dev))
2298                                 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2299                         else
2300                                 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2301
2302                         if (flip_done) {
2303                                 intel_prepare_page_flip(dev, pipe);
2304                                 intel_finish_page_flip_plane(dev, pipe);
2305                         }
2306
2307                         if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2308                                 hsw_pipe_crc_irq_handler(dev, pipe);
2309
2310                         if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2311                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2312                                                                     pipe);
2313
2314
2315                         if (IS_GEN9(dev))
2316                                 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2317                         else
2318                                 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2319
2320                         if (fault_errors)
2321                                 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2322                                           pipe_name(pipe),
2323                                           pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2324                 } else
2325                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2326         }
2327
2328         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2329                 /*
2330                  * FIXME(BDW): Assume for now that the new interrupt handling
2331                  * scheme also closed the SDE interrupt handling race we've seen
2332                  * on older pch-split platforms. But this needs testing.
2333                  */
2334                 u32 pch_iir = I915_READ(SDEIIR);
2335                 if (pch_iir) {
2336                         I915_WRITE(SDEIIR, pch_iir);
2337                         ret = IRQ_HANDLED;
2338                         cpt_irq_handler(dev, pch_iir);
2339                 } else
2340                         DRM_ERROR("The master control interrupt lied (SDE)!\n");
2341
2342         }
2343
2344         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2345         POSTING_READ(GEN8_MASTER_IRQ);
2346
2347         return ret;
2348 }
2349
2350 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2351                                bool reset_completed)
2352 {
2353         struct intel_engine_cs *ring;
2354         int i;
2355
2356         /*
2357          * Notify all waiters for GPU completion events that reset state has
2358          * been changed, and that they need to restart their wait after
2359          * checking for potential errors (and bail out to drop locks if there is
2360          * a gpu reset pending so that i915_error_work_func can acquire them).
2361          */
2362
2363         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2364         for_each_ring(ring, dev_priv, i)
2365                 wake_up_all(&ring->irq_queue);
2366
2367         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2368         wake_up_all(&dev_priv->pending_flip_queue);
2369
2370         /*
2371          * Signal tasks blocked in i915_gem_wait_for_error that the pending
2372          * reset state is cleared.
2373          */
2374         if (reset_completed)
2375                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2376 }
2377
2378 /**
2379  * i915_reset_and_wakeup - do process context error handling work
2380  *
2381  * Fire an error uevent so userspace can see that a hang or error
2382  * was detected.
2383  */
2384 static void i915_reset_and_wakeup(struct drm_device *dev)
2385 {
2386         struct drm_i915_private *dev_priv = to_i915(dev);
2387         struct i915_gpu_error *error = &dev_priv->gpu_error;
2388         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2389         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2390         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2391         int ret;
2392
2393         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2394
2395         /*
2396          * Note that there's only one work item which does gpu resets, so we
2397          * need not worry about concurrent gpu resets potentially incrementing
2398          * error->reset_counter twice. We only need to take care of another
2399          * racing irq/hangcheck declaring the gpu dead for a second time. A
2400          * quick check for that is good enough: schedule_work ensures the
2401          * correct ordering between hang detection and this work item, and since
2402          * the reset in-progress bit is only ever set by code outside of this
2403          * work we don't need to worry about any other races.
2404          */
2405         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2406                 DRM_DEBUG_DRIVER("resetting chip\n");
2407                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2408                                    reset_event);
2409
2410                 /*
2411                  * In most cases it's guaranteed that we get here with an RPM
2412                  * reference held, for example because there is a pending GPU
2413                  * request that won't finish until the reset is done. This
2414                  * isn't the case at least when we get here by doing a
2415                  * simulated reset via debugs, so get an RPM reference.
2416                  */
2417                 intel_runtime_pm_get(dev_priv);
2418
2419                 intel_prepare_reset(dev);
2420
2421                 /*
2422                  * All state reset _must_ be completed before we update the
2423                  * reset counter, for otherwise waiters might miss the reset
2424                  * pending state and not properly drop locks, resulting in
2425                  * deadlocks with the reset work.
2426                  */
2427                 ret = i915_reset(dev);
2428
2429                 intel_finish_reset(dev);
2430
2431                 intel_runtime_pm_put(dev_priv);
2432
2433                 if (ret == 0) {
2434                         /*
2435                          * After all the gem state is reset, increment the reset
2436                          * counter and wake up everyone waiting for the reset to
2437                          * complete.
2438                          *
2439                          * Since unlock operations are a one-sided barrier only,
2440                          * we need to insert a barrier here to order any seqno
2441                          * updates before
2442                          * the counter increment.
2443                          */
2444                         smp_mb__before_atomic();
2445                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2446
2447                         kobject_uevent_env(&dev->primary->kdev->kobj,
2448                                            KOBJ_CHANGE, reset_done_event);
2449                 } else {
2450                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2451                 }
2452
2453                 /*
2454                  * Note: The wake_up also serves as a memory barrier so that
2455                  * waiters see the update value of the reset counter atomic_t.
2456                  */
2457                 i915_error_wake_up(dev_priv, true);
2458         }
2459 }
2460
2461 static void i915_report_and_clear_eir(struct drm_device *dev)
2462 {
2463         struct drm_i915_private *dev_priv = dev->dev_private;
2464         uint32_t instdone[I915_NUM_INSTDONE_REG];
2465         u32 eir = I915_READ(EIR);
2466         int pipe, i;
2467
2468         if (!eir)
2469                 return;
2470
2471         pr_err("render error detected, EIR: 0x%08x\n", eir);
2472
2473         i915_get_extra_instdone(dev, instdone);
2474
2475         if (IS_G4X(dev)) {
2476                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2477                         u32 ipeir = I915_READ(IPEIR_I965);
2478
2479                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2480                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2481                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2482                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2483                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2484                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2485                         I915_WRITE(IPEIR_I965, ipeir);
2486                         POSTING_READ(IPEIR_I965);
2487                 }
2488                 if (eir & GM45_ERROR_PAGE_TABLE) {
2489                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2490                         pr_err("page table error\n");
2491                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2492                         I915_WRITE(PGTBL_ER, pgtbl_err);
2493                         POSTING_READ(PGTBL_ER);
2494                 }
2495         }
2496
2497         if (!IS_GEN2(dev)) {
2498                 if (eir & I915_ERROR_PAGE_TABLE) {
2499                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2500                         pr_err("page table error\n");
2501                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2502                         I915_WRITE(PGTBL_ER, pgtbl_err);
2503                         POSTING_READ(PGTBL_ER);
2504                 }
2505         }
2506
2507         if (eir & I915_ERROR_MEMORY_REFRESH) {
2508                 pr_err("memory refresh error:\n");
2509                 for_each_pipe(dev_priv, pipe)
2510                         pr_err("pipe %c stat: 0x%08x\n",
2511                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2512                 /* pipestat has already been acked */
2513         }
2514         if (eir & I915_ERROR_INSTRUCTION) {
2515                 pr_err("instruction error\n");
2516                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2517                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2518                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2519                 if (INTEL_INFO(dev)->gen < 4) {
2520                         u32 ipeir = I915_READ(IPEIR);
2521
2522                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2523                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2524                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2525                         I915_WRITE(IPEIR, ipeir);
2526                         POSTING_READ(IPEIR);
2527                 } else {
2528                         u32 ipeir = I915_READ(IPEIR_I965);
2529
2530                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2531                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2532                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2533                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2534                         I915_WRITE(IPEIR_I965, ipeir);
2535                         POSTING_READ(IPEIR_I965);
2536                 }
2537         }
2538
2539         I915_WRITE(EIR, eir);
2540         POSTING_READ(EIR);
2541         eir = I915_READ(EIR);
2542         if (eir) {
2543                 /*
2544                  * some errors might have become stuck,
2545                  * mask them.
2546                  */
2547                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2548                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2549                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2550         }
2551 }
2552
2553 /**
2554  * i915_handle_error - handle a gpu error
2555  * @dev: drm device
2556  *
2557  * Do some basic checking of regsiter state at error time and
2558  * dump it to the syslog.  Also call i915_capture_error_state() to make
2559  * sure we get a record and make it available in debugfs.  Fire a uevent
2560  * so userspace knows something bad happened (should trigger collection
2561  * of a ring dump etc.).
2562  */
2563 void i915_handle_error(struct drm_device *dev, bool wedged,
2564                        const char *fmt, ...)
2565 {
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         va_list args;
2568         char error_msg[80];
2569
2570         va_start(args, fmt);
2571         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2572         va_end(args);
2573
2574         i915_capture_error_state(dev, wedged, error_msg);
2575         i915_report_and_clear_eir(dev);
2576
2577         if (wedged) {
2578                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2579                                 &dev_priv->gpu_error.reset_counter);
2580
2581                 /*
2582                  * Wakeup waiting processes so that the reset function
2583                  * i915_reset_and_wakeup doesn't deadlock trying to grab
2584                  * various locks. By bumping the reset counter first, the woken
2585                  * processes will see a reset in progress and back off,
2586                  * releasing their locks and then wait for the reset completion.
2587                  * We must do this for _all_ gpu waiters that might hold locks
2588                  * that the reset work needs to acquire.
2589                  *
2590                  * Note: The wake_up serves as the required memory barrier to
2591                  * ensure that the waiters see the updated value of the reset
2592                  * counter atomic_t.
2593                  */
2594                 i915_error_wake_up(dev_priv, false);
2595         }
2596
2597         i915_reset_and_wakeup(dev);
2598 }
2599
2600 /* Called from drm generic code, passed 'crtc' which
2601  * we use as a pipe index
2602  */
2603 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2604 {
2605         struct drm_i915_private *dev_priv = dev->dev_private;
2606         unsigned long irqflags;
2607
2608         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2609         if (INTEL_INFO(dev)->gen >= 4)
2610                 i915_enable_pipestat(dev_priv, pipe,
2611                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2612         else
2613                 i915_enable_pipestat(dev_priv, pipe,
2614                                      PIPE_VBLANK_INTERRUPT_STATUS);
2615         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2616
2617         return 0;
2618 }
2619
2620 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2621 {
2622         struct drm_i915_private *dev_priv = dev->dev_private;
2623         unsigned long irqflags;
2624         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2625                                                      DE_PIPE_VBLANK(pipe);
2626
2627         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2628         ironlake_enable_display_irq(dev_priv, bit);
2629         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2630
2631         return 0;
2632 }
2633
2634 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2635 {
2636         struct drm_i915_private *dev_priv = dev->dev_private;
2637         unsigned long irqflags;
2638
2639         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2640         i915_enable_pipestat(dev_priv, pipe,
2641                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2642         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2643
2644         return 0;
2645 }
2646
2647 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2648 {
2649         struct drm_i915_private *dev_priv = dev->dev_private;
2650         unsigned long irqflags;
2651
2652         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2653         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2654         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2655         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2656         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2657         return 0;
2658 }
2659
2660 /* Called from drm generic code, passed 'crtc' which
2661  * we use as a pipe index
2662  */
2663 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2664 {
2665         struct drm_i915_private *dev_priv = dev->dev_private;
2666         unsigned long irqflags;
2667
2668         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2669         i915_disable_pipestat(dev_priv, pipe,
2670                               PIPE_VBLANK_INTERRUPT_STATUS |
2671                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2672         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2673 }
2674
2675 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2676 {
2677         struct drm_i915_private *dev_priv = dev->dev_private;
2678         unsigned long irqflags;
2679         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2680                                                      DE_PIPE_VBLANK(pipe);
2681
2682         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2683         ironlake_disable_display_irq(dev_priv, bit);
2684         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2685 }
2686
2687 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2688 {
2689         struct drm_i915_private *dev_priv = dev->dev_private;
2690         unsigned long irqflags;
2691
2692         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2693         i915_disable_pipestat(dev_priv, pipe,
2694                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2695         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2696 }
2697
2698 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2699 {
2700         struct drm_i915_private *dev_priv = dev->dev_private;
2701         unsigned long irqflags;
2702
2703         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2704         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2705         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2706         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2707         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2708 }
2709
2710 static struct drm_i915_gem_request *
2711 ring_last_request(struct intel_engine_cs *ring)
2712 {
2713         return list_entry(ring->request_list.prev,
2714                           struct drm_i915_gem_request, list);
2715 }
2716
2717 static bool
2718 ring_idle(struct intel_engine_cs *ring)
2719 {
2720         return (list_empty(&ring->request_list) ||
2721                 i915_gem_request_completed(ring_last_request(ring), false));
2722 }
2723
2724 static bool
2725 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2726 {
2727         if (INTEL_INFO(dev)->gen >= 8) {
2728                 return (ipehr >> 23) == 0x1c;
2729         } else {
2730                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2731                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2732                                  MI_SEMAPHORE_REGISTER);
2733         }
2734 }
2735
2736 static struct intel_engine_cs *
2737 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2738 {
2739         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2740         struct intel_engine_cs *signaller;
2741         int i;
2742
2743         if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2744                 for_each_ring(signaller, dev_priv, i) {
2745                         if (ring == signaller)
2746                                 continue;
2747
2748                         if (offset == signaller->semaphore.signal_ggtt[ring->id])
2749                                 return signaller;
2750                 }
2751         } else {
2752                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2753
2754                 for_each_ring(signaller, dev_priv, i) {
2755                         if(ring == signaller)
2756                                 continue;
2757
2758                         if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2759                                 return signaller;
2760                 }
2761         }
2762
2763         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2764                   ring->id, ipehr, offset);
2765
2766         return NULL;
2767 }
2768
2769 static struct intel_engine_cs *
2770 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2771 {
2772         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2773         u32 cmd, ipehr, head;
2774         u64 offset = 0;
2775         int i, backwards;
2776
2777         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2778         if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2779                 return NULL;
2780
2781         /*
2782          * HEAD is likely pointing to the dword after the actual command,
2783          * so scan backwards until we find the MBOX. But limit it to just 3
2784          * or 4 dwords depending on the semaphore wait command size.
2785          * Note that we don't care about ACTHD here since that might
2786          * point at at batch, and semaphores are always emitted into the
2787          * ringbuffer itself.
2788          */
2789         head = I915_READ_HEAD(ring) & HEAD_ADDR;
2790         backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2791
2792         for (i = backwards; i; --i) {
2793                 /*
2794                  * Be paranoid and presume the hw has gone off into the wild -
2795                  * our ring is smaller than what the hardware (and hence
2796                  * HEAD_ADDR) allows. Also handles wrap-around.
2797                  */
2798                 head &= ring->buffer->size - 1;
2799
2800                 /* This here seems to blow up */
2801                 cmd = ioread32(ring->buffer->virtual_start + head);
2802                 if (cmd == ipehr)
2803                         break;
2804
2805                 head -= 4;
2806         }
2807
2808         if (!i)
2809                 return NULL;
2810
2811         *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2812         if (INTEL_INFO(ring->dev)->gen >= 8) {
2813                 offset = ioread32(ring->buffer->virtual_start + head + 12);
2814                 offset <<= 32;
2815                 offset = ioread32(ring->buffer->virtual_start + head + 8);
2816         }
2817         return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2818 }
2819
2820 static int semaphore_passed(struct intel_engine_cs *ring)
2821 {
2822         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2823         struct intel_engine_cs *signaller;
2824         u32 seqno;
2825
2826         ring->hangcheck.deadlock++;
2827
2828         signaller = semaphore_waits_for(ring, &seqno);
2829         if (signaller == NULL)
2830                 return -1;
2831
2832         /* Prevent pathological recursion due to driver bugs */
2833         if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2834                 return -1;
2835
2836         if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2837                 return 1;
2838
2839         /* cursory check for an unkickable deadlock */
2840         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2841             semaphore_passed(signaller) < 0)
2842                 return -1;
2843
2844         return 0;
2845 }
2846
2847 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2848 {
2849         struct intel_engine_cs *ring;
2850         int i;
2851
2852         for_each_ring(ring, dev_priv, i)
2853                 ring->hangcheck.deadlock = 0;
2854 }
2855
2856 static enum intel_ring_hangcheck_action
2857 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2858 {
2859         struct drm_device *dev = ring->dev;
2860         struct drm_i915_private *dev_priv = dev->dev_private;
2861         u32 tmp;
2862
2863         if (acthd != ring->hangcheck.acthd) {
2864                 if (acthd > ring->hangcheck.max_acthd) {
2865                         ring->hangcheck.max_acthd = acthd;
2866                         return HANGCHECK_ACTIVE;
2867                 }
2868
2869                 return HANGCHECK_ACTIVE_LOOP;
2870         }
2871
2872         if (IS_GEN2(dev))
2873                 return HANGCHECK_HUNG;
2874
2875         /* Is the chip hanging on a WAIT_FOR_EVENT?
2876          * If so we can simply poke the RB_WAIT bit
2877          * and break the hang. This should work on
2878          * all but the second generation chipsets.
2879          */
2880         tmp = I915_READ_CTL(ring);
2881         if (tmp & RING_WAIT) {
2882                 i915_handle_error(dev, false,
2883                                   "Kicking stuck wait on %s",
2884                                   ring->name);
2885                 I915_WRITE_CTL(ring, tmp);
2886                 return HANGCHECK_KICK;
2887         }
2888
2889         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2890                 switch (semaphore_passed(ring)) {
2891                 default:
2892                         return HANGCHECK_HUNG;
2893                 case 1:
2894                         i915_handle_error(dev, false,
2895                                           "Kicking stuck semaphore on %s",
2896                                           ring->name);
2897                         I915_WRITE_CTL(ring, tmp);
2898                         return HANGCHECK_KICK;
2899                 case 0:
2900                         return HANGCHECK_WAIT;
2901                 }
2902         }
2903
2904         return HANGCHECK_HUNG;
2905 }
2906
2907 /*
2908  * This is called when the chip hasn't reported back with completed
2909  * batchbuffers in a long time. We keep track per ring seqno progress and
2910  * if there are no progress, hangcheck score for that ring is increased.
2911  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2912  * we kick the ring. If we see no progress on three subsequent calls
2913  * we assume chip is wedged and try to fix it by resetting the chip.
2914  */
2915 static void i915_hangcheck_elapsed(struct work_struct *work)
2916 {
2917         struct drm_i915_private *dev_priv =
2918                 container_of(work, typeof(*dev_priv),
2919                              gpu_error.hangcheck_work.work);
2920         struct drm_device *dev = dev_priv->dev;
2921         struct intel_engine_cs *ring;
2922         int i;
2923         int busy_count = 0, rings_hung = 0;
2924         bool stuck[I915_NUM_RINGS] = { 0 };
2925 #define BUSY 1
2926 #define KICK 5
2927 #define HUNG 20
2928
2929         if (!i915.enable_hangcheck)
2930                 return;
2931
2932         for_each_ring(ring, dev_priv, i) {
2933                 u64 acthd;
2934                 u32 seqno;
2935                 bool busy = true;
2936
2937                 semaphore_clear_deadlocks(dev_priv);
2938
2939                 seqno = ring->get_seqno(ring, false);
2940                 acthd = intel_ring_get_active_head(ring);
2941
2942                 if (ring->hangcheck.seqno == seqno) {
2943                         if (ring_idle(ring)) {
2944                                 ring->hangcheck.action = HANGCHECK_IDLE;
2945
2946                                 if (waitqueue_active(&ring->irq_queue)) {
2947                                         /* Issue a wake-up to catch stuck h/w. */
2948                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2949                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2950                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2951                                                                   ring->name);
2952                                                 else
2953                                                         DRM_INFO("Fake missed irq on %s\n",
2954                                                                  ring->name);
2955                                                 wake_up_all(&ring->irq_queue);
2956                                         }
2957                                         /* Safeguard against driver failure */
2958                                         ring->hangcheck.score += BUSY;
2959                                 } else
2960                                         busy = false;
2961                         } else {
2962                                 /* We always increment the hangcheck score
2963                                  * if the ring is busy and still processing
2964                                  * the same request, so that no single request
2965                                  * can run indefinitely (such as a chain of
2966                                  * batches). The only time we do not increment
2967                                  * the hangcheck score on this ring, if this
2968                                  * ring is in a legitimate wait for another
2969                                  * ring. In that case the waiting ring is a
2970                                  * victim and we want to be sure we catch the
2971                                  * right culprit. Then every time we do kick
2972                                  * the ring, add a small increment to the
2973                                  * score so that we can catch a batch that is
2974                                  * being repeatedly kicked and so responsible
2975                                  * for stalling the machine.
2976                                  */
2977                                 ring->hangcheck.action = ring_stuck(ring,
2978                                                                     acthd);
2979
2980                                 switch (ring->hangcheck.action) {
2981                                 case HANGCHECK_IDLE:
2982                                 case HANGCHECK_WAIT:
2983                                 case HANGCHECK_ACTIVE:
2984                                         break;
2985                                 case HANGCHECK_ACTIVE_LOOP:
2986                                         ring->hangcheck.score += BUSY;
2987                                         break;
2988                                 case HANGCHECK_KICK:
2989                                         ring->hangcheck.score += KICK;
2990                                         break;
2991                                 case HANGCHECK_HUNG:
2992                                         ring->hangcheck.score += HUNG;
2993                                         stuck[i] = true;
2994                                         break;
2995                                 }
2996                         }
2997                 } else {
2998                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2999
3000                         /* Gradually reduce the count so that we catch DoS
3001                          * attempts across multiple batches.
3002                          */
3003                         if (ring->hangcheck.score > 0)
3004                                 ring->hangcheck.score--;
3005
3006                         ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3007                 }
3008
3009                 ring->hangcheck.seqno = seqno;
3010                 ring->hangcheck.acthd = acthd;
3011                 busy_count += busy;
3012         }
3013
3014         for_each_ring(ring, dev_priv, i) {
3015                 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3016                         DRM_INFO("%s on %s\n",
3017                                  stuck[i] ? "stuck" : "no progress",
3018                                  ring->name);
3019                         rings_hung++;
3020                 }
3021         }
3022
3023         if (rings_hung)
3024                 return i915_handle_error(dev, true, "Ring hung");
3025
3026         if (busy_count)
3027                 /* Reset timer case chip hangs without another request
3028                  * being added */
3029                 i915_queue_hangcheck(dev);
3030 }
3031
3032 void i915_queue_hangcheck(struct drm_device *dev)
3033 {
3034         struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
3035
3036         if (!i915.enable_hangcheck)
3037                 return;
3038
3039         /* Don't continually defer the hangcheck so that it is always run at
3040          * least once after work has been scheduled on any ring. Otherwise,
3041          * we will ignore a hung ring if a second ring is kept busy.
3042          */
3043
3044         queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3045                            round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3046 }
3047
3048 static void ibx_irq_reset(struct drm_device *dev)
3049 {
3050         struct drm_i915_private *dev_priv = dev->dev_private;
3051
3052         if (HAS_PCH_NOP(dev))
3053                 return;
3054
3055         GEN5_IRQ_RESET(SDE);
3056
3057         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3058                 I915_WRITE(SERR_INT, 0xffffffff);
3059 }
3060
3061 /*
3062  * SDEIER is also touched by the interrupt handler to work around missed PCH
3063  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3064  * instead we unconditionally enable all PCH interrupt sources here, but then
3065  * only unmask them as needed with SDEIMR.
3066  *
3067  * This function needs to be called before interrupts are enabled.
3068  */
3069 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3070 {
3071         struct drm_i915_private *dev_priv = dev->dev_private;
3072
3073         if (HAS_PCH_NOP(dev))
3074                 return;
3075
3076         WARN_ON(I915_READ(SDEIER) != 0);
3077         I915_WRITE(SDEIER, 0xffffffff);
3078         POSTING_READ(SDEIER);
3079 }
3080
3081 static void gen5_gt_irq_reset(struct drm_device *dev)
3082 {
3083         struct drm_i915_private *dev_priv = dev->dev_private;
3084
3085         GEN5_IRQ_RESET(GT);
3086         if (INTEL_INFO(dev)->gen >= 6)
3087                 GEN5_IRQ_RESET(GEN6_PM);
3088 }
3089
3090 /* drm_dma.h hooks
3091 */
3092 static void ironlake_irq_reset(struct drm_device *dev)
3093 {
3094         struct drm_i915_private *dev_priv = dev->dev_private;
3095
3096         I915_WRITE(HWSTAM, 0xffffffff);
3097
3098         GEN5_IRQ_RESET(DE);
3099         if (IS_GEN7(dev))
3100                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3101
3102         gen5_gt_irq_reset(dev);
3103
3104         ibx_irq_reset(dev);
3105 }
3106
3107 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3108 {
3109         enum pipe pipe;
3110
3111         I915_WRITE(PORT_HOTPLUG_EN, 0);
3112         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3113
3114         for_each_pipe(dev_priv, pipe)
3115                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3116
3117         GEN5_IRQ_RESET(VLV_);
3118 }
3119
3120 static void valleyview_irq_preinstall(struct drm_device *dev)
3121 {
3122         struct drm_i915_private *dev_priv = dev->dev_private;
3123
3124         /* VLV magic */
3125         I915_WRITE(VLV_IMR, 0);
3126         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3127         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3128         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3129
3130         gen5_gt_irq_reset(dev);
3131
3132         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3133
3134         vlv_display_irq_reset(dev_priv);
3135 }
3136
3137 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3138 {
3139         GEN8_IRQ_RESET_NDX(GT, 0);
3140         GEN8_IRQ_RESET_NDX(GT, 1);
3141         GEN8_IRQ_RESET_NDX(GT, 2);
3142         GEN8_IRQ_RESET_NDX(GT, 3);
3143 }
3144
3145 static void gen8_irq_reset(struct drm_device *dev)
3146 {
3147         struct drm_i915_private *dev_priv = dev->dev_private;
3148         int pipe;
3149
3150         I915_WRITE(GEN8_MASTER_IRQ, 0);
3151         POSTING_READ(GEN8_MASTER_IRQ);
3152
3153         gen8_gt_irq_reset(dev_priv);
3154
3155         for_each_pipe(dev_priv, pipe)
3156                 if (intel_display_power_is_enabled(dev_priv,
3157                                                    POWER_DOMAIN_PIPE(pipe)))
3158                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3159
3160         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3161         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3162         GEN5_IRQ_RESET(GEN8_PCU_);
3163
3164         ibx_irq_reset(dev);
3165 }
3166
3167 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3168                                      unsigned int pipe_mask)
3169 {
3170         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3171
3172         spin_lock_irq(&dev_priv->irq_lock);
3173         if (pipe_mask & 1 << PIPE_A)
3174                 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
3175                                   dev_priv->de_irq_mask[PIPE_A],
3176                                   ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
3177         if (pipe_mask & 1 << PIPE_B)
3178                 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
3179                                   dev_priv->de_irq_mask[PIPE_B],
3180                                   ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3181         if (pipe_mask & 1 << PIPE_C)
3182                 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
3183                                   dev_priv->de_irq_mask[PIPE_C],
3184                                   ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3185         spin_unlock_irq(&dev_priv->irq_lock);
3186 }
3187
3188 static void cherryview_irq_preinstall(struct drm_device *dev)
3189 {
3190         struct drm_i915_private *dev_priv = dev->dev_private;
3191
3192         I915_WRITE(GEN8_MASTER_IRQ, 0);
3193         POSTING_READ(GEN8_MASTER_IRQ);
3194
3195         gen8_gt_irq_reset(dev_priv);
3196
3197         GEN5_IRQ_RESET(GEN8_PCU_);
3198
3199         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3200
3201         vlv_display_irq_reset(dev_priv);
3202 }
3203
3204 static void ibx_hpd_irq_setup(struct drm_device *dev)
3205 {
3206         struct drm_i915_private *dev_priv = dev->dev_private;
3207         struct intel_encoder *intel_encoder;
3208         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3209
3210         if (HAS_PCH_IBX(dev)) {
3211                 hotplug_irqs = SDE_HOTPLUG_MASK;
3212                 for_each_intel_encoder(dev, intel_encoder)
3213                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3214                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3215         } else {
3216                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3217                 for_each_intel_encoder(dev, intel_encoder)
3218                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3219                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3220         }
3221
3222         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3223
3224         /*
3225          * Enable digital hotplug on the PCH, and configure the DP short pulse
3226          * duration to 2ms (which is the minimum in the Display Port spec)
3227          *
3228          * This register is the same on all known PCH chips.
3229          */
3230         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3231         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3232         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3233         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3234         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3235         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3236 }
3237
3238 static void ibx_irq_postinstall(struct drm_device *dev)
3239 {
3240         struct drm_i915_private *dev_priv = dev->dev_private;
3241         u32 mask;
3242
3243         if (HAS_PCH_NOP(dev))
3244                 return;
3245
3246         if (HAS_PCH_IBX(dev))
3247                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3248         else
3249                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3250
3251         GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3252         I915_WRITE(SDEIMR, ~mask);
3253 }
3254
3255 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3256 {
3257         struct drm_i915_private *dev_priv = dev->dev_private;
3258         u32 pm_irqs, gt_irqs;
3259
3260         pm_irqs = gt_irqs = 0;
3261
3262         dev_priv->gt_irq_mask = ~0;
3263         if (HAS_L3_DPF(dev)) {
3264                 /* L3 parity interrupt is always unmasked. */
3265                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3266                 gt_irqs |= GT_PARITY_ERROR(dev);
3267         }
3268
3269         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3270         if (IS_GEN5(dev)) {
3271                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3272                            ILK_BSD_USER_INTERRUPT;
3273         } else {
3274                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3275         }
3276
3277         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3278
3279         if (INTEL_INFO(dev)->gen >= 6) {
3280                 /*
3281                  * RPS interrupts will get enabled/disabled on demand when RPS
3282                  * itself is enabled/disabled.
3283                  */
3284                 if (HAS_VEBOX(dev))
3285                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3286
3287                 dev_priv->pm_irq_mask = 0xffffffff;
3288                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3289         }
3290 }
3291
3292 static int ironlake_irq_postinstall(struct drm_device *dev)
3293 {
3294         struct drm_i915_private *dev_priv = dev->dev_private;
3295         u32 display_mask, extra_mask;
3296
3297         if (INTEL_INFO(dev)->gen >= 7) {
3298                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3299                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3300                                 DE_PLANEB_FLIP_DONE_IVB |
3301                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3302                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3303                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3304         } else {
3305                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3306                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3307                                 DE_AUX_CHANNEL_A |
3308                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3309                                 DE_POISON);
3310                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3311                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3312         }
3313
3314         dev_priv->irq_mask = ~display_mask;
3315
3316         I915_WRITE(HWSTAM, 0xeffe);
3317
3318         ibx_irq_pre_postinstall(dev);
3319
3320         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3321
3322         gen5_gt_irq_postinstall(dev);
3323
3324         ibx_irq_postinstall(dev);
3325
3326         if (IS_IRONLAKE_M(dev)) {
3327                 /* Enable PCU event interrupts
3328                  *
3329                  * spinlocking not required here for correctness since interrupt
3330                  * setup is guaranteed to run in single-threaded context. But we
3331                  * need it to make the assert_spin_locked happy. */
3332                 spin_lock_irq(&dev_priv->irq_lock);
3333                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3334                 spin_unlock_irq(&dev_priv->irq_lock);
3335         }
3336
3337         return 0;
3338 }
3339
3340 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3341 {
3342         u32 pipestat_mask;
3343         u32 iir_mask;
3344         enum pipe pipe;
3345
3346         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3347                         PIPE_FIFO_UNDERRUN_STATUS;
3348
3349         for_each_pipe(dev_priv, pipe)
3350                 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3351         POSTING_READ(PIPESTAT(PIPE_A));
3352
3353         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3354                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3355
3356         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3357         for_each_pipe(dev_priv, pipe)
3358                       i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3359
3360         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3361                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3362                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3363         if (IS_CHERRYVIEW(dev_priv))
3364                 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3365         dev_priv->irq_mask &= ~iir_mask;
3366
3367         I915_WRITE(VLV_IIR, iir_mask);
3368         I915_WRITE(VLV_IIR, iir_mask);
3369         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3370         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3371         POSTING_READ(VLV_IMR);
3372 }
3373
3374 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3375 {
3376         u32 pipestat_mask;
3377         u32 iir_mask;
3378         enum pipe pipe;
3379
3380         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3381                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3382                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3383         if (IS_CHERRYVIEW(dev_priv))
3384                 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3385
3386         dev_priv->irq_mask |= iir_mask;
3387         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3388         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3389         I915_WRITE(VLV_IIR, iir_mask);
3390         I915_WRITE(VLV_IIR, iir_mask);
3391         POSTING_READ(VLV_IIR);
3392
3393         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3394                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3395
3396         i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3397         for_each_pipe(dev_priv, pipe)
3398                 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3399
3400         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3401                         PIPE_FIFO_UNDERRUN_STATUS;
3402
3403         for_each_pipe(dev_priv, pipe)
3404                 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3405         POSTING_READ(PIPESTAT(PIPE_A));
3406 }
3407
3408 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3409 {
3410         assert_spin_locked(&dev_priv->irq_lock);
3411
3412         if (dev_priv->display_irqs_enabled)
3413                 return;
3414
3415         dev_priv->display_irqs_enabled = true;
3416
3417         if (intel_irqs_enabled(dev_priv))
3418                 valleyview_display_irqs_install(dev_priv);
3419 }
3420
3421 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3422 {
3423         assert_spin_locked(&dev_priv->irq_lock);
3424
3425         if (!dev_priv->display_irqs_enabled)
3426                 return;
3427
3428         dev_priv->display_irqs_enabled = false;
3429
3430         if (intel_irqs_enabled(dev_priv))
3431                 valleyview_display_irqs_uninstall(dev_priv);
3432 }
3433
3434 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3435 {
3436         dev_priv->irq_mask = ~0;
3437
3438         I915_WRITE(PORT_HOTPLUG_EN, 0);
3439         POSTING_READ(PORT_HOTPLUG_EN);
3440
3441         I915_WRITE(VLV_IIR, 0xffffffff);
3442         I915_WRITE(VLV_IIR, 0xffffffff);
3443         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3444         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3445         POSTING_READ(VLV_IMR);
3446
3447         /* Interrupt setup is already guaranteed to be single-threaded, this is
3448          * just to make the assert_spin_locked check happy. */
3449         spin_lock_irq(&dev_priv->irq_lock);
3450         if (dev_priv->display_irqs_enabled)
3451                 valleyview_display_irqs_install(dev_priv);
3452         spin_unlock_irq(&dev_priv->irq_lock);
3453 }
3454
3455 static int valleyview_irq_postinstall(struct drm_device *dev)
3456 {
3457         struct drm_i915_private *dev_priv = dev->dev_private;
3458
3459         vlv_display_irq_postinstall(dev_priv);
3460
3461         gen5_gt_irq_postinstall(dev);
3462
3463         /* ack & enable invalid PTE error interrupts */
3464 #if 0 /* FIXME: add support to irq handler for checking these bits */
3465         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3466         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3467 #endif
3468
3469         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3470
3471         return 0;
3472 }
3473
3474 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3475 {
3476         /* These are interrupts we'll toggle with the ring mask register */
3477         uint32_t gt_interrupts[] = {
3478                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3479                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3480                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3481                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3482                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3483                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3484                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3485                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3486                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3487                 0,
3488                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3489                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3490                 };
3491
3492         dev_priv->pm_irq_mask = 0xffffffff;
3493         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3494         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3495         /*
3496          * RPS interrupts will get enabled/disabled on demand when RPS itself
3497          * is enabled/disabled.
3498          */
3499         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3500         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3501 }
3502
3503 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3504 {
3505         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3506         uint32_t de_pipe_enables;
3507         int pipe;
3508         u32 aux_en = GEN8_AUX_CHANNEL_A;
3509
3510         if (IS_GEN9(dev_priv)) {
3511                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3512                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3513                 aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3514                         GEN9_AUX_CHANNEL_D;
3515         } else
3516                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3517                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3518
3519         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3520                                            GEN8_PIPE_FIFO_UNDERRUN;
3521
3522         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3523         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3524         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3525
3526         for_each_pipe(dev_priv, pipe)
3527                 if (intel_display_power_is_enabled(dev_priv,
3528                                 POWER_DOMAIN_PIPE(pipe)))
3529                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3530                                           dev_priv->de_irq_mask[pipe],
3531                                           de_pipe_enables);
3532
3533         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
3534 }
3535
3536 static int gen8_irq_postinstall(struct drm_device *dev)
3537 {
3538         struct drm_i915_private *dev_priv = dev->dev_private;
3539
3540         ibx_irq_pre_postinstall(dev);
3541
3542         gen8_gt_irq_postinstall(dev_priv);
3543         gen8_de_irq_postinstall(dev_priv);
3544
3545         ibx_irq_postinstall(dev);
3546
3547         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3548         POSTING_READ(GEN8_MASTER_IRQ);
3549
3550         return 0;
3551 }
3552
3553 static int cherryview_irq_postinstall(struct drm_device *dev)
3554 {
3555         struct drm_i915_private *dev_priv = dev->dev_private;
3556
3557         vlv_display_irq_postinstall(dev_priv);
3558
3559         gen8_gt_irq_postinstall(dev_priv);
3560
3561         I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3562         POSTING_READ(GEN8_MASTER_IRQ);
3563
3564         return 0;
3565 }
3566
3567 static void gen8_irq_uninstall(struct drm_device *dev)
3568 {
3569         struct drm_i915_private *dev_priv = dev->dev_private;
3570
3571         if (!dev_priv)
3572                 return;
3573
3574         gen8_irq_reset(dev);
3575 }
3576
3577 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3578 {
3579         /* Interrupt setup is already guaranteed to be single-threaded, this is
3580          * just to make the assert_spin_locked check happy. */
3581         spin_lock_irq(&dev_priv->irq_lock);
3582         if (dev_priv->display_irqs_enabled)
3583                 valleyview_display_irqs_uninstall(dev_priv);
3584         spin_unlock_irq(&dev_priv->irq_lock);
3585
3586         vlv_display_irq_reset(dev_priv);
3587
3588         dev_priv->irq_mask = ~0;
3589 }
3590
3591 static void valleyview_irq_uninstall(struct drm_device *dev)
3592 {
3593         struct drm_i915_private *dev_priv = dev->dev_private;
3594
3595         if (!dev_priv)
3596                 return;
3597
3598         I915_WRITE(VLV_MASTER_IER, 0);
3599
3600         gen5_gt_irq_reset(dev);
3601
3602         I915_WRITE(HWSTAM, 0xffffffff);
3603
3604         vlv_display_irq_uninstall(dev_priv);
3605 }
3606
3607 static void cherryview_irq_uninstall(struct drm_device *dev)
3608 {
3609         struct drm_i915_private *dev_priv = dev->dev_private;
3610
3611         if (!dev_priv)
3612                 return;
3613
3614         I915_WRITE(GEN8_MASTER_IRQ, 0);
3615         POSTING_READ(GEN8_MASTER_IRQ);
3616
3617         gen8_gt_irq_reset(dev_priv);
3618
3619         GEN5_IRQ_RESET(GEN8_PCU_);
3620
3621         vlv_display_irq_uninstall(dev_priv);
3622 }
3623
3624 static void ironlake_irq_uninstall(struct drm_device *dev)
3625 {
3626         struct drm_i915_private *dev_priv = dev->dev_private;
3627
3628         if (!dev_priv)
3629                 return;
3630
3631         ironlake_irq_reset(dev);
3632 }
3633
3634 static void i8xx_irq_preinstall(struct drm_device * dev)
3635 {
3636         struct drm_i915_private *dev_priv = dev->dev_private;
3637         int pipe;
3638
3639         for_each_pipe(dev_priv, pipe)
3640                 I915_WRITE(PIPESTAT(pipe), 0);
3641         I915_WRITE16(IMR, 0xffff);
3642         I915_WRITE16(IER, 0x0);
3643         POSTING_READ16(IER);
3644 }
3645
3646 static int i8xx_irq_postinstall(struct drm_device *dev)
3647 {
3648         struct drm_i915_private *dev_priv = dev->dev_private;
3649
3650         I915_WRITE16(EMR,
3651                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3652
3653         /* Unmask the interrupts that we always want on. */
3654         dev_priv->irq_mask =
3655                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3656                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3657                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3658                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3659                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3660         I915_WRITE16(IMR, dev_priv->irq_mask);
3661
3662         I915_WRITE16(IER,
3663                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3664                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3665                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3666                      I915_USER_INTERRUPT);
3667         POSTING_READ16(IER);
3668
3669         /* Interrupt setup is already guaranteed to be single-threaded, this is
3670          * just to make the assert_spin_locked check happy. */
3671         spin_lock_irq(&dev_priv->irq_lock);
3672         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3673         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3674         spin_unlock_irq(&dev_priv->irq_lock);
3675
3676         return 0;
3677 }
3678
3679 /*
3680  * Returns true when a page flip has completed.
3681  */
3682 static bool i8xx_handle_vblank(struct drm_device *dev,
3683                                int plane, int pipe, u32 iir)
3684 {
3685         struct drm_i915_private *dev_priv = dev->dev_private;
3686         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3687
3688         if (!intel_pipe_handle_vblank(dev, pipe))
3689                 return false;
3690
3691         if ((iir & flip_pending) == 0)
3692                 goto check_page_flip;
3693
3694         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3695          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3696          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3697          * the flip is completed (no longer pending). Since this doesn't raise
3698          * an interrupt per se, we watch for the change at vblank.
3699          */
3700         if (I915_READ16(ISR) & flip_pending)
3701                 goto check_page_flip;
3702
3703         intel_prepare_page_flip(dev, plane);
3704         intel_finish_page_flip(dev, pipe);
3705         return true;
3706
3707 check_page_flip:
3708         intel_check_page_flip(dev, pipe);
3709         return false;
3710 }
3711
3712 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3713 {
3714         struct drm_device *dev = arg;
3715         struct drm_i915_private *dev_priv = dev->dev_private;
3716         u16 iir, new_iir;
3717         u32 pipe_stats[2];
3718         int pipe;
3719         u16 flip_mask =
3720                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3721                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3722
3723         if (!intel_irqs_enabled(dev_priv))
3724                 return IRQ_NONE;
3725
3726         iir = I915_READ16(IIR);
3727         if (iir == 0)
3728                 return IRQ_NONE;
3729
3730         while (iir & ~flip_mask) {
3731                 /* Can't rely on pipestat interrupt bit in iir as it might
3732                  * have been cleared after the pipestat interrupt was received.
3733                  * It doesn't set the bit in iir again, but it still produces
3734                  * interrupts (for non-MSI).
3735                  */
3736                 spin_lock(&dev_priv->irq_lock);
3737                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3738                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3739
3740                 for_each_pipe(dev_priv, pipe) {
3741                         int reg = PIPESTAT(pipe);
3742                         pipe_stats[pipe] = I915_READ(reg);
3743
3744                         /*
3745                          * Clear the PIPE*STAT regs before the IIR
3746                          */
3747                         if (pipe_stats[pipe] & 0x8000ffff)
3748                                 I915_WRITE(reg, pipe_stats[pipe]);
3749                 }
3750                 spin_unlock(&dev_priv->irq_lock);
3751
3752                 I915_WRITE16(IIR, iir & ~flip_mask);
3753                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3754
3755                 if (iir & I915_USER_INTERRUPT)
3756                         notify_ring(dev, &dev_priv->ring[RCS]);
3757
3758                 for_each_pipe(dev_priv, pipe) {
3759                         int plane = pipe;
3760                         if (HAS_FBC(dev))
3761                                 plane = !plane;
3762
3763                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3764                             i8xx_handle_vblank(dev, plane, pipe, iir))
3765                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3766
3767                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3768                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3769
3770                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3771                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3772                                                                     pipe);
3773                 }
3774
3775                 iir = new_iir;
3776         }
3777
3778         return IRQ_HANDLED;
3779 }
3780
3781 static void i8xx_irq_uninstall(struct drm_device * dev)
3782 {
3783         struct drm_i915_private *dev_priv = dev->dev_private;
3784         int pipe;
3785
3786         for_each_pipe(dev_priv, pipe) {
3787                 /* Clear enable bits; then clear status bits */
3788                 I915_WRITE(PIPESTAT(pipe), 0);
3789                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3790         }
3791         I915_WRITE16(IMR, 0xffff);
3792         I915_WRITE16(IER, 0x0);
3793         I915_WRITE16(IIR, I915_READ16(IIR));
3794 }
3795
3796 static void i915_irq_preinstall(struct drm_device * dev)
3797 {
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799         int pipe;
3800
3801         if (I915_HAS_HOTPLUG(dev)) {
3802                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3803                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3804         }
3805
3806         I915_WRITE16(HWSTAM, 0xeffe);
3807         for_each_pipe(dev_priv, pipe)
3808                 I915_WRITE(PIPESTAT(pipe), 0);
3809         I915_WRITE(IMR, 0xffffffff);
3810         I915_WRITE(IER, 0x0);
3811         POSTING_READ(IER);
3812 }
3813
3814 static int i915_irq_postinstall(struct drm_device *dev)
3815 {
3816         struct drm_i915_private *dev_priv = dev->dev_private;
3817         u32 enable_mask;
3818
3819         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3820
3821         /* Unmask the interrupts that we always want on. */
3822         dev_priv->irq_mask =
3823                 ~(I915_ASLE_INTERRUPT |
3824                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3825                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3826                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3827                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3828                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3829
3830         enable_mask =
3831                 I915_ASLE_INTERRUPT |
3832                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3833                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3834                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3835                 I915_USER_INTERRUPT;
3836
3837         if (I915_HAS_HOTPLUG(dev)) {
3838                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3839                 POSTING_READ(PORT_HOTPLUG_EN);
3840
3841                 /* Enable in IER... */
3842                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3843                 /* and unmask in IMR */
3844                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3845         }
3846
3847         I915_WRITE(IMR, dev_priv->irq_mask);
3848         I915_WRITE(IER, enable_mask);
3849         POSTING_READ(IER);
3850
3851         i915_enable_asle_pipestat(dev);
3852
3853         /* Interrupt setup is already guaranteed to be single-threaded, this is
3854          * just to make the assert_spin_locked check happy. */
3855         spin_lock_irq(&dev_priv->irq_lock);
3856         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3857         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3858         spin_unlock_irq(&dev_priv->irq_lock);
3859
3860         return 0;
3861 }
3862
3863 /*
3864  * Returns true when a page flip has completed.
3865  */
3866 static bool i915_handle_vblank(struct drm_device *dev,
3867                                int plane, int pipe, u32 iir)
3868 {
3869         struct drm_i915_private *dev_priv = dev->dev_private;
3870         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3871
3872         if (!intel_pipe_handle_vblank(dev, pipe))
3873                 return false;
3874
3875         if ((iir & flip_pending) == 0)
3876                 goto check_page_flip;
3877
3878         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3879          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3880          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3881          * the flip is completed (no longer pending). Since this doesn't raise
3882          * an interrupt per se, we watch for the change at vblank.
3883          */
3884         if (I915_READ(ISR) & flip_pending)
3885                 goto check_page_flip;
3886
3887         intel_prepare_page_flip(dev, plane);
3888         intel_finish_page_flip(dev, pipe);
3889         return true;
3890
3891 check_page_flip:
3892         intel_check_page_flip(dev, pipe);
3893         return false;
3894 }
3895
3896 static irqreturn_t i915_irq_handler(int irq, void *arg)
3897 {
3898         struct drm_device *dev = arg;
3899         struct drm_i915_private *dev_priv = dev->dev_private;
3900         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3901         u32 flip_mask =
3902                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3903                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3904         int pipe, ret = IRQ_NONE;
3905
3906         if (!intel_irqs_enabled(dev_priv))
3907                 return IRQ_NONE;
3908
3909         iir = I915_READ(IIR);
3910         do {
3911                 bool irq_received = (iir & ~flip_mask) != 0;
3912                 bool blc_event = false;
3913
3914                 /* Can't rely on pipestat interrupt bit in iir as it might
3915                  * have been cleared after the pipestat interrupt was received.
3916                  * It doesn't set the bit in iir again, but it still produces
3917                  * interrupts (for non-MSI).
3918                  */
3919                 spin_lock(&dev_priv->irq_lock);
3920                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3921                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3922
3923                 for_each_pipe(dev_priv, pipe) {
3924                         int reg = PIPESTAT(pipe);
3925                         pipe_stats[pipe] = I915_READ(reg);
3926
3927                         /* Clear the PIPE*STAT regs before the IIR */
3928                         if (pipe_stats[pipe] & 0x8000ffff) {
3929                                 I915_WRITE(reg, pipe_stats[pipe]);
3930                                 irq_received = true;
3931                         }
3932                 }
3933                 spin_unlock(&dev_priv->irq_lock);
3934
3935                 if (!irq_received)
3936                         break;
3937
3938                 /* Consume port.  Then clear IIR or we'll miss events */
3939                 if (I915_HAS_HOTPLUG(dev) &&
3940                     iir & I915_DISPLAY_PORT_INTERRUPT)
3941                         i9xx_hpd_irq_handler(dev);
3942
3943                 I915_WRITE(IIR, iir & ~flip_mask);
3944                 new_iir = I915_READ(IIR); /* Flush posted writes */
3945
3946                 if (iir & I915_USER_INTERRUPT)
3947                         notify_ring(dev, &dev_priv->ring[RCS]);
3948
3949                 for_each_pipe(dev_priv, pipe) {
3950                         int plane = pipe;
3951                         if (HAS_FBC(dev))
3952                                 plane = !plane;
3953
3954                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3955                             i915_handle_vblank(dev, plane, pipe, iir))
3956                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3957
3958                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3959                                 blc_event = true;
3960
3961                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3962                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3963
3964                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3965                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3966                                                                     pipe);
3967                 }
3968
3969                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3970                         intel_opregion_asle_intr(dev);
3971
3972                 /* With MSI, interrupts are only generated when iir
3973                  * transitions from zero to nonzero.  If another bit got
3974                  * set while we were handling the existing iir bits, then
3975                  * we would never get another interrupt.
3976                  *
3977                  * This is fine on non-MSI as well, as if we hit this path
3978                  * we avoid exiting the interrupt handler only to generate
3979                  * another one.
3980                  *
3981                  * Note that for MSI this could cause a stray interrupt report
3982                  * if an interrupt landed in the time between writing IIR and
3983                  * the posting read.  This should be rare enough to never
3984                  * trigger the 99% of 100,000 interrupts test for disabling
3985                  * stray interrupts.
3986                  */
3987                 ret = IRQ_HANDLED;
3988                 iir = new_iir;
3989         } while (iir & ~flip_mask);
3990
3991         return ret;
3992 }
3993
3994 static void i915_irq_uninstall(struct drm_device * dev)
3995 {
3996         struct drm_i915_private *dev_priv = dev->dev_private;
3997         int pipe;
3998
3999         if (I915_HAS_HOTPLUG(dev)) {
4000                 I915_WRITE(PORT_HOTPLUG_EN, 0);
4001                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4002         }
4003
4004         I915_WRITE16(HWSTAM, 0xffff);
4005         for_each_pipe(dev_priv, pipe) {
4006                 /* Clear enable bits; then clear status bits */
4007                 I915_WRITE(PIPESTAT(pipe), 0);
4008                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4009         }
4010         I915_WRITE(IMR, 0xffffffff);
4011         I915_WRITE(IER, 0x0);
4012
4013         I915_WRITE(IIR, I915_READ(IIR));
4014 }
4015
4016 static void i965_irq_preinstall(struct drm_device * dev)
4017 {
4018         struct drm_i915_private *dev_priv = dev->dev_private;
4019         int pipe;
4020
4021         I915_WRITE(PORT_HOTPLUG_EN, 0);
4022         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4023
4024         I915_WRITE(HWSTAM, 0xeffe);
4025         for_each_pipe(dev_priv, pipe)
4026                 I915_WRITE(PIPESTAT(pipe), 0);
4027         I915_WRITE(IMR, 0xffffffff);
4028         I915_WRITE(IER, 0x0);
4029         POSTING_READ(IER);
4030 }
4031
4032 static int i965_irq_postinstall(struct drm_device *dev)
4033 {
4034         struct drm_i915_private *dev_priv = dev->dev_private;
4035         u32 enable_mask;
4036         u32 error_mask;
4037
4038         /* Unmask the interrupts that we always want on. */
4039         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4040                                I915_DISPLAY_PORT_INTERRUPT |
4041                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4042                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4043                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4044                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4045                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4046
4047         enable_mask = ~dev_priv->irq_mask;
4048         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4049                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4050         enable_mask |= I915_USER_INTERRUPT;
4051
4052         if (IS_G4X(dev))
4053                 enable_mask |= I915_BSD_USER_INTERRUPT;
4054
4055         /* Interrupt setup is already guaranteed to be single-threaded, this is
4056          * just to make the assert_spin_locked check happy. */
4057         spin_lock_irq(&dev_priv->irq_lock);
4058         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4059         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4060         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4061         spin_unlock_irq(&dev_priv->irq_lock);
4062
4063         /*
4064          * Enable some error detection, note the instruction error mask
4065          * bit is reserved, so we leave it masked.
4066          */
4067         if (IS_G4X(dev)) {
4068                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4069                                GM45_ERROR_MEM_PRIV |
4070                                GM45_ERROR_CP_PRIV |
4071                                I915_ERROR_MEMORY_REFRESH);
4072         } else {
4073                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4074                                I915_ERROR_MEMORY_REFRESH);
4075         }
4076         I915_WRITE(EMR, error_mask);
4077
4078         I915_WRITE(IMR, dev_priv->irq_mask);
4079         I915_WRITE(IER, enable_mask);
4080         POSTING_READ(IER);
4081
4082         I915_WRITE(PORT_HOTPLUG_EN, 0);
4083         POSTING_READ(PORT_HOTPLUG_EN);
4084
4085         i915_enable_asle_pipestat(dev);
4086
4087         return 0;
4088 }
4089
4090 static void i915_hpd_irq_setup(struct drm_device *dev)
4091 {
4092         struct drm_i915_private *dev_priv = dev->dev_private;
4093         struct intel_encoder *intel_encoder;
4094         u32 hotplug_en;
4095
4096         assert_spin_locked(&dev_priv->irq_lock);
4097
4098         hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4099         hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4100         /* Note HDMI and DP share hotplug bits */
4101         /* enable bits are the same for all generations */
4102         for_each_intel_encoder(dev, intel_encoder)
4103                 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4104                         hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4105         /* Programming the CRT detection parameters tends
4106            to generate a spurious hotplug event about three
4107            seconds later.  So just do it once.
4108         */
4109         if (IS_G4X(dev))
4110                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4111         hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4112         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4113
4114         /* Ignore TV since it's buggy */
4115         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4116 }
4117
4118 static irqreturn_t i965_irq_handler(int irq, void *arg)
4119 {
4120         struct drm_device *dev = arg;
4121         struct drm_i915_private *dev_priv = dev->dev_private;
4122         u32 iir, new_iir;
4123         u32 pipe_stats[I915_MAX_PIPES];
4124         int ret = IRQ_NONE, pipe;
4125         u32 flip_mask =
4126                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4127                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4128
4129         if (!intel_irqs_enabled(dev_priv))
4130                 return IRQ_NONE;
4131
4132         iir = I915_READ(IIR);
4133
4134         for (;;) {
4135                 bool irq_received = (iir & ~flip_mask) != 0;
4136                 bool blc_event = false;
4137
4138                 /* Can't rely on pipestat interrupt bit in iir as it might
4139                  * have been cleared after the pipestat interrupt was received.
4140                  * It doesn't set the bit in iir again, but it still produces
4141                  * interrupts (for non-MSI).
4142                  */
4143                 spin_lock(&dev_priv->irq_lock);
4144                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4145                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4146
4147                 for_each_pipe(dev_priv, pipe) {
4148                         int reg = PIPESTAT(pipe);
4149                         pipe_stats[pipe] = I915_READ(reg);
4150
4151                         /*
4152                          * Clear the PIPE*STAT regs before the IIR
4153                          */
4154                         if (pipe_stats[pipe] & 0x8000ffff) {
4155                                 I915_WRITE(reg, pipe_stats[pipe]);
4156                                 irq_received = true;
4157                         }
4158                 }
4159                 spin_unlock(&dev_priv->irq_lock);
4160
4161                 if (!irq_received)
4162                         break;
4163
4164                 ret = IRQ_HANDLED;
4165
4166                 /* Consume port.  Then clear IIR or we'll miss events */
4167                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4168                         i9xx_hpd_irq_handler(dev);
4169
4170                 I915_WRITE(IIR, iir & ~flip_mask);
4171                 new_iir = I915_READ(IIR); /* Flush posted writes */
4172
4173                 if (iir & I915_USER_INTERRUPT)
4174                         notify_ring(dev, &dev_priv->ring[RCS]);
4175                 if (iir & I915_BSD_USER_INTERRUPT)
4176                         notify_ring(dev, &dev_priv->ring[VCS]);
4177
4178                 for_each_pipe(dev_priv, pipe) {
4179                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4180                             i915_handle_vblank(dev, pipe, pipe, iir))
4181                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4182
4183                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4184                                 blc_event = true;
4185
4186                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4187                                 i9xx_pipe_crc_irq_handler(dev, pipe);
4188
4189                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4190                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4191                 }
4192
4193                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4194                         intel_opregion_asle_intr(dev);
4195
4196                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4197                         gmbus_irq_handler(dev);
4198
4199                 /* With MSI, interrupts are only generated when iir
4200                  * transitions from zero to nonzero.  If another bit got
4201                  * set while we were handling the existing iir bits, then
4202                  * we would never get another interrupt.
4203                  *
4204                  * This is fine on non-MSI as well, as if we hit this path
4205                  * we avoid exiting the interrupt handler only to generate
4206                  * another one.
4207                  *
4208                  * Note that for MSI this could cause a stray interrupt report
4209                  * if an interrupt landed in the time between writing IIR and
4210                  * the posting read.  This should be rare enough to never
4211                  * trigger the 99% of 100,000 interrupts test for disabling
4212                  * stray interrupts.
4213                  */
4214                 iir = new_iir;
4215         }
4216
4217         return ret;
4218 }
4219
4220 static void i965_irq_uninstall(struct drm_device * dev)
4221 {
4222         struct drm_i915_private *dev_priv = dev->dev_private;
4223         int pipe;
4224
4225         if (!dev_priv)
4226                 return;
4227
4228         I915_WRITE(PORT_HOTPLUG_EN, 0);
4229         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4230
4231         I915_WRITE(HWSTAM, 0xffffffff);
4232         for_each_pipe(dev_priv, pipe)
4233                 I915_WRITE(PIPESTAT(pipe), 0);
4234         I915_WRITE(IMR, 0xffffffff);
4235         I915_WRITE(IER, 0x0);
4236
4237         for_each_pipe(dev_priv, pipe)
4238                 I915_WRITE(PIPESTAT(pipe),
4239                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4240         I915_WRITE(IIR, I915_READ(IIR));
4241 }
4242
4243 static void intel_hpd_irq_reenable_work(struct work_struct *work)
4244 {
4245         struct drm_i915_private *dev_priv =
4246                 container_of(work, typeof(*dev_priv),
4247                              hotplug_reenable_work.work);
4248         struct drm_device *dev = dev_priv->dev;
4249         struct drm_mode_config *mode_config = &dev->mode_config;
4250         int i;
4251
4252         intel_runtime_pm_get(dev_priv);
4253
4254         spin_lock_irq(&dev_priv->irq_lock);
4255         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4256                 struct drm_connector *connector;
4257
4258                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4259                         continue;
4260
4261                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4262
4263                 list_for_each_entry(connector, &mode_config->connector_list, head) {
4264                         struct intel_connector *intel_connector = to_intel_connector(connector);
4265
4266                         if (intel_connector->encoder->hpd_pin == i) {
4267                                 if (connector->polled != intel_connector->polled)
4268                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4269                                                          connector->name);
4270                                 connector->polled = intel_connector->polled;
4271                                 if (!connector->polled)
4272                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4273                         }
4274                 }
4275         }
4276         if (dev_priv->display.hpd_irq_setup)
4277                 dev_priv->display.hpd_irq_setup(dev);
4278         spin_unlock_irq(&dev_priv->irq_lock);
4279
4280         intel_runtime_pm_put(dev_priv);
4281 }
4282
4283 /**
4284  * intel_irq_init - initializes irq support
4285  * @dev_priv: i915 device instance
4286  *
4287  * This function initializes all the irq support including work items, timers
4288  * and all the vtables. It does not setup the interrupt itself though.
4289  */
4290 void intel_irq_init(struct drm_i915_private *dev_priv)
4291 {
4292         struct drm_device *dev = dev_priv->dev;
4293
4294         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4295         INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4296         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4297         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4298
4299         /* Let's track the enabled rps events */
4300         if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4301                 /* WaGsvRC0ResidencyMethod:vlv */
4302                 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4303         else
4304                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4305
4306         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4307                           i915_hangcheck_elapsed);
4308         INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4309                           intel_hpd_irq_reenable_work);
4310
4311         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4312
4313         if (IS_GEN2(dev_priv)) {
4314                 dev->max_vblank_count = 0;
4315                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4316         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4317                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4318                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4319         } else {
4320                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4321                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4322         }
4323
4324         /*
4325          * Opt out of the vblank disable timer on everything except gen2.
4326          * Gen2 doesn't have a hardware frame counter and so depends on
4327          * vblank interrupts to produce sane vblank seuquence numbers.
4328          */
4329         if (!IS_GEN2(dev_priv))
4330                 dev->vblank_disable_immediate = true;
4331
4332         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4333         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4334
4335         if (IS_CHERRYVIEW(dev_priv)) {
4336                 dev->driver->irq_handler = cherryview_irq_handler;
4337                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4338                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4339                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4340                 dev->driver->enable_vblank = valleyview_enable_vblank;
4341                 dev->driver->disable_vblank = valleyview_disable_vblank;
4342                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4343         } else if (IS_VALLEYVIEW(dev_priv)) {
4344                 dev->driver->irq_handler = valleyview_irq_handler;
4345                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4346                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4347                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4348                 dev->driver->enable_vblank = valleyview_enable_vblank;
4349                 dev->driver->disable_vblank = valleyview_disable_vblank;
4350                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4351         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4352                 dev->driver->irq_handler = gen8_irq_handler;
4353                 dev->driver->irq_preinstall = gen8_irq_reset;
4354                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4355                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4356                 dev->driver->enable_vblank = gen8_enable_vblank;
4357                 dev->driver->disable_vblank = gen8_disable_vblank;
4358                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4359         } else if (HAS_PCH_SPLIT(dev)) {
4360                 dev->driver->irq_handler = ironlake_irq_handler;
4361                 dev->driver->irq_preinstall = ironlake_irq_reset;
4362                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4363                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4364                 dev->driver->enable_vblank = ironlake_enable_vblank;
4365                 dev->driver->disable_vblank = ironlake_disable_vblank;
4366                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4367         } else {
4368                 if (INTEL_INFO(dev_priv)->gen == 2) {
4369                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4370                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4371                         dev->driver->irq_handler = i8xx_irq_handler;
4372                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4373                 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4374                         dev->driver->irq_preinstall = i915_irq_preinstall;
4375                         dev->driver->irq_postinstall = i915_irq_postinstall;
4376                         dev->driver->irq_uninstall = i915_irq_uninstall;
4377                         dev->driver->irq_handler = i915_irq_handler;
4378                 } else {
4379                         dev->driver->irq_preinstall = i965_irq_preinstall;
4380                         dev->driver->irq_postinstall = i965_irq_postinstall;
4381                         dev->driver->irq_uninstall = i965_irq_uninstall;
4382                         dev->driver->irq_handler = i965_irq_handler;
4383                 }
4384                 if (I915_HAS_HOTPLUG(dev_priv))
4385                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4386                 dev->driver->enable_vblank = i915_enable_vblank;
4387                 dev->driver->disable_vblank = i915_disable_vblank;
4388         }
4389 }
4390
4391 /**
4392  * intel_hpd_init - initializes and enables hpd support
4393  * @dev_priv: i915 device instance
4394  *
4395  * This function enables the hotplug support. It requires that interrupts have
4396  * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4397  * poll request can run concurrently to other code, so locking rules must be
4398  * obeyed.
4399  *
4400  * This is a separate step from interrupt enabling to simplify the locking rules
4401  * in the driver load and resume code.
4402  */
4403 void intel_hpd_init(struct drm_i915_private *dev_priv)
4404 {
4405         struct drm_device *dev = dev_priv->dev;
4406         struct drm_mode_config *mode_config = &dev->mode_config;
4407         struct drm_connector *connector;
4408         int i;
4409
4410         for (i = 1; i < HPD_NUM_PINS; i++) {
4411                 dev_priv->hpd_stats[i].hpd_cnt = 0;
4412                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4413         }
4414         list_for_each_entry(connector, &mode_config->connector_list, head) {
4415                 struct intel_connector *intel_connector = to_intel_connector(connector);
4416                 connector->polled = intel_connector->polled;
4417                 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4418                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4419                 if (intel_connector->mst_port)
4420                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4421         }
4422
4423         /* Interrupt setup is already guaranteed to be single-threaded, this is
4424          * just to make the assert_spin_locked checks happy. */
4425         spin_lock_irq(&dev_priv->irq_lock);
4426         if (dev_priv->display.hpd_irq_setup)
4427                 dev_priv->display.hpd_irq_setup(dev);
4428         spin_unlock_irq(&dev_priv->irq_lock);
4429 }
4430
4431 /**
4432  * intel_irq_install - enables the hardware interrupt
4433  * @dev_priv: i915 device instance
4434  *
4435  * This function enables the hardware interrupt handling, but leaves the hotplug
4436  * handling still disabled. It is called after intel_irq_init().
4437  *
4438  * In the driver load and resume code we need working interrupts in a few places
4439  * but don't want to deal with the hassle of concurrent probe and hotplug
4440  * workers. Hence the split into this two-stage approach.
4441  */
4442 int intel_irq_install(struct drm_i915_private *dev_priv)
4443 {
4444         /*
4445          * We enable some interrupt sources in our postinstall hooks, so mark
4446          * interrupts as enabled _before_ actually enabling them to avoid
4447          * special cases in our ordering checks.
4448          */
4449         dev_priv->pm.irqs_enabled = true;
4450
4451         return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4452 }
4453
4454 /**
4455  * intel_irq_uninstall - finilizes all irq handling
4456  * @dev_priv: i915 device instance
4457  *
4458  * This stops interrupt and hotplug handling and unregisters and frees all
4459  * resources acquired in the init functions.
4460  */
4461 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4462 {
4463         drm_irq_uninstall(dev_priv->dev);
4464         intel_hpd_cancel_work(dev_priv);
4465         dev_priv->pm.irqs_enabled = false;
4466 }
4467
4468 /**
4469  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4470  * @dev_priv: i915 device instance
4471  *
4472  * This function is used to disable interrupts at runtime, both in the runtime
4473  * pm and the system suspend/resume code.
4474  */
4475 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4476 {
4477         dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4478         dev_priv->pm.irqs_enabled = false;
4479         synchronize_irq(dev_priv->dev->irq);
4480 }
4481
4482 /**
4483  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4484  * @dev_priv: i915 device instance
4485  *
4486  * This function is used to enable interrupts at runtime, both in the runtime
4487  * pm and the system suspend/resume code.
4488  */
4489 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4490 {
4491         dev_priv->pm.irqs_enabled = true;
4492         dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4493         dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4494 }