drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 static void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (INTEL_INFO(dev)->gen >= 4)
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low;
 206
 207         if (!i915_pipe_enabled(dev, pipe)) {
 208                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 209                                 "pipe %d\n", pipe);
 210                 return 0;
 211         }
 212
 213         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 214         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 223                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 224                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 225         } while (high1 != high2);
 226
 227         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 228         low >>= PIPE_FRAME_LOW_SHIFT;
 229         return (high1 << 8) | low;
 230 }
 231
 232 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 233 {
 234         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 235         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 236
 237         if (!i915_pipe_enabled(dev, pipe)) {
 238                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 239                                         "pipe %d\n", pipe);
 240                 return 0;
 241         }
 242
 243         return I915_READ(reg);
 244 }
 245
 246 /*
 247  * Handle hotplug events outside the interrupt handler proper.
 248  */
 249 static void i915_hotplug_work_func(struct work_struct *work)
 250 {
 251         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 252                                                     hotplug_work);
 253         struct drm_device *dev = dev_priv->dev;
 254         struct drm_mode_config *mode_config = &dev->mode_config;
 255         struct intel_encoder *encoder;
 256
 257         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 258                 if (encoder->hot_plug)
 259                         encoder->hot_plug(encoder);
 260
 261         /* Just fire off a uevent and let userspace tell us what to do */
 262         drm_helper_hpd_irq_event(dev);
 263 }
 264
 265 static void i915_handle_rps_change(struct drm_device *dev)
 266 {
 267         drm_i915_private_t *dev_priv = dev->dev_private;
 268         u32 busy_up, busy_down, max_avg, min_avg;
 269         u8 new_delay = dev_priv->cur_delay;
 270
 271         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 272         busy_up = I915_READ(RCPREVBSYTUPAVG);
 273         busy_down = I915_READ(RCPREVBSYTDNAVG);
 274         max_avg = I915_READ(RCBMAXAVG);
 275         min_avg = I915_READ(RCBMINAVG);
 276
 277         /* Handle RCS change request from hw */
 278         if (busy_up > max_avg) {
 279                 if (dev_priv->cur_delay != dev_priv->max_delay)
 280                         new_delay = dev_priv->cur_delay - 1;
 281                 if (new_delay < dev_priv->max_delay)
 282                         new_delay = dev_priv->max_delay;
 283         } else if (busy_down < min_avg) {
 284                 if (dev_priv->cur_delay != dev_priv->min_delay)
 285                         new_delay = dev_priv->cur_delay + 1;
 286                 if (new_delay > dev_priv->min_delay)
 287                         new_delay = dev_priv->min_delay;
 288         }
 289
 290         if (ironlake_set_drps(dev, new_delay))
 291                 dev_priv->cur_delay = new_delay;
 292
 293         return;
 294 }
 295
 296 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 297 {
 298         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 299         int ret = IRQ_NONE;
 300         u32 de_iir, gt_iir, de_ier, pch_iir;
 301         struct drm_i915_master_private *master_priv;
 302         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 303
 304         /* disable master interrupt before clearing iir  */
 305         de_ier = I915_READ(DEIER);
 306         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 307         (void)I915_READ(DEIER);
 308
 309         de_iir = I915_READ(DEIIR);
 310         gt_iir = I915_READ(GTIIR);
 311         pch_iir = I915_READ(SDEIIR);
 312
 313         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 314                 goto done;
 315
 316         ret = IRQ_HANDLED;
 317
 318         if (dev->primary->master) {
 319                 master_priv = dev->primary->master->driver_priv;
 320                 if (master_priv->sarea_priv)
 321                         master_priv->sarea_priv->last_dispatch =
 322                                 READ_BREADCRUMB(dev_priv);
 323         }
 324
 325         if (gt_iir & GT_PIPE_NOTIFY) {
 326                 u32 seqno = render_ring->get_gem_seqno(dev, render_ring);
 327                 render_ring->irq_gem_seqno = seqno;
 328                 trace_i915_gem_request_complete(dev, seqno);
 329                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 330                 dev_priv->hangcheck_count = 0;
 331                 mod_timer(&dev_priv->hangcheck_timer,
 332                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 333         }
 334         if (gt_iir & GT_BSD_USER_INTERRUPT)
 335                 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
 336
 337
 338         if (de_iir & DE_GSE)
 339                 intel_opregion_gse_intr(dev);
 340
 341         if (de_iir & DE_PLANEA_FLIP_DONE) {
 342                 intel_prepare_page_flip(dev, 0);
 343                 intel_finish_page_flip_plane(dev, 0);
 344         }
 345
 346         if (de_iir & DE_PLANEB_FLIP_DONE) {
 347                 intel_prepare_page_flip(dev, 1);
 348                 intel_finish_page_flip_plane(dev, 1);
 349         }
 350
 351         if (de_iir & DE_PIPEA_VBLANK)
 352                 drm_handle_vblank(dev, 0);
 353
 354         if (de_iir & DE_PIPEB_VBLANK)
 355                 drm_handle_vblank(dev, 1);
 356
 357         /* check event from PCH */
 358         if ((de_iir & DE_PCH_EVENT) &&
 359             (pch_iir & SDE_HOTPLUG_MASK)) {
 360                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 361         }
 362
 363         if (de_iir & DE_PCU_EVENT) {
 364                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 365                 i915_handle_rps_change(dev);
 366         }
 367
 368         /* should clear PCH hotplug event before clear CPU irq */
 369         I915_WRITE(SDEIIR, pch_iir);
 370         I915_WRITE(GTIIR, gt_iir);
 371         I915_WRITE(DEIIR, de_iir);
 372
 373 done:
 374         I915_WRITE(DEIER, de_ier);
 375         (void)I915_READ(DEIER);
 376
 377         return ret;
 378 }
 379
 380 /**
 381  * i915_error_work_func - do process context error handling work
 382  * @work: work struct
 383  *
 384  * Fire an error uevent so userspace can see that a hang or error
 385  * was detected.
 386  */
 387 static void i915_error_work_func(struct work_struct *work)
 388 {
 389         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 390                                                     error_work);
 391         struct drm_device *dev = dev_priv->dev;
 392         char *error_event[] = { "ERROR=1", NULL };
 393         char *reset_event[] = { "RESET=1", NULL };
 394         char *reset_done_event[] = { "ERROR=0", NULL };
 395
 396         DRM_DEBUG_DRIVER("generating error event\n");
 397         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 398
 399         if (atomic_read(&dev_priv->mm.wedged)) {
 400                 switch (INTEL_INFO(dev)->gen) {
 401                 case 4:
 402                         DRM_DEBUG_DRIVER("resetting chip\n");
 403                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 404                         if (!i965_reset(dev, GRDOM_RENDER)) {
 405                                 atomic_set(&dev_priv->mm.wedged, 0);
 406                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 407                         }
 408                         break;
 409                 default:
 410                         DRM_DEBUG_DRIVER("reboot required\n");
 411                         break;
 412                 }
 413         }
 414 }
 415
 416 #ifdef CONFIG_DEBUG_FS
 417 static struct drm_i915_error_object *
 418 i915_error_object_create(struct drm_device *dev,
 419                          struct drm_gem_object *src)
 420 {
 421         drm_i915_private_t *dev_priv = dev->dev_private;
 422         struct drm_i915_error_object *dst;
 423         struct drm_i915_gem_object *src_priv;
 424         int page, page_count;
 425         u32 reloc_offset;
 426
 427         if (src == NULL)
 428                 return NULL;
 429
 430         src_priv = to_intel_bo(src);
 431         if (src_priv->pages == NULL)
 432                 return NULL;
 433
 434         page_count = src->size / PAGE_SIZE;
 435
 436         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 437         if (dst == NULL)
 438                 return NULL;
 439
 440         reloc_offset = src_priv->gtt_offset;
 441         for (page = 0; page < page_count; page++) {
 442                 unsigned long flags;
 443                 void __iomem *s;
 444                 void *d;
 445
 446                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 447                 if (d == NULL)
 448                         goto unwind;
 449
 450                 local_irq_save(flags);
 451                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 452                                              reloc_offset,
 453                                              KM_IRQ0);
 454                 memcpy_fromio(d, s, PAGE_SIZE);
 455                 io_mapping_unmap_atomic(s, KM_IRQ0);
 456                 local_irq_restore(flags);
 457
 458                 dst->pages[page] = d;
 459
 460                 reloc_offset += PAGE_SIZE;
 461         }
 462         dst->page_count = page_count;
 463         dst->gtt_offset = src_priv->gtt_offset;
 464
 465         return dst;
 466
 467 unwind:
 468         while (page--)
 469                 kfree(dst->pages[page]);
 470         kfree(dst);
 471         return NULL;
 472 }
 473
 474 static void
 475 i915_error_object_free(struct drm_i915_error_object *obj)
 476 {
 477         int page;
 478
 479         if (obj == NULL)
 480                 return;
 481
 482         for (page = 0; page < obj->page_count; page++)
 483                 kfree(obj->pages[page]);
 484
 485         kfree(obj);
 486 }
 487
 488 static void
 489 i915_error_state_free(struct drm_device *dev,
 490                       struct drm_i915_error_state *error)
 491 {
 492         i915_error_object_free(error->batchbuffer[0]);
 493         i915_error_object_free(error->batchbuffer[1]);
 494         i915_error_object_free(error->ringbuffer);
 495         kfree(error->active_bo);
 496         kfree(error->overlay);
 497         kfree(error);
 498 }
 499
 500 static u32
 501 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 502 {
 503         u32 cmd;
 504
 505         if (IS_I830(dev) || IS_845G(dev))
 506                 cmd = MI_BATCH_BUFFER;
 507         else if (INTEL_INFO(dev)->gen >= 4)
 508                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 509                        MI_BATCH_NON_SECURE_I965);
 510         else
 511                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 512
 513         return ring[0] == cmd ? ring[1] : 0;
 514 }
 515
 516 static u32
 517 i915_ringbuffer_last_batch(struct drm_device *dev)
 518 {
 519         struct drm_i915_private *dev_priv = dev->dev_private;
 520         u32 head, bbaddr;
 521         u32 *ring;
 522
 523         /* Locate the current position in the ringbuffer and walk back
 524          * to find the most recently dispatched batch buffer.
 525          */
 526         bbaddr = 0;
 527         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 528         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 529
 530         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 531                 bbaddr = i915_get_bbaddr(dev, ring);
 532                 if (bbaddr)
 533                         break;
 534         }
 535
 536         if (bbaddr == 0) {
 537                 ring = (u32 *)(dev_priv->render_ring.virtual_start
 538                                 + dev_priv->render_ring.size);
 539                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 540                         bbaddr = i915_get_bbaddr(dev, ring);
 541                         if (bbaddr)
 542                                 break;
 543                 }
 544         }
 545
 546         return bbaddr;
 547 }
 548
 549 /**
 550  * i915_capture_error_state - capture an error record for later analysis
 551  * @dev: drm device
 552  *
 553  * Should be called when an error is detected (either a hang or an error
 554  * interrupt) to capture error state from the time of the error.  Fills
 555  * out a structure which becomes available in debugfs for user level tools
 556  * to pick up.
 557  */
 558 static void i915_capture_error_state(struct drm_device *dev)
 559 {
 560         struct drm_i915_private *dev_priv = dev->dev_private;
 561         struct drm_i915_gem_object *obj_priv;
 562         struct drm_i915_error_state *error;
 563         struct drm_gem_object *batchbuffer[2];
 564         unsigned long flags;
 565         u32 bbaddr;
 566         int count;
 567
 568         spin_lock_irqsave(&dev_priv->error_lock, flags);
 569         error = dev_priv->first_error;
 570         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 571         if (error)
 572                 return;
 573
 574         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 575         if (!error) {
 576                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 577                 return;
 578         }
 579
 580         error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring);
 581         error->eir = I915_READ(EIR);
 582         error->pgtbl_er = I915_READ(PGTBL_ER);
 583         error->pipeastat = I915_READ(PIPEASTAT);
 584         error->pipebstat = I915_READ(PIPEBSTAT);
 585         error->instpm = I915_READ(INSTPM);
 586         if (INTEL_INFO(dev)->gen < 4) {
 587                 error->ipeir = I915_READ(IPEIR);
 588                 error->ipehr = I915_READ(IPEHR);
 589                 error->instdone = I915_READ(INSTDONE);
 590                 error->acthd = I915_READ(ACTHD);
 591                 error->bbaddr = 0;
 592         } else {
 593                 error->ipeir = I915_READ(IPEIR_I965);
 594                 error->ipehr = I915_READ(IPEHR_I965);
 595                 error->instdone = I915_READ(INSTDONE_I965);
 596                 error->instps = I915_READ(INSTPS);
 597                 error->instdone1 = I915_READ(INSTDONE1);
 598                 error->acthd = I915_READ(ACTHD_I965);
 599                 error->bbaddr = I915_READ64(BB_ADDR);
 600         }
 601
 602         bbaddr = i915_ringbuffer_last_batch(dev);
 603
 604         /* Grab the current batchbuffer, most likely to have crashed. */
 605         batchbuffer[0] = NULL;
 606         batchbuffer[1] = NULL;
 607         count = 0;
 608         list_for_each_entry(obj_priv,
 609                         &dev_priv->render_ring.active_list, list) {
 610
 611                 struct drm_gem_object *obj = &obj_priv->base;
 612
 613                 if (batchbuffer[0] == NULL &&
 614                     bbaddr >= obj_priv->gtt_offset &&
 615                     bbaddr < obj_priv->gtt_offset + obj->size)
 616                         batchbuffer[0] = obj;
 617
 618                 if (batchbuffer[1] == NULL &&
 619                     error->acthd >= obj_priv->gtt_offset &&
 620                     error->acthd < obj_priv->gtt_offset + obj->size)
 621                         batchbuffer[1] = obj;
 622
 623                 count++;
 624         }
 625         /* Scan the other lists for completeness for those bizarre errors. */
 626         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 627                 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
 628                         struct drm_gem_object *obj = &obj_priv->base;
 629
 630                         if (batchbuffer[0] == NULL &&
 631                             bbaddr >= obj_priv->gtt_offset &&
 632                             bbaddr < obj_priv->gtt_offset + obj->size)
 633                                 batchbuffer[0] = obj;
 634
 635                         if (batchbuffer[1] == NULL &&
 636                             error->acthd >= obj_priv->gtt_offset &&
 637                             error->acthd < obj_priv->gtt_offset + obj->size)
 638                                 batchbuffer[1] = obj;
 639
 640                         if (batchbuffer[0] && batchbuffer[1])
 641                                 break;
 642                 }
 643         }
 644         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 645                 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 646                         struct drm_gem_object *obj = &obj_priv->base;
 647
 648                         if (batchbuffer[0] == NULL &&
 649                             bbaddr >= obj_priv->gtt_offset &&
 650                             bbaddr < obj_priv->gtt_offset + obj->size)
 651                                 batchbuffer[0] = obj;
 652
 653                         if (batchbuffer[1] == NULL &&
 654                             error->acthd >= obj_priv->gtt_offset &&
 655                             error->acthd < obj_priv->gtt_offset + obj->size)
 656                                 batchbuffer[1] = obj;
 657
 658                         if (batchbuffer[0] && batchbuffer[1])
 659                                 break;
 660                 }
 661         }
 662
 663         /* We need to copy these to an anonymous buffer as the simplest
 664          * method to avoid being overwritten by userpace.
 665          */
 666         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 667         if (batchbuffer[1] != batchbuffer[0])
 668                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 669         else
 670                 error->batchbuffer[1] = NULL;
 671
 672         /* Record the ringbuffer */
 673         error->ringbuffer = i915_error_object_create(dev,
 674                         dev_priv->render_ring.gem_object);
 675
 676         /* Record buffers on the active list. */
 677         error->active_bo = NULL;
 678         error->active_bo_count = 0;
 679
 680         if (count)
 681                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 682                                            GFP_ATOMIC);
 683
 684         if (error->active_bo) {
 685                 int i = 0;
 686                 list_for_each_entry(obj_priv,
 687                                 &dev_priv->render_ring.active_list, list) {
 688                         struct drm_gem_object *obj = &obj_priv->base;
 689
 690                         error->active_bo[i].size = obj->size;
 691                         error->active_bo[i].name = obj->name;
 692                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 693                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 694                         error->active_bo[i].read_domains = obj->read_domains;
 695                         error->active_bo[i].write_domain = obj->write_domain;
 696                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 697                         error->active_bo[i].pinned = 0;
 698                         if (obj_priv->pin_count > 0)
 699                                 error->active_bo[i].pinned = 1;
 700                         if (obj_priv->user_pin_count > 0)
 701                                 error->active_bo[i].pinned = -1;
 702                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 703                         error->active_bo[i].dirty = obj_priv->dirty;
 704                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 705
 706                         if (++i == count)
 707                                 break;
 708                 }
 709                 error->active_bo_count = i;
 710         }
 711
 712         do_gettimeofday(&error->time);
 713
 714         error->overlay = intel_overlay_capture_error_state(dev);
 715
 716         spin_lock_irqsave(&dev_priv->error_lock, flags);
 717         if (dev_priv->first_error == NULL) {
 718                 dev_priv->first_error = error;
 719                 error = NULL;
 720         }
 721         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 722
 723         if (error)
 724                 i915_error_state_free(dev, error);
 725 }
 726
 727 void i915_destroy_error_state(struct drm_device *dev)
 728 {
 729         struct drm_i915_private *dev_priv = dev->dev_private;
 730         struct drm_i915_error_state *error;
 731
 732         spin_lock(&dev_priv->error_lock);
 733         error = dev_priv->first_error;
 734         dev_priv->first_error = NULL;
 735         spin_unlock(&dev_priv->error_lock);
 736
 737         if (error)
 738                 i915_error_state_free(dev, error);
 739 }
 740 #else
 741 #define i915_capture_error_state(x)
 742 #endif
 743
 744 static void i915_report_and_clear_eir(struct drm_device *dev)
 745 {
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         u32 eir = I915_READ(EIR);
 748
 749         if (!eir)
 750                 return;
 751
 752         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 753                eir);
 754
 755         if (IS_G4X(dev)) {
 756                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 757                         u32 ipeir = I915_READ(IPEIR_I965);
 758
 759                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 760                                I915_READ(IPEIR_I965));
 761                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 762                                I915_READ(IPEHR_I965));
 763                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 764                                I915_READ(INSTDONE_I965));
 765                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 766                                I915_READ(INSTPS));
 767                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 768                                I915_READ(INSTDONE1));
 769                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 770                                I915_READ(ACTHD_I965));
 771                         I915_WRITE(IPEIR_I965, ipeir);
 772                         (void)I915_READ(IPEIR_I965);
 773                 }
 774                 if (eir & GM45_ERROR_PAGE_TABLE) {
 775                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 776                         printk(KERN_ERR "page table error\n");
 777                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 778                                pgtbl_err);
 779                         I915_WRITE(PGTBL_ER, pgtbl_err);
 780                         (void)I915_READ(PGTBL_ER);
 781                 }
 782         }
 783
 784         if (!IS_GEN2(dev)) {
 785                 if (eir & I915_ERROR_PAGE_TABLE) {
 786                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 787                         printk(KERN_ERR "page table error\n");
 788                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 789                                pgtbl_err);
 790                         I915_WRITE(PGTBL_ER, pgtbl_err);
 791                         (void)I915_READ(PGTBL_ER);
 792                 }
 793         }
 794
 795         if (eir & I915_ERROR_MEMORY_REFRESH) {
 796                 u32 pipea_stats = I915_READ(PIPEASTAT);
 797                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 798
 799                 printk(KERN_ERR "memory refresh error\n");
 800                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 801                        pipea_stats);
 802                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 803                        pipeb_stats);
 804                 /* pipestat has already been acked */
 805         }
 806         if (eir & I915_ERROR_INSTRUCTION) {
 807                 printk(KERN_ERR "instruction error\n");
 808                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 809                        I915_READ(INSTPM));
 810                 if (INTEL_INFO(dev)->gen < 4) {
 811                         u32 ipeir = I915_READ(IPEIR);
 812
 813                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 814                                I915_READ(IPEIR));
 815                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 816                                I915_READ(IPEHR));
 817                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 818                                I915_READ(INSTDONE));
 819                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 820                                I915_READ(ACTHD));
 821                         I915_WRITE(IPEIR, ipeir);
 822                         (void)I915_READ(IPEIR);
 823                 } else {
 824                         u32 ipeir = I915_READ(IPEIR_I965);
 825
 826                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 827                                I915_READ(IPEIR_I965));
 828                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 829                                I915_READ(IPEHR_I965));
 830                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 831                                I915_READ(INSTDONE_I965));
 832                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 833                                I915_READ(INSTPS));
 834                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 835                                I915_READ(INSTDONE1));
 836                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 837                                I915_READ(ACTHD_I965));
 838                         I915_WRITE(IPEIR_I965, ipeir);
 839                         (void)I915_READ(IPEIR_I965);
 840                 }
 841         }
 842
 843         I915_WRITE(EIR, eir);
 844         (void)I915_READ(EIR);
 845         eir = I915_READ(EIR);
 846         if (eir) {
 847                 /*
 848                  * some errors might have become stuck,
 849                  * mask them.
 850                  */
 851                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 852                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 853                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 854         }
 855 }
 856
 857 /**
 858  * i915_handle_error - handle an error interrupt
 859  * @dev: drm device
 860  *
 861  * Do some basic checking of regsiter state at error interrupt time and
 862  * dump it to the syslog.  Also call i915_capture_error_state() to make
 863  * sure we get a record and make it available in debugfs.  Fire a uevent
 864  * so userspace knows something bad happened (should trigger collection
 865  * of a ring dump etc.).
 866  */
 867 static void i915_handle_error(struct drm_device *dev, bool wedged)
 868 {
 869         struct drm_i915_private *dev_priv = dev->dev_private;
 870
 871         i915_capture_error_state(dev);
 872         i915_report_and_clear_eir(dev);
 873
 874         if (wedged) {
 875                 atomic_set(&dev_priv->mm.wedged, 1);
 876
 877                 /*
 878                  * Wakeup waiting processes so they don't hang
 879                  */
 880                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 881         }
 882
 883         queue_work(dev_priv->wq, &dev_priv->error_work);
 884 }
 885
 886 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 887 {
 888         drm_i915_private_t *dev_priv = dev->dev_private;
 889         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 891         struct drm_i915_gem_object *obj_priv;
 892         struct intel_unpin_work *work;
 893         unsigned long flags;
 894         bool stall_detected;
 895
 896         /* Ignore early vblank irqs */
 897         if (intel_crtc == NULL)
 898                 return;
 899
 900         spin_lock_irqsave(&dev->event_lock, flags);
 901         work = intel_crtc->unpin_work;
 902
 903         if (work == NULL || work->pending || !work->enable_stall_check) {
 904                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 905                 spin_unlock_irqrestore(&dev->event_lock, flags);
 906                 return;
 907         }
 908
 909         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 910         obj_priv = to_intel_bo(work->pending_flip_obj);
 911         if (INTEL_INFO(dev)->gen >= 4) {
 912                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
 913                 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
 914         } else {
 915                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
 916                 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
 917                                                         crtc->y * crtc->fb->pitch +
 918                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 919         }
 920
 921         spin_unlock_irqrestore(&dev->event_lock, flags);
 922
 923         if (stall_detected) {
 924                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
 925                 intel_prepare_page_flip(dev, intel_crtc->plane);
 926         }
 927 }
 928
 929 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 930 {
 931         struct drm_device *dev = (struct drm_device *) arg;
 932         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 933         struct drm_i915_master_private *master_priv;
 934         u32 iir, new_iir;
 935         u32 pipea_stats, pipeb_stats;
 936         u32 vblank_status;
 937         int vblank = 0;
 938         unsigned long irqflags;
 939         int irq_received;
 940         int ret = IRQ_NONE;
 941         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 942
 943         atomic_inc(&dev_priv->irq_received);
 944
 945         if (HAS_PCH_SPLIT(dev))
 946                 return ironlake_irq_handler(dev);
 947
 948         iir = I915_READ(IIR);
 949
 950         if (INTEL_INFO(dev)->gen >= 4)
 951                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
 952         else
 953                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 954
 955         for (;;) {
 956                 irq_received = iir != 0;
 957
 958                 /* Can't rely on pipestat interrupt bit in iir as it might
 959                  * have been cleared after the pipestat interrupt was received.
 960                  * It doesn't set the bit in iir again, but it still produces
 961                  * interrupts (for non-MSI).
 962                  */
 963                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 964                 pipea_stats = I915_READ(PIPEASTAT);
 965                 pipeb_stats = I915_READ(PIPEBSTAT);
 966
 967                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 968                         i915_handle_error(dev, false);
 969
 970                 /*
 971                  * Clear the PIPE(A|B)STAT regs before the IIR
 972                  */
 973                 if (pipea_stats & 0x8000ffff) {
 974                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 975                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 976                         I915_WRITE(PIPEASTAT, pipea_stats);
 977                         irq_received = 1;
 978                 }
 979
 980                 if (pipeb_stats & 0x8000ffff) {
 981                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 982                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 983                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 984                         irq_received = 1;
 985                 }
 986                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 987
 988                 if (!irq_received)
 989                         break;
 990
 991                 ret = IRQ_HANDLED;
 992
 993                 /* Consume port.  Then clear IIR or we'll miss events */
 994                 if ((I915_HAS_HOTPLUG(dev)) &&
 995                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 996                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 997
 998                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 999                                   hotplug_status);
1000                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1001                                 queue_work(dev_priv->wq,
1002                                            &dev_priv->hotplug_work);
1003
1004                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1005                         I915_READ(PORT_HOTPLUG_STAT);
1006                 }
1007
1008                 I915_WRITE(IIR, iir);
1009                 new_iir = I915_READ(IIR); /* Flush posted writes */
1010
1011                 if (dev->primary->master) {
1012                         master_priv = dev->primary->master->driver_priv;
1013                         if (master_priv->sarea_priv)
1014                                 master_priv->sarea_priv->last_dispatch =
1015                                         READ_BREADCRUMB(dev_priv);
1016                 }
1017
1018                 if (iir & I915_USER_INTERRUPT) {
1019                         u32 seqno =
1020                                 render_ring->get_gem_seqno(dev, render_ring);
1021                         render_ring->irq_gem_seqno = seqno;
1022                         trace_i915_gem_request_complete(dev, seqno);
1023                         DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1024                         dev_priv->hangcheck_count = 0;
1025                         mod_timer(&dev_priv->hangcheck_timer,
1026                                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1027                 }
1028
1029                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1030                         DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1031
1032                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1033                         intel_prepare_page_flip(dev, 0);
1034                         if (dev_priv->flip_pending_is_done)
1035                                 intel_finish_page_flip_plane(dev, 0);
1036                 }
1037
1038                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1039                         intel_prepare_page_flip(dev, 1);
1040                         if (dev_priv->flip_pending_is_done)
1041                                 intel_finish_page_flip_plane(dev, 1);
1042                 }
1043
1044                 if (pipea_stats & vblank_status) {
1045                         vblank++;
1046                         drm_handle_vblank(dev, 0);
1047                         if (!dev_priv->flip_pending_is_done) {
1048                                 i915_pageflip_stall_check(dev, 0);
1049                                 intel_finish_page_flip(dev, 0);
1050                         }
1051                 }
1052
1053                 if (pipeb_stats & vblank_status) {
1054                         vblank++;
1055                         drm_handle_vblank(dev, 1);
1056                         if (!dev_priv->flip_pending_is_done) {
1057                                 i915_pageflip_stall_check(dev, 1);
1058                                 intel_finish_page_flip(dev, 1);
1059                         }
1060                 }
1061
1062                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1063                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1064                     (iir & I915_ASLE_INTERRUPT))
1065                         intel_opregion_asle_intr(dev);
1066
1067                 /* With MSI, interrupts are only generated when iir
1068                  * transitions from zero to nonzero.  If another bit got
1069                  * set while we were handling the existing iir bits, then
1070                  * we would never get another interrupt.
1071                  *
1072                  * This is fine on non-MSI as well, as if we hit this path
1073                  * we avoid exiting the interrupt handler only to generate
1074                  * another one.
1075                  *
1076                  * Note that for MSI this could cause a stray interrupt report
1077                  * if an interrupt landed in the time between writing IIR and
1078                  * the posting read.  This should be rare enough to never
1079                  * trigger the 99% of 100,000 interrupts test for disabling
1080                  * stray interrupts.
1081                  */
1082                 iir = new_iir;
1083         }
1084
1085         return ret;
1086 }
1087
1088 static int i915_emit_irq(struct drm_device * dev)
1089 {
1090         drm_i915_private_t *dev_priv = dev->dev_private;
1091         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1092
1093         i915_kernel_lost_context(dev);
1094
1095         DRM_DEBUG_DRIVER("\n");
1096
1097         dev_priv->counter++;
1098         if (dev_priv->counter > 0x7FFFFFFFUL)
1099                 dev_priv->counter = 1;
1100         if (master_priv->sarea_priv)
1101                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1102
1103         BEGIN_LP_RING(4);
1104         OUT_RING(MI_STORE_DWORD_INDEX);
1105         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1106         OUT_RING(dev_priv->counter);
1107         OUT_RING(MI_USER_INTERRUPT);
1108         ADVANCE_LP_RING();
1109
1110         return dev_priv->counter;
1111 }
1112
1113 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1114 {
1115         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1116         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1117
1118         if (dev_priv->trace_irq_seqno == 0)
1119                 render_ring->user_irq_get(dev, render_ring);
1120
1121         dev_priv->trace_irq_seqno = seqno;
1122 }
1123
1124 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1125 {
1126         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1127         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1128         int ret = 0;
1129         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1130
1131         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1132                   READ_BREADCRUMB(dev_priv));
1133
1134         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1135                 if (master_priv->sarea_priv)
1136                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1137                 return 0;
1138         }
1139
1140         if (master_priv->sarea_priv)
1141                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1142
1143         render_ring->user_irq_get(dev, render_ring);
1144         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1145                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1146         render_ring->user_irq_put(dev, render_ring);
1147
1148         if (ret == -EBUSY) {
1149                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1150                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1151         }
1152
1153         return ret;
1154 }
1155
1156 /* Needs the lock as it touches the ring.
1157  */
1158 int i915_irq_emit(struct drm_device *dev, void *data,
1159                          struct drm_file *file_priv)
1160 {
1161         drm_i915_private_t *dev_priv = dev->dev_private;
1162         drm_i915_irq_emit_t *emit = data;
1163         int result;
1164
1165         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1166                 DRM_ERROR("called with no initialization\n");
1167                 return -EINVAL;
1168         }
1169
1170         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1171
1172         mutex_lock(&dev->struct_mutex);
1173         result = i915_emit_irq(dev);
1174         mutex_unlock(&dev->struct_mutex);
1175
1176         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1177                 DRM_ERROR("copy_to_user\n");
1178                 return -EFAULT;
1179         }
1180
1181         return 0;
1182 }
1183
1184 /* Doesn't need the hardware lock.
1185  */
1186 int i915_irq_wait(struct drm_device *dev, void *data,
1187                          struct drm_file *file_priv)
1188 {
1189         drm_i915_private_t *dev_priv = dev->dev_private;
1190         drm_i915_irq_wait_t *irqwait = data;
1191
1192         if (!dev_priv) {
1193                 DRM_ERROR("called with no initialization\n");
1194                 return -EINVAL;
1195         }
1196
1197         return i915_wait_irq(dev, irqwait->irq_seq);
1198 }
1199
1200 /* Called from drm generic code, passed 'crtc' which
1201  * we use as a pipe index
1202  */
1203 int i915_enable_vblank(struct drm_device *dev, int pipe)
1204 {
1205         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1206         unsigned long irqflags;
1207
1208         if (!i915_pipe_enabled(dev, pipe))
1209                 return -EINVAL;
1210
1211         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1212         if (HAS_PCH_SPLIT(dev))
1213                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1214                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1215         else if (INTEL_INFO(dev)->gen >= 4)
1216                 i915_enable_pipestat(dev_priv, pipe,
1217                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1218         else
1219                 i915_enable_pipestat(dev_priv, pipe,
1220                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1221         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1222         return 0;
1223 }
1224
1225 /* Called from drm generic code, passed 'crtc' which
1226  * we use as a pipe index
1227  */
1228 void i915_disable_vblank(struct drm_device *dev, int pipe)
1229 {
1230         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1231         unsigned long irqflags;
1232
1233         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1234         if (HAS_PCH_SPLIT(dev))
1235                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1236                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1237         else
1238                 i915_disable_pipestat(dev_priv, pipe,
1239                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1240                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1241         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1242 }
1243
1244 void i915_enable_interrupt (struct drm_device *dev)
1245 {
1246         struct drm_i915_private *dev_priv = dev->dev_private;
1247
1248         if (!HAS_PCH_SPLIT(dev))
1249                 intel_opregion_enable_asle(dev);
1250         dev_priv->irq_enabled = 1;
1251 }
1252
1253
1254 /* Set the vblank monitor pipe
1255  */
1256 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1257                          struct drm_file *file_priv)
1258 {
1259         drm_i915_private_t *dev_priv = dev->dev_private;
1260
1261         if (!dev_priv) {
1262                 DRM_ERROR("called with no initialization\n");
1263                 return -EINVAL;
1264         }
1265
1266         return 0;
1267 }
1268
1269 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1270                          struct drm_file *file_priv)
1271 {
1272         drm_i915_private_t *dev_priv = dev->dev_private;
1273         drm_i915_vblank_pipe_t *pipe = data;
1274
1275         if (!dev_priv) {
1276                 DRM_ERROR("called with no initialization\n");
1277                 return -EINVAL;
1278         }
1279
1280         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1281
1282         return 0;
1283 }
1284
1285 /**
1286  * Schedule buffer swap at given vertical blank.
1287  */
1288 int i915_vblank_swap(struct drm_device *dev, void *data,
1289                      struct drm_file *file_priv)
1290 {
1291         /* The delayed swap mechanism was fundamentally racy, and has been
1292          * removed.  The model was that the client requested a delayed flip/swap
1293          * from the kernel, then waited for vblank before continuing to perform
1294          * rendering.  The problem was that the kernel might wake the client
1295          * up before it dispatched the vblank swap (since the lock has to be
1296          * held while touching the ringbuffer), in which case the client would
1297          * clear and start the next frame before the swap occurred, and
1298          * flicker would occur in addition to likely missing the vblank.
1299          *
1300          * In the absence of this ioctl, userland falls back to a correct path
1301          * of waiting for a vblank, then dispatching the swap on its own.
1302          * Context switching to userland and back is plenty fast enough for
1303          * meeting the requirements of vblank swapping.
1304          */
1305         return -EINVAL;
1306 }
1307
1308 static struct drm_i915_gem_request *
1309 i915_get_tail_request(struct drm_device *dev)
1310 {
1311         drm_i915_private_t *dev_priv = dev->dev_private;
1312         return list_entry(dev_priv->render_ring.request_list.prev,
1313                         struct drm_i915_gem_request, list);
1314 }
1315
1316 /**
1317  * This is called when the chip hasn't reported back with completed
1318  * batchbuffers in a long time. The first time this is called we simply record
1319  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1320  * again, we assume the chip is wedged and try to fix it.
1321  */
1322 void i915_hangcheck_elapsed(unsigned long data)
1323 {
1324         struct drm_device *dev = (struct drm_device *)data;
1325         drm_i915_private_t *dev_priv = dev->dev_private;
1326         uint32_t acthd, instdone, instdone1;
1327
1328         if (INTEL_INFO(dev)->gen < 4) {
1329                 acthd = I915_READ(ACTHD);
1330                 instdone = I915_READ(INSTDONE);
1331                 instdone1 = 0;
1332         } else {
1333                 acthd = I915_READ(ACTHD_I965);
1334                 instdone = I915_READ(INSTDONE_I965);
1335                 instdone1 = I915_READ(INSTDONE1);
1336         }
1337
1338         /* If all work is done then ACTHD clearly hasn't advanced. */
1339         if (list_empty(&dev_priv->render_ring.request_list) ||
1340                 i915_seqno_passed(i915_get_gem_seqno(dev,
1341                                 &dev_priv->render_ring),
1342                         i915_get_tail_request(dev)->seqno)) {
1343                 bool missed_wakeup = false;
1344
1345                 dev_priv->hangcheck_count = 0;
1346
1347                 /* Issue a wake-up to catch stuck h/w. */
1348                 if (dev_priv->render_ring.waiting_gem_seqno &&
1349                     waitqueue_active(&dev_priv->render_ring.irq_queue)) {
1350                         DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1351                         missed_wakeup = true;
1352                 }
1353
1354                 if (dev_priv->bsd_ring.waiting_gem_seqno &&
1355                     waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {
1356                         DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1357                         missed_wakeup = true;
1358                 }
1359
1360                 if (missed_wakeup)
1361                         DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1362                 return;
1363         }
1364
1365         if (dev_priv->last_acthd == acthd &&
1366             dev_priv->last_instdone == instdone &&
1367             dev_priv->last_instdone1 == instdone1) {
1368                 if (dev_priv->hangcheck_count++ > 1) {
1369                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1370
1371                         if (!IS_GEN2(dev)) {
1372                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1373                                  * If so we can simply poke the RB_WAIT bit
1374                                  * and break the hang. This should work on
1375                                  * all but the second generation chipsets.
1376                                  */
1377                                 u32 tmp = I915_READ(PRB0_CTL);
1378                                 if (tmp & RING_WAIT) {
1379                                         I915_WRITE(PRB0_CTL, tmp);
1380                                         POSTING_READ(PRB0_CTL);
1381                                         goto out;
1382                                 }
1383                         }
1384
1385                         i915_handle_error(dev, true);
1386                         return;
1387                 }
1388         } else {
1389                 dev_priv->hangcheck_count = 0;
1390
1391                 dev_priv->last_acthd = acthd;
1392                 dev_priv->last_instdone = instdone;
1393                 dev_priv->last_instdone1 = instdone1;
1394         }
1395
1396 out:
1397         /* Reset timer case chip hangs without another request being added */
1398         mod_timer(&dev_priv->hangcheck_timer,
1399                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1400 }
1401
1402 /* drm_dma.h hooks
1403 */
1404 static void ironlake_irq_preinstall(struct drm_device *dev)
1405 {
1406         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1407
1408         I915_WRITE(HWSTAM, 0xeffe);
1409
1410         /* XXX hotplug from PCH */
1411
1412         I915_WRITE(DEIMR, 0xffffffff);
1413         I915_WRITE(DEIER, 0x0);
1414         (void) I915_READ(DEIER);
1415
1416         /* and GT */
1417         I915_WRITE(GTIMR, 0xffffffff);
1418         I915_WRITE(GTIER, 0x0);
1419         (void) I915_READ(GTIER);
1420
1421         /* south display irq */
1422         I915_WRITE(SDEIMR, 0xffffffff);
1423         I915_WRITE(SDEIER, 0x0);
1424         (void) I915_READ(SDEIER);
1425 }
1426
1427 static int ironlake_irq_postinstall(struct drm_device *dev)
1428 {
1429         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1430         /* enable kind of interrupts always enabled */
1431         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1432                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1433         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1434         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1435                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1436
1437         dev_priv->irq_mask_reg = ~display_mask;
1438         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1439
1440         /* should always can generate irq */
1441         I915_WRITE(DEIIR, I915_READ(DEIIR));
1442         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1443         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1444         (void) I915_READ(DEIER);
1445
1446         /* Gen6 only needs render pipe_control now */
1447         if (IS_GEN6(dev))
1448                 render_mask = GT_PIPE_NOTIFY;
1449
1450         dev_priv->gt_irq_mask_reg = ~render_mask;
1451         dev_priv->gt_irq_enable_reg = render_mask;
1452
1453         I915_WRITE(GTIIR, I915_READ(GTIIR));
1454         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1455         if (IS_GEN6(dev))
1456                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1457         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1458         (void) I915_READ(GTIER);
1459
1460         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1461         dev_priv->pch_irq_enable_reg = hotplug_mask;
1462
1463         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1464         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1465         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1466         (void) I915_READ(SDEIER);
1467
1468         if (IS_IRONLAKE_M(dev)) {
1469                 /* Clear & enable PCU event interrupts */
1470                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1471                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1472                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1473         }
1474
1475         return 0;
1476 }
1477
1478 void i915_driver_irq_preinstall(struct drm_device * dev)
1479 {
1480         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1481
1482         atomic_set(&dev_priv->irq_received, 0);
1483
1484         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1485         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1486
1487         if (HAS_PCH_SPLIT(dev)) {
1488                 ironlake_irq_preinstall(dev);
1489                 return;
1490         }
1491
1492         if (I915_HAS_HOTPLUG(dev)) {
1493                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1494                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1495         }
1496
1497         I915_WRITE(HWSTAM, 0xeffe);
1498         I915_WRITE(PIPEASTAT, 0);
1499         I915_WRITE(PIPEBSTAT, 0);
1500         I915_WRITE(IMR, 0xffffffff);
1501         I915_WRITE(IER, 0x0);
1502         (void) I915_READ(IER);
1503 }
1504
1505 /*
1506  * Must be called after intel_modeset_init or hotplug interrupts won't be
1507  * enabled correctly.
1508  */
1509 int i915_driver_irq_postinstall(struct drm_device *dev)
1510 {
1511         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1512         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1513         u32 error_mask;
1514
1515         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1516
1517         if (HAS_BSD(dev))
1518                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1519
1520         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1521
1522         if (HAS_PCH_SPLIT(dev))
1523                 return ironlake_irq_postinstall(dev);
1524
1525         /* Unmask the interrupts that we always want on. */
1526         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1527
1528         dev_priv->pipestat[0] = 0;
1529         dev_priv->pipestat[1] = 0;
1530
1531         if (I915_HAS_HOTPLUG(dev)) {
1532                 /* Enable in IER... */
1533                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1534                 /* and unmask in IMR */
1535                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1536         }
1537
1538         /*
1539          * Enable some error detection, note the instruction error mask
1540          * bit is reserved, so we leave it masked.
1541          */
1542         if (IS_G4X(dev)) {
1543                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1544                                GM45_ERROR_MEM_PRIV |
1545                                GM45_ERROR_CP_PRIV |
1546                                I915_ERROR_MEMORY_REFRESH);
1547         } else {
1548                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1549                                I915_ERROR_MEMORY_REFRESH);
1550         }
1551         I915_WRITE(EMR, error_mask);
1552
1553         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1554         I915_WRITE(IER, enable_mask);
1555         (void) I915_READ(IER);
1556
1557         if (I915_HAS_HOTPLUG(dev)) {
1558                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1559
1560                 /* Note HDMI and DP share bits */
1561                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1562                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1563                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1564                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1565                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1566                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1567                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1568                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1569                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1570                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1571                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1572                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1573
1574                         /* Programming the CRT detection parameters tends
1575                            to generate a spurious hotplug event about three
1576                            seconds later.  So just do it once.
1577                         */
1578                         if (IS_G4X(dev))
1579                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1580                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1581                 }
1582
1583                 /* Ignore TV since it's buggy */
1584
1585                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1586         }
1587
1588         intel_opregion_enable_asle(dev);
1589
1590         return 0;
1591 }
1592
1593 static void ironlake_irq_uninstall(struct drm_device *dev)
1594 {
1595         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1596         I915_WRITE(HWSTAM, 0xffffffff);
1597
1598         I915_WRITE(DEIMR, 0xffffffff);
1599         I915_WRITE(DEIER, 0x0);
1600         I915_WRITE(DEIIR, I915_READ(DEIIR));
1601
1602         I915_WRITE(GTIMR, 0xffffffff);
1603         I915_WRITE(GTIER, 0x0);
1604         I915_WRITE(GTIIR, I915_READ(GTIIR));
1605 }
1606
1607 void i915_driver_irq_uninstall(struct drm_device * dev)
1608 {
1609         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1610
1611         if (!dev_priv)
1612                 return;
1613
1614         dev_priv->vblank_pipe = 0;
1615
1616         if (HAS_PCH_SPLIT(dev)) {
1617                 ironlake_irq_uninstall(dev);
1618                 return;
1619         }
1620
1621         if (I915_HAS_HOTPLUG(dev)) {
1622                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1623                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1624         }
1625
1626         I915_WRITE(HWSTAM, 0xffffffff);
1627         I915_WRITE(PIPEASTAT, 0);
1628         I915_WRITE(PIPEBSTAT, 0);
1629         I915_WRITE(IMR, 0xffffffff);
1630         I915_WRITE(IER, 0x0);
1631
1632         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1633         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1634         I915_WRITE(IIR, I915_READ(IIR));
1635 }