drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "intel_drv.h"
  38
  39 static const u32 hpd_ibx[] = {
  40         [HPD_CRT] = SDE_CRT_HOTPLUG,
  41         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  42         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  43         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  44         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  45 };
  46
  47 static const u32 hpd_cpt[] = {
  48         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  49         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  50         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  51         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  52         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  53 };
  54
  55 static const u32 hpd_mask_i915[] = {
  56         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  57         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  58         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  59         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  60         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  61         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  62 };
  63
  64 static const u32 hpd_status_gen4[] = {
  65         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  66         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  67         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  69         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  71 };
  72
  73 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  74         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  75         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  76         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  77         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  78         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  80 };
  81
  82 /* For display hotplug interrupt */
  83 static void
  84 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  85 {
  86         assert_spin_locked(&dev_priv->irq_lock);
  87
  88         if ((dev_priv->irq_mask & mask) != 0) {
  89                 dev_priv->irq_mask &= ~mask;
  90                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  91                 POSTING_READ(DEIMR);
  92         }
  93 }
  94
  95 static void
  96 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  97 {
  98         assert_spin_locked(&dev_priv->irq_lock);
  99
 100         if ((dev_priv->irq_mask & mask) != mask) {
 101                 dev_priv->irq_mask |= mask;
 102                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 103                 POSTING_READ(DEIMR);
 104         }
 105 }
 106
 107 /**
 108  * ilk_update_gt_irq - update GTIMR
 109  * @dev_priv: driver private
 110  * @interrupt_mask: mask of interrupt bits to update
 111  * @enabled_irq_mask: mask of interrupt bits to enable
 112  */
 113 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 114                               uint32_t interrupt_mask,
 115                               uint32_t enabled_irq_mask)
 116 {
 117         assert_spin_locked(&dev_priv->irq_lock);
 118
 119         dev_priv->gt_irq_mask &= ~interrupt_mask;
 120         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 121         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 122         POSTING_READ(GTIMR);
 123 }
 124
 125 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 126 {
 127         ilk_update_gt_irq(dev_priv, mask, mask);
 128 }
 129
 130 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 131 {
 132         ilk_update_gt_irq(dev_priv, mask, 0);
 133 }
 134
 135 /**
 136   * snb_update_pm_irq - update GEN6_PMIMR
 137   * @dev_priv: driver private
 138   * @interrupt_mask: mask of interrupt bits to update
 139   * @enabled_irq_mask: mask of interrupt bits to enable
 140   */
 141 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 142                               uint32_t interrupt_mask,
 143                               uint32_t enabled_irq_mask)
 144 {
 145         uint32_t new_val;
 146
 147         assert_spin_locked(&dev_priv->irq_lock);
 148
 149         new_val = dev_priv->pm_irq_mask;
 150         new_val &= ~interrupt_mask;
 151         new_val |= (~enabled_irq_mask & interrupt_mask);
 152
 153         if (new_val != dev_priv->pm_irq_mask) {
 154                 dev_priv->pm_irq_mask = new_val;
 155                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 156                 POSTING_READ(GEN6_PMIMR);
 157         }
 158 }
 159
 160 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 161 {
 162         snb_update_pm_irq(dev_priv, mask, mask);
 163 }
 164
 165 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 166 {
 167         snb_update_pm_irq(dev_priv, mask, 0);
 168 }
 169
 170 static bool ivb_can_enable_err_int(struct drm_device *dev)
 171 {
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct intel_crtc *crtc;
 174         enum pipe pipe;
 175
 176         assert_spin_locked(&dev_priv->irq_lock);
 177
 178         for_each_pipe(pipe) {
 179                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 180
 181                 if (crtc->cpu_fifo_underrun_disabled)
 182                         return false;
 183         }
 184
 185         return true;
 186 }
 187
 188 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 189 {
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         enum pipe pipe;
 192         struct intel_crtc *crtc;
 193
 194         assert_spin_locked(&dev_priv->irq_lock);
 195
 196         for_each_pipe(pipe) {
 197                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 198
 199                 if (crtc->pch_fifo_underrun_disabled)
 200                         return false;
 201         }
 202
 203         return true;
 204 }
 205
 206 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 207                                                  enum pipe pipe, bool enable)
 208 {
 209         struct drm_i915_private *dev_priv = dev->dev_private;
 210         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 211                                           DE_PIPEB_FIFO_UNDERRUN;
 212
 213         if (enable)
 214                 ironlake_enable_display_irq(dev_priv, bit);
 215         else
 216                 ironlake_disable_display_irq(dev_priv, bit);
 217 }
 218
 219 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 220                                                   enum pipe pipe, bool enable)
 221 {
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         if (enable) {
 224                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 225
 226                 if (!ivb_can_enable_err_int(dev))
 227                         return;
 228
 229                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 230         } else {
 231                 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
 232
 233                 /* Change the state _after_ we've read out the current one. */
 234                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 235
 236                 if (!was_enabled &&
 237                     (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
 238                         DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
 239                                       pipe_name(pipe));
 240                 }
 241         }
 242 }
 243
 244 /**
 245  * ibx_display_interrupt_update - update SDEIMR
 246  * @dev_priv: driver private
 247  * @interrupt_mask: mask of interrupt bits to update
 248  * @enabled_irq_mask: mask of interrupt bits to enable
 249  */
 250 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 251                                          uint32_t interrupt_mask,
 252                                          uint32_t enabled_irq_mask)
 253 {
 254         uint32_t sdeimr = I915_READ(SDEIMR);
 255         sdeimr &= ~interrupt_mask;
 256         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 257
 258         assert_spin_locked(&dev_priv->irq_lock);
 259
 260         I915_WRITE(SDEIMR, sdeimr);
 261         POSTING_READ(SDEIMR);
 262 }
 263 #define ibx_enable_display_interrupt(dev_priv, bits) \
 264         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 265 #define ibx_disable_display_interrupt(dev_priv, bits) \
 266         ibx_display_interrupt_update((dev_priv), (bits), 0)
 267
 268 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 269                                             enum transcoder pch_transcoder,
 270                                             bool enable)
 271 {
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 274                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 275
 276         if (enable)
 277                 ibx_enable_display_interrupt(dev_priv, bit);
 278         else
 279                 ibx_disable_display_interrupt(dev_priv, bit);
 280 }
 281
 282 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 283                                             enum transcoder pch_transcoder,
 284                                             bool enable)
 285 {
 286         struct drm_i915_private *dev_priv = dev->dev_private;
 287
 288         if (enable) {
 289                 I915_WRITE(SERR_INT,
 290                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 291
 292                 if (!cpt_can_enable_serr_int(dev))
 293                         return;
 294
 295                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 296         } else {
 297                 uint32_t tmp = I915_READ(SERR_INT);
 298                 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
 299
 300                 /* Change the state _after_ we've read out the current one. */
 301                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 302
 303                 if (!was_enabled &&
 304                     (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
 305                         DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
 306                                       transcoder_name(pch_transcoder));
 307                 }
 308         }
 309 }
 310
 311 /**
 312  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 313  * @dev: drm device
 314  * @pipe: pipe
 315  * @enable: true if we want to report FIFO underrun errors, false otherwise
 316  *
 317  * This function makes us disable or enable CPU fifo underruns for a specific
 318  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 319  * reporting for one pipe may also disable all the other CPU error interruts for
 320  * the other pipes, due to the fact that there's just one interrupt mask/enable
 321  * bit for all the pipes.
 322  *
 323  * Returns the previous state of underrun reporting.
 324  */
 325 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 326                                            enum pipe pipe, bool enable)
 327 {
 328         struct drm_i915_private *dev_priv = dev->dev_private;
 329         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 331         unsigned long flags;
 332         bool ret;
 333
 334         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 335
 336         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 337
 338         if (enable == ret)
 339                 goto done;
 340
 341         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 342
 343         if (IS_GEN5(dev) || IS_GEN6(dev))
 344                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 345         else if (IS_GEN7(dev))
 346                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
 347
 348 done:
 349         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 350         return ret;
 351 }
 352
 353 /**
 354  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 355  * @dev: drm device
 356  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 357  * @enable: true if we want to report FIFO underrun errors, false otherwise
 358  *
 359  * This function makes us disable or enable PCH fifo underruns for a specific
 360  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 361  * underrun reporting for one transcoder may also disable all the other PCH
 362  * error interruts for the other transcoders, due to the fact that there's just
 363  * one interrupt mask/enable bit for all the transcoders.
 364  *
 365  * Returns the previous state of underrun reporting.
 366  */
 367 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 368                                            enum transcoder pch_transcoder,
 369                                            bool enable)
 370 {
 371         struct drm_i915_private *dev_priv = dev->dev_private;
 372         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 374         unsigned long flags;
 375         bool ret;
 376
 377         /*
 378          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 379          * has only one pch transcoder A that all pipes can use. To avoid racy
 380          * pch transcoder -> pipe lookups from interrupt code simply store the
 381          * underrun statistics in crtc A. Since we never expose this anywhere
 382          * nor use it outside of the fifo underrun code here using the "wrong"
 383          * crtc on LPT won't cause issues.
 384          */
 385
 386         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 387
 388         ret = !intel_crtc->pch_fifo_underrun_disabled;
 389
 390         if (enable == ret)
 391                 goto done;
 392
 393         intel_crtc->pch_fifo_underrun_disabled = !enable;
 394
 395         if (HAS_PCH_IBX(dev))
 396                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 397         else
 398                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 399
 400 done:
 401         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 402         return ret;
 403 }
 404
 405
 406 void
 407 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 408 {
 409         u32 reg = PIPESTAT(pipe);
 410         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 411
 412         assert_spin_locked(&dev_priv->irq_lock);
 413
 414         if ((pipestat & mask) == mask)
 415                 return;
 416
 417         /* Enable the interrupt, clear any pending status */
 418         pipestat |= mask | (mask >> 16);
 419         I915_WRITE(reg, pipestat);
 420         POSTING_READ(reg);
 421 }
 422
 423 void
 424 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 425 {
 426         u32 reg = PIPESTAT(pipe);
 427         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 428
 429         assert_spin_locked(&dev_priv->irq_lock);
 430
 431         if ((pipestat & mask) == 0)
 432                 return;
 433
 434         pipestat &= ~mask;
 435         I915_WRITE(reg, pipestat);
 436         POSTING_READ(reg);
 437 }
 438
 439 /**
 440  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 441  */
 442 static void i915_enable_asle_pipestat(struct drm_device *dev)
 443 {
 444         drm_i915_private_t *dev_priv = dev->dev_private;
 445         unsigned long irqflags;
 446
 447         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 448                 return;
 449
 450         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 451
 452         i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
 453         if (INTEL_INFO(dev)->gen >= 4)
 454                 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
 455
 456         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 457 }
 458
 459 /**
 460  * i915_pipe_enabled - check if a pipe is enabled
 461  * @dev: DRM device
 462  * @pipe: pipe to check
 463  *
 464  * Reading certain registers when the pipe is disabled can hang the chip.
 465  * Use this routine to make sure the PLL is running and the pipe is active
 466  * before reading such registers if unsure.
 467  */
 468 static int
 469 i915_pipe_enabled(struct drm_device *dev, int pipe)
 470 {
 471         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 472
 473         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 474                 /* Locking is horribly broken here, but whatever. */
 475                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 476                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 477
 478                 return intel_crtc->active;
 479         } else {
 480                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 481         }
 482 }
 483
 484 /* Called from drm generic code, passed a 'crtc', which
 485  * we use as a pipe index
 486  */
 487 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 488 {
 489         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 490         unsigned long high_frame;
 491         unsigned long low_frame;
 492         u32 high1, high2, low;
 493
 494         if (!i915_pipe_enabled(dev, pipe)) {
 495                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 496                                 "pipe %c\n", pipe_name(pipe));
 497                 return 0;
 498         }
 499
 500         high_frame = PIPEFRAME(pipe);
 501         low_frame = PIPEFRAMEPIXEL(pipe);
 502
 503         /*
 504          * High & low register fields aren't synchronized, so make sure
 505          * we get a low value that's stable across two reads of the high
 506          * register.
 507          */
 508         do {
 509                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 510                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 511                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 512         } while (high1 != high2);
 513
 514         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 515         low >>= PIPE_FRAME_LOW_SHIFT;
 516         return (high1 << 8) | low;
 517 }
 518
 519 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 520 {
 521         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 522         int reg = PIPE_FRMCOUNT_GM45(pipe);
 523
 524         if (!i915_pipe_enabled(dev, pipe)) {
 525                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 526                                  "pipe %c\n", pipe_name(pipe));
 527                 return 0;
 528         }
 529
 530         return I915_READ(reg);
 531 }
 532
 533 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 534                              int *vpos, int *hpos)
 535 {
 536         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 537         u32 vbl = 0, position = 0;
 538         int vbl_start, vbl_end, htotal, vtotal;
 539         bool in_vbl = true;
 540         int ret = 0;
 541         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 542                                                                       pipe);
 543
 544         if (!i915_pipe_enabled(dev, pipe)) {
 545                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 546                                  "pipe %c\n", pipe_name(pipe));
 547                 return 0;
 548         }
 549
 550         /* Get vtotal. */
 551         vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 552
 553         if (INTEL_INFO(dev)->gen >= 4) {
 554                 /* No obvious pixelcount register. Only query vertical
 555                  * scanout position from Display scan line register.
 556                  */
 557                 position = I915_READ(PIPEDSL(pipe));
 558
 559                 /* Decode into vertical scanout position. Don't have
 560                  * horizontal scanout position.
 561                  */
 562                 *vpos = position & 0x1fff;
 563                 *hpos = 0;
 564         } else {
 565                 /* Have access to pixelcount since start of frame.
 566                  * We can split this into vertical and horizontal
 567                  * scanout position.
 568                  */
 569                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 570
 571                 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 572                 *vpos = position / htotal;
 573                 *hpos = position - (*vpos * htotal);
 574         }
 575
 576         /* Query vblank area. */
 577         vbl = I915_READ(VBLANK(cpu_transcoder));
 578
 579         /* Test position against vblank region. */
 580         vbl_start = vbl & 0x1fff;
 581         vbl_end = (vbl >> 16) & 0x1fff;
 582
 583         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 584                 in_vbl = false;
 585
 586         /* Inside "upper part" of vblank area? Apply corrective offset: */
 587         if (in_vbl && (*vpos >= vbl_start))
 588                 *vpos = *vpos - vtotal;
 589
 590         /* Readouts valid? */
 591         if (vbl > 0)
 592                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 593
 594         /* In vblank? */
 595         if (in_vbl)
 596                 ret |= DRM_SCANOUTPOS_INVBL;
 597
 598         return ret;
 599 }
 600
 601 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 602                               int *max_error,
 603                               struct timeval *vblank_time,
 604                               unsigned flags)
 605 {
 606         struct drm_crtc *crtc;
 607
 608         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 609                 DRM_ERROR("Invalid crtc %d\n", pipe);
 610                 return -EINVAL;
 611         }
 612
 613         /* Get drm_crtc to timestamp: */
 614         crtc = intel_get_crtc_for_pipe(dev, pipe);
 615         if (crtc == NULL) {
 616                 DRM_ERROR("Invalid crtc %d\n", pipe);
 617                 return -EINVAL;
 618         }
 619
 620         if (!crtc->enabled) {
 621                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 622                 return -EBUSY;
 623         }
 624
 625         /* Helper routine in DRM core does all the work: */
 626         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 627                                                      vblank_time, flags,
 628                                                      crtc);
 629 }
 630
 631 static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
 632 {
 633         enum drm_connector_status old_status;
 634
 635         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 636         old_status = connector->status;
 637
 638         connector->status = connector->funcs->detect(connector, false);
 639         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
 640                       connector->base.id,
 641                       drm_get_connector_name(connector),
 642                       old_status, connector->status);
 643         return (old_status != connector->status);
 644 }
 645
 646 /*
 647  * Handle hotplug events outside the interrupt handler proper.
 648  */
 649 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 650
 651 static void i915_hotplug_work_func(struct work_struct *work)
 652 {
 653         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 654                                                     hotplug_work);
 655         struct drm_device *dev = dev_priv->dev;
 656         struct drm_mode_config *mode_config = &dev->mode_config;
 657         struct intel_connector *intel_connector;
 658         struct intel_encoder *intel_encoder;
 659         struct drm_connector *connector;
 660         unsigned long irqflags;
 661         bool hpd_disabled = false;
 662         bool changed = false;
 663         u32 hpd_event_bits;
 664
 665         /* HPD irq before everything is fully set up. */
 666         if (!dev_priv->enable_hotplug_processing)
 667                 return;
 668
 669         mutex_lock(&mode_config->mutex);
 670         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 671
 672         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 673
 674         hpd_event_bits = dev_priv->hpd_event_bits;
 675         dev_priv->hpd_event_bits = 0;
 676         list_for_each_entry(connector, &mode_config->connector_list, head) {
 677                 intel_connector = to_intel_connector(connector);
 678                 intel_encoder = intel_connector->encoder;
 679                 if (intel_encoder->hpd_pin > HPD_NONE &&
 680                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 681                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 682                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 683                                  "switching from hotplug detection to polling\n",
 684                                 drm_get_connector_name(connector));
 685                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 686                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 687                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 688                         hpd_disabled = true;
 689                 }
 690                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 691                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 692                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
 693                 }
 694         }
 695          /* if there were no outputs to poll, poll was disabled,
 696           * therefore make sure it's enabled when disabling HPD on
 697           * some connectors */
 698         if (hpd_disabled) {
 699                 drm_kms_helper_poll_enable(dev);
 700                 mod_timer(&dev_priv->hotplug_reenable_timer,
 701                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 702         }
 703
 704         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 705
 706         list_for_each_entry(connector, &mode_config->connector_list, head) {
 707                 intel_connector = to_intel_connector(connector);
 708                 intel_encoder = intel_connector->encoder;
 709                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 710                         if (intel_encoder->hot_plug)
 711                                 intel_encoder->hot_plug(intel_encoder);
 712                         if (intel_hpd_irq_event(dev, connector))
 713                                 changed = true;
 714                 }
 715         }
 716         mutex_unlock(&mode_config->mutex);
 717
 718         if (changed)
 719                 drm_kms_helper_hotplug_event(dev);
 720 }
 721
 722 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 723 {
 724         drm_i915_private_t *dev_priv = dev->dev_private;
 725         u32 busy_up, busy_down, max_avg, min_avg;
 726         u8 new_delay;
 727
 728         spin_lock(&mchdev_lock);
 729
 730         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 731
 732         new_delay = dev_priv->ips.cur_delay;
 733
 734         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 735         busy_up = I915_READ(RCPREVBSYTUPAVG);
 736         busy_down = I915_READ(RCPREVBSYTDNAVG);
 737         max_avg = I915_READ(RCBMAXAVG);
 738         min_avg = I915_READ(RCBMINAVG);
 739
 740         /* Handle RCS change request from hw */
 741         if (busy_up > max_avg) {
 742                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 743                         new_delay = dev_priv->ips.cur_delay - 1;
 744                 if (new_delay < dev_priv->ips.max_delay)
 745                         new_delay = dev_priv->ips.max_delay;
 746         } else if (busy_down < min_avg) {
 747                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 748                         new_delay = dev_priv->ips.cur_delay + 1;
 749                 if (new_delay > dev_priv->ips.min_delay)
 750                         new_delay = dev_priv->ips.min_delay;
 751         }
 752
 753         if (ironlake_set_drps(dev, new_delay))
 754                 dev_priv->ips.cur_delay = new_delay;
 755
 756         spin_unlock(&mchdev_lock);
 757
 758         return;
 759 }
 760
 761 static void notify_ring(struct drm_device *dev,
 762                         struct intel_ring_buffer *ring)
 763 {
 764         if (ring->obj == NULL)
 765                 return;
 766
 767         trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 768
 769         wake_up_all(&ring->irq_queue);
 770         i915_queue_hangcheck(dev);
 771 }
 772
 773 static void gen6_pm_rps_work(struct work_struct *work)
 774 {
 775         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 776                                                     rps.work);
 777         u32 pm_iir;
 778         u8 new_delay;
 779
 780         spin_lock_irq(&dev_priv->irq_lock);
 781         pm_iir = dev_priv->rps.pm_iir;
 782         dev_priv->rps.pm_iir = 0;
 783         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
 784         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
 785         spin_unlock_irq(&dev_priv->irq_lock);
 786
 787         /* Make sure we didn't queue anything we're not going to process. */
 788         WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
 789
 790         if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
 791                 return;
 792
 793         mutex_lock(&dev_priv->rps.hw_lock);
 794
 795         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 796                 new_delay = dev_priv->rps.cur_delay + 1;
 797
 798                 /*
 799                  * For better performance, jump directly
 800                  * to RPe if we're below it.
 801                  */
 802                 if (IS_VALLEYVIEW(dev_priv->dev) &&
 803                     dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
 804                         new_delay = dev_priv->rps.rpe_delay;
 805         } else
 806                 new_delay = dev_priv->rps.cur_delay - 1;
 807
 808         /* sysfs frequency interfaces may have snuck in while servicing the
 809          * interrupt
 810          */
 811         if (new_delay >= dev_priv->rps.min_delay &&
 812             new_delay <= dev_priv->rps.max_delay) {
 813                 if (IS_VALLEYVIEW(dev_priv->dev))
 814                         valleyview_set_rps(dev_priv->dev, new_delay);
 815                 else
 816                         gen6_set_rps(dev_priv->dev, new_delay);
 817         }
 818
 819         if (IS_VALLEYVIEW(dev_priv->dev)) {
 820                 /*
 821                  * On VLV, when we enter RC6 we may not be at the minimum
 822                  * voltage level, so arm a timer to check.  It should only
 823                  * fire when there's activity or once after we've entered
 824                  * RC6, and then won't be re-armed until the next RPS interrupt.
 825                  */
 826                 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
 827                                  msecs_to_jiffies(100));
 828         }
 829
 830         mutex_unlock(&dev_priv->rps.hw_lock);
 831 }
 832
 833
 834 /**
 835  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 836  * occurred.
 837  * @work: workqueue struct
 838  *
 839  * Doesn't actually do anything except notify userspace. As a consequence of
 840  * this event, userspace should try to remap the bad rows since statistically
 841  * it is likely the same row is more likely to go bad again.
 842  */
 843 static void ivybridge_parity_work(struct work_struct *work)
 844 {
 845         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 846                                                     l3_parity.error_work);
 847         u32 error_status, row, bank, subbank;
 848         char *parity_event[5];
 849         uint32_t misccpctl;
 850         unsigned long flags;
 851
 852         /* We must turn off DOP level clock gating to access the L3 registers.
 853          * In order to prevent a get/put style interface, acquire struct mutex
 854          * any time we access those registers.
 855          */
 856         mutex_lock(&dev_priv->dev->struct_mutex);
 857
 858         misccpctl = I915_READ(GEN7_MISCCPCTL);
 859         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 860         POSTING_READ(GEN7_MISCCPCTL);
 861
 862         error_status = I915_READ(GEN7_L3CDERRST1);
 863         row = GEN7_PARITY_ERROR_ROW(error_status);
 864         bank = GEN7_PARITY_ERROR_BANK(error_status);
 865         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 866
 867         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 868                                     GEN7_L3CDERRST1_ENABLE);
 869         POSTING_READ(GEN7_L3CDERRST1);
 870
 871         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 872
 873         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 874         ilk_enable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
 875         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 876
 877         mutex_unlock(&dev_priv->dev->struct_mutex);
 878
 879         parity_event[0] = I915_L3_PARITY_UEVENT "=1";
 880         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 881         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 882         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 883         parity_event[4] = NULL;
 884
 885         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 886                            KOBJ_CHANGE, parity_event);
 887
 888         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 889                   row, bank, subbank);
 890
 891         kfree(parity_event[3]);
 892         kfree(parity_event[2]);
 893         kfree(parity_event[1]);
 894 }
 895
 896 static void ivybridge_parity_error_irq_handler(struct drm_device *dev)
 897 {
 898         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 899
 900         if (!HAS_L3_GPU_CACHE(dev))
 901                 return;
 902
 903         spin_lock(&dev_priv->irq_lock);
 904         ilk_disable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
 905         spin_unlock(&dev_priv->irq_lock);
 906
 907         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 908 }
 909
 910 static void ilk_gt_irq_handler(struct drm_device *dev,
 911                                struct drm_i915_private *dev_priv,
 912                                u32 gt_iir)
 913 {
 914         if (gt_iir &
 915             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
 916                 notify_ring(dev, &dev_priv->ring[RCS]);
 917         if (gt_iir & ILK_BSD_USER_INTERRUPT)
 918                 notify_ring(dev, &dev_priv->ring[VCS]);
 919 }
 920
 921 static void snb_gt_irq_handler(struct drm_device *dev,
 922                                struct drm_i915_private *dev_priv,
 923                                u32 gt_iir)
 924 {
 925
 926         if (gt_iir &
 927             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
 928                 notify_ring(dev, &dev_priv->ring[RCS]);
 929         if (gt_iir & GT_BSD_USER_INTERRUPT)
 930                 notify_ring(dev, &dev_priv->ring[VCS]);
 931         if (gt_iir & GT_BLT_USER_INTERRUPT)
 932                 notify_ring(dev, &dev_priv->ring[BCS]);
 933
 934         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
 935                       GT_BSD_CS_ERROR_INTERRUPT |
 936                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
 937                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 938                 i915_handle_error(dev, false);
 939         }
 940
 941         if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
 942                 ivybridge_parity_error_irq_handler(dev);
 943 }
 944
 945 #define HPD_STORM_DETECT_PERIOD 1000
 946 #define HPD_STORM_THRESHOLD 5
 947
 948 static inline void intel_hpd_irq_handler(struct drm_device *dev,
 949                                          u32 hotplug_trigger,
 950                                          const u32 *hpd)
 951 {
 952         drm_i915_private_t *dev_priv = dev->dev_private;
 953         int i;
 954         bool storm_detected = false;
 955
 956         if (!hotplug_trigger)
 957                 return;
 958
 959         spin_lock(&dev_priv->irq_lock);
 960         for (i = 1; i < HPD_NUM_PINS; i++) {
 961
 962                 WARN(((hpd[i] & hotplug_trigger) &&
 963                       dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
 964                      "Received HPD interrupt although disabled\n");
 965
 966                 if (!(hpd[i] & hotplug_trigger) ||
 967                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
 968                         continue;
 969
 970                 dev_priv->hpd_event_bits |= (1 << i);
 971                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
 972                                    dev_priv->hpd_stats[i].hpd_last_jiffies
 973                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
 974                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
 975                         dev_priv->hpd_stats[i].hpd_cnt = 0;
 976                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
 977                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
 978                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
 979                         dev_priv->hpd_event_bits &= ~(1 << i);
 980                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
 981                         storm_detected = true;
 982                 } else {
 983                         dev_priv->hpd_stats[i].hpd_cnt++;
 984                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
 985                                       dev_priv->hpd_stats[i].hpd_cnt);
 986                 }
 987         }
 988
 989         if (storm_detected)
 990                 dev_priv->display.hpd_irq_setup(dev);
 991         spin_unlock(&dev_priv->irq_lock);
 992
 993         queue_work(dev_priv->wq,
 994                    &dev_priv->hotplug_work);
 995 }
 996
 997 static void gmbus_irq_handler(struct drm_device *dev)
 998 {
 999         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1000
1001         wake_up_all(&dev_priv->gmbus_wait_queue);
1002 }
1003
1004 static void dp_aux_irq_handler(struct drm_device *dev)
1005 {
1006         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1007
1008         wake_up_all(&dev_priv->gmbus_wait_queue);
1009 }
1010
1011 /* The RPS events need forcewake, so we add them to a work queue and mask their
1012  * IMR bits until the work is done. Other interrupts can be processed without
1013  * the work queue. */
1014 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1015 {
1016         if (pm_iir & GEN6_PM_RPS_EVENTS) {
1017                 spin_lock(&dev_priv->irq_lock);
1018                 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1019                 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1020                 spin_unlock(&dev_priv->irq_lock);
1021
1022                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1023         }
1024
1025         if (HAS_VEBOX(dev_priv->dev)) {
1026                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1027                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1028
1029                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1030                         DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1031                         i915_handle_error(dev_priv->dev, false);
1032                 }
1033         }
1034 }
1035
1036 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1037 {
1038         struct drm_device *dev = (struct drm_device *) arg;
1039         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1040         u32 iir, gt_iir, pm_iir;
1041         irqreturn_t ret = IRQ_NONE;
1042         unsigned long irqflags;
1043         int pipe;
1044         u32 pipe_stats[I915_MAX_PIPES];
1045
1046         atomic_inc(&dev_priv->irq_received);
1047
1048         while (true) {
1049                 iir = I915_READ(VLV_IIR);
1050                 gt_iir = I915_READ(GTIIR);
1051                 pm_iir = I915_READ(GEN6_PMIIR);
1052
1053                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1054                         goto out;
1055
1056                 ret = IRQ_HANDLED;
1057
1058                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1059
1060                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1061                 for_each_pipe(pipe) {
1062                         int reg = PIPESTAT(pipe);
1063                         pipe_stats[pipe] = I915_READ(reg);
1064
1065                         /*
1066                          * Clear the PIPE*STAT regs before the IIR
1067                          */
1068                         if (pipe_stats[pipe] & 0x8000ffff) {
1069                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1070                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1071                                                          pipe_name(pipe));
1072                                 I915_WRITE(reg, pipe_stats[pipe]);
1073                         }
1074                 }
1075                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1076
1077                 for_each_pipe(pipe) {
1078                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1079                                 drm_handle_vblank(dev, pipe);
1080
1081                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1082                                 intel_prepare_page_flip(dev, pipe);
1083                                 intel_finish_page_flip(dev, pipe);
1084                         }
1085                 }
1086
1087                 /* Consume port.  Then clear IIR or we'll miss events */
1088                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1089                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1090                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1091
1092                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1093                                          hotplug_status);
1094
1095                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1096
1097                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1098                         I915_READ(PORT_HOTPLUG_STAT);
1099                 }
1100
1101                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1102                         gmbus_irq_handler(dev);
1103
1104                 if (pm_iir)
1105                         gen6_rps_irq_handler(dev_priv, pm_iir);
1106
1107                 I915_WRITE(GTIIR, gt_iir);
1108                 I915_WRITE(GEN6_PMIIR, pm_iir);
1109                 I915_WRITE(VLV_IIR, iir);
1110         }
1111
1112 out:
1113         return ret;
1114 }
1115
1116 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1117 {
1118         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1119         int pipe;
1120         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1121
1122         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1123
1124         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1125                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1126                                SDE_AUDIO_POWER_SHIFT);
1127                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1128                                  port_name(port));
1129         }
1130
1131         if (pch_iir & SDE_AUX_MASK)
1132                 dp_aux_irq_handler(dev);
1133
1134         if (pch_iir & SDE_GMBUS)
1135                 gmbus_irq_handler(dev);
1136
1137         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1138                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1139
1140         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1141                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1142
1143         if (pch_iir & SDE_POISON)
1144                 DRM_ERROR("PCH poison interrupt\n");
1145
1146         if (pch_iir & SDE_FDI_MASK)
1147                 for_each_pipe(pipe)
1148                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1149                                          pipe_name(pipe),
1150                                          I915_READ(FDI_RX_IIR(pipe)));
1151
1152         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1153                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1154
1155         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1156                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1157
1158         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1159                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1160                                                           false))
1161                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1162
1163         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1164                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1165                                                           false))
1166                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1167 }
1168
1169 static void ivb_err_int_handler(struct drm_device *dev)
1170 {
1171         struct drm_i915_private *dev_priv = dev->dev_private;
1172         u32 err_int = I915_READ(GEN7_ERR_INT);
1173
1174         if (err_int & ERR_INT_POISON)
1175                 DRM_ERROR("Poison interrupt\n");
1176
1177         if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1178                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1179                         DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1180
1181         if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1182                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1183                         DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1184
1185         if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1186                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1187                         DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1188
1189         I915_WRITE(GEN7_ERR_INT, err_int);
1190 }
1191
1192 static void cpt_serr_int_handler(struct drm_device *dev)
1193 {
1194         struct drm_i915_private *dev_priv = dev->dev_private;
1195         u32 serr_int = I915_READ(SERR_INT);
1196
1197         if (serr_int & SERR_INT_POISON)
1198                 DRM_ERROR("PCH poison interrupt\n");
1199
1200         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1201                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1202                                                           false))
1203                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1204
1205         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1206                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1207                                                           false))
1208                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1209
1210         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1211                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1212                                                           false))
1213                         DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1214
1215         I915_WRITE(SERR_INT, serr_int);
1216 }
1217
1218 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1219 {
1220         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1221         int pipe;
1222         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1223
1224         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1225
1226         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1227                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1228                                SDE_AUDIO_POWER_SHIFT_CPT);
1229                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1230                                  port_name(port));
1231         }
1232
1233         if (pch_iir & SDE_AUX_MASK_CPT)
1234                 dp_aux_irq_handler(dev);
1235
1236         if (pch_iir & SDE_GMBUS_CPT)
1237                 gmbus_irq_handler(dev);
1238
1239         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1240                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1241
1242         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1243                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1244
1245         if (pch_iir & SDE_FDI_MASK_CPT)
1246                 for_each_pipe(pipe)
1247                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1248                                          pipe_name(pipe),
1249                                          I915_READ(FDI_RX_IIR(pipe)));
1250
1251         if (pch_iir & SDE_ERROR_CPT)
1252                 cpt_serr_int_handler(dev);
1253 }
1254
1255 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1256 {
1257         struct drm_i915_private *dev_priv = dev->dev_private;
1258
1259         if (de_iir & DE_AUX_CHANNEL_A)
1260                 dp_aux_irq_handler(dev);
1261
1262         if (de_iir & DE_GSE)
1263                 intel_opregion_asle_intr(dev);
1264
1265         if (de_iir & DE_PIPEA_VBLANK)
1266                 drm_handle_vblank(dev, 0);
1267
1268         if (de_iir & DE_PIPEB_VBLANK)
1269                 drm_handle_vblank(dev, 1);
1270
1271         if (de_iir & DE_POISON)
1272                 DRM_ERROR("Poison interrupt\n");
1273
1274         if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1275                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1276                         DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1277
1278         if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1279                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1280                         DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1281
1282         if (de_iir & DE_PLANEA_FLIP_DONE) {
1283                 intel_prepare_page_flip(dev, 0);
1284                 intel_finish_page_flip_plane(dev, 0);
1285         }
1286
1287         if (de_iir & DE_PLANEB_FLIP_DONE) {
1288                 intel_prepare_page_flip(dev, 1);
1289                 intel_finish_page_flip_plane(dev, 1);
1290         }
1291
1292         /* check event from PCH */
1293         if (de_iir & DE_PCH_EVENT) {
1294                 u32 pch_iir = I915_READ(SDEIIR);
1295
1296                 if (HAS_PCH_CPT(dev))
1297                         cpt_irq_handler(dev, pch_iir);
1298                 else
1299                         ibx_irq_handler(dev, pch_iir);
1300
1301                 /* should clear PCH hotplug event before clear CPU irq */
1302                 I915_WRITE(SDEIIR, pch_iir);
1303         }
1304
1305         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1306                 ironlake_rps_change_irq_handler(dev);
1307 }
1308
1309 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1310 {
1311         struct drm_i915_private *dev_priv = dev->dev_private;
1312         int i;
1313
1314         if (de_iir & DE_ERR_INT_IVB)
1315                 ivb_err_int_handler(dev);
1316
1317         if (de_iir & DE_AUX_CHANNEL_A_IVB)
1318                 dp_aux_irq_handler(dev);
1319
1320         if (de_iir & DE_GSE_IVB)
1321                 intel_opregion_asle_intr(dev);
1322
1323         for (i = 0; i < 3; i++) {
1324                 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1325                         drm_handle_vblank(dev, i);
1326                 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1327                         intel_prepare_page_flip(dev, i);
1328                         intel_finish_page_flip_plane(dev, i);
1329                 }
1330         }
1331
1332         /* check event from PCH */
1333         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1334                 u32 pch_iir = I915_READ(SDEIIR);
1335
1336                 cpt_irq_handler(dev, pch_iir);
1337
1338                 /* clear PCH hotplug event before clear CPU irq */
1339                 I915_WRITE(SDEIIR, pch_iir);
1340         }
1341 }
1342
1343 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1344 {
1345         struct drm_device *dev = (struct drm_device *) arg;
1346         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1347         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1348         irqreturn_t ret = IRQ_NONE;
1349         bool err_int_reenable = false;
1350
1351         atomic_inc(&dev_priv->irq_received);
1352
1353         /* We get interrupts on unclaimed registers, so check for this before we
1354          * do any I915_{READ,WRITE}. */
1355         intel_uncore_check_errors(dev);
1356
1357         /* disable master interrupt before clearing iir  */
1358         de_ier = I915_READ(DEIER);
1359         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1360         POSTING_READ(DEIER);
1361
1362         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1363          * interrupts will will be stored on its back queue, and then we'll be
1364          * able to process them after we restore SDEIER (as soon as we restore
1365          * it, we'll get an interrupt if SDEIIR still has something to process
1366          * due to its back queue). */
1367         if (!HAS_PCH_NOP(dev)) {
1368                 sde_ier = I915_READ(SDEIER);
1369                 I915_WRITE(SDEIER, 0);
1370                 POSTING_READ(SDEIER);
1371         }
1372
1373         /* On Haswell, also mask ERR_INT because we don't want to risk
1374          * generating "unclaimed register" interrupts from inside the interrupt
1375          * handler. */
1376         if (IS_HASWELL(dev)) {
1377                 spin_lock(&dev_priv->irq_lock);
1378                 err_int_reenable = ~dev_priv->irq_mask & DE_ERR_INT_IVB;
1379                 if (err_int_reenable)
1380                         ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
1381                 spin_unlock(&dev_priv->irq_lock);
1382         }
1383
1384         gt_iir = I915_READ(GTIIR);
1385         if (gt_iir) {
1386                 if (INTEL_INFO(dev)->gen >= 6)
1387                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1388                 else
1389                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1390                 I915_WRITE(GTIIR, gt_iir);
1391                 ret = IRQ_HANDLED;
1392         }
1393
1394         de_iir = I915_READ(DEIIR);
1395         if (de_iir) {
1396                 if (INTEL_INFO(dev)->gen >= 7)
1397                         ivb_display_irq_handler(dev, de_iir);
1398                 else
1399                         ilk_display_irq_handler(dev, de_iir);
1400                 I915_WRITE(DEIIR, de_iir);
1401                 ret = IRQ_HANDLED;
1402         }
1403
1404         if (INTEL_INFO(dev)->gen >= 6) {
1405                 u32 pm_iir = I915_READ(GEN6_PMIIR);
1406                 if (pm_iir) {
1407                         gen6_rps_irq_handler(dev_priv, pm_iir);
1408                         I915_WRITE(GEN6_PMIIR, pm_iir);
1409                         ret = IRQ_HANDLED;
1410                 }
1411         }
1412
1413         if (err_int_reenable) {
1414                 spin_lock(&dev_priv->irq_lock);
1415                 if (ivb_can_enable_err_int(dev))
1416                         ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1417                 spin_unlock(&dev_priv->irq_lock);
1418         }
1419
1420         I915_WRITE(DEIER, de_ier);
1421         POSTING_READ(DEIER);
1422         if (!HAS_PCH_NOP(dev)) {
1423                 I915_WRITE(SDEIER, sde_ier);
1424                 POSTING_READ(SDEIER);
1425         }
1426
1427         return ret;
1428 }
1429
1430 /**
1431  * i915_error_work_func - do process context error handling work
1432  * @work: work struct
1433  *
1434  * Fire an error uevent so userspace can see that a hang or error
1435  * was detected.
1436  */
1437 static void i915_error_work_func(struct work_struct *work)
1438 {
1439         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1440                                                     work);
1441         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1442                                                     gpu_error);
1443         struct drm_device *dev = dev_priv->dev;
1444         struct intel_ring_buffer *ring;
1445         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1446         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1447         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1448         int i, ret;
1449
1450         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1451
1452         /*
1453          * Note that there's only one work item which does gpu resets, so we
1454          * need not worry about concurrent gpu resets potentially incrementing
1455          * error->reset_counter twice. We only need to take care of another
1456          * racing irq/hangcheck declaring the gpu dead for a second time. A
1457          * quick check for that is good enough: schedule_work ensures the
1458          * correct ordering between hang detection and this work item, and since
1459          * the reset in-progress bit is only ever set by code outside of this
1460          * work we don't need to worry about any other races.
1461          */
1462         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1463                 DRM_DEBUG_DRIVER("resetting chip\n");
1464                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1465                                    reset_event);
1466
1467                 ret = i915_reset(dev);
1468
1469                 if (ret == 0) {
1470                         /*
1471                          * After all the gem state is reset, increment the reset
1472                          * counter and wake up everyone waiting for the reset to
1473                          * complete.
1474                          *
1475                          * Since unlock operations are a one-sided barrier only,
1476                          * we need to insert a barrier here to order any seqno
1477                          * updates before
1478                          * the counter increment.
1479                          */
1480                         smp_mb__before_atomic_inc();
1481                         atomic_inc(&dev_priv->gpu_error.reset_counter);
1482
1483                         kobject_uevent_env(&dev->primary->kdev.kobj,
1484                                            KOBJ_CHANGE, reset_done_event);
1485                 } else {
1486                         atomic_set(&error->reset_counter, I915_WEDGED);
1487                 }
1488
1489                 for_each_ring(ring, dev_priv, i)
1490                         wake_up_all(&ring->irq_queue);
1491
1492                 intel_display_handle_reset(dev);
1493
1494                 wake_up_all(&dev_priv->gpu_error.reset_queue);
1495         }
1496 }
1497
1498 static void i915_report_and_clear_eir(struct drm_device *dev)
1499 {
1500         struct drm_i915_private *dev_priv = dev->dev_private;
1501         uint32_t instdone[I915_NUM_INSTDONE_REG];
1502         u32 eir = I915_READ(EIR);
1503         int pipe, i;
1504
1505         if (!eir)
1506                 return;
1507
1508         pr_err("render error detected, EIR: 0x%08x\n", eir);
1509
1510         i915_get_extra_instdone(dev, instdone);
1511
1512         if (IS_G4X(dev)) {
1513                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1514                         u32 ipeir = I915_READ(IPEIR_I965);
1515
1516                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1517                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1518                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1519                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1520                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1521                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1522                         I915_WRITE(IPEIR_I965, ipeir);
1523                         POSTING_READ(IPEIR_I965);
1524                 }
1525                 if (eir & GM45_ERROR_PAGE_TABLE) {
1526                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1527                         pr_err("page table error\n");
1528                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1529                         I915_WRITE(PGTBL_ER, pgtbl_err);
1530                         POSTING_READ(PGTBL_ER);
1531                 }
1532         }
1533
1534         if (!IS_GEN2(dev)) {
1535                 if (eir & I915_ERROR_PAGE_TABLE) {
1536                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1537                         pr_err("page table error\n");
1538                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1539                         I915_WRITE(PGTBL_ER, pgtbl_err);
1540                         POSTING_READ(PGTBL_ER);
1541                 }
1542         }
1543
1544         if (eir & I915_ERROR_MEMORY_REFRESH) {
1545                 pr_err("memory refresh error:\n");
1546                 for_each_pipe(pipe)
1547                         pr_err("pipe %c stat: 0x%08x\n",
1548                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1549                 /* pipestat has already been acked */
1550         }
1551         if (eir & I915_ERROR_INSTRUCTION) {
1552                 pr_err("instruction error\n");
1553                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1554                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1555                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1556                 if (INTEL_INFO(dev)->gen < 4) {
1557                         u32 ipeir = I915_READ(IPEIR);
1558
1559                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1560                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1561                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1562                         I915_WRITE(IPEIR, ipeir);
1563                         POSTING_READ(IPEIR);
1564                 } else {
1565                         u32 ipeir = I915_READ(IPEIR_I965);
1566
1567                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1568                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1569                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1570                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1571                         I915_WRITE(IPEIR_I965, ipeir);
1572                         POSTING_READ(IPEIR_I965);
1573                 }
1574         }
1575
1576         I915_WRITE(EIR, eir);
1577         POSTING_READ(EIR);
1578         eir = I915_READ(EIR);
1579         if (eir) {
1580                 /*
1581                  * some errors might have become stuck,
1582                  * mask them.
1583                  */
1584                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1585                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1586                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1587         }
1588 }
1589
1590 /**
1591  * i915_handle_error - handle an error interrupt
1592  * @dev: drm device
1593  *
1594  * Do some basic checking of regsiter state at error interrupt time and
1595  * dump it to the syslog.  Also call i915_capture_error_state() to make
1596  * sure we get a record and make it available in debugfs.  Fire a uevent
1597  * so userspace knows something bad happened (should trigger collection
1598  * of a ring dump etc.).
1599  */
1600 void i915_handle_error(struct drm_device *dev, bool wedged)
1601 {
1602         struct drm_i915_private *dev_priv = dev->dev_private;
1603         struct intel_ring_buffer *ring;
1604         int i;
1605
1606         i915_capture_error_state(dev);
1607         i915_report_and_clear_eir(dev);
1608
1609         if (wedged) {
1610                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1611                                 &dev_priv->gpu_error.reset_counter);
1612
1613                 /*
1614                  * Wakeup waiting processes so that the reset work item
1615                  * doesn't deadlock trying to grab various locks.
1616                  */
1617                 for_each_ring(ring, dev_priv, i)
1618                         wake_up_all(&ring->irq_queue);
1619         }
1620
1621         queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
1622 }
1623
1624 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1625 {
1626         drm_i915_private_t *dev_priv = dev->dev_private;
1627         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1629         struct drm_i915_gem_object *obj;
1630         struct intel_unpin_work *work;
1631         unsigned long flags;
1632         bool stall_detected;
1633
1634         /* Ignore early vblank irqs */
1635         if (intel_crtc == NULL)
1636                 return;
1637
1638         spin_lock_irqsave(&dev->event_lock, flags);
1639         work = intel_crtc->unpin_work;
1640
1641         if (work == NULL ||
1642             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1643             !work->enable_stall_check) {
1644                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1645                 spin_unlock_irqrestore(&dev->event_lock, flags);
1646                 return;
1647         }
1648
1649         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1650         obj = work->pending_flip_obj;
1651         if (INTEL_INFO(dev)->gen >= 4) {
1652                 int dspsurf = DSPSURF(intel_crtc->plane);
1653                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1654                                         i915_gem_obj_ggtt_offset(obj);
1655         } else {
1656                 int dspaddr = DSPADDR(intel_crtc->plane);
1657                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
1658                                                         crtc->y * crtc->fb->pitches[0] +
1659                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1660         }
1661
1662         spin_unlock_irqrestore(&dev->event_lock, flags);
1663
1664         if (stall_detected) {
1665                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1666                 intel_prepare_page_flip(dev, intel_crtc->plane);
1667         }
1668 }
1669
1670 /* Called from drm generic code, passed 'crtc' which
1671  * we use as a pipe index
1672  */
1673 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1674 {
1675         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1676         unsigned long irqflags;
1677
1678         if (!i915_pipe_enabled(dev, pipe))
1679                 return -EINVAL;
1680
1681         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1682         if (INTEL_INFO(dev)->gen >= 4)
1683                 i915_enable_pipestat(dev_priv, pipe,
1684                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1685         else
1686                 i915_enable_pipestat(dev_priv, pipe,
1687                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1688
1689         /* maintain vblank delivery even in deep C-states */
1690         if (dev_priv->info->gen == 3)
1691                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1692         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1693
1694         return 0;
1695 }
1696
1697 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1698 {
1699         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1700         unsigned long irqflags;
1701         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1702                                                      DE_PIPE_VBLANK_ILK(pipe);
1703
1704         if (!i915_pipe_enabled(dev, pipe))
1705                 return -EINVAL;
1706
1707         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1708         ironlake_enable_display_irq(dev_priv, bit);
1709         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1710
1711         return 0;
1712 }
1713
1714 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1715 {
1716         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1717         unsigned long irqflags;
1718         u32 imr;
1719
1720         if (!i915_pipe_enabled(dev, pipe))
1721                 return -EINVAL;
1722
1723         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1724         imr = I915_READ(VLV_IMR);
1725         if (pipe == 0)
1726                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1727         else
1728                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1729         I915_WRITE(VLV_IMR, imr);
1730         i915_enable_pipestat(dev_priv, pipe,
1731                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1732         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1733
1734         return 0;
1735 }
1736
1737 /* Called from drm generic code, passed 'crtc' which
1738  * we use as a pipe index
1739  */
1740 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1741 {
1742         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1743         unsigned long irqflags;
1744
1745         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1746         if (dev_priv->info->gen == 3)
1747                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1748
1749         i915_disable_pipestat(dev_priv, pipe,
1750                               PIPE_VBLANK_INTERRUPT_ENABLE |
1751                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1752         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1753 }
1754
1755 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1756 {
1757         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1758         unsigned long irqflags;
1759         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1760                                                      DE_PIPE_VBLANK_ILK(pipe);
1761
1762         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1763         ironlake_disable_display_irq(dev_priv, bit);
1764         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1765 }
1766
1767 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1768 {
1769         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1770         unsigned long irqflags;
1771         u32 imr;
1772
1773         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1774         i915_disable_pipestat(dev_priv, pipe,
1775                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1776         imr = I915_READ(VLV_IMR);
1777         if (pipe == 0)
1778                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1779         else
1780                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1781         I915_WRITE(VLV_IMR, imr);
1782         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1783 }
1784
1785 static u32
1786 ring_last_seqno(struct intel_ring_buffer *ring)
1787 {
1788         return list_entry(ring->request_list.prev,
1789                           struct drm_i915_gem_request, list)->seqno;
1790 }
1791
1792 static bool
1793 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
1794 {
1795         return (list_empty(&ring->request_list) ||
1796                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
1797 }
1798
1799 static struct intel_ring_buffer *
1800 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
1801 {
1802         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1803         u32 cmd, ipehr, acthd, acthd_min;
1804
1805         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1806         if ((ipehr & ~(0x3 << 16)) !=
1807             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1808                 return NULL;
1809
1810         /* ACTHD is likely pointing to the dword after the actual command,
1811          * so scan backwards until we find the MBOX.
1812          */
1813         acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1814         acthd_min = max((int)acthd - 3 * 4, 0);
1815         do {
1816                 cmd = ioread32(ring->virtual_start + acthd);
1817                 if (cmd == ipehr)
1818                         break;
1819
1820                 acthd -= 4;
1821                 if (acthd < acthd_min)
1822                         return NULL;
1823         } while (1);
1824
1825         *seqno = ioread32(ring->virtual_start+acthd+4)+1;
1826         return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1827 }
1828
1829 static int semaphore_passed(struct intel_ring_buffer *ring)
1830 {
1831         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1832         struct intel_ring_buffer *signaller;
1833         u32 seqno, ctl;
1834
1835         ring->hangcheck.deadlock = true;
1836
1837         signaller = semaphore_waits_for(ring, &seqno);
1838         if (signaller == NULL || signaller->hangcheck.deadlock)
1839                 return -1;
1840
1841         /* cursory check for an unkickable deadlock */
1842         ctl = I915_READ_CTL(signaller);
1843         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
1844                 return -1;
1845
1846         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
1847 }
1848
1849 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
1850 {
1851         struct intel_ring_buffer *ring;
1852         int i;
1853
1854         for_each_ring(ring, dev_priv, i)
1855                 ring->hangcheck.deadlock = false;
1856 }
1857
1858 static enum intel_ring_hangcheck_action
1859 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1860 {
1861         struct drm_device *dev = ring->dev;
1862         struct drm_i915_private *dev_priv = dev->dev_private;
1863         u32 tmp;
1864
1865         if (ring->hangcheck.acthd != acthd)
1866                 return HANGCHECK_ACTIVE;
1867
1868         if (IS_GEN2(dev))
1869                 return HANGCHECK_HUNG;
1870
1871         /* Is the chip hanging on a WAIT_FOR_EVENT?
1872          * If so we can simply poke the RB_WAIT bit
1873          * and break the hang. This should work on
1874          * all but the second generation chipsets.
1875          */
1876         tmp = I915_READ_CTL(ring);
1877         if (tmp & RING_WAIT) {
1878                 DRM_ERROR("Kicking stuck wait on %s\n",
1879                           ring->name);
1880                 I915_WRITE_CTL(ring, tmp);
1881                 return HANGCHECK_KICK;
1882         }
1883
1884         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
1885                 switch (semaphore_passed(ring)) {
1886                 default:
1887                         return HANGCHECK_HUNG;
1888                 case 1:
1889                         DRM_ERROR("Kicking stuck semaphore on %s\n",
1890                                   ring->name);
1891                         I915_WRITE_CTL(ring, tmp);
1892                         return HANGCHECK_KICK;
1893                 case 0:
1894                         return HANGCHECK_WAIT;
1895                 }
1896         }
1897
1898         return HANGCHECK_HUNG;
1899 }
1900
1901 /**
1902  * This is called when the chip hasn't reported back with completed
1903  * batchbuffers in a long time. We keep track per ring seqno progress and
1904  * if there are no progress, hangcheck score for that ring is increased.
1905  * Further, acthd is inspected to see if the ring is stuck. On stuck case
1906  * we kick the ring. If we see no progress on three subsequent calls
1907  * we assume chip is wedged and try to fix it by resetting the chip.
1908  */
1909 static void i915_hangcheck_elapsed(unsigned long data)
1910 {
1911         struct drm_device *dev = (struct drm_device *)data;
1912         drm_i915_private_t *dev_priv = dev->dev_private;
1913         struct intel_ring_buffer *ring;
1914         int i;
1915         int busy_count = 0, rings_hung = 0;
1916         bool stuck[I915_NUM_RINGS] = { 0 };
1917 #define BUSY 1
1918 #define KICK 5
1919 #define HUNG 20
1920 #define FIRE 30
1921
1922         if (!i915_enable_hangcheck)
1923                 return;
1924
1925         for_each_ring(ring, dev_priv, i) {
1926                 u32 seqno, acthd;
1927                 bool busy = true;
1928
1929                 semaphore_clear_deadlocks(dev_priv);
1930
1931                 seqno = ring->get_seqno(ring, false);
1932                 acthd = intel_ring_get_active_head(ring);
1933
1934                 if (ring->hangcheck.seqno == seqno) {
1935                         if (ring_idle(ring, seqno)) {
1936                                 if (waitqueue_active(&ring->irq_queue)) {
1937                                         /* Issue a wake-up to catch stuck h/w. */
1938                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1939                                                   ring->name);
1940                                         wake_up_all(&ring->irq_queue);
1941                                         ring->hangcheck.score += HUNG;
1942                                 } else
1943                                         busy = false;
1944                         } else {
1945                                 /* We always increment the hangcheck score
1946                                  * if the ring is busy and still processing
1947                                  * the same request, so that no single request
1948                                  * can run indefinitely (such as a chain of
1949                                  * batches). The only time we do not increment
1950                                  * the hangcheck score on this ring, if this
1951                                  * ring is in a legitimate wait for another
1952                                  * ring. In that case the waiting ring is a
1953                                  * victim and we want to be sure we catch the
1954                                  * right culprit. Then every time we do kick
1955                                  * the ring, add a small increment to the
1956                                  * score so that we can catch a batch that is
1957                                  * being repeatedly kicked and so responsible
1958                                  * for stalling the machine.
1959                                  */
1960                                 ring->hangcheck.action = ring_stuck(ring,
1961                                                                     acthd);
1962
1963                                 switch (ring->hangcheck.action) {
1964                                 case HANGCHECK_WAIT:
1965                                         break;
1966                                 case HANGCHECK_ACTIVE:
1967                                         ring->hangcheck.score += BUSY;
1968                                         break;
1969                                 case HANGCHECK_KICK:
1970                                         ring->hangcheck.score += KICK;
1971                                         break;
1972                                 case HANGCHECK_HUNG:
1973                                         ring->hangcheck.score += HUNG;
1974                                         stuck[i] = true;
1975                                         break;
1976                                 }
1977                         }
1978                 } else {
1979                         /* Gradually reduce the count so that we catch DoS
1980                          * attempts across multiple batches.
1981                          */
1982                         if (ring->hangcheck.score > 0)
1983                                 ring->hangcheck.score--;
1984                 }
1985
1986                 ring->hangcheck.seqno = seqno;
1987                 ring->hangcheck.acthd = acthd;
1988                 busy_count += busy;
1989         }
1990
1991         for_each_ring(ring, dev_priv, i) {
1992                 if (ring->hangcheck.score > FIRE) {
1993                         DRM_ERROR("%s on %s\n",
1994                                   stuck[i] ? "stuck" : "no progress",
1995                                   ring->name);
1996                         rings_hung++;
1997                 }
1998         }
1999
2000         if (rings_hung)
2001                 return i915_handle_error(dev, true);
2002
2003         if (busy_count)
2004                 /* Reset timer case chip hangs without another request
2005                  * being added */
2006                 i915_queue_hangcheck(dev);
2007 }
2008
2009 void i915_queue_hangcheck(struct drm_device *dev)
2010 {
2011         struct drm_i915_private *dev_priv = dev->dev_private;
2012         if (!i915_enable_hangcheck)
2013                 return;
2014
2015         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2016                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2017 }
2018
2019 static void ibx_irq_preinstall(struct drm_device *dev)
2020 {
2021         struct drm_i915_private *dev_priv = dev->dev_private;
2022
2023         if (HAS_PCH_NOP(dev))
2024                 return;
2025
2026         /* south display irq */
2027         I915_WRITE(SDEIMR, 0xffffffff);
2028         /*
2029          * SDEIER is also touched by the interrupt handler to work around missed
2030          * PCH interrupts. Hence we can't update it after the interrupt handler
2031          * is enabled - instead we unconditionally enable all PCH interrupt
2032          * sources here, but then only unmask them as needed with SDEIMR.
2033          */
2034         I915_WRITE(SDEIER, 0xffffffff);
2035         POSTING_READ(SDEIER);
2036 }
2037
2038 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2039 {
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041
2042         /* and GT */
2043         I915_WRITE(GTIMR, 0xffffffff);
2044         I915_WRITE(GTIER, 0x0);
2045         POSTING_READ(GTIER);
2046
2047         if (INTEL_INFO(dev)->gen >= 6) {
2048                 /* and PM */
2049                 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2050                 I915_WRITE(GEN6_PMIER, 0x0);
2051                 POSTING_READ(GEN6_PMIER);
2052         }
2053 }
2054
2055 /* drm_dma.h hooks
2056 */
2057 static void ironlake_irq_preinstall(struct drm_device *dev)
2058 {
2059         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2060
2061         atomic_set(&dev_priv->irq_received, 0);
2062
2063         I915_WRITE(HWSTAM, 0xeffe);
2064
2065         I915_WRITE(DEIMR, 0xffffffff);
2066         I915_WRITE(DEIER, 0x0);
2067         POSTING_READ(DEIER);
2068
2069         gen5_gt_irq_preinstall(dev);
2070
2071         ibx_irq_preinstall(dev);
2072 }
2073
2074 static void valleyview_irq_preinstall(struct drm_device *dev)
2075 {
2076         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2077         int pipe;
2078
2079         atomic_set(&dev_priv->irq_received, 0);
2080
2081         /* VLV magic */
2082         I915_WRITE(VLV_IMR, 0);
2083         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2084         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2085         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2086
2087         /* and GT */
2088         I915_WRITE(GTIIR, I915_READ(GTIIR));
2089         I915_WRITE(GTIIR, I915_READ(GTIIR));
2090
2091         gen5_gt_irq_preinstall(dev);
2092
2093         I915_WRITE(DPINVGTT, 0xff);
2094
2095         I915_WRITE(PORT_HOTPLUG_EN, 0);
2096         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2097         for_each_pipe(pipe)
2098                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2099         I915_WRITE(VLV_IIR, 0xffffffff);
2100         I915_WRITE(VLV_IMR, 0xffffffff);
2101         I915_WRITE(VLV_IER, 0x0);
2102         POSTING_READ(VLV_IER);
2103 }
2104
2105 static void ibx_hpd_irq_setup(struct drm_device *dev)
2106 {
2107         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2108         struct drm_mode_config *mode_config = &dev->mode_config;
2109         struct intel_encoder *intel_encoder;
2110         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2111
2112         if (HAS_PCH_IBX(dev)) {
2113                 hotplug_irqs = SDE_HOTPLUG_MASK;
2114                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2115                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2116                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2117         } else {
2118                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2119                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2120                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2121                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2122         }
2123
2124         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2125
2126         /*
2127          * Enable digital hotplug on the PCH, and configure the DP short pulse
2128          * duration to 2ms (which is the minimum in the Display Port spec)
2129          *
2130          * This register is the same on all known PCH chips.
2131          */
2132         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2133         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2134         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2135         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2136         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2137         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2138 }
2139
2140 static void ibx_irq_postinstall(struct drm_device *dev)
2141 {
2142         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2143         u32 mask;
2144
2145         if (HAS_PCH_NOP(dev))
2146                 return;
2147
2148         if (HAS_PCH_IBX(dev)) {
2149                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2150                        SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2151         } else {
2152                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2153
2154                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2155         }
2156
2157         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2158         I915_WRITE(SDEIMR, ~mask);
2159 }
2160
2161 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2162 {
2163         struct drm_i915_private *dev_priv = dev->dev_private;
2164         u32 pm_irqs, gt_irqs;
2165
2166         pm_irqs = gt_irqs = 0;
2167
2168         dev_priv->gt_irq_mask = ~0;
2169         if (HAS_L3_GPU_CACHE(dev)) {
2170                 /* L3 parity interrupt is always unmasked. */
2171                 dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2172                 gt_irqs |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2173         }
2174
2175         gt_irqs |= GT_RENDER_USER_INTERRUPT;
2176         if (IS_GEN5(dev)) {
2177                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2178                            ILK_BSD_USER_INTERRUPT;
2179         } else {
2180                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2181         }
2182
2183         I915_WRITE(GTIIR, I915_READ(GTIIR));
2184         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2185         I915_WRITE(GTIER, gt_irqs);
2186         POSTING_READ(GTIER);
2187
2188         if (INTEL_INFO(dev)->gen >= 6) {
2189                 pm_irqs |= GEN6_PM_RPS_EVENTS;
2190
2191                 if (HAS_VEBOX(dev))
2192                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2193
2194                 dev_priv->pm_irq_mask = 0xffffffff;
2195                 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2196                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2197                 I915_WRITE(GEN6_PMIER, pm_irqs);
2198                 POSTING_READ(GEN6_PMIER);
2199         }
2200 }
2201
2202 static int ironlake_irq_postinstall(struct drm_device *dev)
2203 {
2204         unsigned long irqflags;
2205         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2206         u32 display_mask, extra_mask;
2207
2208         if (INTEL_INFO(dev)->gen >= 7) {
2209                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2210                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2211                                 DE_PLANEB_FLIP_DONE_IVB |
2212                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2213                                 DE_ERR_INT_IVB);
2214                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2215                               DE_PIPEA_VBLANK_IVB);
2216
2217                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2218         } else {
2219                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2220                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2221                                 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2222                                 DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
2223                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2224         }
2225
2226         dev_priv->irq_mask = ~display_mask;
2227
2228         /* should always can generate irq */
2229         I915_WRITE(DEIIR, I915_READ(DEIIR));
2230         I915_WRITE(DEIMR, dev_priv->irq_mask);
2231         I915_WRITE(DEIER, display_mask | extra_mask);
2232         POSTING_READ(DEIER);
2233
2234         gen5_gt_irq_postinstall(dev);
2235
2236         ibx_irq_postinstall(dev);
2237
2238         if (IS_IRONLAKE_M(dev)) {
2239                 /* Enable PCU event interrupts
2240                  *
2241                  * spinlocking not required here for correctness since interrupt
2242                  * setup is guaranteed to run in single-threaded context. But we
2243                  * need it to make the assert_spin_locked happy. */
2244                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2245                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2246                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2247         }
2248
2249         return 0;
2250 }
2251
2252 static int valleyview_irq_postinstall(struct drm_device *dev)
2253 {
2254         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2255         u32 enable_mask;
2256         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2257         unsigned long irqflags;
2258
2259         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2260         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2261                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2262                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2263                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2264
2265         /*
2266          *Leave vblank interrupts masked initially.  enable/disable will
2267          * toggle them based on usage.
2268          */
2269         dev_priv->irq_mask = (~enable_mask) |
2270                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2271                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2272
2273         I915_WRITE(PORT_HOTPLUG_EN, 0);
2274         POSTING_READ(PORT_HOTPLUG_EN);
2275
2276         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2277         I915_WRITE(VLV_IER, enable_mask);
2278         I915_WRITE(VLV_IIR, 0xffffffff);
2279         I915_WRITE(PIPESTAT(0), 0xffff);
2280         I915_WRITE(PIPESTAT(1), 0xffff);
2281         POSTING_READ(VLV_IER);
2282
2283         /* Interrupt setup is already guaranteed to be single-threaded, this is
2284          * just to make the assert_spin_locked check happy. */
2285         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2286         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2287         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2288         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2289         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2290
2291         I915_WRITE(VLV_IIR, 0xffffffff);
2292         I915_WRITE(VLV_IIR, 0xffffffff);
2293
2294         gen5_gt_irq_postinstall(dev);
2295
2296         /* ack & enable invalid PTE error interrupts */
2297 #if 0 /* FIXME: add support to irq handler for checking these bits */
2298         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2299         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2300 #endif
2301
2302         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2303
2304         return 0;
2305 }
2306
2307 static void valleyview_irq_uninstall(struct drm_device *dev)
2308 {
2309         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2310         int pipe;
2311
2312         if (!dev_priv)
2313                 return;
2314
2315         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2316
2317         for_each_pipe(pipe)
2318                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2319
2320         I915_WRITE(HWSTAM, 0xffffffff);
2321         I915_WRITE(PORT_HOTPLUG_EN, 0);
2322         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2323         for_each_pipe(pipe)
2324                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2325         I915_WRITE(VLV_IIR, 0xffffffff);
2326         I915_WRITE(VLV_IMR, 0xffffffff);
2327         I915_WRITE(VLV_IER, 0x0);
2328         POSTING_READ(VLV_IER);
2329 }
2330
2331 static void ironlake_irq_uninstall(struct drm_device *dev)
2332 {
2333         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2334
2335         if (!dev_priv)
2336                 return;
2337
2338         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2339
2340         I915_WRITE(HWSTAM, 0xffffffff);
2341
2342         I915_WRITE(DEIMR, 0xffffffff);
2343         I915_WRITE(DEIER, 0x0);
2344         I915_WRITE(DEIIR, I915_READ(DEIIR));
2345         if (IS_GEN7(dev))
2346                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2347
2348         I915_WRITE(GTIMR, 0xffffffff);
2349         I915_WRITE(GTIER, 0x0);
2350         I915_WRITE(GTIIR, I915_READ(GTIIR));
2351
2352         if (HAS_PCH_NOP(dev))
2353                 return;
2354
2355         I915_WRITE(SDEIMR, 0xffffffff);
2356         I915_WRITE(SDEIER, 0x0);
2357         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2358         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2359                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2360 }
2361
2362 static void i8xx_irq_preinstall(struct drm_device * dev)
2363 {
2364         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2365         int pipe;
2366
2367         atomic_set(&dev_priv->irq_received, 0);
2368
2369         for_each_pipe(pipe)
2370                 I915_WRITE(PIPESTAT(pipe), 0);
2371         I915_WRITE16(IMR, 0xffff);
2372         I915_WRITE16(IER, 0x0);
2373         POSTING_READ16(IER);
2374 }
2375
2376 static int i8xx_irq_postinstall(struct drm_device *dev)
2377 {
2378         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2379
2380         I915_WRITE16(EMR,
2381                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2382
2383         /* Unmask the interrupts that we always want on. */
2384         dev_priv->irq_mask =
2385                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2386                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2387                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2388                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2389                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2390         I915_WRITE16(IMR, dev_priv->irq_mask);
2391
2392         I915_WRITE16(IER,
2393                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2394                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2395                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2396                      I915_USER_INTERRUPT);
2397         POSTING_READ16(IER);
2398
2399         return 0;
2400 }
2401
2402 /*
2403  * Returns true when a page flip has completed.
2404  */
2405 static bool i8xx_handle_vblank(struct drm_device *dev,
2406                                int pipe, u16 iir)
2407 {
2408         drm_i915_private_t *dev_priv = dev->dev_private;
2409         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2410
2411         if (!drm_handle_vblank(dev, pipe))
2412                 return false;
2413
2414         if ((iir & flip_pending) == 0)
2415                 return false;
2416
2417         intel_prepare_page_flip(dev, pipe);
2418
2419         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2420          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2421          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2422          * the flip is completed (no longer pending). Since this doesn't raise
2423          * an interrupt per se, we watch for the change at vblank.
2424          */
2425         if (I915_READ16(ISR) & flip_pending)
2426                 return false;
2427
2428         intel_finish_page_flip(dev, pipe);
2429
2430         return true;
2431 }
2432
2433 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2434 {
2435         struct drm_device *dev = (struct drm_device *) arg;
2436         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2437         u16 iir, new_iir;
2438         u32 pipe_stats[2];
2439         unsigned long irqflags;
2440         int pipe;
2441         u16 flip_mask =
2442                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2443                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2444
2445         atomic_inc(&dev_priv->irq_received);
2446
2447         iir = I915_READ16(IIR);
2448         if (iir == 0)
2449                 return IRQ_NONE;
2450
2451         while (iir & ~flip_mask) {
2452                 /* Can't rely on pipestat interrupt bit in iir as it might
2453                  * have been cleared after the pipestat interrupt was received.
2454                  * It doesn't set the bit in iir again, but it still produces
2455                  * interrupts (for non-MSI).
2456                  */
2457                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2458                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2459                         i915_handle_error(dev, false);
2460
2461                 for_each_pipe(pipe) {
2462                         int reg = PIPESTAT(pipe);
2463                         pipe_stats[pipe] = I915_READ(reg);
2464
2465                         /*
2466                          * Clear the PIPE*STAT regs before the IIR
2467                          */
2468                         if (pipe_stats[pipe] & 0x8000ffff) {
2469                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2470                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2471                                                          pipe_name(pipe));
2472                                 I915_WRITE(reg, pipe_stats[pipe]);
2473                         }
2474                 }
2475                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2476
2477                 I915_WRITE16(IIR, iir & ~flip_mask);
2478                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2479
2480                 i915_update_dri1_breadcrumb(dev);
2481
2482                 if (iir & I915_USER_INTERRUPT)
2483                         notify_ring(dev, &dev_priv->ring[RCS]);
2484
2485                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2486                     i8xx_handle_vblank(dev, 0, iir))
2487                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2488
2489                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2490                     i8xx_handle_vblank(dev, 1, iir))
2491                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2492
2493                 iir = new_iir;
2494         }
2495
2496         return IRQ_HANDLED;
2497 }
2498
2499 static void i8xx_irq_uninstall(struct drm_device * dev)
2500 {
2501         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2502         int pipe;
2503
2504         for_each_pipe(pipe) {
2505                 /* Clear enable bits; then clear status bits */
2506                 I915_WRITE(PIPESTAT(pipe), 0);
2507                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2508         }
2509         I915_WRITE16(IMR, 0xffff);
2510         I915_WRITE16(IER, 0x0);
2511         I915_WRITE16(IIR, I915_READ16(IIR));
2512 }
2513
2514 static void i915_irq_preinstall(struct drm_device * dev)
2515 {
2516         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2517         int pipe;
2518
2519         atomic_set(&dev_priv->irq_received, 0);
2520
2521         if (I915_HAS_HOTPLUG(dev)) {
2522                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2523                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2524         }
2525
2526         I915_WRITE16(HWSTAM, 0xeffe);
2527         for_each_pipe(pipe)
2528                 I915_WRITE(PIPESTAT(pipe), 0);
2529         I915_WRITE(IMR, 0xffffffff);
2530         I915_WRITE(IER, 0x0);
2531         POSTING_READ(IER);
2532 }
2533
2534 static int i915_irq_postinstall(struct drm_device *dev)
2535 {
2536         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2537         u32 enable_mask;
2538
2539         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2540
2541         /* Unmask the interrupts that we always want on. */
2542         dev_priv->irq_mask =
2543                 ~(I915_ASLE_INTERRUPT |
2544                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2545                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2546                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2547                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2548                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2549
2550         enable_mask =
2551                 I915_ASLE_INTERRUPT |
2552                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2553                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2554                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2555                 I915_USER_INTERRUPT;
2556
2557         if (I915_HAS_HOTPLUG(dev)) {
2558                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2559                 POSTING_READ(PORT_HOTPLUG_EN);
2560
2561                 /* Enable in IER... */
2562                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2563                 /* and unmask in IMR */
2564                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2565         }
2566
2567         I915_WRITE(IMR, dev_priv->irq_mask);
2568         I915_WRITE(IER, enable_mask);
2569         POSTING_READ(IER);
2570
2571         i915_enable_asle_pipestat(dev);
2572
2573         return 0;
2574 }
2575
2576 /*
2577  * Returns true when a page flip has completed.
2578  */
2579 static bool i915_handle_vblank(struct drm_device *dev,
2580                                int plane, int pipe, u32 iir)
2581 {
2582         drm_i915_private_t *dev_priv = dev->dev_private;
2583         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2584
2585         if (!drm_handle_vblank(dev, pipe))
2586                 return false;
2587
2588         if ((iir & flip_pending) == 0)
2589                 return false;
2590
2591         intel_prepare_page_flip(dev, plane);
2592
2593         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2594          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2595          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2596          * the flip is completed (no longer pending). Since this doesn't raise
2597          * an interrupt per se, we watch for the change at vblank.
2598          */
2599         if (I915_READ(ISR) & flip_pending)
2600                 return false;
2601
2602         intel_finish_page_flip(dev, pipe);
2603
2604         return true;
2605 }
2606
2607 static irqreturn_t i915_irq_handler(int irq, void *arg)
2608 {
2609         struct drm_device *dev = (struct drm_device *) arg;
2610         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2611         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2612         unsigned long irqflags;
2613         u32 flip_mask =
2614                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2615                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2616         int pipe, ret = IRQ_NONE;
2617
2618         atomic_inc(&dev_priv->irq_received);
2619
2620         iir = I915_READ(IIR);
2621         do {
2622                 bool irq_received = (iir & ~flip_mask) != 0;
2623                 bool blc_event = false;
2624
2625                 /* Can't rely on pipestat interrupt bit in iir as it might
2626                  * have been cleared after the pipestat interrupt was received.
2627                  * It doesn't set the bit in iir again, but it still produces
2628                  * interrupts (for non-MSI).
2629                  */
2630                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2631                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2632                         i915_handle_error(dev, false);
2633
2634                 for_each_pipe(pipe) {
2635                         int reg = PIPESTAT(pipe);
2636                         pipe_stats[pipe] = I915_READ(reg);
2637
2638                         /* Clear the PIPE*STAT regs before the IIR */
2639                         if (pipe_stats[pipe] & 0x8000ffff) {
2640                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2641                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2642                                                          pipe_name(pipe));
2643                                 I915_WRITE(reg, pipe_stats[pipe]);
2644                                 irq_received = true;
2645                         }
2646                 }
2647                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2648
2649                 if (!irq_received)
2650                         break;
2651
2652                 /* Consume port.  Then clear IIR or we'll miss events */
2653                 if ((I915_HAS_HOTPLUG(dev)) &&
2654                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2655                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2656                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2657
2658                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2659                                   hotplug_status);
2660
2661                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
2662
2663                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2664                         POSTING_READ(PORT_HOTPLUG_STAT);
2665                 }
2666
2667                 I915_WRITE(IIR, iir & ~flip_mask);
2668                 new_iir = I915_READ(IIR); /* Flush posted writes */
2669
2670                 if (iir & I915_USER_INTERRUPT)
2671                         notify_ring(dev, &dev_priv->ring[RCS]);
2672
2673                 for_each_pipe(pipe) {
2674                         int plane = pipe;
2675                         if (IS_MOBILE(dev))
2676                                 plane = !plane;
2677
2678                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2679                             i915_handle_vblank(dev, plane, pipe, iir))
2680                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2681
2682                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2683                                 blc_event = true;
2684                 }
2685
2686                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2687                         intel_opregion_asle_intr(dev);
2688
2689                 /* With MSI, interrupts are only generated when iir
2690                  * transitions from zero to nonzero.  If another bit got
2691                  * set while we were handling the existing iir bits, then
2692                  * we would never get another interrupt.
2693                  *
2694                  * This is fine on non-MSI as well, as if we hit this path
2695                  * we avoid exiting the interrupt handler only to generate
2696                  * another one.
2697                  *
2698                  * Note that for MSI this could cause a stray interrupt report
2699                  * if an interrupt landed in the time between writing IIR and
2700                  * the posting read.  This should be rare enough to never
2701                  * trigger the 99% of 100,000 interrupts test for disabling
2702                  * stray interrupts.
2703                  */
2704                 ret = IRQ_HANDLED;
2705                 iir = new_iir;
2706         } while (iir & ~flip_mask);
2707
2708         i915_update_dri1_breadcrumb(dev);
2709
2710         return ret;
2711 }
2712
2713 static void i915_irq_uninstall(struct drm_device * dev)
2714 {
2715         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2716         int pipe;
2717
2718         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2719
2720         if (I915_HAS_HOTPLUG(dev)) {
2721                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2722                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2723         }
2724
2725         I915_WRITE16(HWSTAM, 0xffff);
2726         for_each_pipe(pipe) {
2727                 /* Clear enable bits; then clear status bits */
2728                 I915_WRITE(PIPESTAT(pipe), 0);
2729                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2730         }
2731         I915_WRITE(IMR, 0xffffffff);
2732         I915_WRITE(IER, 0x0);
2733
2734         I915_WRITE(IIR, I915_READ(IIR));
2735 }
2736
2737 static void i965_irq_preinstall(struct drm_device * dev)
2738 {
2739         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2740         int pipe;
2741
2742         atomic_set(&dev_priv->irq_received, 0);
2743
2744         I915_WRITE(PORT_HOTPLUG_EN, 0);
2745         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2746
2747         I915_WRITE(HWSTAM, 0xeffe);
2748         for_each_pipe(pipe)
2749                 I915_WRITE(PIPESTAT(pipe), 0);
2750         I915_WRITE(IMR, 0xffffffff);
2751         I915_WRITE(IER, 0x0);
2752         POSTING_READ(IER);
2753 }
2754
2755 static int i965_irq_postinstall(struct drm_device *dev)
2756 {
2757         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2758         u32 enable_mask;
2759         u32 error_mask;
2760         unsigned long irqflags;
2761
2762         /* Unmask the interrupts that we always want on. */
2763         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2764                                I915_DISPLAY_PORT_INTERRUPT |
2765                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2766                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2767                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2768                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2769                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2770
2771         enable_mask = ~dev_priv->irq_mask;
2772         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2773                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2774         enable_mask |= I915_USER_INTERRUPT;
2775
2776         if (IS_G4X(dev))
2777                 enable_mask |= I915_BSD_USER_INTERRUPT;
2778
2779         /* Interrupt setup is already guaranteed to be single-threaded, this is
2780          * just to make the assert_spin_locked check happy. */
2781         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2782         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2783         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2784
2785         /*
2786          * Enable some error detection, note the instruction error mask
2787          * bit is reserved, so we leave it masked.
2788          */
2789         if (IS_G4X(dev)) {
2790                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2791                                GM45_ERROR_MEM_PRIV |
2792                                GM45_ERROR_CP_PRIV |
2793                                I915_ERROR_MEMORY_REFRESH);
2794         } else {
2795                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2796                                I915_ERROR_MEMORY_REFRESH);
2797         }
2798         I915_WRITE(EMR, error_mask);
2799
2800         I915_WRITE(IMR, dev_priv->irq_mask);
2801         I915_WRITE(IER, enable_mask);
2802         POSTING_READ(IER);
2803
2804         I915_WRITE(PORT_HOTPLUG_EN, 0);
2805         POSTING_READ(PORT_HOTPLUG_EN);
2806
2807         i915_enable_asle_pipestat(dev);
2808
2809         return 0;
2810 }
2811
2812 static void i915_hpd_irq_setup(struct drm_device *dev)
2813 {
2814         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2815         struct drm_mode_config *mode_config = &dev->mode_config;
2816         struct intel_encoder *intel_encoder;
2817         u32 hotplug_en;
2818
2819         assert_spin_locked(&dev_priv->irq_lock);
2820
2821         if (I915_HAS_HOTPLUG(dev)) {
2822                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2823                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2824                 /* Note HDMI and DP share hotplug bits */
2825                 /* enable bits are the same for all generations */
2826                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2827                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2828                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
2829                 /* Programming the CRT detection parameters tends
2830                    to generate a spurious hotplug event about three
2831                    seconds later.  So just do it once.
2832                 */
2833                 if (IS_G4X(dev))
2834                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2835                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
2836                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2837
2838                 /* Ignore TV since it's buggy */
2839                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2840         }
2841 }
2842
2843 static irqreturn_t i965_irq_handler(int irq, void *arg)
2844 {
2845         struct drm_device *dev = (struct drm_device *) arg;
2846         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2847         u32 iir, new_iir;
2848         u32 pipe_stats[I915_MAX_PIPES];
2849         unsigned long irqflags;
2850         int irq_received;
2851         int ret = IRQ_NONE, pipe;
2852         u32 flip_mask =
2853                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2854                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2855
2856         atomic_inc(&dev_priv->irq_received);
2857
2858         iir = I915_READ(IIR);
2859
2860         for (;;) {
2861                 bool blc_event = false;
2862
2863                 irq_received = (iir & ~flip_mask) != 0;
2864
2865                 /* Can't rely on pipestat interrupt bit in iir as it might
2866                  * have been cleared after the pipestat interrupt was received.
2867                  * It doesn't set the bit in iir again, but it still produces
2868                  * interrupts (for non-MSI).
2869                  */
2870                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2871                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2872                         i915_handle_error(dev, false);
2873
2874                 for_each_pipe(pipe) {
2875                         int reg = PIPESTAT(pipe);
2876                         pipe_stats[pipe] = I915_READ(reg);
2877
2878                         /*
2879                          * Clear the PIPE*STAT regs before the IIR
2880                          */
2881                         if (pipe_stats[pipe] & 0x8000ffff) {
2882                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2883                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2884                                                          pipe_name(pipe));
2885                                 I915_WRITE(reg, pipe_stats[pipe]);
2886                                 irq_received = 1;
2887                         }
2888                 }
2889                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2890
2891                 if (!irq_received)
2892                         break;
2893
2894                 ret = IRQ_HANDLED;
2895
2896                 /* Consume port.  Then clear IIR or we'll miss events */
2897                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2898                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2899                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
2900                                                                   HOTPLUG_INT_STATUS_G4X :
2901                                                                   HOTPLUG_INT_STATUS_I915);
2902
2903                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2904                                   hotplug_status);
2905
2906                         intel_hpd_irq_handler(dev, hotplug_trigger,
2907                                               IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
2908
2909                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2910                         I915_READ(PORT_HOTPLUG_STAT);
2911                 }
2912
2913                 I915_WRITE(IIR, iir & ~flip_mask);
2914                 new_iir = I915_READ(IIR); /* Flush posted writes */
2915
2916                 if (iir & I915_USER_INTERRUPT)
2917                         notify_ring(dev, &dev_priv->ring[RCS]);
2918                 if (iir & I915_BSD_USER_INTERRUPT)
2919                         notify_ring(dev, &dev_priv->ring[VCS]);
2920
2921                 for_each_pipe(pipe) {
2922                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2923                             i915_handle_vblank(dev, pipe, pipe, iir))
2924                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
2925
2926                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2927                                 blc_event = true;
2928                 }
2929
2930
2931                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2932                         intel_opregion_asle_intr(dev);
2933
2934                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2935                         gmbus_irq_handler(dev);
2936
2937                 /* With MSI, interrupts are only generated when iir
2938                  * transitions from zero to nonzero.  If another bit got
2939                  * set while we were handling the existing iir bits, then
2940                  * we would never get another interrupt.
2941                  *
2942                  * This is fine on non-MSI as well, as if we hit this path
2943                  * we avoid exiting the interrupt handler only to generate
2944                  * another one.
2945                  *
2946                  * Note that for MSI this could cause a stray interrupt report
2947                  * if an interrupt landed in the time between writing IIR and
2948                  * the posting read.  This should be rare enough to never
2949                  * trigger the 99% of 100,000 interrupts test for disabling
2950                  * stray interrupts.
2951                  */
2952                 iir = new_iir;
2953         }
2954
2955         i915_update_dri1_breadcrumb(dev);
2956
2957         return ret;
2958 }
2959
2960 static void i965_irq_uninstall(struct drm_device * dev)
2961 {
2962         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2963         int pipe;
2964
2965         if (!dev_priv)
2966                 return;
2967
2968         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2969
2970         I915_WRITE(PORT_HOTPLUG_EN, 0);
2971         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2972
2973         I915_WRITE(HWSTAM, 0xffffffff);
2974         for_each_pipe(pipe)
2975                 I915_WRITE(PIPESTAT(pipe), 0);
2976         I915_WRITE(IMR, 0xffffffff);
2977         I915_WRITE(IER, 0x0);
2978
2979         for_each_pipe(pipe)
2980                 I915_WRITE(PIPESTAT(pipe),
2981                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2982         I915_WRITE(IIR, I915_READ(IIR));
2983 }
2984
2985 static void i915_reenable_hotplug_timer_func(unsigned long data)
2986 {
2987         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
2988         struct drm_device *dev = dev_priv->dev;
2989         struct drm_mode_config *mode_config = &dev->mode_config;
2990         unsigned long irqflags;
2991         int i;
2992
2993         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2994         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
2995                 struct drm_connector *connector;
2996
2997                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
2998                         continue;
2999
3000                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3001
3002                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3003                         struct intel_connector *intel_connector = to_intel_connector(connector);
3004
3005                         if (intel_connector->encoder->hpd_pin == i) {
3006                                 if (connector->polled != intel_connector->polled)
3007                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3008                                                          drm_get_connector_name(connector));
3009                                 connector->polled = intel_connector->polled;
3010                                 if (!connector->polled)
3011                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3012                         }
3013                 }
3014         }
3015         if (dev_priv->display.hpd_irq_setup)
3016                 dev_priv->display.hpd_irq_setup(dev);
3017         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3018 }
3019
3020 void intel_irq_init(struct drm_device *dev)
3021 {
3022         struct drm_i915_private *dev_priv = dev->dev_private;
3023
3024         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3025         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3026         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3027         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3028
3029         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3030                     i915_hangcheck_elapsed,
3031                     (unsigned long) dev);
3032         setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3033                     (unsigned long) dev_priv);
3034
3035         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3036
3037         dev->driver->get_vblank_counter = i915_get_vblank_counter;
3038         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3039         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3040                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3041                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3042         }
3043
3044         if (drm_core_check_feature(dev, DRIVER_MODESET))
3045                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3046         else
3047                 dev->driver->get_vblank_timestamp = NULL;
3048         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3049
3050         if (IS_VALLEYVIEW(dev)) {
3051                 dev->driver->irq_handler = valleyview_irq_handler;
3052                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3053                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3054                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3055                 dev->driver->enable_vblank = valleyview_enable_vblank;
3056                 dev->driver->disable_vblank = valleyview_disable_vblank;
3057                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3058         } else if (HAS_PCH_SPLIT(dev)) {
3059                 dev->driver->irq_handler = ironlake_irq_handler;
3060                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3061                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3062                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3063                 dev->driver->enable_vblank = ironlake_enable_vblank;
3064                 dev->driver->disable_vblank = ironlake_disable_vblank;
3065                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3066         } else {
3067                 if (INTEL_INFO(dev)->gen == 2) {
3068                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
3069                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
3070                         dev->driver->irq_handler = i8xx_irq_handler;
3071                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
3072                 } else if (INTEL_INFO(dev)->gen == 3) {
3073                         dev->driver->irq_preinstall = i915_irq_preinstall;
3074                         dev->driver->irq_postinstall = i915_irq_postinstall;
3075                         dev->driver->irq_uninstall = i915_irq_uninstall;
3076                         dev->driver->irq_handler = i915_irq_handler;
3077                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3078                 } else {
3079                         dev->driver->irq_preinstall = i965_irq_preinstall;
3080                         dev->driver->irq_postinstall = i965_irq_postinstall;
3081                         dev->driver->irq_uninstall = i965_irq_uninstall;
3082                         dev->driver->irq_handler = i965_irq_handler;
3083                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3084                 }
3085                 dev->driver->enable_vblank = i915_enable_vblank;
3086                 dev->driver->disable_vblank = i915_disable_vblank;
3087         }
3088 }
3089
3090 void intel_hpd_init(struct drm_device *dev)
3091 {
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093         struct drm_mode_config *mode_config = &dev->mode_config;
3094         struct drm_connector *connector;
3095         unsigned long irqflags;
3096         int i;
3097
3098         for (i = 1; i < HPD_NUM_PINS; i++) {
3099                 dev_priv->hpd_stats[i].hpd_cnt = 0;
3100                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3101         }
3102         list_for_each_entry(connector, &mode_config->connector_list, head) {
3103                 struct intel_connector *intel_connector = to_intel_connector(connector);
3104                 connector->polled = intel_connector->polled;
3105                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3106                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3107         }
3108
3109         /* Interrupt setup is already guaranteed to be single-threaded, this is
3110          * just to make the assert_spin_locked checks happy. */
3111         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3112         if (dev_priv->display.hpd_irq_setup)
3113                 dev_priv->display.hpd_irq_setup(dev);
3114         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3115 }