drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  54 };
  55
  56 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  57         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  58         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  59         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  60         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  61         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  62 };
  63
  64 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  65         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  66         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  67         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  68         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  69         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  70         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  71 };
  72
  73 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  74         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  75         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  76         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  77         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  78         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  80 };
  81
  82 static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are the same */
  83         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  84         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  85         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  86         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  87         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  88         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  89 };
  90
  91 /* IIR can theoretically queue up two events. Be paranoid. */
  92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
  93         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
  94         POSTING_READ(GEN8_##type##_IMR(which)); \
  95         I915_WRITE(GEN8_##type##_IER(which), 0); \
  96         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  97         POSTING_READ(GEN8_##type##_IIR(which)); \
  98         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  99         POSTING_READ(GEN8_##type##_IIR(which)); \
 100 } while (0)
 101
 102 #define GEN5_IRQ_RESET(type) do { \
 103         I915_WRITE(type##IMR, 0xffffffff); \
 104         POSTING_READ(type##IMR); \
 105         I915_WRITE(type##IER, 0); \
 106         I915_WRITE(type##IIR, 0xffffffff); \
 107         POSTING_READ(type##IIR); \
 108         I915_WRITE(type##IIR, 0xffffffff); \
 109         POSTING_READ(type##IIR); \
 110 } while (0)
 111
 112 /*
 113  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 114  */
 115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
 116         u32 val = I915_READ(reg); \
 117         if (val) { \
 118                 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
 119                      (reg), val); \
 120                 I915_WRITE((reg), 0xffffffff); \
 121                 POSTING_READ(reg); \
 122                 I915_WRITE((reg), 0xffffffff); \
 123                 POSTING_READ(reg); \
 124         } \
 125 } while (0)
 126
 127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 128         GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
 129         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 130         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 131         POSTING_READ(GEN8_##type##_IMR(which)); \
 132 } while (0)
 133
 134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 135         GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
 136         I915_WRITE(type##IER, (ier_val)); \
 137         I915_WRITE(type##IMR, (imr_val)); \
 138         POSTING_READ(type##IMR); \
 139 } while (0)
 140
 141 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 142
 143 /* For display hotplug interrupt */
 144 void
 145 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 146 {
 147         assert_spin_locked(&dev_priv->irq_lock);
 148
 149         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 150                 return;
 151
 152         if ((dev_priv->irq_mask & mask) != 0) {
 153                 dev_priv->irq_mask &= ~mask;
 154                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 155                 POSTING_READ(DEIMR);
 156         }
 157 }
 158
 159 void
 160 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 161 {
 162         assert_spin_locked(&dev_priv->irq_lock);
 163
 164         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 165                 return;
 166
 167         if ((dev_priv->irq_mask & mask) != mask) {
 168                 dev_priv->irq_mask |= mask;
 169                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 170                 POSTING_READ(DEIMR);
 171         }
 172 }
 173
 174 /**
 175  * ilk_update_gt_irq - update GTIMR
 176  * @dev_priv: driver private
 177  * @interrupt_mask: mask of interrupt bits to update
 178  * @enabled_irq_mask: mask of interrupt bits to enable
 179  */
 180 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 181                               uint32_t interrupt_mask,
 182                               uint32_t enabled_irq_mask)
 183 {
 184         assert_spin_locked(&dev_priv->irq_lock);
 185
 186         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 187
 188         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 189                 return;
 190
 191         dev_priv->gt_irq_mask &= ~interrupt_mask;
 192         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 193         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 194         POSTING_READ(GTIMR);
 195 }
 196
 197 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 198 {
 199         ilk_update_gt_irq(dev_priv, mask, mask);
 200 }
 201
 202 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 203 {
 204         ilk_update_gt_irq(dev_priv, mask, 0);
 205 }
 206
 207 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
 208 {
 209         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 210 }
 211
 212 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
 213 {
 214         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 215 }
 216
 217 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
 218 {
 219         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 220 }
 221
 222 /**
 223   * snb_update_pm_irq - update GEN6_PMIMR
 224   * @dev_priv: driver private
 225   * @interrupt_mask: mask of interrupt bits to update
 226   * @enabled_irq_mask: mask of interrupt bits to enable
 227   */
 228 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 229                               uint32_t interrupt_mask,
 230                               uint32_t enabled_irq_mask)
 231 {
 232         uint32_t new_val;
 233
 234         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 235
 236         assert_spin_locked(&dev_priv->irq_lock);
 237
 238         new_val = dev_priv->pm_irq_mask;
 239         new_val &= ~interrupt_mask;
 240         new_val |= (~enabled_irq_mask & interrupt_mask);
 241
 242         if (new_val != dev_priv->pm_irq_mask) {
 243                 dev_priv->pm_irq_mask = new_val;
 244                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
 245                 POSTING_READ(gen6_pm_imr(dev_priv));
 246         }
 247 }
 248
 249 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 250 {
 251         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 252                 return;
 253
 254         snb_update_pm_irq(dev_priv, mask, mask);
 255 }
 256
 257 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
 258                                   uint32_t mask)
 259 {
 260         snb_update_pm_irq(dev_priv, mask, 0);
 261 }
 262
 263 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 264 {
 265         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 266                 return;
 267
 268         __gen6_disable_pm_irq(dev_priv, mask);
 269 }
 270
 271 void gen6_reset_rps_interrupts(struct drm_device *dev)
 272 {
 273         struct drm_i915_private *dev_priv = dev->dev_private;
 274         uint32_t reg = gen6_pm_iir(dev_priv);
 275
 276         spin_lock_irq(&dev_priv->irq_lock);
 277         I915_WRITE(reg, dev_priv->pm_rps_events);
 278         I915_WRITE(reg, dev_priv->pm_rps_events);
 279         POSTING_READ(reg);
 280         spin_unlock_irq(&dev_priv->irq_lock);
 281 }
 282
 283 void gen6_enable_rps_interrupts(struct drm_device *dev)
 284 {
 285         struct drm_i915_private *dev_priv = dev->dev_private;
 286
 287         spin_lock_irq(&dev_priv->irq_lock);
 288
 289         WARN_ON(dev_priv->rps.pm_iir);
 290         WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 291         dev_priv->rps.interrupts_enabled = true;
 292         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
 293                                 dev_priv->pm_rps_events);
 294         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 295
 296         spin_unlock_irq(&dev_priv->irq_lock);
 297 }
 298
 299 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 300 {
 301         /*
 302          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
 303          * if GEN6_PM_UP_EI_EXPIRED is masked.
 304          *
 305          * TODO: verify if this can be reproduced on VLV,CHV.
 306          */
 307         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
 308                 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
 309
 310         if (INTEL_INFO(dev_priv)->gen >= 8)
 311                 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
 312
 313         return mask;
 314 }
 315
 316 void gen6_disable_rps_interrupts(struct drm_device *dev)
 317 {
 318         struct drm_i915_private *dev_priv = dev->dev_private;
 319
 320         spin_lock_irq(&dev_priv->irq_lock);
 321         dev_priv->rps.interrupts_enabled = false;
 322         spin_unlock_irq(&dev_priv->irq_lock);
 323
 324         cancel_work_sync(&dev_priv->rps.work);
 325
 326         spin_lock_irq(&dev_priv->irq_lock);
 327
 328         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
 329
 330         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 331         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
 332                                 ~dev_priv->pm_rps_events);
 333         I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
 334         I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
 335
 336         dev_priv->rps.pm_iir = 0;
 337
 338         spin_unlock_irq(&dev_priv->irq_lock);
 339 }
 340
 341 /**
 342  * ibx_display_interrupt_update - update SDEIMR
 343  * @dev_priv: driver private
 344  * @interrupt_mask: mask of interrupt bits to update
 345  * @enabled_irq_mask: mask of interrupt bits to enable
 346  */
 347 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 348                                   uint32_t interrupt_mask,
 349                                   uint32_t enabled_irq_mask)
 350 {
 351         uint32_t sdeimr = I915_READ(SDEIMR);
 352         sdeimr &= ~interrupt_mask;
 353         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 354
 355         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 356
 357         assert_spin_locked(&dev_priv->irq_lock);
 358
 359         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 360                 return;
 361
 362         I915_WRITE(SDEIMR, sdeimr);
 363         POSTING_READ(SDEIMR);
 364 }
 365
 366 static void
 367 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 368                        u32 enable_mask, u32 status_mask)
 369 {
 370         u32 reg = PIPESTAT(pipe);
 371         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 372
 373         assert_spin_locked(&dev_priv->irq_lock);
 374         WARN_ON(!intel_irqs_enabled(dev_priv));
 375
 376         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 377                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 378                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 379                       pipe_name(pipe), enable_mask, status_mask))
 380                 return;
 381
 382         if ((pipestat & enable_mask) == enable_mask)
 383                 return;
 384
 385         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 386
 387         /* Enable the interrupt, clear any pending status */
 388         pipestat |= enable_mask | status_mask;
 389         I915_WRITE(reg, pipestat);
 390         POSTING_READ(reg);
 391 }
 392
 393 static void
 394 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 395                         u32 enable_mask, u32 status_mask)
 396 {
 397         u32 reg = PIPESTAT(pipe);
 398         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 399
 400         assert_spin_locked(&dev_priv->irq_lock);
 401         WARN_ON(!intel_irqs_enabled(dev_priv));
 402
 403         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 404                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 405                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 406                       pipe_name(pipe), enable_mask, status_mask))
 407                 return;
 408
 409         if ((pipestat & enable_mask) == 0)
 410                 return;
 411
 412         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 413
 414         pipestat &= ~enable_mask;
 415         I915_WRITE(reg, pipestat);
 416         POSTING_READ(reg);
 417 }
 418
 419 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 420 {
 421         u32 enable_mask = status_mask << 16;
 422
 423         /*
 424          * On pipe A we don't support the PSR interrupt yet,
 425          * on pipe B and C the same bit MBZ.
 426          */
 427         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 428                 return 0;
 429         /*
 430          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 431          * A the same bit is for perf counters which we don't use either.
 432          */
 433         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 434                 return 0;
 435
 436         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 437                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 438                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 439         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 440                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 441         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 442                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 443
 444         return enable_mask;
 445 }
 446
 447 void
 448 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 449                      u32 status_mask)
 450 {
 451         u32 enable_mask;
 452
 453         if (IS_VALLEYVIEW(dev_priv->dev))
 454                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 455                                                            status_mask);
 456         else
 457                 enable_mask = status_mask << 16;
 458         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 459 }
 460
 461 void
 462 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 463                       u32 status_mask)
 464 {
 465         u32 enable_mask;
 466
 467         if (IS_VALLEYVIEW(dev_priv->dev))
 468                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 469                                                            status_mask);
 470         else
 471                 enable_mask = status_mask << 16;
 472         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 473 }
 474
 475 /**
 476  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 477  */
 478 static void i915_enable_asle_pipestat(struct drm_device *dev)
 479 {
 480         struct drm_i915_private *dev_priv = dev->dev_private;
 481
 482         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 483                 return;
 484
 485         spin_lock_irq(&dev_priv->irq_lock);
 486
 487         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 488         if (INTEL_INFO(dev)->gen >= 4)
 489                 i915_enable_pipestat(dev_priv, PIPE_A,
 490                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 491
 492         spin_unlock_irq(&dev_priv->irq_lock);
 493 }
 494
 495 /*
 496  * This timing diagram depicts the video signal in and
 497  * around the vertical blanking period.
 498  *
 499  * Assumptions about the fictitious mode used in this example:
 500  *  vblank_start >= 3
 501  *  vsync_start = vblank_start + 1
 502  *  vsync_end = vblank_start + 2
 503  *  vtotal = vblank_start + 3
 504  *
 505  *           start of vblank:
 506  *           latch double buffered registers
 507  *           increment frame counter (ctg+)
 508  *           generate start of vblank interrupt (gen4+)
 509  *           |
 510  *           |          frame start:
 511  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 512  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 513  *           |          |
 514  *           |          |  start of vsync:
 515  *           |          |  generate vsync interrupt
 516  *           |          |  |
 517  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 518  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 519  * ----va---> <-----------------vb--------------------> <--------va-------------
 520  *       |          |       <----vs----->                     |
 521  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 522  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 523  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 524  *       |          |                                         |
 525  *       last visible pixel                                   first visible pixel
 526  *                  |                                         increment frame counter (gen3/4)
 527  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 528  *
 529  * x  = horizontal active
 530  * _  = horizontal blanking
 531  * hs = horizontal sync
 532  * va = vertical active
 533  * vb = vertical blanking
 534  * vs = vertical sync
 535  * vbs = vblank_start (number)
 536  *
 537  * Summary:
 538  * - most events happen at the start of horizontal sync
 539  * - frame start happens at the start of horizontal blank, 1-4 lines
 540  *   (depending on PIPECONF settings) after the start of vblank
 541  * - gen3/4 pixel and frame counter are synchronized with the start
 542  *   of horizontal active on the first line of vertical active
 543  */
 544
 545 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 546 {
 547         /* Gen2 doesn't have a hardware frame counter */
 548         return 0;
 549 }
 550
 551 /* Called from drm generic code, passed a 'crtc', which
 552  * we use as a pipe index
 553  */
 554 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 555 {
 556         struct drm_i915_private *dev_priv = dev->dev_private;
 557         unsigned long high_frame;
 558         unsigned long low_frame;
 559         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 560
 561         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 562                 struct intel_crtc *intel_crtc =
 563                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 564                 const struct drm_display_mode *mode =
 565                         &intel_crtc->config->base.adjusted_mode;
 566
 567                 htotal = mode->crtc_htotal;
 568                 hsync_start = mode->crtc_hsync_start;
 569                 vbl_start = mode->crtc_vblank_start;
 570                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 571                         vbl_start = DIV_ROUND_UP(vbl_start, 2);
 572         } else {
 573                 enum transcoder cpu_transcoder = (enum transcoder) pipe;
 574
 575                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
 576                 hsync_start = (I915_READ(HSYNC(cpu_transcoder))  & 0x1fff) + 1;
 577                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
 578                 if ((I915_READ(PIPECONF(cpu_transcoder)) &
 579                      PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
 580                         vbl_start = DIV_ROUND_UP(vbl_start, 2);
 581         }
 582
 583         /* Convert to pixel count */
 584         vbl_start *= htotal;
 585
 586         /* Start of vblank event occurs at start of hsync */
 587         vbl_start -= htotal - hsync_start;
 588
 589         high_frame = PIPEFRAME(pipe);
 590         low_frame = PIPEFRAMEPIXEL(pipe);
 591
 592         /*
 593          * High & low register fields aren't synchronized, so make sure
 594          * we get a low value that's stable across two reads of the high
 595          * register.
 596          */
 597         do {
 598                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 599                 low   = I915_READ(low_frame);
 600                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 601         } while (high1 != high2);
 602
 603         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 604         pixel = low & PIPE_PIXEL_MASK;
 605         low >>= PIPE_FRAME_LOW_SHIFT;
 606
 607         /*
 608          * The frame counter increments at beginning of active.
 609          * Cook up a vblank counter by also checking the pixel
 610          * counter against vblank start.
 611          */
 612         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 613 }
 614
 615 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 616 {
 617         struct drm_i915_private *dev_priv = dev->dev_private;
 618         int reg = PIPE_FRMCOUNT_GM45(pipe);
 619
 620         return I915_READ(reg);
 621 }
 622
 623 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 624 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 625
 626 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 627 {
 628         struct drm_device *dev = crtc->base.dev;
 629         struct drm_i915_private *dev_priv = dev->dev_private;
 630         const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
 631         enum pipe pipe = crtc->pipe;
 632         int position, vtotal;
 633
 634         vtotal = mode->crtc_vtotal;
 635         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 636                 vtotal /= 2;
 637
 638         if (IS_GEN2(dev))
 639                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 640         else
 641                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 642
 643         /*
 644          * See update_scanline_offset() for the details on the
 645          * scanline_offset adjustment.
 646          */
 647         return (position + crtc->scanline_offset) % vtotal;
 648 }
 649
 650 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 651                                     unsigned int flags, int *vpos, int *hpos,
 652                                     ktime_t *stime, ktime_t *etime)
 653 {
 654         struct drm_i915_private *dev_priv = dev->dev_private;
 655         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 657         const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
 658         int position;
 659         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 660         bool in_vbl = true;
 661         int ret = 0;
 662         unsigned long irqflags;
 663
 664         if (!intel_crtc->active) {
 665                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 666                                  "pipe %c\n", pipe_name(pipe));
 667                 return 0;
 668         }
 669
 670         htotal = mode->crtc_htotal;
 671         hsync_start = mode->crtc_hsync_start;
 672         vtotal = mode->crtc_vtotal;
 673         vbl_start = mode->crtc_vblank_start;
 674         vbl_end = mode->crtc_vblank_end;
 675
 676         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 677                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 678                 vbl_end /= 2;
 679                 vtotal /= 2;
 680         }
 681
 682         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 683
 684         /*
 685          * Lock uncore.lock, as we will do multiple timing critical raw
 686          * register reads, potentially with preemption disabled, so the
 687          * following code must not block on uncore.lock.
 688          */
 689         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 690
 691         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 692
 693         /* Get optional system timestamp before query. */
 694         if (stime)
 695                 *stime = ktime_get();
 696
 697         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 698                 /* No obvious pixelcount register. Only query vertical
 699                  * scanout position from Display scan line register.
 700                  */
 701                 position = __intel_get_crtc_scanline(intel_crtc);
 702         } else {
 703                 /* Have access to pixelcount since start of frame.
 704                  * We can split this into vertical and horizontal
 705                  * scanout position.
 706                  */
 707                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 708
 709                 /* convert to pixel counts */
 710                 vbl_start *= htotal;
 711                 vbl_end *= htotal;
 712                 vtotal *= htotal;
 713
 714                 /*
 715                  * In interlaced modes, the pixel counter counts all pixels,
 716                  * so one field will have htotal more pixels. In order to avoid
 717                  * the reported position from jumping backwards when the pixel
 718                  * counter is beyond the length of the shorter field, just
 719                  * clamp the position the length of the shorter field. This
 720                  * matches how the scanline counter based position works since
 721                  * the scanline counter doesn't count the two half lines.
 722                  */
 723                 if (position >= vtotal)
 724                         position = vtotal - 1;
 725
 726                 /*
 727                  * Start of vblank interrupt is triggered at start of hsync,
 728                  * just prior to the first active line of vblank. However we
 729                  * consider lines to start at the leading edge of horizontal
 730                  * active. So, should we get here before we've crossed into
 731                  * the horizontal active of the first line in vblank, we would
 732                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 733                  * always add htotal-hsync_start to the current pixel position.
 734                  */
 735                 position = (position + htotal - hsync_start) % vtotal;
 736         }
 737
 738         /* Get optional system timestamp after query. */
 739         if (etime)
 740                 *etime = ktime_get();
 741
 742         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 743
 744         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 745
 746         in_vbl = position >= vbl_start && position < vbl_end;
 747
 748         /*
 749          * While in vblank, position will be negative
 750          * counting up towards 0 at vbl_end. And outside
 751          * vblank, position will be positive counting
 752          * up since vbl_end.
 753          */
 754         if (position >= vbl_start)
 755                 position -= vbl_end;
 756         else
 757                 position += vtotal - vbl_end;
 758
 759         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 760                 *vpos = position;
 761                 *hpos = 0;
 762         } else {
 763                 *vpos = position / htotal;
 764                 *hpos = position - (*vpos * htotal);
 765         }
 766
 767         /* In vblank? */
 768         if (in_vbl)
 769                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 770
 771         return ret;
 772 }
 773
 774 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 775 {
 776         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 777         unsigned long irqflags;
 778         int position;
 779
 780         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 781         position = __intel_get_crtc_scanline(crtc);
 782         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 783
 784         return position;
 785 }
 786
 787 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 788                               int *max_error,
 789                               struct timeval *vblank_time,
 790                               unsigned flags)
 791 {
 792         struct drm_crtc *crtc;
 793
 794         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 795                 DRM_ERROR("Invalid crtc %d\n", pipe);
 796                 return -EINVAL;
 797         }
 798
 799         /* Get drm_crtc to timestamp: */
 800         crtc = intel_get_crtc_for_pipe(dev, pipe);
 801         if (crtc == NULL) {
 802                 DRM_ERROR("Invalid crtc %d\n", pipe);
 803                 return -EINVAL;
 804         }
 805
 806         if (!crtc->enabled) {
 807                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 808                 return -EBUSY;
 809         }
 810
 811         /* Helper routine in DRM core does all the work: */
 812         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 813                                                      vblank_time, flags,
 814                                                      crtc,
 815                                                      &to_intel_crtc(crtc)->config->base.adjusted_mode);
 816 }
 817
 818 static bool intel_hpd_irq_event(struct drm_device *dev,
 819                                 struct drm_connector *connector)
 820 {
 821         enum drm_connector_status old_status;
 822
 823         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 824         old_status = connector->status;
 825
 826         connector->status = connector->funcs->detect(connector, false);
 827         if (old_status == connector->status)
 828                 return false;
 829
 830         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 831                       connector->base.id,
 832                       connector->name,
 833                       drm_get_connector_status_name(old_status),
 834                       drm_get_connector_status_name(connector->status));
 835
 836         return true;
 837 }
 838
 839 static void i915_digport_work_func(struct work_struct *work)
 840 {
 841         struct drm_i915_private *dev_priv =
 842                 container_of(work, struct drm_i915_private, dig_port_work);
 843         u32 long_port_mask, short_port_mask;
 844         struct intel_digital_port *intel_dig_port;
 845         int i;
 846         u32 old_bits = 0;
 847
 848         spin_lock_irq(&dev_priv->irq_lock);
 849         long_port_mask = dev_priv->long_hpd_port_mask;
 850         dev_priv->long_hpd_port_mask = 0;
 851         short_port_mask = dev_priv->short_hpd_port_mask;
 852         dev_priv->short_hpd_port_mask = 0;
 853         spin_unlock_irq(&dev_priv->irq_lock);
 854
 855         for (i = 0; i < I915_MAX_PORTS; i++) {
 856                 bool valid = false;
 857                 bool long_hpd = false;
 858                 intel_dig_port = dev_priv->hpd_irq_port[i];
 859                 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
 860                         continue;
 861
 862                 if (long_port_mask & (1 << i))  {
 863                         valid = true;
 864                         long_hpd = true;
 865                 } else if (short_port_mask & (1 << i))
 866                         valid = true;
 867
 868                 if (valid) {
 869                         enum irqreturn ret;
 870
 871                         ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
 872                         if (ret == IRQ_NONE) {
 873                                 /* fall back to old school hpd */
 874                                 old_bits |= (1 << intel_dig_port->base.hpd_pin);
 875                         }
 876                 }
 877         }
 878
 879         if (old_bits) {
 880                 spin_lock_irq(&dev_priv->irq_lock);
 881                 dev_priv->hpd_event_bits |= old_bits;
 882                 spin_unlock_irq(&dev_priv->irq_lock);
 883                 schedule_work(&dev_priv->hotplug_work);
 884         }
 885 }
 886
 887 /*
 888  * Handle hotplug events outside the interrupt handler proper.
 889  */
 890 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 891
 892 static void i915_hotplug_work_func(struct work_struct *work)
 893 {
 894         struct drm_i915_private *dev_priv =
 895                 container_of(work, struct drm_i915_private, hotplug_work);
 896         struct drm_device *dev = dev_priv->dev;
 897         struct drm_mode_config *mode_config = &dev->mode_config;
 898         struct intel_connector *intel_connector;
 899         struct intel_encoder *intel_encoder;
 900         struct drm_connector *connector;
 901         bool hpd_disabled = false;
 902         bool changed = false;
 903         u32 hpd_event_bits;
 904
 905         mutex_lock(&mode_config->mutex);
 906         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 907
 908         spin_lock_irq(&dev_priv->irq_lock);
 909
 910         hpd_event_bits = dev_priv->hpd_event_bits;
 911         dev_priv->hpd_event_bits = 0;
 912         list_for_each_entry(connector, &mode_config->connector_list, head) {
 913                 intel_connector = to_intel_connector(connector);
 914                 if (!intel_connector->encoder)
 915                         continue;
 916                 intel_encoder = intel_connector->encoder;
 917                 if (intel_encoder->hpd_pin > HPD_NONE &&
 918                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 919                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 920                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 921                                  "switching from hotplug detection to polling\n",
 922                                 connector->name);
 923                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 924                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 925                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 926                         hpd_disabled = true;
 927                 }
 928                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 929                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 930                                       connector->name, intel_encoder->hpd_pin);
 931                 }
 932         }
 933          /* if there were no outputs to poll, poll was disabled,
 934           * therefore make sure it's enabled when disabling HPD on
 935           * some connectors */
 936         if (hpd_disabled) {
 937                 drm_kms_helper_poll_enable(dev);
 938                 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
 939                                  msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 940         }
 941
 942         spin_unlock_irq(&dev_priv->irq_lock);
 943
 944         list_for_each_entry(connector, &mode_config->connector_list, head) {
 945                 intel_connector = to_intel_connector(connector);
 946                 if (!intel_connector->encoder)
 947                         continue;
 948                 intel_encoder = intel_connector->encoder;
 949                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 950                         if (intel_encoder->hot_plug)
 951                                 intel_encoder->hot_plug(intel_encoder);
 952                         if (intel_hpd_irq_event(dev, connector))
 953                                 changed = true;
 954                 }
 955         }
 956         mutex_unlock(&mode_config->mutex);
 957
 958         if (changed)
 959                 drm_kms_helper_hotplug_event(dev);
 960 }
 961
 962 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 963 {
 964         struct drm_i915_private *dev_priv = dev->dev_private;
 965         u32 busy_up, busy_down, max_avg, min_avg;
 966         u8 new_delay;
 967
 968         spin_lock(&mchdev_lock);
 969
 970         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 971
 972         new_delay = dev_priv->ips.cur_delay;
 973
 974         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 975         busy_up = I915_READ(RCPREVBSYTUPAVG);
 976         busy_down = I915_READ(RCPREVBSYTDNAVG);
 977         max_avg = I915_READ(RCBMAXAVG);
 978         min_avg = I915_READ(RCBMINAVG);
 979
 980         /* Handle RCS change request from hw */
 981         if (busy_up > max_avg) {
 982                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 983                         new_delay = dev_priv->ips.cur_delay - 1;
 984                 if (new_delay < dev_priv->ips.max_delay)
 985                         new_delay = dev_priv->ips.max_delay;
 986         } else if (busy_down < min_avg) {
 987                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 988                         new_delay = dev_priv->ips.cur_delay + 1;
 989                 if (new_delay > dev_priv->ips.min_delay)
 990                         new_delay = dev_priv->ips.min_delay;
 991         }
 992
 993         if (ironlake_set_drps(dev, new_delay))
 994                 dev_priv->ips.cur_delay = new_delay;
 995
 996         spin_unlock(&mchdev_lock);
 997
 998         return;
 999 }
1000
1001 static void notify_ring(struct drm_device *dev,
1002                         struct intel_engine_cs *ring)
1003 {
1004         if (!intel_ring_initialized(ring))
1005                 return;
1006
1007         trace_i915_gem_request_notify(ring);
1008
1009         wake_up_all(&ring->irq_queue);
1010 }
1011
1012 static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
1013                             struct intel_rps_ei *rps_ei)
1014 {
1015         u32 cz_ts, cz_freq_khz;
1016         u32 render_count, media_count;
1017         u32 elapsed_render, elapsed_media, elapsed_time;
1018         u32 residency = 0;
1019
1020         cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1021         cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
1022
1023         render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1024         media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1025
1026         if (rps_ei->cz_clock == 0) {
1027                 rps_ei->cz_clock = cz_ts;
1028                 rps_ei->render_c0 = render_count;
1029                 rps_ei->media_c0 = media_count;
1030
1031                 return dev_priv->rps.cur_freq;
1032         }
1033
1034         elapsed_time = cz_ts - rps_ei->cz_clock;
1035         rps_ei->cz_clock = cz_ts;
1036
1037         elapsed_render = render_count - rps_ei->render_c0;
1038         rps_ei->render_c0 = render_count;
1039
1040         elapsed_media = media_count - rps_ei->media_c0;
1041         rps_ei->media_c0 = media_count;
1042
1043         /* Convert all the counters into common unit of milli sec */
1044         elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1045         elapsed_render /=  cz_freq_khz;
1046         elapsed_media /= cz_freq_khz;
1047
1048         /*
1049          * Calculate overall C0 residency percentage
1050          * only if elapsed time is non zero
1051          */
1052         if (elapsed_time) {
1053                 residency =
1054                         ((max(elapsed_render, elapsed_media) * 100)
1055                                 / elapsed_time);
1056         }
1057
1058         return residency;
1059 }
1060
1061 /**
1062  * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1063  * busy-ness calculated from C0 counters of render & media power wells
1064  * @dev_priv: DRM device private
1065  *
1066  */
1067 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1068 {
1069         u32 residency_C0_up = 0, residency_C0_down = 0;
1070         int new_delay, adj;
1071
1072         dev_priv->rps.ei_interrupt_count++;
1073
1074         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1075
1076
1077         if (dev_priv->rps.up_ei.cz_clock == 0) {
1078                 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1079                 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1080                 return dev_priv->rps.cur_freq;
1081         }
1082
1083
1084         /*
1085          * To down throttle, C0 residency should be less than down threshold
1086          * for continous EI intervals. So calculate down EI counters
1087          * once in VLV_INT_COUNT_FOR_DOWN_EI
1088          */
1089         if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1090
1091                 dev_priv->rps.ei_interrupt_count = 0;
1092
1093                 residency_C0_down = vlv_c0_residency(dev_priv,
1094                                                      &dev_priv->rps.down_ei);
1095         } else {
1096                 residency_C0_up = vlv_c0_residency(dev_priv,
1097                                                    &dev_priv->rps.up_ei);
1098         }
1099
1100         new_delay = dev_priv->rps.cur_freq;
1101
1102         adj = dev_priv->rps.last_adj;
1103         /* C0 residency is greater than UP threshold. Increase Frequency */
1104         if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1105                 if (adj > 0)
1106                         adj *= 2;
1107                 else
1108                         adj = 1;
1109
1110                 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1111                         new_delay = dev_priv->rps.cur_freq + adj;
1112
1113                 /*
1114                  * For better performance, jump directly
1115                  * to RPe if we're below it.
1116                  */
1117                 if (new_delay < dev_priv->rps.efficient_freq)
1118                         new_delay = dev_priv->rps.efficient_freq;
1119
1120         } else if (!dev_priv->rps.ei_interrupt_count &&
1121                         (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1122                 if (adj < 0)
1123                         adj *= 2;
1124                 else
1125                         adj = -1;
1126                 /*
1127                  * This means, C0 residency is less than down threshold over
1128                  * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1129                  */
1130                 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1131                         new_delay = dev_priv->rps.cur_freq + adj;
1132         }
1133
1134         return new_delay;
1135 }
1136
1137 static void gen6_pm_rps_work(struct work_struct *work)
1138 {
1139         struct drm_i915_private *dev_priv =
1140                 container_of(work, struct drm_i915_private, rps.work);
1141         u32 pm_iir;
1142         int new_delay, adj;
1143
1144         spin_lock_irq(&dev_priv->irq_lock);
1145         /* Speed up work cancelation during disabling rps interrupts. */
1146         if (!dev_priv->rps.interrupts_enabled) {
1147                 spin_unlock_irq(&dev_priv->irq_lock);
1148                 return;
1149         }
1150         pm_iir = dev_priv->rps.pm_iir;
1151         dev_priv->rps.pm_iir = 0;
1152         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1153         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1154         spin_unlock_irq(&dev_priv->irq_lock);
1155
1156         /* Make sure we didn't queue anything we're not going to process. */
1157         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1158
1159         if ((pm_iir & dev_priv->pm_rps_events) == 0)
1160                 return;
1161
1162         mutex_lock(&dev_priv->rps.hw_lock);
1163
1164         adj = dev_priv->rps.last_adj;
1165         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1166                 if (adj > 0)
1167                         adj *= 2;
1168                 else {
1169                         /* CHV needs even encode values */
1170                         adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1171                 }
1172                 new_delay = dev_priv->rps.cur_freq + adj;
1173
1174                 /*
1175                  * For better performance, jump directly
1176                  * to RPe if we're below it.
1177                  */
1178                 if (new_delay < dev_priv->rps.efficient_freq)
1179                         new_delay = dev_priv->rps.efficient_freq;
1180         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1181                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1182                         new_delay = dev_priv->rps.efficient_freq;
1183                 else
1184                         new_delay = dev_priv->rps.min_freq_softlimit;
1185                 adj = 0;
1186         } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1187                 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1188         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1189                 if (adj < 0)
1190                         adj *= 2;
1191                 else {
1192                         /* CHV needs even encode values */
1193                         adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1194                 }
1195                 new_delay = dev_priv->rps.cur_freq + adj;
1196         } else { /* unknown event */
1197                 new_delay = dev_priv->rps.cur_freq;
1198         }
1199
1200         /* sysfs frequency interfaces may have snuck in while servicing the
1201          * interrupt
1202          */
1203         new_delay = clamp_t(int, new_delay,
1204                             dev_priv->rps.min_freq_softlimit,
1205                             dev_priv->rps.max_freq_softlimit);
1206
1207         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1208
1209         intel_set_rps(dev_priv->dev, new_delay);
1210
1211         mutex_unlock(&dev_priv->rps.hw_lock);
1212 }
1213
1214
1215 /**
1216  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1217  * occurred.
1218  * @work: workqueue struct
1219  *
1220  * Doesn't actually do anything except notify userspace. As a consequence of
1221  * this event, userspace should try to remap the bad rows since statistically
1222  * it is likely the same row is more likely to go bad again.
1223  */
1224 static void ivybridge_parity_work(struct work_struct *work)
1225 {
1226         struct drm_i915_private *dev_priv =
1227                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1228         u32 error_status, row, bank, subbank;
1229         char *parity_event[6];
1230         uint32_t misccpctl;
1231         uint8_t slice = 0;
1232
1233         /* We must turn off DOP level clock gating to access the L3 registers.
1234          * In order to prevent a get/put style interface, acquire struct mutex
1235          * any time we access those registers.
1236          */
1237         mutex_lock(&dev_priv->dev->struct_mutex);
1238
1239         /* If we've screwed up tracking, just let the interrupt fire again */
1240         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1241                 goto out;
1242
1243         misccpctl = I915_READ(GEN7_MISCCPCTL);
1244         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1245         POSTING_READ(GEN7_MISCCPCTL);
1246
1247         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1248                 u32 reg;
1249
1250                 slice--;
1251                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1252                         break;
1253
1254                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1255
1256                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1257
1258                 error_status = I915_READ(reg);
1259                 row = GEN7_PARITY_ERROR_ROW(error_status);
1260                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1261                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1262
1263                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1264                 POSTING_READ(reg);
1265
1266                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1267                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1268                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1269                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1270                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1271                 parity_event[5] = NULL;
1272
1273                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1274                                    KOBJ_CHANGE, parity_event);
1275
1276                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1277                           slice, row, bank, subbank);
1278
1279                 kfree(parity_event[4]);
1280                 kfree(parity_event[3]);
1281                 kfree(parity_event[2]);
1282                 kfree(parity_event[1]);
1283         }
1284
1285         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1286
1287 out:
1288         WARN_ON(dev_priv->l3_parity.which_slice);
1289         spin_lock_irq(&dev_priv->irq_lock);
1290         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1291         spin_unlock_irq(&dev_priv->irq_lock);
1292
1293         mutex_unlock(&dev_priv->dev->struct_mutex);
1294 }
1295
1296 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1297 {
1298         struct drm_i915_private *dev_priv = dev->dev_private;
1299
1300         if (!HAS_L3_DPF(dev))
1301                 return;
1302
1303         spin_lock(&dev_priv->irq_lock);
1304         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1305         spin_unlock(&dev_priv->irq_lock);
1306
1307         iir &= GT_PARITY_ERROR(dev);
1308         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1309                 dev_priv->l3_parity.which_slice |= 1 << 1;
1310
1311         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1312                 dev_priv->l3_parity.which_slice |= 1 << 0;
1313
1314         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1315 }
1316
1317 static void ilk_gt_irq_handler(struct drm_device *dev,
1318                                struct drm_i915_private *dev_priv,
1319                                u32 gt_iir)
1320 {
1321         if (gt_iir &
1322             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1323                 notify_ring(dev, &dev_priv->ring[RCS]);
1324         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1325                 notify_ring(dev, &dev_priv->ring[VCS]);
1326 }
1327
1328 static void snb_gt_irq_handler(struct drm_device *dev,
1329                                struct drm_i915_private *dev_priv,
1330                                u32 gt_iir)
1331 {
1332
1333         if (gt_iir &
1334             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1335                 notify_ring(dev, &dev_priv->ring[RCS]);
1336         if (gt_iir & GT_BSD_USER_INTERRUPT)
1337                 notify_ring(dev, &dev_priv->ring[VCS]);
1338         if (gt_iir & GT_BLT_USER_INTERRUPT)
1339                 notify_ring(dev, &dev_priv->ring[BCS]);
1340
1341         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1342                       GT_BSD_CS_ERROR_INTERRUPT |
1343                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1344                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1345
1346         if (gt_iir & GT_PARITY_ERROR(dev))
1347                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1348 }
1349
1350 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1351                                        struct drm_i915_private *dev_priv,
1352                                        u32 master_ctl)
1353 {
1354         struct intel_engine_cs *ring;
1355         u32 rcs, bcs, vcs;
1356         uint32_t tmp = 0;
1357         irqreturn_t ret = IRQ_NONE;
1358
1359         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1360                 tmp = I915_READ(GEN8_GT_IIR(0));
1361                 if (tmp) {
1362                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1363                         ret = IRQ_HANDLED;
1364
1365                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1366                         ring = &dev_priv->ring[RCS];
1367                         if (rcs & GT_RENDER_USER_INTERRUPT)
1368                                 notify_ring(dev, ring);
1369                         if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1370                                 intel_lrc_irq_handler(ring);
1371
1372                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1373                         ring = &dev_priv->ring[BCS];
1374                         if (bcs & GT_RENDER_USER_INTERRUPT)
1375                                 notify_ring(dev, ring);
1376                         if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1377                                 intel_lrc_irq_handler(ring);
1378                 } else
1379                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1380         }
1381
1382         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1383                 tmp = I915_READ(GEN8_GT_IIR(1));
1384                 if (tmp) {
1385                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1386                         ret = IRQ_HANDLED;
1387
1388                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1389                         ring = &dev_priv->ring[VCS];
1390                         if (vcs & GT_RENDER_USER_INTERRUPT)
1391                                 notify_ring(dev, ring);
1392                         if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1393                                 intel_lrc_irq_handler(ring);
1394
1395                         vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1396                         ring = &dev_priv->ring[VCS2];
1397                         if (vcs & GT_RENDER_USER_INTERRUPT)
1398                                 notify_ring(dev, ring);
1399                         if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1400                                 intel_lrc_irq_handler(ring);
1401                 } else
1402                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1403         }
1404
1405         if (master_ctl & GEN8_GT_PM_IRQ) {
1406                 tmp = I915_READ(GEN8_GT_IIR(2));
1407                 if (tmp & dev_priv->pm_rps_events) {
1408                         I915_WRITE(GEN8_GT_IIR(2),
1409                                    tmp & dev_priv->pm_rps_events);
1410                         ret = IRQ_HANDLED;
1411                         gen6_rps_irq_handler(dev_priv, tmp);
1412                 } else
1413                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1414         }
1415
1416         if (master_ctl & GEN8_GT_VECS_IRQ) {
1417                 tmp = I915_READ(GEN8_GT_IIR(3));
1418                 if (tmp) {
1419                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1420                         ret = IRQ_HANDLED;
1421
1422                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1423                         ring = &dev_priv->ring[VECS];
1424                         if (vcs & GT_RENDER_USER_INTERRUPT)
1425                                 notify_ring(dev, ring);
1426                         if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1427                                 intel_lrc_irq_handler(ring);
1428                 } else
1429                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1430         }
1431
1432         return ret;
1433 }
1434
1435 #define HPD_STORM_DETECT_PERIOD 1000
1436 #define HPD_STORM_THRESHOLD 5
1437
1438 static int pch_port_to_hotplug_shift(enum port port)
1439 {
1440         switch (port) {
1441         case PORT_A:
1442         case PORT_E:
1443         default:
1444                 return -1;
1445         case PORT_B:
1446                 return 0;
1447         case PORT_C:
1448                 return 8;
1449         case PORT_D:
1450                 return 16;
1451         }
1452 }
1453
1454 static int i915_port_to_hotplug_shift(enum port port)
1455 {
1456         switch (port) {
1457         case PORT_A:
1458         case PORT_E:
1459         default:
1460                 return -1;
1461         case PORT_B:
1462                 return 17;
1463         case PORT_C:
1464                 return 19;
1465         case PORT_D:
1466                 return 21;
1467         }
1468 }
1469
1470 static inline enum port get_port_from_pin(enum hpd_pin pin)
1471 {
1472         switch (pin) {
1473         case HPD_PORT_B:
1474                 return PORT_B;
1475         case HPD_PORT_C:
1476                 return PORT_C;
1477         case HPD_PORT_D:
1478                 return PORT_D;
1479         default:
1480                 return PORT_A; /* no hpd */
1481         }
1482 }
1483
1484 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1485                                          u32 hotplug_trigger,
1486                                          u32 dig_hotplug_reg,
1487                                          const u32 hpd[HPD_NUM_PINS])
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490         int i;
1491         enum port port;
1492         bool storm_detected = false;
1493         bool queue_dig = false, queue_hp = false;
1494         u32 dig_shift;
1495         u32 dig_port_mask = 0;
1496
1497         if (!hotplug_trigger)
1498                 return;
1499
1500         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1501                          hotplug_trigger, dig_hotplug_reg);
1502
1503         spin_lock(&dev_priv->irq_lock);
1504         for (i = 1; i < HPD_NUM_PINS; i++) {
1505                 if (!(hpd[i] & hotplug_trigger))
1506                         continue;
1507
1508                 port = get_port_from_pin(i);
1509                 if (port && dev_priv->hpd_irq_port[port]) {
1510                         bool long_hpd;
1511
1512                         if (HAS_PCH_SPLIT(dev)) {
1513                                 dig_shift = pch_port_to_hotplug_shift(port);
1514                                 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1515                         } else {
1516                                 dig_shift = i915_port_to_hotplug_shift(port);
1517                                 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1518                         }
1519
1520                         DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1521                                          port_name(port),
1522                                          long_hpd ? "long" : "short");
1523                         /* for long HPD pulses we want to have the digital queue happen,
1524                            but we still want HPD storm detection to function. */
1525                         if (long_hpd) {
1526                                 dev_priv->long_hpd_port_mask |= (1 << port);
1527                                 dig_port_mask |= hpd[i];
1528                         } else {
1529                                 /* for short HPD just trigger the digital queue */
1530                                 dev_priv->short_hpd_port_mask |= (1 << port);
1531                                 hotplug_trigger &= ~hpd[i];
1532                         }
1533                         queue_dig = true;
1534                 }
1535         }
1536
1537         for (i = 1; i < HPD_NUM_PINS; i++) {
1538                 if (hpd[i] & hotplug_trigger &&
1539                     dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1540                         /*
1541                          * On GMCH platforms the interrupt mask bits only
1542                          * prevent irq generation, not the setting of the
1543                          * hotplug bits itself. So only WARN about unexpected
1544                          * interrupts on saner platforms.
1545                          */
1546                         WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1547                                   "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1548                                   hotplug_trigger, i, hpd[i]);
1549
1550                         continue;
1551                 }
1552
1553                 if (!(hpd[i] & hotplug_trigger) ||
1554                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1555                         continue;
1556
1557                 if (!(dig_port_mask & hpd[i])) {
1558                         dev_priv->hpd_event_bits |= (1 << i);
1559                         queue_hp = true;
1560                 }
1561
1562                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1563                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1564                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1565                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1566                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1567                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1568                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1569                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1570                         dev_priv->hpd_event_bits &= ~(1 << i);
1571                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1572                         storm_detected = true;
1573                 } else {
1574                         dev_priv->hpd_stats[i].hpd_cnt++;
1575                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1576                                       dev_priv->hpd_stats[i].hpd_cnt);
1577                 }
1578         }
1579
1580         if (storm_detected)
1581                 dev_priv->display.hpd_irq_setup(dev);
1582         spin_unlock(&dev_priv->irq_lock);
1583
1584         /*
1585          * Our hotplug handler can grab modeset locks (by calling down into the
1586          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1587          * queue for otherwise the flush_work in the pageflip code will
1588          * deadlock.
1589          */
1590         if (queue_dig)
1591                 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1592         if (queue_hp)
1593                 schedule_work(&dev_priv->hotplug_work);
1594 }
1595
1596 static void gmbus_irq_handler(struct drm_device *dev)
1597 {
1598         struct drm_i915_private *dev_priv = dev->dev_private;
1599
1600         wake_up_all(&dev_priv->gmbus_wait_queue);
1601 }
1602
1603 static void dp_aux_irq_handler(struct drm_device *dev)
1604 {
1605         struct drm_i915_private *dev_priv = dev->dev_private;
1606
1607         wake_up_all(&dev_priv->gmbus_wait_queue);
1608 }
1609
1610 #if defined(CONFIG_DEBUG_FS)
1611 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1612                                          uint32_t crc0, uint32_t crc1,
1613                                          uint32_t crc2, uint32_t crc3,
1614                                          uint32_t crc4)
1615 {
1616         struct drm_i915_private *dev_priv = dev->dev_private;
1617         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1618         struct intel_pipe_crc_entry *entry;
1619         int head, tail;
1620
1621         spin_lock(&pipe_crc->lock);
1622
1623         if (!pipe_crc->entries) {
1624                 spin_unlock(&pipe_crc->lock);
1625                 DRM_DEBUG_KMS("spurious interrupt\n");
1626                 return;
1627         }
1628
1629         head = pipe_crc->head;
1630         tail = pipe_crc->tail;
1631
1632         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1633                 spin_unlock(&pipe_crc->lock);
1634                 DRM_ERROR("CRC buffer overflowing\n");
1635                 return;
1636         }
1637
1638         entry = &pipe_crc->entries[head];
1639
1640         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1641         entry->crc[0] = crc0;
1642         entry->crc[1] = crc1;
1643         entry->crc[2] = crc2;
1644         entry->crc[3] = crc3;
1645         entry->crc[4] = crc4;
1646
1647         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1648         pipe_crc->head = head;
1649
1650         spin_unlock(&pipe_crc->lock);
1651
1652         wake_up_interruptible(&pipe_crc->wq);
1653 }
1654 #else
1655 static inline void
1656 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1657                              uint32_t crc0, uint32_t crc1,
1658                              uint32_t crc2, uint32_t crc3,
1659                              uint32_t crc4) {}
1660 #endif
1661
1662
1663 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1664 {
1665         struct drm_i915_private *dev_priv = dev->dev_private;
1666
1667         display_pipe_crc_irq_handler(dev, pipe,
1668                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1669                                      0, 0, 0, 0);
1670 }
1671
1672 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1673 {
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675
1676         display_pipe_crc_irq_handler(dev, pipe,
1677                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1678                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1679                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1680                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1681                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1682 }
1683
1684 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1685 {
1686         struct drm_i915_private *dev_priv = dev->dev_private;
1687         uint32_t res1, res2;
1688
1689         if (INTEL_INFO(dev)->gen >= 3)
1690                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1691         else
1692                 res1 = 0;
1693
1694         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1695                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1696         else
1697                 res2 = 0;
1698
1699         display_pipe_crc_irq_handler(dev, pipe,
1700                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1701                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1702                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1703                                      res1, res2);
1704 }
1705
1706 /* The RPS events need forcewake, so we add them to a work queue and mask their
1707  * IMR bits until the work is done. Other interrupts can be processed without
1708  * the work queue. */
1709 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1710 {
1711         /* TODO: RPS on GEN9+ is not supported yet. */
1712         if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
1713                       "GEN9+: unexpected RPS IRQ\n"))
1714                 return;
1715
1716         if (pm_iir & dev_priv->pm_rps_events) {
1717                 spin_lock(&dev_priv->irq_lock);
1718                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1719                 if (dev_priv->rps.interrupts_enabled) {
1720                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1721                         queue_work(dev_priv->wq, &dev_priv->rps.work);
1722                 }
1723                 spin_unlock(&dev_priv->irq_lock);
1724         }
1725
1726         if (INTEL_INFO(dev_priv)->gen >= 8)
1727                 return;
1728
1729         if (HAS_VEBOX(dev_priv->dev)) {
1730                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1731                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1732
1733                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1734                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1735         }
1736 }
1737
1738 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1739 {
1740         if (!drm_handle_vblank(dev, pipe))
1741                 return false;
1742
1743         return true;
1744 }
1745
1746 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1747 {
1748         struct drm_i915_private *dev_priv = dev->dev_private;
1749         u32 pipe_stats[I915_MAX_PIPES] = { };
1750         int pipe;
1751
1752         spin_lock(&dev_priv->irq_lock);
1753         for_each_pipe(dev_priv, pipe) {
1754                 int reg;
1755                 u32 mask, iir_bit = 0;
1756
1757                 /*
1758                  * PIPESTAT bits get signalled even when the interrupt is
1759                  * disabled with the mask bits, and some of the status bits do
1760                  * not generate interrupts at all (like the underrun bit). Hence
1761                  * we need to be careful that we only handle what we want to
1762                  * handle.
1763                  */
1764
1765                 /* fifo underruns are filterered in the underrun handler. */
1766                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1767
1768                 switch (pipe) {
1769                 case PIPE_A:
1770                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1771                         break;
1772                 case PIPE_B:
1773                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1774                         break;
1775                 case PIPE_C:
1776                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1777                         break;
1778                 }
1779                 if (iir & iir_bit)
1780                         mask |= dev_priv->pipestat_irq_mask[pipe];
1781
1782                 if (!mask)
1783                         continue;
1784
1785                 reg = PIPESTAT(pipe);
1786                 mask |= PIPESTAT_INT_ENABLE_MASK;
1787                 pipe_stats[pipe] = I915_READ(reg) & mask;
1788
1789                 /*
1790                  * Clear the PIPE*STAT regs before the IIR
1791                  */
1792                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1793                                         PIPESTAT_INT_STATUS_MASK))
1794                         I915_WRITE(reg, pipe_stats[pipe]);
1795         }
1796         spin_unlock(&dev_priv->irq_lock);
1797
1798         for_each_pipe(dev_priv, pipe) {
1799                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1800                     intel_pipe_handle_vblank(dev, pipe))
1801                         intel_check_page_flip(dev, pipe);
1802
1803                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1804                         intel_prepare_page_flip(dev, pipe);
1805                         intel_finish_page_flip(dev, pipe);
1806                 }
1807
1808                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1809                         i9xx_pipe_crc_irq_handler(dev, pipe);
1810
1811                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1812                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1813         }
1814
1815         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1816                 gmbus_irq_handler(dev);
1817 }
1818
1819 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1820 {
1821         struct drm_i915_private *dev_priv = dev->dev_private;
1822         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1823
1824         if (hotplug_status) {
1825                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1826                 /*
1827                  * Make sure hotplug status is cleared before we clear IIR, or else we
1828                  * may miss hotplug events.
1829                  */
1830                 POSTING_READ(PORT_HOTPLUG_STAT);
1831
1832                 if (IS_G4X(dev)) {
1833                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1834
1835                         intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1836                 } else {
1837                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1838
1839                         intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1840                 }
1841
1842                 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1843                     hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1844                         dp_aux_irq_handler(dev);
1845         }
1846 }
1847
1848 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1849 {
1850         struct drm_device *dev = arg;
1851         struct drm_i915_private *dev_priv = dev->dev_private;
1852         u32 iir, gt_iir, pm_iir;
1853         irqreturn_t ret = IRQ_NONE;
1854
1855         while (true) {
1856                 /* Find, clear, then process each source of interrupt */
1857
1858                 gt_iir = I915_READ(GTIIR);
1859                 if (gt_iir)
1860                         I915_WRITE(GTIIR, gt_iir);
1861
1862                 pm_iir = I915_READ(GEN6_PMIIR);
1863                 if (pm_iir)
1864                         I915_WRITE(GEN6_PMIIR, pm_iir);
1865
1866                 iir = I915_READ(VLV_IIR);
1867                 if (iir) {
1868                         /* Consume port before clearing IIR or we'll miss events */
1869                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
1870                                 i9xx_hpd_irq_handler(dev);
1871                         I915_WRITE(VLV_IIR, iir);
1872                 }
1873
1874                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1875                         goto out;
1876
1877                 ret = IRQ_HANDLED;
1878
1879                 if (gt_iir)
1880                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1881                 if (pm_iir)
1882                         gen6_rps_irq_handler(dev_priv, pm_iir);
1883                 /* Call regardless, as some status bits might not be
1884                  * signalled in iir */
1885                 valleyview_pipestat_irq_handler(dev, iir);
1886         }
1887
1888 out:
1889         return ret;
1890 }
1891
1892 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1893 {
1894         struct drm_device *dev = arg;
1895         struct drm_i915_private *dev_priv = dev->dev_private;
1896         u32 master_ctl, iir;
1897         irqreturn_t ret = IRQ_NONE;
1898
1899         for (;;) {
1900                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1901                 iir = I915_READ(VLV_IIR);
1902
1903                 if (master_ctl == 0 && iir == 0)
1904                         break;
1905
1906                 ret = IRQ_HANDLED;
1907
1908                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1909
1910                 /* Find, clear, then process each source of interrupt */
1911
1912                 if (iir) {
1913                         /* Consume port before clearing IIR or we'll miss events */
1914                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
1915                                 i9xx_hpd_irq_handler(dev);
1916                         I915_WRITE(VLV_IIR, iir);
1917                 }
1918
1919                 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1920
1921                 /* Call regardless, as some status bits might not be
1922                  * signalled in iir */
1923                 valleyview_pipestat_irq_handler(dev, iir);
1924
1925                 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1926                 POSTING_READ(GEN8_MASTER_IRQ);
1927         }
1928
1929         return ret;
1930 }
1931
1932 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1933 {
1934         struct drm_i915_private *dev_priv = dev->dev_private;
1935         int pipe;
1936         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1937         u32 dig_hotplug_reg;
1938
1939         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1940         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1941
1942         intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1943
1944         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1945                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1946                                SDE_AUDIO_POWER_SHIFT);
1947                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1948                                  port_name(port));
1949         }
1950
1951         if (pch_iir & SDE_AUX_MASK)
1952                 dp_aux_irq_handler(dev);
1953
1954         if (pch_iir & SDE_GMBUS)
1955                 gmbus_irq_handler(dev);
1956
1957         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1958                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1959
1960         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1961                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1962
1963         if (pch_iir & SDE_POISON)
1964                 DRM_ERROR("PCH poison interrupt\n");
1965
1966         if (pch_iir & SDE_FDI_MASK)
1967                 for_each_pipe(dev_priv, pipe)
1968                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1969                                          pipe_name(pipe),
1970                                          I915_READ(FDI_RX_IIR(pipe)));
1971
1972         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1973                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1974
1975         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1976                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1977
1978         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1979                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1980
1981         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1982                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1983 }
1984
1985 static void ivb_err_int_handler(struct drm_device *dev)
1986 {
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         u32 err_int = I915_READ(GEN7_ERR_INT);
1989         enum pipe pipe;
1990
1991         if (err_int & ERR_INT_POISON)
1992                 DRM_ERROR("Poison interrupt\n");
1993
1994         for_each_pipe(dev_priv, pipe) {
1995                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1996                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1997
1998                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1999                         if (IS_IVYBRIDGE(dev))
2000                                 ivb_pipe_crc_irq_handler(dev, pipe);
2001                         else
2002                                 hsw_pipe_crc_irq_handler(dev, pipe);
2003                 }
2004         }
2005
2006         I915_WRITE(GEN7_ERR_INT, err_int);
2007 }
2008
2009 static void cpt_serr_int_handler(struct drm_device *dev)
2010 {
2011         struct drm_i915_private *dev_priv = dev->dev_private;
2012         u32 serr_int = I915_READ(SERR_INT);
2013
2014         if (serr_int & SERR_INT_POISON)
2015                 DRM_ERROR("PCH poison interrupt\n");
2016
2017         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2018                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2019
2020         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2021                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2022
2023         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2024                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2025
2026         I915_WRITE(SERR_INT, serr_int);
2027 }
2028
2029 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2030 {
2031         struct drm_i915_private *dev_priv = dev->dev_private;
2032         int pipe;
2033         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2034         u32 dig_hotplug_reg;
2035
2036         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2037         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2038
2039         intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2040
2041         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2042                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2043                                SDE_AUDIO_POWER_SHIFT_CPT);
2044                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2045                                  port_name(port));
2046         }
2047
2048         if (pch_iir & SDE_AUX_MASK_CPT)
2049                 dp_aux_irq_handler(dev);
2050
2051         if (pch_iir & SDE_GMBUS_CPT)
2052                 gmbus_irq_handler(dev);
2053
2054         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2055                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2056
2057         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2058                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2059
2060         if (pch_iir & SDE_FDI_MASK_CPT)
2061                 for_each_pipe(dev_priv, pipe)
2062                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2063                                          pipe_name(pipe),
2064                                          I915_READ(FDI_RX_IIR(pipe)));
2065
2066         if (pch_iir & SDE_ERROR_CPT)
2067                 cpt_serr_int_handler(dev);
2068 }
2069
2070 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2071 {
2072         struct drm_i915_private *dev_priv = dev->dev_private;
2073         enum pipe pipe;
2074
2075         if (de_iir & DE_AUX_CHANNEL_A)
2076                 dp_aux_irq_handler(dev);
2077
2078         if (de_iir & DE_GSE)
2079                 intel_opregion_asle_intr(dev);
2080
2081         if (de_iir & DE_POISON)
2082                 DRM_ERROR("Poison interrupt\n");
2083
2084         for_each_pipe(dev_priv, pipe) {
2085                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2086                     intel_pipe_handle_vblank(dev, pipe))
2087                         intel_check_page_flip(dev, pipe);
2088
2089                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2090                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2091
2092                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2093                         i9xx_pipe_crc_irq_handler(dev, pipe);
2094
2095                 /* plane/pipes map 1:1 on ilk+ */
2096                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2097                         intel_prepare_page_flip(dev, pipe);
2098                         intel_finish_page_flip_plane(dev, pipe);
2099                 }
2100         }
2101
2102         /* check event from PCH */
2103         if (de_iir & DE_PCH_EVENT) {
2104                 u32 pch_iir = I915_READ(SDEIIR);
2105
2106                 if (HAS_PCH_CPT(dev))
2107                         cpt_irq_handler(dev, pch_iir);
2108                 else
2109                         ibx_irq_handler(dev, pch_iir);
2110
2111                 /* should clear PCH hotplug event before clear CPU irq */
2112                 I915_WRITE(SDEIIR, pch_iir);
2113         }
2114
2115         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2116                 ironlake_rps_change_irq_handler(dev);
2117 }
2118
2119 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2120 {
2121         struct drm_i915_private *dev_priv = dev->dev_private;
2122         enum pipe pipe;
2123
2124         if (de_iir & DE_ERR_INT_IVB)
2125                 ivb_err_int_handler(dev);
2126
2127         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2128                 dp_aux_irq_handler(dev);
2129
2130         if (de_iir & DE_GSE_IVB)
2131                 intel_opregion_asle_intr(dev);
2132
2133         for_each_pipe(dev_priv, pipe) {
2134                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2135                     intel_pipe_handle_vblank(dev, pipe))
2136                         intel_check_page_flip(dev, pipe);
2137
2138                 /* plane/pipes map 1:1 on ilk+ */
2139                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2140                         intel_prepare_page_flip(dev, pipe);
2141                         intel_finish_page_flip_plane(dev, pipe);
2142                 }
2143         }
2144
2145         /* check event from PCH */
2146         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2147                 u32 pch_iir = I915_READ(SDEIIR);
2148
2149                 cpt_irq_handler(dev, pch_iir);
2150
2151                 /* clear PCH hotplug event before clear CPU irq */
2152                 I915_WRITE(SDEIIR, pch_iir);
2153         }
2154 }
2155
2156 /*
2157  * To handle irqs with the minimum potential races with fresh interrupts, we:
2158  * 1 - Disable Master Interrupt Control.
2159  * 2 - Find the source(s) of the interrupt.
2160  * 3 - Clear the Interrupt Identity bits (IIR).
2161  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2162  * 5 - Re-enable Master Interrupt Control.
2163  */
2164 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2165 {
2166         struct drm_device *dev = arg;
2167         struct drm_i915_private *dev_priv = dev->dev_private;
2168         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2169         irqreturn_t ret = IRQ_NONE;
2170
2171         /* We get interrupts on unclaimed registers, so check for this before we
2172          * do any I915_{READ,WRITE}. */
2173         intel_uncore_check_errors(dev);
2174
2175         /* disable master interrupt before clearing iir  */
2176         de_ier = I915_READ(DEIER);
2177         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2178         POSTING_READ(DEIER);
2179
2180         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2181          * interrupts will will be stored on its back queue, and then we'll be
2182          * able to process them after we restore SDEIER (as soon as we restore
2183          * it, we'll get an interrupt if SDEIIR still has something to process
2184          * due to its back queue). */
2185         if (!HAS_PCH_NOP(dev)) {
2186                 sde_ier = I915_READ(SDEIER);
2187                 I915_WRITE(SDEIER, 0);
2188                 POSTING_READ(SDEIER);
2189         }
2190
2191         /* Find, clear, then process each source of interrupt */
2192
2193         gt_iir = I915_READ(GTIIR);
2194         if (gt_iir) {
2195                 I915_WRITE(GTIIR, gt_iir);
2196                 ret = IRQ_HANDLED;
2197                 if (INTEL_INFO(dev)->gen >= 6)
2198                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
2199                 else
2200                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2201         }
2202
2203         de_iir = I915_READ(DEIIR);
2204         if (de_iir) {
2205                 I915_WRITE(DEIIR, de_iir);
2206                 ret = IRQ_HANDLED;
2207                 if (INTEL_INFO(dev)->gen >= 7)
2208                         ivb_display_irq_handler(dev, de_iir);
2209                 else
2210                         ilk_display_irq_handler(dev, de_iir);
2211         }
2212
2213         if (INTEL_INFO(dev)->gen >= 6) {
2214                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2215                 if (pm_iir) {
2216                         I915_WRITE(GEN6_PMIIR, pm_iir);
2217                         ret = IRQ_HANDLED;
2218                         gen6_rps_irq_handler(dev_priv, pm_iir);
2219                 }
2220         }
2221
2222         I915_WRITE(DEIER, de_ier);
2223         POSTING_READ(DEIER);
2224         if (!HAS_PCH_NOP(dev)) {
2225                 I915_WRITE(SDEIER, sde_ier);
2226                 POSTING_READ(SDEIER);
2227         }
2228
2229         return ret;
2230 }
2231
2232 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2233 {
2234         struct drm_device *dev = arg;
2235         struct drm_i915_private *dev_priv = dev->dev_private;
2236         u32 master_ctl;
2237         irqreturn_t ret = IRQ_NONE;
2238         uint32_t tmp = 0;
2239         enum pipe pipe;
2240         u32 aux_mask = GEN8_AUX_CHANNEL_A;
2241
2242         if (IS_GEN9(dev))
2243                 aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2244                         GEN9_AUX_CHANNEL_D;
2245
2246         master_ctl = I915_READ(GEN8_MASTER_IRQ);
2247         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2248         if (!master_ctl)
2249                 return IRQ_NONE;
2250
2251         I915_WRITE(GEN8_MASTER_IRQ, 0);
2252         POSTING_READ(GEN8_MASTER_IRQ);
2253
2254         /* Find, clear, then process each source of interrupt */
2255
2256         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2257
2258         if (master_ctl & GEN8_DE_MISC_IRQ) {
2259                 tmp = I915_READ(GEN8_DE_MISC_IIR);
2260                 if (tmp) {
2261                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2262                         ret = IRQ_HANDLED;
2263                         if (tmp & GEN8_DE_MISC_GSE)
2264                                 intel_opregion_asle_intr(dev);
2265                         else
2266                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2267                 }
2268                 else
2269                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2270         }
2271
2272         if (master_ctl & GEN8_DE_PORT_IRQ) {
2273                 tmp = I915_READ(GEN8_DE_PORT_IIR);
2274                 if (tmp) {
2275                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2276                         ret = IRQ_HANDLED;
2277
2278                         if (tmp & aux_mask)
2279                                 dp_aux_irq_handler(dev);
2280                         else
2281                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2282                 }
2283                 else
2284                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2285         }
2286
2287         for_each_pipe(dev_priv, pipe) {
2288                 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2289
2290                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2291                         continue;
2292
2293                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2294                 if (pipe_iir) {
2295                         ret = IRQ_HANDLED;
2296                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2297
2298                         if (pipe_iir & GEN8_PIPE_VBLANK &&
2299                             intel_pipe_handle_vblank(dev, pipe))
2300                                 intel_check_page_flip(dev, pipe);
2301
2302                         if (IS_GEN9(dev))
2303                                 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2304                         else
2305                                 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2306
2307                         if (flip_done) {
2308                                 intel_prepare_page_flip(dev, pipe);
2309                                 intel_finish_page_flip_plane(dev, pipe);
2310                         }
2311
2312                         if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2313                                 hsw_pipe_crc_irq_handler(dev, pipe);
2314
2315                         if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2316                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2317                                                                     pipe);
2318
2319
2320                         if (IS_GEN9(dev))
2321                                 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2322                         else
2323                                 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2324
2325                         if (fault_errors)
2326                                 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2327                                           pipe_name(pipe),
2328                                           pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2329                 } else
2330                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2331         }
2332
2333         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2334                 /*
2335                  * FIXME(BDW): Assume for now that the new interrupt handling
2336                  * scheme also closed the SDE interrupt handling race we've seen
2337                  * on older pch-split platforms. But this needs testing.
2338                  */
2339                 u32 pch_iir = I915_READ(SDEIIR);
2340                 if (pch_iir) {
2341                         I915_WRITE(SDEIIR, pch_iir);
2342                         ret = IRQ_HANDLED;
2343                         cpt_irq_handler(dev, pch_iir);
2344                 } else
2345                         DRM_ERROR("The master control interrupt lied (SDE)!\n");
2346
2347         }
2348
2349         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2350         POSTING_READ(GEN8_MASTER_IRQ);
2351
2352         return ret;
2353 }
2354
2355 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2356                                bool reset_completed)
2357 {
2358         struct intel_engine_cs *ring;
2359         int i;
2360
2361         /*
2362          * Notify all waiters for GPU completion events that reset state has
2363          * been changed, and that they need to restart their wait after
2364          * checking for potential errors (and bail out to drop locks if there is
2365          * a gpu reset pending so that i915_error_work_func can acquire them).
2366          */
2367
2368         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2369         for_each_ring(ring, dev_priv, i)
2370                 wake_up_all(&ring->irq_queue);
2371
2372         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2373         wake_up_all(&dev_priv->pending_flip_queue);
2374
2375         /*
2376          * Signal tasks blocked in i915_gem_wait_for_error that the pending
2377          * reset state is cleared.
2378          */
2379         if (reset_completed)
2380                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2381 }
2382
2383 /**
2384  * i915_reset_and_wakeup - do process context error handling work
2385  *
2386  * Fire an error uevent so userspace can see that a hang or error
2387  * was detected.
2388  */
2389 static void i915_reset_and_wakeup(struct drm_device *dev)
2390 {
2391         struct drm_i915_private *dev_priv = to_i915(dev);
2392         struct i915_gpu_error *error = &dev_priv->gpu_error;
2393         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2394         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2395         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2396         int ret;
2397
2398         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2399
2400         /*
2401          * Note that there's only one work item which does gpu resets, so we
2402          * need not worry about concurrent gpu resets potentially incrementing
2403          * error->reset_counter twice. We only need to take care of another
2404          * racing irq/hangcheck declaring the gpu dead for a second time. A
2405          * quick check for that is good enough: schedule_work ensures the
2406          * correct ordering between hang detection and this work item, and since
2407          * the reset in-progress bit is only ever set by code outside of this
2408          * work we don't need to worry about any other races.
2409          */
2410         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2411                 DRM_DEBUG_DRIVER("resetting chip\n");
2412                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2413                                    reset_event);
2414
2415                 /*
2416                  * In most cases it's guaranteed that we get here with an RPM
2417                  * reference held, for example because there is a pending GPU
2418                  * request that won't finish until the reset is done. This
2419                  * isn't the case at least when we get here by doing a
2420                  * simulated reset via debugs, so get an RPM reference.
2421                  */
2422                 intel_runtime_pm_get(dev_priv);
2423
2424                 intel_prepare_reset(dev);
2425
2426                 /*
2427                  * All state reset _must_ be completed before we update the
2428                  * reset counter, for otherwise waiters might miss the reset
2429                  * pending state and not properly drop locks, resulting in
2430                  * deadlocks with the reset work.
2431                  */
2432                 ret = i915_reset(dev);
2433
2434                 intel_finish_reset(dev);
2435
2436                 intel_runtime_pm_put(dev_priv);
2437
2438                 if (ret == 0) {
2439                         /*
2440                          * After all the gem state is reset, increment the reset
2441                          * counter and wake up everyone waiting for the reset to
2442                          * complete.
2443                          *
2444                          * Since unlock operations are a one-sided barrier only,
2445                          * we need to insert a barrier here to order any seqno
2446                          * updates before
2447                          * the counter increment.
2448                          */
2449                         smp_mb__before_atomic();
2450                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2451
2452                         kobject_uevent_env(&dev->primary->kdev->kobj,
2453                                            KOBJ_CHANGE, reset_done_event);
2454                 } else {
2455                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2456                 }
2457
2458                 /*
2459                  * Note: The wake_up also serves as a memory barrier so that
2460                  * waiters see the update value of the reset counter atomic_t.
2461                  */
2462                 i915_error_wake_up(dev_priv, true);
2463         }
2464 }
2465
2466 static void i915_report_and_clear_eir(struct drm_device *dev)
2467 {
2468         struct drm_i915_private *dev_priv = dev->dev_private;
2469         uint32_t instdone[I915_NUM_INSTDONE_REG];
2470         u32 eir = I915_READ(EIR);
2471         int pipe, i;
2472
2473         if (!eir)
2474                 return;
2475
2476         pr_err("render error detected, EIR: 0x%08x\n", eir);
2477
2478         i915_get_extra_instdone(dev, instdone);
2479
2480         if (IS_G4X(dev)) {
2481                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2482                         u32 ipeir = I915_READ(IPEIR_I965);
2483
2484                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2485                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2486                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2487                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2488                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2489                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2490                         I915_WRITE(IPEIR_I965, ipeir);
2491                         POSTING_READ(IPEIR_I965);
2492                 }
2493                 if (eir & GM45_ERROR_PAGE_TABLE) {
2494                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2495                         pr_err("page table error\n");
2496                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2497                         I915_WRITE(PGTBL_ER, pgtbl_err);
2498                         POSTING_READ(PGTBL_ER);
2499                 }
2500         }
2501
2502         if (!IS_GEN2(dev)) {
2503                 if (eir & I915_ERROR_PAGE_TABLE) {
2504                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2505                         pr_err("page table error\n");
2506                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2507                         I915_WRITE(PGTBL_ER, pgtbl_err);
2508                         POSTING_READ(PGTBL_ER);
2509                 }
2510         }
2511
2512         if (eir & I915_ERROR_MEMORY_REFRESH) {
2513                 pr_err("memory refresh error:\n");
2514                 for_each_pipe(dev_priv, pipe)
2515                         pr_err("pipe %c stat: 0x%08x\n",
2516                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2517                 /* pipestat has already been acked */
2518         }
2519         if (eir & I915_ERROR_INSTRUCTION) {
2520                 pr_err("instruction error\n");
2521                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2522                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2523                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2524                 if (INTEL_INFO(dev)->gen < 4) {
2525                         u32 ipeir = I915_READ(IPEIR);
2526
2527                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2528                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2529                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2530                         I915_WRITE(IPEIR, ipeir);
2531                         POSTING_READ(IPEIR);
2532                 } else {
2533                         u32 ipeir = I915_READ(IPEIR_I965);
2534
2535                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2536                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2537                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2538                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2539                         I915_WRITE(IPEIR_I965, ipeir);
2540                         POSTING_READ(IPEIR_I965);
2541                 }
2542         }
2543
2544         I915_WRITE(EIR, eir);
2545         POSTING_READ(EIR);
2546         eir = I915_READ(EIR);
2547         if (eir) {
2548                 /*
2549                  * some errors might have become stuck,
2550                  * mask them.
2551                  */
2552                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2553                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2554                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2555         }
2556 }
2557
2558 /**
2559  * i915_handle_error - handle a gpu error
2560  * @dev: drm device
2561  *
2562  * Do some basic checking of regsiter state at error time and
2563  * dump it to the syslog.  Also call i915_capture_error_state() to make
2564  * sure we get a record and make it available in debugfs.  Fire a uevent
2565  * so userspace knows something bad happened (should trigger collection
2566  * of a ring dump etc.).
2567  */
2568 void i915_handle_error(struct drm_device *dev, bool wedged,
2569                        const char *fmt, ...)
2570 {
2571         struct drm_i915_private *dev_priv = dev->dev_private;
2572         va_list args;
2573         char error_msg[80];
2574
2575         va_start(args, fmt);
2576         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2577         va_end(args);
2578
2579         i915_capture_error_state(dev, wedged, error_msg);
2580         i915_report_and_clear_eir(dev);
2581
2582         if (wedged) {
2583                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2584                                 &dev_priv->gpu_error.reset_counter);
2585
2586                 /*
2587                  * Wakeup waiting processes so that the reset function
2588                  * i915_reset_and_wakeup doesn't deadlock trying to grab
2589                  * various locks. By bumping the reset counter first, the woken
2590                  * processes will see a reset in progress and back off,
2591                  * releasing their locks and then wait for the reset completion.
2592                  * We must do this for _all_ gpu waiters that might hold locks
2593                  * that the reset work needs to acquire.
2594                  *
2595                  * Note: The wake_up serves as the required memory barrier to
2596                  * ensure that the waiters see the updated value of the reset
2597                  * counter atomic_t.
2598                  */
2599                 i915_error_wake_up(dev_priv, false);
2600         }
2601
2602         i915_reset_and_wakeup(dev);
2603 }
2604
2605 /* Called from drm generic code, passed 'crtc' which
2606  * we use as a pipe index
2607  */
2608 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2609 {
2610         struct drm_i915_private *dev_priv = dev->dev_private;
2611         unsigned long irqflags;
2612
2613         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2614         if (INTEL_INFO(dev)->gen >= 4)
2615                 i915_enable_pipestat(dev_priv, pipe,
2616                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2617         else
2618                 i915_enable_pipestat(dev_priv, pipe,
2619                                      PIPE_VBLANK_INTERRUPT_STATUS);
2620         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2621
2622         return 0;
2623 }
2624
2625 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2626 {
2627         struct drm_i915_private *dev_priv = dev->dev_private;
2628         unsigned long irqflags;
2629         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2630                                                      DE_PIPE_VBLANK(pipe);
2631
2632         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2633         ironlake_enable_display_irq(dev_priv, bit);
2634         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2635
2636         return 0;
2637 }
2638
2639 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2640 {
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         unsigned long irqflags;
2643
2644         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2645         i915_enable_pipestat(dev_priv, pipe,
2646                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2647         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2648
2649         return 0;
2650 }
2651
2652 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2653 {
2654         struct drm_i915_private *dev_priv = dev->dev_private;
2655         unsigned long irqflags;
2656
2657         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2658         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2659         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2660         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2661         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2662         return 0;
2663 }
2664
2665 /* Called from drm generic code, passed 'crtc' which
2666  * we use as a pipe index
2667  */
2668 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2669 {
2670         struct drm_i915_private *dev_priv = dev->dev_private;
2671         unsigned long irqflags;
2672
2673         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2674         i915_disable_pipestat(dev_priv, pipe,
2675                               PIPE_VBLANK_INTERRUPT_STATUS |
2676                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2677         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2678 }
2679
2680 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2681 {
2682         struct drm_i915_private *dev_priv = dev->dev_private;
2683         unsigned long irqflags;
2684         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2685                                                      DE_PIPE_VBLANK(pipe);
2686
2687         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2688         ironlake_disable_display_irq(dev_priv, bit);
2689         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2690 }
2691
2692 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2693 {
2694         struct drm_i915_private *dev_priv = dev->dev_private;
2695         unsigned long irqflags;
2696
2697         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2698         i915_disable_pipestat(dev_priv, pipe,
2699                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2700         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2701 }
2702
2703 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2704 {
2705         struct drm_i915_private *dev_priv = dev->dev_private;
2706         unsigned long irqflags;
2707
2708         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2709         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2710         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2711         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2712         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2713 }
2714
2715 static struct drm_i915_gem_request *
2716 ring_last_request(struct intel_engine_cs *ring)
2717 {
2718         return list_entry(ring->request_list.prev,
2719                           struct drm_i915_gem_request, list);
2720 }
2721
2722 static bool
2723 ring_idle(struct intel_engine_cs *ring)
2724 {
2725         return (list_empty(&ring->request_list) ||
2726                 i915_gem_request_completed(ring_last_request(ring), false));
2727 }
2728
2729 static bool
2730 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2731 {
2732         if (INTEL_INFO(dev)->gen >= 8) {
2733                 return (ipehr >> 23) == 0x1c;
2734         } else {
2735                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2736                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2737                                  MI_SEMAPHORE_REGISTER);
2738         }
2739 }
2740
2741 static struct intel_engine_cs *
2742 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2743 {
2744         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2745         struct intel_engine_cs *signaller;
2746         int i;
2747
2748         if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2749                 for_each_ring(signaller, dev_priv, i) {
2750                         if (ring == signaller)
2751                                 continue;
2752
2753                         if (offset == signaller->semaphore.signal_ggtt[ring->id])
2754                                 return signaller;
2755                 }
2756         } else {
2757                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2758
2759                 for_each_ring(signaller, dev_priv, i) {
2760                         if(ring == signaller)
2761                                 continue;
2762
2763                         if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2764                                 return signaller;
2765                 }
2766         }
2767
2768         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2769                   ring->id, ipehr, offset);
2770
2771         return NULL;
2772 }
2773
2774 static struct intel_engine_cs *
2775 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2776 {
2777         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2778         u32 cmd, ipehr, head;
2779         u64 offset = 0;
2780         int i, backwards;
2781
2782         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2783         if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2784                 return NULL;
2785
2786         /*
2787          * HEAD is likely pointing to the dword after the actual command,
2788          * so scan backwards until we find the MBOX. But limit it to just 3
2789          * or 4 dwords depending on the semaphore wait command size.
2790          * Note that we don't care about ACTHD here since that might
2791          * point at at batch, and semaphores are always emitted into the
2792          * ringbuffer itself.
2793          */
2794         head = I915_READ_HEAD(ring) & HEAD_ADDR;
2795         backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2796
2797         for (i = backwards; i; --i) {
2798                 /*
2799                  * Be paranoid and presume the hw has gone off into the wild -
2800                  * our ring is smaller than what the hardware (and hence
2801                  * HEAD_ADDR) allows. Also handles wrap-around.
2802                  */
2803                 head &= ring->buffer->size - 1;
2804
2805                 /* This here seems to blow up */
2806                 cmd = ioread32(ring->buffer->virtual_start + head);
2807                 if (cmd == ipehr)
2808                         break;
2809
2810                 head -= 4;
2811         }
2812
2813         if (!i)
2814                 return NULL;
2815
2816         *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2817         if (INTEL_INFO(ring->dev)->gen >= 8) {
2818                 offset = ioread32(ring->buffer->virtual_start + head + 12);
2819                 offset <<= 32;
2820                 offset = ioread32(ring->buffer->virtual_start + head + 8);
2821         }
2822         return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2823 }
2824
2825 static int semaphore_passed(struct intel_engine_cs *ring)
2826 {
2827         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2828         struct intel_engine_cs *signaller;
2829         u32 seqno;
2830
2831         ring->hangcheck.deadlock++;
2832
2833         signaller = semaphore_waits_for(ring, &seqno);
2834         if (signaller == NULL)
2835                 return -1;
2836
2837         /* Prevent pathological recursion due to driver bugs */
2838         if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2839                 return -1;
2840
2841         if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2842                 return 1;
2843
2844         /* cursory check for an unkickable deadlock */
2845         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2846             semaphore_passed(signaller) < 0)
2847                 return -1;
2848
2849         return 0;
2850 }
2851
2852 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2853 {
2854         struct intel_engine_cs *ring;
2855         int i;
2856
2857         for_each_ring(ring, dev_priv, i)
2858                 ring->hangcheck.deadlock = 0;
2859 }
2860
2861 static enum intel_ring_hangcheck_action
2862 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2863 {
2864         struct drm_device *dev = ring->dev;
2865         struct drm_i915_private *dev_priv = dev->dev_private;
2866         u32 tmp;
2867
2868         if (acthd != ring->hangcheck.acthd) {
2869                 if (acthd > ring->hangcheck.max_acthd) {
2870                         ring->hangcheck.max_acthd = acthd;
2871                         return HANGCHECK_ACTIVE;
2872                 }
2873
2874                 return HANGCHECK_ACTIVE_LOOP;
2875         }
2876
2877         if (IS_GEN2(dev))
2878                 return HANGCHECK_HUNG;
2879
2880         /* Is the chip hanging on a WAIT_FOR_EVENT?
2881          * If so we can simply poke the RB_WAIT bit
2882          * and break the hang. This should work on
2883          * all but the second generation chipsets.
2884          */
2885         tmp = I915_READ_CTL(ring);
2886         if (tmp & RING_WAIT) {
2887                 i915_handle_error(dev, false,
2888                                   "Kicking stuck wait on %s",
2889                                   ring->name);
2890                 I915_WRITE_CTL(ring, tmp);
2891                 return HANGCHECK_KICK;
2892         }
2893
2894         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2895                 switch (semaphore_passed(ring)) {
2896                 default:
2897                         return HANGCHECK_HUNG;
2898                 case 1:
2899                         i915_handle_error(dev, false,
2900                                           "Kicking stuck semaphore on %s",
2901                                           ring->name);
2902                         I915_WRITE_CTL(ring, tmp);
2903                         return HANGCHECK_KICK;
2904                 case 0:
2905                         return HANGCHECK_WAIT;
2906                 }
2907         }
2908
2909         return HANGCHECK_HUNG;
2910 }
2911
2912 /*
2913  * This is called when the chip hasn't reported back with completed
2914  * batchbuffers in a long time. We keep track per ring seqno progress and
2915  * if there are no progress, hangcheck score for that ring is increased.
2916  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2917  * we kick the ring. If we see no progress on three subsequent calls
2918  * we assume chip is wedged and try to fix it by resetting the chip.
2919  */
2920 static void i915_hangcheck_elapsed(struct work_struct *work)
2921 {
2922         struct drm_i915_private *dev_priv =
2923                 container_of(work, typeof(*dev_priv),
2924                              gpu_error.hangcheck_work.work);
2925         struct drm_device *dev = dev_priv->dev;
2926         struct intel_engine_cs *ring;
2927         int i;
2928         int busy_count = 0, rings_hung = 0;
2929         bool stuck[I915_NUM_RINGS] = { 0 };
2930 #define BUSY 1
2931 #define KICK 5
2932 #define HUNG 20
2933
2934         if (!i915.enable_hangcheck)
2935                 return;
2936
2937         for_each_ring(ring, dev_priv, i) {
2938                 u64 acthd;
2939                 u32 seqno;
2940                 bool busy = true;
2941
2942                 semaphore_clear_deadlocks(dev_priv);
2943
2944                 seqno = ring->get_seqno(ring, false);
2945                 acthd = intel_ring_get_active_head(ring);
2946
2947                 if (ring->hangcheck.seqno == seqno) {
2948                         if (ring_idle(ring)) {
2949                                 ring->hangcheck.action = HANGCHECK_IDLE;
2950
2951                                 if (waitqueue_active(&ring->irq_queue)) {
2952                                         /* Issue a wake-up to catch stuck h/w. */
2953                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2954                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2955                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2956                                                                   ring->name);
2957                                                 else
2958                                                         DRM_INFO("Fake missed irq on %s\n",
2959                                                                  ring->name);
2960                                                 wake_up_all(&ring->irq_queue);
2961                                         }
2962                                         /* Safeguard against driver failure */
2963                                         ring->hangcheck.score += BUSY;
2964                                 } else
2965                                         busy = false;
2966                         } else {
2967                                 /* We always increment the hangcheck score
2968                                  * if the ring is busy and still processing
2969                                  * the same request, so that no single request
2970                                  * can run indefinitely (such as a chain of
2971                                  * batches). The only time we do not increment
2972                                  * the hangcheck score on this ring, if this
2973                                  * ring is in a legitimate wait for another
2974                                  * ring. In that case the waiting ring is a
2975                                  * victim and we want to be sure we catch the
2976                                  * right culprit. Then every time we do kick
2977                                  * the ring, add a small increment to the
2978                                  * score so that we can catch a batch that is
2979                                  * being repeatedly kicked and so responsible
2980                                  * for stalling the machine.
2981                                  */
2982                                 ring->hangcheck.action = ring_stuck(ring,
2983                                                                     acthd);
2984
2985                                 switch (ring->hangcheck.action) {
2986                                 case HANGCHECK_IDLE:
2987                                 case HANGCHECK_WAIT:
2988                                 case HANGCHECK_ACTIVE:
2989                                         break;
2990                                 case HANGCHECK_ACTIVE_LOOP:
2991                                         ring->hangcheck.score += BUSY;
2992                                         break;
2993                                 case HANGCHECK_KICK:
2994                                         ring->hangcheck.score += KICK;
2995                                         break;
2996                                 case HANGCHECK_HUNG:
2997                                         ring->hangcheck.score += HUNG;
2998                                         stuck[i] = true;
2999                                         break;
3000                                 }
3001                         }
3002                 } else {
3003                         ring->hangcheck.action = HANGCHECK_ACTIVE;
3004
3005                         /* Gradually reduce the count so that we catch DoS
3006                          * attempts across multiple batches.
3007                          */
3008                         if (ring->hangcheck.score > 0)
3009                                 ring->hangcheck.score--;
3010
3011                         ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3012                 }
3013
3014                 ring->hangcheck.seqno = seqno;
3015                 ring->hangcheck.acthd = acthd;
3016                 busy_count += busy;
3017         }
3018
3019         for_each_ring(ring, dev_priv, i) {
3020                 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3021                         DRM_INFO("%s on %s\n",
3022                                  stuck[i] ? "stuck" : "no progress",
3023                                  ring->name);
3024                         rings_hung++;
3025                 }
3026         }
3027
3028         if (rings_hung)
3029                 return i915_handle_error(dev, true, "Ring hung");
3030
3031         if (busy_count)
3032                 /* Reset timer case chip hangs without another request
3033                  * being added */
3034                 i915_queue_hangcheck(dev);
3035 }
3036
3037 void i915_queue_hangcheck(struct drm_device *dev)
3038 {
3039         struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
3040
3041         if (!i915.enable_hangcheck)
3042                 return;
3043
3044         /* Don't continually defer the hangcheck so that it is always run at
3045          * least once after work has been scheduled on any ring. Otherwise,
3046          * we will ignore a hung ring if a second ring is kept busy.
3047          */
3048
3049         queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3050                            round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3051 }
3052
3053 static void ibx_irq_reset(struct drm_device *dev)
3054 {
3055         struct drm_i915_private *dev_priv = dev->dev_private;
3056
3057         if (HAS_PCH_NOP(dev))
3058                 return;
3059
3060         GEN5_IRQ_RESET(SDE);
3061
3062         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3063                 I915_WRITE(SERR_INT, 0xffffffff);
3064 }
3065
3066 /*
3067  * SDEIER is also touched by the interrupt handler to work around missed PCH
3068  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3069  * instead we unconditionally enable all PCH interrupt sources here, but then
3070  * only unmask them as needed with SDEIMR.
3071  *
3072  * This function needs to be called before interrupts are enabled.
3073  */
3074 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3075 {
3076         struct drm_i915_private *dev_priv = dev->dev_private;
3077
3078         if (HAS_PCH_NOP(dev))
3079                 return;
3080
3081         WARN_ON(I915_READ(SDEIER) != 0);
3082         I915_WRITE(SDEIER, 0xffffffff);
3083         POSTING_READ(SDEIER);
3084 }
3085
3086 static void gen5_gt_irq_reset(struct drm_device *dev)
3087 {
3088         struct drm_i915_private *dev_priv = dev->dev_private;
3089
3090         GEN5_IRQ_RESET(GT);
3091         if (INTEL_INFO(dev)->gen >= 6)
3092                 GEN5_IRQ_RESET(GEN6_PM);
3093 }
3094
3095 /* drm_dma.h hooks
3096 */
3097 static void ironlake_irq_reset(struct drm_device *dev)
3098 {
3099         struct drm_i915_private *dev_priv = dev->dev_private;
3100
3101         I915_WRITE(HWSTAM, 0xffffffff);
3102
3103         GEN5_IRQ_RESET(DE);
3104         if (IS_GEN7(dev))
3105                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3106
3107         gen5_gt_irq_reset(dev);
3108
3109         ibx_irq_reset(dev);
3110 }
3111
3112 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3113 {
3114         enum pipe pipe;
3115
3116         I915_WRITE(PORT_HOTPLUG_EN, 0);
3117         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3118
3119         for_each_pipe(dev_priv, pipe)
3120                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3121
3122         GEN5_IRQ_RESET(VLV_);
3123 }
3124
3125 static void valleyview_irq_preinstall(struct drm_device *dev)
3126 {
3127         struct drm_i915_private *dev_priv = dev->dev_private;
3128
3129         /* VLV magic */
3130         I915_WRITE(VLV_IMR, 0);
3131         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3132         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3133         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3134
3135         gen5_gt_irq_reset(dev);
3136
3137         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3138
3139         vlv_display_irq_reset(dev_priv);
3140 }
3141
3142 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3143 {
3144         GEN8_IRQ_RESET_NDX(GT, 0);
3145         GEN8_IRQ_RESET_NDX(GT, 1);
3146         GEN8_IRQ_RESET_NDX(GT, 2);
3147         GEN8_IRQ_RESET_NDX(GT, 3);
3148 }
3149
3150 static void gen8_irq_reset(struct drm_device *dev)
3151 {
3152         struct drm_i915_private *dev_priv = dev->dev_private;
3153         int pipe;
3154
3155         I915_WRITE(GEN8_MASTER_IRQ, 0);
3156         POSTING_READ(GEN8_MASTER_IRQ);
3157
3158         gen8_gt_irq_reset(dev_priv);
3159
3160         for_each_pipe(dev_priv, pipe)
3161                 if (intel_display_power_is_enabled(dev_priv,
3162                                                    POWER_DOMAIN_PIPE(pipe)))
3163                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3164
3165         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3166         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3167         GEN5_IRQ_RESET(GEN8_PCU_);
3168
3169         ibx_irq_reset(dev);
3170 }
3171
3172 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3173 {
3174         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3175
3176         spin_lock_irq(&dev_priv->irq_lock);
3177         GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3178                           ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3179         GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3180                           ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3181         spin_unlock_irq(&dev_priv->irq_lock);
3182 }
3183
3184 static void cherryview_irq_preinstall(struct drm_device *dev)
3185 {
3186         struct drm_i915_private *dev_priv = dev->dev_private;
3187
3188         I915_WRITE(GEN8_MASTER_IRQ, 0);
3189         POSTING_READ(GEN8_MASTER_IRQ);
3190
3191         gen8_gt_irq_reset(dev_priv);
3192
3193         GEN5_IRQ_RESET(GEN8_PCU_);
3194
3195         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3196
3197         vlv_display_irq_reset(dev_priv);
3198 }
3199
3200 static void ibx_hpd_irq_setup(struct drm_device *dev)
3201 {
3202         struct drm_i915_private *dev_priv = dev->dev_private;
3203         struct intel_encoder *intel_encoder;
3204         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3205
3206         if (HAS_PCH_IBX(dev)) {
3207                 hotplug_irqs = SDE_HOTPLUG_MASK;
3208                 for_each_intel_encoder(dev, intel_encoder)
3209                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3210                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3211         } else {
3212                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3213                 for_each_intel_encoder(dev, intel_encoder)
3214                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3215                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3216         }
3217
3218         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3219
3220         /*
3221          * Enable digital hotplug on the PCH, and configure the DP short pulse
3222          * duration to 2ms (which is the minimum in the Display Port spec)
3223          *
3224          * This register is the same on all known PCH chips.
3225          */
3226         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3227         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3228         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3229         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3230         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3231         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3232 }
3233
3234 static void ibx_irq_postinstall(struct drm_device *dev)
3235 {
3236         struct drm_i915_private *dev_priv = dev->dev_private;
3237         u32 mask;
3238
3239         if (HAS_PCH_NOP(dev))
3240                 return;
3241
3242         if (HAS_PCH_IBX(dev))
3243                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3244         else
3245                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3246
3247         GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3248         I915_WRITE(SDEIMR, ~mask);
3249 }
3250
3251 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3252 {
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         u32 pm_irqs, gt_irqs;
3255
3256         pm_irqs = gt_irqs = 0;
3257
3258         dev_priv->gt_irq_mask = ~0;
3259         if (HAS_L3_DPF(dev)) {
3260                 /* L3 parity interrupt is always unmasked. */
3261                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3262                 gt_irqs |= GT_PARITY_ERROR(dev);
3263         }
3264
3265         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3266         if (IS_GEN5(dev)) {
3267                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3268                            ILK_BSD_USER_INTERRUPT;
3269         } else {
3270                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3271         }
3272
3273         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3274
3275         if (INTEL_INFO(dev)->gen >= 6) {
3276                 /*
3277                  * RPS interrupts will get enabled/disabled on demand when RPS
3278                  * itself is enabled/disabled.
3279                  */
3280                 if (HAS_VEBOX(dev))
3281                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3282
3283                 dev_priv->pm_irq_mask = 0xffffffff;
3284                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3285         }
3286 }
3287
3288 static int ironlake_irq_postinstall(struct drm_device *dev)
3289 {
3290         struct drm_i915_private *dev_priv = dev->dev_private;
3291         u32 display_mask, extra_mask;
3292
3293         if (INTEL_INFO(dev)->gen >= 7) {
3294                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3295                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3296                                 DE_PLANEB_FLIP_DONE_IVB |
3297                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3298                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3299                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3300         } else {
3301                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3302                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3303                                 DE_AUX_CHANNEL_A |
3304                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3305                                 DE_POISON);
3306                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3307                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3308         }
3309
3310         dev_priv->irq_mask = ~display_mask;
3311
3312         I915_WRITE(HWSTAM, 0xeffe);
3313
3314         ibx_irq_pre_postinstall(dev);
3315
3316         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3317
3318         gen5_gt_irq_postinstall(dev);
3319
3320         ibx_irq_postinstall(dev);
3321
3322         if (IS_IRONLAKE_M(dev)) {
3323                 /* Enable PCU event interrupts
3324                  *
3325                  * spinlocking not required here for correctness since interrupt
3326                  * setup is guaranteed to run in single-threaded context. But we
3327                  * need it to make the assert_spin_locked happy. */
3328                 spin_lock_irq(&dev_priv->irq_lock);
3329                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3330                 spin_unlock_irq(&dev_priv->irq_lock);
3331         }
3332
3333         return 0;
3334 }
3335
3336 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3337 {
3338         u32 pipestat_mask;
3339         u32 iir_mask;
3340         enum pipe pipe;
3341
3342         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3343                         PIPE_FIFO_UNDERRUN_STATUS;
3344
3345         for_each_pipe(dev_priv, pipe)
3346                 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3347         POSTING_READ(PIPESTAT(PIPE_A));
3348
3349         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3350                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3351
3352         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3353         for_each_pipe(dev_priv, pipe)
3354                       i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3355
3356         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3357                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3358                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3359         if (IS_CHERRYVIEW(dev_priv))
3360                 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3361         dev_priv->irq_mask &= ~iir_mask;
3362
3363         I915_WRITE(VLV_IIR, iir_mask);
3364         I915_WRITE(VLV_IIR, iir_mask);
3365         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3366         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3367         POSTING_READ(VLV_IMR);
3368 }
3369
3370 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3371 {
3372         u32 pipestat_mask;
3373         u32 iir_mask;
3374         enum pipe pipe;
3375
3376         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3377                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3378                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3379         if (IS_CHERRYVIEW(dev_priv))
3380                 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3381
3382         dev_priv->irq_mask |= iir_mask;
3383         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3384         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3385         I915_WRITE(VLV_IIR, iir_mask);
3386         I915_WRITE(VLV_IIR, iir_mask);
3387         POSTING_READ(VLV_IIR);
3388
3389         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3390                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3391
3392         i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3393         for_each_pipe(dev_priv, pipe)
3394                 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3395
3396         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3397                         PIPE_FIFO_UNDERRUN_STATUS;
3398
3399         for_each_pipe(dev_priv, pipe)
3400                 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3401         POSTING_READ(PIPESTAT(PIPE_A));
3402 }
3403
3404 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3405 {
3406         assert_spin_locked(&dev_priv->irq_lock);
3407
3408         if (dev_priv->display_irqs_enabled)
3409                 return;
3410
3411         dev_priv->display_irqs_enabled = true;
3412
3413         if (intel_irqs_enabled(dev_priv))
3414                 valleyview_display_irqs_install(dev_priv);
3415 }
3416
3417 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3418 {
3419         assert_spin_locked(&dev_priv->irq_lock);
3420
3421         if (!dev_priv->display_irqs_enabled)
3422                 return;
3423
3424         dev_priv->display_irqs_enabled = false;
3425
3426         if (intel_irqs_enabled(dev_priv))
3427                 valleyview_display_irqs_uninstall(dev_priv);
3428 }
3429
3430 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3431 {
3432         dev_priv->irq_mask = ~0;
3433
3434         I915_WRITE(PORT_HOTPLUG_EN, 0);
3435         POSTING_READ(PORT_HOTPLUG_EN);
3436
3437         I915_WRITE(VLV_IIR, 0xffffffff);
3438         I915_WRITE(VLV_IIR, 0xffffffff);
3439         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3440         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3441         POSTING_READ(VLV_IMR);
3442
3443         /* Interrupt setup is already guaranteed to be single-threaded, this is
3444          * just to make the assert_spin_locked check happy. */
3445         spin_lock_irq(&dev_priv->irq_lock);
3446         if (dev_priv->display_irqs_enabled)
3447                 valleyview_display_irqs_install(dev_priv);
3448         spin_unlock_irq(&dev_priv->irq_lock);
3449 }
3450
3451 static int valleyview_irq_postinstall(struct drm_device *dev)
3452 {
3453         struct drm_i915_private *dev_priv = dev->dev_private;
3454
3455         vlv_display_irq_postinstall(dev_priv);
3456
3457         gen5_gt_irq_postinstall(dev);
3458
3459         /* ack & enable invalid PTE error interrupts */
3460 #if 0 /* FIXME: add support to irq handler for checking these bits */
3461         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3462         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3463 #endif
3464
3465         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3466
3467         return 0;
3468 }
3469
3470 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3471 {
3472         /* These are interrupts we'll toggle with the ring mask register */
3473         uint32_t gt_interrupts[] = {
3474                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3475                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3476                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3477                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3478                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3479                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3480                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3481                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3482                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3483                 0,
3484                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3485                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3486                 };
3487
3488         dev_priv->pm_irq_mask = 0xffffffff;
3489         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3490         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3491         /*
3492          * RPS interrupts will get enabled/disabled on demand when RPS itself
3493          * is enabled/disabled.
3494          */
3495         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3496         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3497 }
3498
3499 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3500 {
3501         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3502         uint32_t de_pipe_enables;
3503         int pipe;
3504         u32 aux_en = GEN8_AUX_CHANNEL_A;
3505
3506         if (IS_GEN9(dev_priv)) {
3507                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3508                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3509                 aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3510                         GEN9_AUX_CHANNEL_D;
3511         } else
3512                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3513                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3514
3515         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3516                                            GEN8_PIPE_FIFO_UNDERRUN;
3517
3518         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3519         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3520         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3521
3522         for_each_pipe(dev_priv, pipe)
3523                 if (intel_display_power_is_enabled(dev_priv,
3524                                 POWER_DOMAIN_PIPE(pipe)))
3525                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3526                                           dev_priv->de_irq_mask[pipe],
3527                                           de_pipe_enables);
3528
3529         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
3530 }
3531
3532 static int gen8_irq_postinstall(struct drm_device *dev)
3533 {
3534         struct drm_i915_private *dev_priv = dev->dev_private;
3535
3536         ibx_irq_pre_postinstall(dev);
3537
3538         gen8_gt_irq_postinstall(dev_priv);
3539         gen8_de_irq_postinstall(dev_priv);
3540
3541         ibx_irq_postinstall(dev);
3542
3543         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3544         POSTING_READ(GEN8_MASTER_IRQ);
3545
3546         return 0;
3547 }
3548
3549 static int cherryview_irq_postinstall(struct drm_device *dev)
3550 {
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552
3553         vlv_display_irq_postinstall(dev_priv);
3554
3555         gen8_gt_irq_postinstall(dev_priv);
3556
3557         I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3558         POSTING_READ(GEN8_MASTER_IRQ);
3559
3560         return 0;
3561 }
3562
3563 static void gen8_irq_uninstall(struct drm_device *dev)
3564 {
3565         struct drm_i915_private *dev_priv = dev->dev_private;
3566
3567         if (!dev_priv)
3568                 return;
3569
3570         gen8_irq_reset(dev);
3571 }
3572
3573 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3574 {
3575         /* Interrupt setup is already guaranteed to be single-threaded, this is
3576          * just to make the assert_spin_locked check happy. */
3577         spin_lock_irq(&dev_priv->irq_lock);
3578         if (dev_priv->display_irqs_enabled)
3579                 valleyview_display_irqs_uninstall(dev_priv);
3580         spin_unlock_irq(&dev_priv->irq_lock);
3581
3582         vlv_display_irq_reset(dev_priv);
3583
3584         dev_priv->irq_mask = ~0;
3585 }
3586
3587 static void valleyview_irq_uninstall(struct drm_device *dev)
3588 {
3589         struct drm_i915_private *dev_priv = dev->dev_private;
3590
3591         if (!dev_priv)
3592                 return;
3593
3594         I915_WRITE(VLV_MASTER_IER, 0);
3595
3596         gen5_gt_irq_reset(dev);
3597
3598         I915_WRITE(HWSTAM, 0xffffffff);
3599
3600         vlv_display_irq_uninstall(dev_priv);
3601 }
3602
3603 static void cherryview_irq_uninstall(struct drm_device *dev)
3604 {
3605         struct drm_i915_private *dev_priv = dev->dev_private;
3606
3607         if (!dev_priv)
3608                 return;
3609
3610         I915_WRITE(GEN8_MASTER_IRQ, 0);
3611         POSTING_READ(GEN8_MASTER_IRQ);
3612
3613         gen8_gt_irq_reset(dev_priv);
3614
3615         GEN5_IRQ_RESET(GEN8_PCU_);
3616
3617         vlv_display_irq_uninstall(dev_priv);
3618 }
3619
3620 static void ironlake_irq_uninstall(struct drm_device *dev)
3621 {
3622         struct drm_i915_private *dev_priv = dev->dev_private;
3623
3624         if (!dev_priv)
3625                 return;
3626
3627         ironlake_irq_reset(dev);
3628 }
3629
3630 static void i8xx_irq_preinstall(struct drm_device * dev)
3631 {
3632         struct drm_i915_private *dev_priv = dev->dev_private;
3633         int pipe;
3634
3635         for_each_pipe(dev_priv, pipe)
3636                 I915_WRITE(PIPESTAT(pipe), 0);
3637         I915_WRITE16(IMR, 0xffff);
3638         I915_WRITE16(IER, 0x0);
3639         POSTING_READ16(IER);
3640 }
3641
3642 static int i8xx_irq_postinstall(struct drm_device *dev)
3643 {
3644         struct drm_i915_private *dev_priv = dev->dev_private;
3645
3646         I915_WRITE16(EMR,
3647                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3648
3649         /* Unmask the interrupts that we always want on. */
3650         dev_priv->irq_mask =
3651                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3652                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3653                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3654                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3655                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3656         I915_WRITE16(IMR, dev_priv->irq_mask);
3657
3658         I915_WRITE16(IER,
3659                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3660                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3661                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3662                      I915_USER_INTERRUPT);
3663         POSTING_READ16(IER);
3664
3665         /* Interrupt setup is already guaranteed to be single-threaded, this is
3666          * just to make the assert_spin_locked check happy. */
3667         spin_lock_irq(&dev_priv->irq_lock);
3668         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3669         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3670         spin_unlock_irq(&dev_priv->irq_lock);
3671
3672         return 0;
3673 }
3674
3675 /*
3676  * Returns true when a page flip has completed.
3677  */
3678 static bool i8xx_handle_vblank(struct drm_device *dev,
3679                                int plane, int pipe, u32 iir)
3680 {
3681         struct drm_i915_private *dev_priv = dev->dev_private;
3682         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3683
3684         if (!intel_pipe_handle_vblank(dev, pipe))
3685                 return false;
3686
3687         if ((iir & flip_pending) == 0)
3688                 goto check_page_flip;
3689
3690         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3691          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3692          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3693          * the flip is completed (no longer pending). Since this doesn't raise
3694          * an interrupt per se, we watch for the change at vblank.
3695          */
3696         if (I915_READ16(ISR) & flip_pending)
3697                 goto check_page_flip;
3698
3699         intel_prepare_page_flip(dev, plane);
3700         intel_finish_page_flip(dev, pipe);
3701         return true;
3702
3703 check_page_flip:
3704         intel_check_page_flip(dev, pipe);
3705         return false;
3706 }
3707
3708 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3709 {
3710         struct drm_device *dev = arg;
3711         struct drm_i915_private *dev_priv = dev->dev_private;
3712         u16 iir, new_iir;
3713         u32 pipe_stats[2];
3714         int pipe;
3715         u16 flip_mask =
3716                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3717                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3718
3719         iir = I915_READ16(IIR);
3720         if (iir == 0)
3721                 return IRQ_NONE;
3722
3723         while (iir & ~flip_mask) {
3724                 /* Can't rely on pipestat interrupt bit in iir as it might
3725                  * have been cleared after the pipestat interrupt was received.
3726                  * It doesn't set the bit in iir again, but it still produces
3727                  * interrupts (for non-MSI).
3728                  */
3729                 spin_lock(&dev_priv->irq_lock);
3730                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3731                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3732
3733                 for_each_pipe(dev_priv, pipe) {
3734                         int reg = PIPESTAT(pipe);
3735                         pipe_stats[pipe] = I915_READ(reg);
3736
3737                         /*
3738                          * Clear the PIPE*STAT regs before the IIR
3739                          */
3740                         if (pipe_stats[pipe] & 0x8000ffff)
3741                                 I915_WRITE(reg, pipe_stats[pipe]);
3742                 }
3743                 spin_unlock(&dev_priv->irq_lock);
3744
3745                 I915_WRITE16(IIR, iir & ~flip_mask);
3746                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3747
3748                 if (iir & I915_USER_INTERRUPT)
3749                         notify_ring(dev, &dev_priv->ring[RCS]);
3750
3751                 for_each_pipe(dev_priv, pipe) {
3752                         int plane = pipe;
3753                         if (HAS_FBC(dev))
3754                                 plane = !plane;
3755
3756                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3757                             i8xx_handle_vblank(dev, plane, pipe, iir))
3758                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3759
3760                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3761                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3762
3763                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3764                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3765                                                                     pipe);
3766                 }
3767
3768                 iir = new_iir;
3769         }
3770
3771         return IRQ_HANDLED;
3772 }
3773
3774 static void i8xx_irq_uninstall(struct drm_device * dev)
3775 {
3776         struct drm_i915_private *dev_priv = dev->dev_private;
3777         int pipe;
3778
3779         for_each_pipe(dev_priv, pipe) {
3780                 /* Clear enable bits; then clear status bits */
3781                 I915_WRITE(PIPESTAT(pipe), 0);
3782                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3783         }
3784         I915_WRITE16(IMR, 0xffff);
3785         I915_WRITE16(IER, 0x0);
3786         I915_WRITE16(IIR, I915_READ16(IIR));
3787 }
3788
3789 static void i915_irq_preinstall(struct drm_device * dev)
3790 {
3791         struct drm_i915_private *dev_priv = dev->dev_private;
3792         int pipe;
3793
3794         if (I915_HAS_HOTPLUG(dev)) {
3795                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3796                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3797         }
3798
3799         I915_WRITE16(HWSTAM, 0xeffe);
3800         for_each_pipe(dev_priv, pipe)
3801                 I915_WRITE(PIPESTAT(pipe), 0);
3802         I915_WRITE(IMR, 0xffffffff);
3803         I915_WRITE(IER, 0x0);
3804         POSTING_READ(IER);
3805 }
3806
3807 static int i915_irq_postinstall(struct drm_device *dev)
3808 {
3809         struct drm_i915_private *dev_priv = dev->dev_private;
3810         u32 enable_mask;
3811
3812         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3813
3814         /* Unmask the interrupts that we always want on. */
3815         dev_priv->irq_mask =
3816                 ~(I915_ASLE_INTERRUPT |
3817                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3818                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3819                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3820                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3821                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3822
3823         enable_mask =
3824                 I915_ASLE_INTERRUPT |
3825                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3826                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3827                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3828                 I915_USER_INTERRUPT;
3829
3830         if (I915_HAS_HOTPLUG(dev)) {
3831                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3832                 POSTING_READ(PORT_HOTPLUG_EN);
3833
3834                 /* Enable in IER... */
3835                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3836                 /* and unmask in IMR */
3837                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3838         }
3839
3840         I915_WRITE(IMR, dev_priv->irq_mask);
3841         I915_WRITE(IER, enable_mask);
3842         POSTING_READ(IER);
3843
3844         i915_enable_asle_pipestat(dev);
3845
3846         /* Interrupt setup is already guaranteed to be single-threaded, this is
3847          * just to make the assert_spin_locked check happy. */
3848         spin_lock_irq(&dev_priv->irq_lock);
3849         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3850         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3851         spin_unlock_irq(&dev_priv->irq_lock);
3852
3853         return 0;
3854 }
3855
3856 /*
3857  * Returns true when a page flip has completed.
3858  */
3859 static bool i915_handle_vblank(struct drm_device *dev,
3860                                int plane, int pipe, u32 iir)
3861 {
3862         struct drm_i915_private *dev_priv = dev->dev_private;
3863         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3864
3865         if (!intel_pipe_handle_vblank(dev, pipe))
3866                 return false;
3867
3868         if ((iir & flip_pending) == 0)
3869                 goto check_page_flip;
3870
3871         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3872          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3873          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3874          * the flip is completed (no longer pending). Since this doesn't raise
3875          * an interrupt per se, we watch for the change at vblank.
3876          */
3877         if (I915_READ(ISR) & flip_pending)
3878                 goto check_page_flip;
3879
3880         intel_prepare_page_flip(dev, plane);
3881         intel_finish_page_flip(dev, pipe);
3882         return true;
3883
3884 check_page_flip:
3885         intel_check_page_flip(dev, pipe);
3886         return false;
3887 }
3888
3889 static irqreturn_t i915_irq_handler(int irq, void *arg)
3890 {
3891         struct drm_device *dev = arg;
3892         struct drm_i915_private *dev_priv = dev->dev_private;
3893         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3894         u32 flip_mask =
3895                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3896                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3897         int pipe, ret = IRQ_NONE;
3898
3899         iir = I915_READ(IIR);
3900         do {
3901                 bool irq_received = (iir & ~flip_mask) != 0;
3902                 bool blc_event = false;
3903
3904                 /* Can't rely on pipestat interrupt bit in iir as it might
3905                  * have been cleared after the pipestat interrupt was received.
3906                  * It doesn't set the bit in iir again, but it still produces
3907                  * interrupts (for non-MSI).
3908                  */
3909                 spin_lock(&dev_priv->irq_lock);
3910                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3911                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3912
3913                 for_each_pipe(dev_priv, pipe) {
3914                         int reg = PIPESTAT(pipe);
3915                         pipe_stats[pipe] = I915_READ(reg);
3916
3917                         /* Clear the PIPE*STAT regs before the IIR */
3918                         if (pipe_stats[pipe] & 0x8000ffff) {
3919                                 I915_WRITE(reg, pipe_stats[pipe]);
3920                                 irq_received = true;
3921                         }
3922                 }
3923                 spin_unlock(&dev_priv->irq_lock);
3924
3925                 if (!irq_received)
3926                         break;
3927
3928                 /* Consume port.  Then clear IIR or we'll miss events */
3929                 if (I915_HAS_HOTPLUG(dev) &&
3930                     iir & I915_DISPLAY_PORT_INTERRUPT)
3931                         i9xx_hpd_irq_handler(dev);
3932
3933                 I915_WRITE(IIR, iir & ~flip_mask);
3934                 new_iir = I915_READ(IIR); /* Flush posted writes */
3935
3936                 if (iir & I915_USER_INTERRUPT)
3937                         notify_ring(dev, &dev_priv->ring[RCS]);
3938
3939                 for_each_pipe(dev_priv, pipe) {
3940                         int plane = pipe;
3941                         if (HAS_FBC(dev))
3942                                 plane = !plane;
3943
3944                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3945                             i915_handle_vblank(dev, plane, pipe, iir))
3946                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3947
3948                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3949                                 blc_event = true;
3950
3951                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3952                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3953
3954                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3955                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3956                                                                     pipe);
3957                 }
3958
3959                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3960                         intel_opregion_asle_intr(dev);
3961
3962                 /* With MSI, interrupts are only generated when iir
3963                  * transitions from zero to nonzero.  If another bit got
3964                  * set while we were handling the existing iir bits, then
3965                  * we would never get another interrupt.
3966                  *
3967                  * This is fine on non-MSI as well, as if we hit this path
3968                  * we avoid exiting the interrupt handler only to generate
3969                  * another one.
3970                  *
3971                  * Note that for MSI this could cause a stray interrupt report
3972                  * if an interrupt landed in the time between writing IIR and
3973                  * the posting read.  This should be rare enough to never
3974                  * trigger the 99% of 100,000 interrupts test for disabling
3975                  * stray interrupts.
3976                  */
3977                 ret = IRQ_HANDLED;
3978                 iir = new_iir;
3979         } while (iir & ~flip_mask);
3980
3981         return ret;
3982 }
3983
3984 static void i915_irq_uninstall(struct drm_device * dev)
3985 {
3986         struct drm_i915_private *dev_priv = dev->dev_private;
3987         int pipe;
3988
3989         if (I915_HAS_HOTPLUG(dev)) {
3990                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3991                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3992         }
3993
3994         I915_WRITE16(HWSTAM, 0xffff);
3995         for_each_pipe(dev_priv, pipe) {
3996                 /* Clear enable bits; then clear status bits */
3997                 I915_WRITE(PIPESTAT(pipe), 0);
3998                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3999         }
4000         I915_WRITE(IMR, 0xffffffff);
4001         I915_WRITE(IER, 0x0);
4002
4003         I915_WRITE(IIR, I915_READ(IIR));
4004 }
4005
4006 static void i965_irq_preinstall(struct drm_device * dev)
4007 {
4008         struct drm_i915_private *dev_priv = dev->dev_private;
4009         int pipe;
4010
4011         I915_WRITE(PORT_HOTPLUG_EN, 0);
4012         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4013
4014         I915_WRITE(HWSTAM, 0xeffe);
4015         for_each_pipe(dev_priv, pipe)
4016                 I915_WRITE(PIPESTAT(pipe), 0);
4017         I915_WRITE(IMR, 0xffffffff);
4018         I915_WRITE(IER, 0x0);
4019         POSTING_READ(IER);
4020 }
4021
4022 static int i965_irq_postinstall(struct drm_device *dev)
4023 {
4024         struct drm_i915_private *dev_priv = dev->dev_private;
4025         u32 enable_mask;
4026         u32 error_mask;
4027
4028         /* Unmask the interrupts that we always want on. */
4029         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4030                                I915_DISPLAY_PORT_INTERRUPT |
4031                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4032                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4033                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4034                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4035                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4036
4037         enable_mask = ~dev_priv->irq_mask;
4038         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4039                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4040         enable_mask |= I915_USER_INTERRUPT;
4041
4042         if (IS_G4X(dev))
4043                 enable_mask |= I915_BSD_USER_INTERRUPT;
4044
4045         /* Interrupt setup is already guaranteed to be single-threaded, this is
4046          * just to make the assert_spin_locked check happy. */
4047         spin_lock_irq(&dev_priv->irq_lock);
4048         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4049         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4050         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4051         spin_unlock_irq(&dev_priv->irq_lock);
4052
4053         /*
4054          * Enable some error detection, note the instruction error mask
4055          * bit is reserved, so we leave it masked.
4056          */
4057         if (IS_G4X(dev)) {
4058                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4059                                GM45_ERROR_MEM_PRIV |
4060                                GM45_ERROR_CP_PRIV |
4061                                I915_ERROR_MEMORY_REFRESH);
4062         } else {
4063                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4064                                I915_ERROR_MEMORY_REFRESH);
4065         }
4066         I915_WRITE(EMR, error_mask);
4067
4068         I915_WRITE(IMR, dev_priv->irq_mask);
4069         I915_WRITE(IER, enable_mask);
4070         POSTING_READ(IER);
4071
4072         I915_WRITE(PORT_HOTPLUG_EN, 0);
4073         POSTING_READ(PORT_HOTPLUG_EN);
4074
4075         i915_enable_asle_pipestat(dev);
4076
4077         return 0;
4078 }
4079
4080 static void i915_hpd_irq_setup(struct drm_device *dev)
4081 {
4082         struct drm_i915_private *dev_priv = dev->dev_private;
4083         struct intel_encoder *intel_encoder;
4084         u32 hotplug_en;
4085
4086         assert_spin_locked(&dev_priv->irq_lock);
4087
4088         hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4089         hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4090         /* Note HDMI and DP share hotplug bits */
4091         /* enable bits are the same for all generations */
4092         for_each_intel_encoder(dev, intel_encoder)
4093                 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4094                         hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4095         /* Programming the CRT detection parameters tends
4096            to generate a spurious hotplug event about three
4097            seconds later.  So just do it once.
4098         */
4099         if (IS_G4X(dev))
4100                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4101         hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4102         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4103
4104         /* Ignore TV since it's buggy */
4105         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4106 }
4107
4108 static irqreturn_t i965_irq_handler(int irq, void *arg)
4109 {
4110         struct drm_device *dev = arg;
4111         struct drm_i915_private *dev_priv = dev->dev_private;
4112         u32 iir, new_iir;
4113         u32 pipe_stats[I915_MAX_PIPES];
4114         int ret = IRQ_NONE, pipe;
4115         u32 flip_mask =
4116                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4117                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4118
4119         iir = I915_READ(IIR);
4120
4121         for (;;) {
4122                 bool irq_received = (iir & ~flip_mask) != 0;
4123                 bool blc_event = false;
4124
4125                 /* Can't rely on pipestat interrupt bit in iir as it might
4126                  * have been cleared after the pipestat interrupt was received.
4127                  * It doesn't set the bit in iir again, but it still produces
4128                  * interrupts (for non-MSI).
4129                  */
4130                 spin_lock(&dev_priv->irq_lock);
4131                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4132                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4133
4134                 for_each_pipe(dev_priv, pipe) {
4135                         int reg = PIPESTAT(pipe);
4136                         pipe_stats[pipe] = I915_READ(reg);
4137
4138                         /*
4139                          * Clear the PIPE*STAT regs before the IIR
4140                          */
4141                         if (pipe_stats[pipe] & 0x8000ffff) {
4142                                 I915_WRITE(reg, pipe_stats[pipe]);
4143                                 irq_received = true;
4144                         }
4145                 }
4146                 spin_unlock(&dev_priv->irq_lock);
4147
4148                 if (!irq_received)
4149                         break;
4150
4151                 ret = IRQ_HANDLED;
4152
4153                 /* Consume port.  Then clear IIR or we'll miss events */
4154                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4155                         i9xx_hpd_irq_handler(dev);
4156
4157                 I915_WRITE(IIR, iir & ~flip_mask);
4158                 new_iir = I915_READ(IIR); /* Flush posted writes */
4159
4160                 if (iir & I915_USER_INTERRUPT)
4161                         notify_ring(dev, &dev_priv->ring[RCS]);
4162                 if (iir & I915_BSD_USER_INTERRUPT)
4163                         notify_ring(dev, &dev_priv->ring[VCS]);
4164
4165                 for_each_pipe(dev_priv, pipe) {
4166                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4167                             i915_handle_vblank(dev, pipe, pipe, iir))
4168                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4169
4170                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4171                                 blc_event = true;
4172
4173                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4174                                 i9xx_pipe_crc_irq_handler(dev, pipe);
4175
4176                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4177                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4178                 }
4179
4180                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4181                         intel_opregion_asle_intr(dev);
4182
4183                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4184                         gmbus_irq_handler(dev);
4185
4186                 /* With MSI, interrupts are only generated when iir
4187                  * transitions from zero to nonzero.  If another bit got
4188                  * set while we were handling the existing iir bits, then
4189                  * we would never get another interrupt.
4190                  *
4191                  * This is fine on non-MSI as well, as if we hit this path
4192                  * we avoid exiting the interrupt handler only to generate
4193                  * another one.
4194                  *
4195                  * Note that for MSI this could cause a stray interrupt report
4196                  * if an interrupt landed in the time between writing IIR and
4197                  * the posting read.  This should be rare enough to never
4198                  * trigger the 99% of 100,000 interrupts test for disabling
4199                  * stray interrupts.
4200                  */
4201                 iir = new_iir;
4202         }
4203
4204         return ret;
4205 }
4206
4207 static void i965_irq_uninstall(struct drm_device * dev)
4208 {
4209         struct drm_i915_private *dev_priv = dev->dev_private;
4210         int pipe;
4211
4212         if (!dev_priv)
4213                 return;
4214
4215         I915_WRITE(PORT_HOTPLUG_EN, 0);
4216         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4217
4218         I915_WRITE(HWSTAM, 0xffffffff);
4219         for_each_pipe(dev_priv, pipe)
4220                 I915_WRITE(PIPESTAT(pipe), 0);
4221         I915_WRITE(IMR, 0xffffffff);
4222         I915_WRITE(IER, 0x0);
4223
4224         for_each_pipe(dev_priv, pipe)
4225                 I915_WRITE(PIPESTAT(pipe),
4226                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4227         I915_WRITE(IIR, I915_READ(IIR));
4228 }
4229
4230 static void intel_hpd_irq_reenable_work(struct work_struct *work)
4231 {
4232         struct drm_i915_private *dev_priv =
4233                 container_of(work, typeof(*dev_priv),
4234                              hotplug_reenable_work.work);
4235         struct drm_device *dev = dev_priv->dev;
4236         struct drm_mode_config *mode_config = &dev->mode_config;
4237         int i;
4238
4239         intel_runtime_pm_get(dev_priv);
4240
4241         spin_lock_irq(&dev_priv->irq_lock);
4242         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4243                 struct drm_connector *connector;
4244
4245                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4246                         continue;
4247
4248                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4249
4250                 list_for_each_entry(connector, &mode_config->connector_list, head) {
4251                         struct intel_connector *intel_connector = to_intel_connector(connector);
4252
4253                         if (intel_connector->encoder->hpd_pin == i) {
4254                                 if (connector->polled != intel_connector->polled)
4255                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4256                                                          connector->name);
4257                                 connector->polled = intel_connector->polled;
4258                                 if (!connector->polled)
4259                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4260                         }
4261                 }
4262         }
4263         if (dev_priv->display.hpd_irq_setup)
4264                 dev_priv->display.hpd_irq_setup(dev);
4265         spin_unlock_irq(&dev_priv->irq_lock);
4266
4267         intel_runtime_pm_put(dev_priv);
4268 }
4269
4270 /**
4271  * intel_irq_init - initializes irq support
4272  * @dev_priv: i915 device instance
4273  *
4274  * This function initializes all the irq support including work items, timers
4275  * and all the vtables. It does not setup the interrupt itself though.
4276  */
4277 void intel_irq_init(struct drm_i915_private *dev_priv)
4278 {
4279         struct drm_device *dev = dev_priv->dev;
4280
4281         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4282         INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4283         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4284         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4285
4286         /* Let's track the enabled rps events */
4287         if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4288                 /* WaGsvRC0ResidencyMethod:vlv */
4289                 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4290         else
4291                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4292
4293         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4294                           i915_hangcheck_elapsed);
4295         INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4296                           intel_hpd_irq_reenable_work);
4297
4298         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4299
4300         if (IS_GEN2(dev_priv)) {
4301                 dev->max_vblank_count = 0;
4302                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4303         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4304                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4305                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4306         } else {
4307                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4308                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4309         }
4310
4311         /*
4312          * Opt out of the vblank disable timer on everything except gen2.
4313          * Gen2 doesn't have a hardware frame counter and so depends on
4314          * vblank interrupts to produce sane vblank seuquence numbers.
4315          */
4316         if (!IS_GEN2(dev_priv))
4317                 dev->vblank_disable_immediate = true;
4318
4319         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4320                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4321                 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4322         }
4323
4324         if (IS_CHERRYVIEW(dev_priv)) {
4325                 dev->driver->irq_handler = cherryview_irq_handler;
4326                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4327                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4328                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4329                 dev->driver->enable_vblank = valleyview_enable_vblank;
4330                 dev->driver->disable_vblank = valleyview_disable_vblank;
4331                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4332         } else if (IS_VALLEYVIEW(dev_priv)) {
4333                 dev->driver->irq_handler = valleyview_irq_handler;
4334                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4335                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4336                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4337                 dev->driver->enable_vblank = valleyview_enable_vblank;
4338                 dev->driver->disable_vblank = valleyview_disable_vblank;
4339                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4340         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4341                 dev->driver->irq_handler = gen8_irq_handler;
4342                 dev->driver->irq_preinstall = gen8_irq_reset;
4343                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4344                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4345                 dev->driver->enable_vblank = gen8_enable_vblank;
4346                 dev->driver->disable_vblank = gen8_disable_vblank;
4347                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4348         } else if (HAS_PCH_SPLIT(dev)) {
4349                 dev->driver->irq_handler = ironlake_irq_handler;
4350                 dev->driver->irq_preinstall = ironlake_irq_reset;
4351                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4352                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4353                 dev->driver->enable_vblank = ironlake_enable_vblank;
4354                 dev->driver->disable_vblank = ironlake_disable_vblank;
4355                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4356         } else {
4357                 if (INTEL_INFO(dev_priv)->gen == 2) {
4358                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4359                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4360                         dev->driver->irq_handler = i8xx_irq_handler;
4361                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4362                 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4363                         dev->driver->irq_preinstall = i915_irq_preinstall;
4364                         dev->driver->irq_postinstall = i915_irq_postinstall;
4365                         dev->driver->irq_uninstall = i915_irq_uninstall;
4366                         dev->driver->irq_handler = i915_irq_handler;
4367                 } else {
4368                         dev->driver->irq_preinstall = i965_irq_preinstall;
4369                         dev->driver->irq_postinstall = i965_irq_postinstall;
4370                         dev->driver->irq_uninstall = i965_irq_uninstall;
4371                         dev->driver->irq_handler = i965_irq_handler;
4372                 }
4373                 if (I915_HAS_HOTPLUG(dev_priv))
4374                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4375                 dev->driver->enable_vblank = i915_enable_vblank;
4376                 dev->driver->disable_vblank = i915_disable_vblank;
4377         }
4378 }
4379
4380 /**
4381  * intel_hpd_init - initializes and enables hpd support
4382  * @dev_priv: i915 device instance
4383  *
4384  * This function enables the hotplug support. It requires that interrupts have
4385  * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4386  * poll request can run concurrently to other code, so locking rules must be
4387  * obeyed.
4388  *
4389  * This is a separate step from interrupt enabling to simplify the locking rules
4390  * in the driver load and resume code.
4391  */
4392 void intel_hpd_init(struct drm_i915_private *dev_priv)
4393 {
4394         struct drm_device *dev = dev_priv->dev;
4395         struct drm_mode_config *mode_config = &dev->mode_config;
4396         struct drm_connector *connector;
4397         int i;
4398
4399         for (i = 1; i < HPD_NUM_PINS; i++) {
4400                 dev_priv->hpd_stats[i].hpd_cnt = 0;
4401                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4402         }
4403         list_for_each_entry(connector, &mode_config->connector_list, head) {
4404                 struct intel_connector *intel_connector = to_intel_connector(connector);
4405                 connector->polled = intel_connector->polled;
4406                 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4407                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4408                 if (intel_connector->mst_port)
4409                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4410         }
4411
4412         /* Interrupt setup is already guaranteed to be single-threaded, this is
4413          * just to make the assert_spin_locked checks happy. */
4414         spin_lock_irq(&dev_priv->irq_lock);
4415         if (dev_priv->display.hpd_irq_setup)
4416                 dev_priv->display.hpd_irq_setup(dev);
4417         spin_unlock_irq(&dev_priv->irq_lock);
4418 }
4419
4420 /**
4421  * intel_irq_install - enables the hardware interrupt
4422  * @dev_priv: i915 device instance
4423  *
4424  * This function enables the hardware interrupt handling, but leaves the hotplug
4425  * handling still disabled. It is called after intel_irq_init().
4426  *
4427  * In the driver load and resume code we need working interrupts in a few places
4428  * but don't want to deal with the hassle of concurrent probe and hotplug
4429  * workers. Hence the split into this two-stage approach.
4430  */
4431 int intel_irq_install(struct drm_i915_private *dev_priv)
4432 {
4433         /*
4434          * We enable some interrupt sources in our postinstall hooks, so mark
4435          * interrupts as enabled _before_ actually enabling them to avoid
4436          * special cases in our ordering checks.
4437          */
4438         dev_priv->pm.irqs_enabled = true;
4439
4440         return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4441 }
4442
4443 /**
4444  * intel_irq_uninstall - finilizes all irq handling
4445  * @dev_priv: i915 device instance
4446  *
4447  * This stops interrupt and hotplug handling and unregisters and frees all
4448  * resources acquired in the init functions.
4449  */
4450 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4451 {
4452         drm_irq_uninstall(dev_priv->dev);
4453         intel_hpd_cancel_work(dev_priv);
4454         dev_priv->pm.irqs_enabled = false;
4455 }
4456
4457 /**
4458  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4459  * @dev_priv: i915 device instance
4460  *
4461  * This function is used to disable interrupts at runtime, both in the runtime
4462  * pm and the system suspend/resume code.
4463  */
4464 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4465 {
4466         dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4467         dev_priv->pm.irqs_enabled = false;
4468 }
4469
4470 /**
4471  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4472  * @dev_priv: i915 device instance
4473  *
4474  * This function is used to enable interrupts at runtime, both in the runtime
4475  * pm and the system suspend/resume code.
4476  */
4477 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4478 {
4479         dev_priv->pm.irqs_enabled = true;
4480         dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4481         dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4482 }