3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
34 struct drm_i915_private *dev_priv = dev->dev_private;
37 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
39 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
42 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
44 struct drm_i915_private *dev_priv = dev->dev_private;
45 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
49 if (!i915_pipe_enabled(dev, pipe))
53 array = dev_priv->save_palette_a;
55 array = dev_priv->save_palette_b;
57 for(i = 0; i < 256; i++)
58 array[i] = I915_READ(reg + (i << 2));
61 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
63 struct drm_i915_private *dev_priv = dev->dev_private;
64 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
68 if (!i915_pipe_enabled(dev, pipe))
72 array = dev_priv->save_palette_a;
74 array = dev_priv->save_palette_b;
76 for(i = 0; i < 256; i++)
77 I915_WRITE(reg + (i << 2), array[i]);
80 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
82 struct drm_i915_private *dev_priv = dev->dev_private;
84 I915_WRITE8(index_port, reg);
85 return I915_READ8(data_port);
88 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
90 struct drm_i915_private *dev_priv = dev->dev_private;
93 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
94 return I915_READ8(VGA_AR_DATA_READ);
97 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
99 struct drm_i915_private *dev_priv = dev->dev_private;
102 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
103 I915_WRITE8(VGA_AR_DATA_WRITE, val);
106 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
108 struct drm_i915_private *dev_priv = dev->dev_private;
110 I915_WRITE8(index_port, reg);
111 I915_WRITE8(data_port, val);
114 static void i915_save_vga(struct drm_device *dev)
116 struct drm_i915_private *dev_priv = dev->dev_private;
118 u16 cr_index, cr_data, st01;
120 /* VGA color palette registers */
121 dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
124 dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
125 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
126 cr_index = VGA_CR_INDEX_CGA;
127 cr_data = VGA_CR_DATA_CGA;
130 cr_index = VGA_CR_INDEX_MDA;
131 cr_data = VGA_CR_DATA_MDA;
135 /* CRT controller regs */
136 i915_write_indexed(dev, cr_index, cr_data, 0x11,
137 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
139 for (i = 0; i <= 0x24; i++)
140 dev_priv->saveCR[i] =
141 i915_read_indexed(dev, cr_index, cr_data, i);
142 /* Make sure we don't turn off CR group 0 writes */
143 dev_priv->saveCR[0x11] &= ~0x80;
145 /* Attribute controller registers */
147 dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
148 for (i = 0; i <= 0x14; i++)
149 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
151 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
154 /* Graphics controller registers */
155 for (i = 0; i < 9; i++)
156 dev_priv->saveGR[i] =
157 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
159 dev_priv->saveGR[0x10] =
160 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
161 dev_priv->saveGR[0x11] =
162 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
163 dev_priv->saveGR[0x18] =
164 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
166 /* Sequencer registers */
167 for (i = 0; i < 8; i++)
168 dev_priv->saveSR[i] =
169 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
172 static void i915_restore_vga(struct drm_device *dev)
174 struct drm_i915_private *dev_priv = dev->dev_private;
176 u16 cr_index, cr_data, st01;
179 I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
180 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
181 cr_index = VGA_CR_INDEX_CGA;
182 cr_data = VGA_CR_DATA_CGA;
185 cr_index = VGA_CR_INDEX_MDA;
186 cr_data = VGA_CR_DATA_MDA;
190 /* Sequencer registers, don't write SR07 */
191 for (i = 0; i < 7; i++)
192 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
193 dev_priv->saveSR[i]);
195 /* CRT controller regs */
196 /* Enable CR group 0 writes */
197 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
198 for (i = 0; i <= 0x24; i++)
199 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
201 /* Graphics controller regs */
202 for (i = 0; i < 9; i++)
203 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
204 dev_priv->saveGR[i]);
206 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
207 dev_priv->saveGR[0x10]);
208 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
209 dev_priv->saveGR[0x11]);
210 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
211 dev_priv->saveGR[0x18]);
213 /* Attribute controller registers */
214 I915_READ8(st01); /* switch back to index mode */
215 for (i = 0; i <= 0x14; i++)
216 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
217 I915_READ8(st01); /* switch back to index mode */
218 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
221 /* VGA color palette registers */
222 I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
225 static void i915_save_modeset_reg(struct drm_device *dev)
227 struct drm_i915_private *dev_priv = dev->dev_private;
229 if (drm_core_check_feature(dev, DRIVER_MODESET))
232 /* Pipe & plane A info */
233 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
234 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
235 dev_priv->saveFPA0 = I915_READ(FPA0);
236 dev_priv->saveFPA1 = I915_READ(FPA1);
237 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
239 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
240 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
241 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
242 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
243 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
244 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
245 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
246 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
248 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
249 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
250 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
251 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
252 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
254 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
255 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
257 i915_save_palette(dev, PIPE_A);
258 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
260 /* Pipe & plane B info */
261 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
262 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
263 dev_priv->saveFPB0 = I915_READ(FPB0);
264 dev_priv->saveFPB1 = I915_READ(FPB1);
265 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
267 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
268 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
269 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
270 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
271 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
272 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
273 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
274 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
276 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
277 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
278 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
279 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
280 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
281 if (IS_I965GM(dev) || IS_GM45(dev)) {
282 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
283 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
285 i915_save_palette(dev, PIPE_B);
286 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
290 static void i915_restore_modeset_reg(struct drm_device *dev)
292 struct drm_i915_private *dev_priv = dev->dev_private;
294 if (drm_core_check_feature(dev, DRIVER_MODESET))
297 /* Pipe & plane A info */
298 /* Prime the clock */
299 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
300 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
304 I915_WRITE(FPA0, dev_priv->saveFPA0);
305 I915_WRITE(FPA1, dev_priv->saveFPA1);
306 /* Actually enable it */
307 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
310 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
314 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
315 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
316 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
317 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
318 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
319 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
320 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
322 /* Restore plane info */
323 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
324 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
325 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
326 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
327 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
329 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
330 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
333 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
335 i915_restore_palette(dev, PIPE_A);
336 /* Enable the plane */
337 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
338 I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
340 /* Pipe & plane B info */
341 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
342 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
346 I915_WRITE(FPB0, dev_priv->saveFPB0);
347 I915_WRITE(FPB1, dev_priv->saveFPB1);
348 /* Actually enable it */
349 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
352 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
356 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
357 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
358 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
359 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
360 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
361 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
362 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
364 /* Restore plane info */
365 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
366 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
367 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
368 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
369 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
371 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
372 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
375 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
377 i915_restore_palette(dev, PIPE_B);
378 /* Enable the plane */
379 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
380 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
385 void i915_save_display(struct drm_device *dev)
387 struct drm_i915_private *dev_priv = dev->dev_private;
389 /* Display arbitration control */
390 dev_priv->saveDSPARB = I915_READ(DSPARB);
392 /* This is only meaningful in non-KMS mode */
393 /* Don't save them in KMS mode */
394 i915_save_modeset_reg(dev);
397 dev_priv->saveCURACNTR = I915_READ(CURACNTR);
398 dev_priv->saveCURAPOS = I915_READ(CURAPOS);
399 dev_priv->saveCURABASE = I915_READ(CURABASE);
400 dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
401 dev_priv->saveCURBPOS = I915_READ(CURBPOS);
402 dev_priv->saveCURBBASE = I915_READ(CURBBASE);
404 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
407 dev_priv->saveADPA = I915_READ(ADPA);
410 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
411 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
412 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
413 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
415 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
416 if (IS_MOBILE(dev) && !IS_I830(dev))
417 dev_priv->saveLVDS = I915_READ(LVDS);
418 if (!IS_I830(dev) && !IS_845G(dev))
419 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
420 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
421 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
422 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
424 /* Display Port state */
425 if (SUPPORTS_INTEGRATED_DP(dev)) {
426 dev_priv->saveDP_B = I915_READ(DP_B);
427 dev_priv->saveDP_C = I915_READ(DP_C);
428 dev_priv->saveDP_D = I915_READ(DP_D);
429 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
430 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
431 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
432 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
433 dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
434 dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
435 dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
436 dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
438 /* FIXME: save TV & SDVO state */
442 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
444 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
445 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
446 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
447 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
451 dev_priv->saveVGA0 = I915_READ(VGA0);
452 dev_priv->saveVGA1 = I915_READ(VGA1);
453 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
454 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
459 void i915_restore_display(struct drm_device *dev)
461 struct drm_i915_private *dev_priv = dev->dev_private;
463 /* Display arbitration */
464 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
466 /* Display port ratios (must be done before clock is set) */
467 if (SUPPORTS_INTEGRATED_DP(dev)) {
468 I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
469 I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
470 I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
471 I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
472 I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
473 I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
474 I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
475 I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
478 /* This is only meaningful in non-KMS mode */
479 /* Don't restore them in KMS mode */
480 i915_restore_modeset_reg(dev);
483 I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
484 I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
485 I915_WRITE(CURABASE, dev_priv->saveCURABASE);
486 I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
487 I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
488 I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
490 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
493 I915_WRITE(ADPA, dev_priv->saveADPA);
497 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
498 if (IS_MOBILE(dev) && !IS_I830(dev))
499 I915_WRITE(LVDS, dev_priv->saveLVDS);
500 if (!IS_I830(dev) && !IS_845G(dev))
501 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
503 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
504 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
505 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
506 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
507 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
508 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
509 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
511 /* Display Port state */
512 if (SUPPORTS_INTEGRATED_DP(dev)) {
513 I915_WRITE(DP_B, dev_priv->saveDP_B);
514 I915_WRITE(DP_C, dev_priv->saveDP_C);
515 I915_WRITE(DP_D, dev_priv->saveDP_D);
517 /* FIXME: restore TV & SDVO state */
521 g4x_disable_fbc(dev);
522 I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
524 i8xx_disable_fbc(dev);
525 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
526 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
527 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
528 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
532 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
533 I915_WRITE(VGA0, dev_priv->saveVGA0);
534 I915_WRITE(VGA1, dev_priv->saveVGA1);
535 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
538 i915_restore_vga(dev);
541 int i915_save_state(struct drm_device *dev)
543 struct drm_i915_private *dev_priv = dev->dev_private;
546 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
549 if (IS_I965G(dev) && IS_MOBILE(dev))
550 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
552 /* Hardware status page */
553 dev_priv->saveHWS = I915_READ(HWS_PGA);
555 i915_save_display(dev);
557 /* Interrupt state */
558 dev_priv->saveIER = I915_READ(IER);
559 dev_priv->saveIMR = I915_READ(IMR);
561 /* Clock gating state */
562 dev_priv->saveD_STATE = I915_READ(D_STATE);
563 dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Not sure about this */
565 /* Cache mode state */
566 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
568 /* Memory Arbitration state */
569 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
572 for (i = 0; i < 16; i++) {
573 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
574 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
576 for (i = 0; i < 3; i++)
577 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
581 for (i = 0; i < 16; i++)
582 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
584 for (i = 0; i < 8; i++)
585 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
587 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
588 for (i = 0; i < 8; i++)
589 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
595 int i915_restore_state(struct drm_device *dev)
597 struct drm_i915_private *dev_priv = dev->dev_private;
600 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
603 if (IS_I965G(dev) && IS_MOBILE(dev))
604 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
606 /* Hardware status page */
607 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
611 for (i = 0; i < 16; i++)
612 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
614 for (i = 0; i < 8; i++)
615 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
616 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
617 for (i = 0; i < 8; i++)
618 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
621 i915_restore_display(dev);
623 /* Interrupt state */
624 I915_WRITE (IER, dev_priv->saveIER);
625 I915_WRITE (IMR, dev_priv->saveIMR);
627 /* Clock gating state */
628 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
629 I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
631 /* Cache mode state */
632 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
634 /* Memory arbitration state */
635 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
637 for (i = 0; i < 16; i++) {
638 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
639 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
641 for (i = 0; i < 3; i++)
642 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);