drivers/gpu/drm/i915/i915_suspend.c

   1 /*
   2  *
   3  * Copyright 2008 (c) Intel Corporation
   4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "i915_drm.h"
  30 #include "intel_drv.h"
  31 #include "i915_reg.h"
  32
  33 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  34 {
  35         struct drm_i915_private *dev_priv = dev->dev_private;
  36         u32     dpll_reg;
  37
  38         if (HAS_PCH_SPLIT(dev))
  39                 dpll_reg = PCH_DPLL(pipe);
  40         else
  41                 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
  42
  43         return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
  44 }
  45
  46 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  47 {
  48         struct drm_i915_private *dev_priv = dev->dev_private;
  49         unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
  50         u32 *array;
  51         int i;
  52
  53         if (!i915_pipe_enabled(dev, pipe))
  54                 return;
  55
  56         if (HAS_PCH_SPLIT(dev))
  57                 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
  58
  59         if (pipe == PIPE_A)
  60                 array = dev_priv->save_palette_a;
  61         else
  62                 array = dev_priv->save_palette_b;
  63
  64         for (i = 0; i < 256; i++)
  65                 array[i] = I915_READ(reg + (i << 2));
  66 }
  67
  68 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71         unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
  72         u32 *array;
  73         int i;
  74
  75         if (!i915_pipe_enabled(dev, pipe))
  76                 return;
  77
  78         if (HAS_PCH_SPLIT(dev))
  79                 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
  80
  81         if (pipe == PIPE_A)
  82                 array = dev_priv->save_palette_a;
  83         else
  84                 array = dev_priv->save_palette_b;
  85
  86         for (i = 0; i < 256; i++)
  87                 I915_WRITE(reg + (i << 2), array[i]);
  88 }
  89
  90 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
  91 {
  92         struct drm_i915_private *dev_priv = dev->dev_private;
  93
  94         I915_WRITE8(index_port, reg);
  95         return I915_READ8(data_port);
  96 }
  97
  98 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
  99 {
 100         struct drm_i915_private *dev_priv = dev->dev_private;
 101
 102         I915_READ8(st01);
 103         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
 104         return I915_READ8(VGA_AR_DATA_READ);
 105 }
 106
 107 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
 108 {
 109         struct drm_i915_private *dev_priv = dev->dev_private;
 110
 111         I915_READ8(st01);
 112         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
 113         I915_WRITE8(VGA_AR_DATA_WRITE, val);
 114 }
 115
 116 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
 117 {
 118         struct drm_i915_private *dev_priv = dev->dev_private;
 119
 120         I915_WRITE8(index_port, reg);
 121         I915_WRITE8(data_port, val);
 122 }
 123
 124 static void i915_save_vga(struct drm_device *dev)
 125 {
 126         struct drm_i915_private *dev_priv = dev->dev_private;
 127         int i;
 128         u16 cr_index, cr_data, st01;
 129
 130         /* VGA color palette registers */
 131         dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
 132
 133         /* MSR bits */
 134         dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
 135         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 136                 cr_index = VGA_CR_INDEX_CGA;
 137                 cr_data = VGA_CR_DATA_CGA;
 138                 st01 = VGA_ST01_CGA;
 139         } else {
 140                 cr_index = VGA_CR_INDEX_MDA;
 141                 cr_data = VGA_CR_DATA_MDA;
 142                 st01 = VGA_ST01_MDA;
 143         }
 144
 145         /* CRT controller regs */
 146         i915_write_indexed(dev, cr_index, cr_data, 0x11,
 147                            i915_read_indexed(dev, cr_index, cr_data, 0x11) &
 148                            (~0x80));
 149         for (i = 0; i <= 0x24; i++)
 150                 dev_priv->saveCR[i] =
 151                         i915_read_indexed(dev, cr_index, cr_data, i);
 152         /* Make sure we don't turn off CR group 0 writes */
 153         dev_priv->saveCR[0x11] &= ~0x80;
 154
 155         /* Attribute controller registers */
 156         I915_READ8(st01);
 157         dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
 158         for (i = 0; i <= 0x14; i++)
 159                 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
 160         I915_READ8(st01);
 161         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
 162         I915_READ8(st01);
 163
 164         /* Graphics controller registers */
 165         for (i = 0; i < 9; i++)
 166                 dev_priv->saveGR[i] =
 167                         i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
 168
 169         dev_priv->saveGR[0x10] =
 170                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 171         dev_priv->saveGR[0x11] =
 172                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 173         dev_priv->saveGR[0x18] =
 174                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 175
 176         /* Sequencer registers */
 177         for (i = 0; i < 8; i++)
 178                 dev_priv->saveSR[i] =
 179                         i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
 180 }
 181
 182 static void i915_restore_vga(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         int i;
 186         u16 cr_index, cr_data, st01;
 187
 188         /* MSR bits */
 189         I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
 190         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 191                 cr_index = VGA_CR_INDEX_CGA;
 192                 cr_data = VGA_CR_DATA_CGA;
 193                 st01 = VGA_ST01_CGA;
 194         } else {
 195                 cr_index = VGA_CR_INDEX_MDA;
 196                 cr_data = VGA_CR_DATA_MDA;
 197                 st01 = VGA_ST01_MDA;
 198         }
 199
 200         /* Sequencer registers, don't write SR07 */
 201         for (i = 0; i < 7; i++)
 202                 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
 203                                    dev_priv->saveSR[i]);
 204
 205         /* CRT controller regs */
 206         /* Enable CR group 0 writes */
 207         i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 208         for (i = 0; i <= 0x24; i++)
 209                 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
 210
 211         /* Graphics controller regs */
 212         for (i = 0; i < 9; i++)
 213                 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
 214                                    dev_priv->saveGR[i]);
 215
 216         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 217                            dev_priv->saveGR[0x10]);
 218         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 219                            dev_priv->saveGR[0x11]);
 220         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 221                            dev_priv->saveGR[0x18]);
 222
 223         /* Attribute controller registers */
 224         I915_READ8(st01); /* switch back to index mode */
 225         for (i = 0; i <= 0x14; i++)
 226                 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
 227         I915_READ8(st01); /* switch back to index mode */
 228         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
 229         I915_READ8(st01);
 230
 231         /* VGA color palette registers */
 232         I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
 233 }
 234
 235 static void i915_save_modeset_reg(struct drm_device *dev)
 236 {
 237         struct drm_i915_private *dev_priv = dev->dev_private;
 238         int i;
 239
 240         if (drm_core_check_feature(dev, DRIVER_MODESET))
 241                 return;
 242
 243         /* Cursor state */
 244         dev_priv->saveCURACNTR = I915_READ(_CURACNTR);
 245         dev_priv->saveCURAPOS = I915_READ(_CURAPOS);
 246         dev_priv->saveCURABASE = I915_READ(_CURABASE);
 247         dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR);
 248         dev_priv->saveCURBPOS = I915_READ(_CURBPOS);
 249         dev_priv->saveCURBBASE = I915_READ(_CURBBASE);
 250         if (IS_GEN2(dev))
 251                 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
 252
 253         if (HAS_PCH_SPLIT(dev)) {
 254                 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
 255                 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
 256         }
 257
 258         /* Pipe & plane A info */
 259         dev_priv->savePIPEACONF = I915_READ(_PIPEACONF);
 260         dev_priv->savePIPEASRC = I915_READ(_PIPEASRC);
 261         if (HAS_PCH_SPLIT(dev)) {
 262                 dev_priv->saveFPA0 = I915_READ(_PCH_FPA0);
 263                 dev_priv->saveFPA1 = I915_READ(_PCH_FPA1);
 264                 dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A);
 265         } else {
 266                 dev_priv->saveFPA0 = I915_READ(_FPA0);
 267                 dev_priv->saveFPA1 = I915_READ(_FPA1);
 268                 dev_priv->saveDPLL_A = I915_READ(_DPLL_A);
 269         }
 270         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
 271                 dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
 272         dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A);
 273         dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A);
 274         dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A);
 275         dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A);
 276         dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A);
 277         dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A);
 278         if (!HAS_PCH_SPLIT(dev))
 279                 dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
 280
 281         if (HAS_PCH_SPLIT(dev)) {
 282                 dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
 283                 dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
 284                 dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
 285                 dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
 286
 287                 dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
 288                 dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
 289
 290                 dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
 291                 dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
 292                 dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
 293
 294                 dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF);
 295                 dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
 296                 dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
 297                 dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
 298                 dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
 299                 dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
 300                 dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
 301         }
 302
 303         dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR);
 304         dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
 305         dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE);
 306         dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS);
 307         dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR);
 308         if (INTEL_INFO(dev)->gen >= 4) {
 309                 dev_priv->saveDSPASURF = I915_READ(_DSPASURF);
 310                 dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
 311         }
 312         i915_save_palette(dev, PIPE_A);
 313         dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT);
 314
 315         /* Pipe & plane B info */
 316         dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF);
 317         dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC);
 318         if (HAS_PCH_SPLIT(dev)) {
 319                 dev_priv->saveFPB0 = I915_READ(_PCH_FPB0);
 320                 dev_priv->saveFPB1 = I915_READ(_PCH_FPB1);
 321                 dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B);
 322         } else {
 323                 dev_priv->saveFPB0 = I915_READ(_FPB0);
 324                 dev_priv->saveFPB1 = I915_READ(_FPB1);
 325                 dev_priv->saveDPLL_B = I915_READ(_DPLL_B);
 326         }
 327         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
 328                 dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
 329         dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B);
 330         dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B);
 331         dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B);
 332         dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B);
 333         dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B);
 334         dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B);
 335         if (!HAS_PCH_SPLIT(dev))
 336                 dev_priv->saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
 337
 338         if (HAS_PCH_SPLIT(dev)) {
 339                 dev_priv->savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
 340                 dev_priv->savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
 341                 dev_priv->savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
 342                 dev_priv->savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
 343
 344                 dev_priv->saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
 345                 dev_priv->saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
 346
 347                 dev_priv->savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
 348                 dev_priv->savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
 349                 dev_priv->savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
 350
 351                 dev_priv->saveTRANSBCONF = I915_READ(_TRANSBCONF);
 352                 dev_priv->saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
 353                 dev_priv->saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
 354                 dev_priv->saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
 355                 dev_priv->saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
 356                 dev_priv->saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
 357                 dev_priv->saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
 358         }
 359
 360         dev_priv->saveDSPBCNTR = I915_READ(_DSPBCNTR);
 361         dev_priv->saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
 362         dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE);
 363         dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS);
 364         dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR);
 365         if (INTEL_INFO(dev)->gen >= 4) {
 366                 dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF);
 367                 dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
 368         }
 369         i915_save_palette(dev, PIPE_B);
 370         dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT);
 371
 372         /* Fences */
 373         switch (INTEL_INFO(dev)->gen) {
 374         case 7:
 375         case 6:
 376                 for (i = 0; i < 16; i++)
 377                         dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 378                 break;
 379         case 5:
 380         case 4:
 381                 for (i = 0; i < 16; i++)
 382                         dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 383                 break;
 384         case 3:
 385                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 386                         for (i = 0; i < 8; i++)
 387                                 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 388         case 2:
 389                 for (i = 0; i < 8; i++)
 390                         dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 391                 break;
 392         }
 393
 394         return;
 395 }
 396
 397 static void i915_restore_modeset_reg(struct drm_device *dev)
 398 {
 399         struct drm_i915_private *dev_priv = dev->dev_private;
 400         int dpll_a_reg, fpa0_reg, fpa1_reg;
 401         int dpll_b_reg, fpb0_reg, fpb1_reg;
 402         int i;
 403
 404         if (drm_core_check_feature(dev, DRIVER_MODESET))
 405                 return;
 406
 407         /* Fences */
 408         switch (INTEL_INFO(dev)->gen) {
 409         case 7:
 410         case 6:
 411                 for (i = 0; i < 16; i++)
 412                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
 413                 break;
 414         case 5:
 415         case 4:
 416                 for (i = 0; i < 16; i++)
 417                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
 418                 break;
 419         case 3:
 420         case 2:
 421                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 422                         for (i = 0; i < 8; i++)
 423                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
 424                 for (i = 0; i < 8; i++)
 425                         I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
 426                 break;
 427         }
 428
 429
 430         if (HAS_PCH_SPLIT(dev)) {
 431                 dpll_a_reg = _PCH_DPLL_A;
 432                 dpll_b_reg = _PCH_DPLL_B;
 433                 fpa0_reg = _PCH_FPA0;
 434                 fpb0_reg = _PCH_FPB0;
 435                 fpa1_reg = _PCH_FPA1;
 436                 fpb1_reg = _PCH_FPB1;
 437         } else {
 438                 dpll_a_reg = _DPLL_A;
 439                 dpll_b_reg = _DPLL_B;
 440                 fpa0_reg = _FPA0;
 441                 fpb0_reg = _FPB0;
 442                 fpa1_reg = _FPA1;
 443                 fpb1_reg = _FPB1;
 444         }
 445
 446         if (HAS_PCH_SPLIT(dev)) {
 447                 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
 448                 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
 449         }
 450
 451         /* Pipe & plane A info */
 452         /* Prime the clock */
 453         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 454                 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
 455                            ~DPLL_VCO_ENABLE);
 456                 POSTING_READ(dpll_a_reg);
 457                 udelay(150);
 458         }
 459         I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
 460         I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
 461         /* Actually enable it */
 462         I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
 463         POSTING_READ(dpll_a_reg);
 464         udelay(150);
 465         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
 466                 I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 467                 POSTING_READ(_DPLL_A_MD);
 468         }
 469         udelay(150);
 470
 471         /* Restore mode */
 472         I915_WRITE(_HTOTAL_A, dev_priv->saveHTOTAL_A);
 473         I915_WRITE(_HBLANK_A, dev_priv->saveHBLANK_A);
 474         I915_WRITE(_HSYNC_A, dev_priv->saveHSYNC_A);
 475         I915_WRITE(_VTOTAL_A, dev_priv->saveVTOTAL_A);
 476         I915_WRITE(_VBLANK_A, dev_priv->saveVBLANK_A);
 477         I915_WRITE(_VSYNC_A, dev_priv->saveVSYNC_A);
 478         if (!HAS_PCH_SPLIT(dev))
 479                 I915_WRITE(_BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 480
 481         if (HAS_PCH_SPLIT(dev)) {
 482                 I915_WRITE(_PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
 483                 I915_WRITE(_PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
 484                 I915_WRITE(_PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
 485                 I915_WRITE(_PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
 486
 487                 I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
 488                 I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
 489
 490                 I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1);
 491                 I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
 492                 I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
 493
 494                 I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF);
 495                 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
 496                 I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
 497                 I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
 498                 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
 499                 I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
 500                 I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
 501         }
 502
 503         /* Restore plane info */
 504         I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE);
 505         I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS);
 506         I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC);
 507         I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR);
 508         I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 509         if (INTEL_INFO(dev)->gen >= 4) {
 510                 I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF);
 511                 I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 512         }
 513
 514         I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF);
 515
 516         i915_restore_palette(dev, PIPE_A);
 517         /* Enable the plane */
 518         I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR);
 519         I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
 520
 521         /* Pipe & plane B info */
 522         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 523                 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
 524                            ~DPLL_VCO_ENABLE);
 525                 POSTING_READ(dpll_b_reg);
 526                 udelay(150);
 527         }
 528         I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
 529         I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
 530         /* Actually enable it */
 531         I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
 532         POSTING_READ(dpll_b_reg);
 533         udelay(150);
 534         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
 535                 I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 536                 POSTING_READ(_DPLL_B_MD);
 537         }
 538         udelay(150);
 539
 540         /* Restore mode */
 541         I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B);
 542         I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B);
 543         I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B);
 544         I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B);
 545         I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B);
 546         I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B);
 547         if (!HAS_PCH_SPLIT(dev))
 548                 I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 549
 550         if (HAS_PCH_SPLIT(dev)) {
 551                 I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
 552                 I915_WRITE(_PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
 553                 I915_WRITE(_PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
 554                 I915_WRITE(_PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
 555
 556                 I915_WRITE(_FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
 557                 I915_WRITE(_FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
 558
 559                 I915_WRITE(_PFB_CTL_1, dev_priv->savePFB_CTL_1);
 560                 I915_WRITE(_PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
 561                 I915_WRITE(_PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
 562
 563                 I915_WRITE(_TRANSBCONF, dev_priv->saveTRANSBCONF);
 564                 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
 565                 I915_WRITE(_TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
 566                 I915_WRITE(_TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
 567                 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
 568                 I915_WRITE(_TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
 569                 I915_WRITE(_TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
 570         }
 571
 572         /* Restore plane info */
 573         I915_WRITE(_DSPBSIZE, dev_priv->saveDSPBSIZE);
 574         I915_WRITE(_DSPBPOS, dev_priv->saveDSPBPOS);
 575         I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC);
 576         I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR);
 577         I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 578         if (INTEL_INFO(dev)->gen >= 4) {
 579                 I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF);
 580                 I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 581         }
 582
 583         I915_WRITE(_PIPEBCONF, dev_priv->savePIPEBCONF);
 584
 585         i915_restore_palette(dev, PIPE_B);
 586         /* Enable the plane */
 587         I915_WRITE(_DSPBCNTR, dev_priv->saveDSPBCNTR);
 588         I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
 589
 590         /* Cursor state */
 591         I915_WRITE(_CURAPOS, dev_priv->saveCURAPOS);
 592         I915_WRITE(_CURACNTR, dev_priv->saveCURACNTR);
 593         I915_WRITE(_CURABASE, dev_priv->saveCURABASE);
 594         I915_WRITE(_CURBPOS, dev_priv->saveCURBPOS);
 595         I915_WRITE(_CURBCNTR, dev_priv->saveCURBCNTR);
 596         I915_WRITE(_CURBBASE, dev_priv->saveCURBBASE);
 597         if (IS_GEN2(dev))
 598                 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
 599
 600         return;
 601 }
 602
 603 static void i915_save_display(struct drm_device *dev)
 604 {
 605         struct drm_i915_private *dev_priv = dev->dev_private;
 606
 607         /* Display arbitration control */
 608         dev_priv->saveDSPARB = I915_READ(DSPARB);
 609
 610         /* This is only meaningful in non-KMS mode */
 611         /* Don't save them in KMS mode */
 612         i915_save_modeset_reg(dev);
 613
 614         /* CRT state */
 615         if (HAS_PCH_SPLIT(dev)) {
 616                 dev_priv->saveADPA = I915_READ(PCH_ADPA);
 617         } else {
 618                 dev_priv->saveADPA = I915_READ(ADPA);
 619         }
 620
 621         /* LVDS state */
 622         if (HAS_PCH_SPLIT(dev)) {
 623                 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
 624                 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
 625                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
 626                 dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
 627                 dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
 628                 dev_priv->saveLVDS = I915_READ(PCH_LVDS);
 629         } else {
 630                 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 631                 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 632                 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 633                 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
 634                 if (INTEL_INFO(dev)->gen >= 4)
 635                         dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 636                 if (IS_MOBILE(dev) && !IS_I830(dev))
 637                         dev_priv->saveLVDS = I915_READ(LVDS);
 638         }
 639
 640         if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
 641                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 642
 643         if (HAS_PCH_SPLIT(dev)) {
 644                 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
 645                 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
 646                 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
 647         } else {
 648                 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
 649                 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
 650                 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
 651         }
 652
 653         /* Display Port state */
 654         if (SUPPORTS_INTEGRATED_DP(dev)) {
 655                 dev_priv->saveDP_B = I915_READ(DP_B);
 656                 dev_priv->saveDP_C = I915_READ(DP_C);
 657                 dev_priv->saveDP_D = I915_READ(DP_D);
 658                 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
 659                 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
 660                 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
 661                 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
 662                 dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
 663                 dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
 664                 dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
 665                 dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
 666         }
 667         /* FIXME: save TV & SDVO state */
 668
 669         /* Only save FBC state on the platform that supports FBC */
 670         if (I915_HAS_FBC(dev)) {
 671                 if (HAS_PCH_SPLIT(dev)) {
 672                         dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
 673                 } else if (IS_GM45(dev)) {
 674                         dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
 675                 } else {
 676                         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 677                         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 678                         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 679                         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 680                 }
 681         }
 682
 683         /* VGA state */
 684         dev_priv->saveVGA0 = I915_READ(VGA0);
 685         dev_priv->saveVGA1 = I915_READ(VGA1);
 686         dev_priv->saveVGA_PD = I915_READ(VGA_PD);
 687         if (HAS_PCH_SPLIT(dev))
 688                 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
 689         else
 690                 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 691
 692         i915_save_vga(dev);
 693 }
 694
 695 static void i915_restore_display(struct drm_device *dev)
 696 {
 697         struct drm_i915_private *dev_priv = dev->dev_private;
 698
 699         /* Display arbitration */
 700         I915_WRITE(DSPARB, dev_priv->saveDSPARB);
 701
 702         /* Display port ratios (must be done before clock is set) */
 703         if (SUPPORTS_INTEGRATED_DP(dev)) {
 704                 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
 705                 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
 706                 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
 707                 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
 708                 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
 709                 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
 710                 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
 711                 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
 712         }
 713
 714         /* This is only meaningful in non-KMS mode */
 715         /* Don't restore them in KMS mode */
 716         i915_restore_modeset_reg(dev);
 717
 718         /* CRT state */
 719         if (HAS_PCH_SPLIT(dev))
 720                 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
 721         else
 722                 I915_WRITE(ADPA, dev_priv->saveADPA);
 723
 724         /* LVDS state */
 725         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
 726                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 727
 728         if (HAS_PCH_SPLIT(dev)) {
 729                 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
 730         } else if (IS_MOBILE(dev) && !IS_I830(dev))
 731                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 732
 733         if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
 734                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 735
 736         if (HAS_PCH_SPLIT(dev)) {
 737                 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
 738                 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
 739                 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
 740                 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
 741                 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
 742                 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
 743                 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
 744                 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
 745                 I915_WRITE(RSTDBYCTL,
 746                            dev_priv->saveMCHBAR_RENDER_STANDBY);
 747         } else {
 748                 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 749                 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 750                 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
 751                 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
 752                 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
 753                 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
 754                 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 755         }
 756
 757         /* Display Port state */
 758         if (SUPPORTS_INTEGRATED_DP(dev)) {
 759                 I915_WRITE(DP_B, dev_priv->saveDP_B);
 760                 I915_WRITE(DP_C, dev_priv->saveDP_C);
 761                 I915_WRITE(DP_D, dev_priv->saveDP_D);
 762         }
 763         /* FIXME: restore TV & SDVO state */
 764
 765         /* only restore FBC info on the platform that supports FBC*/
 766         intel_disable_fbc(dev);
 767         if (I915_HAS_FBC(dev)) {
 768                 if (HAS_PCH_SPLIT(dev)) {
 769                         I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
 770                 } else if (IS_GM45(dev)) {
 771                         I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
 772                 } else {
 773                         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 774                         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 775                         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 776                         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 777                 }
 778         }
 779         /* VGA state */
 780         if (HAS_PCH_SPLIT(dev))
 781                 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
 782         else
 783                 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 784
 785         I915_WRITE(VGA0, dev_priv->saveVGA0);
 786         I915_WRITE(VGA1, dev_priv->saveVGA1);
 787         I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
 788         POSTING_READ(VGA_PD);
 789         udelay(150);
 790
 791         i915_restore_vga(dev);
 792 }
 793
 794 int i915_save_state(struct drm_device *dev)
 795 {
 796         struct drm_i915_private *dev_priv = dev->dev_private;
 797         int i;
 798
 799         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 800
 801         mutex_lock(&dev->struct_mutex);
 802
 803         /* Hardware status page */
 804         dev_priv->saveHWS = I915_READ(HWS_PGA);
 805
 806         i915_save_display(dev);
 807
 808         /* Interrupt state */
 809         if (HAS_PCH_SPLIT(dev)) {
 810                 dev_priv->saveDEIER = I915_READ(DEIER);
 811                 dev_priv->saveDEIMR = I915_READ(DEIMR);
 812                 dev_priv->saveGTIER = I915_READ(GTIER);
 813                 dev_priv->saveGTIMR = I915_READ(GTIMR);
 814                 dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
 815                 dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
 816                 dev_priv->saveMCHBAR_RENDER_STANDBY =
 817                         I915_READ(RSTDBYCTL);
 818                 dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
 819         } else {
 820                 dev_priv->saveIER = I915_READ(IER);
 821                 dev_priv->saveIMR = I915_READ(IMR);
 822         }
 823
 824         if (IS_IRONLAKE_M(dev))
 825                 ironlake_disable_drps(dev);
 826         if (IS_GEN6(dev))
 827                 gen6_disable_rps(dev);
 828
 829         /* Cache mode state */
 830         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 831
 832         /* Memory Arbitration state */
 833         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 834
 835         /* Scratch space */
 836         for (i = 0; i < 16; i++) {
 837                 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
 838                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 839         }
 840         for (i = 0; i < 3; i++)
 841                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 842
 843         mutex_unlock(&dev->struct_mutex);
 844
 845         return 0;
 846 }
 847
 848 int i915_restore_state(struct drm_device *dev)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         int i;
 852
 853         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 854
 855         mutex_lock(&dev->struct_mutex);
 856
 857         /* Hardware status page */
 858         I915_WRITE(HWS_PGA, dev_priv->saveHWS);
 859
 860         i915_restore_display(dev);
 861
 862         /* Interrupt state */
 863         if (HAS_PCH_SPLIT(dev)) {
 864                 I915_WRITE(DEIER, dev_priv->saveDEIER);
 865                 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
 866                 I915_WRITE(GTIER, dev_priv->saveGTIER);
 867                 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
 868                 I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
 869                 I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
 870                 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG);
 871         } else {
 872                 I915_WRITE(IER, dev_priv->saveIER);
 873                 I915_WRITE(IMR, dev_priv->saveIMR);
 874         }
 875         mutex_unlock(&dev->struct_mutex);
 876
 877         if (drm_core_check_feature(dev, DRIVER_MODESET))
 878                 intel_init_clock_gating(dev);
 879
 880         if (IS_IRONLAKE_M(dev)) {
 881                 ironlake_enable_drps(dev);
 882                 intel_init_emon(dev);
 883         }
 884
 885         if (IS_GEN6(dev)) {
 886                 gen6_enable_rps(dev_priv);
 887                 gen6_update_ring_freq(dev_priv);
 888         }
 889
 890         mutex_lock(&dev->struct_mutex);
 891
 892         /* Cache mode state */
 893         I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 894
 895         /* Memory arbitration state */
 896         I915_WRITE(MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
 897
 898         for (i = 0; i < 16; i++) {
 899                 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
 900                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
 901         }
 902         for (i = 0; i < 3; i++)
 903                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 904
 905         mutex_unlock(&dev->struct_mutex);
 906
 907         intel_i2c_reset(dev);
 908
 909         return 0;
 910 }