2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
28 #include <linux/device.h>
29 #include <linux/module.h>
30 #include <linux/stat.h>
31 #include <linux/sysfs.h>
32 #include "intel_drv.h"
35 #define dev_to_drm_minor(d) dev_get_drvdata((d))
38 static u32 calc_residency(struct drm_device *dev, const u32 reg)
40 struct drm_i915_private *dev_priv = dev->dev_private;
41 u64 raw_time; /* 32b value may overflow during fixed point math */
42 u64 units = 128ULL, div = 100000ULL, bias = 100ULL;
45 if (!intel_enable_rc6(dev))
48 intel_runtime_pm_get(dev_priv);
50 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
51 if (IS_VALLEYVIEW(dev)) {
52 u32 clk_reg, czcount_30ns;
54 if (IS_CHERRYVIEW(dev))
55 clk_reg = CHV_CLK_CTL1;
57 clk_reg = VLV_CLK_CTL2;
59 czcount_30ns = I915_READ(clk_reg) >> CLK_CTL2_CZCOUNT_30NS_SHIFT;
62 WARN(!czcount_30ns, "bogus CZ count value");
70 if (IS_CHERRYVIEW(dev)) {
71 /* Special case for 320Mhz */
72 if (czcount_30ns == 1) {
76 /* chv counts are one less */
82 units = DIV_ROUND_UP_ULL(30ULL * bias,
85 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
91 raw_time = I915_READ(reg) * units;
92 ret = DIV_ROUND_UP_ULL(raw_time, div);
95 intel_runtime_pm_put(dev_priv);
100 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
102 struct drm_minor *dminor = dev_to_drm_minor(kdev);
103 return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
107 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
109 struct drm_minor *dminor = dev_get_drvdata(kdev);
110 u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
111 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
115 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
117 struct drm_minor *dminor = dev_to_drm_minor(kdev);
118 u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
119 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
123 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
125 struct drm_minor *dminor = dev_to_drm_minor(kdev);
126 u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
127 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
131 show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
133 struct drm_minor *dminor = dev_get_drvdata(kdev);
134 u32 rc6_residency = calc_residency(dminor->dev, VLV_GT_MEDIA_RC6);
135 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
138 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
139 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
140 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
141 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
142 static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
144 static struct attribute *rc6_attrs[] = {
145 &dev_attr_rc6_enable.attr,
146 &dev_attr_rc6_residency_ms.attr,
150 static struct attribute_group rc6_attr_group = {
151 .name = power_group_name,
155 static struct attribute *rc6p_attrs[] = {
156 &dev_attr_rc6p_residency_ms.attr,
157 &dev_attr_rc6pp_residency_ms.attr,
161 static struct attribute_group rc6p_attr_group = {
162 .name = power_group_name,
166 static struct attribute *media_rc6_attrs[] = {
167 &dev_attr_media_rc6_residency_ms.attr,
171 static struct attribute_group media_rc6_attr_group = {
172 .name = power_group_name,
173 .attrs = media_rc6_attrs
177 static int l3_access_valid(struct drm_device *dev, loff_t offset)
179 if (!HAS_L3_DPF(dev))
185 if (offset >= GEN7_L3LOG_SIZE)
192 i915_l3_read(struct file *filp, struct kobject *kobj,
193 struct bin_attribute *attr, char *buf,
194 loff_t offset, size_t count)
196 struct device *dev = container_of(kobj, struct device, kobj);
197 struct drm_minor *dminor = dev_to_drm_minor(dev);
198 struct drm_device *drm_dev = dminor->dev;
199 struct drm_i915_private *dev_priv = drm_dev->dev_private;
200 int slice = (int)(uintptr_t)attr->private;
203 count = round_down(count, 4);
205 ret = l3_access_valid(drm_dev, offset);
209 count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
211 ret = i915_mutex_lock_interruptible(drm_dev);
215 if (dev_priv->l3_parity.remap_info[slice])
217 dev_priv->l3_parity.remap_info[slice] + (offset/4),
220 memset(buf, 0, count);
222 mutex_unlock(&drm_dev->struct_mutex);
228 i915_l3_write(struct file *filp, struct kobject *kobj,
229 struct bin_attribute *attr, char *buf,
230 loff_t offset, size_t count)
232 struct device *dev = container_of(kobj, struct device, kobj);
233 struct drm_minor *dminor = dev_to_drm_minor(dev);
234 struct drm_device *drm_dev = dminor->dev;
235 struct drm_i915_private *dev_priv = drm_dev->dev_private;
236 struct intel_context *ctx;
237 u32 *temp = NULL; /* Just here to make handling failures easy */
238 int slice = (int)(uintptr_t)attr->private;
241 if (!HAS_HW_CONTEXTS(drm_dev))
244 ret = l3_access_valid(drm_dev, offset);
248 ret = i915_mutex_lock_interruptible(drm_dev);
252 if (!dev_priv->l3_parity.remap_info[slice]) {
253 temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
255 mutex_unlock(&drm_dev->struct_mutex);
260 ret = i915_gpu_idle(drm_dev);
263 mutex_unlock(&drm_dev->struct_mutex);
267 /* TODO: Ideally we really want a GPU reset here to make sure errors
268 * aren't propagated. Since I cannot find a stable way to reset the GPU
269 * at this point it is left as a TODO.
272 dev_priv->l3_parity.remap_info[slice] = temp;
274 memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);
276 /* NB: We defer the remapping until we switch to the context */
277 list_for_each_entry(ctx, &dev_priv->context_list, link)
278 ctx->remap_slice |= (1<<slice);
280 mutex_unlock(&drm_dev->struct_mutex);
285 static struct bin_attribute dpf_attrs = {
286 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
287 .size = GEN7_L3LOG_SIZE,
288 .read = i915_l3_read,
289 .write = i915_l3_write,
294 static struct bin_attribute dpf_attrs_1 = {
295 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
296 .size = GEN7_L3LOG_SIZE,
297 .read = i915_l3_read,
298 .write = i915_l3_write,
303 static ssize_t gt_act_freq_mhz_show(struct device *kdev,
304 struct device_attribute *attr, char *buf)
306 struct drm_minor *minor = dev_to_drm_minor(kdev);
307 struct drm_device *dev = minor->dev;
308 struct drm_i915_private *dev_priv = dev->dev_private;
311 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
313 intel_runtime_pm_get(dev_priv);
315 mutex_lock(&dev_priv->rps.hw_lock);
316 if (IS_VALLEYVIEW(dev_priv->dev)) {
318 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
319 ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
321 u32 rpstat = I915_READ(GEN6_RPSTAT1);
322 if (IS_GEN9(dev_priv))
323 ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
324 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
325 ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
327 ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
328 ret = intel_gpu_freq(dev_priv, ret);
330 mutex_unlock(&dev_priv->rps.hw_lock);
332 intel_runtime_pm_put(dev_priv);
334 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
337 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
338 struct device_attribute *attr, char *buf)
340 struct drm_minor *minor = dev_to_drm_minor(kdev);
341 struct drm_device *dev = minor->dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
345 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
347 intel_runtime_pm_get(dev_priv);
349 mutex_lock(&dev_priv->rps.hw_lock);
350 ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);
351 mutex_unlock(&dev_priv->rps.hw_lock);
353 intel_runtime_pm_put(dev_priv);
355 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
358 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
359 struct device_attribute *attr, char *buf)
361 struct drm_minor *minor = dev_to_drm_minor(kdev);
362 struct drm_device *dev = minor->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
365 return snprintf(buf, PAGE_SIZE,
367 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
370 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
372 struct drm_minor *minor = dev_to_drm_minor(kdev);
373 struct drm_device *dev = minor->dev;
374 struct drm_i915_private *dev_priv = dev->dev_private;
377 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
379 mutex_lock(&dev_priv->rps.hw_lock);
380 ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
381 mutex_unlock(&dev_priv->rps.hw_lock);
383 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
386 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
387 struct device_attribute *attr,
388 const char *buf, size_t count)
390 struct drm_minor *minor = dev_to_drm_minor(kdev);
391 struct drm_device *dev = minor->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
396 ret = kstrtou32(buf, 0, &val);
400 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
402 mutex_lock(&dev_priv->rps.hw_lock);
404 val = intel_freq_opcode(dev_priv, val);
406 if (val < dev_priv->rps.min_freq ||
407 val > dev_priv->rps.max_freq ||
408 val < dev_priv->rps.min_freq_softlimit) {
409 mutex_unlock(&dev_priv->rps.hw_lock);
413 if (val > dev_priv->rps.rp0_freq)
414 DRM_DEBUG("User requested overclocking to %d\n",
415 intel_gpu_freq(dev_priv, val));
417 dev_priv->rps.max_freq_softlimit = val;
419 val = clamp_t(int, dev_priv->rps.cur_freq,
420 dev_priv->rps.min_freq_softlimit,
421 dev_priv->rps.max_freq_softlimit);
423 /* We still need *_set_rps to process the new max_delay and
424 * update the interrupt limits and PMINTRMSK even though
425 * frequency request may be unchanged. */
426 intel_set_rps(dev, val);
428 mutex_unlock(&dev_priv->rps.hw_lock);
433 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
435 struct drm_minor *minor = dev_to_drm_minor(kdev);
436 struct drm_device *dev = minor->dev;
437 struct drm_i915_private *dev_priv = dev->dev_private;
440 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
442 mutex_lock(&dev_priv->rps.hw_lock);
443 ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
444 mutex_unlock(&dev_priv->rps.hw_lock);
446 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
449 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
450 struct device_attribute *attr,
451 const char *buf, size_t count)
453 struct drm_minor *minor = dev_to_drm_minor(kdev);
454 struct drm_device *dev = minor->dev;
455 struct drm_i915_private *dev_priv = dev->dev_private;
459 ret = kstrtou32(buf, 0, &val);
463 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
465 mutex_lock(&dev_priv->rps.hw_lock);
467 val = intel_freq_opcode(dev_priv, val);
469 if (val < dev_priv->rps.min_freq ||
470 val > dev_priv->rps.max_freq ||
471 val > dev_priv->rps.max_freq_softlimit) {
472 mutex_unlock(&dev_priv->rps.hw_lock);
476 dev_priv->rps.min_freq_softlimit = val;
478 val = clamp_t(int, dev_priv->rps.cur_freq,
479 dev_priv->rps.min_freq_softlimit,
480 dev_priv->rps.max_freq_softlimit);
482 /* We still need *_set_rps to process the new min_delay and
483 * update the interrupt limits and PMINTRMSK even though
484 * frequency request may be unchanged. */
485 intel_set_rps(dev, val);
487 mutex_unlock(&dev_priv->rps.hw_lock);
493 static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
494 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
495 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
496 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
498 static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
500 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
501 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
502 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
503 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
505 /* For now we have a static number of RP states */
506 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
508 struct drm_minor *minor = dev_to_drm_minor(kdev);
509 struct drm_device *dev = minor->dev;
510 struct drm_i915_private *dev_priv = dev->dev_private;
513 if (attr == &dev_attr_gt_RP0_freq_mhz)
514 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
515 else if (attr == &dev_attr_gt_RP1_freq_mhz)
516 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
517 else if (attr == &dev_attr_gt_RPn_freq_mhz)
518 val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
522 return snprintf(buf, PAGE_SIZE, "%d\n", val);
525 static const struct attribute *gen6_attrs[] = {
526 &dev_attr_gt_act_freq_mhz.attr,
527 &dev_attr_gt_cur_freq_mhz.attr,
528 &dev_attr_gt_max_freq_mhz.attr,
529 &dev_attr_gt_min_freq_mhz.attr,
530 &dev_attr_gt_RP0_freq_mhz.attr,
531 &dev_attr_gt_RP1_freq_mhz.attr,
532 &dev_attr_gt_RPn_freq_mhz.attr,
536 static const struct attribute *vlv_attrs[] = {
537 &dev_attr_gt_act_freq_mhz.attr,
538 &dev_attr_gt_cur_freq_mhz.attr,
539 &dev_attr_gt_max_freq_mhz.attr,
540 &dev_attr_gt_min_freq_mhz.attr,
541 &dev_attr_gt_RP0_freq_mhz.attr,
542 &dev_attr_gt_RP1_freq_mhz.attr,
543 &dev_attr_gt_RPn_freq_mhz.attr,
544 &dev_attr_vlv_rpe_freq_mhz.attr,
548 static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
549 struct bin_attribute *attr, char *buf,
550 loff_t off, size_t count)
553 struct device *kdev = container_of(kobj, struct device, kobj);
554 struct drm_minor *minor = dev_to_drm_minor(kdev);
555 struct drm_device *dev = minor->dev;
556 struct i915_error_state_file_priv error_priv;
557 struct drm_i915_error_state_buf error_str;
558 ssize_t ret_count = 0;
561 memset(&error_priv, 0, sizeof(error_priv));
563 ret = i915_error_state_buf_init(&error_str, to_i915(dev), count, off);
567 error_priv.dev = dev;
568 i915_error_state_get(dev, &error_priv);
570 ret = i915_error_state_to_str(&error_str, &error_priv);
574 ret_count = count < error_str.bytes ? count : error_str.bytes;
576 memcpy(buf, error_str.buf, ret_count);
578 i915_error_state_put(&error_priv);
579 i915_error_state_buf_release(&error_str);
581 return ret ?: ret_count;
584 static ssize_t error_state_write(struct file *file, struct kobject *kobj,
585 struct bin_attribute *attr, char *buf,
586 loff_t off, size_t count)
588 struct device *kdev = container_of(kobj, struct device, kobj);
589 struct drm_minor *minor = dev_to_drm_minor(kdev);
590 struct drm_device *dev = minor->dev;
593 DRM_DEBUG_DRIVER("Resetting error state\n");
595 ret = mutex_lock_interruptible(&dev->struct_mutex);
599 i915_destroy_error_state(dev);
600 mutex_unlock(&dev->struct_mutex);
605 static struct bin_attribute error_state_attr = {
606 .attr.name = "error",
607 .attr.mode = S_IRUSR | S_IWUSR,
609 .read = error_state_read,
610 .write = error_state_write,
613 void i915_setup_sysfs(struct drm_device *dev)
619 ret = sysfs_merge_group(&dev->primary->kdev->kobj,
622 DRM_ERROR("RC6 residency sysfs setup failed\n");
625 ret = sysfs_merge_group(&dev->primary->kdev->kobj,
628 DRM_ERROR("RC6p residency sysfs setup failed\n");
630 if (IS_VALLEYVIEW(dev)) {
631 ret = sysfs_merge_group(&dev->primary->kdev->kobj,
632 &media_rc6_attr_group);
634 DRM_ERROR("Media RC6 residency sysfs setup failed\n");
637 if (HAS_L3_DPF(dev)) {
638 ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs);
640 DRM_ERROR("l3 parity sysfs setup failed\n");
642 if (NUM_L3_SLICES(dev) > 1) {
643 ret = device_create_bin_file(dev->primary->kdev,
646 DRM_ERROR("l3 parity slice 1 setup failed\n");
651 if (IS_VALLEYVIEW(dev))
652 ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
653 else if (INTEL_INFO(dev)->gen >= 6)
654 ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
656 DRM_ERROR("RPS sysfs setup failed\n");
658 ret = sysfs_create_bin_file(&dev->primary->kdev->kobj,
661 DRM_ERROR("error_state sysfs setup failed\n");
664 void i915_teardown_sysfs(struct drm_device *dev)
666 sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
667 if (IS_VALLEYVIEW(dev))
668 sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
670 sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
671 device_remove_bin_file(dev->primary->kdev, &dpf_attrs_1);
672 device_remove_bin_file(dev->primary->kdev, &dpf_attrs);
674 sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group);
675 sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6p_attr_group);