drivers/gpu/drm/i915/intel_atomic.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: atomic modeset support
  26  *
  27  * The functions here implement the state management and hardware programming
  28  * dispatch required by the atomic modeset infrastructure.
  29  * See intel_atomic_plane.c for the plane-specific atomic functionality.
  30  */
  31
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_plane_helper.h>
  36 #include "intel_drv.h"
  37
  38
  39 /**
  40  * intel_atomic_check - validate state object
  41  * @dev: drm device
  42  * @state: state to validate
  43  */
  44 int intel_atomic_check(struct drm_device *dev,
  45                        struct drm_atomic_state *state)
  46 {
  47         int nplanes = dev->mode_config.num_total_plane;
  48         int ncrtcs = dev->mode_config.num_crtc;
  49         int nconnectors = dev->mode_config.num_connector;
  50         enum pipe nuclear_pipe = INVALID_PIPE;
  51         struct intel_crtc *nuclear_crtc = NULL;
  52         struct intel_crtc_state *crtc_state = NULL;
  53         int ret;
  54         int i;
  55         bool not_nuclear = false;
  56
  57         to_intel_atomic_state(state)->cdclk = to_i915(dev)->cdclk_freq;
  58
  59         /*
  60          * FIXME:  At the moment, we only support "nuclear pageflip" on a
  61          * single CRTC.  Cross-crtc updates will be added later.
  62          */
  63         for (i = 0; i < nplanes; i++) {
  64                 struct intel_plane *plane = to_intel_plane(state->planes[i]);
  65                 if (!plane)
  66                         continue;
  67
  68                 if (nuclear_pipe == INVALID_PIPE) {
  69                         nuclear_pipe = plane->pipe;
  70                 } else if (nuclear_pipe != plane->pipe) {
  71                         DRM_DEBUG_KMS("i915 only support atomic plane operations on a single CRTC at the moment\n");
  72                         return -EINVAL;
  73                 }
  74         }
  75
  76         /*
  77          * FIXME:  We only handle planes for now; make sure there are no CRTC's
  78          * or connectors involved.
  79          */
  80         state->allow_modeset = false;
  81         for (i = 0; i < ncrtcs; i++) {
  82                 struct intel_crtc *crtc = to_intel_crtc(state->crtcs[i]);
  83                 if (crtc)
  84                         memset(&crtc->atomic, 0, sizeof(crtc->atomic));
  85                 if (crtc && crtc->pipe != nuclear_pipe)
  86                         not_nuclear = true;
  87                 if (crtc && crtc->pipe == nuclear_pipe) {
  88                         nuclear_crtc = crtc;
  89                         crtc_state = to_intel_crtc_state(state->crtc_states[i]);
  90                 }
  91         }
  92         for (i = 0; i < nconnectors; i++)
  93                 if (state->connectors[i] != NULL)
  94                         not_nuclear = true;
  95
  96         if (not_nuclear) {
  97                 DRM_DEBUG_KMS("i915 only supports atomic plane operations at the moment\n");
  98                 return -EINVAL;
  99         }
 100
 101         ret = drm_atomic_helper_check_planes(dev, state);
 102         if (ret)
 103                 return ret;
 104
 105         return ret;
 106 }
 107
 108
 109 /**
 110  * intel_atomic_commit - commit validated state object
 111  * @dev: DRM device
 112  * @state: the top-level driver state object
 113  * @async: asynchronous commit
 114  *
 115  * This function commits a top-level state object that has been validated
 116  * with drm_atomic_helper_check().
 117  *
 118  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
 119  * we can only handle plane-related operations and do not yet support
 120  * asynchronous commit.
 121  *
 122  * RETURNS
 123  * Zero for success or -errno.
 124  */
 125 int intel_atomic_commit(struct drm_device *dev,
 126                         struct drm_atomic_state *state,
 127                         bool async)
 128 {
 129         struct drm_crtc_state *crtc_state;
 130         struct drm_crtc *crtc;
 131         int ret;
 132         int i;
 133
 134         if (async) {
 135                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
 136                 return -EINVAL;
 137         }
 138
 139         ret = drm_atomic_helper_prepare_planes(dev, state);
 140         if (ret)
 141                 return ret;
 142
 143         /* Point of no return */
 144         drm_atomic_helper_swap_state(dev, state);
 145
 146         for_each_crtc_in_state(state, crtc, crtc_state, i) {
 147                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
 148
 149                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
 150         }
 151
 152         /* FIXME: This function should eventually call __intel_set_mode when needed */
 153
 154         drm_atomic_helper_wait_for_vblanks(dev, state);
 155         drm_atomic_helper_cleanup_planes(dev, state);
 156         drm_atomic_state_free(state);
 157
 158         return 0;
 159 }
 160
 161 /**
 162  * intel_connector_atomic_get_property - fetch connector property value
 163  * @connector: connector to fetch property for
 164  * @state: state containing the property value
 165  * @property: property to look up
 166  * @val: pointer to write property value into
 167  *
 168  * The DRM core does not store shadow copies of properties for
 169  * atomic-capable drivers.  This entrypoint is used to fetch
 170  * the current value of a driver-specific connector property.
 171  */
 172 int
 173 intel_connector_atomic_get_property(struct drm_connector *connector,
 174                                     const struct drm_connector_state *state,
 175                                     struct drm_property *property,
 176                                     uint64_t *val)
 177 {
 178         int i;
 179
 180         /*
 181          * TODO: We only have atomic modeset for planes at the moment, so the
 182          * crtc/connector code isn't quite ready yet.  Until it's ready,
 183          * continue to look up all property values in the DRM's shadow copy
 184          * in obj->properties->values[].
 185          *
 186          * When the crtc/connector state work matures, this function should
 187          * be updated to read the values out of the state structure instead.
 188          */
 189         for (i = 0; i < connector->base.properties->count; i++) {
 190                 if (connector->base.properties->properties[i] == property) {
 191                         *val = connector->base.properties->values[i];
 192                         return 0;
 193                 }
 194         }
 195
 196         return -EINVAL;
 197 }
 198
 199 /*
 200  * intel_crtc_duplicate_state - duplicate crtc state
 201  * @crtc: drm crtc
 202  *
 203  * Allocates and returns a copy of the crtc state (both common and
 204  * Intel-specific) for the specified crtc.
 205  *
 206  * Returns: The newly allocated crtc state, or NULL on failure.
 207  */
 208 struct drm_crtc_state *
 209 intel_crtc_duplicate_state(struct drm_crtc *crtc)
 210 {
 211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 212         struct intel_crtc_state *crtc_state;
 213
 214         if (WARN_ON(!intel_crtc->config))
 215                 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
 216         else
 217                 crtc_state = kmemdup(intel_crtc->config,
 218                                      sizeof(*intel_crtc->config), GFP_KERNEL);
 219
 220         if (!crtc_state)
 221                 return NULL;
 222
 223         __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base);
 224
 225         crtc_state->base.crtc = crtc;
 226
 227         return &crtc_state->base;
 228 }
 229
 230 /**
 231  * intel_crtc_destroy_state - destroy crtc state
 232  * @crtc: drm crtc
 233  *
 234  * Destroys the crtc state (both common and Intel-specific) for the
 235  * specified crtc.
 236  */
 237 void
 238 intel_crtc_destroy_state(struct drm_crtc *crtc,
 239                           struct drm_crtc_state *state)
 240 {
 241         drm_atomic_helper_crtc_destroy_state(crtc, state);
 242 }
 243
 244 /**
 245  * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
 246  * @dev: DRM device
 247  * @crtc: intel crtc
 248  * @crtc_state: incoming crtc_state to validate and setup scalers
 249  *
 250  * This function sets up scalers based on staged scaling requests for
 251  * a @crtc and its planes. It is called from crtc level check path. If request
 252  * is a supportable request, it attaches scalers to requested planes and crtc.
 253  *
 254  * This function takes into account the current scaler(s) in use by any planes
 255  * not being part of this atomic state
 256  *
 257  *  Returns:
 258  *         0 - scalers were setup succesfully
 259  *         error code - otherwise
 260  */
 261 int intel_atomic_setup_scalers(struct drm_device *dev,
 262         struct intel_crtc *intel_crtc,
 263         struct intel_crtc_state *crtc_state)
 264 {
 265         struct drm_plane *plane = NULL;
 266         struct intel_plane *intel_plane;
 267         struct intel_plane_state *plane_state = NULL;
 268         struct intel_crtc_scaler_state *scaler_state =
 269                 &crtc_state->scaler_state;
 270         struct drm_atomic_state *drm_state = crtc_state->base.state;
 271         int num_scalers_need;
 272         int i, j;
 273
 274         num_scalers_need = hweight32(scaler_state->scaler_users);
 275         DRM_DEBUG_KMS("crtc_state = %p need = %d avail = %d scaler_users = 0x%x\n",
 276                 crtc_state, num_scalers_need, intel_crtc->num_scalers,
 277                 scaler_state->scaler_users);
 278
 279         /*
 280          * High level flow:
 281          * - staged scaler requests are already in scaler_state->scaler_users
 282          * - check whether staged scaling requests can be supported
 283          * - add planes using scalers that aren't in current transaction
 284          * - assign scalers to requested users
 285          * - as part of plane commit, scalers will be committed
 286          *   (i.e., either attached or detached) to respective planes in hw
 287          * - as part of crtc_commit, scaler will be either attached or detached
 288          *   to crtc in hw
 289          */
 290
 291         /* fail if required scalers > available scalers */
 292         if (num_scalers_need > intel_crtc->num_scalers){
 293                 DRM_DEBUG_KMS("Too many scaling requests %d > %d\n",
 294                         num_scalers_need, intel_crtc->num_scalers);
 295                 return -EINVAL;
 296         }
 297
 298         /* walkthrough scaler_users bits and start assigning scalers */
 299         for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
 300                 int *scaler_id;
 301                 const char *name;
 302                 int idx;
 303
 304                 /* skip if scaler not required */
 305                 if (!(scaler_state->scaler_users & (1 << i)))
 306                         continue;
 307
 308                 if (i == SKL_CRTC_INDEX) {
 309                         name = "CRTC";
 310                         idx = intel_crtc->base.base.id;
 311
 312                         /* panel fitter case: assign as a crtc scaler */
 313                         scaler_id = &scaler_state->scaler_id;
 314                 } else {
 315                         name = "PLANE";
 316
 317                         /* plane scaler case: assign as a plane scaler */
 318                         /* find the plane that set the bit as scaler_user */
 319                         plane = drm_state->planes[i];
 320
 321                         /*
 322                          * to enable/disable hq mode, add planes that are using scaler
 323                          * into this transaction
 324                          */
 325                         if (!plane) {
 326                                 struct drm_plane_state *state;
 327                                 plane = drm_plane_from_index(dev, i);
 328                                 state = drm_atomic_get_plane_state(drm_state, plane);
 329                                 if (IS_ERR(state)) {
 330                                         DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
 331                                                 plane->base.id);
 332                                         return PTR_ERR(state);
 333                                 }
 334
 335                                 /*
 336                                  * the plane is added after plane checks are run,
 337                                  * but since this plane is unchanged just do the
 338                                  * minimum required validation.
 339                                  */
 340                                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
 341                                         intel_crtc->atomic.wait_for_flips = true;
 342                                 crtc_state->base.planes_changed = true;
 343                         }
 344
 345                         intel_plane = to_intel_plane(plane);
 346                         idx = plane->base.id;
 347
 348                         /* plane on different crtc cannot be a scaler user of this crtc */
 349                         if (WARN_ON(intel_plane->pipe != intel_crtc->pipe)) {
 350                                 continue;
 351                         }
 352
 353                         plane_state = to_intel_plane_state(drm_state->plane_states[i]);
 354                         scaler_id = &plane_state->scaler_id;
 355                 }
 356
 357                 if (*scaler_id < 0) {
 358                         /* find a free scaler */
 359                         for (j = 0; j < intel_crtc->num_scalers; j++) {
 360                                 if (!scaler_state->scalers[j].in_use) {
 361                                         scaler_state->scalers[j].in_use = 1;
 362                                         *scaler_id = j;
 363                                         DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n",
 364                                                 intel_crtc->pipe, *scaler_id, name, idx);
 365                                         break;
 366                                 }
 367                         }
 368                 }
 369
 370                 if (WARN_ON(*scaler_id < 0)) {
 371                         DRM_DEBUG_KMS("Cannot find scaler for %s:%d\n", name, idx);
 372                         continue;
 373                 }
 374
 375                 /* set scaler mode */
 376                 if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
 377                         /*
 378                          * when only 1 scaler is in use on either pipe A or B,
 379                          * scaler 0 operates in high quality (HQ) mode.
 380                          * In this case use scaler 0 to take advantage of HQ mode
 381                          */
 382                         *scaler_id = 0;
 383                         scaler_state->scalers[0].in_use = 1;
 384                         scaler_state->scalers[0].mode = PS_SCALER_MODE_HQ;
 385                         scaler_state->scalers[1].in_use = 0;
 386                 } else {
 387                         scaler_state->scalers[*scaler_id].mode = PS_SCALER_MODE_DYN;
 388                 }
 389         }
 390
 391         return 0;
 392 }
 393
 394 static void
 395 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
 396                                   struct intel_shared_dpll_config *shared_dpll)
 397 {
 398         enum intel_dpll_id i;
 399
 400         /* Copy shared dpll state */
 401         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 402                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
 403
 404                 shared_dpll[i] = pll->config;
 405         }
 406 }
 407
 408 struct intel_shared_dpll_config *
 409 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
 410 {
 411         struct intel_atomic_state *state = to_intel_atomic_state(s);
 412
 413         WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
 414
 415         if (!state->dpll_set) {
 416                 state->dpll_set = true;
 417
 418                 intel_atomic_duplicate_dpll_state(to_i915(s->dev),
 419                                                   state->shared_dpll);
 420         }
 421
 422         return state->shared_dpll;
 423 }
 424
 425 struct drm_atomic_state *
 426 intel_atomic_state_alloc(struct drm_device *dev)
 427 {
 428         struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
 429
 430         if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
 431                 kfree(state);
 432                 return NULL;
 433         }
 434
 435         return &state->base;
 436 }
 437
 438 void intel_atomic_state_clear(struct drm_atomic_state *s)
 439 {
 440         struct intel_atomic_state *state = to_intel_atomic_state(s);
 441         drm_atomic_state_default_clear(&state->base);
 442         state->dpll_set = false;
 443 }