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25 * DOC: atomic modeset support
27 * The functions here implement the state management and hardware programming
28 * dispatch required by the atomic modeset infrastructure.
29 * See intel_atomic_plane.c for the plane-specific atomic functionality.
33 #include <drm/drm_atomic.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_plane_helper.h>
36 #include "intel_drv.h"
40 * intel_atomic_check - validate state object
42 * @state: state to validate
44 int intel_atomic_check(struct drm_device *dev,
45 struct drm_atomic_state *state)
47 int nplanes = dev->mode_config.num_total_plane;
48 int ncrtcs = dev->mode_config.num_crtc;
49 int nconnectors = dev->mode_config.num_connector;
50 enum pipe nuclear_pipe = INVALID_PIPE;
51 struct intel_crtc *nuclear_crtc = NULL;
52 struct intel_crtc_state *crtc_state = NULL;
55 bool not_nuclear = false;
57 to_intel_atomic_state(state)->cdclk = to_i915(dev)->cdclk_freq;
60 * FIXME: At the moment, we only support "nuclear pageflip" on a
61 * single CRTC. Cross-crtc updates will be added later.
63 for (i = 0; i < nplanes; i++) {
64 struct intel_plane *plane = to_intel_plane(state->planes[i]);
68 if (nuclear_pipe == INVALID_PIPE) {
69 nuclear_pipe = plane->pipe;
70 } else if (nuclear_pipe != plane->pipe) {
71 DRM_DEBUG_KMS("i915 only support atomic plane operations on a single CRTC at the moment\n");
77 * FIXME: We only handle planes for now; make sure there are no CRTC's
78 * or connectors involved.
80 state->allow_modeset = false;
81 for (i = 0; i < ncrtcs; i++) {
82 struct intel_crtc *crtc = to_intel_crtc(state->crtcs[i]);
84 memset(&crtc->atomic, 0, sizeof(crtc->atomic));
85 if (crtc && crtc->pipe != nuclear_pipe)
87 if (crtc && crtc->pipe == nuclear_pipe) {
89 crtc_state = to_intel_crtc_state(state->crtc_states[i]);
92 for (i = 0; i < nconnectors; i++)
93 if (state->connectors[i] != NULL)
97 DRM_DEBUG_KMS("i915 only supports atomic plane operations at the moment\n");
102 crtc_state->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
103 ret = drm_atomic_add_affected_planes(state, &nuclear_crtc->base);
108 ret = drm_atomic_helper_check_planes(dev, state);
117 * intel_atomic_commit - commit validated state object
119 * @state: the top-level driver state object
120 * @async: asynchronous commit
122 * This function commits a top-level state object that has been validated
123 * with drm_atomic_helper_check().
125 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
126 * we can only handle plane-related operations and do not yet support
127 * asynchronous commit.
130 * Zero for success or -errno.
132 int intel_atomic_commit(struct drm_device *dev,
133 struct drm_atomic_state *state,
136 struct drm_crtc_state *crtc_state;
137 struct drm_crtc *crtc;
142 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
146 ret = drm_atomic_helper_prepare_planes(dev, state);
150 /* Point of no return */
151 drm_atomic_helper_swap_state(dev, state);
153 for_each_crtc_in_state(state, crtc, crtc_state, i) {
154 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
156 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
159 /* FIXME: This function should eventually call __intel_set_mode when needed */
161 drm_atomic_helper_wait_for_vblanks(dev, state);
162 drm_atomic_helper_cleanup_planes(dev, state);
163 drm_atomic_state_free(state);
169 * intel_connector_atomic_get_property - fetch connector property value
170 * @connector: connector to fetch property for
171 * @state: state containing the property value
172 * @property: property to look up
173 * @val: pointer to write property value into
175 * The DRM core does not store shadow copies of properties for
176 * atomic-capable drivers. This entrypoint is used to fetch
177 * the current value of a driver-specific connector property.
180 intel_connector_atomic_get_property(struct drm_connector *connector,
181 const struct drm_connector_state *state,
182 struct drm_property *property,
188 * TODO: We only have atomic modeset for planes at the moment, so the
189 * crtc/connector code isn't quite ready yet. Until it's ready,
190 * continue to look up all property values in the DRM's shadow copy
191 * in obj->properties->values[].
193 * When the crtc/connector state work matures, this function should
194 * be updated to read the values out of the state structure instead.
196 for (i = 0; i < connector->base.properties->count; i++) {
197 if (connector->base.properties->properties[i] == property) {
198 *val = connector->base.properties->values[i];
207 * intel_crtc_duplicate_state - duplicate crtc state
210 * Allocates and returns a copy of the crtc state (both common and
211 * Intel-specific) for the specified crtc.
213 * Returns: The newly allocated crtc state, or NULL on failure.
215 struct drm_crtc_state *
216 intel_crtc_duplicate_state(struct drm_crtc *crtc)
218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
219 struct intel_crtc_state *crtc_state;
221 if (WARN_ON(!intel_crtc->config))
222 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
224 crtc_state = kmemdup(intel_crtc->config,
225 sizeof(*intel_crtc->config), GFP_KERNEL);
230 __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base);
232 crtc_state->base.crtc = crtc;
234 return &crtc_state->base;
238 * intel_crtc_destroy_state - destroy crtc state
241 * Destroys the crtc state (both common and Intel-specific) for the
245 intel_crtc_destroy_state(struct drm_crtc *crtc,
246 struct drm_crtc_state *state)
248 drm_atomic_helper_crtc_destroy_state(crtc, state);
252 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
255 * @crtc_state: incoming crtc_state to validate and setup scalers
257 * This function sets up scalers based on staged scaling requests for
258 * a @crtc and its planes. It is called from crtc level check path. If request
259 * is a supportable request, it attaches scalers to requested planes and crtc.
261 * This function takes into account the current scaler(s) in use by any planes
262 * not being part of this atomic state
265 * 0 - scalers were setup succesfully
266 * error code - otherwise
268 int intel_atomic_setup_scalers(struct drm_device *dev,
269 struct intel_crtc *intel_crtc,
270 struct intel_crtc_state *crtc_state)
272 struct drm_plane *plane = NULL;
273 struct intel_plane *intel_plane;
274 struct intel_plane_state *plane_state = NULL;
275 struct intel_crtc_scaler_state *scaler_state =
276 &crtc_state->scaler_state;
277 struct drm_atomic_state *drm_state = crtc_state->base.state;
278 int num_scalers_need;
281 num_scalers_need = hweight32(scaler_state->scaler_users);
282 DRM_DEBUG_KMS("crtc_state = %p need = %d avail = %d scaler_users = 0x%x\n",
283 crtc_state, num_scalers_need, intel_crtc->num_scalers,
284 scaler_state->scaler_users);
288 * - staged scaler requests are already in scaler_state->scaler_users
289 * - check whether staged scaling requests can be supported
290 * - add planes using scalers that aren't in current transaction
291 * - assign scalers to requested users
292 * - as part of plane commit, scalers will be committed
293 * (i.e., either attached or detached) to respective planes in hw
294 * - as part of crtc_commit, scaler will be either attached or detached
298 /* fail if required scalers > available scalers */
299 if (num_scalers_need > intel_crtc->num_scalers){
300 DRM_DEBUG_KMS("Too many scaling requests %d > %d\n",
301 num_scalers_need, intel_crtc->num_scalers);
305 /* walkthrough scaler_users bits and start assigning scalers */
306 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
311 /* skip if scaler not required */
312 if (!(scaler_state->scaler_users & (1 << i)))
315 if (i == SKL_CRTC_INDEX) {
317 idx = intel_crtc->base.base.id;
319 /* panel fitter case: assign as a crtc scaler */
320 scaler_id = &scaler_state->scaler_id;
324 /* plane scaler case: assign as a plane scaler */
325 /* find the plane that set the bit as scaler_user */
326 plane = drm_state->planes[i];
329 * to enable/disable hq mode, add planes that are using scaler
330 * into this transaction
333 struct drm_plane_state *state;
334 plane = drm_plane_from_index(dev, i);
335 state = drm_atomic_get_plane_state(drm_state, plane);
337 DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
339 return PTR_ERR(state);
343 * the plane is added after plane checks are run,
344 * but since this plane is unchanged just do the
345 * minimum required validation.
347 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
348 intel_crtc->atomic.wait_for_flips = true;
349 crtc_state->base.planes_changed = true;
352 intel_plane = to_intel_plane(plane);
353 idx = plane->base.id;
355 /* plane on different crtc cannot be a scaler user of this crtc */
356 if (WARN_ON(intel_plane->pipe != intel_crtc->pipe)) {
360 plane_state = to_intel_plane_state(drm_state->plane_states[i]);
361 scaler_id = &plane_state->scaler_id;
364 if (*scaler_id < 0) {
365 /* find a free scaler */
366 for (j = 0; j < intel_crtc->num_scalers; j++) {
367 if (!scaler_state->scalers[j].in_use) {
368 scaler_state->scalers[j].in_use = 1;
370 DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n",
371 intel_crtc->pipe, *scaler_id, name, idx);
377 if (WARN_ON(*scaler_id < 0)) {
378 DRM_DEBUG_KMS("Cannot find scaler for %s:%d\n", name, idx);
382 /* set scaler mode */
383 if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
385 * when only 1 scaler is in use on either pipe A or B,
386 * scaler 0 operates in high quality (HQ) mode.
387 * In this case use scaler 0 to take advantage of HQ mode
390 scaler_state->scalers[0].in_use = 1;
391 scaler_state->scalers[0].mode = PS_SCALER_MODE_HQ;
392 scaler_state->scalers[1].in_use = 0;
394 scaler_state->scalers[*scaler_id].mode = PS_SCALER_MODE_DYN;
402 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
403 struct intel_shared_dpll_config *shared_dpll)
405 enum intel_dpll_id i;
407 /* Copy shared dpll state */
408 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
409 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
411 shared_dpll[i] = pll->config;
415 struct intel_shared_dpll_config *
416 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
418 struct intel_atomic_state *state = to_intel_atomic_state(s);
420 WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
422 if (!state->dpll_set) {
423 state->dpll_set = true;
425 intel_atomic_duplicate_dpll_state(to_i915(s->dev),
429 return state->shared_dpll;
432 struct drm_atomic_state *
433 intel_atomic_state_alloc(struct drm_device *dev)
435 struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
437 if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
445 void intel_atomic_state_clear(struct drm_atomic_state *s)
447 struct intel_atomic_state *state = to_intel_atomic_state(s);
448 drm_atomic_state_default_clear(&state->base);
449 state->dpll_set = false;