drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  32  * them for both DP and FDI transports, allowing those ports to
  33  * automatically adapt to HDMI connections as well
  34  */
  35 static const u32 hsw_ddi_translations_dp[] = {
  36         0x00FFFFFF, 0x0006000E,         /* DP parameters */
  37         0x00D75FFF, 0x0005000A,
  38         0x00C30FFF, 0x00040006,
  39         0x80AAAFFF, 0x000B0000,
  40         0x00FFFFFF, 0x0005000A,
  41         0x00D75FFF, 0x000C0004,
  42         0x80C30FFF, 0x000B0000,
  43         0x00FFFFFF, 0x00040006,
  44         0x80D75FFF, 0x000B0000,
  45 };
  46
  47 static const u32 hsw_ddi_translations_fdi[] = {
  48         0x00FFFFFF, 0x0007000E,         /* FDI parameters */
  49         0x00D75FFF, 0x000F000A,
  50         0x00C30FFF, 0x00060006,
  51         0x00AAAFFF, 0x001E0000,
  52         0x00FFFFFF, 0x000F000A,
  53         0x00D75FFF, 0x00160004,
  54         0x00C30FFF, 0x001E0000,
  55         0x00FFFFFF, 0x00060006,
  56         0x00D75FFF, 0x001E0000,
  57 };
  58
  59 static const u32 hsw_ddi_translations_hdmi[] = {
  60                                 /* Idx  NT mV diff      T mV diff       db  */
  61         0x00FFFFFF, 0x0006000E, /* 0:   400             400             0   */
  62         0x00E79FFF, 0x000E000C, /* 1:   400             500             2   */
  63         0x00D75FFF, 0x0005000A, /* 2:   400             600             3.5 */
  64         0x00FFFFFF, 0x0005000A, /* 3:   600             600             0   */
  65         0x00E79FFF, 0x001D0007, /* 4:   600             750             2   */
  66         0x00D75FFF, 0x000C0004, /* 5:   600             900             3.5 */
  67         0x00FFFFFF, 0x00040006, /* 6:   800             800             0   */
  68         0x80E79FFF, 0x00030002, /* 7:   800             1000            2   */
  69         0x00FFFFFF, 0x00140005, /* 8:   850             850             0   */
  70         0x00FFFFFF, 0x000C0004, /* 9:   900             900             0   */
  71         0x00FFFFFF, 0x001C0003, /* 10:  950             950             0   */
  72         0x80FFFFFF, 0x00030002, /* 11:  1000            1000            0   */
  73 };
  74
  75 static const u32 bdw_ddi_translations_edp[] = {
  76         0x00FFFFFF, 0x00000012,         /* eDP parameters */
  77         0x00EBAFFF, 0x00020011,
  78         0x00C71FFF, 0x0006000F,
  79         0x00AAAFFF, 0x000E000A,
  80         0x00FFFFFF, 0x00020011,
  81         0x00DB6FFF, 0x0005000F,
  82         0x00BEEFFF, 0x000A000C,
  83         0x00FFFFFF, 0x0005000F,
  84         0x00DB6FFF, 0x000A000C,
  85         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
  86 };
  87
  88 static const u32 bdw_ddi_translations_dp[] = {
  89         0x00FFFFFF, 0x0007000E,         /* DP parameters */
  90         0x00D75FFF, 0x000E000A,
  91         0x00BEFFFF, 0x00140006,
  92         0x80B2CFFF, 0x001B0002,
  93         0x00FFFFFF, 0x000E000A,
  94         0x00D75FFF, 0x00180004,
  95         0x80CB2FFF, 0x001B0002,
  96         0x00F7DFFF, 0x00180004,
  97         0x80D75FFF, 0x001B0002,
  98         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
  99 };
 100
 101 static const u32 bdw_ddi_translations_fdi[] = {
 102         0x00FFFFFF, 0x0001000E,         /* FDI parameters */
 103         0x00D75FFF, 0x0004000A,
 104         0x00C30FFF, 0x00070006,
 105         0x00AAAFFF, 0x000C0000,
 106         0x00FFFFFF, 0x0004000A,
 107         0x00D75FFF, 0x00090004,
 108         0x00C30FFF, 0x000C0000,
 109         0x00FFFFFF, 0x00070006,
 110         0x00D75FFF, 0x000C0000,
 111         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
 112 };
 113
 114 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 115 {
 116         struct drm_encoder *encoder = &intel_encoder->base;
 117         int type = intel_encoder->type;
 118
 119         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 120             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 121                 struct intel_digital_port *intel_dig_port =
 122                         enc_to_dig_port(encoder);
 123                 return intel_dig_port->port;
 124
 125         } else if (type == INTEL_OUTPUT_ANALOG) {
 126                 return PORT_E;
 127
 128         } else {
 129                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
 130                 BUG();
 131         }
 132 }
 133
 134 /*
 135  * Starting with Haswell, DDI port buffers must be programmed with correct
 136  * values in advance. The buffer values are different for FDI and DP modes,
 137  * but the HDMI/DVI fields are shared among those. So we program the DDI
 138  * in either FDI or DP modes only, as HDMI connections will work with both
 139  * of those
 140  */
 141 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 142 {
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144         u32 reg;
 145         int i;
 146         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 147         const u32 *ddi_translations_fdi;
 148         const u32 *ddi_translations_dp;
 149         const u32 *ddi_translations_edp;
 150         const u32 *ddi_translations;
 151
 152         if (IS_BROADWELL(dev)) {
 153                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 154                 ddi_translations_dp = bdw_ddi_translations_dp;
 155                 ddi_translations_edp = bdw_ddi_translations_edp;
 156         } else if (IS_HASWELL(dev)) {
 157                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 158                 ddi_translations_dp = hsw_ddi_translations_dp;
 159                 ddi_translations_edp = hsw_ddi_translations_dp;
 160         } else {
 161                 WARN(1, "ddi translation table missing\n");
 162                 ddi_translations_edp = bdw_ddi_translations_dp;
 163                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 164                 ddi_translations_dp = bdw_ddi_translations_dp;
 165         }
 166
 167         switch (port) {
 168         case PORT_A:
 169                 ddi_translations = ddi_translations_edp;
 170                 break;
 171         case PORT_B:
 172         case PORT_C:
 173                 ddi_translations = ddi_translations_dp;
 174                 break;
 175         case PORT_D:
 176                 if (intel_dp_is_edp(dev, PORT_D))
 177                         ddi_translations = ddi_translations_edp;
 178                 else
 179                         ddi_translations = ddi_translations_dp;
 180                 break;
 181         case PORT_E:
 182                 ddi_translations = ddi_translations_fdi;
 183                 break;
 184         default:
 185                 BUG();
 186         }
 187
 188         for (i = 0, reg = DDI_BUF_TRANS(port);
 189              i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 190                 I915_WRITE(reg, ddi_translations[i]);
 191                 reg += 4;
 192         }
 193         /* Entry 9 is for HDMI: */
 194         for (i = 0; i < 2; i++) {
 195                 I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
 196                 reg += 4;
 197         }
 198 }
 199
 200 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 201  * mode and port E for FDI.
 202  */
 203 void intel_prepare_ddi(struct drm_device *dev)
 204 {
 205         int port;
 206
 207         if (!HAS_DDI(dev))
 208                 return;
 209
 210         for (port = PORT_A; port <= PORT_E; port++)
 211                 intel_prepare_ddi_buffers(dev, port);
 212 }
 213
 214 static const long hsw_ddi_buf_ctl_values[] = {
 215         DDI_BUF_EMP_400MV_0DB_HSW,
 216         DDI_BUF_EMP_400MV_3_5DB_HSW,
 217         DDI_BUF_EMP_400MV_6DB_HSW,
 218         DDI_BUF_EMP_400MV_9_5DB_HSW,
 219         DDI_BUF_EMP_600MV_0DB_HSW,
 220         DDI_BUF_EMP_600MV_3_5DB_HSW,
 221         DDI_BUF_EMP_600MV_6DB_HSW,
 222         DDI_BUF_EMP_800MV_0DB_HSW,
 223         DDI_BUF_EMP_800MV_3_5DB_HSW
 224 };
 225
 226 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 227                                     enum port port)
 228 {
 229         uint32_t reg = DDI_BUF_CTL(port);
 230         int i;
 231
 232         for (i = 0; i < 8; i++) {
 233                 udelay(1);
 234                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 235                         return;
 236         }
 237         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 238 }
 239
 240 /* Starting with Haswell, different DDI ports can work in FDI mode for
 241  * connection to the PCH-located connectors. For this, it is necessary to train
 242  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 243  *
 244  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 245  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 246  * DDI A (which is used for eDP)
 247  */
 248
 249 void hsw_fdi_link_train(struct drm_crtc *crtc)
 250 {
 251         struct drm_device *dev = crtc->dev;
 252         struct drm_i915_private *dev_priv = dev->dev_private;
 253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 254         u32 temp, i, rx_ctl_val;
 255
 256         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 257          * mode set "sequence for CRT port" document:
 258          * - TP1 to TP2 time with the default value
 259          * - FDI delay to 90h
 260          *
 261          * WaFDIAutoLinkSetTimingOverrride:hsw
 262          */
 263         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 264                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 265                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 266
 267         /* Enable the PCH Receiver FDI PLL */
 268         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 269                      FDI_RX_PLL_ENABLE |
 270                      FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
 271         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 272         POSTING_READ(_FDI_RXA_CTL);
 273         udelay(220);
 274
 275         /* Switch from Rawclk to PCDclk */
 276         rx_ctl_val |= FDI_PCDCLK;
 277         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 278
 279         /* Configure Port Clock Select */
 280         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
 281         WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
 282
 283         /* Start the training iterating through available voltages and emphasis,
 284          * testing each value twice. */
 285         for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
 286                 /* Configure DP_TP_CTL with auto-training */
 287                 I915_WRITE(DP_TP_CTL(PORT_E),
 288                                         DP_TP_CTL_FDI_AUTOTRAIN |
 289                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 290                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 291                                         DP_TP_CTL_ENABLE);
 292
 293                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 294                  * DDI E does not support port reversal, the functionality is
 295                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 296                  * port reversal bit */
 297                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 298                            DDI_BUF_CTL_ENABLE |
 299                            ((intel_crtc->config.fdi_lanes - 1) << 1) |
 300                            hsw_ddi_buf_ctl_values[i / 2]);
 301                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 302
 303                 udelay(600);
 304
 305                 /* Program PCH FDI Receiver TU */
 306                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 307
 308                 /* Enable PCH FDI Receiver with auto-training */
 309                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 310                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 311                 POSTING_READ(_FDI_RXA_CTL);
 312
 313                 /* Wait for FDI receiver lane calibration */
 314                 udelay(30);
 315
 316                 /* Unset FDI_RX_MISC pwrdn lanes */
 317                 temp = I915_READ(_FDI_RXA_MISC);
 318                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 319                 I915_WRITE(_FDI_RXA_MISC, temp);
 320                 POSTING_READ(_FDI_RXA_MISC);
 321
 322                 /* Wait for FDI auto training time */
 323                 udelay(5);
 324
 325                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 326                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 327                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 328
 329                         /* Enable normal pixel sending for FDI */
 330                         I915_WRITE(DP_TP_CTL(PORT_E),
 331                                    DP_TP_CTL_FDI_AUTOTRAIN |
 332                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 333                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 334                                    DP_TP_CTL_ENABLE);
 335
 336                         return;
 337                 }
 338
 339                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 340                 temp &= ~DDI_BUF_CTL_ENABLE;
 341                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 342                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 343
 344                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 345                 temp = I915_READ(DP_TP_CTL(PORT_E));
 346                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 347                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 348                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 349                 POSTING_READ(DP_TP_CTL(PORT_E));
 350
 351                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 352
 353                 rx_ctl_val &= ~FDI_RX_ENABLE;
 354                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 355                 POSTING_READ(_FDI_RXA_CTL);
 356
 357                 /* Reset FDI_RX_MISC pwrdn lanes */
 358                 temp = I915_READ(_FDI_RXA_MISC);
 359                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 360                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 361                 I915_WRITE(_FDI_RXA_MISC, temp);
 362                 POSTING_READ(_FDI_RXA_MISC);
 363         }
 364
 365         DRM_ERROR("FDI link training failed!\n");
 366 }
 367
 368 static struct intel_encoder *
 369 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 370 {
 371         struct drm_device *dev = crtc->dev;
 372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 373         struct intel_encoder *intel_encoder, *ret = NULL;
 374         int num_encoders = 0;
 375
 376         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 377                 ret = intel_encoder;
 378                 num_encoders++;
 379         }
 380
 381         if (num_encoders != 1)
 382                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 383                      pipe_name(intel_crtc->pipe));
 384
 385         BUG_ON(ret == NULL);
 386         return ret;
 387 }
 388
 389 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 390 {
 391         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 392         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 393         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 394         uint32_t val;
 395
 396         switch (intel_crtc->config.ddi_pll_sel) {
 397         case PORT_CLK_SEL_WRPLL1:
 398                 plls->wrpll1_refcount--;
 399                 if (plls->wrpll1_refcount == 0) {
 400                         DRM_DEBUG_KMS("Disabling WRPLL 1\n");
 401                         val = I915_READ(WRPLL_CTL1);
 402                         WARN_ON(!(val & WRPLL_PLL_ENABLE));
 403                         I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
 404                         POSTING_READ(WRPLL_CTL1);
 405                 }
 406                 break;
 407         case PORT_CLK_SEL_WRPLL2:
 408                 plls->wrpll2_refcount--;
 409                 if (plls->wrpll2_refcount == 0) {
 410                         DRM_DEBUG_KMS("Disabling WRPLL 2\n");
 411                         val = I915_READ(WRPLL_CTL2);
 412                         WARN_ON(!(val & WRPLL_PLL_ENABLE));
 413                         I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
 414                         POSTING_READ(WRPLL_CTL2);
 415                 }
 416                 break;
 417         }
 418
 419         WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
 420         WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
 421
 422         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
 423 }
 424
 425 #define LC_FREQ 2700
 426 #define LC_FREQ_2K (LC_FREQ * 2000)
 427
 428 #define P_MIN 2
 429 #define P_MAX 64
 430 #define P_INC 2
 431
 432 /* Constraints for PLL good behavior */
 433 #define REF_MIN 48
 434 #define REF_MAX 400
 435 #define VCO_MIN 2400
 436 #define VCO_MAX 4800
 437
 438 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
 439
 440 struct wrpll_rnp {
 441         unsigned p, n2, r2;
 442 };
 443
 444 static unsigned wrpll_get_budget_for_freq(int clock)
 445 {
 446         unsigned budget;
 447
 448         switch (clock) {
 449         case 25175000:
 450         case 25200000:
 451         case 27000000:
 452         case 27027000:
 453         case 37762500:
 454         case 37800000:
 455         case 40500000:
 456         case 40541000:
 457         case 54000000:
 458         case 54054000:
 459         case 59341000:
 460         case 59400000:
 461         case 72000000:
 462         case 74176000:
 463         case 74250000:
 464         case 81000000:
 465         case 81081000:
 466         case 89012000:
 467         case 89100000:
 468         case 108000000:
 469         case 108108000:
 470         case 111264000:
 471         case 111375000:
 472         case 148352000:
 473         case 148500000:
 474         case 162000000:
 475         case 162162000:
 476         case 222525000:
 477         case 222750000:
 478         case 296703000:
 479         case 297000000:
 480                 budget = 0;
 481                 break;
 482         case 233500000:
 483         case 245250000:
 484         case 247750000:
 485         case 253250000:
 486         case 298000000:
 487                 budget = 1500;
 488                 break;
 489         case 169128000:
 490         case 169500000:
 491         case 179500000:
 492         case 202000000:
 493                 budget = 2000;
 494                 break;
 495         case 256250000:
 496         case 262500000:
 497         case 270000000:
 498         case 272500000:
 499         case 273750000:
 500         case 280750000:
 501         case 281250000:
 502         case 286000000:
 503         case 291750000:
 504                 budget = 4000;
 505                 break;
 506         case 267250000:
 507         case 268500000:
 508                 budget = 5000;
 509                 break;
 510         default:
 511                 budget = 1000;
 512                 break;
 513         }
 514
 515         return budget;
 516 }
 517
 518 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 519                              unsigned r2, unsigned n2, unsigned p,
 520                              struct wrpll_rnp *best)
 521 {
 522         uint64_t a, b, c, d, diff, diff_best;
 523
 524         /* No best (r,n,p) yet */
 525         if (best->p == 0) {
 526                 best->p = p;
 527                 best->n2 = n2;
 528                 best->r2 = r2;
 529                 return;
 530         }
 531
 532         /*
 533          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 534          * freq2k.
 535          *
 536          * delta = 1e6 *
 537          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 538          *         freq2k;
 539          *
 540          * and we would like delta <= budget.
 541          *
 542          * If the discrepancy is above the PPM-based budget, always prefer to
 543          * improve upon the previous solution.  However, if you're within the
 544          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 545          */
 546         a = freq2k * budget * p * r2;
 547         b = freq2k * budget * best->p * best->r2;
 548         diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
 549         diff_best = ABS_DIFF((freq2k * best->p * best->r2),
 550                              (LC_FREQ_2K * best->n2));
 551         c = 1000000 * diff;
 552         d = 1000000 * diff_best;
 553
 554         if (a < c && b < d) {
 555                 /* If both are above the budget, pick the closer */
 556                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 557                         best->p = p;
 558                         best->n2 = n2;
 559                         best->r2 = r2;
 560                 }
 561         } else if (a >= c && b < d) {
 562                 /* If A is below the threshold but B is above it?  Update. */
 563                 best->p = p;
 564                 best->n2 = n2;
 565                 best->r2 = r2;
 566         } else if (a >= c && b >= d) {
 567                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 568                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 569                         best->p = p;
 570                         best->n2 = n2;
 571                         best->r2 = r2;
 572                 }
 573         }
 574         /* Otherwise a < c && b >= d, do nothing */
 575 }
 576
 577 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 578                                      int reg)
 579 {
 580         int refclk = LC_FREQ;
 581         int n, p, r;
 582         u32 wrpll;
 583
 584         wrpll = I915_READ(reg);
 585         switch (wrpll & WRPLL_PLL_REF_MASK) {
 586         case WRPLL_PLL_SSC:
 587         case WRPLL_PLL_NON_SSC:
 588                 /*
 589                  * We could calculate spread here, but our checking
 590                  * code only cares about 5% accuracy, and spread is a max of
 591                  * 0.5% downspread.
 592                  */
 593                 refclk = 135;
 594                 break;
 595         case WRPLL_PLL_LCPLL:
 596                 refclk = LC_FREQ;
 597                 break;
 598         default:
 599                 WARN(1, "bad wrpll refclk\n");
 600                 return 0;
 601         }
 602
 603         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 604         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 605         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 606
 607         /* Convert to KHz, p & r have a fixed point portion */
 608         return (refclk * n * 100) / (p * r);
 609 }
 610
 611 static void intel_ddi_clock_get(struct intel_encoder *encoder,
 612                                 struct intel_crtc_config *pipe_config)
 613 {
 614         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 615         enum port port = intel_ddi_get_encoder_port(encoder);
 616         int link_clock = 0;
 617         u32 val, pll;
 618
 619         val = I915_READ(PORT_CLK_SEL(port));
 620         switch (val & PORT_CLK_SEL_MASK) {
 621         case PORT_CLK_SEL_LCPLL_810:
 622                 link_clock = 81000;
 623                 break;
 624         case PORT_CLK_SEL_LCPLL_1350:
 625                 link_clock = 135000;
 626                 break;
 627         case PORT_CLK_SEL_LCPLL_2700:
 628                 link_clock = 270000;
 629                 break;
 630         case PORT_CLK_SEL_WRPLL1:
 631                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
 632                 break;
 633         case PORT_CLK_SEL_WRPLL2:
 634                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
 635                 break;
 636         case PORT_CLK_SEL_SPLL:
 637                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 638                 if (pll == SPLL_PLL_FREQ_810MHz)
 639                         link_clock = 81000;
 640                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 641                         link_clock = 135000;
 642                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 643                         link_clock = 270000;
 644                 else {
 645                         WARN(1, "bad spll freq\n");
 646                         return;
 647                 }
 648                 break;
 649         default:
 650                 WARN(1, "bad port clock sel\n");
 651                 return;
 652         }
 653
 654         pipe_config->port_clock = link_clock * 2;
 655
 656         if (pipe_config->has_pch_encoder)
 657                 pipe_config->adjusted_mode.crtc_clock =
 658                         intel_dotclock_calculate(pipe_config->port_clock,
 659                                                  &pipe_config->fdi_m_n);
 660         else if (pipe_config->has_dp_encoder)
 661                 pipe_config->adjusted_mode.crtc_clock =
 662                         intel_dotclock_calculate(pipe_config->port_clock,
 663                                                  &pipe_config->dp_m_n);
 664         else
 665                 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
 666 }
 667
 668 static void
 669 intel_ddi_calculate_wrpll(int clock /* in Hz */,
 670                           unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 671 {
 672         uint64_t freq2k;
 673         unsigned p, n2, r2;
 674         struct wrpll_rnp best = { 0, 0, 0 };
 675         unsigned budget;
 676
 677         freq2k = clock / 100;
 678
 679         budget = wrpll_get_budget_for_freq(clock);
 680
 681         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 682          * and directly pass the LC PLL to it. */
 683         if (freq2k == 5400000) {
 684                 *n2_out = 2;
 685                 *p_out = 1;
 686                 *r2_out = 2;
 687                 return;
 688         }
 689
 690         /*
 691          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 692          * the WR PLL.
 693          *
 694          * We want R so that REF_MIN <= Ref <= REF_MAX.
 695          * Injecting R2 = 2 * R gives:
 696          *   REF_MAX * r2 > LC_FREQ * 2 and
 697          *   REF_MIN * r2 < LC_FREQ * 2
 698          *
 699          * Which means the desired boundaries for r2 are:
 700          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 701          *
 702          */
 703         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 704              r2 <= LC_FREQ * 2 / REF_MIN;
 705              r2++) {
 706
 707                 /*
 708                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 709                  *
 710                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 711                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 712                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 713                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 714                  *
 715                  * Which means the desired boundaries for n2 are:
 716                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 717                  */
 718                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 719                      n2 <= VCO_MAX * r2 / LC_FREQ;
 720                      n2++) {
 721
 722                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 723                                 wrpll_update_rnp(freq2k, budget,
 724                                                  r2, n2, p, &best);
 725                 }
 726         }
 727
 728         *n2_out = best.n2;
 729         *p_out = best.p;
 730         *r2_out = best.r2;
 731 }
 732
 733 /*
 734  * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and
 735  * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to
 736  * steal the selected PLL. You need to call intel_ddi_pll_enable to actually
 737  * enable the PLL.
 738  */
 739 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 740 {
 741         struct drm_crtc *crtc = &intel_crtc->base;
 742         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 743         struct drm_encoder *encoder = &intel_encoder->base;
 744         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 745         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 746         int type = intel_encoder->type;
 747         enum pipe pipe = intel_crtc->pipe;
 748         int clock = intel_crtc->config.port_clock;
 749
 750         intel_ddi_put_crtc_pll(crtc);
 751
 752         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 753                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 754
 755                 switch (intel_dp->link_bw) {
 756                 case DP_LINK_BW_1_62:
 757                         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 758                         break;
 759                 case DP_LINK_BW_2_7:
 760                         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 761                         break;
 762                 case DP_LINK_BW_5_4:
 763                         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 764                         break;
 765                 default:
 766                         DRM_ERROR("Link bandwidth %d unsupported\n",
 767                                   intel_dp->link_bw);
 768                         return false;
 769                 }
 770
 771         } else if (type == INTEL_OUTPUT_HDMI) {
 772                 uint32_t reg, val;
 773                 unsigned p, n2, r2;
 774
 775                 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 776
 777                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 778                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 779                       WRPLL_DIVIDER_POST(p);
 780
 781                 if (val == I915_READ(WRPLL_CTL1)) {
 782                         DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
 783                                       pipe_name(pipe));
 784                         reg = WRPLL_CTL1;
 785                 } else if (val == I915_READ(WRPLL_CTL2)) {
 786                         DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
 787                                       pipe_name(pipe));
 788                         reg = WRPLL_CTL2;
 789                 } else if (plls->wrpll1_refcount == 0) {
 790                         DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
 791                                       pipe_name(pipe));
 792                         reg = WRPLL_CTL1;
 793                 } else if (plls->wrpll2_refcount == 0) {
 794                         DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
 795                                       pipe_name(pipe));
 796                         reg = WRPLL_CTL2;
 797                 } else {
 798                         DRM_ERROR("No WRPLLs available!\n");
 799                         return false;
 800                 }
 801
 802                 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
 803                               clock, p, n2, r2);
 804
 805                 if (reg == WRPLL_CTL1) {
 806                         plls->wrpll1_refcount++;
 807                         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
 808                 } else {
 809                         plls->wrpll2_refcount++;
 810                         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
 811                 }
 812
 813         } else if (type == INTEL_OUTPUT_ANALOG) {
 814                 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
 815                               pipe_name(pipe));
 816                 intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_SPLL;
 817         } else {
 818                 WARN(1, "Invalid DDI encoder type %d\n", type);
 819                 return false;
 820         }
 821
 822         return true;
 823 }
 824
 825 /*
 826  * To be called after intel_ddi_pll_select(). That one selects the PLL to be
 827  * used, this one actually enables the PLL.
 828  */
 829 void intel_ddi_pll_enable(struct intel_crtc *crtc)
 830 {
 831         struct drm_device *dev = crtc->base.dev;
 832         struct drm_i915_private *dev_priv = dev->dev_private;
 833         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 834         int clock = crtc->config.port_clock;
 835         uint32_t reg, cur_val, new_val;
 836         int refcount;
 837         const char *pll_name;
 838         uint32_t enable_bit = (1 << 31);
 839         unsigned int p, n2, r2;
 840
 841         BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
 842         BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
 843
 844         switch (crtc->config.ddi_pll_sel) {
 845         case PORT_CLK_SEL_WRPLL1:
 846         case PORT_CLK_SEL_WRPLL2:
 847                 if (crtc->config.ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
 848                         pll_name = "WRPLL1";
 849                         reg = WRPLL_CTL1;
 850                         refcount = plls->wrpll1_refcount;
 851                 } else {
 852                         pll_name = "WRPLL2";
 853                         reg = WRPLL_CTL2;
 854                         refcount = plls->wrpll2_refcount;
 855                 }
 856
 857                 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 858
 859                 new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 860                           WRPLL_DIVIDER_REFERENCE(r2) |
 861                           WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p);
 862
 863                 break;
 864
 865         case PORT_CLK_SEL_NONE:
 866                 WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
 867                 return;
 868         default:
 869                 return;
 870         }
 871
 872         cur_val = I915_READ(reg);
 873
 874         WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount);
 875         if (refcount == 1) {
 876                 WARN(cur_val & enable_bit, "%s already enabled\n", pll_name);
 877                 I915_WRITE(reg, new_val);
 878                 POSTING_READ(reg);
 879                 udelay(20);
 880         } else {
 881                 WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name);
 882         }
 883 }
 884
 885 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 886 {
 887         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 889         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 890         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 891         int type = intel_encoder->type;
 892         uint32_t temp;
 893
 894         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 895
 896                 temp = TRANS_MSA_SYNC_CLK;
 897                 switch (intel_crtc->config.pipe_bpp) {
 898                 case 18:
 899                         temp |= TRANS_MSA_6_BPC;
 900                         break;
 901                 case 24:
 902                         temp |= TRANS_MSA_8_BPC;
 903                         break;
 904                 case 30:
 905                         temp |= TRANS_MSA_10_BPC;
 906                         break;
 907                 case 36:
 908                         temp |= TRANS_MSA_12_BPC;
 909                         break;
 910                 default:
 911                         BUG();
 912                 }
 913                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 914         }
 915 }
 916
 917 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 918 {
 919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 920         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 921         struct drm_encoder *encoder = &intel_encoder->base;
 922         struct drm_device *dev = crtc->dev;
 923         struct drm_i915_private *dev_priv = dev->dev_private;
 924         enum pipe pipe = intel_crtc->pipe;
 925         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 926         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 927         int type = intel_encoder->type;
 928         uint32_t temp;
 929
 930         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 931         temp = TRANS_DDI_FUNC_ENABLE;
 932         temp |= TRANS_DDI_SELECT_PORT(port);
 933
 934         switch (intel_crtc->config.pipe_bpp) {
 935         case 18:
 936                 temp |= TRANS_DDI_BPC_6;
 937                 break;
 938         case 24:
 939                 temp |= TRANS_DDI_BPC_8;
 940                 break;
 941         case 30:
 942                 temp |= TRANS_DDI_BPC_10;
 943                 break;
 944         case 36:
 945                 temp |= TRANS_DDI_BPC_12;
 946                 break;
 947         default:
 948                 BUG();
 949         }
 950
 951         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 952                 temp |= TRANS_DDI_PVSYNC;
 953         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 954                 temp |= TRANS_DDI_PHSYNC;
 955
 956         if (cpu_transcoder == TRANSCODER_EDP) {
 957                 switch (pipe) {
 958                 case PIPE_A:
 959                         /* On Haswell, can only use the always-on power well for
 960                          * eDP when not using the panel fitter, and when not
 961                          * using motion blur mitigation (which we don't
 962                          * support). */
 963                         if (IS_HASWELL(dev) &&
 964                             (intel_crtc->config.pch_pfit.enabled ||
 965                              intel_crtc->config.pch_pfit.force_thru))
 966                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 967                         else
 968                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 969                         break;
 970                 case PIPE_B:
 971                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 972                         break;
 973                 case PIPE_C:
 974                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 975                         break;
 976                 default:
 977                         BUG();
 978                         break;
 979                 }
 980         }
 981
 982         if (type == INTEL_OUTPUT_HDMI) {
 983                 if (intel_crtc->config.has_hdmi_sink)
 984                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 985                 else
 986                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 987
 988         } else if (type == INTEL_OUTPUT_ANALOG) {
 989                 temp |= TRANS_DDI_MODE_SELECT_FDI;
 990                 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
 991
 992         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
 993                    type == INTEL_OUTPUT_EDP) {
 994                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 995
 996                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 997
 998                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 999         } else {
1000                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1001                      intel_encoder->type, pipe_name(pipe));
1002         }
1003
1004         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1005 }
1006
1007 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1008                                        enum transcoder cpu_transcoder)
1009 {
1010         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1011         uint32_t val = I915_READ(reg);
1012
1013         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1014         val |= TRANS_DDI_PORT_NONE;
1015         I915_WRITE(reg, val);
1016 }
1017
1018 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1019 {
1020         struct drm_device *dev = intel_connector->base.dev;
1021         struct drm_i915_private *dev_priv = dev->dev_private;
1022         struct intel_encoder *intel_encoder = intel_connector->encoder;
1023         int type = intel_connector->base.connector_type;
1024         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1025         enum pipe pipe = 0;
1026         enum transcoder cpu_transcoder;
1027         enum intel_display_power_domain power_domain;
1028         uint32_t tmp;
1029
1030         power_domain = intel_display_port_power_domain(intel_encoder);
1031         if (!intel_display_power_enabled(dev_priv, power_domain))
1032                 return false;
1033
1034         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1035                 return false;
1036
1037         if (port == PORT_A)
1038                 cpu_transcoder = TRANSCODER_EDP;
1039         else
1040                 cpu_transcoder = (enum transcoder) pipe;
1041
1042         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1043
1044         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1045         case TRANS_DDI_MODE_SELECT_HDMI:
1046         case TRANS_DDI_MODE_SELECT_DVI:
1047                 return (type == DRM_MODE_CONNECTOR_HDMIA);
1048
1049         case TRANS_DDI_MODE_SELECT_DP_SST:
1050                 if (type == DRM_MODE_CONNECTOR_eDP)
1051                         return true;
1052         case TRANS_DDI_MODE_SELECT_DP_MST:
1053                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1054
1055         case TRANS_DDI_MODE_SELECT_FDI:
1056                 return (type == DRM_MODE_CONNECTOR_VGA);
1057
1058         default:
1059                 return false;
1060         }
1061 }
1062
1063 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1064                             enum pipe *pipe)
1065 {
1066         struct drm_device *dev = encoder->base.dev;
1067         struct drm_i915_private *dev_priv = dev->dev_private;
1068         enum port port = intel_ddi_get_encoder_port(encoder);
1069         enum intel_display_power_domain power_domain;
1070         u32 tmp;
1071         int i;
1072
1073         power_domain = intel_display_port_power_domain(encoder);
1074         if (!intel_display_power_enabled(dev_priv, power_domain))
1075                 return false;
1076
1077         tmp = I915_READ(DDI_BUF_CTL(port));
1078
1079         if (!(tmp & DDI_BUF_CTL_ENABLE))
1080                 return false;
1081
1082         if (port == PORT_A) {
1083                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1084
1085                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1086                 case TRANS_DDI_EDP_INPUT_A_ON:
1087                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1088                         *pipe = PIPE_A;
1089                         break;
1090                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1091                         *pipe = PIPE_B;
1092                         break;
1093                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1094                         *pipe = PIPE_C;
1095                         break;
1096                 }
1097
1098                 return true;
1099         } else {
1100                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1101                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1102
1103                         if ((tmp & TRANS_DDI_PORT_MASK)
1104                             == TRANS_DDI_SELECT_PORT(port)) {
1105                                 *pipe = i;
1106                                 return true;
1107                         }
1108                 }
1109         }
1110
1111         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1112
1113         return false;
1114 }
1115
1116 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1117                                        enum pipe pipe)
1118 {
1119         uint32_t temp, ret;
1120         enum port port = I915_MAX_PORTS;
1121         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122                                                                       pipe);
1123         int i;
1124
1125         if (cpu_transcoder == TRANSCODER_EDP) {
1126                 port = PORT_A;
1127         } else {
1128                 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1129                 temp &= TRANS_DDI_PORT_MASK;
1130
1131                 for (i = PORT_B; i <= PORT_E; i++)
1132                         if (temp == TRANS_DDI_SELECT_PORT(i))
1133                                 port = i;
1134         }
1135
1136         if (port == I915_MAX_PORTS) {
1137                 WARN(1, "Pipe %c enabled on an unknown port\n",
1138                      pipe_name(pipe));
1139                 ret = PORT_CLK_SEL_NONE;
1140         } else {
1141                 ret = I915_READ(PORT_CLK_SEL(port));
1142                 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1143                               "0x%08x\n", pipe_name(pipe), port_name(port),
1144                               ret);
1145         }
1146
1147         return ret;
1148 }
1149
1150 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1151 {
1152         struct drm_i915_private *dev_priv = dev->dev_private;
1153         enum pipe pipe;
1154         struct intel_crtc *intel_crtc;
1155
1156         dev_priv->ddi_plls.wrpll1_refcount = 0;
1157         dev_priv->ddi_plls.wrpll2_refcount = 0;
1158
1159         for_each_pipe(pipe) {
1160                 intel_crtc =
1161                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1162
1163                 if (!intel_crtc->active) {
1164                         intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
1165                         continue;
1166                 }
1167
1168                 intel_crtc->config.ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1169                                                                  pipe);
1170
1171                 switch (intel_crtc->config.ddi_pll_sel) {
1172                 case PORT_CLK_SEL_WRPLL1:
1173                         dev_priv->ddi_plls.wrpll1_refcount++;
1174                         break;
1175                 case PORT_CLK_SEL_WRPLL2:
1176                         dev_priv->ddi_plls.wrpll2_refcount++;
1177                         break;
1178                 }
1179         }
1180 }
1181
1182 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1183 {
1184         struct drm_crtc *crtc = &intel_crtc->base;
1185         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1186         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1187         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1188         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1189
1190         if (cpu_transcoder != TRANSCODER_EDP)
1191                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1192                            TRANS_CLK_SEL_PORT(port));
1193 }
1194
1195 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1196 {
1197         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1198         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1199
1200         if (cpu_transcoder != TRANSCODER_EDP)
1201                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1202                            TRANS_CLK_SEL_DISABLED);
1203 }
1204
1205 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1206 {
1207         struct drm_encoder *encoder = &intel_encoder->base;
1208         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1209         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1210         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1211         int type = intel_encoder->type;
1212
1213         if (crtc->config.has_audio) {
1214                 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
1215                                  pipe_name(crtc->pipe));
1216
1217                 /* write eld */
1218                 DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
1219                 intel_write_eld(encoder, &crtc->config.adjusted_mode);
1220         }
1221
1222         if (type == INTEL_OUTPUT_EDP) {
1223                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1224                 intel_edp_panel_on(intel_dp);
1225         }
1226
1227         WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1228         I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1229
1230         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1231                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1232                 struct intel_digital_port *intel_dig_port =
1233                         enc_to_dig_port(encoder);
1234
1235                 intel_dp->DP = intel_dig_port->saved_port_bits |
1236                                DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
1237                 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1238
1239                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1240                 intel_dp_start_link_train(intel_dp);
1241                 intel_dp_complete_link_train(intel_dp);
1242                 if (port != PORT_A)
1243                         intel_dp_stop_link_train(intel_dp);
1244         } else if (type == INTEL_OUTPUT_HDMI) {
1245                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1246
1247                 intel_hdmi->set_infoframes(encoder,
1248                                            crtc->config.has_hdmi_sink,
1249                                            &crtc->config.adjusted_mode);
1250         }
1251 }
1252
1253 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1254 {
1255         struct drm_encoder *encoder = &intel_encoder->base;
1256         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1257         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1258         int type = intel_encoder->type;
1259         uint32_t val;
1260         bool wait = false;
1261
1262         val = I915_READ(DDI_BUF_CTL(port));
1263         if (val & DDI_BUF_CTL_ENABLE) {
1264                 val &= ~DDI_BUF_CTL_ENABLE;
1265                 I915_WRITE(DDI_BUF_CTL(port), val);
1266                 wait = true;
1267         }
1268
1269         val = I915_READ(DP_TP_CTL(port));
1270         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1271         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1272         I915_WRITE(DP_TP_CTL(port), val);
1273
1274         if (wait)
1275                 intel_wait_ddi_buf_idle(dev_priv, port);
1276
1277         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1278                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1279                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1280                 intel_edp_panel_vdd_on(intel_dp);
1281                 intel_edp_panel_off(intel_dp);
1282         }
1283
1284         I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1285 }
1286
1287 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1288 {
1289         struct drm_encoder *encoder = &intel_encoder->base;
1290         struct drm_crtc *crtc = encoder->crtc;
1291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1292         int pipe = intel_crtc->pipe;
1293         struct drm_device *dev = encoder->dev;
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1296         int type = intel_encoder->type;
1297         uint32_t tmp;
1298
1299         if (type == INTEL_OUTPUT_HDMI) {
1300                 struct intel_digital_port *intel_dig_port =
1301                         enc_to_dig_port(encoder);
1302
1303                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1304                  * are ignored so nothing special needs to be done besides
1305                  * enabling the port.
1306                  */
1307                 I915_WRITE(DDI_BUF_CTL(port),
1308                            intel_dig_port->saved_port_bits |
1309                            DDI_BUF_CTL_ENABLE);
1310         } else if (type == INTEL_OUTPUT_EDP) {
1311                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1312
1313                 if (port == PORT_A)
1314                         intel_dp_stop_link_train(intel_dp);
1315
1316                 intel_edp_backlight_on(intel_dp);
1317                 intel_edp_psr_enable(intel_dp);
1318         }
1319
1320         if (intel_crtc->config.has_audio) {
1321                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1322                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1323                 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1324                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1325         }
1326 }
1327
1328 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1329 {
1330         struct drm_encoder *encoder = &intel_encoder->base;
1331         struct drm_crtc *crtc = encoder->crtc;
1332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1333         int pipe = intel_crtc->pipe;
1334         int type = intel_encoder->type;
1335         struct drm_device *dev = encoder->dev;
1336         struct drm_i915_private *dev_priv = dev->dev_private;
1337         uint32_t tmp;
1338
1339         /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
1340          * register is part of the power well on Haswell. */
1341         if (intel_crtc->config.has_audio) {
1342                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1343                 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1344                          (pipe * 4));
1345                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1346                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1347         }
1348
1349         if (type == INTEL_OUTPUT_EDP) {
1350                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1351
1352                 intel_edp_psr_disable(intel_dp);
1353                 intel_edp_backlight_off(intel_dp);
1354         }
1355 }
1356
1357 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1358 {
1359         struct drm_device *dev = dev_priv->dev;
1360         uint32_t lcpll = I915_READ(LCPLL_CTL);
1361         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1362
1363         if (lcpll & LCPLL_CD_SOURCE_FCLK) {
1364                 return 800000;
1365         } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) {
1366                 return 450000;
1367         } else if (freq == LCPLL_CLK_FREQ_450) {
1368                 return 450000;
1369         } else if (IS_HASWELL(dev)) {
1370                 if (IS_ULT(dev))
1371                         return 337500;
1372                 else
1373                         return 540000;
1374         } else {
1375                 if (freq == LCPLL_CLK_FREQ_54O_BDW)
1376                         return 540000;
1377                 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1378                         return 337500;
1379                 else
1380                         return 675000;
1381         }
1382 }
1383
1384 void intel_ddi_pll_init(struct drm_device *dev)
1385 {
1386         struct drm_i915_private *dev_priv = dev->dev_private;
1387         uint32_t val = I915_READ(LCPLL_CTL);
1388
1389         /* The LCPLL register should be turned on by the BIOS. For now let's
1390          * just check its state and print errors in case something is wrong.
1391          * Don't even try to turn it on.
1392          */
1393
1394         DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1395                       intel_ddi_get_cdclk_freq(dev_priv));
1396
1397         if (val & LCPLL_CD_SOURCE_FCLK)
1398                 DRM_ERROR("CDCLK source is not LCPLL\n");
1399
1400         if (val & LCPLL_PLL_DISABLE)
1401                 DRM_ERROR("LCPLL is disabled\n");
1402 }
1403
1404 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1405 {
1406         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1407         struct intel_dp *intel_dp = &intel_dig_port->dp;
1408         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1409         enum port port = intel_dig_port->port;
1410         uint32_t val;
1411         bool wait = false;
1412
1413         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1414                 val = I915_READ(DDI_BUF_CTL(port));
1415                 if (val & DDI_BUF_CTL_ENABLE) {
1416                         val &= ~DDI_BUF_CTL_ENABLE;
1417                         I915_WRITE(DDI_BUF_CTL(port), val);
1418                         wait = true;
1419                 }
1420
1421                 val = I915_READ(DP_TP_CTL(port));
1422                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1423                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1424                 I915_WRITE(DP_TP_CTL(port), val);
1425                 POSTING_READ(DP_TP_CTL(port));
1426
1427                 if (wait)
1428                         intel_wait_ddi_buf_idle(dev_priv, port);
1429         }
1430
1431         val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1432               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1433         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1434                 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1435         I915_WRITE(DP_TP_CTL(port), val);
1436         POSTING_READ(DP_TP_CTL(port));
1437
1438         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1439         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1440         POSTING_READ(DDI_BUF_CTL(port));
1441
1442         udelay(600);
1443 }
1444
1445 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1446 {
1447         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1448         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1449         uint32_t val;
1450
1451         intel_ddi_post_disable(intel_encoder);
1452
1453         val = I915_READ(_FDI_RXA_CTL);
1454         val &= ~FDI_RX_ENABLE;
1455         I915_WRITE(_FDI_RXA_CTL, val);
1456
1457         val = I915_READ(_FDI_RXA_MISC);
1458         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1459         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1460         I915_WRITE(_FDI_RXA_MISC, val);
1461
1462         val = I915_READ(_FDI_RXA_CTL);
1463         val &= ~FDI_PCDCLK;
1464         I915_WRITE(_FDI_RXA_CTL, val);
1465
1466         val = I915_READ(_FDI_RXA_CTL);
1467         val &= ~FDI_RX_PLL_ENABLE;
1468         I915_WRITE(_FDI_RXA_CTL, val);
1469 }
1470
1471 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1472 {
1473         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1474         int type = intel_encoder->type;
1475
1476         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1477                 intel_dp_check_link_status(intel_dp);
1478 }
1479
1480 void intel_ddi_get_config(struct intel_encoder *encoder,
1481                           struct intel_crtc_config *pipe_config)
1482 {
1483         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1484         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1485         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1486         u32 temp, flags = 0;
1487
1488         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1489         if (temp & TRANS_DDI_PHSYNC)
1490                 flags |= DRM_MODE_FLAG_PHSYNC;
1491         else
1492                 flags |= DRM_MODE_FLAG_NHSYNC;
1493         if (temp & TRANS_DDI_PVSYNC)
1494                 flags |= DRM_MODE_FLAG_PVSYNC;
1495         else
1496                 flags |= DRM_MODE_FLAG_NVSYNC;
1497
1498         pipe_config->adjusted_mode.flags |= flags;
1499
1500         switch (temp & TRANS_DDI_BPC_MASK) {
1501         case TRANS_DDI_BPC_6:
1502                 pipe_config->pipe_bpp = 18;
1503                 break;
1504         case TRANS_DDI_BPC_8:
1505                 pipe_config->pipe_bpp = 24;
1506                 break;
1507         case TRANS_DDI_BPC_10:
1508                 pipe_config->pipe_bpp = 30;
1509                 break;
1510         case TRANS_DDI_BPC_12:
1511                 pipe_config->pipe_bpp = 36;
1512                 break;
1513         default:
1514                 break;
1515         }
1516
1517         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1518         case TRANS_DDI_MODE_SELECT_HDMI:
1519                 pipe_config->has_hdmi_sink = true;
1520         case TRANS_DDI_MODE_SELECT_DVI:
1521         case TRANS_DDI_MODE_SELECT_FDI:
1522                 break;
1523         case TRANS_DDI_MODE_SELECT_DP_SST:
1524         case TRANS_DDI_MODE_SELECT_DP_MST:
1525                 pipe_config->has_dp_encoder = true;
1526                 intel_dp_get_m_n(intel_crtc, pipe_config);
1527                 break;
1528         default:
1529                 break;
1530         }
1531
1532         if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1533                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1534                 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
1535                         pipe_config->has_audio = true;
1536         }
1537
1538         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1539             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1540                 /*
1541                  * This is a big fat ugly hack.
1542                  *
1543                  * Some machines in UEFI boot mode provide us a VBT that has 18
1544                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1545                  * unknown we fail to light up. Yet the same BIOS boots up with
1546                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1547                  * max, not what it tells us to use.
1548                  *
1549                  * Note: This will still be broken if the eDP panel is not lit
1550                  * up by the BIOS, and thus we can't get the mode at module
1551                  * load.
1552                  */
1553                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1554                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1555                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1556         }
1557
1558         intel_ddi_clock_get(encoder, pipe_config);
1559 }
1560
1561 static void intel_ddi_destroy(struct drm_encoder *encoder)
1562 {
1563         /* HDMI has nothing special to destroy, so we can go with this. */
1564         intel_dp_encoder_destroy(encoder);
1565 }
1566
1567 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1568                                      struct intel_crtc_config *pipe_config)
1569 {
1570         int type = encoder->type;
1571         int port = intel_ddi_get_encoder_port(encoder);
1572
1573         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1574
1575         if (port == PORT_A)
1576                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1577
1578         if (type == INTEL_OUTPUT_HDMI)
1579                 return intel_hdmi_compute_config(encoder, pipe_config);
1580         else
1581                 return intel_dp_compute_config(encoder, pipe_config);
1582 }
1583
1584 static const struct drm_encoder_funcs intel_ddi_funcs = {
1585         .destroy = intel_ddi_destroy,
1586 };
1587
1588 static struct intel_connector *
1589 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1590 {
1591         struct intel_connector *connector;
1592         enum port port = intel_dig_port->port;
1593
1594         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1595         if (!connector)
1596                 return NULL;
1597
1598         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1599         if (!intel_dp_init_connector(intel_dig_port, connector)) {
1600                 kfree(connector);
1601                 return NULL;
1602         }
1603
1604         return connector;
1605 }
1606
1607 static struct intel_connector *
1608 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1609 {
1610         struct intel_connector *connector;
1611         enum port port = intel_dig_port->port;
1612
1613         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1614         if (!connector)
1615                 return NULL;
1616
1617         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1618         intel_hdmi_init_connector(intel_dig_port, connector);
1619
1620         return connector;
1621 }
1622
1623 void intel_ddi_init(struct drm_device *dev, enum port port)
1624 {
1625         struct drm_i915_private *dev_priv = dev->dev_private;
1626         struct intel_digital_port *intel_dig_port;
1627         struct intel_encoder *intel_encoder;
1628         struct drm_encoder *encoder;
1629         struct intel_connector *hdmi_connector = NULL;
1630         struct intel_connector *dp_connector = NULL;
1631         bool init_hdmi, init_dp;
1632
1633         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1634                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1635         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1636         if (!init_dp && !init_hdmi) {
1637                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
1638                               port_name(port));
1639                 init_hdmi = true;
1640                 init_dp = true;
1641         }
1642
1643         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1644         if (!intel_dig_port)
1645                 return;
1646
1647         intel_encoder = &intel_dig_port->base;
1648         encoder = &intel_encoder->base;
1649
1650         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1651                          DRM_MODE_ENCODER_TMDS);
1652
1653         intel_encoder->compute_config = intel_ddi_compute_config;
1654         intel_encoder->enable = intel_enable_ddi;
1655         intel_encoder->pre_enable = intel_ddi_pre_enable;
1656         intel_encoder->disable = intel_disable_ddi;
1657         intel_encoder->post_disable = intel_ddi_post_disable;
1658         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1659         intel_encoder->get_config = intel_ddi_get_config;
1660
1661         intel_dig_port->port = port;
1662         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1663                                           (DDI_BUF_PORT_REVERSAL |
1664                                            DDI_A_4_LANES);
1665
1666         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1667         intel_encoder->crtc_mask =  (1 << 0) | (1 << 1) | (1 << 2);
1668         intel_encoder->cloneable = 0;
1669         intel_encoder->hot_plug = intel_ddi_hot_plug;
1670
1671         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
1672         dev_priv->hpd_irq_port[port] = intel_dig_port;
1673
1674         if (init_dp)
1675                 dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
1676
1677         /* In theory we don't need the encoder->type check, but leave it just in
1678          * case we have some really bad VBTs... */
1679         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
1680                 hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
1681
1682         if (!dp_connector && !hdmi_connector) {
1683                 drm_encoder_cleanup(encoder);
1684                 kfree(intel_dig_port);
1685         }
1686 }