2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
40 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
52 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
80 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
92 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
98 { 0x00DB6FFF, 0x00160005 },
99 { 0x80C71FFF, 0x001A0002 },
100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
104 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
130 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
133 { 0x00006012, 0x00000088 },
134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
136 { 0x00004014, 0x00000088 },
137 { 0x00006012, 0x00000087 },
138 { 0x00000018, 0x00000088 },
139 { 0x00004014, 0x00000087 },
142 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
143 /* Idx NT mV T mV db */
144 { 0x00000018, 0x000000a0 }, /* 0: 400 400 0 */
145 { 0x00004014, 0x00000098 }, /* 1: 400 600 3.5 */
146 { 0x00006012, 0x00000088 }, /* 2: 400 800 6 */
147 { 0x00000018, 0x0000003c }, /* 3: 450 450 0 */
148 { 0x00000018, 0x00000098 }, /* 4: 600 600 0 */
149 { 0x00003015, 0x00000088 }, /* 5: 600 800 2.5 */
150 { 0x00005013, 0x00000080 }, /* 6: 600 1000 4.5 */
151 { 0x00000018, 0x00000088 }, /* 7: 800 800 0 */
152 { 0x00000096, 0x00000080 }, /* 8: 800 1000 2 */
153 { 0x00000018, 0x00000080 }, /* 9: 1200 1200 0 */
156 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
158 struct drm_encoder *encoder = &intel_encoder->base;
159 int type = intel_encoder->type;
161 if (type == INTEL_OUTPUT_DP_MST) {
162 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
163 return intel_dig_port->port;
164 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
165 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
166 struct intel_digital_port *intel_dig_port =
167 enc_to_dig_port(encoder);
168 return intel_dig_port->port;
170 } else if (type == INTEL_OUTPUT_ANALOG) {
174 DRM_ERROR("Invalid DDI encoder type %d\n", type);
180 * Starting with Haswell, DDI port buffers must be programmed with correct
181 * values in advance. The buffer values are different for FDI and DP modes,
182 * but the HDMI/DVI fields are shared among those. So we program the DDI
183 * in either FDI or DP modes only, as HDMI connections will work with both
186 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
188 struct drm_i915_private *dev_priv = dev->dev_private;
190 int i, n_hdmi_entries, hdmi_800mV_0dB;
191 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
192 const struct ddi_buf_trans *ddi_translations_fdi;
193 const struct ddi_buf_trans *ddi_translations_dp;
194 const struct ddi_buf_trans *ddi_translations_edp;
195 const struct ddi_buf_trans *ddi_translations_hdmi;
196 const struct ddi_buf_trans *ddi_translations;
198 if (IS_SKYLAKE(dev)) {
199 ddi_translations_fdi = NULL;
200 ddi_translations_dp = skl_ddi_translations_dp;
201 ddi_translations_edp = skl_ddi_translations_dp;
202 ddi_translations_hdmi = skl_ddi_translations_hdmi;
203 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
205 } else if (IS_BROADWELL(dev)) {
206 ddi_translations_fdi = bdw_ddi_translations_fdi;
207 ddi_translations_dp = bdw_ddi_translations_dp;
208 ddi_translations_edp = bdw_ddi_translations_edp;
209 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
210 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
212 } else if (IS_HASWELL(dev)) {
213 ddi_translations_fdi = hsw_ddi_translations_fdi;
214 ddi_translations_dp = hsw_ddi_translations_dp;
215 ddi_translations_edp = hsw_ddi_translations_dp;
216 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
217 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
220 WARN(1, "ddi translation table missing\n");
221 ddi_translations_edp = bdw_ddi_translations_dp;
222 ddi_translations_fdi = bdw_ddi_translations_fdi;
223 ddi_translations_dp = bdw_ddi_translations_dp;
224 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
225 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
231 ddi_translations = ddi_translations_edp;
235 ddi_translations = ddi_translations_dp;
238 if (intel_dp_is_edp(dev, PORT_D))
239 ddi_translations = ddi_translations_edp;
241 ddi_translations = ddi_translations_dp;
244 if (ddi_translations_fdi)
245 ddi_translations = ddi_translations_fdi;
247 ddi_translations = ddi_translations_dp;
253 for (i = 0, reg = DDI_BUF_TRANS(port);
254 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
255 I915_WRITE(reg, ddi_translations[i].trans1);
257 I915_WRITE(reg, ddi_translations[i].trans2);
261 /* Choose a good default if VBT is badly populated */
262 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
263 hdmi_level >= n_hdmi_entries)
264 hdmi_level = hdmi_800mV_0dB;
266 /* Entry 9 is for HDMI: */
267 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
269 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
273 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
274 * mode and port E for FDI.
276 void intel_prepare_ddi(struct drm_device *dev)
283 for (port = PORT_A; port <= PORT_E; port++)
284 intel_prepare_ddi_buffers(dev, port);
287 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
290 uint32_t reg = DDI_BUF_CTL(port);
293 for (i = 0; i < 8; i++) {
295 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
298 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
301 /* Starting with Haswell, different DDI ports can work in FDI mode for
302 * connection to the PCH-located connectors. For this, it is necessary to train
303 * both the DDI port and PCH receiver for the desired DDI buffer settings.
305 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
306 * please note that when FDI mode is active on DDI E, it shares 2 lines with
307 * DDI A (which is used for eDP)
310 void hsw_fdi_link_train(struct drm_crtc *crtc)
312 struct drm_device *dev = crtc->dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
315 u32 temp, i, rx_ctl_val;
317 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
318 * mode set "sequence for CRT port" document:
319 * - TP1 to TP2 time with the default value
322 * WaFDIAutoLinkSetTimingOverrride:hsw
324 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
325 FDI_RX_PWRDN_LANE0_VAL(2) |
326 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
328 /* Enable the PCH Receiver FDI PLL */
329 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
331 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
332 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
333 POSTING_READ(_FDI_RXA_CTL);
336 /* Switch from Rawclk to PCDclk */
337 rx_ctl_val |= FDI_PCDCLK;
338 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
340 /* Configure Port Clock Select */
341 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
342 WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
344 /* Start the training iterating through available voltages and emphasis,
345 * testing each value twice. */
346 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
347 /* Configure DP_TP_CTL with auto-training */
348 I915_WRITE(DP_TP_CTL(PORT_E),
349 DP_TP_CTL_FDI_AUTOTRAIN |
350 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
351 DP_TP_CTL_LINK_TRAIN_PAT1 |
354 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
355 * DDI E does not support port reversal, the functionality is
356 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
357 * port reversal bit */
358 I915_WRITE(DDI_BUF_CTL(PORT_E),
360 ((intel_crtc->config.fdi_lanes - 1) << 1) |
361 DDI_BUF_TRANS_SELECT(i / 2));
362 POSTING_READ(DDI_BUF_CTL(PORT_E));
366 /* Program PCH FDI Receiver TU */
367 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
369 /* Enable PCH FDI Receiver with auto-training */
370 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
371 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
372 POSTING_READ(_FDI_RXA_CTL);
374 /* Wait for FDI receiver lane calibration */
377 /* Unset FDI_RX_MISC pwrdn lanes */
378 temp = I915_READ(_FDI_RXA_MISC);
379 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
380 I915_WRITE(_FDI_RXA_MISC, temp);
381 POSTING_READ(_FDI_RXA_MISC);
383 /* Wait for FDI auto training time */
386 temp = I915_READ(DP_TP_STATUS(PORT_E));
387 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
388 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
390 /* Enable normal pixel sending for FDI */
391 I915_WRITE(DP_TP_CTL(PORT_E),
392 DP_TP_CTL_FDI_AUTOTRAIN |
393 DP_TP_CTL_LINK_TRAIN_NORMAL |
394 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
400 temp = I915_READ(DDI_BUF_CTL(PORT_E));
401 temp &= ~DDI_BUF_CTL_ENABLE;
402 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
403 POSTING_READ(DDI_BUF_CTL(PORT_E));
405 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
406 temp = I915_READ(DP_TP_CTL(PORT_E));
407 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
408 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
409 I915_WRITE(DP_TP_CTL(PORT_E), temp);
410 POSTING_READ(DP_TP_CTL(PORT_E));
412 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
414 rx_ctl_val &= ~FDI_RX_ENABLE;
415 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
416 POSTING_READ(_FDI_RXA_CTL);
418 /* Reset FDI_RX_MISC pwrdn lanes */
419 temp = I915_READ(_FDI_RXA_MISC);
420 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
421 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
422 I915_WRITE(_FDI_RXA_MISC, temp);
423 POSTING_READ(_FDI_RXA_MISC);
426 DRM_ERROR("FDI link training failed!\n");
429 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
431 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
432 struct intel_digital_port *intel_dig_port =
433 enc_to_dig_port(&encoder->base);
435 intel_dp->DP = intel_dig_port->saved_port_bits |
436 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
437 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
441 static struct intel_encoder *
442 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
444 struct drm_device *dev = crtc->dev;
445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
446 struct intel_encoder *intel_encoder, *ret = NULL;
447 int num_encoders = 0;
449 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
454 if (num_encoders != 1)
455 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
456 pipe_name(intel_crtc->pipe));
462 static struct intel_encoder *
463 intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
465 struct drm_device *dev = crtc->base.dev;
466 struct intel_encoder *intel_encoder, *ret = NULL;
467 int num_encoders = 0;
469 for_each_intel_encoder(dev, intel_encoder) {
470 if (intel_encoder->new_crtc == crtc) {
476 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
477 pipe_name(crtc->pipe));
484 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
490 /* Constraints for PLL good behavior */
496 #define abs_diff(a, b) ({ \
497 typeof(a) __a = (a); \
498 typeof(b) __b = (b); \
499 (void) (&__a == &__b); \
500 __a > __b ? (__a - __b) : (__b - __a); })
506 static unsigned wrpll_get_budget_for_freq(int clock)
580 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
581 unsigned r2, unsigned n2, unsigned p,
582 struct wrpll_rnp *best)
584 uint64_t a, b, c, d, diff, diff_best;
586 /* No best (r,n,p) yet */
595 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
599 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
602 * and we would like delta <= budget.
604 * If the discrepancy is above the PPM-based budget, always prefer to
605 * improve upon the previous solution. However, if you're within the
606 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
608 a = freq2k * budget * p * r2;
609 b = freq2k * budget * best->p * best->r2;
610 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
611 diff_best = abs_diff(freq2k * best->p * best->r2,
612 LC_FREQ_2K * best->n2);
614 d = 1000000 * diff_best;
616 if (a < c && b < d) {
617 /* If both are above the budget, pick the closer */
618 if (best->p * best->r2 * diff < p * r2 * diff_best) {
623 } else if (a >= c && b < d) {
624 /* If A is below the threshold but B is above it? Update. */
628 } else if (a >= c && b >= d) {
629 /* Both are below the limit, so pick the higher n2/(r2*r2) */
630 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
636 /* Otherwise a < c && b >= d, do nothing */
639 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
642 int refclk = LC_FREQ;
646 wrpll = I915_READ(reg);
647 switch (wrpll & WRPLL_PLL_REF_MASK) {
649 case WRPLL_PLL_NON_SSC:
651 * We could calculate spread here, but our checking
652 * code only cares about 5% accuracy, and spread is a max of
657 case WRPLL_PLL_LCPLL:
661 WARN(1, "bad wrpll refclk\n");
665 r = wrpll & WRPLL_DIVIDER_REF_MASK;
666 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
667 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
669 /* Convert to KHz, p & r have a fixed point portion */
670 return (refclk * n * 100) / (p * r);
673 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
676 uint32_t cfgcr1_reg, cfgcr2_reg;
677 uint32_t cfgcr1_val, cfgcr2_val;
678 uint32_t p0, p1, p2, dco_freq;
680 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
681 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
683 cfgcr1_val = I915_READ(cfgcr1_reg);
684 cfgcr2_val = I915_READ(cfgcr2_reg);
686 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
687 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
689 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
690 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
696 case DPLL_CFGCR2_PDIV_1:
699 case DPLL_CFGCR2_PDIV_2:
702 case DPLL_CFGCR2_PDIV_3:
705 case DPLL_CFGCR2_PDIV_7:
711 case DPLL_CFGCR2_KDIV_5:
714 case DPLL_CFGCR2_KDIV_2:
717 case DPLL_CFGCR2_KDIV_3:
720 case DPLL_CFGCR2_KDIV_1:
725 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
727 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
730 return dco_freq / (p0 * p1 * p2 * 5);
734 static void skl_ddi_clock_get(struct intel_encoder *encoder,
735 struct intel_crtc_config *pipe_config)
737 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
739 uint32_t dpll_ctl1, dpll;
741 dpll = pipe_config->ddi_pll_sel;
743 dpll_ctl1 = I915_READ(DPLL_CTRL1);
745 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
746 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
748 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
749 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
751 switch (link_clock) {
752 case DPLL_CRTL1_LINK_RATE_810:
755 case DPLL_CRTL1_LINK_RATE_1350:
758 case DPLL_CRTL1_LINK_RATE_2700:
762 WARN(1, "Unsupported link rate\n");
768 pipe_config->port_clock = link_clock;
770 if (pipe_config->has_dp_encoder)
771 pipe_config->adjusted_mode.crtc_clock =
772 intel_dotclock_calculate(pipe_config->port_clock,
773 &pipe_config->dp_m_n);
775 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
778 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
779 struct intel_crtc_config *pipe_config)
781 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
785 val = pipe_config->ddi_pll_sel;
786 switch (val & PORT_CLK_SEL_MASK) {
787 case PORT_CLK_SEL_LCPLL_810:
790 case PORT_CLK_SEL_LCPLL_1350:
793 case PORT_CLK_SEL_LCPLL_2700:
796 case PORT_CLK_SEL_WRPLL1:
797 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
799 case PORT_CLK_SEL_WRPLL2:
800 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
802 case PORT_CLK_SEL_SPLL:
803 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
804 if (pll == SPLL_PLL_FREQ_810MHz)
806 else if (pll == SPLL_PLL_FREQ_1350MHz)
808 else if (pll == SPLL_PLL_FREQ_2700MHz)
811 WARN(1, "bad spll freq\n");
816 WARN(1, "bad port clock sel\n");
820 pipe_config->port_clock = link_clock * 2;
822 if (pipe_config->has_pch_encoder)
823 pipe_config->adjusted_mode.crtc_clock =
824 intel_dotclock_calculate(pipe_config->port_clock,
825 &pipe_config->fdi_m_n);
826 else if (pipe_config->has_dp_encoder)
827 pipe_config->adjusted_mode.crtc_clock =
828 intel_dotclock_calculate(pipe_config->port_clock,
829 &pipe_config->dp_m_n);
831 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
834 void intel_ddi_clock_get(struct intel_encoder *encoder,
835 struct intel_crtc_config *pipe_config)
837 struct drm_device *dev = encoder->base.dev;
839 if (INTEL_INFO(dev)->gen <= 8)
840 hsw_ddi_clock_get(encoder, pipe_config);
842 skl_ddi_clock_get(encoder, pipe_config);
846 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
847 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
851 struct wrpll_rnp best = { 0, 0, 0 };
854 freq2k = clock / 100;
856 budget = wrpll_get_budget_for_freq(clock);
858 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
859 * and directly pass the LC PLL to it. */
860 if (freq2k == 5400000) {
868 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
871 * We want R so that REF_MIN <= Ref <= REF_MAX.
872 * Injecting R2 = 2 * R gives:
873 * REF_MAX * r2 > LC_FREQ * 2 and
874 * REF_MIN * r2 < LC_FREQ * 2
876 * Which means the desired boundaries for r2 are:
877 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
880 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
881 r2 <= LC_FREQ * 2 / REF_MIN;
885 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
887 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
888 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
889 * VCO_MAX * r2 > n2 * LC_FREQ and
890 * VCO_MIN * r2 < n2 * LC_FREQ)
892 * Which means the desired boundaries for n2 are:
893 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
895 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
896 n2 <= VCO_MAX * r2 / LC_FREQ;
899 for (p = P_MIN; p <= P_MAX; p += P_INC)
900 wrpll_update_rnp(freq2k, budget,
911 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
912 struct intel_encoder *intel_encoder,
915 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
916 struct intel_shared_dpll *pll;
920 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
922 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
923 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
924 WRPLL_DIVIDER_POST(p);
926 intel_crtc->new_config->dpll_hw_state.wrpll = val;
928 pll = intel_get_shared_dpll(intel_crtc);
930 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
931 pipe_name(intel_crtc->pipe));
935 intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
941 struct skl_wrpll_params {
942 uint32_t dco_fraction;
943 uint32_t dco_integer;
948 uint32_t central_freq;
952 skl_ddi_calculate_wrpll(int clock /* in Hz */,
953 struct skl_wrpll_params *wrpll_params)
955 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
956 uint64_t dco_central_freq[3] = {8400000000ULL,
959 uint32_t min_dco_deviation = 400;
960 uint32_t min_dco_index = 3;
961 uint32_t P0[4] = {1, 2, 3, 7};
962 uint32_t P2[4] = {1, 2, 3, 5};
964 uint32_t candidate_p = 0;
965 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
966 uint32_t candidate_p2[3] = {0};
967 uint32_t dco_central_freq_deviation[3];
968 uint32_t i, P1, k, dco_count;
969 bool retry_with_odd = false;
972 /* Determine P0, P1 or P2 */
973 for (dco_count = 0; dco_count < 3; dco_count++) {
976 div64_u64(dco_central_freq[dco_count], afe_clock);
977 if (retry_with_odd == false)
978 candidate_p = (candidate_p % 2 == 0 ?
979 candidate_p : candidate_p + 1);
981 for (P1 = 1; P1 < candidate_p; P1++) {
982 for (i = 0; i < 4; i++) {
983 if (!(P0[i] != 1 || P1 == 1))
986 for (k = 0; k < 4; k++) {
987 if (P1 != 1 && P2[k] != 2)
990 if (candidate_p == P0[i] * P1 * P2[k]) {
991 /* Found possible P0, P1, P2 */
993 candidate_p0[dco_count] = P0[i];
994 candidate_p1[dco_count] = P1;
995 candidate_p2[dco_count] = P2[k];
1005 dco_central_freq_deviation[dco_count] =
1007 abs_diff((candidate_p * afe_clock),
1008 dco_central_freq[dco_count]),
1009 dco_central_freq[dco_count]);
1011 if (dco_central_freq_deviation[dco_count] <
1012 min_dco_deviation) {
1014 dco_central_freq_deviation[dco_count];
1015 min_dco_index = dco_count;
1019 if (min_dco_index > 2 && dco_count == 2) {
1020 retry_with_odd = true;
1025 if (min_dco_index > 2) {
1026 WARN(1, "No valid values found for the given pixel clock\n");
1028 wrpll_params->central_freq = dco_central_freq[min_dco_index];
1030 switch (dco_central_freq[min_dco_index]) {
1032 wrpll_params->central_freq = 0;
1035 wrpll_params->central_freq = 1;
1038 wrpll_params->central_freq = 3;
1041 switch (candidate_p0[min_dco_index]) {
1043 wrpll_params->pdiv = 0;
1046 wrpll_params->pdiv = 1;
1049 wrpll_params->pdiv = 2;
1052 wrpll_params->pdiv = 4;
1055 WARN(1, "Incorrect PDiv\n");
1058 switch (candidate_p2[min_dco_index]) {
1060 wrpll_params->kdiv = 0;
1063 wrpll_params->kdiv = 1;
1066 wrpll_params->kdiv = 2;
1069 wrpll_params->kdiv = 3;
1072 WARN(1, "Incorrect KDiv\n");
1075 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
1076 wrpll_params->qdiv_mode =
1077 (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
1079 dco_freq = candidate_p0[min_dco_index] *
1080 candidate_p1[min_dco_index] *
1081 candidate_p2[min_dco_index] * afe_clock;
1084 * Intermediate values are in Hz.
1085 * Divide by MHz to match bsepc
1087 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
1088 wrpll_params->dco_fraction =
1089 div_u64(((div_u64(dco_freq, 24) -
1090 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
1097 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1098 struct intel_encoder *intel_encoder,
1101 struct intel_shared_dpll *pll;
1102 uint32_t ctrl1, cfgcr1, cfgcr2;
1105 * See comment in intel_dpll_hw_state to understand why we always use 0
1106 * as the DPLL id in this function.
1109 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1111 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1112 struct skl_wrpll_params wrpll_params = { 0, };
1114 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1116 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
1118 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1119 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1120 wrpll_params.dco_integer;
1122 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1123 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1124 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1125 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1126 wrpll_params.central_freq;
1127 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1128 struct drm_encoder *encoder = &intel_encoder->base;
1129 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1131 switch (intel_dp->link_bw) {
1132 case DP_LINK_BW_1_62:
1133 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
1135 case DP_LINK_BW_2_7:
1136 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
1138 case DP_LINK_BW_5_4:
1139 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
1143 cfgcr1 = cfgcr2 = 0;
1147 intel_crtc->new_config->dpll_hw_state.ctrl1 = ctrl1;
1148 intel_crtc->new_config->dpll_hw_state.cfgcr1 = cfgcr1;
1149 intel_crtc->new_config->dpll_hw_state.cfgcr2 = cfgcr2;
1151 pll = intel_get_shared_dpll(intel_crtc);
1153 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1154 pipe_name(intel_crtc->pipe));
1158 /* shared DPLL id 0 is DPLL 1 */
1159 intel_crtc->new_config->ddi_pll_sel = pll->id + 1;
1165 * Tries to find a *shared* PLL for the CRTC and store it in
1166 * intel_crtc->ddi_pll_sel.
1168 * For private DPLLs, compute_config() should do the selection for us. This
1169 * function should be folded into compute_config() eventually.
1171 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
1173 struct drm_device *dev = intel_crtc->base.dev;
1174 struct intel_encoder *intel_encoder =
1175 intel_ddi_get_crtc_new_encoder(intel_crtc);
1176 int clock = intel_crtc->new_config->port_clock;
1178 if (IS_SKYLAKE(dev))
1179 return skl_ddi_pll_select(intel_crtc, intel_encoder, clock);
1181 return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
1184 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1186 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1188 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1189 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1190 int type = intel_encoder->type;
1193 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1194 temp = TRANS_MSA_SYNC_CLK;
1195 switch (intel_crtc->config.pipe_bpp) {
1197 temp |= TRANS_MSA_6_BPC;
1200 temp |= TRANS_MSA_8_BPC;
1203 temp |= TRANS_MSA_10_BPC;
1206 temp |= TRANS_MSA_12_BPC;
1211 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1215 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1218 struct drm_device *dev = crtc->dev;
1219 struct drm_i915_private *dev_priv = dev->dev_private;
1220 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1222 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1224 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1226 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1227 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1230 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1233 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1234 struct drm_encoder *encoder = &intel_encoder->base;
1235 struct drm_device *dev = crtc->dev;
1236 struct drm_i915_private *dev_priv = dev->dev_private;
1237 enum pipe pipe = intel_crtc->pipe;
1238 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1239 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1240 int type = intel_encoder->type;
1243 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1244 temp = TRANS_DDI_FUNC_ENABLE;
1245 temp |= TRANS_DDI_SELECT_PORT(port);
1247 switch (intel_crtc->config.pipe_bpp) {
1249 temp |= TRANS_DDI_BPC_6;
1252 temp |= TRANS_DDI_BPC_8;
1255 temp |= TRANS_DDI_BPC_10;
1258 temp |= TRANS_DDI_BPC_12;
1264 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1265 temp |= TRANS_DDI_PVSYNC;
1266 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1267 temp |= TRANS_DDI_PHSYNC;
1269 if (cpu_transcoder == TRANSCODER_EDP) {
1272 /* On Haswell, can only use the always-on power well for
1273 * eDP when not using the panel fitter, and when not
1274 * using motion blur mitigation (which we don't
1276 if (IS_HASWELL(dev) &&
1277 (intel_crtc->config.pch_pfit.enabled ||
1278 intel_crtc->config.pch_pfit.force_thru))
1279 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1281 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1284 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1287 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1295 if (type == INTEL_OUTPUT_HDMI) {
1296 if (intel_crtc->config.has_hdmi_sink)
1297 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1299 temp |= TRANS_DDI_MODE_SELECT_DVI;
1301 } else if (type == INTEL_OUTPUT_ANALOG) {
1302 temp |= TRANS_DDI_MODE_SELECT_FDI;
1303 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
1305 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1306 type == INTEL_OUTPUT_EDP) {
1307 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1309 if (intel_dp->is_mst) {
1310 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1312 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1314 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1315 } else if (type == INTEL_OUTPUT_DP_MST) {
1316 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1318 if (intel_dp->is_mst) {
1319 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1321 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1323 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1325 WARN(1, "Invalid encoder type %d for pipe %c\n",
1326 intel_encoder->type, pipe_name(pipe));
1329 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1332 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1333 enum transcoder cpu_transcoder)
1335 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1336 uint32_t val = I915_READ(reg);
1338 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1339 val |= TRANS_DDI_PORT_NONE;
1340 I915_WRITE(reg, val);
1343 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1345 struct drm_device *dev = intel_connector->base.dev;
1346 struct drm_i915_private *dev_priv = dev->dev_private;
1347 struct intel_encoder *intel_encoder = intel_connector->encoder;
1348 int type = intel_connector->base.connector_type;
1349 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1351 enum transcoder cpu_transcoder;
1352 enum intel_display_power_domain power_domain;
1355 power_domain = intel_display_port_power_domain(intel_encoder);
1356 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1359 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1363 cpu_transcoder = TRANSCODER_EDP;
1365 cpu_transcoder = (enum transcoder) pipe;
1367 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1369 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1370 case TRANS_DDI_MODE_SELECT_HDMI:
1371 case TRANS_DDI_MODE_SELECT_DVI:
1372 return (type == DRM_MODE_CONNECTOR_HDMIA);
1374 case TRANS_DDI_MODE_SELECT_DP_SST:
1375 if (type == DRM_MODE_CONNECTOR_eDP)
1377 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1378 case TRANS_DDI_MODE_SELECT_DP_MST:
1379 /* if the transcoder is in MST state then
1380 * connector isn't connected */
1383 case TRANS_DDI_MODE_SELECT_FDI:
1384 return (type == DRM_MODE_CONNECTOR_VGA);
1391 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1394 struct drm_device *dev = encoder->base.dev;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 enum port port = intel_ddi_get_encoder_port(encoder);
1397 enum intel_display_power_domain power_domain;
1401 power_domain = intel_display_port_power_domain(encoder);
1402 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1405 tmp = I915_READ(DDI_BUF_CTL(port));
1407 if (!(tmp & DDI_BUF_CTL_ENABLE))
1410 if (port == PORT_A) {
1411 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1413 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1414 case TRANS_DDI_EDP_INPUT_A_ON:
1415 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1418 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1421 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1428 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1429 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1431 if ((tmp & TRANS_DDI_PORT_MASK)
1432 == TRANS_DDI_SELECT_PORT(port)) {
1433 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1442 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1447 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1449 struct drm_crtc *crtc = &intel_crtc->base;
1450 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1451 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1452 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1453 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1455 if (cpu_transcoder != TRANSCODER_EDP)
1456 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1457 TRANS_CLK_SEL_PORT(port));
1460 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1462 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1463 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1465 if (cpu_transcoder != TRANSCODER_EDP)
1466 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1467 TRANS_CLK_SEL_DISABLED);
1470 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1472 struct drm_encoder *encoder = &intel_encoder->base;
1473 struct drm_device *dev = encoder->dev;
1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1476 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1477 int type = intel_encoder->type;
1479 if (type == INTEL_OUTPUT_EDP) {
1480 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1481 intel_edp_panel_on(intel_dp);
1484 if (IS_SKYLAKE(dev)) {
1485 uint32_t dpll = crtc->config.ddi_pll_sel;
1489 * DPLL0 is used for eDP and is the only "private" DPLL (as
1490 * opposed to shared) on SKL
1492 if (type == INTEL_OUTPUT_EDP) {
1493 WARN_ON(dpll != SKL_DPLL0);
1495 val = I915_READ(DPLL_CTRL1);
1497 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1498 DPLL_CTRL1_SSC(dpll) |
1499 DPLL_CRTL1_LINK_RATE_MASK(dpll));
1500 val |= crtc->config.dpll_hw_state.ctrl1 << (dpll * 6);
1502 I915_WRITE(DPLL_CTRL1, val);
1503 POSTING_READ(DPLL_CTRL1);
1506 /* DDI -> PLL mapping */
1507 val = I915_READ(DPLL_CTRL2);
1509 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1510 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1511 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1512 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1514 I915_WRITE(DPLL_CTRL2, val);
1517 WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1518 I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1521 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1522 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1524 intel_ddi_init_dp_buf_reg(intel_encoder);
1526 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1527 intel_dp_start_link_train(intel_dp);
1528 intel_dp_complete_link_train(intel_dp);
1529 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
1530 intel_dp_stop_link_train(intel_dp);
1531 } else if (type == INTEL_OUTPUT_HDMI) {
1532 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1534 intel_hdmi->set_infoframes(encoder,
1535 crtc->config.has_hdmi_sink,
1536 &crtc->config.adjusted_mode);
1540 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1542 struct drm_encoder *encoder = &intel_encoder->base;
1543 struct drm_device *dev = encoder->dev;
1544 struct drm_i915_private *dev_priv = dev->dev_private;
1545 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1546 int type = intel_encoder->type;
1550 val = I915_READ(DDI_BUF_CTL(port));
1551 if (val & DDI_BUF_CTL_ENABLE) {
1552 val &= ~DDI_BUF_CTL_ENABLE;
1553 I915_WRITE(DDI_BUF_CTL(port), val);
1557 val = I915_READ(DP_TP_CTL(port));
1558 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1559 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1560 I915_WRITE(DP_TP_CTL(port), val);
1563 intel_wait_ddi_buf_idle(dev_priv, port);
1565 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1566 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1567 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1568 intel_edp_panel_vdd_on(intel_dp);
1569 intel_edp_panel_off(intel_dp);
1572 if (IS_SKYLAKE(dev))
1573 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1574 DPLL_CTRL2_DDI_CLK_OFF(port)));
1576 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1579 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1581 struct drm_encoder *encoder = &intel_encoder->base;
1582 struct drm_crtc *crtc = encoder->crtc;
1583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1584 struct drm_device *dev = encoder->dev;
1585 struct drm_i915_private *dev_priv = dev->dev_private;
1586 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1587 int type = intel_encoder->type;
1589 if (type == INTEL_OUTPUT_HDMI) {
1590 struct intel_digital_port *intel_dig_port =
1591 enc_to_dig_port(encoder);
1593 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1594 * are ignored so nothing special needs to be done besides
1595 * enabling the port.
1597 I915_WRITE(DDI_BUF_CTL(port),
1598 intel_dig_port->saved_port_bits |
1599 DDI_BUF_CTL_ENABLE);
1600 } else if (type == INTEL_OUTPUT_EDP) {
1601 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1603 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1604 intel_dp_stop_link_train(intel_dp);
1606 intel_edp_backlight_on(intel_dp);
1607 intel_psr_enable(intel_dp);
1610 if (intel_crtc->config.has_audio) {
1611 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1612 intel_audio_codec_enable(intel_encoder);
1616 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1618 struct drm_encoder *encoder = &intel_encoder->base;
1619 struct drm_crtc *crtc = encoder->crtc;
1620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1621 int type = intel_encoder->type;
1622 struct drm_device *dev = encoder->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1625 if (intel_crtc->config.has_audio) {
1626 intel_audio_codec_disable(intel_encoder);
1627 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1630 if (type == INTEL_OUTPUT_EDP) {
1631 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1633 intel_psr_disable(intel_dp);
1634 intel_edp_backlight_off(intel_dp);
1638 static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
1640 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
1641 uint32_t cdctl = I915_READ(CDCLK_CTL);
1644 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
1645 WARN(1, "LCPLL1 not enabled\n");
1646 return 24000; /* 24MHz is the cd freq with NSSC ref */
1649 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
1652 linkrate = (I915_READ(DPLL_CTRL1) &
1653 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1655 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
1656 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
1658 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1659 case CDCLK_FREQ_450_432:
1661 case CDCLK_FREQ_337_308:
1663 case CDCLK_FREQ_675_617:
1666 WARN(1, "Unknown cd freq selection\n");
1670 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1671 case CDCLK_FREQ_450_432:
1673 case CDCLK_FREQ_337_308:
1675 case CDCLK_FREQ_675_617:
1678 WARN(1, "Unknown cd freq selection\n");
1682 /* error case, do as if DPLL0 isn't enabled */
1686 static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1688 uint32_t lcpll = I915_READ(LCPLL_CTL);
1689 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1691 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1693 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1695 else if (freq == LCPLL_CLK_FREQ_450)
1697 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1699 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1705 static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1707 struct drm_device *dev = dev_priv->dev;
1708 uint32_t lcpll = I915_READ(LCPLL_CTL);
1709 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1711 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1713 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1715 else if (freq == LCPLL_CLK_FREQ_450)
1717 else if (IS_HSW_ULT(dev))
1723 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1725 struct drm_device *dev = dev_priv->dev;
1727 if (IS_SKYLAKE(dev))
1728 return skl_get_cdclk_freq(dev_priv);
1730 if (IS_BROADWELL(dev))
1731 return bdw_get_cdclk_freq(dev_priv);
1734 return hsw_get_cdclk_freq(dev_priv);
1737 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1738 struct intel_shared_dpll *pll)
1740 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
1741 POSTING_READ(WRPLL_CTL(pll->id));
1745 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1746 struct intel_shared_dpll *pll)
1750 val = I915_READ(WRPLL_CTL(pll->id));
1751 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1752 POSTING_READ(WRPLL_CTL(pll->id));
1755 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1756 struct intel_shared_dpll *pll,
1757 struct intel_dpll_hw_state *hw_state)
1761 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1764 val = I915_READ(WRPLL_CTL(pll->id));
1765 hw_state->wrpll = val;
1767 return val & WRPLL_PLL_ENABLE;
1770 static const char * const hsw_ddi_pll_names[] = {
1775 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1779 dev_priv->num_shared_dpll = 2;
1781 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1782 dev_priv->shared_dplls[i].id = i;
1783 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1784 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1785 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1786 dev_priv->shared_dplls[i].get_hw_state =
1787 hsw_ddi_pll_get_hw_state;
1791 static const char * const skl_ddi_pll_names[] = {
1797 struct skl_dpll_regs {
1798 u32 ctl, cfgcr1, cfgcr2;
1801 /* this array is indexed by the *shared* pll id */
1802 static const struct skl_dpll_regs skl_dpll_regs[3] = {
1806 .cfgcr1 = DPLL1_CFGCR1,
1807 .cfgcr2 = DPLL1_CFGCR2,
1812 .cfgcr1 = DPLL2_CFGCR1,
1813 .cfgcr2 = DPLL2_CFGCR2,
1818 .cfgcr1 = DPLL3_CFGCR1,
1819 .cfgcr2 = DPLL3_CFGCR2,
1823 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1824 struct intel_shared_dpll *pll)
1828 const struct skl_dpll_regs *regs = skl_dpll_regs;
1830 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1833 val = I915_READ(DPLL_CTRL1);
1835 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
1836 DPLL_CRTL1_LINK_RATE_MASK(dpll));
1837 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
1839 I915_WRITE(DPLL_CTRL1, val);
1840 POSTING_READ(DPLL_CTRL1);
1842 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
1843 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
1844 POSTING_READ(regs[pll->id].cfgcr1);
1845 POSTING_READ(regs[pll->id].cfgcr2);
1847 /* the enable bit is always bit 31 */
1848 I915_WRITE(regs[pll->id].ctl,
1849 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
1851 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
1852 DRM_ERROR("DPLL %d not locked\n", dpll);
1855 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
1856 struct intel_shared_dpll *pll)
1858 const struct skl_dpll_regs *regs = skl_dpll_regs;
1860 /* the enable bit is always bit 31 */
1861 I915_WRITE(regs[pll->id].ctl,
1862 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
1863 POSTING_READ(regs[pll->id].ctl);
1866 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1867 struct intel_shared_dpll *pll,
1868 struct intel_dpll_hw_state *hw_state)
1872 const struct skl_dpll_regs *regs = skl_dpll_regs;
1874 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1877 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1880 val = I915_READ(regs[pll->id].ctl);
1881 if (!(val & LCPLL_PLL_ENABLE))
1884 val = I915_READ(DPLL_CTRL1);
1885 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
1887 /* avoid reading back stale values if HDMI mode is not enabled */
1888 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
1889 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
1890 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
1896 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
1900 dev_priv->num_shared_dpll = 3;
1902 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1903 dev_priv->shared_dplls[i].id = i;
1904 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
1905 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
1906 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
1907 dev_priv->shared_dplls[i].get_hw_state =
1908 skl_ddi_pll_get_hw_state;
1912 void intel_ddi_pll_init(struct drm_device *dev)
1914 struct drm_i915_private *dev_priv = dev->dev_private;
1915 uint32_t val = I915_READ(LCPLL_CTL);
1917 if (IS_SKYLAKE(dev))
1918 skl_shared_dplls_init(dev_priv);
1920 hsw_shared_dplls_init(dev_priv);
1922 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1923 intel_ddi_get_cdclk_freq(dev_priv));
1925 if (IS_SKYLAKE(dev)) {
1926 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
1927 DRM_ERROR("LCPLL1 is disabled\n");
1930 * The LCPLL register should be turned on by the BIOS. For now
1931 * let's just check its state and print errors in case
1932 * something is wrong. Don't even try to turn it on.
1935 if (val & LCPLL_CD_SOURCE_FCLK)
1936 DRM_ERROR("CDCLK source is not LCPLL\n");
1938 if (val & LCPLL_PLL_DISABLE)
1939 DRM_ERROR("LCPLL is disabled\n");
1943 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1945 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1946 struct intel_dp *intel_dp = &intel_dig_port->dp;
1947 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1948 enum port port = intel_dig_port->port;
1952 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1953 val = I915_READ(DDI_BUF_CTL(port));
1954 if (val & DDI_BUF_CTL_ENABLE) {
1955 val &= ~DDI_BUF_CTL_ENABLE;
1956 I915_WRITE(DDI_BUF_CTL(port), val);
1960 val = I915_READ(DP_TP_CTL(port));
1961 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1962 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1963 I915_WRITE(DP_TP_CTL(port), val);
1964 POSTING_READ(DP_TP_CTL(port));
1967 intel_wait_ddi_buf_idle(dev_priv, port);
1970 val = DP_TP_CTL_ENABLE |
1971 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1972 if (intel_dp->is_mst)
1973 val |= DP_TP_CTL_MODE_MST;
1975 val |= DP_TP_CTL_MODE_SST;
1976 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1977 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1979 I915_WRITE(DP_TP_CTL(port), val);
1980 POSTING_READ(DP_TP_CTL(port));
1982 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1983 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1984 POSTING_READ(DDI_BUF_CTL(port));
1989 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1991 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1992 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1995 intel_ddi_post_disable(intel_encoder);
1997 val = I915_READ(_FDI_RXA_CTL);
1998 val &= ~FDI_RX_ENABLE;
1999 I915_WRITE(_FDI_RXA_CTL, val);
2001 val = I915_READ(_FDI_RXA_MISC);
2002 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2003 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2004 I915_WRITE(_FDI_RXA_MISC, val);
2006 val = I915_READ(_FDI_RXA_CTL);
2008 I915_WRITE(_FDI_RXA_CTL, val);
2010 val = I915_READ(_FDI_RXA_CTL);
2011 val &= ~FDI_RX_PLL_ENABLE;
2012 I915_WRITE(_FDI_RXA_CTL, val);
2015 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
2017 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
2018 int type = intel_dig_port->base.type;
2020 if (type != INTEL_OUTPUT_DISPLAYPORT &&
2021 type != INTEL_OUTPUT_EDP &&
2022 type != INTEL_OUTPUT_UNKNOWN) {
2026 intel_dp_hot_plug(intel_encoder);
2029 void intel_ddi_get_config(struct intel_encoder *encoder,
2030 struct intel_crtc_config *pipe_config)
2032 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2033 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2034 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
2035 struct intel_hdmi *intel_hdmi;
2036 u32 temp, flags = 0;
2038 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2039 if (temp & TRANS_DDI_PHSYNC)
2040 flags |= DRM_MODE_FLAG_PHSYNC;
2042 flags |= DRM_MODE_FLAG_NHSYNC;
2043 if (temp & TRANS_DDI_PVSYNC)
2044 flags |= DRM_MODE_FLAG_PVSYNC;
2046 flags |= DRM_MODE_FLAG_NVSYNC;
2048 pipe_config->adjusted_mode.flags |= flags;
2050 switch (temp & TRANS_DDI_BPC_MASK) {
2051 case TRANS_DDI_BPC_6:
2052 pipe_config->pipe_bpp = 18;
2054 case TRANS_DDI_BPC_8:
2055 pipe_config->pipe_bpp = 24;
2057 case TRANS_DDI_BPC_10:
2058 pipe_config->pipe_bpp = 30;
2060 case TRANS_DDI_BPC_12:
2061 pipe_config->pipe_bpp = 36;
2067 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2068 case TRANS_DDI_MODE_SELECT_HDMI:
2069 pipe_config->has_hdmi_sink = true;
2070 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2072 if (intel_hdmi->infoframe_enabled(&encoder->base))
2073 pipe_config->has_infoframe = true;
2075 case TRANS_DDI_MODE_SELECT_DVI:
2076 case TRANS_DDI_MODE_SELECT_FDI:
2078 case TRANS_DDI_MODE_SELECT_DP_SST:
2079 case TRANS_DDI_MODE_SELECT_DP_MST:
2080 pipe_config->has_dp_encoder = true;
2081 intel_dp_get_m_n(intel_crtc, pipe_config);
2087 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2088 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2089 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2090 pipe_config->has_audio = true;
2093 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2094 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2096 * This is a big fat ugly hack.
2098 * Some machines in UEFI boot mode provide us a VBT that has 18
2099 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2100 * unknown we fail to light up. Yet the same BIOS boots up with
2101 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2102 * max, not what it tells us to use.
2104 * Note: This will still be broken if the eDP panel is not lit
2105 * up by the BIOS, and thus we can't get the mode at module
2108 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2109 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2110 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2113 intel_ddi_clock_get(encoder, pipe_config);
2116 static void intel_ddi_destroy(struct drm_encoder *encoder)
2118 /* HDMI has nothing special to destroy, so we can go with this. */
2119 intel_dp_encoder_destroy(encoder);
2122 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2123 struct intel_crtc_config *pipe_config)
2125 int type = encoder->type;
2126 int port = intel_ddi_get_encoder_port(encoder);
2128 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2131 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2133 if (type == INTEL_OUTPUT_HDMI)
2134 return intel_hdmi_compute_config(encoder, pipe_config);
2136 return intel_dp_compute_config(encoder, pipe_config);
2139 static const struct drm_encoder_funcs intel_ddi_funcs = {
2140 .destroy = intel_ddi_destroy,
2143 static struct intel_connector *
2144 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2146 struct intel_connector *connector;
2147 enum port port = intel_dig_port->port;
2149 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
2153 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2154 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2162 static struct intel_connector *
2163 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2165 struct intel_connector *connector;
2166 enum port port = intel_dig_port->port;
2168 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
2172 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2173 intel_hdmi_init_connector(intel_dig_port, connector);
2178 void intel_ddi_init(struct drm_device *dev, enum port port)
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181 struct intel_digital_port *intel_dig_port;
2182 struct intel_encoder *intel_encoder;
2183 struct drm_encoder *encoder;
2184 bool init_hdmi, init_dp;
2186 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2187 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2188 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2189 if (!init_dp && !init_hdmi) {
2190 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
2196 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2197 if (!intel_dig_port)
2200 intel_encoder = &intel_dig_port->base;
2201 encoder = &intel_encoder->base;
2203 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2204 DRM_MODE_ENCODER_TMDS);
2206 intel_encoder->compute_config = intel_ddi_compute_config;
2207 intel_encoder->enable = intel_enable_ddi;
2208 intel_encoder->pre_enable = intel_ddi_pre_enable;
2209 intel_encoder->disable = intel_disable_ddi;
2210 intel_encoder->post_disable = intel_ddi_post_disable;
2211 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2212 intel_encoder->get_config = intel_ddi_get_config;
2214 intel_dig_port->port = port;
2215 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2216 (DDI_BUF_PORT_REVERSAL |
2219 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2220 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2221 intel_encoder->cloneable = 0;
2222 intel_encoder->hot_plug = intel_ddi_hot_plug;
2225 if (!intel_ddi_init_dp_connector(intel_dig_port))
2228 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2229 dev_priv->hpd_irq_port[port] = intel_dig_port;
2232 /* In theory we don't need the encoder->type check, but leave it just in
2233 * case we have some really bad VBTs... */
2234 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2235 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2242 drm_encoder_cleanup(encoder);
2243 kfree(intel_dig_port);