2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
72 static const uint32_t intel_cursor_formats[] = {
76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_config *pipe_config);
80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config);
83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
85 static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
92 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
97 static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_config *pipe_config);
99 static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_config *pipe_config);
102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
104 if (!connector->mst_port)
105 return connector->encoder;
107 return &connector->mst_port->mst_encoders[pipe]->base;
116 int p2_slow, p2_fast;
119 typedef struct intel_limit intel_limit_t;
121 intel_range_t dot, vco, n, m, m1, m2, p, p1;
126 intel_pch_rawclk(struct drm_device *dev)
128 struct drm_i915_private *dev_priv = dev->dev_private;
130 WARN_ON(!HAS_PCH_SPLIT(dev));
132 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
135 static inline u32 /* units of 100MHz */
136 intel_fdi_link_freq(struct drm_device *dev)
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145 static const intel_limit_t intel_limits_i8xx_dac = {
146 .dot = { .min = 25000, .max = 350000 },
147 .vco = { .min = 908000, .max = 1512000 },
148 .n = { .min = 2, .max = 16 },
149 .m = { .min = 96, .max = 140 },
150 .m1 = { .min = 18, .max = 26 },
151 .m2 = { .min = 6, .max = 16 },
152 .p = { .min = 4, .max = 128 },
153 .p1 = { .min = 2, .max = 33 },
154 .p2 = { .dot_limit = 165000,
155 .p2_slow = 4, .p2_fast = 2 },
158 static const intel_limit_t intel_limits_i8xx_dvo = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 4 },
171 static const intel_limit_t intel_limits_i8xx_lvds = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 1, .max = 6 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 14, .p2_fast = 7 },
184 static const intel_limit_t intel_limits_i9xx_sdvo = {
185 .dot = { .min = 20000, .max = 400000 },
186 .vco = { .min = 1400000, .max = 2800000 },
187 .n = { .min = 1, .max = 6 },
188 .m = { .min = 70, .max = 120 },
189 .m1 = { .min = 8, .max = 18 },
190 .m2 = { .min = 3, .max = 7 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8 },
193 .p2 = { .dot_limit = 200000,
194 .p2_slow = 10, .p2_fast = 5 },
197 static const intel_limit_t intel_limits_i9xx_lvds = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 7, .max = 98 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 112000,
207 .p2_slow = 14, .p2_fast = 7 },
211 static const intel_limit_t intel_limits_g4x_sdvo = {
212 .dot = { .min = 25000, .max = 270000 },
213 .vco = { .min = 1750000, .max = 3500000},
214 .n = { .min = 1, .max = 4 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 10, .max = 30 },
219 .p1 = { .min = 1, .max = 3},
220 .p2 = { .dot_limit = 270000,
226 static const intel_limit_t intel_limits_g4x_hdmi = {
227 .dot = { .min = 22000, .max = 400000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 16, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 5, .max = 80 },
234 .p1 = { .min = 1, .max = 8},
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 10, .p2_fast = 5 },
239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
240 .dot = { .min = 20000, .max = 115000 },
241 .vco = { .min = 1750000, .max = 3500000 },
242 .n = { .min = 1, .max = 3 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 17, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
248 .p2 = { .dot_limit = 0,
249 .p2_slow = 14, .p2_fast = 14
253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
254 .dot = { .min = 80000, .max = 224000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 14, .max = 42 },
261 .p1 = { .min = 2, .max = 6 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 7, .p2_fast = 7
267 static const intel_limit_t intel_limits_pineview_sdvo = {
268 .dot = { .min = 20000, .max = 400000},
269 .vco = { .min = 1700000, .max = 3500000 },
270 /* Pineview's Ncounter is a ring counter */
271 .n = { .min = 3, .max = 6 },
272 .m = { .min = 2, .max = 256 },
273 /* Pineview only has one combined m divider, which we treat as m2. */
274 .m1 = { .min = 0, .max = 0 },
275 .m2 = { .min = 0, .max = 254 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8 },
278 .p2 = { .dot_limit = 200000,
279 .p2_slow = 10, .p2_fast = 5 },
282 static const intel_limit_t intel_limits_pineview_lvds = {
283 .dot = { .min = 20000, .max = 400000 },
284 .vco = { .min = 1700000, .max = 3500000 },
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 7, .max = 112 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 112000,
292 .p2_slow = 14, .p2_fast = 14 },
295 /* Ironlake / Sandybridge
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
300 static const intel_limit_t intel_limits_ironlake_dac = {
301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 5 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 5, .max = 80 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 10, .p2_fast = 5 },
313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 3 },
317 .m = { .min = 79, .max = 118 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 28, .max = 112 },
321 .p1 = { .min = 2, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 14, .p2_fast = 14 },
326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 127 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 14, .max = 56 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 7, .p2_fast = 7 },
339 /* LVDS 100mhz refclk limits. */
340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 2 },
344 .m = { .min = 79, .max = 126 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 28, .max = 112 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 14, .p2_fast = 14 },
353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 14, .max = 42 },
361 .p1 = { .min = 2, .max = 6 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 7, .p2_fast = 7 },
366 static const intel_limit_t intel_limits_vlv = {
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
373 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
374 .vco = { .min = 4000000, .max = 6000000 },
375 .n = { .min = 1, .max = 7 },
376 .m1 = { .min = 2, .max = 3 },
377 .m2 = { .min = 11, .max = 156 },
378 .p1 = { .min = 2, .max = 3 },
379 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
382 static const intel_limit_t intel_limits_chv = {
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
389 .dot = { .min = 25000 * 5, .max = 540000 * 5},
390 .vco = { .min = 4860000, .max = 6700000 },
391 .n = { .min = 1, .max = 1 },
392 .m1 = { .min = 2, .max = 2 },
393 .m2 = { .min = 24 << 22, .max = 175 << 22 },
394 .p1 = { .min = 2, .max = 4 },
395 .p2 = { .p2_slow = 1, .p2_fast = 14 },
398 static void vlv_clock(int refclk, intel_clock_t *clock)
400 clock->m = clock->m1 * clock->m2;
401 clock->p = clock->p1 * clock->p2;
402 if (WARN_ON(clock->n == 0 || clock->p == 0))
404 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
405 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 * Returns whether any output on the specified pipe is of the specified type
411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
413 struct drm_device *dev = crtc->base.dev;
414 struct intel_encoder *encoder;
416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
417 if (encoder->type == type)
424 * Returns whether any output on the specified pipe will have the specified
425 * type after a staged modeset is complete, i.e., the same as
426 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
431 struct drm_device *dev = crtc->base.dev;
432 struct intel_encoder *encoder;
434 for_each_intel_encoder(dev, encoder)
435 if (encoder->new_crtc == crtc && encoder->type == type)
441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
444 struct drm_device *dev = crtc->base.dev;
445 const intel_limit_t *limit;
447 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
448 if (intel_is_dual_link_lvds(dev)) {
449 if (refclk == 100000)
450 limit = &intel_limits_ironlake_dual_lvds_100m;
452 limit = &intel_limits_ironlake_dual_lvds;
454 if (refclk == 100000)
455 limit = &intel_limits_ironlake_single_lvds_100m;
457 limit = &intel_limits_ironlake_single_lvds;
460 limit = &intel_limits_ironlake_dac;
465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
467 struct drm_device *dev = crtc->base.dev;
468 const intel_limit_t *limit;
470 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
471 if (intel_is_dual_link_lvds(dev))
472 limit = &intel_limits_g4x_dual_channel_lvds;
474 limit = &intel_limits_g4x_single_channel_lvds;
475 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
476 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
477 limit = &intel_limits_g4x_hdmi;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
479 limit = &intel_limits_g4x_sdvo;
480 } else /* The option is for other outputs */
481 limit = &intel_limits_i9xx_sdvo;
486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
488 struct drm_device *dev = crtc->base.dev;
489 const intel_limit_t *limit;
491 if (HAS_PCH_SPLIT(dev))
492 limit = intel_ironlake_limit(crtc, refclk);
493 else if (IS_G4X(dev)) {
494 limit = intel_g4x_limit(crtc);
495 } else if (IS_PINEVIEW(dev)) {
496 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
497 limit = &intel_limits_pineview_lvds;
499 limit = &intel_limits_pineview_sdvo;
500 } else if (IS_CHERRYVIEW(dev)) {
501 limit = &intel_limits_chv;
502 } else if (IS_VALLEYVIEW(dev)) {
503 limit = &intel_limits_vlv;
504 } else if (!IS_GEN2(dev)) {
505 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
506 limit = &intel_limits_i9xx_lvds;
508 limit = &intel_limits_i9xx_sdvo;
510 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
511 limit = &intel_limits_i8xx_lvds;
512 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
513 limit = &intel_limits_i8xx_dvo;
515 limit = &intel_limits_i8xx_dac;
520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
521 static void pineview_clock(int refclk, intel_clock_t *clock)
523 clock->m = clock->m2 + 2;
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n == 0 || clock->p == 0))
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
533 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
536 static void i9xx_clock(int refclk, intel_clock_t *clock)
538 clock->m = i9xx_dpll_compute_m(clock);
539 clock->p = clock->p1 * clock->p2;
540 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
542 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
543 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
546 static void chv_clock(int refclk, intel_clock_t *clock)
548 clock->m = clock->m1 * clock->m2;
549 clock->p = clock->p1 * clock->p2;
550 if (WARN_ON(clock->n == 0 || clock->p == 0))
552 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
554 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
557 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
559 * Returns whether the given set of divisors are valid for a given refclk with
560 * the given connectors.
563 static bool intel_PLL_is_valid(struct drm_device *dev,
564 const intel_limit_t *limit,
565 const intel_clock_t *clock)
567 if (clock->n < limit->n.min || limit->n.max < clock->n)
568 INTELPllInvalid("n out of range\n");
569 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
570 INTELPllInvalid("p1 out of range\n");
571 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
572 INTELPllInvalid("m2 out of range\n");
573 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
574 INTELPllInvalid("m1 out of range\n");
576 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
577 if (clock->m1 <= clock->m2)
578 INTELPllInvalid("m1 <= m2\n");
580 if (!IS_VALLEYVIEW(dev)) {
581 if (clock->p < limit->p.min || limit->p.max < clock->p)
582 INTELPllInvalid("p out of range\n");
583 if (clock->m < limit->m.min || limit->m.max < clock->m)
584 INTELPllInvalid("m out of range\n");
587 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
588 INTELPllInvalid("vco out of range\n");
589 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590 * connector, etc., rather than just a single range.
592 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
593 INTELPllInvalid("dot out of range\n");
599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
600 int target, int refclk, intel_clock_t *match_clock,
601 intel_clock_t *best_clock)
603 struct drm_device *dev = crtc->base.dev;
607 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
609 * For LVDS just rely on its current settings for dual-channel.
610 * We haven't figured out how to reliably set up different
611 * single/dual channel state, if we even can.
613 if (intel_is_dual_link_lvds(dev))
614 clock.p2 = limit->p2.p2_fast;
616 clock.p2 = limit->p2.p2_slow;
618 if (target < limit->p2.dot_limit)
619 clock.p2 = limit->p2.p2_slow;
621 clock.p2 = limit->p2.p2_fast;
624 memset(best_clock, 0, sizeof(*best_clock));
626 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
628 for (clock.m2 = limit->m2.min;
629 clock.m2 <= limit->m2.max; clock.m2++) {
630 if (clock.m2 >= clock.m1)
632 for (clock.n = limit->n.min;
633 clock.n <= limit->n.max; clock.n++) {
634 for (clock.p1 = limit->p1.min;
635 clock.p1 <= limit->p1.max; clock.p1++) {
638 i9xx_clock(refclk, &clock);
639 if (!intel_PLL_is_valid(dev, limit,
643 clock.p != match_clock->p)
646 this_err = abs(clock.dot - target);
647 if (this_err < err) {
656 return (err != target);
660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
661 int target, int refclk, intel_clock_t *match_clock,
662 intel_clock_t *best_clock)
664 struct drm_device *dev = crtc->base.dev;
668 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
674 if (intel_is_dual_link_lvds(dev))
675 clock.p2 = limit->p2.p2_fast;
677 clock.p2 = limit->p2.p2_slow;
679 if (target < limit->p2.dot_limit)
680 clock.p2 = limit->p2.p2_slow;
682 clock.p2 = limit->p2.p2_fast;
685 memset(best_clock, 0, sizeof(*best_clock));
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
697 pineview_clock(refclk, &clock);
698 if (!intel_PLL_is_valid(dev, limit,
702 clock.p != match_clock->p)
705 this_err = abs(clock.dot - target);
706 if (this_err < err) {
715 return (err != target);
719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
723 struct drm_device *dev = crtc->base.dev;
727 /* approximately equals target * 0.00585 */
728 int err_most = (target >> 8) + (target >> 9);
731 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
732 if (intel_is_dual_link_lvds(dev))
733 clock.p2 = limit->p2.p2_fast;
735 clock.p2 = limit->p2.p2_slow;
737 if (target < limit->p2.dot_limit)
738 clock.p2 = limit->p2.p2_slow;
740 clock.p2 = limit->p2.p2_fast;
743 memset(best_clock, 0, sizeof(*best_clock));
744 max_n = limit->n.max;
745 /* based on hardware requirement, prefer smaller n to precision */
746 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
747 /* based on hardware requirement, prefere larger m1,m2 */
748 for (clock.m1 = limit->m1.max;
749 clock.m1 >= limit->m1.min; clock.m1--) {
750 for (clock.m2 = limit->m2.max;
751 clock.m2 >= limit->m2.min; clock.m2--) {
752 for (clock.p1 = limit->p1.max;
753 clock.p1 >= limit->p1.min; clock.p1--) {
756 i9xx_clock(refclk, &clock);
757 if (!intel_PLL_is_valid(dev, limit,
761 this_err = abs(clock.dot - target);
762 if (this_err < err_most) {
776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
780 struct drm_device *dev = crtc->base.dev;
782 unsigned int bestppm = 1000000;
783 /* min update 19.2 MHz */
784 int max_n = min(limit->n.max, refclk / 19200);
787 target *= 5; /* fast clock */
789 memset(best_clock, 0, sizeof(*best_clock));
791 /* based on hardware requirement, prefer smaller n to precision */
792 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
793 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
794 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
795 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
796 clock.p = clock.p1 * clock.p2;
797 /* based on hardware requirement, prefer bigger m1,m2 values */
798 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
799 unsigned int ppm, diff;
801 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
804 vlv_clock(refclk, &clock);
806 if (!intel_PLL_is_valid(dev, limit,
810 diff = abs(clock.dot - target);
811 ppm = div_u64(1000000ULL * diff, target);
813 if (ppm < 100 && clock.p > best_clock->p) {
819 if (bestppm >= 10 && ppm < bestppm - 10) {
833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
834 int target, int refclk, intel_clock_t *match_clock,
835 intel_clock_t *best_clock)
837 struct drm_device *dev = crtc->base.dev;
842 memset(best_clock, 0, sizeof(*best_clock));
845 * Based on hardware doc, the n always set to 1, and m1 always
846 * set to 2. If requires to support 200Mhz refclk, we need to
847 * revisit this because n may not 1 anymore.
849 clock.n = 1, clock.m1 = 2;
850 target *= 5; /* fast clock */
852 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
853 for (clock.p2 = limit->p2.p2_fast;
854 clock.p2 >= limit->p2.p2_slow;
855 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
857 clock.p = clock.p1 * clock.p2;
859 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
860 clock.n) << 22, refclk * clock.m1);
862 if (m2 > INT_MAX/clock.m1)
867 chv_clock(refclk, &clock);
869 if (!intel_PLL_is_valid(dev, limit, &clock))
872 /* based on hardware requirement, prefer bigger p
874 if (clock.p > best_clock->p) {
884 bool intel_crtc_active(struct drm_crtc *crtc)
886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
888 /* Be paranoid as we can arrive here with only partial
889 * state retrieved from the hardware during setup.
891 * We can ditch the adjusted_mode.crtc_clock check as soon
892 * as Haswell has gained clock readout/fastboot support.
894 * We can ditch the crtc->primary->fb check as soon as we can
895 * properly reconstruct framebuffers.
897 return intel_crtc->active && crtc->primary->fb &&
898 intel_crtc->config.adjusted_mode.crtc_clock;
901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
904 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
907 return intel_crtc->config.cpu_transcoder;
910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 u32 reg = PIPEDSL(pipe);
918 line_mask = DSL_LINEMASK_GEN2;
920 line_mask = DSL_LINEMASK_GEN3;
922 line1 = I915_READ(reg) & line_mask;
924 line2 = I915_READ(reg) & line_mask;
926 return line1 == line2;
930 * intel_wait_for_pipe_off - wait for pipe to turn off
931 * @crtc: crtc whose pipe to wait for
933 * After disabling a pipe, we can't wait for vblank in the usual way,
934 * spinning on the vblank interrupt status bit, since we won't actually
935 * see an interrupt when the pipe is disabled.
938 * wait for the pipe register state bit to turn off
941 * wait for the display line value to settle (it usually
942 * ends up stopping at the start of the next frame).
945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
947 struct drm_device *dev = crtc->base.dev;
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
950 enum pipe pipe = crtc->pipe;
952 if (INTEL_INFO(dev)->gen >= 4) {
953 int reg = PIPECONF(cpu_transcoder);
955 /* Wait for the Pipe State to go off */
956 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
958 WARN(1, "pipe_off wait timed out\n");
960 /* Wait for the display line to settle */
961 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
962 WARN(1, "pipe_off wait timed out\n");
967 * ibx_digital_port_connected - is the specified port connected?
968 * @dev_priv: i915 private structure
969 * @port: the port to test
971 * Returns true if @port is connected, false otherwise.
973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
974 struct intel_digital_port *port)
978 if (HAS_PCH_IBX(dev_priv->dev)) {
979 switch (port->port) {
981 bit = SDE_PORTB_HOTPLUG;
984 bit = SDE_PORTC_HOTPLUG;
987 bit = SDE_PORTD_HOTPLUG;
993 switch (port->port) {
995 bit = SDE_PORTB_HOTPLUG_CPT;
998 bit = SDE_PORTC_HOTPLUG_CPT;
1001 bit = SDE_PORTD_HOTPLUG_CPT;
1008 return I915_READ(SDEISR) & bit;
1011 static const char *state_string(bool enabled)
1013 return enabled ? "on" : "off";
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, bool state)
1025 val = I915_READ(reg);
1026 cur_state = !!(val & DPLL_VCO_ENABLE);
1027 WARN(cur_state != state,
1028 "PLL state assertion failure (expected %s, current %s)\n",
1029 state_string(state), state_string(cur_state));
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1038 mutex_lock(&dev_priv->dpio_lock);
1039 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040 mutex_unlock(&dev_priv->dpio_lock);
1042 cur_state = val & DSI_PLL_VCO_EN;
1043 WARN(cur_state != state,
1044 "DSI PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state), state_string(cur_state));
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1053 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1055 if (crtc->config.shared_dpll < 0)
1058 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063 struct intel_shared_dpll *pll,
1067 struct intel_dpll_hw_state hw_state;
1070 "asserting DPLL %s with no DPLL\n", state_string(state)))
1073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074 WARN(cur_state != state,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091 val = I915_READ(reg);
1092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
1115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv->dev))
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1159 struct drm_device *dev = dev_priv->dev;
1162 enum pipe panel_pipe = PIPE_A;
1165 if (WARN_ON(HAS_DDI(dev)))
1168 if (HAS_PCH_SPLIT(dev)) {
1171 pp_reg = PCH_PP_CONTROL;
1172 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1174 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176 panel_pipe = PIPE_B;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1183 pp_reg = PP_CONTROL;
1184 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185 panel_pipe = PIPE_B;
1188 val = I915_READ(pp_reg);
1189 if (!(val & PANEL_POWER_ON) ||
1190 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1193 WARN(panel_pipe == pipe && locked,
1194 "panel assertion failure, pipe %c regs locked\n",
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1201 struct drm_device *dev = dev_priv->dev;
1204 if (IS_845G(dev) || IS_I865G(dev))
1205 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1207 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1209 WARN(cur_state != state,
1210 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe), state_string(state), state_string(cur_state));
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
1222 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1225 /* if we need the pipe quirk it must be always on */
1226 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1230 if (!intel_display_power_is_enabled(dev_priv,
1231 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1265 struct drm_device *dev = dev_priv->dev;
1270 /* Primary planes are fixed to pipes on gen4+ */
1271 if (INTEL_INFO(dev)->gen >= 4) {
1272 reg = DSPCNTR(pipe);
1273 val = I915_READ(reg);
1274 WARN(val & DISPLAY_PLANE_ENABLE,
1275 "plane %c assertion failure, should be disabled but not\n",
1280 /* Need to check both planes against the pipe */
1281 for_each_pipe(dev_priv, i) {
1283 val = I915_READ(reg);
1284 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285 DISPPLANE_SEL_PIPE_SHIFT;
1286 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288 plane_name(i), pipe_name(pipe));
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1295 struct drm_device *dev = dev_priv->dev;
1299 if (INTEL_INFO(dev)->gen >= 9) {
1300 for_each_sprite(pipe, sprite) {
1301 val = I915_READ(PLANE_CTL(pipe, sprite));
1302 WARN(val & PLANE_CTL_ENABLE,
1303 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304 sprite, pipe_name(pipe));
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 for_each_sprite(pipe, sprite) {
1308 reg = SPCNTR(pipe, sprite);
1309 val = I915_READ(reg);
1310 WARN(val & SP_ENABLE,
1311 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312 sprite_name(pipe, sprite), pipe_name(pipe));
1314 } else if (INTEL_INFO(dev)->gen >= 7) {
1316 val = I915_READ(reg);
1317 WARN(val & SPRITE_ENABLE,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 plane_name(pipe), pipe_name(pipe));
1320 } else if (INTEL_INFO(dev)->gen >= 5) {
1321 reg = DVSCNTR(pipe);
1322 val = I915_READ(reg);
1323 WARN(val & DVS_ENABLE,
1324 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325 plane_name(pipe), pipe_name(pipe));
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1331 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332 drm_crtc_vblank_put(crtc);
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1340 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1342 val = I915_READ(PCH_DREF_CONTROL);
1343 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344 DREF_SUPERSPREAD_SOURCE_MASK));
1345 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355 reg = PCH_TRANSCONF(pipe);
1356 val = I915_READ(reg);
1357 enabled = !!(val & TRANS_ENABLE);
1359 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 port_sel, u32 val)
1366 if ((val & DP_PORT_EN) == 0)
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1374 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1378 if ((val & DP_PIPE_MASK) != (pipe << 30))
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, u32 val)
1387 if ((val & SDVO_ENABLE) == 0)
1390 if (HAS_PCH_CPT(dev_priv->dev)) {
1391 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1393 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1397 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe, u32 val)
1406 if ((val & LVDS_PORT_EN) == 0)
1409 if (HAS_PCH_CPT(dev_priv->dev)) {
1410 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1413 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, u32 val)
1422 if ((val & ADPA_DAC_ENABLE) == 0)
1424 if (HAS_PCH_CPT(dev_priv->dev)) {
1425 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1428 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435 enum pipe pipe, int reg, u32 port_sel)
1437 u32 val = I915_READ(reg);
1438 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440 reg, pipe_name(pipe));
1442 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443 && (val & DP_PIPEB_SELECT),
1444 "IBX PCH dp port still using transcoder B\n");
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448 enum pipe pipe, int reg)
1450 u32 val = I915_READ(reg);
1451 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453 reg, pipe_name(pipe));
1455 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456 && (val & SDVO_PIPE_B_SELECT),
1457 "IBX PCH hdmi port still using transcoder B\n");
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1466 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1471 val = I915_READ(reg);
1472 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473 "PCH VGA enabled on transcoder %c, should be disabled\n",
1477 val = I915_READ(reg);
1478 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1482 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1487 static void intel_init_dpio(struct drm_device *dev)
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1491 if (!IS_VALLEYVIEW(dev))
1495 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496 * CHV x1 PHY (DP/HDMI D)
1497 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1499 if (IS_CHERRYVIEW(dev)) {
1500 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_config *pipe_config)
1510 struct drm_device *dev = crtc->base.dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 int reg = DPLL(crtc->pipe);
1513 u32 dpll = pipe_config->dpll_hw_state.dpll;
1515 assert_pipe_disabled(dev_priv, crtc->pipe);
1517 /* No really, not for ILK+ */
1518 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1520 /* PLL is protected by panel, make sure we can write it */
1521 if (IS_MOBILE(dev_priv->dev))
1522 assert_panel_unlocked(dev_priv, crtc->pipe);
1524 I915_WRITE(reg, dpll);
1528 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1531 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532 POSTING_READ(DPLL_MD(crtc->pipe));
1534 /* We do this three times for luck */
1535 I915_WRITE(reg, dpll);
1537 udelay(150); /* wait for warmup */
1538 I915_WRITE(reg, dpll);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1543 udelay(150); /* wait for warmup */
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547 const struct intel_crtc_config *pipe_config)
1549 struct drm_device *dev = crtc->base.dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 int pipe = crtc->pipe;
1552 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1555 assert_pipe_disabled(dev_priv, crtc->pipe);
1557 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1559 mutex_lock(&dev_priv->dpio_lock);
1561 /* Enable back the 10bit clock to display controller */
1562 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563 tmp |= DPIO_DCLKP_EN;
1564 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1567 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1572 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1574 /* Check PLL is locked */
1575 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576 DRM_ERROR("PLL %d failed to lock\n", pipe);
1578 /* not sure when this should be written */
1579 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580 POSTING_READ(DPLL_MD(pipe));
1582 mutex_unlock(&dev_priv->dpio_lock);
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1587 struct intel_crtc *crtc;
1590 for_each_intel_crtc(dev, crtc)
1591 count += crtc->active &&
1592 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1599 struct drm_device *dev = crtc->base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 int reg = DPLL(crtc->pipe);
1602 u32 dpll = crtc->config.dpll_hw_state.dpll;
1604 assert_pipe_disabled(dev_priv, crtc->pipe);
1606 /* No really, not for ILK+ */
1607 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1609 /* PLL is protected by panel, make sure we can write it */
1610 if (IS_MOBILE(dev) && !IS_I830(dev))
1611 assert_panel_unlocked(dev_priv, crtc->pipe);
1613 /* Enable DVO 2x clock on both PLLs if necessary */
1614 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1616 * It appears to be important that we don't enable this
1617 * for the current pipe before otherwise configuring the
1618 * PLL. No idea how this should be handled if multiple
1619 * DVO outputs are enabled simultaneosly.
1621 dpll |= DPLL_DVO_2X_MODE;
1622 I915_WRITE(DPLL(!crtc->pipe),
1623 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1626 /* Wait for the clocks to stabilize. */
1630 if (INTEL_INFO(dev)->gen >= 4) {
1631 I915_WRITE(DPLL_MD(crtc->pipe),
1632 crtc->config.dpll_hw_state.dpll_md);
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1637 * So write it again.
1639 I915_WRITE(reg, dpll);
1642 /* We do this three times for luck */
1643 I915_WRITE(reg, dpll);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1651 udelay(150); /* wait for warmup */
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1661 * Note! This is for pre-ILK only.
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1665 struct drm_device *dev = crtc->base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 enum pipe pipe = crtc->pipe;
1669 /* Disable DVO 2x clock on both PLLs if necessary */
1671 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672 intel_num_dvo_pipes(dev) == 1) {
1673 I915_WRITE(DPLL(PIPE_B),
1674 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675 I915_WRITE(DPLL(PIPE_A),
1676 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1687 I915_WRITE(DPLL(pipe), 0);
1688 POSTING_READ(DPLL(pipe));
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv, pipe);
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1703 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704 I915_WRITE(DPLL(pipe), val);
1705 POSTING_READ(DPLL(pipe));
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1711 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
1717 /* Set PLL en = 0 */
1718 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1720 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721 I915_WRITE(DPLL(pipe), val);
1722 POSTING_READ(DPLL(pipe));
1724 mutex_lock(&dev_priv->dpio_lock);
1726 /* Disable 10bit clock to display controller */
1727 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728 val &= ~DPIO_DCLKP_EN;
1729 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1731 /* disable left/right clock distribution */
1732 if (pipe != PIPE_B) {
1733 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1737 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1742 mutex_unlock(&dev_priv->dpio_lock);
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746 struct intel_digital_port *dport)
1751 switch (dport->port) {
1753 port_mask = DPLL_PORTB_READY_MASK;
1757 port_mask = DPLL_PORTC_READY_MASK;
1761 port_mask = DPLL_PORTD_READY_MASK;
1762 dpll_reg = DPIO_PHY_STATUS;
1768 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770 port_name(dport->port), I915_READ(dpll_reg));
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1779 if (WARN_ON(pll == NULL))
1782 WARN_ON(!pll->config.crtc_mask);
1783 if (pll->active == 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1786 assert_shared_dpll_disabled(dev_priv, pll);
1788 pll->mode_set(dev_priv, pll);
1793 * intel_enable_shared_dpll - enable PCH PLL
1794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1806 if (WARN_ON(pll == NULL))
1809 if (WARN_ON(pll->config.crtc_mask == 0))
1812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813 pll->name, pll->active, pll->on,
1814 crtc->base.base.id);
1816 if (pll->active++) {
1818 assert_shared_dpll_enabled(dev_priv, pll);
1823 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1825 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826 pll->enable(dev_priv, pll);
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
1834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1836 /* PCH only available on ILK+ */
1837 BUG_ON(INTEL_INFO(dev)->gen < 5);
1838 if (WARN_ON(pll == NULL))
1841 if (WARN_ON(pll->config.crtc_mask == 0))
1844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll->name, pll->active, pll->on,
1846 crtc->base.base.id);
1848 if (WARN_ON(pll->active == 0)) {
1849 assert_shared_dpll_disabled(dev_priv, pll);
1853 assert_shared_dpll_enabled(dev_priv, pll);
1858 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859 pll->disable(dev_priv, pll);
1862 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1868 struct drm_device *dev = dev_priv->dev;
1869 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871 uint32_t reg, val, pipeconf_val;
1873 /* PCH only available on ILK+ */
1874 BUG_ON(!HAS_PCH_SPLIT(dev));
1876 /* Make sure PCH DPLL is enabled */
1877 assert_shared_dpll_enabled(dev_priv,
1878 intel_crtc_to_shared_dpll(intel_crtc));
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv, pipe);
1882 assert_fdi_rx_enabled(dev_priv, pipe);
1884 if (HAS_PCH_CPT(dev)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg = TRANS_CHICKEN2(pipe);
1888 val = I915_READ(reg);
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(reg, val);
1893 reg = PCH_TRANSCONF(pipe);
1894 val = I915_READ(reg);
1895 pipeconf_val = I915_READ(PIPECONF(pipe));
1897 if (HAS_PCH_IBX(dev_priv->dev)) {
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1902 val &= ~PIPECONF_BPC_MASK;
1903 val |= pipeconf_val & PIPECONF_BPC_MASK;
1906 val &= ~TRANS_INTERLACE_MASK;
1907 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908 if (HAS_PCH_IBX(dev_priv->dev) &&
1909 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910 val |= TRANS_LEGACY_INTERLACED_ILK;
1912 val |= TRANS_INTERLACED;
1914 val |= TRANS_PROGRESSIVE;
1916 I915_WRITE(reg, val | TRANS_ENABLE);
1917 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922 enum transcoder cpu_transcoder)
1924 u32 val, pipeconf_val;
1926 /* PCH only available on ILK+ */
1927 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1929 /* FDI must be feeding us bits for PCH ports */
1930 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1933 /* Workaround: set timing override bit. */
1934 val = I915_READ(_TRANSA_CHICKEN2);
1935 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936 I915_WRITE(_TRANSA_CHICKEN2, val);
1939 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1941 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942 PIPECONF_INTERLACED_ILK)
1943 val |= TRANS_INTERLACED;
1945 val |= TRANS_PROGRESSIVE;
1947 I915_WRITE(LPT_TRANSCONF, val);
1948 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949 DRM_ERROR("Failed to enable PCH transcoder\n");
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1955 struct drm_device *dev = dev_priv->dev;
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv, pipe);
1960 assert_fdi_rx_disabled(dev_priv, pipe);
1962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv, pipe);
1965 reg = PCH_TRANSCONF(pipe);
1966 val = I915_READ(reg);
1967 val &= ~TRANS_ENABLE;
1968 I915_WRITE(reg, val);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1973 if (!HAS_PCH_IBX(dev)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg = TRANS_CHICKEN2(pipe);
1976 val = I915_READ(reg);
1977 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978 I915_WRITE(reg, val);
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 val = I915_READ(LPT_TRANSCONF);
1987 val &= ~TRANS_ENABLE;
1988 I915_WRITE(LPT_TRANSCONF, val);
1989 /* wait for PCH transcoder off, transcoder state */
1990 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991 DRM_ERROR("Failed to disable PCH transcoder\n");
1993 /* Workaround: clear timing override bit. */
1994 val = I915_READ(_TRANSA_CHICKEN2);
1995 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996 I915_WRITE(_TRANSA_CHICKEN2, val);
2000 * intel_enable_pipe - enable a pipe, asserting requirements
2001 * @crtc: crtc responsible for the pipe
2003 * Enable @crtc's pipe, making sure that various hardware specific requirements
2004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2008 struct drm_device *dev = crtc->base.dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 enum pipe pipe = crtc->pipe;
2011 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2013 enum pipe pch_transcoder;
2017 assert_planes_disabled(dev_priv, pipe);
2018 assert_cursor_disabled(dev_priv, pipe);
2019 assert_sprites_disabled(dev_priv, pipe);
2021 if (HAS_PCH_LPT(dev_priv->dev))
2022 pch_transcoder = TRANSCODER_A;
2024 pch_transcoder = pipe;
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2031 if (!HAS_PCH_SPLIT(dev_priv->dev))
2032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033 assert_dsi_pll_enabled(dev_priv);
2035 assert_pll_enabled(dev_priv, pipe);
2037 if (crtc->config.has_pch_encoder) {
2038 /* if driving the PCH, we need FDI enabled */
2039 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040 assert_fdi_tx_pll_enabled(dev_priv,
2041 (enum pipe) cpu_transcoder);
2043 /* FIXME: assert CPU port conditions for SNB+ */
2046 reg = PIPECONF(cpu_transcoder);
2047 val = I915_READ(reg);
2048 if (val & PIPECONF_ENABLE) {
2049 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054 I915_WRITE(reg, val | PIPECONF_ENABLE);
2059 * intel_disable_pipe - disable a pipe, asserting requirements
2060 * @crtc: crtc whose pipes is to be disabled
2062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
2066 * Will wait until the pipe has shut down before returning.
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2070 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072 enum pipe pipe = crtc->pipe;
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2080 assert_planes_disabled(dev_priv, pipe);
2081 assert_cursor_disabled(dev_priv, pipe);
2082 assert_sprites_disabled(dev_priv, pipe);
2084 reg = PIPECONF(cpu_transcoder);
2085 val = I915_READ(reg);
2086 if ((val & PIPECONF_ENABLE) == 0)
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2093 if (crtc->config.double_wide)
2094 val &= ~PIPECONF_DOUBLE_WIDE;
2096 /* Don't disable pipe or pipe PLLs if needed */
2097 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099 val &= ~PIPECONF_ENABLE;
2101 I915_WRITE(reg, val);
2102 if ((val & PIPECONF_ENABLE) == 0)
2103 intel_wait_for_pipe_off(crtc);
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2113 struct drm_device *dev = dev_priv->dev;
2114 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2116 I915_WRITE(reg, I915_READ(reg));
2121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
2125 * Enable @plane on @crtc, making sure that the pipe is running first.
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128 struct drm_crtc *crtc)
2130 struct drm_device *dev = plane->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2137 if (intel_crtc->primary_enabled)
2140 intel_crtc->primary_enabled = true;
2142 dev_priv->display.update_primary_plane(crtc, plane->fb,
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2150 if (IS_BROADWELL(dev))
2151 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 * intel_disable_primary_hw_plane - disable the primary hardware plane
2156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
2159 * Disable @plane on @crtc, making sure that the pipe is running first.
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162 struct drm_crtc *crtc)
2164 struct drm_device *dev = plane->dev;
2165 struct drm_i915_private *dev_priv = dev->dev_private;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2168 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2170 if (!intel_crtc->primary_enabled)
2173 intel_crtc->primary_enabled = false;
2175 dev_priv->display.update_primary_plane(crtc, plane->fb,
2179 static bool need_vtd_wa(struct drm_device *dev)
2181 #ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2192 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193 return ALIGN(height, tile_height);
2197 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198 struct drm_framebuffer *fb,
2199 struct intel_engine_cs *pipelined)
2201 struct drm_device *dev = fb->dev;
2202 struct drm_i915_private *dev_priv = dev->dev_private;
2203 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2207 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2209 switch (obj->tiling_mode) {
2210 case I915_TILING_NONE:
2211 if (INTEL_INFO(dev)->gen >= 9)
2212 alignment = 256 * 1024;
2213 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2214 alignment = 128 * 1024;
2215 else if (INTEL_INFO(dev)->gen >= 4)
2216 alignment = 4 * 1024;
2218 alignment = 64 * 1024;
2221 if (INTEL_INFO(dev)->gen >= 9)
2222 alignment = 256 * 1024;
2224 /* pin() will align the object as required by fence */
2229 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2235 /* Note that the w/a also requires 64 PTE of padding following the
2236 * bo. We currently fill all unused PTE with the shadow page and so
2237 * we should always have valid PTE following the scanout preventing
2240 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241 alignment = 256 * 1024;
2244 * Global gtt pte registers are special registers which actually forward
2245 * writes to a chunk of system memory. Which means that there is no risk
2246 * that the register values disappear as soon as we call
2247 * intel_runtime_pm_put(), so it is correct to wrap only the
2248 * pin/unpin/fence and not more.
2250 intel_runtime_pm_get(dev_priv);
2252 dev_priv->mm.interruptible = false;
2253 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2255 goto err_interruptible;
2257 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258 * fence, whereas 965+ only requires a fence if using
2259 * framebuffer compression. For simplicity, we always install
2260 * a fence as the cost is not that onerous.
2262 ret = i915_gem_object_get_fence(obj);
2266 i915_gem_object_pin_fence(obj);
2268 dev_priv->mm.interruptible = true;
2269 intel_runtime_pm_put(dev_priv);
2273 i915_gem_object_unpin_from_display_plane(obj);
2275 dev_priv->mm.interruptible = true;
2276 intel_runtime_pm_put(dev_priv);
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2282 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2284 i915_gem_object_unpin_fence(obj);
2285 i915_gem_object_unpin_from_display_plane(obj);
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289 * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291 unsigned int tiling_mode,
2295 if (tiling_mode != I915_TILING_NONE) {
2296 unsigned int tile_rows, tiles;
2301 tiles = *x / (512/cpp);
2304 return tile_rows * pitch * 8 + tiles * 4096;
2306 unsigned int offset;
2308 offset = *y * pitch + *x * cpp;
2310 *x = (offset & 4095) / cpp;
2311 return offset & -4096;
2315 int intel_format_to_fourcc(int format)
2318 case DISPPLANE_8BPP:
2319 return DRM_FORMAT_C8;
2320 case DISPPLANE_BGRX555:
2321 return DRM_FORMAT_XRGB1555;
2322 case DISPPLANE_BGRX565:
2323 return DRM_FORMAT_RGB565;
2325 case DISPPLANE_BGRX888:
2326 return DRM_FORMAT_XRGB8888;
2327 case DISPPLANE_RGBX888:
2328 return DRM_FORMAT_XBGR8888;
2329 case DISPPLANE_BGRX101010:
2330 return DRM_FORMAT_XRGB2101010;
2331 case DISPPLANE_RGBX101010:
2332 return DRM_FORMAT_XBGR2101010;
2336 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2337 struct intel_plane_config *plane_config)
2339 struct drm_device *dev = crtc->base.dev;
2340 struct drm_i915_gem_object *obj = NULL;
2341 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342 u32 base = plane_config->base;
2344 if (plane_config->size == 0)
2347 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348 plane_config->size);
2352 if (plane_config->tiled) {
2353 obj->tiling_mode = I915_TILING_X;
2354 obj->stride = crtc->base.primary->fb->pitches[0];
2357 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358 mode_cmd.width = crtc->base.primary->fb->width;
2359 mode_cmd.height = crtc->base.primary->fb->height;
2360 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2362 mutex_lock(&dev->struct_mutex);
2364 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2366 DRM_DEBUG_KMS("intel fb init failed\n");
2370 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2371 mutex_unlock(&dev->struct_mutex);
2373 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2377 drm_gem_object_unreference(&obj->base);
2378 mutex_unlock(&dev->struct_mutex);
2382 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383 struct intel_plane_config *plane_config)
2385 struct drm_device *dev = intel_crtc->base.dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2388 struct intel_crtc *i;
2389 struct drm_i915_gem_object *obj;
2391 if (!intel_crtc->base.primary->fb)
2394 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2397 kfree(intel_crtc->base.primary->fb);
2398 intel_crtc->base.primary->fb = NULL;
2401 * Failed to alloc the obj, check to see if we should share
2402 * an fb with another CRTC instead
2404 for_each_crtc(dev, c) {
2405 i = to_intel_crtc(c);
2407 if (c == &intel_crtc->base)
2413 obj = intel_fb_obj(c->primary->fb);
2417 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2418 if (obj->tiling_mode != I915_TILING_NONE)
2419 dev_priv->preserve_bios_swizzle = true;
2421 drm_framebuffer_reference(c->primary->fb);
2422 intel_crtc->base.primary->fb = c->primary->fb;
2423 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2429 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430 struct drm_framebuffer *fb,
2433 struct drm_device *dev = crtc->dev;
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2436 struct drm_i915_gem_object *obj;
2437 int plane = intel_crtc->plane;
2438 unsigned long linear_offset;
2440 u32 reg = DSPCNTR(plane);
2443 if (!intel_crtc->primary_enabled) {
2445 if (INTEL_INFO(dev)->gen >= 4)
2446 I915_WRITE(DSPSURF(plane), 0);
2448 I915_WRITE(DSPADDR(plane), 0);
2453 obj = intel_fb_obj(fb);
2454 if (WARN_ON(obj == NULL))
2457 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2459 dspcntr = DISPPLANE_GAMMA_ENABLE;
2461 dspcntr |= DISPLAY_PLANE_ENABLE;
2463 if (INTEL_INFO(dev)->gen < 4) {
2464 if (intel_crtc->pipe == PIPE_B)
2465 dspcntr |= DISPPLANE_SEL_PIPE_B;
2467 /* pipesrc and dspsize control the size that is scaled from,
2468 * which should always be the user's requested size.
2470 I915_WRITE(DSPSIZE(plane),
2471 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472 (intel_crtc->config.pipe_src_w - 1));
2473 I915_WRITE(DSPPOS(plane), 0);
2474 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475 I915_WRITE(PRIMSIZE(plane),
2476 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477 (intel_crtc->config.pipe_src_w - 1));
2478 I915_WRITE(PRIMPOS(plane), 0);
2479 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2482 switch (fb->pixel_format) {
2484 dspcntr |= DISPPLANE_8BPP;
2486 case DRM_FORMAT_XRGB1555:
2487 case DRM_FORMAT_ARGB1555:
2488 dspcntr |= DISPPLANE_BGRX555;
2490 case DRM_FORMAT_RGB565:
2491 dspcntr |= DISPPLANE_BGRX565;
2493 case DRM_FORMAT_XRGB8888:
2494 case DRM_FORMAT_ARGB8888:
2495 dspcntr |= DISPPLANE_BGRX888;
2497 case DRM_FORMAT_XBGR8888:
2498 case DRM_FORMAT_ABGR8888:
2499 dspcntr |= DISPPLANE_RGBX888;
2501 case DRM_FORMAT_XRGB2101010:
2502 case DRM_FORMAT_ARGB2101010:
2503 dspcntr |= DISPPLANE_BGRX101010;
2505 case DRM_FORMAT_XBGR2101010:
2506 case DRM_FORMAT_ABGR2101010:
2507 dspcntr |= DISPPLANE_RGBX101010;
2513 if (INTEL_INFO(dev)->gen >= 4 &&
2514 obj->tiling_mode != I915_TILING_NONE)
2515 dspcntr |= DISPPLANE_TILED;
2518 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2520 linear_offset = y * fb->pitches[0] + x * pixel_size;
2522 if (INTEL_INFO(dev)->gen >= 4) {
2523 intel_crtc->dspaddr_offset =
2524 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2527 linear_offset -= intel_crtc->dspaddr_offset;
2529 intel_crtc->dspaddr_offset = linear_offset;
2532 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533 dspcntr |= DISPPLANE_ROTATE_180;
2535 x += (intel_crtc->config.pipe_src_w - 1);
2536 y += (intel_crtc->config.pipe_src_h - 1);
2538 /* Finding the last pixel of the last line of the display
2539 data and adding to linear_offset*/
2541 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2545 I915_WRITE(reg, dspcntr);
2547 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2550 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2551 if (INTEL_INFO(dev)->gen >= 4) {
2552 I915_WRITE(DSPSURF(plane),
2553 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2555 I915_WRITE(DSPLINOFF(plane), linear_offset);
2557 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2561 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562 struct drm_framebuffer *fb,
2565 struct drm_device *dev = crtc->dev;
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568 struct drm_i915_gem_object *obj;
2569 int plane = intel_crtc->plane;
2570 unsigned long linear_offset;
2572 u32 reg = DSPCNTR(plane);
2575 if (!intel_crtc->primary_enabled) {
2577 I915_WRITE(DSPSURF(plane), 0);
2582 obj = intel_fb_obj(fb);
2583 if (WARN_ON(obj == NULL))
2586 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2588 dspcntr = DISPPLANE_GAMMA_ENABLE;
2590 dspcntr |= DISPLAY_PLANE_ENABLE;
2592 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2595 switch (fb->pixel_format) {
2597 dspcntr |= DISPPLANE_8BPP;
2599 case DRM_FORMAT_RGB565:
2600 dspcntr |= DISPPLANE_BGRX565;
2602 case DRM_FORMAT_XRGB8888:
2603 case DRM_FORMAT_ARGB8888:
2604 dspcntr |= DISPPLANE_BGRX888;
2606 case DRM_FORMAT_XBGR8888:
2607 case DRM_FORMAT_ABGR8888:
2608 dspcntr |= DISPPLANE_RGBX888;
2610 case DRM_FORMAT_XRGB2101010:
2611 case DRM_FORMAT_ARGB2101010:
2612 dspcntr |= DISPPLANE_BGRX101010;
2614 case DRM_FORMAT_XBGR2101010:
2615 case DRM_FORMAT_ABGR2101010:
2616 dspcntr |= DISPPLANE_RGBX101010;
2622 if (obj->tiling_mode != I915_TILING_NONE)
2623 dspcntr |= DISPPLANE_TILED;
2625 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2626 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2628 linear_offset = y * fb->pitches[0] + x * pixel_size;
2629 intel_crtc->dspaddr_offset =
2630 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2633 linear_offset -= intel_crtc->dspaddr_offset;
2634 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635 dspcntr |= DISPPLANE_ROTATE_180;
2637 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638 x += (intel_crtc->config.pipe_src_w - 1);
2639 y += (intel_crtc->config.pipe_src_h - 1);
2641 /* Finding the last pixel of the last line of the display
2642 data and adding to linear_offset*/
2644 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2649 I915_WRITE(reg, dspcntr);
2651 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2654 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655 I915_WRITE(DSPSURF(plane),
2656 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2657 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2658 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2660 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661 I915_WRITE(DSPLINOFF(plane), linear_offset);
2666 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667 struct drm_framebuffer *fb,
2670 struct drm_device *dev = crtc->dev;
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673 struct intel_framebuffer *intel_fb;
2674 struct drm_i915_gem_object *obj;
2675 int pipe = intel_crtc->pipe;
2676 u32 plane_ctl, stride;
2678 if (!intel_crtc->primary_enabled) {
2679 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681 POSTING_READ(PLANE_CTL(pipe, 0));
2685 plane_ctl = PLANE_CTL_ENABLE |
2686 PLANE_CTL_PIPE_GAMMA_ENABLE |
2687 PLANE_CTL_PIPE_CSC_ENABLE;
2689 switch (fb->pixel_format) {
2690 case DRM_FORMAT_RGB565:
2691 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2693 case DRM_FORMAT_XRGB8888:
2694 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2696 case DRM_FORMAT_XBGR8888:
2697 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2700 case DRM_FORMAT_XRGB2101010:
2701 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2703 case DRM_FORMAT_XBGR2101010:
2704 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2711 intel_fb = to_intel_framebuffer(fb);
2712 obj = intel_fb->obj;
2715 * The stride is either expressed as a multiple of 64 bytes chunks for
2716 * linear buffers or in number of tiles for tiled buffers.
2718 switch (obj->tiling_mode) {
2719 case I915_TILING_NONE:
2720 stride = fb->pitches[0] >> 6;
2723 plane_ctl |= PLANE_CTL_TILED_X;
2724 stride = fb->pitches[0] >> 9;
2730 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2731 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732 plane_ctl |= PLANE_CTL_ROTATE_180;
2734 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2736 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737 i915_gem_obj_ggtt_offset(obj),
2738 x, y, fb->width, fb->height,
2741 I915_WRITE(PLANE_POS(pipe, 0), 0);
2742 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743 I915_WRITE(PLANE_SIZE(pipe, 0),
2744 (intel_crtc->config.pipe_src_h - 1) << 16 |
2745 (intel_crtc->config.pipe_src_w - 1));
2746 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2749 POSTING_READ(PLANE_SURF(pipe, 0));
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2754 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755 int x, int y, enum mode_set_atomic state)
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2760 if (dev_priv->display.disable_fbc)
2761 dev_priv->display.disable_fbc(dev);
2763 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2768 static void intel_complete_page_flips(struct drm_device *dev)
2770 struct drm_crtc *crtc;
2772 for_each_crtc(dev, crtc) {
2773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2774 enum plane plane = intel_crtc->plane;
2776 intel_prepare_page_flip(dev, plane);
2777 intel_finish_page_flip_plane(dev, plane);
2781 static void intel_update_primary_planes(struct drm_device *dev)
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 struct drm_crtc *crtc;
2786 for_each_crtc(dev, crtc) {
2787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789 drm_modeset_lock(&crtc->mutex, NULL);
2791 * FIXME: Once we have proper support for primary planes (and
2792 * disabling them without disabling the entire crtc) allow again
2793 * a NULL crtc->primary->fb.
2795 if (intel_crtc->active && crtc->primary->fb)
2796 dev_priv->display.update_primary_plane(crtc,
2800 drm_modeset_unlock(&crtc->mutex);
2804 void intel_prepare_reset(struct drm_device *dev)
2806 struct drm_i915_private *dev_priv = to_i915(dev);
2807 struct intel_crtc *crtc;
2809 /* no reset support for gen2 */
2813 /* reset doesn't touch the display */
2814 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2817 drm_modeset_lock_all(dev);
2820 * Disabling the crtcs gracefully seems nicer. Also the
2821 * g33 docs say we should at least disable all the planes.
2823 for_each_intel_crtc(dev, crtc) {
2825 dev_priv->display.crtc_disable(&crtc->base);
2829 void intel_finish_reset(struct drm_device *dev)
2831 struct drm_i915_private *dev_priv = to_i915(dev);
2834 * Flips in the rings will be nuked by the reset,
2835 * so complete all pending flips so that user space
2836 * will get its events and not get stuck.
2838 intel_complete_page_flips(dev);
2840 /* no reset support for gen2 */
2844 /* reset doesn't touch the display */
2845 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2847 * Flips in the rings have been nuked by the reset,
2848 * so update the base address of all primary
2849 * planes to the the last fb to make sure we're
2850 * showing the correct fb after a reset.
2852 intel_update_primary_planes(dev);
2857 * The display has been reset as well,
2858 * so need a full re-initialization.
2860 intel_runtime_pm_disable_interrupts(dev_priv);
2861 intel_runtime_pm_enable_interrupts(dev_priv);
2863 intel_modeset_init_hw(dev);
2865 spin_lock_irq(&dev_priv->irq_lock);
2866 if (dev_priv->display.hpd_irq_setup)
2867 dev_priv->display.hpd_irq_setup(dev);
2868 spin_unlock_irq(&dev_priv->irq_lock);
2870 intel_modeset_setup_hw_state(dev, true);
2872 intel_hpd_init(dev_priv);
2874 drm_modeset_unlock_all(dev);
2878 intel_finish_fb(struct drm_framebuffer *old_fb)
2880 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2881 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2882 bool was_interruptible = dev_priv->mm.interruptible;
2885 /* Big Hammer, we also need to ensure that any pending
2886 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2887 * current scanout is retired before unpinning the old
2890 * This should only fail upon a hung GPU, in which case we
2891 * can safely continue.
2893 dev_priv->mm.interruptible = false;
2894 ret = i915_gem_object_finish_gpu(obj);
2895 dev_priv->mm.interruptible = was_interruptible;
2900 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2902 struct drm_device *dev = crtc->dev;
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2907 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2908 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2911 spin_lock_irq(&dev->event_lock);
2912 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2913 spin_unlock_irq(&dev->event_lock);
2918 static void intel_update_pipe_size(struct intel_crtc *crtc)
2920 struct drm_device *dev = crtc->base.dev;
2921 struct drm_i915_private *dev_priv = dev->dev_private;
2922 const struct drm_display_mode *adjusted_mode;
2928 * Update pipe size and adjust fitter if needed: the reason for this is
2929 * that in compute_mode_changes we check the native mode (not the pfit
2930 * mode) to see if we can flip rather than do a full mode set. In the
2931 * fastboot case, we'll flip, but if we don't update the pipesrc and
2932 * pfit state, we'll end up with a big fb scanned out into the wrong
2935 * To fix this properly, we need to hoist the checks up into
2936 * compute_mode_changes (or above), check the actual pfit state and
2937 * whether the platform allows pfit disable with pipe active, and only
2938 * then update the pipesrc and pfit state, even on the flip path.
2941 adjusted_mode = &crtc->config.adjusted_mode;
2943 I915_WRITE(PIPESRC(crtc->pipe),
2944 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2945 (adjusted_mode->crtc_vdisplay - 1));
2946 if (!crtc->config.pch_pfit.enabled &&
2947 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2948 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2949 I915_WRITE(PF_CTL(crtc->pipe), 0);
2950 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2951 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2953 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2954 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2958 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2959 struct drm_framebuffer *fb)
2961 struct drm_device *dev = crtc->dev;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2964 enum pipe pipe = intel_crtc->pipe;
2965 struct drm_framebuffer *old_fb = crtc->primary->fb;
2966 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2969 if (intel_crtc_has_pending_flip(crtc)) {
2970 DRM_ERROR("pipe is still busy with an old pageflip\n");
2976 DRM_ERROR("No FB bound\n");
2980 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2981 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2982 plane_name(intel_crtc->plane),
2983 INTEL_INFO(dev)->num_pipes);
2987 mutex_lock(&dev->struct_mutex);
2988 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
2990 i915_gem_track_fb(old_obj, intel_fb_obj(fb),
2991 INTEL_FRONTBUFFER_PRIMARY(pipe));
2992 mutex_unlock(&dev->struct_mutex);
2994 DRM_ERROR("pin & fence failed\n");
2998 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3000 if (intel_crtc->active)
3001 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
3003 crtc->primary->fb = fb;
3008 if (intel_crtc->active && old_fb != fb)
3009 intel_wait_for_vblank(dev, intel_crtc->pipe);
3010 mutex_lock(&dev->struct_mutex);
3011 intel_unpin_fb_obj(old_obj);
3012 mutex_unlock(&dev->struct_mutex);
3015 mutex_lock(&dev->struct_mutex);
3016 intel_update_fbc(dev);
3017 mutex_unlock(&dev->struct_mutex);
3022 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3024 struct drm_device *dev = crtc->dev;
3025 struct drm_i915_private *dev_priv = dev->dev_private;
3026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3027 int pipe = intel_crtc->pipe;
3030 /* enable normal train */
3031 reg = FDI_TX_CTL(pipe);
3032 temp = I915_READ(reg);
3033 if (IS_IVYBRIDGE(dev)) {
3034 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3035 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3037 temp &= ~FDI_LINK_TRAIN_NONE;
3038 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3040 I915_WRITE(reg, temp);
3042 reg = FDI_RX_CTL(pipe);
3043 temp = I915_READ(reg);
3044 if (HAS_PCH_CPT(dev)) {
3045 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3046 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3048 temp &= ~FDI_LINK_TRAIN_NONE;
3049 temp |= FDI_LINK_TRAIN_NONE;
3051 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3053 /* wait one idle pattern time */
3057 /* IVB wants error correction enabled */
3058 if (IS_IVYBRIDGE(dev))
3059 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3060 FDI_FE_ERRC_ENABLE);
3063 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3065 return crtc->base.enabled && crtc->active &&
3066 crtc->config.has_pch_encoder;
3069 static void ivb_modeset_global_resources(struct drm_device *dev)
3071 struct drm_i915_private *dev_priv = dev->dev_private;
3072 struct intel_crtc *pipe_B_crtc =
3073 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3074 struct intel_crtc *pipe_C_crtc =
3075 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3079 * When everything is off disable fdi C so that we could enable fdi B
3080 * with all lanes. Note that we don't care about enabled pipes without
3081 * an enabled pch encoder.
3083 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3084 !pipe_has_enabled_pch(pipe_C_crtc)) {
3085 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3086 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3088 temp = I915_READ(SOUTH_CHICKEN1);
3089 temp &= ~FDI_BC_BIFURCATION_SELECT;
3090 DRM_DEBUG_KMS("disabling fdi C rx\n");
3091 I915_WRITE(SOUTH_CHICKEN1, temp);
3095 /* The FDI link training functions for ILK/Ibexpeak. */
3096 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3098 struct drm_device *dev = crtc->dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101 int pipe = intel_crtc->pipe;
3102 u32 reg, temp, tries;
3104 /* FDI needs bits from pipe first */
3105 assert_pipe_enabled(dev_priv, pipe);
3107 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3109 reg = FDI_RX_IMR(pipe);
3110 temp = I915_READ(reg);
3111 temp &= ~FDI_RX_SYMBOL_LOCK;
3112 temp &= ~FDI_RX_BIT_LOCK;
3113 I915_WRITE(reg, temp);
3117 /* enable CPU FDI TX and PCH FDI RX */
3118 reg = FDI_TX_CTL(pipe);
3119 temp = I915_READ(reg);
3120 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3121 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3122 temp &= ~FDI_LINK_TRAIN_NONE;
3123 temp |= FDI_LINK_TRAIN_PATTERN_1;
3124 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3126 reg = FDI_RX_CTL(pipe);
3127 temp = I915_READ(reg);
3128 temp &= ~FDI_LINK_TRAIN_NONE;
3129 temp |= FDI_LINK_TRAIN_PATTERN_1;
3130 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3135 /* Ironlake workaround, enable clock pointer after FDI enable*/
3136 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3137 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3138 FDI_RX_PHASE_SYNC_POINTER_EN);
3140 reg = FDI_RX_IIR(pipe);
3141 for (tries = 0; tries < 5; tries++) {
3142 temp = I915_READ(reg);
3143 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3145 if ((temp & FDI_RX_BIT_LOCK)) {
3146 DRM_DEBUG_KMS("FDI train 1 done.\n");
3147 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3152 DRM_ERROR("FDI train 1 fail!\n");
3155 reg = FDI_TX_CTL(pipe);
3156 temp = I915_READ(reg);
3157 temp &= ~FDI_LINK_TRAIN_NONE;
3158 temp |= FDI_LINK_TRAIN_PATTERN_2;
3159 I915_WRITE(reg, temp);
3161 reg = FDI_RX_CTL(pipe);
3162 temp = I915_READ(reg);
3163 temp &= ~FDI_LINK_TRAIN_NONE;
3164 temp |= FDI_LINK_TRAIN_PATTERN_2;
3165 I915_WRITE(reg, temp);
3170 reg = FDI_RX_IIR(pipe);
3171 for (tries = 0; tries < 5; tries++) {
3172 temp = I915_READ(reg);
3173 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3175 if (temp & FDI_RX_SYMBOL_LOCK) {
3176 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3177 DRM_DEBUG_KMS("FDI train 2 done.\n");
3182 DRM_ERROR("FDI train 2 fail!\n");
3184 DRM_DEBUG_KMS("FDI train done\n");
3188 static const int snb_b_fdi_train_param[] = {
3189 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3190 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3191 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3192 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3195 /* The FDI link training functions for SNB/Cougarpoint. */
3196 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3198 struct drm_device *dev = crtc->dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3201 int pipe = intel_crtc->pipe;
3202 u32 reg, temp, i, retry;
3204 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3206 reg = FDI_RX_IMR(pipe);
3207 temp = I915_READ(reg);
3208 temp &= ~FDI_RX_SYMBOL_LOCK;
3209 temp &= ~FDI_RX_BIT_LOCK;
3210 I915_WRITE(reg, temp);
3215 /* enable CPU FDI TX and PCH FDI RX */
3216 reg = FDI_TX_CTL(pipe);
3217 temp = I915_READ(reg);
3218 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3219 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3220 temp &= ~FDI_LINK_TRAIN_NONE;
3221 temp |= FDI_LINK_TRAIN_PATTERN_1;
3222 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3224 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3225 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3227 I915_WRITE(FDI_RX_MISC(pipe),
3228 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3230 reg = FDI_RX_CTL(pipe);
3231 temp = I915_READ(reg);
3232 if (HAS_PCH_CPT(dev)) {
3233 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3234 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3236 temp &= ~FDI_LINK_TRAIN_NONE;
3237 temp |= FDI_LINK_TRAIN_PATTERN_1;
3239 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3244 for (i = 0; i < 4; i++) {
3245 reg = FDI_TX_CTL(pipe);
3246 temp = I915_READ(reg);
3247 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3248 temp |= snb_b_fdi_train_param[i];
3249 I915_WRITE(reg, temp);
3254 for (retry = 0; retry < 5; retry++) {
3255 reg = FDI_RX_IIR(pipe);
3256 temp = I915_READ(reg);
3257 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3258 if (temp & FDI_RX_BIT_LOCK) {
3259 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3260 DRM_DEBUG_KMS("FDI train 1 done.\n");
3269 DRM_ERROR("FDI train 1 fail!\n");
3272 reg = FDI_TX_CTL(pipe);
3273 temp = I915_READ(reg);
3274 temp &= ~FDI_LINK_TRAIN_NONE;
3275 temp |= FDI_LINK_TRAIN_PATTERN_2;
3277 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3279 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3281 I915_WRITE(reg, temp);
3283 reg = FDI_RX_CTL(pipe);
3284 temp = I915_READ(reg);
3285 if (HAS_PCH_CPT(dev)) {
3286 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3287 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3289 temp &= ~FDI_LINK_TRAIN_NONE;
3290 temp |= FDI_LINK_TRAIN_PATTERN_2;
3292 I915_WRITE(reg, temp);
3297 for (i = 0; i < 4; i++) {
3298 reg = FDI_TX_CTL(pipe);
3299 temp = I915_READ(reg);
3300 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3301 temp |= snb_b_fdi_train_param[i];
3302 I915_WRITE(reg, temp);
3307 for (retry = 0; retry < 5; retry++) {
3308 reg = FDI_RX_IIR(pipe);
3309 temp = I915_READ(reg);
3310 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3311 if (temp & FDI_RX_SYMBOL_LOCK) {
3312 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3313 DRM_DEBUG_KMS("FDI train 2 done.\n");
3322 DRM_ERROR("FDI train 2 fail!\n");
3324 DRM_DEBUG_KMS("FDI train done.\n");
3327 /* Manual link training for Ivy Bridge A0 parts */
3328 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3330 struct drm_device *dev = crtc->dev;
3331 struct drm_i915_private *dev_priv = dev->dev_private;
3332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3333 int pipe = intel_crtc->pipe;
3334 u32 reg, temp, i, j;
3336 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3338 reg = FDI_RX_IMR(pipe);
3339 temp = I915_READ(reg);
3340 temp &= ~FDI_RX_SYMBOL_LOCK;
3341 temp &= ~FDI_RX_BIT_LOCK;
3342 I915_WRITE(reg, temp);
3347 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3348 I915_READ(FDI_RX_IIR(pipe)));
3350 /* Try each vswing and preemphasis setting twice before moving on */
3351 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3352 /* disable first in case we need to retry */
3353 reg = FDI_TX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3356 temp &= ~FDI_TX_ENABLE;
3357 I915_WRITE(reg, temp);
3359 reg = FDI_RX_CTL(pipe);
3360 temp = I915_READ(reg);
3361 temp &= ~FDI_LINK_TRAIN_AUTO;
3362 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3363 temp &= ~FDI_RX_ENABLE;
3364 I915_WRITE(reg, temp);
3366 /* enable CPU FDI TX and PCH FDI RX */
3367 reg = FDI_TX_CTL(pipe);
3368 temp = I915_READ(reg);
3369 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3370 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3371 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3372 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3373 temp |= snb_b_fdi_train_param[j/2];
3374 temp |= FDI_COMPOSITE_SYNC;
3375 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3377 I915_WRITE(FDI_RX_MISC(pipe),
3378 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3380 reg = FDI_RX_CTL(pipe);
3381 temp = I915_READ(reg);
3382 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3383 temp |= FDI_COMPOSITE_SYNC;
3384 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3387 udelay(1); /* should be 0.5us */
3389 for (i = 0; i < 4; i++) {
3390 reg = FDI_RX_IIR(pipe);
3391 temp = I915_READ(reg);
3392 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3394 if (temp & FDI_RX_BIT_LOCK ||
3395 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3396 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3397 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3401 udelay(1); /* should be 0.5us */
3404 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3409 reg = FDI_TX_CTL(pipe);
3410 temp = I915_READ(reg);
3411 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3412 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3413 I915_WRITE(reg, temp);
3415 reg = FDI_RX_CTL(pipe);
3416 temp = I915_READ(reg);
3417 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3418 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3419 I915_WRITE(reg, temp);
3422 udelay(2); /* should be 1.5us */
3424 for (i = 0; i < 4; i++) {
3425 reg = FDI_RX_IIR(pipe);
3426 temp = I915_READ(reg);
3427 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3429 if (temp & FDI_RX_SYMBOL_LOCK ||
3430 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3431 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3432 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3436 udelay(2); /* should be 1.5us */
3439 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3443 DRM_DEBUG_KMS("FDI train done.\n");
3446 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3448 struct drm_device *dev = intel_crtc->base.dev;
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450 int pipe = intel_crtc->pipe;
3454 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3455 reg = FDI_RX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3458 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3459 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3460 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3465 /* Switch from Rawclk to PCDclk */
3466 temp = I915_READ(reg);
3467 I915_WRITE(reg, temp | FDI_PCDCLK);
3472 /* Enable CPU FDI TX PLL, always on for Ironlake */
3473 reg = FDI_TX_CTL(pipe);
3474 temp = I915_READ(reg);
3475 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3476 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3483 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3485 struct drm_device *dev = intel_crtc->base.dev;
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 int pipe = intel_crtc->pipe;
3490 /* Switch from PCDclk to Rawclk */
3491 reg = FDI_RX_CTL(pipe);
3492 temp = I915_READ(reg);
3493 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3495 /* Disable CPU FDI TX PLL */
3496 reg = FDI_TX_CTL(pipe);
3497 temp = I915_READ(reg);
3498 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3503 reg = FDI_RX_CTL(pipe);
3504 temp = I915_READ(reg);
3505 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3507 /* Wait for the clocks to turn off. */
3512 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3514 struct drm_device *dev = crtc->dev;
3515 struct drm_i915_private *dev_priv = dev->dev_private;
3516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517 int pipe = intel_crtc->pipe;
3520 /* disable CPU FDI tx and PCH FDI rx */
3521 reg = FDI_TX_CTL(pipe);
3522 temp = I915_READ(reg);
3523 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 temp &= ~(0x7 << 16);
3529 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3530 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3535 /* Ironlake workaround, disable clock pointer after downing FDI */
3536 if (HAS_PCH_IBX(dev))
3537 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3539 /* still set train pattern 1 */
3540 reg = FDI_TX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 temp &= ~FDI_LINK_TRAIN_NONE;
3543 temp |= FDI_LINK_TRAIN_PATTERN_1;
3544 I915_WRITE(reg, temp);
3546 reg = FDI_RX_CTL(pipe);
3547 temp = I915_READ(reg);
3548 if (HAS_PCH_CPT(dev)) {
3549 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3550 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3552 temp &= ~FDI_LINK_TRAIN_NONE;
3553 temp |= FDI_LINK_TRAIN_PATTERN_1;
3555 /* BPC in FDI rx is consistent with that in PIPECONF */
3556 temp &= ~(0x07 << 16);
3557 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3558 I915_WRITE(reg, temp);
3564 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3566 struct intel_crtc *crtc;
3568 /* Note that we don't need to be called with mode_config.lock here
3569 * as our list of CRTC objects is static for the lifetime of the
3570 * device and so cannot disappear as we iterate. Similarly, we can
3571 * happily treat the predicates as racy, atomic checks as userspace
3572 * cannot claim and pin a new fb without at least acquring the
3573 * struct_mutex and so serialising with us.
3575 for_each_intel_crtc(dev, crtc) {
3576 if (atomic_read(&crtc->unpin_work_count) == 0)
3579 if (crtc->unpin_work)
3580 intel_wait_for_vblank(dev, crtc->pipe);
3588 static void page_flip_completed(struct intel_crtc *intel_crtc)
3590 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3591 struct intel_unpin_work *work = intel_crtc->unpin_work;
3593 /* ensure that the unpin work is consistent wrt ->pending. */
3595 intel_crtc->unpin_work = NULL;
3598 drm_send_vblank_event(intel_crtc->base.dev,
3602 drm_crtc_vblank_put(&intel_crtc->base);
3604 wake_up_all(&dev_priv->pending_flip_queue);
3605 queue_work(dev_priv->wq, &work->work);
3607 trace_i915_flip_complete(intel_crtc->plane,
3608 work->pending_flip_obj);
3611 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3613 struct drm_device *dev = crtc->dev;
3614 struct drm_i915_private *dev_priv = dev->dev_private;
3616 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3617 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3618 !intel_crtc_has_pending_flip(crtc),
3620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622 spin_lock_irq(&dev->event_lock);
3623 if (intel_crtc->unpin_work) {
3624 WARN_ONCE(1, "Removing stuck page flip\n");
3625 page_flip_completed(intel_crtc);
3627 spin_unlock_irq(&dev->event_lock);
3630 if (crtc->primary->fb) {
3631 mutex_lock(&dev->struct_mutex);
3632 intel_finish_fb(crtc->primary->fb);
3633 mutex_unlock(&dev->struct_mutex);
3637 /* Program iCLKIP clock to the desired frequency */
3638 static void lpt_program_iclkip(struct drm_crtc *crtc)
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3643 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3646 mutex_lock(&dev_priv->dpio_lock);
3648 /* It is necessary to ungate the pixclk gate prior to programming
3649 * the divisors, and gate it back when it is done.
3651 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3653 /* Disable SSCCTL */
3654 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3655 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3659 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3660 if (clock == 20000) {
3665 /* The iCLK virtual clock root frequency is in MHz,
3666 * but the adjusted_mode->crtc_clock in in KHz. To get the
3667 * divisors, it is necessary to divide one by another, so we
3668 * convert the virtual clock precision to KHz here for higher
3671 u32 iclk_virtual_root_freq = 172800 * 1000;
3672 u32 iclk_pi_range = 64;
3673 u32 desired_divisor, msb_divisor_value, pi_value;
3675 desired_divisor = (iclk_virtual_root_freq / clock);
3676 msb_divisor_value = desired_divisor / iclk_pi_range;
3677 pi_value = desired_divisor % iclk_pi_range;
3680 divsel = msb_divisor_value - 2;
3681 phaseinc = pi_value;
3684 /* This should not happen with any sane values */
3685 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3686 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3687 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3688 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3690 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3697 /* Program SSCDIVINTPHASE6 */
3698 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3699 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3700 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3701 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3702 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3703 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3704 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3705 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3707 /* Program SSCAUXDIV */
3708 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3709 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3710 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3711 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3713 /* Enable modulator and associated divider */
3714 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3715 temp &= ~SBI_SSCCTL_DISABLE;
3716 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3718 /* Wait for initialization time */
3721 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3723 mutex_unlock(&dev_priv->dpio_lock);
3726 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3727 enum pipe pch_transcoder)
3729 struct drm_device *dev = crtc->base.dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3733 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3734 I915_READ(HTOTAL(cpu_transcoder)));
3735 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3736 I915_READ(HBLANK(cpu_transcoder)));
3737 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3738 I915_READ(HSYNC(cpu_transcoder)));
3740 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3741 I915_READ(VTOTAL(cpu_transcoder)));
3742 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3743 I915_READ(VBLANK(cpu_transcoder)));
3744 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3745 I915_READ(VSYNC(cpu_transcoder)));
3746 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3747 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3750 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3752 struct drm_i915_private *dev_priv = dev->dev_private;
3755 temp = I915_READ(SOUTH_CHICKEN1);
3756 if (temp & FDI_BC_BIFURCATION_SELECT)
3759 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3760 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3762 temp |= FDI_BC_BIFURCATION_SELECT;
3763 DRM_DEBUG_KMS("enabling fdi C rx\n");
3764 I915_WRITE(SOUTH_CHICKEN1, temp);
3765 POSTING_READ(SOUTH_CHICKEN1);
3768 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3770 struct drm_device *dev = intel_crtc->base.dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3773 switch (intel_crtc->pipe) {
3777 if (intel_crtc->config.fdi_lanes > 2)
3778 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3780 cpt_enable_fdi_bc_bifurcation(dev);
3784 cpt_enable_fdi_bc_bifurcation(dev);
3793 * Enable PCH resources required for PCH ports:
3795 * - FDI training & RX/TX
3796 * - update transcoder timings
3797 * - DP transcoding bits
3800 static void ironlake_pch_enable(struct drm_crtc *crtc)
3802 struct drm_device *dev = crtc->dev;
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3805 int pipe = intel_crtc->pipe;
3808 assert_pch_transcoder_disabled(dev_priv, pipe);
3810 if (IS_IVYBRIDGE(dev))
3811 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3813 /* Write the TU size bits before fdi link training, so that error
3814 * detection works. */
3815 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3816 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3818 /* For PCH output, training FDI link */
3819 dev_priv->display.fdi_link_train(crtc);
3821 /* We need to program the right clock selection before writing the pixel
3822 * mutliplier into the DPLL. */
3823 if (HAS_PCH_CPT(dev)) {
3826 temp = I915_READ(PCH_DPLL_SEL);
3827 temp |= TRANS_DPLL_ENABLE(pipe);
3828 sel = TRANS_DPLLB_SEL(pipe);
3829 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3833 I915_WRITE(PCH_DPLL_SEL, temp);
3836 /* XXX: pch pll's can be enabled any time before we enable the PCH
3837 * transcoder, and we actually should do this to not upset any PCH
3838 * transcoder that already use the clock when we share it.
3840 * Note that enable_shared_dpll tries to do the right thing, but
3841 * get_shared_dpll unconditionally resets the pll - we need that to have
3842 * the right LVDS enable sequence. */
3843 intel_enable_shared_dpll(intel_crtc);
3845 /* set transcoder timing, panel must allow it */
3846 assert_panel_unlocked(dev_priv, pipe);
3847 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3849 intel_fdi_normal_train(crtc);
3851 /* For PCH DP, enable TRANS_DP_CTL */
3852 if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3853 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3854 reg = TRANS_DP_CTL(pipe);
3855 temp = I915_READ(reg);
3856 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3857 TRANS_DP_SYNC_MASK |
3859 temp |= (TRANS_DP_OUTPUT_ENABLE |
3860 TRANS_DP_ENH_FRAMING);
3861 temp |= bpc << 9; /* same format but at 11:9 */
3863 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3864 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3865 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3866 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3868 switch (intel_trans_dp_port_sel(crtc)) {
3870 temp |= TRANS_DP_PORT_SEL_B;
3873 temp |= TRANS_DP_PORT_SEL_C;
3876 temp |= TRANS_DP_PORT_SEL_D;
3882 I915_WRITE(reg, temp);
3885 ironlake_enable_pch_transcoder(dev_priv, pipe);
3888 static void lpt_pch_enable(struct drm_crtc *crtc)
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3895 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3897 lpt_program_iclkip(crtc);
3899 /* Set transcoder timing. */
3900 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3902 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3905 void intel_put_shared_dpll(struct intel_crtc *crtc)
3907 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3912 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3913 WARN(1, "bad %s crtc mask\n", pll->name);
3917 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3918 if (pll->config.crtc_mask == 0) {
3920 WARN_ON(pll->active);
3923 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3926 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3928 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3929 struct intel_shared_dpll *pll;
3930 enum intel_dpll_id i;
3932 if (HAS_PCH_IBX(dev_priv->dev)) {
3933 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3934 i = (enum intel_dpll_id) crtc->pipe;
3935 pll = &dev_priv->shared_dplls[i];
3937 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3938 crtc->base.base.id, pll->name);
3940 WARN_ON(pll->new_config->crtc_mask);
3945 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3946 pll = &dev_priv->shared_dplls[i];
3948 /* Only want to check enabled timings first */
3949 if (pll->new_config->crtc_mask == 0)
3952 if (memcmp(&crtc->new_config->dpll_hw_state,
3953 &pll->new_config->hw_state,
3954 sizeof(pll->new_config->hw_state)) == 0) {
3955 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3956 crtc->base.base.id, pll->name,
3957 pll->new_config->crtc_mask,
3963 /* Ok no matching timings, maybe there's a free one? */
3964 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3965 pll = &dev_priv->shared_dplls[i];
3966 if (pll->new_config->crtc_mask == 0) {
3967 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3968 crtc->base.base.id, pll->name);
3976 if (pll->new_config->crtc_mask == 0)
3977 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3979 crtc->new_config->shared_dpll = i;
3980 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3981 pipe_name(crtc->pipe));
3983 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3989 * intel_shared_dpll_start_config - start a new PLL staged config
3990 * @dev_priv: DRM device
3991 * @clear_pipes: mask of pipes that will have their PLLs freed
3993 * Starts a new PLL staged config, copying the current config but
3994 * releasing the references of pipes specified in clear_pipes.
3996 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3997 unsigned clear_pipes)
3999 struct intel_shared_dpll *pll;
4000 enum intel_dpll_id i;
4002 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4003 pll = &dev_priv->shared_dplls[i];
4005 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4007 if (!pll->new_config)
4010 pll->new_config->crtc_mask &= ~clear_pipes;
4017 pll = &dev_priv->shared_dplls[i];
4018 kfree(pll->new_config);
4019 pll->new_config = NULL;
4025 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4027 struct intel_shared_dpll *pll;
4028 enum intel_dpll_id i;
4030 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4031 pll = &dev_priv->shared_dplls[i];
4033 WARN_ON(pll->new_config == &pll->config);
4035 pll->config = *pll->new_config;
4036 kfree(pll->new_config);
4037 pll->new_config = NULL;
4041 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4043 struct intel_shared_dpll *pll;
4044 enum intel_dpll_id i;
4046 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4047 pll = &dev_priv->shared_dplls[i];
4049 WARN_ON(pll->new_config == &pll->config);
4051 kfree(pll->new_config);
4052 pll->new_config = NULL;
4056 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4058 struct drm_i915_private *dev_priv = dev->dev_private;
4059 int dslreg = PIPEDSL(pipe);
4062 temp = I915_READ(dslreg);
4064 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4065 if (wait_for(I915_READ(dslreg) != temp, 5))
4066 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4070 static void skylake_pfit_enable(struct intel_crtc *crtc)
4072 struct drm_device *dev = crtc->base.dev;
4073 struct drm_i915_private *dev_priv = dev->dev_private;
4074 int pipe = crtc->pipe;
4076 if (crtc->config.pch_pfit.enabled) {
4077 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4078 I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4079 I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4083 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4085 struct drm_device *dev = crtc->base.dev;
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 int pipe = crtc->pipe;
4089 if (crtc->config.pch_pfit.enabled) {
4090 /* Force use of hard-coded filter coefficients
4091 * as some pre-programmed values are broken,
4094 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4095 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4096 PF_PIPE_SEL_IVB(pipe));
4098 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4099 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4100 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4104 static void intel_enable_planes(struct drm_crtc *crtc)
4106 struct drm_device *dev = crtc->dev;
4107 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4108 struct drm_plane *plane;
4109 struct intel_plane *intel_plane;
4111 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4112 intel_plane = to_intel_plane(plane);
4113 if (intel_plane->pipe == pipe)
4114 intel_plane_restore(&intel_plane->base);
4118 static void intel_disable_planes(struct drm_crtc *crtc)
4120 struct drm_device *dev = crtc->dev;
4121 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4122 struct drm_plane *plane;
4123 struct intel_plane *intel_plane;
4125 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4126 intel_plane = to_intel_plane(plane);
4127 if (intel_plane->pipe == pipe)
4128 intel_plane_disable(&intel_plane->base);
4132 void hsw_enable_ips(struct intel_crtc *crtc)
4134 struct drm_device *dev = crtc->base.dev;
4135 struct drm_i915_private *dev_priv = dev->dev_private;
4137 if (!crtc->config.ips_enabled)
4140 /* We can only enable IPS after we enable a plane and wait for a vblank */
4141 intel_wait_for_vblank(dev, crtc->pipe);
4143 assert_plane_enabled(dev_priv, crtc->plane);
4144 if (IS_BROADWELL(dev)) {
4145 mutex_lock(&dev_priv->rps.hw_lock);
4146 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4147 mutex_unlock(&dev_priv->rps.hw_lock);
4148 /* Quoting Art Runyan: "its not safe to expect any particular
4149 * value in IPS_CTL bit 31 after enabling IPS through the
4150 * mailbox." Moreover, the mailbox may return a bogus state,
4151 * so we need to just enable it and continue on.
4154 I915_WRITE(IPS_CTL, IPS_ENABLE);
4155 /* The bit only becomes 1 in the next vblank, so this wait here
4156 * is essentially intel_wait_for_vblank. If we don't have this
4157 * and don't wait for vblanks until the end of crtc_enable, then
4158 * the HW state readout code will complain that the expected
4159 * IPS_CTL value is not the one we read. */
4160 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4161 DRM_ERROR("Timed out waiting for IPS enable\n");
4165 void hsw_disable_ips(struct intel_crtc *crtc)
4167 struct drm_device *dev = crtc->base.dev;
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4170 if (!crtc->config.ips_enabled)
4173 assert_plane_enabled(dev_priv, crtc->plane);
4174 if (IS_BROADWELL(dev)) {
4175 mutex_lock(&dev_priv->rps.hw_lock);
4176 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4177 mutex_unlock(&dev_priv->rps.hw_lock);
4178 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4179 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4180 DRM_ERROR("Timed out waiting for IPS disable\n");
4182 I915_WRITE(IPS_CTL, 0);
4183 POSTING_READ(IPS_CTL);
4186 /* We need to wait for a vblank before we can disable the plane. */
4187 intel_wait_for_vblank(dev, crtc->pipe);
4190 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4191 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4193 struct drm_device *dev = crtc->dev;
4194 struct drm_i915_private *dev_priv = dev->dev_private;
4195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196 enum pipe pipe = intel_crtc->pipe;
4197 int palreg = PALETTE(pipe);
4199 bool reenable_ips = false;
4201 /* The clocks have to be on to load the palette. */
4202 if (!crtc->enabled || !intel_crtc->active)
4205 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4206 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4207 assert_dsi_pll_enabled(dev_priv);
4209 assert_pll_enabled(dev_priv, pipe);
4212 /* use legacy palette for Ironlake */
4213 if (!HAS_GMCH_DISPLAY(dev))
4214 palreg = LGC_PALETTE(pipe);
4216 /* Workaround : Do not read or write the pipe palette/gamma data while
4217 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4219 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4220 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4221 GAMMA_MODE_MODE_SPLIT)) {
4222 hsw_disable_ips(intel_crtc);
4223 reenable_ips = true;
4226 for (i = 0; i < 256; i++) {
4227 I915_WRITE(palreg + 4 * i,
4228 (intel_crtc->lut_r[i] << 16) |
4229 (intel_crtc->lut_g[i] << 8) |
4230 intel_crtc->lut_b[i]);
4234 hsw_enable_ips(intel_crtc);
4237 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4239 if (!enable && intel_crtc->overlay) {
4240 struct drm_device *dev = intel_crtc->base.dev;
4241 struct drm_i915_private *dev_priv = dev->dev_private;
4243 mutex_lock(&dev->struct_mutex);
4244 dev_priv->mm.interruptible = false;
4245 (void) intel_overlay_switch_off(intel_crtc->overlay);
4246 dev_priv->mm.interruptible = true;
4247 mutex_unlock(&dev->struct_mutex);
4250 /* Let userspace switch the overlay on again. In most cases userspace
4251 * has to recompute where to put it anyway.
4255 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4257 struct drm_device *dev = crtc->dev;
4258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4259 int pipe = intel_crtc->pipe;
4261 intel_enable_primary_hw_plane(crtc->primary, crtc);
4262 intel_enable_planes(crtc);
4263 intel_crtc_update_cursor(crtc, true);
4264 intel_crtc_dpms_overlay(intel_crtc, true);
4266 hsw_enable_ips(intel_crtc);
4268 mutex_lock(&dev->struct_mutex);
4269 intel_update_fbc(dev);
4270 mutex_unlock(&dev->struct_mutex);
4273 * FIXME: Once we grow proper nuclear flip support out of this we need
4274 * to compute the mask of flip planes precisely. For the time being
4275 * consider this a flip from a NULL plane.
4277 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4280 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4282 struct drm_device *dev = crtc->dev;
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4285 int pipe = intel_crtc->pipe;
4286 int plane = intel_crtc->plane;
4288 intel_crtc_wait_for_pending_flips(crtc);
4290 if (dev_priv->fbc.plane == plane)
4291 intel_disable_fbc(dev);
4293 hsw_disable_ips(intel_crtc);
4295 intel_crtc_dpms_overlay(intel_crtc, false);
4296 intel_crtc_update_cursor(crtc, false);
4297 intel_disable_planes(crtc);
4298 intel_disable_primary_hw_plane(crtc->primary, crtc);
4301 * FIXME: Once we grow proper nuclear flip support out of this we need
4302 * to compute the mask of flip planes precisely. For the time being
4303 * consider this a flip to a NULL plane.
4305 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4308 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4310 struct drm_device *dev = crtc->dev;
4311 struct drm_i915_private *dev_priv = dev->dev_private;
4312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4313 struct intel_encoder *encoder;
4314 int pipe = intel_crtc->pipe;
4316 WARN_ON(!crtc->enabled);
4318 if (intel_crtc->active)
4321 if (intel_crtc->config.has_pch_encoder)
4322 intel_prepare_shared_dpll(intel_crtc);
4324 if (intel_crtc->config.has_dp_encoder)
4325 intel_dp_set_m_n(intel_crtc);
4327 intel_set_pipe_timings(intel_crtc);
4329 if (intel_crtc->config.has_pch_encoder) {
4330 intel_cpu_transcoder_set_m_n(intel_crtc,
4331 &intel_crtc->config.fdi_m_n, NULL);
4334 ironlake_set_pipeconf(crtc);
4336 intel_crtc->active = true;
4338 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4339 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4341 for_each_encoder_on_crtc(dev, crtc, encoder)
4342 if (encoder->pre_enable)
4343 encoder->pre_enable(encoder);
4345 if (intel_crtc->config.has_pch_encoder) {
4346 /* Note: FDI PLL enabling _must_ be done before we enable the
4347 * cpu pipes, hence this is separate from all the other fdi/pch
4349 ironlake_fdi_pll_enable(intel_crtc);
4351 assert_fdi_tx_disabled(dev_priv, pipe);
4352 assert_fdi_rx_disabled(dev_priv, pipe);
4355 ironlake_pfit_enable(intel_crtc);
4358 * On ILK+ LUT must be loaded before the pipe is running but with
4361 intel_crtc_load_lut(crtc);
4363 intel_update_watermarks(crtc);
4364 intel_enable_pipe(intel_crtc);
4366 if (intel_crtc->config.has_pch_encoder)
4367 ironlake_pch_enable(crtc);
4369 for_each_encoder_on_crtc(dev, crtc, encoder)
4370 encoder->enable(encoder);
4372 if (HAS_PCH_CPT(dev))
4373 cpt_verify_modeset(dev, intel_crtc->pipe);
4375 assert_vblank_disabled(crtc);
4376 drm_crtc_vblank_on(crtc);
4378 intel_crtc_enable_planes(crtc);
4381 /* IPS only exists on ULT machines and is tied to pipe A. */
4382 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4384 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4388 * This implements the workaround described in the "notes" section of the mode
4389 * set sequence documentation. When going from no pipes or single pipe to
4390 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4391 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4393 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4395 struct drm_device *dev = crtc->base.dev;
4396 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4398 /* We want to get the other_active_crtc only if there's only 1 other
4400 for_each_intel_crtc(dev, crtc_it) {
4401 if (!crtc_it->active || crtc_it == crtc)
4404 if (other_active_crtc)
4407 other_active_crtc = crtc_it;
4409 if (!other_active_crtc)
4412 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4413 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4416 static void haswell_crtc_enable(struct drm_crtc *crtc)
4418 struct drm_device *dev = crtc->dev;
4419 struct drm_i915_private *dev_priv = dev->dev_private;
4420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4421 struct intel_encoder *encoder;
4422 int pipe = intel_crtc->pipe;
4424 WARN_ON(!crtc->enabled);
4426 if (intel_crtc->active)
4429 if (intel_crtc_to_shared_dpll(intel_crtc))
4430 intel_enable_shared_dpll(intel_crtc);
4432 if (intel_crtc->config.has_dp_encoder)
4433 intel_dp_set_m_n(intel_crtc);
4435 intel_set_pipe_timings(intel_crtc);
4437 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4438 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4439 intel_crtc->config.pixel_multiplier - 1);
4442 if (intel_crtc->config.has_pch_encoder) {
4443 intel_cpu_transcoder_set_m_n(intel_crtc,
4444 &intel_crtc->config.fdi_m_n, NULL);
4447 haswell_set_pipeconf(crtc);
4449 intel_set_pipe_csc(crtc);
4451 intel_crtc->active = true;
4453 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4454 for_each_encoder_on_crtc(dev, crtc, encoder)
4455 if (encoder->pre_enable)
4456 encoder->pre_enable(encoder);
4458 if (intel_crtc->config.has_pch_encoder) {
4459 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4461 dev_priv->display.fdi_link_train(crtc);
4464 intel_ddi_enable_pipe_clock(intel_crtc);
4466 if (IS_SKYLAKE(dev))
4467 skylake_pfit_enable(intel_crtc);
4469 ironlake_pfit_enable(intel_crtc);
4472 * On ILK+ LUT must be loaded before the pipe is running but with
4475 intel_crtc_load_lut(crtc);
4477 intel_ddi_set_pipe_settings(crtc);
4478 intel_ddi_enable_transcoder_func(crtc);
4480 intel_update_watermarks(crtc);
4481 intel_enable_pipe(intel_crtc);
4483 if (intel_crtc->config.has_pch_encoder)
4484 lpt_pch_enable(crtc);
4486 if (intel_crtc->config.dp_encoder_is_mst)
4487 intel_ddi_set_vc_payload_alloc(crtc, true);
4489 for_each_encoder_on_crtc(dev, crtc, encoder) {
4490 encoder->enable(encoder);
4491 intel_opregion_notify_encoder(encoder, true);
4494 assert_vblank_disabled(crtc);
4495 drm_crtc_vblank_on(crtc);
4497 /* If we change the relative order between pipe/planes enabling, we need
4498 * to change the workaround. */
4499 haswell_mode_set_planes_workaround(intel_crtc);
4500 intel_crtc_enable_planes(crtc);
4503 static void skylake_pfit_disable(struct intel_crtc *crtc)
4505 struct drm_device *dev = crtc->base.dev;
4506 struct drm_i915_private *dev_priv = dev->dev_private;
4507 int pipe = crtc->pipe;
4509 /* To avoid upsetting the power well on haswell only disable the pfit if
4510 * it's in use. The hw state code will make sure we get this right. */
4511 if (crtc->config.pch_pfit.enabled) {
4512 I915_WRITE(PS_CTL(pipe), 0);
4513 I915_WRITE(PS_WIN_POS(pipe), 0);
4514 I915_WRITE(PS_WIN_SZ(pipe), 0);
4518 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4520 struct drm_device *dev = crtc->base.dev;
4521 struct drm_i915_private *dev_priv = dev->dev_private;
4522 int pipe = crtc->pipe;
4524 /* To avoid upsetting the power well on haswell only disable the pfit if
4525 * it's in use. The hw state code will make sure we get this right. */
4526 if (crtc->config.pch_pfit.enabled) {
4527 I915_WRITE(PF_CTL(pipe), 0);
4528 I915_WRITE(PF_WIN_POS(pipe), 0);
4529 I915_WRITE(PF_WIN_SZ(pipe), 0);
4533 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4535 struct drm_device *dev = crtc->dev;
4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538 struct intel_encoder *encoder;
4539 int pipe = intel_crtc->pipe;
4542 if (!intel_crtc->active)
4545 intel_crtc_disable_planes(crtc);
4547 drm_crtc_vblank_off(crtc);
4548 assert_vblank_disabled(crtc);
4550 for_each_encoder_on_crtc(dev, crtc, encoder)
4551 encoder->disable(encoder);
4553 if (intel_crtc->config.has_pch_encoder)
4554 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4556 intel_disable_pipe(intel_crtc);
4558 ironlake_pfit_disable(intel_crtc);
4560 for_each_encoder_on_crtc(dev, crtc, encoder)
4561 if (encoder->post_disable)
4562 encoder->post_disable(encoder);
4564 if (intel_crtc->config.has_pch_encoder) {
4565 ironlake_fdi_disable(crtc);
4567 ironlake_disable_pch_transcoder(dev_priv, pipe);
4568 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4570 if (HAS_PCH_CPT(dev)) {
4571 /* disable TRANS_DP_CTL */
4572 reg = TRANS_DP_CTL(pipe);
4573 temp = I915_READ(reg);
4574 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4575 TRANS_DP_PORT_SEL_MASK);
4576 temp |= TRANS_DP_PORT_SEL_NONE;
4577 I915_WRITE(reg, temp);
4579 /* disable DPLL_SEL */
4580 temp = I915_READ(PCH_DPLL_SEL);
4581 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4582 I915_WRITE(PCH_DPLL_SEL, temp);
4585 /* disable PCH DPLL */
4586 intel_disable_shared_dpll(intel_crtc);
4588 ironlake_fdi_pll_disable(intel_crtc);
4591 intel_crtc->active = false;
4592 intel_update_watermarks(crtc);
4594 mutex_lock(&dev->struct_mutex);
4595 intel_update_fbc(dev);
4596 mutex_unlock(&dev->struct_mutex);
4599 static void haswell_crtc_disable(struct drm_crtc *crtc)
4601 struct drm_device *dev = crtc->dev;
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4604 struct intel_encoder *encoder;
4605 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4607 if (!intel_crtc->active)
4610 intel_crtc_disable_planes(crtc);
4612 drm_crtc_vblank_off(crtc);
4613 assert_vblank_disabled(crtc);
4615 for_each_encoder_on_crtc(dev, crtc, encoder) {
4616 intel_opregion_notify_encoder(encoder, false);
4617 encoder->disable(encoder);
4620 if (intel_crtc->config.has_pch_encoder)
4621 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4623 intel_disable_pipe(intel_crtc);
4625 if (intel_crtc->config.dp_encoder_is_mst)
4626 intel_ddi_set_vc_payload_alloc(crtc, false);
4628 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4630 if (IS_SKYLAKE(dev))
4631 skylake_pfit_disable(intel_crtc);
4633 ironlake_pfit_disable(intel_crtc);
4635 intel_ddi_disable_pipe_clock(intel_crtc);
4637 if (intel_crtc->config.has_pch_encoder) {
4638 lpt_disable_pch_transcoder(dev_priv);
4639 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4641 intel_ddi_fdi_disable(crtc);
4644 for_each_encoder_on_crtc(dev, crtc, encoder)
4645 if (encoder->post_disable)
4646 encoder->post_disable(encoder);
4648 intel_crtc->active = false;
4649 intel_update_watermarks(crtc);
4651 mutex_lock(&dev->struct_mutex);
4652 intel_update_fbc(dev);
4653 mutex_unlock(&dev->struct_mutex);
4655 if (intel_crtc_to_shared_dpll(intel_crtc))
4656 intel_disable_shared_dpll(intel_crtc);
4659 static void ironlake_crtc_off(struct drm_crtc *crtc)
4661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4662 intel_put_shared_dpll(intel_crtc);
4666 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4668 struct drm_device *dev = crtc->base.dev;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670 struct intel_crtc_config *pipe_config = &crtc->config;
4672 if (!crtc->config.gmch_pfit.control)
4676 * The panel fitter should only be adjusted whilst the pipe is disabled,
4677 * according to register description and PRM.
4679 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4680 assert_pipe_disabled(dev_priv, crtc->pipe);
4682 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4683 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4685 /* Border color in case we don't scale up to the full screen. Black by
4686 * default, change to something else for debugging. */
4687 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4690 static enum intel_display_power_domain port_to_power_domain(enum port port)
4694 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4696 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4698 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4700 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4703 return POWER_DOMAIN_PORT_OTHER;
4707 #define for_each_power_domain(domain, mask) \
4708 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4709 if ((1 << (domain)) & (mask))
4711 enum intel_display_power_domain
4712 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4714 struct drm_device *dev = intel_encoder->base.dev;
4715 struct intel_digital_port *intel_dig_port;
4717 switch (intel_encoder->type) {
4718 case INTEL_OUTPUT_UNKNOWN:
4719 /* Only DDI platforms should ever use this output type */
4720 WARN_ON_ONCE(!HAS_DDI(dev));
4721 case INTEL_OUTPUT_DISPLAYPORT:
4722 case INTEL_OUTPUT_HDMI:
4723 case INTEL_OUTPUT_EDP:
4724 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4725 return port_to_power_domain(intel_dig_port->port);
4726 case INTEL_OUTPUT_DP_MST:
4727 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4728 return port_to_power_domain(intel_dig_port->port);
4729 case INTEL_OUTPUT_ANALOG:
4730 return POWER_DOMAIN_PORT_CRT;
4731 case INTEL_OUTPUT_DSI:
4732 return POWER_DOMAIN_PORT_DSI;
4734 return POWER_DOMAIN_PORT_OTHER;
4738 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4740 struct drm_device *dev = crtc->dev;
4741 struct intel_encoder *intel_encoder;
4742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4743 enum pipe pipe = intel_crtc->pipe;
4745 enum transcoder transcoder;
4747 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4749 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4750 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4751 if (intel_crtc->config.pch_pfit.enabled ||
4752 intel_crtc->config.pch_pfit.force_thru)
4753 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4755 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4756 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4761 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4763 struct drm_i915_private *dev_priv = dev->dev_private;
4764 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4765 struct intel_crtc *crtc;
4768 * First get all needed power domains, then put all unneeded, to avoid
4769 * any unnecessary toggling of the power wells.
4771 for_each_intel_crtc(dev, crtc) {
4772 enum intel_display_power_domain domain;
4774 if (!crtc->base.enabled)
4777 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4779 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4780 intel_display_power_get(dev_priv, domain);
4783 if (dev_priv->display.modeset_global_resources)
4784 dev_priv->display.modeset_global_resources(dev);
4786 for_each_intel_crtc(dev, crtc) {
4787 enum intel_display_power_domain domain;
4789 for_each_power_domain(domain, crtc->enabled_power_domains)
4790 intel_display_power_put(dev_priv, domain);
4792 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4795 intel_display_set_init_power(dev_priv, false);
4798 /* returns HPLL frequency in kHz */
4799 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4801 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4803 /* Obtain SKU information */
4804 mutex_lock(&dev_priv->dpio_lock);
4805 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4806 CCK_FUSE_HPLL_FREQ_MASK;
4807 mutex_unlock(&dev_priv->dpio_lock);
4809 return vco_freq[hpll_freq] * 1000;
4812 static void vlv_update_cdclk(struct drm_device *dev)
4814 struct drm_i915_private *dev_priv = dev->dev_private;
4816 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4817 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4818 dev_priv->vlv_cdclk_freq);
4821 * Program the gmbus_freq based on the cdclk frequency.
4822 * BSpec erroneously claims we should aim for 4MHz, but
4823 * in fact 1MHz is the correct frequency.
4825 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4828 /* Adjust CDclk dividers to allow high res or save power if possible */
4829 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4834 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4836 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4838 else if (cdclk == 266667)
4843 mutex_lock(&dev_priv->rps.hw_lock);
4844 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4845 val &= ~DSPFREQGUAR_MASK;
4846 val |= (cmd << DSPFREQGUAR_SHIFT);
4847 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4848 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4849 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4851 DRM_ERROR("timed out waiting for CDclk change\n");
4853 mutex_unlock(&dev_priv->rps.hw_lock);
4855 if (cdclk == 400000) {
4858 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4860 mutex_lock(&dev_priv->dpio_lock);
4861 /* adjust cdclk divider */
4862 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4863 val &= ~DISPLAY_FREQUENCY_VALUES;
4865 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4867 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4868 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4870 DRM_ERROR("timed out waiting for CDclk change\n");
4871 mutex_unlock(&dev_priv->dpio_lock);
4874 mutex_lock(&dev_priv->dpio_lock);
4875 /* adjust self-refresh exit latency value */
4876 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4880 * For high bandwidth configs, we set a higher latency in the bunit
4881 * so that the core display fetch happens in time to avoid underruns.
4883 if (cdclk == 400000)
4884 val |= 4500 / 250; /* 4.5 usec */
4886 val |= 3000 / 250; /* 3.0 usec */
4887 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4888 mutex_unlock(&dev_priv->dpio_lock);
4890 vlv_update_cdclk(dev);
4893 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4895 struct drm_i915_private *dev_priv = dev->dev_private;
4898 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4919 mutex_lock(&dev_priv->rps.hw_lock);
4920 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4921 val &= ~DSPFREQGUAR_MASK_CHV;
4922 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4923 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4924 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4925 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4927 DRM_ERROR("timed out waiting for CDclk change\n");
4929 mutex_unlock(&dev_priv->rps.hw_lock);
4931 vlv_update_cdclk(dev);
4934 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4937 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4939 /* FIXME: Punit isn't quite ready yet */
4940 if (IS_CHERRYVIEW(dev_priv->dev))
4944 * Really only a few cases to deal with, as only 4 CDclks are supported:
4947 * 320/333MHz (depends on HPLL freq)
4949 * So we check to see whether we're above 90% of the lower bin and
4952 * We seem to get an unstable or solid color picture at 200MHz.
4953 * Not sure what's wrong. For now use 200MHz only when all pipes
4956 if (max_pixclk > freq_320*9/10)
4958 else if (max_pixclk > 266667*9/10)
4960 else if (max_pixclk > 0)
4966 /* compute the max pixel clock for new configuration */
4967 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4969 struct drm_device *dev = dev_priv->dev;
4970 struct intel_crtc *intel_crtc;
4973 for_each_intel_crtc(dev, intel_crtc) {
4974 if (intel_crtc->new_enabled)
4975 max_pixclk = max(max_pixclk,
4976 intel_crtc->new_config->adjusted_mode.crtc_clock);
4982 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4983 unsigned *prepare_pipes)
4985 struct drm_i915_private *dev_priv = dev->dev_private;
4986 struct intel_crtc *intel_crtc;
4987 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4989 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4990 dev_priv->vlv_cdclk_freq)
4993 /* disable/enable all currently active pipes while we change cdclk */
4994 for_each_intel_crtc(dev, intel_crtc)
4995 if (intel_crtc->base.enabled)
4996 *prepare_pipes |= (1 << intel_crtc->pipe);
4999 static void valleyview_modeset_global_resources(struct drm_device *dev)
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5002 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5003 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5005 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5007 * FIXME: We can end up here with all power domains off, yet
5008 * with a CDCLK frequency other than the minimum. To account
5009 * for this take the PIPE-A power domain, which covers the HW
5010 * blocks needed for the following programming. This can be
5011 * removed once it's guaranteed that we get here either with
5012 * the minimum CDCLK set, or the required power domains
5015 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5017 if (IS_CHERRYVIEW(dev))
5018 cherryview_set_cdclk(dev, req_cdclk);
5020 valleyview_set_cdclk(dev, req_cdclk);
5022 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5026 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5028 struct drm_device *dev = crtc->dev;
5029 struct drm_i915_private *dev_priv = to_i915(dev);
5030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5031 struct intel_encoder *encoder;
5032 int pipe = intel_crtc->pipe;
5035 WARN_ON(!crtc->enabled);
5037 if (intel_crtc->active)
5040 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5043 if (IS_CHERRYVIEW(dev))
5044 chv_prepare_pll(intel_crtc, &intel_crtc->config);
5046 vlv_prepare_pll(intel_crtc, &intel_crtc->config);
5049 if (intel_crtc->config.has_dp_encoder)
5050 intel_dp_set_m_n(intel_crtc);
5052 intel_set_pipe_timings(intel_crtc);
5054 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5055 struct drm_i915_private *dev_priv = dev->dev_private;
5057 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5058 I915_WRITE(CHV_CANVAS(pipe), 0);
5061 i9xx_set_pipeconf(intel_crtc);
5063 intel_crtc->active = true;
5065 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5067 for_each_encoder_on_crtc(dev, crtc, encoder)
5068 if (encoder->pre_pll_enable)
5069 encoder->pre_pll_enable(encoder);
5072 if (IS_CHERRYVIEW(dev))
5073 chv_enable_pll(intel_crtc, &intel_crtc->config);
5075 vlv_enable_pll(intel_crtc, &intel_crtc->config);
5078 for_each_encoder_on_crtc(dev, crtc, encoder)
5079 if (encoder->pre_enable)
5080 encoder->pre_enable(encoder);
5082 i9xx_pfit_enable(intel_crtc);
5084 intel_crtc_load_lut(crtc);
5086 intel_update_watermarks(crtc);
5087 intel_enable_pipe(intel_crtc);
5089 for_each_encoder_on_crtc(dev, crtc, encoder)
5090 encoder->enable(encoder);
5092 assert_vblank_disabled(crtc);
5093 drm_crtc_vblank_on(crtc);
5095 intel_crtc_enable_planes(crtc);
5097 /* Underruns don't raise interrupts, so check manually. */
5098 i9xx_check_fifo_underruns(dev_priv);
5101 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5103 struct drm_device *dev = crtc->base.dev;
5104 struct drm_i915_private *dev_priv = dev->dev_private;
5106 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
5107 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
5110 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5112 struct drm_device *dev = crtc->dev;
5113 struct drm_i915_private *dev_priv = to_i915(dev);
5114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5115 struct intel_encoder *encoder;
5116 int pipe = intel_crtc->pipe;
5118 WARN_ON(!crtc->enabled);
5120 if (intel_crtc->active)
5123 i9xx_set_pll_dividers(intel_crtc);
5125 if (intel_crtc->config.has_dp_encoder)
5126 intel_dp_set_m_n(intel_crtc);
5128 intel_set_pipe_timings(intel_crtc);
5130 i9xx_set_pipeconf(intel_crtc);
5132 intel_crtc->active = true;
5135 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5137 for_each_encoder_on_crtc(dev, crtc, encoder)
5138 if (encoder->pre_enable)
5139 encoder->pre_enable(encoder);
5141 i9xx_enable_pll(intel_crtc);
5143 i9xx_pfit_enable(intel_crtc);
5145 intel_crtc_load_lut(crtc);
5147 intel_update_watermarks(crtc);
5148 intel_enable_pipe(intel_crtc);
5150 for_each_encoder_on_crtc(dev, crtc, encoder)
5151 encoder->enable(encoder);
5153 assert_vblank_disabled(crtc);
5154 drm_crtc_vblank_on(crtc);
5156 intel_crtc_enable_planes(crtc);
5159 * Gen2 reports pipe underruns whenever all planes are disabled.
5160 * So don't enable underrun reporting before at least some planes
5162 * FIXME: Need to fix the logic to work when we turn off all planes
5163 * but leave the pipe running.
5166 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5168 /* Underruns don't raise interrupts, so check manually. */
5169 i9xx_check_fifo_underruns(dev_priv);
5172 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5174 struct drm_device *dev = crtc->base.dev;
5175 struct drm_i915_private *dev_priv = dev->dev_private;
5177 if (!crtc->config.gmch_pfit.control)
5180 assert_pipe_disabled(dev_priv, crtc->pipe);
5182 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5183 I915_READ(PFIT_CONTROL));
5184 I915_WRITE(PFIT_CONTROL, 0);
5187 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5189 struct drm_device *dev = crtc->dev;
5190 struct drm_i915_private *dev_priv = dev->dev_private;
5191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5192 struct intel_encoder *encoder;
5193 int pipe = intel_crtc->pipe;
5195 if (!intel_crtc->active)
5199 * Gen2 reports pipe underruns whenever all planes are disabled.
5200 * So diasble underrun reporting before all the planes get disabled.
5201 * FIXME: Need to fix the logic to work when we turn off all planes
5202 * but leave the pipe running.
5205 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5208 * Vblank time updates from the shadow to live plane control register
5209 * are blocked if the memory self-refresh mode is active at that
5210 * moment. So to make sure the plane gets truly disabled, disable
5211 * first the self-refresh mode. The self-refresh enable bit in turn
5212 * will be checked/applied by the HW only at the next frame start
5213 * event which is after the vblank start event, so we need to have a
5214 * wait-for-vblank between disabling the plane and the pipe.
5216 intel_set_memory_cxsr(dev_priv, false);
5217 intel_crtc_disable_planes(crtc);
5220 * On gen2 planes are double buffered but the pipe isn't, so we must
5221 * wait for planes to fully turn off before disabling the pipe.
5222 * We also need to wait on all gmch platforms because of the
5223 * self-refresh mode constraint explained above.
5225 intel_wait_for_vblank(dev, pipe);
5227 drm_crtc_vblank_off(crtc);
5228 assert_vblank_disabled(crtc);
5230 for_each_encoder_on_crtc(dev, crtc, encoder)
5231 encoder->disable(encoder);
5233 intel_disable_pipe(intel_crtc);
5235 i9xx_pfit_disable(intel_crtc);
5237 for_each_encoder_on_crtc(dev, crtc, encoder)
5238 if (encoder->post_disable)
5239 encoder->post_disable(encoder);
5241 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5242 if (IS_CHERRYVIEW(dev))
5243 chv_disable_pll(dev_priv, pipe);
5244 else if (IS_VALLEYVIEW(dev))
5245 vlv_disable_pll(dev_priv, pipe);
5247 i9xx_disable_pll(intel_crtc);
5251 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5253 intel_crtc->active = false;
5254 intel_update_watermarks(crtc);
5256 mutex_lock(&dev->struct_mutex);
5257 intel_update_fbc(dev);
5258 mutex_unlock(&dev->struct_mutex);
5261 static void i9xx_crtc_off(struct drm_crtc *crtc)
5265 /* Master function to enable/disable CRTC and corresponding power wells */
5266 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5268 struct drm_device *dev = crtc->dev;
5269 struct drm_i915_private *dev_priv = dev->dev_private;
5270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5271 enum intel_display_power_domain domain;
5272 unsigned long domains;
5275 if (!intel_crtc->active) {
5276 domains = get_crtc_power_domains(crtc);
5277 for_each_power_domain(domain, domains)
5278 intel_display_power_get(dev_priv, domain);
5279 intel_crtc->enabled_power_domains = domains;
5281 dev_priv->display.crtc_enable(crtc);
5284 if (intel_crtc->active) {
5285 dev_priv->display.crtc_disable(crtc);
5287 domains = intel_crtc->enabled_power_domains;
5288 for_each_power_domain(domain, domains)
5289 intel_display_power_put(dev_priv, domain);
5290 intel_crtc->enabled_power_domains = 0;
5296 * Sets the power management mode of the pipe and plane.
5298 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5300 struct drm_device *dev = crtc->dev;
5301 struct intel_encoder *intel_encoder;
5302 bool enable = false;
5304 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5305 enable |= intel_encoder->connectors_active;
5307 intel_crtc_control(crtc, enable);
5310 static void intel_crtc_disable(struct drm_crtc *crtc)
5312 struct drm_device *dev = crtc->dev;
5313 struct drm_connector *connector;
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5316 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5318 /* crtc should still be enabled when we disable it. */
5319 WARN_ON(!crtc->enabled);
5321 dev_priv->display.crtc_disable(crtc);
5322 dev_priv->display.off(crtc);
5324 if (crtc->primary->fb) {
5325 mutex_lock(&dev->struct_mutex);
5326 intel_unpin_fb_obj(old_obj);
5327 i915_gem_track_fb(old_obj, NULL,
5328 INTEL_FRONTBUFFER_PRIMARY(pipe));
5329 mutex_unlock(&dev->struct_mutex);
5330 crtc->primary->fb = NULL;
5333 /* Update computed state. */
5334 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5335 if (!connector->encoder || !connector->encoder->crtc)
5338 if (connector->encoder->crtc != crtc)
5341 connector->dpms = DRM_MODE_DPMS_OFF;
5342 to_intel_encoder(connector->encoder)->connectors_active = false;
5346 void intel_encoder_destroy(struct drm_encoder *encoder)
5348 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5350 drm_encoder_cleanup(encoder);
5351 kfree(intel_encoder);
5354 /* Simple dpms helper for encoders with just one connector, no cloning and only
5355 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5356 * state of the entire output pipe. */
5357 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5359 if (mode == DRM_MODE_DPMS_ON) {
5360 encoder->connectors_active = true;
5362 intel_crtc_update_dpms(encoder->base.crtc);
5364 encoder->connectors_active = false;
5366 intel_crtc_update_dpms(encoder->base.crtc);
5370 /* Cross check the actual hw state with our own modeset state tracking (and it's
5371 * internal consistency). */
5372 static void intel_connector_check_state(struct intel_connector *connector)
5374 if (connector->get_hw_state(connector)) {
5375 struct intel_encoder *encoder = connector->encoder;
5376 struct drm_crtc *crtc;
5377 bool encoder_enabled;
5380 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5381 connector->base.base.id,
5382 connector->base.name);
5384 /* there is no real hw state for MST connectors */
5385 if (connector->mst_port)
5388 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5389 "wrong connector dpms state\n");
5390 WARN(connector->base.encoder != &encoder->base,
5391 "active connector not linked to encoder\n");
5394 WARN(!encoder->connectors_active,
5395 "encoder->connectors_active not set\n");
5397 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5398 WARN(!encoder_enabled, "encoder not enabled\n");
5399 if (WARN_ON(!encoder->base.crtc))
5402 crtc = encoder->base.crtc;
5404 WARN(!crtc->enabled, "crtc not enabled\n");
5405 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5406 WARN(pipe != to_intel_crtc(crtc)->pipe,
5407 "encoder active on the wrong pipe\n");
5412 /* Even simpler default implementation, if there's really no special case to
5414 void intel_connector_dpms(struct drm_connector *connector, int mode)
5416 /* All the simple cases only support two dpms states. */
5417 if (mode != DRM_MODE_DPMS_ON)
5418 mode = DRM_MODE_DPMS_OFF;
5420 if (mode == connector->dpms)
5423 connector->dpms = mode;
5425 /* Only need to change hw state when actually enabled */
5426 if (connector->encoder)
5427 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5429 intel_modeset_check_state(connector->dev);
5432 /* Simple connector->get_hw_state implementation for encoders that support only
5433 * one connector and no cloning and hence the encoder state determines the state
5434 * of the connector. */
5435 bool intel_connector_get_hw_state(struct intel_connector *connector)
5438 struct intel_encoder *encoder = connector->encoder;
5440 return encoder->get_hw_state(encoder, &pipe);
5443 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5444 struct intel_crtc_config *pipe_config)
5446 struct drm_i915_private *dev_priv = dev->dev_private;
5447 struct intel_crtc *pipe_B_crtc =
5448 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5450 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5451 pipe_name(pipe), pipe_config->fdi_lanes);
5452 if (pipe_config->fdi_lanes > 4) {
5453 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5454 pipe_name(pipe), pipe_config->fdi_lanes);
5458 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5459 if (pipe_config->fdi_lanes > 2) {
5460 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5461 pipe_config->fdi_lanes);
5468 if (INTEL_INFO(dev)->num_pipes == 2)
5471 /* Ivybridge 3 pipe is really complicated */
5476 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5477 pipe_config->fdi_lanes > 2) {
5478 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5479 pipe_name(pipe), pipe_config->fdi_lanes);
5484 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5485 pipe_B_crtc->config.fdi_lanes <= 2) {
5486 if (pipe_config->fdi_lanes > 2) {
5487 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5488 pipe_name(pipe), pipe_config->fdi_lanes);
5492 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5502 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5503 struct intel_crtc_config *pipe_config)
5505 struct drm_device *dev = intel_crtc->base.dev;
5506 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5507 int lane, link_bw, fdi_dotclock;
5508 bool setup_ok, needs_recompute = false;
5511 /* FDI is a binary signal running at ~2.7GHz, encoding
5512 * each output octet as 10 bits. The actual frequency
5513 * is stored as a divider into a 100MHz clock, and the
5514 * mode pixel clock is stored in units of 1KHz.
5515 * Hence the bw of each lane in terms of the mode signal
5518 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5520 fdi_dotclock = adjusted_mode->crtc_clock;
5522 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5523 pipe_config->pipe_bpp);
5525 pipe_config->fdi_lanes = lane;
5527 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5528 link_bw, &pipe_config->fdi_m_n);
5530 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5531 intel_crtc->pipe, pipe_config);
5532 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5533 pipe_config->pipe_bpp -= 2*3;
5534 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5535 pipe_config->pipe_bpp);
5536 needs_recompute = true;
5537 pipe_config->bw_constrained = true;
5542 if (needs_recompute)
5545 return setup_ok ? 0 : -EINVAL;
5548 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5549 struct intel_crtc_config *pipe_config)
5551 pipe_config->ips_enabled = i915.enable_ips &&
5552 hsw_crtc_supports_ips(crtc) &&
5553 pipe_config->pipe_bpp <= 24;
5556 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5557 struct intel_crtc_config *pipe_config)
5559 struct drm_device *dev = crtc->base.dev;
5560 struct drm_i915_private *dev_priv = dev->dev_private;
5561 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5563 /* FIXME should check pixel clock limits on all platforms */
5564 if (INTEL_INFO(dev)->gen < 4) {
5566 dev_priv->display.get_display_clock_speed(dev);
5569 * Enable pixel doubling when the dot clock
5570 * is > 90% of the (display) core speed.
5572 * GDG double wide on either pipe,
5573 * otherwise pipe A only.
5575 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5576 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5578 pipe_config->double_wide = true;
5581 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5586 * Pipe horizontal size must be even in:
5588 * - LVDS dual channel mode
5589 * - Double wide pipe
5591 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5592 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5593 pipe_config->pipe_src_w &= ~1;
5595 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5596 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5598 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5599 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5602 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5603 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5604 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5605 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5607 pipe_config->pipe_bpp = 8*3;
5611 hsw_compute_ips_config(crtc, pipe_config);
5613 if (pipe_config->has_pch_encoder)
5614 return ironlake_fdi_compute_config(crtc, pipe_config);
5619 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5621 struct drm_i915_private *dev_priv = dev->dev_private;
5625 /* FIXME: Punit isn't quite ready yet */
5626 if (IS_CHERRYVIEW(dev))
5629 if (dev_priv->hpll_freq == 0)
5630 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5632 mutex_lock(&dev_priv->dpio_lock);
5633 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5634 mutex_unlock(&dev_priv->dpio_lock);
5636 divider = val & DISPLAY_FREQUENCY_VALUES;
5638 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5639 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5640 "cdclk change in progress\n");
5642 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5645 static int i945_get_display_clock_speed(struct drm_device *dev)
5650 static int i915_get_display_clock_speed(struct drm_device *dev)
5655 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5660 static int pnv_get_display_clock_speed(struct drm_device *dev)
5664 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5666 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5667 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5669 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5671 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5673 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5676 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5677 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5679 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5684 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5688 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5690 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5693 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5694 case GC_DISPLAY_CLOCK_333_MHZ:
5697 case GC_DISPLAY_CLOCK_190_200_MHZ:
5703 static int i865_get_display_clock_speed(struct drm_device *dev)
5708 static int i855_get_display_clock_speed(struct drm_device *dev)
5711 /* Assume that the hardware is in the high speed state. This
5712 * should be the default.
5714 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5715 case GC_CLOCK_133_200:
5716 case GC_CLOCK_100_200:
5718 case GC_CLOCK_166_250:
5720 case GC_CLOCK_100_133:
5724 /* Shouldn't happen */
5728 static int i830_get_display_clock_speed(struct drm_device *dev)
5734 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5736 while (*num > DATA_LINK_M_N_MASK ||
5737 *den > DATA_LINK_M_N_MASK) {
5743 static void compute_m_n(unsigned int m, unsigned int n,
5744 uint32_t *ret_m, uint32_t *ret_n)
5746 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5747 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5748 intel_reduce_m_n_ratio(ret_m, ret_n);
5752 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5753 int pixel_clock, int link_clock,
5754 struct intel_link_m_n *m_n)
5758 compute_m_n(bits_per_pixel * pixel_clock,
5759 link_clock * nlanes * 8,
5760 &m_n->gmch_m, &m_n->gmch_n);
5762 compute_m_n(pixel_clock, link_clock,
5763 &m_n->link_m, &m_n->link_n);
5766 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5768 if (i915.panel_use_ssc >= 0)
5769 return i915.panel_use_ssc != 0;
5770 return dev_priv->vbt.lvds_use_ssc
5771 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5774 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5776 struct drm_device *dev = crtc->base.dev;
5777 struct drm_i915_private *dev_priv = dev->dev_private;
5780 if (IS_VALLEYVIEW(dev)) {
5782 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5783 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5784 refclk = dev_priv->vbt.lvds_ssc_freq;
5785 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5786 } else if (!IS_GEN2(dev)) {
5795 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5797 return (1 << dpll->n) << 16 | dpll->m2;
5800 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5802 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5805 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5806 intel_clock_t *reduced_clock)
5808 struct drm_device *dev = crtc->base.dev;
5811 if (IS_PINEVIEW(dev)) {
5812 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
5814 fp2 = pnv_dpll_compute_fp(reduced_clock);
5816 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
5818 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5821 crtc->new_config->dpll_hw_state.fp0 = fp;
5823 crtc->lowfreq_avail = false;
5824 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5825 reduced_clock && i915.powersave) {
5826 crtc->new_config->dpll_hw_state.fp1 = fp2;
5827 crtc->lowfreq_avail = true;
5829 crtc->new_config->dpll_hw_state.fp1 = fp;
5833 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5839 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5840 * and set it to a reasonable value instead.
5842 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5843 reg_val &= 0xffffff00;
5844 reg_val |= 0x00000030;
5845 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5847 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5848 reg_val &= 0x8cffffff;
5849 reg_val = 0x8c000000;
5850 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5852 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5853 reg_val &= 0xffffff00;
5854 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5856 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5857 reg_val &= 0x00ffffff;
5858 reg_val |= 0xb0000000;
5859 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5862 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5863 struct intel_link_m_n *m_n)
5865 struct drm_device *dev = crtc->base.dev;
5866 struct drm_i915_private *dev_priv = dev->dev_private;
5867 int pipe = crtc->pipe;
5869 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5870 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5871 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5872 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5875 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5876 struct intel_link_m_n *m_n,
5877 struct intel_link_m_n *m2_n2)
5879 struct drm_device *dev = crtc->base.dev;
5880 struct drm_i915_private *dev_priv = dev->dev_private;
5881 int pipe = crtc->pipe;
5882 enum transcoder transcoder = crtc->config.cpu_transcoder;
5884 if (INTEL_INFO(dev)->gen >= 5) {
5885 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5886 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5887 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5888 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5889 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5890 * for gen < 8) and if DRRS is supported (to make sure the
5891 * registers are not unnecessarily accessed).
5893 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5894 crtc->config.has_drrs) {
5895 I915_WRITE(PIPE_DATA_M2(transcoder),
5896 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5897 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5898 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5899 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5902 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5903 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5904 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5905 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5909 void intel_dp_set_m_n(struct intel_crtc *crtc)
5911 if (crtc->config.has_pch_encoder)
5912 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5914 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5915 &crtc->config.dp_m2_n2);
5918 static void vlv_update_pll(struct intel_crtc *crtc,
5919 struct intel_crtc_config *pipe_config)
5924 * Enable DPIO clock input. We should never disable the reference
5925 * clock for pipe B, since VGA hotplug / manual detection depends
5928 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5929 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5930 /* We should never disable this, set it here for state tracking */
5931 if (crtc->pipe == PIPE_B)
5932 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5933 dpll |= DPLL_VCO_ENABLE;
5934 pipe_config->dpll_hw_state.dpll = dpll;
5936 dpll_md = (pipe_config->pixel_multiplier - 1)
5937 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5938 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5941 static void vlv_prepare_pll(struct intel_crtc *crtc,
5942 const struct intel_crtc_config *pipe_config)
5944 struct drm_device *dev = crtc->base.dev;
5945 struct drm_i915_private *dev_priv = dev->dev_private;
5946 int pipe = crtc->pipe;
5948 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5949 u32 coreclk, reg_val;
5951 mutex_lock(&dev_priv->dpio_lock);
5953 bestn = pipe_config->dpll.n;
5954 bestm1 = pipe_config->dpll.m1;
5955 bestm2 = pipe_config->dpll.m2;
5956 bestp1 = pipe_config->dpll.p1;
5957 bestp2 = pipe_config->dpll.p2;
5959 /* See eDP HDMI DPIO driver vbios notes doc */
5961 /* PLL B needs special handling */
5963 vlv_pllb_recal_opamp(dev_priv, pipe);
5965 /* Set up Tx target for periodic Rcomp update */
5966 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5968 /* Disable target IRef on PLL */
5969 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5970 reg_val &= 0x00ffffff;
5971 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5973 /* Disable fast lock */
5974 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5976 /* Set idtafcrecal before PLL is enabled */
5977 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5978 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5979 mdiv |= ((bestn << DPIO_N_SHIFT));
5980 mdiv |= (1 << DPIO_K_SHIFT);
5983 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5984 * but we don't support that).
5985 * Note: don't use the DAC post divider as it seems unstable.
5987 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5988 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5990 mdiv |= DPIO_ENABLE_CALIBRATION;
5991 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5993 /* Set HBR and RBR LPF coefficients */
5994 if (pipe_config->port_clock == 162000 ||
5995 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5996 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5997 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6000 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6003 if (crtc->config.has_dp_encoder) {
6004 /* Use SSC source */
6006 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6009 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6011 } else { /* HDMI or VGA */
6012 /* Use bend source */
6014 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6017 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6021 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6022 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6023 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6024 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6025 coreclk |= 0x01000000;
6026 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6028 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6029 mutex_unlock(&dev_priv->dpio_lock);
6032 static void chv_update_pll(struct intel_crtc *crtc,
6033 struct intel_crtc_config *pipe_config)
6035 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6036 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6038 if (crtc->pipe != PIPE_A)
6039 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6041 pipe_config->dpll_hw_state.dpll_md =
6042 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6045 static void chv_prepare_pll(struct intel_crtc *crtc,
6046 const struct intel_crtc_config *pipe_config)
6048 struct drm_device *dev = crtc->base.dev;
6049 struct drm_i915_private *dev_priv = dev->dev_private;
6050 int pipe = crtc->pipe;
6051 int dpll_reg = DPLL(crtc->pipe);
6052 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6053 u32 loopfilter, intcoeff;
6054 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6057 bestn = pipe_config->dpll.n;
6058 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6059 bestm1 = pipe_config->dpll.m1;
6060 bestm2 = pipe_config->dpll.m2 >> 22;
6061 bestp1 = pipe_config->dpll.p1;
6062 bestp2 = pipe_config->dpll.p2;
6065 * Enable Refclk and SSC
6067 I915_WRITE(dpll_reg,
6068 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6070 mutex_lock(&dev_priv->dpio_lock);
6072 /* p1 and p2 divider */
6073 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6074 5 << DPIO_CHV_S1_DIV_SHIFT |
6075 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6076 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6077 1 << DPIO_CHV_K_DIV_SHIFT);
6079 /* Feedback post-divider - m2 */
6080 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6082 /* Feedback refclk divider - n and m1 */
6083 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6084 DPIO_CHV_M1_DIV_BY_2 |
6085 1 << DPIO_CHV_N_DIV_SHIFT);
6087 /* M2 fraction division */
6088 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6090 /* M2 fraction division enable */
6091 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6092 DPIO_CHV_FRAC_DIV_EN |
6093 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6096 refclk = i9xx_get_refclk(crtc, 0);
6097 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6098 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6099 if (refclk == 100000)
6101 else if (refclk == 38400)
6105 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6106 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6109 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6110 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6113 mutex_unlock(&dev_priv->dpio_lock);
6117 * vlv_force_pll_on - forcibly enable just the PLL
6118 * @dev_priv: i915 private structure
6119 * @pipe: pipe PLL to enable
6120 * @dpll: PLL configuration
6122 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6123 * in cases where we need the PLL enabled even when @pipe is not going to
6126 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6127 const struct dpll *dpll)
6129 struct intel_crtc *crtc =
6130 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6131 struct intel_crtc_config pipe_config = {
6132 .pixel_multiplier = 1,
6136 if (IS_CHERRYVIEW(dev)) {
6137 chv_update_pll(crtc, &pipe_config);
6138 chv_prepare_pll(crtc, &pipe_config);
6139 chv_enable_pll(crtc, &pipe_config);
6141 vlv_update_pll(crtc, &pipe_config);
6142 vlv_prepare_pll(crtc, &pipe_config);
6143 vlv_enable_pll(crtc, &pipe_config);
6148 * vlv_force_pll_off - forcibly disable just the PLL
6149 * @dev_priv: i915 private structure
6150 * @pipe: pipe PLL to disable
6152 * Disable the PLL for @pipe. To be used in cases where we need
6153 * the PLL enabled even when @pipe is not going to be enabled.
6155 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6157 if (IS_CHERRYVIEW(dev))
6158 chv_disable_pll(to_i915(dev), pipe);
6160 vlv_disable_pll(to_i915(dev), pipe);
6163 static void i9xx_update_pll(struct intel_crtc *crtc,
6164 intel_clock_t *reduced_clock,
6167 struct drm_device *dev = crtc->base.dev;
6168 struct drm_i915_private *dev_priv = dev->dev_private;
6171 struct dpll *clock = &crtc->new_config->dpll;
6173 i9xx_update_pll_dividers(crtc, reduced_clock);
6175 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6176 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6178 dpll = DPLL_VGA_MODE_DIS;
6180 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6181 dpll |= DPLLB_MODE_LVDS;
6183 dpll |= DPLLB_MODE_DAC_SERIAL;
6185 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6186 dpll |= (crtc->new_config->pixel_multiplier - 1)
6187 << SDVO_MULTIPLIER_SHIFT_HIRES;
6191 dpll |= DPLL_SDVO_HIGH_SPEED;
6193 if (crtc->new_config->has_dp_encoder)
6194 dpll |= DPLL_SDVO_HIGH_SPEED;
6196 /* compute bitmask from p1 value */
6197 if (IS_PINEVIEW(dev))
6198 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6200 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6201 if (IS_G4X(dev) && reduced_clock)
6202 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6204 switch (clock->p2) {
6206 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6209 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6212 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6215 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6218 if (INTEL_INFO(dev)->gen >= 4)
6219 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6221 if (crtc->new_config->sdvo_tv_clock)
6222 dpll |= PLL_REF_INPUT_TVCLKINBC;
6223 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6224 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6225 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6227 dpll |= PLL_REF_INPUT_DREFCLK;
6229 dpll |= DPLL_VCO_ENABLE;
6230 crtc->new_config->dpll_hw_state.dpll = dpll;
6232 if (INTEL_INFO(dev)->gen >= 4) {
6233 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6234 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6235 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6239 static void i8xx_update_pll(struct intel_crtc *crtc,
6240 intel_clock_t *reduced_clock,
6243 struct drm_device *dev = crtc->base.dev;
6244 struct drm_i915_private *dev_priv = dev->dev_private;
6246 struct dpll *clock = &crtc->new_config->dpll;
6248 i9xx_update_pll_dividers(crtc, reduced_clock);
6250 dpll = DPLL_VGA_MODE_DIS;
6252 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6253 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6256 dpll |= PLL_P1_DIVIDE_BY_TWO;
6258 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6260 dpll |= PLL_P2_DIVIDE_BY_4;
6263 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6264 dpll |= DPLL_DVO_2X_MODE;
6266 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6267 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6268 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6270 dpll |= PLL_REF_INPUT_DREFCLK;
6272 dpll |= DPLL_VCO_ENABLE;
6273 crtc->new_config->dpll_hw_state.dpll = dpll;
6276 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6278 struct drm_device *dev = intel_crtc->base.dev;
6279 struct drm_i915_private *dev_priv = dev->dev_private;
6280 enum pipe pipe = intel_crtc->pipe;
6281 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6282 struct drm_display_mode *adjusted_mode =
6283 &intel_crtc->config.adjusted_mode;
6284 uint32_t crtc_vtotal, crtc_vblank_end;
6287 /* We need to be careful not to changed the adjusted mode, for otherwise
6288 * the hw state checker will get angry at the mismatch. */
6289 crtc_vtotal = adjusted_mode->crtc_vtotal;
6290 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6292 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6293 /* the chip adds 2 halflines automatically */
6295 crtc_vblank_end -= 1;
6297 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6298 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6300 vsyncshift = adjusted_mode->crtc_hsync_start -
6301 adjusted_mode->crtc_htotal / 2;
6303 vsyncshift += adjusted_mode->crtc_htotal;
6306 if (INTEL_INFO(dev)->gen > 3)
6307 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6309 I915_WRITE(HTOTAL(cpu_transcoder),
6310 (adjusted_mode->crtc_hdisplay - 1) |
6311 ((adjusted_mode->crtc_htotal - 1) << 16));
6312 I915_WRITE(HBLANK(cpu_transcoder),
6313 (adjusted_mode->crtc_hblank_start - 1) |
6314 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6315 I915_WRITE(HSYNC(cpu_transcoder),
6316 (adjusted_mode->crtc_hsync_start - 1) |
6317 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6319 I915_WRITE(VTOTAL(cpu_transcoder),
6320 (adjusted_mode->crtc_vdisplay - 1) |
6321 ((crtc_vtotal - 1) << 16));
6322 I915_WRITE(VBLANK(cpu_transcoder),
6323 (adjusted_mode->crtc_vblank_start - 1) |
6324 ((crtc_vblank_end - 1) << 16));
6325 I915_WRITE(VSYNC(cpu_transcoder),
6326 (adjusted_mode->crtc_vsync_start - 1) |
6327 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6329 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6330 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6331 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6333 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6334 (pipe == PIPE_B || pipe == PIPE_C))
6335 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6337 /* pipesrc controls the size that is scaled from, which should
6338 * always be the user's requested size.
6340 I915_WRITE(PIPESRC(pipe),
6341 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6342 (intel_crtc->config.pipe_src_h - 1));
6345 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6346 struct intel_crtc_config *pipe_config)
6348 struct drm_device *dev = crtc->base.dev;
6349 struct drm_i915_private *dev_priv = dev->dev_private;
6350 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6353 tmp = I915_READ(HTOTAL(cpu_transcoder));
6354 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6355 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6356 tmp = I915_READ(HBLANK(cpu_transcoder));
6357 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6358 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6359 tmp = I915_READ(HSYNC(cpu_transcoder));
6360 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6361 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6363 tmp = I915_READ(VTOTAL(cpu_transcoder));
6364 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6365 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6366 tmp = I915_READ(VBLANK(cpu_transcoder));
6367 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6368 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6369 tmp = I915_READ(VSYNC(cpu_transcoder));
6370 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6371 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6373 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6374 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6375 pipe_config->adjusted_mode.crtc_vtotal += 1;
6376 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6379 tmp = I915_READ(PIPESRC(crtc->pipe));
6380 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6381 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6383 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6384 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6387 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6388 struct intel_crtc_config *pipe_config)
6390 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6391 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6392 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6393 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6395 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6396 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6397 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6398 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6400 mode->flags = pipe_config->adjusted_mode.flags;
6402 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6403 mode->flags |= pipe_config->adjusted_mode.flags;
6406 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6408 struct drm_device *dev = intel_crtc->base.dev;
6409 struct drm_i915_private *dev_priv = dev->dev_private;
6414 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6415 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6416 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6418 if (intel_crtc->config.double_wide)
6419 pipeconf |= PIPECONF_DOUBLE_WIDE;
6421 /* only g4x and later have fancy bpc/dither controls */
6422 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6423 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6424 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6425 pipeconf |= PIPECONF_DITHER_EN |
6426 PIPECONF_DITHER_TYPE_SP;
6428 switch (intel_crtc->config.pipe_bpp) {
6430 pipeconf |= PIPECONF_6BPC;
6433 pipeconf |= PIPECONF_8BPC;
6436 pipeconf |= PIPECONF_10BPC;
6439 /* Case prevented by intel_choose_pipe_bpp_dither. */
6444 if (HAS_PIPE_CXSR(dev)) {
6445 if (intel_crtc->lowfreq_avail) {
6446 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6447 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6449 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6453 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6454 if (INTEL_INFO(dev)->gen < 4 ||
6455 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6456 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6458 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6460 pipeconf |= PIPECONF_PROGRESSIVE;
6462 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6463 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6465 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6466 POSTING_READ(PIPECONF(intel_crtc->pipe));
6469 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6471 struct drm_device *dev = crtc->base.dev;
6472 struct drm_i915_private *dev_priv = dev->dev_private;
6473 int refclk, num_connectors = 0;
6474 intel_clock_t clock, reduced_clock;
6475 bool ok, has_reduced_clock = false;
6476 bool is_lvds = false, is_dsi = false;
6477 struct intel_encoder *encoder;
6478 const intel_limit_t *limit;
6480 for_each_intel_encoder(dev, encoder) {
6481 if (encoder->new_crtc != crtc)
6484 switch (encoder->type) {
6485 case INTEL_OUTPUT_LVDS:
6488 case INTEL_OUTPUT_DSI:
6501 if (!crtc->new_config->clock_set) {
6502 refclk = i9xx_get_refclk(crtc, num_connectors);
6505 * Returns a set of divisors for the desired target clock with
6506 * the given refclk, or FALSE. The returned values represent
6507 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6510 limit = intel_limit(crtc, refclk);
6511 ok = dev_priv->display.find_dpll(limit, crtc,
6512 crtc->new_config->port_clock,
6513 refclk, NULL, &clock);
6515 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6519 if (is_lvds && dev_priv->lvds_downclock_avail) {
6521 * Ensure we match the reduced clock's P to the target
6522 * clock. If the clocks don't match, we can't switch
6523 * the display clock by using the FP0/FP1. In such case
6524 * we will disable the LVDS downclock feature.
6527 dev_priv->display.find_dpll(limit, crtc,
6528 dev_priv->lvds_downclock,
6532 /* Compat-code for transition, will disappear. */
6533 crtc->new_config->dpll.n = clock.n;
6534 crtc->new_config->dpll.m1 = clock.m1;
6535 crtc->new_config->dpll.m2 = clock.m2;
6536 crtc->new_config->dpll.p1 = clock.p1;
6537 crtc->new_config->dpll.p2 = clock.p2;
6541 i8xx_update_pll(crtc,
6542 has_reduced_clock ? &reduced_clock : NULL,
6544 } else if (IS_CHERRYVIEW(dev)) {
6545 chv_update_pll(crtc, crtc->new_config);
6546 } else if (IS_VALLEYVIEW(dev)) {
6547 vlv_update_pll(crtc, crtc->new_config);
6549 i9xx_update_pll(crtc,
6550 has_reduced_clock ? &reduced_clock : NULL,
6557 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6558 struct intel_crtc_config *pipe_config)
6560 struct drm_device *dev = crtc->base.dev;
6561 struct drm_i915_private *dev_priv = dev->dev_private;
6564 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6567 tmp = I915_READ(PFIT_CONTROL);
6568 if (!(tmp & PFIT_ENABLE))
6571 /* Check whether the pfit is attached to our pipe. */
6572 if (INTEL_INFO(dev)->gen < 4) {
6573 if (crtc->pipe != PIPE_B)
6576 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6580 pipe_config->gmch_pfit.control = tmp;
6581 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6582 if (INTEL_INFO(dev)->gen < 5)
6583 pipe_config->gmch_pfit.lvds_border_bits =
6584 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6587 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6588 struct intel_crtc_config *pipe_config)
6590 struct drm_device *dev = crtc->base.dev;
6591 struct drm_i915_private *dev_priv = dev->dev_private;
6592 int pipe = pipe_config->cpu_transcoder;
6593 intel_clock_t clock;
6595 int refclk = 100000;
6597 /* In case of MIPI DPLL will not even be used */
6598 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6601 mutex_lock(&dev_priv->dpio_lock);
6602 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6603 mutex_unlock(&dev_priv->dpio_lock);
6605 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6606 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6607 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6608 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6609 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6611 vlv_clock(refclk, &clock);
6613 /* clock.dot is the fast clock */
6614 pipe_config->port_clock = clock.dot / 5;
6617 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6618 struct intel_plane_config *plane_config)
6620 struct drm_device *dev = crtc->base.dev;
6621 struct drm_i915_private *dev_priv = dev->dev_private;
6622 u32 val, base, offset;
6623 int pipe = crtc->pipe, plane = crtc->plane;
6624 int fourcc, pixel_format;
6627 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6628 if (!crtc->base.primary->fb) {
6629 DRM_DEBUG_KMS("failed to alloc fb\n");
6633 val = I915_READ(DSPCNTR(plane));
6635 if (INTEL_INFO(dev)->gen >= 4)
6636 if (val & DISPPLANE_TILED)
6637 plane_config->tiled = true;
6639 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6640 fourcc = intel_format_to_fourcc(pixel_format);
6641 crtc->base.primary->fb->pixel_format = fourcc;
6642 crtc->base.primary->fb->bits_per_pixel =
6643 drm_format_plane_cpp(fourcc, 0) * 8;
6645 if (INTEL_INFO(dev)->gen >= 4) {
6646 if (plane_config->tiled)
6647 offset = I915_READ(DSPTILEOFF(plane));
6649 offset = I915_READ(DSPLINOFF(plane));
6650 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6652 base = I915_READ(DSPADDR(plane));
6654 plane_config->base = base;
6656 val = I915_READ(PIPESRC(pipe));
6657 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6658 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6660 val = I915_READ(DSPSTRIDE(pipe));
6661 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6663 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6664 plane_config->tiled);
6666 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6669 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6670 pipe, plane, crtc->base.primary->fb->width,
6671 crtc->base.primary->fb->height,
6672 crtc->base.primary->fb->bits_per_pixel, base,
6673 crtc->base.primary->fb->pitches[0],
6674 plane_config->size);
6678 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6679 struct intel_crtc_config *pipe_config)
6681 struct drm_device *dev = crtc->base.dev;
6682 struct drm_i915_private *dev_priv = dev->dev_private;
6683 int pipe = pipe_config->cpu_transcoder;
6684 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6685 intel_clock_t clock;
6686 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6687 int refclk = 100000;
6689 mutex_lock(&dev_priv->dpio_lock);
6690 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6691 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6692 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6693 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6694 mutex_unlock(&dev_priv->dpio_lock);
6696 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6697 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6698 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6699 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6700 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6702 chv_clock(refclk, &clock);
6704 /* clock.dot is the fast clock */
6705 pipe_config->port_clock = clock.dot / 5;
6708 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6709 struct intel_crtc_config *pipe_config)
6711 struct drm_device *dev = crtc->base.dev;
6712 struct drm_i915_private *dev_priv = dev->dev_private;
6715 if (!intel_display_power_is_enabled(dev_priv,
6716 POWER_DOMAIN_PIPE(crtc->pipe)))
6719 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6720 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6722 tmp = I915_READ(PIPECONF(crtc->pipe));
6723 if (!(tmp & PIPECONF_ENABLE))
6726 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6727 switch (tmp & PIPECONF_BPC_MASK) {
6729 pipe_config->pipe_bpp = 18;
6732 pipe_config->pipe_bpp = 24;
6734 case PIPECONF_10BPC:
6735 pipe_config->pipe_bpp = 30;
6742 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6743 pipe_config->limited_color_range = true;
6745 if (INTEL_INFO(dev)->gen < 4)
6746 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6748 intel_get_pipe_timings(crtc, pipe_config);
6750 i9xx_get_pfit_config(crtc, pipe_config);
6752 if (INTEL_INFO(dev)->gen >= 4) {
6753 tmp = I915_READ(DPLL_MD(crtc->pipe));
6754 pipe_config->pixel_multiplier =
6755 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6756 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6757 pipe_config->dpll_hw_state.dpll_md = tmp;
6758 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6759 tmp = I915_READ(DPLL(crtc->pipe));
6760 pipe_config->pixel_multiplier =
6761 ((tmp & SDVO_MULTIPLIER_MASK)
6762 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6764 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6765 * port and will be fixed up in the encoder->get_config
6767 pipe_config->pixel_multiplier = 1;
6769 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6770 if (!IS_VALLEYVIEW(dev)) {
6772 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6773 * on 830. Filter it out here so that we don't
6774 * report errors due to that.
6777 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6779 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6780 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6782 /* Mask out read-only status bits. */
6783 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6784 DPLL_PORTC_READY_MASK |
6785 DPLL_PORTB_READY_MASK);
6788 if (IS_CHERRYVIEW(dev))
6789 chv_crtc_clock_get(crtc, pipe_config);
6790 else if (IS_VALLEYVIEW(dev))
6791 vlv_crtc_clock_get(crtc, pipe_config);
6793 i9xx_crtc_clock_get(crtc, pipe_config);
6798 static void ironlake_init_pch_refclk(struct drm_device *dev)
6800 struct drm_i915_private *dev_priv = dev->dev_private;
6801 struct intel_encoder *encoder;
6803 bool has_lvds = false;
6804 bool has_cpu_edp = false;
6805 bool has_panel = false;
6806 bool has_ck505 = false;
6807 bool can_ssc = false;
6809 /* We need to take the global config into account */
6810 for_each_intel_encoder(dev, encoder) {
6811 switch (encoder->type) {
6812 case INTEL_OUTPUT_LVDS:
6816 case INTEL_OUTPUT_EDP:
6818 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6826 if (HAS_PCH_IBX(dev)) {
6827 has_ck505 = dev_priv->vbt.display_clock_mode;
6828 can_ssc = has_ck505;
6834 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6835 has_panel, has_lvds, has_ck505);
6837 /* Ironlake: try to setup display ref clock before DPLL
6838 * enabling. This is only under driver's control after
6839 * PCH B stepping, previous chipset stepping should be
6840 * ignoring this setting.
6842 val = I915_READ(PCH_DREF_CONTROL);
6844 /* As we must carefully and slowly disable/enable each source in turn,
6845 * compute the final state we want first and check if we need to
6846 * make any changes at all.
6849 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6851 final |= DREF_NONSPREAD_CK505_ENABLE;
6853 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6855 final &= ~DREF_SSC_SOURCE_MASK;
6856 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6857 final &= ~DREF_SSC1_ENABLE;
6860 final |= DREF_SSC_SOURCE_ENABLE;
6862 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6863 final |= DREF_SSC1_ENABLE;
6866 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6867 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6869 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6871 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6873 final |= DREF_SSC_SOURCE_DISABLE;
6874 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6880 /* Always enable nonspread source */
6881 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6884 val |= DREF_NONSPREAD_CK505_ENABLE;
6886 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6889 val &= ~DREF_SSC_SOURCE_MASK;
6890 val |= DREF_SSC_SOURCE_ENABLE;
6892 /* SSC must be turned on before enabling the CPU output */
6893 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6894 DRM_DEBUG_KMS("Using SSC on panel\n");
6895 val |= DREF_SSC1_ENABLE;
6897 val &= ~DREF_SSC1_ENABLE;
6899 /* Get SSC going before enabling the outputs */
6900 I915_WRITE(PCH_DREF_CONTROL, val);
6901 POSTING_READ(PCH_DREF_CONTROL);
6904 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6906 /* Enable CPU source on CPU attached eDP */
6908 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6909 DRM_DEBUG_KMS("Using SSC on eDP\n");
6910 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6912 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6914 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6916 I915_WRITE(PCH_DREF_CONTROL, val);
6917 POSTING_READ(PCH_DREF_CONTROL);
6920 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6922 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6924 /* Turn off CPU output */
6925 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6927 I915_WRITE(PCH_DREF_CONTROL, val);
6928 POSTING_READ(PCH_DREF_CONTROL);
6931 /* Turn off the SSC source */
6932 val &= ~DREF_SSC_SOURCE_MASK;
6933 val |= DREF_SSC_SOURCE_DISABLE;
6936 val &= ~DREF_SSC1_ENABLE;
6938 I915_WRITE(PCH_DREF_CONTROL, val);
6939 POSTING_READ(PCH_DREF_CONTROL);
6943 BUG_ON(val != final);
6946 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6950 tmp = I915_READ(SOUTH_CHICKEN2);
6951 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6952 I915_WRITE(SOUTH_CHICKEN2, tmp);
6954 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6955 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6956 DRM_ERROR("FDI mPHY reset assert timeout\n");
6958 tmp = I915_READ(SOUTH_CHICKEN2);
6959 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6960 I915_WRITE(SOUTH_CHICKEN2, tmp);
6962 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6963 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6964 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6967 /* WaMPhyProgramming:hsw */
6968 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6972 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6973 tmp &= ~(0xFF << 24);
6974 tmp |= (0x12 << 24);
6975 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6977 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6979 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6981 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6983 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6985 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6986 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6987 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6989 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6990 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6991 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6993 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6996 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6998 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7001 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7003 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7006 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7008 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7011 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7013 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7014 tmp &= ~(0xFF << 16);
7015 tmp |= (0x1C << 16);
7016 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7018 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7019 tmp &= ~(0xFF << 16);
7020 tmp |= (0x1C << 16);
7021 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7023 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7025 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7027 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7029 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7031 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7032 tmp &= ~(0xF << 28);
7034 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7036 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7037 tmp &= ~(0xF << 28);
7039 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7042 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7043 * Programming" based on the parameters passed:
7044 * - Sequence to enable CLKOUT_DP
7045 * - Sequence to enable CLKOUT_DP without spread
7046 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7048 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7051 struct drm_i915_private *dev_priv = dev->dev_private;
7054 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7056 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7057 with_fdi, "LP PCH doesn't have FDI\n"))
7060 mutex_lock(&dev_priv->dpio_lock);
7062 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7063 tmp &= ~SBI_SSCCTL_DISABLE;
7064 tmp |= SBI_SSCCTL_PATHALT;
7065 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7070 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7071 tmp &= ~SBI_SSCCTL_PATHALT;
7072 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7075 lpt_reset_fdi_mphy(dev_priv);
7076 lpt_program_fdi_mphy(dev_priv);
7080 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7081 SBI_GEN0 : SBI_DBUFF0;
7082 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7083 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7084 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7086 mutex_unlock(&dev_priv->dpio_lock);
7089 /* Sequence to disable CLKOUT_DP */
7090 static void lpt_disable_clkout_dp(struct drm_device *dev)
7092 struct drm_i915_private *dev_priv = dev->dev_private;
7095 mutex_lock(&dev_priv->dpio_lock);
7097 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7098 SBI_GEN0 : SBI_DBUFF0;
7099 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7100 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7101 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7103 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7104 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7105 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7106 tmp |= SBI_SSCCTL_PATHALT;
7107 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7110 tmp |= SBI_SSCCTL_DISABLE;
7111 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7114 mutex_unlock(&dev_priv->dpio_lock);
7117 static void lpt_init_pch_refclk(struct drm_device *dev)
7119 struct intel_encoder *encoder;
7120 bool has_vga = false;
7122 for_each_intel_encoder(dev, encoder) {
7123 switch (encoder->type) {
7124 case INTEL_OUTPUT_ANALOG:
7133 lpt_enable_clkout_dp(dev, true, true);
7135 lpt_disable_clkout_dp(dev);
7139 * Initialize reference clocks when the driver loads
7141 void intel_init_pch_refclk(struct drm_device *dev)
7143 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7144 ironlake_init_pch_refclk(dev);
7145 else if (HAS_PCH_LPT(dev))
7146 lpt_init_pch_refclk(dev);
7149 static int ironlake_get_refclk(struct drm_crtc *crtc)
7151 struct drm_device *dev = crtc->dev;
7152 struct drm_i915_private *dev_priv = dev->dev_private;
7153 struct intel_encoder *encoder;
7154 int num_connectors = 0;
7155 bool is_lvds = false;
7157 for_each_intel_encoder(dev, encoder) {
7158 if (encoder->new_crtc != to_intel_crtc(crtc))
7161 switch (encoder->type) {
7162 case INTEL_OUTPUT_LVDS:
7171 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7172 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7173 dev_priv->vbt.lvds_ssc_freq);
7174 return dev_priv->vbt.lvds_ssc_freq;
7180 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7182 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7184 int pipe = intel_crtc->pipe;
7189 switch (intel_crtc->config.pipe_bpp) {
7191 val |= PIPECONF_6BPC;
7194 val |= PIPECONF_8BPC;
7197 val |= PIPECONF_10BPC;
7200 val |= PIPECONF_12BPC;
7203 /* Case prevented by intel_choose_pipe_bpp_dither. */
7207 if (intel_crtc->config.dither)
7208 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7210 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7211 val |= PIPECONF_INTERLACED_ILK;
7213 val |= PIPECONF_PROGRESSIVE;
7215 if (intel_crtc->config.limited_color_range)
7216 val |= PIPECONF_COLOR_RANGE_SELECT;
7218 I915_WRITE(PIPECONF(pipe), val);
7219 POSTING_READ(PIPECONF(pipe));
7223 * Set up the pipe CSC unit.
7225 * Currently only full range RGB to limited range RGB conversion
7226 * is supported, but eventually this should handle various
7227 * RGB<->YCbCr scenarios as well.
7229 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7231 struct drm_device *dev = crtc->dev;
7232 struct drm_i915_private *dev_priv = dev->dev_private;
7233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7234 int pipe = intel_crtc->pipe;
7235 uint16_t coeff = 0x7800; /* 1.0 */
7238 * TODO: Check what kind of values actually come out of the pipe
7239 * with these coeff/postoff values and adjust to get the best
7240 * accuracy. Perhaps we even need to take the bpc value into
7244 if (intel_crtc->config.limited_color_range)
7245 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7248 * GY/GU and RY/RU should be the other way around according
7249 * to BSpec, but reality doesn't agree. Just set them up in
7250 * a way that results in the correct picture.
7252 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7253 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7255 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7256 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7258 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7259 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7261 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7262 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7263 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7265 if (INTEL_INFO(dev)->gen > 6) {
7266 uint16_t postoff = 0;
7268 if (intel_crtc->config.limited_color_range)
7269 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7271 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7272 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7273 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7275 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7277 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7279 if (intel_crtc->config.limited_color_range)
7280 mode |= CSC_BLACK_SCREEN_OFFSET;
7282 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7286 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7288 struct drm_device *dev = crtc->dev;
7289 struct drm_i915_private *dev_priv = dev->dev_private;
7290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7291 enum pipe pipe = intel_crtc->pipe;
7292 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7297 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7298 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7300 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7301 val |= PIPECONF_INTERLACED_ILK;
7303 val |= PIPECONF_PROGRESSIVE;
7305 I915_WRITE(PIPECONF(cpu_transcoder), val);
7306 POSTING_READ(PIPECONF(cpu_transcoder));
7308 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7309 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7311 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7314 switch (intel_crtc->config.pipe_bpp) {
7316 val |= PIPEMISC_DITHER_6_BPC;
7319 val |= PIPEMISC_DITHER_8_BPC;
7322 val |= PIPEMISC_DITHER_10_BPC;
7325 val |= PIPEMISC_DITHER_12_BPC;
7328 /* Case prevented by pipe_config_set_bpp. */
7332 if (intel_crtc->config.dither)
7333 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7335 I915_WRITE(PIPEMISC(pipe), val);
7339 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7340 intel_clock_t *clock,
7341 bool *has_reduced_clock,
7342 intel_clock_t *reduced_clock)
7344 struct drm_device *dev = crtc->dev;
7345 struct drm_i915_private *dev_priv = dev->dev_private;
7346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7348 const intel_limit_t *limit;
7349 bool ret, is_lvds = false;
7351 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7353 refclk = ironlake_get_refclk(crtc);
7356 * Returns a set of divisors for the desired target clock with the given
7357 * refclk, or FALSE. The returned values represent the clock equation:
7358 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7360 limit = intel_limit(intel_crtc, refclk);
7361 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7362 intel_crtc->new_config->port_clock,
7363 refclk, NULL, clock);
7367 if (is_lvds && dev_priv->lvds_downclock_avail) {
7369 * Ensure we match the reduced clock's P to the target clock.
7370 * If the clocks don't match, we can't switch the display clock
7371 * by using the FP0/FP1. In such case we will disable the LVDS
7372 * downclock feature.
7374 *has_reduced_clock =
7375 dev_priv->display.find_dpll(limit, intel_crtc,
7376 dev_priv->lvds_downclock,
7384 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7387 * Account for spread spectrum to avoid
7388 * oversubscribing the link. Max center spread
7389 * is 2.5%; use 5% for safety's sake.
7391 u32 bps = target_clock * bpp * 21 / 20;
7392 return DIV_ROUND_UP(bps, link_bw * 8);
7395 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7397 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7400 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7402 intel_clock_t *reduced_clock, u32 *fp2)
7404 struct drm_crtc *crtc = &intel_crtc->base;
7405 struct drm_device *dev = crtc->dev;
7406 struct drm_i915_private *dev_priv = dev->dev_private;
7407 struct intel_encoder *intel_encoder;
7409 int factor, num_connectors = 0;
7410 bool is_lvds = false, is_sdvo = false;
7412 for_each_intel_encoder(dev, intel_encoder) {
7413 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7416 switch (intel_encoder->type) {
7417 case INTEL_OUTPUT_LVDS:
7420 case INTEL_OUTPUT_SDVO:
7421 case INTEL_OUTPUT_HDMI:
7431 /* Enable autotuning of the PLL clock (if permissible) */
7434 if ((intel_panel_use_ssc(dev_priv) &&
7435 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7436 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7438 } else if (intel_crtc->new_config->sdvo_tv_clock)
7441 if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7444 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7450 dpll |= DPLLB_MODE_LVDS;
7452 dpll |= DPLLB_MODE_DAC_SERIAL;
7454 dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7455 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7458 dpll |= DPLL_SDVO_HIGH_SPEED;
7459 if (intel_crtc->new_config->has_dp_encoder)
7460 dpll |= DPLL_SDVO_HIGH_SPEED;
7462 /* compute bitmask from p1 value */
7463 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7465 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7467 switch (intel_crtc->new_config->dpll.p2) {
7469 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7472 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7475 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7478 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7482 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7483 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7485 dpll |= PLL_REF_INPUT_DREFCLK;
7487 return dpll | DPLL_VCO_ENABLE;
7490 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7492 struct drm_device *dev = crtc->base.dev;
7493 intel_clock_t clock, reduced_clock;
7494 u32 dpll = 0, fp = 0, fp2 = 0;
7495 bool ok, has_reduced_clock = false;
7496 bool is_lvds = false;
7497 struct intel_shared_dpll *pll;
7499 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7501 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7502 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7504 ok = ironlake_compute_clocks(&crtc->base, &clock,
7505 &has_reduced_clock, &reduced_clock);
7506 if (!ok && !crtc->new_config->clock_set) {
7507 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7510 /* Compat-code for transition, will disappear. */
7511 if (!crtc->new_config->clock_set) {
7512 crtc->new_config->dpll.n = clock.n;
7513 crtc->new_config->dpll.m1 = clock.m1;
7514 crtc->new_config->dpll.m2 = clock.m2;
7515 crtc->new_config->dpll.p1 = clock.p1;
7516 crtc->new_config->dpll.p2 = clock.p2;
7519 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7520 if (crtc->new_config->has_pch_encoder) {
7521 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7522 if (has_reduced_clock)
7523 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7525 dpll = ironlake_compute_dpll(crtc,
7526 &fp, &reduced_clock,
7527 has_reduced_clock ? &fp2 : NULL);
7529 crtc->new_config->dpll_hw_state.dpll = dpll;
7530 crtc->new_config->dpll_hw_state.fp0 = fp;
7531 if (has_reduced_clock)
7532 crtc->new_config->dpll_hw_state.fp1 = fp2;
7534 crtc->new_config->dpll_hw_state.fp1 = fp;
7536 pll = intel_get_shared_dpll(crtc);
7538 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7539 pipe_name(crtc->pipe));
7544 if (is_lvds && has_reduced_clock && i915.powersave)
7545 crtc->lowfreq_avail = true;
7547 crtc->lowfreq_avail = false;
7552 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7553 struct intel_link_m_n *m_n)
7555 struct drm_device *dev = crtc->base.dev;
7556 struct drm_i915_private *dev_priv = dev->dev_private;
7557 enum pipe pipe = crtc->pipe;
7559 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7560 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7561 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7563 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7564 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7565 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7568 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7569 enum transcoder transcoder,
7570 struct intel_link_m_n *m_n,
7571 struct intel_link_m_n *m2_n2)
7573 struct drm_device *dev = crtc->base.dev;
7574 struct drm_i915_private *dev_priv = dev->dev_private;
7575 enum pipe pipe = crtc->pipe;
7577 if (INTEL_INFO(dev)->gen >= 5) {
7578 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7579 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7580 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7582 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7583 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7584 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7585 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7586 * gen < 8) and if DRRS is supported (to make sure the
7587 * registers are not unnecessarily read).
7589 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7590 crtc->config.has_drrs) {
7591 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7592 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7593 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7595 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7596 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7597 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7600 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7601 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7602 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7604 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7605 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7606 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7610 void intel_dp_get_m_n(struct intel_crtc *crtc,
7611 struct intel_crtc_config *pipe_config)
7613 if (crtc->config.has_pch_encoder)
7614 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7616 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7617 &pipe_config->dp_m_n,
7618 &pipe_config->dp_m2_n2);
7621 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7622 struct intel_crtc_config *pipe_config)
7624 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7625 &pipe_config->fdi_m_n, NULL);
7628 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7629 struct intel_crtc_config *pipe_config)
7631 struct drm_device *dev = crtc->base.dev;
7632 struct drm_i915_private *dev_priv = dev->dev_private;
7635 tmp = I915_READ(PS_CTL(crtc->pipe));
7637 if (tmp & PS_ENABLE) {
7638 pipe_config->pch_pfit.enabled = true;
7639 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7640 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7644 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7645 struct intel_crtc_config *pipe_config)
7647 struct drm_device *dev = crtc->base.dev;
7648 struct drm_i915_private *dev_priv = dev->dev_private;
7651 tmp = I915_READ(PF_CTL(crtc->pipe));
7653 if (tmp & PF_ENABLE) {
7654 pipe_config->pch_pfit.enabled = true;
7655 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7656 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7658 /* We currently do not free assignements of panel fitters on
7659 * ivb/hsw (since we don't use the higher upscaling modes which
7660 * differentiates them) so just WARN about this case for now. */
7662 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7663 PF_PIPE_SEL_IVB(crtc->pipe));
7668 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7669 struct intel_plane_config *plane_config)
7671 struct drm_device *dev = crtc->base.dev;
7672 struct drm_i915_private *dev_priv = dev->dev_private;
7673 u32 val, base, offset;
7674 int pipe = crtc->pipe, plane = crtc->plane;
7675 int fourcc, pixel_format;
7678 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7679 if (!crtc->base.primary->fb) {
7680 DRM_DEBUG_KMS("failed to alloc fb\n");
7684 val = I915_READ(DSPCNTR(plane));
7686 if (INTEL_INFO(dev)->gen >= 4)
7687 if (val & DISPPLANE_TILED)
7688 plane_config->tiled = true;
7690 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7691 fourcc = intel_format_to_fourcc(pixel_format);
7692 crtc->base.primary->fb->pixel_format = fourcc;
7693 crtc->base.primary->fb->bits_per_pixel =
7694 drm_format_plane_cpp(fourcc, 0) * 8;
7696 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7697 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7698 offset = I915_READ(DSPOFFSET(plane));
7700 if (plane_config->tiled)
7701 offset = I915_READ(DSPTILEOFF(plane));
7703 offset = I915_READ(DSPLINOFF(plane));
7705 plane_config->base = base;
7707 val = I915_READ(PIPESRC(pipe));
7708 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7709 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7711 val = I915_READ(DSPSTRIDE(pipe));
7712 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7714 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7715 plane_config->tiled);
7717 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7720 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7721 pipe, plane, crtc->base.primary->fb->width,
7722 crtc->base.primary->fb->height,
7723 crtc->base.primary->fb->bits_per_pixel, base,
7724 crtc->base.primary->fb->pitches[0],
7725 plane_config->size);
7728 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7729 struct intel_crtc_config *pipe_config)
7731 struct drm_device *dev = crtc->base.dev;
7732 struct drm_i915_private *dev_priv = dev->dev_private;
7735 if (!intel_display_power_is_enabled(dev_priv,
7736 POWER_DOMAIN_PIPE(crtc->pipe)))
7739 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7740 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7742 tmp = I915_READ(PIPECONF(crtc->pipe));
7743 if (!(tmp & PIPECONF_ENABLE))
7746 switch (tmp & PIPECONF_BPC_MASK) {
7748 pipe_config->pipe_bpp = 18;
7751 pipe_config->pipe_bpp = 24;
7753 case PIPECONF_10BPC:
7754 pipe_config->pipe_bpp = 30;
7756 case PIPECONF_12BPC:
7757 pipe_config->pipe_bpp = 36;
7763 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7764 pipe_config->limited_color_range = true;
7766 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7767 struct intel_shared_dpll *pll;
7769 pipe_config->has_pch_encoder = true;
7771 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7772 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7773 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7775 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7777 if (HAS_PCH_IBX(dev_priv->dev)) {
7778 pipe_config->shared_dpll =
7779 (enum intel_dpll_id) crtc->pipe;
7781 tmp = I915_READ(PCH_DPLL_SEL);
7782 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7783 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7785 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7788 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7790 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7791 &pipe_config->dpll_hw_state));
7793 tmp = pipe_config->dpll_hw_state.dpll;
7794 pipe_config->pixel_multiplier =
7795 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7796 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7798 ironlake_pch_clock_get(crtc, pipe_config);
7800 pipe_config->pixel_multiplier = 1;
7803 intel_get_pipe_timings(crtc, pipe_config);
7805 ironlake_get_pfit_config(crtc, pipe_config);
7810 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7812 struct drm_device *dev = dev_priv->dev;
7813 struct intel_crtc *crtc;
7815 for_each_intel_crtc(dev, crtc)
7816 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7817 pipe_name(crtc->pipe));
7819 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7820 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7821 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7822 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7823 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7824 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7825 "CPU PWM1 enabled\n");
7826 if (IS_HASWELL(dev))
7827 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7828 "CPU PWM2 enabled\n");
7829 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7830 "PCH PWM1 enabled\n");
7831 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7832 "Utility pin enabled\n");
7833 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7836 * In theory we can still leave IRQs enabled, as long as only the HPD
7837 * interrupts remain enabled. We used to check for that, but since it's
7838 * gen-specific and since we only disable LCPLL after we fully disable
7839 * the interrupts, the check below should be enough.
7841 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7844 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7846 struct drm_device *dev = dev_priv->dev;
7848 if (IS_HASWELL(dev))
7849 return I915_READ(D_COMP_HSW);
7851 return I915_READ(D_COMP_BDW);
7854 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7856 struct drm_device *dev = dev_priv->dev;
7858 if (IS_HASWELL(dev)) {
7859 mutex_lock(&dev_priv->rps.hw_lock);
7860 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7862 DRM_ERROR("Failed to write to D_COMP\n");
7863 mutex_unlock(&dev_priv->rps.hw_lock);
7865 I915_WRITE(D_COMP_BDW, val);
7866 POSTING_READ(D_COMP_BDW);
7871 * This function implements pieces of two sequences from BSpec:
7872 * - Sequence for display software to disable LCPLL
7873 * - Sequence for display software to allow package C8+
7874 * The steps implemented here are just the steps that actually touch the LCPLL
7875 * register. Callers should take care of disabling all the display engine
7876 * functions, doing the mode unset, fixing interrupts, etc.
7878 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7879 bool switch_to_fclk, bool allow_power_down)
7883 assert_can_disable_lcpll(dev_priv);
7885 val = I915_READ(LCPLL_CTL);
7887 if (switch_to_fclk) {
7888 val |= LCPLL_CD_SOURCE_FCLK;
7889 I915_WRITE(LCPLL_CTL, val);
7891 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7892 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7893 DRM_ERROR("Switching to FCLK failed\n");
7895 val = I915_READ(LCPLL_CTL);
7898 val |= LCPLL_PLL_DISABLE;
7899 I915_WRITE(LCPLL_CTL, val);
7900 POSTING_READ(LCPLL_CTL);
7902 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7903 DRM_ERROR("LCPLL still locked\n");
7905 val = hsw_read_dcomp(dev_priv);
7906 val |= D_COMP_COMP_DISABLE;
7907 hsw_write_dcomp(dev_priv, val);
7910 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7912 DRM_ERROR("D_COMP RCOMP still in progress\n");
7914 if (allow_power_down) {
7915 val = I915_READ(LCPLL_CTL);
7916 val |= LCPLL_POWER_DOWN_ALLOW;
7917 I915_WRITE(LCPLL_CTL, val);
7918 POSTING_READ(LCPLL_CTL);
7923 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7926 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7930 val = I915_READ(LCPLL_CTL);
7932 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7933 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7937 * Make sure we're not on PC8 state before disabling PC8, otherwise
7938 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7940 * The other problem is that hsw_restore_lcpll() is called as part of
7941 * the runtime PM resume sequence, so we can't just call
7942 * gen6_gt_force_wake_get() because that function calls
7943 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7944 * while we are on the resume sequence. So to solve this problem we have
7945 * to call special forcewake code that doesn't touch runtime PM and
7946 * doesn't enable the forcewake delayed work.
7948 spin_lock_irq(&dev_priv->uncore.lock);
7949 if (dev_priv->uncore.forcewake_count++ == 0)
7950 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7951 spin_unlock_irq(&dev_priv->uncore.lock);
7953 if (val & LCPLL_POWER_DOWN_ALLOW) {
7954 val &= ~LCPLL_POWER_DOWN_ALLOW;
7955 I915_WRITE(LCPLL_CTL, val);
7956 POSTING_READ(LCPLL_CTL);
7959 val = hsw_read_dcomp(dev_priv);
7960 val |= D_COMP_COMP_FORCE;
7961 val &= ~D_COMP_COMP_DISABLE;
7962 hsw_write_dcomp(dev_priv, val);
7964 val = I915_READ(LCPLL_CTL);
7965 val &= ~LCPLL_PLL_DISABLE;
7966 I915_WRITE(LCPLL_CTL, val);
7968 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7969 DRM_ERROR("LCPLL not locked yet\n");
7971 if (val & LCPLL_CD_SOURCE_FCLK) {
7972 val = I915_READ(LCPLL_CTL);
7973 val &= ~LCPLL_CD_SOURCE_FCLK;
7974 I915_WRITE(LCPLL_CTL, val);
7976 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7977 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7978 DRM_ERROR("Switching back to LCPLL failed\n");
7981 /* See the big comment above. */
7982 spin_lock_irq(&dev_priv->uncore.lock);
7983 if (--dev_priv->uncore.forcewake_count == 0)
7984 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7985 spin_unlock_irq(&dev_priv->uncore.lock);
7989 * Package states C8 and deeper are really deep PC states that can only be
7990 * reached when all the devices on the system allow it, so even if the graphics
7991 * device allows PC8+, it doesn't mean the system will actually get to these
7992 * states. Our driver only allows PC8+ when going into runtime PM.
7994 * The requirements for PC8+ are that all the outputs are disabled, the power
7995 * well is disabled and most interrupts are disabled, and these are also
7996 * requirements for runtime PM. When these conditions are met, we manually do
7997 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7998 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8001 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8002 * the state of some registers, so when we come back from PC8+ we need to
8003 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8004 * need to take care of the registers kept by RC6. Notice that this happens even
8005 * if we don't put the device in PCI D3 state (which is what currently happens
8006 * because of the runtime PM support).
8008 * For more, read "Display Sequences for Package C8" on the hardware
8011 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8013 struct drm_device *dev = dev_priv->dev;
8016 DRM_DEBUG_KMS("Enabling package C8+\n");
8018 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8019 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8020 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8021 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8024 lpt_disable_clkout_dp(dev);
8025 hsw_disable_lcpll(dev_priv, true, true);
8028 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8030 struct drm_device *dev = dev_priv->dev;
8033 DRM_DEBUG_KMS("Disabling package C8+\n");
8035 hsw_restore_lcpll(dev_priv);
8036 lpt_init_pch_refclk(dev);
8038 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8039 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8040 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8041 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8044 intel_prepare_ddi(dev);
8047 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
8049 if (!intel_ddi_pll_select(crtc))
8052 crtc->lowfreq_avail = false;
8057 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8059 struct intel_crtc_config *pipe_config)
8061 u32 temp, dpll_ctl1;
8063 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8064 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8066 switch (pipe_config->ddi_pll_sel) {
8069 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8070 * of the shared DPLL framework and thus needs to be read out
8073 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8074 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8077 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8080 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8083 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8088 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8090 struct intel_crtc_config *pipe_config)
8092 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8094 switch (pipe_config->ddi_pll_sel) {
8095 case PORT_CLK_SEL_WRPLL1:
8096 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8098 case PORT_CLK_SEL_WRPLL2:
8099 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8104 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8105 struct intel_crtc_config *pipe_config)
8107 struct drm_device *dev = crtc->base.dev;
8108 struct drm_i915_private *dev_priv = dev->dev_private;
8109 struct intel_shared_dpll *pll;
8113 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8115 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8117 if (IS_SKYLAKE(dev))
8118 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8120 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8122 if (pipe_config->shared_dpll >= 0) {
8123 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8125 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8126 &pipe_config->dpll_hw_state));
8130 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8131 * DDI E. So just check whether this pipe is wired to DDI E and whether
8132 * the PCH transcoder is on.
8134 if (INTEL_INFO(dev)->gen < 9 &&
8135 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8136 pipe_config->has_pch_encoder = true;
8138 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8139 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8140 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8142 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8146 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8147 struct intel_crtc_config *pipe_config)
8149 struct drm_device *dev = crtc->base.dev;
8150 struct drm_i915_private *dev_priv = dev->dev_private;
8151 enum intel_display_power_domain pfit_domain;
8154 if (!intel_display_power_is_enabled(dev_priv,
8155 POWER_DOMAIN_PIPE(crtc->pipe)))
8158 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8159 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8161 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8162 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8163 enum pipe trans_edp_pipe;
8164 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8166 WARN(1, "unknown pipe linked to edp transcoder\n");
8167 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8168 case TRANS_DDI_EDP_INPUT_A_ON:
8169 trans_edp_pipe = PIPE_A;
8171 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8172 trans_edp_pipe = PIPE_B;
8174 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8175 trans_edp_pipe = PIPE_C;
8179 if (trans_edp_pipe == crtc->pipe)
8180 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8183 if (!intel_display_power_is_enabled(dev_priv,
8184 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8187 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8188 if (!(tmp & PIPECONF_ENABLE))
8191 haswell_get_ddi_port_state(crtc, pipe_config);
8193 intel_get_pipe_timings(crtc, pipe_config);
8195 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8196 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8197 if (IS_SKYLAKE(dev))
8198 skylake_get_pfit_config(crtc, pipe_config);
8200 ironlake_get_pfit_config(crtc, pipe_config);
8203 if (IS_HASWELL(dev))
8204 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8205 (I915_READ(IPS_CTL) & IPS_ENABLE);
8207 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8208 pipe_config->pixel_multiplier =
8209 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8211 pipe_config->pixel_multiplier = 1;
8217 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8219 struct drm_device *dev = crtc->dev;
8220 struct drm_i915_private *dev_priv = dev->dev_private;
8221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8222 uint32_t cntl = 0, size = 0;
8225 unsigned int width = intel_crtc->cursor_width;
8226 unsigned int height = intel_crtc->cursor_height;
8227 unsigned int stride = roundup_pow_of_two(width) * 4;
8231 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8242 cntl |= CURSOR_ENABLE |
8243 CURSOR_GAMMA_ENABLE |
8244 CURSOR_FORMAT_ARGB |
8245 CURSOR_STRIDE(stride);
8247 size = (height << 12) | width;
8250 if (intel_crtc->cursor_cntl != 0 &&
8251 (intel_crtc->cursor_base != base ||
8252 intel_crtc->cursor_size != size ||
8253 intel_crtc->cursor_cntl != cntl)) {
8254 /* On these chipsets we can only modify the base/size/stride
8255 * whilst the cursor is disabled.
8257 I915_WRITE(_CURACNTR, 0);
8258 POSTING_READ(_CURACNTR);
8259 intel_crtc->cursor_cntl = 0;
8262 if (intel_crtc->cursor_base != base) {
8263 I915_WRITE(_CURABASE, base);
8264 intel_crtc->cursor_base = base;
8267 if (intel_crtc->cursor_size != size) {
8268 I915_WRITE(CURSIZE, size);
8269 intel_crtc->cursor_size = size;
8272 if (intel_crtc->cursor_cntl != cntl) {
8273 I915_WRITE(_CURACNTR, cntl);
8274 POSTING_READ(_CURACNTR);
8275 intel_crtc->cursor_cntl = cntl;
8279 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8281 struct drm_device *dev = crtc->dev;
8282 struct drm_i915_private *dev_priv = dev->dev_private;
8283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8284 int pipe = intel_crtc->pipe;
8289 cntl = MCURSOR_GAMMA_ENABLE;
8290 switch (intel_crtc->cursor_width) {
8292 cntl |= CURSOR_MODE_64_ARGB_AX;
8295 cntl |= CURSOR_MODE_128_ARGB_AX;
8298 cntl |= CURSOR_MODE_256_ARGB_AX;
8304 cntl |= pipe << 28; /* Connect to correct pipe */
8306 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8307 cntl |= CURSOR_PIPE_CSC_ENABLE;
8310 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8311 cntl |= CURSOR_ROTATE_180;
8313 if (intel_crtc->cursor_cntl != cntl) {
8314 I915_WRITE(CURCNTR(pipe), cntl);
8315 POSTING_READ(CURCNTR(pipe));
8316 intel_crtc->cursor_cntl = cntl;
8319 /* and commit changes on next vblank */
8320 I915_WRITE(CURBASE(pipe), base);
8321 POSTING_READ(CURBASE(pipe));
8323 intel_crtc->cursor_base = base;
8326 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8327 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8330 struct drm_device *dev = crtc->dev;
8331 struct drm_i915_private *dev_priv = dev->dev_private;
8332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8333 int pipe = intel_crtc->pipe;
8334 int x = crtc->cursor_x;
8335 int y = crtc->cursor_y;
8336 u32 base = 0, pos = 0;
8339 base = intel_crtc->cursor_addr;
8341 if (x >= intel_crtc->config.pipe_src_w)
8344 if (y >= intel_crtc->config.pipe_src_h)
8348 if (x + intel_crtc->cursor_width <= 0)
8351 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8354 pos |= x << CURSOR_X_SHIFT;
8357 if (y + intel_crtc->cursor_height <= 0)
8360 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8363 pos |= y << CURSOR_Y_SHIFT;
8365 if (base == 0 && intel_crtc->cursor_base == 0)
8368 I915_WRITE(CURPOS(pipe), pos);
8370 /* ILK+ do this automagically */
8371 if (HAS_GMCH_DISPLAY(dev) &&
8372 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8373 base += (intel_crtc->cursor_height *
8374 intel_crtc->cursor_width - 1) * 4;
8377 if (IS_845G(dev) || IS_I865G(dev))
8378 i845_update_cursor(crtc, base);
8380 i9xx_update_cursor(crtc, base);
8383 static bool cursor_size_ok(struct drm_device *dev,
8384 uint32_t width, uint32_t height)
8386 if (width == 0 || height == 0)
8390 * 845g/865g are special in that they are only limited by
8391 * the width of their cursors, the height is arbitrary up to
8392 * the precision of the register. Everything else requires
8393 * square cursors, limited to a few power-of-two sizes.
8395 if (IS_845G(dev) || IS_I865G(dev)) {
8396 if ((width & 63) != 0)
8399 if (width > (IS_845G(dev) ? 64 : 512))
8405 switch (width | height) {
8420 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8421 struct drm_i915_gem_object *obj,
8422 uint32_t width, uint32_t height)
8424 struct drm_device *dev = crtc->dev;
8425 struct drm_i915_private *dev_priv = to_i915(dev);
8426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8427 enum pipe pipe = intel_crtc->pipe;
8432 /* if we want to turn off the cursor ignore width and height */
8434 DRM_DEBUG_KMS("cursor off\n");
8436 mutex_lock(&dev->struct_mutex);
8440 /* we only need to pin inside GTT if cursor is non-phy */
8441 mutex_lock(&dev->struct_mutex);
8442 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8446 * Global gtt pte registers are special registers which actually
8447 * forward writes to a chunk of system memory. Which means that
8448 * there is no risk that the register values disappear as soon
8449 * as we call intel_runtime_pm_put(), so it is correct to wrap
8450 * only the pin/unpin/fence and not more.
8452 intel_runtime_pm_get(dev_priv);
8454 /* Note that the w/a also requires 2 PTE of padding following
8455 * the bo. We currently fill all unused PTE with the shadow
8456 * page and so we should always have valid PTE following the
8457 * cursor preventing the VT-d warning.
8460 if (need_vtd_wa(dev))
8461 alignment = 64*1024;
8463 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8465 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8466 intel_runtime_pm_put(dev_priv);
8470 ret = i915_gem_object_put_fence(obj);
8472 DRM_DEBUG_KMS("failed to release fence for cursor");
8473 intel_runtime_pm_put(dev_priv);
8477 addr = i915_gem_obj_ggtt_offset(obj);
8479 intel_runtime_pm_put(dev_priv);
8481 int align = IS_I830(dev) ? 16 * 1024 : 256;
8482 ret = i915_gem_object_attach_phys(obj, align);
8484 DRM_DEBUG_KMS("failed to attach phys object\n");
8487 addr = obj->phys_handle->busaddr;
8491 if (intel_crtc->cursor_bo) {
8492 if (!INTEL_INFO(dev)->cursor_needs_physical)
8493 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8496 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8497 INTEL_FRONTBUFFER_CURSOR(pipe));
8498 mutex_unlock(&dev->struct_mutex);
8500 old_width = intel_crtc->cursor_width;
8502 intel_crtc->cursor_addr = addr;
8503 intel_crtc->cursor_bo = obj;
8504 intel_crtc->cursor_width = width;
8505 intel_crtc->cursor_height = height;
8507 if (intel_crtc->active) {
8508 if (old_width != width)
8509 intel_update_watermarks(crtc);
8510 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8512 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8517 i915_gem_object_unpin_from_display_plane(obj);
8519 mutex_unlock(&dev->struct_mutex);
8523 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8524 u16 *blue, uint32_t start, uint32_t size)
8526 int end = (start + size > 256) ? 256 : start + size, i;
8527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8529 for (i = start; i < end; i++) {
8530 intel_crtc->lut_r[i] = red[i] >> 8;
8531 intel_crtc->lut_g[i] = green[i] >> 8;
8532 intel_crtc->lut_b[i] = blue[i] >> 8;
8535 intel_crtc_load_lut(crtc);
8538 /* VESA 640x480x72Hz mode to set on the pipe */
8539 static struct drm_display_mode load_detect_mode = {
8540 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8541 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8544 struct drm_framebuffer *
8545 __intel_framebuffer_create(struct drm_device *dev,
8546 struct drm_mode_fb_cmd2 *mode_cmd,
8547 struct drm_i915_gem_object *obj)
8549 struct intel_framebuffer *intel_fb;
8552 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8554 drm_gem_object_unreference(&obj->base);
8555 return ERR_PTR(-ENOMEM);
8558 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8562 return &intel_fb->base;
8564 drm_gem_object_unreference(&obj->base);
8567 return ERR_PTR(ret);
8570 static struct drm_framebuffer *
8571 intel_framebuffer_create(struct drm_device *dev,
8572 struct drm_mode_fb_cmd2 *mode_cmd,
8573 struct drm_i915_gem_object *obj)
8575 struct drm_framebuffer *fb;
8578 ret = i915_mutex_lock_interruptible(dev);
8580 return ERR_PTR(ret);
8581 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8582 mutex_unlock(&dev->struct_mutex);
8588 intel_framebuffer_pitch_for_width(int width, int bpp)
8590 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8591 return ALIGN(pitch, 64);
8595 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8597 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8598 return PAGE_ALIGN(pitch * mode->vdisplay);
8601 static struct drm_framebuffer *
8602 intel_framebuffer_create_for_mode(struct drm_device *dev,
8603 struct drm_display_mode *mode,
8606 struct drm_i915_gem_object *obj;
8607 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8609 obj = i915_gem_alloc_object(dev,
8610 intel_framebuffer_size_for_mode(mode, bpp));
8612 return ERR_PTR(-ENOMEM);
8614 mode_cmd.width = mode->hdisplay;
8615 mode_cmd.height = mode->vdisplay;
8616 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8618 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8620 return intel_framebuffer_create(dev, &mode_cmd, obj);
8623 static struct drm_framebuffer *
8624 mode_fits_in_fbdev(struct drm_device *dev,
8625 struct drm_display_mode *mode)
8627 #ifdef CONFIG_DRM_I915_FBDEV
8628 struct drm_i915_private *dev_priv = dev->dev_private;
8629 struct drm_i915_gem_object *obj;
8630 struct drm_framebuffer *fb;
8632 if (!dev_priv->fbdev)
8635 if (!dev_priv->fbdev->fb)
8638 obj = dev_priv->fbdev->fb->obj;
8641 fb = &dev_priv->fbdev->fb->base;
8642 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8643 fb->bits_per_pixel))
8646 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8655 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8656 struct drm_display_mode *mode,
8657 struct intel_load_detect_pipe *old,
8658 struct drm_modeset_acquire_ctx *ctx)
8660 struct intel_crtc *intel_crtc;
8661 struct intel_encoder *intel_encoder =
8662 intel_attached_encoder(connector);
8663 struct drm_crtc *possible_crtc;
8664 struct drm_encoder *encoder = &intel_encoder->base;
8665 struct drm_crtc *crtc = NULL;
8666 struct drm_device *dev = encoder->dev;
8667 struct drm_framebuffer *fb;
8668 struct drm_mode_config *config = &dev->mode_config;
8671 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8672 connector->base.id, connector->name,
8673 encoder->base.id, encoder->name);
8676 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8681 * Algorithm gets a little messy:
8683 * - if the connector already has an assigned crtc, use it (but make
8684 * sure it's on first)
8686 * - try to find the first unused crtc that can drive this connector,
8687 * and use that if we find one
8690 /* See if we already have a CRTC for this connector */
8691 if (encoder->crtc) {
8692 crtc = encoder->crtc;
8694 ret = drm_modeset_lock(&crtc->mutex, ctx);
8697 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8701 old->dpms_mode = connector->dpms;
8702 old->load_detect_temp = false;
8704 /* Make sure the crtc and connector are running */
8705 if (connector->dpms != DRM_MODE_DPMS_ON)
8706 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8711 /* Find an unused one (if possible) */
8712 for_each_crtc(dev, possible_crtc) {
8714 if (!(encoder->possible_crtcs & (1 << i)))
8716 if (possible_crtc->enabled)
8718 /* This can occur when applying the pipe A quirk on resume. */
8719 if (to_intel_crtc(possible_crtc)->new_enabled)
8722 crtc = possible_crtc;
8727 * If we didn't find an unused CRTC, don't use any.
8730 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8734 ret = drm_modeset_lock(&crtc->mutex, ctx);
8737 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8740 intel_encoder->new_crtc = to_intel_crtc(crtc);
8741 to_intel_connector(connector)->new_encoder = intel_encoder;
8743 intel_crtc = to_intel_crtc(crtc);
8744 intel_crtc->new_enabled = true;
8745 intel_crtc->new_config = &intel_crtc->config;
8746 old->dpms_mode = connector->dpms;
8747 old->load_detect_temp = true;
8748 old->release_fb = NULL;
8751 mode = &load_detect_mode;
8753 /* We need a framebuffer large enough to accommodate all accesses
8754 * that the plane may generate whilst we perform load detection.
8755 * We can not rely on the fbcon either being present (we get called
8756 * during its initialisation to detect all boot displays, or it may
8757 * not even exist) or that it is large enough to satisfy the
8760 fb = mode_fits_in_fbdev(dev, mode);
8762 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8763 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8764 old->release_fb = fb;
8766 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8768 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8772 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8773 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8774 if (old->release_fb)
8775 old->release_fb->funcs->destroy(old->release_fb);
8779 /* let the connector get through one full cycle before testing */
8780 intel_wait_for_vblank(dev, intel_crtc->pipe);
8784 intel_crtc->new_enabled = crtc->enabled;
8785 if (intel_crtc->new_enabled)
8786 intel_crtc->new_config = &intel_crtc->config;
8788 intel_crtc->new_config = NULL;
8790 if (ret == -EDEADLK) {
8791 drm_modeset_backoff(ctx);
8798 void intel_release_load_detect_pipe(struct drm_connector *connector,
8799 struct intel_load_detect_pipe *old)
8801 struct intel_encoder *intel_encoder =
8802 intel_attached_encoder(connector);
8803 struct drm_encoder *encoder = &intel_encoder->base;
8804 struct drm_crtc *crtc = encoder->crtc;
8805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8807 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8808 connector->base.id, connector->name,
8809 encoder->base.id, encoder->name);
8811 if (old->load_detect_temp) {
8812 to_intel_connector(connector)->new_encoder = NULL;
8813 intel_encoder->new_crtc = NULL;
8814 intel_crtc->new_enabled = false;
8815 intel_crtc->new_config = NULL;
8816 intel_set_mode(crtc, NULL, 0, 0, NULL);
8818 if (old->release_fb) {
8819 drm_framebuffer_unregister_private(old->release_fb);
8820 drm_framebuffer_unreference(old->release_fb);
8826 /* Switch crtc and encoder back off if necessary */
8827 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8828 connector->funcs->dpms(connector, old->dpms_mode);
8831 static int i9xx_pll_refclk(struct drm_device *dev,
8832 const struct intel_crtc_config *pipe_config)
8834 struct drm_i915_private *dev_priv = dev->dev_private;
8835 u32 dpll = pipe_config->dpll_hw_state.dpll;
8837 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8838 return dev_priv->vbt.lvds_ssc_freq;
8839 else if (HAS_PCH_SPLIT(dev))
8841 else if (!IS_GEN2(dev))
8847 /* Returns the clock of the currently programmed mode of the given pipe. */
8848 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8849 struct intel_crtc_config *pipe_config)
8851 struct drm_device *dev = crtc->base.dev;
8852 struct drm_i915_private *dev_priv = dev->dev_private;
8853 int pipe = pipe_config->cpu_transcoder;
8854 u32 dpll = pipe_config->dpll_hw_state.dpll;
8856 intel_clock_t clock;
8857 int refclk = i9xx_pll_refclk(dev, pipe_config);
8859 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8860 fp = pipe_config->dpll_hw_state.fp0;
8862 fp = pipe_config->dpll_hw_state.fp1;
8864 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8865 if (IS_PINEVIEW(dev)) {
8866 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8867 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8869 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8870 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8873 if (!IS_GEN2(dev)) {
8874 if (IS_PINEVIEW(dev))
8875 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8876 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8878 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8879 DPLL_FPA01_P1_POST_DIV_SHIFT);
8881 switch (dpll & DPLL_MODE_MASK) {
8882 case DPLLB_MODE_DAC_SERIAL:
8883 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8886 case DPLLB_MODE_LVDS:
8887 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8891 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8892 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8896 if (IS_PINEVIEW(dev))
8897 pineview_clock(refclk, &clock);
8899 i9xx_clock(refclk, &clock);
8901 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8902 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8905 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8906 DPLL_FPA01_P1_POST_DIV_SHIFT);
8908 if (lvds & LVDS_CLKB_POWER_UP)
8913 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8916 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8917 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8919 if (dpll & PLL_P2_DIVIDE_BY_4)
8925 i9xx_clock(refclk, &clock);
8929 * This value includes pixel_multiplier. We will use
8930 * port_clock to compute adjusted_mode.crtc_clock in the
8931 * encoder's get_config() function.
8933 pipe_config->port_clock = clock.dot;
8936 int intel_dotclock_calculate(int link_freq,
8937 const struct intel_link_m_n *m_n)
8940 * The calculation for the data clock is:
8941 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8942 * But we want to avoid losing precison if possible, so:
8943 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8945 * and the link clock is simpler:
8946 * link_clock = (m * link_clock) / n
8952 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8955 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8956 struct intel_crtc_config *pipe_config)
8958 struct drm_device *dev = crtc->base.dev;
8960 /* read out port_clock from the DPLL */
8961 i9xx_crtc_clock_get(crtc, pipe_config);
8964 * This value does not include pixel_multiplier.
8965 * We will check that port_clock and adjusted_mode.crtc_clock
8966 * agree once we know their relationship in the encoder's
8967 * get_config() function.
8969 pipe_config->adjusted_mode.crtc_clock =
8970 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8971 &pipe_config->fdi_m_n);
8974 /** Returns the currently programmed mode of the given pipe. */
8975 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8976 struct drm_crtc *crtc)
8978 struct drm_i915_private *dev_priv = dev->dev_private;
8979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8980 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8981 struct drm_display_mode *mode;
8982 struct intel_crtc_config pipe_config;
8983 int htot = I915_READ(HTOTAL(cpu_transcoder));
8984 int hsync = I915_READ(HSYNC(cpu_transcoder));
8985 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8986 int vsync = I915_READ(VSYNC(cpu_transcoder));
8987 enum pipe pipe = intel_crtc->pipe;
8989 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8994 * Construct a pipe_config sufficient for getting the clock info
8995 * back out of crtc_clock_get.
8997 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8998 * to use a real value here instead.
9000 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9001 pipe_config.pixel_multiplier = 1;
9002 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9003 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9004 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9005 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9007 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9008 mode->hdisplay = (htot & 0xffff) + 1;
9009 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9010 mode->hsync_start = (hsync & 0xffff) + 1;
9011 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9012 mode->vdisplay = (vtot & 0xffff) + 1;
9013 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9014 mode->vsync_start = (vsync & 0xffff) + 1;
9015 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9017 drm_mode_set_name(mode);
9022 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9024 struct drm_device *dev = crtc->dev;
9025 struct drm_i915_private *dev_priv = dev->dev_private;
9026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9028 if (!HAS_GMCH_DISPLAY(dev))
9031 if (!dev_priv->lvds_downclock_avail)
9035 * Since this is called by a timer, we should never get here in
9038 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9039 int pipe = intel_crtc->pipe;
9040 int dpll_reg = DPLL(pipe);
9043 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9045 assert_panel_unlocked(dev_priv, pipe);
9047 dpll = I915_READ(dpll_reg);
9048 dpll |= DISPLAY_RATE_SELECT_FPA1;
9049 I915_WRITE(dpll_reg, dpll);
9050 intel_wait_for_vblank(dev, pipe);
9051 dpll = I915_READ(dpll_reg);
9052 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9053 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9058 void intel_mark_busy(struct drm_device *dev)
9060 struct drm_i915_private *dev_priv = dev->dev_private;
9062 if (dev_priv->mm.busy)
9065 intel_runtime_pm_get(dev_priv);
9066 i915_update_gfx_val(dev_priv);
9067 dev_priv->mm.busy = true;
9070 void intel_mark_idle(struct drm_device *dev)
9072 struct drm_i915_private *dev_priv = dev->dev_private;
9073 struct drm_crtc *crtc;
9075 if (!dev_priv->mm.busy)
9078 dev_priv->mm.busy = false;
9080 if (!i915.powersave)
9083 for_each_crtc(dev, crtc) {
9084 if (!crtc->primary->fb)
9087 intel_decrease_pllclock(crtc);
9090 if (INTEL_INFO(dev)->gen >= 6)
9091 gen6_rps_idle(dev->dev_private);
9094 intel_runtime_pm_put(dev_priv);
9097 static void intel_crtc_destroy(struct drm_crtc *crtc)
9099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9100 struct drm_device *dev = crtc->dev;
9101 struct intel_unpin_work *work;
9103 spin_lock_irq(&dev->event_lock);
9104 work = intel_crtc->unpin_work;
9105 intel_crtc->unpin_work = NULL;
9106 spin_unlock_irq(&dev->event_lock);
9109 cancel_work_sync(&work->work);
9113 drm_crtc_cleanup(crtc);
9118 static void intel_unpin_work_fn(struct work_struct *__work)
9120 struct intel_unpin_work *work =
9121 container_of(__work, struct intel_unpin_work, work);
9122 struct drm_device *dev = work->crtc->dev;
9123 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9125 mutex_lock(&dev->struct_mutex);
9126 intel_unpin_fb_obj(work->old_fb_obj);
9127 drm_gem_object_unreference(&work->pending_flip_obj->base);
9128 drm_gem_object_unreference(&work->old_fb_obj->base);
9130 intel_update_fbc(dev);
9131 mutex_unlock(&dev->struct_mutex);
9133 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9135 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9136 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9141 static void do_intel_finish_page_flip(struct drm_device *dev,
9142 struct drm_crtc *crtc)
9144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9145 struct intel_unpin_work *work;
9146 unsigned long flags;
9148 /* Ignore early vblank irqs */
9149 if (intel_crtc == NULL)
9153 * This is called both by irq handlers and the reset code (to complete
9154 * lost pageflips) so needs the full irqsave spinlocks.
9156 spin_lock_irqsave(&dev->event_lock, flags);
9157 work = intel_crtc->unpin_work;
9159 /* Ensure we don't miss a work->pending update ... */
9162 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9163 spin_unlock_irqrestore(&dev->event_lock, flags);
9167 page_flip_completed(intel_crtc);
9169 spin_unlock_irqrestore(&dev->event_lock, flags);
9172 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9174 struct drm_i915_private *dev_priv = dev->dev_private;
9175 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9177 do_intel_finish_page_flip(dev, crtc);
9180 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9182 struct drm_i915_private *dev_priv = dev->dev_private;
9183 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9185 do_intel_finish_page_flip(dev, crtc);
9188 /* Is 'a' after or equal to 'b'? */
9189 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9191 return !((a - b) & 0x80000000);
9194 static bool page_flip_finished(struct intel_crtc *crtc)
9196 struct drm_device *dev = crtc->base.dev;
9197 struct drm_i915_private *dev_priv = dev->dev_private;
9199 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9200 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9204 * The relevant registers doen't exist on pre-ctg.
9205 * As the flip done interrupt doesn't trigger for mmio
9206 * flips on gmch platforms, a flip count check isn't
9207 * really needed there. But since ctg has the registers,
9208 * include it in the check anyway.
9210 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9214 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9215 * used the same base address. In that case the mmio flip might
9216 * have completed, but the CS hasn't even executed the flip yet.
9218 * A flip count check isn't enough as the CS might have updated
9219 * the base address just after start of vblank, but before we
9220 * managed to process the interrupt. This means we'd complete the
9223 * Combining both checks should get us a good enough result. It may
9224 * still happen that the CS flip has been executed, but has not
9225 * yet actually completed. But in case the base address is the same
9226 * anyway, we don't really care.
9228 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9229 crtc->unpin_work->gtt_offset &&
9230 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9231 crtc->unpin_work->flip_count);
9234 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9236 struct drm_i915_private *dev_priv = dev->dev_private;
9237 struct intel_crtc *intel_crtc =
9238 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9239 unsigned long flags;
9243 * This is called both by irq handlers and the reset code (to complete
9244 * lost pageflips) so needs the full irqsave spinlocks.
9246 * NB: An MMIO update of the plane base pointer will also
9247 * generate a page-flip completion irq, i.e. every modeset
9248 * is also accompanied by a spurious intel_prepare_page_flip().
9250 spin_lock_irqsave(&dev->event_lock, flags);
9251 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9252 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9253 spin_unlock_irqrestore(&dev->event_lock, flags);
9256 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9258 /* Ensure that the work item is consistent when activating it ... */
9260 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9261 /* and that it is marked active as soon as the irq could fire. */
9265 static int intel_gen2_queue_flip(struct drm_device *dev,
9266 struct drm_crtc *crtc,
9267 struct drm_framebuffer *fb,
9268 struct drm_i915_gem_object *obj,
9269 struct intel_engine_cs *ring,
9272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9276 ret = intel_ring_begin(ring, 6);
9280 /* Can't queue multiple flips, so wait for the previous
9281 * one to finish before executing the next.
9283 if (intel_crtc->plane)
9284 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9286 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9287 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9288 intel_ring_emit(ring, MI_NOOP);
9289 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9290 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9291 intel_ring_emit(ring, fb->pitches[0]);
9292 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9293 intel_ring_emit(ring, 0); /* aux display base address, unused */
9295 intel_mark_page_flip_active(intel_crtc);
9296 __intel_ring_advance(ring);
9300 static int intel_gen3_queue_flip(struct drm_device *dev,
9301 struct drm_crtc *crtc,
9302 struct drm_framebuffer *fb,
9303 struct drm_i915_gem_object *obj,
9304 struct intel_engine_cs *ring,
9307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9311 ret = intel_ring_begin(ring, 6);
9315 if (intel_crtc->plane)
9316 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9318 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9319 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9320 intel_ring_emit(ring, MI_NOOP);
9321 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9322 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9323 intel_ring_emit(ring, fb->pitches[0]);
9324 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9325 intel_ring_emit(ring, MI_NOOP);
9327 intel_mark_page_flip_active(intel_crtc);
9328 __intel_ring_advance(ring);
9332 static int intel_gen4_queue_flip(struct drm_device *dev,
9333 struct drm_crtc *crtc,
9334 struct drm_framebuffer *fb,
9335 struct drm_i915_gem_object *obj,
9336 struct intel_engine_cs *ring,
9339 struct drm_i915_private *dev_priv = dev->dev_private;
9340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9341 uint32_t pf, pipesrc;
9344 ret = intel_ring_begin(ring, 4);
9348 /* i965+ uses the linear or tiled offsets from the
9349 * Display Registers (which do not change across a page-flip)
9350 * so we need only reprogram the base address.
9352 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9353 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9354 intel_ring_emit(ring, fb->pitches[0]);
9355 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9358 /* XXX Enabling the panel-fitter across page-flip is so far
9359 * untested on non-native modes, so ignore it for now.
9360 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9363 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9364 intel_ring_emit(ring, pf | pipesrc);
9366 intel_mark_page_flip_active(intel_crtc);
9367 __intel_ring_advance(ring);
9371 static int intel_gen6_queue_flip(struct drm_device *dev,
9372 struct drm_crtc *crtc,
9373 struct drm_framebuffer *fb,
9374 struct drm_i915_gem_object *obj,
9375 struct intel_engine_cs *ring,
9378 struct drm_i915_private *dev_priv = dev->dev_private;
9379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9380 uint32_t pf, pipesrc;
9383 ret = intel_ring_begin(ring, 4);
9387 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9388 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9389 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9390 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9392 /* Contrary to the suggestions in the documentation,
9393 * "Enable Panel Fitter" does not seem to be required when page
9394 * flipping with a non-native mode, and worse causes a normal
9396 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9399 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9400 intel_ring_emit(ring, pf | pipesrc);
9402 intel_mark_page_flip_active(intel_crtc);
9403 __intel_ring_advance(ring);
9407 static int intel_gen7_queue_flip(struct drm_device *dev,
9408 struct drm_crtc *crtc,
9409 struct drm_framebuffer *fb,
9410 struct drm_i915_gem_object *obj,
9411 struct intel_engine_cs *ring,
9414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9415 uint32_t plane_bit = 0;
9418 switch (intel_crtc->plane) {
9420 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9423 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9426 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9429 WARN_ONCE(1, "unknown plane in flip command\n");
9434 if (ring->id == RCS) {
9437 * On Gen 8, SRM is now taking an extra dword to accommodate
9438 * 48bits addresses, and we need a NOOP for the batch size to
9446 * BSpec MI_DISPLAY_FLIP for IVB:
9447 * "The full packet must be contained within the same cache line."
9449 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9450 * cacheline, if we ever start emitting more commands before
9451 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9452 * then do the cacheline alignment, and finally emit the
9455 ret = intel_ring_cacheline_align(ring);
9459 ret = intel_ring_begin(ring, len);
9463 /* Unmask the flip-done completion message. Note that the bspec says that
9464 * we should do this for both the BCS and RCS, and that we must not unmask
9465 * more than one flip event at any time (or ensure that one flip message
9466 * can be sent by waiting for flip-done prior to queueing new flips).
9467 * Experimentation says that BCS works despite DERRMR masking all
9468 * flip-done completion events and that unmasking all planes at once
9469 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9470 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9472 if (ring->id == RCS) {
9473 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9474 intel_ring_emit(ring, DERRMR);
9475 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9476 DERRMR_PIPEB_PRI_FLIP_DONE |
9477 DERRMR_PIPEC_PRI_FLIP_DONE));
9479 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9480 MI_SRM_LRM_GLOBAL_GTT);
9482 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9483 MI_SRM_LRM_GLOBAL_GTT);
9484 intel_ring_emit(ring, DERRMR);
9485 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9487 intel_ring_emit(ring, 0);
9488 intel_ring_emit(ring, MI_NOOP);
9492 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9493 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9494 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9495 intel_ring_emit(ring, (MI_NOOP));
9497 intel_mark_page_flip_active(intel_crtc);
9498 __intel_ring_advance(ring);
9502 static bool use_mmio_flip(struct intel_engine_cs *ring,
9503 struct drm_i915_gem_object *obj)
9506 * This is not being used for older platforms, because
9507 * non-availability of flip done interrupt forces us to use
9508 * CS flips. Older platforms derive flip done using some clever
9509 * tricks involving the flip_pending status bits and vblank irqs.
9510 * So using MMIO flips there would disrupt this mechanism.
9516 if (INTEL_INFO(ring->dev)->gen < 5)
9519 if (i915.use_mmio_flip < 0)
9521 else if (i915.use_mmio_flip > 0)
9523 else if (i915.enable_execlists)
9526 return ring != obj->ring;
9529 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9531 struct drm_device *dev = intel_crtc->base.dev;
9532 struct drm_i915_private *dev_priv = dev->dev_private;
9533 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9534 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9535 struct drm_i915_gem_object *obj = intel_fb->obj;
9536 const enum pipe pipe = intel_crtc->pipe;
9539 ctl = I915_READ(PLANE_CTL(pipe, 0));
9540 ctl &= ~PLANE_CTL_TILED_MASK;
9541 if (obj->tiling_mode == I915_TILING_X)
9542 ctl |= PLANE_CTL_TILED_X;
9545 * The stride is either expressed as a multiple of 64 bytes chunks for
9546 * linear buffers or in number of tiles for tiled buffers.
9548 stride = fb->pitches[0] >> 6;
9549 if (obj->tiling_mode == I915_TILING_X)
9550 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9553 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9554 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9556 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9557 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9559 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9560 POSTING_READ(PLANE_SURF(pipe, 0));
9563 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9565 struct drm_device *dev = intel_crtc->base.dev;
9566 struct drm_i915_private *dev_priv = dev->dev_private;
9567 struct intel_framebuffer *intel_fb =
9568 to_intel_framebuffer(intel_crtc->base.primary->fb);
9569 struct drm_i915_gem_object *obj = intel_fb->obj;
9573 reg = DSPCNTR(intel_crtc->plane);
9574 dspcntr = I915_READ(reg);
9576 if (obj->tiling_mode != I915_TILING_NONE)
9577 dspcntr |= DISPPLANE_TILED;
9579 dspcntr &= ~DISPPLANE_TILED;
9581 I915_WRITE(reg, dspcntr);
9583 I915_WRITE(DSPSURF(intel_crtc->plane),
9584 intel_crtc->unpin_work->gtt_offset);
9585 POSTING_READ(DSPSURF(intel_crtc->plane));
9590 * XXX: This is the temporary way to update the plane registers until we get
9591 * around to using the usual plane update functions for MMIO flips
9593 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9595 struct drm_device *dev = intel_crtc->base.dev;
9597 u32 start_vbl_count;
9599 intel_mark_page_flip_active(intel_crtc);
9601 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9603 if (INTEL_INFO(dev)->gen >= 9)
9604 skl_do_mmio_flip(intel_crtc);
9606 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9607 ilk_do_mmio_flip(intel_crtc);
9610 intel_pipe_update_end(intel_crtc, start_vbl_count);
9613 static void intel_mmio_flip_work_func(struct work_struct *work)
9615 struct intel_crtc *crtc =
9616 container_of(work, struct intel_crtc, mmio_flip.work);
9617 struct intel_mmio_flip *mmio_flip;
9619 mmio_flip = &crtc->mmio_flip;
9621 WARN_ON(__i915_wait_request(mmio_flip->req,
9622 crtc->reset_counter,
9623 false, NULL, NULL) != 0);
9625 intel_do_mmio_flip(crtc);
9626 if (mmio_flip->req) {
9627 mutex_lock(&crtc->base.dev->struct_mutex);
9628 i915_gem_request_unreference(mmio_flip->req);
9629 mutex_unlock(&crtc->base.dev->struct_mutex);
9631 mmio_flip->req = NULL;
9634 static int intel_queue_mmio_flip(struct drm_device *dev,
9635 struct drm_crtc *crtc,
9636 struct drm_framebuffer *fb,
9637 struct drm_i915_gem_object *obj,
9638 struct intel_engine_cs *ring,
9641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9643 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9644 obj->last_write_req);
9646 schedule_work(&intel_crtc->mmio_flip.work);
9651 static int intel_gen9_queue_flip(struct drm_device *dev,
9652 struct drm_crtc *crtc,
9653 struct drm_framebuffer *fb,
9654 struct drm_i915_gem_object *obj,
9655 struct intel_engine_cs *ring,
9658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9659 uint32_t plane = 0, stride;
9662 switch(intel_crtc->pipe) {
9664 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9667 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9670 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9673 WARN_ONCE(1, "unknown plane in flip command\n");
9677 switch (obj->tiling_mode) {
9678 case I915_TILING_NONE:
9679 stride = fb->pitches[0] >> 6;
9682 stride = fb->pitches[0] >> 9;
9685 WARN_ONCE(1, "unknown tiling in flip command\n");
9689 ret = intel_ring_begin(ring, 10);
9693 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9694 intel_ring_emit(ring, DERRMR);
9695 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9696 DERRMR_PIPEB_PRI_FLIP_DONE |
9697 DERRMR_PIPEC_PRI_FLIP_DONE));
9698 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9699 MI_SRM_LRM_GLOBAL_GTT);
9700 intel_ring_emit(ring, DERRMR);
9701 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9702 intel_ring_emit(ring, 0);
9704 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9705 intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9706 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9708 intel_mark_page_flip_active(intel_crtc);
9709 __intel_ring_advance(ring);
9714 static int intel_default_queue_flip(struct drm_device *dev,
9715 struct drm_crtc *crtc,
9716 struct drm_framebuffer *fb,
9717 struct drm_i915_gem_object *obj,
9718 struct intel_engine_cs *ring,
9724 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9725 struct drm_crtc *crtc)
9727 struct drm_i915_private *dev_priv = dev->dev_private;
9728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9729 struct intel_unpin_work *work = intel_crtc->unpin_work;
9732 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9735 if (!work->enable_stall_check)
9738 if (work->flip_ready_vblank == 0) {
9739 if (work->flip_queued_ring &&
9740 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9741 work->flip_queued_seqno))
9744 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9747 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9750 /* Potential stall - if we see that the flip has happened,
9751 * assume a missed interrupt. */
9752 if (INTEL_INFO(dev)->gen >= 4)
9753 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9755 addr = I915_READ(DSPADDR(intel_crtc->plane));
9757 /* There is a potential issue here with a false positive after a flip
9758 * to the same address. We could address this by checking for a
9759 * non-incrementing frame counter.
9761 return addr == work->gtt_offset;
9764 void intel_check_page_flip(struct drm_device *dev, int pipe)
9766 struct drm_i915_private *dev_priv = dev->dev_private;
9767 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9775 spin_lock(&dev->event_lock);
9776 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9777 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9778 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9779 page_flip_completed(intel_crtc);
9781 spin_unlock(&dev->event_lock);
9784 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9785 struct drm_framebuffer *fb,
9786 struct drm_pending_vblank_event *event,
9787 uint32_t page_flip_flags)
9789 struct drm_device *dev = crtc->dev;
9790 struct drm_i915_private *dev_priv = dev->dev_private;
9791 struct drm_framebuffer *old_fb = crtc->primary->fb;
9792 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9794 enum pipe pipe = intel_crtc->pipe;
9795 struct intel_unpin_work *work;
9796 struct intel_engine_cs *ring;
9800 * drm_mode_page_flip_ioctl() should already catch this, but double
9801 * check to be safe. In the future we may enable pageflipping from
9802 * a disabled primary plane.
9804 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9807 /* Can't change pixel format via MI display flips. */
9808 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9812 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9813 * Note that pitch changes could also affect these register.
9815 if (INTEL_INFO(dev)->gen > 3 &&
9816 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9817 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9820 if (i915_terminally_wedged(&dev_priv->gpu_error))
9823 work = kzalloc(sizeof(*work), GFP_KERNEL);
9827 work->event = event;
9829 work->old_fb_obj = intel_fb_obj(old_fb);
9830 INIT_WORK(&work->work, intel_unpin_work_fn);
9832 ret = drm_crtc_vblank_get(crtc);
9836 /* We borrow the event spin lock for protecting unpin_work */
9837 spin_lock_irq(&dev->event_lock);
9838 if (intel_crtc->unpin_work) {
9839 /* Before declaring the flip queue wedged, check if
9840 * the hardware completed the operation behind our backs.
9842 if (__intel_pageflip_stall_check(dev, crtc)) {
9843 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9844 page_flip_completed(intel_crtc);
9846 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9847 spin_unlock_irq(&dev->event_lock);
9849 drm_crtc_vblank_put(crtc);
9854 intel_crtc->unpin_work = work;
9855 spin_unlock_irq(&dev->event_lock);
9857 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9858 flush_workqueue(dev_priv->wq);
9860 ret = i915_mutex_lock_interruptible(dev);
9864 /* Reference the objects for the scheduled work. */
9865 drm_gem_object_reference(&work->old_fb_obj->base);
9866 drm_gem_object_reference(&obj->base);
9868 crtc->primary->fb = fb;
9870 work->pending_flip_obj = obj;
9872 atomic_inc(&intel_crtc->unpin_work_count);
9873 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9875 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9876 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9878 if (IS_VALLEYVIEW(dev)) {
9879 ring = &dev_priv->ring[BCS];
9880 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9881 /* vlv: DISPLAY_FLIP fails to change tiling */
9883 } else if (IS_IVYBRIDGE(dev)) {
9884 ring = &dev_priv->ring[BCS];
9885 } else if (INTEL_INFO(dev)->gen >= 7) {
9887 if (ring == NULL || ring->id != RCS)
9888 ring = &dev_priv->ring[BCS];
9890 ring = &dev_priv->ring[RCS];
9893 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9895 goto cleanup_pending;
9898 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9900 if (use_mmio_flip(ring, obj)) {
9901 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9906 work->flip_queued_seqno =
9907 i915_gem_request_get_seqno(obj->last_write_req);
9908 work->flip_queued_ring = obj->ring;
9910 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9915 work->flip_queued_seqno =
9916 i915_gem_request_get_seqno(intel_ring_get_request(ring));
9917 work->flip_queued_ring = ring;
9920 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9921 work->enable_stall_check = true;
9923 i915_gem_track_fb(work->old_fb_obj, obj,
9924 INTEL_FRONTBUFFER_PRIMARY(pipe));
9926 intel_disable_fbc(dev);
9927 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9928 mutex_unlock(&dev->struct_mutex);
9930 trace_i915_flip_request(intel_crtc->plane, obj);
9935 intel_unpin_fb_obj(obj);
9937 atomic_dec(&intel_crtc->unpin_work_count);
9938 crtc->primary->fb = old_fb;
9939 drm_gem_object_unreference(&work->old_fb_obj->base);
9940 drm_gem_object_unreference(&obj->base);
9941 mutex_unlock(&dev->struct_mutex);
9944 spin_lock_irq(&dev->event_lock);
9945 intel_crtc->unpin_work = NULL;
9946 spin_unlock_irq(&dev->event_lock);
9948 drm_crtc_vblank_put(crtc);
9954 intel_crtc_wait_for_pending_flips(crtc);
9955 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9956 if (ret == 0 && event) {
9957 spin_lock_irq(&dev->event_lock);
9958 drm_send_vblank_event(dev, pipe, event);
9959 spin_unlock_irq(&dev->event_lock);
9965 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9966 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9967 .load_lut = intel_crtc_load_lut,
9971 * intel_modeset_update_staged_output_state
9973 * Updates the staged output configuration state, e.g. after we've read out the
9976 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9978 struct intel_crtc *crtc;
9979 struct intel_encoder *encoder;
9980 struct intel_connector *connector;
9982 list_for_each_entry(connector, &dev->mode_config.connector_list,
9984 connector->new_encoder =
9985 to_intel_encoder(connector->base.encoder);
9988 for_each_intel_encoder(dev, encoder) {
9990 to_intel_crtc(encoder->base.crtc);
9993 for_each_intel_crtc(dev, crtc) {
9994 crtc->new_enabled = crtc->base.enabled;
9996 if (crtc->new_enabled)
9997 crtc->new_config = &crtc->config;
9999 crtc->new_config = NULL;
10004 * intel_modeset_commit_output_state
10006 * This function copies the stage display pipe configuration to the real one.
10008 static void intel_modeset_commit_output_state(struct drm_device *dev)
10010 struct intel_crtc *crtc;
10011 struct intel_encoder *encoder;
10012 struct intel_connector *connector;
10014 list_for_each_entry(connector, &dev->mode_config.connector_list,
10016 connector->base.encoder = &connector->new_encoder->base;
10019 for_each_intel_encoder(dev, encoder) {
10020 encoder->base.crtc = &encoder->new_crtc->base;
10023 for_each_intel_crtc(dev, crtc) {
10024 crtc->base.enabled = crtc->new_enabled;
10029 connected_sink_compute_bpp(struct intel_connector *connector,
10030 struct intel_crtc_config *pipe_config)
10032 int bpp = pipe_config->pipe_bpp;
10034 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10035 connector->base.base.id,
10036 connector->base.name);
10038 /* Don't use an invalid EDID bpc value */
10039 if (connector->base.display_info.bpc &&
10040 connector->base.display_info.bpc * 3 < bpp) {
10041 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10042 bpp, connector->base.display_info.bpc*3);
10043 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10046 /* Clamp bpp to 8 on screens without EDID 1.4 */
10047 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10048 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10050 pipe_config->pipe_bpp = 24;
10055 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10056 struct drm_framebuffer *fb,
10057 struct intel_crtc_config *pipe_config)
10059 struct drm_device *dev = crtc->base.dev;
10060 struct intel_connector *connector;
10063 switch (fb->pixel_format) {
10064 case DRM_FORMAT_C8:
10065 bpp = 8*3; /* since we go through a colormap */
10067 case DRM_FORMAT_XRGB1555:
10068 case DRM_FORMAT_ARGB1555:
10069 /* checked in intel_framebuffer_init already */
10070 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10072 case DRM_FORMAT_RGB565:
10073 bpp = 6*3; /* min is 18bpp */
10075 case DRM_FORMAT_XBGR8888:
10076 case DRM_FORMAT_ABGR8888:
10077 /* checked in intel_framebuffer_init already */
10078 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10080 case DRM_FORMAT_XRGB8888:
10081 case DRM_FORMAT_ARGB8888:
10084 case DRM_FORMAT_XRGB2101010:
10085 case DRM_FORMAT_ARGB2101010:
10086 case DRM_FORMAT_XBGR2101010:
10087 case DRM_FORMAT_ABGR2101010:
10088 /* checked in intel_framebuffer_init already */
10089 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10093 /* TODO: gen4+ supports 16 bpc floating point, too. */
10095 DRM_DEBUG_KMS("unsupported depth\n");
10099 pipe_config->pipe_bpp = bpp;
10101 /* Clamp display bpp to EDID value */
10102 list_for_each_entry(connector, &dev->mode_config.connector_list,
10104 if (!connector->new_encoder ||
10105 connector->new_encoder->new_crtc != crtc)
10108 connected_sink_compute_bpp(connector, pipe_config);
10114 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10116 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10117 "type: 0x%x flags: 0x%x\n",
10119 mode->crtc_hdisplay, mode->crtc_hsync_start,
10120 mode->crtc_hsync_end, mode->crtc_htotal,
10121 mode->crtc_vdisplay, mode->crtc_vsync_start,
10122 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10125 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10126 struct intel_crtc_config *pipe_config,
10127 const char *context)
10129 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10130 context, pipe_name(crtc->pipe));
10132 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10133 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10134 pipe_config->pipe_bpp, pipe_config->dither);
10135 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10136 pipe_config->has_pch_encoder,
10137 pipe_config->fdi_lanes,
10138 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10139 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10140 pipe_config->fdi_m_n.tu);
10141 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10142 pipe_config->has_dp_encoder,
10143 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10144 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10145 pipe_config->dp_m_n.tu);
10147 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10148 pipe_config->has_dp_encoder,
10149 pipe_config->dp_m2_n2.gmch_m,
10150 pipe_config->dp_m2_n2.gmch_n,
10151 pipe_config->dp_m2_n2.link_m,
10152 pipe_config->dp_m2_n2.link_n,
10153 pipe_config->dp_m2_n2.tu);
10155 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10156 pipe_config->has_audio,
10157 pipe_config->has_infoframe);
10159 DRM_DEBUG_KMS("requested mode:\n");
10160 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10161 DRM_DEBUG_KMS("adjusted mode:\n");
10162 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10163 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10164 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10165 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10166 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10167 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10168 pipe_config->gmch_pfit.control,
10169 pipe_config->gmch_pfit.pgm_ratios,
10170 pipe_config->gmch_pfit.lvds_border_bits);
10171 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10172 pipe_config->pch_pfit.pos,
10173 pipe_config->pch_pfit.size,
10174 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10175 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10176 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10179 static bool encoders_cloneable(const struct intel_encoder *a,
10180 const struct intel_encoder *b)
10182 /* masks could be asymmetric, so check both ways */
10183 return a == b || (a->cloneable & (1 << b->type) &&
10184 b->cloneable & (1 << a->type));
10187 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10188 struct intel_encoder *encoder)
10190 struct drm_device *dev = crtc->base.dev;
10191 struct intel_encoder *source_encoder;
10193 for_each_intel_encoder(dev, source_encoder) {
10194 if (source_encoder->new_crtc != crtc)
10197 if (!encoders_cloneable(encoder, source_encoder))
10204 static bool check_encoder_cloning(struct intel_crtc *crtc)
10206 struct drm_device *dev = crtc->base.dev;
10207 struct intel_encoder *encoder;
10209 for_each_intel_encoder(dev, encoder) {
10210 if (encoder->new_crtc != crtc)
10213 if (!check_single_encoder_cloning(crtc, encoder))
10220 static bool check_digital_port_conflicts(struct drm_device *dev)
10222 struct intel_connector *connector;
10223 unsigned int used_ports = 0;
10226 * Walk the connector list instead of the encoder
10227 * list to detect the problem on ddi platforms
10228 * where there's just one encoder per digital port.
10230 list_for_each_entry(connector,
10231 &dev->mode_config.connector_list, base.head) {
10232 struct intel_encoder *encoder = connector->new_encoder;
10237 WARN_ON(!encoder->new_crtc);
10239 switch (encoder->type) {
10240 unsigned int port_mask;
10241 case INTEL_OUTPUT_UNKNOWN:
10242 if (WARN_ON(!HAS_DDI(dev)))
10244 case INTEL_OUTPUT_DISPLAYPORT:
10245 case INTEL_OUTPUT_HDMI:
10246 case INTEL_OUTPUT_EDP:
10247 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10249 /* the same port mustn't appear more than once */
10250 if (used_ports & port_mask)
10253 used_ports |= port_mask;
10262 static struct intel_crtc_config *
10263 intel_modeset_pipe_config(struct drm_crtc *crtc,
10264 struct drm_framebuffer *fb,
10265 struct drm_display_mode *mode)
10267 struct drm_device *dev = crtc->dev;
10268 struct intel_encoder *encoder;
10269 struct intel_crtc_config *pipe_config;
10270 int plane_bpp, ret = -EINVAL;
10273 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10274 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10275 return ERR_PTR(-EINVAL);
10278 if (!check_digital_port_conflicts(dev)) {
10279 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10280 return ERR_PTR(-EINVAL);
10283 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10285 return ERR_PTR(-ENOMEM);
10287 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10288 drm_mode_copy(&pipe_config->requested_mode, mode);
10290 pipe_config->cpu_transcoder =
10291 (enum transcoder) to_intel_crtc(crtc)->pipe;
10292 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10295 * Sanitize sync polarity flags based on requested ones. If neither
10296 * positive or negative polarity is requested, treat this as meaning
10297 * negative polarity.
10299 if (!(pipe_config->adjusted_mode.flags &
10300 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10301 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10303 if (!(pipe_config->adjusted_mode.flags &
10304 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10305 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10307 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10308 * plane pixel format and any sink constraints into account. Returns the
10309 * source plane bpp so that dithering can be selected on mismatches
10310 * after encoders and crtc also have had their say. */
10311 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10317 * Determine the real pipe dimensions. Note that stereo modes can
10318 * increase the actual pipe size due to the frame doubling and
10319 * insertion of additional space for blanks between the frame. This
10320 * is stored in the crtc timings. We use the requested mode to do this
10321 * computation to clearly distinguish it from the adjusted mode, which
10322 * can be changed by the connectors in the below retry loop.
10324 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10325 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10326 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10329 /* Ensure the port clock defaults are reset when retrying. */
10330 pipe_config->port_clock = 0;
10331 pipe_config->pixel_multiplier = 1;
10333 /* Fill in default crtc timings, allow encoders to overwrite them. */
10334 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10336 /* Pass our mode to the connectors and the CRTC to give them a chance to
10337 * adjust it according to limitations or connector properties, and also
10338 * a chance to reject the mode entirely.
10340 for_each_intel_encoder(dev, encoder) {
10342 if (&encoder->new_crtc->base != crtc)
10345 if (!(encoder->compute_config(encoder, pipe_config))) {
10346 DRM_DEBUG_KMS("Encoder config failure\n");
10351 /* Set default port clock if not overwritten by the encoder. Needs to be
10352 * done afterwards in case the encoder adjusts the mode. */
10353 if (!pipe_config->port_clock)
10354 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10355 * pipe_config->pixel_multiplier;
10357 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10359 DRM_DEBUG_KMS("CRTC fixup failed\n");
10363 if (ret == RETRY) {
10364 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10369 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10371 goto encoder_retry;
10374 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10375 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10376 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10378 return pipe_config;
10380 kfree(pipe_config);
10381 return ERR_PTR(ret);
10384 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10385 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10387 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10388 unsigned *prepare_pipes, unsigned *disable_pipes)
10390 struct intel_crtc *intel_crtc;
10391 struct drm_device *dev = crtc->dev;
10392 struct intel_encoder *encoder;
10393 struct intel_connector *connector;
10394 struct drm_crtc *tmp_crtc;
10396 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10398 /* Check which crtcs have changed outputs connected to them, these need
10399 * to be part of the prepare_pipes mask. We don't (yet) support global
10400 * modeset across multiple crtcs, so modeset_pipes will only have one
10401 * bit set at most. */
10402 list_for_each_entry(connector, &dev->mode_config.connector_list,
10404 if (connector->base.encoder == &connector->new_encoder->base)
10407 if (connector->base.encoder) {
10408 tmp_crtc = connector->base.encoder->crtc;
10410 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10413 if (connector->new_encoder)
10415 1 << connector->new_encoder->new_crtc->pipe;
10418 for_each_intel_encoder(dev, encoder) {
10419 if (encoder->base.crtc == &encoder->new_crtc->base)
10422 if (encoder->base.crtc) {
10423 tmp_crtc = encoder->base.crtc;
10425 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10428 if (encoder->new_crtc)
10429 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10432 /* Check for pipes that will be enabled/disabled ... */
10433 for_each_intel_crtc(dev, intel_crtc) {
10434 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10437 if (!intel_crtc->new_enabled)
10438 *disable_pipes |= 1 << intel_crtc->pipe;
10440 *prepare_pipes |= 1 << intel_crtc->pipe;
10444 /* set_mode is also used to update properties on life display pipes. */
10445 intel_crtc = to_intel_crtc(crtc);
10446 if (intel_crtc->new_enabled)
10447 *prepare_pipes |= 1 << intel_crtc->pipe;
10450 * For simplicity do a full modeset on any pipe where the output routing
10451 * changed. We could be more clever, but that would require us to be
10452 * more careful with calling the relevant encoder->mode_set functions.
10454 if (*prepare_pipes)
10455 *modeset_pipes = *prepare_pipes;
10457 /* ... and mask these out. */
10458 *modeset_pipes &= ~(*disable_pipes);
10459 *prepare_pipes &= ~(*disable_pipes);
10462 * HACK: We don't (yet) fully support global modesets. intel_set_config
10463 * obies this rule, but the modeset restore mode of
10464 * intel_modeset_setup_hw_state does not.
10466 *modeset_pipes &= 1 << intel_crtc->pipe;
10467 *prepare_pipes &= 1 << intel_crtc->pipe;
10469 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10470 *modeset_pipes, *prepare_pipes, *disable_pipes);
10473 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10475 struct drm_encoder *encoder;
10476 struct drm_device *dev = crtc->dev;
10478 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10479 if (encoder->crtc == crtc)
10486 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10488 struct drm_i915_private *dev_priv = dev->dev_private;
10489 struct intel_encoder *intel_encoder;
10490 struct intel_crtc *intel_crtc;
10491 struct drm_connector *connector;
10493 intel_shared_dpll_commit(dev_priv);
10495 for_each_intel_encoder(dev, intel_encoder) {
10496 if (!intel_encoder->base.crtc)
10499 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10501 if (prepare_pipes & (1 << intel_crtc->pipe))
10502 intel_encoder->connectors_active = false;
10505 intel_modeset_commit_output_state(dev);
10507 /* Double check state. */
10508 for_each_intel_crtc(dev, intel_crtc) {
10509 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10510 WARN_ON(intel_crtc->new_config &&
10511 intel_crtc->new_config != &intel_crtc->config);
10512 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10515 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10516 if (!connector->encoder || !connector->encoder->crtc)
10519 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10521 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10522 struct drm_property *dpms_property =
10523 dev->mode_config.dpms_property;
10525 connector->dpms = DRM_MODE_DPMS_ON;
10526 drm_object_property_set_value(&connector->base,
10530 intel_encoder = to_intel_encoder(connector->encoder);
10531 intel_encoder->connectors_active = true;
10537 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10541 if (clock1 == clock2)
10544 if (!clock1 || !clock2)
10547 diff = abs(clock1 - clock2);
10549 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10555 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10556 list_for_each_entry((intel_crtc), \
10557 &(dev)->mode_config.crtc_list, \
10559 if (mask & (1 <<(intel_crtc)->pipe))
10562 intel_pipe_config_compare(struct drm_device *dev,
10563 struct intel_crtc_config *current_config,
10564 struct intel_crtc_config *pipe_config)
10566 #define PIPE_CONF_CHECK_X(name) \
10567 if (current_config->name != pipe_config->name) { \
10568 DRM_ERROR("mismatch in " #name " " \
10569 "(expected 0x%08x, found 0x%08x)\n", \
10570 current_config->name, \
10571 pipe_config->name); \
10575 #define PIPE_CONF_CHECK_I(name) \
10576 if (current_config->name != pipe_config->name) { \
10577 DRM_ERROR("mismatch in " #name " " \
10578 "(expected %i, found %i)\n", \
10579 current_config->name, \
10580 pipe_config->name); \
10584 /* This is required for BDW+ where there is only one set of registers for
10585 * switching between high and low RR.
10586 * This macro can be used whenever a comparison has to be made between one
10587 * hw state and multiple sw state variables.
10589 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10590 if ((current_config->name != pipe_config->name) && \
10591 (current_config->alt_name != pipe_config->name)) { \
10592 DRM_ERROR("mismatch in " #name " " \
10593 "(expected %i or %i, found %i)\n", \
10594 current_config->name, \
10595 current_config->alt_name, \
10596 pipe_config->name); \
10600 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10601 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10602 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10603 "(expected %i, found %i)\n", \
10604 current_config->name & (mask), \
10605 pipe_config->name & (mask)); \
10609 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10610 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10611 DRM_ERROR("mismatch in " #name " " \
10612 "(expected %i, found %i)\n", \
10613 current_config->name, \
10614 pipe_config->name); \
10618 #define PIPE_CONF_QUIRK(quirk) \
10619 ((current_config->quirks | pipe_config->quirks) & (quirk))
10621 PIPE_CONF_CHECK_I(cpu_transcoder);
10623 PIPE_CONF_CHECK_I(has_pch_encoder);
10624 PIPE_CONF_CHECK_I(fdi_lanes);
10625 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10626 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10627 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10628 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10629 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10631 PIPE_CONF_CHECK_I(has_dp_encoder);
10633 if (INTEL_INFO(dev)->gen < 8) {
10634 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10635 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10636 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10637 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10638 PIPE_CONF_CHECK_I(dp_m_n.tu);
10640 if (current_config->has_drrs) {
10641 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10642 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10643 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10644 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10645 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10648 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10649 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10650 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10651 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10652 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10655 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10656 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10657 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10658 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10659 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10660 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10662 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10663 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10664 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10665 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10666 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10667 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10669 PIPE_CONF_CHECK_I(pixel_multiplier);
10670 PIPE_CONF_CHECK_I(has_hdmi_sink);
10671 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10672 IS_VALLEYVIEW(dev))
10673 PIPE_CONF_CHECK_I(limited_color_range);
10674 PIPE_CONF_CHECK_I(has_infoframe);
10676 PIPE_CONF_CHECK_I(has_audio);
10678 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10679 DRM_MODE_FLAG_INTERLACE);
10681 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10682 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10683 DRM_MODE_FLAG_PHSYNC);
10684 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10685 DRM_MODE_FLAG_NHSYNC);
10686 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10687 DRM_MODE_FLAG_PVSYNC);
10688 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10689 DRM_MODE_FLAG_NVSYNC);
10692 PIPE_CONF_CHECK_I(pipe_src_w);
10693 PIPE_CONF_CHECK_I(pipe_src_h);
10696 * FIXME: BIOS likes to set up a cloned config with lvds+external
10697 * screen. Since we don't yet re-compute the pipe config when moving
10698 * just the lvds port away to another pipe the sw tracking won't match.
10700 * Proper atomic modesets with recomputed global state will fix this.
10701 * Until then just don't check gmch state for inherited modes.
10703 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10704 PIPE_CONF_CHECK_I(gmch_pfit.control);
10705 /* pfit ratios are autocomputed by the hw on gen4+ */
10706 if (INTEL_INFO(dev)->gen < 4)
10707 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10708 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10711 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10712 if (current_config->pch_pfit.enabled) {
10713 PIPE_CONF_CHECK_I(pch_pfit.pos);
10714 PIPE_CONF_CHECK_I(pch_pfit.size);
10717 /* BDW+ don't expose a synchronous way to read the state */
10718 if (IS_HASWELL(dev))
10719 PIPE_CONF_CHECK_I(ips_enabled);
10721 PIPE_CONF_CHECK_I(double_wide);
10723 PIPE_CONF_CHECK_X(ddi_pll_sel);
10725 PIPE_CONF_CHECK_I(shared_dpll);
10726 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10727 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10728 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10729 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10730 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10731 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10732 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10733 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10735 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10736 PIPE_CONF_CHECK_I(pipe_bpp);
10738 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10739 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10741 #undef PIPE_CONF_CHECK_X
10742 #undef PIPE_CONF_CHECK_I
10743 #undef PIPE_CONF_CHECK_I_ALT
10744 #undef PIPE_CONF_CHECK_FLAGS
10745 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10746 #undef PIPE_CONF_QUIRK
10751 static void check_wm_state(struct drm_device *dev)
10753 struct drm_i915_private *dev_priv = dev->dev_private;
10754 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10755 struct intel_crtc *intel_crtc;
10758 if (INTEL_INFO(dev)->gen < 9)
10761 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10762 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10764 for_each_intel_crtc(dev, intel_crtc) {
10765 struct skl_ddb_entry *hw_entry, *sw_entry;
10766 const enum pipe pipe = intel_crtc->pipe;
10768 if (!intel_crtc->active)
10772 for_each_plane(pipe, plane) {
10773 hw_entry = &hw_ddb.plane[pipe][plane];
10774 sw_entry = &sw_ddb->plane[pipe][plane];
10776 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10779 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10780 "(expected (%u,%u), found (%u,%u))\n",
10781 pipe_name(pipe), plane + 1,
10782 sw_entry->start, sw_entry->end,
10783 hw_entry->start, hw_entry->end);
10787 hw_entry = &hw_ddb.cursor[pipe];
10788 sw_entry = &sw_ddb->cursor[pipe];
10790 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10793 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10794 "(expected (%u,%u), found (%u,%u))\n",
10796 sw_entry->start, sw_entry->end,
10797 hw_entry->start, hw_entry->end);
10802 check_connector_state(struct drm_device *dev)
10804 struct intel_connector *connector;
10806 list_for_each_entry(connector, &dev->mode_config.connector_list,
10808 /* This also checks the encoder/connector hw state with the
10809 * ->get_hw_state callbacks. */
10810 intel_connector_check_state(connector);
10812 WARN(&connector->new_encoder->base != connector->base.encoder,
10813 "connector's staged encoder doesn't match current encoder\n");
10818 check_encoder_state(struct drm_device *dev)
10820 struct intel_encoder *encoder;
10821 struct intel_connector *connector;
10823 for_each_intel_encoder(dev, encoder) {
10824 bool enabled = false;
10825 bool active = false;
10826 enum pipe pipe, tracked_pipe;
10828 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10829 encoder->base.base.id,
10830 encoder->base.name);
10832 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10833 "encoder's stage crtc doesn't match current crtc\n");
10834 WARN(encoder->connectors_active && !encoder->base.crtc,
10835 "encoder's active_connectors set, but no crtc\n");
10837 list_for_each_entry(connector, &dev->mode_config.connector_list,
10839 if (connector->base.encoder != &encoder->base)
10842 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10846 * for MST connectors if we unplug the connector is gone
10847 * away but the encoder is still connected to a crtc
10848 * until a modeset happens in response to the hotplug.
10850 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10853 WARN(!!encoder->base.crtc != enabled,
10854 "encoder's enabled state mismatch "
10855 "(expected %i, found %i)\n",
10856 !!encoder->base.crtc, enabled);
10857 WARN(active && !encoder->base.crtc,
10858 "active encoder with no crtc\n");
10860 WARN(encoder->connectors_active != active,
10861 "encoder's computed active state doesn't match tracked active state "
10862 "(expected %i, found %i)\n", active, encoder->connectors_active);
10864 active = encoder->get_hw_state(encoder, &pipe);
10865 WARN(active != encoder->connectors_active,
10866 "encoder's hw state doesn't match sw tracking "
10867 "(expected %i, found %i)\n",
10868 encoder->connectors_active, active);
10870 if (!encoder->base.crtc)
10873 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10874 WARN(active && pipe != tracked_pipe,
10875 "active encoder's pipe doesn't match"
10876 "(expected %i, found %i)\n",
10877 tracked_pipe, pipe);
10883 check_crtc_state(struct drm_device *dev)
10885 struct drm_i915_private *dev_priv = dev->dev_private;
10886 struct intel_crtc *crtc;
10887 struct intel_encoder *encoder;
10888 struct intel_crtc_config pipe_config;
10890 for_each_intel_crtc(dev, crtc) {
10891 bool enabled = false;
10892 bool active = false;
10894 memset(&pipe_config, 0, sizeof(pipe_config));
10896 DRM_DEBUG_KMS("[CRTC:%d]\n",
10897 crtc->base.base.id);
10899 WARN(crtc->active && !crtc->base.enabled,
10900 "active crtc, but not enabled in sw tracking\n");
10902 for_each_intel_encoder(dev, encoder) {
10903 if (encoder->base.crtc != &crtc->base)
10906 if (encoder->connectors_active)
10910 WARN(active != crtc->active,
10911 "crtc's computed active state doesn't match tracked active state "
10912 "(expected %i, found %i)\n", active, crtc->active);
10913 WARN(enabled != crtc->base.enabled,
10914 "crtc's computed enabled state doesn't match tracked enabled state "
10915 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10917 active = dev_priv->display.get_pipe_config(crtc,
10920 /* hw state is inconsistent with the pipe quirk */
10921 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10922 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10923 active = crtc->active;
10925 for_each_intel_encoder(dev, encoder) {
10927 if (encoder->base.crtc != &crtc->base)
10929 if (encoder->get_hw_state(encoder, &pipe))
10930 encoder->get_config(encoder, &pipe_config);
10933 WARN(crtc->active != active,
10934 "crtc active state doesn't match with hw state "
10935 "(expected %i, found %i)\n", crtc->active, active);
10938 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10939 WARN(1, "pipe state doesn't match!\n");
10940 intel_dump_pipe_config(crtc, &pipe_config,
10942 intel_dump_pipe_config(crtc, &crtc->config,
10949 check_shared_dpll_state(struct drm_device *dev)
10951 struct drm_i915_private *dev_priv = dev->dev_private;
10952 struct intel_crtc *crtc;
10953 struct intel_dpll_hw_state dpll_hw_state;
10956 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10957 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10958 int enabled_crtcs = 0, active_crtcs = 0;
10961 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10963 DRM_DEBUG_KMS("%s\n", pll->name);
10965 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10967 WARN(pll->active > hweight32(pll->config.crtc_mask),
10968 "more active pll users than references: %i vs %i\n",
10969 pll->active, hweight32(pll->config.crtc_mask));
10970 WARN(pll->active && !pll->on,
10971 "pll in active use but not on in sw tracking\n");
10972 WARN(pll->on && !pll->active,
10973 "pll in on but not on in use in sw tracking\n");
10974 WARN(pll->on != active,
10975 "pll on state mismatch (expected %i, found %i)\n",
10978 for_each_intel_crtc(dev, crtc) {
10979 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10981 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10984 WARN(pll->active != active_crtcs,
10985 "pll active crtcs mismatch (expected %i, found %i)\n",
10986 pll->active, active_crtcs);
10987 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10988 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10989 hweight32(pll->config.crtc_mask), enabled_crtcs);
10991 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10992 sizeof(dpll_hw_state)),
10993 "pll hw state mismatch\n");
10998 intel_modeset_check_state(struct drm_device *dev)
11000 check_wm_state(dev);
11001 check_connector_state(dev);
11002 check_encoder_state(dev);
11003 check_crtc_state(dev);
11004 check_shared_dpll_state(dev);
11007 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
11011 * FDI already provided one idea for the dotclock.
11012 * Yell if the encoder disagrees.
11014 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
11015 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11016 pipe_config->adjusted_mode.crtc_clock, dotclock);
11019 static void update_scanline_offset(struct intel_crtc *crtc)
11021 struct drm_device *dev = crtc->base.dev;
11024 * The scanline counter increments at the leading edge of hsync.
11026 * On most platforms it starts counting from vtotal-1 on the
11027 * first active line. That means the scanline counter value is
11028 * always one less than what we would expect. Ie. just after
11029 * start of vblank, which also occurs at start of hsync (on the
11030 * last active line), the scanline counter will read vblank_start-1.
11032 * On gen2 the scanline counter starts counting from 1 instead
11033 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11034 * to keep the value positive), instead of adding one.
11036 * On HSW+ the behaviour of the scanline counter depends on the output
11037 * type. For DP ports it behaves like most other platforms, but on HDMI
11038 * there's an extra 1 line difference. So we need to add two instead of
11039 * one to the value.
11041 if (IS_GEN2(dev)) {
11042 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
11045 vtotal = mode->crtc_vtotal;
11046 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11049 crtc->scanline_offset = vtotal - 1;
11050 } else if (HAS_DDI(dev) &&
11051 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11052 crtc->scanline_offset = 2;
11054 crtc->scanline_offset = 1;
11057 static struct intel_crtc_config *
11058 intel_modeset_compute_config(struct drm_crtc *crtc,
11059 struct drm_display_mode *mode,
11060 struct drm_framebuffer *fb,
11061 unsigned *modeset_pipes,
11062 unsigned *prepare_pipes,
11063 unsigned *disable_pipes)
11065 struct intel_crtc_config *pipe_config = NULL;
11067 intel_modeset_affected_pipes(crtc, modeset_pipes,
11068 prepare_pipes, disable_pipes);
11070 if ((*modeset_pipes) == 0)
11074 * Note this needs changes when we start tracking multiple modes
11075 * and crtcs. At that point we'll need to compute the whole config
11076 * (i.e. one pipe_config for each crtc) rather than just the one
11079 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11080 if (IS_ERR(pipe_config)) {
11083 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11087 return pipe_config;
11090 static int __intel_set_mode(struct drm_crtc *crtc,
11091 struct drm_display_mode *mode,
11092 int x, int y, struct drm_framebuffer *fb,
11093 struct intel_crtc_config *pipe_config,
11094 unsigned modeset_pipes,
11095 unsigned prepare_pipes,
11096 unsigned disable_pipes)
11098 struct drm_device *dev = crtc->dev;
11099 struct drm_i915_private *dev_priv = dev->dev_private;
11100 struct drm_display_mode *saved_mode;
11101 struct intel_crtc *intel_crtc;
11104 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11108 *saved_mode = crtc->mode;
11111 to_intel_crtc(crtc)->new_config = pipe_config;
11114 * See if the config requires any additional preparation, e.g.
11115 * to adjust global state with pipes off. We need to do this
11116 * here so we can get the modeset_pipe updated config for the new
11117 * mode set on this crtc. For other crtcs we need to use the
11118 * adjusted_mode bits in the crtc directly.
11120 if (IS_VALLEYVIEW(dev)) {
11121 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11123 /* may have added more to prepare_pipes than we should */
11124 prepare_pipes &= ~disable_pipes;
11127 if (dev_priv->display.crtc_compute_clock) {
11128 unsigned clear_pipes = modeset_pipes | disable_pipes;
11130 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11134 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11135 ret = dev_priv->display.crtc_compute_clock(intel_crtc);
11137 intel_shared_dpll_abort_config(dev_priv);
11143 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11144 intel_crtc_disable(&intel_crtc->base);
11146 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11147 if (intel_crtc->base.enabled)
11148 dev_priv->display.crtc_disable(&intel_crtc->base);
11151 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11152 * to set it here already despite that we pass it down the callchain.
11154 * Note we'll need to fix this up when we start tracking multiple
11155 * pipes; here we assume a single modeset_pipe and only track the
11156 * single crtc and mode.
11158 if (modeset_pipes) {
11159 crtc->mode = *mode;
11160 /* mode_set/enable/disable functions rely on a correct pipe
11162 to_intel_crtc(crtc)->config = *pipe_config;
11163 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
11166 * Calculate and store various constants which
11167 * are later needed by vblank and swap-completion
11168 * timestamping. They are derived from true hwmode.
11170 drm_calc_timestamping_constants(crtc,
11171 &pipe_config->adjusted_mode);
11174 /* Only after disabling all output pipelines that will be changed can we
11175 * update the the output configuration. */
11176 intel_modeset_update_state(dev, prepare_pipes);
11178 modeset_update_crtc_power_domains(dev);
11180 /* Set up the DPLL and any encoders state that needs to adjust or depend
11183 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11184 struct drm_framebuffer *old_fb = crtc->primary->fb;
11185 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11186 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11188 mutex_lock(&dev->struct_mutex);
11189 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
11191 DRM_ERROR("pin & fence failed\n");
11192 mutex_unlock(&dev->struct_mutex);
11196 intel_unpin_fb_obj(old_obj);
11197 i915_gem_track_fb(old_obj, obj,
11198 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11199 mutex_unlock(&dev->struct_mutex);
11201 crtc->primary->fb = fb;
11206 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11207 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11208 update_scanline_offset(intel_crtc);
11210 dev_priv->display.crtc_enable(&intel_crtc->base);
11213 /* FIXME: add subpixel order */
11215 if (ret && crtc->enabled)
11216 crtc->mode = *saved_mode;
11218 kfree(pipe_config);
11223 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11224 struct drm_display_mode *mode,
11225 int x, int y, struct drm_framebuffer *fb,
11226 struct intel_crtc_config *pipe_config,
11227 unsigned modeset_pipes,
11228 unsigned prepare_pipes,
11229 unsigned disable_pipes)
11233 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11234 prepare_pipes, disable_pipes);
11237 intel_modeset_check_state(crtc->dev);
11242 static int intel_set_mode(struct drm_crtc *crtc,
11243 struct drm_display_mode *mode,
11244 int x, int y, struct drm_framebuffer *fb)
11246 struct intel_crtc_config *pipe_config;
11247 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11249 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11254 if (IS_ERR(pipe_config))
11255 return PTR_ERR(pipe_config);
11257 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11258 modeset_pipes, prepare_pipes,
11262 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11264 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11267 #undef for_each_intel_crtc_masked
11269 static void intel_set_config_free(struct intel_set_config *config)
11274 kfree(config->save_connector_encoders);
11275 kfree(config->save_encoder_crtcs);
11276 kfree(config->save_crtc_enabled);
11280 static int intel_set_config_save_state(struct drm_device *dev,
11281 struct intel_set_config *config)
11283 struct drm_crtc *crtc;
11284 struct drm_encoder *encoder;
11285 struct drm_connector *connector;
11288 config->save_crtc_enabled =
11289 kcalloc(dev->mode_config.num_crtc,
11290 sizeof(bool), GFP_KERNEL);
11291 if (!config->save_crtc_enabled)
11294 config->save_encoder_crtcs =
11295 kcalloc(dev->mode_config.num_encoder,
11296 sizeof(struct drm_crtc *), GFP_KERNEL);
11297 if (!config->save_encoder_crtcs)
11300 config->save_connector_encoders =
11301 kcalloc(dev->mode_config.num_connector,
11302 sizeof(struct drm_encoder *), GFP_KERNEL);
11303 if (!config->save_connector_encoders)
11306 /* Copy data. Note that driver private data is not affected.
11307 * Should anything bad happen only the expected state is
11308 * restored, not the drivers personal bookkeeping.
11311 for_each_crtc(dev, crtc) {
11312 config->save_crtc_enabled[count++] = crtc->enabled;
11316 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11317 config->save_encoder_crtcs[count++] = encoder->crtc;
11321 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11322 config->save_connector_encoders[count++] = connector->encoder;
11328 static void intel_set_config_restore_state(struct drm_device *dev,
11329 struct intel_set_config *config)
11331 struct intel_crtc *crtc;
11332 struct intel_encoder *encoder;
11333 struct intel_connector *connector;
11337 for_each_intel_crtc(dev, crtc) {
11338 crtc->new_enabled = config->save_crtc_enabled[count++];
11340 if (crtc->new_enabled)
11341 crtc->new_config = &crtc->config;
11343 crtc->new_config = NULL;
11347 for_each_intel_encoder(dev, encoder) {
11348 encoder->new_crtc =
11349 to_intel_crtc(config->save_encoder_crtcs[count++]);
11353 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11354 connector->new_encoder =
11355 to_intel_encoder(config->save_connector_encoders[count++]);
11360 is_crtc_connector_off(struct drm_mode_set *set)
11364 if (set->num_connectors == 0)
11367 if (WARN_ON(set->connectors == NULL))
11370 for (i = 0; i < set->num_connectors; i++)
11371 if (set->connectors[i]->encoder &&
11372 set->connectors[i]->encoder->crtc == set->crtc &&
11373 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11380 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11381 struct intel_set_config *config)
11384 /* We should be able to check here if the fb has the same properties
11385 * and then just flip_or_move it */
11386 if (is_crtc_connector_off(set)) {
11387 config->mode_changed = true;
11388 } else if (set->crtc->primary->fb != set->fb) {
11390 * If we have no fb, we can only flip as long as the crtc is
11391 * active, otherwise we need a full mode set. The crtc may
11392 * be active if we've only disabled the primary plane, or
11393 * in fastboot situations.
11395 if (set->crtc->primary->fb == NULL) {
11396 struct intel_crtc *intel_crtc =
11397 to_intel_crtc(set->crtc);
11399 if (intel_crtc->active) {
11400 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11401 config->fb_changed = true;
11403 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11404 config->mode_changed = true;
11406 } else if (set->fb == NULL) {
11407 config->mode_changed = true;
11408 } else if (set->fb->pixel_format !=
11409 set->crtc->primary->fb->pixel_format) {
11410 config->mode_changed = true;
11412 config->fb_changed = true;
11416 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11417 config->fb_changed = true;
11419 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11420 DRM_DEBUG_KMS("modes are different, full mode set\n");
11421 drm_mode_debug_printmodeline(&set->crtc->mode);
11422 drm_mode_debug_printmodeline(set->mode);
11423 config->mode_changed = true;
11426 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11427 set->crtc->base.id, config->mode_changed, config->fb_changed);
11431 intel_modeset_stage_output_state(struct drm_device *dev,
11432 struct drm_mode_set *set,
11433 struct intel_set_config *config)
11435 struct intel_connector *connector;
11436 struct intel_encoder *encoder;
11437 struct intel_crtc *crtc;
11440 /* The upper layers ensure that we either disable a crtc or have a list
11441 * of connectors. For paranoia, double-check this. */
11442 WARN_ON(!set->fb && (set->num_connectors != 0));
11443 WARN_ON(set->fb && (set->num_connectors == 0));
11445 list_for_each_entry(connector, &dev->mode_config.connector_list,
11447 /* Otherwise traverse passed in connector list and get encoders
11449 for (ro = 0; ro < set->num_connectors; ro++) {
11450 if (set->connectors[ro] == &connector->base) {
11451 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11456 /* If we disable the crtc, disable all its connectors. Also, if
11457 * the connector is on the changing crtc but not on the new
11458 * connector list, disable it. */
11459 if ((!set->fb || ro == set->num_connectors) &&
11460 connector->base.encoder &&
11461 connector->base.encoder->crtc == set->crtc) {
11462 connector->new_encoder = NULL;
11464 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11465 connector->base.base.id,
11466 connector->base.name);
11470 if (&connector->new_encoder->base != connector->base.encoder) {
11471 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11472 config->mode_changed = true;
11475 /* connector->new_encoder is now updated for all connectors. */
11477 /* Update crtc of enabled connectors. */
11478 list_for_each_entry(connector, &dev->mode_config.connector_list,
11480 struct drm_crtc *new_crtc;
11482 if (!connector->new_encoder)
11485 new_crtc = connector->new_encoder->base.crtc;
11487 for (ro = 0; ro < set->num_connectors; ro++) {
11488 if (set->connectors[ro] == &connector->base)
11489 new_crtc = set->crtc;
11492 /* Make sure the new CRTC will work with the encoder */
11493 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11497 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11499 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11500 connector->base.base.id,
11501 connector->base.name,
11502 new_crtc->base.id);
11505 /* Check for any encoders that needs to be disabled. */
11506 for_each_intel_encoder(dev, encoder) {
11507 int num_connectors = 0;
11508 list_for_each_entry(connector,
11509 &dev->mode_config.connector_list,
11511 if (connector->new_encoder == encoder) {
11512 WARN_ON(!connector->new_encoder->new_crtc);
11517 if (num_connectors == 0)
11518 encoder->new_crtc = NULL;
11519 else if (num_connectors > 1)
11522 /* Only now check for crtc changes so we don't miss encoders
11523 * that will be disabled. */
11524 if (&encoder->new_crtc->base != encoder->base.crtc) {
11525 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11526 config->mode_changed = true;
11529 /* Now we've also updated encoder->new_crtc for all encoders. */
11530 list_for_each_entry(connector, &dev->mode_config.connector_list,
11532 if (connector->new_encoder)
11533 if (connector->new_encoder != connector->encoder)
11534 connector->encoder = connector->new_encoder;
11536 for_each_intel_crtc(dev, crtc) {
11537 crtc->new_enabled = false;
11539 for_each_intel_encoder(dev, encoder) {
11540 if (encoder->new_crtc == crtc) {
11541 crtc->new_enabled = true;
11546 if (crtc->new_enabled != crtc->base.enabled) {
11547 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11548 crtc->new_enabled ? "en" : "dis");
11549 config->mode_changed = true;
11552 if (crtc->new_enabled)
11553 crtc->new_config = &crtc->config;
11555 crtc->new_config = NULL;
11561 static void disable_crtc_nofb(struct intel_crtc *crtc)
11563 struct drm_device *dev = crtc->base.dev;
11564 struct intel_encoder *encoder;
11565 struct intel_connector *connector;
11567 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11568 pipe_name(crtc->pipe));
11570 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11571 if (connector->new_encoder &&
11572 connector->new_encoder->new_crtc == crtc)
11573 connector->new_encoder = NULL;
11576 for_each_intel_encoder(dev, encoder) {
11577 if (encoder->new_crtc == crtc)
11578 encoder->new_crtc = NULL;
11581 crtc->new_enabled = false;
11582 crtc->new_config = NULL;
11585 static int intel_crtc_set_config(struct drm_mode_set *set)
11587 struct drm_device *dev;
11588 struct drm_mode_set save_set;
11589 struct intel_set_config *config;
11590 struct intel_crtc_config *pipe_config;
11591 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11595 BUG_ON(!set->crtc);
11596 BUG_ON(!set->crtc->helper_private);
11598 /* Enforce sane interface api - has been abused by the fb helper. */
11599 BUG_ON(!set->mode && set->fb);
11600 BUG_ON(set->fb && set->num_connectors == 0);
11603 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11604 set->crtc->base.id, set->fb->base.id,
11605 (int)set->num_connectors, set->x, set->y);
11607 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11610 dev = set->crtc->dev;
11613 config = kzalloc(sizeof(*config), GFP_KERNEL);
11617 ret = intel_set_config_save_state(dev, config);
11621 save_set.crtc = set->crtc;
11622 save_set.mode = &set->crtc->mode;
11623 save_set.x = set->crtc->x;
11624 save_set.y = set->crtc->y;
11625 save_set.fb = set->crtc->primary->fb;
11627 /* Compute whether we need a full modeset, only an fb base update or no
11628 * change at all. In the future we might also check whether only the
11629 * mode changed, e.g. for LVDS where we only change the panel fitter in
11631 intel_set_config_compute_mode_changes(set, config);
11633 ret = intel_modeset_stage_output_state(dev, set, config);
11637 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11642 if (IS_ERR(pipe_config)) {
11643 ret = PTR_ERR(pipe_config);
11645 } else if (pipe_config) {
11646 if (pipe_config->has_audio !=
11647 to_intel_crtc(set->crtc)->config.has_audio)
11648 config->mode_changed = true;
11650 /* Force mode sets for any infoframe stuff */
11651 if (pipe_config->has_infoframe ||
11652 to_intel_crtc(set->crtc)->config.has_infoframe)
11653 config->mode_changed = true;
11656 /* set_mode will free it in the mode_changed case */
11657 if (!config->mode_changed)
11658 kfree(pipe_config);
11660 intel_update_pipe_size(to_intel_crtc(set->crtc));
11662 if (config->mode_changed) {
11663 ret = intel_set_mode_pipes(set->crtc, set->mode,
11664 set->x, set->y, set->fb, pipe_config,
11665 modeset_pipes, prepare_pipes,
11667 } else if (config->fb_changed) {
11668 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11670 intel_crtc_wait_for_pending_flips(set->crtc);
11672 ret = intel_pipe_set_base(set->crtc,
11673 set->x, set->y, set->fb);
11676 * We need to make sure the primary plane is re-enabled if it
11677 * has previously been turned off.
11679 if (!intel_crtc->primary_enabled && ret == 0) {
11680 WARN_ON(!intel_crtc->active);
11681 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11685 * In the fastboot case this may be our only check of the
11686 * state after boot. It would be better to only do it on
11687 * the first update, but we don't have a nice way of doing that
11688 * (and really, set_config isn't used much for high freq page
11689 * flipping, so increasing its cost here shouldn't be a big
11692 if (i915.fastboot && ret == 0)
11693 intel_modeset_check_state(set->crtc->dev);
11697 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11698 set->crtc->base.id, ret);
11700 intel_set_config_restore_state(dev, config);
11703 * HACK: if the pipe was on, but we didn't have a framebuffer,
11704 * force the pipe off to avoid oopsing in the modeset code
11705 * due to fb==NULL. This should only happen during boot since
11706 * we don't yet reconstruct the FB from the hardware state.
11708 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11709 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11711 /* Try to restore the config */
11712 if (config->mode_changed &&
11713 intel_set_mode(save_set.crtc, save_set.mode,
11714 save_set.x, save_set.y, save_set.fb))
11715 DRM_ERROR("failed to restore config after modeset failure\n");
11719 intel_set_config_free(config);
11723 static const struct drm_crtc_funcs intel_crtc_funcs = {
11724 .gamma_set = intel_crtc_gamma_set,
11725 .set_config = intel_crtc_set_config,
11726 .destroy = intel_crtc_destroy,
11727 .page_flip = intel_crtc_page_flip,
11730 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11731 struct intel_shared_dpll *pll,
11732 struct intel_dpll_hw_state *hw_state)
11736 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11739 val = I915_READ(PCH_DPLL(pll->id));
11740 hw_state->dpll = val;
11741 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11742 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11744 return val & DPLL_VCO_ENABLE;
11747 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11748 struct intel_shared_dpll *pll)
11750 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11751 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11754 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11755 struct intel_shared_dpll *pll)
11757 /* PCH refclock must be enabled first */
11758 ibx_assert_pch_refclk_enabled(dev_priv);
11760 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11762 /* Wait for the clocks to stabilize. */
11763 POSTING_READ(PCH_DPLL(pll->id));
11766 /* The pixel multiplier can only be updated once the
11767 * DPLL is enabled and the clocks are stable.
11769 * So write it again.
11771 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11772 POSTING_READ(PCH_DPLL(pll->id));
11776 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11777 struct intel_shared_dpll *pll)
11779 struct drm_device *dev = dev_priv->dev;
11780 struct intel_crtc *crtc;
11782 /* Make sure no transcoder isn't still depending on us. */
11783 for_each_intel_crtc(dev, crtc) {
11784 if (intel_crtc_to_shared_dpll(crtc) == pll)
11785 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11788 I915_WRITE(PCH_DPLL(pll->id), 0);
11789 POSTING_READ(PCH_DPLL(pll->id));
11793 static char *ibx_pch_dpll_names[] = {
11798 static void ibx_pch_dpll_init(struct drm_device *dev)
11800 struct drm_i915_private *dev_priv = dev->dev_private;
11803 dev_priv->num_shared_dpll = 2;
11805 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11806 dev_priv->shared_dplls[i].id = i;
11807 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11808 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11809 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11810 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11811 dev_priv->shared_dplls[i].get_hw_state =
11812 ibx_pch_dpll_get_hw_state;
11816 static void intel_shared_dpll_init(struct drm_device *dev)
11818 struct drm_i915_private *dev_priv = dev->dev_private;
11821 intel_ddi_pll_init(dev);
11822 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11823 ibx_pch_dpll_init(dev);
11825 dev_priv->num_shared_dpll = 0;
11827 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11831 intel_primary_plane_disable(struct drm_plane *plane)
11833 struct drm_device *dev = plane->dev;
11834 struct intel_crtc *intel_crtc;
11839 BUG_ON(!plane->crtc);
11841 intel_crtc = to_intel_crtc(plane->crtc);
11844 * Even though we checked plane->fb above, it's still possible that
11845 * the primary plane has been implicitly disabled because the crtc
11846 * coordinates given weren't visible, or because we detected
11847 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11848 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11849 * In either case, we need to unpin the FB and let the fb pointer get
11850 * updated, but otherwise we don't need to touch the hardware.
11852 if (!intel_crtc->primary_enabled)
11853 goto disable_unpin;
11855 intel_crtc_wait_for_pending_flips(plane->crtc);
11856 intel_disable_primary_hw_plane(plane, plane->crtc);
11859 mutex_lock(&dev->struct_mutex);
11860 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11861 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11862 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11863 mutex_unlock(&dev->struct_mutex);
11870 intel_check_primary_plane(struct drm_plane *plane,
11871 struct intel_plane_state *state)
11873 struct drm_crtc *crtc = state->crtc;
11874 struct drm_framebuffer *fb = state->fb;
11875 struct drm_rect *dest = &state->dst;
11876 struct drm_rect *src = &state->src;
11877 const struct drm_rect *clip = &state->clip;
11879 return drm_plane_helper_check_update(plane, crtc, fb,
11881 DRM_PLANE_HELPER_NO_SCALING,
11882 DRM_PLANE_HELPER_NO_SCALING,
11883 false, true, &state->visible);
11887 intel_prepare_primary_plane(struct drm_plane *plane,
11888 struct intel_plane_state *state)
11890 struct drm_crtc *crtc = state->crtc;
11891 struct drm_framebuffer *fb = state->fb;
11892 struct drm_device *dev = crtc->dev;
11893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11894 enum pipe pipe = intel_crtc->pipe;
11895 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11896 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11899 intel_crtc_wait_for_pending_flips(crtc);
11901 if (intel_crtc_has_pending_flip(crtc)) {
11902 DRM_ERROR("pipe is still busy with an old pageflip\n");
11906 if (old_obj != obj) {
11907 mutex_lock(&dev->struct_mutex);
11908 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11910 i915_gem_track_fb(old_obj, obj,
11911 INTEL_FRONTBUFFER_PRIMARY(pipe));
11912 mutex_unlock(&dev->struct_mutex);
11914 DRM_DEBUG_KMS("pin & fence failed\n");
11923 intel_commit_primary_plane(struct drm_plane *plane,
11924 struct intel_plane_state *state)
11926 struct drm_crtc *crtc = state->crtc;
11927 struct drm_framebuffer *fb = state->fb;
11928 struct drm_device *dev = crtc->dev;
11929 struct drm_i915_private *dev_priv = dev->dev_private;
11930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11931 enum pipe pipe = intel_crtc->pipe;
11932 struct drm_framebuffer *old_fb = plane->fb;
11933 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11934 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11935 struct intel_plane *intel_plane = to_intel_plane(plane);
11936 struct drm_rect *src = &state->src;
11938 crtc->primary->fb = fb;
11939 crtc->x = src->x1 >> 16;
11940 crtc->y = src->y1 >> 16;
11942 intel_plane->crtc_x = state->orig_dst.x1;
11943 intel_plane->crtc_y = state->orig_dst.y1;
11944 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11945 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11946 intel_plane->src_x = state->orig_src.x1;
11947 intel_plane->src_y = state->orig_src.y1;
11948 intel_plane->src_w = drm_rect_width(&state->orig_src);
11949 intel_plane->src_h = drm_rect_height(&state->orig_src);
11950 intel_plane->obj = obj;
11952 if (intel_crtc->active) {
11954 * FBC does not work on some platforms for rotated
11955 * planes, so disable it when rotation is not 0 and
11956 * update it when rotation is set back to 0.
11958 * FIXME: This is redundant with the fbc update done in
11959 * the primary plane enable function except that that
11960 * one is done too late. We eventually need to unify
11963 if (intel_crtc->primary_enabled &&
11964 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11965 dev_priv->fbc.plane == intel_crtc->plane &&
11966 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11967 intel_disable_fbc(dev);
11970 if (state->visible) {
11971 bool was_enabled = intel_crtc->primary_enabled;
11973 /* FIXME: kill this fastboot hack */
11974 intel_update_pipe_size(intel_crtc);
11976 intel_crtc->primary_enabled = true;
11978 dev_priv->display.update_primary_plane(crtc, plane->fb,
11982 * BDW signals flip done immediately if the plane
11983 * is disabled, even if the plane enable is already
11984 * armed to occur at the next vblank :(
11986 if (IS_BROADWELL(dev) && !was_enabled)
11987 intel_wait_for_vblank(dev, intel_crtc->pipe);
11990 * If clipping results in a non-visible primary plane,
11991 * we'll disable the primary plane. Note that this is
11992 * a bit different than what happens if userspace
11993 * explicitly disables the plane by passing fb=0
11994 * because plane->fb still gets set and pinned.
11996 intel_disable_primary_hw_plane(plane, crtc);
11999 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
12001 mutex_lock(&dev->struct_mutex);
12002 intel_update_fbc(dev);
12003 mutex_unlock(&dev->struct_mutex);
12006 if (old_fb && old_fb != fb) {
12007 if (intel_crtc->active)
12008 intel_wait_for_vblank(dev, intel_crtc->pipe);
12010 mutex_lock(&dev->struct_mutex);
12011 intel_unpin_fb_obj(old_obj);
12012 mutex_unlock(&dev->struct_mutex);
12017 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
12018 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12019 unsigned int crtc_w, unsigned int crtc_h,
12020 uint32_t src_x, uint32_t src_y,
12021 uint32_t src_w, uint32_t src_h)
12023 struct intel_plane_state state;
12024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12030 /* sample coordinates in 16.16 fixed point */
12031 state.src.x1 = src_x;
12032 state.src.x2 = src_x + src_w;
12033 state.src.y1 = src_y;
12034 state.src.y2 = src_y + src_h;
12036 /* integer pixels */
12037 state.dst.x1 = crtc_x;
12038 state.dst.x2 = crtc_x + crtc_w;
12039 state.dst.y1 = crtc_y;
12040 state.dst.y2 = crtc_y + crtc_h;
12044 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12045 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12047 state.orig_src = state.src;
12048 state.orig_dst = state.dst;
12050 ret = intel_check_primary_plane(plane, &state);
12054 ret = intel_prepare_primary_plane(plane, &state);
12058 intel_commit_primary_plane(plane, &state);
12063 /* Common destruction function for both primary and cursor planes */
12064 static void intel_plane_destroy(struct drm_plane *plane)
12066 struct intel_plane *intel_plane = to_intel_plane(plane);
12067 drm_plane_cleanup(plane);
12068 kfree(intel_plane);
12071 static const struct drm_plane_funcs intel_primary_plane_funcs = {
12072 .update_plane = intel_primary_plane_setplane,
12073 .disable_plane = intel_primary_plane_disable,
12074 .destroy = intel_plane_destroy,
12075 .set_property = intel_plane_set_property
12078 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12081 struct intel_plane *primary;
12082 const uint32_t *intel_primary_formats;
12085 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12086 if (primary == NULL)
12089 primary->can_scale = false;
12090 primary->max_downscale = 1;
12091 primary->pipe = pipe;
12092 primary->plane = pipe;
12093 primary->rotation = BIT(DRM_ROTATE_0);
12094 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12095 primary->plane = !pipe;
12097 if (INTEL_INFO(dev)->gen <= 3) {
12098 intel_primary_formats = intel_primary_formats_gen2;
12099 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12101 intel_primary_formats = intel_primary_formats_gen4;
12102 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12105 drm_universal_plane_init(dev, &primary->base, 0,
12106 &intel_primary_plane_funcs,
12107 intel_primary_formats, num_formats,
12108 DRM_PLANE_TYPE_PRIMARY);
12110 if (INTEL_INFO(dev)->gen >= 4) {
12111 if (!dev->mode_config.rotation_property)
12112 dev->mode_config.rotation_property =
12113 drm_mode_create_rotation_property(dev,
12114 BIT(DRM_ROTATE_0) |
12115 BIT(DRM_ROTATE_180));
12116 if (dev->mode_config.rotation_property)
12117 drm_object_attach_property(&primary->base.base,
12118 dev->mode_config.rotation_property,
12119 primary->rotation);
12122 return &primary->base;
12126 intel_cursor_plane_disable(struct drm_plane *plane)
12131 BUG_ON(!plane->crtc);
12133 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
12137 intel_check_cursor_plane(struct drm_plane *plane,
12138 struct intel_plane_state *state)
12140 struct drm_crtc *crtc = state->crtc;
12141 struct drm_device *dev = crtc->dev;
12142 struct drm_framebuffer *fb = state->fb;
12143 struct drm_rect *dest = &state->dst;
12144 struct drm_rect *src = &state->src;
12145 const struct drm_rect *clip = &state->clip;
12146 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12147 int crtc_w, crtc_h;
12151 ret = drm_plane_helper_check_update(plane, crtc, fb,
12153 DRM_PLANE_HELPER_NO_SCALING,
12154 DRM_PLANE_HELPER_NO_SCALING,
12155 true, true, &state->visible);
12160 /* if we want to turn off the cursor ignore width and height */
12164 /* Check for which cursor types we support */
12165 crtc_w = drm_rect_width(&state->orig_dst);
12166 crtc_h = drm_rect_height(&state->orig_dst);
12167 if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
12168 DRM_DEBUG("Cursor dimension not supported\n");
12172 stride = roundup_pow_of_two(crtc_w) * 4;
12173 if (obj->base.size < stride * crtc_h) {
12174 DRM_DEBUG_KMS("buffer is too small\n");
12178 if (fb == crtc->cursor->fb)
12181 /* we only need to pin inside GTT if cursor is non-phy */
12182 mutex_lock(&dev->struct_mutex);
12183 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12184 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12187 mutex_unlock(&dev->struct_mutex);
12193 intel_commit_cursor_plane(struct drm_plane *plane,
12194 struct intel_plane_state *state)
12196 struct drm_crtc *crtc = state->crtc;
12197 struct drm_framebuffer *fb = state->fb;
12198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12199 struct intel_plane *intel_plane = to_intel_plane(plane);
12200 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12201 struct drm_i915_gem_object *obj = intel_fb->obj;
12202 int crtc_w, crtc_h;
12204 crtc->cursor_x = state->orig_dst.x1;
12205 crtc->cursor_y = state->orig_dst.y1;
12207 intel_plane->crtc_x = state->orig_dst.x1;
12208 intel_plane->crtc_y = state->orig_dst.y1;
12209 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
12210 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
12211 intel_plane->src_x = state->orig_src.x1;
12212 intel_plane->src_y = state->orig_src.y1;
12213 intel_plane->src_w = drm_rect_width(&state->orig_src);
12214 intel_plane->src_h = drm_rect_height(&state->orig_src);
12215 intel_plane->obj = obj;
12217 if (fb != crtc->cursor->fb) {
12218 crtc_w = drm_rect_width(&state->orig_dst);
12219 crtc_h = drm_rect_height(&state->orig_dst);
12220 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12222 intel_crtc_update_cursor(crtc, state->visible);
12224 intel_frontbuffer_flip(crtc->dev,
12225 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12232 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12233 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12234 unsigned int crtc_w, unsigned int crtc_h,
12235 uint32_t src_x, uint32_t src_y,
12236 uint32_t src_w, uint32_t src_h)
12238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12239 struct intel_plane_state state;
12245 /* sample coordinates in 16.16 fixed point */
12246 state.src.x1 = src_x;
12247 state.src.x2 = src_x + src_w;
12248 state.src.y1 = src_y;
12249 state.src.y2 = src_y + src_h;
12251 /* integer pixels */
12252 state.dst.x1 = crtc_x;
12253 state.dst.x2 = crtc_x + crtc_w;
12254 state.dst.y1 = crtc_y;
12255 state.dst.y2 = crtc_y + crtc_h;
12259 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12260 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12262 state.orig_src = state.src;
12263 state.orig_dst = state.dst;
12265 ret = intel_check_cursor_plane(plane, &state);
12269 return intel_commit_cursor_plane(plane, &state);
12272 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12273 .update_plane = intel_cursor_plane_update,
12274 .disable_plane = intel_cursor_plane_disable,
12275 .destroy = intel_plane_destroy,
12276 .set_property = intel_plane_set_property,
12279 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12282 struct intel_plane *cursor;
12284 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12285 if (cursor == NULL)
12288 cursor->can_scale = false;
12289 cursor->max_downscale = 1;
12290 cursor->pipe = pipe;
12291 cursor->plane = pipe;
12292 cursor->rotation = BIT(DRM_ROTATE_0);
12294 drm_universal_plane_init(dev, &cursor->base, 0,
12295 &intel_cursor_plane_funcs,
12296 intel_cursor_formats,
12297 ARRAY_SIZE(intel_cursor_formats),
12298 DRM_PLANE_TYPE_CURSOR);
12300 if (INTEL_INFO(dev)->gen >= 4) {
12301 if (!dev->mode_config.rotation_property)
12302 dev->mode_config.rotation_property =
12303 drm_mode_create_rotation_property(dev,
12304 BIT(DRM_ROTATE_0) |
12305 BIT(DRM_ROTATE_180));
12306 if (dev->mode_config.rotation_property)
12307 drm_object_attach_property(&cursor->base.base,
12308 dev->mode_config.rotation_property,
12312 return &cursor->base;
12315 static void intel_crtc_init(struct drm_device *dev, int pipe)
12317 struct drm_i915_private *dev_priv = dev->dev_private;
12318 struct intel_crtc *intel_crtc;
12319 struct drm_plane *primary = NULL;
12320 struct drm_plane *cursor = NULL;
12323 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12324 if (intel_crtc == NULL)
12327 primary = intel_primary_plane_create(dev, pipe);
12331 cursor = intel_cursor_plane_create(dev, pipe);
12335 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12336 cursor, &intel_crtc_funcs);
12340 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12341 for (i = 0; i < 256; i++) {
12342 intel_crtc->lut_r[i] = i;
12343 intel_crtc->lut_g[i] = i;
12344 intel_crtc->lut_b[i] = i;
12348 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12349 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12351 intel_crtc->pipe = pipe;
12352 intel_crtc->plane = pipe;
12353 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12354 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12355 intel_crtc->plane = !pipe;
12358 intel_crtc->cursor_base = ~0;
12359 intel_crtc->cursor_cntl = ~0;
12360 intel_crtc->cursor_size = ~0;
12362 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12363 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12364 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12365 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12367 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12369 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12371 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12376 drm_plane_cleanup(primary);
12378 drm_plane_cleanup(cursor);
12382 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12384 struct drm_encoder *encoder = connector->base.encoder;
12385 struct drm_device *dev = connector->base.dev;
12387 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12389 if (!encoder || WARN_ON(!encoder->crtc))
12390 return INVALID_PIPE;
12392 return to_intel_crtc(encoder->crtc)->pipe;
12395 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12396 struct drm_file *file)
12398 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12399 struct drm_crtc *drmmode_crtc;
12400 struct intel_crtc *crtc;
12402 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12405 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12407 if (!drmmode_crtc) {
12408 DRM_ERROR("no such CRTC id\n");
12412 crtc = to_intel_crtc(drmmode_crtc);
12413 pipe_from_crtc_id->pipe = crtc->pipe;
12418 static int intel_encoder_clones(struct intel_encoder *encoder)
12420 struct drm_device *dev = encoder->base.dev;
12421 struct intel_encoder *source_encoder;
12422 int index_mask = 0;
12425 for_each_intel_encoder(dev, source_encoder) {
12426 if (encoders_cloneable(encoder, source_encoder))
12427 index_mask |= (1 << entry);
12435 static bool has_edp_a(struct drm_device *dev)
12437 struct drm_i915_private *dev_priv = dev->dev_private;
12439 if (!IS_MOBILE(dev))
12442 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12445 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12451 const char *intel_output_name(int output)
12453 static const char *names[] = {
12454 [INTEL_OUTPUT_UNUSED] = "Unused",
12455 [INTEL_OUTPUT_ANALOG] = "Analog",
12456 [INTEL_OUTPUT_DVO] = "DVO",
12457 [INTEL_OUTPUT_SDVO] = "SDVO",
12458 [INTEL_OUTPUT_LVDS] = "LVDS",
12459 [INTEL_OUTPUT_TVOUT] = "TV",
12460 [INTEL_OUTPUT_HDMI] = "HDMI",
12461 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12462 [INTEL_OUTPUT_EDP] = "eDP",
12463 [INTEL_OUTPUT_DSI] = "DSI",
12464 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12467 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12470 return names[output];
12473 static bool intel_crt_present(struct drm_device *dev)
12475 struct drm_i915_private *dev_priv = dev->dev_private;
12477 if (INTEL_INFO(dev)->gen >= 9)
12480 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12483 if (IS_CHERRYVIEW(dev))
12486 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12492 static void intel_setup_outputs(struct drm_device *dev)
12494 struct drm_i915_private *dev_priv = dev->dev_private;
12495 struct intel_encoder *encoder;
12496 bool dpd_is_edp = false;
12498 intel_lvds_init(dev);
12500 if (intel_crt_present(dev))
12501 intel_crt_init(dev);
12503 if (HAS_DDI(dev)) {
12506 /* Haswell uses DDI functions to detect digital outputs */
12507 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12508 /* DDI A only supports eDP */
12510 intel_ddi_init(dev, PORT_A);
12512 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12514 found = I915_READ(SFUSE_STRAP);
12516 if (found & SFUSE_STRAP_DDIB_DETECTED)
12517 intel_ddi_init(dev, PORT_B);
12518 if (found & SFUSE_STRAP_DDIC_DETECTED)
12519 intel_ddi_init(dev, PORT_C);
12520 if (found & SFUSE_STRAP_DDID_DETECTED)
12521 intel_ddi_init(dev, PORT_D);
12522 } else if (HAS_PCH_SPLIT(dev)) {
12524 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12526 if (has_edp_a(dev))
12527 intel_dp_init(dev, DP_A, PORT_A);
12529 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12530 /* PCH SDVOB multiplex with HDMIB */
12531 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12533 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12534 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12535 intel_dp_init(dev, PCH_DP_B, PORT_B);
12538 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12539 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12541 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12542 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12544 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12545 intel_dp_init(dev, PCH_DP_C, PORT_C);
12547 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12548 intel_dp_init(dev, PCH_DP_D, PORT_D);
12549 } else if (IS_VALLEYVIEW(dev)) {
12551 * The DP_DETECTED bit is the latched state of the DDC
12552 * SDA pin at boot. However since eDP doesn't require DDC
12553 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12554 * eDP ports may have been muxed to an alternate function.
12555 * Thus we can't rely on the DP_DETECTED bit alone to detect
12556 * eDP ports. Consult the VBT as well as DP_DETECTED to
12557 * detect eDP ports.
12559 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12560 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12562 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12563 intel_dp_is_edp(dev, PORT_B))
12564 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12566 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12567 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12569 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12570 intel_dp_is_edp(dev, PORT_C))
12571 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12573 if (IS_CHERRYVIEW(dev)) {
12574 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12575 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12577 /* eDP not supported on port D, so don't check VBT */
12578 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12579 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12582 intel_dsi_init(dev);
12583 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12584 bool found = false;
12586 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12587 DRM_DEBUG_KMS("probing SDVOB\n");
12588 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12589 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12590 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12591 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12594 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12595 intel_dp_init(dev, DP_B, PORT_B);
12598 /* Before G4X SDVOC doesn't have its own detect register */
12600 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12601 DRM_DEBUG_KMS("probing SDVOC\n");
12602 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12605 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12607 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12608 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12609 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12611 if (SUPPORTS_INTEGRATED_DP(dev))
12612 intel_dp_init(dev, DP_C, PORT_C);
12615 if (SUPPORTS_INTEGRATED_DP(dev) &&
12616 (I915_READ(DP_D) & DP_DETECTED))
12617 intel_dp_init(dev, DP_D, PORT_D);
12618 } else if (IS_GEN2(dev))
12619 intel_dvo_init(dev);
12621 if (SUPPORTS_TV(dev))
12622 intel_tv_init(dev);
12624 intel_psr_init(dev);
12626 for_each_intel_encoder(dev, encoder) {
12627 encoder->base.possible_crtcs = encoder->crtc_mask;
12628 encoder->base.possible_clones =
12629 intel_encoder_clones(encoder);
12632 intel_init_pch_refclk(dev);
12634 drm_helper_move_panel_connectors_to_head(dev);
12637 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12639 struct drm_device *dev = fb->dev;
12640 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12642 drm_framebuffer_cleanup(fb);
12643 mutex_lock(&dev->struct_mutex);
12644 WARN_ON(!intel_fb->obj->framebuffer_references--);
12645 drm_gem_object_unreference(&intel_fb->obj->base);
12646 mutex_unlock(&dev->struct_mutex);
12650 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12651 struct drm_file *file,
12652 unsigned int *handle)
12654 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12655 struct drm_i915_gem_object *obj = intel_fb->obj;
12657 return drm_gem_handle_create(file, &obj->base, handle);
12660 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12661 .destroy = intel_user_framebuffer_destroy,
12662 .create_handle = intel_user_framebuffer_create_handle,
12665 static int intel_framebuffer_init(struct drm_device *dev,
12666 struct intel_framebuffer *intel_fb,
12667 struct drm_mode_fb_cmd2 *mode_cmd,
12668 struct drm_i915_gem_object *obj)
12670 int aligned_height;
12674 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12676 if (obj->tiling_mode == I915_TILING_Y) {
12677 DRM_DEBUG("hardware does not support tiling Y\n");
12681 if (mode_cmd->pitches[0] & 63) {
12682 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12683 mode_cmd->pitches[0]);
12687 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12688 pitch_limit = 32*1024;
12689 } else if (INTEL_INFO(dev)->gen >= 4) {
12690 if (obj->tiling_mode)
12691 pitch_limit = 16*1024;
12693 pitch_limit = 32*1024;
12694 } else if (INTEL_INFO(dev)->gen >= 3) {
12695 if (obj->tiling_mode)
12696 pitch_limit = 8*1024;
12698 pitch_limit = 16*1024;
12700 /* XXX DSPC is limited to 4k tiled */
12701 pitch_limit = 8*1024;
12703 if (mode_cmd->pitches[0] > pitch_limit) {
12704 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12705 obj->tiling_mode ? "tiled" : "linear",
12706 mode_cmd->pitches[0], pitch_limit);
12710 if (obj->tiling_mode != I915_TILING_NONE &&
12711 mode_cmd->pitches[0] != obj->stride) {
12712 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12713 mode_cmd->pitches[0], obj->stride);
12717 /* Reject formats not supported by any plane early. */
12718 switch (mode_cmd->pixel_format) {
12719 case DRM_FORMAT_C8:
12720 case DRM_FORMAT_RGB565:
12721 case DRM_FORMAT_XRGB8888:
12722 case DRM_FORMAT_ARGB8888:
12724 case DRM_FORMAT_XRGB1555:
12725 case DRM_FORMAT_ARGB1555:
12726 if (INTEL_INFO(dev)->gen > 3) {
12727 DRM_DEBUG("unsupported pixel format: %s\n",
12728 drm_get_format_name(mode_cmd->pixel_format));
12732 case DRM_FORMAT_XBGR8888:
12733 case DRM_FORMAT_ABGR8888:
12734 case DRM_FORMAT_XRGB2101010:
12735 case DRM_FORMAT_ARGB2101010:
12736 case DRM_FORMAT_XBGR2101010:
12737 case DRM_FORMAT_ABGR2101010:
12738 if (INTEL_INFO(dev)->gen < 4) {
12739 DRM_DEBUG("unsupported pixel format: %s\n",
12740 drm_get_format_name(mode_cmd->pixel_format));
12744 case DRM_FORMAT_YUYV:
12745 case DRM_FORMAT_UYVY:
12746 case DRM_FORMAT_YVYU:
12747 case DRM_FORMAT_VYUY:
12748 if (INTEL_INFO(dev)->gen < 5) {
12749 DRM_DEBUG("unsupported pixel format: %s\n",
12750 drm_get_format_name(mode_cmd->pixel_format));
12755 DRM_DEBUG("unsupported pixel format: %s\n",
12756 drm_get_format_name(mode_cmd->pixel_format));
12760 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12761 if (mode_cmd->offsets[0] != 0)
12764 aligned_height = intel_align_height(dev, mode_cmd->height,
12766 /* FIXME drm helper for size checks (especially planar formats)? */
12767 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12770 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12771 intel_fb->obj = obj;
12772 intel_fb->obj->framebuffer_references++;
12774 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12776 DRM_ERROR("framebuffer init failed %d\n", ret);
12783 static struct drm_framebuffer *
12784 intel_user_framebuffer_create(struct drm_device *dev,
12785 struct drm_file *filp,
12786 struct drm_mode_fb_cmd2 *mode_cmd)
12788 struct drm_i915_gem_object *obj;
12790 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12791 mode_cmd->handles[0]));
12792 if (&obj->base == NULL)
12793 return ERR_PTR(-ENOENT);
12795 return intel_framebuffer_create(dev, mode_cmd, obj);
12798 #ifndef CONFIG_DRM_I915_FBDEV
12799 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12804 static const struct drm_mode_config_funcs intel_mode_funcs = {
12805 .fb_create = intel_user_framebuffer_create,
12806 .output_poll_changed = intel_fbdev_output_poll_changed,
12809 /* Set up chip specific display functions */
12810 static void intel_init_display(struct drm_device *dev)
12812 struct drm_i915_private *dev_priv = dev->dev_private;
12814 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12815 dev_priv->display.find_dpll = g4x_find_best_dpll;
12816 else if (IS_CHERRYVIEW(dev))
12817 dev_priv->display.find_dpll = chv_find_best_dpll;
12818 else if (IS_VALLEYVIEW(dev))
12819 dev_priv->display.find_dpll = vlv_find_best_dpll;
12820 else if (IS_PINEVIEW(dev))
12821 dev_priv->display.find_dpll = pnv_find_best_dpll;
12823 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12825 if (HAS_DDI(dev)) {
12826 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12827 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12828 dev_priv->display.crtc_compute_clock =
12829 haswell_crtc_compute_clock;
12830 dev_priv->display.crtc_enable = haswell_crtc_enable;
12831 dev_priv->display.crtc_disable = haswell_crtc_disable;
12832 dev_priv->display.off = ironlake_crtc_off;
12833 if (INTEL_INFO(dev)->gen >= 9)
12834 dev_priv->display.update_primary_plane =
12835 skylake_update_primary_plane;
12837 dev_priv->display.update_primary_plane =
12838 ironlake_update_primary_plane;
12839 } else if (HAS_PCH_SPLIT(dev)) {
12840 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12841 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12842 dev_priv->display.crtc_compute_clock =
12843 ironlake_crtc_compute_clock;
12844 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12845 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12846 dev_priv->display.off = ironlake_crtc_off;
12847 dev_priv->display.update_primary_plane =
12848 ironlake_update_primary_plane;
12849 } else if (IS_VALLEYVIEW(dev)) {
12850 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12851 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12852 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12853 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12854 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12855 dev_priv->display.off = i9xx_crtc_off;
12856 dev_priv->display.update_primary_plane =
12857 i9xx_update_primary_plane;
12859 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12860 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12861 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12862 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12863 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12864 dev_priv->display.off = i9xx_crtc_off;
12865 dev_priv->display.update_primary_plane =
12866 i9xx_update_primary_plane;
12869 /* Returns the core display clock speed */
12870 if (IS_VALLEYVIEW(dev))
12871 dev_priv->display.get_display_clock_speed =
12872 valleyview_get_display_clock_speed;
12873 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12874 dev_priv->display.get_display_clock_speed =
12875 i945_get_display_clock_speed;
12876 else if (IS_I915G(dev))
12877 dev_priv->display.get_display_clock_speed =
12878 i915_get_display_clock_speed;
12879 else if (IS_I945GM(dev) || IS_845G(dev))
12880 dev_priv->display.get_display_clock_speed =
12881 i9xx_misc_get_display_clock_speed;
12882 else if (IS_PINEVIEW(dev))
12883 dev_priv->display.get_display_clock_speed =
12884 pnv_get_display_clock_speed;
12885 else if (IS_I915GM(dev))
12886 dev_priv->display.get_display_clock_speed =
12887 i915gm_get_display_clock_speed;
12888 else if (IS_I865G(dev))
12889 dev_priv->display.get_display_clock_speed =
12890 i865_get_display_clock_speed;
12891 else if (IS_I85X(dev))
12892 dev_priv->display.get_display_clock_speed =
12893 i855_get_display_clock_speed;
12894 else /* 852, 830 */
12895 dev_priv->display.get_display_clock_speed =
12896 i830_get_display_clock_speed;
12898 if (IS_GEN5(dev)) {
12899 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12900 } else if (IS_GEN6(dev)) {
12901 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12902 } else if (IS_IVYBRIDGE(dev)) {
12903 /* FIXME: detect B0+ stepping and use auto training */
12904 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12905 dev_priv->display.modeset_global_resources =
12906 ivb_modeset_global_resources;
12907 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12908 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12909 } else if (IS_VALLEYVIEW(dev)) {
12910 dev_priv->display.modeset_global_resources =
12911 valleyview_modeset_global_resources;
12914 /* Default just returns -ENODEV to indicate unsupported */
12915 dev_priv->display.queue_flip = intel_default_queue_flip;
12917 switch (INTEL_INFO(dev)->gen) {
12919 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12923 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12928 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12932 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12935 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12936 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12939 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12943 intel_panel_init_backlight_funcs(dev);
12945 mutex_init(&dev_priv->pps_mutex);
12949 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12950 * resume, or other times. This quirk makes sure that's the case for
12951 * affected systems.
12953 static void quirk_pipea_force(struct drm_device *dev)
12955 struct drm_i915_private *dev_priv = dev->dev_private;
12957 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12958 DRM_INFO("applying pipe a force quirk\n");
12961 static void quirk_pipeb_force(struct drm_device *dev)
12963 struct drm_i915_private *dev_priv = dev->dev_private;
12965 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12966 DRM_INFO("applying pipe b force quirk\n");
12970 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12972 static void quirk_ssc_force_disable(struct drm_device *dev)
12974 struct drm_i915_private *dev_priv = dev->dev_private;
12975 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12976 DRM_INFO("applying lvds SSC disable quirk\n");
12980 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12983 static void quirk_invert_brightness(struct drm_device *dev)
12985 struct drm_i915_private *dev_priv = dev->dev_private;
12986 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12987 DRM_INFO("applying inverted panel brightness quirk\n");
12990 /* Some VBT's incorrectly indicate no backlight is present */
12991 static void quirk_backlight_present(struct drm_device *dev)
12993 struct drm_i915_private *dev_priv = dev->dev_private;
12994 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12995 DRM_INFO("applying backlight present quirk\n");
12998 struct intel_quirk {
13000 int subsystem_vendor;
13001 int subsystem_device;
13002 void (*hook)(struct drm_device *dev);
13005 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13006 struct intel_dmi_quirk {
13007 void (*hook)(struct drm_device *dev);
13008 const struct dmi_system_id (*dmi_id_list)[];
13011 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13013 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13017 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13019 .dmi_id_list = &(const struct dmi_system_id[]) {
13021 .callback = intel_dmi_reverse_brightness,
13022 .ident = "NCR Corporation",
13023 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13024 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13027 { } /* terminating entry */
13029 .hook = quirk_invert_brightness,
13033 static struct intel_quirk intel_quirks[] = {
13034 /* HP Mini needs pipe A force quirk (LP: #322104) */
13035 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13037 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13038 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13040 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13041 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13043 /* 830 needs to leave pipe A & dpll A up */
13044 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13046 /* 830 needs to leave pipe B & dpll B up */
13047 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13049 /* Lenovo U160 cannot use SSC on LVDS */
13050 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13052 /* Sony Vaio Y cannot use SSC on LVDS */
13053 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13055 /* Acer Aspire 5734Z must invert backlight brightness */
13056 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13058 /* Acer/eMachines G725 */
13059 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13061 /* Acer/eMachines e725 */
13062 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13064 /* Acer/Packard Bell NCL20 */
13065 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13067 /* Acer Aspire 4736Z */
13068 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13070 /* Acer Aspire 5336 */
13071 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13073 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13074 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13076 /* Acer C720 Chromebook (Core i3 4005U) */
13077 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13079 /* Apple Macbook 2,1 (Core 2 T7400) */
13080 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13082 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13083 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13085 /* HP Chromebook 14 (Celeron 2955U) */
13086 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13089 static void intel_init_quirks(struct drm_device *dev)
13091 struct pci_dev *d = dev->pdev;
13094 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13095 struct intel_quirk *q = &intel_quirks[i];
13097 if (d->device == q->device &&
13098 (d->subsystem_vendor == q->subsystem_vendor ||
13099 q->subsystem_vendor == PCI_ANY_ID) &&
13100 (d->subsystem_device == q->subsystem_device ||
13101 q->subsystem_device == PCI_ANY_ID))
13104 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13105 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13106 intel_dmi_quirks[i].hook(dev);
13110 /* Disable the VGA plane that we never use */
13111 static void i915_disable_vga(struct drm_device *dev)
13113 struct drm_i915_private *dev_priv = dev->dev_private;
13115 u32 vga_reg = i915_vgacntrl_reg(dev);
13117 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13118 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13119 outb(SR01, VGA_SR_INDEX);
13120 sr1 = inb(VGA_SR_DATA);
13121 outb(sr1 | 1<<5, VGA_SR_DATA);
13122 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13126 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
13127 * from S3 without preserving (some of?) the other bits.
13129 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
13130 POSTING_READ(vga_reg);
13133 void intel_modeset_init_hw(struct drm_device *dev)
13135 intel_prepare_ddi(dev);
13137 if (IS_VALLEYVIEW(dev))
13138 vlv_update_cdclk(dev);
13140 intel_init_clock_gating(dev);
13142 intel_enable_gt_powersave(dev);
13145 void intel_modeset_init(struct drm_device *dev)
13147 struct drm_i915_private *dev_priv = dev->dev_private;
13150 struct intel_crtc *crtc;
13152 drm_mode_config_init(dev);
13154 dev->mode_config.min_width = 0;
13155 dev->mode_config.min_height = 0;
13157 dev->mode_config.preferred_depth = 24;
13158 dev->mode_config.prefer_shadow = 1;
13160 dev->mode_config.funcs = &intel_mode_funcs;
13162 intel_init_quirks(dev);
13164 intel_init_pm(dev);
13166 if (INTEL_INFO(dev)->num_pipes == 0)
13169 intel_init_display(dev);
13170 intel_init_audio(dev);
13172 if (IS_GEN2(dev)) {
13173 dev->mode_config.max_width = 2048;
13174 dev->mode_config.max_height = 2048;
13175 } else if (IS_GEN3(dev)) {
13176 dev->mode_config.max_width = 4096;
13177 dev->mode_config.max_height = 4096;
13179 dev->mode_config.max_width = 8192;
13180 dev->mode_config.max_height = 8192;
13183 if (IS_845G(dev) || IS_I865G(dev)) {
13184 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13185 dev->mode_config.cursor_height = 1023;
13186 } else if (IS_GEN2(dev)) {
13187 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13188 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13190 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13191 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13194 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13196 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13197 INTEL_INFO(dev)->num_pipes,
13198 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13200 for_each_pipe(dev_priv, pipe) {
13201 intel_crtc_init(dev, pipe);
13202 for_each_sprite(pipe, sprite) {
13203 ret = intel_plane_init(dev, pipe, sprite);
13205 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13206 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13210 intel_init_dpio(dev);
13212 intel_shared_dpll_init(dev);
13214 /* save the BIOS value before clobbering it */
13215 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13216 /* Just disable it once at startup */
13217 i915_disable_vga(dev);
13218 intel_setup_outputs(dev);
13220 /* Just in case the BIOS is doing something questionable. */
13221 intel_disable_fbc(dev);
13223 drm_modeset_lock_all(dev);
13224 intel_modeset_setup_hw_state(dev, false);
13225 drm_modeset_unlock_all(dev);
13227 for_each_intel_crtc(dev, crtc) {
13232 * Note that reserving the BIOS fb up front prevents us
13233 * from stuffing other stolen allocations like the ring
13234 * on top. This prevents some ugliness at boot time, and
13235 * can even allow for smooth boot transitions if the BIOS
13236 * fb is large enough for the active pipe configuration.
13238 if (dev_priv->display.get_plane_config) {
13239 dev_priv->display.get_plane_config(crtc,
13240 &crtc->plane_config);
13242 * If the fb is shared between multiple heads, we'll
13243 * just get the first one.
13245 intel_find_plane_obj(crtc, &crtc->plane_config);
13250 static void intel_enable_pipe_a(struct drm_device *dev)
13252 struct intel_connector *connector;
13253 struct drm_connector *crt = NULL;
13254 struct intel_load_detect_pipe load_detect_temp;
13255 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13257 /* We can't just switch on the pipe A, we need to set things up with a
13258 * proper mode and output configuration. As a gross hack, enable pipe A
13259 * by enabling the load detect pipe once. */
13260 list_for_each_entry(connector,
13261 &dev->mode_config.connector_list,
13263 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13264 crt = &connector->base;
13272 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13273 intel_release_load_detect_pipe(crt, &load_detect_temp);
13277 intel_check_plane_mapping(struct intel_crtc *crtc)
13279 struct drm_device *dev = crtc->base.dev;
13280 struct drm_i915_private *dev_priv = dev->dev_private;
13283 if (INTEL_INFO(dev)->num_pipes == 1)
13286 reg = DSPCNTR(!crtc->plane);
13287 val = I915_READ(reg);
13289 if ((val & DISPLAY_PLANE_ENABLE) &&
13290 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13296 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13298 struct drm_device *dev = crtc->base.dev;
13299 struct drm_i915_private *dev_priv = dev->dev_private;
13302 /* Clear any frame start delays used for debugging left by the BIOS */
13303 reg = PIPECONF(crtc->config.cpu_transcoder);
13304 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13306 /* restore vblank interrupts to correct state */
13307 if (crtc->active) {
13308 update_scanline_offset(crtc);
13309 drm_vblank_on(dev, crtc->pipe);
13311 drm_vblank_off(dev, crtc->pipe);
13313 /* We need to sanitize the plane -> pipe mapping first because this will
13314 * disable the crtc (and hence change the state) if it is wrong. Note
13315 * that gen4+ has a fixed plane -> pipe mapping. */
13316 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13317 struct intel_connector *connector;
13320 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13321 crtc->base.base.id);
13323 /* Pipe has the wrong plane attached and the plane is active.
13324 * Temporarily change the plane mapping and disable everything
13326 plane = crtc->plane;
13327 crtc->plane = !plane;
13328 crtc->primary_enabled = true;
13329 dev_priv->display.crtc_disable(&crtc->base);
13330 crtc->plane = plane;
13332 /* ... and break all links. */
13333 list_for_each_entry(connector, &dev->mode_config.connector_list,
13335 if (connector->encoder->base.crtc != &crtc->base)
13338 connector->base.dpms = DRM_MODE_DPMS_OFF;
13339 connector->base.encoder = NULL;
13341 /* multiple connectors may have the same encoder:
13342 * handle them and break crtc link separately */
13343 list_for_each_entry(connector, &dev->mode_config.connector_list,
13345 if (connector->encoder->base.crtc == &crtc->base) {
13346 connector->encoder->base.crtc = NULL;
13347 connector->encoder->connectors_active = false;
13350 WARN_ON(crtc->active);
13351 crtc->base.enabled = false;
13354 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13355 crtc->pipe == PIPE_A && !crtc->active) {
13356 /* BIOS forgot to enable pipe A, this mostly happens after
13357 * resume. Force-enable the pipe to fix this, the update_dpms
13358 * call below we restore the pipe to the right state, but leave
13359 * the required bits on. */
13360 intel_enable_pipe_a(dev);
13363 /* Adjust the state of the output pipe according to whether we
13364 * have active connectors/encoders. */
13365 intel_crtc_update_dpms(&crtc->base);
13367 if (crtc->active != crtc->base.enabled) {
13368 struct intel_encoder *encoder;
13370 /* This can happen either due to bugs in the get_hw_state
13371 * functions or because the pipe is force-enabled due to the
13373 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13374 crtc->base.base.id,
13375 crtc->base.enabled ? "enabled" : "disabled",
13376 crtc->active ? "enabled" : "disabled");
13378 crtc->base.enabled = crtc->active;
13380 /* Because we only establish the connector -> encoder ->
13381 * crtc links if something is active, this means the
13382 * crtc is now deactivated. Break the links. connector
13383 * -> encoder links are only establish when things are
13384 * actually up, hence no need to break them. */
13385 WARN_ON(crtc->active);
13387 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13388 WARN_ON(encoder->connectors_active);
13389 encoder->base.crtc = NULL;
13393 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13395 * We start out with underrun reporting disabled to avoid races.
13396 * For correct bookkeeping mark this on active crtcs.
13398 * Also on gmch platforms we dont have any hardware bits to
13399 * disable the underrun reporting. Which means we need to start
13400 * out with underrun reporting disabled also on inactive pipes,
13401 * since otherwise we'll complain about the garbage we read when
13402 * e.g. coming up after runtime pm.
13404 * No protection against concurrent access is required - at
13405 * worst a fifo underrun happens which also sets this to false.
13407 crtc->cpu_fifo_underrun_disabled = true;
13408 crtc->pch_fifo_underrun_disabled = true;
13412 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13414 struct intel_connector *connector;
13415 struct drm_device *dev = encoder->base.dev;
13417 /* We need to check both for a crtc link (meaning that the
13418 * encoder is active and trying to read from a pipe) and the
13419 * pipe itself being active. */
13420 bool has_active_crtc = encoder->base.crtc &&
13421 to_intel_crtc(encoder->base.crtc)->active;
13423 if (encoder->connectors_active && !has_active_crtc) {
13424 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13425 encoder->base.base.id,
13426 encoder->base.name);
13428 /* Connector is active, but has no active pipe. This is
13429 * fallout from our resume register restoring. Disable
13430 * the encoder manually again. */
13431 if (encoder->base.crtc) {
13432 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13433 encoder->base.base.id,
13434 encoder->base.name);
13435 encoder->disable(encoder);
13436 if (encoder->post_disable)
13437 encoder->post_disable(encoder);
13439 encoder->base.crtc = NULL;
13440 encoder->connectors_active = false;
13442 /* Inconsistent output/port/pipe state happens presumably due to
13443 * a bug in one of the get_hw_state functions. Or someplace else
13444 * in our code, like the register restore mess on resume. Clamp
13445 * things to off as a safer default. */
13446 list_for_each_entry(connector,
13447 &dev->mode_config.connector_list,
13449 if (connector->encoder != encoder)
13451 connector->base.dpms = DRM_MODE_DPMS_OFF;
13452 connector->base.encoder = NULL;
13455 /* Enabled encoders without active connectors will be fixed in
13456 * the crtc fixup. */
13459 void i915_redisable_vga_power_on(struct drm_device *dev)
13461 struct drm_i915_private *dev_priv = dev->dev_private;
13462 u32 vga_reg = i915_vgacntrl_reg(dev);
13464 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13465 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13466 i915_disable_vga(dev);
13470 void i915_redisable_vga(struct drm_device *dev)
13472 struct drm_i915_private *dev_priv = dev->dev_private;
13474 /* This function can be called both from intel_modeset_setup_hw_state or
13475 * at a very early point in our resume sequence, where the power well
13476 * structures are not yet restored. Since this function is at a very
13477 * paranoid "someone might have enabled VGA while we were not looking"
13478 * level, just check if the power well is enabled instead of trying to
13479 * follow the "don't touch the power well if we don't need it" policy
13480 * the rest of the driver uses. */
13481 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13484 i915_redisable_vga_power_on(dev);
13487 static bool primary_get_hw_state(struct intel_crtc *crtc)
13489 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13494 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13497 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13499 struct drm_i915_private *dev_priv = dev->dev_private;
13501 struct intel_crtc *crtc;
13502 struct intel_encoder *encoder;
13503 struct intel_connector *connector;
13506 for_each_intel_crtc(dev, crtc) {
13507 memset(&crtc->config, 0, sizeof(crtc->config));
13509 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13511 crtc->active = dev_priv->display.get_pipe_config(crtc,
13514 crtc->base.enabled = crtc->active;
13515 crtc->primary_enabled = primary_get_hw_state(crtc);
13517 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13518 crtc->base.base.id,
13519 crtc->active ? "enabled" : "disabled");
13522 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13523 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13525 pll->on = pll->get_hw_state(dev_priv, pll,
13526 &pll->config.hw_state);
13528 pll->config.crtc_mask = 0;
13529 for_each_intel_crtc(dev, crtc) {
13530 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13532 pll->config.crtc_mask |= 1 << crtc->pipe;
13536 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13537 pll->name, pll->config.crtc_mask, pll->on);
13539 if (pll->config.crtc_mask)
13540 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13543 for_each_intel_encoder(dev, encoder) {
13546 if (encoder->get_hw_state(encoder, &pipe)) {
13547 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13548 encoder->base.crtc = &crtc->base;
13549 encoder->get_config(encoder, &crtc->config);
13551 encoder->base.crtc = NULL;
13554 encoder->connectors_active = false;
13555 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13556 encoder->base.base.id,
13557 encoder->base.name,
13558 encoder->base.crtc ? "enabled" : "disabled",
13562 list_for_each_entry(connector, &dev->mode_config.connector_list,
13564 if (connector->get_hw_state(connector)) {
13565 connector->base.dpms = DRM_MODE_DPMS_ON;
13566 connector->encoder->connectors_active = true;
13567 connector->base.encoder = &connector->encoder->base;
13569 connector->base.dpms = DRM_MODE_DPMS_OFF;
13570 connector->base.encoder = NULL;
13572 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13573 connector->base.base.id,
13574 connector->base.name,
13575 connector->base.encoder ? "enabled" : "disabled");
13579 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13580 * and i915 state tracking structures. */
13581 void intel_modeset_setup_hw_state(struct drm_device *dev,
13582 bool force_restore)
13584 struct drm_i915_private *dev_priv = dev->dev_private;
13586 struct intel_crtc *crtc;
13587 struct intel_encoder *encoder;
13590 intel_modeset_readout_hw_state(dev);
13593 * Now that we have the config, copy it to each CRTC struct
13594 * Note that this could go away if we move to using crtc_config
13595 * checking everywhere.
13597 for_each_intel_crtc(dev, crtc) {
13598 if (crtc->active && i915.fastboot) {
13599 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13600 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13601 crtc->base.base.id);
13602 drm_mode_debug_printmodeline(&crtc->base.mode);
13606 /* HW state is read out, now we need to sanitize this mess. */
13607 for_each_intel_encoder(dev, encoder) {
13608 intel_sanitize_encoder(encoder);
13611 for_each_pipe(dev_priv, pipe) {
13612 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13613 intel_sanitize_crtc(crtc);
13614 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13617 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13618 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13620 if (!pll->on || pll->active)
13623 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13625 pll->disable(dev_priv, pll);
13630 skl_wm_get_hw_state(dev);
13631 else if (HAS_PCH_SPLIT(dev))
13632 ilk_wm_get_hw_state(dev);
13634 if (force_restore) {
13635 i915_redisable_vga(dev);
13638 * We need to use raw interfaces for restoring state to avoid
13639 * checking (bogus) intermediate states.
13641 for_each_pipe(dev_priv, pipe) {
13642 struct drm_crtc *crtc =
13643 dev_priv->pipe_to_crtc_mapping[pipe];
13645 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13646 crtc->primary->fb);
13649 intel_modeset_update_staged_output_state(dev);
13652 intel_modeset_check_state(dev);
13655 void intel_modeset_gem_init(struct drm_device *dev)
13657 struct drm_i915_private *dev_priv = dev->dev_private;
13658 struct drm_crtc *c;
13659 struct drm_i915_gem_object *obj;
13661 mutex_lock(&dev->struct_mutex);
13662 intel_init_gt_powersave(dev);
13663 mutex_unlock(&dev->struct_mutex);
13666 * There may be no VBT; and if the BIOS enabled SSC we can
13667 * just keep using it to avoid unnecessary flicker. Whereas if the
13668 * BIOS isn't using it, don't assume it will work even if the VBT
13669 * indicates as much.
13671 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13672 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13675 intel_modeset_init_hw(dev);
13677 intel_setup_overlay(dev);
13680 * Make sure any fbs we allocated at startup are properly
13681 * pinned & fenced. When we do the allocation it's too early
13684 mutex_lock(&dev->struct_mutex);
13685 for_each_crtc(dev, c) {
13686 obj = intel_fb_obj(c->primary->fb);
13690 if (intel_pin_and_fence_fb_obj(c->primary,
13693 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13694 to_intel_crtc(c)->pipe);
13695 drm_framebuffer_unreference(c->primary->fb);
13696 c->primary->fb = NULL;
13699 mutex_unlock(&dev->struct_mutex);
13701 intel_backlight_register(dev);
13704 void intel_connector_unregister(struct intel_connector *intel_connector)
13706 struct drm_connector *connector = &intel_connector->base;
13708 intel_panel_destroy_backlight(connector);
13709 drm_connector_unregister(connector);
13712 void intel_modeset_cleanup(struct drm_device *dev)
13714 struct drm_i915_private *dev_priv = dev->dev_private;
13715 struct drm_connector *connector;
13717 intel_disable_gt_powersave(dev);
13719 intel_backlight_unregister(dev);
13722 * Interrupts and polling as the first thing to avoid creating havoc.
13723 * Too much stuff here (turning of connectors, ...) would
13724 * experience fancy races otherwise.
13726 intel_irq_uninstall(dev_priv);
13729 * Due to the hpd irq storm handling the hotplug work can re-arm the
13730 * poll handlers. Hence disable polling after hpd handling is shut down.
13732 drm_kms_helper_poll_fini(dev);
13734 mutex_lock(&dev->struct_mutex);
13736 intel_unregister_dsm_handler();
13738 intel_disable_fbc(dev);
13740 ironlake_teardown_rc6(dev);
13742 mutex_unlock(&dev->struct_mutex);
13744 /* flush any delayed tasks or pending work */
13745 flush_scheduled_work();
13747 /* destroy the backlight and sysfs files before encoders/connectors */
13748 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13749 struct intel_connector *intel_connector;
13751 intel_connector = to_intel_connector(connector);
13752 intel_connector->unregister(intel_connector);
13755 drm_mode_config_cleanup(dev);
13757 intel_cleanup_overlay(dev);
13759 mutex_lock(&dev->struct_mutex);
13760 intel_cleanup_gt_powersave(dev);
13761 mutex_unlock(&dev->struct_mutex);
13765 * Return which encoder is currently attached for connector.
13767 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13769 return &intel_attached_encoder(connector)->base;
13772 void intel_connector_attach_encoder(struct intel_connector *connector,
13773 struct intel_encoder *encoder)
13775 connector->encoder = encoder;
13776 drm_mode_connector_attach_encoder(&connector->base,
13781 * set vga decode state - true == enable VGA decode
13783 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13785 struct drm_i915_private *dev_priv = dev->dev_private;
13786 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13789 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13790 DRM_ERROR("failed to read control word\n");
13794 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13798 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13800 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13802 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13803 DRM_ERROR("failed to write control word\n");
13810 struct intel_display_error_state {
13812 u32 power_well_driver;
13814 int num_transcoders;
13816 struct intel_cursor_error_state {
13821 } cursor[I915_MAX_PIPES];
13823 struct intel_pipe_error_state {
13824 bool power_domain_on;
13827 } pipe[I915_MAX_PIPES];
13829 struct intel_plane_error_state {
13837 } plane[I915_MAX_PIPES];
13839 struct intel_transcoder_error_state {
13840 bool power_domain_on;
13841 enum transcoder cpu_transcoder;
13854 struct intel_display_error_state *
13855 intel_display_capture_error_state(struct drm_device *dev)
13857 struct drm_i915_private *dev_priv = dev->dev_private;
13858 struct intel_display_error_state *error;
13859 int transcoders[] = {
13867 if (INTEL_INFO(dev)->num_pipes == 0)
13870 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13874 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13875 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13877 for_each_pipe(dev_priv, i) {
13878 error->pipe[i].power_domain_on =
13879 __intel_display_power_is_enabled(dev_priv,
13880 POWER_DOMAIN_PIPE(i));
13881 if (!error->pipe[i].power_domain_on)
13884 error->cursor[i].control = I915_READ(CURCNTR(i));
13885 error->cursor[i].position = I915_READ(CURPOS(i));
13886 error->cursor[i].base = I915_READ(CURBASE(i));
13888 error->plane[i].control = I915_READ(DSPCNTR(i));
13889 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13890 if (INTEL_INFO(dev)->gen <= 3) {
13891 error->plane[i].size = I915_READ(DSPSIZE(i));
13892 error->plane[i].pos = I915_READ(DSPPOS(i));
13894 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13895 error->plane[i].addr = I915_READ(DSPADDR(i));
13896 if (INTEL_INFO(dev)->gen >= 4) {
13897 error->plane[i].surface = I915_READ(DSPSURF(i));
13898 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13901 error->pipe[i].source = I915_READ(PIPESRC(i));
13903 if (HAS_GMCH_DISPLAY(dev))
13904 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13907 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13908 if (HAS_DDI(dev_priv->dev))
13909 error->num_transcoders++; /* Account for eDP. */
13911 for (i = 0; i < error->num_transcoders; i++) {
13912 enum transcoder cpu_transcoder = transcoders[i];
13914 error->transcoder[i].power_domain_on =
13915 __intel_display_power_is_enabled(dev_priv,
13916 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13917 if (!error->transcoder[i].power_domain_on)
13920 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13922 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13923 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13924 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13925 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13926 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13927 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13928 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13934 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13937 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13938 struct drm_device *dev,
13939 struct intel_display_error_state *error)
13941 struct drm_i915_private *dev_priv = dev->dev_private;
13947 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13948 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13949 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13950 error->power_well_driver);
13951 for_each_pipe(dev_priv, i) {
13952 err_printf(m, "Pipe [%d]:\n", i);
13953 err_printf(m, " Power: %s\n",
13954 error->pipe[i].power_domain_on ? "on" : "off");
13955 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13956 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13958 err_printf(m, "Plane [%d]:\n", i);
13959 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13960 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13961 if (INTEL_INFO(dev)->gen <= 3) {
13962 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13963 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13965 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13966 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13967 if (INTEL_INFO(dev)->gen >= 4) {
13968 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13969 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13972 err_printf(m, "Cursor [%d]:\n", i);
13973 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13974 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13975 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13978 for (i = 0; i < error->num_transcoders; i++) {
13979 err_printf(m, "CPU transcoder: %c\n",
13980 transcoder_name(error->transcoder[i].cpu_transcoder));
13981 err_printf(m, " Power: %s\n",
13982 error->transcoder[i].power_domain_on ? "on" : "off");
13983 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13984 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13985 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13986 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13987 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13988 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13989 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13993 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13995 struct intel_crtc *crtc;
13997 for_each_intel_crtc(dev, crtc) {
13998 struct intel_unpin_work *work;
14000 spin_lock_irq(&dev->event_lock);
14002 work = crtc->unpin_work;
14004 if (work && work->event &&
14005 work->event->base.file_priv == file) {
14006 kfree(work->event);
14007 work->event = NULL;
14010 spin_unlock_irq(&dev->event_lock);