drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  45         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  46
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  51                                 struct intel_crtc_config *pipe_config);
  52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  53                                    struct intel_crtc_config *pipe_config);
  54
  55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  56                           int x, int y, struct drm_framebuffer *old_fb);
  57 static int intel_framebuffer_init(struct drm_device *dev,
  58                                   struct intel_framebuffer *ifb,
  59                                   struct drm_mode_fb_cmd2 *mode_cmd,
  60                                   struct drm_i915_gem_object *obj);
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74         intel_p2_t          p2;
  75 };
  76
  77 int
  78 intel_pch_rawclk(struct drm_device *dev)
  79 {
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81
  82         WARN_ON(!HAS_PCH_SPLIT(dev));
  83
  84         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  85 }
  86
  87 static inline u32 /* units of 100MHz */
  88 intel_fdi_link_freq(struct drm_device *dev)
  89 {
  90         if (IS_GEN5(dev)) {
  91                 struct drm_i915_private *dev_priv = dev->dev_private;
  92                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  93         } else
  94                 return 27;
  95 }
  96
  97 static const intel_limit_t intel_limits_i8xx_dac = {
  98         .dot = { .min = 25000, .max = 350000 },
  99         .vco = { .min = 908000, .max = 1512000 },
 100         .n = { .min = 2, .max = 16 },
 101         .m = { .min = 96, .max = 140 },
 102         .m1 = { .min = 18, .max = 26 },
 103         .m2 = { .min = 6, .max = 16 },
 104         .p = { .min = 4, .max = 128 },
 105         .p1 = { .min = 2, .max = 33 },
 106         .p2 = { .dot_limit = 165000,
 107                 .p2_slow = 4, .p2_fast = 2 },
 108 };
 109
 110 static const intel_limit_t intel_limits_i8xx_dvo = {
 111         .dot = { .min = 25000, .max = 350000 },
 112         .vco = { .min = 908000, .max = 1512000 },
 113         .n = { .min = 2, .max = 16 },
 114         .m = { .min = 96, .max = 140 },
 115         .m1 = { .min = 18, .max = 26 },
 116         .m2 = { .min = 6, .max = 16 },
 117         .p = { .min = 4, .max = 128 },
 118         .p1 = { .min = 2, .max = 33 },
 119         .p2 = { .dot_limit = 165000,
 120                 .p2_slow = 4, .p2_fast = 4 },
 121 };
 122
 123 static const intel_limit_t intel_limits_i8xx_lvds = {
 124         .dot = { .min = 25000, .max = 350000 },
 125         .vco = { .min = 908000, .max = 1512000 },
 126         .n = { .min = 2, .max = 16 },
 127         .m = { .min = 96, .max = 140 },
 128         .m1 = { .min = 18, .max = 26 },
 129         .m2 = { .min = 6, .max = 16 },
 130         .p = { .min = 4, .max = 128 },
 131         .p1 = { .min = 1, .max = 6 },
 132         .p2 = { .dot_limit = 165000,
 133                 .p2_slow = 14, .p2_fast = 7 },
 134 };
 135
 136 static const intel_limit_t intel_limits_i9xx_sdvo = {
 137         .dot = { .min = 20000, .max = 400000 },
 138         .vco = { .min = 1400000, .max = 2800000 },
 139         .n = { .min = 1, .max = 6 },
 140         .m = { .min = 70, .max = 120 },
 141         .m1 = { .min = 8, .max = 18 },
 142         .m2 = { .min = 3, .max = 7 },
 143         .p = { .min = 5, .max = 80 },
 144         .p1 = { .min = 1, .max = 8 },
 145         .p2 = { .dot_limit = 200000,
 146                 .p2_slow = 10, .p2_fast = 5 },
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 8, .max = 18 },
 155         .m2 = { .min = 3, .max = 7 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160 };
 161
 162
 163 static const intel_limit_t intel_limits_g4x_sdvo = {
 164         .dot = { .min = 25000, .max = 270000 },
 165         .vco = { .min = 1750000, .max = 3500000},
 166         .n = { .min = 1, .max = 4 },
 167         .m = { .min = 104, .max = 138 },
 168         .m1 = { .min = 17, .max = 23 },
 169         .m2 = { .min = 5, .max = 11 },
 170         .p = { .min = 10, .max = 30 },
 171         .p1 = { .min = 1, .max = 3},
 172         .p2 = { .dot_limit = 270000,
 173                 .p2_slow = 10,
 174                 .p2_fast = 10
 175         },
 176 };
 177
 178 static const intel_limit_t intel_limits_g4x_hdmi = {
 179         .dot = { .min = 22000, .max = 400000 },
 180         .vco = { .min = 1750000, .max = 3500000},
 181         .n = { .min = 1, .max = 4 },
 182         .m = { .min = 104, .max = 138 },
 183         .m1 = { .min = 16, .max = 23 },
 184         .m2 = { .min = 5, .max = 11 },
 185         .p = { .min = 5, .max = 80 },
 186         .p1 = { .min = 1, .max = 8},
 187         .p2 = { .dot_limit = 165000,
 188                 .p2_slow = 10, .p2_fast = 5 },
 189 };
 190
 191 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 192         .dot = { .min = 20000, .max = 115000 },
 193         .vco = { .min = 1750000, .max = 3500000 },
 194         .n = { .min = 1, .max = 3 },
 195         .m = { .min = 104, .max = 138 },
 196         .m1 = { .min = 17, .max = 23 },
 197         .m2 = { .min = 5, .max = 11 },
 198         .p = { .min = 28, .max = 112 },
 199         .p1 = { .min = 2, .max = 8 },
 200         .p2 = { .dot_limit = 0,
 201                 .p2_slow = 14, .p2_fast = 14
 202         },
 203 };
 204
 205 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 206         .dot = { .min = 80000, .max = 224000 },
 207         .vco = { .min = 1750000, .max = 3500000 },
 208         .n = { .min = 1, .max = 3 },
 209         .m = { .min = 104, .max = 138 },
 210         .m1 = { .min = 17, .max = 23 },
 211         .m2 = { .min = 5, .max = 11 },
 212         .p = { .min = 14, .max = 42 },
 213         .p1 = { .min = 2, .max = 6 },
 214         .p2 = { .dot_limit = 0,
 215                 .p2_slow = 7, .p2_fast = 7
 216         },
 217 };
 218
 219 static const intel_limit_t intel_limits_pineview_sdvo = {
 220         .dot = { .min = 20000, .max = 400000},
 221         .vco = { .min = 1700000, .max = 3500000 },
 222         /* Pineview's Ncounter is a ring counter */
 223         .n = { .min = 3, .max = 6 },
 224         .m = { .min = 2, .max = 256 },
 225         /* Pineview only has one combined m divider, which we treat as m2. */
 226         .m1 = { .min = 0, .max = 0 },
 227         .m2 = { .min = 0, .max = 254 },
 228         .p = { .min = 5, .max = 80 },
 229         .p1 = { .min = 1, .max = 8 },
 230         .p2 = { .dot_limit = 200000,
 231                 .p2_slow = 10, .p2_fast = 5 },
 232 };
 233
 234 static const intel_limit_t intel_limits_pineview_lvds = {
 235         .dot = { .min = 20000, .max = 400000 },
 236         .vco = { .min = 1700000, .max = 3500000 },
 237         .n = { .min = 3, .max = 6 },
 238         .m = { .min = 2, .max = 256 },
 239         .m1 = { .min = 0, .max = 0 },
 240         .m2 = { .min = 0, .max = 254 },
 241         .p = { .min = 7, .max = 112 },
 242         .p1 = { .min = 1, .max = 8 },
 243         .p2 = { .dot_limit = 112000,
 244                 .p2_slow = 14, .p2_fast = 14 },
 245 };
 246
 247 /* Ironlake / Sandybridge
 248  *
 249  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 250  * the range value for them is (actual_value - 2).
 251  */
 252 static const intel_limit_t intel_limits_ironlake_dac = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 1760000, .max = 3510000 },
 255         .n = { .min = 1, .max = 5 },
 256         .m = { .min = 79, .max = 127 },
 257         .m1 = { .min = 12, .max = 22 },
 258         .m2 = { .min = 5, .max = 9 },
 259         .p = { .min = 5, .max = 80 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 225000,
 262                 .p2_slow = 10, .p2_fast = 5 },
 263 };
 264
 265 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 266         .dot = { .min = 25000, .max = 350000 },
 267         .vco = { .min = 1760000, .max = 3510000 },
 268         .n = { .min = 1, .max = 3 },
 269         .m = { .min = 79, .max = 118 },
 270         .m1 = { .min = 12, .max = 22 },
 271         .m2 = { .min = 5, .max = 9 },
 272         .p = { .min = 28, .max = 112 },
 273         .p1 = { .min = 2, .max = 8 },
 274         .p2 = { .dot_limit = 225000,
 275                 .p2_slow = 14, .p2_fast = 14 },
 276 };
 277
 278 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 3 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 14, .max = 56 },
 286         .p1 = { .min = 2, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 7, .p2_fast = 7 },
 289 };
 290
 291 /* LVDS 100mhz refclk limits. */
 292 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 2 },
 296         .m = { .min = 79, .max = 126 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303 };
 304
 305 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 3 },
 309         .m = { .min = 79, .max = 126 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 14, .max = 42 },
 313         .p1 = { .min = 2, .max = 6 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 7, .p2_fast = 7 },
 316 };
 317
 318 static const intel_limit_t intel_limits_vlv = {
 319          /*
 320           * These are the data rate limits (measured in fast clocks)
 321           * since those are the strictest limits we have. The fast
 322           * clock and actual rate limits are more relaxed, so checking
 323           * them would make no difference.
 324           */
 325         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 326         .vco = { .min = 4000000, .max = 6000000 },
 327         .n = { .min = 1, .max = 7 },
 328         .m1 = { .min = 2, .max = 3 },
 329         .m2 = { .min = 11, .max = 156 },
 330         .p1 = { .min = 2, .max = 3 },
 331         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 332 };
 333
 334 static const intel_limit_t intel_limits_chv = {
 335         /*
 336          * These are the data rate limits (measured in fast clocks)
 337          * since those are the strictest limits we have.  The fast
 338          * clock and actual rate limits are more relaxed, so checking
 339          * them would make no difference.
 340          */
 341         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 342         .vco = { .min = 4860000, .max = 6700000 },
 343         .n = { .min = 1, .max = 1 },
 344         .m1 = { .min = 2, .max = 2 },
 345         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 346         .p1 = { .min = 2, .max = 4 },
 347         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 348 };
 349
 350 static void vlv_clock(int refclk, intel_clock_t *clock)
 351 {
 352         clock->m = clock->m1 * clock->m2;
 353         clock->p = clock->p1 * clock->p2;
 354         if (WARN_ON(clock->n == 0 || clock->p == 0))
 355                 return;
 356         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 357         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 358 }
 359
 360 /**
 361  * Returns whether any output on the specified pipe is of the specified type
 362  */
 363 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         struct intel_encoder *encoder;
 367
 368         for_each_encoder_on_crtc(dev, crtc, encoder)
 369                 if (encoder->type == type)
 370                         return true;
 371
 372         return false;
 373 }
 374
 375 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 376                                                 int refclk)
 377 {
 378         struct drm_device *dev = crtc->dev;
 379         const intel_limit_t *limit;
 380
 381         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 382                 if (intel_is_dual_link_lvds(dev)) {
 383                         if (refclk == 100000)
 384                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 385                         else
 386                                 limit = &intel_limits_ironlake_dual_lvds;
 387                 } else {
 388                         if (refclk == 100000)
 389                                 limit = &intel_limits_ironlake_single_lvds_100m;
 390                         else
 391                                 limit = &intel_limits_ironlake_single_lvds;
 392                 }
 393         } else
 394                 limit = &intel_limits_ironlake_dac;
 395
 396         return limit;
 397 }
 398
 399 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 400 {
 401         struct drm_device *dev = crtc->dev;
 402         const intel_limit_t *limit;
 403
 404         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 405                 if (intel_is_dual_link_lvds(dev))
 406                         limit = &intel_limits_g4x_dual_channel_lvds;
 407                 else
 408                         limit = &intel_limits_g4x_single_channel_lvds;
 409         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 410                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 411                 limit = &intel_limits_g4x_hdmi;
 412         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 413                 limit = &intel_limits_g4x_sdvo;
 414         } else /* The option is for other outputs */
 415                 limit = &intel_limits_i9xx_sdvo;
 416
 417         return limit;
 418 }
 419
 420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 421 {
 422         struct drm_device *dev = crtc->dev;
 423         const intel_limit_t *limit;
 424
 425         if (HAS_PCH_SPLIT(dev))
 426                 limit = intel_ironlake_limit(crtc, refclk);
 427         else if (IS_G4X(dev)) {
 428                 limit = intel_g4x_limit(crtc);
 429         } else if (IS_PINEVIEW(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_pineview_lvds;
 432                 else
 433                         limit = &intel_limits_pineview_sdvo;
 434         } else if (IS_CHERRYVIEW(dev)) {
 435                 limit = &intel_limits_chv;
 436         } else if (IS_VALLEYVIEW(dev)) {
 437                 limit = &intel_limits_vlv;
 438         } else if (!IS_GEN2(dev)) {
 439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 440                         limit = &intel_limits_i9xx_lvds;
 441                 else
 442                         limit = &intel_limits_i9xx_sdvo;
 443         } else {
 444                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 445                         limit = &intel_limits_i8xx_lvds;
 446                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 447                         limit = &intel_limits_i8xx_dvo;
 448                 else
 449                         limit = &intel_limits_i8xx_dac;
 450         }
 451         return limit;
 452 }
 453
 454 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 455 static void pineview_clock(int refclk, intel_clock_t *clock)
 456 {
 457         clock->m = clock->m2 + 2;
 458         clock->p = clock->p1 * clock->p2;
 459         if (WARN_ON(clock->n == 0 || clock->p == 0))
 460                 return;
 461         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 462         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 463 }
 464
 465 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 466 {
 467         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 468 }
 469
 470 static void i9xx_clock(int refclk, intel_clock_t *clock)
 471 {
 472         clock->m = i9xx_dpll_compute_m(clock);
 473         clock->p = clock->p1 * clock->p2;
 474         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 475                 return;
 476         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 477         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 478 }
 479
 480 static void chv_clock(int refclk, intel_clock_t *clock)
 481 {
 482         clock->m = clock->m1 * clock->m2;
 483         clock->p = clock->p1 * clock->p2;
 484         if (WARN_ON(clock->n == 0 || clock->p == 0))
 485                 return;
 486         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 487                         clock->n << 22);
 488         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 489 }
 490
 491 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 492 /**
 493  * Returns whether the given set of divisors are valid for a given refclk with
 494  * the given connectors.
 495  */
 496
 497 static bool intel_PLL_is_valid(struct drm_device *dev,
 498                                const intel_limit_t *limit,
 499                                const intel_clock_t *clock)
 500 {
 501         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 502                 INTELPllInvalid("n out of range\n");
 503         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 504                 INTELPllInvalid("p1 out of range\n");
 505         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 506                 INTELPllInvalid("m2 out of range\n");
 507         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 508                 INTELPllInvalid("m1 out of range\n");
 509
 510         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 511                 if (clock->m1 <= clock->m2)
 512                         INTELPllInvalid("m1 <= m2\n");
 513
 514         if (!IS_VALLEYVIEW(dev)) {
 515                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 516                         INTELPllInvalid("p out of range\n");
 517                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 518                         INTELPllInvalid("m out of range\n");
 519         }
 520
 521         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 522                 INTELPllInvalid("vco out of range\n");
 523         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 524          * connector, etc., rather than just a single range.
 525          */
 526         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 527                 INTELPllInvalid("dot out of range\n");
 528
 529         return true;
 530 }
 531
 532 static bool
 533 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 534                     int target, int refclk, intel_clock_t *match_clock,
 535                     intel_clock_t *best_clock)
 536 {
 537         struct drm_device *dev = crtc->dev;
 538         intel_clock_t clock;
 539         int err = target;
 540
 541         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 542                 /*
 543                  * For LVDS just rely on its current settings for dual-channel.
 544                  * We haven't figured out how to reliably set up different
 545                  * single/dual channel state, if we even can.
 546                  */
 547                 if (intel_is_dual_link_lvds(dev))
 548                         clock.p2 = limit->p2.p2_fast;
 549                 else
 550                         clock.p2 = limit->p2.p2_slow;
 551         } else {
 552                 if (target < limit->p2.dot_limit)
 553                         clock.p2 = limit->p2.p2_slow;
 554                 else
 555                         clock.p2 = limit->p2.p2_fast;
 556         }
 557
 558         memset(best_clock, 0, sizeof(*best_clock));
 559
 560         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 561              clock.m1++) {
 562                 for (clock.m2 = limit->m2.min;
 563                      clock.m2 <= limit->m2.max; clock.m2++) {
 564                         if (clock.m2 >= clock.m1)
 565                                 break;
 566                         for (clock.n = limit->n.min;
 567                              clock.n <= limit->n.max; clock.n++) {
 568                                 for (clock.p1 = limit->p1.min;
 569                                         clock.p1 <= limit->p1.max; clock.p1++) {
 570                                         int this_err;
 571
 572                                         i9xx_clock(refclk, &clock);
 573                                         if (!intel_PLL_is_valid(dev, limit,
 574                                                                 &clock))
 575                                                 continue;
 576                                         if (match_clock &&
 577                                             clock.p != match_clock->p)
 578                                                 continue;
 579
 580                                         this_err = abs(clock.dot - target);
 581                                         if (this_err < err) {
 582                                                 *best_clock = clock;
 583                                                 err = this_err;
 584                                         }
 585                                 }
 586                         }
 587                 }
 588         }
 589
 590         return (err != target);
 591 }
 592
 593 static bool
 594 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 595                    int target, int refclk, intel_clock_t *match_clock,
 596                    intel_clock_t *best_clock)
 597 {
 598         struct drm_device *dev = crtc->dev;
 599         intel_clock_t clock;
 600         int err = target;
 601
 602         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 603                 /*
 604                  * For LVDS just rely on its current settings for dual-channel.
 605                  * We haven't figured out how to reliably set up different
 606                  * single/dual channel state, if we even can.
 607                  */
 608                 if (intel_is_dual_link_lvds(dev))
 609                         clock.p2 = limit->p2.p2_fast;
 610                 else
 611                         clock.p2 = limit->p2.p2_slow;
 612         } else {
 613                 if (target < limit->p2.dot_limit)
 614                         clock.p2 = limit->p2.p2_slow;
 615                 else
 616                         clock.p2 = limit->p2.p2_fast;
 617         }
 618
 619         memset(best_clock, 0, sizeof(*best_clock));
 620
 621         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 622              clock.m1++) {
 623                 for (clock.m2 = limit->m2.min;
 624                      clock.m2 <= limit->m2.max; clock.m2++) {
 625                         for (clock.n = limit->n.min;
 626                              clock.n <= limit->n.max; clock.n++) {
 627                                 for (clock.p1 = limit->p1.min;
 628                                         clock.p1 <= limit->p1.max; clock.p1++) {
 629                                         int this_err;
 630
 631                                         pineview_clock(refclk, &clock);
 632                                         if (!intel_PLL_is_valid(dev, limit,
 633                                                                 &clock))
 634                                                 continue;
 635                                         if (match_clock &&
 636                                             clock.p != match_clock->p)
 637                                                 continue;
 638
 639                                         this_err = abs(clock.dot - target);
 640                                         if (this_err < err) {
 641                                                 *best_clock = clock;
 642                                                 err = this_err;
 643                                         }
 644                                 }
 645                         }
 646                 }
 647         }
 648
 649         return (err != target);
 650 }
 651
 652 static bool
 653 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 654                    int target, int refclk, intel_clock_t *match_clock,
 655                    intel_clock_t *best_clock)
 656 {
 657         struct drm_device *dev = crtc->dev;
 658         intel_clock_t clock;
 659         int max_n;
 660         bool found;
 661         /* approximately equals target * 0.00585 */
 662         int err_most = (target >> 8) + (target >> 9);
 663         found = false;
 664
 665         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 666                 if (intel_is_dual_link_lvds(dev))
 667                         clock.p2 = limit->p2.p2_fast;
 668                 else
 669                         clock.p2 = limit->p2.p2_slow;
 670         } else {
 671                 if (target < limit->p2.dot_limit)
 672                         clock.p2 = limit->p2.p2_slow;
 673                 else
 674                         clock.p2 = limit->p2.p2_fast;
 675         }
 676
 677         memset(best_clock, 0, sizeof(*best_clock));
 678         max_n = limit->n.max;
 679         /* based on hardware requirement, prefer smaller n to precision */
 680         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 681                 /* based on hardware requirement, prefere larger m1,m2 */
 682                 for (clock.m1 = limit->m1.max;
 683                      clock.m1 >= limit->m1.min; clock.m1--) {
 684                         for (clock.m2 = limit->m2.max;
 685                              clock.m2 >= limit->m2.min; clock.m2--) {
 686                                 for (clock.p1 = limit->p1.max;
 687                                      clock.p1 >= limit->p1.min; clock.p1--) {
 688                                         int this_err;
 689
 690                                         i9xx_clock(refclk, &clock);
 691                                         if (!intel_PLL_is_valid(dev, limit,
 692                                                                 &clock))
 693                                                 continue;
 694
 695                                         this_err = abs(clock.dot - target);
 696                                         if (this_err < err_most) {
 697                                                 *best_clock = clock;
 698                                                 err_most = this_err;
 699                                                 max_n = clock.n;
 700                                                 found = true;
 701                                         }
 702                                 }
 703                         }
 704                 }
 705         }
 706         return found;
 707 }
 708
 709 static bool
 710 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 711                    int target, int refclk, intel_clock_t *match_clock,
 712                    intel_clock_t *best_clock)
 713 {
 714         struct drm_device *dev = crtc->dev;
 715         intel_clock_t clock;
 716         unsigned int bestppm = 1000000;
 717         /* min update 19.2 MHz */
 718         int max_n = min(limit->n.max, refclk / 19200);
 719         bool found = false;
 720
 721         target *= 5; /* fast clock */
 722
 723         memset(best_clock, 0, sizeof(*best_clock));
 724
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 727                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 728                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 729                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 730                                 clock.p = clock.p1 * clock.p2;
 731                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 732                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 733                                         unsigned int ppm, diff;
 734
 735                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 736                                                                      refclk * clock.m1);
 737
 738                                         vlv_clock(refclk, &clock);
 739
 740                                         if (!intel_PLL_is_valid(dev, limit,
 741                                                                 &clock))
 742                                                 continue;
 743
 744                                         diff = abs(clock.dot - target);
 745                                         ppm = div_u64(1000000ULL * diff, target);
 746
 747                                         if (ppm < 100 && clock.p > best_clock->p) {
 748                                                 bestppm = 0;
 749                                                 *best_clock = clock;
 750                                                 found = true;
 751                                         }
 752
 753                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 754                                                 bestppm = ppm;
 755                                                 *best_clock = clock;
 756                                                 found = true;
 757                                         }
 758                                 }
 759                         }
 760                 }
 761         }
 762
 763         return found;
 764 }
 765
 766 static bool
 767 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 768                    int target, int refclk, intel_clock_t *match_clock,
 769                    intel_clock_t *best_clock)
 770 {
 771         struct drm_device *dev = crtc->dev;
 772         intel_clock_t clock;
 773         uint64_t m2;
 774         int found = false;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         /*
 779          * Based on hardware doc, the n always set to 1, and m1 always
 780          * set to 2.  If requires to support 200Mhz refclk, we need to
 781          * revisit this because n may not 1 anymore.
 782          */
 783         clock.n = 1, clock.m1 = 2;
 784         target *= 5;    /* fast clock */
 785
 786         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 787                 for (clock.p2 = limit->p2.p2_fast;
 788                                 clock.p2 >= limit->p2.p2_slow;
 789                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 790
 791                         clock.p = clock.p1 * clock.p2;
 792
 793                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 794                                         clock.n) << 22, refclk * clock.m1);
 795
 796                         if (m2 > INT_MAX/clock.m1)
 797                                 continue;
 798
 799                         clock.m2 = m2;
 800
 801                         chv_clock(refclk, &clock);
 802
 803                         if (!intel_PLL_is_valid(dev, limit, &clock))
 804                                 continue;
 805
 806                         /* based on hardware requirement, prefer bigger p
 807                          */
 808                         if (clock.p > best_clock->p) {
 809                                 *best_clock = clock;
 810                                 found = true;
 811                         }
 812                 }
 813         }
 814
 815         return found;
 816 }
 817
 818 bool intel_crtc_active(struct drm_crtc *crtc)
 819 {
 820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 821
 822         /* Be paranoid as we can arrive here with only partial
 823          * state retrieved from the hardware during setup.
 824          *
 825          * We can ditch the adjusted_mode.crtc_clock check as soon
 826          * as Haswell has gained clock readout/fastboot support.
 827          *
 828          * We can ditch the crtc->primary->fb check as soon as we can
 829          * properly reconstruct framebuffers.
 830          */
 831         return intel_crtc->active && crtc->primary->fb &&
 832                 intel_crtc->config.adjusted_mode.crtc_clock;
 833 }
 834
 835 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 836                                              enum pipe pipe)
 837 {
 838         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 840
 841         return intel_crtc->config.cpu_transcoder;
 842 }
 843
 844 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 845 {
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 848
 849         frame = I915_READ(frame_reg);
 850
 851         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 852                 WARN(1, "vblank wait timed out\n");
 853 }
 854
 855 /**
 856  * intel_wait_for_vblank - wait for vblank on a given pipe
 857  * @dev: drm device
 858  * @pipe: pipe to wait for
 859  *
 860  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 861  * mode setting code.
 862  */
 863 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 864 {
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         int pipestat_reg = PIPESTAT(pipe);
 867
 868         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 869                 g4x_wait_for_vblank(dev, pipe);
 870                 return;
 871         }
 872
 873         /* Clear existing vblank status. Note this will clear any other
 874          * sticky status fields as well.
 875          *
 876          * This races with i915_driver_irq_handler() with the result
 877          * that either function could miss a vblank event.  Here it is not
 878          * fatal, as we will either wait upon the next vblank interrupt or
 879          * timeout.  Generally speaking intel_wait_for_vblank() is only
 880          * called during modeset at which time the GPU should be idle and
 881          * should *not* be performing page flips and thus not waiting on
 882          * vblanks...
 883          * Currently, the result of us stealing a vblank from the irq
 884          * handler is that a single frame will be skipped during swapbuffers.
 885          */
 886         I915_WRITE(pipestat_reg,
 887                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 888
 889         /* Wait for vblank interrupt bit to set */
 890         if (wait_for(I915_READ(pipestat_reg) &
 891                      PIPE_VBLANK_INTERRUPT_STATUS,
 892                      50))
 893                 DRM_DEBUG_KMS("vblank wait timed out\n");
 894 }
 895
 896 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 897 {
 898         struct drm_i915_private *dev_priv = dev->dev_private;
 899         u32 reg = PIPEDSL(pipe);
 900         u32 line1, line2;
 901         u32 line_mask;
 902
 903         if (IS_GEN2(dev))
 904                 line_mask = DSL_LINEMASK_GEN2;
 905         else
 906                 line_mask = DSL_LINEMASK_GEN3;
 907
 908         line1 = I915_READ(reg) & line_mask;
 909         mdelay(5);
 910         line2 = I915_READ(reg) & line_mask;
 911
 912         return line1 == line2;
 913 }
 914
 915 /*
 916  * intel_wait_for_pipe_off - wait for pipe to turn off
 917  * @dev: drm device
 918  * @pipe: pipe to wait for
 919  *
 920  * After disabling a pipe, we can't wait for vblank in the usual way,
 921  * spinning on the vblank interrupt status bit, since we won't actually
 922  * see an interrupt when the pipe is disabled.
 923  *
 924  * On Gen4 and above:
 925  *   wait for the pipe register state bit to turn off
 926  *
 927  * Otherwise:
 928  *   wait for the display line value to settle (it usually
 929  *   ends up stopping at the start of the next frame).
 930  *
 931  */
 932 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 933 {
 934         struct drm_i915_private *dev_priv = dev->dev_private;
 935         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 936                                                                       pipe);
 937
 938         if (INTEL_INFO(dev)->gen >= 4) {
 939                 int reg = PIPECONF(cpu_transcoder);
 940
 941                 /* Wait for the Pipe State to go off */
 942                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 943                              100))
 944                         WARN(1, "pipe_off wait timed out\n");
 945         } else {
 946                 /* Wait for the display line to settle */
 947                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 948                         WARN(1, "pipe_off wait timed out\n");
 949         }
 950 }
 951
 952 /*
 953  * ibx_digital_port_connected - is the specified port connected?
 954  * @dev_priv: i915 private structure
 955  * @port: the port to test
 956  *
 957  * Returns true if @port is connected, false otherwise.
 958  */
 959 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 960                                 struct intel_digital_port *port)
 961 {
 962         u32 bit;
 963
 964         if (HAS_PCH_IBX(dev_priv->dev)) {
 965                 switch(port->port) {
 966                 case PORT_B:
 967                         bit = SDE_PORTB_HOTPLUG;
 968                         break;
 969                 case PORT_C:
 970                         bit = SDE_PORTC_HOTPLUG;
 971                         break;
 972                 case PORT_D:
 973                         bit = SDE_PORTD_HOTPLUG;
 974                         break;
 975                 default:
 976                         return true;
 977                 }
 978         } else {
 979                 switch(port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG_CPT;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG_CPT;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG_CPT;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         }
 993
 994         return I915_READ(SDEISR) & bit;
 995 }
 996
 997 static const char *state_string(bool enabled)
 998 {
 999         return enabled ? "on" : "off";
1000 }
1001
1002 /* Only for pre-ILK configs */
1003 void assert_pll(struct drm_i915_private *dev_priv,
1004                 enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = DPLL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & DPLL_VCO_ENABLE);
1013         WARN(cur_state != state,
1014              "PLL state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017
1018 /* XXX: the dsi pll is shared between MIPI DSI ports */
1019 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1020 {
1021         u32 val;
1022         bool cur_state;
1023
1024         mutex_lock(&dev_priv->dpio_lock);
1025         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1026         mutex_unlock(&dev_priv->dpio_lock);
1027
1028         cur_state = val & DSI_PLL_VCO_EN;
1029         WARN(cur_state != state,
1030              "DSI PLL state assertion failure (expected %s, current %s)\n",
1031              state_string(state), state_string(cur_state));
1032 }
1033 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1034 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1035
1036 struct intel_shared_dpll *
1037 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1038 {
1039         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1040
1041         if (crtc->config.shared_dpll < 0)
1042                 return NULL;
1043
1044         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1045 }
1046
1047 /* For ILK+ */
1048 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1049                         struct intel_shared_dpll *pll,
1050                         bool state)
1051 {
1052         bool cur_state;
1053         struct intel_dpll_hw_state hw_state;
1054
1055         if (HAS_PCH_LPT(dev_priv->dev)) {
1056                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1057                 return;
1058         }
1059
1060         if (WARN (!pll,
1061                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1062                 return;
1063
1064         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1065         WARN(cur_state != state,
1066              "%s assertion failure (expected %s, current %s)\n",
1067              pll->name, state_string(state), state_string(cur_state));
1068 }
1069
1070 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1071                           enum pipe pipe, bool state)
1072 {
1073         int reg;
1074         u32 val;
1075         bool cur_state;
1076         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1077                                                                       pipe);
1078
1079         if (HAS_DDI(dev_priv->dev)) {
1080                 /* DDI does not have a specific FDI_TX register */
1081                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1082                 val = I915_READ(reg);
1083                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1084         } else {
1085                 reg = FDI_TX_CTL(pipe);
1086                 val = I915_READ(reg);
1087                 cur_state = !!(val & FDI_TX_ENABLE);
1088         }
1089         WARN(cur_state != state,
1090              "FDI TX state assertion failure (expected %s, current %s)\n",
1091              state_string(state), state_string(cur_state));
1092 }
1093 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1094 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1095
1096 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1097                           enum pipe pipe, bool state)
1098 {
1099         int reg;
1100         u32 val;
1101         bool cur_state;
1102
1103         reg = FDI_RX_CTL(pipe);
1104         val = I915_READ(reg);
1105         cur_state = !!(val & FDI_RX_ENABLE);
1106         WARN(cur_state != state,
1107              "FDI RX state assertion failure (expected %s, current %s)\n",
1108              state_string(state), state_string(cur_state));
1109 }
1110 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1111 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1112
1113 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1114                                       enum pipe pipe)
1115 {
1116         int reg;
1117         u32 val;
1118
1119         /* ILK FDI PLL is always enabled */
1120         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1121                 return;
1122
1123         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1124         if (HAS_DDI(dev_priv->dev))
1125                 return;
1126
1127         reg = FDI_TX_CTL(pipe);
1128         val = I915_READ(reg);
1129         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1130 }
1131
1132 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1133                        enum pipe pipe, bool state)
1134 {
1135         int reg;
1136         u32 val;
1137         bool cur_state;
1138
1139         reg = FDI_RX_CTL(pipe);
1140         val = I915_READ(reg);
1141         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1142         WARN(cur_state != state,
1143              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1144              state_string(state), state_string(cur_state));
1145 }
1146
1147 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1148                                   enum pipe pipe)
1149 {
1150         int pp_reg, lvds_reg;
1151         u32 val;
1152         enum pipe panel_pipe = PIPE_A;
1153         bool locked = true;
1154
1155         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1156                 pp_reg = PCH_PP_CONTROL;
1157                 lvds_reg = PCH_LVDS;
1158         } else {
1159                 pp_reg = PP_CONTROL;
1160                 lvds_reg = LVDS;
1161         }
1162
1163         val = I915_READ(pp_reg);
1164         if (!(val & PANEL_POWER_ON) ||
1165             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1166                 locked = false;
1167
1168         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1169                 panel_pipe = PIPE_B;
1170
1171         WARN(panel_pipe == pipe && locked,
1172              "panel assertion failure, pipe %c regs locked\n",
1173              pipe_name(pipe));
1174 }
1175
1176 static void assert_cursor(struct drm_i915_private *dev_priv,
1177                           enum pipe pipe, bool state)
1178 {
1179         struct drm_device *dev = dev_priv->dev;
1180         bool cur_state;
1181
1182         if (IS_845G(dev) || IS_I865G(dev))
1183                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1184         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1185                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1186         else
1187                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1188
1189         WARN(cur_state != state,
1190              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191              pipe_name(pipe), state_string(state), state_string(cur_state));
1192 }
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1195
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197                  enum pipe pipe, bool state)
1198 {
1199         int reg;
1200         u32 val;
1201         bool cur_state;
1202         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1203                                                                       pipe);
1204
1205         /* if we need the pipe A quirk it must be always on */
1206         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1207                 state = true;
1208
1209         if (!intel_display_power_enabled(dev_priv,
1210                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1211                 cur_state = false;
1212         } else {
1213                 reg = PIPECONF(cpu_transcoder);
1214                 val = I915_READ(reg);
1215                 cur_state = !!(val & PIPECONF_ENABLE);
1216         }
1217
1218         WARN(cur_state != state,
1219              "pipe %c assertion failure (expected %s, current %s)\n",
1220              pipe_name(pipe), state_string(state), state_string(cur_state));
1221 }
1222
1223 static void assert_plane(struct drm_i915_private *dev_priv,
1224                          enum plane plane, bool state)
1225 {
1226         int reg;
1227         u32 val;
1228         bool cur_state;
1229
1230         reg = DSPCNTR(plane);
1231         val = I915_READ(reg);
1232         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1233         WARN(cur_state != state,
1234              "plane %c assertion failure (expected %s, current %s)\n",
1235              plane_name(plane), state_string(state), state_string(cur_state));
1236 }
1237
1238 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1239 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1240
1241 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1242                                    enum pipe pipe)
1243 {
1244         struct drm_device *dev = dev_priv->dev;
1245         int reg, i;
1246         u32 val;
1247         int cur_pipe;
1248
1249         /* Primary planes are fixed to pipes on gen4+ */
1250         if (INTEL_INFO(dev)->gen >= 4) {
1251                 reg = DSPCNTR(pipe);
1252                 val = I915_READ(reg);
1253                 WARN(val & DISPLAY_PLANE_ENABLE,
1254                      "plane %c assertion failure, should be disabled but not\n",
1255                      plane_name(pipe));
1256                 return;
1257         }
1258
1259         /* Need to check both planes against the pipe */
1260         for_each_pipe(i) {
1261                 reg = DSPCNTR(i);
1262                 val = I915_READ(reg);
1263                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1264                         DISPPLANE_SEL_PIPE_SHIFT;
1265                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1266                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1267                      plane_name(i), pipe_name(pipe));
1268         }
1269 }
1270
1271 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1272                                     enum pipe pipe)
1273 {
1274         struct drm_device *dev = dev_priv->dev;
1275         int reg, sprite;
1276         u32 val;
1277
1278         if (IS_VALLEYVIEW(dev)) {
1279                 for_each_sprite(pipe, sprite) {
1280                         reg = SPCNTR(pipe, sprite);
1281                         val = I915_READ(reg);
1282                         WARN(val & SP_ENABLE,
1283                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                              sprite_name(pipe, sprite), pipe_name(pipe));
1285                 }
1286         } else if (INTEL_INFO(dev)->gen >= 7) {
1287                 reg = SPRCTL(pipe);
1288                 val = I915_READ(reg);
1289                 WARN(val & SPRITE_ENABLE,
1290                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291                      plane_name(pipe), pipe_name(pipe));
1292         } else if (INTEL_INFO(dev)->gen >= 5) {
1293                 reg = DVSCNTR(pipe);
1294                 val = I915_READ(reg);
1295                 WARN(val & DVS_ENABLE,
1296                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297                      plane_name(pipe), pipe_name(pipe));
1298         }
1299 }
1300
1301 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1302 {
1303         u32 val;
1304         bool enabled;
1305
1306         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1307
1308         val = I915_READ(PCH_DREF_CONTROL);
1309         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310                             DREF_SUPERSPREAD_SOURCE_MASK));
1311         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1312 }
1313
1314 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1315                                            enum pipe pipe)
1316 {
1317         int reg;
1318         u32 val;
1319         bool enabled;
1320
1321         reg = PCH_TRANSCONF(pipe);
1322         val = I915_READ(reg);
1323         enabled = !!(val & TRANS_ENABLE);
1324         WARN(enabled,
1325              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326              pipe_name(pipe));
1327 }
1328
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330                             enum pipe pipe, u32 port_sel, u32 val)
1331 {
1332         if ((val & DP_PORT_EN) == 0)
1333                 return false;
1334
1335         if (HAS_PCH_CPT(dev_priv->dev)) {
1336                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1339                         return false;
1340         } else {
1341                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1342                         return false;
1343         }
1344         return true;
1345 }
1346
1347 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1348                               enum pipe pipe, u32 val)
1349 {
1350         if ((val & SDVO_ENABLE) == 0)
1351                 return false;
1352
1353         if (HAS_PCH_CPT(dev_priv->dev)) {
1354                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1355                         return false;
1356         } else {
1357                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1358                         return false;
1359         }
1360         return true;
1361 }
1362
1363 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1364                               enum pipe pipe, u32 val)
1365 {
1366         if ((val & LVDS_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1371                         return false;
1372         } else {
1373                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1374                         return false;
1375         }
1376         return true;
1377 }
1378
1379 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1380                               enum pipe pipe, u32 val)
1381 {
1382         if ((val & ADPA_DAC_ENABLE) == 0)
1383                 return false;
1384         if (HAS_PCH_CPT(dev_priv->dev)) {
1385                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1386                         return false;
1387         } else {
1388                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1389                         return false;
1390         }
1391         return true;
1392 }
1393
1394 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1395                                    enum pipe pipe, int reg, u32 port_sel)
1396 {
1397         u32 val = I915_READ(reg);
1398         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1399              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1400              reg, pipe_name(pipe));
1401
1402         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1403              && (val & DP_PIPEB_SELECT),
1404              "IBX PCH dp port still using transcoder B\n");
1405 }
1406
1407 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1408                                      enum pipe pipe, int reg)
1409 {
1410         u32 val = I915_READ(reg);
1411         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1412              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1413              reg, pipe_name(pipe));
1414
1415         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1416              && (val & SDVO_PIPE_B_SELECT),
1417              "IBX PCH hdmi port still using transcoder B\n");
1418 }
1419
1420 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1421                                       enum pipe pipe)
1422 {
1423         int reg;
1424         u32 val;
1425
1426         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1427         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1429
1430         reg = PCH_ADPA;
1431         val = I915_READ(reg);
1432         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1433              "PCH VGA enabled on transcoder %c, should be disabled\n",
1434              pipe_name(pipe));
1435
1436         reg = PCH_LVDS;
1437         val = I915_READ(reg);
1438         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1439              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1440              pipe_name(pipe));
1441
1442         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1443         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1444         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1445 }
1446
1447 static void intel_init_dpio(struct drm_device *dev)
1448 {
1449         struct drm_i915_private *dev_priv = dev->dev_private;
1450
1451         if (!IS_VALLEYVIEW(dev))
1452                 return;
1453
1454         /*
1455          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1456          * CHV x1 PHY (DP/HDMI D)
1457          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1458          */
1459         if (IS_CHERRYVIEW(dev)) {
1460                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1461                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1462         } else {
1463                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1464         }
1465 }
1466
1467 static void intel_reset_dpio(struct drm_device *dev)
1468 {
1469         struct drm_i915_private *dev_priv = dev->dev_private;
1470
1471         if (!IS_VALLEYVIEW(dev))
1472                 return;
1473
1474         /*
1475          * Enable the CRI clock source so we can get at the display and the
1476          * reference clock for VGA hotplug / manual detection.
1477          */
1478         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1479                    DPLL_REFA_CLK_ENABLE_VLV |
1480                    DPLL_INTEGRATED_CRI_CLK_VLV);
1481
1482         if (IS_CHERRYVIEW(dev)) {
1483                 enum dpio_phy phy;
1484                 u32 val;
1485
1486                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1487                         /* Poll for phypwrgood signal */
1488                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1489                                                 PHY_POWERGOOD(phy), 1))
1490                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1491
1492                         /*
1493                          * Deassert common lane reset for PHY.
1494                          *
1495                          * This should only be done on init and resume from S3
1496                          * with both PLLs disabled, or we risk losing DPIO and
1497                          * PLL synchronization.
1498                          */
1499                         val = I915_READ(DISPLAY_PHY_CONTROL);
1500                         I915_WRITE(DISPLAY_PHY_CONTROL,
1501                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1502                 }
1503
1504         } else {
1505                 /*
1506                  * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1507                  *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1508                  *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1509                  *   b. The other bits such as sfr settings / modesel may all
1510                  *      be set to 0.
1511                  *
1512                  * This should only be done on init and resume from S3 with
1513                  * both PLLs disabled, or we risk losing DPIO and PLL
1514                  * synchronization.
1515                  */
1516                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1517         }
1518 }
1519
1520 static void vlv_enable_pll(struct intel_crtc *crtc)
1521 {
1522         struct drm_device *dev = crtc->base.dev;
1523         struct drm_i915_private *dev_priv = dev->dev_private;
1524         int reg = DPLL(crtc->pipe);
1525         u32 dpll = crtc->config.dpll_hw_state.dpll;
1526
1527         assert_pipe_disabled(dev_priv, crtc->pipe);
1528
1529         /* No really, not for ILK+ */
1530         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1531
1532         /* PLL is protected by panel, make sure we can write it */
1533         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1534                 assert_panel_unlocked(dev_priv, crtc->pipe);
1535
1536         I915_WRITE(reg, dpll);
1537         POSTING_READ(reg);
1538         udelay(150);
1539
1540         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1541                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1542
1543         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1544         POSTING_READ(DPLL_MD(crtc->pipe));
1545
1546         /* We do this three times for luck */
1547         I915_WRITE(reg, dpll);
1548         POSTING_READ(reg);
1549         udelay(150); /* wait for warmup */
1550         I915_WRITE(reg, dpll);
1551         POSTING_READ(reg);
1552         udelay(150); /* wait for warmup */
1553         I915_WRITE(reg, dpll);
1554         POSTING_READ(reg);
1555         udelay(150); /* wait for warmup */
1556 }
1557
1558 static void i9xx_enable_pll(struct intel_crtc *crtc)
1559 {
1560         struct drm_device *dev = crtc->base.dev;
1561         struct drm_i915_private *dev_priv = dev->dev_private;
1562         int reg = DPLL(crtc->pipe);
1563         u32 dpll = crtc->config.dpll_hw_state.dpll;
1564
1565         assert_pipe_disabled(dev_priv, crtc->pipe);
1566
1567         /* No really, not for ILK+ */
1568         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1569
1570         /* PLL is protected by panel, make sure we can write it */
1571         if (IS_MOBILE(dev) && !IS_I830(dev))
1572                 assert_panel_unlocked(dev_priv, crtc->pipe);
1573
1574         I915_WRITE(reg, dpll);
1575
1576         /* Wait for the clocks to stabilize. */
1577         POSTING_READ(reg);
1578         udelay(150);
1579
1580         if (INTEL_INFO(dev)->gen >= 4) {
1581                 I915_WRITE(DPLL_MD(crtc->pipe),
1582                            crtc->config.dpll_hw_state.dpll_md);
1583         } else {
1584                 /* The pixel multiplier can only be updated once the
1585                  * DPLL is enabled and the clocks are stable.
1586                  *
1587                  * So write it again.
1588                  */
1589                 I915_WRITE(reg, dpll);
1590         }
1591
1592         /* We do this three times for luck */
1593         I915_WRITE(reg, dpll);
1594         POSTING_READ(reg);
1595         udelay(150); /* wait for warmup */
1596         I915_WRITE(reg, dpll);
1597         POSTING_READ(reg);
1598         udelay(150); /* wait for warmup */
1599         I915_WRITE(reg, dpll);
1600         POSTING_READ(reg);
1601         udelay(150); /* wait for warmup */
1602 }
1603
1604 /**
1605  * i9xx_disable_pll - disable a PLL
1606  * @dev_priv: i915 private structure
1607  * @pipe: pipe PLL to disable
1608  *
1609  * Disable the PLL for @pipe, making sure the pipe is off first.
1610  *
1611  * Note!  This is for pre-ILK only.
1612  */
1613 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1614 {
1615         /* Don't disable pipe A or pipe A PLLs if needed */
1616         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1617                 return;
1618
1619         /* Make sure the pipe isn't still relying on us */
1620         assert_pipe_disabled(dev_priv, pipe);
1621
1622         I915_WRITE(DPLL(pipe), 0);
1623         POSTING_READ(DPLL(pipe));
1624 }
1625
1626 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1627 {
1628         u32 val = 0;
1629
1630         /* Make sure the pipe isn't still relying on us */
1631         assert_pipe_disabled(dev_priv, pipe);
1632
1633         /*
1634          * Leave integrated clock source and reference clock enabled for pipe B.
1635          * The latter is needed for VGA hotplug / manual detection.
1636          */
1637         if (pipe == PIPE_B)
1638                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1639         I915_WRITE(DPLL(pipe), val);
1640         POSTING_READ(DPLL(pipe));
1641
1642 }
1643
1644 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1645 {
1646         int dpll = DPLL(pipe);
1647         u32 val;
1648
1649         /* Set PLL en = 0 */
1650         val = I915_READ(dpll);
1651         val &= ~DPLL_VCO_ENABLE;
1652         I915_WRITE(dpll, val);
1653
1654 }
1655
1656 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1657                 struct intel_digital_port *dport)
1658 {
1659         u32 port_mask;
1660         int dpll_reg;
1661
1662         switch (dport->port) {
1663         case PORT_B:
1664                 port_mask = DPLL_PORTB_READY_MASK;
1665                 dpll_reg = DPLL(0);
1666                 break;
1667         case PORT_C:
1668                 port_mask = DPLL_PORTC_READY_MASK;
1669                 dpll_reg = DPLL(0);
1670                 break;
1671         case PORT_D:
1672                 port_mask = DPLL_PORTD_READY_MASK;
1673                 dpll_reg = DPIO_PHY_STATUS;
1674                 break;
1675         default:
1676                 BUG();
1677         }
1678
1679         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1680                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1681                      port_name(dport->port), I915_READ(dpll_reg));
1682 }
1683
1684 /**
1685  * ironlake_enable_shared_dpll - enable PCH PLL
1686  * @dev_priv: i915 private structure
1687  * @pipe: pipe PLL to enable
1688  *
1689  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1690  * drives the transcoder clock.
1691  */
1692 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1693 {
1694         struct drm_device *dev = crtc->base.dev;
1695         struct drm_i915_private *dev_priv = dev->dev_private;
1696         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1697
1698         /* PCH PLLs only available on ILK, SNB and IVB */
1699         BUG_ON(INTEL_INFO(dev)->gen < 5);
1700         if (WARN_ON(pll == NULL))
1701                 return;
1702
1703         if (WARN_ON(pll->refcount == 0))
1704                 return;
1705
1706         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1707                       pll->name, pll->active, pll->on,
1708                       crtc->base.base.id);
1709
1710         if (pll->active++) {
1711                 WARN_ON(!pll->on);
1712                 assert_shared_dpll_enabled(dev_priv, pll);
1713                 return;
1714         }
1715         WARN_ON(pll->on);
1716
1717         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1718         pll->enable(dev_priv, pll);
1719         pll->on = true;
1720 }
1721
1722 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1723 {
1724         struct drm_device *dev = crtc->base.dev;
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1727
1728         /* PCH only available on ILK+ */
1729         BUG_ON(INTEL_INFO(dev)->gen < 5);
1730         if (WARN_ON(pll == NULL))
1731                return;
1732
1733         if (WARN_ON(pll->refcount == 0))
1734                 return;
1735
1736         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1737                       pll->name, pll->active, pll->on,
1738                       crtc->base.base.id);
1739
1740         if (WARN_ON(pll->active == 0)) {
1741                 assert_shared_dpll_disabled(dev_priv, pll);
1742                 return;
1743         }
1744
1745         assert_shared_dpll_enabled(dev_priv, pll);
1746         WARN_ON(!pll->on);
1747         if (--pll->active)
1748                 return;
1749
1750         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1751         pll->disable(dev_priv, pll);
1752         pll->on = false;
1753 }
1754
1755 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1756                                            enum pipe pipe)
1757 {
1758         struct drm_device *dev = dev_priv->dev;
1759         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1760         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1761         uint32_t reg, val, pipeconf_val;
1762
1763         /* PCH only available on ILK+ */
1764         BUG_ON(INTEL_INFO(dev)->gen < 5);
1765
1766         /* Make sure PCH DPLL is enabled */
1767         assert_shared_dpll_enabled(dev_priv,
1768                                    intel_crtc_to_shared_dpll(intel_crtc));
1769
1770         /* FDI must be feeding us bits for PCH ports */
1771         assert_fdi_tx_enabled(dev_priv, pipe);
1772         assert_fdi_rx_enabled(dev_priv, pipe);
1773
1774         if (HAS_PCH_CPT(dev)) {
1775                 /* Workaround: Set the timing override bit before enabling the
1776                  * pch transcoder. */
1777                 reg = TRANS_CHICKEN2(pipe);
1778                 val = I915_READ(reg);
1779                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1780                 I915_WRITE(reg, val);
1781         }
1782
1783         reg = PCH_TRANSCONF(pipe);
1784         val = I915_READ(reg);
1785         pipeconf_val = I915_READ(PIPECONF(pipe));
1786
1787         if (HAS_PCH_IBX(dev_priv->dev)) {
1788                 /*
1789                  * make the BPC in transcoder be consistent with
1790                  * that in pipeconf reg.
1791                  */
1792                 val &= ~PIPECONF_BPC_MASK;
1793                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1794         }
1795
1796         val &= ~TRANS_INTERLACE_MASK;
1797         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1798                 if (HAS_PCH_IBX(dev_priv->dev) &&
1799                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1800                         val |= TRANS_LEGACY_INTERLACED_ILK;
1801                 else
1802                         val |= TRANS_INTERLACED;
1803         else
1804                 val |= TRANS_PROGRESSIVE;
1805
1806         I915_WRITE(reg, val | TRANS_ENABLE);
1807         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1808                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1809 }
1810
1811 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1812                                       enum transcoder cpu_transcoder)
1813 {
1814         u32 val, pipeconf_val;
1815
1816         /* PCH only available on ILK+ */
1817         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1818
1819         /* FDI must be feeding us bits for PCH ports */
1820         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1821         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1822
1823         /* Workaround: set timing override bit. */
1824         val = I915_READ(_TRANSA_CHICKEN2);
1825         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1826         I915_WRITE(_TRANSA_CHICKEN2, val);
1827
1828         val = TRANS_ENABLE;
1829         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1830
1831         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1832             PIPECONF_INTERLACED_ILK)
1833                 val |= TRANS_INTERLACED;
1834         else
1835                 val |= TRANS_PROGRESSIVE;
1836
1837         I915_WRITE(LPT_TRANSCONF, val);
1838         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1839                 DRM_ERROR("Failed to enable PCH transcoder\n");
1840 }
1841
1842 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1843                                             enum pipe pipe)
1844 {
1845         struct drm_device *dev = dev_priv->dev;
1846         uint32_t reg, val;
1847
1848         /* FDI relies on the transcoder */
1849         assert_fdi_tx_disabled(dev_priv, pipe);
1850         assert_fdi_rx_disabled(dev_priv, pipe);
1851
1852         /* Ports must be off as well */
1853         assert_pch_ports_disabled(dev_priv, pipe);
1854
1855         reg = PCH_TRANSCONF(pipe);
1856         val = I915_READ(reg);
1857         val &= ~TRANS_ENABLE;
1858         I915_WRITE(reg, val);
1859         /* wait for PCH transcoder off, transcoder state */
1860         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1861                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1862
1863         if (!HAS_PCH_IBX(dev)) {
1864                 /* Workaround: Clear the timing override chicken bit again. */
1865                 reg = TRANS_CHICKEN2(pipe);
1866                 val = I915_READ(reg);
1867                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1868                 I915_WRITE(reg, val);
1869         }
1870 }
1871
1872 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1873 {
1874         u32 val;
1875
1876         val = I915_READ(LPT_TRANSCONF);
1877         val &= ~TRANS_ENABLE;
1878         I915_WRITE(LPT_TRANSCONF, val);
1879         /* wait for PCH transcoder off, transcoder state */
1880         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1881                 DRM_ERROR("Failed to disable PCH transcoder\n");
1882
1883         /* Workaround: clear timing override bit. */
1884         val = I915_READ(_TRANSA_CHICKEN2);
1885         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1886         I915_WRITE(_TRANSA_CHICKEN2, val);
1887 }
1888
1889 /**
1890  * intel_enable_pipe - enable a pipe, asserting requirements
1891  * @crtc: crtc responsible for the pipe
1892  *
1893  * Enable @crtc's pipe, making sure that various hardware specific requirements
1894  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1895  */
1896 static void intel_enable_pipe(struct intel_crtc *crtc)
1897 {
1898         struct drm_device *dev = crtc->base.dev;
1899         struct drm_i915_private *dev_priv = dev->dev_private;
1900         enum pipe pipe = crtc->pipe;
1901         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1902                                                                       pipe);
1903         enum pipe pch_transcoder;
1904         int reg;
1905         u32 val;
1906
1907         assert_planes_disabled(dev_priv, pipe);
1908         assert_cursor_disabled(dev_priv, pipe);
1909         assert_sprites_disabled(dev_priv, pipe);
1910
1911         if (HAS_PCH_LPT(dev_priv->dev))
1912                 pch_transcoder = TRANSCODER_A;
1913         else
1914                 pch_transcoder = pipe;
1915
1916         /*
1917          * A pipe without a PLL won't actually be able to drive bits from
1918          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1919          * need the check.
1920          */
1921         if (!HAS_PCH_SPLIT(dev_priv->dev))
1922                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1923                         assert_dsi_pll_enabled(dev_priv);
1924                 else
1925                         assert_pll_enabled(dev_priv, pipe);
1926         else {
1927                 if (crtc->config.has_pch_encoder) {
1928                         /* if driving the PCH, we need FDI enabled */
1929                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1930                         assert_fdi_tx_pll_enabled(dev_priv,
1931                                                   (enum pipe) cpu_transcoder);
1932                 }
1933                 /* FIXME: assert CPU port conditions for SNB+ */
1934         }
1935
1936         reg = PIPECONF(cpu_transcoder);
1937         val = I915_READ(reg);
1938         if (val & PIPECONF_ENABLE) {
1939                 WARN_ON(!(pipe == PIPE_A &&
1940                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1941                 return;
1942         }
1943
1944         I915_WRITE(reg, val | PIPECONF_ENABLE);
1945         POSTING_READ(reg);
1946 }
1947
1948 /**
1949  * intel_disable_pipe - disable a pipe, asserting requirements
1950  * @dev_priv: i915 private structure
1951  * @pipe: pipe to disable
1952  *
1953  * Disable @pipe, making sure that various hardware specific requirements
1954  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1955  *
1956  * @pipe should be %PIPE_A or %PIPE_B.
1957  *
1958  * Will wait until the pipe has shut down before returning.
1959  */
1960 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1961                                enum pipe pipe)
1962 {
1963         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1964                                                                       pipe);
1965         int reg;
1966         u32 val;
1967
1968         /*
1969          * Make sure planes won't keep trying to pump pixels to us,
1970          * or we might hang the display.
1971          */
1972         assert_planes_disabled(dev_priv, pipe);
1973         assert_cursor_disabled(dev_priv, pipe);
1974         assert_sprites_disabled(dev_priv, pipe);
1975
1976         /* Don't disable pipe A or pipe A PLLs if needed */
1977         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1978                 return;
1979
1980         reg = PIPECONF(cpu_transcoder);
1981         val = I915_READ(reg);
1982         if ((val & PIPECONF_ENABLE) == 0)
1983                 return;
1984
1985         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1986         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1987 }
1988
1989 /*
1990  * Plane regs are double buffered, going from enabled->disabled needs a
1991  * trigger in order to latch.  The display address reg provides this.
1992  */
1993 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1994                                enum plane plane)
1995 {
1996         struct drm_device *dev = dev_priv->dev;
1997         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1998
1999         I915_WRITE(reg, I915_READ(reg));
2000         POSTING_READ(reg);
2001 }
2002
2003 /**
2004  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2005  * @dev_priv: i915 private structure
2006  * @plane: plane to enable
2007  * @pipe: pipe being fed
2008  *
2009  * Enable @plane on @pipe, making sure that @pipe is running first.
2010  */
2011 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2012                                           enum plane plane, enum pipe pipe)
2013 {
2014         struct intel_crtc *intel_crtc =
2015                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2016         int reg;
2017         u32 val;
2018
2019         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2020         assert_pipe_enabled(dev_priv, pipe);
2021
2022         if (intel_crtc->primary_enabled)
2023                 return;
2024
2025         intel_crtc->primary_enabled = true;
2026
2027         reg = DSPCNTR(plane);
2028         val = I915_READ(reg);
2029         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2030
2031         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2032         intel_flush_primary_plane(dev_priv, plane);
2033         intel_wait_for_vblank(dev_priv->dev, pipe);
2034 }
2035
2036 /**
2037  * intel_disable_primary_hw_plane - disable the primary hardware plane
2038  * @dev_priv: i915 private structure
2039  * @plane: plane to disable
2040  * @pipe: pipe consuming the data
2041  *
2042  * Disable @plane; should be an independent operation.
2043  */
2044 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2045                                            enum plane plane, enum pipe pipe)
2046 {
2047         struct intel_crtc *intel_crtc =
2048                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2049         int reg;
2050         u32 val;
2051
2052         if (!intel_crtc->primary_enabled)
2053                 return;
2054
2055         intel_crtc->primary_enabled = false;
2056
2057         reg = DSPCNTR(plane);
2058         val = I915_READ(reg);
2059         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2060
2061         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2062         intel_flush_primary_plane(dev_priv, plane);
2063         intel_wait_for_vblank(dev_priv->dev, pipe);
2064 }
2065
2066 static bool need_vtd_wa(struct drm_device *dev)
2067 {
2068 #ifdef CONFIG_INTEL_IOMMU
2069         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2070                 return true;
2071 #endif
2072         return false;
2073 }
2074
2075 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2076 {
2077         int tile_height;
2078
2079         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2080         return ALIGN(height, tile_height);
2081 }
2082
2083 int
2084 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2085                            struct drm_i915_gem_object *obj,
2086                            struct intel_ring_buffer *pipelined)
2087 {
2088         struct drm_i915_private *dev_priv = dev->dev_private;
2089         u32 alignment;
2090         int ret;
2091
2092         switch (obj->tiling_mode) {
2093         case I915_TILING_NONE:
2094                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2095                         alignment = 128 * 1024;
2096                 else if (INTEL_INFO(dev)->gen >= 4)
2097                         alignment = 4 * 1024;
2098                 else
2099                         alignment = 64 * 1024;
2100                 break;
2101         case I915_TILING_X:
2102                 /* pin() will align the object as required by fence */
2103                 alignment = 0;
2104                 break;
2105         case I915_TILING_Y:
2106                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2107                 return -EINVAL;
2108         default:
2109                 BUG();
2110         }
2111
2112         /* Note that the w/a also requires 64 PTE of padding following the
2113          * bo. We currently fill all unused PTE with the shadow page and so
2114          * we should always have valid PTE following the scanout preventing
2115          * the VT-d warning.
2116          */
2117         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2118                 alignment = 256 * 1024;
2119
2120         dev_priv->mm.interruptible = false;
2121         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2122         if (ret)
2123                 goto err_interruptible;
2124
2125         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2126          * fence, whereas 965+ only requires a fence if using
2127          * framebuffer compression.  For simplicity, we always install
2128          * a fence as the cost is not that onerous.
2129          */
2130         ret = i915_gem_object_get_fence(obj);
2131         if (ret)
2132                 goto err_unpin;
2133
2134         i915_gem_object_pin_fence(obj);
2135
2136         dev_priv->mm.interruptible = true;
2137         return 0;
2138
2139 err_unpin:
2140         i915_gem_object_unpin_from_display_plane(obj);
2141 err_interruptible:
2142         dev_priv->mm.interruptible = true;
2143         return ret;
2144 }
2145
2146 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2147 {
2148         i915_gem_object_unpin_fence(obj);
2149         i915_gem_object_unpin_from_display_plane(obj);
2150 }
2151
2152 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2153  * is assumed to be a power-of-two. */
2154 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2155                                              unsigned int tiling_mode,
2156                                              unsigned int cpp,
2157                                              unsigned int pitch)
2158 {
2159         if (tiling_mode != I915_TILING_NONE) {
2160                 unsigned int tile_rows, tiles;
2161
2162                 tile_rows = *y / 8;
2163                 *y %= 8;
2164
2165                 tiles = *x / (512/cpp);
2166                 *x %= 512/cpp;
2167
2168                 return tile_rows * pitch * 8 + tiles * 4096;
2169         } else {
2170                 unsigned int offset;
2171
2172                 offset = *y * pitch + *x * cpp;
2173                 *y = 0;
2174                 *x = (offset & 4095) / cpp;
2175                 return offset & -4096;
2176         }
2177 }
2178
2179 int intel_format_to_fourcc(int format)
2180 {
2181         switch (format) {
2182         case DISPPLANE_8BPP:
2183                 return DRM_FORMAT_C8;
2184         case DISPPLANE_BGRX555:
2185                 return DRM_FORMAT_XRGB1555;
2186         case DISPPLANE_BGRX565:
2187                 return DRM_FORMAT_RGB565;
2188         default:
2189         case DISPPLANE_BGRX888:
2190                 return DRM_FORMAT_XRGB8888;
2191         case DISPPLANE_RGBX888:
2192                 return DRM_FORMAT_XBGR8888;
2193         case DISPPLANE_BGRX101010:
2194                 return DRM_FORMAT_XRGB2101010;
2195         case DISPPLANE_RGBX101010:
2196                 return DRM_FORMAT_XBGR2101010;
2197         }
2198 }
2199
2200 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2201                                   struct intel_plane_config *plane_config)
2202 {
2203         struct drm_device *dev = crtc->base.dev;
2204         struct drm_i915_gem_object *obj = NULL;
2205         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2206         u32 base = plane_config->base;
2207
2208         if (plane_config->size == 0)
2209                 return false;
2210
2211         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2212                                                              plane_config->size);
2213         if (!obj)
2214                 return false;
2215
2216         if (plane_config->tiled) {
2217                 obj->tiling_mode = I915_TILING_X;
2218                 obj->stride = crtc->base.primary->fb->pitches[0];
2219         }
2220
2221         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2222         mode_cmd.width = crtc->base.primary->fb->width;
2223         mode_cmd.height = crtc->base.primary->fb->height;
2224         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2225
2226         mutex_lock(&dev->struct_mutex);
2227
2228         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2229                                    &mode_cmd, obj)) {
2230                 DRM_DEBUG_KMS("intel fb init failed\n");
2231                 goto out_unref_obj;
2232         }
2233
2234         mutex_unlock(&dev->struct_mutex);
2235
2236         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2237         return true;
2238
2239 out_unref_obj:
2240         drm_gem_object_unreference(&obj->base);
2241         mutex_unlock(&dev->struct_mutex);
2242         return false;
2243 }
2244
2245 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2246                                  struct intel_plane_config *plane_config)
2247 {
2248         struct drm_device *dev = intel_crtc->base.dev;
2249         struct drm_crtc *c;
2250         struct intel_crtc *i;
2251         struct intel_framebuffer *fb;
2252
2253         if (!intel_crtc->base.primary->fb)
2254                 return;
2255
2256         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2257                 return;
2258
2259         kfree(intel_crtc->base.primary->fb);
2260         intel_crtc->base.primary->fb = NULL;
2261
2262         /*
2263          * Failed to alloc the obj, check to see if we should share
2264          * an fb with another CRTC instead
2265          */
2266         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2267                 i = to_intel_crtc(c);
2268
2269                 if (c == &intel_crtc->base)
2270                         continue;
2271
2272                 if (!i->active || !c->primary->fb)
2273                         continue;
2274
2275                 fb = to_intel_framebuffer(c->primary->fb);
2276                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2277                         drm_framebuffer_reference(c->primary->fb);
2278                         intel_crtc->base.primary->fb = c->primary->fb;
2279                         break;
2280                 }
2281         }
2282 }
2283
2284 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2285                                      struct drm_framebuffer *fb,
2286                                      int x, int y)
2287 {
2288         struct drm_device *dev = crtc->dev;
2289         struct drm_i915_private *dev_priv = dev->dev_private;
2290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291         struct intel_framebuffer *intel_fb;
2292         struct drm_i915_gem_object *obj;
2293         int plane = intel_crtc->plane;
2294         unsigned long linear_offset;
2295         u32 dspcntr;
2296         u32 reg;
2297
2298         intel_fb = to_intel_framebuffer(fb);
2299         obj = intel_fb->obj;
2300
2301         reg = DSPCNTR(plane);
2302         dspcntr = I915_READ(reg);
2303         /* Mask out pixel format bits in case we change it */
2304         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2305         switch (fb->pixel_format) {
2306         case DRM_FORMAT_C8:
2307                 dspcntr |= DISPPLANE_8BPP;
2308                 break;
2309         case DRM_FORMAT_XRGB1555:
2310         case DRM_FORMAT_ARGB1555:
2311                 dspcntr |= DISPPLANE_BGRX555;
2312                 break;
2313         case DRM_FORMAT_RGB565:
2314                 dspcntr |= DISPPLANE_BGRX565;
2315                 break;
2316         case DRM_FORMAT_XRGB8888:
2317         case DRM_FORMAT_ARGB8888:
2318                 dspcntr |= DISPPLANE_BGRX888;
2319                 break;
2320         case DRM_FORMAT_XBGR8888:
2321         case DRM_FORMAT_ABGR8888:
2322                 dspcntr |= DISPPLANE_RGBX888;
2323                 break;
2324         case DRM_FORMAT_XRGB2101010:
2325         case DRM_FORMAT_ARGB2101010:
2326                 dspcntr |= DISPPLANE_BGRX101010;
2327                 break;
2328         case DRM_FORMAT_XBGR2101010:
2329         case DRM_FORMAT_ABGR2101010:
2330                 dspcntr |= DISPPLANE_RGBX101010;
2331                 break;
2332         default:
2333                 BUG();
2334         }
2335
2336         if (INTEL_INFO(dev)->gen >= 4) {
2337                 if (obj->tiling_mode != I915_TILING_NONE)
2338                         dspcntr |= DISPPLANE_TILED;
2339                 else
2340                         dspcntr &= ~DISPPLANE_TILED;
2341         }
2342
2343         if (IS_G4X(dev))
2344                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2345
2346         I915_WRITE(reg, dspcntr);
2347
2348         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2349
2350         if (INTEL_INFO(dev)->gen >= 4) {
2351                 intel_crtc->dspaddr_offset =
2352                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2353                                                        fb->bits_per_pixel / 8,
2354                                                        fb->pitches[0]);
2355                 linear_offset -= intel_crtc->dspaddr_offset;
2356         } else {
2357                 intel_crtc->dspaddr_offset = linear_offset;
2358         }
2359
2360         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2361                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2362                       fb->pitches[0]);
2363         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2364         if (INTEL_INFO(dev)->gen >= 4) {
2365                 I915_WRITE(DSPSURF(plane),
2366                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2367                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2368                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2369         } else
2370                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2371         POSTING_READ(reg);
2372
2373         return 0;
2374 }
2375
2376 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2377                                          struct drm_framebuffer *fb,
2378                                          int x, int y)
2379 {
2380         struct drm_device *dev = crtc->dev;
2381         struct drm_i915_private *dev_priv = dev->dev_private;
2382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2383         struct intel_framebuffer *intel_fb;
2384         struct drm_i915_gem_object *obj;
2385         int plane = intel_crtc->plane;
2386         unsigned long linear_offset;
2387         u32 dspcntr;
2388         u32 reg;
2389
2390         intel_fb = to_intel_framebuffer(fb);
2391         obj = intel_fb->obj;
2392
2393         reg = DSPCNTR(plane);
2394         dspcntr = I915_READ(reg);
2395         /* Mask out pixel format bits in case we change it */
2396         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2397         switch (fb->pixel_format) {
2398         case DRM_FORMAT_C8:
2399                 dspcntr |= DISPPLANE_8BPP;
2400                 break;
2401         case DRM_FORMAT_RGB565:
2402                 dspcntr |= DISPPLANE_BGRX565;
2403                 break;
2404         case DRM_FORMAT_XRGB8888:
2405         case DRM_FORMAT_ARGB8888:
2406                 dspcntr |= DISPPLANE_BGRX888;
2407                 break;
2408         case DRM_FORMAT_XBGR8888:
2409         case DRM_FORMAT_ABGR8888:
2410                 dspcntr |= DISPPLANE_RGBX888;
2411                 break;
2412         case DRM_FORMAT_XRGB2101010:
2413         case DRM_FORMAT_ARGB2101010:
2414                 dspcntr |= DISPPLANE_BGRX101010;
2415                 break;
2416         case DRM_FORMAT_XBGR2101010:
2417         case DRM_FORMAT_ABGR2101010:
2418                 dspcntr |= DISPPLANE_RGBX101010;
2419                 break;
2420         default:
2421                 BUG();
2422         }
2423
2424         if (obj->tiling_mode != I915_TILING_NONE)
2425                 dspcntr |= DISPPLANE_TILED;
2426         else
2427                 dspcntr &= ~DISPPLANE_TILED;
2428
2429         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2430                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2431         else
2432                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2433
2434         I915_WRITE(reg, dspcntr);
2435
2436         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2437         intel_crtc->dspaddr_offset =
2438                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2439                                                fb->bits_per_pixel / 8,
2440                                                fb->pitches[0]);
2441         linear_offset -= intel_crtc->dspaddr_offset;
2442
2443         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2444                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2445                       fb->pitches[0]);
2446         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2447         I915_WRITE(DSPSURF(plane),
2448                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2449         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2450                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2451         } else {
2452                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2453                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2454         }
2455         POSTING_READ(reg);
2456
2457         return 0;
2458 }
2459
2460 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2461 static int
2462 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2463                            int x, int y, enum mode_set_atomic state)
2464 {
2465         struct drm_device *dev = crtc->dev;
2466         struct drm_i915_private *dev_priv = dev->dev_private;
2467
2468         if (dev_priv->display.disable_fbc)
2469                 dev_priv->display.disable_fbc(dev);
2470         intel_increase_pllclock(crtc);
2471
2472         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2473 }
2474
2475 void intel_display_handle_reset(struct drm_device *dev)
2476 {
2477         struct drm_i915_private *dev_priv = dev->dev_private;
2478         struct drm_crtc *crtc;
2479
2480         /*
2481          * Flips in the rings have been nuked by the reset,
2482          * so complete all pending flips so that user space
2483          * will get its events and not get stuck.
2484          *
2485          * Also update the base address of all primary
2486          * planes to the the last fb to make sure we're
2487          * showing the correct fb after a reset.
2488          *
2489          * Need to make two loops over the crtcs so that we
2490          * don't try to grab a crtc mutex before the
2491          * pending_flip_queue really got woken up.
2492          */
2493
2494         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2495                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2496                 enum plane plane = intel_crtc->plane;
2497
2498                 intel_prepare_page_flip(dev, plane);
2499                 intel_finish_page_flip_plane(dev, plane);
2500         }
2501
2502         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2503                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2504
2505                 mutex_lock(&crtc->mutex);
2506                 /*
2507                  * FIXME: Once we have proper support for primary planes (and
2508                  * disabling them without disabling the entire crtc) allow again
2509                  * a NULL crtc->primary->fb.
2510                  */
2511                 if (intel_crtc->active && crtc->primary->fb)
2512                         dev_priv->display.update_primary_plane(crtc,
2513                                                                crtc->primary->fb,
2514                                                                crtc->x,
2515                                                                crtc->y);
2516                 mutex_unlock(&crtc->mutex);
2517         }
2518 }
2519
2520 static int
2521 intel_finish_fb(struct drm_framebuffer *old_fb)
2522 {
2523         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2524         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2525         bool was_interruptible = dev_priv->mm.interruptible;
2526         int ret;
2527
2528         /* Big Hammer, we also need to ensure that any pending
2529          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2530          * current scanout is retired before unpinning the old
2531          * framebuffer.
2532          *
2533          * This should only fail upon a hung GPU, in which case we
2534          * can safely continue.
2535          */
2536         dev_priv->mm.interruptible = false;
2537         ret = i915_gem_object_finish_gpu(obj);
2538         dev_priv->mm.interruptible = was_interruptible;
2539
2540         return ret;
2541 }
2542
2543 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2544 {
2545         struct drm_device *dev = crtc->dev;
2546         struct drm_i915_private *dev_priv = dev->dev_private;
2547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2548         unsigned long flags;
2549         bool pending;
2550
2551         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2552             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2553                 return false;
2554
2555         spin_lock_irqsave(&dev->event_lock, flags);
2556         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2557         spin_unlock_irqrestore(&dev->event_lock, flags);
2558
2559         return pending;
2560 }
2561
2562 static int
2563 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2564                     struct drm_framebuffer *fb)
2565 {
2566         struct drm_device *dev = crtc->dev;
2567         struct drm_i915_private *dev_priv = dev->dev_private;
2568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2569         struct drm_framebuffer *old_fb;
2570         int ret;
2571
2572         if (intel_crtc_has_pending_flip(crtc)) {
2573                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2574                 return -EBUSY;
2575         }
2576
2577         /* no fb bound */
2578         if (!fb) {
2579                 DRM_ERROR("No FB bound\n");
2580                 return 0;
2581         }
2582
2583         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2584                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2585                           plane_name(intel_crtc->plane),
2586                           INTEL_INFO(dev)->num_pipes);
2587                 return -EINVAL;
2588         }
2589
2590         mutex_lock(&dev->struct_mutex);
2591         ret = intel_pin_and_fence_fb_obj(dev,
2592                                          to_intel_framebuffer(fb)->obj,
2593                                          NULL);
2594         mutex_unlock(&dev->struct_mutex);
2595         if (ret != 0) {
2596                 DRM_ERROR("pin & fence failed\n");
2597                 return ret;
2598         }
2599
2600         /*
2601          * Update pipe size and adjust fitter if needed: the reason for this is
2602          * that in compute_mode_changes we check the native mode (not the pfit
2603          * mode) to see if we can flip rather than do a full mode set. In the
2604          * fastboot case, we'll flip, but if we don't update the pipesrc and
2605          * pfit state, we'll end up with a big fb scanned out into the wrong
2606          * sized surface.
2607          *
2608          * To fix this properly, we need to hoist the checks up into
2609          * compute_mode_changes (or above), check the actual pfit state and
2610          * whether the platform allows pfit disable with pipe active, and only
2611          * then update the pipesrc and pfit state, even on the flip path.
2612          */
2613         if (i915.fastboot) {
2614                 const struct drm_display_mode *adjusted_mode =
2615                         &intel_crtc->config.adjusted_mode;
2616
2617                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2618                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2619                            (adjusted_mode->crtc_vdisplay - 1));
2620                 if (!intel_crtc->config.pch_pfit.enabled &&
2621                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2622                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2623                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2624                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2625                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2626                 }
2627                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2628                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2629         }
2630
2631         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2632         if (ret) {
2633                 mutex_lock(&dev->struct_mutex);
2634                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2635                 mutex_unlock(&dev->struct_mutex);
2636                 DRM_ERROR("failed to update base address\n");
2637                 return ret;
2638         }
2639
2640         old_fb = crtc->primary->fb;
2641         crtc->primary->fb = fb;
2642         crtc->x = x;
2643         crtc->y = y;
2644
2645         if (old_fb) {
2646                 if (intel_crtc->active && old_fb != fb)
2647                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2648                 mutex_lock(&dev->struct_mutex);
2649                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2650                 mutex_unlock(&dev->struct_mutex);
2651         }
2652
2653         mutex_lock(&dev->struct_mutex);
2654         intel_update_fbc(dev);
2655         intel_edp_psr_update(dev);
2656         mutex_unlock(&dev->struct_mutex);
2657
2658         return 0;
2659 }
2660
2661 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2662 {
2663         struct drm_device *dev = crtc->dev;
2664         struct drm_i915_private *dev_priv = dev->dev_private;
2665         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2666         int pipe = intel_crtc->pipe;
2667         u32 reg, temp;
2668
2669         /* enable normal train */
2670         reg = FDI_TX_CTL(pipe);
2671         temp = I915_READ(reg);
2672         if (IS_IVYBRIDGE(dev)) {
2673                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2674                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2675         } else {
2676                 temp &= ~FDI_LINK_TRAIN_NONE;
2677                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2678         }
2679         I915_WRITE(reg, temp);
2680
2681         reg = FDI_RX_CTL(pipe);
2682         temp = I915_READ(reg);
2683         if (HAS_PCH_CPT(dev)) {
2684                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2685                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2686         } else {
2687                 temp &= ~FDI_LINK_TRAIN_NONE;
2688                 temp |= FDI_LINK_TRAIN_NONE;
2689         }
2690         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2691
2692         /* wait one idle pattern time */
2693         POSTING_READ(reg);
2694         udelay(1000);
2695
2696         /* IVB wants error correction enabled */
2697         if (IS_IVYBRIDGE(dev))
2698                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2699                            FDI_FE_ERRC_ENABLE);
2700 }
2701
2702 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2703 {
2704         return crtc->base.enabled && crtc->active &&
2705                 crtc->config.has_pch_encoder;
2706 }
2707
2708 static void ivb_modeset_global_resources(struct drm_device *dev)
2709 {
2710         struct drm_i915_private *dev_priv = dev->dev_private;
2711         struct intel_crtc *pipe_B_crtc =
2712                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2713         struct intel_crtc *pipe_C_crtc =
2714                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2715         uint32_t temp;
2716
2717         /*
2718          * When everything is off disable fdi C so that we could enable fdi B
2719          * with all lanes. Note that we don't care about enabled pipes without
2720          * an enabled pch encoder.
2721          */
2722         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2723             !pipe_has_enabled_pch(pipe_C_crtc)) {
2724                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2725                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2726
2727                 temp = I915_READ(SOUTH_CHICKEN1);
2728                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2729                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2730                 I915_WRITE(SOUTH_CHICKEN1, temp);
2731         }
2732 }
2733
2734 /* The FDI link training functions for ILK/Ibexpeak. */
2735 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2736 {
2737         struct drm_device *dev = crtc->dev;
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740         int pipe = intel_crtc->pipe;
2741         u32 reg, temp, tries;
2742
2743         /* FDI needs bits from pipe first */
2744         assert_pipe_enabled(dev_priv, pipe);
2745
2746         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2747            for train result */
2748         reg = FDI_RX_IMR(pipe);
2749         temp = I915_READ(reg);
2750         temp &= ~FDI_RX_SYMBOL_LOCK;
2751         temp &= ~FDI_RX_BIT_LOCK;
2752         I915_WRITE(reg, temp);
2753         I915_READ(reg);
2754         udelay(150);
2755
2756         /* enable CPU FDI TX and PCH FDI RX */
2757         reg = FDI_TX_CTL(pipe);
2758         temp = I915_READ(reg);
2759         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2760         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2761         temp &= ~FDI_LINK_TRAIN_NONE;
2762         temp |= FDI_LINK_TRAIN_PATTERN_1;
2763         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2764
2765         reg = FDI_RX_CTL(pipe);
2766         temp = I915_READ(reg);
2767         temp &= ~FDI_LINK_TRAIN_NONE;
2768         temp |= FDI_LINK_TRAIN_PATTERN_1;
2769         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2770
2771         POSTING_READ(reg);
2772         udelay(150);
2773
2774         /* Ironlake workaround, enable clock pointer after FDI enable*/
2775         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2776         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2777                    FDI_RX_PHASE_SYNC_POINTER_EN);
2778
2779         reg = FDI_RX_IIR(pipe);
2780         for (tries = 0; tries < 5; tries++) {
2781                 temp = I915_READ(reg);
2782                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2783
2784                 if ((temp & FDI_RX_BIT_LOCK)) {
2785                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2786                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2787                         break;
2788                 }
2789         }
2790         if (tries == 5)
2791                 DRM_ERROR("FDI train 1 fail!\n");
2792
2793         /* Train 2 */
2794         reg = FDI_TX_CTL(pipe);
2795         temp = I915_READ(reg);
2796         temp &= ~FDI_LINK_TRAIN_NONE;
2797         temp |= FDI_LINK_TRAIN_PATTERN_2;
2798         I915_WRITE(reg, temp);
2799
2800         reg = FDI_RX_CTL(pipe);
2801         temp = I915_READ(reg);
2802         temp &= ~FDI_LINK_TRAIN_NONE;
2803         temp |= FDI_LINK_TRAIN_PATTERN_2;
2804         I915_WRITE(reg, temp);
2805
2806         POSTING_READ(reg);
2807         udelay(150);
2808
2809         reg = FDI_RX_IIR(pipe);
2810         for (tries = 0; tries < 5; tries++) {
2811                 temp = I915_READ(reg);
2812                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2813
2814                 if (temp & FDI_RX_SYMBOL_LOCK) {
2815                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2816                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2817                         break;
2818                 }
2819         }
2820         if (tries == 5)
2821                 DRM_ERROR("FDI train 2 fail!\n");
2822
2823         DRM_DEBUG_KMS("FDI train done\n");
2824
2825 }
2826
2827 static const int snb_b_fdi_train_param[] = {
2828         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2829         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2830         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2831         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2832 };
2833
2834 /* The FDI link training functions for SNB/Cougarpoint. */
2835 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2836 {
2837         struct drm_device *dev = crtc->dev;
2838         struct drm_i915_private *dev_priv = dev->dev_private;
2839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2840         int pipe = intel_crtc->pipe;
2841         u32 reg, temp, i, retry;
2842
2843         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2844            for train result */
2845         reg = FDI_RX_IMR(pipe);
2846         temp = I915_READ(reg);
2847         temp &= ~FDI_RX_SYMBOL_LOCK;
2848         temp &= ~FDI_RX_BIT_LOCK;
2849         I915_WRITE(reg, temp);
2850
2851         POSTING_READ(reg);
2852         udelay(150);
2853
2854         /* enable CPU FDI TX and PCH FDI RX */
2855         reg = FDI_TX_CTL(pipe);
2856         temp = I915_READ(reg);
2857         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2858         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2859         temp &= ~FDI_LINK_TRAIN_NONE;
2860         temp |= FDI_LINK_TRAIN_PATTERN_1;
2861         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2862         /* SNB-B */
2863         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2864         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2865
2866         I915_WRITE(FDI_RX_MISC(pipe),
2867                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2868
2869         reg = FDI_RX_CTL(pipe);
2870         temp = I915_READ(reg);
2871         if (HAS_PCH_CPT(dev)) {
2872                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2873                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2874         } else {
2875                 temp &= ~FDI_LINK_TRAIN_NONE;
2876                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2877         }
2878         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2879
2880         POSTING_READ(reg);
2881         udelay(150);
2882
2883         for (i = 0; i < 4; i++) {
2884                 reg = FDI_TX_CTL(pipe);
2885                 temp = I915_READ(reg);
2886                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2887                 temp |= snb_b_fdi_train_param[i];
2888                 I915_WRITE(reg, temp);
2889
2890                 POSTING_READ(reg);
2891                 udelay(500);
2892
2893                 for (retry = 0; retry < 5; retry++) {
2894                         reg = FDI_RX_IIR(pipe);
2895                         temp = I915_READ(reg);
2896                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2897                         if (temp & FDI_RX_BIT_LOCK) {
2898                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2899                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2900                                 break;
2901                         }
2902                         udelay(50);
2903                 }
2904                 if (retry < 5)
2905                         break;
2906         }
2907         if (i == 4)
2908                 DRM_ERROR("FDI train 1 fail!\n");
2909
2910         /* Train 2 */
2911         reg = FDI_TX_CTL(pipe);
2912         temp = I915_READ(reg);
2913         temp &= ~FDI_LINK_TRAIN_NONE;
2914         temp |= FDI_LINK_TRAIN_PATTERN_2;
2915         if (IS_GEN6(dev)) {
2916                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2917                 /* SNB-B */
2918                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2919         }
2920         I915_WRITE(reg, temp);
2921
2922         reg = FDI_RX_CTL(pipe);
2923         temp = I915_READ(reg);
2924         if (HAS_PCH_CPT(dev)) {
2925                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2926                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2927         } else {
2928                 temp &= ~FDI_LINK_TRAIN_NONE;
2929                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2930         }
2931         I915_WRITE(reg, temp);
2932
2933         POSTING_READ(reg);
2934         udelay(150);
2935
2936         for (i = 0; i < 4; i++) {
2937                 reg = FDI_TX_CTL(pipe);
2938                 temp = I915_READ(reg);
2939                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2940                 temp |= snb_b_fdi_train_param[i];
2941                 I915_WRITE(reg, temp);
2942
2943                 POSTING_READ(reg);
2944                 udelay(500);
2945
2946                 for (retry = 0; retry < 5; retry++) {
2947                         reg = FDI_RX_IIR(pipe);
2948                         temp = I915_READ(reg);
2949                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2950                         if (temp & FDI_RX_SYMBOL_LOCK) {
2951                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2952                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2953                                 break;
2954                         }
2955                         udelay(50);
2956                 }
2957                 if (retry < 5)
2958                         break;
2959         }
2960         if (i == 4)
2961                 DRM_ERROR("FDI train 2 fail!\n");
2962
2963         DRM_DEBUG_KMS("FDI train done.\n");
2964 }
2965
2966 /* Manual link training for Ivy Bridge A0 parts */
2967 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2968 {
2969         struct drm_device *dev = crtc->dev;
2970         struct drm_i915_private *dev_priv = dev->dev_private;
2971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2972         int pipe = intel_crtc->pipe;
2973         u32 reg, temp, i, j;
2974
2975         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2976            for train result */
2977         reg = FDI_RX_IMR(pipe);
2978         temp = I915_READ(reg);
2979         temp &= ~FDI_RX_SYMBOL_LOCK;
2980         temp &= ~FDI_RX_BIT_LOCK;
2981         I915_WRITE(reg, temp);
2982
2983         POSTING_READ(reg);
2984         udelay(150);
2985
2986         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2987                       I915_READ(FDI_RX_IIR(pipe)));
2988
2989         /* Try each vswing and preemphasis setting twice before moving on */
2990         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2991                 /* disable first in case we need to retry */
2992                 reg = FDI_TX_CTL(pipe);
2993                 temp = I915_READ(reg);
2994                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2995                 temp &= ~FDI_TX_ENABLE;
2996                 I915_WRITE(reg, temp);
2997
2998                 reg = FDI_RX_CTL(pipe);
2999                 temp = I915_READ(reg);
3000                 temp &= ~FDI_LINK_TRAIN_AUTO;
3001                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3002                 temp &= ~FDI_RX_ENABLE;
3003                 I915_WRITE(reg, temp);
3004
3005                 /* enable CPU FDI TX and PCH FDI RX */
3006                 reg = FDI_TX_CTL(pipe);
3007                 temp = I915_READ(reg);
3008                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3009                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3010                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3011                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3012                 temp |= snb_b_fdi_train_param[j/2];
3013                 temp |= FDI_COMPOSITE_SYNC;
3014                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3015
3016                 I915_WRITE(FDI_RX_MISC(pipe),
3017                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3018
3019                 reg = FDI_RX_CTL(pipe);
3020                 temp = I915_READ(reg);
3021                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3022                 temp |= FDI_COMPOSITE_SYNC;
3023                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3024
3025                 POSTING_READ(reg);
3026                 udelay(1); /* should be 0.5us */
3027
3028                 for (i = 0; i < 4; i++) {
3029                         reg = FDI_RX_IIR(pipe);
3030                         temp = I915_READ(reg);
3031                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3032
3033                         if (temp & FDI_RX_BIT_LOCK ||
3034                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3035                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3036                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3037                                               i);
3038                                 break;
3039                         }
3040                         udelay(1); /* should be 0.5us */
3041                 }
3042                 if (i == 4) {
3043                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3044                         continue;
3045                 }
3046
3047                 /* Train 2 */
3048                 reg = FDI_TX_CTL(pipe);
3049                 temp = I915_READ(reg);
3050                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3051                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3052                 I915_WRITE(reg, temp);
3053
3054                 reg = FDI_RX_CTL(pipe);
3055                 temp = I915_READ(reg);
3056                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3057                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3058                 I915_WRITE(reg, temp);
3059
3060                 POSTING_READ(reg);
3061                 udelay(2); /* should be 1.5us */
3062
3063                 for (i = 0; i < 4; i++) {
3064                         reg = FDI_RX_IIR(pipe);
3065                         temp = I915_READ(reg);
3066                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3067
3068                         if (temp & FDI_RX_SYMBOL_LOCK ||
3069                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3070                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3071                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3072                                               i);
3073                                 goto train_done;
3074                         }
3075                         udelay(2); /* should be 1.5us */
3076                 }
3077                 if (i == 4)
3078                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3079         }
3080
3081 train_done:
3082         DRM_DEBUG_KMS("FDI train done.\n");
3083 }
3084
3085 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3086 {
3087         struct drm_device *dev = intel_crtc->base.dev;
3088         struct drm_i915_private *dev_priv = dev->dev_private;
3089         int pipe = intel_crtc->pipe;
3090         u32 reg, temp;
3091
3092
3093         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3094         reg = FDI_RX_CTL(pipe);
3095         temp = I915_READ(reg);
3096         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3097         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3098         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3099         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3100
3101         POSTING_READ(reg);
3102         udelay(200);
3103
3104         /* Switch from Rawclk to PCDclk */
3105         temp = I915_READ(reg);
3106         I915_WRITE(reg, temp | FDI_PCDCLK);
3107
3108         POSTING_READ(reg);
3109         udelay(200);
3110
3111         /* Enable CPU FDI TX PLL, always on for Ironlake */
3112         reg = FDI_TX_CTL(pipe);
3113         temp = I915_READ(reg);
3114         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3115                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3116
3117                 POSTING_READ(reg);
3118                 udelay(100);
3119         }
3120 }
3121
3122 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3123 {
3124         struct drm_device *dev = intel_crtc->base.dev;
3125         struct drm_i915_private *dev_priv = dev->dev_private;
3126         int pipe = intel_crtc->pipe;
3127         u32 reg, temp;
3128
3129         /* Switch from PCDclk to Rawclk */
3130         reg = FDI_RX_CTL(pipe);
3131         temp = I915_READ(reg);
3132         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3133
3134         /* Disable CPU FDI TX PLL */
3135         reg = FDI_TX_CTL(pipe);
3136         temp = I915_READ(reg);
3137         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3138
3139         POSTING_READ(reg);
3140         udelay(100);
3141
3142         reg = FDI_RX_CTL(pipe);
3143         temp = I915_READ(reg);
3144         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3145
3146         /* Wait for the clocks to turn off. */
3147         POSTING_READ(reg);
3148         udelay(100);
3149 }
3150
3151 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3152 {
3153         struct drm_device *dev = crtc->dev;
3154         struct drm_i915_private *dev_priv = dev->dev_private;
3155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3156         int pipe = intel_crtc->pipe;
3157         u32 reg, temp;
3158
3159         /* disable CPU FDI tx and PCH FDI rx */
3160         reg = FDI_TX_CTL(pipe);
3161         temp = I915_READ(reg);
3162         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3163         POSTING_READ(reg);
3164
3165         reg = FDI_RX_CTL(pipe);
3166         temp = I915_READ(reg);
3167         temp &= ~(0x7 << 16);
3168         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3169         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3170
3171         POSTING_READ(reg);
3172         udelay(100);
3173
3174         /* Ironlake workaround, disable clock pointer after downing FDI */
3175         if (HAS_PCH_IBX(dev)) {
3176                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3177         }
3178
3179         /* still set train pattern 1 */
3180         reg = FDI_TX_CTL(pipe);
3181         temp = I915_READ(reg);
3182         temp &= ~FDI_LINK_TRAIN_NONE;
3183         temp |= FDI_LINK_TRAIN_PATTERN_1;
3184         I915_WRITE(reg, temp);
3185
3186         reg = FDI_RX_CTL(pipe);
3187         temp = I915_READ(reg);
3188         if (HAS_PCH_CPT(dev)) {
3189                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3190                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3191         } else {
3192                 temp &= ~FDI_LINK_TRAIN_NONE;
3193                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3194         }
3195         /* BPC in FDI rx is consistent with that in PIPECONF */
3196         temp &= ~(0x07 << 16);
3197         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3198         I915_WRITE(reg, temp);
3199
3200         POSTING_READ(reg);
3201         udelay(100);
3202 }
3203
3204 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3205 {
3206         struct intel_crtc *crtc;
3207
3208         /* Note that we don't need to be called with mode_config.lock here
3209          * as our list of CRTC objects is static for the lifetime of the
3210          * device and so cannot disappear as we iterate. Similarly, we can
3211          * happily treat the predicates as racy, atomic checks as userspace
3212          * cannot claim and pin a new fb without at least acquring the
3213          * struct_mutex and so serialising with us.
3214          */
3215         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3216                 if (atomic_read(&crtc->unpin_work_count) == 0)
3217                         continue;
3218
3219                 if (crtc->unpin_work)
3220                         intel_wait_for_vblank(dev, crtc->pipe);
3221
3222                 return true;
3223         }
3224
3225         return false;
3226 }
3227
3228 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3229 {
3230         struct drm_device *dev = crtc->dev;
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232
3233         if (crtc->primary->fb == NULL)
3234                 return;
3235
3236         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3237
3238         wait_event(dev_priv->pending_flip_queue,
3239                    !intel_crtc_has_pending_flip(crtc));
3240
3241         mutex_lock(&dev->struct_mutex);
3242         intel_finish_fb(crtc->primary->fb);
3243         mutex_unlock(&dev->struct_mutex);
3244 }
3245
3246 /* Program iCLKIP clock to the desired frequency */
3247 static void lpt_program_iclkip(struct drm_crtc *crtc)
3248 {
3249         struct drm_device *dev = crtc->dev;
3250         struct drm_i915_private *dev_priv = dev->dev_private;
3251         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3252         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3253         u32 temp;
3254
3255         mutex_lock(&dev_priv->dpio_lock);
3256
3257         /* It is necessary to ungate the pixclk gate prior to programming
3258          * the divisors, and gate it back when it is done.
3259          */
3260         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3261
3262         /* Disable SSCCTL */
3263         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3264                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3265                                 SBI_SSCCTL_DISABLE,
3266                         SBI_ICLK);
3267
3268         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3269         if (clock == 20000) {
3270                 auxdiv = 1;
3271                 divsel = 0x41;
3272                 phaseinc = 0x20;
3273         } else {
3274                 /* The iCLK virtual clock root frequency is in MHz,
3275                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3276                  * divisors, it is necessary to divide one by another, so we
3277                  * convert the virtual clock precision to KHz here for higher
3278                  * precision.
3279                  */
3280                 u32 iclk_virtual_root_freq = 172800 * 1000;
3281                 u32 iclk_pi_range = 64;
3282                 u32 desired_divisor, msb_divisor_value, pi_value;
3283
3284                 desired_divisor = (iclk_virtual_root_freq / clock);
3285                 msb_divisor_value = desired_divisor / iclk_pi_range;
3286                 pi_value = desired_divisor % iclk_pi_range;
3287
3288                 auxdiv = 0;
3289                 divsel = msb_divisor_value - 2;
3290                 phaseinc = pi_value;
3291         }
3292
3293         /* This should not happen with any sane values */
3294         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3295                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3296         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3297                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3298
3299         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3300                         clock,
3301                         auxdiv,
3302                         divsel,
3303                         phasedir,
3304                         phaseinc);
3305
3306         /* Program SSCDIVINTPHASE6 */
3307         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3308         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3309         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3310         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3311         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3312         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3313         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3314         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3315
3316         /* Program SSCAUXDIV */
3317         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3318         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3319         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3320         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3321
3322         /* Enable modulator and associated divider */
3323         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3324         temp &= ~SBI_SSCCTL_DISABLE;
3325         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3326
3327         /* Wait for initialization time */
3328         udelay(24);
3329
3330         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3331
3332         mutex_unlock(&dev_priv->dpio_lock);
3333 }
3334
3335 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3336                                                 enum pipe pch_transcoder)
3337 {
3338         struct drm_device *dev = crtc->base.dev;
3339         struct drm_i915_private *dev_priv = dev->dev_private;
3340         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3341
3342         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3343                    I915_READ(HTOTAL(cpu_transcoder)));
3344         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3345                    I915_READ(HBLANK(cpu_transcoder)));
3346         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3347                    I915_READ(HSYNC(cpu_transcoder)));
3348
3349         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3350                    I915_READ(VTOTAL(cpu_transcoder)));
3351         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3352                    I915_READ(VBLANK(cpu_transcoder)));
3353         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3354                    I915_READ(VSYNC(cpu_transcoder)));
3355         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3356                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3357 }
3358
3359 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3360 {
3361         struct drm_i915_private *dev_priv = dev->dev_private;
3362         uint32_t temp;
3363
3364         temp = I915_READ(SOUTH_CHICKEN1);
3365         if (temp & FDI_BC_BIFURCATION_SELECT)
3366                 return;
3367
3368         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3369         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3370
3371         temp |= FDI_BC_BIFURCATION_SELECT;
3372         DRM_DEBUG_KMS("enabling fdi C rx\n");
3373         I915_WRITE(SOUTH_CHICKEN1, temp);
3374         POSTING_READ(SOUTH_CHICKEN1);
3375 }
3376
3377 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3378 {
3379         struct drm_device *dev = intel_crtc->base.dev;
3380         struct drm_i915_private *dev_priv = dev->dev_private;
3381
3382         switch (intel_crtc->pipe) {
3383         case PIPE_A:
3384                 break;
3385         case PIPE_B:
3386                 if (intel_crtc->config.fdi_lanes > 2)
3387                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3388                 else
3389                         cpt_enable_fdi_bc_bifurcation(dev);
3390
3391                 break;
3392         case PIPE_C:
3393                 cpt_enable_fdi_bc_bifurcation(dev);
3394
3395                 break;
3396         default:
3397                 BUG();
3398         }
3399 }
3400
3401 /*
3402  * Enable PCH resources required for PCH ports:
3403  *   - PCH PLLs
3404  *   - FDI training & RX/TX
3405  *   - update transcoder timings
3406  *   - DP transcoding bits
3407  *   - transcoder
3408  */
3409 static void ironlake_pch_enable(struct drm_crtc *crtc)
3410 {
3411         struct drm_device *dev = crtc->dev;
3412         struct drm_i915_private *dev_priv = dev->dev_private;
3413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3414         int pipe = intel_crtc->pipe;
3415         u32 reg, temp;
3416
3417         assert_pch_transcoder_disabled(dev_priv, pipe);
3418
3419         if (IS_IVYBRIDGE(dev))
3420                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3421
3422         /* Write the TU size bits before fdi link training, so that error
3423          * detection works. */
3424         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3425                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3426
3427         /* For PCH output, training FDI link */
3428         dev_priv->display.fdi_link_train(crtc);
3429
3430         /* We need to program the right clock selection before writing the pixel
3431          * mutliplier into the DPLL. */
3432         if (HAS_PCH_CPT(dev)) {
3433                 u32 sel;
3434
3435                 temp = I915_READ(PCH_DPLL_SEL);
3436                 temp |= TRANS_DPLL_ENABLE(pipe);
3437                 sel = TRANS_DPLLB_SEL(pipe);
3438                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3439                         temp |= sel;
3440                 else
3441                         temp &= ~sel;
3442                 I915_WRITE(PCH_DPLL_SEL, temp);
3443         }
3444
3445         /* XXX: pch pll's can be enabled any time before we enable the PCH
3446          * transcoder, and we actually should do this to not upset any PCH
3447          * transcoder that already use the clock when we share it.
3448          *
3449          * Note that enable_shared_dpll tries to do the right thing, but
3450          * get_shared_dpll unconditionally resets the pll - we need that to have
3451          * the right LVDS enable sequence. */
3452         ironlake_enable_shared_dpll(intel_crtc);
3453
3454         /* set transcoder timing, panel must allow it */
3455         assert_panel_unlocked(dev_priv, pipe);
3456         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3457
3458         intel_fdi_normal_train(crtc);
3459
3460         /* For PCH DP, enable TRANS_DP_CTL */
3461         if (HAS_PCH_CPT(dev) &&
3462             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3463              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3464                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3465                 reg = TRANS_DP_CTL(pipe);
3466                 temp = I915_READ(reg);
3467                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3468                           TRANS_DP_SYNC_MASK |
3469                           TRANS_DP_BPC_MASK);
3470                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3471                          TRANS_DP_ENH_FRAMING);
3472                 temp |= bpc << 9; /* same format but at 11:9 */
3473
3474                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3475                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3476                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3477                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3478
3479                 switch (intel_trans_dp_port_sel(crtc)) {
3480                 case PCH_DP_B:
3481                         temp |= TRANS_DP_PORT_SEL_B;
3482                         break;
3483                 case PCH_DP_C:
3484                         temp |= TRANS_DP_PORT_SEL_C;
3485                         break;
3486                 case PCH_DP_D:
3487                         temp |= TRANS_DP_PORT_SEL_D;
3488                         break;
3489                 default:
3490                         BUG();
3491                 }
3492
3493                 I915_WRITE(reg, temp);
3494         }
3495
3496         ironlake_enable_pch_transcoder(dev_priv, pipe);
3497 }
3498
3499 static void lpt_pch_enable(struct drm_crtc *crtc)
3500 {
3501         struct drm_device *dev = crtc->dev;
3502         struct drm_i915_private *dev_priv = dev->dev_private;
3503         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3504         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3505
3506         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3507
3508         lpt_program_iclkip(crtc);
3509
3510         /* Set transcoder timing. */
3511         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3512
3513         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3514 }
3515
3516 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3517 {
3518         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3519
3520         if (pll == NULL)
3521                 return;
3522
3523         if (pll->refcount == 0) {
3524                 WARN(1, "bad %s refcount\n", pll->name);
3525                 return;
3526         }
3527
3528         if (--pll->refcount == 0) {
3529                 WARN_ON(pll->on);
3530                 WARN_ON(pll->active);
3531         }
3532
3533         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3534 }
3535
3536 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3537 {
3538         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3539         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3540         enum intel_dpll_id i;
3541
3542         if (pll) {
3543                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3544                               crtc->base.base.id, pll->name);
3545                 intel_put_shared_dpll(crtc);
3546         }
3547
3548         if (HAS_PCH_IBX(dev_priv->dev)) {
3549                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3550                 i = (enum intel_dpll_id) crtc->pipe;
3551                 pll = &dev_priv->shared_dplls[i];
3552
3553                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3554                               crtc->base.base.id, pll->name);
3555
3556                 goto found;
3557         }
3558
3559         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3560                 pll = &dev_priv->shared_dplls[i];
3561
3562                 /* Only want to check enabled timings first */
3563                 if (pll->refcount == 0)
3564                         continue;
3565
3566                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3567                            sizeof(pll->hw_state)) == 0) {
3568                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3569                                       crtc->base.base.id,
3570                                       pll->name, pll->refcount, pll->active);
3571
3572                         goto found;
3573                 }
3574         }
3575
3576         /* Ok no matching timings, maybe there's a free one? */
3577         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3578                 pll = &dev_priv->shared_dplls[i];
3579                 if (pll->refcount == 0) {
3580                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3581                                       crtc->base.base.id, pll->name);
3582                         goto found;
3583                 }
3584         }
3585
3586         return NULL;
3587
3588 found:
3589         crtc->config.shared_dpll = i;
3590         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3591                          pipe_name(crtc->pipe));
3592
3593         if (pll->active == 0) {
3594                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3595                        sizeof(pll->hw_state));
3596
3597                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3598                 WARN_ON(pll->on);
3599                 assert_shared_dpll_disabled(dev_priv, pll);
3600
3601                 pll->mode_set(dev_priv, pll);
3602         }
3603         pll->refcount++;
3604
3605         return pll;
3606 }
3607
3608 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3609 {
3610         struct drm_i915_private *dev_priv = dev->dev_private;
3611         int dslreg = PIPEDSL(pipe);
3612         u32 temp;
3613
3614         temp = I915_READ(dslreg);
3615         udelay(500);
3616         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3617                 if (wait_for(I915_READ(dslreg) != temp, 5))
3618                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3619         }
3620 }
3621
3622 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3623 {
3624         struct drm_device *dev = crtc->base.dev;
3625         struct drm_i915_private *dev_priv = dev->dev_private;
3626         int pipe = crtc->pipe;
3627
3628         if (crtc->config.pch_pfit.enabled) {
3629                 /* Force use of hard-coded filter coefficients
3630                  * as some pre-programmed values are broken,
3631                  * e.g. x201.
3632                  */
3633                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3634                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3635                                                  PF_PIPE_SEL_IVB(pipe));
3636                 else
3637                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3638                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3639                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3640         }
3641 }
3642
3643 static void intel_enable_planes(struct drm_crtc *crtc)
3644 {
3645         struct drm_device *dev = crtc->dev;
3646         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3647         struct drm_plane *plane;
3648         struct intel_plane *intel_plane;
3649
3650         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3651                 intel_plane = to_intel_plane(plane);
3652                 if (intel_plane->pipe == pipe)
3653                         intel_plane_restore(&intel_plane->base);
3654         }
3655 }
3656
3657 static void intel_disable_planes(struct drm_crtc *crtc)
3658 {
3659         struct drm_device *dev = crtc->dev;
3660         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3661         struct drm_plane *plane;
3662         struct intel_plane *intel_plane;
3663
3664         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3665                 intel_plane = to_intel_plane(plane);
3666                 if (intel_plane->pipe == pipe)
3667                         intel_plane_disable(&intel_plane->base);
3668         }
3669 }
3670
3671 void hsw_enable_ips(struct intel_crtc *crtc)
3672 {
3673         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3674
3675         if (!crtc->config.ips_enabled)
3676                 return;
3677
3678         /* We can only enable IPS after we enable a plane and wait for a vblank.
3679          * We guarantee that the plane is enabled by calling intel_enable_ips
3680          * only after intel_enable_plane. And intel_enable_plane already waits
3681          * for a vblank, so all we need to do here is to enable the IPS bit. */
3682         assert_plane_enabled(dev_priv, crtc->plane);
3683         if (IS_BROADWELL(crtc->base.dev)) {
3684                 mutex_lock(&dev_priv->rps.hw_lock);
3685                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3686                 mutex_unlock(&dev_priv->rps.hw_lock);
3687                 /* Quoting Art Runyan: "its not safe to expect any particular
3688                  * value in IPS_CTL bit 31 after enabling IPS through the
3689                  * mailbox." Moreover, the mailbox may return a bogus state,
3690                  * so we need to just enable it and continue on.
3691                  */
3692         } else {
3693                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3694                 /* The bit only becomes 1 in the next vblank, so this wait here
3695                  * is essentially intel_wait_for_vblank. If we don't have this
3696                  * and don't wait for vblanks until the end of crtc_enable, then
3697                  * the HW state readout code will complain that the expected
3698                  * IPS_CTL value is not the one we read. */
3699                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3700                         DRM_ERROR("Timed out waiting for IPS enable\n");
3701         }
3702 }
3703
3704 void hsw_disable_ips(struct intel_crtc *crtc)
3705 {
3706         struct drm_device *dev = crtc->base.dev;
3707         struct drm_i915_private *dev_priv = dev->dev_private;
3708
3709         if (!crtc->config.ips_enabled)
3710                 return;
3711
3712         assert_plane_enabled(dev_priv, crtc->plane);
3713         if (IS_BROADWELL(dev)) {
3714                 mutex_lock(&dev_priv->rps.hw_lock);
3715                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3716                 mutex_unlock(&dev_priv->rps.hw_lock);
3717                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3718                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3719                         DRM_ERROR("Timed out waiting for IPS disable\n");
3720         } else {
3721                 I915_WRITE(IPS_CTL, 0);
3722                 POSTING_READ(IPS_CTL);
3723         }
3724
3725         /* We need to wait for a vblank before we can disable the plane. */
3726         intel_wait_for_vblank(dev, crtc->pipe);
3727 }
3728
3729 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3730 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3731 {
3732         struct drm_device *dev = crtc->dev;
3733         struct drm_i915_private *dev_priv = dev->dev_private;
3734         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3735         enum pipe pipe = intel_crtc->pipe;
3736         int palreg = PALETTE(pipe);
3737         int i;
3738         bool reenable_ips = false;
3739
3740         /* The clocks have to be on to load the palette. */
3741         if (!crtc->enabled || !intel_crtc->active)
3742                 return;
3743
3744         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3745                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3746                         assert_dsi_pll_enabled(dev_priv);
3747                 else
3748                         assert_pll_enabled(dev_priv, pipe);
3749         }
3750
3751         /* use legacy palette for Ironlake */
3752         if (HAS_PCH_SPLIT(dev))
3753                 palreg = LGC_PALETTE(pipe);
3754
3755         /* Workaround : Do not read or write the pipe palette/gamma data while
3756          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3757          */
3758         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3759             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3760              GAMMA_MODE_MODE_SPLIT)) {
3761                 hsw_disable_ips(intel_crtc);
3762                 reenable_ips = true;
3763         }
3764
3765         for (i = 0; i < 256; i++) {
3766                 I915_WRITE(palreg + 4 * i,
3767                            (intel_crtc->lut_r[i] << 16) |
3768                            (intel_crtc->lut_g[i] << 8) |
3769                            intel_crtc->lut_b[i]);
3770         }
3771
3772         if (reenable_ips)
3773                 hsw_enable_ips(intel_crtc);
3774 }
3775
3776 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3777 {
3778         if (!enable && intel_crtc->overlay) {
3779                 struct drm_device *dev = intel_crtc->base.dev;
3780                 struct drm_i915_private *dev_priv = dev->dev_private;
3781
3782                 mutex_lock(&dev->struct_mutex);
3783                 dev_priv->mm.interruptible = false;
3784                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3785                 dev_priv->mm.interruptible = true;
3786                 mutex_unlock(&dev->struct_mutex);
3787         }
3788
3789         /* Let userspace switch the overlay on again. In most cases userspace
3790          * has to recompute where to put it anyway.
3791          */
3792 }
3793
3794 /**
3795  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3796  * cursor plane briefly if not already running after enabling the display
3797  * plane.
3798  * This workaround avoids occasional blank screens when self refresh is
3799  * enabled.
3800  */
3801 static void
3802 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3803 {
3804         u32 cntl = I915_READ(CURCNTR(pipe));
3805
3806         if ((cntl & CURSOR_MODE) == 0) {
3807                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3808
3809                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3810                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3811                 intel_wait_for_vblank(dev_priv->dev, pipe);
3812                 I915_WRITE(CURCNTR(pipe), cntl);
3813                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3814                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3815         }
3816 }
3817
3818 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3819 {
3820         struct drm_device *dev = crtc->dev;
3821         struct drm_i915_private *dev_priv = dev->dev_private;
3822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3823         int pipe = intel_crtc->pipe;
3824         int plane = intel_crtc->plane;
3825
3826         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3827         intel_enable_planes(crtc);
3828         /* The fixup needs to happen before cursor is enabled */
3829         if (IS_G4X(dev))
3830                 g4x_fixup_plane(dev_priv, pipe);
3831         intel_crtc_update_cursor(crtc, true);
3832         intel_crtc_dpms_overlay(intel_crtc, true);
3833
3834         hsw_enable_ips(intel_crtc);
3835
3836         mutex_lock(&dev->struct_mutex);
3837         intel_update_fbc(dev);
3838         mutex_unlock(&dev->struct_mutex);
3839 }
3840
3841 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3842 {
3843         struct drm_device *dev = crtc->dev;
3844         struct drm_i915_private *dev_priv = dev->dev_private;
3845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3846         int pipe = intel_crtc->pipe;
3847         int plane = intel_crtc->plane;
3848
3849         intel_crtc_wait_for_pending_flips(crtc);
3850         drm_vblank_off(dev, pipe);
3851
3852         if (dev_priv->fbc.plane == plane)
3853                 intel_disable_fbc(dev);
3854
3855         hsw_disable_ips(intel_crtc);
3856
3857         intel_crtc_dpms_overlay(intel_crtc, false);
3858         intel_crtc_update_cursor(crtc, false);
3859         intel_disable_planes(crtc);
3860         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3861 }
3862
3863 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3864 {
3865         struct drm_device *dev = crtc->dev;
3866         struct drm_i915_private *dev_priv = dev->dev_private;
3867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3868         struct intel_encoder *encoder;
3869         int pipe = intel_crtc->pipe;
3870
3871         WARN_ON(!crtc->enabled);
3872
3873         if (intel_crtc->active)
3874                 return;
3875
3876         intel_crtc->active = true;
3877
3878         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3879         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3880
3881         for_each_encoder_on_crtc(dev, crtc, encoder)
3882                 if (encoder->pre_enable)
3883                         encoder->pre_enable(encoder);
3884
3885         if (intel_crtc->config.has_pch_encoder) {
3886                 /* Note: FDI PLL enabling _must_ be done before we enable the
3887                  * cpu pipes, hence this is separate from all the other fdi/pch
3888                  * enabling. */
3889                 ironlake_fdi_pll_enable(intel_crtc);
3890         } else {
3891                 assert_fdi_tx_disabled(dev_priv, pipe);
3892                 assert_fdi_rx_disabled(dev_priv, pipe);
3893         }
3894
3895         ironlake_pfit_enable(intel_crtc);
3896
3897         /*
3898          * On ILK+ LUT must be loaded before the pipe is running but with
3899          * clocks enabled
3900          */
3901         intel_crtc_load_lut(crtc);
3902
3903         intel_update_watermarks(crtc);
3904         intel_enable_pipe(intel_crtc);
3905
3906         if (intel_crtc->config.has_pch_encoder)
3907                 ironlake_pch_enable(crtc);
3908
3909         for_each_encoder_on_crtc(dev, crtc, encoder)
3910                 encoder->enable(encoder);
3911
3912         if (HAS_PCH_CPT(dev))
3913                 cpt_verify_modeset(dev, intel_crtc->pipe);
3914
3915         intel_crtc_enable_planes(crtc);
3916
3917         /*
3918          * There seems to be a race in PCH platform hw (at least on some
3919          * outputs) where an enabled pipe still completes any pageflip right
3920          * away (as if the pipe is off) instead of waiting for vblank. As soon
3921          * as the first vblank happend, everything works as expected. Hence just
3922          * wait for one vblank before returning to avoid strange things
3923          * happening.
3924          */
3925         intel_wait_for_vblank(dev, intel_crtc->pipe);
3926 }
3927
3928 /* IPS only exists on ULT machines and is tied to pipe A. */
3929 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3930 {
3931         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3932 }
3933
3934 /*
3935  * This implements the workaround described in the "notes" section of the mode
3936  * set sequence documentation. When going from no pipes or single pipe to
3937  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3938  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3939  */
3940 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3941 {
3942         struct drm_device *dev = crtc->base.dev;
3943         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3944
3945         /* We want to get the other_active_crtc only if there's only 1 other
3946          * active crtc. */
3947         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3948                 if (!crtc_it->active || crtc_it == crtc)
3949                         continue;
3950
3951                 if (other_active_crtc)
3952                         return;
3953
3954                 other_active_crtc = crtc_it;
3955         }
3956         if (!other_active_crtc)
3957                 return;
3958
3959         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3960         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3961 }
3962
3963 static void haswell_crtc_enable(struct drm_crtc *crtc)
3964 {
3965         struct drm_device *dev = crtc->dev;
3966         struct drm_i915_private *dev_priv = dev->dev_private;
3967         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3968         struct intel_encoder *encoder;
3969         int pipe = intel_crtc->pipe;
3970
3971         WARN_ON(!crtc->enabled);
3972
3973         if (intel_crtc->active)
3974                 return;
3975
3976         intel_crtc->active = true;
3977
3978         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3979         if (intel_crtc->config.has_pch_encoder)
3980                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3981
3982         if (intel_crtc->config.has_pch_encoder)
3983                 dev_priv->display.fdi_link_train(crtc);
3984
3985         for_each_encoder_on_crtc(dev, crtc, encoder)
3986                 if (encoder->pre_enable)
3987                         encoder->pre_enable(encoder);
3988
3989         intel_ddi_enable_pipe_clock(intel_crtc);
3990
3991         ironlake_pfit_enable(intel_crtc);
3992
3993         /*
3994          * On ILK+ LUT must be loaded before the pipe is running but with
3995          * clocks enabled
3996          */
3997         intel_crtc_load_lut(crtc);
3998
3999         intel_ddi_set_pipe_settings(crtc);
4000         intel_ddi_enable_transcoder_func(crtc);
4001
4002         intel_update_watermarks(crtc);
4003         intel_enable_pipe(intel_crtc);
4004
4005         if (intel_crtc->config.has_pch_encoder)
4006                 lpt_pch_enable(crtc);
4007
4008         for_each_encoder_on_crtc(dev, crtc, encoder) {
4009                 encoder->enable(encoder);
4010                 intel_opregion_notify_encoder(encoder, true);
4011         }
4012
4013         /* If we change the relative order between pipe/planes enabling, we need
4014          * to change the workaround. */
4015         haswell_mode_set_planes_workaround(intel_crtc);
4016         intel_crtc_enable_planes(crtc);
4017 }
4018
4019 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4020 {
4021         struct drm_device *dev = crtc->base.dev;
4022         struct drm_i915_private *dev_priv = dev->dev_private;
4023         int pipe = crtc->pipe;
4024
4025         /* To avoid upsetting the power well on haswell only disable the pfit if
4026          * it's in use. The hw state code will make sure we get this right. */
4027         if (crtc->config.pch_pfit.enabled) {
4028                 I915_WRITE(PF_CTL(pipe), 0);
4029                 I915_WRITE(PF_WIN_POS(pipe), 0);
4030                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4031         }
4032 }
4033
4034 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4035 {
4036         struct drm_device *dev = crtc->dev;
4037         struct drm_i915_private *dev_priv = dev->dev_private;
4038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4039         struct intel_encoder *encoder;
4040         int pipe = intel_crtc->pipe;
4041         u32 reg, temp;
4042
4043         if (!intel_crtc->active)
4044                 return;
4045
4046         intel_crtc_disable_planes(crtc);
4047
4048         for_each_encoder_on_crtc(dev, crtc, encoder)
4049                 encoder->disable(encoder);
4050
4051         if (intel_crtc->config.has_pch_encoder)
4052                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4053
4054         intel_disable_pipe(dev_priv, pipe);
4055
4056         ironlake_pfit_disable(intel_crtc);
4057
4058         for_each_encoder_on_crtc(dev, crtc, encoder)
4059                 if (encoder->post_disable)
4060                         encoder->post_disable(encoder);
4061
4062         if (intel_crtc->config.has_pch_encoder) {
4063                 ironlake_fdi_disable(crtc);
4064
4065                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4066                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4067
4068                 if (HAS_PCH_CPT(dev)) {
4069                         /* disable TRANS_DP_CTL */
4070                         reg = TRANS_DP_CTL(pipe);
4071                         temp = I915_READ(reg);
4072                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4073                                   TRANS_DP_PORT_SEL_MASK);
4074                         temp |= TRANS_DP_PORT_SEL_NONE;
4075                         I915_WRITE(reg, temp);
4076
4077                         /* disable DPLL_SEL */
4078                         temp = I915_READ(PCH_DPLL_SEL);
4079                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4080                         I915_WRITE(PCH_DPLL_SEL, temp);
4081                 }
4082
4083                 /* disable PCH DPLL */
4084                 intel_disable_shared_dpll(intel_crtc);
4085
4086                 ironlake_fdi_pll_disable(intel_crtc);
4087         }
4088
4089         intel_crtc->active = false;
4090         intel_update_watermarks(crtc);
4091
4092         mutex_lock(&dev->struct_mutex);
4093         intel_update_fbc(dev);
4094         mutex_unlock(&dev->struct_mutex);
4095 }
4096
4097 static void haswell_crtc_disable(struct drm_crtc *crtc)
4098 {
4099         struct drm_device *dev = crtc->dev;
4100         struct drm_i915_private *dev_priv = dev->dev_private;
4101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4102         struct intel_encoder *encoder;
4103         int pipe = intel_crtc->pipe;
4104         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4105
4106         if (!intel_crtc->active)
4107                 return;
4108
4109         intel_crtc_disable_planes(crtc);
4110
4111         for_each_encoder_on_crtc(dev, crtc, encoder) {
4112                 intel_opregion_notify_encoder(encoder, false);
4113                 encoder->disable(encoder);
4114         }
4115
4116         if (intel_crtc->config.has_pch_encoder)
4117                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4118         intel_disable_pipe(dev_priv, pipe);
4119
4120         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4121
4122         ironlake_pfit_disable(intel_crtc);
4123
4124         intel_ddi_disable_pipe_clock(intel_crtc);
4125
4126         for_each_encoder_on_crtc(dev, crtc, encoder)
4127                 if (encoder->post_disable)
4128                         encoder->post_disable(encoder);
4129
4130         if (intel_crtc->config.has_pch_encoder) {
4131                 lpt_disable_pch_transcoder(dev_priv);
4132                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4133                 intel_ddi_fdi_disable(crtc);
4134         }
4135
4136         intel_crtc->active = false;
4137         intel_update_watermarks(crtc);
4138
4139         mutex_lock(&dev->struct_mutex);
4140         intel_update_fbc(dev);
4141         mutex_unlock(&dev->struct_mutex);
4142 }
4143
4144 static void ironlake_crtc_off(struct drm_crtc *crtc)
4145 {
4146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4147         intel_put_shared_dpll(intel_crtc);
4148 }
4149
4150 static void haswell_crtc_off(struct drm_crtc *crtc)
4151 {
4152         intel_ddi_put_crtc_pll(crtc);
4153 }
4154
4155 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4156 {
4157         struct drm_device *dev = crtc->base.dev;
4158         struct drm_i915_private *dev_priv = dev->dev_private;
4159         struct intel_crtc_config *pipe_config = &crtc->config;
4160
4161         if (!crtc->config.gmch_pfit.control)
4162                 return;
4163
4164         /*
4165          * The panel fitter should only be adjusted whilst the pipe is disabled,
4166          * according to register description and PRM.
4167          */
4168         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4169         assert_pipe_disabled(dev_priv, crtc->pipe);
4170
4171         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4172         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4173
4174         /* Border color in case we don't scale up to the full screen. Black by
4175          * default, change to something else for debugging. */
4176         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4177 }
4178
4179 #define for_each_power_domain(domain, mask)                             \
4180         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4181                 if ((1 << (domain)) & (mask))
4182
4183 enum intel_display_power_domain
4184 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4185 {
4186         struct drm_device *dev = intel_encoder->base.dev;
4187         struct intel_digital_port *intel_dig_port;
4188
4189         switch (intel_encoder->type) {
4190         case INTEL_OUTPUT_UNKNOWN:
4191                 /* Only DDI platforms should ever use this output type */
4192                 WARN_ON_ONCE(!HAS_DDI(dev));
4193         case INTEL_OUTPUT_DISPLAYPORT:
4194         case INTEL_OUTPUT_HDMI:
4195         case INTEL_OUTPUT_EDP:
4196                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4197                 switch (intel_dig_port->port) {
4198                 case PORT_A:
4199                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4200                 case PORT_B:
4201                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4202                 case PORT_C:
4203                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4204                 case PORT_D:
4205                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4206                 default:
4207                         WARN_ON_ONCE(1);
4208                         return POWER_DOMAIN_PORT_OTHER;
4209                 }
4210         case INTEL_OUTPUT_ANALOG:
4211                 return POWER_DOMAIN_PORT_CRT;
4212         case INTEL_OUTPUT_DSI:
4213                 return POWER_DOMAIN_PORT_DSI;
4214         default:
4215                 return POWER_DOMAIN_PORT_OTHER;
4216         }
4217 }
4218
4219 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4220 {
4221         struct drm_device *dev = crtc->dev;
4222         struct intel_encoder *intel_encoder;
4223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4224         enum pipe pipe = intel_crtc->pipe;
4225         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4226         unsigned long mask;
4227         enum transcoder transcoder;
4228
4229         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4230
4231         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4232         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4233         if (pfit_enabled)
4234                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4235
4236         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4237                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4238
4239         return mask;
4240 }
4241
4242 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4243                                   bool enable)
4244 {
4245         if (dev_priv->power_domains.init_power_on == enable)
4246                 return;
4247
4248         if (enable)
4249                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4250         else
4251                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4252
4253         dev_priv->power_domains.init_power_on = enable;
4254 }
4255
4256 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4257 {
4258         struct drm_i915_private *dev_priv = dev->dev_private;
4259         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4260         struct intel_crtc *crtc;
4261
4262         /*
4263          * First get all needed power domains, then put all unneeded, to avoid
4264          * any unnecessary toggling of the power wells.
4265          */
4266         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4267                 enum intel_display_power_domain domain;
4268
4269                 if (!crtc->base.enabled)
4270                         continue;
4271
4272                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4273
4274                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4275                         intel_display_power_get(dev_priv, domain);
4276         }
4277
4278         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4279                 enum intel_display_power_domain domain;
4280
4281                 for_each_power_domain(domain, crtc->enabled_power_domains)
4282                         intel_display_power_put(dev_priv, domain);
4283
4284                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4285         }
4286
4287         intel_display_set_init_power(dev_priv, false);
4288 }
4289
4290 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4291 {
4292         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4293
4294         /* Obtain SKU information */
4295         mutex_lock(&dev_priv->dpio_lock);
4296         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4297                 CCK_FUSE_HPLL_FREQ_MASK;
4298         mutex_unlock(&dev_priv->dpio_lock);
4299
4300         return vco_freq[hpll_freq];
4301 }
4302
4303 /* Adjust CDclk dividers to allow high res or save power if possible */
4304 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4305 {
4306         struct drm_i915_private *dev_priv = dev->dev_private;
4307         u32 val, cmd;
4308
4309         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4310         dev_priv->vlv_cdclk_freq = cdclk;
4311
4312         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4313                 cmd = 2;
4314         else if (cdclk == 266)
4315                 cmd = 1;
4316         else
4317                 cmd = 0;
4318
4319         mutex_lock(&dev_priv->rps.hw_lock);
4320         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4321         val &= ~DSPFREQGUAR_MASK;
4322         val |= (cmd << DSPFREQGUAR_SHIFT);
4323         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4324         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4325                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4326                      50)) {
4327                 DRM_ERROR("timed out waiting for CDclk change\n");
4328         }
4329         mutex_unlock(&dev_priv->rps.hw_lock);
4330
4331         if (cdclk == 400) {
4332                 u32 divider, vco;
4333
4334                 vco = valleyview_get_vco(dev_priv);
4335                 divider = ((vco << 1) / cdclk) - 1;
4336
4337                 mutex_lock(&dev_priv->dpio_lock);
4338                 /* adjust cdclk divider */
4339                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4340                 val &= ~0xf;
4341                 val |= divider;
4342                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4343                 mutex_unlock(&dev_priv->dpio_lock);
4344         }
4345
4346         mutex_lock(&dev_priv->dpio_lock);
4347         /* adjust self-refresh exit latency value */
4348         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4349         val &= ~0x7f;
4350
4351         /*
4352          * For high bandwidth configs, we set a higher latency in the bunit
4353          * so that the core display fetch happens in time to avoid underruns.
4354          */
4355         if (cdclk == 400)
4356                 val |= 4500 / 250; /* 4.5 usec */
4357         else
4358                 val |= 3000 / 250; /* 3.0 usec */
4359         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4360         mutex_unlock(&dev_priv->dpio_lock);
4361
4362         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4363         intel_i2c_reset(dev);
4364 }
4365
4366 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4367 {
4368         int cur_cdclk, vco;
4369         int divider;
4370
4371         vco = valleyview_get_vco(dev_priv);
4372
4373         mutex_lock(&dev_priv->dpio_lock);
4374         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4375         mutex_unlock(&dev_priv->dpio_lock);
4376
4377         divider &= 0xf;
4378
4379         cur_cdclk = (vco << 1) / (divider + 1);
4380
4381         return cur_cdclk;
4382 }
4383
4384 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4385                                  int max_pixclk)
4386 {
4387         /*
4388          * Really only a few cases to deal with, as only 4 CDclks are supported:
4389          *   200MHz
4390          *   267MHz
4391          *   320MHz
4392          *   400MHz
4393          * So we check to see whether we're above 90% of the lower bin and
4394          * adjust if needed.
4395          */
4396         if (max_pixclk > 288000) {
4397                 return 400;
4398         } else if (max_pixclk > 240000) {
4399                 return 320;
4400         } else
4401                 return 266;
4402         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4403 }
4404
4405 /* compute the max pixel clock for new configuration */
4406 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4407 {
4408         struct drm_device *dev = dev_priv->dev;
4409         struct intel_crtc *intel_crtc;
4410         int max_pixclk = 0;
4411
4412         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4413                             base.head) {
4414                 if (intel_crtc->new_enabled)
4415                         max_pixclk = max(max_pixclk,
4416                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4417         }
4418
4419         return max_pixclk;
4420 }
4421
4422 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4423                                             unsigned *prepare_pipes)
4424 {
4425         struct drm_i915_private *dev_priv = dev->dev_private;
4426         struct intel_crtc *intel_crtc;
4427         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4428
4429         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4430             dev_priv->vlv_cdclk_freq)
4431                 return;
4432
4433         /* disable/enable all currently active pipes while we change cdclk */
4434         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4435                             base.head)
4436                 if (intel_crtc->base.enabled)
4437                         *prepare_pipes |= (1 << intel_crtc->pipe);
4438 }
4439
4440 static void valleyview_modeset_global_resources(struct drm_device *dev)
4441 {
4442         struct drm_i915_private *dev_priv = dev->dev_private;
4443         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4444         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4445
4446         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4447                 valleyview_set_cdclk(dev, req_cdclk);
4448         modeset_update_crtc_power_domains(dev);
4449 }
4450
4451 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4452 {
4453         struct drm_device *dev = crtc->dev;
4454         struct drm_i915_private *dev_priv = dev->dev_private;
4455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4456         struct intel_encoder *encoder;
4457         int pipe = intel_crtc->pipe;
4458         bool is_dsi;
4459
4460         WARN_ON(!crtc->enabled);
4461
4462         if (intel_crtc->active)
4463                 return;
4464
4465         intel_crtc->active = true;
4466
4467         for_each_encoder_on_crtc(dev, crtc, encoder)
4468                 if (encoder->pre_pll_enable)
4469                         encoder->pre_pll_enable(encoder);
4470
4471         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4472
4473         if (!is_dsi)
4474                 vlv_enable_pll(intel_crtc);
4475
4476         for_each_encoder_on_crtc(dev, crtc, encoder)
4477                 if (encoder->pre_enable)
4478                         encoder->pre_enable(encoder);
4479
4480         i9xx_pfit_enable(intel_crtc);
4481
4482         intel_crtc_load_lut(crtc);
4483
4484         intel_update_watermarks(crtc);
4485         intel_enable_pipe(intel_crtc);
4486         intel_wait_for_vblank(dev_priv->dev, pipe);
4487         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4488
4489         intel_crtc_enable_planes(crtc);
4490
4491         for_each_encoder_on_crtc(dev, crtc, encoder)
4492                 encoder->enable(encoder);
4493 }
4494
4495 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4496 {
4497         struct drm_device *dev = crtc->dev;
4498         struct drm_i915_private *dev_priv = dev->dev_private;
4499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4500         struct intel_encoder *encoder;
4501         int pipe = intel_crtc->pipe;
4502
4503         WARN_ON(!crtc->enabled);
4504
4505         if (intel_crtc->active)
4506                 return;
4507
4508         intel_crtc->active = true;
4509
4510         for_each_encoder_on_crtc(dev, crtc, encoder)
4511                 if (encoder->pre_enable)
4512                         encoder->pre_enable(encoder);
4513
4514         i9xx_enable_pll(intel_crtc);
4515
4516         i9xx_pfit_enable(intel_crtc);
4517
4518         intel_crtc_load_lut(crtc);
4519
4520         intel_update_watermarks(crtc);
4521         intel_enable_pipe(intel_crtc);
4522         intel_wait_for_vblank(dev_priv->dev, pipe);
4523         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4524
4525         intel_crtc_enable_planes(crtc);
4526
4527         for_each_encoder_on_crtc(dev, crtc, encoder)
4528                 encoder->enable(encoder);
4529 }
4530
4531 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4532 {
4533         struct drm_device *dev = crtc->base.dev;
4534         struct drm_i915_private *dev_priv = dev->dev_private;
4535
4536         if (!crtc->config.gmch_pfit.control)
4537                 return;
4538
4539         assert_pipe_disabled(dev_priv, crtc->pipe);
4540
4541         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4542                          I915_READ(PFIT_CONTROL));
4543         I915_WRITE(PFIT_CONTROL, 0);
4544 }
4545
4546 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4547 {
4548         struct drm_device *dev = crtc->dev;
4549         struct drm_i915_private *dev_priv = dev->dev_private;
4550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4551         struct intel_encoder *encoder;
4552         int pipe = intel_crtc->pipe;
4553
4554         if (!intel_crtc->active)
4555                 return;
4556
4557         for_each_encoder_on_crtc(dev, crtc, encoder)
4558                 encoder->disable(encoder);
4559
4560         intel_crtc_disable_planes(crtc);
4561
4562         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4563         intel_disable_pipe(dev_priv, pipe);
4564
4565         i9xx_pfit_disable(intel_crtc);
4566
4567         for_each_encoder_on_crtc(dev, crtc, encoder)
4568                 if (encoder->post_disable)
4569                         encoder->post_disable(encoder);
4570
4571         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4572                 if (IS_CHERRYVIEW(dev))
4573                         chv_disable_pll(dev_priv, pipe);
4574                 else if (IS_VALLEYVIEW(dev))
4575                         vlv_disable_pll(dev_priv, pipe);
4576                 else
4577                         i9xx_disable_pll(dev_priv, pipe);
4578         }
4579
4580         intel_crtc->active = false;
4581         intel_update_watermarks(crtc);
4582
4583         intel_update_fbc(dev);
4584 }
4585
4586 static void i9xx_crtc_off(struct drm_crtc *crtc)
4587 {
4588 }
4589
4590 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4591                                     bool enabled)
4592 {
4593         struct drm_device *dev = crtc->dev;
4594         struct drm_i915_master_private *master_priv;
4595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4596         int pipe = intel_crtc->pipe;
4597
4598         if (!dev->primary->master)
4599                 return;
4600
4601         master_priv = dev->primary->master->driver_priv;
4602         if (!master_priv->sarea_priv)
4603                 return;
4604
4605         switch (pipe) {
4606         case 0:
4607                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4608                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4609                 break;
4610         case 1:
4611                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4612                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4613                 break;
4614         default:
4615                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4616                 break;
4617         }
4618 }
4619
4620 /**
4621  * Sets the power management mode of the pipe and plane.
4622  */
4623 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4624 {
4625         struct drm_device *dev = crtc->dev;
4626         struct drm_i915_private *dev_priv = dev->dev_private;
4627         struct intel_encoder *intel_encoder;
4628         bool enable = false;
4629
4630         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4631                 enable |= intel_encoder->connectors_active;
4632
4633         if (enable)
4634                 dev_priv->display.crtc_enable(crtc);
4635         else
4636                 dev_priv->display.crtc_disable(crtc);
4637
4638         intel_crtc_update_sarea(crtc, enable);
4639 }
4640
4641 static void intel_crtc_disable(struct drm_crtc *crtc)
4642 {
4643         struct drm_device *dev = crtc->dev;
4644         struct drm_connector *connector;
4645         struct drm_i915_private *dev_priv = dev->dev_private;
4646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4647
4648         /* crtc should still be enabled when we disable it. */
4649         WARN_ON(!crtc->enabled);
4650
4651         dev_priv->display.crtc_disable(crtc);
4652         intel_crtc->eld_vld = false;
4653         intel_crtc_update_sarea(crtc, false);
4654         dev_priv->display.off(crtc);
4655
4656         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4657         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4658         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4659
4660         if (crtc->primary->fb) {
4661                 mutex_lock(&dev->struct_mutex);
4662                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4663                 mutex_unlock(&dev->struct_mutex);
4664                 crtc->primary->fb = NULL;
4665         }
4666
4667         /* Update computed state. */
4668         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4669                 if (!connector->encoder || !connector->encoder->crtc)
4670                         continue;
4671
4672                 if (connector->encoder->crtc != crtc)
4673                         continue;
4674
4675                 connector->dpms = DRM_MODE_DPMS_OFF;
4676                 to_intel_encoder(connector->encoder)->connectors_active = false;
4677         }
4678 }
4679
4680 void intel_encoder_destroy(struct drm_encoder *encoder)
4681 {
4682         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4683
4684         drm_encoder_cleanup(encoder);
4685         kfree(intel_encoder);
4686 }
4687
4688 /* Simple dpms helper for encoders with just one connector, no cloning and only
4689  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4690  * state of the entire output pipe. */
4691 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4692 {
4693         if (mode == DRM_MODE_DPMS_ON) {
4694                 encoder->connectors_active = true;
4695
4696                 intel_crtc_update_dpms(encoder->base.crtc);
4697         } else {
4698                 encoder->connectors_active = false;
4699
4700                 intel_crtc_update_dpms(encoder->base.crtc);
4701         }
4702 }
4703
4704 /* Cross check the actual hw state with our own modeset state tracking (and it's
4705  * internal consistency). */
4706 static void intel_connector_check_state(struct intel_connector *connector)
4707 {
4708         if (connector->get_hw_state(connector)) {
4709                 struct intel_encoder *encoder = connector->encoder;
4710                 struct drm_crtc *crtc;
4711                 bool encoder_enabled;
4712                 enum pipe pipe;
4713
4714                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4715                               connector->base.base.id,
4716                               drm_get_connector_name(&connector->base));
4717
4718                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4719                      "wrong connector dpms state\n");
4720                 WARN(connector->base.encoder != &encoder->base,
4721                      "active connector not linked to encoder\n");
4722                 WARN(!encoder->connectors_active,
4723                      "encoder->connectors_active not set\n");
4724
4725                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4726                 WARN(!encoder_enabled, "encoder not enabled\n");
4727                 if (WARN_ON(!encoder->base.crtc))
4728                         return;
4729
4730                 crtc = encoder->base.crtc;
4731
4732                 WARN(!crtc->enabled, "crtc not enabled\n");
4733                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4734                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4735                      "encoder active on the wrong pipe\n");
4736         }
4737 }
4738
4739 /* Even simpler default implementation, if there's really no special case to
4740  * consider. */
4741 void intel_connector_dpms(struct drm_connector *connector, int mode)
4742 {
4743         /* All the simple cases only support two dpms states. */
4744         if (mode != DRM_MODE_DPMS_ON)
4745                 mode = DRM_MODE_DPMS_OFF;
4746
4747         if (mode == connector->dpms)
4748                 return;
4749
4750         connector->dpms = mode;
4751
4752         /* Only need to change hw state when actually enabled */
4753         if (connector->encoder)
4754                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4755
4756         intel_modeset_check_state(connector->dev);
4757 }
4758
4759 /* Simple connector->get_hw_state implementation for encoders that support only
4760  * one connector and no cloning and hence the encoder state determines the state
4761  * of the connector. */
4762 bool intel_connector_get_hw_state(struct intel_connector *connector)
4763 {
4764         enum pipe pipe = 0;
4765         struct intel_encoder *encoder = connector->encoder;
4766
4767         return encoder->get_hw_state(encoder, &pipe);
4768 }
4769
4770 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4771                                      struct intel_crtc_config *pipe_config)
4772 {
4773         struct drm_i915_private *dev_priv = dev->dev_private;
4774         struct intel_crtc *pipe_B_crtc =
4775                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4776
4777         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4778                       pipe_name(pipe), pipe_config->fdi_lanes);
4779         if (pipe_config->fdi_lanes > 4) {
4780                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4781                               pipe_name(pipe), pipe_config->fdi_lanes);
4782                 return false;
4783         }
4784
4785         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4786                 if (pipe_config->fdi_lanes > 2) {
4787                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4788                                       pipe_config->fdi_lanes);
4789                         return false;
4790                 } else {
4791                         return true;
4792                 }
4793         }
4794
4795         if (INTEL_INFO(dev)->num_pipes == 2)
4796                 return true;
4797
4798         /* Ivybridge 3 pipe is really complicated */
4799         switch (pipe) {
4800         case PIPE_A:
4801                 return true;
4802         case PIPE_B:
4803                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4804                     pipe_config->fdi_lanes > 2) {
4805                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4806                                       pipe_name(pipe), pipe_config->fdi_lanes);
4807                         return false;
4808                 }
4809                 return true;
4810         case PIPE_C:
4811                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4812                     pipe_B_crtc->config.fdi_lanes <= 2) {
4813                         if (pipe_config->fdi_lanes > 2) {
4814                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4815                                               pipe_name(pipe), pipe_config->fdi_lanes);
4816                                 return false;
4817                         }
4818                 } else {
4819                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4820                         return false;
4821                 }
4822                 return true;
4823         default:
4824                 BUG();
4825         }
4826 }
4827
4828 #define RETRY 1
4829 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4830                                        struct intel_crtc_config *pipe_config)
4831 {
4832         struct drm_device *dev = intel_crtc->base.dev;
4833         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4834         int lane, link_bw, fdi_dotclock;
4835         bool setup_ok, needs_recompute = false;
4836
4837 retry:
4838         /* FDI is a binary signal running at ~2.7GHz, encoding
4839          * each output octet as 10 bits. The actual frequency
4840          * is stored as a divider into a 100MHz clock, and the
4841          * mode pixel clock is stored in units of 1KHz.
4842          * Hence the bw of each lane in terms of the mode signal
4843          * is:
4844          */
4845         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4846
4847         fdi_dotclock = adjusted_mode->crtc_clock;
4848
4849         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4850                                            pipe_config->pipe_bpp);
4851
4852         pipe_config->fdi_lanes = lane;
4853
4854         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4855                                link_bw, &pipe_config->fdi_m_n);
4856
4857         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4858                                             intel_crtc->pipe, pipe_config);
4859         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4860                 pipe_config->pipe_bpp -= 2*3;
4861                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4862                               pipe_config->pipe_bpp);
4863                 needs_recompute = true;
4864                 pipe_config->bw_constrained = true;
4865
4866                 goto retry;
4867         }
4868
4869         if (needs_recompute)
4870                 return RETRY;
4871
4872         return setup_ok ? 0 : -EINVAL;
4873 }
4874
4875 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4876                                    struct intel_crtc_config *pipe_config)
4877 {
4878         pipe_config->ips_enabled = i915.enable_ips &&
4879                                    hsw_crtc_supports_ips(crtc) &&
4880                                    pipe_config->pipe_bpp <= 24;
4881 }
4882
4883 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4884                                      struct intel_crtc_config *pipe_config)
4885 {
4886         struct drm_device *dev = crtc->base.dev;
4887         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4888
4889         /* FIXME should check pixel clock limits on all platforms */
4890         if (INTEL_INFO(dev)->gen < 4) {
4891                 struct drm_i915_private *dev_priv = dev->dev_private;
4892                 int clock_limit =
4893                         dev_priv->display.get_display_clock_speed(dev);
4894
4895                 /*
4896                  * Enable pixel doubling when the dot clock
4897                  * is > 90% of the (display) core speed.
4898                  *
4899                  * GDG double wide on either pipe,
4900                  * otherwise pipe A only.
4901                  */
4902                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4903                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4904                         clock_limit *= 2;
4905                         pipe_config->double_wide = true;
4906                 }
4907
4908                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4909                         return -EINVAL;
4910         }
4911
4912         /*
4913          * Pipe horizontal size must be even in:
4914          * - DVO ganged mode
4915          * - LVDS dual channel mode
4916          * - Double wide pipe
4917          */
4918         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4919              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4920                 pipe_config->pipe_src_w &= ~1;
4921
4922         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4923          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4924          */
4925         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4926                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4927                 return -EINVAL;
4928
4929         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4930                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4931         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4932                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4933                  * for lvds. */
4934                 pipe_config->pipe_bpp = 8*3;
4935         }
4936
4937         if (HAS_IPS(dev))
4938                 hsw_compute_ips_config(crtc, pipe_config);
4939
4940         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4941          * clock survives for now. */
4942         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4943                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4944
4945         if (pipe_config->has_pch_encoder)
4946                 return ironlake_fdi_compute_config(crtc, pipe_config);
4947
4948         return 0;
4949 }
4950
4951 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4952 {
4953         return 400000; /* FIXME */
4954 }
4955
4956 static int i945_get_display_clock_speed(struct drm_device *dev)
4957 {
4958         return 400000;
4959 }
4960
4961 static int i915_get_display_clock_speed(struct drm_device *dev)
4962 {
4963         return 333000;
4964 }
4965
4966 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4967 {
4968         return 200000;
4969 }
4970
4971 static int pnv_get_display_clock_speed(struct drm_device *dev)
4972 {
4973         u16 gcfgc = 0;
4974
4975         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4976
4977         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4978         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4979                 return 267000;
4980         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4981                 return 333000;
4982         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4983                 return 444000;
4984         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4985                 return 200000;
4986         default:
4987                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4988         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4989                 return 133000;
4990         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4991                 return 167000;
4992         }
4993 }
4994
4995 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4996 {
4997         u16 gcfgc = 0;
4998
4999         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5000
5001         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5002                 return 133000;
5003         else {
5004                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5005                 case GC_DISPLAY_CLOCK_333_MHZ:
5006                         return 333000;
5007                 default:
5008                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5009                         return 190000;
5010                 }
5011         }
5012 }
5013
5014 static int i865_get_display_clock_speed(struct drm_device *dev)
5015 {
5016         return 266000;
5017 }
5018
5019 static int i855_get_display_clock_speed(struct drm_device *dev)
5020 {
5021         u16 hpllcc = 0;
5022         /* Assume that the hardware is in the high speed state.  This
5023          * should be the default.
5024          */
5025         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5026         case GC_CLOCK_133_200:
5027         case GC_CLOCK_100_200:
5028                 return 200000;
5029         case GC_CLOCK_166_250:
5030                 return 250000;
5031         case GC_CLOCK_100_133:
5032                 return 133000;
5033         }
5034
5035         /* Shouldn't happen */
5036         return 0;
5037 }
5038
5039 static int i830_get_display_clock_speed(struct drm_device *dev)
5040 {
5041         return 133000;
5042 }
5043
5044 static void
5045 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5046 {
5047         while (*num > DATA_LINK_M_N_MASK ||
5048                *den > DATA_LINK_M_N_MASK) {
5049                 *num >>= 1;
5050                 *den >>= 1;
5051         }
5052 }
5053
5054 static void compute_m_n(unsigned int m, unsigned int n,
5055                         uint32_t *ret_m, uint32_t *ret_n)
5056 {
5057         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5058         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5059         intel_reduce_m_n_ratio(ret_m, ret_n);
5060 }
5061
5062 void
5063 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5064                        int pixel_clock, int link_clock,
5065                        struct intel_link_m_n *m_n)
5066 {
5067         m_n->tu = 64;
5068
5069         compute_m_n(bits_per_pixel * pixel_clock,
5070                     link_clock * nlanes * 8,
5071                     &m_n->gmch_m, &m_n->gmch_n);
5072
5073         compute_m_n(pixel_clock, link_clock,
5074                     &m_n->link_m, &m_n->link_n);
5075 }
5076
5077 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5078 {
5079         if (i915.panel_use_ssc >= 0)
5080                 return i915.panel_use_ssc != 0;
5081         return dev_priv->vbt.lvds_use_ssc
5082                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5083 }
5084
5085 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5086 {
5087         struct drm_device *dev = crtc->dev;
5088         struct drm_i915_private *dev_priv = dev->dev_private;
5089         int refclk;
5090
5091         if (IS_VALLEYVIEW(dev)) {
5092                 refclk = 100000;
5093         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5094             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5095                 refclk = dev_priv->vbt.lvds_ssc_freq;
5096                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5097         } else if (!IS_GEN2(dev)) {
5098                 refclk = 96000;
5099         } else {
5100                 refclk = 48000;
5101         }
5102
5103         return refclk;
5104 }
5105
5106 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5107 {
5108         return (1 << dpll->n) << 16 | dpll->m2;
5109 }
5110
5111 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5112 {
5113         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5114 }
5115
5116 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5117                                      intel_clock_t *reduced_clock)
5118 {
5119         struct drm_device *dev = crtc->base.dev;
5120         struct drm_i915_private *dev_priv = dev->dev_private;
5121         int pipe = crtc->pipe;
5122         u32 fp, fp2 = 0;
5123
5124         if (IS_PINEVIEW(dev)) {
5125                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5126                 if (reduced_clock)
5127                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5128         } else {
5129                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5130                 if (reduced_clock)
5131                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5132         }
5133
5134         I915_WRITE(FP0(pipe), fp);
5135         crtc->config.dpll_hw_state.fp0 = fp;
5136
5137         crtc->lowfreq_avail = false;
5138         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5139             reduced_clock && i915.powersave) {
5140                 I915_WRITE(FP1(pipe), fp2);
5141                 crtc->config.dpll_hw_state.fp1 = fp2;
5142                 crtc->lowfreq_avail = true;
5143         } else {
5144                 I915_WRITE(FP1(pipe), fp);
5145                 crtc->config.dpll_hw_state.fp1 = fp;
5146         }
5147 }
5148
5149 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5150                 pipe)
5151 {
5152         u32 reg_val;
5153
5154         /*
5155          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5156          * and set it to a reasonable value instead.
5157          */
5158         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5159         reg_val &= 0xffffff00;
5160         reg_val |= 0x00000030;
5161         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5162
5163         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5164         reg_val &= 0x8cffffff;
5165         reg_val = 0x8c000000;
5166         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5167
5168         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5169         reg_val &= 0xffffff00;
5170         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5171
5172         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5173         reg_val &= 0x00ffffff;
5174         reg_val |= 0xb0000000;
5175         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5176 }
5177
5178 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5179                                          struct intel_link_m_n *m_n)
5180 {
5181         struct drm_device *dev = crtc->base.dev;
5182         struct drm_i915_private *dev_priv = dev->dev_private;
5183         int pipe = crtc->pipe;
5184
5185         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5186         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5187         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5188         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5189 }
5190
5191 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5192                                          struct intel_link_m_n *m_n)
5193 {
5194         struct drm_device *dev = crtc->base.dev;
5195         struct drm_i915_private *dev_priv = dev->dev_private;
5196         int pipe = crtc->pipe;
5197         enum transcoder transcoder = crtc->config.cpu_transcoder;
5198
5199         if (INTEL_INFO(dev)->gen >= 5) {
5200                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5201                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5202                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5203                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5204         } else {
5205                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5206                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5207                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5208                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5209         }
5210 }
5211
5212 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5213 {
5214         if (crtc->config.has_pch_encoder)
5215                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5216         else
5217                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5218 }
5219
5220 static void vlv_update_pll(struct intel_crtc *crtc)
5221 {
5222         struct drm_device *dev = crtc->base.dev;
5223         struct drm_i915_private *dev_priv = dev->dev_private;
5224         int pipe = crtc->pipe;
5225         u32 dpll, mdiv;
5226         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5227         u32 coreclk, reg_val, dpll_md;
5228
5229         mutex_lock(&dev_priv->dpio_lock);
5230
5231         bestn = crtc->config.dpll.n;
5232         bestm1 = crtc->config.dpll.m1;
5233         bestm2 = crtc->config.dpll.m2;
5234         bestp1 = crtc->config.dpll.p1;
5235         bestp2 = crtc->config.dpll.p2;
5236
5237         /* See eDP HDMI DPIO driver vbios notes doc */
5238
5239         /* PLL B needs special handling */
5240         if (pipe)
5241                 vlv_pllb_recal_opamp(dev_priv, pipe);
5242
5243         /* Set up Tx target for periodic Rcomp update */
5244         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5245
5246         /* Disable target IRef on PLL */
5247         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5248         reg_val &= 0x00ffffff;
5249         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5250
5251         /* Disable fast lock */
5252         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5253
5254         /* Set idtafcrecal before PLL is enabled */
5255         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5256         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5257         mdiv |= ((bestn << DPIO_N_SHIFT));
5258         mdiv |= (1 << DPIO_K_SHIFT);
5259
5260         /*
5261          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5262          * but we don't support that).
5263          * Note: don't use the DAC post divider as it seems unstable.
5264          */
5265         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5266         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5267
5268         mdiv |= DPIO_ENABLE_CALIBRATION;
5269         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5270
5271         /* Set HBR and RBR LPF coefficients */
5272         if (crtc->config.port_clock == 162000 ||
5273             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5274             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5275                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5276                                  0x009f0003);
5277         else
5278                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5279                                  0x00d0000f);
5280
5281         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5282             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5283                 /* Use SSC source */
5284                 if (!pipe)
5285                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5286                                          0x0df40000);
5287                 else
5288                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5289                                          0x0df70000);
5290         } else { /* HDMI or VGA */
5291                 /* Use bend source */
5292                 if (!pipe)
5293                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5294                                          0x0df70000);
5295                 else
5296                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5297                                          0x0df40000);
5298         }
5299
5300         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5301         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5302         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5303             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5304                 coreclk |= 0x01000000;
5305         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5306
5307         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5308
5309         /*
5310          * Enable DPIO clock input. We should never disable the reference
5311          * clock for pipe B, since VGA hotplug / manual detection depends
5312          * on it.
5313          */
5314         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5315                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5316         /* We should never disable this, set it here for state tracking */
5317         if (pipe == PIPE_B)
5318                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5319         dpll |= DPLL_VCO_ENABLE;
5320         crtc->config.dpll_hw_state.dpll = dpll;
5321
5322         dpll_md = (crtc->config.pixel_multiplier - 1)
5323                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5324         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5325
5326         mutex_unlock(&dev_priv->dpio_lock);
5327 }
5328
5329 static void i9xx_update_pll(struct intel_crtc *crtc,
5330                             intel_clock_t *reduced_clock,
5331                             int num_connectors)
5332 {
5333         struct drm_device *dev = crtc->base.dev;
5334         struct drm_i915_private *dev_priv = dev->dev_private;
5335         u32 dpll;
5336         bool is_sdvo;
5337         struct dpll *clock = &crtc->config.dpll;
5338
5339         i9xx_update_pll_dividers(crtc, reduced_clock);
5340
5341         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5342                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5343
5344         dpll = DPLL_VGA_MODE_DIS;
5345
5346         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5347                 dpll |= DPLLB_MODE_LVDS;
5348         else
5349                 dpll |= DPLLB_MODE_DAC_SERIAL;
5350
5351         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5352                 dpll |= (crtc->config.pixel_multiplier - 1)
5353                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5354         }
5355
5356         if (is_sdvo)
5357                 dpll |= DPLL_SDVO_HIGH_SPEED;
5358
5359         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5360                 dpll |= DPLL_SDVO_HIGH_SPEED;
5361
5362         /* compute bitmask from p1 value */
5363         if (IS_PINEVIEW(dev))
5364                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5365         else {
5366                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5367                 if (IS_G4X(dev) && reduced_clock)
5368                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5369         }
5370         switch (clock->p2) {
5371         case 5:
5372                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5373                 break;
5374         case 7:
5375                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5376                 break;
5377         case 10:
5378                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5379                 break;
5380         case 14:
5381                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5382                 break;
5383         }
5384         if (INTEL_INFO(dev)->gen >= 4)
5385                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5386
5387         if (crtc->config.sdvo_tv_clock)
5388                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5389         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5390                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5391                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5392         else
5393                 dpll |= PLL_REF_INPUT_DREFCLK;
5394
5395         dpll |= DPLL_VCO_ENABLE;
5396         crtc->config.dpll_hw_state.dpll = dpll;
5397
5398         if (INTEL_INFO(dev)->gen >= 4) {
5399                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5400                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5401                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5402         }
5403 }
5404
5405 static void i8xx_update_pll(struct intel_crtc *crtc,
5406                             intel_clock_t *reduced_clock,
5407                             int num_connectors)
5408 {
5409         struct drm_device *dev = crtc->base.dev;
5410         struct drm_i915_private *dev_priv = dev->dev_private;
5411         u32 dpll;
5412         struct dpll *clock = &crtc->config.dpll;
5413
5414         i9xx_update_pll_dividers(crtc, reduced_clock);
5415
5416         dpll = DPLL_VGA_MODE_DIS;
5417
5418         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5419                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5420         } else {
5421                 if (clock->p1 == 2)
5422                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5423                 else
5424                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5425                 if (clock->p2 == 4)
5426                         dpll |= PLL_P2_DIVIDE_BY_4;
5427         }
5428
5429         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5430                 dpll |= DPLL_DVO_2X_MODE;
5431
5432         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5433                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5434                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5435         else
5436                 dpll |= PLL_REF_INPUT_DREFCLK;
5437
5438         dpll |= DPLL_VCO_ENABLE;
5439         crtc->config.dpll_hw_state.dpll = dpll;
5440 }
5441
5442 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5443 {
5444         struct drm_device *dev = intel_crtc->base.dev;
5445         struct drm_i915_private *dev_priv = dev->dev_private;
5446         enum pipe pipe = intel_crtc->pipe;
5447         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5448         struct drm_display_mode *adjusted_mode =
5449                 &intel_crtc->config.adjusted_mode;
5450         uint32_t crtc_vtotal, crtc_vblank_end;
5451         int vsyncshift = 0;
5452
5453         /* We need to be careful not to changed the adjusted mode, for otherwise
5454          * the hw state checker will get angry at the mismatch. */
5455         crtc_vtotal = adjusted_mode->crtc_vtotal;
5456         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5457
5458         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5459                 /* the chip adds 2 halflines automatically */
5460                 crtc_vtotal -= 1;
5461                 crtc_vblank_end -= 1;
5462
5463                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5464                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5465                 else
5466                         vsyncshift = adjusted_mode->crtc_hsync_start -
5467                                 adjusted_mode->crtc_htotal / 2;
5468                 if (vsyncshift < 0)
5469                         vsyncshift += adjusted_mode->crtc_htotal;
5470         }
5471
5472         if (INTEL_INFO(dev)->gen > 3)
5473                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5474
5475         I915_WRITE(HTOTAL(cpu_transcoder),
5476                    (adjusted_mode->crtc_hdisplay - 1) |
5477                    ((adjusted_mode->crtc_htotal - 1) << 16));
5478         I915_WRITE(HBLANK(cpu_transcoder),
5479                    (adjusted_mode->crtc_hblank_start - 1) |
5480                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5481         I915_WRITE(HSYNC(cpu_transcoder),
5482                    (adjusted_mode->crtc_hsync_start - 1) |
5483                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5484
5485         I915_WRITE(VTOTAL(cpu_transcoder),
5486                    (adjusted_mode->crtc_vdisplay - 1) |
5487                    ((crtc_vtotal - 1) << 16));
5488         I915_WRITE(VBLANK(cpu_transcoder),
5489                    (adjusted_mode->crtc_vblank_start - 1) |
5490                    ((crtc_vblank_end - 1) << 16));
5491         I915_WRITE(VSYNC(cpu_transcoder),
5492                    (adjusted_mode->crtc_vsync_start - 1) |
5493                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5494
5495         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5496          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5497          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5498          * bits. */
5499         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5500             (pipe == PIPE_B || pipe == PIPE_C))
5501                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5502
5503         /* pipesrc controls the size that is scaled from, which should
5504          * always be the user's requested size.
5505          */
5506         I915_WRITE(PIPESRC(pipe),
5507                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5508                    (intel_crtc->config.pipe_src_h - 1));
5509 }
5510
5511 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5512                                    struct intel_crtc_config *pipe_config)
5513 {
5514         struct drm_device *dev = crtc->base.dev;
5515         struct drm_i915_private *dev_priv = dev->dev_private;
5516         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5517         uint32_t tmp;
5518
5519         tmp = I915_READ(HTOTAL(cpu_transcoder));
5520         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5521         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5522         tmp = I915_READ(HBLANK(cpu_transcoder));
5523         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5524         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5525         tmp = I915_READ(HSYNC(cpu_transcoder));
5526         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5527         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5528
5529         tmp = I915_READ(VTOTAL(cpu_transcoder));
5530         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5531         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5532         tmp = I915_READ(VBLANK(cpu_transcoder));
5533         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5534         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5535         tmp = I915_READ(VSYNC(cpu_transcoder));
5536         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5537         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5538
5539         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5540                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5541                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5542                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5543         }
5544
5545         tmp = I915_READ(PIPESRC(crtc->pipe));
5546         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5547         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5548
5549         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5550         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5551 }
5552
5553 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5554                                  struct intel_crtc_config *pipe_config)
5555 {
5556         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5557         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5558         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5559         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5560
5561         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5562         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5563         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5564         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5565
5566         mode->flags = pipe_config->adjusted_mode.flags;
5567
5568         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5569         mode->flags |= pipe_config->adjusted_mode.flags;
5570 }
5571
5572 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5573 {
5574         struct drm_device *dev = intel_crtc->base.dev;
5575         struct drm_i915_private *dev_priv = dev->dev_private;
5576         uint32_t pipeconf;
5577
5578         pipeconf = 0;
5579
5580         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5581             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5582                 pipeconf |= PIPECONF_ENABLE;
5583
5584         if (intel_crtc->config.double_wide)
5585                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5586
5587         /* only g4x and later have fancy bpc/dither controls */
5588         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5589                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5590                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5591                         pipeconf |= PIPECONF_DITHER_EN |
5592                                     PIPECONF_DITHER_TYPE_SP;
5593
5594                 switch (intel_crtc->config.pipe_bpp) {
5595                 case 18:
5596                         pipeconf |= PIPECONF_6BPC;
5597                         break;
5598                 case 24:
5599                         pipeconf |= PIPECONF_8BPC;
5600                         break;
5601                 case 30:
5602                         pipeconf |= PIPECONF_10BPC;
5603                         break;
5604                 default:
5605                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5606                         BUG();
5607                 }
5608         }
5609
5610         if (HAS_PIPE_CXSR(dev)) {
5611                 if (intel_crtc->lowfreq_avail) {
5612                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5613                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5614                 } else {
5615                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5616                 }
5617         }
5618
5619         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5620                 if (INTEL_INFO(dev)->gen < 4 ||
5621                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5622                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5623                 else
5624                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5625         } else
5626                 pipeconf |= PIPECONF_PROGRESSIVE;
5627
5628         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5629                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5630
5631         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5632         POSTING_READ(PIPECONF(intel_crtc->pipe));
5633 }
5634
5635 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5636                               int x, int y,
5637                               struct drm_framebuffer *fb)
5638 {
5639         struct drm_device *dev = crtc->dev;
5640         struct drm_i915_private *dev_priv = dev->dev_private;
5641         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5642         int pipe = intel_crtc->pipe;
5643         int plane = intel_crtc->plane;
5644         int refclk, num_connectors = 0;
5645         intel_clock_t clock, reduced_clock;
5646         u32 dspcntr;
5647         bool ok, has_reduced_clock = false;
5648         bool is_lvds = false, is_dsi = false;
5649         struct intel_encoder *encoder;
5650         const intel_limit_t *limit;
5651         int ret;
5652
5653         for_each_encoder_on_crtc(dev, crtc, encoder) {
5654                 switch (encoder->type) {
5655                 case INTEL_OUTPUT_LVDS:
5656                         is_lvds = true;
5657                         break;
5658                 case INTEL_OUTPUT_DSI:
5659                         is_dsi = true;
5660                         break;
5661                 }
5662
5663                 num_connectors++;
5664         }
5665
5666         if (is_dsi)
5667                 goto skip_dpll;
5668
5669         if (!intel_crtc->config.clock_set) {
5670                 refclk = i9xx_get_refclk(crtc, num_connectors);
5671
5672                 /*
5673                  * Returns a set of divisors for the desired target clock with
5674                  * the given refclk, or FALSE.  The returned values represent
5675                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5676                  * 2) / p1 / p2.
5677                  */
5678                 limit = intel_limit(crtc, refclk);
5679                 ok = dev_priv->display.find_dpll(limit, crtc,
5680                                                  intel_crtc->config.port_clock,
5681                                                  refclk, NULL, &clock);
5682                 if (!ok) {
5683                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5684                         return -EINVAL;
5685                 }
5686
5687                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5688                         /*
5689                          * Ensure we match the reduced clock's P to the target
5690                          * clock.  If the clocks don't match, we can't switch
5691                          * the display clock by using the FP0/FP1. In such case
5692                          * we will disable the LVDS downclock feature.
5693                          */
5694                         has_reduced_clock =
5695                                 dev_priv->display.find_dpll(limit, crtc,
5696                                                             dev_priv->lvds_downclock,
5697                                                             refclk, &clock,
5698                                                             &reduced_clock);
5699                 }
5700                 /* Compat-code for transition, will disappear. */
5701                 intel_crtc->config.dpll.n = clock.n;
5702                 intel_crtc->config.dpll.m1 = clock.m1;
5703                 intel_crtc->config.dpll.m2 = clock.m2;
5704                 intel_crtc->config.dpll.p1 = clock.p1;
5705                 intel_crtc->config.dpll.p2 = clock.p2;
5706         }
5707
5708         if (IS_GEN2(dev)) {
5709                 i8xx_update_pll(intel_crtc,
5710                                 has_reduced_clock ? &reduced_clock : NULL,
5711                                 num_connectors);
5712         } else if (IS_VALLEYVIEW(dev)) {
5713                 vlv_update_pll(intel_crtc);
5714         } else {
5715                 i9xx_update_pll(intel_crtc,
5716                                 has_reduced_clock ? &reduced_clock : NULL,
5717                                 num_connectors);
5718         }
5719
5720 skip_dpll:
5721         /* Set up the display plane register */
5722         dspcntr = DISPPLANE_GAMMA_ENABLE;
5723
5724         if (!IS_VALLEYVIEW(dev)) {
5725                 if (pipe == 0)
5726                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5727                 else
5728                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5729         }
5730
5731         if (intel_crtc->config.has_dp_encoder)
5732                 intel_dp_set_m_n(intel_crtc);
5733
5734         intel_set_pipe_timings(intel_crtc);
5735
5736         /* pipesrc and dspsize control the size that is scaled from,
5737          * which should always be the user's requested size.
5738          */
5739         I915_WRITE(DSPSIZE(plane),
5740                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5741                    (intel_crtc->config.pipe_src_w - 1));
5742         I915_WRITE(DSPPOS(plane), 0);
5743
5744         i9xx_set_pipeconf(intel_crtc);
5745
5746         I915_WRITE(DSPCNTR(plane), dspcntr);
5747         POSTING_READ(DSPCNTR(plane));
5748
5749         ret = intel_pipe_set_base(crtc, x, y, fb);
5750
5751         return ret;
5752 }
5753
5754 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5755                                  struct intel_crtc_config *pipe_config)
5756 {
5757         struct drm_device *dev = crtc->base.dev;
5758         struct drm_i915_private *dev_priv = dev->dev_private;
5759         uint32_t tmp;
5760
5761         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5762                 return;
5763
5764         tmp = I915_READ(PFIT_CONTROL);
5765         if (!(tmp & PFIT_ENABLE))
5766                 return;
5767
5768         /* Check whether the pfit is attached to our pipe. */
5769         if (INTEL_INFO(dev)->gen < 4) {
5770                 if (crtc->pipe != PIPE_B)
5771                         return;
5772         } else {
5773                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5774                         return;
5775         }
5776
5777         pipe_config->gmch_pfit.control = tmp;
5778         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5779         if (INTEL_INFO(dev)->gen < 5)
5780                 pipe_config->gmch_pfit.lvds_border_bits =
5781                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5782 }
5783
5784 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5785                                struct intel_crtc_config *pipe_config)
5786 {
5787         struct drm_device *dev = crtc->base.dev;
5788         struct drm_i915_private *dev_priv = dev->dev_private;
5789         int pipe = pipe_config->cpu_transcoder;
5790         intel_clock_t clock;
5791         u32 mdiv;
5792         int refclk = 100000;
5793
5794         mutex_lock(&dev_priv->dpio_lock);
5795         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5796         mutex_unlock(&dev_priv->dpio_lock);
5797
5798         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5799         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5800         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5801         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5802         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5803
5804         vlv_clock(refclk, &clock);
5805
5806         /* clock.dot is the fast clock */
5807         pipe_config->port_clock = clock.dot / 5;
5808 }
5809
5810 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5811                                   struct intel_plane_config *plane_config)
5812 {
5813         struct drm_device *dev = crtc->base.dev;
5814         struct drm_i915_private *dev_priv = dev->dev_private;
5815         u32 val, base, offset;
5816         int pipe = crtc->pipe, plane = crtc->plane;
5817         int fourcc, pixel_format;
5818         int aligned_height;
5819
5820         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5821         if (!crtc->base.primary->fb) {
5822                 DRM_DEBUG_KMS("failed to alloc fb\n");
5823                 return;
5824         }
5825
5826         val = I915_READ(DSPCNTR(plane));
5827
5828         if (INTEL_INFO(dev)->gen >= 4)
5829                 if (val & DISPPLANE_TILED)
5830                         plane_config->tiled = true;
5831
5832         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5833         fourcc = intel_format_to_fourcc(pixel_format);
5834         crtc->base.primary->fb->pixel_format = fourcc;
5835         crtc->base.primary->fb->bits_per_pixel =
5836                 drm_format_plane_cpp(fourcc, 0) * 8;
5837
5838         if (INTEL_INFO(dev)->gen >= 4) {
5839                 if (plane_config->tiled)
5840                         offset = I915_READ(DSPTILEOFF(plane));
5841                 else
5842                         offset = I915_READ(DSPLINOFF(plane));
5843                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5844         } else {
5845                 base = I915_READ(DSPADDR(plane));
5846         }
5847         plane_config->base = base;
5848
5849         val = I915_READ(PIPESRC(pipe));
5850         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5851         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5852
5853         val = I915_READ(DSPSTRIDE(pipe));
5854         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5855
5856         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5857                                             plane_config->tiled);
5858
5859         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5860                                    aligned_height, PAGE_SIZE);
5861
5862         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5863                       pipe, plane, crtc->base.primary->fb->width,
5864                       crtc->base.primary->fb->height,
5865                       crtc->base.primary->fb->bits_per_pixel, base,
5866                       crtc->base.primary->fb->pitches[0],
5867                       plane_config->size);
5868
5869 }
5870
5871 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5872                                  struct intel_crtc_config *pipe_config)
5873 {
5874         struct drm_device *dev = crtc->base.dev;
5875         struct drm_i915_private *dev_priv = dev->dev_private;
5876         uint32_t tmp;
5877
5878         if (!intel_display_power_enabled(dev_priv,
5879                                          POWER_DOMAIN_PIPE(crtc->pipe)))
5880                 return false;
5881
5882         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5883         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5884
5885         tmp = I915_READ(PIPECONF(crtc->pipe));
5886         if (!(tmp & PIPECONF_ENABLE))
5887                 return false;
5888
5889         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5890                 switch (tmp & PIPECONF_BPC_MASK) {
5891                 case PIPECONF_6BPC:
5892                         pipe_config->pipe_bpp = 18;
5893                         break;
5894                 case PIPECONF_8BPC:
5895                         pipe_config->pipe_bpp = 24;
5896                         break;
5897                 case PIPECONF_10BPC:
5898                         pipe_config->pipe_bpp = 30;
5899                         break;
5900                 default:
5901                         break;
5902                 }
5903         }
5904
5905         if (INTEL_INFO(dev)->gen < 4)
5906                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5907
5908         intel_get_pipe_timings(crtc, pipe_config);
5909
5910         i9xx_get_pfit_config(crtc, pipe_config);
5911
5912         if (INTEL_INFO(dev)->gen >= 4) {
5913                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5914                 pipe_config->pixel_multiplier =
5915                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5916                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5917                 pipe_config->dpll_hw_state.dpll_md = tmp;
5918         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5919                 tmp = I915_READ(DPLL(crtc->pipe));
5920                 pipe_config->pixel_multiplier =
5921                         ((tmp & SDVO_MULTIPLIER_MASK)
5922                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5923         } else {
5924                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5925                  * port and will be fixed up in the encoder->get_config
5926                  * function. */
5927                 pipe_config->pixel_multiplier = 1;
5928         }
5929         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5930         if (!IS_VALLEYVIEW(dev)) {
5931                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5932                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5933         } else {
5934                 /* Mask out read-only status bits. */
5935                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5936                                                      DPLL_PORTC_READY_MASK |
5937                                                      DPLL_PORTB_READY_MASK);
5938         }
5939
5940         if (IS_VALLEYVIEW(dev))
5941                 vlv_crtc_clock_get(crtc, pipe_config);
5942         else
5943                 i9xx_crtc_clock_get(crtc, pipe_config);
5944
5945         return true;
5946 }
5947
5948 static void ironlake_init_pch_refclk(struct drm_device *dev)
5949 {
5950         struct drm_i915_private *dev_priv = dev->dev_private;
5951         struct drm_mode_config *mode_config = &dev->mode_config;
5952         struct intel_encoder *encoder;
5953         u32 val, final;
5954         bool has_lvds = false;
5955         bool has_cpu_edp = false;
5956         bool has_panel = false;
5957         bool has_ck505 = false;
5958         bool can_ssc = false;
5959
5960         /* We need to take the global config into account */
5961         list_for_each_entry(encoder, &mode_config->encoder_list,
5962                             base.head) {
5963                 switch (encoder->type) {
5964                 case INTEL_OUTPUT_LVDS:
5965                         has_panel = true;
5966                         has_lvds = true;
5967                         break;
5968                 case INTEL_OUTPUT_EDP:
5969                         has_panel = true;
5970                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5971                                 has_cpu_edp = true;
5972                         break;
5973                 }
5974         }
5975
5976         if (HAS_PCH_IBX(dev)) {
5977                 has_ck505 = dev_priv->vbt.display_clock_mode;
5978                 can_ssc = has_ck505;
5979         } else {
5980                 has_ck505 = false;
5981                 can_ssc = true;
5982         }
5983
5984         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5985                       has_panel, has_lvds, has_ck505);
5986
5987         /* Ironlake: try to setup display ref clock before DPLL
5988          * enabling. This is only under driver's control after
5989          * PCH B stepping, previous chipset stepping should be
5990          * ignoring this setting.
5991          */
5992         val = I915_READ(PCH_DREF_CONTROL);
5993
5994         /* As we must carefully and slowly disable/enable each source in turn,
5995          * compute the final state we want first and check if we need to
5996          * make any changes at all.
5997          */
5998         final = val;
5999         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6000         if (has_ck505)
6001                 final |= DREF_NONSPREAD_CK505_ENABLE;
6002         else
6003                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6004
6005         final &= ~DREF_SSC_SOURCE_MASK;
6006         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6007         final &= ~DREF_SSC1_ENABLE;
6008
6009         if (has_panel) {
6010                 final |= DREF_SSC_SOURCE_ENABLE;
6011
6012                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6013                         final |= DREF_SSC1_ENABLE;
6014
6015                 if (has_cpu_edp) {
6016                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6017                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6018                         else
6019                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6020                 } else
6021                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6022         } else {
6023                 final |= DREF_SSC_SOURCE_DISABLE;
6024                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6025         }
6026
6027         if (final == val)
6028                 return;
6029
6030         /* Always enable nonspread source */
6031         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6032
6033         if (has_ck505)
6034                 val |= DREF_NONSPREAD_CK505_ENABLE;
6035         else
6036                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6037
6038         if (has_panel) {
6039                 val &= ~DREF_SSC_SOURCE_MASK;
6040                 val |= DREF_SSC_SOURCE_ENABLE;
6041
6042                 /* SSC must be turned on before enabling the CPU output  */
6043                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6044                         DRM_DEBUG_KMS("Using SSC on panel\n");
6045                         val |= DREF_SSC1_ENABLE;
6046                 } else
6047                         val &= ~DREF_SSC1_ENABLE;
6048
6049                 /* Get SSC going before enabling the outputs */
6050                 I915_WRITE(PCH_DREF_CONTROL, val);
6051                 POSTING_READ(PCH_DREF_CONTROL);
6052                 udelay(200);
6053
6054                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6055
6056                 /* Enable CPU source on CPU attached eDP */
6057                 if (has_cpu_edp) {
6058                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6059                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6060                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6061                         }
6062                         else
6063                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6064                 } else
6065                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6066
6067                 I915_WRITE(PCH_DREF_CONTROL, val);
6068                 POSTING_READ(PCH_DREF_CONTROL);
6069                 udelay(200);
6070         } else {
6071                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6072
6073                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6074
6075                 /* Turn off CPU output */
6076                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6077
6078                 I915_WRITE(PCH_DREF_CONTROL, val);
6079                 POSTING_READ(PCH_DREF_CONTROL);
6080                 udelay(200);
6081
6082                 /* Turn off the SSC source */
6083                 val &= ~DREF_SSC_SOURCE_MASK;
6084                 val |= DREF_SSC_SOURCE_DISABLE;
6085
6086                 /* Turn off SSC1 */
6087                 val &= ~DREF_SSC1_ENABLE;
6088
6089                 I915_WRITE(PCH_DREF_CONTROL, val);
6090                 POSTING_READ(PCH_DREF_CONTROL);
6091                 udelay(200);
6092         }
6093
6094         BUG_ON(val != final);
6095 }
6096
6097 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6098 {
6099         uint32_t tmp;
6100
6101         tmp = I915_READ(SOUTH_CHICKEN2);
6102         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6103         I915_WRITE(SOUTH_CHICKEN2, tmp);
6104
6105         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6106                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6107                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6108
6109         tmp = I915_READ(SOUTH_CHICKEN2);
6110         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6111         I915_WRITE(SOUTH_CHICKEN2, tmp);
6112
6113         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6114                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6115                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6116 }
6117
6118 /* WaMPhyProgramming:hsw */
6119 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6120 {
6121         uint32_t tmp;
6122
6123         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6124         tmp &= ~(0xFF << 24);
6125         tmp |= (0x12 << 24);
6126         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6127
6128         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6129         tmp |= (1 << 11);
6130         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6131
6132         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6133         tmp |= (1 << 11);
6134         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6135
6136         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6137         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6138         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6139
6140         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6141         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6142         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6143
6144         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6145         tmp &= ~(7 << 13);
6146         tmp |= (5 << 13);
6147         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6148
6149         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6150         tmp &= ~(7 << 13);
6151         tmp |= (5 << 13);
6152         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6153
6154         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6155         tmp &= ~0xFF;
6156         tmp |= 0x1C;
6157         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6158
6159         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6160         tmp &= ~0xFF;
6161         tmp |= 0x1C;
6162         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6163
6164         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6165         tmp &= ~(0xFF << 16);
6166         tmp |= (0x1C << 16);
6167         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6168
6169         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6170         tmp &= ~(0xFF << 16);
6171         tmp |= (0x1C << 16);
6172         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6173
6174         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6175         tmp |= (1 << 27);
6176         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6177
6178         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6179         tmp |= (1 << 27);
6180         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6181
6182         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6183         tmp &= ~(0xF << 28);
6184         tmp |= (4 << 28);
6185         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6186
6187         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6188         tmp &= ~(0xF << 28);
6189         tmp |= (4 << 28);
6190         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6191 }
6192
6193 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6194  * Programming" based on the parameters passed:
6195  * - Sequence to enable CLKOUT_DP
6196  * - Sequence to enable CLKOUT_DP without spread
6197  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6198  */
6199 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6200                                  bool with_fdi)
6201 {
6202         struct drm_i915_private *dev_priv = dev->dev_private;
6203         uint32_t reg, tmp;
6204
6205         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6206                 with_spread = true;
6207         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6208                  with_fdi, "LP PCH doesn't have FDI\n"))
6209                 with_fdi = false;
6210
6211         mutex_lock(&dev_priv->dpio_lock);
6212
6213         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6214         tmp &= ~SBI_SSCCTL_DISABLE;
6215         tmp |= SBI_SSCCTL_PATHALT;
6216         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6217
6218         udelay(24);
6219
6220         if (with_spread) {
6221                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6222                 tmp &= ~SBI_SSCCTL_PATHALT;
6223                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6224
6225                 if (with_fdi) {
6226                         lpt_reset_fdi_mphy(dev_priv);
6227                         lpt_program_fdi_mphy(dev_priv);
6228                 }
6229         }
6230
6231         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6232                SBI_GEN0 : SBI_DBUFF0;
6233         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6234         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6235         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6236
6237         mutex_unlock(&dev_priv->dpio_lock);
6238 }
6239
6240 /* Sequence to disable CLKOUT_DP */
6241 static void lpt_disable_clkout_dp(struct drm_device *dev)
6242 {
6243         struct drm_i915_private *dev_priv = dev->dev_private;
6244         uint32_t reg, tmp;
6245
6246         mutex_lock(&dev_priv->dpio_lock);
6247
6248         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6249                SBI_GEN0 : SBI_DBUFF0;
6250         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6251         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6252         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6253
6254         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6255         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6256                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6257                         tmp |= SBI_SSCCTL_PATHALT;
6258                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6259                         udelay(32);
6260                 }
6261                 tmp |= SBI_SSCCTL_DISABLE;
6262                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6263         }
6264
6265         mutex_unlock(&dev_priv->dpio_lock);
6266 }
6267
6268 static void lpt_init_pch_refclk(struct drm_device *dev)
6269 {
6270         struct drm_mode_config *mode_config = &dev->mode_config;
6271         struct intel_encoder *encoder;
6272         bool has_vga = false;
6273
6274         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6275                 switch (encoder->type) {
6276                 case INTEL_OUTPUT_ANALOG:
6277                         has_vga = true;
6278                         break;
6279                 }
6280         }
6281
6282         if (has_vga)
6283                 lpt_enable_clkout_dp(dev, true, true);
6284         else
6285                 lpt_disable_clkout_dp(dev);
6286 }
6287
6288 /*
6289  * Initialize reference clocks when the driver loads
6290  */
6291 void intel_init_pch_refclk(struct drm_device *dev)
6292 {
6293         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6294                 ironlake_init_pch_refclk(dev);
6295         else if (HAS_PCH_LPT(dev))
6296                 lpt_init_pch_refclk(dev);
6297 }
6298
6299 static int ironlake_get_refclk(struct drm_crtc *crtc)
6300 {
6301         struct drm_device *dev = crtc->dev;
6302         struct drm_i915_private *dev_priv = dev->dev_private;
6303         struct intel_encoder *encoder;
6304         int num_connectors = 0;
6305         bool is_lvds = false;
6306
6307         for_each_encoder_on_crtc(dev, crtc, encoder) {
6308                 switch (encoder->type) {
6309                 case INTEL_OUTPUT_LVDS:
6310                         is_lvds = true;
6311                         break;
6312                 }
6313                 num_connectors++;
6314         }
6315
6316         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6317                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6318                               dev_priv->vbt.lvds_ssc_freq);
6319                 return dev_priv->vbt.lvds_ssc_freq;
6320         }
6321
6322         return 120000;
6323 }
6324
6325 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6326 {
6327         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6329         int pipe = intel_crtc->pipe;
6330         uint32_t val;
6331
6332         val = 0;
6333
6334         switch (intel_crtc->config.pipe_bpp) {
6335         case 18:
6336                 val |= PIPECONF_6BPC;
6337                 break;
6338         case 24:
6339                 val |= PIPECONF_8BPC;
6340                 break;
6341         case 30:
6342                 val |= PIPECONF_10BPC;
6343                 break;
6344         case 36:
6345                 val |= PIPECONF_12BPC;
6346                 break;
6347         default:
6348                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6349                 BUG();
6350         }
6351
6352         if (intel_crtc->config.dither)
6353                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6354
6355         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6356                 val |= PIPECONF_INTERLACED_ILK;
6357         else
6358                 val |= PIPECONF_PROGRESSIVE;
6359
6360         if (intel_crtc->config.limited_color_range)
6361                 val |= PIPECONF_COLOR_RANGE_SELECT;
6362
6363         I915_WRITE(PIPECONF(pipe), val);
6364         POSTING_READ(PIPECONF(pipe));
6365 }
6366
6367 /*
6368  * Set up the pipe CSC unit.
6369  *
6370  * Currently only full range RGB to limited range RGB conversion
6371  * is supported, but eventually this should handle various
6372  * RGB<->YCbCr scenarios as well.
6373  */
6374 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6375 {
6376         struct drm_device *dev = crtc->dev;
6377         struct drm_i915_private *dev_priv = dev->dev_private;
6378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379         int pipe = intel_crtc->pipe;
6380         uint16_t coeff = 0x7800; /* 1.0 */
6381
6382         /*
6383          * TODO: Check what kind of values actually come out of the pipe
6384          * with these coeff/postoff values and adjust to get the best
6385          * accuracy. Perhaps we even need to take the bpc value into
6386          * consideration.
6387          */
6388
6389         if (intel_crtc->config.limited_color_range)
6390                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6391
6392         /*
6393          * GY/GU and RY/RU should be the other way around according
6394          * to BSpec, but reality doesn't agree. Just set them up in
6395          * a way that results in the correct picture.
6396          */
6397         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6398         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6399
6400         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6401         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6402
6403         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6404         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6405
6406         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6407         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6408         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6409
6410         if (INTEL_INFO(dev)->gen > 6) {
6411                 uint16_t postoff = 0;
6412
6413                 if (intel_crtc->config.limited_color_range)
6414                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6415
6416                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6417                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6418                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6419
6420                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6421         } else {
6422                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6423
6424                 if (intel_crtc->config.limited_color_range)
6425                         mode |= CSC_BLACK_SCREEN_OFFSET;
6426
6427                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6428         }
6429 }
6430
6431 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6432 {
6433         struct drm_device *dev = crtc->dev;
6434         struct drm_i915_private *dev_priv = dev->dev_private;
6435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6436         enum pipe pipe = intel_crtc->pipe;
6437         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6438         uint32_t val;
6439
6440         val = 0;
6441
6442         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6443                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6444
6445         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6446                 val |= PIPECONF_INTERLACED_ILK;
6447         else
6448                 val |= PIPECONF_PROGRESSIVE;
6449
6450         I915_WRITE(PIPECONF(cpu_transcoder), val);
6451         POSTING_READ(PIPECONF(cpu_transcoder));
6452
6453         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6454         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6455
6456         if (IS_BROADWELL(dev)) {
6457                 val = 0;
6458
6459                 switch (intel_crtc->config.pipe_bpp) {
6460                 case 18:
6461                         val |= PIPEMISC_DITHER_6_BPC;
6462                         break;
6463                 case 24:
6464                         val |= PIPEMISC_DITHER_8_BPC;
6465                         break;
6466                 case 30:
6467                         val |= PIPEMISC_DITHER_10_BPC;
6468                         break;
6469                 case 36:
6470                         val |= PIPEMISC_DITHER_12_BPC;
6471                         break;
6472                 default:
6473                         /* Case prevented by pipe_config_set_bpp. */
6474                         BUG();
6475                 }
6476
6477                 if (intel_crtc->config.dither)
6478                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6479
6480                 I915_WRITE(PIPEMISC(pipe), val);
6481         }
6482 }
6483
6484 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6485                                     intel_clock_t *clock,
6486                                     bool *has_reduced_clock,
6487                                     intel_clock_t *reduced_clock)
6488 {
6489         struct drm_device *dev = crtc->dev;
6490         struct drm_i915_private *dev_priv = dev->dev_private;
6491         struct intel_encoder *intel_encoder;
6492         int refclk;
6493         const intel_limit_t *limit;
6494         bool ret, is_lvds = false;
6495
6496         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6497                 switch (intel_encoder->type) {
6498                 case INTEL_OUTPUT_LVDS:
6499                         is_lvds = true;
6500                         break;
6501                 }
6502         }
6503
6504         refclk = ironlake_get_refclk(crtc);
6505
6506         /*
6507          * Returns a set of divisors for the desired target clock with the given
6508          * refclk, or FALSE.  The returned values represent the clock equation:
6509          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6510          */
6511         limit = intel_limit(crtc, refclk);
6512         ret = dev_priv->display.find_dpll(limit, crtc,
6513                                           to_intel_crtc(crtc)->config.port_clock,
6514                                           refclk, NULL, clock);
6515         if (!ret)
6516                 return false;
6517
6518         if (is_lvds && dev_priv->lvds_downclock_avail) {
6519                 /*
6520                  * Ensure we match the reduced clock's P to the target clock.
6521                  * If the clocks don't match, we can't switch the display clock
6522                  * by using the FP0/FP1. In such case we will disable the LVDS
6523                  * downclock feature.
6524                 */
6525                 *has_reduced_clock =
6526                         dev_priv->display.find_dpll(limit, crtc,
6527                                                     dev_priv->lvds_downclock,
6528                                                     refclk, clock,
6529                                                     reduced_clock);
6530         }
6531
6532         return true;
6533 }
6534
6535 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6536 {
6537         /*
6538          * Account for spread spectrum to avoid
6539          * oversubscribing the link. Max center spread
6540          * is 2.5%; use 5% for safety's sake.
6541          */
6542         u32 bps = target_clock * bpp * 21 / 20;
6543         return DIV_ROUND_UP(bps, link_bw * 8);
6544 }
6545
6546 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6547 {
6548         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6549 }
6550
6551 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6552                                       u32 *fp,
6553                                       intel_clock_t *reduced_clock, u32 *fp2)
6554 {
6555         struct drm_crtc *crtc = &intel_crtc->base;
6556         struct drm_device *dev = crtc->dev;
6557         struct drm_i915_private *dev_priv = dev->dev_private;
6558         struct intel_encoder *intel_encoder;
6559         uint32_t dpll;
6560         int factor, num_connectors = 0;
6561         bool is_lvds = false, is_sdvo = false;
6562
6563         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6564                 switch (intel_encoder->type) {
6565                 case INTEL_OUTPUT_LVDS:
6566                         is_lvds = true;
6567                         break;
6568                 case INTEL_OUTPUT_SDVO:
6569                 case INTEL_OUTPUT_HDMI:
6570                         is_sdvo = true;
6571                         break;
6572                 }
6573
6574                 num_connectors++;
6575         }
6576
6577         /* Enable autotuning of the PLL clock (if permissible) */
6578         factor = 21;
6579         if (is_lvds) {
6580                 if ((intel_panel_use_ssc(dev_priv) &&
6581                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6582                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6583                         factor = 25;
6584         } else if (intel_crtc->config.sdvo_tv_clock)
6585                 factor = 20;
6586
6587         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6588                 *fp |= FP_CB_TUNE;
6589
6590         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6591                 *fp2 |= FP_CB_TUNE;
6592
6593         dpll = 0;
6594
6595         if (is_lvds)
6596                 dpll |= DPLLB_MODE_LVDS;
6597         else
6598                 dpll |= DPLLB_MODE_DAC_SERIAL;
6599
6600         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6601                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6602
6603         if (is_sdvo)
6604                 dpll |= DPLL_SDVO_HIGH_SPEED;
6605         if (intel_crtc->config.has_dp_encoder)
6606                 dpll |= DPLL_SDVO_HIGH_SPEED;
6607
6608         /* compute bitmask from p1 value */
6609         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6610         /* also FPA1 */
6611         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6612
6613         switch (intel_crtc->config.dpll.p2) {
6614         case 5:
6615                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6616                 break;
6617         case 7:
6618                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6619                 break;
6620         case 10:
6621                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6622                 break;
6623         case 14:
6624                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6625                 break;
6626         }
6627
6628         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6629                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6630         else
6631                 dpll |= PLL_REF_INPUT_DREFCLK;
6632
6633         return dpll | DPLL_VCO_ENABLE;
6634 }
6635
6636 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6637                                   int x, int y,
6638                                   struct drm_framebuffer *fb)
6639 {
6640         struct drm_device *dev = crtc->dev;
6641         struct drm_i915_private *dev_priv = dev->dev_private;
6642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6643         int pipe = intel_crtc->pipe;
6644         int plane = intel_crtc->plane;
6645         int num_connectors = 0;
6646         intel_clock_t clock, reduced_clock;
6647         u32 dpll = 0, fp = 0, fp2 = 0;
6648         bool ok, has_reduced_clock = false;
6649         bool is_lvds = false;
6650         struct intel_encoder *encoder;
6651         struct intel_shared_dpll *pll;
6652         int ret;
6653
6654         for_each_encoder_on_crtc(dev, crtc, encoder) {
6655                 switch (encoder->type) {
6656                 case INTEL_OUTPUT_LVDS:
6657                         is_lvds = true;
6658                         break;
6659                 }
6660
6661                 num_connectors++;
6662         }
6663
6664         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6665              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6666
6667         ok = ironlake_compute_clocks(crtc, &clock,
6668                                      &has_reduced_clock, &reduced_clock);
6669         if (!ok && !intel_crtc->config.clock_set) {
6670                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6671                 return -EINVAL;
6672         }
6673         /* Compat-code for transition, will disappear. */
6674         if (!intel_crtc->config.clock_set) {
6675                 intel_crtc->config.dpll.n = clock.n;
6676                 intel_crtc->config.dpll.m1 = clock.m1;
6677                 intel_crtc->config.dpll.m2 = clock.m2;
6678                 intel_crtc->config.dpll.p1 = clock.p1;
6679                 intel_crtc->config.dpll.p2 = clock.p2;
6680         }
6681
6682         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6683         if (intel_crtc->config.has_pch_encoder) {
6684                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6685                 if (has_reduced_clock)
6686                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6687
6688                 dpll = ironlake_compute_dpll(intel_crtc,
6689                                              &fp, &reduced_clock,
6690                                              has_reduced_clock ? &fp2 : NULL);
6691
6692                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6693                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6694                 if (has_reduced_clock)
6695                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6696                 else
6697                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6698
6699                 pll = intel_get_shared_dpll(intel_crtc);
6700                 if (pll == NULL) {
6701                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6702                                          pipe_name(pipe));
6703                         return -EINVAL;
6704                 }
6705         } else
6706                 intel_put_shared_dpll(intel_crtc);
6707
6708         if (intel_crtc->config.has_dp_encoder)
6709                 intel_dp_set_m_n(intel_crtc);
6710
6711         if (is_lvds && has_reduced_clock && i915.powersave)
6712                 intel_crtc->lowfreq_avail = true;
6713         else
6714                 intel_crtc->lowfreq_avail = false;
6715
6716         intel_set_pipe_timings(intel_crtc);
6717
6718         if (intel_crtc->config.has_pch_encoder) {
6719                 intel_cpu_transcoder_set_m_n(intel_crtc,
6720                                              &intel_crtc->config.fdi_m_n);
6721         }
6722
6723         ironlake_set_pipeconf(crtc);
6724
6725         /* Set up the display plane register */
6726         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6727         POSTING_READ(DSPCNTR(plane));
6728
6729         ret = intel_pipe_set_base(crtc, x, y, fb);
6730
6731         return ret;
6732 }
6733
6734 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6735                                          struct intel_link_m_n *m_n)
6736 {
6737         struct drm_device *dev = crtc->base.dev;
6738         struct drm_i915_private *dev_priv = dev->dev_private;
6739         enum pipe pipe = crtc->pipe;
6740
6741         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6742         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6743         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6744                 & ~TU_SIZE_MASK;
6745         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6746         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6747                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6748 }
6749
6750 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6751                                          enum transcoder transcoder,
6752                                          struct intel_link_m_n *m_n)
6753 {
6754         struct drm_device *dev = crtc->base.dev;
6755         struct drm_i915_private *dev_priv = dev->dev_private;
6756         enum pipe pipe = crtc->pipe;
6757
6758         if (INTEL_INFO(dev)->gen >= 5) {
6759                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6760                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6761                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6762                         & ~TU_SIZE_MASK;
6763                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6764                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6765                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6766         } else {
6767                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6768                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6769                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6770                         & ~TU_SIZE_MASK;
6771                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6772                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6773                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6774         }
6775 }
6776
6777 void intel_dp_get_m_n(struct intel_crtc *crtc,
6778                       struct intel_crtc_config *pipe_config)
6779 {
6780         if (crtc->config.has_pch_encoder)
6781                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6782         else
6783                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6784                                              &pipe_config->dp_m_n);
6785 }
6786
6787 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6788                                         struct intel_crtc_config *pipe_config)
6789 {
6790         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6791                                      &pipe_config->fdi_m_n);
6792 }
6793
6794 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6795                                      struct intel_crtc_config *pipe_config)
6796 {
6797         struct drm_device *dev = crtc->base.dev;
6798         struct drm_i915_private *dev_priv = dev->dev_private;
6799         uint32_t tmp;
6800
6801         tmp = I915_READ(PF_CTL(crtc->pipe));
6802
6803         if (tmp & PF_ENABLE) {
6804                 pipe_config->pch_pfit.enabled = true;
6805                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6806                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6807
6808                 /* We currently do not free assignements of panel fitters on
6809                  * ivb/hsw (since we don't use the higher upscaling modes which
6810                  * differentiates them) so just WARN about this case for now. */
6811                 if (IS_GEN7(dev)) {
6812                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6813                                 PF_PIPE_SEL_IVB(crtc->pipe));
6814                 }
6815         }
6816 }
6817
6818 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6819                                       struct intel_plane_config *plane_config)
6820 {
6821         struct drm_device *dev = crtc->base.dev;
6822         struct drm_i915_private *dev_priv = dev->dev_private;
6823         u32 val, base, offset;
6824         int pipe = crtc->pipe, plane = crtc->plane;
6825         int fourcc, pixel_format;
6826         int aligned_height;
6827
6828         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6829         if (!crtc->base.primary->fb) {
6830                 DRM_DEBUG_KMS("failed to alloc fb\n");
6831                 return;
6832         }
6833
6834         val = I915_READ(DSPCNTR(plane));
6835
6836         if (INTEL_INFO(dev)->gen >= 4)
6837                 if (val & DISPPLANE_TILED)
6838                         plane_config->tiled = true;
6839
6840         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6841         fourcc = intel_format_to_fourcc(pixel_format);
6842         crtc->base.primary->fb->pixel_format = fourcc;
6843         crtc->base.primary->fb->bits_per_pixel =
6844                 drm_format_plane_cpp(fourcc, 0) * 8;
6845
6846         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6847         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6848                 offset = I915_READ(DSPOFFSET(plane));
6849         } else {
6850                 if (plane_config->tiled)
6851                         offset = I915_READ(DSPTILEOFF(plane));
6852                 else
6853                         offset = I915_READ(DSPLINOFF(plane));
6854         }
6855         plane_config->base = base;
6856
6857         val = I915_READ(PIPESRC(pipe));
6858         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6859         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6860
6861         val = I915_READ(DSPSTRIDE(pipe));
6862         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6863
6864         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6865                                             plane_config->tiled);
6866
6867         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6868                                    aligned_height, PAGE_SIZE);
6869
6870         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6871                       pipe, plane, crtc->base.primary->fb->width,
6872                       crtc->base.primary->fb->height,
6873                       crtc->base.primary->fb->bits_per_pixel, base,
6874                       crtc->base.primary->fb->pitches[0],
6875                       plane_config->size);
6876 }
6877
6878 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6879                                      struct intel_crtc_config *pipe_config)
6880 {
6881         struct drm_device *dev = crtc->base.dev;
6882         struct drm_i915_private *dev_priv = dev->dev_private;
6883         uint32_t tmp;
6884
6885         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6886         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6887
6888         tmp = I915_READ(PIPECONF(crtc->pipe));
6889         if (!(tmp & PIPECONF_ENABLE))
6890                 return false;
6891
6892         switch (tmp & PIPECONF_BPC_MASK) {
6893         case PIPECONF_6BPC:
6894                 pipe_config->pipe_bpp = 18;
6895                 break;
6896         case PIPECONF_8BPC:
6897                 pipe_config->pipe_bpp = 24;
6898                 break;
6899         case PIPECONF_10BPC:
6900                 pipe_config->pipe_bpp = 30;
6901                 break;
6902         case PIPECONF_12BPC:
6903                 pipe_config->pipe_bpp = 36;
6904                 break;
6905         default:
6906                 break;
6907         }
6908
6909         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6910                 struct intel_shared_dpll *pll;
6911
6912                 pipe_config->has_pch_encoder = true;
6913
6914                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6915                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6916                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6917
6918                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6919
6920                 if (HAS_PCH_IBX(dev_priv->dev)) {
6921                         pipe_config->shared_dpll =
6922                                 (enum intel_dpll_id) crtc->pipe;
6923                 } else {
6924                         tmp = I915_READ(PCH_DPLL_SEL);
6925                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6926                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6927                         else
6928                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6929                 }
6930
6931                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6932
6933                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6934                                            &pipe_config->dpll_hw_state));
6935
6936                 tmp = pipe_config->dpll_hw_state.dpll;
6937                 pipe_config->pixel_multiplier =
6938                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6939                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6940
6941                 ironlake_pch_clock_get(crtc, pipe_config);
6942         } else {
6943                 pipe_config->pixel_multiplier = 1;
6944         }
6945
6946         intel_get_pipe_timings(crtc, pipe_config);
6947
6948         ironlake_get_pfit_config(crtc, pipe_config);
6949
6950         return true;
6951 }
6952
6953 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6954 {
6955         struct drm_device *dev = dev_priv->dev;
6956         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6957         struct intel_crtc *crtc;
6958
6959         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6960                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6961                      pipe_name(crtc->pipe));
6962
6963         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6964         WARN(plls->spll_refcount, "SPLL enabled\n");
6965         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6966         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6967         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6968         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6969              "CPU PWM1 enabled\n");
6970         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6971              "CPU PWM2 enabled\n");
6972         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6973              "PCH PWM1 enabled\n");
6974         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6975              "Utility pin enabled\n");
6976         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6977
6978         /*
6979          * In theory we can still leave IRQs enabled, as long as only the HPD
6980          * interrupts remain enabled. We used to check for that, but since it's
6981          * gen-specific and since we only disable LCPLL after we fully disable
6982          * the interrupts, the check below should be enough.
6983          */
6984         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
6985 }
6986
6987 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
6988 {
6989         struct drm_device *dev = dev_priv->dev;
6990
6991         if (IS_HASWELL(dev)) {
6992                 mutex_lock(&dev_priv->rps.hw_lock);
6993                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
6994                                             val))
6995                         DRM_ERROR("Failed to disable D_COMP\n");
6996                 mutex_unlock(&dev_priv->rps.hw_lock);
6997         } else {
6998                 I915_WRITE(D_COMP, val);
6999         }
7000         POSTING_READ(D_COMP);
7001 }
7002
7003 /*
7004  * This function implements pieces of two sequences from BSpec:
7005  * - Sequence for display software to disable LCPLL
7006  * - Sequence for display software to allow package C8+
7007  * The steps implemented here are just the steps that actually touch the LCPLL
7008  * register. Callers should take care of disabling all the display engine
7009  * functions, doing the mode unset, fixing interrupts, etc.
7010  */
7011 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7012                               bool switch_to_fclk, bool allow_power_down)
7013 {
7014         uint32_t val;
7015
7016         assert_can_disable_lcpll(dev_priv);
7017
7018         val = I915_READ(LCPLL_CTL);
7019
7020         if (switch_to_fclk) {
7021                 val |= LCPLL_CD_SOURCE_FCLK;
7022                 I915_WRITE(LCPLL_CTL, val);
7023
7024                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7025                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7026                         DRM_ERROR("Switching to FCLK failed\n");
7027
7028                 val = I915_READ(LCPLL_CTL);
7029         }
7030
7031         val |= LCPLL_PLL_DISABLE;
7032         I915_WRITE(LCPLL_CTL, val);
7033         POSTING_READ(LCPLL_CTL);
7034
7035         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7036                 DRM_ERROR("LCPLL still locked\n");
7037
7038         val = I915_READ(D_COMP);
7039         val |= D_COMP_COMP_DISABLE;
7040         hsw_write_dcomp(dev_priv, val);
7041         ndelay(100);
7042
7043         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7044                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7045
7046         if (allow_power_down) {
7047                 val = I915_READ(LCPLL_CTL);
7048                 val |= LCPLL_POWER_DOWN_ALLOW;
7049                 I915_WRITE(LCPLL_CTL, val);
7050                 POSTING_READ(LCPLL_CTL);
7051         }
7052 }
7053
7054 /*
7055  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7056  * source.
7057  */
7058 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7059 {
7060         uint32_t val;
7061         unsigned long irqflags;
7062
7063         val = I915_READ(LCPLL_CTL);
7064
7065         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7066                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7067                 return;
7068
7069         /*
7070          * Make sure we're not on PC8 state before disabling PC8, otherwise
7071          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7072          *
7073          * The other problem is that hsw_restore_lcpll() is called as part of
7074          * the runtime PM resume sequence, so we can't just call
7075          * gen6_gt_force_wake_get() because that function calls
7076          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7077          * while we are on the resume sequence. So to solve this problem we have
7078          * to call special forcewake code that doesn't touch runtime PM and
7079          * doesn't enable the forcewake delayed work.
7080          */
7081         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7082         if (dev_priv->uncore.forcewake_count++ == 0)
7083                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7084         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7085
7086         if (val & LCPLL_POWER_DOWN_ALLOW) {
7087                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7088                 I915_WRITE(LCPLL_CTL, val);
7089                 POSTING_READ(LCPLL_CTL);
7090         }
7091
7092         val = I915_READ(D_COMP);
7093         val |= D_COMP_COMP_FORCE;
7094         val &= ~D_COMP_COMP_DISABLE;
7095         hsw_write_dcomp(dev_priv, val);
7096
7097         val = I915_READ(LCPLL_CTL);
7098         val &= ~LCPLL_PLL_DISABLE;
7099         I915_WRITE(LCPLL_CTL, val);
7100
7101         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7102                 DRM_ERROR("LCPLL not locked yet\n");
7103
7104         if (val & LCPLL_CD_SOURCE_FCLK) {
7105                 val = I915_READ(LCPLL_CTL);
7106                 val &= ~LCPLL_CD_SOURCE_FCLK;
7107                 I915_WRITE(LCPLL_CTL, val);
7108
7109                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7110                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7111                         DRM_ERROR("Switching back to LCPLL failed\n");
7112         }
7113
7114         /* See the big comment above. */
7115         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7116         if (--dev_priv->uncore.forcewake_count == 0)
7117                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7118         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7119 }
7120
7121 /*
7122  * Package states C8 and deeper are really deep PC states that can only be
7123  * reached when all the devices on the system allow it, so even if the graphics
7124  * device allows PC8+, it doesn't mean the system will actually get to these
7125  * states. Our driver only allows PC8+ when going into runtime PM.
7126  *
7127  * The requirements for PC8+ are that all the outputs are disabled, the power
7128  * well is disabled and most interrupts are disabled, and these are also
7129  * requirements for runtime PM. When these conditions are met, we manually do
7130  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7131  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7132  * hang the machine.
7133  *
7134  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7135  * the state of some registers, so when we come back from PC8+ we need to
7136  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7137  * need to take care of the registers kept by RC6. Notice that this happens even
7138  * if we don't put the device in PCI D3 state (which is what currently happens
7139  * because of the runtime PM support).
7140  *
7141  * For more, read "Display Sequences for Package C8" on the hardware
7142  * documentation.
7143  */
7144 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7145 {
7146         struct drm_device *dev = dev_priv->dev;
7147         uint32_t val;
7148
7149         DRM_DEBUG_KMS("Enabling package C8+\n");
7150
7151         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7152                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7153                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7154                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7155         }
7156
7157         lpt_disable_clkout_dp(dev);
7158         hsw_disable_lcpll(dev_priv, true, true);
7159 }
7160
7161 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7162 {
7163         struct drm_device *dev = dev_priv->dev;
7164         uint32_t val;
7165
7166         DRM_DEBUG_KMS("Disabling package C8+\n");
7167
7168         hsw_restore_lcpll(dev_priv);
7169         lpt_init_pch_refclk(dev);
7170
7171         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7172                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7173                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7174                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7175         }
7176
7177         intel_prepare_ddi(dev);
7178 }
7179
7180 static void snb_modeset_global_resources(struct drm_device *dev)
7181 {
7182         modeset_update_crtc_power_domains(dev);
7183 }
7184
7185 static void haswell_modeset_global_resources(struct drm_device *dev)
7186 {
7187         modeset_update_crtc_power_domains(dev);
7188 }
7189
7190 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7191                                  int x, int y,
7192                                  struct drm_framebuffer *fb)
7193 {
7194         struct drm_device *dev = crtc->dev;
7195         struct drm_i915_private *dev_priv = dev->dev_private;
7196         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7197         int plane = intel_crtc->plane;
7198         int ret;
7199
7200         if (!intel_ddi_pll_select(intel_crtc))
7201                 return -EINVAL;
7202         intel_ddi_pll_enable(intel_crtc);
7203
7204         if (intel_crtc->config.has_dp_encoder)
7205                 intel_dp_set_m_n(intel_crtc);
7206
7207         intel_crtc->lowfreq_avail = false;
7208
7209         intel_set_pipe_timings(intel_crtc);
7210
7211         if (intel_crtc->config.has_pch_encoder) {
7212                 intel_cpu_transcoder_set_m_n(intel_crtc,
7213                                              &intel_crtc->config.fdi_m_n);
7214         }
7215
7216         haswell_set_pipeconf(crtc);
7217
7218         intel_set_pipe_csc(crtc);
7219
7220         /* Set up the display plane register */
7221         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7222         POSTING_READ(DSPCNTR(plane));
7223
7224         ret = intel_pipe_set_base(crtc, x, y, fb);
7225
7226         return ret;
7227 }
7228
7229 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7230                                     struct intel_crtc_config *pipe_config)
7231 {
7232         struct drm_device *dev = crtc->base.dev;
7233         struct drm_i915_private *dev_priv = dev->dev_private;
7234         enum intel_display_power_domain pfit_domain;
7235         uint32_t tmp;
7236
7237         if (!intel_display_power_enabled(dev_priv,
7238                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7239                 return false;
7240
7241         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7242         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7243
7244         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7245         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7246                 enum pipe trans_edp_pipe;
7247                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7248                 default:
7249                         WARN(1, "unknown pipe linked to edp transcoder\n");
7250                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7251                 case TRANS_DDI_EDP_INPUT_A_ON:
7252                         trans_edp_pipe = PIPE_A;
7253                         break;
7254                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7255                         trans_edp_pipe = PIPE_B;
7256                         break;
7257                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7258                         trans_edp_pipe = PIPE_C;
7259                         break;
7260                 }
7261
7262                 if (trans_edp_pipe == crtc->pipe)
7263                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7264         }
7265
7266         if (!intel_display_power_enabled(dev_priv,
7267                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7268                 return false;
7269
7270         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7271         if (!(tmp & PIPECONF_ENABLE))
7272                 return false;
7273
7274         /*
7275          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7276          * DDI E. So just check whether this pipe is wired to DDI E and whether
7277          * the PCH transcoder is on.
7278          */
7279         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7280         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7281             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7282                 pipe_config->has_pch_encoder = true;
7283
7284                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7285                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7286                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7287
7288                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7289         }
7290
7291         intel_get_pipe_timings(crtc, pipe_config);
7292
7293         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7294         if (intel_display_power_enabled(dev_priv, pfit_domain))
7295                 ironlake_get_pfit_config(crtc, pipe_config);
7296
7297         if (IS_HASWELL(dev))
7298                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7299                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7300
7301         pipe_config->pixel_multiplier = 1;
7302
7303         return true;
7304 }
7305
7306 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7307                                int x, int y,
7308                                struct drm_framebuffer *fb)
7309 {
7310         struct drm_device *dev = crtc->dev;
7311         struct drm_i915_private *dev_priv = dev->dev_private;
7312         struct intel_encoder *encoder;
7313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7314         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7315         int pipe = intel_crtc->pipe;
7316         int ret;
7317
7318         drm_vblank_pre_modeset(dev, pipe);
7319
7320         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7321
7322         drm_vblank_post_modeset(dev, pipe);
7323
7324         if (ret != 0)
7325                 return ret;
7326
7327         for_each_encoder_on_crtc(dev, crtc, encoder) {
7328                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7329                         encoder->base.base.id,
7330                         drm_get_encoder_name(&encoder->base),
7331                         mode->base.id, mode->name);
7332
7333                 if (encoder->mode_set)
7334                         encoder->mode_set(encoder);
7335         }
7336
7337         return 0;
7338 }
7339
7340 static struct {
7341         int clock;
7342         u32 config;
7343 } hdmi_audio_clock[] = {
7344         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7345         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7346         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7347         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7348         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7349         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7350         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7351         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7352         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7353         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7354 };
7355
7356 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7357 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7358 {
7359         int i;
7360
7361         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7362                 if (mode->clock == hdmi_audio_clock[i].clock)
7363                         break;
7364         }
7365
7366         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7367                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7368                 i = 1;
7369         }
7370
7371         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7372                       hdmi_audio_clock[i].clock,
7373                       hdmi_audio_clock[i].config);
7374
7375         return hdmi_audio_clock[i].config;
7376 }
7377
7378 static bool intel_eld_uptodate(struct drm_connector *connector,
7379                                int reg_eldv, uint32_t bits_eldv,
7380                                int reg_elda, uint32_t bits_elda,
7381                                int reg_edid)
7382 {
7383         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7384         uint8_t *eld = connector->eld;
7385         uint32_t i;
7386
7387         i = I915_READ(reg_eldv);
7388         i &= bits_eldv;
7389
7390         if (!eld[0])
7391                 return !i;
7392
7393         if (!i)
7394                 return false;
7395
7396         i = I915_READ(reg_elda);
7397         i &= ~bits_elda;
7398         I915_WRITE(reg_elda, i);
7399
7400         for (i = 0; i < eld[2]; i++)
7401                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7402                         return false;
7403
7404         return true;
7405 }
7406
7407 static void g4x_write_eld(struct drm_connector *connector,
7408                           struct drm_crtc *crtc,
7409                           struct drm_display_mode *mode)
7410 {
7411         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7412         uint8_t *eld = connector->eld;
7413         uint32_t eldv;
7414         uint32_t len;
7415         uint32_t i;
7416
7417         i = I915_READ(G4X_AUD_VID_DID);
7418
7419         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7420                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7421         else
7422                 eldv = G4X_ELDV_DEVCTG;
7423
7424         if (intel_eld_uptodate(connector,
7425                                G4X_AUD_CNTL_ST, eldv,
7426                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7427                                G4X_HDMIW_HDMIEDID))
7428                 return;
7429
7430         i = I915_READ(G4X_AUD_CNTL_ST);
7431         i &= ~(eldv | G4X_ELD_ADDR);
7432         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7433         I915_WRITE(G4X_AUD_CNTL_ST, i);
7434
7435         if (!eld[0])
7436                 return;
7437
7438         len = min_t(uint8_t, eld[2], len);
7439         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7440         for (i = 0; i < len; i++)
7441                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7442
7443         i = I915_READ(G4X_AUD_CNTL_ST);
7444         i |= eldv;
7445         I915_WRITE(G4X_AUD_CNTL_ST, i);
7446 }
7447
7448 static void haswell_write_eld(struct drm_connector *connector,
7449                               struct drm_crtc *crtc,
7450                               struct drm_display_mode *mode)
7451 {
7452         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7453         uint8_t *eld = connector->eld;
7454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7455         uint32_t eldv;
7456         uint32_t i;
7457         int len;
7458         int pipe = to_intel_crtc(crtc)->pipe;
7459         int tmp;
7460
7461         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7462         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7463         int aud_config = HSW_AUD_CFG(pipe);
7464         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7465
7466         /* Audio output enable */
7467         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7468         tmp = I915_READ(aud_cntrl_st2);
7469         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7470         I915_WRITE(aud_cntrl_st2, tmp);
7471         POSTING_READ(aud_cntrl_st2);
7472
7473         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7474
7475         /* Set ELD valid state */
7476         tmp = I915_READ(aud_cntrl_st2);
7477         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7478         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7479         I915_WRITE(aud_cntrl_st2, tmp);
7480         tmp = I915_READ(aud_cntrl_st2);
7481         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7482
7483         /* Enable HDMI mode */
7484         tmp = I915_READ(aud_config);
7485         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7486         /* clear N_programing_enable and N_value_index */
7487         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7488         I915_WRITE(aud_config, tmp);
7489
7490         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7491
7492         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7493         intel_crtc->eld_vld = true;
7494
7495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7496                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7497                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7498                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7499         } else {
7500                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7501         }
7502
7503         if (intel_eld_uptodate(connector,
7504                                aud_cntrl_st2, eldv,
7505                                aud_cntl_st, IBX_ELD_ADDRESS,
7506                                hdmiw_hdmiedid))
7507                 return;
7508
7509         i = I915_READ(aud_cntrl_st2);
7510         i &= ~eldv;
7511         I915_WRITE(aud_cntrl_st2, i);
7512
7513         if (!eld[0])
7514                 return;
7515
7516         i = I915_READ(aud_cntl_st);
7517         i &= ~IBX_ELD_ADDRESS;
7518         I915_WRITE(aud_cntl_st, i);
7519         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7520         DRM_DEBUG_DRIVER("port num:%d\n", i);
7521
7522         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7523         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7524         for (i = 0; i < len; i++)
7525                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7526
7527         i = I915_READ(aud_cntrl_st2);
7528         i |= eldv;
7529         I915_WRITE(aud_cntrl_st2, i);
7530
7531 }
7532
7533 static void ironlake_write_eld(struct drm_connector *connector,
7534                                struct drm_crtc *crtc,
7535                                struct drm_display_mode *mode)
7536 {
7537         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7538         uint8_t *eld = connector->eld;
7539         uint32_t eldv;
7540         uint32_t i;
7541         int len;
7542         int hdmiw_hdmiedid;
7543         int aud_config;
7544         int aud_cntl_st;
7545         int aud_cntrl_st2;
7546         int pipe = to_intel_crtc(crtc)->pipe;
7547
7548         if (HAS_PCH_IBX(connector->dev)) {
7549                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7550                 aud_config = IBX_AUD_CFG(pipe);
7551                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7552                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7553         } else if (IS_VALLEYVIEW(connector->dev)) {
7554                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7555                 aud_config = VLV_AUD_CFG(pipe);
7556                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7557                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7558         } else {
7559                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7560                 aud_config = CPT_AUD_CFG(pipe);
7561                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7562                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7563         }
7564
7565         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7566
7567         if (IS_VALLEYVIEW(connector->dev))  {
7568                 struct intel_encoder *intel_encoder;
7569                 struct intel_digital_port *intel_dig_port;
7570
7571                 intel_encoder = intel_attached_encoder(connector);
7572                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7573                 i = intel_dig_port->port;
7574         } else {
7575                 i = I915_READ(aud_cntl_st);
7576                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7577                 /* DIP_Port_Select, 0x1 = PortB */
7578         }
7579
7580         if (!i) {
7581                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7582                 /* operate blindly on all ports */
7583                 eldv = IBX_ELD_VALIDB;
7584                 eldv |= IBX_ELD_VALIDB << 4;
7585                 eldv |= IBX_ELD_VALIDB << 8;
7586         } else {
7587                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7588                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7589         }
7590
7591         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7592                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7593                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7594                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7595         } else {
7596                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7597         }
7598
7599         if (intel_eld_uptodate(connector,
7600                                aud_cntrl_st2, eldv,
7601                                aud_cntl_st, IBX_ELD_ADDRESS,
7602                                hdmiw_hdmiedid))
7603                 return;
7604
7605         i = I915_READ(aud_cntrl_st2);
7606         i &= ~eldv;
7607         I915_WRITE(aud_cntrl_st2, i);
7608
7609         if (!eld[0])
7610                 return;
7611
7612         i = I915_READ(aud_cntl_st);
7613         i &= ~IBX_ELD_ADDRESS;
7614         I915_WRITE(aud_cntl_st, i);
7615
7616         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7617         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7618         for (i = 0; i < len; i++)
7619                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7620
7621         i = I915_READ(aud_cntrl_st2);
7622         i |= eldv;
7623         I915_WRITE(aud_cntrl_st2, i);
7624 }
7625
7626 void intel_write_eld(struct drm_encoder *encoder,
7627                      struct drm_display_mode *mode)
7628 {
7629         struct drm_crtc *crtc = encoder->crtc;
7630         struct drm_connector *connector;
7631         struct drm_device *dev = encoder->dev;
7632         struct drm_i915_private *dev_priv = dev->dev_private;
7633
7634         connector = drm_select_eld(encoder, mode);
7635         if (!connector)
7636                 return;
7637
7638         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7639                          connector->base.id,
7640                          drm_get_connector_name(connector),
7641                          connector->encoder->base.id,
7642                          drm_get_encoder_name(connector->encoder));
7643
7644         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7645
7646         if (dev_priv->display.write_eld)
7647                 dev_priv->display.write_eld(connector, crtc, mode);
7648 }
7649
7650 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7651 {
7652         struct drm_device *dev = crtc->dev;
7653         struct drm_i915_private *dev_priv = dev->dev_private;
7654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7655         bool visible = base != 0;
7656         u32 cntl;
7657
7658         if (intel_crtc->cursor_visible == visible)
7659                 return;
7660
7661         cntl = I915_READ(_CURACNTR);
7662         if (visible) {
7663                 /* On these chipsets we can only modify the base whilst
7664                  * the cursor is disabled.
7665                  */
7666                 I915_WRITE(_CURABASE, base);
7667
7668                 cntl &= ~(CURSOR_FORMAT_MASK);
7669                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7670                 cntl |= CURSOR_ENABLE |
7671                         CURSOR_GAMMA_ENABLE |
7672                         CURSOR_FORMAT_ARGB;
7673         } else
7674                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7675         I915_WRITE(_CURACNTR, cntl);
7676
7677         intel_crtc->cursor_visible = visible;
7678 }
7679
7680 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7681 {
7682         struct drm_device *dev = crtc->dev;
7683         struct drm_i915_private *dev_priv = dev->dev_private;
7684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7685         int pipe = intel_crtc->pipe;
7686         bool visible = base != 0;
7687
7688         if (intel_crtc->cursor_visible != visible) {
7689                 int16_t width = intel_crtc->cursor_width;
7690                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7691                 if (base) {
7692                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7693                         cntl |= MCURSOR_GAMMA_ENABLE;
7694
7695                         switch (width) {
7696                         case 64:
7697                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7698                                 break;
7699                         case 128:
7700                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7701                                 break;
7702                         case 256:
7703                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7704                                 break;
7705                         default:
7706                                 WARN_ON(1);
7707                                 return;
7708                         }
7709                         cntl |= pipe << 28; /* Connect to correct pipe */
7710                 } else {
7711                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7712                         cntl |= CURSOR_MODE_DISABLE;
7713                 }
7714                 I915_WRITE(CURCNTR(pipe), cntl);
7715
7716                 intel_crtc->cursor_visible = visible;
7717         }
7718         /* and commit changes on next vblank */
7719         POSTING_READ(CURCNTR(pipe));
7720         I915_WRITE(CURBASE(pipe), base);
7721         POSTING_READ(CURBASE(pipe));
7722 }
7723
7724 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7725 {
7726         struct drm_device *dev = crtc->dev;
7727         struct drm_i915_private *dev_priv = dev->dev_private;
7728         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7729         int pipe = intel_crtc->pipe;
7730         bool visible = base != 0;
7731
7732         if (intel_crtc->cursor_visible != visible) {
7733                 int16_t width = intel_crtc->cursor_width;
7734                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7735                 if (base) {
7736                         cntl &= ~CURSOR_MODE;
7737                         cntl |= MCURSOR_GAMMA_ENABLE;
7738                         switch (width) {
7739                         case 64:
7740                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7741                                 break;
7742                         case 128:
7743                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7744                                 break;
7745                         case 256:
7746                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7747                                 break;
7748                         default:
7749                                 WARN_ON(1);
7750                                 return;
7751                         }
7752                 } else {
7753                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7754                         cntl |= CURSOR_MODE_DISABLE;
7755                 }
7756                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7757                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7758                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7759                 }
7760                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7761
7762                 intel_crtc->cursor_visible = visible;
7763         }
7764         /* and commit changes on next vblank */
7765         POSTING_READ(CURCNTR_IVB(pipe));
7766         I915_WRITE(CURBASE_IVB(pipe), base);
7767         POSTING_READ(CURBASE_IVB(pipe));
7768 }
7769
7770 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7771 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7772                                      bool on)
7773 {
7774         struct drm_device *dev = crtc->dev;
7775         struct drm_i915_private *dev_priv = dev->dev_private;
7776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7777         int pipe = intel_crtc->pipe;
7778         int x = intel_crtc->cursor_x;
7779         int y = intel_crtc->cursor_y;
7780         u32 base = 0, pos = 0;
7781         bool visible;
7782
7783         if (on)
7784                 base = intel_crtc->cursor_addr;
7785
7786         if (x >= intel_crtc->config.pipe_src_w)
7787                 base = 0;
7788
7789         if (y >= intel_crtc->config.pipe_src_h)
7790                 base = 0;
7791
7792         if (x < 0) {
7793                 if (x + intel_crtc->cursor_width <= 0)
7794                         base = 0;
7795
7796                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7797                 x = -x;
7798         }
7799         pos |= x << CURSOR_X_SHIFT;
7800
7801         if (y < 0) {
7802                 if (y + intel_crtc->cursor_height <= 0)
7803                         base = 0;
7804
7805                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7806                 y = -y;
7807         }
7808         pos |= y << CURSOR_Y_SHIFT;
7809
7810         visible = base != 0;
7811         if (!visible && !intel_crtc->cursor_visible)
7812                 return;
7813
7814         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7815                 I915_WRITE(CURPOS_IVB(pipe), pos);
7816                 ivb_update_cursor(crtc, base);
7817         } else {
7818                 I915_WRITE(CURPOS(pipe), pos);
7819                 if (IS_845G(dev) || IS_I865G(dev))
7820                         i845_update_cursor(crtc, base);
7821                 else
7822                         i9xx_update_cursor(crtc, base);
7823         }
7824 }
7825
7826 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7827                                  struct drm_file *file,
7828                                  uint32_t handle,
7829                                  uint32_t width, uint32_t height)
7830 {
7831         struct drm_device *dev = crtc->dev;
7832         struct drm_i915_private *dev_priv = dev->dev_private;
7833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7834         struct drm_i915_gem_object *obj;
7835         unsigned old_width;
7836         uint32_t addr;
7837         int ret;
7838
7839         /* if we want to turn off the cursor ignore width and height */
7840         if (!handle) {
7841                 DRM_DEBUG_KMS("cursor off\n");
7842                 addr = 0;
7843                 obj = NULL;
7844                 mutex_lock(&dev->struct_mutex);
7845                 goto finish;
7846         }
7847
7848         /* Check for which cursor types we support */
7849         if (!((width == 64 && height == 64) ||
7850                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7851                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7852                 DRM_DEBUG("Cursor dimension not supported\n");
7853                 return -EINVAL;
7854         }
7855
7856         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7857         if (&obj->base == NULL)
7858                 return -ENOENT;
7859
7860         if (obj->base.size < width * height * 4) {
7861                 DRM_DEBUG_KMS("buffer is to small\n");
7862                 ret = -ENOMEM;
7863                 goto fail;
7864         }
7865
7866         /* we only need to pin inside GTT if cursor is non-phy */
7867         mutex_lock(&dev->struct_mutex);
7868         if (!INTEL_INFO(dev)->cursor_needs_physical) {
7869                 unsigned alignment;
7870
7871                 if (obj->tiling_mode) {
7872                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
7873                         ret = -EINVAL;
7874                         goto fail_locked;
7875                 }
7876
7877                 /* Note that the w/a also requires 2 PTE of padding following
7878                  * the bo. We currently fill all unused PTE with the shadow
7879                  * page and so we should always have valid PTE following the
7880                  * cursor preventing the VT-d warning.
7881                  */
7882                 alignment = 0;
7883                 if (need_vtd_wa(dev))
7884                         alignment = 64*1024;
7885
7886                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7887                 if (ret) {
7888                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7889                         goto fail_locked;
7890                 }
7891
7892                 ret = i915_gem_object_put_fence(obj);
7893                 if (ret) {
7894                         DRM_DEBUG_KMS("failed to release fence for cursor");
7895                         goto fail_unpin;
7896                 }
7897
7898                 addr = i915_gem_obj_ggtt_offset(obj);
7899         } else {
7900                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7901                 ret = i915_gem_attach_phys_object(dev, obj,
7902                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7903                                                   align);
7904                 if (ret) {
7905                         DRM_DEBUG_KMS("failed to attach phys object\n");
7906                         goto fail_locked;
7907                 }
7908                 addr = obj->phys_obj->handle->busaddr;
7909         }
7910
7911         if (IS_GEN2(dev))
7912                 I915_WRITE(CURSIZE, (height << 12) | width);
7913
7914  finish:
7915         if (intel_crtc->cursor_bo) {
7916                 if (INTEL_INFO(dev)->cursor_needs_physical) {
7917                         if (intel_crtc->cursor_bo != obj)
7918                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7919                 } else
7920                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7921                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7922         }
7923
7924         mutex_unlock(&dev->struct_mutex);
7925
7926         old_width = intel_crtc->cursor_width;
7927
7928         intel_crtc->cursor_addr = addr;
7929         intel_crtc->cursor_bo = obj;
7930         intel_crtc->cursor_width = width;
7931         intel_crtc->cursor_height = height;
7932
7933         if (intel_crtc->active) {
7934                 if (old_width != width)
7935                         intel_update_watermarks(crtc);
7936                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7937         }
7938
7939         return 0;
7940 fail_unpin:
7941         i915_gem_object_unpin_from_display_plane(obj);
7942 fail_locked:
7943         mutex_unlock(&dev->struct_mutex);
7944 fail:
7945         drm_gem_object_unreference_unlocked(&obj->base);
7946         return ret;
7947 }
7948
7949 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7950 {
7951         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7952
7953         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7954         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7955
7956         if (intel_crtc->active)
7957                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7958
7959         return 0;
7960 }
7961
7962 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7963                                  u16 *blue, uint32_t start, uint32_t size)
7964 {
7965         int end = (start + size > 256) ? 256 : start + size, i;
7966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7967
7968         for (i = start; i < end; i++) {
7969                 intel_crtc->lut_r[i] = red[i] >> 8;
7970                 intel_crtc->lut_g[i] = green[i] >> 8;
7971                 intel_crtc->lut_b[i] = blue[i] >> 8;
7972         }
7973
7974         intel_crtc_load_lut(crtc);
7975 }
7976
7977 /* VESA 640x480x72Hz mode to set on the pipe */
7978 static struct drm_display_mode load_detect_mode = {
7979         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7980                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7981 };
7982
7983 struct drm_framebuffer *
7984 __intel_framebuffer_create(struct drm_device *dev,
7985                            struct drm_mode_fb_cmd2 *mode_cmd,
7986                            struct drm_i915_gem_object *obj)
7987 {
7988         struct intel_framebuffer *intel_fb;
7989         int ret;
7990
7991         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7992         if (!intel_fb) {
7993                 drm_gem_object_unreference_unlocked(&obj->base);
7994                 return ERR_PTR(-ENOMEM);
7995         }
7996
7997         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7998         if (ret)
7999                 goto err;
8000
8001         return &intel_fb->base;
8002 err:
8003         drm_gem_object_unreference_unlocked(&obj->base);
8004         kfree(intel_fb);
8005
8006         return ERR_PTR(ret);
8007 }
8008
8009 static struct drm_framebuffer *
8010 intel_framebuffer_create(struct drm_device *dev,
8011                          struct drm_mode_fb_cmd2 *mode_cmd,
8012                          struct drm_i915_gem_object *obj)
8013 {
8014         struct drm_framebuffer *fb;
8015         int ret;
8016
8017         ret = i915_mutex_lock_interruptible(dev);
8018         if (ret)
8019                 return ERR_PTR(ret);
8020         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8021         mutex_unlock(&dev->struct_mutex);
8022
8023         return fb;
8024 }
8025
8026 static u32
8027 intel_framebuffer_pitch_for_width(int width, int bpp)
8028 {
8029         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8030         return ALIGN(pitch, 64);
8031 }
8032
8033 static u32
8034 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8035 {
8036         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8037         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8038 }
8039
8040 static struct drm_framebuffer *
8041 intel_framebuffer_create_for_mode(struct drm_device *dev,
8042                                   struct drm_display_mode *mode,
8043                                   int depth, int bpp)
8044 {
8045         struct drm_i915_gem_object *obj;
8046         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8047
8048         obj = i915_gem_alloc_object(dev,
8049                                     intel_framebuffer_size_for_mode(mode, bpp));
8050         if (obj == NULL)
8051                 return ERR_PTR(-ENOMEM);
8052
8053         mode_cmd.width = mode->hdisplay;
8054         mode_cmd.height = mode->vdisplay;
8055         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8056                                                                 bpp);
8057         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8058
8059         return intel_framebuffer_create(dev, &mode_cmd, obj);
8060 }
8061
8062 static struct drm_framebuffer *
8063 mode_fits_in_fbdev(struct drm_device *dev,
8064                    struct drm_display_mode *mode)
8065 {
8066 #ifdef CONFIG_DRM_I915_FBDEV
8067         struct drm_i915_private *dev_priv = dev->dev_private;
8068         struct drm_i915_gem_object *obj;
8069         struct drm_framebuffer *fb;
8070
8071         if (!dev_priv->fbdev)
8072                 return NULL;
8073
8074         if (!dev_priv->fbdev->fb)
8075                 return NULL;
8076
8077         obj = dev_priv->fbdev->fb->obj;
8078         BUG_ON(!obj);
8079
8080         fb = &dev_priv->fbdev->fb->base;
8081         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8082                                                                fb->bits_per_pixel))
8083                 return NULL;
8084
8085         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8086                 return NULL;
8087
8088         return fb;
8089 #else
8090         return NULL;
8091 #endif
8092 }
8093
8094 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8095                                 struct drm_display_mode *mode,
8096                                 struct intel_load_detect_pipe *old)
8097 {
8098         struct intel_crtc *intel_crtc;
8099         struct intel_encoder *intel_encoder =
8100                 intel_attached_encoder(connector);
8101         struct drm_crtc *possible_crtc;
8102         struct drm_encoder *encoder = &intel_encoder->base;
8103         struct drm_crtc *crtc = NULL;
8104         struct drm_device *dev = encoder->dev;
8105         struct drm_framebuffer *fb;
8106         int i = -1;
8107
8108         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8109                       connector->base.id, drm_get_connector_name(connector),
8110                       encoder->base.id, drm_get_encoder_name(encoder));
8111
8112         /*
8113          * Algorithm gets a little messy:
8114          *
8115          *   - if the connector already has an assigned crtc, use it (but make
8116          *     sure it's on first)
8117          *
8118          *   - try to find the first unused crtc that can drive this connector,
8119          *     and use that if we find one
8120          */
8121
8122         /* See if we already have a CRTC for this connector */
8123         if (encoder->crtc) {
8124                 crtc = encoder->crtc;
8125
8126                 mutex_lock(&crtc->mutex);
8127
8128                 old->dpms_mode = connector->dpms;
8129                 old->load_detect_temp = false;
8130
8131                 /* Make sure the crtc and connector are running */
8132                 if (connector->dpms != DRM_MODE_DPMS_ON)
8133                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8134
8135                 return true;
8136         }
8137
8138         /* Find an unused one (if possible) */
8139         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8140                 i++;
8141                 if (!(encoder->possible_crtcs & (1 << i)))
8142                         continue;
8143                 if (!possible_crtc->enabled) {
8144                         crtc = possible_crtc;
8145                         break;
8146                 }
8147         }
8148
8149         /*
8150          * If we didn't find an unused CRTC, don't use any.
8151          */
8152         if (!crtc) {
8153                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8154                 return false;
8155         }
8156
8157         mutex_lock(&crtc->mutex);
8158         intel_encoder->new_crtc = to_intel_crtc(crtc);
8159         to_intel_connector(connector)->new_encoder = intel_encoder;
8160
8161         intel_crtc = to_intel_crtc(crtc);
8162         intel_crtc->new_enabled = true;
8163         intel_crtc->new_config = &intel_crtc->config;
8164         old->dpms_mode = connector->dpms;
8165         old->load_detect_temp = true;
8166         old->release_fb = NULL;
8167
8168         if (!mode)
8169                 mode = &load_detect_mode;
8170
8171         /* We need a framebuffer large enough to accommodate all accesses
8172          * that the plane may generate whilst we perform load detection.
8173          * We can not rely on the fbcon either being present (we get called
8174          * during its initialisation to detect all boot displays, or it may
8175          * not even exist) or that it is large enough to satisfy the
8176          * requested mode.
8177          */
8178         fb = mode_fits_in_fbdev(dev, mode);
8179         if (fb == NULL) {
8180                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8181                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8182                 old->release_fb = fb;
8183         } else
8184                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8185         if (IS_ERR(fb)) {
8186                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8187                 goto fail;
8188         }
8189
8190         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8191                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8192                 if (old->release_fb)
8193                         old->release_fb->funcs->destroy(old->release_fb);
8194                 goto fail;
8195         }
8196
8197         /* let the connector get through one full cycle before testing */
8198         intel_wait_for_vblank(dev, intel_crtc->pipe);
8199         return true;
8200
8201  fail:
8202         intel_crtc->new_enabled = crtc->enabled;
8203         if (intel_crtc->new_enabled)
8204                 intel_crtc->new_config = &intel_crtc->config;
8205         else
8206                 intel_crtc->new_config = NULL;
8207         mutex_unlock(&crtc->mutex);
8208         return false;
8209 }
8210
8211 void intel_release_load_detect_pipe(struct drm_connector *connector,
8212                                     struct intel_load_detect_pipe *old)
8213 {
8214         struct intel_encoder *intel_encoder =
8215                 intel_attached_encoder(connector);
8216         struct drm_encoder *encoder = &intel_encoder->base;
8217         struct drm_crtc *crtc = encoder->crtc;
8218         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8219
8220         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8221                       connector->base.id, drm_get_connector_name(connector),
8222                       encoder->base.id, drm_get_encoder_name(encoder));
8223
8224         if (old->load_detect_temp) {
8225                 to_intel_connector(connector)->new_encoder = NULL;
8226                 intel_encoder->new_crtc = NULL;
8227                 intel_crtc->new_enabled = false;
8228                 intel_crtc->new_config = NULL;
8229                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8230
8231                 if (old->release_fb) {
8232                         drm_framebuffer_unregister_private(old->release_fb);
8233                         drm_framebuffer_unreference(old->release_fb);
8234                 }
8235
8236                 mutex_unlock(&crtc->mutex);
8237                 return;
8238         }
8239
8240         /* Switch crtc and encoder back off if necessary */
8241         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8242                 connector->funcs->dpms(connector, old->dpms_mode);
8243
8244         mutex_unlock(&crtc->mutex);
8245 }
8246
8247 static int i9xx_pll_refclk(struct drm_device *dev,
8248                            const struct intel_crtc_config *pipe_config)
8249 {
8250         struct drm_i915_private *dev_priv = dev->dev_private;
8251         u32 dpll = pipe_config->dpll_hw_state.dpll;
8252
8253         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8254                 return dev_priv->vbt.lvds_ssc_freq;
8255         else if (HAS_PCH_SPLIT(dev))
8256                 return 120000;
8257         else if (!IS_GEN2(dev))
8258                 return 96000;
8259         else
8260                 return 48000;
8261 }
8262
8263 /* Returns the clock of the currently programmed mode of the given pipe. */
8264 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8265                                 struct intel_crtc_config *pipe_config)
8266 {
8267         struct drm_device *dev = crtc->base.dev;
8268         struct drm_i915_private *dev_priv = dev->dev_private;
8269         int pipe = pipe_config->cpu_transcoder;
8270         u32 dpll = pipe_config->dpll_hw_state.dpll;
8271         u32 fp;
8272         intel_clock_t clock;
8273         int refclk = i9xx_pll_refclk(dev, pipe_config);
8274
8275         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8276                 fp = pipe_config->dpll_hw_state.fp0;
8277         else
8278                 fp = pipe_config->dpll_hw_state.fp1;
8279
8280         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8281         if (IS_PINEVIEW(dev)) {
8282                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8283                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8284         } else {
8285                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8286                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8287         }
8288
8289         if (!IS_GEN2(dev)) {
8290                 if (IS_PINEVIEW(dev))
8291                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8292                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8293                 else
8294                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8295                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8296
8297                 switch (dpll & DPLL_MODE_MASK) {
8298                 case DPLLB_MODE_DAC_SERIAL:
8299                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8300                                 5 : 10;
8301                         break;
8302                 case DPLLB_MODE_LVDS:
8303                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8304                                 7 : 14;
8305                         break;
8306                 default:
8307                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8308                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8309                         return;
8310                 }
8311
8312                 if (IS_PINEVIEW(dev))
8313                         pineview_clock(refclk, &clock);
8314                 else
8315                         i9xx_clock(refclk, &clock);
8316         } else {
8317                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8318                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8319
8320                 if (is_lvds) {
8321                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8322                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8323
8324                         if (lvds & LVDS_CLKB_POWER_UP)
8325                                 clock.p2 = 7;
8326                         else
8327                                 clock.p2 = 14;
8328                 } else {
8329                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8330                                 clock.p1 = 2;
8331                         else {
8332                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8333                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8334                         }
8335                         if (dpll & PLL_P2_DIVIDE_BY_4)
8336                                 clock.p2 = 4;
8337                         else
8338                                 clock.p2 = 2;
8339                 }
8340
8341                 i9xx_clock(refclk, &clock);
8342         }
8343
8344         /*
8345          * This value includes pixel_multiplier. We will use
8346          * port_clock to compute adjusted_mode.crtc_clock in the
8347          * encoder's get_config() function.
8348          */
8349         pipe_config->port_clock = clock.dot;
8350 }
8351
8352 int intel_dotclock_calculate(int link_freq,
8353                              const struct intel_link_m_n *m_n)
8354 {
8355         /*
8356          * The calculation for the data clock is:
8357          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8358          * But we want to avoid losing precison if possible, so:
8359          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8360          *
8361          * and the link clock is simpler:
8362          * link_clock = (m * link_clock) / n
8363          */
8364
8365         if (!m_n->link_n)
8366                 return 0;
8367
8368         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8369 }
8370
8371 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8372                                    struct intel_crtc_config *pipe_config)
8373 {
8374         struct drm_device *dev = crtc->base.dev;
8375
8376         /* read out port_clock from the DPLL */
8377         i9xx_crtc_clock_get(crtc, pipe_config);
8378
8379         /*
8380          * This value does not include pixel_multiplier.
8381          * We will check that port_clock and adjusted_mode.crtc_clock
8382          * agree once we know their relationship in the encoder's
8383          * get_config() function.
8384          */
8385         pipe_config->adjusted_mode.crtc_clock =
8386                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8387                                          &pipe_config->fdi_m_n);
8388 }
8389
8390 /** Returns the currently programmed mode of the given pipe. */
8391 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8392                                              struct drm_crtc *crtc)
8393 {
8394         struct drm_i915_private *dev_priv = dev->dev_private;
8395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8396         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8397         struct drm_display_mode *mode;
8398         struct intel_crtc_config pipe_config;
8399         int htot = I915_READ(HTOTAL(cpu_transcoder));
8400         int hsync = I915_READ(HSYNC(cpu_transcoder));
8401         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8402         int vsync = I915_READ(VSYNC(cpu_transcoder));
8403         enum pipe pipe = intel_crtc->pipe;
8404
8405         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8406         if (!mode)
8407                 return NULL;
8408
8409         /*
8410          * Construct a pipe_config sufficient for getting the clock info
8411          * back out of crtc_clock_get.
8412          *
8413          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8414          * to use a real value here instead.
8415          */
8416         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8417         pipe_config.pixel_multiplier = 1;
8418         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8419         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8420         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8421         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8422
8423         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8424         mode->hdisplay = (htot & 0xffff) + 1;
8425         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8426         mode->hsync_start = (hsync & 0xffff) + 1;
8427         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8428         mode->vdisplay = (vtot & 0xffff) + 1;
8429         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8430         mode->vsync_start = (vsync & 0xffff) + 1;
8431         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8432
8433         drm_mode_set_name(mode);
8434
8435         return mode;
8436 }
8437
8438 static void intel_increase_pllclock(struct drm_crtc *crtc)
8439 {
8440         struct drm_device *dev = crtc->dev;
8441         struct drm_i915_private *dev_priv = dev->dev_private;
8442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8443         int pipe = intel_crtc->pipe;
8444         int dpll_reg = DPLL(pipe);
8445         int dpll;
8446
8447         if (HAS_PCH_SPLIT(dev))
8448                 return;
8449
8450         if (!dev_priv->lvds_downclock_avail)
8451                 return;
8452
8453         dpll = I915_READ(dpll_reg);
8454         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8455                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8456
8457                 assert_panel_unlocked(dev_priv, pipe);
8458
8459                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8460                 I915_WRITE(dpll_reg, dpll);
8461                 intel_wait_for_vblank(dev, pipe);
8462
8463                 dpll = I915_READ(dpll_reg);
8464                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8465                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8466         }
8467 }
8468
8469 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8470 {
8471         struct drm_device *dev = crtc->dev;
8472         struct drm_i915_private *dev_priv = dev->dev_private;
8473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8474
8475         if (HAS_PCH_SPLIT(dev))
8476                 return;
8477
8478         if (!dev_priv->lvds_downclock_avail)
8479                 return;
8480
8481         /*
8482          * Since this is called by a timer, we should never get here in
8483          * the manual case.
8484          */
8485         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8486                 int pipe = intel_crtc->pipe;
8487                 int dpll_reg = DPLL(pipe);
8488                 int dpll;
8489
8490                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8491
8492                 assert_panel_unlocked(dev_priv, pipe);
8493
8494                 dpll = I915_READ(dpll_reg);
8495                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8496                 I915_WRITE(dpll_reg, dpll);
8497                 intel_wait_for_vblank(dev, pipe);
8498                 dpll = I915_READ(dpll_reg);
8499                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8500                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8501         }
8502
8503 }
8504
8505 void intel_mark_busy(struct drm_device *dev)
8506 {
8507         struct drm_i915_private *dev_priv = dev->dev_private;
8508
8509         if (dev_priv->mm.busy)
8510                 return;
8511
8512         intel_runtime_pm_get(dev_priv);
8513         i915_update_gfx_val(dev_priv);
8514         dev_priv->mm.busy = true;
8515 }
8516
8517 void intel_mark_idle(struct drm_device *dev)
8518 {
8519         struct drm_i915_private *dev_priv = dev->dev_private;
8520         struct drm_crtc *crtc;
8521
8522         if (!dev_priv->mm.busy)
8523                 return;
8524
8525         dev_priv->mm.busy = false;
8526
8527         if (!i915.powersave)
8528                 goto out;
8529
8530         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8531                 if (!crtc->primary->fb)
8532                         continue;
8533
8534                 intel_decrease_pllclock(crtc);
8535         }
8536
8537         if (INTEL_INFO(dev)->gen >= 6)
8538                 gen6_rps_idle(dev->dev_private);
8539
8540 out:
8541         intel_runtime_pm_put(dev_priv);
8542 }
8543
8544 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8545                         struct intel_ring_buffer *ring)
8546 {
8547         struct drm_device *dev = obj->base.dev;
8548         struct drm_crtc *crtc;
8549
8550         if (!i915.powersave)
8551                 return;
8552
8553         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8554                 if (!crtc->primary->fb)
8555                         continue;
8556
8557                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8558                         continue;
8559
8560                 intel_increase_pllclock(crtc);
8561                 if (ring && intel_fbc_enabled(dev))
8562                         ring->fbc_dirty = true;
8563         }
8564 }
8565
8566 static void intel_crtc_destroy(struct drm_crtc *crtc)
8567 {
8568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8569         struct drm_device *dev = crtc->dev;
8570         struct intel_unpin_work *work;
8571         unsigned long flags;
8572
8573         spin_lock_irqsave(&dev->event_lock, flags);
8574         work = intel_crtc->unpin_work;
8575         intel_crtc->unpin_work = NULL;
8576         spin_unlock_irqrestore(&dev->event_lock, flags);
8577
8578         if (work) {
8579                 cancel_work_sync(&work->work);
8580                 kfree(work);
8581         }
8582
8583         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8584
8585         drm_crtc_cleanup(crtc);
8586
8587         kfree(intel_crtc);
8588 }
8589
8590 static void intel_unpin_work_fn(struct work_struct *__work)
8591 {
8592         struct intel_unpin_work *work =
8593                 container_of(__work, struct intel_unpin_work, work);
8594         struct drm_device *dev = work->crtc->dev;
8595
8596         mutex_lock(&dev->struct_mutex);
8597         intel_unpin_fb_obj(work->old_fb_obj);
8598         drm_gem_object_unreference(&work->pending_flip_obj->base);
8599         drm_gem_object_unreference(&work->old_fb_obj->base);
8600
8601         intel_update_fbc(dev);
8602         mutex_unlock(&dev->struct_mutex);
8603
8604         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8605         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8606
8607         kfree(work);
8608 }
8609
8610 static void do_intel_finish_page_flip(struct drm_device *dev,
8611                                       struct drm_crtc *crtc)
8612 {
8613         struct drm_i915_private *dev_priv = dev->dev_private;
8614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8615         struct intel_unpin_work *work;
8616         unsigned long flags;
8617
8618         /* Ignore early vblank irqs */
8619         if (intel_crtc == NULL)
8620                 return;
8621
8622         spin_lock_irqsave(&dev->event_lock, flags);
8623         work = intel_crtc->unpin_work;
8624
8625         /* Ensure we don't miss a work->pending update ... */
8626         smp_rmb();
8627
8628         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8629                 spin_unlock_irqrestore(&dev->event_lock, flags);
8630                 return;
8631         }
8632
8633         /* and that the unpin work is consistent wrt ->pending. */
8634         smp_rmb();
8635
8636         intel_crtc->unpin_work = NULL;
8637
8638         if (work->event)
8639                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8640
8641         drm_vblank_put(dev, intel_crtc->pipe);
8642
8643         spin_unlock_irqrestore(&dev->event_lock, flags);
8644
8645         wake_up_all(&dev_priv->pending_flip_queue);
8646
8647         queue_work(dev_priv->wq, &work->work);
8648
8649         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8650 }
8651
8652 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8653 {
8654         struct drm_i915_private *dev_priv = dev->dev_private;
8655         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8656
8657         do_intel_finish_page_flip(dev, crtc);
8658 }
8659
8660 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8661 {
8662         struct drm_i915_private *dev_priv = dev->dev_private;
8663         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8664
8665         do_intel_finish_page_flip(dev, crtc);
8666 }
8667
8668 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8669 {
8670         struct drm_i915_private *dev_priv = dev->dev_private;
8671         struct intel_crtc *intel_crtc =
8672                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8673         unsigned long flags;
8674
8675         /* NB: An MMIO update of the plane base pointer will also
8676          * generate a page-flip completion irq, i.e. every modeset
8677          * is also accompanied by a spurious intel_prepare_page_flip().
8678          */
8679         spin_lock_irqsave(&dev->event_lock, flags);
8680         if (intel_crtc->unpin_work)
8681                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8682         spin_unlock_irqrestore(&dev->event_lock, flags);
8683 }
8684
8685 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8686 {
8687         /* Ensure that the work item is consistent when activating it ... */
8688         smp_wmb();
8689         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8690         /* and that it is marked active as soon as the irq could fire. */
8691         smp_wmb();
8692 }
8693
8694 static int intel_gen2_queue_flip(struct drm_device *dev,
8695                                  struct drm_crtc *crtc,
8696                                  struct drm_framebuffer *fb,
8697                                  struct drm_i915_gem_object *obj,
8698                                  uint32_t flags)
8699 {
8700         struct drm_i915_private *dev_priv = dev->dev_private;
8701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8702         u32 flip_mask;
8703         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8704         int ret;
8705
8706         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8707         if (ret)
8708                 goto err;
8709
8710         ret = intel_ring_begin(ring, 6);
8711         if (ret)
8712                 goto err_unpin;
8713
8714         /* Can't queue multiple flips, so wait for the previous
8715          * one to finish before executing the next.
8716          */
8717         if (intel_crtc->plane)
8718                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8719         else
8720                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8721         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8722         intel_ring_emit(ring, MI_NOOP);
8723         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8724                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8725         intel_ring_emit(ring, fb->pitches[0]);
8726         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8727         intel_ring_emit(ring, 0); /* aux display base address, unused */
8728
8729         intel_mark_page_flip_active(intel_crtc);
8730         __intel_ring_advance(ring);
8731         return 0;
8732
8733 err_unpin:
8734         intel_unpin_fb_obj(obj);
8735 err:
8736         return ret;
8737 }
8738
8739 static int intel_gen3_queue_flip(struct drm_device *dev,
8740                                  struct drm_crtc *crtc,
8741                                  struct drm_framebuffer *fb,
8742                                  struct drm_i915_gem_object *obj,
8743                                  uint32_t flags)
8744 {
8745         struct drm_i915_private *dev_priv = dev->dev_private;
8746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8747         u32 flip_mask;
8748         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8749         int ret;
8750
8751         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8752         if (ret)
8753                 goto err;
8754
8755         ret = intel_ring_begin(ring, 6);
8756         if (ret)
8757                 goto err_unpin;
8758
8759         if (intel_crtc->plane)
8760                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8761         else
8762                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8763         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8764         intel_ring_emit(ring, MI_NOOP);
8765         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8766                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8767         intel_ring_emit(ring, fb->pitches[0]);
8768         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8769         intel_ring_emit(ring, MI_NOOP);
8770
8771         intel_mark_page_flip_active(intel_crtc);
8772         __intel_ring_advance(ring);
8773         return 0;
8774
8775 err_unpin:
8776         intel_unpin_fb_obj(obj);
8777 err:
8778         return ret;
8779 }
8780
8781 static int intel_gen4_queue_flip(struct drm_device *dev,
8782                                  struct drm_crtc *crtc,
8783                                  struct drm_framebuffer *fb,
8784                                  struct drm_i915_gem_object *obj,
8785                                  uint32_t flags)
8786 {
8787         struct drm_i915_private *dev_priv = dev->dev_private;
8788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8789         uint32_t pf, pipesrc;
8790         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8791         int ret;
8792
8793         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8794         if (ret)
8795                 goto err;
8796
8797         ret = intel_ring_begin(ring, 4);
8798         if (ret)
8799                 goto err_unpin;
8800
8801         /* i965+ uses the linear or tiled offsets from the
8802          * Display Registers (which do not change across a page-flip)
8803          * so we need only reprogram the base address.
8804          */
8805         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8806                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8807         intel_ring_emit(ring, fb->pitches[0]);
8808         intel_ring_emit(ring,
8809                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8810                         obj->tiling_mode);
8811
8812         /* XXX Enabling the panel-fitter across page-flip is so far
8813          * untested on non-native modes, so ignore it for now.
8814          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8815          */
8816         pf = 0;
8817         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8818         intel_ring_emit(ring, pf | pipesrc);
8819
8820         intel_mark_page_flip_active(intel_crtc);
8821         __intel_ring_advance(ring);
8822         return 0;
8823
8824 err_unpin:
8825         intel_unpin_fb_obj(obj);
8826 err:
8827         return ret;
8828 }
8829
8830 static int intel_gen6_queue_flip(struct drm_device *dev,
8831                                  struct drm_crtc *crtc,
8832                                  struct drm_framebuffer *fb,
8833                                  struct drm_i915_gem_object *obj,
8834                                  uint32_t flags)
8835 {
8836         struct drm_i915_private *dev_priv = dev->dev_private;
8837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8838         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8839         uint32_t pf, pipesrc;
8840         int ret;
8841
8842         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8843         if (ret)
8844                 goto err;
8845
8846         ret = intel_ring_begin(ring, 4);
8847         if (ret)
8848                 goto err_unpin;
8849
8850         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8851                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8852         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8853         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8854
8855         /* Contrary to the suggestions in the documentation,
8856          * "Enable Panel Fitter" does not seem to be required when page
8857          * flipping with a non-native mode, and worse causes a normal
8858          * modeset to fail.
8859          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8860          */
8861         pf = 0;
8862         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8863         intel_ring_emit(ring, pf | pipesrc);
8864
8865         intel_mark_page_flip_active(intel_crtc);
8866         __intel_ring_advance(ring);
8867         return 0;
8868
8869 err_unpin:
8870         intel_unpin_fb_obj(obj);
8871 err:
8872         return ret;
8873 }
8874
8875 static int intel_gen7_queue_flip(struct drm_device *dev,
8876                                  struct drm_crtc *crtc,
8877                                  struct drm_framebuffer *fb,
8878                                  struct drm_i915_gem_object *obj,
8879                                  uint32_t flags)
8880 {
8881         struct drm_i915_private *dev_priv = dev->dev_private;
8882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8883         struct intel_ring_buffer *ring;
8884         uint32_t plane_bit = 0;
8885         int len, ret;
8886
8887         ring = obj->ring;
8888         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8889                 ring = &dev_priv->ring[BCS];
8890
8891         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8892         if (ret)
8893                 goto err;
8894
8895         switch(intel_crtc->plane) {
8896         case PLANE_A:
8897                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8898                 break;
8899         case PLANE_B:
8900                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8901                 break;
8902         case PLANE_C:
8903                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8904                 break;
8905         default:
8906                 WARN_ONCE(1, "unknown plane in flip command\n");
8907                 ret = -ENODEV;
8908                 goto err_unpin;
8909         }
8910
8911         len = 4;
8912         if (ring->id == RCS) {
8913                 len += 6;
8914                 /*
8915                  * On Gen 8, SRM is now taking an extra dword to accommodate
8916                  * 48bits addresses, and we need a NOOP for the batch size to
8917                  * stay even.
8918                  */
8919                 if (IS_GEN8(dev))
8920                         len += 2;
8921         }
8922
8923         /*
8924          * BSpec MI_DISPLAY_FLIP for IVB:
8925          * "The full packet must be contained within the same cache line."
8926          *
8927          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8928          * cacheline, if we ever start emitting more commands before
8929          * the MI_DISPLAY_FLIP we may need to first emit everything else,
8930          * then do the cacheline alignment, and finally emit the
8931          * MI_DISPLAY_FLIP.
8932          */
8933         ret = intel_ring_cacheline_align(ring);
8934         if (ret)
8935                 goto err_unpin;
8936
8937         ret = intel_ring_begin(ring, len);
8938         if (ret)
8939                 goto err_unpin;
8940
8941         /* Unmask the flip-done completion message. Note that the bspec says that
8942          * we should do this for both the BCS and RCS, and that we must not unmask
8943          * more than one flip event at any time (or ensure that one flip message
8944          * can be sent by waiting for flip-done prior to queueing new flips).
8945          * Experimentation says that BCS works despite DERRMR masking all
8946          * flip-done completion events and that unmasking all planes at once
8947          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8948          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8949          */
8950         if (ring->id == RCS) {
8951                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8952                 intel_ring_emit(ring, DERRMR);
8953                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8954                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8955                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8956                 if (IS_GEN8(dev))
8957                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
8958                                               MI_SRM_LRM_GLOBAL_GTT);
8959                 else
8960                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8961                                               MI_SRM_LRM_GLOBAL_GTT);
8962                 intel_ring_emit(ring, DERRMR);
8963                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8964                 if (IS_GEN8(dev)) {
8965                         intel_ring_emit(ring, 0);
8966                         intel_ring_emit(ring, MI_NOOP);
8967                 }
8968         }
8969
8970         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8971         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8972         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8973         intel_ring_emit(ring, (MI_NOOP));
8974
8975         intel_mark_page_flip_active(intel_crtc);
8976         __intel_ring_advance(ring);
8977         return 0;
8978
8979 err_unpin:
8980         intel_unpin_fb_obj(obj);
8981 err:
8982         return ret;
8983 }
8984
8985 static int intel_default_queue_flip(struct drm_device *dev,
8986                                     struct drm_crtc *crtc,
8987                                     struct drm_framebuffer *fb,
8988                                     struct drm_i915_gem_object *obj,
8989                                     uint32_t flags)
8990 {
8991         return -ENODEV;
8992 }
8993
8994 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8995                                 struct drm_framebuffer *fb,
8996                                 struct drm_pending_vblank_event *event,
8997                                 uint32_t page_flip_flags)
8998 {
8999         struct drm_device *dev = crtc->dev;
9000         struct drm_i915_private *dev_priv = dev->dev_private;
9001         struct drm_framebuffer *old_fb = crtc->primary->fb;
9002         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9004         struct intel_unpin_work *work;
9005         unsigned long flags;
9006         int ret;
9007
9008         /* Can't change pixel format via MI display flips. */
9009         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9010                 return -EINVAL;
9011
9012         /*
9013          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9014          * Note that pitch changes could also affect these register.
9015          */
9016         if (INTEL_INFO(dev)->gen > 3 &&
9017             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9018              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9019                 return -EINVAL;
9020
9021         if (i915_terminally_wedged(&dev_priv->gpu_error))
9022                 goto out_hang;
9023
9024         work = kzalloc(sizeof(*work), GFP_KERNEL);
9025         if (work == NULL)
9026                 return -ENOMEM;
9027
9028         work->event = event;
9029         work->crtc = crtc;
9030         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9031         INIT_WORK(&work->work, intel_unpin_work_fn);
9032
9033         ret = drm_vblank_get(dev, intel_crtc->pipe);
9034         if (ret)
9035                 goto free_work;
9036
9037         /* We borrow the event spin lock for protecting unpin_work */
9038         spin_lock_irqsave(&dev->event_lock, flags);
9039         if (intel_crtc->unpin_work) {
9040                 spin_unlock_irqrestore(&dev->event_lock, flags);
9041                 kfree(work);
9042                 drm_vblank_put(dev, intel_crtc->pipe);
9043
9044                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9045                 return -EBUSY;
9046         }
9047         intel_crtc->unpin_work = work;
9048         spin_unlock_irqrestore(&dev->event_lock, flags);
9049
9050         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9051                 flush_workqueue(dev_priv->wq);
9052
9053         ret = i915_mutex_lock_interruptible(dev);
9054         if (ret)
9055                 goto cleanup;
9056
9057         /* Reference the objects for the scheduled work. */
9058         drm_gem_object_reference(&work->old_fb_obj->base);
9059         drm_gem_object_reference(&obj->base);
9060
9061         crtc->primary->fb = fb;
9062
9063         work->pending_flip_obj = obj;
9064
9065         work->enable_stall_check = true;
9066
9067         atomic_inc(&intel_crtc->unpin_work_count);
9068         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9069
9070         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
9071         if (ret)
9072                 goto cleanup_pending;
9073
9074         intel_disable_fbc(dev);
9075         intel_mark_fb_busy(obj, NULL);
9076         mutex_unlock(&dev->struct_mutex);
9077
9078         trace_i915_flip_request(intel_crtc->plane, obj);
9079
9080         return 0;
9081
9082 cleanup_pending:
9083         atomic_dec(&intel_crtc->unpin_work_count);
9084         crtc->primary->fb = old_fb;
9085         drm_gem_object_unreference(&work->old_fb_obj->base);
9086         drm_gem_object_unreference(&obj->base);
9087         mutex_unlock(&dev->struct_mutex);
9088
9089 cleanup:
9090         spin_lock_irqsave(&dev->event_lock, flags);
9091         intel_crtc->unpin_work = NULL;
9092         spin_unlock_irqrestore(&dev->event_lock, flags);
9093
9094         drm_vblank_put(dev, intel_crtc->pipe);
9095 free_work:
9096         kfree(work);
9097
9098         if (ret == -EIO) {
9099 out_hang:
9100                 intel_crtc_wait_for_pending_flips(crtc);
9101                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9102                 if (ret == 0 && event)
9103                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9104         }
9105         return ret;
9106 }
9107
9108 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9109         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9110         .load_lut = intel_crtc_load_lut,
9111 };
9112
9113 /**
9114  * intel_modeset_update_staged_output_state
9115  *
9116  * Updates the staged output configuration state, e.g. after we've read out the
9117  * current hw state.
9118  */
9119 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9120 {
9121         struct intel_crtc *crtc;
9122         struct intel_encoder *encoder;
9123         struct intel_connector *connector;
9124
9125         list_for_each_entry(connector, &dev->mode_config.connector_list,
9126                             base.head) {
9127                 connector->new_encoder =
9128                         to_intel_encoder(connector->base.encoder);
9129         }
9130
9131         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9132                             base.head) {
9133                 encoder->new_crtc =
9134                         to_intel_crtc(encoder->base.crtc);
9135         }
9136
9137         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9138                             base.head) {
9139                 crtc->new_enabled = crtc->base.enabled;
9140
9141                 if (crtc->new_enabled)
9142                         crtc->new_config = &crtc->config;
9143                 else
9144                         crtc->new_config = NULL;
9145         }
9146 }
9147
9148 /**
9149  * intel_modeset_commit_output_state
9150  *
9151  * This function copies the stage display pipe configuration to the real one.
9152  */
9153 static void intel_modeset_commit_output_state(struct drm_device *dev)
9154 {
9155         struct intel_crtc *crtc;
9156         struct intel_encoder *encoder;
9157         struct intel_connector *connector;
9158
9159         list_for_each_entry(connector, &dev->mode_config.connector_list,
9160                             base.head) {
9161                 connector->base.encoder = &connector->new_encoder->base;
9162         }
9163
9164         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9165                             base.head) {
9166                 encoder->base.crtc = &encoder->new_crtc->base;
9167         }
9168
9169         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9170                             base.head) {
9171                 crtc->base.enabled = crtc->new_enabled;
9172         }
9173 }
9174
9175 static void
9176 connected_sink_compute_bpp(struct intel_connector * connector,
9177                            struct intel_crtc_config *pipe_config)
9178 {
9179         int bpp = pipe_config->pipe_bpp;
9180
9181         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9182                 connector->base.base.id,
9183                 drm_get_connector_name(&connector->base));
9184
9185         /* Don't use an invalid EDID bpc value */
9186         if (connector->base.display_info.bpc &&
9187             connector->base.display_info.bpc * 3 < bpp) {
9188                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9189                               bpp, connector->base.display_info.bpc*3);
9190                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9191         }
9192
9193         /* Clamp bpp to 8 on screens without EDID 1.4 */
9194         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9195                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9196                               bpp);
9197                 pipe_config->pipe_bpp = 24;
9198         }
9199 }
9200
9201 static int
9202 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9203                           struct drm_framebuffer *fb,
9204                           struct intel_crtc_config *pipe_config)
9205 {
9206         struct drm_device *dev = crtc->base.dev;
9207         struct intel_connector *connector;
9208         int bpp;
9209
9210         switch (fb->pixel_format) {
9211         case DRM_FORMAT_C8:
9212                 bpp = 8*3; /* since we go through a colormap */
9213                 break;
9214         case DRM_FORMAT_XRGB1555:
9215         case DRM_FORMAT_ARGB1555:
9216                 /* checked in intel_framebuffer_init already */
9217                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9218                         return -EINVAL;
9219         case DRM_FORMAT_RGB565:
9220                 bpp = 6*3; /* min is 18bpp */
9221                 break;
9222         case DRM_FORMAT_XBGR8888:
9223         case DRM_FORMAT_ABGR8888:
9224                 /* checked in intel_framebuffer_init already */
9225                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9226                         return -EINVAL;
9227         case DRM_FORMAT_XRGB8888:
9228         case DRM_FORMAT_ARGB8888:
9229                 bpp = 8*3;
9230                 break;
9231         case DRM_FORMAT_XRGB2101010:
9232         case DRM_FORMAT_ARGB2101010:
9233         case DRM_FORMAT_XBGR2101010:
9234         case DRM_FORMAT_ABGR2101010:
9235                 /* checked in intel_framebuffer_init already */
9236                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9237                         return -EINVAL;
9238                 bpp = 10*3;
9239                 break;
9240         /* TODO: gen4+ supports 16 bpc floating point, too. */
9241         default:
9242                 DRM_DEBUG_KMS("unsupported depth\n");
9243                 return -EINVAL;
9244         }
9245
9246         pipe_config->pipe_bpp = bpp;
9247
9248         /* Clamp display bpp to EDID value */
9249         list_for_each_entry(connector, &dev->mode_config.connector_list,
9250                             base.head) {
9251                 if (!connector->new_encoder ||
9252                     connector->new_encoder->new_crtc != crtc)
9253                         continue;
9254
9255                 connected_sink_compute_bpp(connector, pipe_config);
9256         }
9257
9258         return bpp;
9259 }
9260
9261 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9262 {
9263         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9264                         "type: 0x%x flags: 0x%x\n",
9265                 mode->crtc_clock,
9266                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9267                 mode->crtc_hsync_end, mode->crtc_htotal,
9268                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9269                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9270 }
9271
9272 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9273                                    struct intel_crtc_config *pipe_config,
9274                                    const char *context)
9275 {
9276         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9277                       context, pipe_name(crtc->pipe));
9278
9279         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9280         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9281                       pipe_config->pipe_bpp, pipe_config->dither);
9282         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9283                       pipe_config->has_pch_encoder,
9284                       pipe_config->fdi_lanes,
9285                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9286                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9287                       pipe_config->fdi_m_n.tu);
9288         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9289                       pipe_config->has_dp_encoder,
9290                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9291                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9292                       pipe_config->dp_m_n.tu);
9293         DRM_DEBUG_KMS("requested mode:\n");
9294         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9295         DRM_DEBUG_KMS("adjusted mode:\n");
9296         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9297         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9298         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9299         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9300                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9301         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9302                       pipe_config->gmch_pfit.control,
9303                       pipe_config->gmch_pfit.pgm_ratios,
9304                       pipe_config->gmch_pfit.lvds_border_bits);
9305         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9306                       pipe_config->pch_pfit.pos,
9307                       pipe_config->pch_pfit.size,
9308                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9309         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9310         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9311 }
9312
9313 static bool encoders_cloneable(const struct intel_encoder *a,
9314                                const struct intel_encoder *b)
9315 {
9316         /* masks could be asymmetric, so check both ways */
9317         return a == b || (a->cloneable & (1 << b->type) &&
9318                           b->cloneable & (1 << a->type));
9319 }
9320
9321 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9322                                          struct intel_encoder *encoder)
9323 {
9324         struct drm_device *dev = crtc->base.dev;
9325         struct intel_encoder *source_encoder;
9326
9327         list_for_each_entry(source_encoder,
9328                             &dev->mode_config.encoder_list, base.head) {
9329                 if (source_encoder->new_crtc != crtc)
9330                         continue;
9331
9332                 if (!encoders_cloneable(encoder, source_encoder))
9333                         return false;
9334         }
9335
9336         return true;
9337 }
9338
9339 static bool check_encoder_cloning(struct intel_crtc *crtc)
9340 {
9341         struct drm_device *dev = crtc->base.dev;
9342         struct intel_encoder *encoder;
9343
9344         list_for_each_entry(encoder,
9345                             &dev->mode_config.encoder_list, base.head) {
9346                 if (encoder->new_crtc != crtc)
9347                         continue;
9348
9349                 if (!check_single_encoder_cloning(crtc, encoder))
9350                         return false;
9351         }
9352
9353         return true;
9354 }
9355
9356 static struct intel_crtc_config *
9357 intel_modeset_pipe_config(struct drm_crtc *crtc,
9358                           struct drm_framebuffer *fb,
9359                           struct drm_display_mode *mode)
9360 {
9361         struct drm_device *dev = crtc->dev;
9362         struct intel_encoder *encoder;
9363         struct intel_crtc_config *pipe_config;
9364         int plane_bpp, ret = -EINVAL;
9365         bool retry = true;
9366
9367         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9368                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9369                 return ERR_PTR(-EINVAL);
9370         }
9371
9372         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9373         if (!pipe_config)
9374                 return ERR_PTR(-ENOMEM);
9375
9376         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9377         drm_mode_copy(&pipe_config->requested_mode, mode);
9378
9379         pipe_config->cpu_transcoder =
9380                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9381         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9382
9383         /*
9384          * Sanitize sync polarity flags based on requested ones. If neither
9385          * positive or negative polarity is requested, treat this as meaning
9386          * negative polarity.
9387          */
9388         if (!(pipe_config->adjusted_mode.flags &
9389               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9390                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9391
9392         if (!(pipe_config->adjusted_mode.flags &
9393               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9394                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9395
9396         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9397          * plane pixel format and any sink constraints into account. Returns the
9398          * source plane bpp so that dithering can be selected on mismatches
9399          * after encoders and crtc also have had their say. */
9400         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9401                                               fb, pipe_config);
9402         if (plane_bpp < 0)
9403                 goto fail;
9404
9405         /*
9406          * Determine the real pipe dimensions. Note that stereo modes can
9407          * increase the actual pipe size due to the frame doubling and
9408          * insertion of additional space for blanks between the frame. This
9409          * is stored in the crtc timings. We use the requested mode to do this
9410          * computation to clearly distinguish it from the adjusted mode, which
9411          * can be changed by the connectors in the below retry loop.
9412          */
9413         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9414         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9415         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9416
9417 encoder_retry:
9418         /* Ensure the port clock defaults are reset when retrying. */
9419         pipe_config->port_clock = 0;
9420         pipe_config->pixel_multiplier = 1;
9421
9422         /* Fill in default crtc timings, allow encoders to overwrite them. */
9423         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9424
9425         /* Pass our mode to the connectors and the CRTC to give them a chance to
9426          * adjust it according to limitations or connector properties, and also
9427          * a chance to reject the mode entirely.
9428          */
9429         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9430                             base.head) {
9431
9432                 if (&encoder->new_crtc->base != crtc)
9433                         continue;
9434
9435                 if (!(encoder->compute_config(encoder, pipe_config))) {
9436                         DRM_DEBUG_KMS("Encoder config failure\n");
9437                         goto fail;
9438                 }
9439         }
9440
9441         /* Set default port clock if not overwritten by the encoder. Needs to be
9442          * done afterwards in case the encoder adjusts the mode. */
9443         if (!pipe_config->port_clock)
9444                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9445                         * pipe_config->pixel_multiplier;
9446
9447         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9448         if (ret < 0) {
9449                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9450                 goto fail;
9451         }
9452
9453         if (ret == RETRY) {
9454                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9455                         ret = -EINVAL;
9456                         goto fail;
9457                 }
9458
9459                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9460                 retry = false;
9461                 goto encoder_retry;
9462         }
9463
9464         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9465         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9466                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9467
9468         return pipe_config;
9469 fail:
9470         kfree(pipe_config);
9471         return ERR_PTR(ret);
9472 }
9473
9474 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9475  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9476 static void
9477 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9478                              unsigned *prepare_pipes, unsigned *disable_pipes)
9479 {
9480         struct intel_crtc *intel_crtc;
9481         struct drm_device *dev = crtc->dev;
9482         struct intel_encoder *encoder;
9483         struct intel_connector *connector;
9484         struct drm_crtc *tmp_crtc;
9485
9486         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9487
9488         /* Check which crtcs have changed outputs connected to them, these need
9489          * to be part of the prepare_pipes mask. We don't (yet) support global
9490          * modeset across multiple crtcs, so modeset_pipes will only have one
9491          * bit set at most. */
9492         list_for_each_entry(connector, &dev->mode_config.connector_list,
9493                             base.head) {
9494                 if (connector->base.encoder == &connector->new_encoder->base)
9495                         continue;
9496
9497                 if (connector->base.encoder) {
9498                         tmp_crtc = connector->base.encoder->crtc;
9499
9500                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9501                 }
9502
9503                 if (connector->new_encoder)
9504                         *prepare_pipes |=
9505                                 1 << connector->new_encoder->new_crtc->pipe;
9506         }
9507
9508         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9509                             base.head) {
9510                 if (encoder->base.crtc == &encoder->new_crtc->base)
9511                         continue;
9512
9513                 if (encoder->base.crtc) {
9514                         tmp_crtc = encoder->base.crtc;
9515
9516                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9517                 }
9518
9519                 if (encoder->new_crtc)
9520                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9521         }
9522
9523         /* Check for pipes that will be enabled/disabled ... */
9524         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9525                             base.head) {
9526                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9527                         continue;
9528
9529                 if (!intel_crtc->new_enabled)
9530                         *disable_pipes |= 1 << intel_crtc->pipe;
9531                 else
9532                         *prepare_pipes |= 1 << intel_crtc->pipe;
9533         }
9534
9535
9536         /* set_mode is also used to update properties on life display pipes. */
9537         intel_crtc = to_intel_crtc(crtc);
9538         if (intel_crtc->new_enabled)
9539                 *prepare_pipes |= 1 << intel_crtc->pipe;
9540
9541         /*
9542          * For simplicity do a full modeset on any pipe where the output routing
9543          * changed. We could be more clever, but that would require us to be
9544          * more careful with calling the relevant encoder->mode_set functions.
9545          */
9546         if (*prepare_pipes)
9547                 *modeset_pipes = *prepare_pipes;
9548
9549         /* ... and mask these out. */
9550         *modeset_pipes &= ~(*disable_pipes);
9551         *prepare_pipes &= ~(*disable_pipes);
9552
9553         /*
9554          * HACK: We don't (yet) fully support global modesets. intel_set_config
9555          * obies this rule, but the modeset restore mode of
9556          * intel_modeset_setup_hw_state does not.
9557          */
9558         *modeset_pipes &= 1 << intel_crtc->pipe;
9559         *prepare_pipes &= 1 << intel_crtc->pipe;
9560
9561         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9562                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9563 }
9564
9565 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9566 {
9567         struct drm_encoder *encoder;
9568         struct drm_device *dev = crtc->dev;
9569
9570         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9571                 if (encoder->crtc == crtc)
9572                         return true;
9573
9574         return false;
9575 }
9576
9577 static void
9578 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9579 {
9580         struct intel_encoder *intel_encoder;
9581         struct intel_crtc *intel_crtc;
9582         struct drm_connector *connector;
9583
9584         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9585                             base.head) {
9586                 if (!intel_encoder->base.crtc)
9587                         continue;
9588
9589                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9590
9591                 if (prepare_pipes & (1 << intel_crtc->pipe))
9592                         intel_encoder->connectors_active = false;
9593         }
9594
9595         intel_modeset_commit_output_state(dev);
9596
9597         /* Double check state. */
9598         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9599                             base.head) {
9600                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9601                 WARN_ON(intel_crtc->new_config &&
9602                         intel_crtc->new_config != &intel_crtc->config);
9603                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9604         }
9605
9606         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9607                 if (!connector->encoder || !connector->encoder->crtc)
9608                         continue;
9609
9610                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9611
9612                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9613                         struct drm_property *dpms_property =
9614                                 dev->mode_config.dpms_property;
9615
9616                         connector->dpms = DRM_MODE_DPMS_ON;
9617                         drm_object_property_set_value(&connector->base,
9618                                                          dpms_property,
9619                                                          DRM_MODE_DPMS_ON);
9620
9621                         intel_encoder = to_intel_encoder(connector->encoder);
9622                         intel_encoder->connectors_active = true;
9623                 }
9624         }
9625
9626 }
9627
9628 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9629 {
9630         int diff;
9631
9632         if (clock1 == clock2)
9633                 return true;
9634
9635         if (!clock1 || !clock2)
9636                 return false;
9637
9638         diff = abs(clock1 - clock2);
9639
9640         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9641                 return true;
9642
9643         return false;
9644 }
9645
9646 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9647         list_for_each_entry((intel_crtc), \
9648                             &(dev)->mode_config.crtc_list, \
9649                             base.head) \
9650                 if (mask & (1 <<(intel_crtc)->pipe))
9651
9652 static bool
9653 intel_pipe_config_compare(struct drm_device *dev,
9654                           struct intel_crtc_config *current_config,
9655                           struct intel_crtc_config *pipe_config)
9656 {
9657 #define PIPE_CONF_CHECK_X(name) \
9658         if (current_config->name != pipe_config->name) { \
9659                 DRM_ERROR("mismatch in " #name " " \
9660                           "(expected 0x%08x, found 0x%08x)\n", \
9661                           current_config->name, \
9662                           pipe_config->name); \
9663                 return false; \
9664         }
9665
9666 #define PIPE_CONF_CHECK_I(name) \
9667         if (current_config->name != pipe_config->name) { \
9668                 DRM_ERROR("mismatch in " #name " " \
9669                           "(expected %i, found %i)\n", \
9670                           current_config->name, \
9671                           pipe_config->name); \
9672                 return false; \
9673         }
9674
9675 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9676         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9677                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9678                           "(expected %i, found %i)\n", \
9679                           current_config->name & (mask), \
9680                           pipe_config->name & (mask)); \
9681                 return false; \
9682         }
9683
9684 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9685         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9686                 DRM_ERROR("mismatch in " #name " " \
9687                           "(expected %i, found %i)\n", \
9688                           current_config->name, \
9689                           pipe_config->name); \
9690                 return false; \
9691         }
9692
9693 #define PIPE_CONF_QUIRK(quirk)  \
9694         ((current_config->quirks | pipe_config->quirks) & (quirk))
9695
9696         PIPE_CONF_CHECK_I(cpu_transcoder);
9697
9698         PIPE_CONF_CHECK_I(has_pch_encoder);
9699         PIPE_CONF_CHECK_I(fdi_lanes);
9700         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9701         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9702         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9703         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9704         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9705
9706         PIPE_CONF_CHECK_I(has_dp_encoder);
9707         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9708         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9709         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9710         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9711         PIPE_CONF_CHECK_I(dp_m_n.tu);
9712
9713         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9714         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9715         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9716         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9717         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9718         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9719
9720         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9721         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9722         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9723         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9724         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9725         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9726
9727         PIPE_CONF_CHECK_I(pixel_multiplier);
9728
9729         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9730                               DRM_MODE_FLAG_INTERLACE);
9731
9732         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9733                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9734                                       DRM_MODE_FLAG_PHSYNC);
9735                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9736                                       DRM_MODE_FLAG_NHSYNC);
9737                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9738                                       DRM_MODE_FLAG_PVSYNC);
9739                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9740                                       DRM_MODE_FLAG_NVSYNC);
9741         }
9742
9743         PIPE_CONF_CHECK_I(pipe_src_w);
9744         PIPE_CONF_CHECK_I(pipe_src_h);
9745
9746         /*
9747          * FIXME: BIOS likes to set up a cloned config with lvds+external
9748          * screen. Since we don't yet re-compute the pipe config when moving
9749          * just the lvds port away to another pipe the sw tracking won't match.
9750          *
9751          * Proper atomic modesets with recomputed global state will fix this.
9752          * Until then just don't check gmch state for inherited modes.
9753          */
9754         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9755                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9756                 /* pfit ratios are autocomputed by the hw on gen4+ */
9757                 if (INTEL_INFO(dev)->gen < 4)
9758                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9759                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9760         }
9761
9762         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9763         if (current_config->pch_pfit.enabled) {
9764                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9765                 PIPE_CONF_CHECK_I(pch_pfit.size);
9766         }
9767
9768         /* BDW+ don't expose a synchronous way to read the state */
9769         if (IS_HASWELL(dev))
9770                 PIPE_CONF_CHECK_I(ips_enabled);
9771
9772         PIPE_CONF_CHECK_I(double_wide);
9773
9774         PIPE_CONF_CHECK_I(shared_dpll);
9775         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9776         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9777         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9778         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9779
9780         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9781                 PIPE_CONF_CHECK_I(pipe_bpp);
9782
9783         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9784         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9785
9786 #undef PIPE_CONF_CHECK_X
9787 #undef PIPE_CONF_CHECK_I
9788 #undef PIPE_CONF_CHECK_FLAGS
9789 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9790 #undef PIPE_CONF_QUIRK
9791
9792         return true;
9793 }
9794
9795 static void
9796 check_connector_state(struct drm_device *dev)
9797 {
9798         struct intel_connector *connector;
9799
9800         list_for_each_entry(connector, &dev->mode_config.connector_list,
9801                             base.head) {
9802                 /* This also checks the encoder/connector hw state with the
9803                  * ->get_hw_state callbacks. */
9804                 intel_connector_check_state(connector);
9805
9806                 WARN(&connector->new_encoder->base != connector->base.encoder,
9807                      "connector's staged encoder doesn't match current encoder\n");
9808         }
9809 }
9810
9811 static void
9812 check_encoder_state(struct drm_device *dev)
9813 {
9814         struct intel_encoder *encoder;
9815         struct intel_connector *connector;
9816
9817         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9818                             base.head) {
9819                 bool enabled = false;
9820                 bool active = false;
9821                 enum pipe pipe, tracked_pipe;
9822
9823                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9824                               encoder->base.base.id,
9825                               drm_get_encoder_name(&encoder->base));
9826
9827                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9828                      "encoder's stage crtc doesn't match current crtc\n");
9829                 WARN(encoder->connectors_active && !encoder->base.crtc,
9830                      "encoder's active_connectors set, but no crtc\n");
9831
9832                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9833                                     base.head) {
9834                         if (connector->base.encoder != &encoder->base)
9835                                 continue;
9836                         enabled = true;
9837                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9838                                 active = true;
9839                 }
9840                 WARN(!!encoder->base.crtc != enabled,
9841                      "encoder's enabled state mismatch "
9842                      "(expected %i, found %i)\n",
9843                      !!encoder->base.crtc, enabled);
9844                 WARN(active && !encoder->base.crtc,
9845                      "active encoder with no crtc\n");
9846
9847                 WARN(encoder->connectors_active != active,
9848                      "encoder's computed active state doesn't match tracked active state "
9849                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9850
9851                 active = encoder->get_hw_state(encoder, &pipe);
9852                 WARN(active != encoder->connectors_active,
9853                      "encoder's hw state doesn't match sw tracking "
9854                      "(expected %i, found %i)\n",
9855                      encoder->connectors_active, active);
9856
9857                 if (!encoder->base.crtc)
9858                         continue;
9859
9860                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9861                 WARN(active && pipe != tracked_pipe,
9862                      "active encoder's pipe doesn't match"
9863                      "(expected %i, found %i)\n",
9864                      tracked_pipe, pipe);
9865
9866         }
9867 }
9868
9869 static void
9870 check_crtc_state(struct drm_device *dev)
9871 {
9872         struct drm_i915_private *dev_priv = dev->dev_private;
9873         struct intel_crtc *crtc;
9874         struct intel_encoder *encoder;
9875         struct intel_crtc_config pipe_config;
9876
9877         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9878                             base.head) {
9879                 bool enabled = false;
9880                 bool active = false;
9881
9882                 memset(&pipe_config, 0, sizeof(pipe_config));
9883
9884                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9885                               crtc->base.base.id);
9886
9887                 WARN(crtc->active && !crtc->base.enabled,
9888                      "active crtc, but not enabled in sw tracking\n");
9889
9890                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9891                                     base.head) {
9892                         if (encoder->base.crtc != &crtc->base)
9893                                 continue;
9894                         enabled = true;
9895                         if (encoder->connectors_active)
9896                                 active = true;
9897                 }
9898
9899                 WARN(active != crtc->active,
9900                      "crtc's computed active state doesn't match tracked active state "
9901                      "(expected %i, found %i)\n", active, crtc->active);
9902                 WARN(enabled != crtc->base.enabled,
9903                      "crtc's computed enabled state doesn't match tracked enabled state "
9904                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9905
9906                 active = dev_priv->display.get_pipe_config(crtc,
9907                                                            &pipe_config);
9908
9909                 /* hw state is inconsistent with the pipe A quirk */
9910                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9911                         active = crtc->active;
9912
9913                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9914                                     base.head) {
9915                         enum pipe pipe;
9916                         if (encoder->base.crtc != &crtc->base)
9917                                 continue;
9918                         if (encoder->get_hw_state(encoder, &pipe))
9919                                 encoder->get_config(encoder, &pipe_config);
9920                 }
9921
9922                 WARN(crtc->active != active,
9923                      "crtc active state doesn't match with hw state "
9924                      "(expected %i, found %i)\n", crtc->active, active);
9925
9926                 if (active &&
9927                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9928                         WARN(1, "pipe state doesn't match!\n");
9929                         intel_dump_pipe_config(crtc, &pipe_config,
9930                                                "[hw state]");
9931                         intel_dump_pipe_config(crtc, &crtc->config,
9932                                                "[sw state]");
9933                 }
9934         }
9935 }
9936
9937 static void
9938 check_shared_dpll_state(struct drm_device *dev)
9939 {
9940         struct drm_i915_private *dev_priv = dev->dev_private;
9941         struct intel_crtc *crtc;
9942         struct intel_dpll_hw_state dpll_hw_state;
9943         int i;
9944
9945         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9946                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9947                 int enabled_crtcs = 0, active_crtcs = 0;
9948                 bool active;
9949
9950                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9951
9952                 DRM_DEBUG_KMS("%s\n", pll->name);
9953
9954                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9955
9956                 WARN(pll->active > pll->refcount,
9957                      "more active pll users than references: %i vs %i\n",
9958                      pll->active, pll->refcount);
9959                 WARN(pll->active && !pll->on,
9960                      "pll in active use but not on in sw tracking\n");
9961                 WARN(pll->on && !pll->active,
9962                      "pll in on but not on in use in sw tracking\n");
9963                 WARN(pll->on != active,
9964                      "pll on state mismatch (expected %i, found %i)\n",
9965                      pll->on, active);
9966
9967                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9968                                     base.head) {
9969                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9970                                 enabled_crtcs++;
9971                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9972                                 active_crtcs++;
9973                 }
9974                 WARN(pll->active != active_crtcs,
9975                      "pll active crtcs mismatch (expected %i, found %i)\n",
9976                      pll->active, active_crtcs);
9977                 WARN(pll->refcount != enabled_crtcs,
9978                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9979                      pll->refcount, enabled_crtcs);
9980
9981                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9982                                        sizeof(dpll_hw_state)),
9983                      "pll hw state mismatch\n");
9984         }
9985 }
9986
9987 void
9988 intel_modeset_check_state(struct drm_device *dev)
9989 {
9990         check_connector_state(dev);
9991         check_encoder_state(dev);
9992         check_crtc_state(dev);
9993         check_shared_dpll_state(dev);
9994 }
9995
9996 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9997                                      int dotclock)
9998 {
9999         /*
10000          * FDI already provided one idea for the dotclock.
10001          * Yell if the encoder disagrees.
10002          */
10003         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10004              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10005              pipe_config->adjusted_mode.crtc_clock, dotclock);
10006 }
10007
10008 static int __intel_set_mode(struct drm_crtc *crtc,
10009                             struct drm_display_mode *mode,
10010                             int x, int y, struct drm_framebuffer *fb)
10011 {
10012         struct drm_device *dev = crtc->dev;
10013         struct drm_i915_private *dev_priv = dev->dev_private;
10014         struct drm_display_mode *saved_mode;
10015         struct intel_crtc_config *pipe_config = NULL;
10016         struct intel_crtc *intel_crtc;
10017         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10018         int ret = 0;
10019
10020         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10021         if (!saved_mode)
10022                 return -ENOMEM;
10023
10024         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10025                                      &prepare_pipes, &disable_pipes);
10026
10027         *saved_mode = crtc->mode;
10028
10029         /* Hack: Because we don't (yet) support global modeset on multiple
10030          * crtcs, we don't keep track of the new mode for more than one crtc.
10031          * Hence simply check whether any bit is set in modeset_pipes in all the
10032          * pieces of code that are not yet converted to deal with mutliple crtcs
10033          * changing their mode at the same time. */
10034         if (modeset_pipes) {
10035                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10036                 if (IS_ERR(pipe_config)) {
10037                         ret = PTR_ERR(pipe_config);
10038                         pipe_config = NULL;
10039
10040                         goto out;
10041                 }
10042                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10043                                        "[modeset]");
10044                 to_intel_crtc(crtc)->new_config = pipe_config;
10045         }
10046
10047         /*
10048          * See if the config requires any additional preparation, e.g.
10049          * to adjust global state with pipes off.  We need to do this
10050          * here so we can get the modeset_pipe updated config for the new
10051          * mode set on this crtc.  For other crtcs we need to use the
10052          * adjusted_mode bits in the crtc directly.
10053          */
10054         if (IS_VALLEYVIEW(dev)) {
10055                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10056
10057                 /* may have added more to prepare_pipes than we should */
10058                 prepare_pipes &= ~disable_pipes;
10059         }
10060
10061         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10062                 intel_crtc_disable(&intel_crtc->base);
10063
10064         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10065                 if (intel_crtc->base.enabled)
10066                         dev_priv->display.crtc_disable(&intel_crtc->base);
10067         }
10068
10069         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10070          * to set it here already despite that we pass it down the callchain.
10071          */
10072         if (modeset_pipes) {
10073                 crtc->mode = *mode;
10074                 /* mode_set/enable/disable functions rely on a correct pipe
10075                  * config. */
10076                 to_intel_crtc(crtc)->config = *pipe_config;
10077                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10078
10079                 /*
10080                  * Calculate and store various constants which
10081                  * are later needed by vblank and swap-completion
10082                  * timestamping. They are derived from true hwmode.
10083                  */
10084                 drm_calc_timestamping_constants(crtc,
10085                                                 &pipe_config->adjusted_mode);
10086         }
10087
10088         /* Only after disabling all output pipelines that will be changed can we
10089          * update the the output configuration. */
10090         intel_modeset_update_state(dev, prepare_pipes);
10091
10092         if (dev_priv->display.modeset_global_resources)
10093                 dev_priv->display.modeset_global_resources(dev);
10094
10095         /* Set up the DPLL and any encoders state that needs to adjust or depend
10096          * on the DPLL.
10097          */
10098         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10099                 ret = intel_crtc_mode_set(&intel_crtc->base,
10100                                           x, y, fb);
10101                 if (ret)
10102                         goto done;
10103         }
10104
10105         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10106         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10107                 dev_priv->display.crtc_enable(&intel_crtc->base);
10108
10109         /* FIXME: add subpixel order */
10110 done:
10111         if (ret && crtc->enabled)
10112                 crtc->mode = *saved_mode;
10113
10114 out:
10115         kfree(pipe_config);
10116         kfree(saved_mode);
10117         return ret;
10118 }
10119
10120 static int intel_set_mode(struct drm_crtc *crtc,
10121                           struct drm_display_mode *mode,
10122                           int x, int y, struct drm_framebuffer *fb)
10123 {
10124         int ret;
10125
10126         ret = __intel_set_mode(crtc, mode, x, y, fb);
10127
10128         if (ret == 0)
10129                 intel_modeset_check_state(crtc->dev);
10130
10131         return ret;
10132 }
10133
10134 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10135 {
10136         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10137 }
10138
10139 #undef for_each_intel_crtc_masked
10140
10141 static void intel_set_config_free(struct intel_set_config *config)
10142 {
10143         if (!config)
10144                 return;
10145
10146         kfree(config->save_connector_encoders);
10147         kfree(config->save_encoder_crtcs);
10148         kfree(config->save_crtc_enabled);
10149         kfree(config);
10150 }
10151
10152 static int intel_set_config_save_state(struct drm_device *dev,
10153                                        struct intel_set_config *config)
10154 {
10155         struct drm_crtc *crtc;
10156         struct drm_encoder *encoder;
10157         struct drm_connector *connector;
10158         int count;
10159
10160         config->save_crtc_enabled =
10161                 kcalloc(dev->mode_config.num_crtc,
10162                         sizeof(bool), GFP_KERNEL);
10163         if (!config->save_crtc_enabled)
10164                 return -ENOMEM;
10165
10166         config->save_encoder_crtcs =
10167                 kcalloc(dev->mode_config.num_encoder,
10168                         sizeof(struct drm_crtc *), GFP_KERNEL);
10169         if (!config->save_encoder_crtcs)
10170                 return -ENOMEM;
10171
10172         config->save_connector_encoders =
10173                 kcalloc(dev->mode_config.num_connector,
10174                         sizeof(struct drm_encoder *), GFP_KERNEL);
10175         if (!config->save_connector_encoders)
10176                 return -ENOMEM;
10177
10178         /* Copy data. Note that driver private data is not affected.
10179          * Should anything bad happen only the expected state is
10180          * restored, not the drivers personal bookkeeping.
10181          */
10182         count = 0;
10183         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10184                 config->save_crtc_enabled[count++] = crtc->enabled;
10185         }
10186
10187         count = 0;
10188         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10189                 config->save_encoder_crtcs[count++] = encoder->crtc;
10190         }
10191
10192         count = 0;
10193         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10194                 config->save_connector_encoders[count++] = connector->encoder;
10195         }
10196
10197         return 0;
10198 }
10199
10200 static void intel_set_config_restore_state(struct drm_device *dev,
10201                                            struct intel_set_config *config)
10202 {
10203         struct intel_crtc *crtc;
10204         struct intel_encoder *encoder;
10205         struct intel_connector *connector;
10206         int count;
10207
10208         count = 0;
10209         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10210                 crtc->new_enabled = config->save_crtc_enabled[count++];
10211
10212                 if (crtc->new_enabled)
10213                         crtc->new_config = &crtc->config;
10214                 else
10215                         crtc->new_config = NULL;
10216         }
10217
10218         count = 0;
10219         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10220                 encoder->new_crtc =
10221                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10222         }
10223
10224         count = 0;
10225         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10226                 connector->new_encoder =
10227                         to_intel_encoder(config->save_connector_encoders[count++]);
10228         }
10229 }
10230
10231 static bool
10232 is_crtc_connector_off(struct drm_mode_set *set)
10233 {
10234         int i;
10235
10236         if (set->num_connectors == 0)
10237                 return false;
10238
10239         if (WARN_ON(set->connectors == NULL))
10240                 return false;
10241
10242         for (i = 0; i < set->num_connectors; i++)
10243                 if (set->connectors[i]->encoder &&
10244                     set->connectors[i]->encoder->crtc == set->crtc &&
10245                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10246                         return true;
10247
10248         return false;
10249 }
10250
10251 static void
10252 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10253                                       struct intel_set_config *config)
10254 {
10255
10256         /* We should be able to check here if the fb has the same properties
10257          * and then just flip_or_move it */
10258         if (is_crtc_connector_off(set)) {
10259                 config->mode_changed = true;
10260         } else if (set->crtc->primary->fb != set->fb) {
10261                 /* If we have no fb then treat it as a full mode set */
10262                 if (set->crtc->primary->fb == NULL) {
10263                         struct intel_crtc *intel_crtc =
10264                                 to_intel_crtc(set->crtc);
10265
10266                         if (intel_crtc->active && i915.fastboot) {
10267                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10268                                 config->fb_changed = true;
10269                         } else {
10270                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10271                                 config->mode_changed = true;
10272                         }
10273                 } else if (set->fb == NULL) {
10274                         config->mode_changed = true;
10275                 } else if (set->fb->pixel_format !=
10276                            set->crtc->primary->fb->pixel_format) {
10277                         config->mode_changed = true;
10278                 } else {
10279                         config->fb_changed = true;
10280                 }
10281         }
10282
10283         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10284                 config->fb_changed = true;
10285
10286         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10287                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10288                 drm_mode_debug_printmodeline(&set->crtc->mode);
10289                 drm_mode_debug_printmodeline(set->mode);
10290                 config->mode_changed = true;
10291         }
10292
10293         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10294                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10295 }
10296
10297 static int
10298 intel_modeset_stage_output_state(struct drm_device *dev,
10299                                  struct drm_mode_set *set,
10300                                  struct intel_set_config *config)
10301 {
10302         struct intel_connector *connector;
10303         struct intel_encoder *encoder;
10304         struct intel_crtc *crtc;
10305         int ro;
10306
10307         /* The upper layers ensure that we either disable a crtc or have a list
10308          * of connectors. For paranoia, double-check this. */
10309         WARN_ON(!set->fb && (set->num_connectors != 0));
10310         WARN_ON(set->fb && (set->num_connectors == 0));
10311
10312         list_for_each_entry(connector, &dev->mode_config.connector_list,
10313                             base.head) {
10314                 /* Otherwise traverse passed in connector list and get encoders
10315                  * for them. */
10316                 for (ro = 0; ro < set->num_connectors; ro++) {
10317                         if (set->connectors[ro] == &connector->base) {
10318                                 connector->new_encoder = connector->encoder;
10319                                 break;
10320                         }
10321                 }
10322
10323                 /* If we disable the crtc, disable all its connectors. Also, if
10324                  * the connector is on the changing crtc but not on the new
10325                  * connector list, disable it. */
10326                 if ((!set->fb || ro == set->num_connectors) &&
10327                     connector->base.encoder &&
10328                     connector->base.encoder->crtc == set->crtc) {
10329                         connector->new_encoder = NULL;
10330
10331                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10332                                 connector->base.base.id,
10333                                 drm_get_connector_name(&connector->base));
10334                 }
10335
10336
10337                 if (&connector->new_encoder->base != connector->base.encoder) {
10338                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10339                         config->mode_changed = true;
10340                 }
10341         }
10342         /* connector->new_encoder is now updated for all connectors. */
10343
10344         /* Update crtc of enabled connectors. */
10345         list_for_each_entry(connector, &dev->mode_config.connector_list,
10346                             base.head) {
10347                 struct drm_crtc *new_crtc;
10348
10349                 if (!connector->new_encoder)
10350                         continue;
10351
10352                 new_crtc = connector->new_encoder->base.crtc;
10353
10354                 for (ro = 0; ro < set->num_connectors; ro++) {
10355                         if (set->connectors[ro] == &connector->base)
10356                                 new_crtc = set->crtc;
10357                 }
10358
10359                 /* Make sure the new CRTC will work with the encoder */
10360                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10361                                          new_crtc)) {
10362                         return -EINVAL;
10363                 }
10364                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10365
10366                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10367                         connector->base.base.id,
10368                         drm_get_connector_name(&connector->base),
10369                         new_crtc->base.id);
10370         }
10371
10372         /* Check for any encoders that needs to be disabled. */
10373         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10374                             base.head) {
10375                 int num_connectors = 0;
10376                 list_for_each_entry(connector,
10377                                     &dev->mode_config.connector_list,
10378                                     base.head) {
10379                         if (connector->new_encoder == encoder) {
10380                                 WARN_ON(!connector->new_encoder->new_crtc);
10381                                 num_connectors++;
10382                         }
10383                 }
10384
10385                 if (num_connectors == 0)
10386                         encoder->new_crtc = NULL;
10387                 else if (num_connectors > 1)
10388                         return -EINVAL;
10389
10390                 /* Only now check for crtc changes so we don't miss encoders
10391                  * that will be disabled. */
10392                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10393                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10394                         config->mode_changed = true;
10395                 }
10396         }
10397         /* Now we've also updated encoder->new_crtc for all encoders. */
10398
10399         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10400                             base.head) {
10401                 crtc->new_enabled = false;
10402
10403                 list_for_each_entry(encoder,
10404                                     &dev->mode_config.encoder_list,
10405                                     base.head) {
10406                         if (encoder->new_crtc == crtc) {
10407                                 crtc->new_enabled = true;
10408                                 break;
10409                         }
10410                 }
10411
10412                 if (crtc->new_enabled != crtc->base.enabled) {
10413                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10414                                       crtc->new_enabled ? "en" : "dis");
10415                         config->mode_changed = true;
10416                 }
10417
10418                 if (crtc->new_enabled)
10419                         crtc->new_config = &crtc->config;
10420                 else
10421                         crtc->new_config = NULL;
10422         }
10423
10424         return 0;
10425 }
10426
10427 static void disable_crtc_nofb(struct intel_crtc *crtc)
10428 {
10429         struct drm_device *dev = crtc->base.dev;
10430         struct intel_encoder *encoder;
10431         struct intel_connector *connector;
10432
10433         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10434                       pipe_name(crtc->pipe));
10435
10436         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10437                 if (connector->new_encoder &&
10438                     connector->new_encoder->new_crtc == crtc)
10439                         connector->new_encoder = NULL;
10440         }
10441
10442         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10443                 if (encoder->new_crtc == crtc)
10444                         encoder->new_crtc = NULL;
10445         }
10446
10447         crtc->new_enabled = false;
10448         crtc->new_config = NULL;
10449 }
10450
10451 static int intel_crtc_set_config(struct drm_mode_set *set)
10452 {
10453         struct drm_device *dev;
10454         struct drm_mode_set save_set;
10455         struct intel_set_config *config;
10456         int ret;
10457
10458         BUG_ON(!set);
10459         BUG_ON(!set->crtc);
10460         BUG_ON(!set->crtc->helper_private);
10461
10462         /* Enforce sane interface api - has been abused by the fb helper. */
10463         BUG_ON(!set->mode && set->fb);
10464         BUG_ON(set->fb && set->num_connectors == 0);
10465
10466         if (set->fb) {
10467                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10468                                 set->crtc->base.id, set->fb->base.id,
10469                                 (int)set->num_connectors, set->x, set->y);
10470         } else {
10471                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10472         }
10473
10474         dev = set->crtc->dev;
10475
10476         ret = -ENOMEM;
10477         config = kzalloc(sizeof(*config), GFP_KERNEL);
10478         if (!config)
10479                 goto out_config;
10480
10481         ret = intel_set_config_save_state(dev, config);
10482         if (ret)
10483                 goto out_config;
10484
10485         save_set.crtc = set->crtc;
10486         save_set.mode = &set->crtc->mode;
10487         save_set.x = set->crtc->x;
10488         save_set.y = set->crtc->y;
10489         save_set.fb = set->crtc->primary->fb;
10490
10491         /* Compute whether we need a full modeset, only an fb base update or no
10492          * change at all. In the future we might also check whether only the
10493          * mode changed, e.g. for LVDS where we only change the panel fitter in
10494          * such cases. */
10495         intel_set_config_compute_mode_changes(set, config);
10496
10497         ret = intel_modeset_stage_output_state(dev, set, config);
10498         if (ret)
10499                 goto fail;
10500
10501         if (config->mode_changed) {
10502                 ret = intel_set_mode(set->crtc, set->mode,
10503                                      set->x, set->y, set->fb);
10504         } else if (config->fb_changed) {
10505                 intel_crtc_wait_for_pending_flips(set->crtc);
10506
10507                 ret = intel_pipe_set_base(set->crtc,
10508                                           set->x, set->y, set->fb);
10509                 /*
10510                  * In the fastboot case this may be our only check of the
10511                  * state after boot.  It would be better to only do it on
10512                  * the first update, but we don't have a nice way of doing that
10513                  * (and really, set_config isn't used much for high freq page
10514                  * flipping, so increasing its cost here shouldn't be a big
10515                  * deal).
10516                  */
10517                 if (i915.fastboot && ret == 0)
10518                         intel_modeset_check_state(set->crtc->dev);
10519         }
10520
10521         if (ret) {
10522                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10523                               set->crtc->base.id, ret);
10524 fail:
10525                 intel_set_config_restore_state(dev, config);
10526
10527                 /*
10528                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10529                  * force the pipe off to avoid oopsing in the modeset code
10530                  * due to fb==NULL. This should only happen during boot since
10531                  * we don't yet reconstruct the FB from the hardware state.
10532                  */
10533                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10534                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10535
10536                 /* Try to restore the config */
10537                 if (config->mode_changed &&
10538                     intel_set_mode(save_set.crtc, save_set.mode,
10539                                    save_set.x, save_set.y, save_set.fb))
10540                         DRM_ERROR("failed to restore config after modeset failure\n");
10541         }
10542
10543 out_config:
10544         intel_set_config_free(config);
10545         return ret;
10546 }
10547
10548 static const struct drm_crtc_funcs intel_crtc_funcs = {
10549         .cursor_set = intel_crtc_cursor_set,
10550         .cursor_move = intel_crtc_cursor_move,
10551         .gamma_set = intel_crtc_gamma_set,
10552         .set_config = intel_crtc_set_config,
10553         .destroy = intel_crtc_destroy,
10554         .page_flip = intel_crtc_page_flip,
10555 };
10556
10557 static void intel_cpu_pll_init(struct drm_device *dev)
10558 {
10559         if (HAS_DDI(dev))
10560                 intel_ddi_pll_init(dev);
10561 }
10562
10563 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10564                                       struct intel_shared_dpll *pll,
10565                                       struct intel_dpll_hw_state *hw_state)
10566 {
10567         uint32_t val;
10568
10569         val = I915_READ(PCH_DPLL(pll->id));
10570         hw_state->dpll = val;
10571         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10572         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10573
10574         return val & DPLL_VCO_ENABLE;
10575 }
10576
10577 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10578                                   struct intel_shared_dpll *pll)
10579 {
10580         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10581         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10582 }
10583
10584 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10585                                 struct intel_shared_dpll *pll)
10586 {
10587         /* PCH refclock must be enabled first */
10588         ibx_assert_pch_refclk_enabled(dev_priv);
10589
10590         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10591
10592         /* Wait for the clocks to stabilize. */
10593         POSTING_READ(PCH_DPLL(pll->id));
10594         udelay(150);
10595
10596         /* The pixel multiplier can only be updated once the
10597          * DPLL is enabled and the clocks are stable.
10598          *
10599          * So write it again.
10600          */
10601         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10602         POSTING_READ(PCH_DPLL(pll->id));
10603         udelay(200);
10604 }
10605
10606 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10607                                  struct intel_shared_dpll *pll)
10608 {
10609         struct drm_device *dev = dev_priv->dev;
10610         struct intel_crtc *crtc;
10611
10612         /* Make sure no transcoder isn't still depending on us. */
10613         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10614                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10615                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10616         }
10617
10618         I915_WRITE(PCH_DPLL(pll->id), 0);
10619         POSTING_READ(PCH_DPLL(pll->id));
10620         udelay(200);
10621 }
10622
10623 static char *ibx_pch_dpll_names[] = {
10624         "PCH DPLL A",
10625         "PCH DPLL B",
10626 };
10627
10628 static void ibx_pch_dpll_init(struct drm_device *dev)
10629 {
10630         struct drm_i915_private *dev_priv = dev->dev_private;
10631         int i;
10632
10633         dev_priv->num_shared_dpll = 2;
10634
10635         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10636                 dev_priv->shared_dplls[i].id = i;
10637                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10638                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10639                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10640                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10641                 dev_priv->shared_dplls[i].get_hw_state =
10642                         ibx_pch_dpll_get_hw_state;
10643         }
10644 }
10645
10646 static void intel_shared_dpll_init(struct drm_device *dev)
10647 {
10648         struct drm_i915_private *dev_priv = dev->dev_private;
10649
10650         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10651                 ibx_pch_dpll_init(dev);
10652         else
10653                 dev_priv->num_shared_dpll = 0;
10654
10655         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10656 }
10657
10658 static void intel_crtc_init(struct drm_device *dev, int pipe)
10659 {
10660         struct drm_i915_private *dev_priv = dev->dev_private;
10661         struct intel_crtc *intel_crtc;
10662         int i;
10663
10664         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10665         if (intel_crtc == NULL)
10666                 return;
10667
10668         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10669
10670         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10671         for (i = 0; i < 256; i++) {
10672                 intel_crtc->lut_r[i] = i;
10673                 intel_crtc->lut_g[i] = i;
10674                 intel_crtc->lut_b[i] = i;
10675         }
10676
10677         /*
10678          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10679          * is hooked to plane B. Hence we want plane A feeding pipe B.
10680          */
10681         intel_crtc->pipe = pipe;
10682         intel_crtc->plane = pipe;
10683         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10684                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10685                 intel_crtc->plane = !pipe;
10686         }
10687
10688         init_waitqueue_head(&intel_crtc->vbl_wait);
10689
10690         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10691                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10692         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10693         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10694
10695         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10696 }
10697
10698 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10699 {
10700         struct drm_encoder *encoder = connector->base.encoder;
10701
10702         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10703
10704         if (!encoder)
10705                 return INVALID_PIPE;
10706
10707         return to_intel_crtc(encoder->crtc)->pipe;
10708 }
10709
10710 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10711                                 struct drm_file *file)
10712 {
10713         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10714         struct drm_mode_object *drmmode_obj;
10715         struct intel_crtc *crtc;
10716
10717         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10718                 return -ENODEV;
10719
10720         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10721                         DRM_MODE_OBJECT_CRTC);
10722
10723         if (!drmmode_obj) {
10724                 DRM_ERROR("no such CRTC id\n");
10725                 return -ENOENT;
10726         }
10727
10728         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10729         pipe_from_crtc_id->pipe = crtc->pipe;
10730
10731         return 0;
10732 }
10733
10734 static int intel_encoder_clones(struct intel_encoder *encoder)
10735 {
10736         struct drm_device *dev = encoder->base.dev;
10737         struct intel_encoder *source_encoder;
10738         int index_mask = 0;
10739         int entry = 0;
10740
10741         list_for_each_entry(source_encoder,
10742                             &dev->mode_config.encoder_list, base.head) {
10743                 if (encoders_cloneable(encoder, source_encoder))
10744                         index_mask |= (1 << entry);
10745
10746                 entry++;
10747         }
10748
10749         return index_mask;
10750 }
10751
10752 static bool has_edp_a(struct drm_device *dev)
10753 {
10754         struct drm_i915_private *dev_priv = dev->dev_private;
10755
10756         if (!IS_MOBILE(dev))
10757                 return false;
10758
10759         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10760                 return false;
10761
10762         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10763                 return false;
10764
10765         return true;
10766 }
10767
10768 const char *intel_output_name(int output)
10769 {
10770         static const char *names[] = {
10771                 [INTEL_OUTPUT_UNUSED] = "Unused",
10772                 [INTEL_OUTPUT_ANALOG] = "Analog",
10773                 [INTEL_OUTPUT_DVO] = "DVO",
10774                 [INTEL_OUTPUT_SDVO] = "SDVO",
10775                 [INTEL_OUTPUT_LVDS] = "LVDS",
10776                 [INTEL_OUTPUT_TVOUT] = "TV",
10777                 [INTEL_OUTPUT_HDMI] = "HDMI",
10778                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10779                 [INTEL_OUTPUT_EDP] = "eDP",
10780                 [INTEL_OUTPUT_DSI] = "DSI",
10781                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10782         };
10783
10784         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10785                 return "Invalid";
10786
10787         return names[output];
10788 }
10789
10790 static void intel_setup_outputs(struct drm_device *dev)
10791 {
10792         struct drm_i915_private *dev_priv = dev->dev_private;
10793         struct intel_encoder *encoder;
10794         bool dpd_is_edp = false;
10795
10796         intel_lvds_init(dev);
10797
10798         if (!IS_ULT(dev))
10799                 intel_crt_init(dev);
10800
10801         if (HAS_DDI(dev)) {
10802                 int found;
10803
10804                 /* Haswell uses DDI functions to detect digital outputs */
10805                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10806                 /* DDI A only supports eDP */
10807                 if (found)
10808                         intel_ddi_init(dev, PORT_A);
10809
10810                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10811                  * register */
10812                 found = I915_READ(SFUSE_STRAP);
10813
10814                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10815                         intel_ddi_init(dev, PORT_B);
10816                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10817                         intel_ddi_init(dev, PORT_C);
10818                 if (found & SFUSE_STRAP_DDID_DETECTED)
10819                         intel_ddi_init(dev, PORT_D);
10820         } else if (HAS_PCH_SPLIT(dev)) {
10821                 int found;
10822                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10823
10824                 if (has_edp_a(dev))
10825                         intel_dp_init(dev, DP_A, PORT_A);
10826
10827                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10828                         /* PCH SDVOB multiplex with HDMIB */
10829                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10830                         if (!found)
10831                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10832                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10833                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10834                 }
10835
10836                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10837                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10838
10839                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10840                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10841
10842                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10843                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10844
10845                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10846                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10847         } else if (IS_VALLEYVIEW(dev)) {
10848                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10849                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10850                                         PORT_B);
10851                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10852                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10853                 }
10854
10855                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10856                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10857                                         PORT_C);
10858                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10859                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10860                 }
10861
10862                 intel_dsi_init(dev);
10863         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10864                 bool found = false;
10865
10866                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10867                         DRM_DEBUG_KMS("probing SDVOB\n");
10868                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10869                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10870                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10871                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10872                         }
10873
10874                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10875                                 intel_dp_init(dev, DP_B, PORT_B);
10876                 }
10877
10878                 /* Before G4X SDVOC doesn't have its own detect register */
10879
10880                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10881                         DRM_DEBUG_KMS("probing SDVOC\n");
10882                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10883                 }
10884
10885                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10886
10887                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10888                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10889                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10890                         }
10891                         if (SUPPORTS_INTEGRATED_DP(dev))
10892                                 intel_dp_init(dev, DP_C, PORT_C);
10893                 }
10894
10895                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10896                     (I915_READ(DP_D) & DP_DETECTED))
10897                         intel_dp_init(dev, DP_D, PORT_D);
10898         } else if (IS_GEN2(dev))
10899                 intel_dvo_init(dev);
10900
10901         if (SUPPORTS_TV(dev))
10902                 intel_tv_init(dev);
10903
10904         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10905                 encoder->base.possible_crtcs = encoder->crtc_mask;
10906                 encoder->base.possible_clones =
10907                         intel_encoder_clones(encoder);
10908         }
10909
10910         intel_init_pch_refclk(dev);
10911
10912         drm_helper_move_panel_connectors_to_head(dev);
10913 }
10914
10915 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10916 {
10917         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10918
10919         drm_framebuffer_cleanup(fb);
10920         WARN_ON(!intel_fb->obj->framebuffer_references--);
10921         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10922         kfree(intel_fb);
10923 }
10924
10925 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10926                                                 struct drm_file *file,
10927                                                 unsigned int *handle)
10928 {
10929         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10930         struct drm_i915_gem_object *obj = intel_fb->obj;
10931
10932         return drm_gem_handle_create(file, &obj->base, handle);
10933 }
10934
10935 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10936         .destroy = intel_user_framebuffer_destroy,
10937         .create_handle = intel_user_framebuffer_create_handle,
10938 };
10939
10940 static int intel_framebuffer_init(struct drm_device *dev,
10941                                   struct intel_framebuffer *intel_fb,
10942                                   struct drm_mode_fb_cmd2 *mode_cmd,
10943                                   struct drm_i915_gem_object *obj)
10944 {
10945         int aligned_height;
10946         int pitch_limit;
10947         int ret;
10948
10949         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10950
10951         if (obj->tiling_mode == I915_TILING_Y) {
10952                 DRM_DEBUG("hardware does not support tiling Y\n");
10953                 return -EINVAL;
10954         }
10955
10956         if (mode_cmd->pitches[0] & 63) {
10957                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10958                           mode_cmd->pitches[0]);
10959                 return -EINVAL;
10960         }
10961
10962         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10963                 pitch_limit = 32*1024;
10964         } else if (INTEL_INFO(dev)->gen >= 4) {
10965                 if (obj->tiling_mode)
10966                         pitch_limit = 16*1024;
10967                 else
10968                         pitch_limit = 32*1024;
10969         } else if (INTEL_INFO(dev)->gen >= 3) {
10970                 if (obj->tiling_mode)
10971                         pitch_limit = 8*1024;
10972                 else
10973                         pitch_limit = 16*1024;
10974         } else
10975                 /* XXX DSPC is limited to 4k tiled */
10976                 pitch_limit = 8*1024;
10977
10978         if (mode_cmd->pitches[0] > pitch_limit) {
10979                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10980                           obj->tiling_mode ? "tiled" : "linear",
10981                           mode_cmd->pitches[0], pitch_limit);
10982                 return -EINVAL;
10983         }
10984
10985         if (obj->tiling_mode != I915_TILING_NONE &&
10986             mode_cmd->pitches[0] != obj->stride) {
10987                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10988                           mode_cmd->pitches[0], obj->stride);
10989                 return -EINVAL;
10990         }
10991
10992         /* Reject formats not supported by any plane early. */
10993         switch (mode_cmd->pixel_format) {
10994         case DRM_FORMAT_C8:
10995         case DRM_FORMAT_RGB565:
10996         case DRM_FORMAT_XRGB8888:
10997         case DRM_FORMAT_ARGB8888:
10998                 break;
10999         case DRM_FORMAT_XRGB1555:
11000         case DRM_FORMAT_ARGB1555:
11001                 if (INTEL_INFO(dev)->gen > 3) {
11002                         DRM_DEBUG("unsupported pixel format: %s\n",
11003                                   drm_get_format_name(mode_cmd->pixel_format));
11004                         return -EINVAL;
11005                 }
11006                 break;
11007         case DRM_FORMAT_XBGR8888:
11008         case DRM_FORMAT_ABGR8888:
11009         case DRM_FORMAT_XRGB2101010:
11010         case DRM_FORMAT_ARGB2101010:
11011         case DRM_FORMAT_XBGR2101010:
11012         case DRM_FORMAT_ABGR2101010:
11013                 if (INTEL_INFO(dev)->gen < 4) {
11014                         DRM_DEBUG("unsupported pixel format: %s\n",
11015                                   drm_get_format_name(mode_cmd->pixel_format));
11016                         return -EINVAL;
11017                 }
11018                 break;
11019         case DRM_FORMAT_YUYV:
11020         case DRM_FORMAT_UYVY:
11021         case DRM_FORMAT_YVYU:
11022         case DRM_FORMAT_VYUY:
11023                 if (INTEL_INFO(dev)->gen < 5) {
11024                         DRM_DEBUG("unsupported pixel format: %s\n",
11025                                   drm_get_format_name(mode_cmd->pixel_format));
11026                         return -EINVAL;
11027                 }
11028                 break;
11029         default:
11030                 DRM_DEBUG("unsupported pixel format: %s\n",
11031                           drm_get_format_name(mode_cmd->pixel_format));
11032                 return -EINVAL;
11033         }
11034
11035         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11036         if (mode_cmd->offsets[0] != 0)
11037                 return -EINVAL;
11038
11039         aligned_height = intel_align_height(dev, mode_cmd->height,
11040                                             obj->tiling_mode);
11041         /* FIXME drm helper for size checks (especially planar formats)? */
11042         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11043                 return -EINVAL;
11044
11045         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11046         intel_fb->obj = obj;
11047         intel_fb->obj->framebuffer_references++;
11048
11049         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11050         if (ret) {
11051                 DRM_ERROR("framebuffer init failed %d\n", ret);
11052                 return ret;
11053         }
11054
11055         return 0;
11056 }
11057
11058 static struct drm_framebuffer *
11059 intel_user_framebuffer_create(struct drm_device *dev,
11060                               struct drm_file *filp,
11061                               struct drm_mode_fb_cmd2 *mode_cmd)
11062 {
11063         struct drm_i915_gem_object *obj;
11064
11065         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11066                                                 mode_cmd->handles[0]));
11067         if (&obj->base == NULL)
11068                 return ERR_PTR(-ENOENT);
11069
11070         return intel_framebuffer_create(dev, mode_cmd, obj);
11071 }
11072
11073 #ifndef CONFIG_DRM_I915_FBDEV
11074 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11075 {
11076 }
11077 #endif
11078
11079 static const struct drm_mode_config_funcs intel_mode_funcs = {
11080         .fb_create = intel_user_framebuffer_create,
11081         .output_poll_changed = intel_fbdev_output_poll_changed,
11082 };
11083
11084 /* Set up chip specific display functions */
11085 static void intel_init_display(struct drm_device *dev)
11086 {
11087         struct drm_i915_private *dev_priv = dev->dev_private;
11088
11089         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11090                 dev_priv->display.find_dpll = g4x_find_best_dpll;
11091         else if (IS_CHERRYVIEW(dev))
11092                 dev_priv->display.find_dpll = chv_find_best_dpll;
11093         else if (IS_VALLEYVIEW(dev))
11094                 dev_priv->display.find_dpll = vlv_find_best_dpll;
11095         else if (IS_PINEVIEW(dev))
11096                 dev_priv->display.find_dpll = pnv_find_best_dpll;
11097         else
11098                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11099
11100         if (HAS_DDI(dev)) {
11101                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11102                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11103                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11104                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11105                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11106                 dev_priv->display.off = haswell_crtc_off;
11107                 dev_priv->display.update_primary_plane =
11108                         ironlake_update_primary_plane;
11109         } else if (HAS_PCH_SPLIT(dev)) {
11110                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11111                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11112                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11113                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11114                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11115                 dev_priv->display.off = ironlake_crtc_off;
11116                 dev_priv->display.update_primary_plane =
11117                         ironlake_update_primary_plane;
11118         } else if (IS_VALLEYVIEW(dev)) {
11119                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11120                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11121                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11122                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11123                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11124                 dev_priv->display.off = i9xx_crtc_off;
11125                 dev_priv->display.update_primary_plane =
11126                         i9xx_update_primary_plane;
11127         } else {
11128                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11129                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11130                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11131                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11132                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11133                 dev_priv->display.off = i9xx_crtc_off;
11134                 dev_priv->display.update_primary_plane =
11135                         i9xx_update_primary_plane;
11136         }
11137
11138         /* Returns the core display clock speed */
11139         if (IS_VALLEYVIEW(dev))
11140                 dev_priv->display.get_display_clock_speed =
11141                         valleyview_get_display_clock_speed;
11142         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11143                 dev_priv->display.get_display_clock_speed =
11144                         i945_get_display_clock_speed;
11145         else if (IS_I915G(dev))
11146                 dev_priv->display.get_display_clock_speed =
11147                         i915_get_display_clock_speed;
11148         else if (IS_I945GM(dev) || IS_845G(dev))
11149                 dev_priv->display.get_display_clock_speed =
11150                         i9xx_misc_get_display_clock_speed;
11151         else if (IS_PINEVIEW(dev))
11152                 dev_priv->display.get_display_clock_speed =
11153                         pnv_get_display_clock_speed;
11154         else if (IS_I915GM(dev))
11155                 dev_priv->display.get_display_clock_speed =
11156                         i915gm_get_display_clock_speed;
11157         else if (IS_I865G(dev))
11158                 dev_priv->display.get_display_clock_speed =
11159                         i865_get_display_clock_speed;
11160         else if (IS_I85X(dev))
11161                 dev_priv->display.get_display_clock_speed =
11162                         i855_get_display_clock_speed;
11163         else /* 852, 830 */
11164                 dev_priv->display.get_display_clock_speed =
11165                         i830_get_display_clock_speed;
11166
11167         if (HAS_PCH_SPLIT(dev)) {
11168                 if (IS_GEN5(dev)) {
11169                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11170                         dev_priv->display.write_eld = ironlake_write_eld;
11171                 } else if (IS_GEN6(dev)) {
11172                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11173                         dev_priv->display.write_eld = ironlake_write_eld;
11174                         dev_priv->display.modeset_global_resources =
11175                                 snb_modeset_global_resources;
11176                 } else if (IS_IVYBRIDGE(dev)) {
11177                         /* FIXME: detect B0+ stepping and use auto training */
11178                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11179                         dev_priv->display.write_eld = ironlake_write_eld;
11180                         dev_priv->display.modeset_global_resources =
11181                                 ivb_modeset_global_resources;
11182                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11183                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11184                         dev_priv->display.write_eld = haswell_write_eld;
11185                         dev_priv->display.modeset_global_resources =
11186                                 haswell_modeset_global_resources;
11187                 }
11188         } else if (IS_G4X(dev)) {
11189                 dev_priv->display.write_eld = g4x_write_eld;
11190         } else if (IS_VALLEYVIEW(dev)) {
11191                 dev_priv->display.modeset_global_resources =
11192                         valleyview_modeset_global_resources;
11193                 dev_priv->display.write_eld = ironlake_write_eld;
11194         }
11195
11196         /* Default just returns -ENODEV to indicate unsupported */
11197         dev_priv->display.queue_flip = intel_default_queue_flip;
11198
11199         switch (INTEL_INFO(dev)->gen) {
11200         case 2:
11201                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11202                 break;
11203
11204         case 3:
11205                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11206                 break;
11207
11208         case 4:
11209         case 5:
11210                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11211                 break;
11212
11213         case 6:
11214                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11215                 break;
11216         case 7:
11217         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11218                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11219                 break;
11220         }
11221
11222         intel_panel_init_backlight_funcs(dev);
11223 }
11224
11225 /*
11226  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11227  * resume, or other times.  This quirk makes sure that's the case for
11228  * affected systems.
11229  */
11230 static void quirk_pipea_force(struct drm_device *dev)
11231 {
11232         struct drm_i915_private *dev_priv = dev->dev_private;
11233
11234         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11235         DRM_INFO("applying pipe a force quirk\n");
11236 }
11237
11238 /*
11239  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11240  */
11241 static void quirk_ssc_force_disable(struct drm_device *dev)
11242 {
11243         struct drm_i915_private *dev_priv = dev->dev_private;
11244         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11245         DRM_INFO("applying lvds SSC disable quirk\n");
11246 }
11247
11248 /*
11249  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11250  * brightness value
11251  */
11252 static void quirk_invert_brightness(struct drm_device *dev)
11253 {
11254         struct drm_i915_private *dev_priv = dev->dev_private;
11255         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11256         DRM_INFO("applying inverted panel brightness quirk\n");
11257 }
11258
11259 struct intel_quirk {
11260         int device;
11261         int subsystem_vendor;
11262         int subsystem_device;
11263         void (*hook)(struct drm_device *dev);
11264 };
11265
11266 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11267 struct intel_dmi_quirk {
11268         void (*hook)(struct drm_device *dev);
11269         const struct dmi_system_id (*dmi_id_list)[];
11270 };
11271
11272 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11273 {
11274         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11275         return 1;
11276 }
11277
11278 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11279         {
11280                 .dmi_id_list = &(const struct dmi_system_id[]) {
11281                         {
11282                                 .callback = intel_dmi_reverse_brightness,
11283                                 .ident = "NCR Corporation",
11284                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11285                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11286                                 },
11287                         },
11288                         { }  /* terminating entry */
11289                 },
11290                 .hook = quirk_invert_brightness,
11291         },
11292 };
11293
11294 static struct intel_quirk intel_quirks[] = {
11295         /* HP Mini needs pipe A force quirk (LP: #322104) */
11296         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11297
11298         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11299         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11300
11301         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11302         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11303
11304         /* 830 needs to leave pipe A & dpll A up */
11305         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11306
11307         /* Lenovo U160 cannot use SSC on LVDS */
11308         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11309
11310         /* Sony Vaio Y cannot use SSC on LVDS */
11311         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11312
11313         /* Acer Aspire 5734Z must invert backlight brightness */
11314         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11315
11316         /* Acer/eMachines G725 */
11317         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11318
11319         /* Acer/eMachines e725 */
11320         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11321
11322         /* Acer/Packard Bell NCL20 */
11323         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11324
11325         /* Acer Aspire 4736Z */
11326         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11327
11328         /* Acer Aspire 5336 */
11329         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11330 };
11331
11332 static void intel_init_quirks(struct drm_device *dev)
11333 {
11334         struct pci_dev *d = dev->pdev;
11335         int i;
11336
11337         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11338                 struct intel_quirk *q = &intel_quirks[i];
11339
11340                 if (d->device == q->device &&
11341                     (d->subsystem_vendor == q->subsystem_vendor ||
11342                      q->subsystem_vendor == PCI_ANY_ID) &&
11343                     (d->subsystem_device == q->subsystem_device ||
11344                      q->subsystem_device == PCI_ANY_ID))
11345                         q->hook(dev);
11346         }
11347         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11348                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11349                         intel_dmi_quirks[i].hook(dev);
11350         }
11351 }
11352
11353 /* Disable the VGA plane that we never use */
11354 static void i915_disable_vga(struct drm_device *dev)
11355 {
11356         struct drm_i915_private *dev_priv = dev->dev_private;
11357         u8 sr1;
11358         u32 vga_reg = i915_vgacntrl_reg(dev);
11359
11360         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11361         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11362         outb(SR01, VGA_SR_INDEX);
11363         sr1 = inb(VGA_SR_DATA);
11364         outb(sr1 | 1<<5, VGA_SR_DATA);
11365         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11366         udelay(300);
11367
11368         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11369         POSTING_READ(vga_reg);
11370 }
11371
11372 void intel_modeset_init_hw(struct drm_device *dev)
11373 {
11374         intel_prepare_ddi(dev);
11375
11376         intel_init_clock_gating(dev);
11377
11378         intel_reset_dpio(dev);
11379
11380         intel_enable_gt_powersave(dev);
11381 }
11382
11383 void intel_modeset_suspend_hw(struct drm_device *dev)
11384 {
11385         intel_suspend_hw(dev);
11386 }
11387
11388 void intel_modeset_init(struct drm_device *dev)
11389 {
11390         struct drm_i915_private *dev_priv = dev->dev_private;
11391         int sprite, ret;
11392         enum pipe pipe;
11393         struct intel_crtc *crtc;
11394
11395         drm_mode_config_init(dev);
11396
11397         dev->mode_config.min_width = 0;
11398         dev->mode_config.min_height = 0;
11399
11400         dev->mode_config.preferred_depth = 24;
11401         dev->mode_config.prefer_shadow = 1;
11402
11403         dev->mode_config.funcs = &intel_mode_funcs;
11404
11405         intel_init_quirks(dev);
11406
11407         intel_init_pm(dev);
11408
11409         if (INTEL_INFO(dev)->num_pipes == 0)
11410                 return;
11411
11412         intel_init_display(dev);
11413
11414         if (IS_GEN2(dev)) {
11415                 dev->mode_config.max_width = 2048;
11416                 dev->mode_config.max_height = 2048;
11417         } else if (IS_GEN3(dev)) {
11418                 dev->mode_config.max_width = 4096;
11419                 dev->mode_config.max_height = 4096;
11420         } else {
11421                 dev->mode_config.max_width = 8192;
11422                 dev->mode_config.max_height = 8192;
11423         }
11424
11425         if (IS_GEN2(dev)) {
11426                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11427                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11428         } else {
11429                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11430                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11431         }
11432
11433         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11434
11435         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11436                       INTEL_INFO(dev)->num_pipes,
11437                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11438
11439         for_each_pipe(pipe) {
11440                 intel_crtc_init(dev, pipe);
11441                 for_each_sprite(pipe, sprite) {
11442                         ret = intel_plane_init(dev, pipe, sprite);
11443                         if (ret)
11444                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11445                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11446                 }
11447         }
11448
11449         intel_init_dpio(dev);
11450         intel_reset_dpio(dev);
11451
11452         intel_cpu_pll_init(dev);
11453         intel_shared_dpll_init(dev);
11454
11455         /* Just disable it once at startup */
11456         i915_disable_vga(dev);
11457         intel_setup_outputs(dev);
11458
11459         /* Just in case the BIOS is doing something questionable. */
11460         intel_disable_fbc(dev);
11461
11462         mutex_lock(&dev->mode_config.mutex);
11463         intel_modeset_setup_hw_state(dev, false);
11464         mutex_unlock(&dev->mode_config.mutex);
11465
11466         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11467                             base.head) {
11468                 if (!crtc->active)
11469                         continue;
11470
11471                 /*
11472                  * Note that reserving the BIOS fb up front prevents us
11473                  * from stuffing other stolen allocations like the ring
11474                  * on top.  This prevents some ugliness at boot time, and
11475                  * can even allow for smooth boot transitions if the BIOS
11476                  * fb is large enough for the active pipe configuration.
11477                  */
11478                 if (dev_priv->display.get_plane_config) {
11479                         dev_priv->display.get_plane_config(crtc,
11480                                                            &crtc->plane_config);
11481                         /*
11482                          * If the fb is shared between multiple heads, we'll
11483                          * just get the first one.
11484                          */
11485                         intel_find_plane_obj(crtc, &crtc->plane_config);
11486                 }
11487         }
11488 }
11489
11490 static void
11491 intel_connector_break_all_links(struct intel_connector *connector)
11492 {
11493         connector->base.dpms = DRM_MODE_DPMS_OFF;
11494         connector->base.encoder = NULL;
11495         connector->encoder->connectors_active = false;
11496         connector->encoder->base.crtc = NULL;
11497 }
11498
11499 static void intel_enable_pipe_a(struct drm_device *dev)
11500 {
11501         struct intel_connector *connector;
11502         struct drm_connector *crt = NULL;
11503         struct intel_load_detect_pipe load_detect_temp;
11504
11505         /* We can't just switch on the pipe A, we need to set things up with a
11506          * proper mode and output configuration. As a gross hack, enable pipe A
11507          * by enabling the load detect pipe once. */
11508         list_for_each_entry(connector,
11509                             &dev->mode_config.connector_list,
11510                             base.head) {
11511                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11512                         crt = &connector->base;
11513                         break;
11514                 }
11515         }
11516
11517         if (!crt)
11518                 return;
11519
11520         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11521                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11522
11523
11524 }
11525
11526 static bool
11527 intel_check_plane_mapping(struct intel_crtc *crtc)
11528 {
11529         struct drm_device *dev = crtc->base.dev;
11530         struct drm_i915_private *dev_priv = dev->dev_private;
11531         u32 reg, val;
11532
11533         if (INTEL_INFO(dev)->num_pipes == 1)
11534                 return true;
11535
11536         reg = DSPCNTR(!crtc->plane);
11537         val = I915_READ(reg);
11538
11539         if ((val & DISPLAY_PLANE_ENABLE) &&
11540             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11541                 return false;
11542
11543         return true;
11544 }
11545
11546 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11547 {
11548         struct drm_device *dev = crtc->base.dev;
11549         struct drm_i915_private *dev_priv = dev->dev_private;
11550         u32 reg;
11551
11552         /* Clear any frame start delays used for debugging left by the BIOS */
11553         reg = PIPECONF(crtc->config.cpu_transcoder);
11554         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11555
11556         /* We need to sanitize the plane -> pipe mapping first because this will
11557          * disable the crtc (and hence change the state) if it is wrong. Note
11558          * that gen4+ has a fixed plane -> pipe mapping.  */
11559         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11560                 struct intel_connector *connector;
11561                 bool plane;
11562
11563                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11564                               crtc->base.base.id);
11565
11566                 /* Pipe has the wrong plane attached and the plane is active.
11567                  * Temporarily change the plane mapping and disable everything
11568                  * ...  */
11569                 plane = crtc->plane;
11570                 crtc->plane = !plane;
11571                 dev_priv->display.crtc_disable(&crtc->base);
11572                 crtc->plane = plane;
11573
11574                 /* ... and break all links. */
11575                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11576                                     base.head) {
11577                         if (connector->encoder->base.crtc != &crtc->base)
11578                                 continue;
11579
11580                         intel_connector_break_all_links(connector);
11581                 }
11582
11583                 WARN_ON(crtc->active);
11584                 crtc->base.enabled = false;
11585         }
11586
11587         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11588             crtc->pipe == PIPE_A && !crtc->active) {
11589                 /* BIOS forgot to enable pipe A, this mostly happens after
11590                  * resume. Force-enable the pipe to fix this, the update_dpms
11591                  * call below we restore the pipe to the right state, but leave
11592                  * the required bits on. */
11593                 intel_enable_pipe_a(dev);
11594         }
11595
11596         /* Adjust the state of the output pipe according to whether we
11597          * have active connectors/encoders. */
11598         intel_crtc_update_dpms(&crtc->base);
11599
11600         if (crtc->active != crtc->base.enabled) {
11601                 struct intel_encoder *encoder;
11602
11603                 /* This can happen either due to bugs in the get_hw_state
11604                  * functions or because the pipe is force-enabled due to the
11605                  * pipe A quirk. */
11606                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11607                               crtc->base.base.id,
11608                               crtc->base.enabled ? "enabled" : "disabled",
11609                               crtc->active ? "enabled" : "disabled");
11610
11611                 crtc->base.enabled = crtc->active;
11612
11613                 /* Because we only establish the connector -> encoder ->
11614                  * crtc links if something is active, this means the
11615                  * crtc is now deactivated. Break the links. connector
11616                  * -> encoder links are only establish when things are
11617                  *  actually up, hence no need to break them. */
11618                 WARN_ON(crtc->active);
11619
11620                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11621                         WARN_ON(encoder->connectors_active);
11622                         encoder->base.crtc = NULL;
11623                 }
11624         }
11625         if (crtc->active) {
11626                 /*
11627                  * We start out with underrun reporting disabled to avoid races.
11628                  * For correct bookkeeping mark this on active crtcs.
11629                  *
11630                  * No protection against concurrent access is required - at
11631                  * worst a fifo underrun happens which also sets this to false.
11632                  */
11633                 crtc->cpu_fifo_underrun_disabled = true;
11634                 crtc->pch_fifo_underrun_disabled = true;
11635         }
11636 }
11637
11638 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11639 {
11640         struct intel_connector *connector;
11641         struct drm_device *dev = encoder->base.dev;
11642
11643         /* We need to check both for a crtc link (meaning that the
11644          * encoder is active and trying to read from a pipe) and the
11645          * pipe itself being active. */
11646         bool has_active_crtc = encoder->base.crtc &&
11647                 to_intel_crtc(encoder->base.crtc)->active;
11648
11649         if (encoder->connectors_active && !has_active_crtc) {
11650                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11651                               encoder->base.base.id,
11652                               drm_get_encoder_name(&encoder->base));
11653
11654                 /* Connector is active, but has no active pipe. This is
11655                  * fallout from our resume register restoring. Disable
11656                  * the encoder manually again. */
11657                 if (encoder->base.crtc) {
11658                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11659                                       encoder->base.base.id,
11660                                       drm_get_encoder_name(&encoder->base));
11661                         encoder->disable(encoder);
11662                 }
11663
11664                 /* Inconsistent output/port/pipe state happens presumably due to
11665                  * a bug in one of the get_hw_state functions. Or someplace else
11666                  * in our code, like the register restore mess on resume. Clamp
11667                  * things to off as a safer default. */
11668                 list_for_each_entry(connector,
11669                                     &dev->mode_config.connector_list,
11670                                     base.head) {
11671                         if (connector->encoder != encoder)
11672                                 continue;
11673
11674                         intel_connector_break_all_links(connector);
11675                 }
11676         }
11677         /* Enabled encoders without active connectors will be fixed in
11678          * the crtc fixup. */
11679 }
11680
11681 void i915_redisable_vga_power_on(struct drm_device *dev)
11682 {
11683         struct drm_i915_private *dev_priv = dev->dev_private;
11684         u32 vga_reg = i915_vgacntrl_reg(dev);
11685
11686         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11687                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11688                 i915_disable_vga(dev);
11689         }
11690 }
11691
11692 void i915_redisable_vga(struct drm_device *dev)
11693 {
11694         struct drm_i915_private *dev_priv = dev->dev_private;
11695
11696         /* This function can be called both from intel_modeset_setup_hw_state or
11697          * at a very early point in our resume sequence, where the power well
11698          * structures are not yet restored. Since this function is at a very
11699          * paranoid "someone might have enabled VGA while we were not looking"
11700          * level, just check if the power well is enabled instead of trying to
11701          * follow the "don't touch the power well if we don't need it" policy
11702          * the rest of the driver uses. */
11703         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11704                 return;
11705
11706         i915_redisable_vga_power_on(dev);
11707 }
11708
11709 static bool primary_get_hw_state(struct intel_crtc *crtc)
11710 {
11711         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11712
11713         if (!crtc->active)
11714                 return false;
11715
11716         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11717 }
11718
11719 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11720 {
11721         struct drm_i915_private *dev_priv = dev->dev_private;
11722         enum pipe pipe;
11723         struct intel_crtc *crtc;
11724         struct intel_encoder *encoder;
11725         struct intel_connector *connector;
11726         int i;
11727
11728         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11729                             base.head) {
11730                 memset(&crtc->config, 0, sizeof(crtc->config));
11731
11732                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11733
11734                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11735                                                                  &crtc->config);
11736
11737                 crtc->base.enabled = crtc->active;
11738                 crtc->primary_enabled = primary_get_hw_state(crtc);
11739
11740                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11741                               crtc->base.base.id,
11742                               crtc->active ? "enabled" : "disabled");
11743         }
11744
11745         /* FIXME: Smash this into the new shared dpll infrastructure. */
11746         if (HAS_DDI(dev))
11747                 intel_ddi_setup_hw_pll_state(dev);
11748
11749         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11750                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11751
11752                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11753                 pll->active = 0;
11754                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11755                                     base.head) {
11756                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11757                                 pll->active++;
11758                 }
11759                 pll->refcount = pll->active;
11760
11761                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11762                               pll->name, pll->refcount, pll->on);
11763         }
11764
11765         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11766                             base.head) {
11767                 pipe = 0;
11768
11769                 if (encoder->get_hw_state(encoder, &pipe)) {
11770                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11771                         encoder->base.crtc = &crtc->base;
11772                         encoder->get_config(encoder, &crtc->config);
11773                 } else {
11774                         encoder->base.crtc = NULL;
11775                 }
11776
11777                 encoder->connectors_active = false;
11778                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11779                               encoder->base.base.id,
11780                               drm_get_encoder_name(&encoder->base),
11781                               encoder->base.crtc ? "enabled" : "disabled",
11782                               pipe_name(pipe));
11783         }
11784
11785         list_for_each_entry(connector, &dev->mode_config.connector_list,
11786                             base.head) {
11787                 if (connector->get_hw_state(connector)) {
11788                         connector->base.dpms = DRM_MODE_DPMS_ON;
11789                         connector->encoder->connectors_active = true;
11790                         connector->base.encoder = &connector->encoder->base;
11791                 } else {
11792                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11793                         connector->base.encoder = NULL;
11794                 }
11795                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11796                               connector->base.base.id,
11797                               drm_get_connector_name(&connector->base),
11798                               connector->base.encoder ? "enabled" : "disabled");
11799         }
11800 }
11801
11802 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11803  * and i915 state tracking structures. */
11804 void intel_modeset_setup_hw_state(struct drm_device *dev,
11805                                   bool force_restore)
11806 {
11807         struct drm_i915_private *dev_priv = dev->dev_private;
11808         enum pipe pipe;
11809         struct intel_crtc *crtc;
11810         struct intel_encoder *encoder;
11811         int i;
11812
11813         intel_modeset_readout_hw_state(dev);
11814
11815         /*
11816          * Now that we have the config, copy it to each CRTC struct
11817          * Note that this could go away if we move to using crtc_config
11818          * checking everywhere.
11819          */
11820         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11821                             base.head) {
11822                 if (crtc->active && i915.fastboot) {
11823                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11824                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11825                                       crtc->base.base.id);
11826                         drm_mode_debug_printmodeline(&crtc->base.mode);
11827                 }
11828         }
11829
11830         /* HW state is read out, now we need to sanitize this mess. */
11831         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11832                             base.head) {
11833                 intel_sanitize_encoder(encoder);
11834         }
11835
11836         for_each_pipe(pipe) {
11837                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11838                 intel_sanitize_crtc(crtc);
11839                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11840         }
11841
11842         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11843                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11844
11845                 if (!pll->on || pll->active)
11846                         continue;
11847
11848                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11849
11850                 pll->disable(dev_priv, pll);
11851                 pll->on = false;
11852         }
11853
11854         if (HAS_PCH_SPLIT(dev))
11855                 ilk_wm_get_hw_state(dev);
11856
11857         if (force_restore) {
11858                 i915_redisable_vga(dev);
11859
11860                 /*
11861                  * We need to use raw interfaces for restoring state to avoid
11862                  * checking (bogus) intermediate states.
11863                  */
11864                 for_each_pipe(pipe) {
11865                         struct drm_crtc *crtc =
11866                                 dev_priv->pipe_to_crtc_mapping[pipe];
11867
11868                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11869                                          crtc->primary->fb);
11870                 }
11871         } else {
11872                 intel_modeset_update_staged_output_state(dev);
11873         }
11874
11875         intel_modeset_check_state(dev);
11876 }
11877
11878 void intel_modeset_gem_init(struct drm_device *dev)
11879 {
11880         struct drm_crtc *c;
11881         struct intel_framebuffer *fb;
11882
11883         mutex_lock(&dev->struct_mutex);
11884         intel_init_gt_powersave(dev);
11885         mutex_unlock(&dev->struct_mutex);
11886
11887         intel_modeset_init_hw(dev);
11888
11889         intel_setup_overlay(dev);
11890
11891         /*
11892          * Make sure any fbs we allocated at startup are properly
11893          * pinned & fenced.  When we do the allocation it's too early
11894          * for this.
11895          */
11896         mutex_lock(&dev->struct_mutex);
11897         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
11898                 if (!c->primary->fb)
11899                         continue;
11900
11901                 fb = to_intel_framebuffer(c->primary->fb);
11902                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
11903                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
11904                                   to_intel_crtc(c)->pipe);
11905                         drm_framebuffer_unreference(c->primary->fb);
11906                         c->primary->fb = NULL;
11907                 }
11908         }
11909         mutex_unlock(&dev->struct_mutex);
11910 }
11911
11912 void intel_connector_unregister(struct intel_connector *intel_connector)
11913 {
11914         struct drm_connector *connector = &intel_connector->base;
11915
11916         intel_panel_destroy_backlight(connector);
11917         drm_sysfs_connector_remove(connector);
11918 }
11919
11920 void intel_modeset_cleanup(struct drm_device *dev)
11921 {
11922         struct drm_i915_private *dev_priv = dev->dev_private;
11923         struct drm_crtc *crtc;
11924         struct drm_connector *connector;
11925
11926         /*
11927          * Interrupts and polling as the first thing to avoid creating havoc.
11928          * Too much stuff here (turning of rps, connectors, ...) would
11929          * experience fancy races otherwise.
11930          */
11931         drm_irq_uninstall(dev);
11932         cancel_work_sync(&dev_priv->hotplug_work);
11933         /*
11934          * Due to the hpd irq storm handling the hotplug work can re-arm the
11935          * poll handlers. Hence disable polling after hpd handling is shut down.
11936          */
11937         drm_kms_helper_poll_fini(dev);
11938
11939         mutex_lock(&dev->struct_mutex);
11940
11941         intel_unregister_dsm_handler();
11942
11943         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11944                 /* Skip inactive CRTCs */
11945                 if (!crtc->primary->fb)
11946                         continue;
11947
11948                 intel_increase_pllclock(crtc);
11949         }
11950
11951         intel_disable_fbc(dev);
11952
11953         intel_disable_gt_powersave(dev);
11954
11955         ironlake_teardown_rc6(dev);
11956
11957         mutex_unlock(&dev->struct_mutex);
11958
11959         /* flush any delayed tasks or pending work */
11960         flush_scheduled_work();
11961
11962         /* destroy the backlight and sysfs files before encoders/connectors */
11963         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11964                 struct intel_connector *intel_connector;
11965
11966                 intel_connector = to_intel_connector(connector);
11967                 intel_connector->unregister(intel_connector);
11968         }
11969
11970         drm_mode_config_cleanup(dev);
11971
11972         intel_cleanup_overlay(dev);
11973
11974         mutex_lock(&dev->struct_mutex);
11975         intel_cleanup_gt_powersave(dev);
11976         mutex_unlock(&dev->struct_mutex);
11977 }
11978
11979 /*
11980  * Return which encoder is currently attached for connector.
11981  */
11982 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11983 {
11984         return &intel_attached_encoder(connector)->base;
11985 }
11986
11987 void intel_connector_attach_encoder(struct intel_connector *connector,
11988                                     struct intel_encoder *encoder)
11989 {
11990         connector->encoder = encoder;
11991         drm_mode_connector_attach_encoder(&connector->base,
11992                                           &encoder->base);
11993 }
11994
11995 /*
11996  * set vga decode state - true == enable VGA decode
11997  */
11998 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11999 {
12000         struct drm_i915_private *dev_priv = dev->dev_private;
12001         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12002         u16 gmch_ctrl;
12003
12004         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12005                 DRM_ERROR("failed to read control word\n");
12006                 return -EIO;
12007         }
12008
12009         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12010                 return 0;
12011
12012         if (state)
12013                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12014         else
12015                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12016
12017         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12018                 DRM_ERROR("failed to write control word\n");
12019                 return -EIO;
12020         }
12021
12022         return 0;
12023 }
12024
12025 struct intel_display_error_state {
12026
12027         u32 power_well_driver;
12028
12029         int num_transcoders;
12030
12031         struct intel_cursor_error_state {
12032                 u32 control;
12033                 u32 position;
12034                 u32 base;
12035                 u32 size;
12036         } cursor[I915_MAX_PIPES];
12037
12038         struct intel_pipe_error_state {
12039                 bool power_domain_on;
12040                 u32 source;
12041                 u32 stat;
12042         } pipe[I915_MAX_PIPES];
12043
12044         struct intel_plane_error_state {
12045                 u32 control;
12046                 u32 stride;
12047                 u32 size;
12048                 u32 pos;
12049                 u32 addr;
12050                 u32 surface;
12051                 u32 tile_offset;
12052         } plane[I915_MAX_PIPES];
12053
12054         struct intel_transcoder_error_state {
12055                 bool power_domain_on;
12056                 enum transcoder cpu_transcoder;
12057
12058                 u32 conf;
12059
12060                 u32 htotal;
12061                 u32 hblank;
12062                 u32 hsync;
12063                 u32 vtotal;
12064                 u32 vblank;
12065                 u32 vsync;
12066         } transcoder[4];
12067 };
12068
12069 struct intel_display_error_state *
12070 intel_display_capture_error_state(struct drm_device *dev)
12071 {
12072         struct drm_i915_private *dev_priv = dev->dev_private;
12073         struct intel_display_error_state *error;
12074         int transcoders[] = {
12075                 TRANSCODER_A,
12076                 TRANSCODER_B,
12077                 TRANSCODER_C,
12078                 TRANSCODER_EDP,
12079         };
12080         int i;
12081
12082         if (INTEL_INFO(dev)->num_pipes == 0)
12083                 return NULL;
12084
12085         error = kzalloc(sizeof(*error), GFP_ATOMIC);
12086         if (error == NULL)
12087                 return NULL;
12088
12089         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12090                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12091
12092         for_each_pipe(i) {
12093                 error->pipe[i].power_domain_on =
12094                         intel_display_power_enabled_sw(dev_priv,
12095                                                        POWER_DOMAIN_PIPE(i));
12096                 if (!error->pipe[i].power_domain_on)
12097                         continue;
12098
12099                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
12100                         error->cursor[i].control = I915_READ(CURCNTR(i));
12101                         error->cursor[i].position = I915_READ(CURPOS(i));
12102                         error->cursor[i].base = I915_READ(CURBASE(i));
12103                 } else {
12104                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
12105                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
12106                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
12107                 }
12108
12109                 error->plane[i].control = I915_READ(DSPCNTR(i));
12110                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12111                 if (INTEL_INFO(dev)->gen <= 3) {
12112                         error->plane[i].size = I915_READ(DSPSIZE(i));
12113                         error->plane[i].pos = I915_READ(DSPPOS(i));
12114                 }
12115                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12116                         error->plane[i].addr = I915_READ(DSPADDR(i));
12117                 if (INTEL_INFO(dev)->gen >= 4) {
12118                         error->plane[i].surface = I915_READ(DSPSURF(i));
12119                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12120                 }
12121
12122                 error->pipe[i].source = I915_READ(PIPESRC(i));
12123
12124                 if (!HAS_PCH_SPLIT(dev))
12125                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12126         }
12127
12128         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12129         if (HAS_DDI(dev_priv->dev))
12130                 error->num_transcoders++; /* Account for eDP. */
12131
12132         for (i = 0; i < error->num_transcoders; i++) {
12133                 enum transcoder cpu_transcoder = transcoders[i];
12134
12135                 error->transcoder[i].power_domain_on =
12136                         intel_display_power_enabled_sw(dev_priv,
12137                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12138                 if (!error->transcoder[i].power_domain_on)
12139                         continue;
12140
12141                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12142
12143                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12144                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12145                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12146                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12147                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12148                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12149                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12150         }
12151
12152         return error;
12153 }
12154
12155 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12156
12157 void
12158 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12159                                 struct drm_device *dev,
12160                                 struct intel_display_error_state *error)
12161 {
12162         int i;
12163
12164         if (!error)
12165                 return;
12166
12167         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12168         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12169                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12170                            error->power_well_driver);
12171         for_each_pipe(i) {
12172                 err_printf(m, "Pipe [%d]:\n", i);
12173                 err_printf(m, "  Power: %s\n",
12174                            error->pipe[i].power_domain_on ? "on" : "off");
12175                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12176                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12177
12178                 err_printf(m, "Plane [%d]:\n", i);
12179                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12180                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12181                 if (INTEL_INFO(dev)->gen <= 3) {
12182                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12183                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12184                 }
12185                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12186                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12187                 if (INTEL_INFO(dev)->gen >= 4) {
12188                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12189                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12190                 }
12191
12192                 err_printf(m, "Cursor [%d]:\n", i);
12193                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12194                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12195                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12196         }
12197
12198         for (i = 0; i < error->num_transcoders; i++) {
12199                 err_printf(m, "CPU transcoder: %c\n",
12200                            transcoder_name(error->transcoder[i].cpu_transcoder));
12201                 err_printf(m, "  Power: %s\n",
12202                            error->transcoder[i].power_domain_on ? "on" : "off");
12203                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12204                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12205                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12206                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12207                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12208                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12209                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12210         }
12211 }