drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic_helper.h>
  41 #include <drm/drm_dp_helper.h>
  42 #include <drm/drm_crtc_helper.h>
  43 #include <drm/drm_plane_helper.h>
  44 #include <drm/drm_rect.h>
  45 #include <linux/dma_remapping.h>
  46
  47 /* Primary plane formats supported by all gen */
  48 #define COMMON_PRIMARY_FORMATS \
  49         DRM_FORMAT_C8, \
  50         DRM_FORMAT_RGB565, \
  51         DRM_FORMAT_XRGB8888, \
  52         DRM_FORMAT_ARGB8888
  53
  54 /* Primary plane formats for gen <= 3 */
  55 static const uint32_t intel_primary_formats_gen2[] = {
  56         COMMON_PRIMARY_FORMATS,
  57         DRM_FORMAT_XRGB1555,
  58         DRM_FORMAT_ARGB1555,
  59 };
  60
  61 /* Primary plane formats for gen >= 4 */
  62 static const uint32_t intel_primary_formats_gen4[] = {
  63         COMMON_PRIMARY_FORMATS, \
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_ABGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_ARGB2101010,
  68         DRM_FORMAT_XBGR2101010,
  69         DRM_FORMAT_ABGR2101010,
  70 };
  71
  72 /* Cursor formats */
  73 static const uint32_t intel_cursor_formats[] = {
  74         DRM_FORMAT_ARGB8888,
  75 };
  76
  77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  78
  79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  80                                 struct intel_crtc_state *pipe_config);
  81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  82                                    struct intel_crtc_state *pipe_config);
  83
  84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  85                           int x, int y, struct drm_framebuffer *old_fb);
  86 static int intel_framebuffer_init(struct drm_device *dev,
  87                                   struct intel_framebuffer *ifb,
  88                                   struct drm_mode_fb_cmd2 *mode_cmd,
  89                                   struct drm_i915_gem_object *obj);
  90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  93                                          struct intel_link_m_n *m_n,
  94                                          struct intel_link_m_n *m2_n2);
  95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  98 static void vlv_prepare_pll(struct intel_crtc *crtc,
  99                             const struct intel_crtc_state *pipe_config);
 100 static void chv_prepare_pll(struct intel_crtc *crtc,
 101                             const struct intel_crtc_state *pipe_config);
 102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 104
 105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 106 {
 107         if (!connector->mst_port)
 108                 return connector->encoder;
 109         else
 110                 return &connector->mst_port->mst_encoders[pipe]->base;
 111 }
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4860000, .max = 6700000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static void vlv_clock(int refclk, intel_clock_t *clock)
 402 {
 403         clock->m = clock->m1 * clock->m2;
 404         clock->p = clock->p1 * clock->p2;
 405         if (WARN_ON(clock->n == 0 || clock->p == 0))
 406                 return;
 407         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 408         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 409 }
 410
 411 /**
 412  * Returns whether any output on the specified pipe is of the specified type
 413  */
 414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 415 {
 416         struct drm_device *dev = crtc->base.dev;
 417         struct intel_encoder *encoder;
 418
 419         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 420                 if (encoder->type == type)
 421                         return true;
 422
 423         return false;
 424 }
 425
 426 /**
 427  * Returns whether any output on the specified pipe will have the specified
 428  * type after a staged modeset is complete, i.e., the same as
 429  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 430  * encoder->crtc.
 431  */
 432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 433 {
 434         struct drm_device *dev = crtc->base.dev;
 435         struct intel_encoder *encoder;
 436
 437         for_each_intel_encoder(dev, encoder)
 438                 if (encoder->new_crtc == crtc && encoder->type == type)
 439                         return true;
 440
 441         return false;
 442 }
 443
 444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 445                                                 int refclk)
 446 {
 447         struct drm_device *dev = crtc->base.dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev)) {
 452                         if (refclk == 100000)
 453                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 454                         else
 455                                 limit = &intel_limits_ironlake_dual_lvds;
 456                 } else {
 457                         if (refclk == 100000)
 458                                 limit = &intel_limits_ironlake_single_lvds_100m;
 459                         else
 460                                 limit = &intel_limits_ironlake_single_lvds;
 461                 }
 462         } else
 463                 limit = &intel_limits_ironlake_dac;
 464
 465         return limit;
 466 }
 467
 468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 469 {
 470         struct drm_device *dev = crtc->base.dev;
 471         const intel_limit_t *limit;
 472
 473         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 474                 if (intel_is_dual_link_lvds(dev))
 475                         limit = &intel_limits_g4x_dual_channel_lvds;
 476                 else
 477                         limit = &intel_limits_g4x_single_channel_lvds;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 479                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 480                 limit = &intel_limits_g4x_hdmi;
 481         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 482                 limit = &intel_limits_g4x_sdvo;
 483         } else /* The option is for other outputs */
 484                 limit = &intel_limits_i9xx_sdvo;
 485
 486         return limit;
 487 }
 488
 489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 490 {
 491         struct drm_device *dev = crtc->base.dev;
 492         const intel_limit_t *limit;
 493
 494         if (HAS_PCH_SPLIT(dev))
 495                 limit = intel_ironlake_limit(crtc, refclk);
 496         else if (IS_G4X(dev)) {
 497                 limit = intel_g4x_limit(crtc);
 498         } else if (IS_PINEVIEW(dev)) {
 499                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 500                         limit = &intel_limits_pineview_lvds;
 501                 else
 502                         limit = &intel_limits_pineview_sdvo;
 503         } else if (IS_CHERRYVIEW(dev)) {
 504                 limit = &intel_limits_chv;
 505         } else if (IS_VALLEYVIEW(dev)) {
 506                 limit = &intel_limits_vlv;
 507         } else if (!IS_GEN2(dev)) {
 508                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 509                         limit = &intel_limits_i9xx_lvds;
 510                 else
 511                         limit = &intel_limits_i9xx_sdvo;
 512         } else {
 513                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 514                         limit = &intel_limits_i8xx_lvds;
 515                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 516                         limit = &intel_limits_i8xx_dvo;
 517                 else
 518                         limit = &intel_limits_i8xx_dac;
 519         }
 520         return limit;
 521 }
 522
 523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 524 static void pineview_clock(int refclk, intel_clock_t *clock)
 525 {
 526         clock->m = clock->m2 + 2;
 527         clock->p = clock->p1 * clock->p2;
 528         if (WARN_ON(clock->n == 0 || clock->p == 0))
 529                 return;
 530         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 531         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 532 }
 533
 534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 535 {
 536         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 537 }
 538
 539 static void i9xx_clock(int refclk, intel_clock_t *clock)
 540 {
 541         clock->m = i9xx_dpll_compute_m(clock);
 542         clock->p = clock->p1 * clock->p2;
 543         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 544                 return;
 545         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 546         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 547 }
 548
 549 static void chv_clock(int refclk, intel_clock_t *clock)
 550 {
 551         clock->m = clock->m1 * clock->m2;
 552         clock->p = clock->p1 * clock->p2;
 553         if (WARN_ON(clock->n == 0 || clock->p == 0))
 554                 return;
 555         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 556                         clock->n << 22);
 557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 558 }
 559
 560 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 561 /**
 562  * Returns whether the given set of divisors are valid for a given refclk with
 563  * the given connectors.
 564  */
 565
 566 static bool intel_PLL_is_valid(struct drm_device *dev,
 567                                const intel_limit_t *limit,
 568                                const intel_clock_t *clock)
 569 {
 570         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 571                 INTELPllInvalid("n out of range\n");
 572         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 573                 INTELPllInvalid("p1 out of range\n");
 574         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 575                 INTELPllInvalid("m2 out of range\n");
 576         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 577                 INTELPllInvalid("m1 out of range\n");
 578
 579         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 580                 if (clock->m1 <= clock->m2)
 581                         INTELPllInvalid("m1 <= m2\n");
 582
 583         if (!IS_VALLEYVIEW(dev)) {
 584                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 585                         INTELPllInvalid("p out of range\n");
 586                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 587                         INTELPllInvalid("m out of range\n");
 588         }
 589
 590         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 591                 INTELPllInvalid("vco out of range\n");
 592         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 593          * connector, etc., rather than just a single range.
 594          */
 595         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 596                 INTELPllInvalid("dot out of range\n");
 597
 598         return true;
 599 }
 600
 601 static bool
 602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 603                     int target, int refclk, intel_clock_t *match_clock,
 604                     intel_clock_t *best_clock)
 605 {
 606         struct drm_device *dev = crtc->base.dev;
 607         intel_clock_t clock;
 608         int err = target;
 609
 610         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 611                 /*
 612                  * For LVDS just rely on its current settings for dual-channel.
 613                  * We haven't figured out how to reliably set up different
 614                  * single/dual channel state, if we even can.
 615                  */
 616                 if (intel_is_dual_link_lvds(dev))
 617                         clock.p2 = limit->p2.p2_fast;
 618                 else
 619                         clock.p2 = limit->p2.p2_slow;
 620         } else {
 621                 if (target < limit->p2.dot_limit)
 622                         clock.p2 = limit->p2.p2_slow;
 623                 else
 624                         clock.p2 = limit->p2.p2_fast;
 625         }
 626
 627         memset(best_clock, 0, sizeof(*best_clock));
 628
 629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 630              clock.m1++) {
 631                 for (clock.m2 = limit->m2.min;
 632                      clock.m2 <= limit->m2.max; clock.m2++) {
 633                         if (clock.m2 >= clock.m1)
 634                                 break;
 635                         for (clock.n = limit->n.min;
 636                              clock.n <= limit->n.max; clock.n++) {
 637                                 for (clock.p1 = limit->p1.min;
 638                                         clock.p1 <= limit->p1.max; clock.p1++) {
 639                                         int this_err;
 640
 641                                         i9xx_clock(refclk, &clock);
 642                                         if (!intel_PLL_is_valid(dev, limit,
 643                                                                 &clock))
 644                                                 continue;
 645                                         if (match_clock &&
 646                                             clock.p != match_clock->p)
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err) {
 651                                                 *best_clock = clock;
 652                                                 err = this_err;
 653                                         }
 654                                 }
 655                         }
 656                 }
 657         }
 658
 659         return (err != target);
 660 }
 661
 662 static bool
 663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 664                    int target, int refclk, intel_clock_t *match_clock,
 665                    intel_clock_t *best_clock)
 666 {
 667         struct drm_device *dev = crtc->base.dev;
 668         intel_clock_t clock;
 669         int err = target;
 670
 671         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 672                 /*
 673                  * For LVDS just rely on its current settings for dual-channel.
 674                  * We haven't figured out how to reliably set up different
 675                  * single/dual channel state, if we even can.
 676                  */
 677                 if (intel_is_dual_link_lvds(dev))
 678                         clock.p2 = limit->p2.p2_fast;
 679                 else
 680                         clock.p2 = limit->p2.p2_slow;
 681         } else {
 682                 if (target < limit->p2.dot_limit)
 683                         clock.p2 = limit->p2.p2_slow;
 684                 else
 685                         clock.p2 = limit->p2.p2_fast;
 686         }
 687
 688         memset(best_clock, 0, sizeof(*best_clock));
 689
 690         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 691              clock.m1++) {
 692                 for (clock.m2 = limit->m2.min;
 693                      clock.m2 <= limit->m2.max; clock.m2++) {
 694                         for (clock.n = limit->n.min;
 695                              clock.n <= limit->n.max; clock.n++) {
 696                                 for (clock.p1 = limit->p1.min;
 697                                         clock.p1 <= limit->p1.max; clock.p1++) {
 698                                         int this_err;
 699
 700                                         pineview_clock(refclk, &clock);
 701                                         if (!intel_PLL_is_valid(dev, limit,
 702                                                                 &clock))
 703                                                 continue;
 704                                         if (match_clock &&
 705                                             clock.p != match_clock->p)
 706                                                 continue;
 707
 708                                         this_err = abs(clock.dot - target);
 709                                         if (this_err < err) {
 710                                                 *best_clock = clock;
 711                                                 err = this_err;
 712                                         }
 713                                 }
 714                         }
 715                 }
 716         }
 717
 718         return (err != target);
 719 }
 720
 721 static bool
 722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 723                    int target, int refclk, intel_clock_t *match_clock,
 724                    intel_clock_t *best_clock)
 725 {
 726         struct drm_device *dev = crtc->base.dev;
 727         intel_clock_t clock;
 728         int max_n;
 729         bool found;
 730         /* approximately equals target * 0.00585 */
 731         int err_most = (target >> 8) + (target >> 9);
 732         found = false;
 733
 734         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 735                 if (intel_is_dual_link_lvds(dev))
 736                         clock.p2 = limit->p2.p2_fast;
 737                 else
 738                         clock.p2 = limit->p2.p2_slow;
 739         } else {
 740                 if (target < limit->p2.dot_limit)
 741                         clock.p2 = limit->p2.p2_slow;
 742                 else
 743                         clock.p2 = limit->p2.p2_fast;
 744         }
 745
 746         memset(best_clock, 0, sizeof(*best_clock));
 747         max_n = limit->n.max;
 748         /* based on hardware requirement, prefer smaller n to precision */
 749         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 750                 /* based on hardware requirement, prefere larger m1,m2 */
 751                 for (clock.m1 = limit->m1.max;
 752                      clock.m1 >= limit->m1.min; clock.m1--) {
 753                         for (clock.m2 = limit->m2.max;
 754                              clock.m2 >= limit->m2.min; clock.m2--) {
 755                                 for (clock.p1 = limit->p1.max;
 756                                      clock.p1 >= limit->p1.min; clock.p1--) {
 757                                         int this_err;
 758
 759                                         i9xx_clock(refclk, &clock);
 760                                         if (!intel_PLL_is_valid(dev, limit,
 761                                                                 &clock))
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err_most) {
 766                                                 *best_clock = clock;
 767                                                 err_most = this_err;
 768                                                 max_n = clock.n;
 769                                                 found = true;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775         return found;
 776 }
 777
 778 static bool
 779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 780                    int target, int refclk, intel_clock_t *match_clock,
 781                    intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->base.dev;
 784         intel_clock_t clock;
 785         unsigned int bestppm = 1000000;
 786         /* min update 19.2 MHz */
 787         int max_n = min(limit->n.max, refclk / 19200);
 788         bool found = false;
 789
 790         target *= 5; /* fast clock */
 791
 792         memset(best_clock, 0, sizeof(*best_clock));
 793
 794         /* based on hardware requirement, prefer smaller n to precision */
 795         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 796                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 797                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 798                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 799                                 clock.p = clock.p1 * clock.p2;
 800                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 801                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 802                                         unsigned int ppm, diff;
 803
 804                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 805                                                                      refclk * clock.m1);
 806
 807                                         vlv_clock(refclk, &clock);
 808
 809                                         if (!intel_PLL_is_valid(dev, limit,
 810                                                                 &clock))
 811                                                 continue;
 812
 813                                         diff = abs(clock.dot - target);
 814                                         ppm = div_u64(1000000ULL * diff, target);
 815
 816                                         if (ppm < 100 && clock.p > best_clock->p) {
 817                                                 bestppm = 0;
 818                                                 *best_clock = clock;
 819                                                 found = true;
 820                                         }
 821
 822                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 823                                                 bestppm = ppm;
 824                                                 *best_clock = clock;
 825                                                 found = true;
 826                                         }
 827                                 }
 828                         }
 829                 }
 830         }
 831
 832         return found;
 833 }
 834
 835 static bool
 836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 837                    int target, int refclk, intel_clock_t *match_clock,
 838                    intel_clock_t *best_clock)
 839 {
 840         struct drm_device *dev = crtc->base.dev;
 841         intel_clock_t clock;
 842         uint64_t m2;
 843         int found = false;
 844
 845         memset(best_clock, 0, sizeof(*best_clock));
 846
 847         /*
 848          * Based on hardware doc, the n always set to 1, and m1 always
 849          * set to 2.  If requires to support 200Mhz refclk, we need to
 850          * revisit this because n may not 1 anymore.
 851          */
 852         clock.n = 1, clock.m1 = 2;
 853         target *= 5;    /* fast clock */
 854
 855         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 856                 for (clock.p2 = limit->p2.p2_fast;
 857                                 clock.p2 >= limit->p2.p2_slow;
 858                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 859
 860                         clock.p = clock.p1 * clock.p2;
 861
 862                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 863                                         clock.n) << 22, refclk * clock.m1);
 864
 865                         if (m2 > INT_MAX/clock.m1)
 866                                 continue;
 867
 868                         clock.m2 = m2;
 869
 870                         chv_clock(refclk, &clock);
 871
 872                         if (!intel_PLL_is_valid(dev, limit, &clock))
 873                                 continue;
 874
 875                         /* based on hardware requirement, prefer bigger p
 876                          */
 877                         if (clock.p > best_clock->p) {
 878                                 *best_clock = clock;
 879                                 found = true;
 880                         }
 881                 }
 882         }
 883
 884         return found;
 885 }
 886
 887 bool intel_crtc_active(struct drm_crtc *crtc)
 888 {
 889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 890
 891         /* Be paranoid as we can arrive here with only partial
 892          * state retrieved from the hardware during setup.
 893          *
 894          * We can ditch the adjusted_mode.crtc_clock check as soon
 895          * as Haswell has gained clock readout/fastboot support.
 896          *
 897          * We can ditch the crtc->primary->fb check as soon as we can
 898          * properly reconstruct framebuffers.
 899          */
 900         return intel_crtc->active && crtc->primary->fb &&
 901                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 902 }
 903
 904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 905                                              enum pipe pipe)
 906 {
 907         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 909
 910         return intel_crtc->config->cpu_transcoder;
 911 }
 912
 913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 914 {
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         u32 reg = PIPEDSL(pipe);
 917         u32 line1, line2;
 918         u32 line_mask;
 919
 920         if (IS_GEN2(dev))
 921                 line_mask = DSL_LINEMASK_GEN2;
 922         else
 923                 line_mask = DSL_LINEMASK_GEN3;
 924
 925         line1 = I915_READ(reg) & line_mask;
 926         mdelay(5);
 927         line2 = I915_READ(reg) & line_mask;
 928
 929         return line1 == line2;
 930 }
 931
 932 /*
 933  * intel_wait_for_pipe_off - wait for pipe to turn off
 934  * @crtc: crtc whose pipe to wait for
 935  *
 936  * After disabling a pipe, we can't wait for vblank in the usual way,
 937  * spinning on the vblank interrupt status bit, since we won't actually
 938  * see an interrupt when the pipe is disabled.
 939  *
 940  * On Gen4 and above:
 941  *   wait for the pipe register state bit to turn off
 942  *
 943  * Otherwise:
 944  *   wait for the display line value to settle (it usually
 945  *   ends up stopping at the start of the next frame).
 946  *
 947  */
 948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 949 {
 950         struct drm_device *dev = crtc->base.dev;
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
 953         enum pipe pipe = crtc->pipe;
 954
 955         if (INTEL_INFO(dev)->gen >= 4) {
 956                 int reg = PIPECONF(cpu_transcoder);
 957
 958                 /* Wait for the Pipe State to go off */
 959                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 960                              100))
 961                         WARN(1, "pipe_off wait timed out\n");
 962         } else {
 963                 /* Wait for the display line to settle */
 964                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 965                         WARN(1, "pipe_off wait timed out\n");
 966         }
 967 }
 968
 969 /*
 970  * ibx_digital_port_connected - is the specified port connected?
 971  * @dev_priv: i915 private structure
 972  * @port: the port to test
 973  *
 974  * Returns true if @port is connected, false otherwise.
 975  */
 976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 977                                 struct intel_digital_port *port)
 978 {
 979         u32 bit;
 980
 981         if (HAS_PCH_IBX(dev_priv->dev)) {
 982                 switch (port->port) {
 983                 case PORT_B:
 984                         bit = SDE_PORTB_HOTPLUG;
 985                         break;
 986                 case PORT_C:
 987                         bit = SDE_PORTC_HOTPLUG;
 988                         break;
 989                 case PORT_D:
 990                         bit = SDE_PORTD_HOTPLUG;
 991                         break;
 992                 default:
 993                         return true;
 994                 }
 995         } else {
 996                 switch (port->port) {
 997                 case PORT_B:
 998                         bit = SDE_PORTB_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_C:
1001                         bit = SDE_PORTC_HOTPLUG_CPT;
1002                         break;
1003                 case PORT_D:
1004                         bit = SDE_PORTD_HOTPLUG_CPT;
1005                         break;
1006                 default:
1007                         return true;
1008                 }
1009         }
1010
1011         return I915_READ(SDEISR) & bit;
1012 }
1013
1014 static const char *state_string(bool enabled)
1015 {
1016         return enabled ? "on" : "off";
1017 }
1018
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021                 enum pipe pipe, bool state)
1022 {
1023         int reg;
1024         u32 val;
1025         bool cur_state;
1026
1027         reg = DPLL(pipe);
1028         val = I915_READ(reg);
1029         cur_state = !!(val & DPLL_VCO_ENABLE);
1030         I915_STATE_WARN(cur_state != state,
1031              "PLL state assertion failure (expected %s, current %s)\n",
1032              state_string(state), state_string(cur_state));
1033 }
1034
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037 {
1038         u32 val;
1039         bool cur_state;
1040
1041         mutex_lock(&dev_priv->dpio_lock);
1042         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043         mutex_unlock(&dev_priv->dpio_lock);
1044
1045         cur_state = val & DSI_PLL_VCO_EN;
1046         I915_STATE_WARN(cur_state != state,
1047              "DSI PLL state assertion failure (expected %s, current %s)\n",
1048              state_string(state), state_string(cur_state));
1049 }
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055 {
1056         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
1058         if (crtc->config->shared_dpll < 0)
1059                 return NULL;
1060
1061         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1062 }
1063
1064 /* For ILK+ */
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066                         struct intel_shared_dpll *pll,
1067                         bool state)
1068 {
1069         bool cur_state;
1070         struct intel_dpll_hw_state hw_state;
1071
1072         if (WARN (!pll,
1073                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1074                 return;
1075
1076         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077         I915_STATE_WARN(cur_state != state,
1078              "%s assertion failure (expected %s, current %s)\n",
1079              pll->name, state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083                           enum pipe pipe, bool state)
1084 {
1085         int reg;
1086         u32 val;
1087         bool cur_state;
1088         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089                                                                       pipe);
1090
1091         if (HAS_DDI(dev_priv->dev)) {
1092                 /* DDI does not have a specific FDI_TX register */
1093                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094                 val = I915_READ(reg);
1095                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1096         } else {
1097                 reg = FDI_TX_CTL(pipe);
1098                 val = I915_READ(reg);
1099                 cur_state = !!(val & FDI_TX_ENABLE);
1100         }
1101         I915_STATE_WARN(cur_state != state,
1102              "FDI TX state assertion failure (expected %s, current %s)\n",
1103              state_string(state), state_string(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109                           enum pipe pipe, bool state)
1110 {
1111         int reg;
1112         u32 val;
1113         bool cur_state;
1114
1115         reg = FDI_RX_CTL(pipe);
1116         val = I915_READ(reg);
1117         cur_state = !!(val & FDI_RX_ENABLE);
1118         I915_STATE_WARN(cur_state != state,
1119              "FDI RX state assertion failure (expected %s, current %s)\n",
1120              state_string(state), state_string(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126                                       enum pipe pipe)
1127 {
1128         int reg;
1129         u32 val;
1130
1131         /* ILK FDI PLL is always enabled */
1132         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1133                 return;
1134
1135         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136         if (HAS_DDI(dev_priv->dev))
1137                 return;
1138
1139         reg = FDI_TX_CTL(pipe);
1140         val = I915_READ(reg);
1141         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142 }
1143
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145                        enum pipe pipe, bool state)
1146 {
1147         int reg;
1148         u32 val;
1149         bool cur_state;
1150
1151         reg = FDI_RX_CTL(pipe);
1152         val = I915_READ(reg);
1153         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154         I915_STATE_WARN(cur_state != state,
1155              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156              state_string(state), state_string(cur_state));
1157 }
1158
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160                            enum pipe pipe)
1161 {
1162         struct drm_device *dev = dev_priv->dev;
1163         int pp_reg;
1164         u32 val;
1165         enum pipe panel_pipe = PIPE_A;
1166         bool locked = true;
1167
1168         if (WARN_ON(HAS_DDI(dev)))
1169                 return;
1170
1171         if (HAS_PCH_SPLIT(dev)) {
1172                 u32 port_sel;
1173
1174                 pp_reg = PCH_PP_CONTROL;
1175                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179                         panel_pipe = PIPE_B;
1180                 /* XXX: else fix for eDP */
1181         } else if (IS_VALLEYVIEW(dev)) {
1182                 /* presumably write lock depends on pipe, not port select */
1183                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184                 panel_pipe = pipe;
1185         } else {
1186                 pp_reg = PP_CONTROL;
1187                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188                         panel_pipe = PIPE_B;
1189         }
1190
1191         val = I915_READ(pp_reg);
1192         if (!(val & PANEL_POWER_ON) ||
1193             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1194                 locked = false;
1195
1196         I915_STATE_WARN(panel_pipe == pipe && locked,
1197              "panel assertion failure, pipe %c regs locked\n",
1198              pipe_name(pipe));
1199 }
1200
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202                           enum pipe pipe, bool state)
1203 {
1204         struct drm_device *dev = dev_priv->dev;
1205         bool cur_state;
1206
1207         if (IS_845G(dev) || IS_I865G(dev))
1208                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1209         else
1210                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1211
1212         I915_STATE_WARN(cur_state != state,
1213              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214              pipe_name(pipe), state_string(state), state_string(cur_state));
1215 }
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220                  enum pipe pipe, bool state)
1221 {
1222         int reg;
1223         u32 val;
1224         bool cur_state;
1225         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226                                                                       pipe);
1227
1228         /* if we need the pipe quirk it must be always on */
1229         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1231                 state = true;
1232
1233         if (!intel_display_power_is_enabled(dev_priv,
1234                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1235                 cur_state = false;
1236         } else {
1237                 reg = PIPECONF(cpu_transcoder);
1238                 val = I915_READ(reg);
1239                 cur_state = !!(val & PIPECONF_ENABLE);
1240         }
1241
1242         I915_STATE_WARN(cur_state != state,
1243              "pipe %c assertion failure (expected %s, current %s)\n",
1244              pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248                          enum plane plane, bool state)
1249 {
1250         int reg;
1251         u32 val;
1252         bool cur_state;
1253
1254         reg = DSPCNTR(plane);
1255         val = I915_READ(reg);
1256         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257         I915_STATE_WARN(cur_state != state,
1258              "plane %c assertion failure (expected %s, current %s)\n",
1259              plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266                                    enum pipe pipe)
1267 {
1268         struct drm_device *dev = dev_priv->dev;
1269         int reg, i;
1270         u32 val;
1271         int cur_pipe;
1272
1273         /* Primary planes are fixed to pipes on gen4+ */
1274         if (INTEL_INFO(dev)->gen >= 4) {
1275                 reg = DSPCNTR(pipe);
1276                 val = I915_READ(reg);
1277                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278                      "plane %c assertion failure, should be disabled but not\n",
1279                      plane_name(pipe));
1280                 return;
1281         }
1282
1283         /* Need to check both planes against the pipe */
1284         for_each_pipe(dev_priv, i) {
1285                 reg = DSPCNTR(i);
1286                 val = I915_READ(reg);
1287                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288                         DISPPLANE_SEL_PIPE_SHIFT;
1289                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291                      plane_name(i), pipe_name(pipe));
1292         }
1293 }
1294
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296                                     enum pipe pipe)
1297 {
1298         struct drm_device *dev = dev_priv->dev;
1299         int reg, sprite;
1300         u32 val;
1301
1302         if (INTEL_INFO(dev)->gen >= 9) {
1303                 for_each_sprite(pipe, sprite) {
1304                         val = I915_READ(PLANE_CTL(pipe, sprite));
1305                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307                              sprite, pipe_name(pipe));
1308                 }
1309         } else if (IS_VALLEYVIEW(dev)) {
1310                 for_each_sprite(pipe, sprite) {
1311                         reg = SPCNTR(pipe, sprite);
1312                         val = I915_READ(reg);
1313                         I915_STATE_WARN(val & SP_ENABLE,
1314                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315                              sprite_name(pipe, sprite), pipe_name(pipe));
1316                 }
1317         } else if (INTEL_INFO(dev)->gen >= 7) {
1318                 reg = SPRCTL(pipe);
1319                 val = I915_READ(reg);
1320                 I915_STATE_WARN(val & SPRITE_ENABLE,
1321                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322                      plane_name(pipe), pipe_name(pipe));
1323         } else if (INTEL_INFO(dev)->gen >= 5) {
1324                 reg = DVSCNTR(pipe);
1325                 val = I915_READ(reg);
1326                 I915_STATE_WARN(val & DVS_ENABLE,
1327                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328                      plane_name(pipe), pipe_name(pipe));
1329         }
1330 }
1331
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1333 {
1334         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335                 drm_crtc_vblank_put(crtc);
1336 }
1337
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1339 {
1340         u32 val;
1341         bool enabled;
1342
1343         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1344
1345         val = I915_READ(PCH_DREF_CONTROL);
1346         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347                             DREF_SUPERSPREAD_SOURCE_MASK));
1348         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1349 }
1350
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352                                            enum pipe pipe)
1353 {
1354         int reg;
1355         u32 val;
1356         bool enabled;
1357
1358         reg = PCH_TRANSCONF(pipe);
1359         val = I915_READ(reg);
1360         enabled = !!(val & TRANS_ENABLE);
1361         I915_STATE_WARN(enabled,
1362              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363              pipe_name(pipe));
1364 }
1365
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367                             enum pipe pipe, u32 port_sel, u32 val)
1368 {
1369         if ((val & DP_PORT_EN) == 0)
1370                 return false;
1371
1372         if (HAS_PCH_CPT(dev_priv->dev)) {
1373                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376                         return false;
1377         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379                         return false;
1380         } else {
1381                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382                         return false;
1383         }
1384         return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388                               enum pipe pipe, u32 val)
1389 {
1390         if ((val & SDVO_ENABLE) == 0)
1391                 return false;
1392
1393         if (HAS_PCH_CPT(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395                         return false;
1396         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407                               enum pipe pipe, u32 val)
1408 {
1409         if ((val & LVDS_PORT_EN) == 0)
1410                 return false;
1411
1412         if (HAS_PCH_CPT(dev_priv->dev)) {
1413                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414                         return false;
1415         } else {
1416                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417                         return false;
1418         }
1419         return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423                               enum pipe pipe, u32 val)
1424 {
1425         if ((val & ADPA_DAC_ENABLE) == 0)
1426                 return false;
1427         if (HAS_PCH_CPT(dev_priv->dev)) {
1428                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432                         return false;
1433         }
1434         return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438                                    enum pipe pipe, int reg, u32 port_sel)
1439 {
1440         u32 val = I915_READ(reg);
1441         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443              reg, pipe_name(pipe));
1444
1445         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446              && (val & DP_PIPEB_SELECT),
1447              "IBX PCH dp port still using transcoder B\n");
1448 }
1449
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451                                      enum pipe pipe, int reg)
1452 {
1453         u32 val = I915_READ(reg);
1454         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456              reg, pipe_name(pipe));
1457
1458         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459              && (val & SDVO_PIPE_B_SELECT),
1460              "IBX PCH hdmi port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464                                       enum pipe pipe)
1465 {
1466         int reg;
1467         u32 val;
1468
1469         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473         reg = PCH_ADPA;
1474         val = I915_READ(reg);
1475         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476              "PCH VGA enabled on transcoder %c, should be disabled\n",
1477              pipe_name(pipe));
1478
1479         reg = PCH_LVDS;
1480         val = I915_READ(reg);
1481         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483              pipe_name(pipe));
1484
1485         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1488 }
1489
1490 static void intel_init_dpio(struct drm_device *dev)
1491 {
1492         struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494         if (!IS_VALLEYVIEW(dev))
1495                 return;
1496
1497         /*
1498          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499          * CHV x1 PHY (DP/HDMI D)
1500          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501          */
1502         if (IS_CHERRYVIEW(dev)) {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505         } else {
1506                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507         }
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511                            const struct intel_crtc_state *pipe_config)
1512 {
1513         struct drm_device *dev = crtc->base.dev;
1514         struct drm_i915_private *dev_priv = dev->dev_private;
1515         int reg = DPLL(crtc->pipe);
1516         u32 dpll = pipe_config->dpll_hw_state.dpll;
1517
1518         assert_pipe_disabled(dev_priv, crtc->pipe);
1519
1520         /* No really, not for ILK+ */
1521         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523         /* PLL is protected by panel, make sure we can write it */
1524         if (IS_MOBILE(dev_priv->dev))
1525                 assert_panel_unlocked(dev_priv, crtc->pipe);
1526
1527         I915_WRITE(reg, dpll);
1528         POSTING_READ(reg);
1529         udelay(150);
1530
1531         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
1534         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535         POSTING_READ(DPLL_MD(crtc->pipe));
1536
1537         /* We do this three times for luck */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544         I915_WRITE(reg, dpll);
1545         POSTING_READ(reg);
1546         udelay(150); /* wait for warmup */
1547 }
1548
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550                            const struct intel_crtc_state *pipe_config)
1551 {
1552         struct drm_device *dev = crtc->base.dev;
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         int pipe = crtc->pipe;
1555         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1556         u32 tmp;
1557
1558         assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562         mutex_lock(&dev_priv->dpio_lock);
1563
1564         /* Enable back the 10bit clock to display controller */
1565         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566         tmp |= DPIO_DCLKP_EN;
1567         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569         /*
1570          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571          */
1572         udelay(1);
1573
1574         /* Enable PLL */
1575         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1576
1577         /* Check PLL is locked */
1578         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
1581         /* not sure when this should be written */
1582         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583         POSTING_READ(DPLL_MD(pipe));
1584
1585         mutex_unlock(&dev_priv->dpio_lock);
1586 }
1587
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1589 {
1590         struct intel_crtc *crtc;
1591         int count = 0;
1592
1593         for_each_intel_crtc(dev, crtc)
1594                 count += crtc->active &&
1595                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1596
1597         return count;
1598 }
1599
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1601 {
1602         struct drm_device *dev = crtc->base.dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         int reg = DPLL(crtc->pipe);
1605         u32 dpll = crtc->config->dpll_hw_state.dpll;
1606
1607         assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609         /* No really, not for ILK+ */
1610         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1611
1612         /* PLL is protected by panel, make sure we can write it */
1613         if (IS_MOBILE(dev) && !IS_I830(dev))
1614                 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616         /* Enable DVO 2x clock on both PLLs if necessary */
1617         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618                 /*
1619                  * It appears to be important that we don't enable this
1620                  * for the current pipe before otherwise configuring the
1621                  * PLL. No idea how this should be handled if multiple
1622                  * DVO outputs are enabled simultaneosly.
1623                  */
1624                 dpll |= DPLL_DVO_2X_MODE;
1625                 I915_WRITE(DPLL(!crtc->pipe),
1626                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627         }
1628
1629         /* Wait for the clocks to stabilize. */
1630         POSTING_READ(reg);
1631         udelay(150);
1632
1633         if (INTEL_INFO(dev)->gen >= 4) {
1634                 I915_WRITE(DPLL_MD(crtc->pipe),
1635                            crtc->config->dpll_hw_state.dpll_md);
1636         } else {
1637                 /* The pixel multiplier can only be updated once the
1638                  * DPLL is enabled and the clocks are stable.
1639                  *
1640                  * So write it again.
1641                  */
1642                 I915_WRITE(reg, dpll);
1643         }
1644
1645         /* We do this three times for luck */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652         I915_WRITE(reg, dpll);
1653         POSTING_READ(reg);
1654         udelay(150); /* wait for warmup */
1655 }
1656
1657 /**
1658  * i9xx_disable_pll - disable a PLL
1659  * @dev_priv: i915 private structure
1660  * @pipe: pipe PLL to disable
1661  *
1662  * Disable the PLL for @pipe, making sure the pipe is off first.
1663  *
1664  * Note!  This is for pre-ILK only.
1665  */
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1667 {
1668         struct drm_device *dev = crtc->base.dev;
1669         struct drm_i915_private *dev_priv = dev->dev_private;
1670         enum pipe pipe = crtc->pipe;
1671
1672         /* Disable DVO 2x clock on both PLLs if necessary */
1673         if (IS_I830(dev) &&
1674             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675             intel_num_dvo_pipes(dev) == 1) {
1676                 I915_WRITE(DPLL(PIPE_B),
1677                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678                 I915_WRITE(DPLL(PIPE_A),
1679                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680         }
1681
1682         /* Don't disable pipe or pipe PLLs if needed */
1683         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1685                 return;
1686
1687         /* Make sure the pipe isn't still relying on us */
1688         assert_pipe_disabled(dev_priv, pipe);
1689
1690         I915_WRITE(DPLL(pipe), 0);
1691         POSTING_READ(DPLL(pipe));
1692 }
1693
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696         u32 val = 0;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         /*
1702          * Leave integrated clock source and reference clock enabled for pipe B.
1703          * The latter is needed for VGA hotplug / manual detection.
1704          */
1705         if (pipe == PIPE_B)
1706                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707         I915_WRITE(DPLL(pipe), val);
1708         POSTING_READ(DPLL(pipe));
1709
1710 }
1711
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715         u32 val;
1716
1717         /* Make sure the pipe isn't still relying on us */
1718         assert_pipe_disabled(dev_priv, pipe);
1719
1720         /* Set PLL en = 0 */
1721         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1722         if (pipe != PIPE_A)
1723                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726
1727         mutex_lock(&dev_priv->dpio_lock);
1728
1729         /* Disable 10bit clock to display controller */
1730         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731         val &= ~DPIO_DCLKP_EN;
1732         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734         /* disable left/right clock distribution */
1735         if (pipe != PIPE_B) {
1736                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739         } else {
1740                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743         }
1744
1745         mutex_unlock(&dev_priv->dpio_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749                 struct intel_digital_port *dport)
1750 {
1751         u32 port_mask;
1752         int dpll_reg;
1753
1754         switch (dport->port) {
1755         case PORT_B:
1756                 port_mask = DPLL_PORTB_READY_MASK;
1757                 dpll_reg = DPLL(0);
1758                 break;
1759         case PORT_C:
1760                 port_mask = DPLL_PORTC_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 break;
1763         case PORT_D:
1764                 port_mask = DPLL_PORTD_READY_MASK;
1765                 dpll_reg = DPIO_PHY_STATUS;
1766                 break;
1767         default:
1768                 BUG();
1769         }
1770
1771         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773                      port_name(dport->port), I915_READ(dpll_reg));
1774 }
1775
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777 {
1778         struct drm_device *dev = crtc->base.dev;
1779         struct drm_i915_private *dev_priv = dev->dev_private;
1780         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782         if (WARN_ON(pll == NULL))
1783                 return;
1784
1785         WARN_ON(!pll->config.crtc_mask);
1786         if (pll->active == 0) {
1787                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788                 WARN_ON(pll->on);
1789                 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791                 pll->mode_set(dev_priv, pll);
1792         }
1793 }
1794
1795 /**
1796  * intel_enable_shared_dpll - enable PCH PLL
1797  * @dev_priv: i915 private structure
1798  * @pipe: pipe PLL to enable
1799  *
1800  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801  * drives the transcoder clock.
1802  */
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804 {
1805         struct drm_device *dev = crtc->base.dev;
1806         struct drm_i915_private *dev_priv = dev->dev_private;
1807         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809         if (WARN_ON(pll == NULL))
1810                 return;
1811
1812         if (WARN_ON(pll->config.crtc_mask == 0))
1813                 return;
1814
1815         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816                       pll->name, pll->active, pll->on,
1817                       crtc->base.base.id);
1818
1819         if (pll->active++) {
1820                 WARN_ON(!pll->on);
1821                 assert_shared_dpll_enabled(dev_priv, pll);
1822                 return;
1823         }
1824         WARN_ON(pll->on);
1825
1826         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829         pll->enable(dev_priv, pll);
1830         pll->on = true;
1831 }
1832
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835         struct drm_device *dev = crtc->base.dev;
1836         struct drm_i915_private *dev_priv = dev->dev_private;
1837         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839         /* PCH only available on ILK+ */
1840         BUG_ON(INTEL_INFO(dev)->gen < 5);
1841         if (WARN_ON(pll == NULL))
1842                return;
1843
1844         if (WARN_ON(pll->config.crtc_mask == 0))
1845                 return;
1846
1847         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848                       pll->name, pll->active, pll->on,
1849                       crtc->base.base.id);
1850
1851         if (WARN_ON(pll->active == 0)) {
1852                 assert_shared_dpll_disabled(dev_priv, pll);
1853                 return;
1854         }
1855
1856         assert_shared_dpll_enabled(dev_priv, pll);
1857         WARN_ON(!pll->on);
1858         if (--pll->active)
1859                 return;
1860
1861         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862         pll->disable(dev_priv, pll);
1863         pll->on = false;
1864
1865         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866 }
1867
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869                                            enum pipe pipe)
1870 {
1871         struct drm_device *dev = dev_priv->dev;
1872         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874         uint32_t reg, val, pipeconf_val;
1875
1876         /* PCH only available on ILK+ */
1877         BUG_ON(!HAS_PCH_SPLIT(dev));
1878
1879         /* Make sure PCH DPLL is enabled */
1880         assert_shared_dpll_enabled(dev_priv,
1881                                    intel_crtc_to_shared_dpll(intel_crtc));
1882
1883         /* FDI must be feeding us bits for PCH ports */
1884         assert_fdi_tx_enabled(dev_priv, pipe);
1885         assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887         if (HAS_PCH_CPT(dev)) {
1888                 /* Workaround: Set the timing override bit before enabling the
1889                  * pch transcoder. */
1890                 reg = TRANS_CHICKEN2(pipe);
1891                 val = I915_READ(reg);
1892                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893                 I915_WRITE(reg, val);
1894         }
1895
1896         reg = PCH_TRANSCONF(pipe);
1897         val = I915_READ(reg);
1898         pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900         if (HAS_PCH_IBX(dev_priv->dev)) {
1901                 /*
1902                  * make the BPC in transcoder be consistent with
1903                  * that in pipeconf reg.
1904                  */
1905                 val &= ~PIPECONF_BPC_MASK;
1906                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907         }
1908
1909         val &= ~TRANS_INTERLACE_MASK;
1910         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911                 if (HAS_PCH_IBX(dev_priv->dev) &&
1912                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913                         val |= TRANS_LEGACY_INTERLACED_ILK;
1914                 else
1915                         val |= TRANS_INTERLACED;
1916         else
1917                 val |= TRANS_PROGRESSIVE;
1918
1919         I915_WRITE(reg, val | TRANS_ENABLE);
1920         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922 }
1923
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925                                       enum transcoder cpu_transcoder)
1926 {
1927         u32 val, pipeconf_val;
1928
1929         /* PCH only available on ILK+ */
1930         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1931
1932         /* FDI must be feeding us bits for PCH ports */
1933         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936         /* Workaround: set timing override bit. */
1937         val = I915_READ(_TRANSA_CHICKEN2);
1938         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939         I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941         val = TRANS_ENABLE;
1942         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945             PIPECONF_INTERLACED_ILK)
1946                 val |= TRANS_INTERLACED;
1947         else
1948                 val |= TRANS_PROGRESSIVE;
1949
1950         I915_WRITE(LPT_TRANSCONF, val);
1951         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952                 DRM_ERROR("Failed to enable PCH transcoder\n");
1953 }
1954
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956                                             enum pipe pipe)
1957 {
1958         struct drm_device *dev = dev_priv->dev;
1959         uint32_t reg, val;
1960
1961         /* FDI relies on the transcoder */
1962         assert_fdi_tx_disabled(dev_priv, pipe);
1963         assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965         /* Ports must be off as well */
1966         assert_pch_ports_disabled(dev_priv, pipe);
1967
1968         reg = PCH_TRANSCONF(pipe);
1969         val = I915_READ(reg);
1970         val &= ~TRANS_ENABLE;
1971         I915_WRITE(reg, val);
1972         /* wait for PCH transcoder off, transcoder state */
1973         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976         if (!HAS_PCH_IBX(dev)) {
1977                 /* Workaround: Clear the timing override chicken bit again. */
1978                 reg = TRANS_CHICKEN2(pipe);
1979                 val = I915_READ(reg);
1980                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981                 I915_WRITE(reg, val);
1982         }
1983 }
1984
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 {
1987         u32 val;
1988
1989         val = I915_READ(LPT_TRANSCONF);
1990         val &= ~TRANS_ENABLE;
1991         I915_WRITE(LPT_TRANSCONF, val);
1992         /* wait for PCH transcoder off, transcoder state */
1993         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994                 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996         /* Workaround: clear timing override bit. */
1997         val = I915_READ(_TRANSA_CHICKEN2);
1998         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999         I915_WRITE(_TRANSA_CHICKEN2, val);
2000 }
2001
2002 /**
2003  * intel_enable_pipe - enable a pipe, asserting requirements
2004  * @crtc: crtc responsible for the pipe
2005  *
2006  * Enable @crtc's pipe, making sure that various hardware specific requirements
2007  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008  */
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2010 {
2011         struct drm_device *dev = crtc->base.dev;
2012         struct drm_i915_private *dev_priv = dev->dev_private;
2013         enum pipe pipe = crtc->pipe;
2014         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015                                                                       pipe);
2016         enum pipe pch_transcoder;
2017         int reg;
2018         u32 val;
2019
2020         assert_planes_disabled(dev_priv, pipe);
2021         assert_cursor_disabled(dev_priv, pipe);
2022         assert_sprites_disabled(dev_priv, pipe);
2023
2024         if (HAS_PCH_LPT(dev_priv->dev))
2025                 pch_transcoder = TRANSCODER_A;
2026         else
2027                 pch_transcoder = pipe;
2028
2029         /*
2030          * A pipe without a PLL won't actually be able to drive bits from
2031          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2032          * need the check.
2033          */
2034         if (!HAS_PCH_SPLIT(dev_priv->dev))
2035                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036                         assert_dsi_pll_enabled(dev_priv);
2037                 else
2038                         assert_pll_enabled(dev_priv, pipe);
2039         else {
2040                 if (crtc->config->has_pch_encoder) {
2041                         /* if driving the PCH, we need FDI enabled */
2042                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043                         assert_fdi_tx_pll_enabled(dev_priv,
2044                                                   (enum pipe) cpu_transcoder);
2045                 }
2046                 /* FIXME: assert CPU port conditions for SNB+ */
2047         }
2048
2049         reg = PIPECONF(cpu_transcoder);
2050         val = I915_READ(reg);
2051         if (val & PIPECONF_ENABLE) {
2052                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054                 return;
2055         }
2056
2057         I915_WRITE(reg, val | PIPECONF_ENABLE);
2058         POSTING_READ(reg);
2059 }
2060
2061 /**
2062  * intel_disable_pipe - disable a pipe, asserting requirements
2063  * @crtc: crtc whose pipes is to be disabled
2064  *
2065  * Disable the pipe of @crtc, making sure that various hardware
2066  * specific requirements are met, if applicable, e.g. plane
2067  * disabled, panel fitter off, etc.
2068  *
2069  * Will wait until the pipe has shut down before returning.
2070  */
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2072 {
2073         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075         enum pipe pipe = crtc->pipe;
2076         int reg;
2077         u32 val;
2078
2079         /*
2080          * Make sure planes won't keep trying to pump pixels to us,
2081          * or we might hang the display.
2082          */
2083         assert_planes_disabled(dev_priv, pipe);
2084         assert_cursor_disabled(dev_priv, pipe);
2085         assert_sprites_disabled(dev_priv, pipe);
2086
2087         reg = PIPECONF(cpu_transcoder);
2088         val = I915_READ(reg);
2089         if ((val & PIPECONF_ENABLE) == 0)
2090                 return;
2091
2092         /*
2093          * Double wide has implications for planes
2094          * so best keep it disabled when not needed.
2095          */
2096         if (crtc->config->double_wide)
2097                 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099         /* Don't disable pipe or pipe PLLs if needed */
2100         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102                 val &= ~PIPECONF_ENABLE;
2103
2104         I915_WRITE(reg, val);
2105         if ((val & PIPECONF_ENABLE) == 0)
2106                 intel_wait_for_pipe_off(crtc);
2107 }
2108
2109 /*
2110  * Plane regs are double buffered, going from enabled->disabled needs a
2111  * trigger in order to latch.  The display address reg provides this.
2112  */
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114                                enum plane plane)
2115 {
2116         struct drm_device *dev = dev_priv->dev;
2117         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2118
2119         I915_WRITE(reg, I915_READ(reg));
2120         POSTING_READ(reg);
2121 }
2122
2123 /**
2124  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125  * @plane:  plane to be enabled
2126  * @crtc: crtc for the plane
2127  *
2128  * Enable @plane on @crtc, making sure that the pipe is running first.
2129  */
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131                                           struct drm_crtc *crtc)
2132 {
2133         struct drm_device *dev = plane->dev;
2134         struct drm_i915_private *dev_priv = dev->dev_private;
2135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2139
2140         if (intel_crtc->primary_enabled)
2141                 return;
2142
2143         intel_crtc->primary_enabled = true;
2144
2145         dev_priv->display.update_primary_plane(crtc, plane->fb,
2146                                                crtc->x, crtc->y);
2147
2148         /*
2149          * BDW signals flip done immediately if the plane
2150          * is disabled, even if the plane enable is already
2151          * armed to occur at the next vblank :(
2152          */
2153         if (IS_BROADWELL(dev))
2154                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 }
2156
2157 /**
2158  * intel_disable_primary_hw_plane - disable the primary hardware plane
2159  * @plane: plane to be disabled
2160  * @crtc: crtc for the plane
2161  *
2162  * Disable @plane on @crtc, making sure that the pipe is running first.
2163  */
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165                                            struct drm_crtc *crtc)
2166 {
2167         struct drm_device *dev = plane->dev;
2168         struct drm_i915_private *dev_priv = dev->dev_private;
2169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
2171         if (WARN_ON(!intel_crtc->active))
2172                 return;
2173
2174         if (!intel_crtc->primary_enabled)
2175                 return;
2176
2177         intel_crtc->primary_enabled = false;
2178
2179         dev_priv->display.update_primary_plane(crtc, plane->fb,
2180                                                crtc->x, crtc->y);
2181 }
2182
2183 static bool need_vtd_wa(struct drm_device *dev)
2184 {
2185 #ifdef CONFIG_INTEL_IOMMU
2186         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187                 return true;
2188 #endif
2189         return false;
2190 }
2191
2192 int
2193 intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
2194 {
2195         int tile_height;
2196
2197         tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
2198         return ALIGN(height, tile_height);
2199 }
2200
2201 int
2202 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2203                            struct drm_framebuffer *fb,
2204                            struct intel_engine_cs *pipelined)
2205 {
2206         struct drm_device *dev = fb->dev;
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2209         u32 alignment;
2210         int ret;
2211
2212         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2213
2214         switch (obj->tiling_mode) {
2215         case I915_TILING_NONE:
2216                 if (INTEL_INFO(dev)->gen >= 9)
2217                         alignment = 256 * 1024;
2218                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2219                         alignment = 128 * 1024;
2220                 else if (INTEL_INFO(dev)->gen >= 4)
2221                         alignment = 4 * 1024;
2222                 else
2223                         alignment = 64 * 1024;
2224                 break;
2225         case I915_TILING_X:
2226                 if (INTEL_INFO(dev)->gen >= 9)
2227                         alignment = 256 * 1024;
2228                 else {
2229                         /* pin() will align the object as required by fence */
2230                         alignment = 0;
2231                 }
2232                 break;
2233         case I915_TILING_Y:
2234                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2235                 return -EINVAL;
2236         default:
2237                 BUG();
2238         }
2239
2240         /* Note that the w/a also requires 64 PTE of padding following the
2241          * bo. We currently fill all unused PTE with the shadow page and so
2242          * we should always have valid PTE following the scanout preventing
2243          * the VT-d warning.
2244          */
2245         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2246                 alignment = 256 * 1024;
2247
2248         /*
2249          * Global gtt pte registers are special registers which actually forward
2250          * writes to a chunk of system memory. Which means that there is no risk
2251          * that the register values disappear as soon as we call
2252          * intel_runtime_pm_put(), so it is correct to wrap only the
2253          * pin/unpin/fence and not more.
2254          */
2255         intel_runtime_pm_get(dev_priv);
2256
2257         dev_priv->mm.interruptible = false;
2258         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2259         if (ret)
2260                 goto err_interruptible;
2261
2262         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2263          * fence, whereas 965+ only requires a fence if using
2264          * framebuffer compression.  For simplicity, we always install
2265          * a fence as the cost is not that onerous.
2266          */
2267         ret = i915_gem_object_get_fence(obj);
2268         if (ret)
2269                 goto err_unpin;
2270
2271         i915_gem_object_pin_fence(obj);
2272
2273         dev_priv->mm.interruptible = true;
2274         intel_runtime_pm_put(dev_priv);
2275         return 0;
2276
2277 err_unpin:
2278         i915_gem_object_unpin_from_display_plane(obj);
2279 err_interruptible:
2280         dev_priv->mm.interruptible = true;
2281         intel_runtime_pm_put(dev_priv);
2282         return ret;
2283 }
2284
2285 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2286 {
2287         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2288
2289         i915_gem_object_unpin_fence(obj);
2290         i915_gem_object_unpin_from_display_plane(obj);
2291 }
2292
2293 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2294  * is assumed to be a power-of-two. */
2295 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2296                                              unsigned int tiling_mode,
2297                                              unsigned int cpp,
2298                                              unsigned int pitch)
2299 {
2300         if (tiling_mode != I915_TILING_NONE) {
2301                 unsigned int tile_rows, tiles;
2302
2303                 tile_rows = *y / 8;
2304                 *y %= 8;
2305
2306                 tiles = *x / (512/cpp);
2307                 *x %= 512/cpp;
2308
2309                 return tile_rows * pitch * 8 + tiles * 4096;
2310         } else {
2311                 unsigned int offset;
2312
2313                 offset = *y * pitch + *x * cpp;
2314                 *y = 0;
2315                 *x = (offset & 4095) / cpp;
2316                 return offset & -4096;
2317         }
2318 }
2319
2320 static int i9xx_format_to_fourcc(int format)
2321 {
2322         switch (format) {
2323         case DISPPLANE_8BPP:
2324                 return DRM_FORMAT_C8;
2325         case DISPPLANE_BGRX555:
2326                 return DRM_FORMAT_XRGB1555;
2327         case DISPPLANE_BGRX565:
2328                 return DRM_FORMAT_RGB565;
2329         default:
2330         case DISPPLANE_BGRX888:
2331                 return DRM_FORMAT_XRGB8888;
2332         case DISPPLANE_RGBX888:
2333                 return DRM_FORMAT_XBGR8888;
2334         case DISPPLANE_BGRX101010:
2335                 return DRM_FORMAT_XRGB2101010;
2336         case DISPPLANE_RGBX101010:
2337                 return DRM_FORMAT_XBGR2101010;
2338         }
2339 }
2340
2341 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2342 {
2343         switch (format) {
2344         case PLANE_CTL_FORMAT_RGB_565:
2345                 return DRM_FORMAT_RGB565;
2346         default:
2347         case PLANE_CTL_FORMAT_XRGB_8888:
2348                 if (rgb_order) {
2349                         if (alpha)
2350                                 return DRM_FORMAT_ABGR8888;
2351                         else
2352                                 return DRM_FORMAT_XBGR8888;
2353                 } else {
2354                         if (alpha)
2355                                 return DRM_FORMAT_ARGB8888;
2356                         else
2357                                 return DRM_FORMAT_XRGB8888;
2358                 }
2359         case PLANE_CTL_FORMAT_XRGB_2101010:
2360                 if (rgb_order)
2361                         return DRM_FORMAT_XBGR2101010;
2362                 else
2363                         return DRM_FORMAT_XRGB2101010;
2364         }
2365 }
2366
2367 static bool
2368 intel_alloc_plane_obj(struct intel_crtc *crtc,
2369                       struct intel_initial_plane_config *plane_config)
2370 {
2371         struct drm_device *dev = crtc->base.dev;
2372         struct drm_i915_gem_object *obj = NULL;
2373         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2374         struct drm_framebuffer *fb = &plane_config->fb->base;
2375         u32 base = plane_config->base;
2376
2377         if (plane_config->size == 0)
2378                 return false;
2379
2380         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2381                                                              plane_config->size);
2382         if (!obj)
2383                 return false;
2384
2385         obj->tiling_mode = plane_config->tiling;
2386         if (obj->tiling_mode == I915_TILING_X)
2387                 obj->stride = fb->pitches[0];
2388
2389         mode_cmd.pixel_format = fb->pixel_format;
2390         mode_cmd.width = fb->width;
2391         mode_cmd.height = fb->height;
2392         mode_cmd.pitches[0] = fb->pitches[0];
2393
2394         mutex_lock(&dev->struct_mutex);
2395
2396         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2397                                    &mode_cmd, obj)) {
2398                 DRM_DEBUG_KMS("intel fb init failed\n");
2399                 goto out_unref_obj;
2400         }
2401
2402         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2403         mutex_unlock(&dev->struct_mutex);
2404
2405         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2406         return true;
2407
2408 out_unref_obj:
2409         drm_gem_object_unreference(&obj->base);
2410         mutex_unlock(&dev->struct_mutex);
2411         return false;
2412 }
2413
2414 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2415 static void
2416 update_state_fb(struct drm_plane *plane)
2417 {
2418         if (plane->fb == plane->state->fb)
2419                 return;
2420
2421         if (plane->state->fb)
2422                 drm_framebuffer_unreference(plane->state->fb);
2423         plane->state->fb = plane->fb;
2424         if (plane->state->fb)
2425                 drm_framebuffer_reference(plane->state->fb);
2426 }
2427
2428 static void
2429 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2430                      struct intel_initial_plane_config *plane_config)
2431 {
2432         struct drm_device *dev = intel_crtc->base.dev;
2433         struct drm_i915_private *dev_priv = dev->dev_private;
2434         struct drm_crtc *c;
2435         struct intel_crtc *i;
2436         struct drm_i915_gem_object *obj;
2437
2438         if (!plane_config->fb)
2439                 return;
2440
2441         if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2442                 struct drm_plane *primary = intel_crtc->base.primary;
2443
2444                 primary->fb = &plane_config->fb->base;
2445                 primary->state->crtc = &intel_crtc->base;
2446                 update_state_fb(primary);
2447
2448                 return;
2449         }
2450
2451         kfree(plane_config->fb);
2452
2453         /*
2454          * Failed to alloc the obj, check to see if we should share
2455          * an fb with another CRTC instead
2456          */
2457         for_each_crtc(dev, c) {
2458                 i = to_intel_crtc(c);
2459
2460                 if (c == &intel_crtc->base)
2461                         continue;
2462
2463                 if (!i->active)
2464                         continue;
2465
2466                 obj = intel_fb_obj(c->primary->fb);
2467                 if (obj == NULL)
2468                         continue;
2469
2470                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2471                         struct drm_plane *primary = intel_crtc->base.primary;
2472
2473                         if (obj->tiling_mode != I915_TILING_NONE)
2474                                 dev_priv->preserve_bios_swizzle = true;
2475
2476                         drm_framebuffer_reference(c->primary->fb);
2477                         primary->fb = c->primary->fb;
2478                         primary->state->crtc = &intel_crtc->base;
2479                         update_state_fb(intel_crtc->base.primary);
2480                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2481                         break;
2482                 }
2483         }
2484
2485 }
2486
2487 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2488                                       struct drm_framebuffer *fb,
2489                                       int x, int y)
2490 {
2491         struct drm_device *dev = crtc->dev;
2492         struct drm_i915_private *dev_priv = dev->dev_private;
2493         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2494         struct drm_i915_gem_object *obj;
2495         int plane = intel_crtc->plane;
2496         unsigned long linear_offset;
2497         u32 dspcntr;
2498         u32 reg = DSPCNTR(plane);
2499         int pixel_size;
2500
2501         if (!intel_crtc->primary_enabled) {
2502                 I915_WRITE(reg, 0);
2503                 if (INTEL_INFO(dev)->gen >= 4)
2504                         I915_WRITE(DSPSURF(plane), 0);
2505                 else
2506                         I915_WRITE(DSPADDR(plane), 0);
2507                 POSTING_READ(reg);
2508                 return;
2509         }
2510
2511         obj = intel_fb_obj(fb);
2512         if (WARN_ON(obj == NULL))
2513                 return;
2514
2515         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2516
2517         dspcntr = DISPPLANE_GAMMA_ENABLE;
2518
2519         dspcntr |= DISPLAY_PLANE_ENABLE;
2520
2521         if (INTEL_INFO(dev)->gen < 4) {
2522                 if (intel_crtc->pipe == PIPE_B)
2523                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2524
2525                 /* pipesrc and dspsize control the size that is scaled from,
2526                  * which should always be the user's requested size.
2527                  */
2528                 I915_WRITE(DSPSIZE(plane),
2529                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2530                            (intel_crtc->config->pipe_src_w - 1));
2531                 I915_WRITE(DSPPOS(plane), 0);
2532         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2533                 I915_WRITE(PRIMSIZE(plane),
2534                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2535                            (intel_crtc->config->pipe_src_w - 1));
2536                 I915_WRITE(PRIMPOS(plane), 0);
2537                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2538         }
2539
2540         switch (fb->pixel_format) {
2541         case DRM_FORMAT_C8:
2542                 dspcntr |= DISPPLANE_8BPP;
2543                 break;
2544         case DRM_FORMAT_XRGB1555:
2545         case DRM_FORMAT_ARGB1555:
2546                 dspcntr |= DISPPLANE_BGRX555;
2547                 break;
2548         case DRM_FORMAT_RGB565:
2549                 dspcntr |= DISPPLANE_BGRX565;
2550                 break;
2551         case DRM_FORMAT_XRGB8888:
2552         case DRM_FORMAT_ARGB8888:
2553                 dspcntr |= DISPPLANE_BGRX888;
2554                 break;
2555         case DRM_FORMAT_XBGR8888:
2556         case DRM_FORMAT_ABGR8888:
2557                 dspcntr |= DISPPLANE_RGBX888;
2558                 break;
2559         case DRM_FORMAT_XRGB2101010:
2560         case DRM_FORMAT_ARGB2101010:
2561                 dspcntr |= DISPPLANE_BGRX101010;
2562                 break;
2563         case DRM_FORMAT_XBGR2101010:
2564         case DRM_FORMAT_ABGR2101010:
2565                 dspcntr |= DISPPLANE_RGBX101010;
2566                 break;
2567         default:
2568                 BUG();
2569         }
2570
2571         if (INTEL_INFO(dev)->gen >= 4 &&
2572             obj->tiling_mode != I915_TILING_NONE)
2573                 dspcntr |= DISPPLANE_TILED;
2574
2575         if (IS_G4X(dev))
2576                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2577
2578         linear_offset = y * fb->pitches[0] + x * pixel_size;
2579
2580         if (INTEL_INFO(dev)->gen >= 4) {
2581                 intel_crtc->dspaddr_offset =
2582                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2583                                                        pixel_size,
2584                                                        fb->pitches[0]);
2585                 linear_offset -= intel_crtc->dspaddr_offset;
2586         } else {
2587                 intel_crtc->dspaddr_offset = linear_offset;
2588         }
2589
2590         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2591                 dspcntr |= DISPPLANE_ROTATE_180;
2592
2593                 x += (intel_crtc->config->pipe_src_w - 1);
2594                 y += (intel_crtc->config->pipe_src_h - 1);
2595
2596                 /* Finding the last pixel of the last line of the display
2597                 data and adding to linear_offset*/
2598                 linear_offset +=
2599                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2600                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2601         }
2602
2603         I915_WRITE(reg, dspcntr);
2604
2605         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2606                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2607                       fb->pitches[0]);
2608         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2609         if (INTEL_INFO(dev)->gen >= 4) {
2610                 I915_WRITE(DSPSURF(plane),
2611                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2612                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2613                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2614         } else
2615                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2616         POSTING_READ(reg);
2617 }
2618
2619 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2620                                           struct drm_framebuffer *fb,
2621                                           int x, int y)
2622 {
2623         struct drm_device *dev = crtc->dev;
2624         struct drm_i915_private *dev_priv = dev->dev_private;
2625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2626         struct drm_i915_gem_object *obj;
2627         int plane = intel_crtc->plane;
2628         unsigned long linear_offset;
2629         u32 dspcntr;
2630         u32 reg = DSPCNTR(plane);
2631         int pixel_size;
2632
2633         if (!intel_crtc->primary_enabled) {
2634                 I915_WRITE(reg, 0);
2635                 I915_WRITE(DSPSURF(plane), 0);
2636                 POSTING_READ(reg);
2637                 return;
2638         }
2639
2640         obj = intel_fb_obj(fb);
2641         if (WARN_ON(obj == NULL))
2642                 return;
2643
2644         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2645
2646         dspcntr = DISPPLANE_GAMMA_ENABLE;
2647
2648         dspcntr |= DISPLAY_PLANE_ENABLE;
2649
2650         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2651                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2652
2653         switch (fb->pixel_format) {
2654         case DRM_FORMAT_C8:
2655                 dspcntr |= DISPPLANE_8BPP;
2656                 break;
2657         case DRM_FORMAT_RGB565:
2658                 dspcntr |= DISPPLANE_BGRX565;
2659                 break;
2660         case DRM_FORMAT_XRGB8888:
2661         case DRM_FORMAT_ARGB8888:
2662                 dspcntr |= DISPPLANE_BGRX888;
2663                 break;
2664         case DRM_FORMAT_XBGR8888:
2665         case DRM_FORMAT_ABGR8888:
2666                 dspcntr |= DISPPLANE_RGBX888;
2667                 break;
2668         case DRM_FORMAT_XRGB2101010:
2669         case DRM_FORMAT_ARGB2101010:
2670                 dspcntr |= DISPPLANE_BGRX101010;
2671                 break;
2672         case DRM_FORMAT_XBGR2101010:
2673         case DRM_FORMAT_ABGR2101010:
2674                 dspcntr |= DISPPLANE_RGBX101010;
2675                 break;
2676         default:
2677                 BUG();
2678         }
2679
2680         if (obj->tiling_mode != I915_TILING_NONE)
2681                 dspcntr |= DISPPLANE_TILED;
2682
2683         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2684                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2685
2686         linear_offset = y * fb->pitches[0] + x * pixel_size;
2687         intel_crtc->dspaddr_offset =
2688                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2689                                                pixel_size,
2690                                                fb->pitches[0]);
2691         linear_offset -= intel_crtc->dspaddr_offset;
2692         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2693                 dspcntr |= DISPPLANE_ROTATE_180;
2694
2695                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2696                         x += (intel_crtc->config->pipe_src_w - 1);
2697                         y += (intel_crtc->config->pipe_src_h - 1);
2698
2699                         /* Finding the last pixel of the last line of the display
2700                         data and adding to linear_offset*/
2701                         linear_offset +=
2702                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2703                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2704                 }
2705         }
2706
2707         I915_WRITE(reg, dspcntr);
2708
2709         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2710                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2711                       fb->pitches[0]);
2712         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2713         I915_WRITE(DSPSURF(plane),
2714                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2715         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2716                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2717         } else {
2718                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2719                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2720         }
2721         POSTING_READ(reg);
2722 }
2723
2724 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2725                                          struct drm_framebuffer *fb,
2726                                          int x, int y)
2727 {
2728         struct drm_device *dev = crtc->dev;
2729         struct drm_i915_private *dev_priv = dev->dev_private;
2730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731         struct intel_framebuffer *intel_fb;
2732         struct drm_i915_gem_object *obj;
2733         int pipe = intel_crtc->pipe;
2734         u32 plane_ctl, stride;
2735
2736         if (!intel_crtc->primary_enabled) {
2737                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2738                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2739                 POSTING_READ(PLANE_CTL(pipe, 0));
2740                 return;
2741         }
2742
2743         plane_ctl = PLANE_CTL_ENABLE |
2744                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2745                     PLANE_CTL_PIPE_CSC_ENABLE;
2746
2747         switch (fb->pixel_format) {
2748         case DRM_FORMAT_RGB565:
2749                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2750                 break;
2751         case DRM_FORMAT_XRGB8888:
2752                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2753                 break;
2754         case DRM_FORMAT_XBGR8888:
2755                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2756                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2757                 break;
2758         case DRM_FORMAT_XRGB2101010:
2759                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2760                 break;
2761         case DRM_FORMAT_XBGR2101010:
2762                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2763                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2764                 break;
2765         default:
2766                 BUG();
2767         }
2768
2769         intel_fb = to_intel_framebuffer(fb);
2770         obj = intel_fb->obj;
2771
2772         /*
2773          * The stride is either expressed as a multiple of 64 bytes chunks for
2774          * linear buffers or in number of tiles for tiled buffers.
2775          */
2776         switch (obj->tiling_mode) {
2777         case I915_TILING_NONE:
2778                 stride = fb->pitches[0] >> 6;
2779                 break;
2780         case I915_TILING_X:
2781                 plane_ctl |= PLANE_CTL_TILED_X;
2782                 stride = fb->pitches[0] >> 9;
2783                 break;
2784         default:
2785                 BUG();
2786         }
2787
2788         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2789         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2790                 plane_ctl |= PLANE_CTL_ROTATE_180;
2791
2792         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2793
2794         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2795                       i915_gem_obj_ggtt_offset(obj),
2796                       x, y, fb->width, fb->height,
2797                       fb->pitches[0]);
2798
2799         I915_WRITE(PLANE_POS(pipe, 0), 0);
2800         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2801         I915_WRITE(PLANE_SIZE(pipe, 0),
2802                    (intel_crtc->config->pipe_src_h - 1) << 16 |
2803                    (intel_crtc->config->pipe_src_w - 1));
2804         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2805         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2806
2807         POSTING_READ(PLANE_SURF(pipe, 0));
2808 }
2809
2810 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2811 static int
2812 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2813                            int x, int y, enum mode_set_atomic state)
2814 {
2815         struct drm_device *dev = crtc->dev;
2816         struct drm_i915_private *dev_priv = dev->dev_private;
2817
2818         if (dev_priv->display.disable_fbc)
2819                 dev_priv->display.disable_fbc(dev);
2820
2821         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2822
2823         return 0;
2824 }
2825
2826 static void intel_complete_page_flips(struct drm_device *dev)
2827 {
2828         struct drm_crtc *crtc;
2829
2830         for_each_crtc(dev, crtc) {
2831                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2832                 enum plane plane = intel_crtc->plane;
2833
2834                 intel_prepare_page_flip(dev, plane);
2835                 intel_finish_page_flip_plane(dev, plane);
2836         }
2837 }
2838
2839 static void intel_update_primary_planes(struct drm_device *dev)
2840 {
2841         struct drm_i915_private *dev_priv = dev->dev_private;
2842         struct drm_crtc *crtc;
2843
2844         for_each_crtc(dev, crtc) {
2845                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2846
2847                 drm_modeset_lock(&crtc->mutex, NULL);
2848                 /*
2849                  * FIXME: Once we have proper support for primary planes (and
2850                  * disabling them without disabling the entire crtc) allow again
2851                  * a NULL crtc->primary->fb.
2852                  */
2853                 if (intel_crtc->active && crtc->primary->fb)
2854                         dev_priv->display.update_primary_plane(crtc,
2855                                                                crtc->primary->fb,
2856                                                                crtc->x,
2857                                                                crtc->y);
2858                 drm_modeset_unlock(&crtc->mutex);
2859         }
2860 }
2861
2862 void intel_prepare_reset(struct drm_device *dev)
2863 {
2864         struct drm_i915_private *dev_priv = to_i915(dev);
2865         struct intel_crtc *crtc;
2866
2867         /* no reset support for gen2 */
2868         if (IS_GEN2(dev))
2869                 return;
2870
2871         /* reset doesn't touch the display */
2872         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2873                 return;
2874
2875         drm_modeset_lock_all(dev);
2876
2877         /*
2878          * Disabling the crtcs gracefully seems nicer. Also the
2879          * g33 docs say we should at least disable all the planes.
2880          */
2881         for_each_intel_crtc(dev, crtc) {
2882                 if (crtc->active)
2883                         dev_priv->display.crtc_disable(&crtc->base);
2884         }
2885 }
2886
2887 void intel_finish_reset(struct drm_device *dev)
2888 {
2889         struct drm_i915_private *dev_priv = to_i915(dev);
2890
2891         /*
2892          * Flips in the rings will be nuked by the reset,
2893          * so complete all pending flips so that user space
2894          * will get its events and not get stuck.
2895          */
2896         intel_complete_page_flips(dev);
2897
2898         /* no reset support for gen2 */
2899         if (IS_GEN2(dev))
2900                 return;
2901
2902         /* reset doesn't touch the display */
2903         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2904                 /*
2905                  * Flips in the rings have been nuked by the reset,
2906                  * so update the base address of all primary
2907                  * planes to the the last fb to make sure we're
2908                  * showing the correct fb after a reset.
2909                  */
2910                 intel_update_primary_planes(dev);
2911                 return;
2912         }
2913
2914         /*
2915          * The display has been reset as well,
2916          * so need a full re-initialization.
2917          */
2918         intel_runtime_pm_disable_interrupts(dev_priv);
2919         intel_runtime_pm_enable_interrupts(dev_priv);
2920
2921         intel_modeset_init_hw(dev);
2922
2923         spin_lock_irq(&dev_priv->irq_lock);
2924         if (dev_priv->display.hpd_irq_setup)
2925                 dev_priv->display.hpd_irq_setup(dev);
2926         spin_unlock_irq(&dev_priv->irq_lock);
2927
2928         intel_modeset_setup_hw_state(dev, true);
2929
2930         intel_hpd_init(dev_priv);
2931
2932         drm_modeset_unlock_all(dev);
2933 }
2934
2935 static int
2936 intel_finish_fb(struct drm_framebuffer *old_fb)
2937 {
2938         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2939         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2940         bool was_interruptible = dev_priv->mm.interruptible;
2941         int ret;
2942
2943         /* Big Hammer, we also need to ensure that any pending
2944          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2945          * current scanout is retired before unpinning the old
2946          * framebuffer.
2947          *
2948          * This should only fail upon a hung GPU, in which case we
2949          * can safely continue.
2950          */
2951         dev_priv->mm.interruptible = false;
2952         ret = i915_gem_object_finish_gpu(obj);
2953         dev_priv->mm.interruptible = was_interruptible;
2954
2955         return ret;
2956 }
2957
2958 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2959 {
2960         struct drm_device *dev = crtc->dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963         bool pending;
2964
2965         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2966             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2967                 return false;
2968
2969         spin_lock_irq(&dev->event_lock);
2970         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2971         spin_unlock_irq(&dev->event_lock);
2972
2973         return pending;
2974 }
2975
2976 static void intel_update_pipe_size(struct intel_crtc *crtc)
2977 {
2978         struct drm_device *dev = crtc->base.dev;
2979         struct drm_i915_private *dev_priv = dev->dev_private;
2980         const struct drm_display_mode *adjusted_mode;
2981
2982         if (!i915.fastboot)
2983                 return;
2984
2985         /*
2986          * Update pipe size and adjust fitter if needed: the reason for this is
2987          * that in compute_mode_changes we check the native mode (not the pfit
2988          * mode) to see if we can flip rather than do a full mode set. In the
2989          * fastboot case, we'll flip, but if we don't update the pipesrc and
2990          * pfit state, we'll end up with a big fb scanned out into the wrong
2991          * sized surface.
2992          *
2993          * To fix this properly, we need to hoist the checks up into
2994          * compute_mode_changes (or above), check the actual pfit state and
2995          * whether the platform allows pfit disable with pipe active, and only
2996          * then update the pipesrc and pfit state, even on the flip path.
2997          */
2998
2999         adjusted_mode = &crtc->config->base.adjusted_mode;
3000
3001         I915_WRITE(PIPESRC(crtc->pipe),
3002                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3003                    (adjusted_mode->crtc_vdisplay - 1));
3004         if (!crtc->config->pch_pfit.enabled &&
3005             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3006              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3007                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3008                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3009                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3010         }
3011         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3012         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3013 }
3014
3015 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3016 {
3017         struct drm_device *dev = crtc->dev;
3018         struct drm_i915_private *dev_priv = dev->dev_private;
3019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3020         int pipe = intel_crtc->pipe;
3021         u32 reg, temp;
3022
3023         /* enable normal train */
3024         reg = FDI_TX_CTL(pipe);
3025         temp = I915_READ(reg);
3026         if (IS_IVYBRIDGE(dev)) {
3027                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3028                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3029         } else {
3030                 temp &= ~FDI_LINK_TRAIN_NONE;
3031                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3032         }
3033         I915_WRITE(reg, temp);
3034
3035         reg = FDI_RX_CTL(pipe);
3036         temp = I915_READ(reg);
3037         if (HAS_PCH_CPT(dev)) {
3038                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3039                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3040         } else {
3041                 temp &= ~FDI_LINK_TRAIN_NONE;
3042                 temp |= FDI_LINK_TRAIN_NONE;
3043         }
3044         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3045
3046         /* wait one idle pattern time */
3047         POSTING_READ(reg);
3048         udelay(1000);
3049
3050         /* IVB wants error correction enabled */
3051         if (IS_IVYBRIDGE(dev))
3052                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3053                            FDI_FE_ERRC_ENABLE);
3054 }
3055
3056 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3057 {
3058         return crtc->base.enabled && crtc->active &&
3059                 crtc->config->has_pch_encoder;
3060 }
3061
3062 static void ivb_modeset_global_resources(struct drm_device *dev)
3063 {
3064         struct drm_i915_private *dev_priv = dev->dev_private;
3065         struct intel_crtc *pipe_B_crtc =
3066                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3067         struct intel_crtc *pipe_C_crtc =
3068                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3069         uint32_t temp;
3070
3071         /*
3072          * When everything is off disable fdi C so that we could enable fdi B
3073          * with all lanes. Note that we don't care about enabled pipes without
3074          * an enabled pch encoder.
3075          */
3076         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3077             !pipe_has_enabled_pch(pipe_C_crtc)) {
3078                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3079                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3080
3081                 temp = I915_READ(SOUTH_CHICKEN1);
3082                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3083                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3084                 I915_WRITE(SOUTH_CHICKEN1, temp);
3085         }
3086 }
3087
3088 /* The FDI link training functions for ILK/Ibexpeak. */
3089 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3090 {
3091         struct drm_device *dev = crtc->dev;
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3094         int pipe = intel_crtc->pipe;
3095         u32 reg, temp, tries;
3096
3097         /* FDI needs bits from pipe first */
3098         assert_pipe_enabled(dev_priv, pipe);
3099
3100         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3101            for train result */
3102         reg = FDI_RX_IMR(pipe);
3103         temp = I915_READ(reg);
3104         temp &= ~FDI_RX_SYMBOL_LOCK;
3105         temp &= ~FDI_RX_BIT_LOCK;
3106         I915_WRITE(reg, temp);
3107         I915_READ(reg);
3108         udelay(150);
3109
3110         /* enable CPU FDI TX and PCH FDI RX */
3111         reg = FDI_TX_CTL(pipe);
3112         temp = I915_READ(reg);
3113         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3114         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3115         temp &= ~FDI_LINK_TRAIN_NONE;
3116         temp |= FDI_LINK_TRAIN_PATTERN_1;
3117         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3118
3119         reg = FDI_RX_CTL(pipe);
3120         temp = I915_READ(reg);
3121         temp &= ~FDI_LINK_TRAIN_NONE;
3122         temp |= FDI_LINK_TRAIN_PATTERN_1;
3123         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3124
3125         POSTING_READ(reg);
3126         udelay(150);
3127
3128         /* Ironlake workaround, enable clock pointer after FDI enable*/
3129         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3130         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3131                    FDI_RX_PHASE_SYNC_POINTER_EN);
3132
3133         reg = FDI_RX_IIR(pipe);
3134         for (tries = 0; tries < 5; tries++) {
3135                 temp = I915_READ(reg);
3136                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3137
3138                 if ((temp & FDI_RX_BIT_LOCK)) {
3139                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3140                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3141                         break;
3142                 }
3143         }
3144         if (tries == 5)
3145                 DRM_ERROR("FDI train 1 fail!\n");
3146
3147         /* Train 2 */
3148         reg = FDI_TX_CTL(pipe);
3149         temp = I915_READ(reg);
3150         temp &= ~FDI_LINK_TRAIN_NONE;
3151         temp |= FDI_LINK_TRAIN_PATTERN_2;
3152         I915_WRITE(reg, temp);
3153
3154         reg = FDI_RX_CTL(pipe);
3155         temp = I915_READ(reg);
3156         temp &= ~FDI_LINK_TRAIN_NONE;
3157         temp |= FDI_LINK_TRAIN_PATTERN_2;
3158         I915_WRITE(reg, temp);
3159
3160         POSTING_READ(reg);
3161         udelay(150);
3162
3163         reg = FDI_RX_IIR(pipe);
3164         for (tries = 0; tries < 5; tries++) {
3165                 temp = I915_READ(reg);
3166                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3167
3168                 if (temp & FDI_RX_SYMBOL_LOCK) {
3169                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3170                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3171                         break;
3172                 }
3173         }
3174         if (tries == 5)
3175                 DRM_ERROR("FDI train 2 fail!\n");
3176
3177         DRM_DEBUG_KMS("FDI train done\n");
3178
3179 }
3180
3181 static const int snb_b_fdi_train_param[] = {
3182         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3183         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3184         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3185         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3186 };
3187
3188 /* The FDI link training functions for SNB/Cougarpoint. */
3189 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3190 {
3191         struct drm_device *dev = crtc->dev;
3192         struct drm_i915_private *dev_priv = dev->dev_private;
3193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3194         int pipe = intel_crtc->pipe;
3195         u32 reg, temp, i, retry;
3196
3197         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3198            for train result */
3199         reg = FDI_RX_IMR(pipe);
3200         temp = I915_READ(reg);
3201         temp &= ~FDI_RX_SYMBOL_LOCK;
3202         temp &= ~FDI_RX_BIT_LOCK;
3203         I915_WRITE(reg, temp);
3204
3205         POSTING_READ(reg);
3206         udelay(150);
3207
3208         /* enable CPU FDI TX and PCH FDI RX */
3209         reg = FDI_TX_CTL(pipe);
3210         temp = I915_READ(reg);
3211         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3212         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3213         temp &= ~FDI_LINK_TRAIN_NONE;
3214         temp |= FDI_LINK_TRAIN_PATTERN_1;
3215         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3216         /* SNB-B */
3217         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3218         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3219
3220         I915_WRITE(FDI_RX_MISC(pipe),
3221                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3222
3223         reg = FDI_RX_CTL(pipe);
3224         temp = I915_READ(reg);
3225         if (HAS_PCH_CPT(dev)) {
3226                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3227                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3228         } else {
3229                 temp &= ~FDI_LINK_TRAIN_NONE;
3230                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3231         }
3232         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3233
3234         POSTING_READ(reg);
3235         udelay(150);
3236
3237         for (i = 0; i < 4; i++) {
3238                 reg = FDI_TX_CTL(pipe);
3239                 temp = I915_READ(reg);
3240                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3241                 temp |= snb_b_fdi_train_param[i];
3242                 I915_WRITE(reg, temp);
3243
3244                 POSTING_READ(reg);
3245                 udelay(500);
3246
3247                 for (retry = 0; retry < 5; retry++) {
3248                         reg = FDI_RX_IIR(pipe);
3249                         temp = I915_READ(reg);
3250                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3251                         if (temp & FDI_RX_BIT_LOCK) {
3252                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3253                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3254                                 break;
3255                         }
3256                         udelay(50);
3257                 }
3258                 if (retry < 5)
3259                         break;
3260         }
3261         if (i == 4)
3262                 DRM_ERROR("FDI train 1 fail!\n");
3263
3264         /* Train 2 */
3265         reg = FDI_TX_CTL(pipe);
3266         temp = I915_READ(reg);
3267         temp &= ~FDI_LINK_TRAIN_NONE;
3268         temp |= FDI_LINK_TRAIN_PATTERN_2;
3269         if (IS_GEN6(dev)) {
3270                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3271                 /* SNB-B */
3272                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3273         }
3274         I915_WRITE(reg, temp);
3275
3276         reg = FDI_RX_CTL(pipe);
3277         temp = I915_READ(reg);
3278         if (HAS_PCH_CPT(dev)) {
3279                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3280                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3281         } else {
3282                 temp &= ~FDI_LINK_TRAIN_NONE;
3283                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3284         }
3285         I915_WRITE(reg, temp);
3286
3287         POSTING_READ(reg);
3288         udelay(150);
3289
3290         for (i = 0; i < 4; i++) {
3291                 reg = FDI_TX_CTL(pipe);
3292                 temp = I915_READ(reg);
3293                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3294                 temp |= snb_b_fdi_train_param[i];
3295                 I915_WRITE(reg, temp);
3296
3297                 POSTING_READ(reg);
3298                 udelay(500);
3299
3300                 for (retry = 0; retry < 5; retry++) {
3301                         reg = FDI_RX_IIR(pipe);
3302                         temp = I915_READ(reg);
3303                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3304                         if (temp & FDI_RX_SYMBOL_LOCK) {
3305                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3306                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3307                                 break;
3308                         }
3309                         udelay(50);
3310                 }
3311                 if (retry < 5)
3312                         break;
3313         }
3314         if (i == 4)
3315                 DRM_ERROR("FDI train 2 fail!\n");
3316
3317         DRM_DEBUG_KMS("FDI train done.\n");
3318 }
3319
3320 /* Manual link training for Ivy Bridge A0 parts */
3321 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3322 {
3323         struct drm_device *dev = crtc->dev;
3324         struct drm_i915_private *dev_priv = dev->dev_private;
3325         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3326         int pipe = intel_crtc->pipe;
3327         u32 reg, temp, i, j;
3328
3329         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3330            for train result */
3331         reg = FDI_RX_IMR(pipe);
3332         temp = I915_READ(reg);
3333         temp &= ~FDI_RX_SYMBOL_LOCK;
3334         temp &= ~FDI_RX_BIT_LOCK;
3335         I915_WRITE(reg, temp);
3336
3337         POSTING_READ(reg);
3338         udelay(150);
3339
3340         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3341                       I915_READ(FDI_RX_IIR(pipe)));
3342
3343         /* Try each vswing and preemphasis setting twice before moving on */
3344         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3345                 /* disable first in case we need to retry */
3346                 reg = FDI_TX_CTL(pipe);
3347                 temp = I915_READ(reg);
3348                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3349                 temp &= ~FDI_TX_ENABLE;
3350                 I915_WRITE(reg, temp);
3351
3352                 reg = FDI_RX_CTL(pipe);
3353                 temp = I915_READ(reg);
3354                 temp &= ~FDI_LINK_TRAIN_AUTO;
3355                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356                 temp &= ~FDI_RX_ENABLE;
3357                 I915_WRITE(reg, temp);
3358
3359                 /* enable CPU FDI TX and PCH FDI RX */
3360                 reg = FDI_TX_CTL(pipe);
3361                 temp = I915_READ(reg);
3362                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3363                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3364                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3365                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3366                 temp |= snb_b_fdi_train_param[j/2];
3367                 temp |= FDI_COMPOSITE_SYNC;
3368                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3369
3370                 I915_WRITE(FDI_RX_MISC(pipe),
3371                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3372
3373                 reg = FDI_RX_CTL(pipe);
3374                 temp = I915_READ(reg);
3375                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3376                 temp |= FDI_COMPOSITE_SYNC;
3377                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3378
3379                 POSTING_READ(reg);
3380                 udelay(1); /* should be 0.5us */
3381
3382                 for (i = 0; i < 4; i++) {
3383                         reg = FDI_RX_IIR(pipe);
3384                         temp = I915_READ(reg);
3385                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3386
3387                         if (temp & FDI_RX_BIT_LOCK ||
3388                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3389                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3390                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3391                                               i);
3392                                 break;
3393                         }
3394                         udelay(1); /* should be 0.5us */
3395                 }
3396                 if (i == 4) {
3397                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3398                         continue;
3399                 }
3400
3401                 /* Train 2 */
3402                 reg = FDI_TX_CTL(pipe);
3403                 temp = I915_READ(reg);
3404                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3405                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3406                 I915_WRITE(reg, temp);
3407
3408                 reg = FDI_RX_CTL(pipe);
3409                 temp = I915_READ(reg);
3410                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3411                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3412                 I915_WRITE(reg, temp);
3413
3414                 POSTING_READ(reg);
3415                 udelay(2); /* should be 1.5us */
3416
3417                 for (i = 0; i < 4; i++) {
3418                         reg = FDI_RX_IIR(pipe);
3419                         temp = I915_READ(reg);
3420                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3421
3422                         if (temp & FDI_RX_SYMBOL_LOCK ||
3423                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3424                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3425                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3426                                               i);
3427                                 goto train_done;
3428                         }
3429                         udelay(2); /* should be 1.5us */
3430                 }
3431                 if (i == 4)
3432                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3433         }
3434
3435 train_done:
3436         DRM_DEBUG_KMS("FDI train done.\n");
3437 }
3438
3439 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3440 {
3441         struct drm_device *dev = intel_crtc->base.dev;
3442         struct drm_i915_private *dev_priv = dev->dev_private;
3443         int pipe = intel_crtc->pipe;
3444         u32 reg, temp;
3445
3446
3447         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3448         reg = FDI_RX_CTL(pipe);
3449         temp = I915_READ(reg);
3450         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3451         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3452         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3453         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3454
3455         POSTING_READ(reg);
3456         udelay(200);
3457
3458         /* Switch from Rawclk to PCDclk */
3459         temp = I915_READ(reg);
3460         I915_WRITE(reg, temp | FDI_PCDCLK);
3461
3462         POSTING_READ(reg);
3463         udelay(200);
3464
3465         /* Enable CPU FDI TX PLL, always on for Ironlake */
3466         reg = FDI_TX_CTL(pipe);
3467         temp = I915_READ(reg);
3468         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3469                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3470
3471                 POSTING_READ(reg);
3472                 udelay(100);
3473         }
3474 }
3475
3476 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3477 {
3478         struct drm_device *dev = intel_crtc->base.dev;
3479         struct drm_i915_private *dev_priv = dev->dev_private;
3480         int pipe = intel_crtc->pipe;
3481         u32 reg, temp;
3482
3483         /* Switch from PCDclk to Rawclk */
3484         reg = FDI_RX_CTL(pipe);
3485         temp = I915_READ(reg);
3486         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3487
3488         /* Disable CPU FDI TX PLL */
3489         reg = FDI_TX_CTL(pipe);
3490         temp = I915_READ(reg);
3491         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3492
3493         POSTING_READ(reg);
3494         udelay(100);
3495
3496         reg = FDI_RX_CTL(pipe);
3497         temp = I915_READ(reg);
3498         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3499
3500         /* Wait for the clocks to turn off. */
3501         POSTING_READ(reg);
3502         udelay(100);
3503 }
3504
3505 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3506 {
3507         struct drm_device *dev = crtc->dev;
3508         struct drm_i915_private *dev_priv = dev->dev_private;
3509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3510         int pipe = intel_crtc->pipe;
3511         u32 reg, temp;
3512
3513         /* disable CPU FDI tx and PCH FDI rx */
3514         reg = FDI_TX_CTL(pipe);
3515         temp = I915_READ(reg);
3516         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3517         POSTING_READ(reg);
3518
3519         reg = FDI_RX_CTL(pipe);
3520         temp = I915_READ(reg);
3521         temp &= ~(0x7 << 16);
3522         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3523         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3524
3525         POSTING_READ(reg);
3526         udelay(100);
3527
3528         /* Ironlake workaround, disable clock pointer after downing FDI */
3529         if (HAS_PCH_IBX(dev))
3530                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3531
3532         /* still set train pattern 1 */
3533         reg = FDI_TX_CTL(pipe);
3534         temp = I915_READ(reg);
3535         temp &= ~FDI_LINK_TRAIN_NONE;
3536         temp |= FDI_LINK_TRAIN_PATTERN_1;
3537         I915_WRITE(reg, temp);
3538
3539         reg = FDI_RX_CTL(pipe);
3540         temp = I915_READ(reg);
3541         if (HAS_PCH_CPT(dev)) {
3542                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3543                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3544         } else {
3545                 temp &= ~FDI_LINK_TRAIN_NONE;
3546                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3547         }
3548         /* BPC in FDI rx is consistent with that in PIPECONF */
3549         temp &= ~(0x07 << 16);
3550         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3551         I915_WRITE(reg, temp);
3552
3553         POSTING_READ(reg);
3554         udelay(100);
3555 }
3556
3557 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3558 {
3559         struct intel_crtc *crtc;
3560
3561         /* Note that we don't need to be called with mode_config.lock here
3562          * as our list of CRTC objects is static for the lifetime of the
3563          * device and so cannot disappear as we iterate. Similarly, we can
3564          * happily treat the predicates as racy, atomic checks as userspace
3565          * cannot claim and pin a new fb without at least acquring the
3566          * struct_mutex and so serialising with us.
3567          */
3568         for_each_intel_crtc(dev, crtc) {
3569                 if (atomic_read(&crtc->unpin_work_count) == 0)
3570                         continue;
3571
3572                 if (crtc->unpin_work)
3573                         intel_wait_for_vblank(dev, crtc->pipe);
3574
3575                 return true;
3576         }
3577
3578         return false;
3579 }
3580
3581 static void page_flip_completed(struct intel_crtc *intel_crtc)
3582 {
3583         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3584         struct intel_unpin_work *work = intel_crtc->unpin_work;
3585
3586         /* ensure that the unpin work is consistent wrt ->pending. */
3587         smp_rmb();
3588         intel_crtc->unpin_work = NULL;
3589
3590         if (work->event)
3591                 drm_send_vblank_event(intel_crtc->base.dev,
3592                                       intel_crtc->pipe,
3593                                       work->event);
3594
3595         drm_crtc_vblank_put(&intel_crtc->base);
3596
3597         wake_up_all(&dev_priv->pending_flip_queue);
3598         queue_work(dev_priv->wq, &work->work);
3599
3600         trace_i915_flip_complete(intel_crtc->plane,
3601                                  work->pending_flip_obj);
3602 }
3603
3604 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3605 {
3606         struct drm_device *dev = crtc->dev;
3607         struct drm_i915_private *dev_priv = dev->dev_private;
3608
3609         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3610         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3611                                        !intel_crtc_has_pending_flip(crtc),
3612                                        60*HZ) == 0)) {
3613                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614
3615                 spin_lock_irq(&dev->event_lock);
3616                 if (intel_crtc->unpin_work) {
3617                         WARN_ONCE(1, "Removing stuck page flip\n");
3618                         page_flip_completed(intel_crtc);
3619                 }
3620                 spin_unlock_irq(&dev->event_lock);
3621         }
3622
3623         if (crtc->primary->fb) {
3624                 mutex_lock(&dev->struct_mutex);
3625                 intel_finish_fb(crtc->primary->fb);
3626                 mutex_unlock(&dev->struct_mutex);
3627         }
3628 }
3629
3630 /* Program iCLKIP clock to the desired frequency */
3631 static void lpt_program_iclkip(struct drm_crtc *crtc)
3632 {
3633         struct drm_device *dev = crtc->dev;
3634         struct drm_i915_private *dev_priv = dev->dev_private;
3635         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3636         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3637         u32 temp;
3638
3639         mutex_lock(&dev_priv->dpio_lock);
3640
3641         /* It is necessary to ungate the pixclk gate prior to programming
3642          * the divisors, and gate it back when it is done.
3643          */
3644         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3645
3646         /* Disable SSCCTL */
3647         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3648                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3649                                 SBI_SSCCTL_DISABLE,
3650                         SBI_ICLK);
3651
3652         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3653         if (clock == 20000) {
3654                 auxdiv = 1;
3655                 divsel = 0x41;
3656                 phaseinc = 0x20;
3657         } else {
3658                 /* The iCLK virtual clock root frequency is in MHz,
3659                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3660                  * divisors, it is necessary to divide one by another, so we
3661                  * convert the virtual clock precision to KHz here for higher
3662                  * precision.
3663                  */
3664                 u32 iclk_virtual_root_freq = 172800 * 1000;
3665                 u32 iclk_pi_range = 64;
3666                 u32 desired_divisor, msb_divisor_value, pi_value;
3667
3668                 desired_divisor = (iclk_virtual_root_freq / clock);
3669                 msb_divisor_value = desired_divisor / iclk_pi_range;
3670                 pi_value = desired_divisor % iclk_pi_range;
3671
3672                 auxdiv = 0;
3673                 divsel = msb_divisor_value - 2;
3674                 phaseinc = pi_value;
3675         }
3676
3677         /* This should not happen with any sane values */
3678         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3679                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3680         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3681                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3682
3683         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3684                         clock,
3685                         auxdiv,
3686                         divsel,
3687                         phasedir,
3688                         phaseinc);
3689
3690         /* Program SSCDIVINTPHASE6 */
3691         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3692         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3693         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3694         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3695         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3696         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3697         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3698         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3699
3700         /* Program SSCAUXDIV */
3701         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3702         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3703         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3704         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3705
3706         /* Enable modulator and associated divider */
3707         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3708         temp &= ~SBI_SSCCTL_DISABLE;
3709         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3710
3711         /* Wait for initialization time */
3712         udelay(24);
3713
3714         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3715
3716         mutex_unlock(&dev_priv->dpio_lock);
3717 }
3718
3719 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3720                                                 enum pipe pch_transcoder)
3721 {
3722         struct drm_device *dev = crtc->base.dev;
3723         struct drm_i915_private *dev_priv = dev->dev_private;
3724         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3725
3726         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3727                    I915_READ(HTOTAL(cpu_transcoder)));
3728         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3729                    I915_READ(HBLANK(cpu_transcoder)));
3730         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3731                    I915_READ(HSYNC(cpu_transcoder)));
3732
3733         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3734                    I915_READ(VTOTAL(cpu_transcoder)));
3735         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3736                    I915_READ(VBLANK(cpu_transcoder)));
3737         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3738                    I915_READ(VSYNC(cpu_transcoder)));
3739         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3740                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3741 }
3742
3743 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3744 {
3745         struct drm_i915_private *dev_priv = dev->dev_private;
3746         uint32_t temp;
3747
3748         temp = I915_READ(SOUTH_CHICKEN1);
3749         if (temp & FDI_BC_BIFURCATION_SELECT)
3750                 return;
3751
3752         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3753         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3754
3755         temp |= FDI_BC_BIFURCATION_SELECT;
3756         DRM_DEBUG_KMS("enabling fdi C rx\n");
3757         I915_WRITE(SOUTH_CHICKEN1, temp);
3758         POSTING_READ(SOUTH_CHICKEN1);
3759 }
3760
3761 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3762 {
3763         struct drm_device *dev = intel_crtc->base.dev;
3764         struct drm_i915_private *dev_priv = dev->dev_private;
3765
3766         switch (intel_crtc->pipe) {
3767         case PIPE_A:
3768                 break;
3769         case PIPE_B:
3770                 if (intel_crtc->config->fdi_lanes > 2)
3771                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3772                 else
3773                         cpt_enable_fdi_bc_bifurcation(dev);
3774
3775                 break;
3776         case PIPE_C:
3777                 cpt_enable_fdi_bc_bifurcation(dev);
3778
3779                 break;
3780         default:
3781                 BUG();
3782         }
3783 }
3784
3785 /*
3786  * Enable PCH resources required for PCH ports:
3787  *   - PCH PLLs
3788  *   - FDI training & RX/TX
3789  *   - update transcoder timings
3790  *   - DP transcoding bits
3791  *   - transcoder
3792  */
3793 static void ironlake_pch_enable(struct drm_crtc *crtc)
3794 {
3795         struct drm_device *dev = crtc->dev;
3796         struct drm_i915_private *dev_priv = dev->dev_private;
3797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798         int pipe = intel_crtc->pipe;
3799         u32 reg, temp;
3800
3801         assert_pch_transcoder_disabled(dev_priv, pipe);
3802
3803         if (IS_IVYBRIDGE(dev))
3804                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3805
3806         /* Write the TU size bits before fdi link training, so that error
3807          * detection works. */
3808         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3809                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3810
3811         /* For PCH output, training FDI link */
3812         dev_priv->display.fdi_link_train(crtc);
3813
3814         /* We need to program the right clock selection before writing the pixel
3815          * mutliplier into the DPLL. */
3816         if (HAS_PCH_CPT(dev)) {
3817                 u32 sel;
3818
3819                 temp = I915_READ(PCH_DPLL_SEL);
3820                 temp |= TRANS_DPLL_ENABLE(pipe);
3821                 sel = TRANS_DPLLB_SEL(pipe);
3822                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3823                         temp |= sel;
3824                 else
3825                         temp &= ~sel;
3826                 I915_WRITE(PCH_DPLL_SEL, temp);
3827         }
3828
3829         /* XXX: pch pll's can be enabled any time before we enable the PCH
3830          * transcoder, and we actually should do this to not upset any PCH
3831          * transcoder that already use the clock when we share it.
3832          *
3833          * Note that enable_shared_dpll tries to do the right thing, but
3834          * get_shared_dpll unconditionally resets the pll - we need that to have
3835          * the right LVDS enable sequence. */
3836         intel_enable_shared_dpll(intel_crtc);
3837
3838         /* set transcoder timing, panel must allow it */
3839         assert_panel_unlocked(dev_priv, pipe);
3840         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3841
3842         intel_fdi_normal_train(crtc);
3843
3844         /* For PCH DP, enable TRANS_DP_CTL */
3845         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3846                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3847                 reg = TRANS_DP_CTL(pipe);
3848                 temp = I915_READ(reg);
3849                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3850                           TRANS_DP_SYNC_MASK |
3851                           TRANS_DP_BPC_MASK);
3852                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3853                          TRANS_DP_ENH_FRAMING);
3854                 temp |= bpc << 9; /* same format but at 11:9 */
3855
3856                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3857                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3858                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3859                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3860
3861                 switch (intel_trans_dp_port_sel(crtc)) {
3862                 case PCH_DP_B:
3863                         temp |= TRANS_DP_PORT_SEL_B;
3864                         break;
3865                 case PCH_DP_C:
3866                         temp |= TRANS_DP_PORT_SEL_C;
3867                         break;
3868                 case PCH_DP_D:
3869                         temp |= TRANS_DP_PORT_SEL_D;
3870                         break;
3871                 default:
3872                         BUG();
3873                 }
3874
3875                 I915_WRITE(reg, temp);
3876         }
3877
3878         ironlake_enable_pch_transcoder(dev_priv, pipe);
3879 }
3880
3881 static void lpt_pch_enable(struct drm_crtc *crtc)
3882 {
3883         struct drm_device *dev = crtc->dev;
3884         struct drm_i915_private *dev_priv = dev->dev_private;
3885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3886         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3887
3888         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3889
3890         lpt_program_iclkip(crtc);
3891
3892         /* Set transcoder timing. */
3893         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3894
3895         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3896 }
3897
3898 void intel_put_shared_dpll(struct intel_crtc *crtc)
3899 {
3900         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3901
3902         if (pll == NULL)
3903                 return;
3904
3905         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3906                 WARN(1, "bad %s crtc mask\n", pll->name);
3907                 return;
3908         }
3909
3910         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3911         if (pll->config.crtc_mask == 0) {
3912                 WARN_ON(pll->on);
3913                 WARN_ON(pll->active);
3914         }
3915
3916         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3917 }
3918
3919 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3920                                                 struct intel_crtc_state *crtc_state)
3921 {
3922         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3923         struct intel_shared_dpll *pll;
3924         enum intel_dpll_id i;
3925
3926         if (HAS_PCH_IBX(dev_priv->dev)) {
3927                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3928                 i = (enum intel_dpll_id) crtc->pipe;
3929                 pll = &dev_priv->shared_dplls[i];
3930
3931                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3932                               crtc->base.base.id, pll->name);
3933
3934                 WARN_ON(pll->new_config->crtc_mask);
3935
3936                 goto found;
3937         }
3938
3939         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3940                 pll = &dev_priv->shared_dplls[i];
3941
3942                 /* Only want to check enabled timings first */
3943                 if (pll->new_config->crtc_mask == 0)
3944                         continue;
3945
3946                 if (memcmp(&crtc_state->dpll_hw_state,
3947                            &pll->new_config->hw_state,
3948                            sizeof(pll->new_config->hw_state)) == 0) {
3949                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3950                                       crtc->base.base.id, pll->name,
3951                                       pll->new_config->crtc_mask,
3952                                       pll->active);
3953                         goto found;
3954                 }
3955         }
3956
3957         /* Ok no matching timings, maybe there's a free one? */
3958         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3959                 pll = &dev_priv->shared_dplls[i];
3960                 if (pll->new_config->crtc_mask == 0) {
3961                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3962                                       crtc->base.base.id, pll->name);
3963                         goto found;
3964                 }
3965         }
3966
3967         return NULL;
3968
3969 found:
3970         if (pll->new_config->crtc_mask == 0)
3971                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3972
3973         crtc_state->shared_dpll = i;
3974         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3975                          pipe_name(crtc->pipe));
3976
3977         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3978
3979         return pll;
3980 }
3981
3982 /**
3983  * intel_shared_dpll_start_config - start a new PLL staged config
3984  * @dev_priv: DRM device
3985  * @clear_pipes: mask of pipes that will have their PLLs freed
3986  *
3987  * Starts a new PLL staged config, copying the current config but
3988  * releasing the references of pipes specified in clear_pipes.
3989  */
3990 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3991                                           unsigned clear_pipes)
3992 {
3993         struct intel_shared_dpll *pll;
3994         enum intel_dpll_id i;
3995
3996         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3997                 pll = &dev_priv->shared_dplls[i];
3998
3999                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4000                                           GFP_KERNEL);
4001                 if (!pll->new_config)
4002                         goto cleanup;
4003
4004                 pll->new_config->crtc_mask &= ~clear_pipes;
4005         }
4006
4007         return 0;
4008
4009 cleanup:
4010         while (--i >= 0) {
4011                 pll = &dev_priv->shared_dplls[i];
4012                 kfree(pll->new_config);
4013                 pll->new_config = NULL;
4014         }
4015
4016         return -ENOMEM;
4017 }
4018
4019 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4020 {
4021         struct intel_shared_dpll *pll;
4022         enum intel_dpll_id i;
4023
4024         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4025                 pll = &dev_priv->shared_dplls[i];
4026
4027                 WARN_ON(pll->new_config == &pll->config);
4028
4029                 pll->config = *pll->new_config;
4030                 kfree(pll->new_config);
4031                 pll->new_config = NULL;
4032         }
4033 }
4034
4035 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4036 {
4037         struct intel_shared_dpll *pll;
4038         enum intel_dpll_id i;
4039
4040         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4041                 pll = &dev_priv->shared_dplls[i];
4042
4043                 WARN_ON(pll->new_config == &pll->config);
4044
4045                 kfree(pll->new_config);
4046                 pll->new_config = NULL;
4047         }
4048 }
4049
4050 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4051 {
4052         struct drm_i915_private *dev_priv = dev->dev_private;
4053         int dslreg = PIPEDSL(pipe);
4054         u32 temp;
4055
4056         temp = I915_READ(dslreg);
4057         udelay(500);
4058         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4059                 if (wait_for(I915_READ(dslreg) != temp, 5))
4060                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4061         }
4062 }
4063
4064 static void skylake_pfit_enable(struct intel_crtc *crtc)
4065 {
4066         struct drm_device *dev = crtc->base.dev;
4067         struct drm_i915_private *dev_priv = dev->dev_private;
4068         int pipe = crtc->pipe;
4069
4070         if (crtc->config->pch_pfit.enabled) {
4071                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4072                 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4073                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4074         }
4075 }
4076
4077 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4078 {
4079         struct drm_device *dev = crtc->base.dev;
4080         struct drm_i915_private *dev_priv = dev->dev_private;
4081         int pipe = crtc->pipe;
4082
4083         if (crtc->config->pch_pfit.enabled) {
4084                 /* Force use of hard-coded filter coefficients
4085                  * as some pre-programmed values are broken,
4086                  * e.g. x201.
4087                  */
4088                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4089                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4090                                                  PF_PIPE_SEL_IVB(pipe));
4091                 else
4092                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4093                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4094                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4095         }
4096 }
4097
4098 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4099 {
4100         struct drm_device *dev = crtc->dev;
4101         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4102         struct drm_plane *plane;
4103         struct intel_plane *intel_plane;
4104
4105         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4106                 intel_plane = to_intel_plane(plane);
4107                 if (intel_plane->pipe == pipe)
4108                         intel_plane_restore(&intel_plane->base);
4109         }
4110 }
4111
4112 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4113 {
4114         struct drm_device *dev = crtc->dev;
4115         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4116         struct drm_plane *plane;
4117         struct intel_plane *intel_plane;
4118
4119         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4120                 intel_plane = to_intel_plane(plane);
4121                 if (intel_plane->pipe == pipe)
4122                         plane->funcs->disable_plane(plane);
4123         }
4124 }
4125
4126 void hsw_enable_ips(struct intel_crtc *crtc)
4127 {
4128         struct drm_device *dev = crtc->base.dev;
4129         struct drm_i915_private *dev_priv = dev->dev_private;
4130
4131         if (!crtc->config->ips_enabled)
4132                 return;
4133
4134         /* We can only enable IPS after we enable a plane and wait for a vblank */
4135         intel_wait_for_vblank(dev, crtc->pipe);
4136
4137         assert_plane_enabled(dev_priv, crtc->plane);
4138         if (IS_BROADWELL(dev)) {
4139                 mutex_lock(&dev_priv->rps.hw_lock);
4140                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4141                 mutex_unlock(&dev_priv->rps.hw_lock);
4142                 /* Quoting Art Runyan: "its not safe to expect any particular
4143                  * value in IPS_CTL bit 31 after enabling IPS through the
4144                  * mailbox." Moreover, the mailbox may return a bogus state,
4145                  * so we need to just enable it and continue on.
4146                  */
4147         } else {
4148                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4149                 /* The bit only becomes 1 in the next vblank, so this wait here
4150                  * is essentially intel_wait_for_vblank. If we don't have this
4151                  * and don't wait for vblanks until the end of crtc_enable, then
4152                  * the HW state readout code will complain that the expected
4153                  * IPS_CTL value is not the one we read. */
4154                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4155                         DRM_ERROR("Timed out waiting for IPS enable\n");
4156         }
4157 }
4158
4159 void hsw_disable_ips(struct intel_crtc *crtc)
4160 {
4161         struct drm_device *dev = crtc->base.dev;
4162         struct drm_i915_private *dev_priv = dev->dev_private;
4163
4164         if (!crtc->config->ips_enabled)
4165                 return;
4166
4167         assert_plane_enabled(dev_priv, crtc->plane);
4168         if (IS_BROADWELL(dev)) {
4169                 mutex_lock(&dev_priv->rps.hw_lock);
4170                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4171                 mutex_unlock(&dev_priv->rps.hw_lock);
4172                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4173                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4174                         DRM_ERROR("Timed out waiting for IPS disable\n");
4175         } else {
4176                 I915_WRITE(IPS_CTL, 0);
4177                 POSTING_READ(IPS_CTL);
4178         }
4179
4180         /* We need to wait for a vblank before we can disable the plane. */
4181         intel_wait_for_vblank(dev, crtc->pipe);
4182 }
4183
4184 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4185 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4186 {
4187         struct drm_device *dev = crtc->dev;
4188         struct drm_i915_private *dev_priv = dev->dev_private;
4189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4190         enum pipe pipe = intel_crtc->pipe;
4191         int palreg = PALETTE(pipe);
4192         int i;
4193         bool reenable_ips = false;
4194
4195         /* The clocks have to be on to load the palette. */
4196         if (!crtc->enabled || !intel_crtc->active)
4197                 return;
4198
4199         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4200                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4201                         assert_dsi_pll_enabled(dev_priv);
4202                 else
4203                         assert_pll_enabled(dev_priv, pipe);
4204         }
4205
4206         /* use legacy palette for Ironlake */
4207         if (!HAS_GMCH_DISPLAY(dev))
4208                 palreg = LGC_PALETTE(pipe);
4209
4210         /* Workaround : Do not read or write the pipe palette/gamma data while
4211          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4212          */
4213         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4214             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4215              GAMMA_MODE_MODE_SPLIT)) {
4216                 hsw_disable_ips(intel_crtc);
4217                 reenable_ips = true;
4218         }
4219
4220         for (i = 0; i < 256; i++) {
4221                 I915_WRITE(palreg + 4 * i,
4222                            (intel_crtc->lut_r[i] << 16) |
4223                            (intel_crtc->lut_g[i] << 8) |
4224                            intel_crtc->lut_b[i]);
4225         }
4226
4227         if (reenable_ips)
4228                 hsw_enable_ips(intel_crtc);
4229 }
4230
4231 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4232 {
4233         if (!enable && intel_crtc->overlay) {
4234                 struct drm_device *dev = intel_crtc->base.dev;
4235                 struct drm_i915_private *dev_priv = dev->dev_private;
4236
4237                 mutex_lock(&dev->struct_mutex);
4238                 dev_priv->mm.interruptible = false;
4239                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4240                 dev_priv->mm.interruptible = true;
4241                 mutex_unlock(&dev->struct_mutex);
4242         }
4243
4244         /* Let userspace switch the overlay on again. In most cases userspace
4245          * has to recompute where to put it anyway.
4246          */
4247 }
4248
4249 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4250 {
4251         struct drm_device *dev = crtc->dev;
4252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4253         int pipe = intel_crtc->pipe;
4254
4255         intel_enable_primary_hw_plane(crtc->primary, crtc);
4256         intel_enable_sprite_planes(crtc);
4257         intel_crtc_update_cursor(crtc, true);
4258         intel_crtc_dpms_overlay(intel_crtc, true);
4259
4260         hsw_enable_ips(intel_crtc);
4261
4262         mutex_lock(&dev->struct_mutex);
4263         intel_fbc_update(dev);
4264         mutex_unlock(&dev->struct_mutex);
4265
4266         /*
4267          * FIXME: Once we grow proper nuclear flip support out of this we need
4268          * to compute the mask of flip planes precisely. For the time being
4269          * consider this a flip from a NULL plane.
4270          */
4271         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4272 }
4273
4274 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4275 {
4276         struct drm_device *dev = crtc->dev;
4277         struct drm_i915_private *dev_priv = dev->dev_private;
4278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4279         int pipe = intel_crtc->pipe;
4280
4281         intel_crtc_wait_for_pending_flips(crtc);
4282
4283         if (dev_priv->fbc.crtc == intel_crtc)
4284                 intel_fbc_disable(dev);
4285
4286         hsw_disable_ips(intel_crtc);
4287
4288         intel_crtc_dpms_overlay(intel_crtc, false);
4289         intel_crtc_update_cursor(crtc, false);
4290         intel_disable_sprite_planes(crtc);
4291         intel_disable_primary_hw_plane(crtc->primary, crtc);
4292
4293         /*
4294          * FIXME: Once we grow proper nuclear flip support out of this we need
4295          * to compute the mask of flip planes precisely. For the time being
4296          * consider this a flip to a NULL plane.
4297          */
4298         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4299 }
4300
4301 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4302 {
4303         struct drm_device *dev = crtc->dev;
4304         struct drm_i915_private *dev_priv = dev->dev_private;
4305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4306         struct intel_encoder *encoder;
4307         int pipe = intel_crtc->pipe;
4308
4309         WARN_ON(!crtc->enabled);
4310
4311         if (intel_crtc->active)
4312                 return;
4313
4314         if (intel_crtc->config->has_pch_encoder)
4315                 intel_prepare_shared_dpll(intel_crtc);
4316
4317         if (intel_crtc->config->has_dp_encoder)
4318                 intel_dp_set_m_n(intel_crtc);
4319
4320         intel_set_pipe_timings(intel_crtc);
4321
4322         if (intel_crtc->config->has_pch_encoder) {
4323                 intel_cpu_transcoder_set_m_n(intel_crtc,
4324                                      &intel_crtc->config->fdi_m_n, NULL);
4325         }
4326
4327         ironlake_set_pipeconf(crtc);
4328
4329         intel_crtc->active = true;
4330
4331         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4332         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4333
4334         for_each_encoder_on_crtc(dev, crtc, encoder)
4335                 if (encoder->pre_enable)
4336                         encoder->pre_enable(encoder);
4337
4338         if (intel_crtc->config->has_pch_encoder) {
4339                 /* Note: FDI PLL enabling _must_ be done before we enable the
4340                  * cpu pipes, hence this is separate from all the other fdi/pch
4341                  * enabling. */
4342                 ironlake_fdi_pll_enable(intel_crtc);
4343         } else {
4344                 assert_fdi_tx_disabled(dev_priv, pipe);
4345                 assert_fdi_rx_disabled(dev_priv, pipe);
4346         }
4347
4348         ironlake_pfit_enable(intel_crtc);
4349
4350         /*
4351          * On ILK+ LUT must be loaded before the pipe is running but with
4352          * clocks enabled
4353          */
4354         intel_crtc_load_lut(crtc);
4355
4356         intel_update_watermarks(crtc);
4357         intel_enable_pipe(intel_crtc);
4358
4359         if (intel_crtc->config->has_pch_encoder)
4360                 ironlake_pch_enable(crtc);
4361
4362         assert_vblank_disabled(crtc);
4363         drm_crtc_vblank_on(crtc);
4364
4365         for_each_encoder_on_crtc(dev, crtc, encoder)
4366                 encoder->enable(encoder);
4367
4368         if (HAS_PCH_CPT(dev))
4369                 cpt_verify_modeset(dev, intel_crtc->pipe);
4370
4371         intel_crtc_enable_planes(crtc);
4372 }
4373
4374 /* IPS only exists on ULT machines and is tied to pipe A. */
4375 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4376 {
4377         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4378 }
4379
4380 /*
4381  * This implements the workaround described in the "notes" section of the mode
4382  * set sequence documentation. When going from no pipes or single pipe to
4383  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4384  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4385  */
4386 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4387 {
4388         struct drm_device *dev = crtc->base.dev;
4389         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4390
4391         /* We want to get the other_active_crtc only if there's only 1 other
4392          * active crtc. */
4393         for_each_intel_crtc(dev, crtc_it) {
4394                 if (!crtc_it->active || crtc_it == crtc)
4395                         continue;
4396
4397                 if (other_active_crtc)
4398                         return;
4399
4400                 other_active_crtc = crtc_it;
4401         }
4402         if (!other_active_crtc)
4403                 return;
4404
4405         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4406         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4407 }
4408
4409 static void haswell_crtc_enable(struct drm_crtc *crtc)
4410 {
4411         struct drm_device *dev = crtc->dev;
4412         struct drm_i915_private *dev_priv = dev->dev_private;
4413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4414         struct intel_encoder *encoder;
4415         int pipe = intel_crtc->pipe;
4416
4417         WARN_ON(!crtc->enabled);
4418
4419         if (intel_crtc->active)
4420                 return;
4421
4422         if (intel_crtc_to_shared_dpll(intel_crtc))
4423                 intel_enable_shared_dpll(intel_crtc);
4424
4425         if (intel_crtc->config->has_dp_encoder)
4426                 intel_dp_set_m_n(intel_crtc);
4427
4428         intel_set_pipe_timings(intel_crtc);
4429
4430         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4431                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4432                            intel_crtc->config->pixel_multiplier - 1);
4433         }
4434
4435         if (intel_crtc->config->has_pch_encoder) {
4436                 intel_cpu_transcoder_set_m_n(intel_crtc,
4437                                      &intel_crtc->config->fdi_m_n, NULL);
4438         }
4439
4440         haswell_set_pipeconf(crtc);
4441
4442         intel_set_pipe_csc(crtc);
4443
4444         intel_crtc->active = true;
4445
4446         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4447         for_each_encoder_on_crtc(dev, crtc, encoder)
4448                 if (encoder->pre_enable)
4449                         encoder->pre_enable(encoder);
4450
4451         if (intel_crtc->config->has_pch_encoder) {
4452                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4453                                                       true);
4454                 dev_priv->display.fdi_link_train(crtc);
4455         }
4456
4457         intel_ddi_enable_pipe_clock(intel_crtc);
4458
4459         if (IS_SKYLAKE(dev))
4460                 skylake_pfit_enable(intel_crtc);
4461         else
4462                 ironlake_pfit_enable(intel_crtc);
4463
4464         /*
4465          * On ILK+ LUT must be loaded before the pipe is running but with
4466          * clocks enabled
4467          */
4468         intel_crtc_load_lut(crtc);
4469
4470         intel_ddi_set_pipe_settings(crtc);
4471         intel_ddi_enable_transcoder_func(crtc);
4472
4473         intel_update_watermarks(crtc);
4474         intel_enable_pipe(intel_crtc);
4475
4476         if (intel_crtc->config->has_pch_encoder)
4477                 lpt_pch_enable(crtc);
4478
4479         if (intel_crtc->config->dp_encoder_is_mst)
4480                 intel_ddi_set_vc_payload_alloc(crtc, true);
4481
4482         assert_vblank_disabled(crtc);
4483         drm_crtc_vblank_on(crtc);
4484
4485         for_each_encoder_on_crtc(dev, crtc, encoder) {
4486                 encoder->enable(encoder);
4487                 intel_opregion_notify_encoder(encoder, true);
4488         }
4489
4490         /* If we change the relative order between pipe/planes enabling, we need
4491          * to change the workaround. */
4492         haswell_mode_set_planes_workaround(intel_crtc);
4493         intel_crtc_enable_planes(crtc);
4494 }
4495
4496 static void skylake_pfit_disable(struct intel_crtc *crtc)
4497 {
4498         struct drm_device *dev = crtc->base.dev;
4499         struct drm_i915_private *dev_priv = dev->dev_private;
4500         int pipe = crtc->pipe;
4501
4502         /* To avoid upsetting the power well on haswell only disable the pfit if
4503          * it's in use. The hw state code will make sure we get this right. */
4504         if (crtc->config->pch_pfit.enabled) {
4505                 I915_WRITE(PS_CTL(pipe), 0);
4506                 I915_WRITE(PS_WIN_POS(pipe), 0);
4507                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4508         }
4509 }
4510
4511 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4512 {
4513         struct drm_device *dev = crtc->base.dev;
4514         struct drm_i915_private *dev_priv = dev->dev_private;
4515         int pipe = crtc->pipe;
4516
4517         /* To avoid upsetting the power well on haswell only disable the pfit if
4518          * it's in use. The hw state code will make sure we get this right. */
4519         if (crtc->config->pch_pfit.enabled) {
4520                 I915_WRITE(PF_CTL(pipe), 0);
4521                 I915_WRITE(PF_WIN_POS(pipe), 0);
4522                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4523         }
4524 }
4525
4526 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4527 {
4528         struct drm_device *dev = crtc->dev;
4529         struct drm_i915_private *dev_priv = dev->dev_private;
4530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4531         struct intel_encoder *encoder;
4532         int pipe = intel_crtc->pipe;
4533         u32 reg, temp;
4534
4535         if (!intel_crtc->active)
4536                 return;
4537
4538         intel_crtc_disable_planes(crtc);
4539
4540         for_each_encoder_on_crtc(dev, crtc, encoder)
4541                 encoder->disable(encoder);
4542
4543         drm_crtc_vblank_off(crtc);
4544         assert_vblank_disabled(crtc);
4545
4546         if (intel_crtc->config->has_pch_encoder)
4547                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4548
4549         intel_disable_pipe(intel_crtc);
4550
4551         ironlake_pfit_disable(intel_crtc);
4552
4553         for_each_encoder_on_crtc(dev, crtc, encoder)
4554                 if (encoder->post_disable)
4555                         encoder->post_disable(encoder);
4556
4557         if (intel_crtc->config->has_pch_encoder) {
4558                 ironlake_fdi_disable(crtc);
4559
4560                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4561
4562                 if (HAS_PCH_CPT(dev)) {
4563                         /* disable TRANS_DP_CTL */
4564                         reg = TRANS_DP_CTL(pipe);
4565                         temp = I915_READ(reg);
4566                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4567                                   TRANS_DP_PORT_SEL_MASK);
4568                         temp |= TRANS_DP_PORT_SEL_NONE;
4569                         I915_WRITE(reg, temp);
4570
4571                         /* disable DPLL_SEL */
4572                         temp = I915_READ(PCH_DPLL_SEL);
4573                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4574                         I915_WRITE(PCH_DPLL_SEL, temp);
4575                 }
4576
4577                 /* disable PCH DPLL */
4578                 intel_disable_shared_dpll(intel_crtc);
4579
4580                 ironlake_fdi_pll_disable(intel_crtc);
4581         }
4582
4583         intel_crtc->active = false;
4584         intel_update_watermarks(crtc);
4585
4586         mutex_lock(&dev->struct_mutex);
4587         intel_fbc_update(dev);
4588         mutex_unlock(&dev->struct_mutex);
4589 }
4590
4591 static void haswell_crtc_disable(struct drm_crtc *crtc)
4592 {
4593         struct drm_device *dev = crtc->dev;
4594         struct drm_i915_private *dev_priv = dev->dev_private;
4595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4596         struct intel_encoder *encoder;
4597         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4598
4599         if (!intel_crtc->active)
4600                 return;
4601
4602         intel_crtc_disable_planes(crtc);
4603
4604         for_each_encoder_on_crtc(dev, crtc, encoder) {
4605                 intel_opregion_notify_encoder(encoder, false);
4606                 encoder->disable(encoder);
4607         }
4608
4609         drm_crtc_vblank_off(crtc);
4610         assert_vblank_disabled(crtc);
4611
4612         if (intel_crtc->config->has_pch_encoder)
4613                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4614                                                       false);
4615         intel_disable_pipe(intel_crtc);
4616
4617         if (intel_crtc->config->dp_encoder_is_mst)
4618                 intel_ddi_set_vc_payload_alloc(crtc, false);
4619
4620         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4621
4622         if (IS_SKYLAKE(dev))
4623                 skylake_pfit_disable(intel_crtc);
4624         else
4625                 ironlake_pfit_disable(intel_crtc);
4626
4627         intel_ddi_disable_pipe_clock(intel_crtc);
4628
4629         if (intel_crtc->config->has_pch_encoder) {
4630                 lpt_disable_pch_transcoder(dev_priv);
4631                 intel_ddi_fdi_disable(crtc);
4632         }
4633
4634         for_each_encoder_on_crtc(dev, crtc, encoder)
4635                 if (encoder->post_disable)
4636                         encoder->post_disable(encoder);
4637
4638         intel_crtc->active = false;
4639         intel_update_watermarks(crtc);
4640
4641         mutex_lock(&dev->struct_mutex);
4642         intel_fbc_update(dev);
4643         mutex_unlock(&dev->struct_mutex);
4644
4645         if (intel_crtc_to_shared_dpll(intel_crtc))
4646                 intel_disable_shared_dpll(intel_crtc);
4647 }
4648
4649 static void ironlake_crtc_off(struct drm_crtc *crtc)
4650 {
4651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4652         intel_put_shared_dpll(intel_crtc);
4653 }
4654
4655
4656 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4657 {
4658         struct drm_device *dev = crtc->base.dev;
4659         struct drm_i915_private *dev_priv = dev->dev_private;
4660         struct intel_crtc_state *pipe_config = crtc->config;
4661
4662         if (!pipe_config->gmch_pfit.control)
4663                 return;
4664
4665         /*
4666          * The panel fitter should only be adjusted whilst the pipe is disabled,
4667          * according to register description and PRM.
4668          */
4669         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4670         assert_pipe_disabled(dev_priv, crtc->pipe);
4671
4672         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4673         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4674
4675         /* Border color in case we don't scale up to the full screen. Black by
4676          * default, change to something else for debugging. */
4677         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4678 }
4679
4680 static enum intel_display_power_domain port_to_power_domain(enum port port)
4681 {
4682         switch (port) {
4683         case PORT_A:
4684                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4685         case PORT_B:
4686                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4687         case PORT_C:
4688                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4689         case PORT_D:
4690                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4691         default:
4692                 WARN_ON_ONCE(1);
4693                 return POWER_DOMAIN_PORT_OTHER;
4694         }
4695 }
4696
4697 #define for_each_power_domain(domain, mask)                             \
4698         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4699                 if ((1 << (domain)) & (mask))
4700
4701 enum intel_display_power_domain
4702 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4703 {
4704         struct drm_device *dev = intel_encoder->base.dev;
4705         struct intel_digital_port *intel_dig_port;
4706
4707         switch (intel_encoder->type) {
4708         case INTEL_OUTPUT_UNKNOWN:
4709                 /* Only DDI platforms should ever use this output type */
4710                 WARN_ON_ONCE(!HAS_DDI(dev));
4711         case INTEL_OUTPUT_DISPLAYPORT:
4712         case INTEL_OUTPUT_HDMI:
4713         case INTEL_OUTPUT_EDP:
4714                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4715                 return port_to_power_domain(intel_dig_port->port);
4716         case INTEL_OUTPUT_DP_MST:
4717                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4718                 return port_to_power_domain(intel_dig_port->port);
4719         case INTEL_OUTPUT_ANALOG:
4720                 return POWER_DOMAIN_PORT_CRT;
4721         case INTEL_OUTPUT_DSI:
4722                 return POWER_DOMAIN_PORT_DSI;
4723         default:
4724                 return POWER_DOMAIN_PORT_OTHER;
4725         }
4726 }
4727
4728 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4729 {
4730         struct drm_device *dev = crtc->dev;
4731         struct intel_encoder *intel_encoder;
4732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4733         enum pipe pipe = intel_crtc->pipe;
4734         unsigned long mask;
4735         enum transcoder transcoder;
4736
4737         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4738
4739         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4740         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4741         if (intel_crtc->config->pch_pfit.enabled ||
4742             intel_crtc->config->pch_pfit.force_thru)
4743                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4744
4745         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4746                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4747
4748         return mask;
4749 }
4750
4751 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4752 {
4753         struct drm_i915_private *dev_priv = dev->dev_private;
4754         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4755         struct intel_crtc *crtc;
4756
4757         /*
4758          * First get all needed power domains, then put all unneeded, to avoid
4759          * any unnecessary toggling of the power wells.
4760          */
4761         for_each_intel_crtc(dev, crtc) {
4762                 enum intel_display_power_domain domain;
4763
4764                 if (!crtc->base.enabled)
4765                         continue;
4766
4767                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4768
4769                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4770                         intel_display_power_get(dev_priv, domain);
4771         }
4772
4773         if (dev_priv->display.modeset_global_resources)
4774                 dev_priv->display.modeset_global_resources(dev);
4775
4776         for_each_intel_crtc(dev, crtc) {
4777                 enum intel_display_power_domain domain;
4778
4779                 for_each_power_domain(domain, crtc->enabled_power_domains)
4780                         intel_display_power_put(dev_priv, domain);
4781
4782                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4783         }
4784
4785         intel_display_set_init_power(dev_priv, false);
4786 }
4787
4788 /* returns HPLL frequency in kHz */
4789 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4790 {
4791         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4792
4793         /* Obtain SKU information */
4794         mutex_lock(&dev_priv->dpio_lock);
4795         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4796                 CCK_FUSE_HPLL_FREQ_MASK;
4797         mutex_unlock(&dev_priv->dpio_lock);
4798
4799         return vco_freq[hpll_freq] * 1000;
4800 }
4801
4802 static void vlv_update_cdclk(struct drm_device *dev)
4803 {
4804         struct drm_i915_private *dev_priv = dev->dev_private;
4805
4806         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4807         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4808                          dev_priv->vlv_cdclk_freq);
4809
4810         /*
4811          * Program the gmbus_freq based on the cdclk frequency.
4812          * BSpec erroneously claims we should aim for 4MHz, but
4813          * in fact 1MHz is the correct frequency.
4814          */
4815         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4816 }
4817
4818 /* Adjust CDclk dividers to allow high res or save power if possible */
4819 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4820 {
4821         struct drm_i915_private *dev_priv = dev->dev_private;
4822         u32 val, cmd;
4823
4824         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4825
4826         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4827                 cmd = 2;
4828         else if (cdclk == 266667)
4829                 cmd = 1;
4830         else
4831                 cmd = 0;
4832
4833         mutex_lock(&dev_priv->rps.hw_lock);
4834         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4835         val &= ~DSPFREQGUAR_MASK;
4836         val |= (cmd << DSPFREQGUAR_SHIFT);
4837         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4838         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4839                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4840                      50)) {
4841                 DRM_ERROR("timed out waiting for CDclk change\n");
4842         }
4843         mutex_unlock(&dev_priv->rps.hw_lock);
4844
4845         if (cdclk == 400000) {
4846                 u32 divider;
4847
4848                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4849
4850                 mutex_lock(&dev_priv->dpio_lock);
4851                 /* adjust cdclk divider */
4852                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4853                 val &= ~DISPLAY_FREQUENCY_VALUES;
4854                 val |= divider;
4855                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4856
4857                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4858                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4859                              50))
4860                         DRM_ERROR("timed out waiting for CDclk change\n");
4861                 mutex_unlock(&dev_priv->dpio_lock);
4862         }
4863
4864         mutex_lock(&dev_priv->dpio_lock);
4865         /* adjust self-refresh exit latency value */
4866         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4867         val &= ~0x7f;
4868
4869         /*
4870          * For high bandwidth configs, we set a higher latency in the bunit
4871          * so that the core display fetch happens in time to avoid underruns.
4872          */
4873         if (cdclk == 400000)
4874                 val |= 4500 / 250; /* 4.5 usec */
4875         else
4876                 val |= 3000 / 250; /* 3.0 usec */
4877         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4878         mutex_unlock(&dev_priv->dpio_lock);
4879
4880         vlv_update_cdclk(dev);
4881 }
4882
4883 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4884 {
4885         struct drm_i915_private *dev_priv = dev->dev_private;
4886         u32 val, cmd;
4887
4888         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4889
4890         switch (cdclk) {
4891         case 400000:
4892                 cmd = 3;
4893                 break;
4894         case 333333:
4895         case 320000:
4896                 cmd = 2;
4897                 break;
4898         case 266667:
4899                 cmd = 1;
4900                 break;
4901         case 200000:
4902                 cmd = 0;
4903                 break;
4904         default:
4905                 MISSING_CASE(cdclk);
4906                 return;
4907         }
4908
4909         mutex_lock(&dev_priv->rps.hw_lock);
4910         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4911         val &= ~DSPFREQGUAR_MASK_CHV;
4912         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4913         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4914         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4915                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4916                      50)) {
4917                 DRM_ERROR("timed out waiting for CDclk change\n");
4918         }
4919         mutex_unlock(&dev_priv->rps.hw_lock);
4920
4921         vlv_update_cdclk(dev);
4922 }
4923
4924 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4925                                  int max_pixclk)
4926 {
4927         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4928
4929         /* FIXME: Punit isn't quite ready yet */
4930         if (IS_CHERRYVIEW(dev_priv->dev))
4931                 return 400000;
4932
4933         /*
4934          * Really only a few cases to deal with, as only 4 CDclks are supported:
4935          *   200MHz
4936          *   267MHz
4937          *   320/333MHz (depends on HPLL freq)
4938          *   400MHz
4939          * So we check to see whether we're above 90% of the lower bin and
4940          * adjust if needed.
4941          *
4942          * We seem to get an unstable or solid color picture at 200MHz.
4943          * Not sure what's wrong. For now use 200MHz only when all pipes
4944          * are off.
4945          */
4946         if (max_pixclk > freq_320*9/10)
4947                 return 400000;
4948         else if (max_pixclk > 266667*9/10)
4949                 return freq_320;
4950         else if (max_pixclk > 0)
4951                 return 266667;
4952         else
4953                 return 200000;
4954 }
4955
4956 /* compute the max pixel clock for new configuration */
4957 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4958 {
4959         struct drm_device *dev = dev_priv->dev;
4960         struct intel_crtc *intel_crtc;
4961         int max_pixclk = 0;
4962
4963         for_each_intel_crtc(dev, intel_crtc) {
4964                 if (intel_crtc->new_enabled)
4965                         max_pixclk = max(max_pixclk,
4966                                          intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4967         }
4968
4969         return max_pixclk;
4970 }
4971
4972 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4973                                             unsigned *prepare_pipes)
4974 {
4975         struct drm_i915_private *dev_priv = dev->dev_private;
4976         struct intel_crtc *intel_crtc;
4977         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4978
4979         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4980             dev_priv->vlv_cdclk_freq)
4981                 return;
4982
4983         /* disable/enable all currently active pipes while we change cdclk */
4984         for_each_intel_crtc(dev, intel_crtc)
4985                 if (intel_crtc->base.enabled)
4986                         *prepare_pipes |= (1 << intel_crtc->pipe);
4987 }
4988
4989 static void valleyview_modeset_global_resources(struct drm_device *dev)
4990 {
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4993         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4994
4995         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4996                 /*
4997                  * FIXME: We can end up here with all power domains off, yet
4998                  * with a CDCLK frequency other than the minimum. To account
4999                  * for this take the PIPE-A power domain, which covers the HW
5000                  * blocks needed for the following programming. This can be
5001                  * removed once it's guaranteed that we get here either with
5002                  * the minimum CDCLK set, or the required power domains
5003                  * enabled.
5004                  */
5005                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5006
5007                 if (IS_CHERRYVIEW(dev))
5008                         cherryview_set_cdclk(dev, req_cdclk);
5009                 else
5010                         valleyview_set_cdclk(dev, req_cdclk);
5011
5012                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5013         }
5014 }
5015
5016 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5017 {
5018         struct drm_device *dev = crtc->dev;
5019         struct drm_i915_private *dev_priv = to_i915(dev);
5020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5021         struct intel_encoder *encoder;
5022         int pipe = intel_crtc->pipe;
5023         bool is_dsi;
5024
5025         WARN_ON(!crtc->enabled);
5026
5027         if (intel_crtc->active)
5028                 return;
5029
5030         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5031
5032         if (!is_dsi) {
5033                 if (IS_CHERRYVIEW(dev))
5034                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5035                 else
5036                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5037         }
5038
5039         if (intel_crtc->config->has_dp_encoder)
5040                 intel_dp_set_m_n(intel_crtc);
5041
5042         intel_set_pipe_timings(intel_crtc);
5043
5044         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5045                 struct drm_i915_private *dev_priv = dev->dev_private;
5046
5047                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5048                 I915_WRITE(CHV_CANVAS(pipe), 0);
5049         }
5050
5051         i9xx_set_pipeconf(intel_crtc);
5052
5053         intel_crtc->active = true;
5054
5055         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5056
5057         for_each_encoder_on_crtc(dev, crtc, encoder)
5058                 if (encoder->pre_pll_enable)
5059                         encoder->pre_pll_enable(encoder);
5060
5061         if (!is_dsi) {
5062                 if (IS_CHERRYVIEW(dev))
5063                         chv_enable_pll(intel_crtc, intel_crtc->config);
5064                 else
5065                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5066         }
5067
5068         for_each_encoder_on_crtc(dev, crtc, encoder)
5069                 if (encoder->pre_enable)
5070                         encoder->pre_enable(encoder);
5071
5072         i9xx_pfit_enable(intel_crtc);
5073
5074         intel_crtc_load_lut(crtc);
5075
5076         intel_update_watermarks(crtc);
5077         intel_enable_pipe(intel_crtc);
5078
5079         assert_vblank_disabled(crtc);
5080         drm_crtc_vblank_on(crtc);
5081
5082         for_each_encoder_on_crtc(dev, crtc, encoder)
5083                 encoder->enable(encoder);
5084
5085         intel_crtc_enable_planes(crtc);
5086
5087         /* Underruns don't raise interrupts, so check manually. */
5088         i9xx_check_fifo_underruns(dev_priv);
5089 }
5090
5091 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5092 {
5093         struct drm_device *dev = crtc->base.dev;
5094         struct drm_i915_private *dev_priv = dev->dev_private;
5095
5096         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5097         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5098 }
5099
5100 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5101 {
5102         struct drm_device *dev = crtc->dev;
5103         struct drm_i915_private *dev_priv = to_i915(dev);
5104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5105         struct intel_encoder *encoder;
5106         int pipe = intel_crtc->pipe;
5107
5108         WARN_ON(!crtc->enabled);
5109
5110         if (intel_crtc->active)
5111                 return;
5112
5113         i9xx_set_pll_dividers(intel_crtc);
5114
5115         if (intel_crtc->config->has_dp_encoder)
5116                 intel_dp_set_m_n(intel_crtc);
5117
5118         intel_set_pipe_timings(intel_crtc);
5119
5120         i9xx_set_pipeconf(intel_crtc);
5121
5122         intel_crtc->active = true;
5123
5124         if (!IS_GEN2(dev))
5125                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5126
5127         for_each_encoder_on_crtc(dev, crtc, encoder)
5128                 if (encoder->pre_enable)
5129                         encoder->pre_enable(encoder);
5130
5131         i9xx_enable_pll(intel_crtc);
5132
5133         i9xx_pfit_enable(intel_crtc);
5134
5135         intel_crtc_load_lut(crtc);
5136
5137         intel_update_watermarks(crtc);
5138         intel_enable_pipe(intel_crtc);
5139
5140         assert_vblank_disabled(crtc);
5141         drm_crtc_vblank_on(crtc);
5142
5143         for_each_encoder_on_crtc(dev, crtc, encoder)
5144                 encoder->enable(encoder);
5145
5146         intel_crtc_enable_planes(crtc);
5147
5148         /*
5149          * Gen2 reports pipe underruns whenever all planes are disabled.
5150          * So don't enable underrun reporting before at least some planes
5151          * are enabled.
5152          * FIXME: Need to fix the logic to work when we turn off all planes
5153          * but leave the pipe running.
5154          */
5155         if (IS_GEN2(dev))
5156                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5157
5158         /* Underruns don't raise interrupts, so check manually. */
5159         i9xx_check_fifo_underruns(dev_priv);
5160 }
5161
5162 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5163 {
5164         struct drm_device *dev = crtc->base.dev;
5165         struct drm_i915_private *dev_priv = dev->dev_private;
5166
5167         if (!crtc->config->gmch_pfit.control)
5168                 return;
5169
5170         assert_pipe_disabled(dev_priv, crtc->pipe);
5171
5172         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5173                          I915_READ(PFIT_CONTROL));
5174         I915_WRITE(PFIT_CONTROL, 0);
5175 }
5176
5177 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5178 {
5179         struct drm_device *dev = crtc->dev;
5180         struct drm_i915_private *dev_priv = dev->dev_private;
5181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5182         struct intel_encoder *encoder;
5183         int pipe = intel_crtc->pipe;
5184
5185         if (!intel_crtc->active)
5186                 return;
5187
5188         /*
5189          * Gen2 reports pipe underruns whenever all planes are disabled.
5190          * So diasble underrun reporting before all the planes get disabled.
5191          * FIXME: Need to fix the logic to work when we turn off all planes
5192          * but leave the pipe running.
5193          */
5194         if (IS_GEN2(dev))
5195                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5196
5197         /*
5198          * Vblank time updates from the shadow to live plane control register
5199          * are blocked if the memory self-refresh mode is active at that
5200          * moment. So to make sure the plane gets truly disabled, disable
5201          * first the self-refresh mode. The self-refresh enable bit in turn
5202          * will be checked/applied by the HW only at the next frame start
5203          * event which is after the vblank start event, so we need to have a
5204          * wait-for-vblank between disabling the plane and the pipe.
5205          */
5206         intel_set_memory_cxsr(dev_priv, false);
5207         intel_crtc_disable_planes(crtc);
5208
5209         /*
5210          * On gen2 planes are double buffered but the pipe isn't, so we must
5211          * wait for planes to fully turn off before disabling the pipe.
5212          * We also need to wait on all gmch platforms because of the
5213          * self-refresh mode constraint explained above.
5214          */
5215         intel_wait_for_vblank(dev, pipe);
5216
5217         for_each_encoder_on_crtc(dev, crtc, encoder)
5218                 encoder->disable(encoder);
5219
5220         drm_crtc_vblank_off(crtc);
5221         assert_vblank_disabled(crtc);
5222
5223         intel_disable_pipe(intel_crtc);
5224
5225         i9xx_pfit_disable(intel_crtc);
5226
5227         for_each_encoder_on_crtc(dev, crtc, encoder)
5228                 if (encoder->post_disable)
5229                         encoder->post_disable(encoder);
5230
5231         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5232                 if (IS_CHERRYVIEW(dev))
5233                         chv_disable_pll(dev_priv, pipe);
5234                 else if (IS_VALLEYVIEW(dev))
5235                         vlv_disable_pll(dev_priv, pipe);
5236                 else
5237                         i9xx_disable_pll(intel_crtc);
5238         }
5239
5240         if (!IS_GEN2(dev))
5241                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5242
5243         intel_crtc->active = false;
5244         intel_update_watermarks(crtc);
5245
5246         mutex_lock(&dev->struct_mutex);
5247         intel_fbc_update(dev);
5248         mutex_unlock(&dev->struct_mutex);
5249 }
5250
5251 static void i9xx_crtc_off(struct drm_crtc *crtc)
5252 {
5253 }
5254
5255 /* Master function to enable/disable CRTC and corresponding power wells */
5256 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5257 {
5258         struct drm_device *dev = crtc->dev;
5259         struct drm_i915_private *dev_priv = dev->dev_private;
5260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5261         enum intel_display_power_domain domain;
5262         unsigned long domains;
5263
5264         if (enable) {
5265                 if (!intel_crtc->active) {
5266                         domains = get_crtc_power_domains(crtc);
5267                         for_each_power_domain(domain, domains)
5268                                 intel_display_power_get(dev_priv, domain);
5269                         intel_crtc->enabled_power_domains = domains;
5270
5271                         dev_priv->display.crtc_enable(crtc);
5272                 }
5273         } else {
5274                 if (intel_crtc->active) {
5275                         dev_priv->display.crtc_disable(crtc);
5276
5277                         domains = intel_crtc->enabled_power_domains;
5278                         for_each_power_domain(domain, domains)
5279                                 intel_display_power_put(dev_priv, domain);
5280                         intel_crtc->enabled_power_domains = 0;
5281                 }
5282         }
5283 }
5284
5285 /**
5286  * Sets the power management mode of the pipe and plane.
5287  */
5288 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5289 {
5290         struct drm_device *dev = crtc->dev;
5291         struct intel_encoder *intel_encoder;
5292         bool enable = false;
5293
5294         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5295                 enable |= intel_encoder->connectors_active;
5296
5297         intel_crtc_control(crtc, enable);
5298 }
5299
5300 static void intel_crtc_disable(struct drm_crtc *crtc)
5301 {
5302         struct drm_device *dev = crtc->dev;
5303         struct drm_connector *connector;
5304         struct drm_i915_private *dev_priv = dev->dev_private;
5305
5306         /* crtc should still be enabled when we disable it. */
5307         WARN_ON(!crtc->enabled);
5308
5309         dev_priv->display.crtc_disable(crtc);
5310         dev_priv->display.off(crtc);
5311
5312         crtc->primary->funcs->disable_plane(crtc->primary);
5313
5314         /* Update computed state. */
5315         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5316                 if (!connector->encoder || !connector->encoder->crtc)
5317                         continue;
5318
5319                 if (connector->encoder->crtc != crtc)
5320                         continue;
5321
5322                 connector->dpms = DRM_MODE_DPMS_OFF;
5323                 to_intel_encoder(connector->encoder)->connectors_active = false;
5324         }
5325 }
5326
5327 void intel_encoder_destroy(struct drm_encoder *encoder)
5328 {
5329         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5330
5331         drm_encoder_cleanup(encoder);
5332         kfree(intel_encoder);
5333 }
5334
5335 /* Simple dpms helper for encoders with just one connector, no cloning and only
5336  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5337  * state of the entire output pipe. */
5338 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5339 {
5340         if (mode == DRM_MODE_DPMS_ON) {
5341                 encoder->connectors_active = true;
5342
5343                 intel_crtc_update_dpms(encoder->base.crtc);
5344         } else {
5345                 encoder->connectors_active = false;
5346
5347                 intel_crtc_update_dpms(encoder->base.crtc);
5348         }
5349 }
5350
5351 /* Cross check the actual hw state with our own modeset state tracking (and it's
5352  * internal consistency). */
5353 static void intel_connector_check_state(struct intel_connector *connector)
5354 {
5355         if (connector->get_hw_state(connector)) {
5356                 struct intel_encoder *encoder = connector->encoder;
5357                 struct drm_crtc *crtc;
5358                 bool encoder_enabled;
5359                 enum pipe pipe;
5360
5361                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5362                               connector->base.base.id,
5363                               connector->base.name);
5364
5365                 /* there is no real hw state for MST connectors */
5366                 if (connector->mst_port)
5367                         return;
5368
5369                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5370                      "wrong connector dpms state\n");
5371                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5372                      "active connector not linked to encoder\n");
5373
5374                 if (encoder) {
5375                         I915_STATE_WARN(!encoder->connectors_active,
5376                              "encoder->connectors_active not set\n");
5377
5378                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5379                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5380                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
5381                                 return;
5382
5383                         crtc = encoder->base.crtc;
5384
5385                         I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5386                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5387                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5388                              "encoder active on the wrong pipe\n");
5389                 }
5390         }
5391 }
5392
5393 /* Even simpler default implementation, if there's really no special case to
5394  * consider. */
5395 void intel_connector_dpms(struct drm_connector *connector, int mode)
5396 {
5397         /* All the simple cases only support two dpms states. */
5398         if (mode != DRM_MODE_DPMS_ON)
5399                 mode = DRM_MODE_DPMS_OFF;
5400
5401         if (mode == connector->dpms)
5402                 return;
5403
5404         connector->dpms = mode;
5405
5406         /* Only need to change hw state when actually enabled */
5407         if (connector->encoder)
5408                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5409
5410         intel_modeset_check_state(connector->dev);
5411 }
5412
5413 /* Simple connector->get_hw_state implementation for encoders that support only
5414  * one connector and no cloning and hence the encoder state determines the state
5415  * of the connector. */
5416 bool intel_connector_get_hw_state(struct intel_connector *connector)
5417 {
5418         enum pipe pipe = 0;
5419         struct intel_encoder *encoder = connector->encoder;
5420
5421         return encoder->get_hw_state(encoder, &pipe);
5422 }
5423
5424 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5425                                      struct intel_crtc_state *pipe_config)
5426 {
5427         struct drm_i915_private *dev_priv = dev->dev_private;
5428         struct intel_crtc *pipe_B_crtc =
5429                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5430
5431         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5432                       pipe_name(pipe), pipe_config->fdi_lanes);
5433         if (pipe_config->fdi_lanes > 4) {
5434                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5435                               pipe_name(pipe), pipe_config->fdi_lanes);
5436                 return false;
5437         }
5438
5439         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5440                 if (pipe_config->fdi_lanes > 2) {
5441                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5442                                       pipe_config->fdi_lanes);
5443                         return false;
5444                 } else {
5445                         return true;
5446                 }
5447         }
5448
5449         if (INTEL_INFO(dev)->num_pipes == 2)
5450                 return true;
5451
5452         /* Ivybridge 3 pipe is really complicated */
5453         switch (pipe) {
5454         case PIPE_A:
5455                 return true;
5456         case PIPE_B:
5457                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5458                     pipe_config->fdi_lanes > 2) {
5459                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5460                                       pipe_name(pipe), pipe_config->fdi_lanes);
5461                         return false;
5462                 }
5463                 return true;
5464         case PIPE_C:
5465                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5466                     pipe_B_crtc->config->fdi_lanes <= 2) {
5467                         if (pipe_config->fdi_lanes > 2) {
5468                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5469                                               pipe_name(pipe), pipe_config->fdi_lanes);
5470                                 return false;
5471                         }
5472                 } else {
5473                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5474                         return false;
5475                 }
5476                 return true;
5477         default:
5478                 BUG();
5479         }
5480 }
5481
5482 #define RETRY 1
5483 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5484                                        struct intel_crtc_state *pipe_config)
5485 {
5486         struct drm_device *dev = intel_crtc->base.dev;
5487         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5488         int lane, link_bw, fdi_dotclock;
5489         bool setup_ok, needs_recompute = false;
5490
5491 retry:
5492         /* FDI is a binary signal running at ~2.7GHz, encoding
5493          * each output octet as 10 bits. The actual frequency
5494          * is stored as a divider into a 100MHz clock, and the
5495          * mode pixel clock is stored in units of 1KHz.
5496          * Hence the bw of each lane in terms of the mode signal
5497          * is:
5498          */
5499         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5500
5501         fdi_dotclock = adjusted_mode->crtc_clock;
5502
5503         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5504                                            pipe_config->pipe_bpp);
5505
5506         pipe_config->fdi_lanes = lane;
5507
5508         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5509                                link_bw, &pipe_config->fdi_m_n);
5510
5511         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5512                                             intel_crtc->pipe, pipe_config);
5513         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5514                 pipe_config->pipe_bpp -= 2*3;
5515                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5516                               pipe_config->pipe_bpp);
5517                 needs_recompute = true;
5518                 pipe_config->bw_constrained = true;
5519
5520                 goto retry;
5521         }
5522
5523         if (needs_recompute)
5524                 return RETRY;
5525
5526         return setup_ok ? 0 : -EINVAL;
5527 }
5528
5529 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5530                                    struct intel_crtc_state *pipe_config)
5531 {
5532         pipe_config->ips_enabled = i915.enable_ips &&
5533                                    hsw_crtc_supports_ips(crtc) &&
5534                                    pipe_config->pipe_bpp <= 24;
5535 }
5536
5537 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5538                                      struct intel_crtc_state *pipe_config)
5539 {
5540         struct drm_device *dev = crtc->base.dev;
5541         struct drm_i915_private *dev_priv = dev->dev_private;
5542         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5543
5544         /* FIXME should check pixel clock limits on all platforms */
5545         if (INTEL_INFO(dev)->gen < 4) {
5546                 int clock_limit =
5547                         dev_priv->display.get_display_clock_speed(dev);
5548
5549                 /*
5550                  * Enable pixel doubling when the dot clock
5551                  * is > 90% of the (display) core speed.
5552                  *
5553                  * GDG double wide on either pipe,
5554                  * otherwise pipe A only.
5555                  */
5556                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5557                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5558                         clock_limit *= 2;
5559                         pipe_config->double_wide = true;
5560                 }
5561
5562                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5563                         return -EINVAL;
5564         }
5565
5566         /*
5567          * Pipe horizontal size must be even in:
5568          * - DVO ganged mode
5569          * - LVDS dual channel mode
5570          * - Double wide pipe
5571          */
5572         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5573              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5574                 pipe_config->pipe_src_w &= ~1;
5575
5576         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5577          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5578          */
5579         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5580                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5581                 return -EINVAL;
5582
5583         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5584                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5585         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5586                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5587                  * for lvds. */
5588                 pipe_config->pipe_bpp = 8*3;
5589         }
5590
5591         if (HAS_IPS(dev))
5592                 hsw_compute_ips_config(crtc, pipe_config);
5593
5594         if (pipe_config->has_pch_encoder)
5595                 return ironlake_fdi_compute_config(crtc, pipe_config);
5596
5597         return 0;
5598 }
5599
5600 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5601 {
5602         struct drm_i915_private *dev_priv = dev->dev_private;
5603         u32 val;
5604         int divider;
5605
5606         /* FIXME: Punit isn't quite ready yet */
5607         if (IS_CHERRYVIEW(dev))
5608                 return 400000;
5609
5610         if (dev_priv->hpll_freq == 0)
5611                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5612
5613         mutex_lock(&dev_priv->dpio_lock);
5614         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5615         mutex_unlock(&dev_priv->dpio_lock);
5616
5617         divider = val & DISPLAY_FREQUENCY_VALUES;
5618
5619         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5620              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5621              "cdclk change in progress\n");
5622
5623         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5624 }
5625
5626 static int i945_get_display_clock_speed(struct drm_device *dev)
5627 {
5628         return 400000;
5629 }
5630
5631 static int i915_get_display_clock_speed(struct drm_device *dev)
5632 {
5633         return 333000;
5634 }
5635
5636 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5637 {
5638         return 200000;
5639 }
5640
5641 static int pnv_get_display_clock_speed(struct drm_device *dev)
5642 {
5643         u16 gcfgc = 0;
5644
5645         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5646
5647         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5648         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5649                 return 267000;
5650         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5651                 return 333000;
5652         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5653                 return 444000;
5654         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5655                 return 200000;
5656         default:
5657                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5658         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5659                 return 133000;
5660         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5661                 return 167000;
5662         }
5663 }
5664
5665 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5666 {
5667         u16 gcfgc = 0;
5668
5669         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5670
5671         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5672                 return 133000;
5673         else {
5674                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5675                 case GC_DISPLAY_CLOCK_333_MHZ:
5676                         return 333000;
5677                 default:
5678                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5679                         return 190000;
5680                 }
5681         }
5682 }
5683
5684 static int i865_get_display_clock_speed(struct drm_device *dev)
5685 {
5686         return 266000;
5687 }
5688
5689 static int i855_get_display_clock_speed(struct drm_device *dev)
5690 {
5691         u16 hpllcc = 0;
5692         /* Assume that the hardware is in the high speed state.  This
5693          * should be the default.
5694          */
5695         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5696         case GC_CLOCK_133_200:
5697         case GC_CLOCK_100_200:
5698                 return 200000;
5699         case GC_CLOCK_166_250:
5700                 return 250000;
5701         case GC_CLOCK_100_133:
5702                 return 133000;
5703         }
5704
5705         /* Shouldn't happen */
5706         return 0;
5707 }
5708
5709 static int i830_get_display_clock_speed(struct drm_device *dev)
5710 {
5711         return 133000;
5712 }
5713
5714 static void
5715 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5716 {
5717         while (*num > DATA_LINK_M_N_MASK ||
5718                *den > DATA_LINK_M_N_MASK) {
5719                 *num >>= 1;
5720                 *den >>= 1;
5721         }
5722 }
5723
5724 static void compute_m_n(unsigned int m, unsigned int n,
5725                         uint32_t *ret_m, uint32_t *ret_n)
5726 {
5727         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5728         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5729         intel_reduce_m_n_ratio(ret_m, ret_n);
5730 }
5731
5732 void
5733 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5734                        int pixel_clock, int link_clock,
5735                        struct intel_link_m_n *m_n)
5736 {
5737         m_n->tu = 64;
5738
5739         compute_m_n(bits_per_pixel * pixel_clock,
5740                     link_clock * nlanes * 8,
5741                     &m_n->gmch_m, &m_n->gmch_n);
5742
5743         compute_m_n(pixel_clock, link_clock,
5744                     &m_n->link_m, &m_n->link_n);
5745 }
5746
5747 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5748 {
5749         if (i915.panel_use_ssc >= 0)
5750                 return i915.panel_use_ssc != 0;
5751         return dev_priv->vbt.lvds_use_ssc
5752                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5753 }
5754
5755 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5756 {
5757         struct drm_device *dev = crtc->base.dev;
5758         struct drm_i915_private *dev_priv = dev->dev_private;
5759         int refclk;
5760
5761         if (IS_VALLEYVIEW(dev)) {
5762                 refclk = 100000;
5763         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5764             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5765                 refclk = dev_priv->vbt.lvds_ssc_freq;
5766                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5767         } else if (!IS_GEN2(dev)) {
5768                 refclk = 96000;
5769         } else {
5770                 refclk = 48000;
5771         }
5772
5773         return refclk;
5774 }
5775
5776 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5777 {
5778         return (1 << dpll->n) << 16 | dpll->m2;
5779 }
5780
5781 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5782 {
5783         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5784 }
5785
5786 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5787                                      struct intel_crtc_state *crtc_state,
5788                                      intel_clock_t *reduced_clock)
5789 {
5790         struct drm_device *dev = crtc->base.dev;
5791         u32 fp, fp2 = 0;
5792
5793         if (IS_PINEVIEW(dev)) {
5794                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5795                 if (reduced_clock)
5796                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5797         } else {
5798                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5799                 if (reduced_clock)
5800                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5801         }
5802
5803         crtc_state->dpll_hw_state.fp0 = fp;
5804
5805         crtc->lowfreq_avail = false;
5806         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5807             reduced_clock && i915.powersave) {
5808                 crtc_state->dpll_hw_state.fp1 = fp2;
5809                 crtc->lowfreq_avail = true;
5810         } else {
5811                 crtc_state->dpll_hw_state.fp1 = fp;
5812         }
5813 }
5814
5815 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5816                 pipe)
5817 {
5818         u32 reg_val;
5819
5820         /*
5821          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5822          * and set it to a reasonable value instead.
5823          */
5824         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5825         reg_val &= 0xffffff00;
5826         reg_val |= 0x00000030;
5827         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5828
5829         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5830         reg_val &= 0x8cffffff;
5831         reg_val = 0x8c000000;
5832         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5833
5834         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5835         reg_val &= 0xffffff00;
5836         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5837
5838         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5839         reg_val &= 0x00ffffff;
5840         reg_val |= 0xb0000000;
5841         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5842 }
5843
5844 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5845                                          struct intel_link_m_n *m_n)
5846 {
5847         struct drm_device *dev = crtc->base.dev;
5848         struct drm_i915_private *dev_priv = dev->dev_private;
5849         int pipe = crtc->pipe;
5850
5851         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5852         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5853         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5854         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5855 }
5856
5857 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5858                                          struct intel_link_m_n *m_n,
5859                                          struct intel_link_m_n *m2_n2)
5860 {
5861         struct drm_device *dev = crtc->base.dev;
5862         struct drm_i915_private *dev_priv = dev->dev_private;
5863         int pipe = crtc->pipe;
5864         enum transcoder transcoder = crtc->config->cpu_transcoder;
5865
5866         if (INTEL_INFO(dev)->gen >= 5) {
5867                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5868                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5869                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5870                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5871                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5872                  * for gen < 8) and if DRRS is supported (to make sure the
5873                  * registers are not unnecessarily accessed).
5874                  */
5875                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5876                         crtc->config->has_drrs) {
5877                         I915_WRITE(PIPE_DATA_M2(transcoder),
5878                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5879                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5880                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5881                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5882                 }
5883         } else {
5884                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5885                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5886                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5887                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5888         }
5889 }
5890
5891 void intel_dp_set_m_n(struct intel_crtc *crtc)
5892 {
5893         if (crtc->config->has_pch_encoder)
5894                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5895         else
5896                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
5897                                                    &crtc->config->dp_m2_n2);
5898 }
5899
5900 static void vlv_update_pll(struct intel_crtc *crtc,
5901                            struct intel_crtc_state *pipe_config)
5902 {
5903         u32 dpll, dpll_md;
5904
5905         /*
5906          * Enable DPIO clock input. We should never disable the reference
5907          * clock for pipe B, since VGA hotplug / manual detection depends
5908          * on it.
5909          */
5910         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5911                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5912         /* We should never disable this, set it here for state tracking */
5913         if (crtc->pipe == PIPE_B)
5914                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5915         dpll |= DPLL_VCO_ENABLE;
5916         pipe_config->dpll_hw_state.dpll = dpll;
5917
5918         dpll_md = (pipe_config->pixel_multiplier - 1)
5919                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5920         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5921 }
5922
5923 static void vlv_prepare_pll(struct intel_crtc *crtc,
5924                             const struct intel_crtc_state *pipe_config)
5925 {
5926         struct drm_device *dev = crtc->base.dev;
5927         struct drm_i915_private *dev_priv = dev->dev_private;
5928         int pipe = crtc->pipe;
5929         u32 mdiv;
5930         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5931         u32 coreclk, reg_val;
5932
5933         mutex_lock(&dev_priv->dpio_lock);
5934
5935         bestn = pipe_config->dpll.n;
5936         bestm1 = pipe_config->dpll.m1;
5937         bestm2 = pipe_config->dpll.m2;
5938         bestp1 = pipe_config->dpll.p1;
5939         bestp2 = pipe_config->dpll.p2;
5940
5941         /* See eDP HDMI DPIO driver vbios notes doc */
5942
5943         /* PLL B needs special handling */
5944         if (pipe == PIPE_B)
5945                 vlv_pllb_recal_opamp(dev_priv, pipe);
5946
5947         /* Set up Tx target for periodic Rcomp update */
5948         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5949
5950         /* Disable target IRef on PLL */
5951         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5952         reg_val &= 0x00ffffff;
5953         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5954
5955         /* Disable fast lock */
5956         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5957
5958         /* Set idtafcrecal before PLL is enabled */
5959         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5960         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5961         mdiv |= ((bestn << DPIO_N_SHIFT));
5962         mdiv |= (1 << DPIO_K_SHIFT);
5963
5964         /*
5965          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5966          * but we don't support that).
5967          * Note: don't use the DAC post divider as it seems unstable.
5968          */
5969         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5970         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5971
5972         mdiv |= DPIO_ENABLE_CALIBRATION;
5973         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5974
5975         /* Set HBR and RBR LPF coefficients */
5976         if (pipe_config->port_clock == 162000 ||
5977             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5978             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5979                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5980                                  0x009f0003);
5981         else
5982                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5983                                  0x00d0000f);
5984
5985         if (pipe_config->has_dp_encoder) {
5986                 /* Use SSC source */
5987                 if (pipe == PIPE_A)
5988                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5989                                          0x0df40000);
5990                 else
5991                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5992                                          0x0df70000);
5993         } else { /* HDMI or VGA */
5994                 /* Use bend source */
5995                 if (pipe == PIPE_A)
5996                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5997                                          0x0df70000);
5998                 else
5999                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6000                                          0x0df40000);
6001         }
6002
6003         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6004         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6005         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6006             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6007                 coreclk |= 0x01000000;
6008         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6009
6010         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6011         mutex_unlock(&dev_priv->dpio_lock);
6012 }
6013
6014 static void chv_update_pll(struct intel_crtc *crtc,
6015                            struct intel_crtc_state *pipe_config)
6016 {
6017         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6018                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6019                 DPLL_VCO_ENABLE;
6020         if (crtc->pipe != PIPE_A)
6021                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6022
6023         pipe_config->dpll_hw_state.dpll_md =
6024                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6025 }
6026
6027 static void chv_prepare_pll(struct intel_crtc *crtc,
6028                             const struct intel_crtc_state *pipe_config)
6029 {
6030         struct drm_device *dev = crtc->base.dev;
6031         struct drm_i915_private *dev_priv = dev->dev_private;
6032         int pipe = crtc->pipe;
6033         int dpll_reg = DPLL(crtc->pipe);
6034         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6035         u32 loopfilter, intcoeff;
6036         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6037         int refclk;
6038
6039         bestn = pipe_config->dpll.n;
6040         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6041         bestm1 = pipe_config->dpll.m1;
6042         bestm2 = pipe_config->dpll.m2 >> 22;
6043         bestp1 = pipe_config->dpll.p1;
6044         bestp2 = pipe_config->dpll.p2;
6045
6046         /*
6047          * Enable Refclk and SSC
6048          */
6049         I915_WRITE(dpll_reg,
6050                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6051
6052         mutex_lock(&dev_priv->dpio_lock);
6053
6054         /* p1 and p2 divider */
6055         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6056                         5 << DPIO_CHV_S1_DIV_SHIFT |
6057                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6058                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6059                         1 << DPIO_CHV_K_DIV_SHIFT);
6060
6061         /* Feedback post-divider - m2 */
6062         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6063
6064         /* Feedback refclk divider - n and m1 */
6065         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6066                         DPIO_CHV_M1_DIV_BY_2 |
6067                         1 << DPIO_CHV_N_DIV_SHIFT);
6068
6069         /* M2 fraction division */
6070         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6071
6072         /* M2 fraction division enable */
6073         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6074                        DPIO_CHV_FRAC_DIV_EN |
6075                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6076
6077         /* Loop filter */
6078         refclk = i9xx_get_refclk(crtc, 0);
6079         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6080                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6081         if (refclk == 100000)
6082                 intcoeff = 11;
6083         else if (refclk == 38400)
6084                 intcoeff = 10;
6085         else
6086                 intcoeff = 9;
6087         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6088         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6089
6090         /* AFC Recal */
6091         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6092                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6093                         DPIO_AFC_RECAL);
6094
6095         mutex_unlock(&dev_priv->dpio_lock);
6096 }
6097
6098 /**
6099  * vlv_force_pll_on - forcibly enable just the PLL
6100  * @dev_priv: i915 private structure
6101  * @pipe: pipe PLL to enable
6102  * @dpll: PLL configuration
6103  *
6104  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6105  * in cases where we need the PLL enabled even when @pipe is not going to
6106  * be enabled.
6107  */
6108 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6109                       const struct dpll *dpll)
6110 {
6111         struct intel_crtc *crtc =
6112                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6113         struct intel_crtc_state pipe_config = {
6114                 .pixel_multiplier = 1,
6115                 .dpll = *dpll,
6116         };
6117
6118         if (IS_CHERRYVIEW(dev)) {
6119                 chv_update_pll(crtc, &pipe_config);
6120                 chv_prepare_pll(crtc, &pipe_config);
6121                 chv_enable_pll(crtc, &pipe_config);
6122         } else {
6123                 vlv_update_pll(crtc, &pipe_config);
6124                 vlv_prepare_pll(crtc, &pipe_config);
6125                 vlv_enable_pll(crtc, &pipe_config);
6126         }
6127 }
6128
6129 /**
6130  * vlv_force_pll_off - forcibly disable just the PLL
6131  * @dev_priv: i915 private structure
6132  * @pipe: pipe PLL to disable
6133  *
6134  * Disable the PLL for @pipe. To be used in cases where we need
6135  * the PLL enabled even when @pipe is not going to be enabled.
6136  */
6137 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6138 {
6139         if (IS_CHERRYVIEW(dev))
6140                 chv_disable_pll(to_i915(dev), pipe);
6141         else
6142                 vlv_disable_pll(to_i915(dev), pipe);
6143 }
6144
6145 static void i9xx_update_pll(struct intel_crtc *crtc,
6146                             struct intel_crtc_state *crtc_state,
6147                             intel_clock_t *reduced_clock,
6148                             int num_connectors)
6149 {
6150         struct drm_device *dev = crtc->base.dev;
6151         struct drm_i915_private *dev_priv = dev->dev_private;
6152         u32 dpll;
6153         bool is_sdvo;
6154         struct dpll *clock = &crtc_state->dpll;
6155
6156         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6157
6158         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6159                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6160
6161         dpll = DPLL_VGA_MODE_DIS;
6162
6163         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6164                 dpll |= DPLLB_MODE_LVDS;
6165         else
6166                 dpll |= DPLLB_MODE_DAC_SERIAL;
6167
6168         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6169                 dpll |= (crtc_state->pixel_multiplier - 1)
6170                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6171         }
6172
6173         if (is_sdvo)
6174                 dpll |= DPLL_SDVO_HIGH_SPEED;
6175
6176         if (crtc_state->has_dp_encoder)
6177                 dpll |= DPLL_SDVO_HIGH_SPEED;
6178
6179         /* compute bitmask from p1 value */
6180         if (IS_PINEVIEW(dev))
6181                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6182         else {
6183                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6184                 if (IS_G4X(dev) && reduced_clock)
6185                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6186         }
6187         switch (clock->p2) {
6188         case 5:
6189                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6190                 break;
6191         case 7:
6192                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6193                 break;
6194         case 10:
6195                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6196                 break;
6197         case 14:
6198                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6199                 break;
6200         }
6201         if (INTEL_INFO(dev)->gen >= 4)
6202                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6203
6204         if (crtc_state->sdvo_tv_clock)
6205                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6206         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6207                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6208                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6209         else
6210                 dpll |= PLL_REF_INPUT_DREFCLK;
6211
6212         dpll |= DPLL_VCO_ENABLE;
6213         crtc_state->dpll_hw_state.dpll = dpll;
6214
6215         if (INTEL_INFO(dev)->gen >= 4) {
6216                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6217                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6218                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6219         }
6220 }
6221
6222 static void i8xx_update_pll(struct intel_crtc *crtc,
6223                             struct intel_crtc_state *crtc_state,
6224                             intel_clock_t *reduced_clock,
6225                             int num_connectors)
6226 {
6227         struct drm_device *dev = crtc->base.dev;
6228         struct drm_i915_private *dev_priv = dev->dev_private;
6229         u32 dpll;
6230         struct dpll *clock = &crtc_state->dpll;
6231
6232         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6233
6234         dpll = DPLL_VGA_MODE_DIS;
6235
6236         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6237                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6238         } else {
6239                 if (clock->p1 == 2)
6240                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6241                 else
6242                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6243                 if (clock->p2 == 4)
6244                         dpll |= PLL_P2_DIVIDE_BY_4;
6245         }
6246
6247         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6248                 dpll |= DPLL_DVO_2X_MODE;
6249
6250         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6251                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6252                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6253         else
6254                 dpll |= PLL_REF_INPUT_DREFCLK;
6255
6256         dpll |= DPLL_VCO_ENABLE;
6257         crtc_state->dpll_hw_state.dpll = dpll;
6258 }
6259
6260 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6261 {
6262         struct drm_device *dev = intel_crtc->base.dev;
6263         struct drm_i915_private *dev_priv = dev->dev_private;
6264         enum pipe pipe = intel_crtc->pipe;
6265         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6266         struct drm_display_mode *adjusted_mode =
6267                 &intel_crtc->config->base.adjusted_mode;
6268         uint32_t crtc_vtotal, crtc_vblank_end;
6269         int vsyncshift = 0;
6270
6271         /* We need to be careful not to changed the adjusted mode, for otherwise
6272          * the hw state checker will get angry at the mismatch. */
6273         crtc_vtotal = adjusted_mode->crtc_vtotal;
6274         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6275
6276         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6277                 /* the chip adds 2 halflines automatically */
6278                 crtc_vtotal -= 1;
6279                 crtc_vblank_end -= 1;
6280
6281                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6282                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6283                 else
6284                         vsyncshift = adjusted_mode->crtc_hsync_start -
6285                                 adjusted_mode->crtc_htotal / 2;
6286                 if (vsyncshift < 0)
6287                         vsyncshift += adjusted_mode->crtc_htotal;
6288         }
6289
6290         if (INTEL_INFO(dev)->gen > 3)
6291                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6292
6293         I915_WRITE(HTOTAL(cpu_transcoder),
6294                    (adjusted_mode->crtc_hdisplay - 1) |
6295                    ((adjusted_mode->crtc_htotal - 1) << 16));
6296         I915_WRITE(HBLANK(cpu_transcoder),
6297                    (adjusted_mode->crtc_hblank_start - 1) |
6298                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6299         I915_WRITE(HSYNC(cpu_transcoder),
6300                    (adjusted_mode->crtc_hsync_start - 1) |
6301                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6302
6303         I915_WRITE(VTOTAL(cpu_transcoder),
6304                    (adjusted_mode->crtc_vdisplay - 1) |
6305                    ((crtc_vtotal - 1) << 16));
6306         I915_WRITE(VBLANK(cpu_transcoder),
6307                    (adjusted_mode->crtc_vblank_start - 1) |
6308                    ((crtc_vblank_end - 1) << 16));
6309         I915_WRITE(VSYNC(cpu_transcoder),
6310                    (adjusted_mode->crtc_vsync_start - 1) |
6311                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6312
6313         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6314          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6315          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6316          * bits. */
6317         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6318             (pipe == PIPE_B || pipe == PIPE_C))
6319                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6320
6321         /* pipesrc controls the size that is scaled from, which should
6322          * always be the user's requested size.
6323          */
6324         I915_WRITE(PIPESRC(pipe),
6325                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6326                    (intel_crtc->config->pipe_src_h - 1));
6327 }
6328
6329 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6330                                    struct intel_crtc_state *pipe_config)
6331 {
6332         struct drm_device *dev = crtc->base.dev;
6333         struct drm_i915_private *dev_priv = dev->dev_private;
6334         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6335         uint32_t tmp;
6336
6337         tmp = I915_READ(HTOTAL(cpu_transcoder));
6338         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6339         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6340         tmp = I915_READ(HBLANK(cpu_transcoder));
6341         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6342         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6343         tmp = I915_READ(HSYNC(cpu_transcoder));
6344         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6345         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6346
6347         tmp = I915_READ(VTOTAL(cpu_transcoder));
6348         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6349         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6350         tmp = I915_READ(VBLANK(cpu_transcoder));
6351         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6352         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6353         tmp = I915_READ(VSYNC(cpu_transcoder));
6354         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6355         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6356
6357         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6358                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6359                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6360                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6361         }
6362
6363         tmp = I915_READ(PIPESRC(crtc->pipe));
6364         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6365         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6366
6367         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6368         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6369 }
6370
6371 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6372                                  struct intel_crtc_state *pipe_config)
6373 {
6374         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6375         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6376         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6377         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6378
6379         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6380         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6381         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6382         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6383
6384         mode->flags = pipe_config->base.adjusted_mode.flags;
6385
6386         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6387         mode->flags |= pipe_config->base.adjusted_mode.flags;
6388 }
6389
6390 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6391 {
6392         struct drm_device *dev = intel_crtc->base.dev;
6393         struct drm_i915_private *dev_priv = dev->dev_private;
6394         uint32_t pipeconf;
6395
6396         pipeconf = 0;
6397
6398         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6399             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6400                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6401
6402         if (intel_crtc->config->double_wide)
6403                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6404
6405         /* only g4x and later have fancy bpc/dither controls */
6406         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6407                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6408                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6409                         pipeconf |= PIPECONF_DITHER_EN |
6410                                     PIPECONF_DITHER_TYPE_SP;
6411
6412                 switch (intel_crtc->config->pipe_bpp) {
6413                 case 18:
6414                         pipeconf |= PIPECONF_6BPC;
6415                         break;
6416                 case 24:
6417                         pipeconf |= PIPECONF_8BPC;
6418                         break;
6419                 case 30:
6420                         pipeconf |= PIPECONF_10BPC;
6421                         break;
6422                 default:
6423                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6424                         BUG();
6425                 }
6426         }
6427
6428         if (HAS_PIPE_CXSR(dev)) {
6429                 if (intel_crtc->lowfreq_avail) {
6430                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6431                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6432                 } else {
6433                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6434                 }
6435         }
6436
6437         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6438                 if (INTEL_INFO(dev)->gen < 4 ||
6439                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6440                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6441                 else
6442                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6443         } else
6444                 pipeconf |= PIPECONF_PROGRESSIVE;
6445
6446         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6447                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6448
6449         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6450         POSTING_READ(PIPECONF(intel_crtc->pipe));
6451 }
6452
6453 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6454                                    struct intel_crtc_state *crtc_state)
6455 {
6456         struct drm_device *dev = crtc->base.dev;
6457         struct drm_i915_private *dev_priv = dev->dev_private;
6458         int refclk, num_connectors = 0;
6459         intel_clock_t clock, reduced_clock;
6460         bool ok, has_reduced_clock = false;
6461         bool is_lvds = false, is_dsi = false;
6462         struct intel_encoder *encoder;
6463         const intel_limit_t *limit;
6464
6465         for_each_intel_encoder(dev, encoder) {
6466                 if (encoder->new_crtc != crtc)
6467                         continue;
6468
6469                 switch (encoder->type) {
6470                 case INTEL_OUTPUT_LVDS:
6471                         is_lvds = true;
6472                         break;
6473                 case INTEL_OUTPUT_DSI:
6474                         is_dsi = true;
6475                         break;
6476                 default:
6477                         break;
6478                 }
6479
6480                 num_connectors++;
6481         }
6482
6483         if (is_dsi)
6484                 return 0;
6485
6486         if (!crtc_state->clock_set) {
6487                 refclk = i9xx_get_refclk(crtc, num_connectors);
6488
6489                 /*
6490                  * Returns a set of divisors for the desired target clock with
6491                  * the given refclk, or FALSE.  The returned values represent
6492                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6493                  * 2) / p1 / p2.
6494                  */
6495                 limit = intel_limit(crtc, refclk);
6496                 ok = dev_priv->display.find_dpll(limit, crtc,
6497                                                  crtc_state->port_clock,
6498                                                  refclk, NULL, &clock);
6499                 if (!ok) {
6500                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6501                         return -EINVAL;
6502                 }
6503
6504                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6505                         /*
6506                          * Ensure we match the reduced clock's P to the target
6507                          * clock.  If the clocks don't match, we can't switch
6508                          * the display clock by using the FP0/FP1. In such case
6509                          * we will disable the LVDS downclock feature.
6510                          */
6511                         has_reduced_clock =
6512                                 dev_priv->display.find_dpll(limit, crtc,
6513                                                             dev_priv->lvds_downclock,
6514                                                             refclk, &clock,
6515                                                             &reduced_clock);
6516                 }
6517                 /* Compat-code for transition, will disappear. */
6518                 crtc_state->dpll.n = clock.n;
6519                 crtc_state->dpll.m1 = clock.m1;
6520                 crtc_state->dpll.m2 = clock.m2;
6521                 crtc_state->dpll.p1 = clock.p1;
6522                 crtc_state->dpll.p2 = clock.p2;
6523         }
6524
6525         if (IS_GEN2(dev)) {
6526                 i8xx_update_pll(crtc, crtc_state,
6527                                 has_reduced_clock ? &reduced_clock : NULL,
6528                                 num_connectors);
6529         } else if (IS_CHERRYVIEW(dev)) {
6530                 chv_update_pll(crtc, crtc_state);
6531         } else if (IS_VALLEYVIEW(dev)) {
6532                 vlv_update_pll(crtc, crtc_state);
6533         } else {
6534                 i9xx_update_pll(crtc, crtc_state,
6535                                 has_reduced_clock ? &reduced_clock : NULL,
6536                                 num_connectors);
6537         }
6538
6539         return 0;
6540 }
6541
6542 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6543                                  struct intel_crtc_state *pipe_config)
6544 {
6545         struct drm_device *dev = crtc->base.dev;
6546         struct drm_i915_private *dev_priv = dev->dev_private;
6547         uint32_t tmp;
6548
6549         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6550                 return;
6551
6552         tmp = I915_READ(PFIT_CONTROL);
6553         if (!(tmp & PFIT_ENABLE))
6554                 return;
6555
6556         /* Check whether the pfit is attached to our pipe. */
6557         if (INTEL_INFO(dev)->gen < 4) {
6558                 if (crtc->pipe != PIPE_B)
6559                         return;
6560         } else {
6561                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6562                         return;
6563         }
6564
6565         pipe_config->gmch_pfit.control = tmp;
6566         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6567         if (INTEL_INFO(dev)->gen < 5)
6568                 pipe_config->gmch_pfit.lvds_border_bits =
6569                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6570 }
6571
6572 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6573                                struct intel_crtc_state *pipe_config)
6574 {
6575         struct drm_device *dev = crtc->base.dev;
6576         struct drm_i915_private *dev_priv = dev->dev_private;
6577         int pipe = pipe_config->cpu_transcoder;
6578         intel_clock_t clock;
6579         u32 mdiv;
6580         int refclk = 100000;
6581
6582         /* In case of MIPI DPLL will not even be used */
6583         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6584                 return;
6585
6586         mutex_lock(&dev_priv->dpio_lock);
6587         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6588         mutex_unlock(&dev_priv->dpio_lock);
6589
6590         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6591         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6592         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6593         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6594         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6595
6596         vlv_clock(refclk, &clock);
6597
6598         /* clock.dot is the fast clock */
6599         pipe_config->port_clock = clock.dot / 5;
6600 }
6601
6602 static void
6603 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6604                               struct intel_initial_plane_config *plane_config)
6605 {
6606         struct drm_device *dev = crtc->base.dev;
6607         struct drm_i915_private *dev_priv = dev->dev_private;
6608         u32 val, base, offset;
6609         int pipe = crtc->pipe, plane = crtc->plane;
6610         int fourcc, pixel_format;
6611         int aligned_height;
6612         struct drm_framebuffer *fb;
6613         struct intel_framebuffer *intel_fb;
6614
6615         val = I915_READ(DSPCNTR(plane));
6616         if (!(val & DISPLAY_PLANE_ENABLE))
6617                 return;
6618
6619         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6620         if (!intel_fb) {
6621                 DRM_DEBUG_KMS("failed to alloc fb\n");
6622                 return;
6623         }
6624
6625         fb = &intel_fb->base;
6626
6627         if (INTEL_INFO(dev)->gen >= 4)
6628                 if (val & DISPPLANE_TILED)
6629                         plane_config->tiling = I915_TILING_X;
6630
6631         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6632         fourcc = i9xx_format_to_fourcc(pixel_format);
6633         fb->pixel_format = fourcc;
6634         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6635
6636         if (INTEL_INFO(dev)->gen >= 4) {
6637                 if (plane_config->tiling)
6638                         offset = I915_READ(DSPTILEOFF(plane));
6639                 else
6640                         offset = I915_READ(DSPLINOFF(plane));
6641                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6642         } else {
6643                 base = I915_READ(DSPADDR(plane));
6644         }
6645         plane_config->base = base;
6646
6647         val = I915_READ(PIPESRC(pipe));
6648         fb->width = ((val >> 16) & 0xfff) + 1;
6649         fb->height = ((val >> 0) & 0xfff) + 1;
6650
6651         val = I915_READ(DSPSTRIDE(pipe));
6652         fb->pitches[0] = val & 0xffffffc0;
6653
6654         aligned_height = intel_fb_align_height(dev, fb->height,
6655                                                plane_config->tiling);
6656
6657         plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
6658
6659         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6660                       pipe_name(pipe), plane, fb->width, fb->height,
6661                       fb->bits_per_pixel, base, fb->pitches[0],
6662                       plane_config->size);
6663
6664         plane_config->fb = intel_fb;
6665 }
6666
6667 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6668                                struct intel_crtc_state *pipe_config)
6669 {
6670         struct drm_device *dev = crtc->base.dev;
6671         struct drm_i915_private *dev_priv = dev->dev_private;
6672         int pipe = pipe_config->cpu_transcoder;
6673         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6674         intel_clock_t clock;
6675         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6676         int refclk = 100000;
6677
6678         mutex_lock(&dev_priv->dpio_lock);
6679         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6680         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6681         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6682         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6683         mutex_unlock(&dev_priv->dpio_lock);
6684
6685         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6686         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6687         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6688         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6689         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6690
6691         chv_clock(refclk, &clock);
6692
6693         /* clock.dot is the fast clock */
6694         pipe_config->port_clock = clock.dot / 5;
6695 }
6696
6697 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6698                                  struct intel_crtc_state *pipe_config)
6699 {
6700         struct drm_device *dev = crtc->base.dev;
6701         struct drm_i915_private *dev_priv = dev->dev_private;
6702         uint32_t tmp;
6703
6704         if (!intel_display_power_is_enabled(dev_priv,
6705                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6706                 return false;
6707
6708         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6709         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6710
6711         tmp = I915_READ(PIPECONF(crtc->pipe));
6712         if (!(tmp & PIPECONF_ENABLE))
6713                 return false;
6714
6715         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6716                 switch (tmp & PIPECONF_BPC_MASK) {
6717                 case PIPECONF_6BPC:
6718                         pipe_config->pipe_bpp = 18;
6719                         break;
6720                 case PIPECONF_8BPC:
6721                         pipe_config->pipe_bpp = 24;
6722                         break;
6723                 case PIPECONF_10BPC:
6724                         pipe_config->pipe_bpp = 30;
6725                         break;
6726                 default:
6727                         break;
6728                 }
6729         }
6730
6731         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6732                 pipe_config->limited_color_range = true;
6733
6734         if (INTEL_INFO(dev)->gen < 4)
6735                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6736
6737         intel_get_pipe_timings(crtc, pipe_config);
6738
6739         i9xx_get_pfit_config(crtc, pipe_config);
6740
6741         if (INTEL_INFO(dev)->gen >= 4) {
6742                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6743                 pipe_config->pixel_multiplier =
6744                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6745                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6746                 pipe_config->dpll_hw_state.dpll_md = tmp;
6747         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6748                 tmp = I915_READ(DPLL(crtc->pipe));
6749                 pipe_config->pixel_multiplier =
6750                         ((tmp & SDVO_MULTIPLIER_MASK)
6751                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6752         } else {
6753                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6754                  * port and will be fixed up in the encoder->get_config
6755                  * function. */
6756                 pipe_config->pixel_multiplier = 1;
6757         }
6758         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6759         if (!IS_VALLEYVIEW(dev)) {
6760                 /*
6761                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6762                  * on 830. Filter it out here so that we don't
6763                  * report errors due to that.
6764                  */
6765                 if (IS_I830(dev))
6766                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6767
6768                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6769                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6770         } else {
6771                 /* Mask out read-only status bits. */
6772                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6773                                                      DPLL_PORTC_READY_MASK |
6774                                                      DPLL_PORTB_READY_MASK);
6775         }
6776
6777         if (IS_CHERRYVIEW(dev))
6778                 chv_crtc_clock_get(crtc, pipe_config);
6779         else if (IS_VALLEYVIEW(dev))
6780                 vlv_crtc_clock_get(crtc, pipe_config);
6781         else
6782                 i9xx_crtc_clock_get(crtc, pipe_config);
6783
6784         return true;
6785 }
6786
6787 static void ironlake_init_pch_refclk(struct drm_device *dev)
6788 {
6789         struct drm_i915_private *dev_priv = dev->dev_private;
6790         struct intel_encoder *encoder;
6791         u32 val, final;
6792         bool has_lvds = false;
6793         bool has_cpu_edp = false;
6794         bool has_panel = false;
6795         bool has_ck505 = false;
6796         bool can_ssc = false;
6797
6798         /* We need to take the global config into account */
6799         for_each_intel_encoder(dev, encoder) {
6800                 switch (encoder->type) {
6801                 case INTEL_OUTPUT_LVDS:
6802                         has_panel = true;
6803                         has_lvds = true;
6804                         break;
6805                 case INTEL_OUTPUT_EDP:
6806                         has_panel = true;
6807                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6808                                 has_cpu_edp = true;
6809                         break;
6810                 default:
6811                         break;
6812                 }
6813         }
6814
6815         if (HAS_PCH_IBX(dev)) {
6816                 has_ck505 = dev_priv->vbt.display_clock_mode;
6817                 can_ssc = has_ck505;
6818         } else {
6819                 has_ck505 = false;
6820                 can_ssc = true;
6821         }
6822
6823         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6824                       has_panel, has_lvds, has_ck505);
6825
6826         /* Ironlake: try to setup display ref clock before DPLL
6827          * enabling. This is only under driver's control after
6828          * PCH B stepping, previous chipset stepping should be
6829          * ignoring this setting.
6830          */
6831         val = I915_READ(PCH_DREF_CONTROL);
6832
6833         /* As we must carefully and slowly disable/enable each source in turn,
6834          * compute the final state we want first and check if we need to
6835          * make any changes at all.
6836          */
6837         final = val;
6838         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6839         if (has_ck505)
6840                 final |= DREF_NONSPREAD_CK505_ENABLE;
6841         else
6842                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6843
6844         final &= ~DREF_SSC_SOURCE_MASK;
6845         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6846         final &= ~DREF_SSC1_ENABLE;
6847
6848         if (has_panel) {
6849                 final |= DREF_SSC_SOURCE_ENABLE;
6850
6851                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6852                         final |= DREF_SSC1_ENABLE;
6853
6854                 if (has_cpu_edp) {
6855                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6856                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6857                         else
6858                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6859                 } else
6860                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6861         } else {
6862                 final |= DREF_SSC_SOURCE_DISABLE;
6863                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6864         }
6865
6866         if (final == val)
6867                 return;
6868
6869         /* Always enable nonspread source */
6870         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6871
6872         if (has_ck505)
6873                 val |= DREF_NONSPREAD_CK505_ENABLE;
6874         else
6875                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6876
6877         if (has_panel) {
6878                 val &= ~DREF_SSC_SOURCE_MASK;
6879                 val |= DREF_SSC_SOURCE_ENABLE;
6880
6881                 /* SSC must be turned on before enabling the CPU output  */
6882                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6883                         DRM_DEBUG_KMS("Using SSC on panel\n");
6884                         val |= DREF_SSC1_ENABLE;
6885                 } else
6886                         val &= ~DREF_SSC1_ENABLE;
6887
6888                 /* Get SSC going before enabling the outputs */
6889                 I915_WRITE(PCH_DREF_CONTROL, val);
6890                 POSTING_READ(PCH_DREF_CONTROL);
6891                 udelay(200);
6892
6893                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6894
6895                 /* Enable CPU source on CPU attached eDP */
6896                 if (has_cpu_edp) {
6897                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6898                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6899                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6900                         } else
6901                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6902                 } else
6903                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6904
6905                 I915_WRITE(PCH_DREF_CONTROL, val);
6906                 POSTING_READ(PCH_DREF_CONTROL);
6907                 udelay(200);
6908         } else {
6909                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6910
6911                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6912
6913                 /* Turn off CPU output */
6914                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6915
6916                 I915_WRITE(PCH_DREF_CONTROL, val);
6917                 POSTING_READ(PCH_DREF_CONTROL);
6918                 udelay(200);
6919
6920                 /* Turn off the SSC source */
6921                 val &= ~DREF_SSC_SOURCE_MASK;
6922                 val |= DREF_SSC_SOURCE_DISABLE;
6923
6924                 /* Turn off SSC1 */
6925                 val &= ~DREF_SSC1_ENABLE;
6926
6927                 I915_WRITE(PCH_DREF_CONTROL, val);
6928                 POSTING_READ(PCH_DREF_CONTROL);
6929                 udelay(200);
6930         }
6931
6932         BUG_ON(val != final);
6933 }
6934
6935 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6936 {
6937         uint32_t tmp;
6938
6939         tmp = I915_READ(SOUTH_CHICKEN2);
6940         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6941         I915_WRITE(SOUTH_CHICKEN2, tmp);
6942
6943         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6944                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6945                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6946
6947         tmp = I915_READ(SOUTH_CHICKEN2);
6948         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6949         I915_WRITE(SOUTH_CHICKEN2, tmp);
6950
6951         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6952                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6953                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6954 }
6955
6956 /* WaMPhyProgramming:hsw */
6957 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6958 {
6959         uint32_t tmp;
6960
6961         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6962         tmp &= ~(0xFF << 24);
6963         tmp |= (0x12 << 24);
6964         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6965
6966         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6967         tmp |= (1 << 11);
6968         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6969
6970         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6971         tmp |= (1 << 11);
6972         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6973
6974         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6975         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6976         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6977
6978         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6979         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6980         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6981
6982         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6983         tmp &= ~(7 << 13);
6984         tmp |= (5 << 13);
6985         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6986
6987         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6988         tmp &= ~(7 << 13);
6989         tmp |= (5 << 13);
6990         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6991
6992         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6993         tmp &= ~0xFF;
6994         tmp |= 0x1C;
6995         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6996
6997         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6998         tmp &= ~0xFF;
6999         tmp |= 0x1C;
7000         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7001
7002         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7003         tmp &= ~(0xFF << 16);
7004         tmp |= (0x1C << 16);
7005         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7006
7007         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7008         tmp &= ~(0xFF << 16);
7009         tmp |= (0x1C << 16);
7010         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7011
7012         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7013         tmp |= (1 << 27);
7014         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7015
7016         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7017         tmp |= (1 << 27);
7018         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7019
7020         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7021         tmp &= ~(0xF << 28);
7022         tmp |= (4 << 28);
7023         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7024
7025         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7026         tmp &= ~(0xF << 28);
7027         tmp |= (4 << 28);
7028         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7029 }
7030
7031 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7032  * Programming" based on the parameters passed:
7033  * - Sequence to enable CLKOUT_DP
7034  * - Sequence to enable CLKOUT_DP without spread
7035  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7036  */
7037 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7038                                  bool with_fdi)
7039 {
7040         struct drm_i915_private *dev_priv = dev->dev_private;
7041         uint32_t reg, tmp;
7042
7043         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7044                 with_spread = true;
7045         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7046                  with_fdi, "LP PCH doesn't have FDI\n"))
7047                 with_fdi = false;
7048
7049         mutex_lock(&dev_priv->dpio_lock);
7050
7051         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7052         tmp &= ~SBI_SSCCTL_DISABLE;
7053         tmp |= SBI_SSCCTL_PATHALT;
7054         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7055
7056         udelay(24);
7057
7058         if (with_spread) {
7059                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7060                 tmp &= ~SBI_SSCCTL_PATHALT;
7061                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7062
7063                 if (with_fdi) {
7064                         lpt_reset_fdi_mphy(dev_priv);
7065                         lpt_program_fdi_mphy(dev_priv);
7066                 }
7067         }
7068
7069         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7070                SBI_GEN0 : SBI_DBUFF0;
7071         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7072         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7073         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7074
7075         mutex_unlock(&dev_priv->dpio_lock);
7076 }
7077
7078 /* Sequence to disable CLKOUT_DP */
7079 static void lpt_disable_clkout_dp(struct drm_device *dev)
7080 {
7081         struct drm_i915_private *dev_priv = dev->dev_private;
7082         uint32_t reg, tmp;
7083
7084         mutex_lock(&dev_priv->dpio_lock);
7085
7086         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7087                SBI_GEN0 : SBI_DBUFF0;
7088         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7089         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7090         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7091
7092         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7093         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7094                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7095                         tmp |= SBI_SSCCTL_PATHALT;
7096                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7097                         udelay(32);
7098                 }
7099                 tmp |= SBI_SSCCTL_DISABLE;
7100                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7101         }
7102
7103         mutex_unlock(&dev_priv->dpio_lock);
7104 }
7105
7106 static void lpt_init_pch_refclk(struct drm_device *dev)
7107 {
7108         struct intel_encoder *encoder;
7109         bool has_vga = false;
7110
7111         for_each_intel_encoder(dev, encoder) {
7112                 switch (encoder->type) {
7113                 case INTEL_OUTPUT_ANALOG:
7114                         has_vga = true;
7115                         break;
7116                 default:
7117                         break;
7118                 }
7119         }
7120
7121         if (has_vga)
7122                 lpt_enable_clkout_dp(dev, true, true);
7123         else
7124                 lpt_disable_clkout_dp(dev);
7125 }
7126
7127 /*
7128  * Initialize reference clocks when the driver loads
7129  */
7130 void intel_init_pch_refclk(struct drm_device *dev)
7131 {
7132         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7133                 ironlake_init_pch_refclk(dev);
7134         else if (HAS_PCH_LPT(dev))
7135                 lpt_init_pch_refclk(dev);
7136 }
7137
7138 static int ironlake_get_refclk(struct drm_crtc *crtc)
7139 {
7140         struct drm_device *dev = crtc->dev;
7141         struct drm_i915_private *dev_priv = dev->dev_private;
7142         struct intel_encoder *encoder;
7143         int num_connectors = 0;
7144         bool is_lvds = false;
7145
7146         for_each_intel_encoder(dev, encoder) {
7147                 if (encoder->new_crtc != to_intel_crtc(crtc))
7148                         continue;
7149
7150                 switch (encoder->type) {
7151                 case INTEL_OUTPUT_LVDS:
7152                         is_lvds = true;
7153                         break;
7154                 default:
7155                         break;
7156                 }
7157                 num_connectors++;
7158         }
7159
7160         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7161                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7162                               dev_priv->vbt.lvds_ssc_freq);
7163                 return dev_priv->vbt.lvds_ssc_freq;
7164         }
7165
7166         return 120000;
7167 }
7168
7169 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7170 {
7171         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7172         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7173         int pipe = intel_crtc->pipe;
7174         uint32_t val;
7175
7176         val = 0;
7177
7178         switch (intel_crtc->config->pipe_bpp) {
7179         case 18:
7180                 val |= PIPECONF_6BPC;
7181                 break;
7182         case 24:
7183                 val |= PIPECONF_8BPC;
7184                 break;
7185         case 30:
7186                 val |= PIPECONF_10BPC;
7187                 break;
7188         case 36:
7189                 val |= PIPECONF_12BPC;
7190                 break;
7191         default:
7192                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7193                 BUG();
7194         }
7195
7196         if (intel_crtc->config->dither)
7197                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7198
7199         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7200                 val |= PIPECONF_INTERLACED_ILK;
7201         else
7202                 val |= PIPECONF_PROGRESSIVE;
7203
7204         if (intel_crtc->config->limited_color_range)
7205                 val |= PIPECONF_COLOR_RANGE_SELECT;
7206
7207         I915_WRITE(PIPECONF(pipe), val);
7208         POSTING_READ(PIPECONF(pipe));
7209 }
7210
7211 /*
7212  * Set up the pipe CSC unit.
7213  *
7214  * Currently only full range RGB to limited range RGB conversion
7215  * is supported, but eventually this should handle various
7216  * RGB<->YCbCr scenarios as well.
7217  */
7218 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7219 {
7220         struct drm_device *dev = crtc->dev;
7221         struct drm_i915_private *dev_priv = dev->dev_private;
7222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7223         int pipe = intel_crtc->pipe;
7224         uint16_t coeff = 0x7800; /* 1.0 */
7225
7226         /*
7227          * TODO: Check what kind of values actually come out of the pipe
7228          * with these coeff/postoff values and adjust to get the best
7229          * accuracy. Perhaps we even need to take the bpc value into
7230          * consideration.
7231          */
7232
7233         if (intel_crtc->config->limited_color_range)
7234                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7235
7236         /*
7237          * GY/GU and RY/RU should be the other way around according
7238          * to BSpec, but reality doesn't agree. Just set them up in
7239          * a way that results in the correct picture.
7240          */
7241         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7242         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7243
7244         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7245         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7246
7247         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7248         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7249
7250         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7251         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7252         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7253
7254         if (INTEL_INFO(dev)->gen > 6) {
7255                 uint16_t postoff = 0;
7256
7257                 if (intel_crtc->config->limited_color_range)
7258                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7259
7260                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7261                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7262                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7263
7264                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7265         } else {
7266                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7267
7268                 if (intel_crtc->config->limited_color_range)
7269                         mode |= CSC_BLACK_SCREEN_OFFSET;
7270
7271                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7272         }
7273 }
7274
7275 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7276 {
7277         struct drm_device *dev = crtc->dev;
7278         struct drm_i915_private *dev_priv = dev->dev_private;
7279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7280         enum pipe pipe = intel_crtc->pipe;
7281         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7282         uint32_t val;
7283
7284         val = 0;
7285
7286         if (IS_HASWELL(dev) && intel_crtc->config->dither)
7287                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7288
7289         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7290                 val |= PIPECONF_INTERLACED_ILK;
7291         else
7292                 val |= PIPECONF_PROGRESSIVE;
7293
7294         I915_WRITE(PIPECONF(cpu_transcoder), val);
7295         POSTING_READ(PIPECONF(cpu_transcoder));
7296
7297         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7298         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7299
7300         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7301                 val = 0;
7302
7303                 switch (intel_crtc->config->pipe_bpp) {
7304                 case 18:
7305                         val |= PIPEMISC_DITHER_6_BPC;
7306                         break;
7307                 case 24:
7308                         val |= PIPEMISC_DITHER_8_BPC;
7309                         break;
7310                 case 30:
7311                         val |= PIPEMISC_DITHER_10_BPC;
7312                         break;
7313                 case 36:
7314                         val |= PIPEMISC_DITHER_12_BPC;
7315                         break;
7316                 default:
7317                         /* Case prevented by pipe_config_set_bpp. */
7318                         BUG();
7319                 }
7320
7321                 if (intel_crtc->config->dither)
7322                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7323
7324                 I915_WRITE(PIPEMISC(pipe), val);
7325         }
7326 }
7327
7328 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7329                                     struct intel_crtc_state *crtc_state,
7330                                     intel_clock_t *clock,
7331                                     bool *has_reduced_clock,
7332                                     intel_clock_t *reduced_clock)
7333 {
7334         struct drm_device *dev = crtc->dev;
7335         struct drm_i915_private *dev_priv = dev->dev_private;
7336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7337         int refclk;
7338         const intel_limit_t *limit;
7339         bool ret, is_lvds = false;
7340
7341         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7342
7343         refclk = ironlake_get_refclk(crtc);
7344
7345         /*
7346          * Returns a set of divisors for the desired target clock with the given
7347          * refclk, or FALSE.  The returned values represent the clock equation:
7348          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7349          */
7350         limit = intel_limit(intel_crtc, refclk);
7351         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7352                                           crtc_state->port_clock,
7353                                           refclk, NULL, clock);
7354         if (!ret)
7355                 return false;
7356
7357         if (is_lvds && dev_priv->lvds_downclock_avail) {
7358                 /*
7359                  * Ensure we match the reduced clock's P to the target clock.
7360                  * If the clocks don't match, we can't switch the display clock
7361                  * by using the FP0/FP1. In such case we will disable the LVDS
7362                  * downclock feature.
7363                 */
7364                 *has_reduced_clock =
7365                         dev_priv->display.find_dpll(limit, intel_crtc,
7366                                                     dev_priv->lvds_downclock,
7367                                                     refclk, clock,
7368                                                     reduced_clock);
7369         }
7370
7371         return true;
7372 }
7373
7374 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7375 {
7376         /*
7377          * Account for spread spectrum to avoid
7378          * oversubscribing the link. Max center spread
7379          * is 2.5%; use 5% for safety's sake.
7380          */
7381         u32 bps = target_clock * bpp * 21 / 20;
7382         return DIV_ROUND_UP(bps, link_bw * 8);
7383 }
7384
7385 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7386 {
7387         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7388 }
7389
7390 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7391                                       struct intel_crtc_state *crtc_state,
7392                                       u32 *fp,
7393                                       intel_clock_t *reduced_clock, u32 *fp2)
7394 {
7395         struct drm_crtc *crtc = &intel_crtc->base;
7396         struct drm_device *dev = crtc->dev;
7397         struct drm_i915_private *dev_priv = dev->dev_private;
7398         struct intel_encoder *intel_encoder;
7399         uint32_t dpll;
7400         int factor, num_connectors = 0;
7401         bool is_lvds = false, is_sdvo = false;
7402
7403         for_each_intel_encoder(dev, intel_encoder) {
7404                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7405                         continue;
7406
7407                 switch (intel_encoder->type) {
7408                 case INTEL_OUTPUT_LVDS:
7409                         is_lvds = true;
7410                         break;
7411                 case INTEL_OUTPUT_SDVO:
7412                 case INTEL_OUTPUT_HDMI:
7413                         is_sdvo = true;
7414                         break;
7415                 default:
7416                         break;
7417                 }
7418
7419                 num_connectors++;
7420         }
7421
7422         /* Enable autotuning of the PLL clock (if permissible) */
7423         factor = 21;
7424         if (is_lvds) {
7425                 if ((intel_panel_use_ssc(dev_priv) &&
7426                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7427                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7428                         factor = 25;
7429         } else if (crtc_state->sdvo_tv_clock)
7430                 factor = 20;
7431
7432         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7433                 *fp |= FP_CB_TUNE;
7434
7435         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7436                 *fp2 |= FP_CB_TUNE;
7437
7438         dpll = 0;
7439
7440         if (is_lvds)
7441                 dpll |= DPLLB_MODE_LVDS;
7442         else
7443                 dpll |= DPLLB_MODE_DAC_SERIAL;
7444
7445         dpll |= (crtc_state->pixel_multiplier - 1)
7446                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7447
7448         if (is_sdvo)
7449                 dpll |= DPLL_SDVO_HIGH_SPEED;
7450         if (crtc_state->has_dp_encoder)
7451                 dpll |= DPLL_SDVO_HIGH_SPEED;
7452
7453         /* compute bitmask from p1 value */
7454         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7455         /* also FPA1 */
7456         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7457
7458         switch (crtc_state->dpll.p2) {
7459         case 5:
7460                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7461                 break;
7462         case 7:
7463                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7464                 break;
7465         case 10:
7466                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7467                 break;
7468         case 14:
7469                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7470                 break;
7471         }
7472
7473         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7474                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7475         else
7476                 dpll |= PLL_REF_INPUT_DREFCLK;
7477
7478         return dpll | DPLL_VCO_ENABLE;
7479 }
7480
7481 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7482                                        struct intel_crtc_state *crtc_state)
7483 {
7484         struct drm_device *dev = crtc->base.dev;
7485         intel_clock_t clock, reduced_clock;
7486         u32 dpll = 0, fp = 0, fp2 = 0;
7487         bool ok, has_reduced_clock = false;
7488         bool is_lvds = false;
7489         struct intel_shared_dpll *pll;
7490
7491         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7492
7493         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7494              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7495
7496         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7497                                      &has_reduced_clock, &reduced_clock);
7498         if (!ok && !crtc_state->clock_set) {
7499                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7500                 return -EINVAL;
7501         }
7502         /* Compat-code for transition, will disappear. */
7503         if (!crtc_state->clock_set) {
7504                 crtc_state->dpll.n = clock.n;
7505                 crtc_state->dpll.m1 = clock.m1;
7506                 crtc_state->dpll.m2 = clock.m2;
7507                 crtc_state->dpll.p1 = clock.p1;
7508                 crtc_state->dpll.p2 = clock.p2;
7509         }
7510
7511         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7512         if (crtc_state->has_pch_encoder) {
7513                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7514                 if (has_reduced_clock)
7515                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7516
7517                 dpll = ironlake_compute_dpll(crtc, crtc_state,
7518                                              &fp, &reduced_clock,
7519                                              has_reduced_clock ? &fp2 : NULL);
7520
7521                 crtc_state->dpll_hw_state.dpll = dpll;
7522                 crtc_state->dpll_hw_state.fp0 = fp;
7523                 if (has_reduced_clock)
7524                         crtc_state->dpll_hw_state.fp1 = fp2;
7525                 else
7526                         crtc_state->dpll_hw_state.fp1 = fp;
7527
7528                 pll = intel_get_shared_dpll(crtc, crtc_state);
7529                 if (pll == NULL) {
7530                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7531                                          pipe_name(crtc->pipe));
7532                         return -EINVAL;
7533                 }
7534         }
7535
7536         if (is_lvds && has_reduced_clock && i915.powersave)
7537                 crtc->lowfreq_avail = true;
7538         else
7539                 crtc->lowfreq_avail = false;
7540
7541         return 0;
7542 }
7543
7544 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7545                                          struct intel_link_m_n *m_n)
7546 {
7547         struct drm_device *dev = crtc->base.dev;
7548         struct drm_i915_private *dev_priv = dev->dev_private;
7549         enum pipe pipe = crtc->pipe;
7550
7551         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7552         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7553         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7554                 & ~TU_SIZE_MASK;
7555         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7556         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7557                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7558 }
7559
7560 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7561                                          enum transcoder transcoder,
7562                                          struct intel_link_m_n *m_n,
7563                                          struct intel_link_m_n *m2_n2)
7564 {
7565         struct drm_device *dev = crtc->base.dev;
7566         struct drm_i915_private *dev_priv = dev->dev_private;
7567         enum pipe pipe = crtc->pipe;
7568
7569         if (INTEL_INFO(dev)->gen >= 5) {
7570                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7571                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7572                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7573                         & ~TU_SIZE_MASK;
7574                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7575                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7576                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7577                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7578                  * gen < 8) and if DRRS is supported (to make sure the
7579                  * registers are not unnecessarily read).
7580                  */
7581                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7582                         crtc->config->has_drrs) {
7583                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7584                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7585                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7586                                         & ~TU_SIZE_MASK;
7587                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7588                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7589                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7590                 }
7591         } else {
7592                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7593                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7594                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7595                         & ~TU_SIZE_MASK;
7596                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7597                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7598                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7599         }
7600 }
7601
7602 void intel_dp_get_m_n(struct intel_crtc *crtc,
7603                       struct intel_crtc_state *pipe_config)
7604 {
7605         if (pipe_config->has_pch_encoder)
7606                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7607         else
7608                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7609                                              &pipe_config->dp_m_n,
7610                                              &pipe_config->dp_m2_n2);
7611 }
7612
7613 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7614                                         struct intel_crtc_state *pipe_config)
7615 {
7616         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7617                                      &pipe_config->fdi_m_n, NULL);
7618 }
7619
7620 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7621                                     struct intel_crtc_state *pipe_config)
7622 {
7623         struct drm_device *dev = crtc->base.dev;
7624         struct drm_i915_private *dev_priv = dev->dev_private;
7625         uint32_t tmp;
7626
7627         tmp = I915_READ(PS_CTL(crtc->pipe));
7628
7629         if (tmp & PS_ENABLE) {
7630                 pipe_config->pch_pfit.enabled = true;
7631                 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7632                 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7633         }
7634 }
7635
7636 static void
7637 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7638                                  struct intel_initial_plane_config *plane_config)
7639 {
7640         struct drm_device *dev = crtc->base.dev;
7641         struct drm_i915_private *dev_priv = dev->dev_private;
7642         u32 val, base, offset, stride_mult;
7643         int pipe = crtc->pipe;
7644         int fourcc, pixel_format;
7645         int aligned_height;
7646         struct drm_framebuffer *fb;
7647         struct intel_framebuffer *intel_fb;
7648
7649         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7650         if (!intel_fb) {
7651                 DRM_DEBUG_KMS("failed to alloc fb\n");
7652                 return;
7653         }
7654
7655         fb = &intel_fb->base;
7656
7657         val = I915_READ(PLANE_CTL(pipe, 0));
7658         if (!(val & PLANE_CTL_ENABLE))
7659                 goto error;
7660
7661         if (val & PLANE_CTL_TILED_MASK)
7662                 plane_config->tiling = I915_TILING_X;
7663
7664         pixel_format = val & PLANE_CTL_FORMAT_MASK;
7665         fourcc = skl_format_to_fourcc(pixel_format,
7666                                       val & PLANE_CTL_ORDER_RGBX,
7667                                       val & PLANE_CTL_ALPHA_MASK);
7668         fb->pixel_format = fourcc;
7669         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7670
7671         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7672         plane_config->base = base;
7673
7674         offset = I915_READ(PLANE_OFFSET(pipe, 0));
7675
7676         val = I915_READ(PLANE_SIZE(pipe, 0));
7677         fb->height = ((val >> 16) & 0xfff) + 1;
7678         fb->width = ((val >> 0) & 0x1fff) + 1;
7679
7680         val = I915_READ(PLANE_STRIDE(pipe, 0));
7681         switch (plane_config->tiling) {
7682         case I915_TILING_NONE:
7683                 stride_mult = 64;
7684                 break;
7685         case I915_TILING_X:
7686                 stride_mult = 512;
7687                 break;
7688         default:
7689                 MISSING_CASE(plane_config->tiling);
7690                 goto error;
7691         }
7692         fb->pitches[0] = (val & 0x3ff) * stride_mult;
7693
7694         aligned_height = intel_fb_align_height(dev, fb->height,
7695                                                plane_config->tiling);
7696
7697         plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
7698
7699         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7700                       pipe_name(pipe), fb->width, fb->height,
7701                       fb->bits_per_pixel, base, fb->pitches[0],
7702                       plane_config->size);
7703
7704         plane_config->fb = intel_fb;
7705         return;
7706
7707 error:
7708         kfree(fb);
7709 }
7710
7711 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7712                                      struct intel_crtc_state *pipe_config)
7713 {
7714         struct drm_device *dev = crtc->base.dev;
7715         struct drm_i915_private *dev_priv = dev->dev_private;
7716         uint32_t tmp;
7717
7718         tmp = I915_READ(PF_CTL(crtc->pipe));
7719
7720         if (tmp & PF_ENABLE) {
7721                 pipe_config->pch_pfit.enabled = true;
7722                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7723                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7724
7725                 /* We currently do not free assignements of panel fitters on
7726                  * ivb/hsw (since we don't use the higher upscaling modes which
7727                  * differentiates them) so just WARN about this case for now. */
7728                 if (IS_GEN7(dev)) {
7729                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7730                                 PF_PIPE_SEL_IVB(crtc->pipe));
7731                 }
7732         }
7733 }
7734
7735 static void
7736 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7737                                   struct intel_initial_plane_config *plane_config)
7738 {
7739         struct drm_device *dev = crtc->base.dev;
7740         struct drm_i915_private *dev_priv = dev->dev_private;
7741         u32 val, base, offset;
7742         int pipe = crtc->pipe;
7743         int fourcc, pixel_format;
7744         int aligned_height;
7745         struct drm_framebuffer *fb;
7746         struct intel_framebuffer *intel_fb;
7747
7748         val = I915_READ(DSPCNTR(pipe));
7749         if (!(val & DISPLAY_PLANE_ENABLE))
7750                 return;
7751
7752         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7753         if (!intel_fb) {
7754                 DRM_DEBUG_KMS("failed to alloc fb\n");
7755                 return;
7756         }
7757
7758         fb = &intel_fb->base;
7759
7760         if (INTEL_INFO(dev)->gen >= 4)
7761                 if (val & DISPPLANE_TILED)
7762                         plane_config->tiling = I915_TILING_X;
7763
7764         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7765         fourcc = i9xx_format_to_fourcc(pixel_format);
7766         fb->pixel_format = fourcc;
7767         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7768
7769         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7770         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7771                 offset = I915_READ(DSPOFFSET(pipe));
7772         } else {
7773                 if (plane_config->tiling)
7774                         offset = I915_READ(DSPTILEOFF(pipe));
7775                 else
7776                         offset = I915_READ(DSPLINOFF(pipe));
7777         }
7778         plane_config->base = base;
7779
7780         val = I915_READ(PIPESRC(pipe));
7781         fb->width = ((val >> 16) & 0xfff) + 1;
7782         fb->height = ((val >> 0) & 0xfff) + 1;
7783
7784         val = I915_READ(DSPSTRIDE(pipe));
7785         fb->pitches[0] = val & 0xffffffc0;
7786
7787         aligned_height = intel_fb_align_height(dev, fb->height,
7788                                                plane_config->tiling);
7789
7790         plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
7791
7792         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7793                       pipe_name(pipe), fb->width, fb->height,
7794                       fb->bits_per_pixel, base, fb->pitches[0],
7795                       plane_config->size);
7796
7797         plane_config->fb = intel_fb;
7798 }
7799
7800 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7801                                      struct intel_crtc_state *pipe_config)
7802 {
7803         struct drm_device *dev = crtc->base.dev;
7804         struct drm_i915_private *dev_priv = dev->dev_private;
7805         uint32_t tmp;
7806
7807         if (!intel_display_power_is_enabled(dev_priv,
7808                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7809                 return false;
7810
7811         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7812         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7813
7814         tmp = I915_READ(PIPECONF(crtc->pipe));
7815         if (!(tmp & PIPECONF_ENABLE))
7816                 return false;
7817
7818         switch (tmp & PIPECONF_BPC_MASK) {
7819         case PIPECONF_6BPC:
7820                 pipe_config->pipe_bpp = 18;
7821                 break;
7822         case PIPECONF_8BPC:
7823                 pipe_config->pipe_bpp = 24;
7824                 break;
7825         case PIPECONF_10BPC:
7826                 pipe_config->pipe_bpp = 30;
7827                 break;
7828         case PIPECONF_12BPC:
7829                 pipe_config->pipe_bpp = 36;
7830                 break;
7831         default:
7832                 break;
7833         }
7834
7835         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7836                 pipe_config->limited_color_range = true;
7837
7838         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7839                 struct intel_shared_dpll *pll;
7840
7841                 pipe_config->has_pch_encoder = true;
7842
7843                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7844                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7845                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7846
7847                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7848
7849                 if (HAS_PCH_IBX(dev_priv->dev)) {
7850                         pipe_config->shared_dpll =
7851                                 (enum intel_dpll_id) crtc->pipe;
7852                 } else {
7853                         tmp = I915_READ(PCH_DPLL_SEL);
7854                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7855                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7856                         else
7857                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7858                 }
7859
7860                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7861
7862                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7863                                            &pipe_config->dpll_hw_state));
7864
7865                 tmp = pipe_config->dpll_hw_state.dpll;
7866                 pipe_config->pixel_multiplier =
7867                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7868                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7869
7870                 ironlake_pch_clock_get(crtc, pipe_config);
7871         } else {
7872                 pipe_config->pixel_multiplier = 1;
7873         }
7874
7875         intel_get_pipe_timings(crtc, pipe_config);
7876
7877         ironlake_get_pfit_config(crtc, pipe_config);
7878
7879         return true;
7880 }
7881
7882 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7883 {
7884         struct drm_device *dev = dev_priv->dev;
7885         struct intel_crtc *crtc;
7886
7887         for_each_intel_crtc(dev, crtc)
7888                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7889                      pipe_name(crtc->pipe));
7890
7891         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7892         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7893         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7894         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7895         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7896         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7897              "CPU PWM1 enabled\n");
7898         if (IS_HASWELL(dev))
7899                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7900                      "CPU PWM2 enabled\n");
7901         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7902              "PCH PWM1 enabled\n");
7903         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7904              "Utility pin enabled\n");
7905         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7906
7907         /*
7908          * In theory we can still leave IRQs enabled, as long as only the HPD
7909          * interrupts remain enabled. We used to check for that, but since it's
7910          * gen-specific and since we only disable LCPLL after we fully disable
7911          * the interrupts, the check below should be enough.
7912          */
7913         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7914 }
7915
7916 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7917 {
7918         struct drm_device *dev = dev_priv->dev;
7919
7920         if (IS_HASWELL(dev))
7921                 return I915_READ(D_COMP_HSW);
7922         else
7923                 return I915_READ(D_COMP_BDW);
7924 }
7925
7926 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7927 {
7928         struct drm_device *dev = dev_priv->dev;
7929
7930         if (IS_HASWELL(dev)) {
7931                 mutex_lock(&dev_priv->rps.hw_lock);
7932                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7933                                             val))
7934                         DRM_ERROR("Failed to write to D_COMP\n");
7935                 mutex_unlock(&dev_priv->rps.hw_lock);
7936         } else {
7937                 I915_WRITE(D_COMP_BDW, val);
7938                 POSTING_READ(D_COMP_BDW);
7939         }
7940 }
7941
7942 /*
7943  * This function implements pieces of two sequences from BSpec:
7944  * - Sequence for display software to disable LCPLL
7945  * - Sequence for display software to allow package C8+
7946  * The steps implemented here are just the steps that actually touch the LCPLL
7947  * register. Callers should take care of disabling all the display engine
7948  * functions, doing the mode unset, fixing interrupts, etc.
7949  */
7950 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7951                               bool switch_to_fclk, bool allow_power_down)
7952 {
7953         uint32_t val;
7954
7955         assert_can_disable_lcpll(dev_priv);
7956
7957         val = I915_READ(LCPLL_CTL);
7958
7959         if (switch_to_fclk) {
7960                 val |= LCPLL_CD_SOURCE_FCLK;
7961                 I915_WRITE(LCPLL_CTL, val);
7962
7963                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7964                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7965                         DRM_ERROR("Switching to FCLK failed\n");
7966
7967                 val = I915_READ(LCPLL_CTL);
7968         }
7969
7970         val |= LCPLL_PLL_DISABLE;
7971         I915_WRITE(LCPLL_CTL, val);
7972         POSTING_READ(LCPLL_CTL);
7973
7974         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7975                 DRM_ERROR("LCPLL still locked\n");
7976
7977         val = hsw_read_dcomp(dev_priv);
7978         val |= D_COMP_COMP_DISABLE;
7979         hsw_write_dcomp(dev_priv, val);
7980         ndelay(100);
7981
7982         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7983                      1))
7984                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7985
7986         if (allow_power_down) {
7987                 val = I915_READ(LCPLL_CTL);
7988                 val |= LCPLL_POWER_DOWN_ALLOW;
7989                 I915_WRITE(LCPLL_CTL, val);
7990                 POSTING_READ(LCPLL_CTL);
7991         }
7992 }
7993
7994 /*
7995  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7996  * source.
7997  */
7998 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7999 {
8000         uint32_t val;
8001
8002         val = I915_READ(LCPLL_CTL);
8003
8004         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8005                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8006                 return;
8007
8008         /*
8009          * Make sure we're not on PC8 state before disabling PC8, otherwise
8010          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8011          */
8012         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8013
8014         if (val & LCPLL_POWER_DOWN_ALLOW) {
8015                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8016                 I915_WRITE(LCPLL_CTL, val);
8017                 POSTING_READ(LCPLL_CTL);
8018         }
8019
8020         val = hsw_read_dcomp(dev_priv);
8021         val |= D_COMP_COMP_FORCE;
8022         val &= ~D_COMP_COMP_DISABLE;
8023         hsw_write_dcomp(dev_priv, val);
8024
8025         val = I915_READ(LCPLL_CTL);
8026         val &= ~LCPLL_PLL_DISABLE;
8027         I915_WRITE(LCPLL_CTL, val);
8028
8029         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8030                 DRM_ERROR("LCPLL not locked yet\n");
8031
8032         if (val & LCPLL_CD_SOURCE_FCLK) {
8033                 val = I915_READ(LCPLL_CTL);
8034                 val &= ~LCPLL_CD_SOURCE_FCLK;
8035                 I915_WRITE(LCPLL_CTL, val);
8036
8037                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8038                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8039                         DRM_ERROR("Switching back to LCPLL failed\n");
8040         }
8041
8042         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8043 }
8044
8045 /*
8046  * Package states C8 and deeper are really deep PC states that can only be
8047  * reached when all the devices on the system allow it, so even if the graphics
8048  * device allows PC8+, it doesn't mean the system will actually get to these
8049  * states. Our driver only allows PC8+ when going into runtime PM.
8050  *
8051  * The requirements for PC8+ are that all the outputs are disabled, the power
8052  * well is disabled and most interrupts are disabled, and these are also
8053  * requirements for runtime PM. When these conditions are met, we manually do
8054  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8055  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8056  * hang the machine.
8057  *
8058  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8059  * the state of some registers, so when we come back from PC8+ we need to
8060  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8061  * need to take care of the registers kept by RC6. Notice that this happens even
8062  * if we don't put the device in PCI D3 state (which is what currently happens
8063  * because of the runtime PM support).
8064  *
8065  * For more, read "Display Sequences for Package C8" on the hardware
8066  * documentation.
8067  */
8068 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8069 {
8070         struct drm_device *dev = dev_priv->dev;
8071         uint32_t val;
8072
8073         DRM_DEBUG_KMS("Enabling package C8+\n");
8074
8075         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8076                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8077                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8078                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8079         }
8080
8081         lpt_disable_clkout_dp(dev);
8082         hsw_disable_lcpll(dev_priv, true, true);
8083 }
8084
8085 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8086 {
8087         struct drm_device *dev = dev_priv->dev;
8088         uint32_t val;
8089
8090         DRM_DEBUG_KMS("Disabling package C8+\n");
8091
8092         hsw_restore_lcpll(dev_priv);
8093         lpt_init_pch_refclk(dev);
8094
8095         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8096                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8097                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8098                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8099         }
8100
8101         intel_prepare_ddi(dev);
8102 }
8103
8104 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8105                                       struct intel_crtc_state *crtc_state)
8106 {
8107         if (!intel_ddi_pll_select(crtc, crtc_state))
8108                 return -EINVAL;
8109
8110         crtc->lowfreq_avail = false;
8111
8112         return 0;
8113 }
8114
8115 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8116                                 enum port port,
8117                                 struct intel_crtc_state *pipe_config)
8118 {
8119         u32 temp, dpll_ctl1;
8120
8121         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8122         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8123
8124         switch (pipe_config->ddi_pll_sel) {
8125         case SKL_DPLL0:
8126                 /*
8127                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8128                  * of the shared DPLL framework and thus needs to be read out
8129                  * separately
8130                  */
8131                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8132                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8133                 break;
8134         case SKL_DPLL1:
8135                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8136                 break;
8137         case SKL_DPLL2:
8138                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8139                 break;
8140         case SKL_DPLL3:
8141                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8142                 break;
8143         }
8144 }
8145
8146 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8147                                 enum port port,
8148                                 struct intel_crtc_state *pipe_config)
8149 {
8150         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8151
8152         switch (pipe_config->ddi_pll_sel) {
8153         case PORT_CLK_SEL_WRPLL1:
8154                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8155                 break;
8156         case PORT_CLK_SEL_WRPLL2:
8157                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8158                 break;
8159         }
8160 }
8161
8162 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8163                                        struct intel_crtc_state *pipe_config)
8164 {
8165         struct drm_device *dev = crtc->base.dev;
8166         struct drm_i915_private *dev_priv = dev->dev_private;
8167         struct intel_shared_dpll *pll;
8168         enum port port;
8169         uint32_t tmp;
8170
8171         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8172
8173         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8174
8175         if (IS_SKYLAKE(dev))
8176                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8177         else
8178                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8179
8180         if (pipe_config->shared_dpll >= 0) {
8181                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8182
8183                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8184                                            &pipe_config->dpll_hw_state));
8185         }
8186
8187         /*
8188          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8189          * DDI E. So just check whether this pipe is wired to DDI E and whether
8190          * the PCH transcoder is on.
8191          */
8192         if (INTEL_INFO(dev)->gen < 9 &&
8193             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8194                 pipe_config->has_pch_encoder = true;
8195
8196                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8197                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8198                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8199
8200                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8201         }
8202 }
8203
8204 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8205                                     struct intel_crtc_state *pipe_config)
8206 {
8207         struct drm_device *dev = crtc->base.dev;
8208         struct drm_i915_private *dev_priv = dev->dev_private;
8209         enum intel_display_power_domain pfit_domain;
8210         uint32_t tmp;
8211
8212         if (!intel_display_power_is_enabled(dev_priv,
8213                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8214                 return false;
8215
8216         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8217         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8218
8219         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8220         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8221                 enum pipe trans_edp_pipe;
8222                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8223                 default:
8224                         WARN(1, "unknown pipe linked to edp transcoder\n");
8225                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8226                 case TRANS_DDI_EDP_INPUT_A_ON:
8227                         trans_edp_pipe = PIPE_A;
8228                         break;
8229                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8230                         trans_edp_pipe = PIPE_B;
8231                         break;
8232                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8233                         trans_edp_pipe = PIPE_C;
8234                         break;
8235                 }
8236
8237                 if (trans_edp_pipe == crtc->pipe)
8238                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8239         }
8240
8241         if (!intel_display_power_is_enabled(dev_priv,
8242                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8243                 return false;
8244
8245         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8246         if (!(tmp & PIPECONF_ENABLE))
8247                 return false;
8248
8249         haswell_get_ddi_port_state(crtc, pipe_config);
8250
8251         intel_get_pipe_timings(crtc, pipe_config);
8252
8253         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8254         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8255                 if (IS_SKYLAKE(dev))
8256                         skylake_get_pfit_config(crtc, pipe_config);
8257                 else
8258                         ironlake_get_pfit_config(crtc, pipe_config);
8259         }
8260
8261         if (IS_HASWELL(dev))
8262                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8263                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8264
8265         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8266                 pipe_config->pixel_multiplier =
8267                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8268         } else {
8269                 pipe_config->pixel_multiplier = 1;
8270         }
8271
8272         return true;
8273 }
8274
8275 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8276 {
8277         struct drm_device *dev = crtc->dev;
8278         struct drm_i915_private *dev_priv = dev->dev_private;
8279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8280         uint32_t cntl = 0, size = 0;
8281
8282         if (base) {
8283                 unsigned int width = intel_crtc->cursor_width;
8284                 unsigned int height = intel_crtc->cursor_height;
8285                 unsigned int stride = roundup_pow_of_two(width) * 4;
8286
8287                 switch (stride) {
8288                 default:
8289                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8290                                   width, stride);
8291                         stride = 256;
8292                         /* fallthrough */
8293                 case 256:
8294                 case 512:
8295                 case 1024:
8296                 case 2048:
8297                         break;
8298                 }
8299
8300                 cntl |= CURSOR_ENABLE |
8301                         CURSOR_GAMMA_ENABLE |
8302                         CURSOR_FORMAT_ARGB |
8303                         CURSOR_STRIDE(stride);
8304
8305                 size = (height << 12) | width;
8306         }
8307
8308         if (intel_crtc->cursor_cntl != 0 &&
8309             (intel_crtc->cursor_base != base ||
8310              intel_crtc->cursor_size != size ||
8311              intel_crtc->cursor_cntl != cntl)) {
8312                 /* On these chipsets we can only modify the base/size/stride
8313                  * whilst the cursor is disabled.
8314                  */
8315                 I915_WRITE(_CURACNTR, 0);
8316                 POSTING_READ(_CURACNTR);
8317                 intel_crtc->cursor_cntl = 0;
8318         }
8319
8320         if (intel_crtc->cursor_base != base) {
8321                 I915_WRITE(_CURABASE, base);
8322                 intel_crtc->cursor_base = base;
8323         }
8324
8325         if (intel_crtc->cursor_size != size) {
8326                 I915_WRITE(CURSIZE, size);
8327                 intel_crtc->cursor_size = size;
8328         }
8329
8330         if (intel_crtc->cursor_cntl != cntl) {
8331                 I915_WRITE(_CURACNTR, cntl);
8332                 POSTING_READ(_CURACNTR);
8333                 intel_crtc->cursor_cntl = cntl;
8334         }
8335 }
8336
8337 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8338 {
8339         struct drm_device *dev = crtc->dev;
8340         struct drm_i915_private *dev_priv = dev->dev_private;
8341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8342         int pipe = intel_crtc->pipe;
8343         uint32_t cntl;
8344
8345         cntl = 0;
8346         if (base) {
8347                 cntl = MCURSOR_GAMMA_ENABLE;
8348                 switch (intel_crtc->cursor_width) {
8349                         case 64:
8350                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8351                                 break;
8352                         case 128:
8353                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8354                                 break;
8355                         case 256:
8356                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8357                                 break;
8358                         default:
8359                                 MISSING_CASE(intel_crtc->cursor_width);
8360                                 return;
8361                 }
8362                 cntl |= pipe << 28; /* Connect to correct pipe */
8363
8364                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8365                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8366         }
8367
8368         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8369                 cntl |= CURSOR_ROTATE_180;
8370
8371         if (intel_crtc->cursor_cntl != cntl) {
8372                 I915_WRITE(CURCNTR(pipe), cntl);
8373                 POSTING_READ(CURCNTR(pipe));
8374                 intel_crtc->cursor_cntl = cntl;
8375         }
8376
8377         /* and commit changes on next vblank */
8378         I915_WRITE(CURBASE(pipe), base);
8379         POSTING_READ(CURBASE(pipe));
8380
8381         intel_crtc->cursor_base = base;
8382 }
8383
8384 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8385 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8386                                      bool on)
8387 {
8388         struct drm_device *dev = crtc->dev;
8389         struct drm_i915_private *dev_priv = dev->dev_private;
8390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8391         int pipe = intel_crtc->pipe;
8392         int x = crtc->cursor_x;
8393         int y = crtc->cursor_y;
8394         u32 base = 0, pos = 0;
8395
8396         if (on)
8397                 base = intel_crtc->cursor_addr;
8398
8399         if (x >= intel_crtc->config->pipe_src_w)
8400                 base = 0;
8401
8402         if (y >= intel_crtc->config->pipe_src_h)
8403                 base = 0;
8404
8405         if (x < 0) {
8406                 if (x + intel_crtc->cursor_width <= 0)
8407                         base = 0;
8408
8409                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8410                 x = -x;
8411         }
8412         pos |= x << CURSOR_X_SHIFT;
8413
8414         if (y < 0) {
8415                 if (y + intel_crtc->cursor_height <= 0)
8416                         base = 0;
8417
8418                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8419                 y = -y;
8420         }
8421         pos |= y << CURSOR_Y_SHIFT;
8422
8423         if (base == 0 && intel_crtc->cursor_base == 0)
8424                 return;
8425
8426         I915_WRITE(CURPOS(pipe), pos);
8427
8428         /* ILK+ do this automagically */
8429         if (HAS_GMCH_DISPLAY(dev) &&
8430             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8431                 base += (intel_crtc->cursor_height *
8432                         intel_crtc->cursor_width - 1) * 4;
8433         }
8434
8435         if (IS_845G(dev) || IS_I865G(dev))
8436                 i845_update_cursor(crtc, base);
8437         else
8438                 i9xx_update_cursor(crtc, base);
8439 }
8440
8441 static bool cursor_size_ok(struct drm_device *dev,
8442                            uint32_t width, uint32_t height)
8443 {
8444         if (width == 0 || height == 0)
8445                 return false;
8446
8447         /*
8448          * 845g/865g are special in that they are only limited by
8449          * the width of their cursors, the height is arbitrary up to
8450          * the precision of the register. Everything else requires
8451          * square cursors, limited to a few power-of-two sizes.
8452          */
8453         if (IS_845G(dev) || IS_I865G(dev)) {
8454                 if ((width & 63) != 0)
8455                         return false;
8456
8457                 if (width > (IS_845G(dev) ? 64 : 512))
8458                         return false;
8459
8460                 if (height > 1023)
8461                         return false;
8462         } else {
8463                 switch (width | height) {
8464                 case 256:
8465                 case 128:
8466                         if (IS_GEN2(dev))
8467                                 return false;
8468                 case 64:
8469                         break;
8470                 default:
8471                         return false;
8472                 }
8473         }
8474
8475         return true;
8476 }
8477
8478 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8479                                  u16 *blue, uint32_t start, uint32_t size)
8480 {
8481         int end = (start + size > 256) ? 256 : start + size, i;
8482         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8483
8484         for (i = start; i < end; i++) {
8485                 intel_crtc->lut_r[i] = red[i] >> 8;
8486                 intel_crtc->lut_g[i] = green[i] >> 8;
8487                 intel_crtc->lut_b[i] = blue[i] >> 8;
8488         }
8489
8490         intel_crtc_load_lut(crtc);
8491 }
8492
8493 /* VESA 640x480x72Hz mode to set on the pipe */
8494 static struct drm_display_mode load_detect_mode = {
8495         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8496                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8497 };
8498
8499 struct drm_framebuffer *
8500 __intel_framebuffer_create(struct drm_device *dev,
8501                            struct drm_mode_fb_cmd2 *mode_cmd,
8502                            struct drm_i915_gem_object *obj)
8503 {
8504         struct intel_framebuffer *intel_fb;
8505         int ret;
8506
8507         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8508         if (!intel_fb) {
8509                 drm_gem_object_unreference(&obj->base);
8510                 return ERR_PTR(-ENOMEM);
8511         }
8512
8513         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8514         if (ret)
8515                 goto err;
8516
8517         return &intel_fb->base;
8518 err:
8519         drm_gem_object_unreference(&obj->base);
8520         kfree(intel_fb);
8521
8522         return ERR_PTR(ret);
8523 }
8524
8525 static struct drm_framebuffer *
8526 intel_framebuffer_create(struct drm_device *dev,
8527                          struct drm_mode_fb_cmd2 *mode_cmd,
8528                          struct drm_i915_gem_object *obj)
8529 {
8530         struct drm_framebuffer *fb;
8531         int ret;
8532
8533         ret = i915_mutex_lock_interruptible(dev);
8534         if (ret)
8535                 return ERR_PTR(ret);
8536         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8537         mutex_unlock(&dev->struct_mutex);
8538
8539         return fb;
8540 }
8541
8542 static u32
8543 intel_framebuffer_pitch_for_width(int width, int bpp)
8544 {
8545         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8546         return ALIGN(pitch, 64);
8547 }
8548
8549 static u32
8550 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8551 {
8552         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8553         return PAGE_ALIGN(pitch * mode->vdisplay);
8554 }
8555
8556 static struct drm_framebuffer *
8557 intel_framebuffer_create_for_mode(struct drm_device *dev,
8558                                   struct drm_display_mode *mode,
8559                                   int depth, int bpp)
8560 {
8561         struct drm_i915_gem_object *obj;
8562         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8563
8564         obj = i915_gem_alloc_object(dev,
8565                                     intel_framebuffer_size_for_mode(mode, bpp));
8566         if (obj == NULL)
8567                 return ERR_PTR(-ENOMEM);
8568
8569         mode_cmd.width = mode->hdisplay;
8570         mode_cmd.height = mode->vdisplay;
8571         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8572                                                                 bpp);
8573         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8574
8575         return intel_framebuffer_create(dev, &mode_cmd, obj);
8576 }
8577
8578 static struct drm_framebuffer *
8579 mode_fits_in_fbdev(struct drm_device *dev,
8580                    struct drm_display_mode *mode)
8581 {
8582 #ifdef CONFIG_DRM_I915_FBDEV
8583         struct drm_i915_private *dev_priv = dev->dev_private;
8584         struct drm_i915_gem_object *obj;
8585         struct drm_framebuffer *fb;
8586
8587         if (!dev_priv->fbdev)
8588                 return NULL;
8589
8590         if (!dev_priv->fbdev->fb)
8591                 return NULL;
8592
8593         obj = dev_priv->fbdev->fb->obj;
8594         BUG_ON(!obj);
8595
8596         fb = &dev_priv->fbdev->fb->base;
8597         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8598                                                                fb->bits_per_pixel))
8599                 return NULL;
8600
8601         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8602                 return NULL;
8603
8604         return fb;
8605 #else
8606         return NULL;
8607 #endif
8608 }
8609
8610 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8611                                 struct drm_display_mode *mode,
8612                                 struct intel_load_detect_pipe *old,
8613                                 struct drm_modeset_acquire_ctx *ctx)
8614 {
8615         struct intel_crtc *intel_crtc;
8616         struct intel_encoder *intel_encoder =
8617                 intel_attached_encoder(connector);
8618         struct drm_crtc *possible_crtc;
8619         struct drm_encoder *encoder = &intel_encoder->base;
8620         struct drm_crtc *crtc = NULL;
8621         struct drm_device *dev = encoder->dev;
8622         struct drm_framebuffer *fb;
8623         struct drm_mode_config *config = &dev->mode_config;
8624         int ret, i = -1;
8625
8626         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8627                       connector->base.id, connector->name,
8628                       encoder->base.id, encoder->name);
8629
8630 retry:
8631         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8632         if (ret)
8633                 goto fail_unlock;
8634
8635         /*
8636          * Algorithm gets a little messy:
8637          *
8638          *   - if the connector already has an assigned crtc, use it (but make
8639          *     sure it's on first)
8640          *
8641          *   - try to find the first unused crtc that can drive this connector,
8642          *     and use that if we find one
8643          */
8644
8645         /* See if we already have a CRTC for this connector */
8646         if (encoder->crtc) {
8647                 crtc = encoder->crtc;
8648
8649                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8650                 if (ret)
8651                         goto fail_unlock;
8652                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8653                 if (ret)
8654                         goto fail_unlock;
8655
8656                 old->dpms_mode = connector->dpms;
8657                 old->load_detect_temp = false;
8658
8659                 /* Make sure the crtc and connector are running */
8660                 if (connector->dpms != DRM_MODE_DPMS_ON)
8661                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8662
8663                 return true;
8664         }
8665
8666         /* Find an unused one (if possible) */
8667         for_each_crtc(dev, possible_crtc) {
8668                 i++;
8669                 if (!(encoder->possible_crtcs & (1 << i)))
8670                         continue;
8671                 if (possible_crtc->enabled)
8672                         continue;
8673                 /* This can occur when applying the pipe A quirk on resume. */
8674                 if (to_intel_crtc(possible_crtc)->new_enabled)
8675                         continue;
8676
8677                 crtc = possible_crtc;
8678                 break;
8679         }
8680
8681         /*
8682          * If we didn't find an unused CRTC, don't use any.
8683          */
8684         if (!crtc) {
8685                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8686                 goto fail_unlock;
8687         }
8688
8689         ret = drm_modeset_lock(&crtc->mutex, ctx);
8690         if (ret)
8691                 goto fail_unlock;
8692         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8693         if (ret)
8694                 goto fail_unlock;
8695         intel_encoder->new_crtc = to_intel_crtc(crtc);
8696         to_intel_connector(connector)->new_encoder = intel_encoder;
8697
8698         intel_crtc = to_intel_crtc(crtc);
8699         intel_crtc->new_enabled = true;
8700         intel_crtc->new_config = intel_crtc->config;
8701         old->dpms_mode = connector->dpms;
8702         old->load_detect_temp = true;
8703         old->release_fb = NULL;
8704
8705         if (!mode)
8706                 mode = &load_detect_mode;
8707
8708         /* We need a framebuffer large enough to accommodate all accesses
8709          * that the plane may generate whilst we perform load detection.
8710          * We can not rely on the fbcon either being present (we get called
8711          * during its initialisation to detect all boot displays, or it may
8712          * not even exist) or that it is large enough to satisfy the
8713          * requested mode.
8714          */
8715         fb = mode_fits_in_fbdev(dev, mode);
8716         if (fb == NULL) {
8717                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8718                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8719                 old->release_fb = fb;
8720         } else
8721                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8722         if (IS_ERR(fb)) {
8723                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8724                 goto fail;
8725         }
8726
8727         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8728                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8729                 if (old->release_fb)
8730                         old->release_fb->funcs->destroy(old->release_fb);
8731                 goto fail;
8732         }
8733
8734         /* let the connector get through one full cycle before testing */
8735         intel_wait_for_vblank(dev, intel_crtc->pipe);
8736         return true;
8737
8738  fail:
8739         intel_crtc->new_enabled = crtc->enabled;
8740         if (intel_crtc->new_enabled)
8741                 intel_crtc->new_config = intel_crtc->config;
8742         else
8743                 intel_crtc->new_config = NULL;
8744 fail_unlock:
8745         if (ret == -EDEADLK) {
8746                 drm_modeset_backoff(ctx);
8747                 goto retry;
8748         }
8749
8750         return false;
8751 }
8752
8753 void intel_release_load_detect_pipe(struct drm_connector *connector,
8754                                     struct intel_load_detect_pipe *old)
8755 {
8756         struct intel_encoder *intel_encoder =
8757                 intel_attached_encoder(connector);
8758         struct drm_encoder *encoder = &intel_encoder->base;
8759         struct drm_crtc *crtc = encoder->crtc;
8760         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8761
8762         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8763                       connector->base.id, connector->name,
8764                       encoder->base.id, encoder->name);
8765
8766         if (old->load_detect_temp) {
8767                 to_intel_connector(connector)->new_encoder = NULL;
8768                 intel_encoder->new_crtc = NULL;
8769                 intel_crtc->new_enabled = false;
8770                 intel_crtc->new_config = NULL;
8771                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8772
8773                 if (old->release_fb) {
8774                         drm_framebuffer_unregister_private(old->release_fb);
8775                         drm_framebuffer_unreference(old->release_fb);
8776                 }
8777
8778                 return;
8779         }
8780
8781         /* Switch crtc and encoder back off if necessary */
8782         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8783                 connector->funcs->dpms(connector, old->dpms_mode);
8784 }
8785
8786 static int i9xx_pll_refclk(struct drm_device *dev,
8787                            const struct intel_crtc_state *pipe_config)
8788 {
8789         struct drm_i915_private *dev_priv = dev->dev_private;
8790         u32 dpll = pipe_config->dpll_hw_state.dpll;
8791
8792         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8793                 return dev_priv->vbt.lvds_ssc_freq;
8794         else if (HAS_PCH_SPLIT(dev))
8795                 return 120000;
8796         else if (!IS_GEN2(dev))
8797                 return 96000;
8798         else
8799                 return 48000;
8800 }
8801
8802 /* Returns the clock of the currently programmed mode of the given pipe. */
8803 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8804                                 struct intel_crtc_state *pipe_config)
8805 {
8806         struct drm_device *dev = crtc->base.dev;
8807         struct drm_i915_private *dev_priv = dev->dev_private;
8808         int pipe = pipe_config->cpu_transcoder;
8809         u32 dpll = pipe_config->dpll_hw_state.dpll;
8810         u32 fp;
8811         intel_clock_t clock;
8812         int refclk = i9xx_pll_refclk(dev, pipe_config);
8813
8814         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8815                 fp = pipe_config->dpll_hw_state.fp0;
8816         else
8817                 fp = pipe_config->dpll_hw_state.fp1;
8818
8819         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8820         if (IS_PINEVIEW(dev)) {
8821                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8822                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8823         } else {
8824                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8825                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8826         }
8827
8828         if (!IS_GEN2(dev)) {
8829                 if (IS_PINEVIEW(dev))
8830                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8831                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8832                 else
8833                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8834                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8835
8836                 switch (dpll & DPLL_MODE_MASK) {
8837                 case DPLLB_MODE_DAC_SERIAL:
8838                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8839                                 5 : 10;
8840                         break;
8841                 case DPLLB_MODE_LVDS:
8842                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8843                                 7 : 14;
8844                         break;
8845                 default:
8846                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8847                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8848                         return;
8849                 }
8850
8851                 if (IS_PINEVIEW(dev))
8852                         pineview_clock(refclk, &clock);
8853                 else
8854                         i9xx_clock(refclk, &clock);
8855         } else {
8856                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8857                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8858
8859                 if (is_lvds) {
8860                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8861                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8862
8863                         if (lvds & LVDS_CLKB_POWER_UP)
8864                                 clock.p2 = 7;
8865                         else
8866                                 clock.p2 = 14;
8867                 } else {
8868                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8869                                 clock.p1 = 2;
8870                         else {
8871                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8872                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8873                         }
8874                         if (dpll & PLL_P2_DIVIDE_BY_4)
8875                                 clock.p2 = 4;
8876                         else
8877                                 clock.p2 = 2;
8878                 }
8879
8880                 i9xx_clock(refclk, &clock);
8881         }
8882
8883         /*
8884          * This value includes pixel_multiplier. We will use
8885          * port_clock to compute adjusted_mode.crtc_clock in the
8886          * encoder's get_config() function.
8887          */
8888         pipe_config->port_clock = clock.dot;
8889 }
8890
8891 int intel_dotclock_calculate(int link_freq,
8892                              const struct intel_link_m_n *m_n)
8893 {
8894         /*
8895          * The calculation for the data clock is:
8896          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8897          * But we want to avoid losing precison if possible, so:
8898          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8899          *
8900          * and the link clock is simpler:
8901          * link_clock = (m * link_clock) / n
8902          */
8903
8904         if (!m_n->link_n)
8905                 return 0;
8906
8907         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8908 }
8909
8910 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8911                                    struct intel_crtc_state *pipe_config)
8912 {
8913         struct drm_device *dev = crtc->base.dev;
8914
8915         /* read out port_clock from the DPLL */
8916         i9xx_crtc_clock_get(crtc, pipe_config);
8917
8918         /*
8919          * This value does not include pixel_multiplier.
8920          * We will check that port_clock and adjusted_mode.crtc_clock
8921          * agree once we know their relationship in the encoder's
8922          * get_config() function.
8923          */
8924         pipe_config->base.adjusted_mode.crtc_clock =
8925                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8926                                          &pipe_config->fdi_m_n);
8927 }
8928
8929 /** Returns the currently programmed mode of the given pipe. */
8930 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8931                                              struct drm_crtc *crtc)
8932 {
8933         struct drm_i915_private *dev_priv = dev->dev_private;
8934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8935         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8936         struct drm_display_mode *mode;
8937         struct intel_crtc_state pipe_config;
8938         int htot = I915_READ(HTOTAL(cpu_transcoder));
8939         int hsync = I915_READ(HSYNC(cpu_transcoder));
8940         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8941         int vsync = I915_READ(VSYNC(cpu_transcoder));
8942         enum pipe pipe = intel_crtc->pipe;
8943
8944         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8945         if (!mode)
8946                 return NULL;
8947
8948         /*
8949          * Construct a pipe_config sufficient for getting the clock info
8950          * back out of crtc_clock_get.
8951          *
8952          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8953          * to use a real value here instead.
8954          */
8955         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8956         pipe_config.pixel_multiplier = 1;
8957         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8958         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8959         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8960         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8961
8962         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8963         mode->hdisplay = (htot & 0xffff) + 1;
8964         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8965         mode->hsync_start = (hsync & 0xffff) + 1;
8966         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8967         mode->vdisplay = (vtot & 0xffff) + 1;
8968         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8969         mode->vsync_start = (vsync & 0xffff) + 1;
8970         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8971
8972         drm_mode_set_name(mode);
8973
8974         return mode;
8975 }
8976
8977 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8978 {
8979         struct drm_device *dev = crtc->dev;
8980         struct drm_i915_private *dev_priv = dev->dev_private;
8981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8982
8983         if (!HAS_GMCH_DISPLAY(dev))
8984                 return;
8985
8986         if (!dev_priv->lvds_downclock_avail)
8987                 return;
8988
8989         /*
8990          * Since this is called by a timer, we should never get here in
8991          * the manual case.
8992          */
8993         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8994                 int pipe = intel_crtc->pipe;
8995                 int dpll_reg = DPLL(pipe);
8996                 int dpll;
8997
8998                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8999
9000                 assert_panel_unlocked(dev_priv, pipe);
9001
9002                 dpll = I915_READ(dpll_reg);
9003                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9004                 I915_WRITE(dpll_reg, dpll);
9005                 intel_wait_for_vblank(dev, pipe);
9006                 dpll = I915_READ(dpll_reg);
9007                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9008                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9009         }
9010
9011 }
9012
9013 void intel_mark_busy(struct drm_device *dev)
9014 {
9015         struct drm_i915_private *dev_priv = dev->dev_private;
9016
9017         if (dev_priv->mm.busy)
9018                 return;
9019
9020         intel_runtime_pm_get(dev_priv);
9021         i915_update_gfx_val(dev_priv);
9022         dev_priv->mm.busy = true;
9023 }
9024
9025 void intel_mark_idle(struct drm_device *dev)
9026 {
9027         struct drm_i915_private *dev_priv = dev->dev_private;
9028         struct drm_crtc *crtc;
9029
9030         if (!dev_priv->mm.busy)
9031                 return;
9032
9033         dev_priv->mm.busy = false;
9034
9035         if (!i915.powersave)
9036                 goto out;
9037
9038         for_each_crtc(dev, crtc) {
9039                 if (!crtc->primary->fb)
9040                         continue;
9041
9042                 intel_decrease_pllclock(crtc);
9043         }
9044
9045         if (INTEL_INFO(dev)->gen >= 6)
9046                 gen6_rps_idle(dev->dev_private);
9047
9048 out:
9049         intel_runtime_pm_put(dev_priv);
9050 }
9051
9052 static void intel_crtc_set_state(struct intel_crtc *crtc,
9053                                  struct intel_crtc_state *crtc_state)
9054 {
9055         kfree(crtc->config);
9056         crtc->config = crtc_state;
9057         crtc->base.state = &crtc_state->base;
9058 }
9059
9060 static void intel_crtc_destroy(struct drm_crtc *crtc)
9061 {
9062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9063         struct drm_device *dev = crtc->dev;
9064         struct intel_unpin_work *work;
9065
9066         spin_lock_irq(&dev->event_lock);
9067         work = intel_crtc->unpin_work;
9068         intel_crtc->unpin_work = NULL;
9069         spin_unlock_irq(&dev->event_lock);
9070
9071         if (work) {
9072                 cancel_work_sync(&work->work);
9073                 kfree(work);
9074         }
9075
9076         intel_crtc_set_state(intel_crtc, NULL);
9077         drm_crtc_cleanup(crtc);
9078
9079         kfree(intel_crtc);
9080 }
9081
9082 static void intel_unpin_work_fn(struct work_struct *__work)
9083 {
9084         struct intel_unpin_work *work =
9085                 container_of(__work, struct intel_unpin_work, work);
9086         struct drm_device *dev = work->crtc->dev;
9087         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9088
9089         mutex_lock(&dev->struct_mutex);
9090         intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9091         drm_gem_object_unreference(&work->pending_flip_obj->base);
9092         drm_framebuffer_unreference(work->old_fb);
9093
9094         intel_fbc_update(dev);
9095
9096         if (work->flip_queued_req)
9097                 i915_gem_request_assign(&work->flip_queued_req, NULL);
9098         mutex_unlock(&dev->struct_mutex);
9099
9100         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9101
9102         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9103         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9104
9105         kfree(work);
9106 }
9107
9108 static void do_intel_finish_page_flip(struct drm_device *dev,
9109                                       struct drm_crtc *crtc)
9110 {
9111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9112         struct intel_unpin_work *work;
9113         unsigned long flags;
9114
9115         /* Ignore early vblank irqs */
9116         if (intel_crtc == NULL)
9117                 return;
9118
9119         /*
9120          * This is called both by irq handlers and the reset code (to complete
9121          * lost pageflips) so needs the full irqsave spinlocks.
9122          */
9123         spin_lock_irqsave(&dev->event_lock, flags);
9124         work = intel_crtc->unpin_work;
9125
9126         /* Ensure we don't miss a work->pending update ... */
9127         smp_rmb();
9128
9129         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9130                 spin_unlock_irqrestore(&dev->event_lock, flags);
9131                 return;
9132         }
9133
9134         page_flip_completed(intel_crtc);
9135
9136         spin_unlock_irqrestore(&dev->event_lock, flags);
9137 }
9138
9139 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9140 {
9141         struct drm_i915_private *dev_priv = dev->dev_private;
9142         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9143
9144         do_intel_finish_page_flip(dev, crtc);
9145 }
9146
9147 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9148 {
9149         struct drm_i915_private *dev_priv = dev->dev_private;
9150         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9151
9152         do_intel_finish_page_flip(dev, crtc);
9153 }
9154
9155 /* Is 'a' after or equal to 'b'? */
9156 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9157 {
9158         return !((a - b) & 0x80000000);
9159 }
9160
9161 static bool page_flip_finished(struct intel_crtc *crtc)
9162 {
9163         struct drm_device *dev = crtc->base.dev;
9164         struct drm_i915_private *dev_priv = dev->dev_private;
9165
9166         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9167             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9168                 return true;
9169
9170         /*
9171          * The relevant registers doen't exist on pre-ctg.
9172          * As the flip done interrupt doesn't trigger for mmio
9173          * flips on gmch platforms, a flip count check isn't
9174          * really needed there. But since ctg has the registers,
9175          * include it in the check anyway.
9176          */
9177         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9178                 return true;
9179
9180         /*
9181          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9182          * used the same base address. In that case the mmio flip might
9183          * have completed, but the CS hasn't even executed the flip yet.
9184          *
9185          * A flip count check isn't enough as the CS might have updated
9186          * the base address just after start of vblank, but before we
9187          * managed to process the interrupt. This means we'd complete the
9188          * CS flip too soon.
9189          *
9190          * Combining both checks should get us a good enough result. It may
9191          * still happen that the CS flip has been executed, but has not
9192          * yet actually completed. But in case the base address is the same
9193          * anyway, we don't really care.
9194          */
9195         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9196                 crtc->unpin_work->gtt_offset &&
9197                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9198                                     crtc->unpin_work->flip_count);
9199 }
9200
9201 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9202 {
9203         struct drm_i915_private *dev_priv = dev->dev_private;
9204         struct intel_crtc *intel_crtc =
9205                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9206         unsigned long flags;
9207
9208
9209         /*
9210          * This is called both by irq handlers and the reset code (to complete
9211          * lost pageflips) so needs the full irqsave spinlocks.
9212          *
9213          * NB: An MMIO update of the plane base pointer will also
9214          * generate a page-flip completion irq, i.e. every modeset
9215          * is also accompanied by a spurious intel_prepare_page_flip().
9216          */
9217         spin_lock_irqsave(&dev->event_lock, flags);
9218         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9219                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9220         spin_unlock_irqrestore(&dev->event_lock, flags);
9221 }
9222
9223 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9224 {
9225         /* Ensure that the work item is consistent when activating it ... */
9226         smp_wmb();
9227         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9228         /* and that it is marked active as soon as the irq could fire. */
9229         smp_wmb();
9230 }
9231
9232 static int intel_gen2_queue_flip(struct drm_device *dev,
9233                                  struct drm_crtc *crtc,
9234                                  struct drm_framebuffer *fb,
9235                                  struct drm_i915_gem_object *obj,
9236                                  struct intel_engine_cs *ring,
9237                                  uint32_t flags)
9238 {
9239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9240         u32 flip_mask;
9241         int ret;
9242
9243         ret = intel_ring_begin(ring, 6);
9244         if (ret)
9245                 return ret;
9246
9247         /* Can't queue multiple flips, so wait for the previous
9248          * one to finish before executing the next.
9249          */
9250         if (intel_crtc->plane)
9251                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9252         else
9253                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9254         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9255         intel_ring_emit(ring, MI_NOOP);
9256         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9257                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9258         intel_ring_emit(ring, fb->pitches[0]);
9259         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9260         intel_ring_emit(ring, 0); /* aux display base address, unused */
9261
9262         intel_mark_page_flip_active(intel_crtc);
9263         __intel_ring_advance(ring);
9264         return 0;
9265 }
9266
9267 static int intel_gen3_queue_flip(struct drm_device *dev,
9268                                  struct drm_crtc *crtc,
9269                                  struct drm_framebuffer *fb,
9270                                  struct drm_i915_gem_object *obj,
9271                                  struct intel_engine_cs *ring,
9272                                  uint32_t flags)
9273 {
9274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9275         u32 flip_mask;
9276         int ret;
9277
9278         ret = intel_ring_begin(ring, 6);
9279         if (ret)
9280                 return ret;
9281
9282         if (intel_crtc->plane)
9283                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9284         else
9285                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9286         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9287         intel_ring_emit(ring, MI_NOOP);
9288         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9289                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9290         intel_ring_emit(ring, fb->pitches[0]);
9291         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9292         intel_ring_emit(ring, MI_NOOP);
9293
9294         intel_mark_page_flip_active(intel_crtc);
9295         __intel_ring_advance(ring);
9296         return 0;
9297 }
9298
9299 static int intel_gen4_queue_flip(struct drm_device *dev,
9300                                  struct drm_crtc *crtc,
9301                                  struct drm_framebuffer *fb,
9302                                  struct drm_i915_gem_object *obj,
9303                                  struct intel_engine_cs *ring,
9304                                  uint32_t flags)
9305 {
9306         struct drm_i915_private *dev_priv = dev->dev_private;
9307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9308         uint32_t pf, pipesrc;
9309         int ret;
9310
9311         ret = intel_ring_begin(ring, 4);
9312         if (ret)
9313                 return ret;
9314
9315         /* i965+ uses the linear or tiled offsets from the
9316          * Display Registers (which do not change across a page-flip)
9317          * so we need only reprogram the base address.
9318          */
9319         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9320                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9321         intel_ring_emit(ring, fb->pitches[0]);
9322         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9323                         obj->tiling_mode);
9324
9325         /* XXX Enabling the panel-fitter across page-flip is so far
9326          * untested on non-native modes, so ignore it for now.
9327          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9328          */
9329         pf = 0;
9330         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9331         intel_ring_emit(ring, pf | pipesrc);
9332
9333         intel_mark_page_flip_active(intel_crtc);
9334         __intel_ring_advance(ring);
9335         return 0;
9336 }
9337
9338 static int intel_gen6_queue_flip(struct drm_device *dev,
9339                                  struct drm_crtc *crtc,
9340                                  struct drm_framebuffer *fb,
9341                                  struct drm_i915_gem_object *obj,
9342                                  struct intel_engine_cs *ring,
9343                                  uint32_t flags)
9344 {
9345         struct drm_i915_private *dev_priv = dev->dev_private;
9346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9347         uint32_t pf, pipesrc;
9348         int ret;
9349
9350         ret = intel_ring_begin(ring, 4);
9351         if (ret)
9352                 return ret;
9353
9354         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9355                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9356         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9357         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9358
9359         /* Contrary to the suggestions in the documentation,
9360          * "Enable Panel Fitter" does not seem to be required when page
9361          * flipping with a non-native mode, and worse causes a normal
9362          * modeset to fail.
9363          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9364          */
9365         pf = 0;
9366         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9367         intel_ring_emit(ring, pf | pipesrc);
9368
9369         intel_mark_page_flip_active(intel_crtc);
9370         __intel_ring_advance(ring);
9371         return 0;
9372 }
9373
9374 static int intel_gen7_queue_flip(struct drm_device *dev,
9375                                  struct drm_crtc *crtc,
9376                                  struct drm_framebuffer *fb,
9377                                  struct drm_i915_gem_object *obj,
9378                                  struct intel_engine_cs *ring,
9379                                  uint32_t flags)
9380 {
9381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9382         uint32_t plane_bit = 0;
9383         int len, ret;
9384
9385         switch (intel_crtc->plane) {
9386         case PLANE_A:
9387                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9388                 break;
9389         case PLANE_B:
9390                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9391                 break;
9392         case PLANE_C:
9393                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9394                 break;
9395         default:
9396                 WARN_ONCE(1, "unknown plane in flip command\n");
9397                 return -ENODEV;
9398         }
9399
9400         len = 4;
9401         if (ring->id == RCS) {
9402                 len += 6;
9403                 /*
9404                  * On Gen 8, SRM is now taking an extra dword to accommodate
9405                  * 48bits addresses, and we need a NOOP for the batch size to
9406                  * stay even.
9407                  */
9408                 if (IS_GEN8(dev))
9409                         len += 2;
9410         }
9411
9412         /*
9413          * BSpec MI_DISPLAY_FLIP for IVB:
9414          * "The full packet must be contained within the same cache line."
9415          *
9416          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9417          * cacheline, if we ever start emitting more commands before
9418          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9419          * then do the cacheline alignment, and finally emit the
9420          * MI_DISPLAY_FLIP.
9421          */
9422         ret = intel_ring_cacheline_align(ring);
9423         if (ret)
9424                 return ret;
9425
9426         ret = intel_ring_begin(ring, len);
9427         if (ret)
9428                 return ret;
9429
9430         /* Unmask the flip-done completion message. Note that the bspec says that
9431          * we should do this for both the BCS and RCS, and that we must not unmask
9432          * more than one flip event at any time (or ensure that one flip message
9433          * can be sent by waiting for flip-done prior to queueing new flips).
9434          * Experimentation says that BCS works despite DERRMR masking all
9435          * flip-done completion events and that unmasking all planes at once
9436          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9437          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9438          */
9439         if (ring->id == RCS) {
9440                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9441                 intel_ring_emit(ring, DERRMR);
9442                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9443                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9444                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9445                 if (IS_GEN8(dev))
9446                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9447                                               MI_SRM_LRM_GLOBAL_GTT);
9448                 else
9449                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9450                                               MI_SRM_LRM_GLOBAL_GTT);
9451                 intel_ring_emit(ring, DERRMR);
9452                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9453                 if (IS_GEN8(dev)) {
9454                         intel_ring_emit(ring, 0);
9455                         intel_ring_emit(ring, MI_NOOP);
9456                 }
9457         }
9458
9459         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9460         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9461         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9462         intel_ring_emit(ring, (MI_NOOP));
9463
9464         intel_mark_page_flip_active(intel_crtc);
9465         __intel_ring_advance(ring);
9466         return 0;
9467 }
9468
9469 static bool use_mmio_flip(struct intel_engine_cs *ring,
9470                           struct drm_i915_gem_object *obj)
9471 {
9472         /*
9473          * This is not being used for older platforms, because
9474          * non-availability of flip done interrupt forces us to use
9475          * CS flips. Older platforms derive flip done using some clever
9476          * tricks involving the flip_pending status bits and vblank irqs.
9477          * So using MMIO flips there would disrupt this mechanism.
9478          */
9479
9480         if (ring == NULL)
9481                 return true;
9482
9483         if (INTEL_INFO(ring->dev)->gen < 5)
9484                 return false;
9485
9486         if (i915.use_mmio_flip < 0)
9487                 return false;
9488         else if (i915.use_mmio_flip > 0)
9489                 return true;
9490         else if (i915.enable_execlists)
9491                 return true;
9492         else
9493                 return ring != i915_gem_request_get_ring(obj->last_read_req);
9494 }
9495
9496 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9497 {
9498         struct drm_device *dev = intel_crtc->base.dev;
9499         struct drm_i915_private *dev_priv = dev->dev_private;
9500         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9501         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9502         struct drm_i915_gem_object *obj = intel_fb->obj;
9503         const enum pipe pipe = intel_crtc->pipe;
9504         u32 ctl, stride;
9505
9506         ctl = I915_READ(PLANE_CTL(pipe, 0));
9507         ctl &= ~PLANE_CTL_TILED_MASK;
9508         if (obj->tiling_mode == I915_TILING_X)
9509                 ctl |= PLANE_CTL_TILED_X;
9510
9511         /*
9512          * The stride is either expressed as a multiple of 64 bytes chunks for
9513          * linear buffers or in number of tiles for tiled buffers.
9514          */
9515         stride = fb->pitches[0] >> 6;
9516         if (obj->tiling_mode == I915_TILING_X)
9517                 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9518
9519         /*
9520          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9521          * PLANE_SURF updates, the update is then guaranteed to be atomic.
9522          */
9523         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9524         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9525
9526         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9527         POSTING_READ(PLANE_SURF(pipe, 0));
9528 }
9529
9530 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9531 {
9532         struct drm_device *dev = intel_crtc->base.dev;
9533         struct drm_i915_private *dev_priv = dev->dev_private;
9534         struct intel_framebuffer *intel_fb =
9535                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9536         struct drm_i915_gem_object *obj = intel_fb->obj;
9537         u32 dspcntr;
9538         u32 reg;
9539
9540         reg = DSPCNTR(intel_crtc->plane);
9541         dspcntr = I915_READ(reg);
9542
9543         if (obj->tiling_mode != I915_TILING_NONE)
9544                 dspcntr |= DISPPLANE_TILED;
9545         else
9546                 dspcntr &= ~DISPPLANE_TILED;
9547
9548         I915_WRITE(reg, dspcntr);
9549
9550         I915_WRITE(DSPSURF(intel_crtc->plane),
9551                    intel_crtc->unpin_work->gtt_offset);
9552         POSTING_READ(DSPSURF(intel_crtc->plane));
9553
9554 }
9555
9556 /*
9557  * XXX: This is the temporary way to update the plane registers until we get
9558  * around to using the usual plane update functions for MMIO flips
9559  */
9560 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9561 {
9562         struct drm_device *dev = intel_crtc->base.dev;
9563         bool atomic_update;
9564         u32 start_vbl_count;
9565
9566         intel_mark_page_flip_active(intel_crtc);
9567
9568         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9569
9570         if (INTEL_INFO(dev)->gen >= 9)
9571                 skl_do_mmio_flip(intel_crtc);
9572         else
9573                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9574                 ilk_do_mmio_flip(intel_crtc);
9575
9576         if (atomic_update)
9577                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9578 }
9579
9580 static void intel_mmio_flip_work_func(struct work_struct *work)
9581 {
9582         struct intel_crtc *crtc =
9583                 container_of(work, struct intel_crtc, mmio_flip.work);
9584         struct intel_mmio_flip *mmio_flip;
9585
9586         mmio_flip = &crtc->mmio_flip;
9587         if (mmio_flip->req)
9588                 WARN_ON(__i915_wait_request(mmio_flip->req,
9589                                             crtc->reset_counter,
9590                                             false, NULL, NULL) != 0);
9591
9592         intel_do_mmio_flip(crtc);
9593         if (mmio_flip->req) {
9594                 mutex_lock(&crtc->base.dev->struct_mutex);
9595                 i915_gem_request_assign(&mmio_flip->req, NULL);
9596                 mutex_unlock(&crtc->base.dev->struct_mutex);
9597         }
9598 }
9599
9600 static int intel_queue_mmio_flip(struct drm_device *dev,
9601                                  struct drm_crtc *crtc,
9602                                  struct drm_framebuffer *fb,
9603                                  struct drm_i915_gem_object *obj,
9604                                  struct intel_engine_cs *ring,
9605                                  uint32_t flags)
9606 {
9607         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9608
9609         i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9610                                 obj->last_write_req);
9611
9612         schedule_work(&intel_crtc->mmio_flip.work);
9613
9614         return 0;
9615 }
9616
9617 static int intel_gen9_queue_flip(struct drm_device *dev,
9618                                  struct drm_crtc *crtc,
9619                                  struct drm_framebuffer *fb,
9620                                  struct drm_i915_gem_object *obj,
9621                                  struct intel_engine_cs *ring,
9622                                  uint32_t flags)
9623 {
9624         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9625         uint32_t plane = 0, stride;
9626         int ret;
9627
9628         switch(intel_crtc->pipe) {
9629         case PIPE_A:
9630                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9631                 break;
9632         case PIPE_B:
9633                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9634                 break;
9635         case PIPE_C:
9636                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9637                 break;
9638         default:
9639                 WARN_ONCE(1, "unknown plane in flip command\n");
9640                 return -ENODEV;
9641         }
9642
9643         switch (obj->tiling_mode) {
9644         case I915_TILING_NONE:
9645                 stride = fb->pitches[0] >> 6;
9646                 break;
9647         case I915_TILING_X:
9648                 stride = fb->pitches[0] >> 9;
9649                 break;
9650         default:
9651                 WARN_ONCE(1, "unknown tiling in flip command\n");
9652                 return -ENODEV;
9653         }
9654
9655         ret = intel_ring_begin(ring, 10);
9656         if (ret)
9657                 return ret;
9658
9659         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9660         intel_ring_emit(ring, DERRMR);
9661         intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9662                                 DERRMR_PIPEB_PRI_FLIP_DONE |
9663                                 DERRMR_PIPEC_PRI_FLIP_DONE));
9664         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9665                               MI_SRM_LRM_GLOBAL_GTT);
9666         intel_ring_emit(ring, DERRMR);
9667         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9668         intel_ring_emit(ring, 0);
9669
9670         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9671         intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9672         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9673
9674         intel_mark_page_flip_active(intel_crtc);
9675         __intel_ring_advance(ring);
9676
9677         return 0;
9678 }
9679
9680 static int intel_default_queue_flip(struct drm_device *dev,
9681                                     struct drm_crtc *crtc,
9682                                     struct drm_framebuffer *fb,
9683                                     struct drm_i915_gem_object *obj,
9684                                     struct intel_engine_cs *ring,
9685                                     uint32_t flags)
9686 {
9687         return -ENODEV;
9688 }
9689
9690 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9691                                          struct drm_crtc *crtc)
9692 {
9693         struct drm_i915_private *dev_priv = dev->dev_private;
9694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9695         struct intel_unpin_work *work = intel_crtc->unpin_work;
9696         u32 addr;
9697
9698         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9699                 return true;
9700
9701         if (!work->enable_stall_check)
9702                 return false;
9703
9704         if (work->flip_ready_vblank == 0) {
9705                 if (work->flip_queued_req &&
9706                     !i915_gem_request_completed(work->flip_queued_req, true))
9707                         return false;
9708
9709                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9710         }
9711
9712         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9713                 return false;
9714
9715         /* Potential stall - if we see that the flip has happened,
9716          * assume a missed interrupt. */
9717         if (INTEL_INFO(dev)->gen >= 4)
9718                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9719         else
9720                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9721
9722         /* There is a potential issue here with a false positive after a flip
9723          * to the same address. We could address this by checking for a
9724          * non-incrementing frame counter.
9725          */
9726         return addr == work->gtt_offset;
9727 }
9728
9729 void intel_check_page_flip(struct drm_device *dev, int pipe)
9730 {
9731         struct drm_i915_private *dev_priv = dev->dev_private;
9732         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9734
9735         WARN_ON(!in_irq());
9736
9737         if (crtc == NULL)
9738                 return;
9739
9740         spin_lock(&dev->event_lock);
9741         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9742                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9743                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9744                 page_flip_completed(intel_crtc);
9745         }
9746         spin_unlock(&dev->event_lock);
9747 }
9748
9749 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9750                                 struct drm_framebuffer *fb,
9751                                 struct drm_pending_vblank_event *event,
9752                                 uint32_t page_flip_flags)
9753 {
9754         struct drm_device *dev = crtc->dev;
9755         struct drm_i915_private *dev_priv = dev->dev_private;
9756         struct drm_framebuffer *old_fb = crtc->primary->fb;
9757         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9759         struct drm_plane *primary = crtc->primary;
9760         enum pipe pipe = intel_crtc->pipe;
9761         struct intel_unpin_work *work;
9762         struct intel_engine_cs *ring;
9763         int ret;
9764
9765         /*
9766          * drm_mode_page_flip_ioctl() should already catch this, but double
9767          * check to be safe.  In the future we may enable pageflipping from
9768          * a disabled primary plane.
9769          */
9770         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9771                 return -EBUSY;
9772
9773         /* Can't change pixel format via MI display flips. */
9774         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9775                 return -EINVAL;
9776
9777         /*
9778          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9779          * Note that pitch changes could also affect these register.
9780          */
9781         if (INTEL_INFO(dev)->gen > 3 &&
9782             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9783              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9784                 return -EINVAL;
9785
9786         if (i915_terminally_wedged(&dev_priv->gpu_error))
9787                 goto out_hang;
9788
9789         work = kzalloc(sizeof(*work), GFP_KERNEL);
9790         if (work == NULL)
9791                 return -ENOMEM;
9792
9793         work->event = event;
9794         work->crtc = crtc;
9795         work->old_fb = old_fb;
9796         INIT_WORK(&work->work, intel_unpin_work_fn);
9797
9798         ret = drm_crtc_vblank_get(crtc);
9799         if (ret)
9800                 goto free_work;
9801
9802         /* We borrow the event spin lock for protecting unpin_work */
9803         spin_lock_irq(&dev->event_lock);
9804         if (intel_crtc->unpin_work) {
9805                 /* Before declaring the flip queue wedged, check if
9806                  * the hardware completed the operation behind our backs.
9807                  */
9808                 if (__intel_pageflip_stall_check(dev, crtc)) {
9809                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9810                         page_flip_completed(intel_crtc);
9811                 } else {
9812                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9813                         spin_unlock_irq(&dev->event_lock);
9814
9815                         drm_crtc_vblank_put(crtc);
9816                         kfree(work);
9817                         return -EBUSY;
9818                 }
9819         }
9820         intel_crtc->unpin_work = work;
9821         spin_unlock_irq(&dev->event_lock);
9822
9823         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9824                 flush_workqueue(dev_priv->wq);
9825
9826         ret = i915_mutex_lock_interruptible(dev);
9827         if (ret)
9828                 goto cleanup;
9829
9830         /* Reference the objects for the scheduled work. */
9831         drm_framebuffer_reference(work->old_fb);
9832         drm_gem_object_reference(&obj->base);
9833
9834         crtc->primary->fb = fb;
9835         update_state_fb(crtc->primary);
9836
9837         work->pending_flip_obj = obj;
9838
9839         atomic_inc(&intel_crtc->unpin_work_count);
9840         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9841
9842         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9843                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9844
9845         if (IS_VALLEYVIEW(dev)) {
9846                 ring = &dev_priv->ring[BCS];
9847                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9848                         /* vlv: DISPLAY_FLIP fails to change tiling */
9849                         ring = NULL;
9850         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9851                 ring = &dev_priv->ring[BCS];
9852         } else if (INTEL_INFO(dev)->gen >= 7) {
9853                 ring = i915_gem_request_get_ring(obj->last_read_req);
9854                 if (ring == NULL || ring->id != RCS)
9855                         ring = &dev_priv->ring[BCS];
9856         } else {
9857                 ring = &dev_priv->ring[RCS];
9858         }
9859
9860         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9861         if (ret)
9862                 goto cleanup_pending;
9863
9864         work->gtt_offset =
9865                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9866
9867         if (use_mmio_flip(ring, obj)) {
9868                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9869                                             page_flip_flags);
9870                 if (ret)
9871                         goto cleanup_unpin;
9872
9873                 i915_gem_request_assign(&work->flip_queued_req,
9874                                         obj->last_write_req);
9875         } else {
9876                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9877                                                    page_flip_flags);
9878                 if (ret)
9879                         goto cleanup_unpin;
9880
9881                 i915_gem_request_assign(&work->flip_queued_req,
9882                                         intel_ring_get_request(ring));
9883         }
9884
9885         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9886         work->enable_stall_check = true;
9887
9888         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9889                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9890
9891         intel_fbc_disable(dev);
9892         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9893         mutex_unlock(&dev->struct_mutex);
9894
9895         trace_i915_flip_request(intel_crtc->plane, obj);
9896
9897         return 0;
9898
9899 cleanup_unpin:
9900         intel_unpin_fb_obj(obj);
9901 cleanup_pending:
9902         atomic_dec(&intel_crtc->unpin_work_count);
9903         crtc->primary->fb = old_fb;
9904         update_state_fb(crtc->primary);
9905         drm_framebuffer_unreference(work->old_fb);
9906         drm_gem_object_unreference(&obj->base);
9907         mutex_unlock(&dev->struct_mutex);
9908
9909 cleanup:
9910         spin_lock_irq(&dev->event_lock);
9911         intel_crtc->unpin_work = NULL;
9912         spin_unlock_irq(&dev->event_lock);
9913
9914         drm_crtc_vblank_put(crtc);
9915 free_work:
9916         kfree(work);
9917
9918         if (ret == -EIO) {
9919 out_hang:
9920                 ret = intel_plane_restore(primary);
9921                 if (ret == 0 && event) {
9922                         spin_lock_irq(&dev->event_lock);
9923                         drm_send_vblank_event(dev, pipe, event);
9924                         spin_unlock_irq(&dev->event_lock);
9925                 }
9926         }
9927         return ret;
9928 }
9929
9930 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9931         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9932         .load_lut = intel_crtc_load_lut,
9933         .atomic_begin = intel_begin_crtc_commit,
9934         .atomic_flush = intel_finish_crtc_commit,
9935 };
9936
9937 /**
9938  * intel_modeset_update_staged_output_state
9939  *
9940  * Updates the staged output configuration state, e.g. after we've read out the
9941  * current hw state.
9942  */
9943 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9944 {
9945         struct intel_crtc *crtc;
9946         struct intel_encoder *encoder;
9947         struct intel_connector *connector;
9948
9949         list_for_each_entry(connector, &dev->mode_config.connector_list,
9950                             base.head) {
9951                 connector->new_encoder =
9952                         to_intel_encoder(connector->base.encoder);
9953         }
9954
9955         for_each_intel_encoder(dev, encoder) {
9956                 encoder->new_crtc =
9957                         to_intel_crtc(encoder->base.crtc);
9958         }
9959
9960         for_each_intel_crtc(dev, crtc) {
9961                 crtc->new_enabled = crtc->base.enabled;
9962
9963                 if (crtc->new_enabled)
9964                         crtc->new_config = crtc->config;
9965                 else
9966                         crtc->new_config = NULL;
9967         }
9968 }
9969
9970 /**
9971  * intel_modeset_commit_output_state
9972  *
9973  * This function copies the stage display pipe configuration to the real one.
9974  */
9975 static void intel_modeset_commit_output_state(struct drm_device *dev)
9976 {
9977         struct intel_crtc *crtc;
9978         struct intel_encoder *encoder;
9979         struct intel_connector *connector;
9980
9981         list_for_each_entry(connector, &dev->mode_config.connector_list,
9982                             base.head) {
9983                 connector->base.encoder = &connector->new_encoder->base;
9984         }
9985
9986         for_each_intel_encoder(dev, encoder) {
9987                 encoder->base.crtc = &encoder->new_crtc->base;
9988         }
9989
9990         for_each_intel_crtc(dev, crtc) {
9991                 crtc->base.enabled = crtc->new_enabled;
9992         }
9993 }
9994
9995 static void
9996 connected_sink_compute_bpp(struct intel_connector *connector,
9997                            struct intel_crtc_state *pipe_config)
9998 {
9999         int bpp = pipe_config->pipe_bpp;
10000
10001         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10002                 connector->base.base.id,
10003                 connector->base.name);
10004
10005         /* Don't use an invalid EDID bpc value */
10006         if (connector->base.display_info.bpc &&
10007             connector->base.display_info.bpc * 3 < bpp) {
10008                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10009                               bpp, connector->base.display_info.bpc*3);
10010                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10011         }
10012
10013         /* Clamp bpp to 8 on screens without EDID 1.4 */
10014         if (connector->base.display_info.bpc == 0 && bpp > 24) {
10015                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10016                               bpp);
10017                 pipe_config->pipe_bpp = 24;
10018         }
10019 }
10020
10021 static int
10022 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10023                           struct drm_framebuffer *fb,
10024                           struct intel_crtc_state *pipe_config)
10025 {
10026         struct drm_device *dev = crtc->base.dev;
10027         struct intel_connector *connector;
10028         int bpp;
10029
10030         switch (fb->pixel_format) {
10031         case DRM_FORMAT_C8:
10032                 bpp = 8*3; /* since we go through a colormap */
10033                 break;
10034         case DRM_FORMAT_XRGB1555:
10035         case DRM_FORMAT_ARGB1555:
10036                 /* checked in intel_framebuffer_init already */
10037                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10038                         return -EINVAL;
10039         case DRM_FORMAT_RGB565:
10040                 bpp = 6*3; /* min is 18bpp */
10041                 break;
10042         case DRM_FORMAT_XBGR8888:
10043         case DRM_FORMAT_ABGR8888:
10044                 /* checked in intel_framebuffer_init already */
10045                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10046                         return -EINVAL;
10047         case DRM_FORMAT_XRGB8888:
10048         case DRM_FORMAT_ARGB8888:
10049                 bpp = 8*3;
10050                 break;
10051         case DRM_FORMAT_XRGB2101010:
10052         case DRM_FORMAT_ARGB2101010:
10053         case DRM_FORMAT_XBGR2101010:
10054         case DRM_FORMAT_ABGR2101010:
10055                 /* checked in intel_framebuffer_init already */
10056                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10057                         return -EINVAL;
10058                 bpp = 10*3;
10059                 break;
10060         /* TODO: gen4+ supports 16 bpc floating point, too. */
10061         default:
10062                 DRM_DEBUG_KMS("unsupported depth\n");
10063                 return -EINVAL;
10064         }
10065
10066         pipe_config->pipe_bpp = bpp;
10067
10068         /* Clamp display bpp to EDID value */
10069         list_for_each_entry(connector, &dev->mode_config.connector_list,
10070                             base.head) {
10071                 if (!connector->new_encoder ||
10072                     connector->new_encoder->new_crtc != crtc)
10073                         continue;
10074
10075                 connected_sink_compute_bpp(connector, pipe_config);
10076         }
10077
10078         return bpp;
10079 }
10080
10081 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10082 {
10083         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10084                         "type: 0x%x flags: 0x%x\n",
10085                 mode->crtc_clock,
10086                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10087                 mode->crtc_hsync_end, mode->crtc_htotal,
10088                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10089                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10090 }
10091
10092 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10093                                    struct intel_crtc_state *pipe_config,
10094                                    const char *context)
10095 {
10096         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10097                       context, pipe_name(crtc->pipe));
10098
10099         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10100         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10101                       pipe_config->pipe_bpp, pipe_config->dither);
10102         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10103                       pipe_config->has_pch_encoder,
10104                       pipe_config->fdi_lanes,
10105                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10106                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10107                       pipe_config->fdi_m_n.tu);
10108         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10109                       pipe_config->has_dp_encoder,
10110                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10111                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10112                       pipe_config->dp_m_n.tu);
10113
10114         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10115                       pipe_config->has_dp_encoder,
10116                       pipe_config->dp_m2_n2.gmch_m,
10117                       pipe_config->dp_m2_n2.gmch_n,
10118                       pipe_config->dp_m2_n2.link_m,
10119                       pipe_config->dp_m2_n2.link_n,
10120                       pipe_config->dp_m2_n2.tu);
10121
10122         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10123                       pipe_config->has_audio,
10124                       pipe_config->has_infoframe);
10125
10126         DRM_DEBUG_KMS("requested mode:\n");
10127         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10128         DRM_DEBUG_KMS("adjusted mode:\n");
10129         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10130         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10131         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10132         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10133                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10134         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10135                       pipe_config->gmch_pfit.control,
10136                       pipe_config->gmch_pfit.pgm_ratios,
10137                       pipe_config->gmch_pfit.lvds_border_bits);
10138         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10139                       pipe_config->pch_pfit.pos,
10140                       pipe_config->pch_pfit.size,
10141                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10142         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10143         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10144 }
10145
10146 static bool encoders_cloneable(const struct intel_encoder *a,
10147                                const struct intel_encoder *b)
10148 {
10149         /* masks could be asymmetric, so check both ways */
10150         return a == b || (a->cloneable & (1 << b->type) &&
10151                           b->cloneable & (1 << a->type));
10152 }
10153
10154 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10155                                          struct intel_encoder *encoder)
10156 {
10157         struct drm_device *dev = crtc->base.dev;
10158         struct intel_encoder *source_encoder;
10159
10160         for_each_intel_encoder(dev, source_encoder) {
10161                 if (source_encoder->new_crtc != crtc)
10162                         continue;
10163
10164                 if (!encoders_cloneable(encoder, source_encoder))
10165                         return false;
10166         }
10167
10168         return true;
10169 }
10170
10171 static bool check_encoder_cloning(struct intel_crtc *crtc)
10172 {
10173         struct drm_device *dev = crtc->base.dev;
10174         struct intel_encoder *encoder;
10175
10176         for_each_intel_encoder(dev, encoder) {
10177                 if (encoder->new_crtc != crtc)
10178                         continue;
10179
10180                 if (!check_single_encoder_cloning(crtc, encoder))
10181                         return false;
10182         }
10183
10184         return true;
10185 }
10186
10187 static bool check_digital_port_conflicts(struct drm_device *dev)
10188 {
10189         struct intel_connector *connector;
10190         unsigned int used_ports = 0;
10191
10192         /*
10193          * Walk the connector list instead of the encoder
10194          * list to detect the problem on ddi platforms
10195          * where there's just one encoder per digital port.
10196          */
10197         list_for_each_entry(connector,
10198                             &dev->mode_config.connector_list, base.head) {
10199                 struct intel_encoder *encoder = connector->new_encoder;
10200
10201                 if (!encoder)
10202                         continue;
10203
10204                 WARN_ON(!encoder->new_crtc);
10205
10206                 switch (encoder->type) {
10207                         unsigned int port_mask;
10208                 case INTEL_OUTPUT_UNKNOWN:
10209                         if (WARN_ON(!HAS_DDI(dev)))
10210                                 break;
10211                 case INTEL_OUTPUT_DISPLAYPORT:
10212                 case INTEL_OUTPUT_HDMI:
10213                 case INTEL_OUTPUT_EDP:
10214                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10215
10216                         /* the same port mustn't appear more than once */
10217                         if (used_ports & port_mask)
10218                                 return false;
10219
10220                         used_ports |= port_mask;
10221                 default:
10222                         break;
10223                 }
10224         }
10225
10226         return true;
10227 }
10228
10229 static struct intel_crtc_state *
10230 intel_modeset_pipe_config(struct drm_crtc *crtc,
10231                           struct drm_framebuffer *fb,
10232                           struct drm_display_mode *mode)
10233 {
10234         struct drm_device *dev = crtc->dev;
10235         struct intel_encoder *encoder;
10236         struct intel_crtc_state *pipe_config;
10237         int plane_bpp, ret = -EINVAL;
10238         bool retry = true;
10239
10240         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10241                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10242                 return ERR_PTR(-EINVAL);
10243         }
10244
10245         if (!check_digital_port_conflicts(dev)) {
10246                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10247                 return ERR_PTR(-EINVAL);
10248         }
10249
10250         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10251         if (!pipe_config)
10252                 return ERR_PTR(-ENOMEM);
10253
10254         drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10255         drm_mode_copy(&pipe_config->base.mode, mode);
10256
10257         pipe_config->cpu_transcoder =
10258                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10259         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10260
10261         /*
10262          * Sanitize sync polarity flags based on requested ones. If neither
10263          * positive or negative polarity is requested, treat this as meaning
10264          * negative polarity.
10265          */
10266         if (!(pipe_config->base.adjusted_mode.flags &
10267               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10268                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10269
10270         if (!(pipe_config->base.adjusted_mode.flags &
10271               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10272                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10273
10274         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10275          * plane pixel format and any sink constraints into account. Returns the
10276          * source plane bpp so that dithering can be selected on mismatches
10277          * after encoders and crtc also have had their say. */
10278         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10279                                               fb, pipe_config);
10280         if (plane_bpp < 0)
10281                 goto fail;
10282
10283         /*
10284          * Determine the real pipe dimensions. Note that stereo modes can
10285          * increase the actual pipe size due to the frame doubling and
10286          * insertion of additional space for blanks between the frame. This
10287          * is stored in the crtc timings. We use the requested mode to do this
10288          * computation to clearly distinguish it from the adjusted mode, which
10289          * can be changed by the connectors in the below retry loop.
10290          */
10291         drm_crtc_get_hv_timing(&pipe_config->base.mode,
10292                                &pipe_config->pipe_src_w,
10293                                &pipe_config->pipe_src_h);
10294
10295 encoder_retry:
10296         /* Ensure the port clock defaults are reset when retrying. */
10297         pipe_config->port_clock = 0;
10298         pipe_config->pixel_multiplier = 1;
10299
10300         /* Fill in default crtc timings, allow encoders to overwrite them. */
10301         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10302                               CRTC_STEREO_DOUBLE);
10303
10304         /* Pass our mode to the connectors and the CRTC to give them a chance to
10305          * adjust it according to limitations or connector properties, and also
10306          * a chance to reject the mode entirely.
10307          */
10308         for_each_intel_encoder(dev, encoder) {
10309
10310                 if (&encoder->new_crtc->base != crtc)
10311                         continue;
10312
10313                 if (!(encoder->compute_config(encoder, pipe_config))) {
10314                         DRM_DEBUG_KMS("Encoder config failure\n");
10315                         goto fail;
10316                 }
10317         }
10318
10319         /* Set default port clock if not overwritten by the encoder. Needs to be
10320          * done afterwards in case the encoder adjusts the mode. */
10321         if (!pipe_config->port_clock)
10322                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10323                         * pipe_config->pixel_multiplier;
10324
10325         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10326         if (ret < 0) {
10327                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10328                 goto fail;
10329         }
10330
10331         if (ret == RETRY) {
10332                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10333                         ret = -EINVAL;
10334                         goto fail;
10335                 }
10336
10337                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10338                 retry = false;
10339                 goto encoder_retry;
10340         }
10341
10342         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10343         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10344                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10345
10346         return pipe_config;
10347 fail:
10348         kfree(pipe_config);
10349         return ERR_PTR(ret);
10350 }
10351
10352 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10353  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10354 static void
10355 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10356                              unsigned *prepare_pipes, unsigned *disable_pipes)
10357 {
10358         struct intel_crtc *intel_crtc;
10359         struct drm_device *dev = crtc->dev;
10360         struct intel_encoder *encoder;
10361         struct intel_connector *connector;
10362         struct drm_crtc *tmp_crtc;
10363
10364         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10365
10366         /* Check which crtcs have changed outputs connected to them, these need
10367          * to be part of the prepare_pipes mask. We don't (yet) support global
10368          * modeset across multiple crtcs, so modeset_pipes will only have one
10369          * bit set at most. */
10370         list_for_each_entry(connector, &dev->mode_config.connector_list,
10371                             base.head) {
10372                 if (connector->base.encoder == &connector->new_encoder->base)
10373                         continue;
10374
10375                 if (connector->base.encoder) {
10376                         tmp_crtc = connector->base.encoder->crtc;
10377
10378                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10379                 }
10380
10381                 if (connector->new_encoder)
10382                         *prepare_pipes |=
10383                                 1 << connector->new_encoder->new_crtc->pipe;
10384         }
10385
10386         for_each_intel_encoder(dev, encoder) {
10387                 if (encoder->base.crtc == &encoder->new_crtc->base)
10388                         continue;
10389
10390                 if (encoder->base.crtc) {
10391                         tmp_crtc = encoder->base.crtc;
10392
10393                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10394                 }
10395
10396                 if (encoder->new_crtc)
10397                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10398         }
10399
10400         /* Check for pipes that will be enabled/disabled ... */
10401         for_each_intel_crtc(dev, intel_crtc) {
10402                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10403                         continue;
10404
10405                 if (!intel_crtc->new_enabled)
10406                         *disable_pipes |= 1 << intel_crtc->pipe;
10407                 else
10408                         *prepare_pipes |= 1 << intel_crtc->pipe;
10409         }
10410
10411
10412         /* set_mode is also used to update properties on life display pipes. */
10413         intel_crtc = to_intel_crtc(crtc);
10414         if (intel_crtc->new_enabled)
10415                 *prepare_pipes |= 1 << intel_crtc->pipe;
10416
10417         /*
10418          * For simplicity do a full modeset on any pipe where the output routing
10419          * changed. We could be more clever, but that would require us to be
10420          * more careful with calling the relevant encoder->mode_set functions.
10421          */
10422         if (*prepare_pipes)
10423                 *modeset_pipes = *prepare_pipes;
10424
10425         /* ... and mask these out. */
10426         *modeset_pipes &= ~(*disable_pipes);
10427         *prepare_pipes &= ~(*disable_pipes);
10428
10429         /*
10430          * HACK: We don't (yet) fully support global modesets. intel_set_config
10431          * obies this rule, but the modeset restore mode of
10432          * intel_modeset_setup_hw_state does not.
10433          */
10434         *modeset_pipes &= 1 << intel_crtc->pipe;
10435         *prepare_pipes &= 1 << intel_crtc->pipe;
10436
10437         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10438                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10439 }
10440
10441 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10442 {
10443         struct drm_encoder *encoder;
10444         struct drm_device *dev = crtc->dev;
10445
10446         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10447                 if (encoder->crtc == crtc)
10448                         return true;
10449
10450         return false;
10451 }
10452
10453 static void
10454 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10455 {
10456         struct drm_i915_private *dev_priv = dev->dev_private;
10457         struct intel_encoder *intel_encoder;
10458         struct intel_crtc *intel_crtc;
10459         struct drm_connector *connector;
10460
10461         intel_shared_dpll_commit(dev_priv);
10462
10463         for_each_intel_encoder(dev, intel_encoder) {
10464                 if (!intel_encoder->base.crtc)
10465                         continue;
10466
10467                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10468
10469                 if (prepare_pipes & (1 << intel_crtc->pipe))
10470                         intel_encoder->connectors_active = false;
10471         }
10472
10473         intel_modeset_commit_output_state(dev);
10474
10475         /* Double check state. */
10476         for_each_intel_crtc(dev, intel_crtc) {
10477                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10478                 WARN_ON(intel_crtc->new_config &&
10479                         intel_crtc->new_config != intel_crtc->config);
10480                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10481         }
10482
10483         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10484                 if (!connector->encoder || !connector->encoder->crtc)
10485                         continue;
10486
10487                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10488
10489                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10490                         struct drm_property *dpms_property =
10491                                 dev->mode_config.dpms_property;
10492
10493                         connector->dpms = DRM_MODE_DPMS_ON;
10494                         drm_object_property_set_value(&connector->base,
10495                                                          dpms_property,
10496                                                          DRM_MODE_DPMS_ON);
10497
10498                         intel_encoder = to_intel_encoder(connector->encoder);
10499                         intel_encoder->connectors_active = true;
10500                 }
10501         }
10502
10503 }
10504
10505 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10506 {
10507         int diff;
10508
10509         if (clock1 == clock2)
10510                 return true;
10511
10512         if (!clock1 || !clock2)
10513                 return false;
10514
10515         diff = abs(clock1 - clock2);
10516
10517         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10518                 return true;
10519
10520         return false;
10521 }
10522
10523 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10524         list_for_each_entry((intel_crtc), \
10525                             &(dev)->mode_config.crtc_list, \
10526                             base.head) \
10527                 if (mask & (1 <<(intel_crtc)->pipe))
10528
10529 static bool
10530 intel_pipe_config_compare(struct drm_device *dev,
10531                           struct intel_crtc_state *current_config,
10532                           struct intel_crtc_state *pipe_config)
10533 {
10534 #define PIPE_CONF_CHECK_X(name) \
10535         if (current_config->name != pipe_config->name) { \
10536                 DRM_ERROR("mismatch in " #name " " \
10537                           "(expected 0x%08x, found 0x%08x)\n", \
10538                           current_config->name, \
10539                           pipe_config->name); \
10540                 return false; \
10541         }
10542
10543 #define PIPE_CONF_CHECK_I(name) \
10544         if (current_config->name != pipe_config->name) { \
10545                 DRM_ERROR("mismatch in " #name " " \
10546                           "(expected %i, found %i)\n", \
10547                           current_config->name, \
10548                           pipe_config->name); \
10549                 return false; \
10550         }
10551
10552 /* This is required for BDW+ where there is only one set of registers for
10553  * switching between high and low RR.
10554  * This macro can be used whenever a comparison has to be made between one
10555  * hw state and multiple sw state variables.
10556  */
10557 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10558         if ((current_config->name != pipe_config->name) && \
10559                 (current_config->alt_name != pipe_config->name)) { \
10560                         DRM_ERROR("mismatch in " #name " " \
10561                                   "(expected %i or %i, found %i)\n", \
10562                                   current_config->name, \
10563                                   current_config->alt_name, \
10564                                   pipe_config->name); \
10565                         return false; \
10566         }
10567
10568 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10569         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10570                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10571                           "(expected %i, found %i)\n", \
10572                           current_config->name & (mask), \
10573                           pipe_config->name & (mask)); \
10574                 return false; \
10575         }
10576
10577 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10578         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10579                 DRM_ERROR("mismatch in " #name " " \
10580                           "(expected %i, found %i)\n", \
10581                           current_config->name, \
10582                           pipe_config->name); \
10583                 return false; \
10584         }
10585
10586 #define PIPE_CONF_QUIRK(quirk)  \
10587         ((current_config->quirks | pipe_config->quirks) & (quirk))
10588
10589         PIPE_CONF_CHECK_I(cpu_transcoder);
10590
10591         PIPE_CONF_CHECK_I(has_pch_encoder);
10592         PIPE_CONF_CHECK_I(fdi_lanes);
10593         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10594         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10595         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10596         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10597         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10598
10599         PIPE_CONF_CHECK_I(has_dp_encoder);
10600
10601         if (INTEL_INFO(dev)->gen < 8) {
10602                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10603                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10604                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10605                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10606                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10607
10608                 if (current_config->has_drrs) {
10609                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10610                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10611                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10612                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10613                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10614                 }
10615         } else {
10616                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10617                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10618                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10619                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10620                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10621         }
10622
10623         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10624         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10625         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10626         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10627         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10628         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10629
10630         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10631         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10632         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10633         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10634         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10635         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10636
10637         PIPE_CONF_CHECK_I(pixel_multiplier);
10638         PIPE_CONF_CHECK_I(has_hdmi_sink);
10639         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10640             IS_VALLEYVIEW(dev))
10641                 PIPE_CONF_CHECK_I(limited_color_range);
10642         PIPE_CONF_CHECK_I(has_infoframe);
10643
10644         PIPE_CONF_CHECK_I(has_audio);
10645
10646         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10647                               DRM_MODE_FLAG_INTERLACE);
10648
10649         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10650                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10651                                       DRM_MODE_FLAG_PHSYNC);
10652                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10653                                       DRM_MODE_FLAG_NHSYNC);
10654                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10655                                       DRM_MODE_FLAG_PVSYNC);
10656                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10657                                       DRM_MODE_FLAG_NVSYNC);
10658         }
10659
10660         PIPE_CONF_CHECK_I(pipe_src_w);
10661         PIPE_CONF_CHECK_I(pipe_src_h);
10662
10663         /*
10664          * FIXME: BIOS likes to set up a cloned config with lvds+external
10665          * screen. Since we don't yet re-compute the pipe config when moving
10666          * just the lvds port away to another pipe the sw tracking won't match.
10667          *
10668          * Proper atomic modesets with recomputed global state will fix this.
10669          * Until then just don't check gmch state for inherited modes.
10670          */
10671         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10672                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10673                 /* pfit ratios are autocomputed by the hw on gen4+ */
10674                 if (INTEL_INFO(dev)->gen < 4)
10675                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10676                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10677         }
10678
10679         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10680         if (current_config->pch_pfit.enabled) {
10681                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10682                 PIPE_CONF_CHECK_I(pch_pfit.size);
10683         }
10684
10685         /* BDW+ don't expose a synchronous way to read the state */
10686         if (IS_HASWELL(dev))
10687                 PIPE_CONF_CHECK_I(ips_enabled);
10688
10689         PIPE_CONF_CHECK_I(double_wide);
10690
10691         PIPE_CONF_CHECK_X(ddi_pll_sel);
10692
10693         PIPE_CONF_CHECK_I(shared_dpll);
10694         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10695         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10696         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10697         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10698         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10699         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10700         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10701         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10702
10703         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10704                 PIPE_CONF_CHECK_I(pipe_bpp);
10705
10706         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10707         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10708
10709 #undef PIPE_CONF_CHECK_X
10710 #undef PIPE_CONF_CHECK_I
10711 #undef PIPE_CONF_CHECK_I_ALT
10712 #undef PIPE_CONF_CHECK_FLAGS
10713 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10714 #undef PIPE_CONF_QUIRK
10715
10716         return true;
10717 }
10718
10719 static void check_wm_state(struct drm_device *dev)
10720 {
10721         struct drm_i915_private *dev_priv = dev->dev_private;
10722         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10723         struct intel_crtc *intel_crtc;
10724         int plane;
10725
10726         if (INTEL_INFO(dev)->gen < 9)
10727                 return;
10728
10729         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10730         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10731
10732         for_each_intel_crtc(dev, intel_crtc) {
10733                 struct skl_ddb_entry *hw_entry, *sw_entry;
10734                 const enum pipe pipe = intel_crtc->pipe;
10735
10736                 if (!intel_crtc->active)
10737                         continue;
10738
10739                 /* planes */
10740                 for_each_plane(pipe, plane) {
10741                         hw_entry = &hw_ddb.plane[pipe][plane];
10742                         sw_entry = &sw_ddb->plane[pipe][plane];
10743
10744                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10745                                 continue;
10746
10747                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10748                                   "(expected (%u,%u), found (%u,%u))\n",
10749                                   pipe_name(pipe), plane + 1,
10750                                   sw_entry->start, sw_entry->end,
10751                                   hw_entry->start, hw_entry->end);
10752                 }
10753
10754                 /* cursor */
10755                 hw_entry = &hw_ddb.cursor[pipe];
10756                 sw_entry = &sw_ddb->cursor[pipe];
10757
10758                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10759                         continue;
10760
10761                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10762                           "(expected (%u,%u), found (%u,%u))\n",
10763                           pipe_name(pipe),
10764                           sw_entry->start, sw_entry->end,
10765                           hw_entry->start, hw_entry->end);
10766         }
10767 }
10768
10769 static void
10770 check_connector_state(struct drm_device *dev)
10771 {
10772         struct intel_connector *connector;
10773
10774         list_for_each_entry(connector, &dev->mode_config.connector_list,
10775                             base.head) {
10776                 /* This also checks the encoder/connector hw state with the
10777                  * ->get_hw_state callbacks. */
10778                 intel_connector_check_state(connector);
10779
10780                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10781                      "connector's staged encoder doesn't match current encoder\n");
10782         }
10783 }
10784
10785 static void
10786 check_encoder_state(struct drm_device *dev)
10787 {
10788         struct intel_encoder *encoder;
10789         struct intel_connector *connector;
10790
10791         for_each_intel_encoder(dev, encoder) {
10792                 bool enabled = false;
10793                 bool active = false;
10794                 enum pipe pipe, tracked_pipe;
10795
10796                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10797                               encoder->base.base.id,
10798                               encoder->base.name);
10799
10800                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10801                      "encoder's stage crtc doesn't match current crtc\n");
10802                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10803                      "encoder's active_connectors set, but no crtc\n");
10804
10805                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10806                                     base.head) {
10807                         if (connector->base.encoder != &encoder->base)
10808                                 continue;
10809                         enabled = true;
10810                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10811                                 active = true;
10812                 }
10813                 /*
10814                  * for MST connectors if we unplug the connector is gone
10815                  * away but the encoder is still connected to a crtc
10816                  * until a modeset happens in response to the hotplug.
10817                  */
10818                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10819                         continue;
10820
10821                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10822                      "encoder's enabled state mismatch "
10823                      "(expected %i, found %i)\n",
10824                      !!encoder->base.crtc, enabled);
10825                 I915_STATE_WARN(active && !encoder->base.crtc,
10826                      "active encoder with no crtc\n");
10827
10828                 I915_STATE_WARN(encoder->connectors_active != active,
10829                      "encoder's computed active state doesn't match tracked active state "
10830                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10831
10832                 active = encoder->get_hw_state(encoder, &pipe);
10833                 I915_STATE_WARN(active != encoder->connectors_active,
10834                      "encoder's hw state doesn't match sw tracking "
10835                      "(expected %i, found %i)\n",
10836                      encoder->connectors_active, active);
10837
10838                 if (!encoder->base.crtc)
10839                         continue;
10840
10841                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10842                 I915_STATE_WARN(active && pipe != tracked_pipe,
10843                      "active encoder's pipe doesn't match"
10844                      "(expected %i, found %i)\n",
10845                      tracked_pipe, pipe);
10846
10847         }
10848 }
10849
10850 static void
10851 check_crtc_state(struct drm_device *dev)
10852 {
10853         struct drm_i915_private *dev_priv = dev->dev_private;
10854         struct intel_crtc *crtc;
10855         struct intel_encoder *encoder;
10856         struct intel_crtc_state pipe_config;
10857
10858         for_each_intel_crtc(dev, crtc) {
10859                 bool enabled = false;
10860                 bool active = false;
10861
10862                 memset(&pipe_config, 0, sizeof(pipe_config));
10863
10864                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10865                               crtc->base.base.id);
10866
10867                 I915_STATE_WARN(crtc->active && !crtc->base.enabled,
10868                      "active crtc, but not enabled in sw tracking\n");
10869
10870                 for_each_intel_encoder(dev, encoder) {
10871                         if (encoder->base.crtc != &crtc->base)
10872                                 continue;
10873                         enabled = true;
10874                         if (encoder->connectors_active)
10875                                 active = true;
10876                 }
10877
10878                 I915_STATE_WARN(active != crtc->active,
10879                      "crtc's computed active state doesn't match tracked active state "
10880                      "(expected %i, found %i)\n", active, crtc->active);
10881                 I915_STATE_WARN(enabled != crtc->base.enabled,
10882                      "crtc's computed enabled state doesn't match tracked enabled state "
10883                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10884
10885                 active = dev_priv->display.get_pipe_config(crtc,
10886                                                            &pipe_config);
10887
10888                 /* hw state is inconsistent with the pipe quirk */
10889                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10890                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10891                         active = crtc->active;
10892
10893                 for_each_intel_encoder(dev, encoder) {
10894                         enum pipe pipe;
10895                         if (encoder->base.crtc != &crtc->base)
10896                                 continue;
10897                         if (encoder->get_hw_state(encoder, &pipe))
10898                                 encoder->get_config(encoder, &pipe_config);
10899                 }
10900
10901                 I915_STATE_WARN(crtc->active != active,
10902                      "crtc active state doesn't match with hw state "
10903                      "(expected %i, found %i)\n", crtc->active, active);
10904
10905                 if (active &&
10906                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10907                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
10908                         intel_dump_pipe_config(crtc, &pipe_config,
10909                                                "[hw state]");
10910                         intel_dump_pipe_config(crtc, crtc->config,
10911                                                "[sw state]");
10912                 }
10913         }
10914 }
10915
10916 static void
10917 check_shared_dpll_state(struct drm_device *dev)
10918 {
10919         struct drm_i915_private *dev_priv = dev->dev_private;
10920         struct intel_crtc *crtc;
10921         struct intel_dpll_hw_state dpll_hw_state;
10922         int i;
10923
10924         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10925                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10926                 int enabled_crtcs = 0, active_crtcs = 0;
10927                 bool active;
10928
10929                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10930
10931                 DRM_DEBUG_KMS("%s\n", pll->name);
10932
10933                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10934
10935                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10936                      "more active pll users than references: %i vs %i\n",
10937                      pll->active, hweight32(pll->config.crtc_mask));
10938                 I915_STATE_WARN(pll->active && !pll->on,
10939                      "pll in active use but not on in sw tracking\n");
10940                 I915_STATE_WARN(pll->on && !pll->active,
10941                      "pll in on but not on in use in sw tracking\n");
10942                 I915_STATE_WARN(pll->on != active,
10943                      "pll on state mismatch (expected %i, found %i)\n",
10944                      pll->on, active);
10945
10946                 for_each_intel_crtc(dev, crtc) {
10947                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10948                                 enabled_crtcs++;
10949                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10950                                 active_crtcs++;
10951                 }
10952                 I915_STATE_WARN(pll->active != active_crtcs,
10953                      "pll active crtcs mismatch (expected %i, found %i)\n",
10954                      pll->active, active_crtcs);
10955                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10956                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10957                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10958
10959                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10960                                        sizeof(dpll_hw_state)),
10961                      "pll hw state mismatch\n");
10962         }
10963 }
10964
10965 void
10966 intel_modeset_check_state(struct drm_device *dev)
10967 {
10968         check_wm_state(dev);
10969         check_connector_state(dev);
10970         check_encoder_state(dev);
10971         check_crtc_state(dev);
10972         check_shared_dpll_state(dev);
10973 }
10974
10975 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10976                                      int dotclock)
10977 {
10978         /*
10979          * FDI already provided one idea for the dotclock.
10980          * Yell if the encoder disagrees.
10981          */
10982         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10983              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10984              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10985 }
10986
10987 static void update_scanline_offset(struct intel_crtc *crtc)
10988 {
10989         struct drm_device *dev = crtc->base.dev;
10990
10991         /*
10992          * The scanline counter increments at the leading edge of hsync.
10993          *
10994          * On most platforms it starts counting from vtotal-1 on the
10995          * first active line. That means the scanline counter value is
10996          * always one less than what we would expect. Ie. just after
10997          * start of vblank, which also occurs at start of hsync (on the
10998          * last active line), the scanline counter will read vblank_start-1.
10999          *
11000          * On gen2 the scanline counter starts counting from 1 instead
11001          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11002          * to keep the value positive), instead of adding one.
11003          *
11004          * On HSW+ the behaviour of the scanline counter depends on the output
11005          * type. For DP ports it behaves like most other platforms, but on HDMI
11006          * there's an extra 1 line difference. So we need to add two instead of
11007          * one to the value.
11008          */
11009         if (IS_GEN2(dev)) {
11010                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11011                 int vtotal;
11012
11013                 vtotal = mode->crtc_vtotal;
11014                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11015                         vtotal /= 2;
11016
11017                 crtc->scanline_offset = vtotal - 1;
11018         } else if (HAS_DDI(dev) &&
11019                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11020                 crtc->scanline_offset = 2;
11021         } else
11022                 crtc->scanline_offset = 1;
11023 }
11024
11025 static struct intel_crtc_state *
11026 intel_modeset_compute_config(struct drm_crtc *crtc,
11027                              struct drm_display_mode *mode,
11028                              struct drm_framebuffer *fb,
11029                              unsigned *modeset_pipes,
11030                              unsigned *prepare_pipes,
11031                              unsigned *disable_pipes)
11032 {
11033         struct intel_crtc_state *pipe_config = NULL;
11034
11035         intel_modeset_affected_pipes(crtc, modeset_pipes,
11036                                      prepare_pipes, disable_pipes);
11037
11038         if ((*modeset_pipes) == 0)
11039                 goto out;
11040
11041         /*
11042          * Note this needs changes when we start tracking multiple modes
11043          * and crtcs.  At that point we'll need to compute the whole config
11044          * (i.e. one pipe_config for each crtc) rather than just the one
11045          * for this crtc.
11046          */
11047         pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11048         if (IS_ERR(pipe_config)) {
11049                 goto out;
11050         }
11051         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11052                                "[modeset]");
11053
11054 out:
11055         return pipe_config;
11056 }
11057
11058 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11059                                        unsigned modeset_pipes,
11060                                        unsigned disable_pipes)
11061 {
11062         struct drm_i915_private *dev_priv = to_i915(dev);
11063         unsigned clear_pipes = modeset_pipes | disable_pipes;
11064         struct intel_crtc *intel_crtc;
11065         int ret = 0;
11066
11067         if (!dev_priv->display.crtc_compute_clock)
11068                 return 0;
11069
11070         ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11071         if (ret)
11072                 goto done;
11073
11074         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11075                 struct intel_crtc_state *state = intel_crtc->new_config;
11076                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11077                                                            state);
11078                 if (ret) {
11079                         intel_shared_dpll_abort_config(dev_priv);
11080                         goto done;
11081                 }
11082         }
11083
11084 done:
11085         return ret;
11086 }
11087
11088 static int __intel_set_mode(struct drm_crtc *crtc,
11089                             struct drm_display_mode *mode,
11090                             int x, int y, struct drm_framebuffer *fb,
11091                             struct intel_crtc_state *pipe_config,
11092                             unsigned modeset_pipes,
11093                             unsigned prepare_pipes,
11094                             unsigned disable_pipes)
11095 {
11096         struct drm_device *dev = crtc->dev;
11097         struct drm_i915_private *dev_priv = dev->dev_private;
11098         struct drm_display_mode *saved_mode;
11099         struct intel_crtc *intel_crtc;
11100         int ret = 0;
11101
11102         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11103         if (!saved_mode)
11104                 return -ENOMEM;
11105
11106         *saved_mode = crtc->mode;
11107
11108         if (modeset_pipes)
11109                 to_intel_crtc(crtc)->new_config = pipe_config;
11110
11111         /*
11112          * See if the config requires any additional preparation, e.g.
11113          * to adjust global state with pipes off.  We need to do this
11114          * here so we can get the modeset_pipe updated config for the new
11115          * mode set on this crtc.  For other crtcs we need to use the
11116          * adjusted_mode bits in the crtc directly.
11117          */
11118         if (IS_VALLEYVIEW(dev)) {
11119                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11120
11121                 /* may have added more to prepare_pipes than we should */
11122                 prepare_pipes &= ~disable_pipes;
11123         }
11124
11125         ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11126         if (ret)
11127                 goto done;
11128
11129         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11130                 intel_crtc_disable(&intel_crtc->base);
11131
11132         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11133                 if (intel_crtc->base.enabled)
11134                         dev_priv->display.crtc_disable(&intel_crtc->base);
11135         }
11136
11137         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11138          * to set it here already despite that we pass it down the callchain.
11139          *
11140          * Note we'll need to fix this up when we start tracking multiple
11141          * pipes; here we assume a single modeset_pipe and only track the
11142          * single crtc and mode.
11143          */
11144         if (modeset_pipes) {
11145                 crtc->mode = *mode;
11146                 /* mode_set/enable/disable functions rely on a correct pipe
11147                  * config. */
11148                 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11149
11150                 /*
11151                  * Calculate and store various constants which
11152                  * are later needed by vblank and swap-completion
11153                  * timestamping. They are derived from true hwmode.
11154                  */
11155                 drm_calc_timestamping_constants(crtc,
11156                                                 &pipe_config->base.adjusted_mode);
11157         }
11158
11159         /* Only after disabling all output pipelines that will be changed can we
11160          * update the the output configuration. */
11161         intel_modeset_update_state(dev, prepare_pipes);
11162
11163         modeset_update_crtc_power_domains(dev);
11164
11165         /* Set up the DPLL and any encoders state that needs to adjust or depend
11166          * on the DPLL.
11167          */
11168         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11169                 struct drm_plane *primary = intel_crtc->base.primary;
11170                 int vdisplay, hdisplay;
11171
11172                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11173                 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11174                                                    fb, 0, 0,
11175                                                    hdisplay, vdisplay,
11176                                                    x << 16, y << 16,
11177                                                    hdisplay << 16, vdisplay << 16);
11178         }
11179
11180         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11181         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11182                 update_scanline_offset(intel_crtc);
11183
11184                 dev_priv->display.crtc_enable(&intel_crtc->base);
11185         }
11186
11187         /* FIXME: add subpixel order */
11188 done:
11189         if (ret && crtc->enabled)
11190                 crtc->mode = *saved_mode;
11191
11192         kfree(saved_mode);
11193         return ret;
11194 }
11195
11196 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11197                                 struct drm_display_mode *mode,
11198                                 int x, int y, struct drm_framebuffer *fb,
11199                                 struct intel_crtc_state *pipe_config,
11200                                 unsigned modeset_pipes,
11201                                 unsigned prepare_pipes,
11202                                 unsigned disable_pipes)
11203 {
11204         int ret;
11205
11206         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11207                                prepare_pipes, disable_pipes);
11208
11209         if (ret == 0)
11210                 intel_modeset_check_state(crtc->dev);
11211
11212         return ret;
11213 }
11214
11215 static int intel_set_mode(struct drm_crtc *crtc,
11216                           struct drm_display_mode *mode,
11217                           int x, int y, struct drm_framebuffer *fb)
11218 {
11219         struct intel_crtc_state *pipe_config;
11220         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11221
11222         pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11223                                                    &modeset_pipes,
11224                                                    &prepare_pipes,
11225                                                    &disable_pipes);
11226
11227         if (IS_ERR(pipe_config))
11228                 return PTR_ERR(pipe_config);
11229
11230         return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11231                                     modeset_pipes, prepare_pipes,
11232                                     disable_pipes);
11233 }
11234
11235 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11236 {
11237         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11238 }
11239
11240 #undef for_each_intel_crtc_masked
11241
11242 static void intel_set_config_free(struct intel_set_config *config)
11243 {
11244         if (!config)
11245                 return;
11246
11247         kfree(config->save_connector_encoders);
11248         kfree(config->save_encoder_crtcs);
11249         kfree(config->save_crtc_enabled);
11250         kfree(config);
11251 }
11252
11253 static int intel_set_config_save_state(struct drm_device *dev,
11254                                        struct intel_set_config *config)
11255 {
11256         struct drm_crtc *crtc;
11257         struct drm_encoder *encoder;
11258         struct drm_connector *connector;
11259         int count;
11260
11261         config->save_crtc_enabled =
11262                 kcalloc(dev->mode_config.num_crtc,
11263                         sizeof(bool), GFP_KERNEL);
11264         if (!config->save_crtc_enabled)
11265                 return -ENOMEM;
11266
11267         config->save_encoder_crtcs =
11268                 kcalloc(dev->mode_config.num_encoder,
11269                         sizeof(struct drm_crtc *), GFP_KERNEL);
11270         if (!config->save_encoder_crtcs)
11271                 return -ENOMEM;
11272
11273         config->save_connector_encoders =
11274                 kcalloc(dev->mode_config.num_connector,
11275                         sizeof(struct drm_encoder *), GFP_KERNEL);
11276         if (!config->save_connector_encoders)
11277                 return -ENOMEM;
11278
11279         /* Copy data. Note that driver private data is not affected.
11280          * Should anything bad happen only the expected state is
11281          * restored, not the drivers personal bookkeeping.
11282          */
11283         count = 0;
11284         for_each_crtc(dev, crtc) {
11285                 config->save_crtc_enabled[count++] = crtc->enabled;
11286         }
11287
11288         count = 0;
11289         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11290                 config->save_encoder_crtcs[count++] = encoder->crtc;
11291         }
11292
11293         count = 0;
11294         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11295                 config->save_connector_encoders[count++] = connector->encoder;
11296         }
11297
11298         return 0;
11299 }
11300
11301 static void intel_set_config_restore_state(struct drm_device *dev,
11302                                            struct intel_set_config *config)
11303 {
11304         struct intel_crtc *crtc;
11305         struct intel_encoder *encoder;
11306         struct intel_connector *connector;
11307         int count;
11308
11309         count = 0;
11310         for_each_intel_crtc(dev, crtc) {
11311                 crtc->new_enabled = config->save_crtc_enabled[count++];
11312
11313                 if (crtc->new_enabled)
11314                         crtc->new_config = crtc->config;
11315                 else
11316                         crtc->new_config = NULL;
11317         }
11318
11319         count = 0;
11320         for_each_intel_encoder(dev, encoder) {
11321                 encoder->new_crtc =
11322                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11323         }
11324
11325         count = 0;
11326         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11327                 connector->new_encoder =
11328                         to_intel_encoder(config->save_connector_encoders[count++]);
11329         }
11330 }
11331
11332 static bool
11333 is_crtc_connector_off(struct drm_mode_set *set)
11334 {
11335         int i;
11336
11337         if (set->num_connectors == 0)
11338                 return false;
11339
11340         if (WARN_ON(set->connectors == NULL))
11341                 return false;
11342
11343         for (i = 0; i < set->num_connectors; i++)
11344                 if (set->connectors[i]->encoder &&
11345                     set->connectors[i]->encoder->crtc == set->crtc &&
11346                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11347                         return true;
11348
11349         return false;
11350 }
11351
11352 static void
11353 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11354                                       struct intel_set_config *config)
11355 {
11356
11357         /* We should be able to check here if the fb has the same properties
11358          * and then just flip_or_move it */
11359         if (is_crtc_connector_off(set)) {
11360                 config->mode_changed = true;
11361         } else if (set->crtc->primary->fb != set->fb) {
11362                 /*
11363                  * If we have no fb, we can only flip as long as the crtc is
11364                  * active, otherwise we need a full mode set.  The crtc may
11365                  * be active if we've only disabled the primary plane, or
11366                  * in fastboot situations.
11367                  */
11368                 if (set->crtc->primary->fb == NULL) {
11369                         struct intel_crtc *intel_crtc =
11370                                 to_intel_crtc(set->crtc);
11371
11372                         if (intel_crtc->active) {
11373                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11374                                 config->fb_changed = true;
11375                         } else {
11376                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11377                                 config->mode_changed = true;
11378                         }
11379                 } else if (set->fb == NULL) {
11380                         config->mode_changed = true;
11381                 } else if (set->fb->pixel_format !=
11382                            set->crtc->primary->fb->pixel_format) {
11383                         config->mode_changed = true;
11384                 } else {
11385                         config->fb_changed = true;
11386                 }
11387         }
11388
11389         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11390                 config->fb_changed = true;
11391
11392         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11393                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11394                 drm_mode_debug_printmodeline(&set->crtc->mode);
11395                 drm_mode_debug_printmodeline(set->mode);
11396                 config->mode_changed = true;
11397         }
11398
11399         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11400                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11401 }
11402
11403 static int
11404 intel_modeset_stage_output_state(struct drm_device *dev,
11405                                  struct drm_mode_set *set,
11406                                  struct intel_set_config *config)
11407 {
11408         struct intel_connector *connector;
11409         struct intel_encoder *encoder;
11410         struct intel_crtc *crtc;
11411         int ro;
11412
11413         /* The upper layers ensure that we either disable a crtc or have a list
11414          * of connectors. For paranoia, double-check this. */
11415         WARN_ON(!set->fb && (set->num_connectors != 0));
11416         WARN_ON(set->fb && (set->num_connectors == 0));
11417
11418         list_for_each_entry(connector, &dev->mode_config.connector_list,
11419                             base.head) {
11420                 /* Otherwise traverse passed in connector list and get encoders
11421                  * for them. */
11422                 for (ro = 0; ro < set->num_connectors; ro++) {
11423                         if (set->connectors[ro] == &connector->base) {
11424                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11425                                 break;
11426                         }
11427                 }
11428
11429                 /* If we disable the crtc, disable all its connectors. Also, if
11430                  * the connector is on the changing crtc but not on the new
11431                  * connector list, disable it. */
11432                 if ((!set->fb || ro == set->num_connectors) &&
11433                     connector->base.encoder &&
11434                     connector->base.encoder->crtc == set->crtc) {
11435                         connector->new_encoder = NULL;
11436
11437                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11438                                 connector->base.base.id,
11439                                 connector->base.name);
11440                 }
11441
11442
11443                 if (&connector->new_encoder->base != connector->base.encoder) {
11444                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11445                         config->mode_changed = true;
11446                 }
11447         }
11448         /* connector->new_encoder is now updated for all connectors. */
11449
11450         /* Update crtc of enabled connectors. */
11451         list_for_each_entry(connector, &dev->mode_config.connector_list,
11452                             base.head) {
11453                 struct drm_crtc *new_crtc;
11454
11455                 if (!connector->new_encoder)
11456                         continue;
11457
11458                 new_crtc = connector->new_encoder->base.crtc;
11459
11460                 for (ro = 0; ro < set->num_connectors; ro++) {
11461                         if (set->connectors[ro] == &connector->base)
11462                                 new_crtc = set->crtc;
11463                 }
11464
11465                 /* Make sure the new CRTC will work with the encoder */
11466                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11467                                          new_crtc)) {
11468                         return -EINVAL;
11469                 }
11470                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11471
11472                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11473                         connector->base.base.id,
11474                         connector->base.name,
11475                         new_crtc->base.id);
11476         }
11477
11478         /* Check for any encoders that needs to be disabled. */
11479         for_each_intel_encoder(dev, encoder) {
11480                 int num_connectors = 0;
11481                 list_for_each_entry(connector,
11482                                     &dev->mode_config.connector_list,
11483                                     base.head) {
11484                         if (connector->new_encoder == encoder) {
11485                                 WARN_ON(!connector->new_encoder->new_crtc);
11486                                 num_connectors++;
11487                         }
11488                 }
11489
11490                 if (num_connectors == 0)
11491                         encoder->new_crtc = NULL;
11492                 else if (num_connectors > 1)
11493                         return -EINVAL;
11494
11495                 /* Only now check for crtc changes so we don't miss encoders
11496                  * that will be disabled. */
11497                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11498                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11499                         config->mode_changed = true;
11500                 }
11501         }
11502         /* Now we've also updated encoder->new_crtc for all encoders. */
11503         list_for_each_entry(connector, &dev->mode_config.connector_list,
11504                             base.head) {
11505                 if (connector->new_encoder)
11506                         if (connector->new_encoder != connector->encoder)
11507                                 connector->encoder = connector->new_encoder;
11508         }
11509         for_each_intel_crtc(dev, crtc) {
11510                 crtc->new_enabled = false;
11511
11512                 for_each_intel_encoder(dev, encoder) {
11513                         if (encoder->new_crtc == crtc) {
11514                                 crtc->new_enabled = true;
11515                                 break;
11516                         }
11517                 }
11518
11519                 if (crtc->new_enabled != crtc->base.enabled) {
11520                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11521                                       crtc->new_enabled ? "en" : "dis");
11522                         config->mode_changed = true;
11523                 }
11524
11525                 if (crtc->new_enabled)
11526                         crtc->new_config = crtc->config;
11527                 else
11528                         crtc->new_config = NULL;
11529         }
11530
11531         return 0;
11532 }
11533
11534 static void disable_crtc_nofb(struct intel_crtc *crtc)
11535 {
11536         struct drm_device *dev = crtc->base.dev;
11537         struct intel_encoder *encoder;
11538         struct intel_connector *connector;
11539
11540         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11541                       pipe_name(crtc->pipe));
11542
11543         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11544                 if (connector->new_encoder &&
11545                     connector->new_encoder->new_crtc == crtc)
11546                         connector->new_encoder = NULL;
11547         }
11548
11549         for_each_intel_encoder(dev, encoder) {
11550                 if (encoder->new_crtc == crtc)
11551                         encoder->new_crtc = NULL;
11552         }
11553
11554         crtc->new_enabled = false;
11555         crtc->new_config = NULL;
11556 }
11557
11558 static int intel_crtc_set_config(struct drm_mode_set *set)
11559 {
11560         struct drm_device *dev;
11561         struct drm_mode_set save_set;
11562         struct intel_set_config *config;
11563         struct intel_crtc_state *pipe_config;
11564         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11565         int ret;
11566
11567         BUG_ON(!set);
11568         BUG_ON(!set->crtc);
11569         BUG_ON(!set->crtc->helper_private);
11570
11571         /* Enforce sane interface api - has been abused by the fb helper. */
11572         BUG_ON(!set->mode && set->fb);
11573         BUG_ON(set->fb && set->num_connectors == 0);
11574
11575         if (set->fb) {
11576                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11577                                 set->crtc->base.id, set->fb->base.id,
11578                                 (int)set->num_connectors, set->x, set->y);
11579         } else {
11580                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11581         }
11582
11583         dev = set->crtc->dev;
11584
11585         ret = -ENOMEM;
11586         config = kzalloc(sizeof(*config), GFP_KERNEL);
11587         if (!config)
11588                 goto out_config;
11589
11590         ret = intel_set_config_save_state(dev, config);
11591         if (ret)
11592                 goto out_config;
11593
11594         save_set.crtc = set->crtc;
11595         save_set.mode = &set->crtc->mode;
11596         save_set.x = set->crtc->x;
11597         save_set.y = set->crtc->y;
11598         save_set.fb = set->crtc->primary->fb;
11599
11600         /* Compute whether we need a full modeset, only an fb base update or no
11601          * change at all. In the future we might also check whether only the
11602          * mode changed, e.g. for LVDS where we only change the panel fitter in
11603          * such cases. */
11604         intel_set_config_compute_mode_changes(set, config);
11605
11606         ret = intel_modeset_stage_output_state(dev, set, config);
11607         if (ret)
11608                 goto fail;
11609
11610         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11611                                                    set->fb,
11612                                                    &modeset_pipes,
11613                                                    &prepare_pipes,
11614                                                    &disable_pipes);
11615         if (IS_ERR(pipe_config)) {
11616                 ret = PTR_ERR(pipe_config);
11617                 goto fail;
11618         } else if (pipe_config) {
11619                 if (pipe_config->has_audio !=
11620                     to_intel_crtc(set->crtc)->config->has_audio)
11621                         config->mode_changed = true;
11622
11623                 /*
11624                  * Note we have an issue here with infoframes: current code
11625                  * only updates them on the full mode set path per hw
11626                  * requirements.  So here we should be checking for any
11627                  * required changes and forcing a mode set.
11628                  */
11629         }
11630
11631         /* set_mode will free it in the mode_changed case */
11632         if (!config->mode_changed)
11633                 kfree(pipe_config);
11634
11635         intel_update_pipe_size(to_intel_crtc(set->crtc));
11636
11637         if (config->mode_changed) {
11638                 ret = intel_set_mode_pipes(set->crtc, set->mode,
11639                                            set->x, set->y, set->fb, pipe_config,
11640                                            modeset_pipes, prepare_pipes,
11641                                            disable_pipes);
11642         } else if (config->fb_changed) {
11643                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11644                 struct drm_plane *primary = set->crtc->primary;
11645                 int vdisplay, hdisplay;
11646
11647                 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11648                 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11649                                                    0, 0, hdisplay, vdisplay,
11650                                                    set->x << 16, set->y << 16,
11651                                                    hdisplay << 16, vdisplay << 16);
11652
11653                 /*
11654                  * We need to make sure the primary plane is re-enabled if it
11655                  * has previously been turned off.
11656                  */
11657                 if (!intel_crtc->primary_enabled && ret == 0) {
11658                         WARN_ON(!intel_crtc->active);
11659                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11660                 }
11661
11662                 /*
11663                  * In the fastboot case this may be our only check of the
11664                  * state after boot.  It would be better to only do it on
11665                  * the first update, but we don't have a nice way of doing that
11666                  * (and really, set_config isn't used much for high freq page
11667                  * flipping, so increasing its cost here shouldn't be a big
11668                  * deal).
11669                  */
11670                 if (i915.fastboot && ret == 0)
11671                         intel_modeset_check_state(set->crtc->dev);
11672         }
11673
11674         if (ret) {
11675                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11676                               set->crtc->base.id, ret);
11677 fail:
11678                 intel_set_config_restore_state(dev, config);
11679
11680                 /*
11681                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11682                  * force the pipe off to avoid oopsing in the modeset code
11683                  * due to fb==NULL. This should only happen during boot since
11684                  * we don't yet reconstruct the FB from the hardware state.
11685                  */
11686                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11687                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11688
11689                 /* Try to restore the config */
11690                 if (config->mode_changed &&
11691                     intel_set_mode(save_set.crtc, save_set.mode,
11692                                    save_set.x, save_set.y, save_set.fb))
11693                         DRM_ERROR("failed to restore config after modeset failure\n");
11694         }
11695
11696 out_config:
11697         intel_set_config_free(config);
11698         return ret;
11699 }
11700
11701 static const struct drm_crtc_funcs intel_crtc_funcs = {
11702         .gamma_set = intel_crtc_gamma_set,
11703         .set_config = intel_crtc_set_config,
11704         .destroy = intel_crtc_destroy,
11705         .page_flip = intel_crtc_page_flip,
11706         .atomic_duplicate_state = intel_crtc_duplicate_state,
11707         .atomic_destroy_state = intel_crtc_destroy_state,
11708 };
11709
11710 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11711                                       struct intel_shared_dpll *pll,
11712                                       struct intel_dpll_hw_state *hw_state)
11713 {
11714         uint32_t val;
11715
11716         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11717                 return false;
11718
11719         val = I915_READ(PCH_DPLL(pll->id));
11720         hw_state->dpll = val;
11721         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11722         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11723
11724         return val & DPLL_VCO_ENABLE;
11725 }
11726
11727 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11728                                   struct intel_shared_dpll *pll)
11729 {
11730         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11731         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11732 }
11733
11734 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11735                                 struct intel_shared_dpll *pll)
11736 {
11737         /* PCH refclock must be enabled first */
11738         ibx_assert_pch_refclk_enabled(dev_priv);
11739
11740         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11741
11742         /* Wait for the clocks to stabilize. */
11743         POSTING_READ(PCH_DPLL(pll->id));
11744         udelay(150);
11745
11746         /* The pixel multiplier can only be updated once the
11747          * DPLL is enabled and the clocks are stable.
11748          *
11749          * So write it again.
11750          */
11751         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11752         POSTING_READ(PCH_DPLL(pll->id));
11753         udelay(200);
11754 }
11755
11756 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11757                                  struct intel_shared_dpll *pll)
11758 {
11759         struct drm_device *dev = dev_priv->dev;
11760         struct intel_crtc *crtc;
11761
11762         /* Make sure no transcoder isn't still depending on us. */
11763         for_each_intel_crtc(dev, crtc) {
11764                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11765                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11766         }
11767
11768         I915_WRITE(PCH_DPLL(pll->id), 0);
11769         POSTING_READ(PCH_DPLL(pll->id));
11770         udelay(200);
11771 }
11772
11773 static char *ibx_pch_dpll_names[] = {
11774         "PCH DPLL A",
11775         "PCH DPLL B",
11776 };
11777
11778 static void ibx_pch_dpll_init(struct drm_device *dev)
11779 {
11780         struct drm_i915_private *dev_priv = dev->dev_private;
11781         int i;
11782
11783         dev_priv->num_shared_dpll = 2;
11784
11785         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11786                 dev_priv->shared_dplls[i].id = i;
11787                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11788                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11789                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11790                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11791                 dev_priv->shared_dplls[i].get_hw_state =
11792                         ibx_pch_dpll_get_hw_state;
11793         }
11794 }
11795
11796 static void intel_shared_dpll_init(struct drm_device *dev)
11797 {
11798         struct drm_i915_private *dev_priv = dev->dev_private;
11799
11800         if (HAS_DDI(dev))
11801                 intel_ddi_pll_init(dev);
11802         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11803                 ibx_pch_dpll_init(dev);
11804         else
11805                 dev_priv->num_shared_dpll = 0;
11806
11807         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11808 }
11809
11810 /**
11811  * intel_prepare_plane_fb - Prepare fb for usage on plane
11812  * @plane: drm plane to prepare for
11813  * @fb: framebuffer to prepare for presentation
11814  *
11815  * Prepares a framebuffer for usage on a display plane.  Generally this
11816  * involves pinning the underlying object and updating the frontbuffer tracking
11817  * bits.  Some older platforms need special physical address handling for
11818  * cursor planes.
11819  *
11820  * Returns 0 on success, negative error code on failure.
11821  */
11822 int
11823 intel_prepare_plane_fb(struct drm_plane *plane,
11824                        struct drm_framebuffer *fb)
11825 {
11826         struct drm_device *dev = plane->dev;
11827         struct intel_plane *intel_plane = to_intel_plane(plane);
11828         enum pipe pipe = intel_plane->pipe;
11829         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11830         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11831         unsigned frontbuffer_bits = 0;
11832         int ret = 0;
11833
11834         if (!obj)
11835                 return 0;
11836
11837         switch (plane->type) {
11838         case DRM_PLANE_TYPE_PRIMARY:
11839                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11840                 break;
11841         case DRM_PLANE_TYPE_CURSOR:
11842                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11843                 break;
11844         case DRM_PLANE_TYPE_OVERLAY:
11845                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11846                 break;
11847         }
11848
11849         mutex_lock(&dev->struct_mutex);
11850
11851         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11852             INTEL_INFO(dev)->cursor_needs_physical) {
11853                 int align = IS_I830(dev) ? 16 * 1024 : 256;
11854                 ret = i915_gem_object_attach_phys(obj, align);
11855                 if (ret)
11856                         DRM_DEBUG_KMS("failed to attach phys object\n");
11857         } else {
11858                 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11859         }
11860
11861         if (ret == 0)
11862                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11863
11864         mutex_unlock(&dev->struct_mutex);
11865
11866         return ret;
11867 }
11868
11869 /**
11870  * intel_cleanup_plane_fb - Cleans up an fb after plane use
11871  * @plane: drm plane to clean up for
11872  * @fb: old framebuffer that was on plane
11873  *
11874  * Cleans up a framebuffer that has just been removed from a plane.
11875  */
11876 void
11877 intel_cleanup_plane_fb(struct drm_plane *plane,
11878                        struct drm_framebuffer *fb)
11879 {
11880         struct drm_device *dev = plane->dev;
11881         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11882
11883         if (WARN_ON(!obj))
11884                 return;
11885
11886         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11887             !INTEL_INFO(dev)->cursor_needs_physical) {
11888                 mutex_lock(&dev->struct_mutex);
11889                 intel_unpin_fb_obj(obj);
11890                 mutex_unlock(&dev->struct_mutex);
11891         }
11892 }
11893
11894 static int
11895 intel_check_primary_plane(struct drm_plane *plane,
11896                           struct intel_plane_state *state)
11897 {
11898         struct drm_device *dev = plane->dev;
11899         struct drm_i915_private *dev_priv = dev->dev_private;
11900         struct drm_crtc *crtc = state->base.crtc;
11901         struct intel_crtc *intel_crtc;
11902         struct drm_framebuffer *fb = state->base.fb;
11903         struct drm_rect *dest = &state->dst;
11904         struct drm_rect *src = &state->src;
11905         const struct drm_rect *clip = &state->clip;
11906         int ret;
11907
11908         crtc = crtc ? crtc : plane->crtc;
11909         intel_crtc = to_intel_crtc(crtc);
11910
11911         ret = drm_plane_helper_check_update(plane, crtc, fb,
11912                                             src, dest, clip,
11913                                             DRM_PLANE_HELPER_NO_SCALING,
11914                                             DRM_PLANE_HELPER_NO_SCALING,
11915                                             false, true, &state->visible);
11916         if (ret)
11917                 return ret;
11918
11919         if (intel_crtc->active) {
11920                 intel_crtc->atomic.wait_for_flips = true;
11921
11922                 /*
11923                  * FBC does not work on some platforms for rotated
11924                  * planes, so disable it when rotation is not 0 and
11925                  * update it when rotation is set back to 0.
11926                  *
11927                  * FIXME: This is redundant with the fbc update done in
11928                  * the primary plane enable function except that that
11929                  * one is done too late. We eventually need to unify
11930                  * this.
11931                  */
11932                 if (intel_crtc->primary_enabled &&
11933                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11934                     dev_priv->fbc.crtc == intel_crtc &&
11935                     state->base.rotation != BIT(DRM_ROTATE_0)) {
11936                         intel_crtc->atomic.disable_fbc = true;
11937                 }
11938
11939                 if (state->visible) {
11940                         /*
11941                          * BDW signals flip done immediately if the plane
11942                          * is disabled, even if the plane enable is already
11943                          * armed to occur at the next vblank :(
11944                          */
11945                         if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11946                                 intel_crtc->atomic.wait_vblank = true;
11947                 }
11948
11949                 intel_crtc->atomic.fb_bits |=
11950                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11951
11952                 intel_crtc->atomic.update_fbc = true;
11953         }
11954
11955         return 0;
11956 }
11957
11958 static void
11959 intel_commit_primary_plane(struct drm_plane *plane,
11960                            struct intel_plane_state *state)
11961 {
11962         struct drm_crtc *crtc = state->base.crtc;
11963         struct drm_framebuffer *fb = state->base.fb;
11964         struct drm_device *dev = plane->dev;
11965         struct drm_i915_private *dev_priv = dev->dev_private;
11966         struct intel_crtc *intel_crtc;
11967         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11968         struct intel_plane *intel_plane = to_intel_plane(plane);
11969         struct drm_rect *src = &state->src;
11970
11971         crtc = crtc ? crtc : plane->crtc;
11972         intel_crtc = to_intel_crtc(crtc);
11973
11974         plane->fb = fb;
11975         crtc->x = src->x1 >> 16;
11976         crtc->y = src->y1 >> 16;
11977
11978         intel_plane->obj = obj;
11979
11980         if (intel_crtc->active) {
11981                 if (state->visible) {
11982                         /* FIXME: kill this fastboot hack */
11983                         intel_update_pipe_size(intel_crtc);
11984
11985                         intel_crtc->primary_enabled = true;
11986
11987                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11988                                         crtc->x, crtc->y);
11989                 } else {
11990                         /*
11991                          * If clipping results in a non-visible primary plane,
11992                          * we'll disable the primary plane.  Note that this is
11993                          * a bit different than what happens if userspace
11994                          * explicitly disables the plane by passing fb=0
11995                          * because plane->fb still gets set and pinned.
11996                          */
11997                         intel_disable_primary_hw_plane(plane, crtc);
11998                 }
11999         }
12000 }
12001
12002 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12003 {
12004         struct drm_device *dev = crtc->dev;
12005         struct drm_i915_private *dev_priv = dev->dev_private;
12006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12007         struct intel_plane *intel_plane;
12008         struct drm_plane *p;
12009         unsigned fb_bits = 0;
12010
12011         /* Track fb's for any planes being disabled */
12012         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12013                 intel_plane = to_intel_plane(p);
12014
12015                 if (intel_crtc->atomic.disabled_planes &
12016                     (1 << drm_plane_index(p))) {
12017                         switch (p->type) {
12018                         case DRM_PLANE_TYPE_PRIMARY:
12019                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12020                                 break;
12021                         case DRM_PLANE_TYPE_CURSOR:
12022                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12023                                 break;
12024                         case DRM_PLANE_TYPE_OVERLAY:
12025                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12026                                 break;
12027                         }
12028
12029                         mutex_lock(&dev->struct_mutex);
12030                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12031                         mutex_unlock(&dev->struct_mutex);
12032                 }
12033         }
12034
12035         if (intel_crtc->atomic.wait_for_flips)
12036                 intel_crtc_wait_for_pending_flips(crtc);
12037
12038         if (intel_crtc->atomic.disable_fbc)
12039                 intel_fbc_disable(dev);
12040
12041         if (intel_crtc->atomic.pre_disable_primary)
12042                 intel_pre_disable_primary(crtc);
12043
12044         if (intel_crtc->atomic.update_wm)
12045                 intel_update_watermarks(crtc);
12046
12047         intel_runtime_pm_get(dev_priv);
12048
12049         /* Perform vblank evasion around commit operation */
12050         if (intel_crtc->active)
12051                 intel_crtc->atomic.evade =
12052                         intel_pipe_update_start(intel_crtc,
12053                                                 &intel_crtc->atomic.start_vbl_count);
12054 }
12055
12056 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12057 {
12058         struct drm_device *dev = crtc->dev;
12059         struct drm_i915_private *dev_priv = dev->dev_private;
12060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12061         struct drm_plane *p;
12062
12063         if (intel_crtc->atomic.evade)
12064                 intel_pipe_update_end(intel_crtc,
12065                                       intel_crtc->atomic.start_vbl_count);
12066
12067         intel_runtime_pm_put(dev_priv);
12068
12069         if (intel_crtc->atomic.wait_vblank)
12070                 intel_wait_for_vblank(dev, intel_crtc->pipe);
12071
12072         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12073
12074         if (intel_crtc->atomic.update_fbc) {
12075                 mutex_lock(&dev->struct_mutex);
12076                 intel_fbc_update(dev);
12077                 mutex_unlock(&dev->struct_mutex);
12078         }
12079
12080         if (intel_crtc->atomic.post_enable_primary)
12081                 intel_post_enable_primary(crtc);
12082
12083         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12084                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12085                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12086                                                        false, false);
12087
12088         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12089 }
12090
12091 /**
12092  * intel_plane_destroy - destroy a plane
12093  * @plane: plane to destroy
12094  *
12095  * Common destruction function for all types of planes (primary, cursor,
12096  * sprite).
12097  */
12098 void intel_plane_destroy(struct drm_plane *plane)
12099 {
12100         struct intel_plane *intel_plane = to_intel_plane(plane);
12101         drm_plane_cleanup(plane);
12102         kfree(intel_plane);
12103 }
12104
12105 const struct drm_plane_funcs intel_plane_funcs = {
12106         .update_plane = drm_atomic_helper_update_plane,
12107         .disable_plane = drm_atomic_helper_disable_plane,
12108         .destroy = intel_plane_destroy,
12109         .set_property = drm_atomic_helper_plane_set_property,
12110         .atomic_get_property = intel_plane_atomic_get_property,
12111         .atomic_set_property = intel_plane_atomic_set_property,
12112         .atomic_duplicate_state = intel_plane_duplicate_state,
12113         .atomic_destroy_state = intel_plane_destroy_state,
12114
12115 };
12116
12117 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12118                                                     int pipe)
12119 {
12120         struct intel_plane *primary;
12121         struct intel_plane_state *state;
12122         const uint32_t *intel_primary_formats;
12123         int num_formats;
12124
12125         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12126         if (primary == NULL)
12127                 return NULL;
12128
12129         state = intel_create_plane_state(&primary->base);
12130         if (!state) {
12131                 kfree(primary);
12132                 return NULL;
12133         }
12134         primary->base.state = &state->base;
12135
12136         primary->can_scale = false;
12137         primary->max_downscale = 1;
12138         primary->pipe = pipe;
12139         primary->plane = pipe;
12140         primary->check_plane = intel_check_primary_plane;
12141         primary->commit_plane = intel_commit_primary_plane;
12142         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12143                 primary->plane = !pipe;
12144
12145         if (INTEL_INFO(dev)->gen <= 3) {
12146                 intel_primary_formats = intel_primary_formats_gen2;
12147                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12148         } else {
12149                 intel_primary_formats = intel_primary_formats_gen4;
12150                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12151         }
12152
12153         drm_universal_plane_init(dev, &primary->base, 0,
12154                                  &intel_plane_funcs,
12155                                  intel_primary_formats, num_formats,
12156                                  DRM_PLANE_TYPE_PRIMARY);
12157
12158         if (INTEL_INFO(dev)->gen >= 4) {
12159                 if (!dev->mode_config.rotation_property)
12160                         dev->mode_config.rotation_property =
12161                                 drm_mode_create_rotation_property(dev,
12162                                                         BIT(DRM_ROTATE_0) |
12163                                                         BIT(DRM_ROTATE_180));
12164                 if (dev->mode_config.rotation_property)
12165                         drm_object_attach_property(&primary->base.base,
12166                                 dev->mode_config.rotation_property,
12167                                 state->base.rotation);
12168         }
12169
12170         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12171
12172         return &primary->base;
12173 }
12174
12175 static int
12176 intel_check_cursor_plane(struct drm_plane *plane,
12177                          struct intel_plane_state *state)
12178 {
12179         struct drm_crtc *crtc = state->base.crtc;
12180         struct drm_device *dev = plane->dev;
12181         struct drm_framebuffer *fb = state->base.fb;
12182         struct drm_rect *dest = &state->dst;
12183         struct drm_rect *src = &state->src;
12184         const struct drm_rect *clip = &state->clip;
12185         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12186         struct intel_crtc *intel_crtc;
12187         unsigned stride;
12188         int ret;
12189
12190         crtc = crtc ? crtc : plane->crtc;
12191         intel_crtc = to_intel_crtc(crtc);
12192
12193         ret = drm_plane_helper_check_update(plane, crtc, fb,
12194                                             src, dest, clip,
12195                                             DRM_PLANE_HELPER_NO_SCALING,
12196                                             DRM_PLANE_HELPER_NO_SCALING,
12197                                             true, true, &state->visible);
12198         if (ret)
12199                 return ret;
12200
12201
12202         /* if we want to turn off the cursor ignore width and height */
12203         if (!obj)
12204                 goto finish;
12205
12206         /* Check for which cursor types we support */
12207         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12208                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12209                           state->base.crtc_w, state->base.crtc_h);
12210                 return -EINVAL;
12211         }
12212
12213         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12214         if (obj->base.size < stride * state->base.crtc_h) {
12215                 DRM_DEBUG_KMS("buffer is too small\n");
12216                 return -ENOMEM;
12217         }
12218
12219         if (fb == crtc->cursor->fb)
12220                 return 0;
12221
12222         /* we only need to pin inside GTT if cursor is non-phy */
12223         mutex_lock(&dev->struct_mutex);
12224         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12225                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12226                 ret = -EINVAL;
12227         }
12228         mutex_unlock(&dev->struct_mutex);
12229
12230 finish:
12231         if (intel_crtc->active) {
12232                 if (intel_crtc->cursor_width != state->base.crtc_w)
12233                         intel_crtc->atomic.update_wm = true;
12234
12235                 intel_crtc->atomic.fb_bits |=
12236                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12237         }
12238
12239         return ret;
12240 }
12241
12242 static void
12243 intel_commit_cursor_plane(struct drm_plane *plane,
12244                           struct intel_plane_state *state)
12245 {
12246         struct drm_crtc *crtc = state->base.crtc;
12247         struct drm_device *dev = plane->dev;
12248         struct intel_crtc *intel_crtc;
12249         struct intel_plane *intel_plane = to_intel_plane(plane);
12250         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12251         uint32_t addr;
12252
12253         crtc = crtc ? crtc : plane->crtc;
12254         intel_crtc = to_intel_crtc(crtc);
12255
12256         plane->fb = state->base.fb;
12257         crtc->cursor_x = state->base.crtc_x;
12258         crtc->cursor_y = state->base.crtc_y;
12259
12260         intel_plane->obj = obj;
12261
12262         if (intel_crtc->cursor_bo == obj)
12263                 goto update;
12264
12265         if (!obj)
12266                 addr = 0;
12267         else if (!INTEL_INFO(dev)->cursor_needs_physical)
12268                 addr = i915_gem_obj_ggtt_offset(obj);
12269         else
12270                 addr = obj->phys_handle->busaddr;
12271
12272         intel_crtc->cursor_addr = addr;
12273         intel_crtc->cursor_bo = obj;
12274 update:
12275         intel_crtc->cursor_width = state->base.crtc_w;
12276         intel_crtc->cursor_height = state->base.crtc_h;
12277
12278         if (intel_crtc->active)
12279                 intel_crtc_update_cursor(crtc, state->visible);
12280 }
12281
12282 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12283                                                    int pipe)
12284 {
12285         struct intel_plane *cursor;
12286         struct intel_plane_state *state;
12287
12288         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12289         if (cursor == NULL)
12290                 return NULL;
12291
12292         state = intel_create_plane_state(&cursor->base);
12293         if (!state) {
12294                 kfree(cursor);
12295                 return NULL;
12296         }
12297         cursor->base.state = &state->base;
12298
12299         cursor->can_scale = false;
12300         cursor->max_downscale = 1;
12301         cursor->pipe = pipe;
12302         cursor->plane = pipe;
12303         cursor->check_plane = intel_check_cursor_plane;
12304         cursor->commit_plane = intel_commit_cursor_plane;
12305
12306         drm_universal_plane_init(dev, &cursor->base, 0,
12307                                  &intel_plane_funcs,
12308                                  intel_cursor_formats,
12309                                  ARRAY_SIZE(intel_cursor_formats),
12310                                  DRM_PLANE_TYPE_CURSOR);
12311
12312         if (INTEL_INFO(dev)->gen >= 4) {
12313                 if (!dev->mode_config.rotation_property)
12314                         dev->mode_config.rotation_property =
12315                                 drm_mode_create_rotation_property(dev,
12316                                                         BIT(DRM_ROTATE_0) |
12317                                                         BIT(DRM_ROTATE_180));
12318                 if (dev->mode_config.rotation_property)
12319                         drm_object_attach_property(&cursor->base.base,
12320                                 dev->mode_config.rotation_property,
12321                                 state->base.rotation);
12322         }
12323
12324         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12325
12326         return &cursor->base;
12327 }
12328
12329 static void intel_crtc_init(struct drm_device *dev, int pipe)
12330 {
12331         struct drm_i915_private *dev_priv = dev->dev_private;
12332         struct intel_crtc *intel_crtc;
12333         struct intel_crtc_state *crtc_state = NULL;
12334         struct drm_plane *primary = NULL;
12335         struct drm_plane *cursor = NULL;
12336         int i, ret;
12337
12338         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12339         if (intel_crtc == NULL)
12340                 return;
12341
12342         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12343         if (!crtc_state)
12344                 goto fail;
12345         intel_crtc_set_state(intel_crtc, crtc_state);
12346
12347         primary = intel_primary_plane_create(dev, pipe);
12348         if (!primary)
12349                 goto fail;
12350
12351         cursor = intel_cursor_plane_create(dev, pipe);
12352         if (!cursor)
12353                 goto fail;
12354
12355         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12356                                         cursor, &intel_crtc_funcs);
12357         if (ret)
12358                 goto fail;
12359
12360         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12361         for (i = 0; i < 256; i++) {
12362                 intel_crtc->lut_r[i] = i;
12363                 intel_crtc->lut_g[i] = i;
12364                 intel_crtc->lut_b[i] = i;
12365         }
12366
12367         /*
12368          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12369          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12370          */
12371         intel_crtc->pipe = pipe;
12372         intel_crtc->plane = pipe;
12373         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12374                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12375                 intel_crtc->plane = !pipe;
12376         }
12377
12378         intel_crtc->cursor_base = ~0;
12379         intel_crtc->cursor_cntl = ~0;
12380         intel_crtc->cursor_size = ~0;
12381
12382         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12383                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12384         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12385         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12386
12387         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12388
12389         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12390
12391         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12392         return;
12393
12394 fail:
12395         if (primary)
12396                 drm_plane_cleanup(primary);
12397         if (cursor)
12398                 drm_plane_cleanup(cursor);
12399         kfree(crtc_state);
12400         kfree(intel_crtc);
12401 }
12402
12403 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12404 {
12405         struct drm_encoder *encoder = connector->base.encoder;
12406         struct drm_device *dev = connector->base.dev;
12407
12408         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12409
12410         if (!encoder || WARN_ON(!encoder->crtc))
12411                 return INVALID_PIPE;
12412
12413         return to_intel_crtc(encoder->crtc)->pipe;
12414 }
12415
12416 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12417                                 struct drm_file *file)
12418 {
12419         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12420         struct drm_crtc *drmmode_crtc;
12421         struct intel_crtc *crtc;
12422
12423         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12424                 return -ENODEV;
12425
12426         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12427
12428         if (!drmmode_crtc) {
12429                 DRM_ERROR("no such CRTC id\n");
12430                 return -ENOENT;
12431         }
12432
12433         crtc = to_intel_crtc(drmmode_crtc);
12434         pipe_from_crtc_id->pipe = crtc->pipe;
12435
12436         return 0;
12437 }
12438
12439 static int intel_encoder_clones(struct intel_encoder *encoder)
12440 {
12441         struct drm_device *dev = encoder->base.dev;
12442         struct intel_encoder *source_encoder;
12443         int index_mask = 0;
12444         int entry = 0;
12445
12446         for_each_intel_encoder(dev, source_encoder) {
12447                 if (encoders_cloneable(encoder, source_encoder))
12448                         index_mask |= (1 << entry);
12449
12450                 entry++;
12451         }
12452
12453         return index_mask;
12454 }
12455
12456 static bool has_edp_a(struct drm_device *dev)
12457 {
12458         struct drm_i915_private *dev_priv = dev->dev_private;
12459
12460         if (!IS_MOBILE(dev))
12461                 return false;
12462
12463         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12464                 return false;
12465
12466         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12467                 return false;
12468
12469         return true;
12470 }
12471
12472 static bool intel_crt_present(struct drm_device *dev)
12473 {
12474         struct drm_i915_private *dev_priv = dev->dev_private;
12475
12476         if (INTEL_INFO(dev)->gen >= 9)
12477                 return false;
12478
12479         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12480                 return false;
12481
12482         if (IS_CHERRYVIEW(dev))
12483                 return false;
12484
12485         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12486                 return false;
12487
12488         return true;
12489 }
12490
12491 static void intel_setup_outputs(struct drm_device *dev)
12492 {
12493         struct drm_i915_private *dev_priv = dev->dev_private;
12494         struct intel_encoder *encoder;
12495         struct drm_connector *connector;
12496         bool dpd_is_edp = false;
12497
12498         intel_lvds_init(dev);
12499
12500         if (intel_crt_present(dev))
12501                 intel_crt_init(dev);
12502
12503         if (HAS_DDI(dev)) {
12504                 int found;
12505
12506                 /* Haswell uses DDI functions to detect digital outputs */
12507                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12508                 /* DDI A only supports eDP */
12509                 if (found)
12510                         intel_ddi_init(dev, PORT_A);
12511
12512                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12513                  * register */
12514                 found = I915_READ(SFUSE_STRAP);
12515
12516                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12517                         intel_ddi_init(dev, PORT_B);
12518                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12519                         intel_ddi_init(dev, PORT_C);
12520                 if (found & SFUSE_STRAP_DDID_DETECTED)
12521                         intel_ddi_init(dev, PORT_D);
12522         } else if (HAS_PCH_SPLIT(dev)) {
12523                 int found;
12524                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12525
12526                 if (has_edp_a(dev))
12527                         intel_dp_init(dev, DP_A, PORT_A);
12528
12529                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12530                         /* PCH SDVOB multiplex with HDMIB */
12531                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12532                         if (!found)
12533                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12534                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12535                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12536                 }
12537
12538                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12539                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12540
12541                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12542                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12543
12544                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12545                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12546
12547                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12548                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12549         } else if (IS_VALLEYVIEW(dev)) {
12550                 /*
12551                  * The DP_DETECTED bit is the latched state of the DDC
12552                  * SDA pin at boot. However since eDP doesn't require DDC
12553                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12554                  * eDP ports may have been muxed to an alternate function.
12555                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12556                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12557                  * detect eDP ports.
12558                  */
12559                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12560                     !intel_dp_is_edp(dev, PORT_B))
12561                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12562                                         PORT_B);
12563                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12564                     intel_dp_is_edp(dev, PORT_B))
12565                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12566
12567                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12568                     !intel_dp_is_edp(dev, PORT_C))
12569                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12570                                         PORT_C);
12571                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12572                     intel_dp_is_edp(dev, PORT_C))
12573                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12574
12575                 if (IS_CHERRYVIEW(dev)) {
12576                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12577                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12578                                                 PORT_D);
12579                         /* eDP not supported on port D, so don't check VBT */
12580                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12581                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12582                 }
12583
12584                 intel_dsi_init(dev);
12585         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12586                 bool found = false;
12587
12588                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12589                         DRM_DEBUG_KMS("probing SDVOB\n");
12590                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12591                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12592                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12593                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12594                         }
12595
12596                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12597                                 intel_dp_init(dev, DP_B, PORT_B);
12598                 }
12599
12600                 /* Before G4X SDVOC doesn't have its own detect register */
12601
12602                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12603                         DRM_DEBUG_KMS("probing SDVOC\n");
12604                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12605                 }
12606
12607                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12608
12609                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12610                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12611                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12612                         }
12613                         if (SUPPORTS_INTEGRATED_DP(dev))
12614                                 intel_dp_init(dev, DP_C, PORT_C);
12615                 }
12616
12617                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12618                     (I915_READ(DP_D) & DP_DETECTED))
12619                         intel_dp_init(dev, DP_D, PORT_D);
12620         } else if (IS_GEN2(dev))
12621                 intel_dvo_init(dev);
12622
12623         if (SUPPORTS_TV(dev))
12624                 intel_tv_init(dev);
12625
12626         /*
12627          * FIXME:  We don't have full atomic support yet, but we want to be
12628          * able to enable/test plane updates via the atomic interface in the
12629          * meantime.  However as soon as we flip DRIVER_ATOMIC on, the DRM core
12630          * will take some atomic codepaths to lookup properties during
12631          * drmModeGetConnector() that unconditionally dereference
12632          * connector->state.
12633          *
12634          * We create a dummy connector state here for each connector to ensure
12635          * the DRM core doesn't try to dereference a NULL connector->state.
12636          * The actual connector properties will never be updated or contain
12637          * useful information, but since we're doing this specifically for
12638          * testing/debug of the plane operations (and only when a specific
12639          * kernel module option is given), that shouldn't really matter.
12640          *
12641          * Once atomic support for crtc's + connectors lands, this loop should
12642          * be removed since we'll be setting up real connector state, which
12643          * will contain Intel-specific properties.
12644          */
12645         if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12646                 list_for_each_entry(connector,
12647                                     &dev->mode_config.connector_list,
12648                                     head) {
12649                         if (!WARN_ON(connector->state)) {
12650                                 connector->state =
12651                                         kzalloc(sizeof(*connector->state),
12652                                                 GFP_KERNEL);
12653                         }
12654                 }
12655         }
12656
12657         intel_psr_init(dev);
12658
12659         for_each_intel_encoder(dev, encoder) {
12660                 encoder->base.possible_crtcs = encoder->crtc_mask;
12661                 encoder->base.possible_clones =
12662                         intel_encoder_clones(encoder);
12663         }
12664
12665         intel_init_pch_refclk(dev);
12666
12667         drm_helper_move_panel_connectors_to_head(dev);
12668 }
12669
12670 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12671 {
12672         struct drm_device *dev = fb->dev;
12673         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12674
12675         drm_framebuffer_cleanup(fb);
12676         mutex_lock(&dev->struct_mutex);
12677         WARN_ON(!intel_fb->obj->framebuffer_references--);
12678         drm_gem_object_unreference(&intel_fb->obj->base);
12679         mutex_unlock(&dev->struct_mutex);
12680         kfree(intel_fb);
12681 }
12682
12683 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12684                                                 struct drm_file *file,
12685                                                 unsigned int *handle)
12686 {
12687         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12688         struct drm_i915_gem_object *obj = intel_fb->obj;
12689
12690         return drm_gem_handle_create(file, &obj->base, handle);
12691 }
12692
12693 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12694         .destroy = intel_user_framebuffer_destroy,
12695         .create_handle = intel_user_framebuffer_create_handle,
12696 };
12697
12698 static int intel_framebuffer_init(struct drm_device *dev,
12699                                   struct intel_framebuffer *intel_fb,
12700                                   struct drm_mode_fb_cmd2 *mode_cmd,
12701                                   struct drm_i915_gem_object *obj)
12702 {
12703         int aligned_height;
12704         int pitch_limit;
12705         int ret;
12706
12707         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12708
12709         if (obj->tiling_mode == I915_TILING_Y) {
12710                 DRM_DEBUG("hardware does not support tiling Y\n");
12711                 return -EINVAL;
12712         }
12713
12714         if (mode_cmd->pitches[0] & 63) {
12715                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12716                           mode_cmd->pitches[0]);
12717                 return -EINVAL;
12718         }
12719
12720         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12721                 pitch_limit = 32*1024;
12722         } else if (INTEL_INFO(dev)->gen >= 4) {
12723                 if (obj->tiling_mode)
12724                         pitch_limit = 16*1024;
12725                 else
12726                         pitch_limit = 32*1024;
12727         } else if (INTEL_INFO(dev)->gen >= 3) {
12728                 if (obj->tiling_mode)
12729                         pitch_limit = 8*1024;
12730                 else
12731                         pitch_limit = 16*1024;
12732         } else
12733                 /* XXX DSPC is limited to 4k tiled */
12734                 pitch_limit = 8*1024;
12735
12736         if (mode_cmd->pitches[0] > pitch_limit) {
12737                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12738                           obj->tiling_mode ? "tiled" : "linear",
12739                           mode_cmd->pitches[0], pitch_limit);
12740                 return -EINVAL;
12741         }
12742
12743         if (obj->tiling_mode != I915_TILING_NONE &&
12744             mode_cmd->pitches[0] != obj->stride) {
12745                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12746                           mode_cmd->pitches[0], obj->stride);
12747                 return -EINVAL;
12748         }
12749
12750         /* Reject formats not supported by any plane early. */
12751         switch (mode_cmd->pixel_format) {
12752         case DRM_FORMAT_C8:
12753         case DRM_FORMAT_RGB565:
12754         case DRM_FORMAT_XRGB8888:
12755         case DRM_FORMAT_ARGB8888:
12756                 break;
12757         case DRM_FORMAT_XRGB1555:
12758         case DRM_FORMAT_ARGB1555:
12759                 if (INTEL_INFO(dev)->gen > 3) {
12760                         DRM_DEBUG("unsupported pixel format: %s\n",
12761                                   drm_get_format_name(mode_cmd->pixel_format));
12762                         return -EINVAL;
12763                 }
12764                 break;
12765         case DRM_FORMAT_XBGR8888:
12766         case DRM_FORMAT_ABGR8888:
12767         case DRM_FORMAT_XRGB2101010:
12768         case DRM_FORMAT_ARGB2101010:
12769         case DRM_FORMAT_XBGR2101010:
12770         case DRM_FORMAT_ABGR2101010:
12771                 if (INTEL_INFO(dev)->gen < 4) {
12772                         DRM_DEBUG("unsupported pixel format: %s\n",
12773                                   drm_get_format_name(mode_cmd->pixel_format));
12774                         return -EINVAL;
12775                 }
12776                 break;
12777         case DRM_FORMAT_YUYV:
12778         case DRM_FORMAT_UYVY:
12779         case DRM_FORMAT_YVYU:
12780         case DRM_FORMAT_VYUY:
12781                 if (INTEL_INFO(dev)->gen < 5) {
12782                         DRM_DEBUG("unsupported pixel format: %s\n",
12783                                   drm_get_format_name(mode_cmd->pixel_format));
12784                         return -EINVAL;
12785                 }
12786                 break;
12787         default:
12788                 DRM_DEBUG("unsupported pixel format: %s\n",
12789                           drm_get_format_name(mode_cmd->pixel_format));
12790                 return -EINVAL;
12791         }
12792
12793         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12794         if (mode_cmd->offsets[0] != 0)
12795                 return -EINVAL;
12796
12797         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12798                                                obj->tiling_mode);
12799         /* FIXME drm helper for size checks (especially planar formats)? */
12800         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12801                 return -EINVAL;
12802
12803         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12804         intel_fb->obj = obj;
12805         intel_fb->obj->framebuffer_references++;
12806
12807         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12808         if (ret) {
12809                 DRM_ERROR("framebuffer init failed %d\n", ret);
12810                 return ret;
12811         }
12812
12813         return 0;
12814 }
12815
12816 static struct drm_framebuffer *
12817 intel_user_framebuffer_create(struct drm_device *dev,
12818                               struct drm_file *filp,
12819                               struct drm_mode_fb_cmd2 *mode_cmd)
12820 {
12821         struct drm_i915_gem_object *obj;
12822
12823         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12824                                                 mode_cmd->handles[0]));
12825         if (&obj->base == NULL)
12826                 return ERR_PTR(-ENOENT);
12827
12828         return intel_framebuffer_create(dev, mode_cmd, obj);
12829 }
12830
12831 #ifndef CONFIG_DRM_I915_FBDEV
12832 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12833 {
12834 }
12835 #endif
12836
12837 static const struct drm_mode_config_funcs intel_mode_funcs = {
12838         .fb_create = intel_user_framebuffer_create,
12839         .output_poll_changed = intel_fbdev_output_poll_changed,
12840         .atomic_check = intel_atomic_check,
12841         .atomic_commit = intel_atomic_commit,
12842 };
12843
12844 /* Set up chip specific display functions */
12845 static void intel_init_display(struct drm_device *dev)
12846 {
12847         struct drm_i915_private *dev_priv = dev->dev_private;
12848
12849         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12850                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12851         else if (IS_CHERRYVIEW(dev))
12852                 dev_priv->display.find_dpll = chv_find_best_dpll;
12853         else if (IS_VALLEYVIEW(dev))
12854                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12855         else if (IS_PINEVIEW(dev))
12856                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12857         else
12858                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12859
12860         if (INTEL_INFO(dev)->gen >= 9) {
12861                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12862                 dev_priv->display.get_initial_plane_config =
12863                         skylake_get_initial_plane_config;
12864                 dev_priv->display.crtc_compute_clock =
12865                         haswell_crtc_compute_clock;
12866                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12867                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12868                 dev_priv->display.off = ironlake_crtc_off;
12869                 dev_priv->display.update_primary_plane =
12870                         skylake_update_primary_plane;
12871         } else if (HAS_DDI(dev)) {
12872                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12873                 dev_priv->display.get_initial_plane_config =
12874                         ironlake_get_initial_plane_config;
12875                 dev_priv->display.crtc_compute_clock =
12876                         haswell_crtc_compute_clock;
12877                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12878                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12879                 dev_priv->display.off = ironlake_crtc_off;
12880                 dev_priv->display.update_primary_plane =
12881                         ironlake_update_primary_plane;
12882         } else if (HAS_PCH_SPLIT(dev)) {
12883                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12884                 dev_priv->display.get_initial_plane_config =
12885                         ironlake_get_initial_plane_config;
12886                 dev_priv->display.crtc_compute_clock =
12887                         ironlake_crtc_compute_clock;
12888                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12889                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12890                 dev_priv->display.off = ironlake_crtc_off;
12891                 dev_priv->display.update_primary_plane =
12892                         ironlake_update_primary_plane;
12893         } else if (IS_VALLEYVIEW(dev)) {
12894                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12895                 dev_priv->display.get_initial_plane_config =
12896                         i9xx_get_initial_plane_config;
12897                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12898                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12899                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12900                 dev_priv->display.off = i9xx_crtc_off;
12901                 dev_priv->display.update_primary_plane =
12902                         i9xx_update_primary_plane;
12903         } else {
12904                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12905                 dev_priv->display.get_initial_plane_config =
12906                         i9xx_get_initial_plane_config;
12907                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12908                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12909                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12910                 dev_priv->display.off = i9xx_crtc_off;
12911                 dev_priv->display.update_primary_plane =
12912                         i9xx_update_primary_plane;
12913         }
12914
12915         /* Returns the core display clock speed */
12916         if (IS_VALLEYVIEW(dev))
12917                 dev_priv->display.get_display_clock_speed =
12918                         valleyview_get_display_clock_speed;
12919         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12920                 dev_priv->display.get_display_clock_speed =
12921                         i945_get_display_clock_speed;
12922         else if (IS_I915G(dev))
12923                 dev_priv->display.get_display_clock_speed =
12924                         i915_get_display_clock_speed;
12925         else if (IS_I945GM(dev) || IS_845G(dev))
12926                 dev_priv->display.get_display_clock_speed =
12927                         i9xx_misc_get_display_clock_speed;
12928         else if (IS_PINEVIEW(dev))
12929                 dev_priv->display.get_display_clock_speed =
12930                         pnv_get_display_clock_speed;
12931         else if (IS_I915GM(dev))
12932                 dev_priv->display.get_display_clock_speed =
12933                         i915gm_get_display_clock_speed;
12934         else if (IS_I865G(dev))
12935                 dev_priv->display.get_display_clock_speed =
12936                         i865_get_display_clock_speed;
12937         else if (IS_I85X(dev))
12938                 dev_priv->display.get_display_clock_speed =
12939                         i855_get_display_clock_speed;
12940         else /* 852, 830 */
12941                 dev_priv->display.get_display_clock_speed =
12942                         i830_get_display_clock_speed;
12943
12944         if (IS_GEN5(dev)) {
12945                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12946         } else if (IS_GEN6(dev)) {
12947                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12948         } else if (IS_IVYBRIDGE(dev)) {
12949                 /* FIXME: detect B0+ stepping and use auto training */
12950                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12951                 dev_priv->display.modeset_global_resources =
12952                         ivb_modeset_global_resources;
12953         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12954                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12955         } else if (IS_VALLEYVIEW(dev)) {
12956                 dev_priv->display.modeset_global_resources =
12957                         valleyview_modeset_global_resources;
12958         }
12959
12960         /* Default just returns -ENODEV to indicate unsupported */
12961         dev_priv->display.queue_flip = intel_default_queue_flip;
12962
12963         switch (INTEL_INFO(dev)->gen) {
12964         case 2:
12965                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12966                 break;
12967
12968         case 3:
12969                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12970                 break;
12971
12972         case 4:
12973         case 5:
12974                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12975                 break;
12976
12977         case 6:
12978                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12979                 break;
12980         case 7:
12981         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12982                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12983                 break;
12984         case 9:
12985                 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12986                 break;
12987         }
12988
12989         intel_panel_init_backlight_funcs(dev);
12990
12991         mutex_init(&dev_priv->pps_mutex);
12992 }
12993
12994 /*
12995  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12996  * resume, or other times.  This quirk makes sure that's the case for
12997  * affected systems.
12998  */
12999 static void quirk_pipea_force(struct drm_device *dev)
13000 {
13001         struct drm_i915_private *dev_priv = dev->dev_private;
13002
13003         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13004         DRM_INFO("applying pipe a force quirk\n");
13005 }
13006
13007 static void quirk_pipeb_force(struct drm_device *dev)
13008 {
13009         struct drm_i915_private *dev_priv = dev->dev_private;
13010
13011         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13012         DRM_INFO("applying pipe b force quirk\n");
13013 }
13014
13015 /*
13016  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13017  */
13018 static void quirk_ssc_force_disable(struct drm_device *dev)
13019 {
13020         struct drm_i915_private *dev_priv = dev->dev_private;
13021         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13022         DRM_INFO("applying lvds SSC disable quirk\n");
13023 }
13024
13025 /*
13026  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13027  * brightness value
13028  */
13029 static void quirk_invert_brightness(struct drm_device *dev)
13030 {
13031         struct drm_i915_private *dev_priv = dev->dev_private;
13032         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13033         DRM_INFO("applying inverted panel brightness quirk\n");
13034 }
13035
13036 /* Some VBT's incorrectly indicate no backlight is present */
13037 static void quirk_backlight_present(struct drm_device *dev)
13038 {
13039         struct drm_i915_private *dev_priv = dev->dev_private;
13040         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13041         DRM_INFO("applying backlight present quirk\n");
13042 }
13043
13044 struct intel_quirk {
13045         int device;
13046         int subsystem_vendor;
13047         int subsystem_device;
13048         void (*hook)(struct drm_device *dev);
13049 };
13050
13051 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13052 struct intel_dmi_quirk {
13053         void (*hook)(struct drm_device *dev);
13054         const struct dmi_system_id (*dmi_id_list)[];
13055 };
13056
13057 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13058 {
13059         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13060         return 1;
13061 }
13062
13063 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13064         {
13065                 .dmi_id_list = &(const struct dmi_system_id[]) {
13066                         {
13067                                 .callback = intel_dmi_reverse_brightness,
13068                                 .ident = "NCR Corporation",
13069                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13070                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
13071                                 },
13072                         },
13073                         { }  /* terminating entry */
13074                 },
13075                 .hook = quirk_invert_brightness,
13076         },
13077 };
13078
13079 static struct intel_quirk intel_quirks[] = {
13080         /* HP Mini needs pipe A force quirk (LP: #322104) */
13081         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13082
13083         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13084         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13085
13086         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13087         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13088
13089         /* 830 needs to leave pipe A & dpll A up */
13090         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13091
13092         /* 830 needs to leave pipe B & dpll B up */
13093         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13094
13095         /* Lenovo U160 cannot use SSC on LVDS */
13096         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13097
13098         /* Sony Vaio Y cannot use SSC on LVDS */
13099         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13100
13101         /* Acer Aspire 5734Z must invert backlight brightness */
13102         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13103
13104         /* Acer/eMachines G725 */
13105         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13106
13107         /* Acer/eMachines e725 */
13108         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13109
13110         /* Acer/Packard Bell NCL20 */
13111         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13112
13113         /* Acer Aspire 4736Z */
13114         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13115
13116         /* Acer Aspire 5336 */
13117         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13118
13119         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13120         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13121
13122         /* Acer C720 Chromebook (Core i3 4005U) */
13123         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13124
13125         /* Apple Macbook 2,1 (Core 2 T7400) */
13126         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13127
13128         /* Toshiba CB35 Chromebook (Celeron 2955U) */
13129         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13130
13131         /* HP Chromebook 14 (Celeron 2955U) */
13132         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13133 };
13134
13135 static void intel_init_quirks(struct drm_device *dev)
13136 {
13137         struct pci_dev *d = dev->pdev;
13138         int i;
13139
13140         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13141                 struct intel_quirk *q = &intel_quirks[i];
13142
13143                 if (d->device == q->device &&
13144                     (d->subsystem_vendor == q->subsystem_vendor ||
13145                      q->subsystem_vendor == PCI_ANY_ID) &&
13146                     (d->subsystem_device == q->subsystem_device ||
13147                      q->subsystem_device == PCI_ANY_ID))
13148                         q->hook(dev);
13149         }
13150         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13151                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13152                         intel_dmi_quirks[i].hook(dev);
13153         }
13154 }
13155
13156 /* Disable the VGA plane that we never use */
13157 static void i915_disable_vga(struct drm_device *dev)
13158 {
13159         struct drm_i915_private *dev_priv = dev->dev_private;
13160         u8 sr1;
13161         u32 vga_reg = i915_vgacntrl_reg(dev);
13162
13163         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13164         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13165         outb(SR01, VGA_SR_INDEX);
13166         sr1 = inb(VGA_SR_DATA);
13167         outb(sr1 | 1<<5, VGA_SR_DATA);
13168         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13169         udelay(300);
13170
13171         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13172         POSTING_READ(vga_reg);
13173 }
13174
13175 void intel_modeset_init_hw(struct drm_device *dev)
13176 {
13177         intel_prepare_ddi(dev);
13178
13179         if (IS_VALLEYVIEW(dev))
13180                 vlv_update_cdclk(dev);
13181
13182         intel_init_clock_gating(dev);
13183
13184         intel_enable_gt_powersave(dev);
13185 }
13186
13187 void intel_modeset_init(struct drm_device *dev)
13188 {
13189         struct drm_i915_private *dev_priv = dev->dev_private;
13190         int sprite, ret;
13191         enum pipe pipe;
13192         struct intel_crtc *crtc;
13193
13194         drm_mode_config_init(dev);
13195
13196         dev->mode_config.min_width = 0;
13197         dev->mode_config.min_height = 0;
13198
13199         dev->mode_config.preferred_depth = 24;
13200         dev->mode_config.prefer_shadow = 1;
13201
13202         dev->mode_config.funcs = &intel_mode_funcs;
13203
13204         intel_init_quirks(dev);
13205
13206         intel_init_pm(dev);
13207
13208         if (INTEL_INFO(dev)->num_pipes == 0)
13209                 return;
13210
13211         intel_init_display(dev);
13212         intel_init_audio(dev);
13213
13214         if (IS_GEN2(dev)) {
13215                 dev->mode_config.max_width = 2048;
13216                 dev->mode_config.max_height = 2048;
13217         } else if (IS_GEN3(dev)) {
13218                 dev->mode_config.max_width = 4096;
13219                 dev->mode_config.max_height = 4096;
13220         } else {
13221                 dev->mode_config.max_width = 8192;
13222                 dev->mode_config.max_height = 8192;
13223         }
13224
13225         if (IS_845G(dev) || IS_I865G(dev)) {
13226                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13227                 dev->mode_config.cursor_height = 1023;
13228         } else if (IS_GEN2(dev)) {
13229                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13230                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13231         } else {
13232                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13233                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13234         }
13235
13236         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13237
13238         DRM_DEBUG_KMS("%d display pipe%s available.\n",
13239                       INTEL_INFO(dev)->num_pipes,
13240                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13241
13242         for_each_pipe(dev_priv, pipe) {
13243                 intel_crtc_init(dev, pipe);
13244                 for_each_sprite(pipe, sprite) {
13245                         ret = intel_plane_init(dev, pipe, sprite);
13246                         if (ret)
13247                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13248                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13249                 }
13250         }
13251
13252         intel_init_dpio(dev);
13253
13254         intel_shared_dpll_init(dev);
13255
13256         /* Just disable it once at startup */
13257         i915_disable_vga(dev);
13258         intel_setup_outputs(dev);
13259
13260         /* Just in case the BIOS is doing something questionable. */
13261         intel_fbc_disable(dev);
13262
13263         drm_modeset_lock_all(dev);
13264         intel_modeset_setup_hw_state(dev, false);
13265         drm_modeset_unlock_all(dev);
13266
13267         for_each_intel_crtc(dev, crtc) {
13268                 if (!crtc->active)
13269                         continue;
13270
13271                 /*
13272                  * Note that reserving the BIOS fb up front prevents us
13273                  * from stuffing other stolen allocations like the ring
13274                  * on top.  This prevents some ugliness at boot time, and
13275                  * can even allow for smooth boot transitions if the BIOS
13276                  * fb is large enough for the active pipe configuration.
13277                  */
13278                 if (dev_priv->display.get_initial_plane_config) {
13279                         dev_priv->display.get_initial_plane_config(crtc,
13280                                                            &crtc->plane_config);
13281                         /*
13282                          * If the fb is shared between multiple heads, we'll
13283                          * just get the first one.
13284                          */
13285                         intel_find_plane_obj(crtc, &crtc->plane_config);
13286                 }
13287         }
13288 }
13289
13290 static void intel_enable_pipe_a(struct drm_device *dev)
13291 {
13292         struct intel_connector *connector;
13293         struct drm_connector *crt = NULL;
13294         struct intel_load_detect_pipe load_detect_temp;
13295         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13296
13297         /* We can't just switch on the pipe A, we need to set things up with a
13298          * proper mode and output configuration. As a gross hack, enable pipe A
13299          * by enabling the load detect pipe once. */
13300         list_for_each_entry(connector,
13301                             &dev->mode_config.connector_list,
13302                             base.head) {
13303                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13304                         crt = &connector->base;
13305                         break;
13306                 }
13307         }
13308
13309         if (!crt)
13310                 return;
13311
13312         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13313                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13314 }
13315
13316 static bool
13317 intel_check_plane_mapping(struct intel_crtc *crtc)
13318 {
13319         struct drm_device *dev = crtc->base.dev;
13320         struct drm_i915_private *dev_priv = dev->dev_private;
13321         u32 reg, val;
13322
13323         if (INTEL_INFO(dev)->num_pipes == 1)
13324                 return true;
13325
13326         reg = DSPCNTR(!crtc->plane);
13327         val = I915_READ(reg);
13328
13329         if ((val & DISPLAY_PLANE_ENABLE) &&
13330             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13331                 return false;
13332
13333         return true;
13334 }
13335
13336 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13337 {
13338         struct drm_device *dev = crtc->base.dev;
13339         struct drm_i915_private *dev_priv = dev->dev_private;
13340         u32 reg;
13341
13342         /* Clear any frame start delays used for debugging left by the BIOS */
13343         reg = PIPECONF(crtc->config->cpu_transcoder);
13344         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13345
13346         /* restore vblank interrupts to correct state */
13347         if (crtc->active) {
13348                 update_scanline_offset(crtc);
13349                 drm_vblank_on(dev, crtc->pipe);
13350         } else
13351                 drm_vblank_off(dev, crtc->pipe);
13352
13353         /* We need to sanitize the plane -> pipe mapping first because this will
13354          * disable the crtc (and hence change the state) if it is wrong. Note
13355          * that gen4+ has a fixed plane -> pipe mapping.  */
13356         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13357                 struct intel_connector *connector;
13358                 bool plane;
13359
13360                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13361                               crtc->base.base.id);
13362
13363                 /* Pipe has the wrong plane attached and the plane is active.
13364                  * Temporarily change the plane mapping and disable everything
13365                  * ...  */
13366                 plane = crtc->plane;
13367                 crtc->plane = !plane;
13368                 crtc->primary_enabled = true;
13369                 dev_priv->display.crtc_disable(&crtc->base);
13370                 crtc->plane = plane;
13371
13372                 /* ... and break all links. */
13373                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13374                                     base.head) {
13375                         if (connector->encoder->base.crtc != &crtc->base)
13376                                 continue;
13377
13378                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13379                         connector->base.encoder = NULL;
13380                 }
13381                 /* multiple connectors may have the same encoder:
13382                  *  handle them and break crtc link separately */
13383                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13384                                     base.head)
13385                         if (connector->encoder->base.crtc == &crtc->base) {
13386                                 connector->encoder->base.crtc = NULL;
13387                                 connector->encoder->connectors_active = false;
13388                         }
13389
13390                 WARN_ON(crtc->active);
13391                 crtc->base.enabled = false;
13392         }
13393
13394         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13395             crtc->pipe == PIPE_A && !crtc->active) {
13396                 /* BIOS forgot to enable pipe A, this mostly happens after
13397                  * resume. Force-enable the pipe to fix this, the update_dpms
13398                  * call below we restore the pipe to the right state, but leave
13399                  * the required bits on. */
13400                 intel_enable_pipe_a(dev);
13401         }
13402
13403         /* Adjust the state of the output pipe according to whether we
13404          * have active connectors/encoders. */
13405         intel_crtc_update_dpms(&crtc->base);
13406
13407         if (crtc->active != crtc->base.enabled) {
13408                 struct intel_encoder *encoder;
13409
13410                 /* This can happen either due to bugs in the get_hw_state
13411                  * functions or because the pipe is force-enabled due to the
13412                  * pipe A quirk. */
13413                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13414                               crtc->base.base.id,
13415                               crtc->base.enabled ? "enabled" : "disabled",
13416                               crtc->active ? "enabled" : "disabled");
13417
13418                 crtc->base.enabled = crtc->active;
13419
13420                 /* Because we only establish the connector -> encoder ->
13421                  * crtc links if something is active, this means the
13422                  * crtc is now deactivated. Break the links. connector
13423                  * -> encoder links are only establish when things are
13424                  *  actually up, hence no need to break them. */
13425                 WARN_ON(crtc->active);
13426
13427                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13428                         WARN_ON(encoder->connectors_active);
13429                         encoder->base.crtc = NULL;
13430                 }
13431         }
13432
13433         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13434                 /*
13435                  * We start out with underrun reporting disabled to avoid races.
13436                  * For correct bookkeeping mark this on active crtcs.
13437                  *
13438                  * Also on gmch platforms we dont have any hardware bits to
13439                  * disable the underrun reporting. Which means we need to start
13440                  * out with underrun reporting disabled also on inactive pipes,
13441                  * since otherwise we'll complain about the garbage we read when
13442                  * e.g. coming up after runtime pm.
13443                  *
13444                  * No protection against concurrent access is required - at
13445                  * worst a fifo underrun happens which also sets this to false.
13446                  */
13447                 crtc->cpu_fifo_underrun_disabled = true;
13448                 crtc->pch_fifo_underrun_disabled = true;
13449         }
13450 }
13451
13452 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13453 {
13454         struct intel_connector *connector;
13455         struct drm_device *dev = encoder->base.dev;
13456
13457         /* We need to check both for a crtc link (meaning that the
13458          * encoder is active and trying to read from a pipe) and the
13459          * pipe itself being active. */
13460         bool has_active_crtc = encoder->base.crtc &&
13461                 to_intel_crtc(encoder->base.crtc)->active;
13462
13463         if (encoder->connectors_active && !has_active_crtc) {
13464                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13465                               encoder->base.base.id,
13466                               encoder->base.name);
13467
13468                 /* Connector is active, but has no active pipe. This is
13469                  * fallout from our resume register restoring. Disable
13470                  * the encoder manually again. */
13471                 if (encoder->base.crtc) {
13472                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13473                                       encoder->base.base.id,
13474                                       encoder->base.name);
13475                         encoder->disable(encoder);
13476                         if (encoder->post_disable)
13477                                 encoder->post_disable(encoder);
13478                 }
13479                 encoder->base.crtc = NULL;
13480                 encoder->connectors_active = false;
13481
13482                 /* Inconsistent output/port/pipe state happens presumably due to
13483                  * a bug in one of the get_hw_state functions. Or someplace else
13484                  * in our code, like the register restore mess on resume. Clamp
13485                  * things to off as a safer default. */
13486                 list_for_each_entry(connector,
13487                                     &dev->mode_config.connector_list,
13488                                     base.head) {
13489                         if (connector->encoder != encoder)
13490                                 continue;
13491                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13492                         connector->base.encoder = NULL;
13493                 }
13494         }
13495         /* Enabled encoders without active connectors will be fixed in
13496          * the crtc fixup. */
13497 }
13498
13499 void i915_redisable_vga_power_on(struct drm_device *dev)
13500 {
13501         struct drm_i915_private *dev_priv = dev->dev_private;
13502         u32 vga_reg = i915_vgacntrl_reg(dev);
13503
13504         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13505                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13506                 i915_disable_vga(dev);
13507         }
13508 }
13509
13510 void i915_redisable_vga(struct drm_device *dev)
13511 {
13512         struct drm_i915_private *dev_priv = dev->dev_private;
13513
13514         /* This function can be called both from intel_modeset_setup_hw_state or
13515          * at a very early point in our resume sequence, where the power well
13516          * structures are not yet restored. Since this function is at a very
13517          * paranoid "someone might have enabled VGA while we were not looking"
13518          * level, just check if the power well is enabled instead of trying to
13519          * follow the "don't touch the power well if we don't need it" policy
13520          * the rest of the driver uses. */
13521         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13522                 return;
13523
13524         i915_redisable_vga_power_on(dev);
13525 }
13526
13527 static bool primary_get_hw_state(struct intel_crtc *crtc)
13528 {
13529         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13530
13531         if (!crtc->active)
13532                 return false;
13533
13534         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13535 }
13536
13537 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13538 {
13539         struct drm_i915_private *dev_priv = dev->dev_private;
13540         enum pipe pipe;
13541         struct intel_crtc *crtc;
13542         struct intel_encoder *encoder;
13543         struct intel_connector *connector;
13544         int i;
13545
13546         for_each_intel_crtc(dev, crtc) {
13547                 memset(crtc->config, 0, sizeof(*crtc->config));
13548
13549                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13550
13551                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13552                                                                  crtc->config);
13553
13554                 crtc->base.enabled = crtc->active;
13555                 crtc->primary_enabled = primary_get_hw_state(crtc);
13556
13557                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13558                               crtc->base.base.id,
13559                               crtc->active ? "enabled" : "disabled");
13560         }
13561
13562         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13563                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13564
13565                 pll->on = pll->get_hw_state(dev_priv, pll,
13566                                             &pll->config.hw_state);
13567                 pll->active = 0;
13568                 pll->config.crtc_mask = 0;
13569                 for_each_intel_crtc(dev, crtc) {
13570                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13571                                 pll->active++;
13572                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13573                         }
13574                 }
13575
13576                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13577                               pll->name, pll->config.crtc_mask, pll->on);
13578
13579                 if (pll->config.crtc_mask)
13580                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13581         }
13582
13583         for_each_intel_encoder(dev, encoder) {
13584                 pipe = 0;
13585
13586                 if (encoder->get_hw_state(encoder, &pipe)) {
13587                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13588                         encoder->base.crtc = &crtc->base;
13589                         encoder->get_config(encoder, crtc->config);
13590                 } else {
13591                         encoder->base.crtc = NULL;
13592                 }
13593
13594                 encoder->connectors_active = false;
13595                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13596                               encoder->base.base.id,
13597                               encoder->base.name,
13598                               encoder->base.crtc ? "enabled" : "disabled",
13599                               pipe_name(pipe));
13600         }
13601
13602         list_for_each_entry(connector, &dev->mode_config.connector_list,
13603                             base.head) {
13604                 if (connector->get_hw_state(connector)) {
13605                         connector->base.dpms = DRM_MODE_DPMS_ON;
13606                         connector->encoder->connectors_active = true;
13607                         connector->base.encoder = &connector->encoder->base;
13608                 } else {
13609                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13610                         connector->base.encoder = NULL;
13611                 }
13612                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13613                               connector->base.base.id,
13614                               connector->base.name,
13615                               connector->base.encoder ? "enabled" : "disabled");
13616         }
13617 }
13618
13619 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13620  * and i915 state tracking structures. */
13621 void intel_modeset_setup_hw_state(struct drm_device *dev,
13622                                   bool force_restore)
13623 {
13624         struct drm_i915_private *dev_priv = dev->dev_private;
13625         enum pipe pipe;
13626         struct intel_crtc *crtc;
13627         struct intel_encoder *encoder;
13628         int i;
13629
13630         intel_modeset_readout_hw_state(dev);
13631
13632         /*
13633          * Now that we have the config, copy it to each CRTC struct
13634          * Note that this could go away if we move to using crtc_config
13635          * checking everywhere.
13636          */
13637         for_each_intel_crtc(dev, crtc) {
13638                 if (crtc->active && i915.fastboot) {
13639                         intel_mode_from_pipe_config(&crtc->base.mode,
13640                                                     crtc->config);
13641                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13642                                       crtc->base.base.id);
13643                         drm_mode_debug_printmodeline(&crtc->base.mode);
13644                 }
13645         }
13646
13647         /* HW state is read out, now we need to sanitize this mess. */
13648         for_each_intel_encoder(dev, encoder) {
13649                 intel_sanitize_encoder(encoder);
13650         }
13651
13652         for_each_pipe(dev_priv, pipe) {
13653                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13654                 intel_sanitize_crtc(crtc);
13655                 intel_dump_pipe_config(crtc, crtc->config,
13656                                        "[setup_hw_state]");
13657         }
13658
13659         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13660                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13661
13662                 if (!pll->on || pll->active)
13663                         continue;
13664
13665                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13666
13667                 pll->disable(dev_priv, pll);
13668                 pll->on = false;
13669         }
13670
13671         if (IS_GEN9(dev))
13672                 skl_wm_get_hw_state(dev);
13673         else if (HAS_PCH_SPLIT(dev))
13674                 ilk_wm_get_hw_state(dev);
13675
13676         if (force_restore) {
13677                 i915_redisable_vga(dev);
13678
13679                 /*
13680                  * We need to use raw interfaces for restoring state to avoid
13681                  * checking (bogus) intermediate states.
13682                  */
13683                 for_each_pipe(dev_priv, pipe) {
13684                         struct drm_crtc *crtc =
13685                                 dev_priv->pipe_to_crtc_mapping[pipe];
13686
13687                         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13688                                        crtc->primary->fb);
13689                 }
13690         } else {
13691                 intel_modeset_update_staged_output_state(dev);
13692         }
13693
13694         intel_modeset_check_state(dev);
13695 }
13696
13697 void intel_modeset_gem_init(struct drm_device *dev)
13698 {
13699         struct drm_i915_private *dev_priv = dev->dev_private;
13700         struct drm_crtc *c;
13701         struct drm_i915_gem_object *obj;
13702
13703         mutex_lock(&dev->struct_mutex);
13704         intel_init_gt_powersave(dev);
13705         mutex_unlock(&dev->struct_mutex);
13706
13707         /*
13708          * There may be no VBT; and if the BIOS enabled SSC we can
13709          * just keep using it to avoid unnecessary flicker.  Whereas if the
13710          * BIOS isn't using it, don't assume it will work even if the VBT
13711          * indicates as much.
13712          */
13713         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13714                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13715                                                 DREF_SSC1_ENABLE);
13716
13717         intel_modeset_init_hw(dev);
13718
13719         intel_setup_overlay(dev);
13720
13721         /*
13722          * Make sure any fbs we allocated at startup are properly
13723          * pinned & fenced.  When we do the allocation it's too early
13724          * for this.
13725          */
13726         mutex_lock(&dev->struct_mutex);
13727         for_each_crtc(dev, c) {
13728                 obj = intel_fb_obj(c->primary->fb);
13729                 if (obj == NULL)
13730                         continue;
13731
13732                 if (intel_pin_and_fence_fb_obj(c->primary,
13733                                                c->primary->fb,
13734                                                NULL)) {
13735                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13736                                   to_intel_crtc(c)->pipe);
13737                         drm_framebuffer_unreference(c->primary->fb);
13738                         c->primary->fb = NULL;
13739                         update_state_fb(c->primary);
13740                 }
13741         }
13742         mutex_unlock(&dev->struct_mutex);
13743
13744         intel_backlight_register(dev);
13745 }
13746
13747 void intel_connector_unregister(struct intel_connector *intel_connector)
13748 {
13749         struct drm_connector *connector = &intel_connector->base;
13750
13751         intel_panel_destroy_backlight(connector);
13752         drm_connector_unregister(connector);
13753 }
13754
13755 void intel_modeset_cleanup(struct drm_device *dev)
13756 {
13757         struct drm_i915_private *dev_priv = dev->dev_private;
13758         struct drm_connector *connector;
13759
13760         intel_disable_gt_powersave(dev);
13761
13762         intel_backlight_unregister(dev);
13763
13764         /*
13765          * Interrupts and polling as the first thing to avoid creating havoc.
13766          * Too much stuff here (turning of connectors, ...) would
13767          * experience fancy races otherwise.
13768          */
13769         intel_irq_uninstall(dev_priv);
13770
13771         /*
13772          * Due to the hpd irq storm handling the hotplug work can re-arm the
13773          * poll handlers. Hence disable polling after hpd handling is shut down.
13774          */
13775         drm_kms_helper_poll_fini(dev);
13776
13777         mutex_lock(&dev->struct_mutex);
13778
13779         intel_unregister_dsm_handler();
13780
13781         intel_fbc_disable(dev);
13782
13783         ironlake_teardown_rc6(dev);
13784
13785         mutex_unlock(&dev->struct_mutex);
13786
13787         /* flush any delayed tasks or pending work */
13788         flush_scheduled_work();
13789
13790         /* destroy the backlight and sysfs files before encoders/connectors */
13791         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13792                 struct intel_connector *intel_connector;
13793
13794                 intel_connector = to_intel_connector(connector);
13795                 intel_connector->unregister(intel_connector);
13796         }
13797
13798         drm_mode_config_cleanup(dev);
13799
13800         intel_cleanup_overlay(dev);
13801
13802         mutex_lock(&dev->struct_mutex);
13803         intel_cleanup_gt_powersave(dev);
13804         mutex_unlock(&dev->struct_mutex);
13805 }
13806
13807 /*
13808  * Return which encoder is currently attached for connector.
13809  */
13810 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13811 {
13812         return &intel_attached_encoder(connector)->base;
13813 }
13814
13815 void intel_connector_attach_encoder(struct intel_connector *connector,
13816                                     struct intel_encoder *encoder)
13817 {
13818         connector->encoder = encoder;
13819         drm_mode_connector_attach_encoder(&connector->base,
13820                                           &encoder->base);
13821 }
13822
13823 /*
13824  * set vga decode state - true == enable VGA decode
13825  */
13826 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13827 {
13828         struct drm_i915_private *dev_priv = dev->dev_private;
13829         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13830         u16 gmch_ctrl;
13831
13832         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13833                 DRM_ERROR("failed to read control word\n");
13834                 return -EIO;
13835         }
13836
13837         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13838                 return 0;
13839
13840         if (state)
13841                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13842         else
13843                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13844
13845         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13846                 DRM_ERROR("failed to write control word\n");
13847                 return -EIO;
13848         }
13849
13850         return 0;
13851 }
13852
13853 struct intel_display_error_state {
13854
13855         u32 power_well_driver;
13856
13857         int num_transcoders;
13858
13859         struct intel_cursor_error_state {
13860                 u32 control;
13861                 u32 position;
13862                 u32 base;
13863                 u32 size;
13864         } cursor[I915_MAX_PIPES];
13865
13866         struct intel_pipe_error_state {
13867                 bool power_domain_on;
13868                 u32 source;
13869                 u32 stat;
13870         } pipe[I915_MAX_PIPES];
13871
13872         struct intel_plane_error_state {
13873                 u32 control;
13874                 u32 stride;
13875                 u32 size;
13876                 u32 pos;
13877                 u32 addr;
13878                 u32 surface;
13879                 u32 tile_offset;
13880         } plane[I915_MAX_PIPES];
13881
13882         struct intel_transcoder_error_state {
13883                 bool power_domain_on;
13884                 enum transcoder cpu_transcoder;
13885
13886                 u32 conf;
13887
13888                 u32 htotal;
13889                 u32 hblank;
13890                 u32 hsync;
13891                 u32 vtotal;
13892                 u32 vblank;
13893                 u32 vsync;
13894         } transcoder[4];
13895 };
13896
13897 struct intel_display_error_state *
13898 intel_display_capture_error_state(struct drm_device *dev)
13899 {
13900         struct drm_i915_private *dev_priv = dev->dev_private;
13901         struct intel_display_error_state *error;
13902         int transcoders[] = {
13903                 TRANSCODER_A,
13904                 TRANSCODER_B,
13905                 TRANSCODER_C,
13906                 TRANSCODER_EDP,
13907         };
13908         int i;
13909
13910         if (INTEL_INFO(dev)->num_pipes == 0)
13911                 return NULL;
13912
13913         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13914         if (error == NULL)
13915                 return NULL;
13916
13917         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13918                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13919
13920         for_each_pipe(dev_priv, i) {
13921                 error->pipe[i].power_domain_on =
13922                         __intel_display_power_is_enabled(dev_priv,
13923                                                          POWER_DOMAIN_PIPE(i));
13924                 if (!error->pipe[i].power_domain_on)
13925                         continue;
13926
13927                 error->cursor[i].control = I915_READ(CURCNTR(i));
13928                 error->cursor[i].position = I915_READ(CURPOS(i));
13929                 error->cursor[i].base = I915_READ(CURBASE(i));
13930
13931                 error->plane[i].control = I915_READ(DSPCNTR(i));
13932                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13933                 if (INTEL_INFO(dev)->gen <= 3) {
13934                         error->plane[i].size = I915_READ(DSPSIZE(i));
13935                         error->plane[i].pos = I915_READ(DSPPOS(i));
13936                 }
13937                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13938                         error->plane[i].addr = I915_READ(DSPADDR(i));
13939                 if (INTEL_INFO(dev)->gen >= 4) {
13940                         error->plane[i].surface = I915_READ(DSPSURF(i));
13941                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13942                 }
13943
13944                 error->pipe[i].source = I915_READ(PIPESRC(i));
13945
13946                 if (HAS_GMCH_DISPLAY(dev))
13947                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13948         }
13949
13950         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13951         if (HAS_DDI(dev_priv->dev))
13952                 error->num_transcoders++; /* Account for eDP. */
13953
13954         for (i = 0; i < error->num_transcoders; i++) {
13955                 enum transcoder cpu_transcoder = transcoders[i];
13956
13957                 error->transcoder[i].power_domain_on =
13958                         __intel_display_power_is_enabled(dev_priv,
13959                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13960                 if (!error->transcoder[i].power_domain_on)
13961                         continue;
13962
13963                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13964
13965                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13966                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13967                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13968                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13969                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13970                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13971                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13972         }
13973
13974         return error;
13975 }
13976
13977 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13978
13979 void
13980 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13981                                 struct drm_device *dev,
13982                                 struct intel_display_error_state *error)
13983 {
13984         struct drm_i915_private *dev_priv = dev->dev_private;
13985         int i;
13986
13987         if (!error)
13988                 return;
13989
13990         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13991         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13992                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13993                            error->power_well_driver);
13994         for_each_pipe(dev_priv, i) {
13995                 err_printf(m, "Pipe [%d]:\n", i);
13996                 err_printf(m, "  Power: %s\n",
13997                            error->pipe[i].power_domain_on ? "on" : "off");
13998                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13999                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
14000
14001                 err_printf(m, "Plane [%d]:\n", i);
14002                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
14003                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
14004                 if (INTEL_INFO(dev)->gen <= 3) {
14005                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
14006                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
14007                 }
14008                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14009                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
14010                 if (INTEL_INFO(dev)->gen >= 4) {
14011                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
14012                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
14013                 }
14014
14015                 err_printf(m, "Cursor [%d]:\n", i);
14016                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
14017                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
14018                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
14019         }
14020
14021         for (i = 0; i < error->num_transcoders; i++) {
14022                 err_printf(m, "CPU transcoder: %c\n",
14023                            transcoder_name(error->transcoder[i].cpu_transcoder));
14024                 err_printf(m, "  Power: %s\n",
14025                            error->transcoder[i].power_domain_on ? "on" : "off");
14026                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
14027                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
14028                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
14029                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
14030                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
14031                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
14032                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
14033         }
14034 }
14035
14036 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14037 {
14038         struct intel_crtc *crtc;
14039
14040         for_each_intel_crtc(dev, crtc) {
14041                 struct intel_unpin_work *work;
14042
14043                 spin_lock_irq(&dev->event_lock);
14044
14045                 work = crtc->unpin_work;
14046
14047                 if (work && work->event &&
14048                     work->event->base.file_priv == file) {
14049                         kfree(work->event);
14050                         work->event = NULL;
14051                 }
14052
14053                 spin_unlock_irq(&dev->event_lock);
14054         }
14055 }