drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic_helper.h>
  41 #include <drm/drm_dp_helper.h>
  42 #include <drm/drm_crtc_helper.h>
  43 #include <drm/drm_plane_helper.h>
  44 #include <drm/drm_rect.h>
  45 #include <linux/dma_remapping.h>
  46
  47 /* Primary plane formats supported by all gen */
  48 #define COMMON_PRIMARY_FORMATS \
  49         DRM_FORMAT_C8, \
  50         DRM_FORMAT_RGB565, \
  51         DRM_FORMAT_XRGB8888, \
  52         DRM_FORMAT_ARGB8888
  53
  54 /* Primary plane formats for gen <= 3 */
  55 static const uint32_t intel_primary_formats_gen2[] = {
  56         COMMON_PRIMARY_FORMATS,
  57         DRM_FORMAT_XRGB1555,
  58         DRM_FORMAT_ARGB1555,
  59 };
  60
  61 /* Primary plane formats for gen >= 4 */
  62 static const uint32_t intel_primary_formats_gen4[] = {
  63         COMMON_PRIMARY_FORMATS, \
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_ABGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_ARGB2101010,
  68         DRM_FORMAT_XBGR2101010,
  69         DRM_FORMAT_ABGR2101010,
  70 };
  71
  72 /* Cursor formats */
  73 static const uint32_t intel_cursor_formats[] = {
  74         DRM_FORMAT_ARGB8888,
  75 };
  76
  77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  78
  79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  80                                 struct intel_crtc_state *pipe_config);
  81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  82                                    struct intel_crtc_state *pipe_config);
  83
  84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  85                           int x, int y, struct drm_framebuffer *old_fb);
  86 static int intel_framebuffer_init(struct drm_device *dev,
  87                                   struct intel_framebuffer *ifb,
  88                                   struct drm_mode_fb_cmd2 *mode_cmd,
  89                                   struct drm_i915_gem_object *obj);
  90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  93                                          struct intel_link_m_n *m_n,
  94                                          struct intel_link_m_n *m2_n2);
  95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  98 static void vlv_prepare_pll(struct intel_crtc *crtc,
  99                             const struct intel_crtc_state *pipe_config);
 100 static void chv_prepare_pll(struct intel_crtc *crtc,
 101                             const struct intel_crtc_state *pipe_config);
 102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 104
 105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 106 {
 107         if (!connector->mst_port)
 108                 return connector->encoder;
 109         else
 110                 return &connector->mst_port->mst_encoders[pipe]->base;
 111 }
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4800000, .max = 6480000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static void vlv_clock(int refclk, intel_clock_t *clock)
 402 {
 403         clock->m = clock->m1 * clock->m2;
 404         clock->p = clock->p1 * clock->p2;
 405         if (WARN_ON(clock->n == 0 || clock->p == 0))
 406                 return;
 407         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 408         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 409 }
 410
 411 /**
 412  * Returns whether any output on the specified pipe is of the specified type
 413  */
 414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 415 {
 416         struct drm_device *dev = crtc->base.dev;
 417         struct intel_encoder *encoder;
 418
 419         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 420                 if (encoder->type == type)
 421                         return true;
 422
 423         return false;
 424 }
 425
 426 /**
 427  * Returns whether any output on the specified pipe will have the specified
 428  * type after a staged modeset is complete, i.e., the same as
 429  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 430  * encoder->crtc.
 431  */
 432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 433 {
 434         struct drm_device *dev = crtc->base.dev;
 435         struct intel_encoder *encoder;
 436
 437         for_each_intel_encoder(dev, encoder)
 438                 if (encoder->new_crtc == crtc && encoder->type == type)
 439                         return true;
 440
 441         return false;
 442 }
 443
 444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 445                                                 int refclk)
 446 {
 447         struct drm_device *dev = crtc->base.dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev)) {
 452                         if (refclk == 100000)
 453                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 454                         else
 455                                 limit = &intel_limits_ironlake_dual_lvds;
 456                 } else {
 457                         if (refclk == 100000)
 458                                 limit = &intel_limits_ironlake_single_lvds_100m;
 459                         else
 460                                 limit = &intel_limits_ironlake_single_lvds;
 461                 }
 462         } else
 463                 limit = &intel_limits_ironlake_dac;
 464
 465         return limit;
 466 }
 467
 468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 469 {
 470         struct drm_device *dev = crtc->base.dev;
 471         const intel_limit_t *limit;
 472
 473         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 474                 if (intel_is_dual_link_lvds(dev))
 475                         limit = &intel_limits_g4x_dual_channel_lvds;
 476                 else
 477                         limit = &intel_limits_g4x_single_channel_lvds;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 479                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 480                 limit = &intel_limits_g4x_hdmi;
 481         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 482                 limit = &intel_limits_g4x_sdvo;
 483         } else /* The option is for other outputs */
 484                 limit = &intel_limits_i9xx_sdvo;
 485
 486         return limit;
 487 }
 488
 489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 490 {
 491         struct drm_device *dev = crtc->base.dev;
 492         const intel_limit_t *limit;
 493
 494         if (HAS_PCH_SPLIT(dev))
 495                 limit = intel_ironlake_limit(crtc, refclk);
 496         else if (IS_G4X(dev)) {
 497                 limit = intel_g4x_limit(crtc);
 498         } else if (IS_PINEVIEW(dev)) {
 499                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 500                         limit = &intel_limits_pineview_lvds;
 501                 else
 502                         limit = &intel_limits_pineview_sdvo;
 503         } else if (IS_CHERRYVIEW(dev)) {
 504                 limit = &intel_limits_chv;
 505         } else if (IS_VALLEYVIEW(dev)) {
 506                 limit = &intel_limits_vlv;
 507         } else if (!IS_GEN2(dev)) {
 508                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 509                         limit = &intel_limits_i9xx_lvds;
 510                 else
 511                         limit = &intel_limits_i9xx_sdvo;
 512         } else {
 513                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 514                         limit = &intel_limits_i8xx_lvds;
 515                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 516                         limit = &intel_limits_i8xx_dvo;
 517                 else
 518                         limit = &intel_limits_i8xx_dac;
 519         }
 520         return limit;
 521 }
 522
 523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 524 static void pineview_clock(int refclk, intel_clock_t *clock)
 525 {
 526         clock->m = clock->m2 + 2;
 527         clock->p = clock->p1 * clock->p2;
 528         if (WARN_ON(clock->n == 0 || clock->p == 0))
 529                 return;
 530         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 531         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 532 }
 533
 534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 535 {
 536         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 537 }
 538
 539 static void i9xx_clock(int refclk, intel_clock_t *clock)
 540 {
 541         clock->m = i9xx_dpll_compute_m(clock);
 542         clock->p = clock->p1 * clock->p2;
 543         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 544                 return;
 545         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 546         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 547 }
 548
 549 static void chv_clock(int refclk, intel_clock_t *clock)
 550 {
 551         clock->m = clock->m1 * clock->m2;
 552         clock->p = clock->p1 * clock->p2;
 553         if (WARN_ON(clock->n == 0 || clock->p == 0))
 554                 return;
 555         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 556                         clock->n << 22);
 557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 558 }
 559
 560 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 561 /**
 562  * Returns whether the given set of divisors are valid for a given refclk with
 563  * the given connectors.
 564  */
 565
 566 static bool intel_PLL_is_valid(struct drm_device *dev,
 567                                const intel_limit_t *limit,
 568                                const intel_clock_t *clock)
 569 {
 570         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 571                 INTELPllInvalid("n out of range\n");
 572         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 573                 INTELPllInvalid("p1 out of range\n");
 574         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 575                 INTELPllInvalid("m2 out of range\n");
 576         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 577                 INTELPllInvalid("m1 out of range\n");
 578
 579         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 580                 if (clock->m1 <= clock->m2)
 581                         INTELPllInvalid("m1 <= m2\n");
 582
 583         if (!IS_VALLEYVIEW(dev)) {
 584                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 585                         INTELPllInvalid("p out of range\n");
 586                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 587                         INTELPllInvalid("m out of range\n");
 588         }
 589
 590         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 591                 INTELPllInvalid("vco out of range\n");
 592         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 593          * connector, etc., rather than just a single range.
 594          */
 595         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 596                 INTELPllInvalid("dot out of range\n");
 597
 598         return true;
 599 }
 600
 601 static bool
 602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 603                     int target, int refclk, intel_clock_t *match_clock,
 604                     intel_clock_t *best_clock)
 605 {
 606         struct drm_device *dev = crtc->base.dev;
 607         intel_clock_t clock;
 608         int err = target;
 609
 610         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 611                 /*
 612                  * For LVDS just rely on its current settings for dual-channel.
 613                  * We haven't figured out how to reliably set up different
 614                  * single/dual channel state, if we even can.
 615                  */
 616                 if (intel_is_dual_link_lvds(dev))
 617                         clock.p2 = limit->p2.p2_fast;
 618                 else
 619                         clock.p2 = limit->p2.p2_slow;
 620         } else {
 621                 if (target < limit->p2.dot_limit)
 622                         clock.p2 = limit->p2.p2_slow;
 623                 else
 624                         clock.p2 = limit->p2.p2_fast;
 625         }
 626
 627         memset(best_clock, 0, sizeof(*best_clock));
 628
 629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 630              clock.m1++) {
 631                 for (clock.m2 = limit->m2.min;
 632                      clock.m2 <= limit->m2.max; clock.m2++) {
 633                         if (clock.m2 >= clock.m1)
 634                                 break;
 635                         for (clock.n = limit->n.min;
 636                              clock.n <= limit->n.max; clock.n++) {
 637                                 for (clock.p1 = limit->p1.min;
 638                                         clock.p1 <= limit->p1.max; clock.p1++) {
 639                                         int this_err;
 640
 641                                         i9xx_clock(refclk, &clock);
 642                                         if (!intel_PLL_is_valid(dev, limit,
 643                                                                 &clock))
 644                                                 continue;
 645                                         if (match_clock &&
 646                                             clock.p != match_clock->p)
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err) {
 651                                                 *best_clock = clock;
 652                                                 err = this_err;
 653                                         }
 654                                 }
 655                         }
 656                 }
 657         }
 658
 659         return (err != target);
 660 }
 661
 662 static bool
 663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 664                    int target, int refclk, intel_clock_t *match_clock,
 665                    intel_clock_t *best_clock)
 666 {
 667         struct drm_device *dev = crtc->base.dev;
 668         intel_clock_t clock;
 669         int err = target;
 670
 671         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 672                 /*
 673                  * For LVDS just rely on its current settings for dual-channel.
 674                  * We haven't figured out how to reliably set up different
 675                  * single/dual channel state, if we even can.
 676                  */
 677                 if (intel_is_dual_link_lvds(dev))
 678                         clock.p2 = limit->p2.p2_fast;
 679                 else
 680                         clock.p2 = limit->p2.p2_slow;
 681         } else {
 682                 if (target < limit->p2.dot_limit)
 683                         clock.p2 = limit->p2.p2_slow;
 684                 else
 685                         clock.p2 = limit->p2.p2_fast;
 686         }
 687
 688         memset(best_clock, 0, sizeof(*best_clock));
 689
 690         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 691              clock.m1++) {
 692                 for (clock.m2 = limit->m2.min;
 693                      clock.m2 <= limit->m2.max; clock.m2++) {
 694                         for (clock.n = limit->n.min;
 695                              clock.n <= limit->n.max; clock.n++) {
 696                                 for (clock.p1 = limit->p1.min;
 697                                         clock.p1 <= limit->p1.max; clock.p1++) {
 698                                         int this_err;
 699
 700                                         pineview_clock(refclk, &clock);
 701                                         if (!intel_PLL_is_valid(dev, limit,
 702                                                                 &clock))
 703                                                 continue;
 704                                         if (match_clock &&
 705                                             clock.p != match_clock->p)
 706                                                 continue;
 707
 708                                         this_err = abs(clock.dot - target);
 709                                         if (this_err < err) {
 710                                                 *best_clock = clock;
 711                                                 err = this_err;
 712                                         }
 713                                 }
 714                         }
 715                 }
 716         }
 717
 718         return (err != target);
 719 }
 720
 721 static bool
 722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 723                    int target, int refclk, intel_clock_t *match_clock,
 724                    intel_clock_t *best_clock)
 725 {
 726         struct drm_device *dev = crtc->base.dev;
 727         intel_clock_t clock;
 728         int max_n;
 729         bool found;
 730         /* approximately equals target * 0.00585 */
 731         int err_most = (target >> 8) + (target >> 9);
 732         found = false;
 733
 734         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 735                 if (intel_is_dual_link_lvds(dev))
 736                         clock.p2 = limit->p2.p2_fast;
 737                 else
 738                         clock.p2 = limit->p2.p2_slow;
 739         } else {
 740                 if (target < limit->p2.dot_limit)
 741                         clock.p2 = limit->p2.p2_slow;
 742                 else
 743                         clock.p2 = limit->p2.p2_fast;
 744         }
 745
 746         memset(best_clock, 0, sizeof(*best_clock));
 747         max_n = limit->n.max;
 748         /* based on hardware requirement, prefer smaller n to precision */
 749         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 750                 /* based on hardware requirement, prefere larger m1,m2 */
 751                 for (clock.m1 = limit->m1.max;
 752                      clock.m1 >= limit->m1.min; clock.m1--) {
 753                         for (clock.m2 = limit->m2.max;
 754                              clock.m2 >= limit->m2.min; clock.m2--) {
 755                                 for (clock.p1 = limit->p1.max;
 756                                      clock.p1 >= limit->p1.min; clock.p1--) {
 757                                         int this_err;
 758
 759                                         i9xx_clock(refclk, &clock);
 760                                         if (!intel_PLL_is_valid(dev, limit,
 761                                                                 &clock))
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err_most) {
 766                                                 *best_clock = clock;
 767                                                 err_most = this_err;
 768                                                 max_n = clock.n;
 769                                                 found = true;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775         return found;
 776 }
 777
 778 static bool
 779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 780                    int target, int refclk, intel_clock_t *match_clock,
 781                    intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->base.dev;
 784         intel_clock_t clock;
 785         unsigned int bestppm = 1000000;
 786         /* min update 19.2 MHz */
 787         int max_n = min(limit->n.max, refclk / 19200);
 788         bool found = false;
 789
 790         target *= 5; /* fast clock */
 791
 792         memset(best_clock, 0, sizeof(*best_clock));
 793
 794         /* based on hardware requirement, prefer smaller n to precision */
 795         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 796                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 797                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 798                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 799                                 clock.p = clock.p1 * clock.p2;
 800                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 801                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 802                                         unsigned int ppm, diff;
 803
 804                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 805                                                                      refclk * clock.m1);
 806
 807                                         vlv_clock(refclk, &clock);
 808
 809                                         if (!intel_PLL_is_valid(dev, limit,
 810                                                                 &clock))
 811                                                 continue;
 812
 813                                         diff = abs(clock.dot - target);
 814                                         ppm = div_u64(1000000ULL * diff, target);
 815
 816                                         if (ppm < 100 && clock.p > best_clock->p) {
 817                                                 bestppm = 0;
 818                                                 *best_clock = clock;
 819                                                 found = true;
 820                                         }
 821
 822                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 823                                                 bestppm = ppm;
 824                                                 *best_clock = clock;
 825                                                 found = true;
 826                                         }
 827                                 }
 828                         }
 829                 }
 830         }
 831
 832         return found;
 833 }
 834
 835 static bool
 836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 837                    int target, int refclk, intel_clock_t *match_clock,
 838                    intel_clock_t *best_clock)
 839 {
 840         struct drm_device *dev = crtc->base.dev;
 841         intel_clock_t clock;
 842         uint64_t m2;
 843         int found = false;
 844
 845         memset(best_clock, 0, sizeof(*best_clock));
 846
 847         /*
 848          * Based on hardware doc, the n always set to 1, and m1 always
 849          * set to 2.  If requires to support 200Mhz refclk, we need to
 850          * revisit this because n may not 1 anymore.
 851          */
 852         clock.n = 1, clock.m1 = 2;
 853         target *= 5;    /* fast clock */
 854
 855         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 856                 for (clock.p2 = limit->p2.p2_fast;
 857                                 clock.p2 >= limit->p2.p2_slow;
 858                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 859
 860                         clock.p = clock.p1 * clock.p2;
 861
 862                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 863                                         clock.n) << 22, refclk * clock.m1);
 864
 865                         if (m2 > INT_MAX/clock.m1)
 866                                 continue;
 867
 868                         clock.m2 = m2;
 869
 870                         chv_clock(refclk, &clock);
 871
 872                         if (!intel_PLL_is_valid(dev, limit, &clock))
 873                                 continue;
 874
 875                         /* based on hardware requirement, prefer bigger p
 876                          */
 877                         if (clock.p > best_clock->p) {
 878                                 *best_clock = clock;
 879                                 found = true;
 880                         }
 881                 }
 882         }
 883
 884         return found;
 885 }
 886
 887 bool intel_crtc_active(struct drm_crtc *crtc)
 888 {
 889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 890
 891         /* Be paranoid as we can arrive here with only partial
 892          * state retrieved from the hardware during setup.
 893          *
 894          * We can ditch the adjusted_mode.crtc_clock check as soon
 895          * as Haswell has gained clock readout/fastboot support.
 896          *
 897          * We can ditch the crtc->primary->fb check as soon as we can
 898          * properly reconstruct framebuffers.
 899          *
 900          * FIXME: The intel_crtc->active here should be switched to
 901          * crtc->state->active once we have proper CRTC states wired up
 902          * for atomic.
 903          */
 904         return intel_crtc->active && crtc->primary->state->fb &&
 905                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 906 }
 907
 908 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 909                                              enum pipe pipe)
 910 {
 911         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 913
 914         return intel_crtc->config->cpu_transcoder;
 915 }
 916
 917 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 918 {
 919         struct drm_i915_private *dev_priv = dev->dev_private;
 920         u32 reg = PIPEDSL(pipe);
 921         u32 line1, line2;
 922         u32 line_mask;
 923
 924         if (IS_GEN2(dev))
 925                 line_mask = DSL_LINEMASK_GEN2;
 926         else
 927                 line_mask = DSL_LINEMASK_GEN3;
 928
 929         line1 = I915_READ(reg) & line_mask;
 930         mdelay(5);
 931         line2 = I915_READ(reg) & line_mask;
 932
 933         return line1 == line2;
 934 }
 935
 936 /*
 937  * intel_wait_for_pipe_off - wait for pipe to turn off
 938  * @crtc: crtc whose pipe to wait for
 939  *
 940  * After disabling a pipe, we can't wait for vblank in the usual way,
 941  * spinning on the vblank interrupt status bit, since we won't actually
 942  * see an interrupt when the pipe is disabled.
 943  *
 944  * On Gen4 and above:
 945  *   wait for the pipe register state bit to turn off
 946  *
 947  * Otherwise:
 948  *   wait for the display line value to settle (it usually
 949  *   ends up stopping at the start of the next frame).
 950  *
 951  */
 952 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 953 {
 954         struct drm_device *dev = crtc->base.dev;
 955         struct drm_i915_private *dev_priv = dev->dev_private;
 956         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
 957         enum pipe pipe = crtc->pipe;
 958
 959         if (INTEL_INFO(dev)->gen >= 4) {
 960                 int reg = PIPECONF(cpu_transcoder);
 961
 962                 /* Wait for the Pipe State to go off */
 963                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 964                              100))
 965                         WARN(1, "pipe_off wait timed out\n");
 966         } else {
 967                 /* Wait for the display line to settle */
 968                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 969                         WARN(1, "pipe_off wait timed out\n");
 970         }
 971 }
 972
 973 /*
 974  * ibx_digital_port_connected - is the specified port connected?
 975  * @dev_priv: i915 private structure
 976  * @port: the port to test
 977  *
 978  * Returns true if @port is connected, false otherwise.
 979  */
 980 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 981                                 struct intel_digital_port *port)
 982 {
 983         u32 bit;
 984
 985         if (HAS_PCH_IBX(dev_priv->dev)) {
 986                 switch (port->port) {
 987                 case PORT_B:
 988                         bit = SDE_PORTB_HOTPLUG;
 989                         break;
 990                 case PORT_C:
 991                         bit = SDE_PORTC_HOTPLUG;
 992                         break;
 993                 case PORT_D:
 994                         bit = SDE_PORTD_HOTPLUG;
 995                         break;
 996                 default:
 997                         return true;
 998                 }
 999         } else {
1000                 switch (port->port) {
1001                 case PORT_B:
1002                         bit = SDE_PORTB_HOTPLUG_CPT;
1003                         break;
1004                 case PORT_C:
1005                         bit = SDE_PORTC_HOTPLUG_CPT;
1006                         break;
1007                 case PORT_D:
1008                         bit = SDE_PORTD_HOTPLUG_CPT;
1009                         break;
1010                 default:
1011                         return true;
1012                 }
1013         }
1014
1015         return I915_READ(SDEISR) & bit;
1016 }
1017
1018 static const char *state_string(bool enabled)
1019 {
1020         return enabled ? "on" : "off";
1021 }
1022
1023 /* Only for pre-ILK configs */
1024 void assert_pll(struct drm_i915_private *dev_priv,
1025                 enum pipe pipe, bool state)
1026 {
1027         int reg;
1028         u32 val;
1029         bool cur_state;
1030
1031         reg = DPLL(pipe);
1032         val = I915_READ(reg);
1033         cur_state = !!(val & DPLL_VCO_ENABLE);
1034         I915_STATE_WARN(cur_state != state,
1035              "PLL state assertion failure (expected %s, current %s)\n",
1036              state_string(state), state_string(cur_state));
1037 }
1038
1039 /* XXX: the dsi pll is shared between MIPI DSI ports */
1040 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1041 {
1042         u32 val;
1043         bool cur_state;
1044
1045         mutex_lock(&dev_priv->dpio_lock);
1046         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1047         mutex_unlock(&dev_priv->dpio_lock);
1048
1049         cur_state = val & DSI_PLL_VCO_EN;
1050         I915_STATE_WARN(cur_state != state,
1051              "DSI PLL state assertion failure (expected %s, current %s)\n",
1052              state_string(state), state_string(cur_state));
1053 }
1054 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1055 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1056
1057 struct intel_shared_dpll *
1058 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1059 {
1060         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1061
1062         if (crtc->config->shared_dpll < 0)
1063                 return NULL;
1064
1065         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1066 }
1067
1068 /* For ILK+ */
1069 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1070                         struct intel_shared_dpll *pll,
1071                         bool state)
1072 {
1073         bool cur_state;
1074         struct intel_dpll_hw_state hw_state;
1075
1076         if (WARN (!pll,
1077                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1078                 return;
1079
1080         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1081         I915_STATE_WARN(cur_state != state,
1082              "%s assertion failure (expected %s, current %s)\n",
1083              pll->name, state_string(state), state_string(cur_state));
1084 }
1085
1086 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1087                           enum pipe pipe, bool state)
1088 {
1089         int reg;
1090         u32 val;
1091         bool cur_state;
1092         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1093                                                                       pipe);
1094
1095         if (HAS_DDI(dev_priv->dev)) {
1096                 /* DDI does not have a specific FDI_TX register */
1097                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1098                 val = I915_READ(reg);
1099                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1100         } else {
1101                 reg = FDI_TX_CTL(pipe);
1102                 val = I915_READ(reg);
1103                 cur_state = !!(val & FDI_TX_ENABLE);
1104         }
1105         I915_STATE_WARN(cur_state != state,
1106              "FDI TX state assertion failure (expected %s, current %s)\n",
1107              state_string(state), state_string(cur_state));
1108 }
1109 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1110 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1111
1112 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1113                           enum pipe pipe, bool state)
1114 {
1115         int reg;
1116         u32 val;
1117         bool cur_state;
1118
1119         reg = FDI_RX_CTL(pipe);
1120         val = I915_READ(reg);
1121         cur_state = !!(val & FDI_RX_ENABLE);
1122         I915_STATE_WARN(cur_state != state,
1123              "FDI RX state assertion failure (expected %s, current %s)\n",
1124              state_string(state), state_string(cur_state));
1125 }
1126 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1127 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1128
1129 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1130                                       enum pipe pipe)
1131 {
1132         int reg;
1133         u32 val;
1134
1135         /* ILK FDI PLL is always enabled */
1136         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1137                 return;
1138
1139         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1140         if (HAS_DDI(dev_priv->dev))
1141                 return;
1142
1143         reg = FDI_TX_CTL(pipe);
1144         val = I915_READ(reg);
1145         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1146 }
1147
1148 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1149                        enum pipe pipe, bool state)
1150 {
1151         int reg;
1152         u32 val;
1153         bool cur_state;
1154
1155         reg = FDI_RX_CTL(pipe);
1156         val = I915_READ(reg);
1157         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1158         I915_STATE_WARN(cur_state != state,
1159              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1160              state_string(state), state_string(cur_state));
1161 }
1162
1163 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1164                            enum pipe pipe)
1165 {
1166         struct drm_device *dev = dev_priv->dev;
1167         int pp_reg;
1168         u32 val;
1169         enum pipe panel_pipe = PIPE_A;
1170         bool locked = true;
1171
1172         if (WARN_ON(HAS_DDI(dev)))
1173                 return;
1174
1175         if (HAS_PCH_SPLIT(dev)) {
1176                 u32 port_sel;
1177
1178                 pp_reg = PCH_PP_CONTROL;
1179                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1180
1181                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1182                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1183                         panel_pipe = PIPE_B;
1184                 /* XXX: else fix for eDP */
1185         } else if (IS_VALLEYVIEW(dev)) {
1186                 /* presumably write lock depends on pipe, not port select */
1187                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1188                 panel_pipe = pipe;
1189         } else {
1190                 pp_reg = PP_CONTROL;
1191                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1192                         panel_pipe = PIPE_B;
1193         }
1194
1195         val = I915_READ(pp_reg);
1196         if (!(val & PANEL_POWER_ON) ||
1197             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1198                 locked = false;
1199
1200         I915_STATE_WARN(panel_pipe == pipe && locked,
1201              "panel assertion failure, pipe %c regs locked\n",
1202              pipe_name(pipe));
1203 }
1204
1205 static void assert_cursor(struct drm_i915_private *dev_priv,
1206                           enum pipe pipe, bool state)
1207 {
1208         struct drm_device *dev = dev_priv->dev;
1209         bool cur_state;
1210
1211         if (IS_845G(dev) || IS_I865G(dev))
1212                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1213         else
1214                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1215
1216         I915_STATE_WARN(cur_state != state,
1217              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1218              pipe_name(pipe), state_string(state), state_string(cur_state));
1219 }
1220 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1221 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1222
1223 void assert_pipe(struct drm_i915_private *dev_priv,
1224                  enum pipe pipe, bool state)
1225 {
1226         int reg;
1227         u32 val;
1228         bool cur_state;
1229         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1230                                                                       pipe);
1231
1232         /* if we need the pipe quirk it must be always on */
1233         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1234             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1235                 state = true;
1236
1237         if (!intel_display_power_is_enabled(dev_priv,
1238                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1239                 cur_state = false;
1240         } else {
1241                 reg = PIPECONF(cpu_transcoder);
1242                 val = I915_READ(reg);
1243                 cur_state = !!(val & PIPECONF_ENABLE);
1244         }
1245
1246         I915_STATE_WARN(cur_state != state,
1247              "pipe %c assertion failure (expected %s, current %s)\n",
1248              pipe_name(pipe), state_string(state), state_string(cur_state));
1249 }
1250
1251 static void assert_plane(struct drm_i915_private *dev_priv,
1252                          enum plane plane, bool state)
1253 {
1254         int reg;
1255         u32 val;
1256         bool cur_state;
1257
1258         reg = DSPCNTR(plane);
1259         val = I915_READ(reg);
1260         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1261         I915_STATE_WARN(cur_state != state,
1262              "plane %c assertion failure (expected %s, current %s)\n",
1263              plane_name(plane), state_string(state), state_string(cur_state));
1264 }
1265
1266 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1267 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1268
1269 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1270                                    enum pipe pipe)
1271 {
1272         struct drm_device *dev = dev_priv->dev;
1273         int reg, i;
1274         u32 val;
1275         int cur_pipe;
1276
1277         /* Primary planes are fixed to pipes on gen4+ */
1278         if (INTEL_INFO(dev)->gen >= 4) {
1279                 reg = DSPCNTR(pipe);
1280                 val = I915_READ(reg);
1281                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1282                      "plane %c assertion failure, should be disabled but not\n",
1283                      plane_name(pipe));
1284                 return;
1285         }
1286
1287         /* Need to check both planes against the pipe */
1288         for_each_pipe(dev_priv, i) {
1289                 reg = DSPCNTR(i);
1290                 val = I915_READ(reg);
1291                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1292                         DISPPLANE_SEL_PIPE_SHIFT;
1293                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1294                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1295                      plane_name(i), pipe_name(pipe));
1296         }
1297 }
1298
1299 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1300                                     enum pipe pipe)
1301 {
1302         struct drm_device *dev = dev_priv->dev;
1303         int reg, sprite;
1304         u32 val;
1305
1306         if (INTEL_INFO(dev)->gen >= 9) {
1307                 for_each_sprite(dev_priv, pipe, sprite) {
1308                         val = I915_READ(PLANE_CTL(pipe, sprite));
1309                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1310                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1311                              sprite, pipe_name(pipe));
1312                 }
1313         } else if (IS_VALLEYVIEW(dev)) {
1314                 for_each_sprite(dev_priv, pipe, sprite) {
1315                         reg = SPCNTR(pipe, sprite);
1316                         val = I915_READ(reg);
1317                         I915_STATE_WARN(val & SP_ENABLE,
1318                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                              sprite_name(pipe, sprite), pipe_name(pipe));
1320                 }
1321         } else if (INTEL_INFO(dev)->gen >= 7) {
1322                 reg = SPRCTL(pipe);
1323                 val = I915_READ(reg);
1324                 I915_STATE_WARN(val & SPRITE_ENABLE,
1325                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1326                      plane_name(pipe), pipe_name(pipe));
1327         } else if (INTEL_INFO(dev)->gen >= 5) {
1328                 reg = DVSCNTR(pipe);
1329                 val = I915_READ(reg);
1330                 I915_STATE_WARN(val & DVS_ENABLE,
1331                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1332                      plane_name(pipe), pipe_name(pipe));
1333         }
1334 }
1335
1336 static void assert_vblank_disabled(struct drm_crtc *crtc)
1337 {
1338         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1339                 drm_crtc_vblank_put(crtc);
1340 }
1341
1342 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1343 {
1344         u32 val;
1345         bool enabled;
1346
1347         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1348
1349         val = I915_READ(PCH_DREF_CONTROL);
1350         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1351                             DREF_SUPERSPREAD_SOURCE_MASK));
1352         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1353 }
1354
1355 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1356                                            enum pipe pipe)
1357 {
1358         int reg;
1359         u32 val;
1360         bool enabled;
1361
1362         reg = PCH_TRANSCONF(pipe);
1363         val = I915_READ(reg);
1364         enabled = !!(val & TRANS_ENABLE);
1365         I915_STATE_WARN(enabled,
1366              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1367              pipe_name(pipe));
1368 }
1369
1370 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1371                             enum pipe pipe, u32 port_sel, u32 val)
1372 {
1373         if ((val & DP_PORT_EN) == 0)
1374                 return false;
1375
1376         if (HAS_PCH_CPT(dev_priv->dev)) {
1377                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1378                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1379                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1380                         return false;
1381         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1382                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1383                         return false;
1384         } else {
1385                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1386                         return false;
1387         }
1388         return true;
1389 }
1390
1391 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1392                               enum pipe pipe, u32 val)
1393 {
1394         if ((val & SDVO_ENABLE) == 0)
1395                 return false;
1396
1397         if (HAS_PCH_CPT(dev_priv->dev)) {
1398                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1399                         return false;
1400         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1401                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1402                         return false;
1403         } else {
1404                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1405                         return false;
1406         }
1407         return true;
1408 }
1409
1410 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1411                               enum pipe pipe, u32 val)
1412 {
1413         if ((val & LVDS_PORT_EN) == 0)
1414                 return false;
1415
1416         if (HAS_PCH_CPT(dev_priv->dev)) {
1417                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1418                         return false;
1419         } else {
1420                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1421                         return false;
1422         }
1423         return true;
1424 }
1425
1426 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1427                               enum pipe pipe, u32 val)
1428 {
1429         if ((val & ADPA_DAC_ENABLE) == 0)
1430                 return false;
1431         if (HAS_PCH_CPT(dev_priv->dev)) {
1432                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1433                         return false;
1434         } else {
1435                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1436                         return false;
1437         }
1438         return true;
1439 }
1440
1441 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1442                                    enum pipe pipe, int reg, u32 port_sel)
1443 {
1444         u32 val = I915_READ(reg);
1445         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1446              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1447              reg, pipe_name(pipe));
1448
1449         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1450              && (val & DP_PIPEB_SELECT),
1451              "IBX PCH dp port still using transcoder B\n");
1452 }
1453
1454 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1455                                      enum pipe pipe, int reg)
1456 {
1457         u32 val = I915_READ(reg);
1458         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1459              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1460              reg, pipe_name(pipe));
1461
1462         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1463              && (val & SDVO_PIPE_B_SELECT),
1464              "IBX PCH hdmi port still using transcoder B\n");
1465 }
1466
1467 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1468                                       enum pipe pipe)
1469 {
1470         int reg;
1471         u32 val;
1472
1473         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1476
1477         reg = PCH_ADPA;
1478         val = I915_READ(reg);
1479         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480              "PCH VGA enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482
1483         reg = PCH_LVDS;
1484         val = I915_READ(reg);
1485         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1486              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1487              pipe_name(pipe));
1488
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1490         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1491         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1492 }
1493
1494 static void intel_init_dpio(struct drm_device *dev)
1495 {
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497
1498         if (!IS_VALLEYVIEW(dev))
1499                 return;
1500
1501         /*
1502          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1503          * CHV x1 PHY (DP/HDMI D)
1504          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1505          */
1506         if (IS_CHERRYVIEW(dev)) {
1507                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1508                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1509         } else {
1510                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1511         }
1512 }
1513
1514 static void vlv_enable_pll(struct intel_crtc *crtc,
1515                            const struct intel_crtc_state *pipe_config)
1516 {
1517         struct drm_device *dev = crtc->base.dev;
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519         int reg = DPLL(crtc->pipe);
1520         u32 dpll = pipe_config->dpll_hw_state.dpll;
1521
1522         assert_pipe_disabled(dev_priv, crtc->pipe);
1523
1524         /* No really, not for ILK+ */
1525         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1526
1527         /* PLL is protected by panel, make sure we can write it */
1528         if (IS_MOBILE(dev_priv->dev))
1529                 assert_panel_unlocked(dev_priv, crtc->pipe);
1530
1531         I915_WRITE(reg, dpll);
1532         POSTING_READ(reg);
1533         udelay(150);
1534
1535         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1536                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1537
1538         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1539         POSTING_READ(DPLL_MD(crtc->pipe));
1540
1541         /* We do this three times for luck */
1542         I915_WRITE(reg, dpll);
1543         POSTING_READ(reg);
1544         udelay(150); /* wait for warmup */
1545         I915_WRITE(reg, dpll);
1546         POSTING_READ(reg);
1547         udelay(150); /* wait for warmup */
1548         I915_WRITE(reg, dpll);
1549         POSTING_READ(reg);
1550         udelay(150); /* wait for warmup */
1551 }
1552
1553 static void chv_enable_pll(struct intel_crtc *crtc,
1554                            const struct intel_crtc_state *pipe_config)
1555 {
1556         struct drm_device *dev = crtc->base.dev;
1557         struct drm_i915_private *dev_priv = dev->dev_private;
1558         int pipe = crtc->pipe;
1559         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1560         u32 tmp;
1561
1562         assert_pipe_disabled(dev_priv, crtc->pipe);
1563
1564         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1565
1566         mutex_lock(&dev_priv->dpio_lock);
1567
1568         /* Enable back the 10bit clock to display controller */
1569         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1570         tmp |= DPIO_DCLKP_EN;
1571         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1572
1573         /*
1574          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1575          */
1576         udelay(1);
1577
1578         /* Enable PLL */
1579         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1580
1581         /* Check PLL is locked */
1582         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1583                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1584
1585         /* not sure when this should be written */
1586         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1587         POSTING_READ(DPLL_MD(pipe));
1588
1589         mutex_unlock(&dev_priv->dpio_lock);
1590 }
1591
1592 static int intel_num_dvo_pipes(struct drm_device *dev)
1593 {
1594         struct intel_crtc *crtc;
1595         int count = 0;
1596
1597         for_each_intel_crtc(dev, crtc)
1598                 count += crtc->active &&
1599                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1600
1601         return count;
1602 }
1603
1604 static void i9xx_enable_pll(struct intel_crtc *crtc)
1605 {
1606         struct drm_device *dev = crtc->base.dev;
1607         struct drm_i915_private *dev_priv = dev->dev_private;
1608         int reg = DPLL(crtc->pipe);
1609         u32 dpll = crtc->config->dpll_hw_state.dpll;
1610
1611         assert_pipe_disabled(dev_priv, crtc->pipe);
1612
1613         /* No really, not for ILK+ */
1614         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1615
1616         /* PLL is protected by panel, make sure we can write it */
1617         if (IS_MOBILE(dev) && !IS_I830(dev))
1618                 assert_panel_unlocked(dev_priv, crtc->pipe);
1619
1620         /* Enable DVO 2x clock on both PLLs if necessary */
1621         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1622                 /*
1623                  * It appears to be important that we don't enable this
1624                  * for the current pipe before otherwise configuring the
1625                  * PLL. No idea how this should be handled if multiple
1626                  * DVO outputs are enabled simultaneosly.
1627                  */
1628                 dpll |= DPLL_DVO_2X_MODE;
1629                 I915_WRITE(DPLL(!crtc->pipe),
1630                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1631         }
1632
1633         /* Wait for the clocks to stabilize. */
1634         POSTING_READ(reg);
1635         udelay(150);
1636
1637         if (INTEL_INFO(dev)->gen >= 4) {
1638                 I915_WRITE(DPLL_MD(crtc->pipe),
1639                            crtc->config->dpll_hw_state.dpll_md);
1640         } else {
1641                 /* The pixel multiplier can only be updated once the
1642                  * DPLL is enabled and the clocks are stable.
1643                  *
1644                  * So write it again.
1645                  */
1646                 I915_WRITE(reg, dpll);
1647         }
1648
1649         /* We do this three times for luck */
1650         I915_WRITE(reg, dpll);
1651         POSTING_READ(reg);
1652         udelay(150); /* wait for warmup */
1653         I915_WRITE(reg, dpll);
1654         POSTING_READ(reg);
1655         udelay(150); /* wait for warmup */
1656         I915_WRITE(reg, dpll);
1657         POSTING_READ(reg);
1658         udelay(150); /* wait for warmup */
1659 }
1660
1661 /**
1662  * i9xx_disable_pll - disable a PLL
1663  * @dev_priv: i915 private structure
1664  * @pipe: pipe PLL to disable
1665  *
1666  * Disable the PLL for @pipe, making sure the pipe is off first.
1667  *
1668  * Note!  This is for pre-ILK only.
1669  */
1670 static void i9xx_disable_pll(struct intel_crtc *crtc)
1671 {
1672         struct drm_device *dev = crtc->base.dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         enum pipe pipe = crtc->pipe;
1675
1676         /* Disable DVO 2x clock on both PLLs if necessary */
1677         if (IS_I830(dev) &&
1678             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1679             intel_num_dvo_pipes(dev) == 1) {
1680                 I915_WRITE(DPLL(PIPE_B),
1681                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1682                 I915_WRITE(DPLL(PIPE_A),
1683                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1684         }
1685
1686         /* Don't disable pipe or pipe PLLs if needed */
1687         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1688             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1689                 return;
1690
1691         /* Make sure the pipe isn't still relying on us */
1692         assert_pipe_disabled(dev_priv, pipe);
1693
1694         I915_WRITE(DPLL(pipe), 0);
1695         POSTING_READ(DPLL(pipe));
1696 }
1697
1698 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1699 {
1700         u32 val = 0;
1701
1702         /* Make sure the pipe isn't still relying on us */
1703         assert_pipe_disabled(dev_priv, pipe);
1704
1705         /*
1706          * Leave integrated clock source and reference clock enabled for pipe B.
1707          * The latter is needed for VGA hotplug / manual detection.
1708          */
1709         if (pipe == PIPE_B)
1710                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1711         I915_WRITE(DPLL(pipe), val);
1712         POSTING_READ(DPLL(pipe));
1713
1714 }
1715
1716 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1717 {
1718         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1719         u32 val;
1720
1721         /* Make sure the pipe isn't still relying on us */
1722         assert_pipe_disabled(dev_priv, pipe);
1723
1724         /* Set PLL en = 0 */
1725         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1726         if (pipe != PIPE_A)
1727                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1728         I915_WRITE(DPLL(pipe), val);
1729         POSTING_READ(DPLL(pipe));
1730
1731         mutex_lock(&dev_priv->dpio_lock);
1732
1733         /* Disable 10bit clock to display controller */
1734         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1735         val &= ~DPIO_DCLKP_EN;
1736         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1737
1738         /* disable left/right clock distribution */
1739         if (pipe != PIPE_B) {
1740                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1741                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1742                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1743         } else {
1744                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1745                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1746                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1747         }
1748
1749         mutex_unlock(&dev_priv->dpio_lock);
1750 }
1751
1752 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1753                 struct intel_digital_port *dport)
1754 {
1755         u32 port_mask;
1756         int dpll_reg;
1757
1758         switch (dport->port) {
1759         case PORT_B:
1760                 port_mask = DPLL_PORTB_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 break;
1763         case PORT_C:
1764                 port_mask = DPLL_PORTC_READY_MASK;
1765                 dpll_reg = DPLL(0);
1766                 break;
1767         case PORT_D:
1768                 port_mask = DPLL_PORTD_READY_MASK;
1769                 dpll_reg = DPIO_PHY_STATUS;
1770                 break;
1771         default:
1772                 BUG();
1773         }
1774
1775         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1776                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1777                      port_name(dport->port), I915_READ(dpll_reg));
1778 }
1779
1780 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1781 {
1782         struct drm_device *dev = crtc->base.dev;
1783         struct drm_i915_private *dev_priv = dev->dev_private;
1784         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1785
1786         if (WARN_ON(pll == NULL))
1787                 return;
1788
1789         WARN_ON(!pll->config.crtc_mask);
1790         if (pll->active == 0) {
1791                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1792                 WARN_ON(pll->on);
1793                 assert_shared_dpll_disabled(dev_priv, pll);
1794
1795                 pll->mode_set(dev_priv, pll);
1796         }
1797 }
1798
1799 /**
1800  * intel_enable_shared_dpll - enable PCH PLL
1801  * @dev_priv: i915 private structure
1802  * @pipe: pipe PLL to enable
1803  *
1804  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1805  * drives the transcoder clock.
1806  */
1807 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1808 {
1809         struct drm_device *dev = crtc->base.dev;
1810         struct drm_i915_private *dev_priv = dev->dev_private;
1811         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1812
1813         if (WARN_ON(pll == NULL))
1814                 return;
1815
1816         if (WARN_ON(pll->config.crtc_mask == 0))
1817                 return;
1818
1819         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1820                       pll->name, pll->active, pll->on,
1821                       crtc->base.base.id);
1822
1823         if (pll->active++) {
1824                 WARN_ON(!pll->on);
1825                 assert_shared_dpll_enabled(dev_priv, pll);
1826                 return;
1827         }
1828         WARN_ON(pll->on);
1829
1830         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1831
1832         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1833         pll->enable(dev_priv, pll);
1834         pll->on = true;
1835 }
1836
1837 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1838 {
1839         struct drm_device *dev = crtc->base.dev;
1840         struct drm_i915_private *dev_priv = dev->dev_private;
1841         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1842
1843         /* PCH only available on ILK+ */
1844         BUG_ON(INTEL_INFO(dev)->gen < 5);
1845         if (WARN_ON(pll == NULL))
1846                return;
1847
1848         if (WARN_ON(pll->config.crtc_mask == 0))
1849                 return;
1850
1851         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1852                       pll->name, pll->active, pll->on,
1853                       crtc->base.base.id);
1854
1855         if (WARN_ON(pll->active == 0)) {
1856                 assert_shared_dpll_disabled(dev_priv, pll);
1857                 return;
1858         }
1859
1860         assert_shared_dpll_enabled(dev_priv, pll);
1861         WARN_ON(!pll->on);
1862         if (--pll->active)
1863                 return;
1864
1865         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1866         pll->disable(dev_priv, pll);
1867         pll->on = false;
1868
1869         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1870 }
1871
1872 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1873                                            enum pipe pipe)
1874 {
1875         struct drm_device *dev = dev_priv->dev;
1876         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1878         uint32_t reg, val, pipeconf_val;
1879
1880         /* PCH only available on ILK+ */
1881         BUG_ON(!HAS_PCH_SPLIT(dev));
1882
1883         /* Make sure PCH DPLL is enabled */
1884         assert_shared_dpll_enabled(dev_priv,
1885                                    intel_crtc_to_shared_dpll(intel_crtc));
1886
1887         /* FDI must be feeding us bits for PCH ports */
1888         assert_fdi_tx_enabled(dev_priv, pipe);
1889         assert_fdi_rx_enabled(dev_priv, pipe);
1890
1891         if (HAS_PCH_CPT(dev)) {
1892                 /* Workaround: Set the timing override bit before enabling the
1893                  * pch transcoder. */
1894                 reg = TRANS_CHICKEN2(pipe);
1895                 val = I915_READ(reg);
1896                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1897                 I915_WRITE(reg, val);
1898         }
1899
1900         reg = PCH_TRANSCONF(pipe);
1901         val = I915_READ(reg);
1902         pipeconf_val = I915_READ(PIPECONF(pipe));
1903
1904         if (HAS_PCH_IBX(dev_priv->dev)) {
1905                 /*
1906                  * make the BPC in transcoder be consistent with
1907                  * that in pipeconf reg.
1908                  */
1909                 val &= ~PIPECONF_BPC_MASK;
1910                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1911         }
1912
1913         val &= ~TRANS_INTERLACE_MASK;
1914         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1915                 if (HAS_PCH_IBX(dev_priv->dev) &&
1916                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1917                         val |= TRANS_LEGACY_INTERLACED_ILK;
1918                 else
1919                         val |= TRANS_INTERLACED;
1920         else
1921                 val |= TRANS_PROGRESSIVE;
1922
1923         I915_WRITE(reg, val | TRANS_ENABLE);
1924         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1925                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1926 }
1927
1928 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1929                                       enum transcoder cpu_transcoder)
1930 {
1931         u32 val, pipeconf_val;
1932
1933         /* PCH only available on ILK+ */
1934         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1935
1936         /* FDI must be feeding us bits for PCH ports */
1937         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1938         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1939
1940         /* Workaround: set timing override bit. */
1941         val = I915_READ(_TRANSA_CHICKEN2);
1942         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1943         I915_WRITE(_TRANSA_CHICKEN2, val);
1944
1945         val = TRANS_ENABLE;
1946         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1947
1948         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1949             PIPECONF_INTERLACED_ILK)
1950                 val |= TRANS_INTERLACED;
1951         else
1952                 val |= TRANS_PROGRESSIVE;
1953
1954         I915_WRITE(LPT_TRANSCONF, val);
1955         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1956                 DRM_ERROR("Failed to enable PCH transcoder\n");
1957 }
1958
1959 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1960                                             enum pipe pipe)
1961 {
1962         struct drm_device *dev = dev_priv->dev;
1963         uint32_t reg, val;
1964
1965         /* FDI relies on the transcoder */
1966         assert_fdi_tx_disabled(dev_priv, pipe);
1967         assert_fdi_rx_disabled(dev_priv, pipe);
1968
1969         /* Ports must be off as well */
1970         assert_pch_ports_disabled(dev_priv, pipe);
1971
1972         reg = PCH_TRANSCONF(pipe);
1973         val = I915_READ(reg);
1974         val &= ~TRANS_ENABLE;
1975         I915_WRITE(reg, val);
1976         /* wait for PCH transcoder off, transcoder state */
1977         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1978                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1979
1980         if (!HAS_PCH_IBX(dev)) {
1981                 /* Workaround: Clear the timing override chicken bit again. */
1982                 reg = TRANS_CHICKEN2(pipe);
1983                 val = I915_READ(reg);
1984                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1985                 I915_WRITE(reg, val);
1986         }
1987 }
1988
1989 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1990 {
1991         u32 val;
1992
1993         val = I915_READ(LPT_TRANSCONF);
1994         val &= ~TRANS_ENABLE;
1995         I915_WRITE(LPT_TRANSCONF, val);
1996         /* wait for PCH transcoder off, transcoder state */
1997         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1998                 DRM_ERROR("Failed to disable PCH transcoder\n");
1999
2000         /* Workaround: clear timing override bit. */
2001         val = I915_READ(_TRANSA_CHICKEN2);
2002         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2003         I915_WRITE(_TRANSA_CHICKEN2, val);
2004 }
2005
2006 /**
2007  * intel_enable_pipe - enable a pipe, asserting requirements
2008  * @crtc: crtc responsible for the pipe
2009  *
2010  * Enable @crtc's pipe, making sure that various hardware specific requirements
2011  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2012  */
2013 static void intel_enable_pipe(struct intel_crtc *crtc)
2014 {
2015         struct drm_device *dev = crtc->base.dev;
2016         struct drm_i915_private *dev_priv = dev->dev_private;
2017         enum pipe pipe = crtc->pipe;
2018         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2019                                                                       pipe);
2020         enum pipe pch_transcoder;
2021         int reg;
2022         u32 val;
2023
2024         assert_planes_disabled(dev_priv, pipe);
2025         assert_cursor_disabled(dev_priv, pipe);
2026         assert_sprites_disabled(dev_priv, pipe);
2027
2028         if (HAS_PCH_LPT(dev_priv->dev))
2029                 pch_transcoder = TRANSCODER_A;
2030         else
2031                 pch_transcoder = pipe;
2032
2033         /*
2034          * A pipe without a PLL won't actually be able to drive bits from
2035          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2036          * need the check.
2037          */
2038         if (!HAS_PCH_SPLIT(dev_priv->dev))
2039                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2040                         assert_dsi_pll_enabled(dev_priv);
2041                 else
2042                         assert_pll_enabled(dev_priv, pipe);
2043         else {
2044                 if (crtc->config->has_pch_encoder) {
2045                         /* if driving the PCH, we need FDI enabled */
2046                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2047                         assert_fdi_tx_pll_enabled(dev_priv,
2048                                                   (enum pipe) cpu_transcoder);
2049                 }
2050                 /* FIXME: assert CPU port conditions for SNB+ */
2051         }
2052
2053         reg = PIPECONF(cpu_transcoder);
2054         val = I915_READ(reg);
2055         if (val & PIPECONF_ENABLE) {
2056                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2057                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2058                 return;
2059         }
2060
2061         I915_WRITE(reg, val | PIPECONF_ENABLE);
2062         POSTING_READ(reg);
2063 }
2064
2065 /**
2066  * intel_disable_pipe - disable a pipe, asserting requirements
2067  * @crtc: crtc whose pipes is to be disabled
2068  *
2069  * Disable the pipe of @crtc, making sure that various hardware
2070  * specific requirements are met, if applicable, e.g. plane
2071  * disabled, panel fitter off, etc.
2072  *
2073  * Will wait until the pipe has shut down before returning.
2074  */
2075 static void intel_disable_pipe(struct intel_crtc *crtc)
2076 {
2077         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2078         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2079         enum pipe pipe = crtc->pipe;
2080         int reg;
2081         u32 val;
2082
2083         /*
2084          * Make sure planes won't keep trying to pump pixels to us,
2085          * or we might hang the display.
2086          */
2087         assert_planes_disabled(dev_priv, pipe);
2088         assert_cursor_disabled(dev_priv, pipe);
2089         assert_sprites_disabled(dev_priv, pipe);
2090
2091         reg = PIPECONF(cpu_transcoder);
2092         val = I915_READ(reg);
2093         if ((val & PIPECONF_ENABLE) == 0)
2094                 return;
2095
2096         /*
2097          * Double wide has implications for planes
2098          * so best keep it disabled when not needed.
2099          */
2100         if (crtc->config->double_wide)
2101                 val &= ~PIPECONF_DOUBLE_WIDE;
2102
2103         /* Don't disable pipe or pipe PLLs if needed */
2104         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2105             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2106                 val &= ~PIPECONF_ENABLE;
2107
2108         I915_WRITE(reg, val);
2109         if ((val & PIPECONF_ENABLE) == 0)
2110                 intel_wait_for_pipe_off(crtc);
2111 }
2112
2113 /*
2114  * Plane regs are double buffered, going from enabled->disabled needs a
2115  * trigger in order to latch.  The display address reg provides this.
2116  */
2117 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2118                                enum plane plane)
2119 {
2120         struct drm_device *dev = dev_priv->dev;
2121         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2122
2123         I915_WRITE(reg, I915_READ(reg));
2124         POSTING_READ(reg);
2125 }
2126
2127 /**
2128  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2129  * @plane:  plane to be enabled
2130  * @crtc: crtc for the plane
2131  *
2132  * Enable @plane on @crtc, making sure that the pipe is running first.
2133  */
2134 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2135                                           struct drm_crtc *crtc)
2136 {
2137         struct drm_device *dev = plane->dev;
2138         struct drm_i915_private *dev_priv = dev->dev_private;
2139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140
2141         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2142         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2143
2144         if (intel_crtc->primary_enabled)
2145                 return;
2146
2147         intel_crtc->primary_enabled = true;
2148
2149         dev_priv->display.update_primary_plane(crtc, plane->fb,
2150                                                crtc->x, crtc->y);
2151
2152         /*
2153          * BDW signals flip done immediately if the plane
2154          * is disabled, even if the plane enable is already
2155          * armed to occur at the next vblank :(
2156          */
2157         if (IS_BROADWELL(dev))
2158                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2159 }
2160
2161 /**
2162  * intel_disable_primary_hw_plane - disable the primary hardware plane
2163  * @plane: plane to be disabled
2164  * @crtc: crtc for the plane
2165  *
2166  * Disable @plane on @crtc, making sure that the pipe is running first.
2167  */
2168 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2169                                            struct drm_crtc *crtc)
2170 {
2171         struct drm_device *dev = plane->dev;
2172         struct drm_i915_private *dev_priv = dev->dev_private;
2173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2174
2175         if (WARN_ON(!intel_crtc->active))
2176                 return;
2177
2178         if (!intel_crtc->primary_enabled)
2179                 return;
2180
2181         intel_crtc->primary_enabled = false;
2182
2183         dev_priv->display.update_primary_plane(crtc, plane->fb,
2184                                                crtc->x, crtc->y);
2185 }
2186
2187 static bool need_vtd_wa(struct drm_device *dev)
2188 {
2189 #ifdef CONFIG_INTEL_IOMMU
2190         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2191                 return true;
2192 #endif
2193         return false;
2194 }
2195
2196 int
2197 intel_fb_align_height(struct drm_device *dev, int height,
2198                       uint32_t pixel_format,
2199                       uint64_t fb_format_modifier)
2200 {
2201         int tile_height;
2202         uint32_t bits_per_pixel;
2203
2204         switch (fb_format_modifier) {
2205         case DRM_FORMAT_MOD_NONE:
2206                 tile_height = 1;
2207                 break;
2208         case I915_FORMAT_MOD_X_TILED:
2209                 tile_height = IS_GEN2(dev) ? 16 : 8;
2210                 break;
2211         case I915_FORMAT_MOD_Y_TILED:
2212                 tile_height = 32;
2213                 break;
2214         case I915_FORMAT_MOD_Yf_TILED:
2215                 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2216                 switch (bits_per_pixel) {
2217                 default:
2218                 case 8:
2219                         tile_height = 64;
2220                         break;
2221                 case 16:
2222                 case 32:
2223                         tile_height = 32;
2224                         break;
2225                 case 64:
2226                         tile_height = 16;
2227                         break;
2228                 case 128:
2229                         WARN_ONCE(1,
2230                                   "128-bit pixels are not supported for display!");
2231                         tile_height = 16;
2232                         break;
2233                 }
2234                 break;
2235         default:
2236                 MISSING_CASE(fb_format_modifier);
2237                 tile_height = 1;
2238                 break;
2239         }
2240
2241         return ALIGN(height, tile_height);
2242 }
2243
2244 int
2245 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2246                            struct drm_framebuffer *fb,
2247                            struct intel_engine_cs *pipelined)
2248 {
2249         struct drm_device *dev = fb->dev;
2250         struct drm_i915_private *dev_priv = dev->dev_private;
2251         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2252         u32 alignment;
2253         int ret;
2254
2255         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2256
2257         switch (fb->modifier[0]) {
2258         case DRM_FORMAT_MOD_NONE:
2259                 if (INTEL_INFO(dev)->gen >= 9)
2260                         alignment = 256 * 1024;
2261                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2262                         alignment = 128 * 1024;
2263                 else if (INTEL_INFO(dev)->gen >= 4)
2264                         alignment = 4 * 1024;
2265                 else
2266                         alignment = 64 * 1024;
2267                 break;
2268         case I915_FORMAT_MOD_X_TILED:
2269                 if (INTEL_INFO(dev)->gen >= 9)
2270                         alignment = 256 * 1024;
2271                 else {
2272                         /* pin() will align the object as required by fence */
2273                         alignment = 0;
2274                 }
2275                 break;
2276         case I915_FORMAT_MOD_Y_TILED:
2277         case I915_FORMAT_MOD_Yf_TILED:
2278                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2279                           "Y tiling bo slipped through, driver bug!\n"))
2280                         return -EINVAL;
2281                 alignment = 1 * 1024 * 1024;
2282                 break;
2283         default:
2284                 MISSING_CASE(fb->modifier[0]);
2285                 return -EINVAL;
2286         }
2287
2288         /* Note that the w/a also requires 64 PTE of padding following the
2289          * bo. We currently fill all unused PTE with the shadow page and so
2290          * we should always have valid PTE following the scanout preventing
2291          * the VT-d warning.
2292          */
2293         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2294                 alignment = 256 * 1024;
2295
2296         /*
2297          * Global gtt pte registers are special registers which actually forward
2298          * writes to a chunk of system memory. Which means that there is no risk
2299          * that the register values disappear as soon as we call
2300          * intel_runtime_pm_put(), so it is correct to wrap only the
2301          * pin/unpin/fence and not more.
2302          */
2303         intel_runtime_pm_get(dev_priv);
2304
2305         dev_priv->mm.interruptible = false;
2306         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2307         if (ret)
2308                 goto err_interruptible;
2309
2310         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2311          * fence, whereas 965+ only requires a fence if using
2312          * framebuffer compression.  For simplicity, we always install
2313          * a fence as the cost is not that onerous.
2314          */
2315         ret = i915_gem_object_get_fence(obj);
2316         if (ret)
2317                 goto err_unpin;
2318
2319         i915_gem_object_pin_fence(obj);
2320
2321         dev_priv->mm.interruptible = true;
2322         intel_runtime_pm_put(dev_priv);
2323         return 0;
2324
2325 err_unpin:
2326         i915_gem_object_unpin_from_display_plane(obj);
2327 err_interruptible:
2328         dev_priv->mm.interruptible = true;
2329         intel_runtime_pm_put(dev_priv);
2330         return ret;
2331 }
2332
2333 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2334 {
2335         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2336
2337         i915_gem_object_unpin_fence(obj);
2338         i915_gem_object_unpin_from_display_plane(obj);
2339 }
2340
2341 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2342  * is assumed to be a power-of-two. */
2343 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2344                                              unsigned int tiling_mode,
2345                                              unsigned int cpp,
2346                                              unsigned int pitch)
2347 {
2348         if (tiling_mode != I915_TILING_NONE) {
2349                 unsigned int tile_rows, tiles;
2350
2351                 tile_rows = *y / 8;
2352                 *y %= 8;
2353
2354                 tiles = *x / (512/cpp);
2355                 *x %= 512/cpp;
2356
2357                 return tile_rows * pitch * 8 + tiles * 4096;
2358         } else {
2359                 unsigned int offset;
2360
2361                 offset = *y * pitch + *x * cpp;
2362                 *y = 0;
2363                 *x = (offset & 4095) / cpp;
2364                 return offset & -4096;
2365         }
2366 }
2367
2368 static int i9xx_format_to_fourcc(int format)
2369 {
2370         switch (format) {
2371         case DISPPLANE_8BPP:
2372                 return DRM_FORMAT_C8;
2373         case DISPPLANE_BGRX555:
2374                 return DRM_FORMAT_XRGB1555;
2375         case DISPPLANE_BGRX565:
2376                 return DRM_FORMAT_RGB565;
2377         default:
2378         case DISPPLANE_BGRX888:
2379                 return DRM_FORMAT_XRGB8888;
2380         case DISPPLANE_RGBX888:
2381                 return DRM_FORMAT_XBGR8888;
2382         case DISPPLANE_BGRX101010:
2383                 return DRM_FORMAT_XRGB2101010;
2384         case DISPPLANE_RGBX101010:
2385                 return DRM_FORMAT_XBGR2101010;
2386         }
2387 }
2388
2389 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2390 {
2391         switch (format) {
2392         case PLANE_CTL_FORMAT_RGB_565:
2393                 return DRM_FORMAT_RGB565;
2394         default:
2395         case PLANE_CTL_FORMAT_XRGB_8888:
2396                 if (rgb_order) {
2397                         if (alpha)
2398                                 return DRM_FORMAT_ABGR8888;
2399                         else
2400                                 return DRM_FORMAT_XBGR8888;
2401                 } else {
2402                         if (alpha)
2403                                 return DRM_FORMAT_ARGB8888;
2404                         else
2405                                 return DRM_FORMAT_XRGB8888;
2406                 }
2407         case PLANE_CTL_FORMAT_XRGB_2101010:
2408                 if (rgb_order)
2409                         return DRM_FORMAT_XBGR2101010;
2410                 else
2411                         return DRM_FORMAT_XRGB2101010;
2412         }
2413 }
2414
2415 static bool
2416 intel_alloc_plane_obj(struct intel_crtc *crtc,
2417                       struct intel_initial_plane_config *plane_config)
2418 {
2419         struct drm_device *dev = crtc->base.dev;
2420         struct drm_i915_gem_object *obj = NULL;
2421         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2422         struct drm_framebuffer *fb = &plane_config->fb->base;
2423         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2424         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2425                                     PAGE_SIZE);
2426
2427         size_aligned -= base_aligned;
2428
2429         if (plane_config->size == 0)
2430                 return false;
2431
2432         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2433                                                              base_aligned,
2434                                                              base_aligned,
2435                                                              size_aligned);
2436         if (!obj)
2437                 return false;
2438
2439         obj->tiling_mode = plane_config->tiling;
2440         if (obj->tiling_mode == I915_TILING_X)
2441                 obj->stride = fb->pitches[0];
2442
2443         mode_cmd.pixel_format = fb->pixel_format;
2444         mode_cmd.width = fb->width;
2445         mode_cmd.height = fb->height;
2446         mode_cmd.pitches[0] = fb->pitches[0];
2447         mode_cmd.modifier[0] = fb->modifier[0];
2448         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2449
2450         mutex_lock(&dev->struct_mutex);
2451
2452         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2453                                    &mode_cmd, obj)) {
2454                 DRM_DEBUG_KMS("intel fb init failed\n");
2455                 goto out_unref_obj;
2456         }
2457
2458         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2459         mutex_unlock(&dev->struct_mutex);
2460
2461         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2462         return true;
2463
2464 out_unref_obj:
2465         drm_gem_object_unreference(&obj->base);
2466         mutex_unlock(&dev->struct_mutex);
2467         return false;
2468 }
2469
2470 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2471 static void
2472 update_state_fb(struct drm_plane *plane)
2473 {
2474         if (plane->fb == plane->state->fb)
2475                 return;
2476
2477         if (plane->state->fb)
2478                 drm_framebuffer_unreference(plane->state->fb);
2479         plane->state->fb = plane->fb;
2480         if (plane->state->fb)
2481                 drm_framebuffer_reference(plane->state->fb);
2482 }
2483
2484 static void
2485 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2486                      struct intel_initial_plane_config *plane_config)
2487 {
2488         struct drm_device *dev = intel_crtc->base.dev;
2489         struct drm_i915_private *dev_priv = dev->dev_private;
2490         struct drm_crtc *c;
2491         struct intel_crtc *i;
2492         struct drm_i915_gem_object *obj;
2493
2494         if (!plane_config->fb)
2495                 return;
2496
2497         if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2498                 struct drm_plane *primary = intel_crtc->base.primary;
2499
2500                 primary->fb = &plane_config->fb->base;
2501                 primary->state->crtc = &intel_crtc->base;
2502                 update_state_fb(primary);
2503
2504                 return;
2505         }
2506
2507         kfree(plane_config->fb);
2508
2509         /*
2510          * Failed to alloc the obj, check to see if we should share
2511          * an fb with another CRTC instead
2512          */
2513         for_each_crtc(dev, c) {
2514                 i = to_intel_crtc(c);
2515
2516                 if (c == &intel_crtc->base)
2517                         continue;
2518
2519                 if (!i->active)
2520                         continue;
2521
2522                 obj = intel_fb_obj(c->primary->fb);
2523                 if (obj == NULL)
2524                         continue;
2525
2526                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2527                         struct drm_plane *primary = intel_crtc->base.primary;
2528
2529                         if (obj->tiling_mode != I915_TILING_NONE)
2530                                 dev_priv->preserve_bios_swizzle = true;
2531
2532                         drm_framebuffer_reference(c->primary->fb);
2533                         primary->fb = c->primary->fb;
2534                         primary->state->crtc = &intel_crtc->base;
2535                         update_state_fb(intel_crtc->base.primary);
2536                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2537                         break;
2538                 }
2539         }
2540
2541 }
2542
2543 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2544                                       struct drm_framebuffer *fb,
2545                                       int x, int y)
2546 {
2547         struct drm_device *dev = crtc->dev;
2548         struct drm_i915_private *dev_priv = dev->dev_private;
2549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2550         struct drm_i915_gem_object *obj;
2551         int plane = intel_crtc->plane;
2552         unsigned long linear_offset;
2553         u32 dspcntr;
2554         u32 reg = DSPCNTR(plane);
2555         int pixel_size;
2556
2557         if (!intel_crtc->primary_enabled) {
2558                 I915_WRITE(reg, 0);
2559                 if (INTEL_INFO(dev)->gen >= 4)
2560                         I915_WRITE(DSPSURF(plane), 0);
2561                 else
2562                         I915_WRITE(DSPADDR(plane), 0);
2563                 POSTING_READ(reg);
2564                 return;
2565         }
2566
2567         obj = intel_fb_obj(fb);
2568         if (WARN_ON(obj == NULL))
2569                 return;
2570
2571         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2572
2573         dspcntr = DISPPLANE_GAMMA_ENABLE;
2574
2575         dspcntr |= DISPLAY_PLANE_ENABLE;
2576
2577         if (INTEL_INFO(dev)->gen < 4) {
2578                 if (intel_crtc->pipe == PIPE_B)
2579                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2580
2581                 /* pipesrc and dspsize control the size that is scaled from,
2582                  * which should always be the user's requested size.
2583                  */
2584                 I915_WRITE(DSPSIZE(plane),
2585                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2586                            (intel_crtc->config->pipe_src_w - 1));
2587                 I915_WRITE(DSPPOS(plane), 0);
2588         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2589                 I915_WRITE(PRIMSIZE(plane),
2590                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2591                            (intel_crtc->config->pipe_src_w - 1));
2592                 I915_WRITE(PRIMPOS(plane), 0);
2593                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2594         }
2595
2596         switch (fb->pixel_format) {
2597         case DRM_FORMAT_C8:
2598                 dspcntr |= DISPPLANE_8BPP;
2599                 break;
2600         case DRM_FORMAT_XRGB1555:
2601         case DRM_FORMAT_ARGB1555:
2602                 dspcntr |= DISPPLANE_BGRX555;
2603                 break;
2604         case DRM_FORMAT_RGB565:
2605                 dspcntr |= DISPPLANE_BGRX565;
2606                 break;
2607         case DRM_FORMAT_XRGB8888:
2608         case DRM_FORMAT_ARGB8888:
2609                 dspcntr |= DISPPLANE_BGRX888;
2610                 break;
2611         case DRM_FORMAT_XBGR8888:
2612         case DRM_FORMAT_ABGR8888:
2613                 dspcntr |= DISPPLANE_RGBX888;
2614                 break;
2615         case DRM_FORMAT_XRGB2101010:
2616         case DRM_FORMAT_ARGB2101010:
2617                 dspcntr |= DISPPLANE_BGRX101010;
2618                 break;
2619         case DRM_FORMAT_XBGR2101010:
2620         case DRM_FORMAT_ABGR2101010:
2621                 dspcntr |= DISPPLANE_RGBX101010;
2622                 break;
2623         default:
2624                 BUG();
2625         }
2626
2627         if (INTEL_INFO(dev)->gen >= 4 &&
2628             obj->tiling_mode != I915_TILING_NONE)
2629                 dspcntr |= DISPPLANE_TILED;
2630
2631         if (IS_G4X(dev))
2632                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2633
2634         linear_offset = y * fb->pitches[0] + x * pixel_size;
2635
2636         if (INTEL_INFO(dev)->gen >= 4) {
2637                 intel_crtc->dspaddr_offset =
2638                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2639                                                        pixel_size,
2640                                                        fb->pitches[0]);
2641                 linear_offset -= intel_crtc->dspaddr_offset;
2642         } else {
2643                 intel_crtc->dspaddr_offset = linear_offset;
2644         }
2645
2646         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2647                 dspcntr |= DISPPLANE_ROTATE_180;
2648
2649                 x += (intel_crtc->config->pipe_src_w - 1);
2650                 y += (intel_crtc->config->pipe_src_h - 1);
2651
2652                 /* Finding the last pixel of the last line of the display
2653                 data and adding to linear_offset*/
2654                 linear_offset +=
2655                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2656                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2657         }
2658
2659         I915_WRITE(reg, dspcntr);
2660
2661         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2662                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2663                       fb->pitches[0]);
2664         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2665         if (INTEL_INFO(dev)->gen >= 4) {
2666                 I915_WRITE(DSPSURF(plane),
2667                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2668                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2669                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2670         } else
2671                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2672         POSTING_READ(reg);
2673 }
2674
2675 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2676                                           struct drm_framebuffer *fb,
2677                                           int x, int y)
2678 {
2679         struct drm_device *dev = crtc->dev;
2680         struct drm_i915_private *dev_priv = dev->dev_private;
2681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2682         struct drm_i915_gem_object *obj;
2683         int plane = intel_crtc->plane;
2684         unsigned long linear_offset;
2685         u32 dspcntr;
2686         u32 reg = DSPCNTR(plane);
2687         int pixel_size;
2688
2689         if (!intel_crtc->primary_enabled) {
2690                 I915_WRITE(reg, 0);
2691                 I915_WRITE(DSPSURF(plane), 0);
2692                 POSTING_READ(reg);
2693                 return;
2694         }
2695
2696         obj = intel_fb_obj(fb);
2697         if (WARN_ON(obj == NULL))
2698                 return;
2699
2700         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2701
2702         dspcntr = DISPPLANE_GAMMA_ENABLE;
2703
2704         dspcntr |= DISPLAY_PLANE_ENABLE;
2705
2706         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2707                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2708
2709         switch (fb->pixel_format) {
2710         case DRM_FORMAT_C8:
2711                 dspcntr |= DISPPLANE_8BPP;
2712                 break;
2713         case DRM_FORMAT_RGB565:
2714                 dspcntr |= DISPPLANE_BGRX565;
2715                 break;
2716         case DRM_FORMAT_XRGB8888:
2717         case DRM_FORMAT_ARGB8888:
2718                 dspcntr |= DISPPLANE_BGRX888;
2719                 break;
2720         case DRM_FORMAT_XBGR8888:
2721         case DRM_FORMAT_ABGR8888:
2722                 dspcntr |= DISPPLANE_RGBX888;
2723                 break;
2724         case DRM_FORMAT_XRGB2101010:
2725         case DRM_FORMAT_ARGB2101010:
2726                 dspcntr |= DISPPLANE_BGRX101010;
2727                 break;
2728         case DRM_FORMAT_XBGR2101010:
2729         case DRM_FORMAT_ABGR2101010:
2730                 dspcntr |= DISPPLANE_RGBX101010;
2731                 break;
2732         default:
2733                 BUG();
2734         }
2735
2736         if (obj->tiling_mode != I915_TILING_NONE)
2737                 dspcntr |= DISPPLANE_TILED;
2738
2739         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2740                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2741
2742         linear_offset = y * fb->pitches[0] + x * pixel_size;
2743         intel_crtc->dspaddr_offset =
2744                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2745                                                pixel_size,
2746                                                fb->pitches[0]);
2747         linear_offset -= intel_crtc->dspaddr_offset;
2748         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2749                 dspcntr |= DISPPLANE_ROTATE_180;
2750
2751                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2752                         x += (intel_crtc->config->pipe_src_w - 1);
2753                         y += (intel_crtc->config->pipe_src_h - 1);
2754
2755                         /* Finding the last pixel of the last line of the display
2756                         data and adding to linear_offset*/
2757                         linear_offset +=
2758                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2759                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2760                 }
2761         }
2762
2763         I915_WRITE(reg, dspcntr);
2764
2765         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2766                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2767                       fb->pitches[0]);
2768         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2769         I915_WRITE(DSPSURF(plane),
2770                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2771         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2772                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2773         } else {
2774                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2775                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2776         }
2777         POSTING_READ(reg);
2778 }
2779
2780 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2781                               uint32_t pixel_format)
2782 {
2783         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2784
2785         /*
2786          * The stride is either expressed as a multiple of 64 bytes
2787          * chunks for linear buffers or in number of tiles for tiled
2788          * buffers.
2789          */
2790         switch (fb_modifier) {
2791         case DRM_FORMAT_MOD_NONE:
2792                 return 64;
2793         case I915_FORMAT_MOD_X_TILED:
2794                 if (INTEL_INFO(dev)->gen == 2)
2795                         return 128;
2796                 return 512;
2797         case I915_FORMAT_MOD_Y_TILED:
2798                 /* No need to check for old gens and Y tiling since this is
2799                  * about the display engine and those will be blocked before
2800                  * we get here.
2801                  */
2802                 return 128;
2803         case I915_FORMAT_MOD_Yf_TILED:
2804                 if (bits_per_pixel == 8)
2805                         return 64;
2806                 else
2807                         return 128;
2808         default:
2809                 MISSING_CASE(fb_modifier);
2810                 return 64;
2811         }
2812 }
2813
2814 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2815                                          struct drm_framebuffer *fb,
2816                                          int x, int y)
2817 {
2818         struct drm_device *dev = crtc->dev;
2819         struct drm_i915_private *dev_priv = dev->dev_private;
2820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2821         struct drm_i915_gem_object *obj;
2822         int pipe = intel_crtc->pipe;
2823         u32 plane_ctl, stride_div;
2824
2825         if (!intel_crtc->primary_enabled) {
2826                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2827                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2828                 POSTING_READ(PLANE_CTL(pipe, 0));
2829                 return;
2830         }
2831
2832         plane_ctl = PLANE_CTL_ENABLE |
2833                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2834                     PLANE_CTL_PIPE_CSC_ENABLE;
2835
2836         switch (fb->pixel_format) {
2837         case DRM_FORMAT_RGB565:
2838                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2839                 break;
2840         case DRM_FORMAT_XRGB8888:
2841                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2842                 break;
2843         case DRM_FORMAT_ARGB8888:
2844                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2845                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2846                 break;
2847         case DRM_FORMAT_XBGR8888:
2848                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2849                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2850                 break;
2851         case DRM_FORMAT_ABGR8888:
2852                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2853                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2854                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2855                 break;
2856         case DRM_FORMAT_XRGB2101010:
2857                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2858                 break;
2859         case DRM_FORMAT_XBGR2101010:
2860                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2861                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2862                 break;
2863         default:
2864                 BUG();
2865         }
2866
2867         switch (fb->modifier[0]) {
2868         case DRM_FORMAT_MOD_NONE:
2869                 break;
2870         case I915_FORMAT_MOD_X_TILED:
2871                 plane_ctl |= PLANE_CTL_TILED_X;
2872                 break;
2873         case I915_FORMAT_MOD_Y_TILED:
2874                 plane_ctl |= PLANE_CTL_TILED_Y;
2875                 break;
2876         case I915_FORMAT_MOD_Yf_TILED:
2877                 plane_ctl |= PLANE_CTL_TILED_YF;
2878                 break;
2879         default:
2880                 MISSING_CASE(fb->modifier[0]);
2881         }
2882
2883         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2884         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2885                 plane_ctl |= PLANE_CTL_ROTATE_180;
2886
2887         obj = intel_fb_obj(fb);
2888         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2889                                                fb->pixel_format);
2890
2891         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2892
2893         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2894                       i915_gem_obj_ggtt_offset(obj),
2895                       x, y, fb->width, fb->height,
2896                       fb->pitches[0]);
2897
2898         I915_WRITE(PLANE_POS(pipe, 0), 0);
2899         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2900         I915_WRITE(PLANE_SIZE(pipe, 0),
2901                    (intel_crtc->config->pipe_src_h - 1) << 16 |
2902                    (intel_crtc->config->pipe_src_w - 1));
2903         I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2904         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2905
2906         POSTING_READ(PLANE_SURF(pipe, 0));
2907 }
2908
2909 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2910 static int
2911 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2912                            int x, int y, enum mode_set_atomic state)
2913 {
2914         struct drm_device *dev = crtc->dev;
2915         struct drm_i915_private *dev_priv = dev->dev_private;
2916
2917         if (dev_priv->display.disable_fbc)
2918                 dev_priv->display.disable_fbc(dev);
2919
2920         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2921
2922         return 0;
2923 }
2924
2925 static void intel_complete_page_flips(struct drm_device *dev)
2926 {
2927         struct drm_crtc *crtc;
2928
2929         for_each_crtc(dev, crtc) {
2930                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2931                 enum plane plane = intel_crtc->plane;
2932
2933                 intel_prepare_page_flip(dev, plane);
2934                 intel_finish_page_flip_plane(dev, plane);
2935         }
2936 }
2937
2938 static void intel_update_primary_planes(struct drm_device *dev)
2939 {
2940         struct drm_i915_private *dev_priv = dev->dev_private;
2941         struct drm_crtc *crtc;
2942
2943         for_each_crtc(dev, crtc) {
2944                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2945
2946                 drm_modeset_lock(&crtc->mutex, NULL);
2947                 /*
2948                  * FIXME: Once we have proper support for primary planes (and
2949                  * disabling them without disabling the entire crtc) allow again
2950                  * a NULL crtc->primary->fb.
2951                  */
2952                 if (intel_crtc->active && crtc->primary->fb)
2953                         dev_priv->display.update_primary_plane(crtc,
2954                                                                crtc->primary->fb,
2955                                                                crtc->x,
2956                                                                crtc->y);
2957                 drm_modeset_unlock(&crtc->mutex);
2958         }
2959 }
2960
2961 void intel_prepare_reset(struct drm_device *dev)
2962 {
2963         struct drm_i915_private *dev_priv = to_i915(dev);
2964         struct intel_crtc *crtc;
2965
2966         /* no reset support for gen2 */
2967         if (IS_GEN2(dev))
2968                 return;
2969
2970         /* reset doesn't touch the display */
2971         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2972                 return;
2973
2974         drm_modeset_lock_all(dev);
2975
2976         /*
2977          * Disabling the crtcs gracefully seems nicer. Also the
2978          * g33 docs say we should at least disable all the planes.
2979          */
2980         for_each_intel_crtc(dev, crtc) {
2981                 if (crtc->active)
2982                         dev_priv->display.crtc_disable(&crtc->base);
2983         }
2984 }
2985
2986 void intel_finish_reset(struct drm_device *dev)
2987 {
2988         struct drm_i915_private *dev_priv = to_i915(dev);
2989
2990         /*
2991          * Flips in the rings will be nuked by the reset,
2992          * so complete all pending flips so that user space
2993          * will get its events and not get stuck.
2994          */
2995         intel_complete_page_flips(dev);
2996
2997         /* no reset support for gen2 */
2998         if (IS_GEN2(dev))
2999                 return;
3000
3001         /* reset doesn't touch the display */
3002         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3003                 /*
3004                  * Flips in the rings have been nuked by the reset,
3005                  * so update the base address of all primary
3006                  * planes to the the last fb to make sure we're
3007                  * showing the correct fb after a reset.
3008                  */
3009                 intel_update_primary_planes(dev);
3010                 return;
3011         }
3012
3013         /*
3014          * The display has been reset as well,
3015          * so need a full re-initialization.
3016          */
3017         intel_runtime_pm_disable_interrupts(dev_priv);
3018         intel_runtime_pm_enable_interrupts(dev_priv);
3019
3020         intel_modeset_init_hw(dev);
3021
3022         spin_lock_irq(&dev_priv->irq_lock);
3023         if (dev_priv->display.hpd_irq_setup)
3024                 dev_priv->display.hpd_irq_setup(dev);
3025         spin_unlock_irq(&dev_priv->irq_lock);
3026
3027         intel_modeset_setup_hw_state(dev, true);
3028
3029         intel_hpd_init(dev_priv);
3030
3031         drm_modeset_unlock_all(dev);
3032 }
3033
3034 static int
3035 intel_finish_fb(struct drm_framebuffer *old_fb)
3036 {
3037         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3038         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3039         bool was_interruptible = dev_priv->mm.interruptible;
3040         int ret;
3041
3042         /* Big Hammer, we also need to ensure that any pending
3043          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3044          * current scanout is retired before unpinning the old
3045          * framebuffer.
3046          *
3047          * This should only fail upon a hung GPU, in which case we
3048          * can safely continue.
3049          */
3050         dev_priv->mm.interruptible = false;
3051         ret = i915_gem_object_finish_gpu(obj);
3052         dev_priv->mm.interruptible = was_interruptible;
3053
3054         return ret;
3055 }
3056
3057 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3058 {
3059         struct drm_device *dev = crtc->dev;
3060         struct drm_i915_private *dev_priv = dev->dev_private;
3061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3062         bool pending;
3063
3064         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3065             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3066                 return false;
3067
3068         spin_lock_irq(&dev->event_lock);
3069         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3070         spin_unlock_irq(&dev->event_lock);
3071
3072         return pending;
3073 }
3074
3075 static void intel_update_pipe_size(struct intel_crtc *crtc)
3076 {
3077         struct drm_device *dev = crtc->base.dev;
3078         struct drm_i915_private *dev_priv = dev->dev_private;
3079         const struct drm_display_mode *adjusted_mode;
3080
3081         if (!i915.fastboot)
3082                 return;
3083
3084         /*
3085          * Update pipe size and adjust fitter if needed: the reason for this is
3086          * that in compute_mode_changes we check the native mode (not the pfit
3087          * mode) to see if we can flip rather than do a full mode set. In the
3088          * fastboot case, we'll flip, but if we don't update the pipesrc and
3089          * pfit state, we'll end up with a big fb scanned out into the wrong
3090          * sized surface.
3091          *
3092          * To fix this properly, we need to hoist the checks up into
3093          * compute_mode_changes (or above), check the actual pfit state and
3094          * whether the platform allows pfit disable with pipe active, and only
3095          * then update the pipesrc and pfit state, even on the flip path.
3096          */
3097
3098         adjusted_mode = &crtc->config->base.adjusted_mode;
3099
3100         I915_WRITE(PIPESRC(crtc->pipe),
3101                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3102                    (adjusted_mode->crtc_vdisplay - 1));
3103         if (!crtc->config->pch_pfit.enabled &&
3104             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3105              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3106                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3107                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3108                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3109         }
3110         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3111         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3112 }
3113
3114 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3115 {
3116         struct drm_device *dev = crtc->dev;
3117         struct drm_i915_private *dev_priv = dev->dev_private;
3118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3119         int pipe = intel_crtc->pipe;
3120         u32 reg, temp;
3121
3122         /* enable normal train */
3123         reg = FDI_TX_CTL(pipe);
3124         temp = I915_READ(reg);
3125         if (IS_IVYBRIDGE(dev)) {
3126                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3127                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3128         } else {
3129                 temp &= ~FDI_LINK_TRAIN_NONE;
3130                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3131         }
3132         I915_WRITE(reg, temp);
3133
3134         reg = FDI_RX_CTL(pipe);
3135         temp = I915_READ(reg);
3136         if (HAS_PCH_CPT(dev)) {
3137                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3138                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3139         } else {
3140                 temp &= ~FDI_LINK_TRAIN_NONE;
3141                 temp |= FDI_LINK_TRAIN_NONE;
3142         }
3143         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3144
3145         /* wait one idle pattern time */
3146         POSTING_READ(reg);
3147         udelay(1000);
3148
3149         /* IVB wants error correction enabled */
3150         if (IS_IVYBRIDGE(dev))
3151                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3152                            FDI_FE_ERRC_ENABLE);
3153 }
3154
3155 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3156 {
3157         return crtc->base.state->enable && crtc->active &&
3158                 crtc->config->has_pch_encoder;
3159 }
3160
3161 static void ivb_modeset_global_resources(struct drm_device *dev)
3162 {
3163         struct drm_i915_private *dev_priv = dev->dev_private;
3164         struct intel_crtc *pipe_B_crtc =
3165                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3166         struct intel_crtc *pipe_C_crtc =
3167                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3168         uint32_t temp;
3169
3170         /*
3171          * When everything is off disable fdi C so that we could enable fdi B
3172          * with all lanes. Note that we don't care about enabled pipes without
3173          * an enabled pch encoder.
3174          */
3175         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3176             !pipe_has_enabled_pch(pipe_C_crtc)) {
3177                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3178                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3179
3180                 temp = I915_READ(SOUTH_CHICKEN1);
3181                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3182                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3183                 I915_WRITE(SOUTH_CHICKEN1, temp);
3184         }
3185 }
3186
3187 /* The FDI link training functions for ILK/Ibexpeak. */
3188 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3189 {
3190         struct drm_device *dev = crtc->dev;
3191         struct drm_i915_private *dev_priv = dev->dev_private;
3192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193         int pipe = intel_crtc->pipe;
3194         u32 reg, temp, tries;
3195
3196         /* FDI needs bits from pipe first */
3197         assert_pipe_enabled(dev_priv, pipe);
3198
3199         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3200            for train result */
3201         reg = FDI_RX_IMR(pipe);
3202         temp = I915_READ(reg);
3203         temp &= ~FDI_RX_SYMBOL_LOCK;
3204         temp &= ~FDI_RX_BIT_LOCK;
3205         I915_WRITE(reg, temp);
3206         I915_READ(reg);
3207         udelay(150);
3208
3209         /* enable CPU FDI TX and PCH FDI RX */
3210         reg = FDI_TX_CTL(pipe);
3211         temp = I915_READ(reg);
3212         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3213         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3214         temp &= ~FDI_LINK_TRAIN_NONE;
3215         temp |= FDI_LINK_TRAIN_PATTERN_1;
3216         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3217
3218         reg = FDI_RX_CTL(pipe);
3219         temp = I915_READ(reg);
3220         temp &= ~FDI_LINK_TRAIN_NONE;
3221         temp |= FDI_LINK_TRAIN_PATTERN_1;
3222         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3223
3224         POSTING_READ(reg);
3225         udelay(150);
3226
3227         /* Ironlake workaround, enable clock pointer after FDI enable*/
3228         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3229         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3230                    FDI_RX_PHASE_SYNC_POINTER_EN);
3231
3232         reg = FDI_RX_IIR(pipe);
3233         for (tries = 0; tries < 5; tries++) {
3234                 temp = I915_READ(reg);
3235                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3236
3237                 if ((temp & FDI_RX_BIT_LOCK)) {
3238                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3239                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3240                         break;
3241                 }
3242         }
3243         if (tries == 5)
3244                 DRM_ERROR("FDI train 1 fail!\n");
3245
3246         /* Train 2 */
3247         reg = FDI_TX_CTL(pipe);
3248         temp = I915_READ(reg);
3249         temp &= ~FDI_LINK_TRAIN_NONE;
3250         temp |= FDI_LINK_TRAIN_PATTERN_2;
3251         I915_WRITE(reg, temp);
3252
3253         reg = FDI_RX_CTL(pipe);
3254         temp = I915_READ(reg);
3255         temp &= ~FDI_LINK_TRAIN_NONE;
3256         temp |= FDI_LINK_TRAIN_PATTERN_2;
3257         I915_WRITE(reg, temp);
3258
3259         POSTING_READ(reg);
3260         udelay(150);
3261
3262         reg = FDI_RX_IIR(pipe);
3263         for (tries = 0; tries < 5; tries++) {
3264                 temp = I915_READ(reg);
3265                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3266
3267                 if (temp & FDI_RX_SYMBOL_LOCK) {
3268                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3269                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3270                         break;
3271                 }
3272         }
3273         if (tries == 5)
3274                 DRM_ERROR("FDI train 2 fail!\n");
3275
3276         DRM_DEBUG_KMS("FDI train done\n");
3277
3278 }
3279
3280 static const int snb_b_fdi_train_param[] = {
3281         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3282         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3283         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3284         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3285 };
3286
3287 /* The FDI link training functions for SNB/Cougarpoint. */
3288 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3289 {
3290         struct drm_device *dev = crtc->dev;
3291         struct drm_i915_private *dev_priv = dev->dev_private;
3292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3293         int pipe = intel_crtc->pipe;
3294         u32 reg, temp, i, retry;
3295
3296         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3297            for train result */
3298         reg = FDI_RX_IMR(pipe);
3299         temp = I915_READ(reg);
3300         temp &= ~FDI_RX_SYMBOL_LOCK;
3301         temp &= ~FDI_RX_BIT_LOCK;
3302         I915_WRITE(reg, temp);
3303
3304         POSTING_READ(reg);
3305         udelay(150);
3306
3307         /* enable CPU FDI TX and PCH FDI RX */
3308         reg = FDI_TX_CTL(pipe);
3309         temp = I915_READ(reg);
3310         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3311         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3312         temp &= ~FDI_LINK_TRAIN_NONE;
3313         temp |= FDI_LINK_TRAIN_PATTERN_1;
3314         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3315         /* SNB-B */
3316         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3317         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3318
3319         I915_WRITE(FDI_RX_MISC(pipe),
3320                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3321
3322         reg = FDI_RX_CTL(pipe);
3323         temp = I915_READ(reg);
3324         if (HAS_PCH_CPT(dev)) {
3325                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3326                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3327         } else {
3328                 temp &= ~FDI_LINK_TRAIN_NONE;
3329                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3330         }
3331         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3332
3333         POSTING_READ(reg);
3334         udelay(150);
3335
3336         for (i = 0; i < 4; i++) {
3337                 reg = FDI_TX_CTL(pipe);
3338                 temp = I915_READ(reg);
3339                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3340                 temp |= snb_b_fdi_train_param[i];
3341                 I915_WRITE(reg, temp);
3342
3343                 POSTING_READ(reg);
3344                 udelay(500);
3345
3346                 for (retry = 0; retry < 5; retry++) {
3347                         reg = FDI_RX_IIR(pipe);
3348                         temp = I915_READ(reg);
3349                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3350                         if (temp & FDI_RX_BIT_LOCK) {
3351                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3352                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3353                                 break;
3354                         }
3355                         udelay(50);
3356                 }
3357                 if (retry < 5)
3358                         break;
3359         }
3360         if (i == 4)
3361                 DRM_ERROR("FDI train 1 fail!\n");
3362
3363         /* Train 2 */
3364         reg = FDI_TX_CTL(pipe);
3365         temp = I915_READ(reg);
3366         temp &= ~FDI_LINK_TRAIN_NONE;
3367         temp |= FDI_LINK_TRAIN_PATTERN_2;
3368         if (IS_GEN6(dev)) {
3369                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3370                 /* SNB-B */
3371                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3372         }
3373         I915_WRITE(reg, temp);
3374
3375         reg = FDI_RX_CTL(pipe);
3376         temp = I915_READ(reg);
3377         if (HAS_PCH_CPT(dev)) {
3378                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3379                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3380         } else {
3381                 temp &= ~FDI_LINK_TRAIN_NONE;
3382                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3383         }
3384         I915_WRITE(reg, temp);
3385
3386         POSTING_READ(reg);
3387         udelay(150);
3388
3389         for (i = 0; i < 4; i++) {
3390                 reg = FDI_TX_CTL(pipe);
3391                 temp = I915_READ(reg);
3392                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3393                 temp |= snb_b_fdi_train_param[i];
3394                 I915_WRITE(reg, temp);
3395
3396                 POSTING_READ(reg);
3397                 udelay(500);
3398
3399                 for (retry = 0; retry < 5; retry++) {
3400                         reg = FDI_RX_IIR(pipe);
3401                         temp = I915_READ(reg);
3402                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3403                         if (temp & FDI_RX_SYMBOL_LOCK) {
3404                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3405                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3406                                 break;
3407                         }
3408                         udelay(50);
3409                 }
3410                 if (retry < 5)
3411                         break;
3412         }
3413         if (i == 4)
3414                 DRM_ERROR("FDI train 2 fail!\n");
3415
3416         DRM_DEBUG_KMS("FDI train done.\n");
3417 }
3418
3419 /* Manual link training for Ivy Bridge A0 parts */
3420 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3421 {
3422         struct drm_device *dev = crtc->dev;
3423         struct drm_i915_private *dev_priv = dev->dev_private;
3424         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3425         int pipe = intel_crtc->pipe;
3426         u32 reg, temp, i, j;
3427
3428         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3429            for train result */
3430         reg = FDI_RX_IMR(pipe);
3431         temp = I915_READ(reg);
3432         temp &= ~FDI_RX_SYMBOL_LOCK;
3433         temp &= ~FDI_RX_BIT_LOCK;
3434         I915_WRITE(reg, temp);
3435
3436         POSTING_READ(reg);
3437         udelay(150);
3438
3439         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3440                       I915_READ(FDI_RX_IIR(pipe)));
3441
3442         /* Try each vswing and preemphasis setting twice before moving on */
3443         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3444                 /* disable first in case we need to retry */
3445                 reg = FDI_TX_CTL(pipe);
3446                 temp = I915_READ(reg);
3447                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3448                 temp &= ~FDI_TX_ENABLE;
3449                 I915_WRITE(reg, temp);
3450
3451                 reg = FDI_RX_CTL(pipe);
3452                 temp = I915_READ(reg);
3453                 temp &= ~FDI_LINK_TRAIN_AUTO;
3454                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3455                 temp &= ~FDI_RX_ENABLE;
3456                 I915_WRITE(reg, temp);
3457
3458                 /* enable CPU FDI TX and PCH FDI RX */
3459                 reg = FDI_TX_CTL(pipe);
3460                 temp = I915_READ(reg);
3461                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3462                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3463                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3464                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3465                 temp |= snb_b_fdi_train_param[j/2];
3466                 temp |= FDI_COMPOSITE_SYNC;
3467                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3468
3469                 I915_WRITE(FDI_RX_MISC(pipe),
3470                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3471
3472                 reg = FDI_RX_CTL(pipe);
3473                 temp = I915_READ(reg);
3474                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3475                 temp |= FDI_COMPOSITE_SYNC;
3476                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3477
3478                 POSTING_READ(reg);
3479                 udelay(1); /* should be 0.5us */
3480
3481                 for (i = 0; i < 4; i++) {
3482                         reg = FDI_RX_IIR(pipe);
3483                         temp = I915_READ(reg);
3484                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3485
3486                         if (temp & FDI_RX_BIT_LOCK ||
3487                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3488                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3489                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3490                                               i);
3491                                 break;
3492                         }
3493                         udelay(1); /* should be 0.5us */
3494                 }
3495                 if (i == 4) {
3496                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3497                         continue;
3498                 }
3499
3500                 /* Train 2 */
3501                 reg = FDI_TX_CTL(pipe);
3502                 temp = I915_READ(reg);
3503                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3504                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3505                 I915_WRITE(reg, temp);
3506
3507                 reg = FDI_RX_CTL(pipe);
3508                 temp = I915_READ(reg);
3509                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3510                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3511                 I915_WRITE(reg, temp);
3512
3513                 POSTING_READ(reg);
3514                 udelay(2); /* should be 1.5us */
3515
3516                 for (i = 0; i < 4; i++) {
3517                         reg = FDI_RX_IIR(pipe);
3518                         temp = I915_READ(reg);
3519                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3520
3521                         if (temp & FDI_RX_SYMBOL_LOCK ||
3522                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3523                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3524                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3525                                               i);
3526                                 goto train_done;
3527                         }
3528                         udelay(2); /* should be 1.5us */
3529                 }
3530                 if (i == 4)
3531                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3532         }
3533
3534 train_done:
3535         DRM_DEBUG_KMS("FDI train done.\n");
3536 }
3537
3538 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3539 {
3540         struct drm_device *dev = intel_crtc->base.dev;
3541         struct drm_i915_private *dev_priv = dev->dev_private;
3542         int pipe = intel_crtc->pipe;
3543         u32 reg, temp;
3544
3545
3546         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3547         reg = FDI_RX_CTL(pipe);
3548         temp = I915_READ(reg);
3549         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3550         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3551         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3552         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3553
3554         POSTING_READ(reg);
3555         udelay(200);
3556
3557         /* Switch from Rawclk to PCDclk */
3558         temp = I915_READ(reg);
3559         I915_WRITE(reg, temp | FDI_PCDCLK);
3560
3561         POSTING_READ(reg);
3562         udelay(200);
3563
3564         /* Enable CPU FDI TX PLL, always on for Ironlake */
3565         reg = FDI_TX_CTL(pipe);
3566         temp = I915_READ(reg);
3567         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3568                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3569
3570                 POSTING_READ(reg);
3571                 udelay(100);
3572         }
3573 }
3574
3575 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3576 {
3577         struct drm_device *dev = intel_crtc->base.dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         int pipe = intel_crtc->pipe;
3580         u32 reg, temp;
3581
3582         /* Switch from PCDclk to Rawclk */
3583         reg = FDI_RX_CTL(pipe);
3584         temp = I915_READ(reg);
3585         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3586
3587         /* Disable CPU FDI TX PLL */
3588         reg = FDI_TX_CTL(pipe);
3589         temp = I915_READ(reg);
3590         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3591
3592         POSTING_READ(reg);
3593         udelay(100);
3594
3595         reg = FDI_RX_CTL(pipe);
3596         temp = I915_READ(reg);
3597         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3598
3599         /* Wait for the clocks to turn off. */
3600         POSTING_READ(reg);
3601         udelay(100);
3602 }
3603
3604 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3605 {
3606         struct drm_device *dev = crtc->dev;
3607         struct drm_i915_private *dev_priv = dev->dev_private;
3608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3609         int pipe = intel_crtc->pipe;
3610         u32 reg, temp;
3611
3612         /* disable CPU FDI tx and PCH FDI rx */
3613         reg = FDI_TX_CTL(pipe);
3614         temp = I915_READ(reg);
3615         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3616         POSTING_READ(reg);
3617
3618         reg = FDI_RX_CTL(pipe);
3619         temp = I915_READ(reg);
3620         temp &= ~(0x7 << 16);
3621         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3622         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3623
3624         POSTING_READ(reg);
3625         udelay(100);
3626
3627         /* Ironlake workaround, disable clock pointer after downing FDI */
3628         if (HAS_PCH_IBX(dev))
3629                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3630
3631         /* still set train pattern 1 */
3632         reg = FDI_TX_CTL(pipe);
3633         temp = I915_READ(reg);
3634         temp &= ~FDI_LINK_TRAIN_NONE;
3635         temp |= FDI_LINK_TRAIN_PATTERN_1;
3636         I915_WRITE(reg, temp);
3637
3638         reg = FDI_RX_CTL(pipe);
3639         temp = I915_READ(reg);
3640         if (HAS_PCH_CPT(dev)) {
3641                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3642                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3643         } else {
3644                 temp &= ~FDI_LINK_TRAIN_NONE;
3645                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3646         }
3647         /* BPC in FDI rx is consistent with that in PIPECONF */
3648         temp &= ~(0x07 << 16);
3649         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3650         I915_WRITE(reg, temp);
3651
3652         POSTING_READ(reg);
3653         udelay(100);
3654 }
3655
3656 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3657 {
3658         struct intel_crtc *crtc;
3659
3660         /* Note that we don't need to be called with mode_config.lock here
3661          * as our list of CRTC objects is static for the lifetime of the
3662          * device and so cannot disappear as we iterate. Similarly, we can
3663          * happily treat the predicates as racy, atomic checks as userspace
3664          * cannot claim and pin a new fb without at least acquring the
3665          * struct_mutex and so serialising with us.
3666          */
3667         for_each_intel_crtc(dev, crtc) {
3668                 if (atomic_read(&crtc->unpin_work_count) == 0)
3669                         continue;
3670
3671                 if (crtc->unpin_work)
3672                         intel_wait_for_vblank(dev, crtc->pipe);
3673
3674                 return true;
3675         }
3676
3677         return false;
3678 }
3679
3680 static void page_flip_completed(struct intel_crtc *intel_crtc)
3681 {
3682         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3683         struct intel_unpin_work *work = intel_crtc->unpin_work;
3684
3685         /* ensure that the unpin work is consistent wrt ->pending. */
3686         smp_rmb();
3687         intel_crtc->unpin_work = NULL;
3688
3689         if (work->event)
3690                 drm_send_vblank_event(intel_crtc->base.dev,
3691                                       intel_crtc->pipe,
3692                                       work->event);
3693
3694         drm_crtc_vblank_put(&intel_crtc->base);
3695
3696         wake_up_all(&dev_priv->pending_flip_queue);
3697         queue_work(dev_priv->wq, &work->work);
3698
3699         trace_i915_flip_complete(intel_crtc->plane,
3700                                  work->pending_flip_obj);
3701 }
3702
3703 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3704 {
3705         struct drm_device *dev = crtc->dev;
3706         struct drm_i915_private *dev_priv = dev->dev_private;
3707
3708         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3709         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3710                                        !intel_crtc_has_pending_flip(crtc),
3711                                        60*HZ) == 0)) {
3712                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3713
3714                 spin_lock_irq(&dev->event_lock);
3715                 if (intel_crtc->unpin_work) {
3716                         WARN_ONCE(1, "Removing stuck page flip\n");
3717                         page_flip_completed(intel_crtc);
3718                 }
3719                 spin_unlock_irq(&dev->event_lock);
3720         }
3721
3722         if (crtc->primary->fb) {
3723                 mutex_lock(&dev->struct_mutex);
3724                 intel_finish_fb(crtc->primary->fb);
3725                 mutex_unlock(&dev->struct_mutex);
3726         }
3727 }
3728
3729 /* Program iCLKIP clock to the desired frequency */
3730 static void lpt_program_iclkip(struct drm_crtc *crtc)
3731 {
3732         struct drm_device *dev = crtc->dev;
3733         struct drm_i915_private *dev_priv = dev->dev_private;
3734         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3735         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3736         u32 temp;
3737
3738         mutex_lock(&dev_priv->dpio_lock);
3739
3740         /* It is necessary to ungate the pixclk gate prior to programming
3741          * the divisors, and gate it back when it is done.
3742          */
3743         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3744
3745         /* Disable SSCCTL */
3746         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3747                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3748                                 SBI_SSCCTL_DISABLE,
3749                         SBI_ICLK);
3750
3751         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3752         if (clock == 20000) {
3753                 auxdiv = 1;
3754                 divsel = 0x41;
3755                 phaseinc = 0x20;
3756         } else {
3757                 /* The iCLK virtual clock root frequency is in MHz,
3758                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3759                  * divisors, it is necessary to divide one by another, so we
3760                  * convert the virtual clock precision to KHz here for higher
3761                  * precision.
3762                  */
3763                 u32 iclk_virtual_root_freq = 172800 * 1000;
3764                 u32 iclk_pi_range = 64;
3765                 u32 desired_divisor, msb_divisor_value, pi_value;
3766
3767                 desired_divisor = (iclk_virtual_root_freq / clock);
3768                 msb_divisor_value = desired_divisor / iclk_pi_range;
3769                 pi_value = desired_divisor % iclk_pi_range;
3770
3771                 auxdiv = 0;
3772                 divsel = msb_divisor_value - 2;
3773                 phaseinc = pi_value;
3774         }
3775
3776         /* This should not happen with any sane values */
3777         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3778                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3779         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3780                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3781
3782         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3783                         clock,
3784                         auxdiv,
3785                         divsel,
3786                         phasedir,
3787                         phaseinc);
3788
3789         /* Program SSCDIVINTPHASE6 */
3790         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3791         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3792         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3793         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3794         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3795         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3796         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3797         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3798
3799         /* Program SSCAUXDIV */
3800         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3801         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3802         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3803         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3804
3805         /* Enable modulator and associated divider */
3806         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3807         temp &= ~SBI_SSCCTL_DISABLE;
3808         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3809
3810         /* Wait for initialization time */
3811         udelay(24);
3812
3813         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3814
3815         mutex_unlock(&dev_priv->dpio_lock);
3816 }
3817
3818 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3819                                                 enum pipe pch_transcoder)
3820 {
3821         struct drm_device *dev = crtc->base.dev;
3822         struct drm_i915_private *dev_priv = dev->dev_private;
3823         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3824
3825         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3826                    I915_READ(HTOTAL(cpu_transcoder)));
3827         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3828                    I915_READ(HBLANK(cpu_transcoder)));
3829         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3830                    I915_READ(HSYNC(cpu_transcoder)));
3831
3832         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3833                    I915_READ(VTOTAL(cpu_transcoder)));
3834         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3835                    I915_READ(VBLANK(cpu_transcoder)));
3836         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3837                    I915_READ(VSYNC(cpu_transcoder)));
3838         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3839                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3840 }
3841
3842 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3843 {
3844         struct drm_i915_private *dev_priv = dev->dev_private;
3845         uint32_t temp;
3846
3847         temp = I915_READ(SOUTH_CHICKEN1);
3848         if (temp & FDI_BC_BIFURCATION_SELECT)
3849                 return;
3850
3851         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3852         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3853
3854         temp |= FDI_BC_BIFURCATION_SELECT;
3855         DRM_DEBUG_KMS("enabling fdi C rx\n");
3856         I915_WRITE(SOUTH_CHICKEN1, temp);
3857         POSTING_READ(SOUTH_CHICKEN1);
3858 }
3859
3860 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3861 {
3862         struct drm_device *dev = intel_crtc->base.dev;
3863         struct drm_i915_private *dev_priv = dev->dev_private;
3864
3865         switch (intel_crtc->pipe) {
3866         case PIPE_A:
3867                 break;
3868         case PIPE_B:
3869                 if (intel_crtc->config->fdi_lanes > 2)
3870                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3871                 else
3872                         cpt_enable_fdi_bc_bifurcation(dev);
3873
3874                 break;
3875         case PIPE_C:
3876                 cpt_enable_fdi_bc_bifurcation(dev);
3877
3878                 break;
3879         default:
3880                 BUG();
3881         }
3882 }
3883
3884 /*
3885  * Enable PCH resources required for PCH ports:
3886  *   - PCH PLLs
3887  *   - FDI training & RX/TX
3888  *   - update transcoder timings
3889  *   - DP transcoding bits
3890  *   - transcoder
3891  */
3892 static void ironlake_pch_enable(struct drm_crtc *crtc)
3893 {
3894         struct drm_device *dev = crtc->dev;
3895         struct drm_i915_private *dev_priv = dev->dev_private;
3896         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3897         int pipe = intel_crtc->pipe;
3898         u32 reg, temp;
3899
3900         assert_pch_transcoder_disabled(dev_priv, pipe);
3901
3902         if (IS_IVYBRIDGE(dev))
3903                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3904
3905         /* Write the TU size bits before fdi link training, so that error
3906          * detection works. */
3907         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3908                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3909
3910         /* For PCH output, training FDI link */
3911         dev_priv->display.fdi_link_train(crtc);
3912
3913         /* We need to program the right clock selection before writing the pixel
3914          * mutliplier into the DPLL. */
3915         if (HAS_PCH_CPT(dev)) {
3916                 u32 sel;
3917
3918                 temp = I915_READ(PCH_DPLL_SEL);
3919                 temp |= TRANS_DPLL_ENABLE(pipe);
3920                 sel = TRANS_DPLLB_SEL(pipe);
3921                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3922                         temp |= sel;
3923                 else
3924                         temp &= ~sel;
3925                 I915_WRITE(PCH_DPLL_SEL, temp);
3926         }
3927
3928         /* XXX: pch pll's can be enabled any time before we enable the PCH
3929          * transcoder, and we actually should do this to not upset any PCH
3930          * transcoder that already use the clock when we share it.
3931          *
3932          * Note that enable_shared_dpll tries to do the right thing, but
3933          * get_shared_dpll unconditionally resets the pll - we need that to have
3934          * the right LVDS enable sequence. */
3935         intel_enable_shared_dpll(intel_crtc);
3936
3937         /* set transcoder timing, panel must allow it */
3938         assert_panel_unlocked(dev_priv, pipe);
3939         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3940
3941         intel_fdi_normal_train(crtc);
3942
3943         /* For PCH DP, enable TRANS_DP_CTL */
3944         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3945                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3946                 reg = TRANS_DP_CTL(pipe);
3947                 temp = I915_READ(reg);
3948                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3949                           TRANS_DP_SYNC_MASK |
3950                           TRANS_DP_BPC_MASK);
3951                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3952                          TRANS_DP_ENH_FRAMING);
3953                 temp |= bpc << 9; /* same format but at 11:9 */
3954
3955                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3956                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3957                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3958                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3959
3960                 switch (intel_trans_dp_port_sel(crtc)) {
3961                 case PCH_DP_B:
3962                         temp |= TRANS_DP_PORT_SEL_B;
3963                         break;
3964                 case PCH_DP_C:
3965                         temp |= TRANS_DP_PORT_SEL_C;
3966                         break;
3967                 case PCH_DP_D:
3968                         temp |= TRANS_DP_PORT_SEL_D;
3969                         break;
3970                 default:
3971                         BUG();
3972                 }
3973
3974                 I915_WRITE(reg, temp);
3975         }
3976
3977         ironlake_enable_pch_transcoder(dev_priv, pipe);
3978 }
3979
3980 static void lpt_pch_enable(struct drm_crtc *crtc)
3981 {
3982         struct drm_device *dev = crtc->dev;
3983         struct drm_i915_private *dev_priv = dev->dev_private;
3984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3985         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3986
3987         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3988
3989         lpt_program_iclkip(crtc);
3990
3991         /* Set transcoder timing. */
3992         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3993
3994         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3995 }
3996
3997 void intel_put_shared_dpll(struct intel_crtc *crtc)
3998 {
3999         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4000
4001         if (pll == NULL)
4002                 return;
4003
4004         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4005                 WARN(1, "bad %s crtc mask\n", pll->name);
4006                 return;
4007         }
4008
4009         pll->config.crtc_mask &= ~(1 << crtc->pipe);
4010         if (pll->config.crtc_mask == 0) {
4011                 WARN_ON(pll->on);
4012                 WARN_ON(pll->active);
4013         }
4014
4015         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4016 }
4017
4018 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4019                                                 struct intel_crtc_state *crtc_state)
4020 {
4021         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4022         struct intel_shared_dpll *pll;
4023         enum intel_dpll_id i;
4024
4025         if (HAS_PCH_IBX(dev_priv->dev)) {
4026                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4027                 i = (enum intel_dpll_id) crtc->pipe;
4028                 pll = &dev_priv->shared_dplls[i];
4029
4030                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4031                               crtc->base.base.id, pll->name);
4032
4033                 WARN_ON(pll->new_config->crtc_mask);
4034
4035                 goto found;
4036         }
4037
4038         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4039                 pll = &dev_priv->shared_dplls[i];
4040
4041                 /* Only want to check enabled timings first */
4042                 if (pll->new_config->crtc_mask == 0)
4043                         continue;
4044
4045                 if (memcmp(&crtc_state->dpll_hw_state,
4046                            &pll->new_config->hw_state,
4047                            sizeof(pll->new_config->hw_state)) == 0) {
4048                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4049                                       crtc->base.base.id, pll->name,
4050                                       pll->new_config->crtc_mask,
4051                                       pll->active);
4052                         goto found;
4053                 }
4054         }
4055
4056         /* Ok no matching timings, maybe there's a free one? */
4057         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4058                 pll = &dev_priv->shared_dplls[i];
4059                 if (pll->new_config->crtc_mask == 0) {
4060                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4061                                       crtc->base.base.id, pll->name);
4062                         goto found;
4063                 }
4064         }
4065
4066         return NULL;
4067
4068 found:
4069         if (pll->new_config->crtc_mask == 0)
4070                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4071
4072         crtc_state->shared_dpll = i;
4073         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4074                          pipe_name(crtc->pipe));
4075
4076         pll->new_config->crtc_mask |= 1 << crtc->pipe;
4077
4078         return pll;
4079 }
4080
4081 /**
4082  * intel_shared_dpll_start_config - start a new PLL staged config
4083  * @dev_priv: DRM device
4084  * @clear_pipes: mask of pipes that will have their PLLs freed
4085  *
4086  * Starts a new PLL staged config, copying the current config but
4087  * releasing the references of pipes specified in clear_pipes.
4088  */
4089 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4090                                           unsigned clear_pipes)
4091 {
4092         struct intel_shared_dpll *pll;
4093         enum intel_dpll_id i;
4094
4095         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4096                 pll = &dev_priv->shared_dplls[i];
4097
4098                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4099                                           GFP_KERNEL);
4100                 if (!pll->new_config)
4101                         goto cleanup;
4102
4103                 pll->new_config->crtc_mask &= ~clear_pipes;
4104         }
4105
4106         return 0;
4107
4108 cleanup:
4109         while (--i >= 0) {
4110                 pll = &dev_priv->shared_dplls[i];
4111                 kfree(pll->new_config);
4112                 pll->new_config = NULL;
4113         }
4114
4115         return -ENOMEM;
4116 }
4117
4118 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4119 {
4120         struct intel_shared_dpll *pll;
4121         enum intel_dpll_id i;
4122
4123         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4124                 pll = &dev_priv->shared_dplls[i];
4125
4126                 WARN_ON(pll->new_config == &pll->config);
4127
4128                 pll->config = *pll->new_config;
4129                 kfree(pll->new_config);
4130                 pll->new_config = NULL;
4131         }
4132 }
4133
4134 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4135 {
4136         struct intel_shared_dpll *pll;
4137         enum intel_dpll_id i;
4138
4139         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4140                 pll = &dev_priv->shared_dplls[i];
4141
4142                 WARN_ON(pll->new_config == &pll->config);
4143
4144                 kfree(pll->new_config);
4145                 pll->new_config = NULL;
4146         }
4147 }
4148
4149 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4150 {
4151         struct drm_i915_private *dev_priv = dev->dev_private;
4152         int dslreg = PIPEDSL(pipe);
4153         u32 temp;
4154
4155         temp = I915_READ(dslreg);
4156         udelay(500);
4157         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4158                 if (wait_for(I915_READ(dslreg) != temp, 5))
4159                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4160         }
4161 }
4162
4163 static void skylake_pfit_enable(struct intel_crtc *crtc)
4164 {
4165         struct drm_device *dev = crtc->base.dev;
4166         struct drm_i915_private *dev_priv = dev->dev_private;
4167         int pipe = crtc->pipe;
4168
4169         if (crtc->config->pch_pfit.enabled) {
4170                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4171                 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4172                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4173         }
4174 }
4175
4176 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4177 {
4178         struct drm_device *dev = crtc->base.dev;
4179         struct drm_i915_private *dev_priv = dev->dev_private;
4180         int pipe = crtc->pipe;
4181
4182         if (crtc->config->pch_pfit.enabled) {
4183                 /* Force use of hard-coded filter coefficients
4184                  * as some pre-programmed values are broken,
4185                  * e.g. x201.
4186                  */
4187                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4188                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4189                                                  PF_PIPE_SEL_IVB(pipe));
4190                 else
4191                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4192                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4193                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4194         }
4195 }
4196
4197 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4198 {
4199         struct drm_device *dev = crtc->dev;
4200         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4201         struct drm_plane *plane;
4202         struct intel_plane *intel_plane;
4203
4204         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4205                 intel_plane = to_intel_plane(plane);
4206                 if (intel_plane->pipe == pipe)
4207                         intel_plane_restore(&intel_plane->base);
4208         }
4209 }
4210
4211 /*
4212  * Disable a plane internally without actually modifying the plane's state.
4213  * This will allow us to easily restore the plane later by just reprogramming
4214  * its state.
4215  */
4216 static void disable_plane_internal(struct drm_plane *plane)
4217 {
4218         struct intel_plane *intel_plane = to_intel_plane(plane);
4219         struct drm_plane_state *state =
4220                 plane->funcs->atomic_duplicate_state(plane);
4221         struct intel_plane_state *intel_state = to_intel_plane_state(state);
4222
4223         intel_state->visible = false;
4224         intel_plane->commit_plane(plane, intel_state);
4225
4226         intel_plane_destroy_state(plane, state);
4227 }
4228
4229 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4230 {
4231         struct drm_device *dev = crtc->dev;
4232         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4233         struct drm_plane *plane;
4234         struct intel_plane *intel_plane;
4235
4236         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4237                 intel_plane = to_intel_plane(plane);
4238                 if (plane->fb && intel_plane->pipe == pipe)
4239                         disable_plane_internal(plane);
4240         }
4241 }
4242
4243 void hsw_enable_ips(struct intel_crtc *crtc)
4244 {
4245         struct drm_device *dev = crtc->base.dev;
4246         struct drm_i915_private *dev_priv = dev->dev_private;
4247
4248         if (!crtc->config->ips_enabled)
4249                 return;
4250
4251         /* We can only enable IPS after we enable a plane and wait for a vblank */
4252         intel_wait_for_vblank(dev, crtc->pipe);
4253
4254         assert_plane_enabled(dev_priv, crtc->plane);
4255         if (IS_BROADWELL(dev)) {
4256                 mutex_lock(&dev_priv->rps.hw_lock);
4257                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4258                 mutex_unlock(&dev_priv->rps.hw_lock);
4259                 /* Quoting Art Runyan: "its not safe to expect any particular
4260                  * value in IPS_CTL bit 31 after enabling IPS through the
4261                  * mailbox." Moreover, the mailbox may return a bogus state,
4262                  * so we need to just enable it and continue on.
4263                  */
4264         } else {
4265                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4266                 /* The bit only becomes 1 in the next vblank, so this wait here
4267                  * is essentially intel_wait_for_vblank. If we don't have this
4268                  * and don't wait for vblanks until the end of crtc_enable, then
4269                  * the HW state readout code will complain that the expected
4270                  * IPS_CTL value is not the one we read. */
4271                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4272                         DRM_ERROR("Timed out waiting for IPS enable\n");
4273         }
4274 }
4275
4276 void hsw_disable_ips(struct intel_crtc *crtc)
4277 {
4278         struct drm_device *dev = crtc->base.dev;
4279         struct drm_i915_private *dev_priv = dev->dev_private;
4280
4281         if (!crtc->config->ips_enabled)
4282                 return;
4283
4284         assert_plane_enabled(dev_priv, crtc->plane);
4285         if (IS_BROADWELL(dev)) {
4286                 mutex_lock(&dev_priv->rps.hw_lock);
4287                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4288                 mutex_unlock(&dev_priv->rps.hw_lock);
4289                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4290                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4291                         DRM_ERROR("Timed out waiting for IPS disable\n");
4292         } else {
4293                 I915_WRITE(IPS_CTL, 0);
4294                 POSTING_READ(IPS_CTL);
4295         }
4296
4297         /* We need to wait for a vblank before we can disable the plane. */
4298         intel_wait_for_vblank(dev, crtc->pipe);
4299 }
4300
4301 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4302 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4303 {
4304         struct drm_device *dev = crtc->dev;
4305         struct drm_i915_private *dev_priv = dev->dev_private;
4306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4307         enum pipe pipe = intel_crtc->pipe;
4308         int palreg = PALETTE(pipe);
4309         int i;
4310         bool reenable_ips = false;
4311
4312         /* The clocks have to be on to load the palette. */
4313         if (!crtc->state->enable || !intel_crtc->active)
4314                 return;
4315
4316         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4317                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4318                         assert_dsi_pll_enabled(dev_priv);
4319                 else
4320                         assert_pll_enabled(dev_priv, pipe);
4321         }
4322
4323         /* use legacy palette for Ironlake */
4324         if (!HAS_GMCH_DISPLAY(dev))
4325                 palreg = LGC_PALETTE(pipe);
4326
4327         /* Workaround : Do not read or write the pipe palette/gamma data while
4328          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4329          */
4330         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4331             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4332              GAMMA_MODE_MODE_SPLIT)) {
4333                 hsw_disable_ips(intel_crtc);
4334                 reenable_ips = true;
4335         }
4336
4337         for (i = 0; i < 256; i++) {
4338                 I915_WRITE(palreg + 4 * i,
4339                            (intel_crtc->lut_r[i] << 16) |
4340                            (intel_crtc->lut_g[i] << 8) |
4341                            intel_crtc->lut_b[i]);
4342         }
4343
4344         if (reenable_ips)
4345                 hsw_enable_ips(intel_crtc);
4346 }
4347
4348 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4349 {
4350         if (!enable && intel_crtc->overlay) {
4351                 struct drm_device *dev = intel_crtc->base.dev;
4352                 struct drm_i915_private *dev_priv = dev->dev_private;
4353
4354                 mutex_lock(&dev->struct_mutex);
4355                 dev_priv->mm.interruptible = false;
4356                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4357                 dev_priv->mm.interruptible = true;
4358                 mutex_unlock(&dev->struct_mutex);
4359         }
4360
4361         /* Let userspace switch the overlay on again. In most cases userspace
4362          * has to recompute where to put it anyway.
4363          */
4364 }
4365
4366 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4367 {
4368         struct drm_device *dev = crtc->dev;
4369         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4370         int pipe = intel_crtc->pipe;
4371
4372         intel_enable_primary_hw_plane(crtc->primary, crtc);
4373         intel_enable_sprite_planes(crtc);
4374         intel_crtc_update_cursor(crtc, true);
4375         intel_crtc_dpms_overlay(intel_crtc, true);
4376
4377         hsw_enable_ips(intel_crtc);
4378
4379         mutex_lock(&dev->struct_mutex);
4380         intel_fbc_update(dev);
4381         mutex_unlock(&dev->struct_mutex);
4382
4383         /*
4384          * FIXME: Once we grow proper nuclear flip support out of this we need
4385          * to compute the mask of flip planes precisely. For the time being
4386          * consider this a flip from a NULL plane.
4387          */
4388         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4389 }
4390
4391 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4392 {
4393         struct drm_device *dev = crtc->dev;
4394         struct drm_i915_private *dev_priv = dev->dev_private;
4395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4396         int pipe = intel_crtc->pipe;
4397
4398         intel_crtc_wait_for_pending_flips(crtc);
4399
4400         if (dev_priv->fbc.crtc == intel_crtc)
4401                 intel_fbc_disable(dev);
4402
4403         hsw_disable_ips(intel_crtc);
4404
4405         intel_crtc_dpms_overlay(intel_crtc, false);
4406         intel_crtc_update_cursor(crtc, false);
4407         intel_disable_sprite_planes(crtc);
4408         intel_disable_primary_hw_plane(crtc->primary, crtc);
4409
4410         /*
4411          * FIXME: Once we grow proper nuclear flip support out of this we need
4412          * to compute the mask of flip planes precisely. For the time being
4413          * consider this a flip to a NULL plane.
4414          */
4415         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4416 }
4417
4418 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4419 {
4420         struct drm_device *dev = crtc->dev;
4421         struct drm_i915_private *dev_priv = dev->dev_private;
4422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4423         struct intel_encoder *encoder;
4424         int pipe = intel_crtc->pipe;
4425
4426         WARN_ON(!crtc->state->enable);
4427
4428         if (intel_crtc->active)
4429                 return;
4430
4431         if (intel_crtc->config->has_pch_encoder)
4432                 intel_prepare_shared_dpll(intel_crtc);
4433
4434         if (intel_crtc->config->has_dp_encoder)
4435                 intel_dp_set_m_n(intel_crtc, M1_N1);
4436
4437         intel_set_pipe_timings(intel_crtc);
4438
4439         if (intel_crtc->config->has_pch_encoder) {
4440                 intel_cpu_transcoder_set_m_n(intel_crtc,
4441                                      &intel_crtc->config->fdi_m_n, NULL);
4442         }
4443
4444         ironlake_set_pipeconf(crtc);
4445
4446         intel_crtc->active = true;
4447
4448         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4449         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4450
4451         for_each_encoder_on_crtc(dev, crtc, encoder)
4452                 if (encoder->pre_enable)
4453                         encoder->pre_enable(encoder);
4454
4455         if (intel_crtc->config->has_pch_encoder) {
4456                 /* Note: FDI PLL enabling _must_ be done before we enable the
4457                  * cpu pipes, hence this is separate from all the other fdi/pch
4458                  * enabling. */
4459                 ironlake_fdi_pll_enable(intel_crtc);
4460         } else {
4461                 assert_fdi_tx_disabled(dev_priv, pipe);
4462                 assert_fdi_rx_disabled(dev_priv, pipe);
4463         }
4464
4465         ironlake_pfit_enable(intel_crtc);
4466
4467         /*
4468          * On ILK+ LUT must be loaded before the pipe is running but with
4469          * clocks enabled
4470          */
4471         intel_crtc_load_lut(crtc);
4472
4473         intel_update_watermarks(crtc);
4474         intel_enable_pipe(intel_crtc);
4475
4476         if (intel_crtc->config->has_pch_encoder)
4477                 ironlake_pch_enable(crtc);
4478
4479         assert_vblank_disabled(crtc);
4480         drm_crtc_vblank_on(crtc);
4481
4482         for_each_encoder_on_crtc(dev, crtc, encoder)
4483                 encoder->enable(encoder);
4484
4485         if (HAS_PCH_CPT(dev))
4486                 cpt_verify_modeset(dev, intel_crtc->pipe);
4487
4488         intel_crtc_enable_planes(crtc);
4489 }
4490
4491 /* IPS only exists on ULT machines and is tied to pipe A. */
4492 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4493 {
4494         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4495 }
4496
4497 /*
4498  * This implements the workaround described in the "notes" section of the mode
4499  * set sequence documentation. When going from no pipes or single pipe to
4500  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4501  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4502  */
4503 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4504 {
4505         struct drm_device *dev = crtc->base.dev;
4506         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4507
4508         /* We want to get the other_active_crtc only if there's only 1 other
4509          * active crtc. */
4510         for_each_intel_crtc(dev, crtc_it) {
4511                 if (!crtc_it->active || crtc_it == crtc)
4512                         continue;
4513
4514                 if (other_active_crtc)
4515                         return;
4516
4517                 other_active_crtc = crtc_it;
4518         }
4519         if (!other_active_crtc)
4520                 return;
4521
4522         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4523         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4524 }
4525
4526 static void haswell_crtc_enable(struct drm_crtc *crtc)
4527 {
4528         struct drm_device *dev = crtc->dev;
4529         struct drm_i915_private *dev_priv = dev->dev_private;
4530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4531         struct intel_encoder *encoder;
4532         int pipe = intel_crtc->pipe;
4533
4534         WARN_ON(!crtc->state->enable);
4535
4536         if (intel_crtc->active)
4537                 return;
4538
4539         if (intel_crtc_to_shared_dpll(intel_crtc))
4540                 intel_enable_shared_dpll(intel_crtc);
4541
4542         if (intel_crtc->config->has_dp_encoder)
4543                 intel_dp_set_m_n(intel_crtc, M1_N1);
4544
4545         intel_set_pipe_timings(intel_crtc);
4546
4547         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4548                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4549                            intel_crtc->config->pixel_multiplier - 1);
4550         }
4551
4552         if (intel_crtc->config->has_pch_encoder) {
4553                 intel_cpu_transcoder_set_m_n(intel_crtc,
4554                                      &intel_crtc->config->fdi_m_n, NULL);
4555         }
4556
4557         haswell_set_pipeconf(crtc);
4558
4559         intel_set_pipe_csc(crtc);
4560
4561         intel_crtc->active = true;
4562
4563         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4564         for_each_encoder_on_crtc(dev, crtc, encoder)
4565                 if (encoder->pre_enable)
4566                         encoder->pre_enable(encoder);
4567
4568         if (intel_crtc->config->has_pch_encoder) {
4569                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4570                                                       true);
4571                 dev_priv->display.fdi_link_train(crtc);
4572         }
4573
4574         intel_ddi_enable_pipe_clock(intel_crtc);
4575
4576         if (IS_SKYLAKE(dev))
4577                 skylake_pfit_enable(intel_crtc);
4578         else
4579                 ironlake_pfit_enable(intel_crtc);
4580
4581         /*
4582          * On ILK+ LUT must be loaded before the pipe is running but with
4583          * clocks enabled
4584          */
4585         intel_crtc_load_lut(crtc);
4586
4587         intel_ddi_set_pipe_settings(crtc);
4588         intel_ddi_enable_transcoder_func(crtc);
4589
4590         intel_update_watermarks(crtc);
4591         intel_enable_pipe(intel_crtc);
4592
4593         if (intel_crtc->config->has_pch_encoder)
4594                 lpt_pch_enable(crtc);
4595
4596         if (intel_crtc->config->dp_encoder_is_mst)
4597                 intel_ddi_set_vc_payload_alloc(crtc, true);
4598
4599         assert_vblank_disabled(crtc);
4600         drm_crtc_vblank_on(crtc);
4601
4602         for_each_encoder_on_crtc(dev, crtc, encoder) {
4603                 encoder->enable(encoder);
4604                 intel_opregion_notify_encoder(encoder, true);
4605         }
4606
4607         /* If we change the relative order between pipe/planes enabling, we need
4608          * to change the workaround. */
4609         haswell_mode_set_planes_workaround(intel_crtc);
4610         intel_crtc_enable_planes(crtc);
4611 }
4612
4613 static void skylake_pfit_disable(struct intel_crtc *crtc)
4614 {
4615         struct drm_device *dev = crtc->base.dev;
4616         struct drm_i915_private *dev_priv = dev->dev_private;
4617         int pipe = crtc->pipe;
4618
4619         /* To avoid upsetting the power well on haswell only disable the pfit if
4620          * it's in use. The hw state code will make sure we get this right. */
4621         if (crtc->config->pch_pfit.enabled) {
4622                 I915_WRITE(PS_CTL(pipe), 0);
4623                 I915_WRITE(PS_WIN_POS(pipe), 0);
4624                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4625         }
4626 }
4627
4628 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4629 {
4630         struct drm_device *dev = crtc->base.dev;
4631         struct drm_i915_private *dev_priv = dev->dev_private;
4632         int pipe = crtc->pipe;
4633
4634         /* To avoid upsetting the power well on haswell only disable the pfit if
4635          * it's in use. The hw state code will make sure we get this right. */
4636         if (crtc->config->pch_pfit.enabled) {
4637                 I915_WRITE(PF_CTL(pipe), 0);
4638                 I915_WRITE(PF_WIN_POS(pipe), 0);
4639                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4640         }
4641 }
4642
4643 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4644 {
4645         struct drm_device *dev = crtc->dev;
4646         struct drm_i915_private *dev_priv = dev->dev_private;
4647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4648         struct intel_encoder *encoder;
4649         int pipe = intel_crtc->pipe;
4650         u32 reg, temp;
4651
4652         if (!intel_crtc->active)
4653                 return;
4654
4655         intel_crtc_disable_planes(crtc);
4656
4657         for_each_encoder_on_crtc(dev, crtc, encoder)
4658                 encoder->disable(encoder);
4659
4660         drm_crtc_vblank_off(crtc);
4661         assert_vblank_disabled(crtc);
4662
4663         if (intel_crtc->config->has_pch_encoder)
4664                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4665
4666         intel_disable_pipe(intel_crtc);
4667
4668         ironlake_pfit_disable(intel_crtc);
4669
4670         for_each_encoder_on_crtc(dev, crtc, encoder)
4671                 if (encoder->post_disable)
4672                         encoder->post_disable(encoder);
4673
4674         if (intel_crtc->config->has_pch_encoder) {
4675                 ironlake_fdi_disable(crtc);
4676
4677                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4678
4679                 if (HAS_PCH_CPT(dev)) {
4680                         /* disable TRANS_DP_CTL */
4681                         reg = TRANS_DP_CTL(pipe);
4682                         temp = I915_READ(reg);
4683                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4684                                   TRANS_DP_PORT_SEL_MASK);
4685                         temp |= TRANS_DP_PORT_SEL_NONE;
4686                         I915_WRITE(reg, temp);
4687
4688                         /* disable DPLL_SEL */
4689                         temp = I915_READ(PCH_DPLL_SEL);
4690                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4691                         I915_WRITE(PCH_DPLL_SEL, temp);
4692                 }
4693
4694                 /* disable PCH DPLL */
4695                 intel_disable_shared_dpll(intel_crtc);
4696
4697                 ironlake_fdi_pll_disable(intel_crtc);
4698         }
4699
4700         intel_crtc->active = false;
4701         intel_update_watermarks(crtc);
4702
4703         mutex_lock(&dev->struct_mutex);
4704         intel_fbc_update(dev);
4705         mutex_unlock(&dev->struct_mutex);
4706 }
4707
4708 static void haswell_crtc_disable(struct drm_crtc *crtc)
4709 {
4710         struct drm_device *dev = crtc->dev;
4711         struct drm_i915_private *dev_priv = dev->dev_private;
4712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713         struct intel_encoder *encoder;
4714         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4715
4716         if (!intel_crtc->active)
4717                 return;
4718
4719         intel_crtc_disable_planes(crtc);
4720
4721         for_each_encoder_on_crtc(dev, crtc, encoder) {
4722                 intel_opregion_notify_encoder(encoder, false);
4723                 encoder->disable(encoder);
4724         }
4725
4726         drm_crtc_vblank_off(crtc);
4727         assert_vblank_disabled(crtc);
4728
4729         if (intel_crtc->config->has_pch_encoder)
4730                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4731                                                       false);
4732         intel_disable_pipe(intel_crtc);
4733
4734         if (intel_crtc->config->dp_encoder_is_mst)
4735                 intel_ddi_set_vc_payload_alloc(crtc, false);
4736
4737         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4738
4739         if (IS_SKYLAKE(dev))
4740                 skylake_pfit_disable(intel_crtc);
4741         else
4742                 ironlake_pfit_disable(intel_crtc);
4743
4744         intel_ddi_disable_pipe_clock(intel_crtc);
4745
4746         if (intel_crtc->config->has_pch_encoder) {
4747                 lpt_disable_pch_transcoder(dev_priv);
4748                 intel_ddi_fdi_disable(crtc);
4749         }
4750
4751         for_each_encoder_on_crtc(dev, crtc, encoder)
4752                 if (encoder->post_disable)
4753                         encoder->post_disable(encoder);
4754
4755         intel_crtc->active = false;
4756         intel_update_watermarks(crtc);
4757
4758         mutex_lock(&dev->struct_mutex);
4759         intel_fbc_update(dev);
4760         mutex_unlock(&dev->struct_mutex);
4761
4762         if (intel_crtc_to_shared_dpll(intel_crtc))
4763                 intel_disable_shared_dpll(intel_crtc);
4764 }
4765
4766 static void ironlake_crtc_off(struct drm_crtc *crtc)
4767 {
4768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4769         intel_put_shared_dpll(intel_crtc);
4770 }
4771
4772
4773 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4774 {
4775         struct drm_device *dev = crtc->base.dev;
4776         struct drm_i915_private *dev_priv = dev->dev_private;
4777         struct intel_crtc_state *pipe_config = crtc->config;
4778
4779         if (!pipe_config->gmch_pfit.control)
4780                 return;
4781
4782         /*
4783          * The panel fitter should only be adjusted whilst the pipe is disabled,
4784          * according to register description and PRM.
4785          */
4786         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4787         assert_pipe_disabled(dev_priv, crtc->pipe);
4788
4789         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4790         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4791
4792         /* Border color in case we don't scale up to the full screen. Black by
4793          * default, change to something else for debugging. */
4794         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4795 }
4796
4797 static enum intel_display_power_domain port_to_power_domain(enum port port)
4798 {
4799         switch (port) {
4800         case PORT_A:
4801                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4802         case PORT_B:
4803                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4804         case PORT_C:
4805                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4806         case PORT_D:
4807                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4808         default:
4809                 WARN_ON_ONCE(1);
4810                 return POWER_DOMAIN_PORT_OTHER;
4811         }
4812 }
4813
4814 #define for_each_power_domain(domain, mask)                             \
4815         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4816                 if ((1 << (domain)) & (mask))
4817
4818 enum intel_display_power_domain
4819 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4820 {
4821         struct drm_device *dev = intel_encoder->base.dev;
4822         struct intel_digital_port *intel_dig_port;
4823
4824         switch (intel_encoder->type) {
4825         case INTEL_OUTPUT_UNKNOWN:
4826                 /* Only DDI platforms should ever use this output type */
4827                 WARN_ON_ONCE(!HAS_DDI(dev));
4828         case INTEL_OUTPUT_DISPLAYPORT:
4829         case INTEL_OUTPUT_HDMI:
4830         case INTEL_OUTPUT_EDP:
4831                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4832                 return port_to_power_domain(intel_dig_port->port);
4833         case INTEL_OUTPUT_DP_MST:
4834                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4835                 return port_to_power_domain(intel_dig_port->port);
4836         case INTEL_OUTPUT_ANALOG:
4837                 return POWER_DOMAIN_PORT_CRT;
4838         case INTEL_OUTPUT_DSI:
4839                 return POWER_DOMAIN_PORT_DSI;
4840         default:
4841                 return POWER_DOMAIN_PORT_OTHER;
4842         }
4843 }
4844
4845 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4846 {
4847         struct drm_device *dev = crtc->dev;
4848         struct intel_encoder *intel_encoder;
4849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4850         enum pipe pipe = intel_crtc->pipe;
4851         unsigned long mask;
4852         enum transcoder transcoder;
4853
4854         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4855
4856         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4857         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4858         if (intel_crtc->config->pch_pfit.enabled ||
4859             intel_crtc->config->pch_pfit.force_thru)
4860                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4861
4862         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4863                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4864
4865         return mask;
4866 }
4867
4868 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4869 {
4870         struct drm_i915_private *dev_priv = dev->dev_private;
4871         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4872         struct intel_crtc *crtc;
4873
4874         /*
4875          * First get all needed power domains, then put all unneeded, to avoid
4876          * any unnecessary toggling of the power wells.
4877          */
4878         for_each_intel_crtc(dev, crtc) {
4879                 enum intel_display_power_domain domain;
4880
4881                 if (!crtc->base.state->enable)
4882                         continue;
4883
4884                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4885
4886                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4887                         intel_display_power_get(dev_priv, domain);
4888         }
4889
4890         if (dev_priv->display.modeset_global_resources)
4891                 dev_priv->display.modeset_global_resources(dev);
4892
4893         for_each_intel_crtc(dev, crtc) {
4894                 enum intel_display_power_domain domain;
4895
4896                 for_each_power_domain(domain, crtc->enabled_power_domains)
4897                         intel_display_power_put(dev_priv, domain);
4898
4899                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4900         }
4901
4902         intel_display_set_init_power(dev_priv, false);
4903 }
4904
4905 /* returns HPLL frequency in kHz */
4906 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4907 {
4908         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4909
4910         /* Obtain SKU information */
4911         mutex_lock(&dev_priv->dpio_lock);
4912         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4913                 CCK_FUSE_HPLL_FREQ_MASK;
4914         mutex_unlock(&dev_priv->dpio_lock);
4915
4916         return vco_freq[hpll_freq] * 1000;
4917 }
4918
4919 static void vlv_update_cdclk(struct drm_device *dev)
4920 {
4921         struct drm_i915_private *dev_priv = dev->dev_private;
4922
4923         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4924         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4925                          dev_priv->vlv_cdclk_freq);
4926
4927         /*
4928          * Program the gmbus_freq based on the cdclk frequency.
4929          * BSpec erroneously claims we should aim for 4MHz, but
4930          * in fact 1MHz is the correct frequency.
4931          */
4932         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4933 }
4934
4935 /* Adjust CDclk dividers to allow high res or save power if possible */
4936 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4937 {
4938         struct drm_i915_private *dev_priv = dev->dev_private;
4939         u32 val, cmd;
4940
4941         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4942
4943         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4944                 cmd = 2;
4945         else if (cdclk == 266667)
4946                 cmd = 1;
4947         else
4948                 cmd = 0;
4949
4950         mutex_lock(&dev_priv->rps.hw_lock);
4951         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4952         val &= ~DSPFREQGUAR_MASK;
4953         val |= (cmd << DSPFREQGUAR_SHIFT);
4954         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4955         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4956                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4957                      50)) {
4958                 DRM_ERROR("timed out waiting for CDclk change\n");
4959         }
4960         mutex_unlock(&dev_priv->rps.hw_lock);
4961
4962         if (cdclk == 400000) {
4963                 u32 divider;
4964
4965                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4966
4967                 mutex_lock(&dev_priv->dpio_lock);
4968                 /* adjust cdclk divider */
4969                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4970                 val &= ~DISPLAY_FREQUENCY_VALUES;
4971                 val |= divider;
4972                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4973
4974                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4975                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4976                              50))
4977                         DRM_ERROR("timed out waiting for CDclk change\n");
4978                 mutex_unlock(&dev_priv->dpio_lock);
4979         }
4980
4981         mutex_lock(&dev_priv->dpio_lock);
4982         /* adjust self-refresh exit latency value */
4983         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4984         val &= ~0x7f;
4985
4986         /*
4987          * For high bandwidth configs, we set a higher latency in the bunit
4988          * so that the core display fetch happens in time to avoid underruns.
4989          */
4990         if (cdclk == 400000)
4991                 val |= 4500 / 250; /* 4.5 usec */
4992         else
4993                 val |= 3000 / 250; /* 3.0 usec */
4994         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4995         mutex_unlock(&dev_priv->dpio_lock);
4996
4997         vlv_update_cdclk(dev);
4998 }
4999
5000 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5001 {
5002         struct drm_i915_private *dev_priv = dev->dev_private;
5003         u32 val, cmd;
5004
5005         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5006
5007         switch (cdclk) {
5008         case 333333:
5009         case 320000:
5010         case 266667:
5011         case 200000:
5012                 break;
5013         default:
5014                 MISSING_CASE(cdclk);
5015                 return;
5016         }
5017
5018         /*
5019          * Specs are full of misinformation, but testing on actual
5020          * hardware has shown that we just need to write the desired
5021          * CCK divider into the Punit register.
5022          */
5023         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5024
5025         mutex_lock(&dev_priv->rps.hw_lock);
5026         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5027         val &= ~DSPFREQGUAR_MASK_CHV;
5028         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5029         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5030         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5031                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5032                      50)) {
5033                 DRM_ERROR("timed out waiting for CDclk change\n");
5034         }
5035         mutex_unlock(&dev_priv->rps.hw_lock);
5036
5037         vlv_update_cdclk(dev);
5038 }
5039
5040 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5041                                  int max_pixclk)
5042 {
5043         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5044         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5045
5046         /*
5047          * Really only a few cases to deal with, as only 4 CDclks are supported:
5048          *   200MHz
5049          *   267MHz
5050          *   320/333MHz (depends on HPLL freq)
5051          *   400MHz (VLV only)
5052          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5053          * of the lower bin and adjust if needed.
5054          *
5055          * We seem to get an unstable or solid color picture at 200MHz.
5056          * Not sure what's wrong. For now use 200MHz only when all pipes
5057          * are off.
5058          */
5059         if (!IS_CHERRYVIEW(dev_priv) &&
5060             max_pixclk > freq_320*limit/100)
5061                 return 400000;
5062         else if (max_pixclk > 266667*limit/100)
5063                 return freq_320;
5064         else if (max_pixclk > 0)
5065                 return 266667;
5066         else
5067                 return 200000;
5068 }
5069
5070 /* compute the max pixel clock for new configuration */
5071 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5072 {
5073         struct drm_device *dev = dev_priv->dev;
5074         struct intel_crtc *intel_crtc;
5075         int max_pixclk = 0;
5076
5077         for_each_intel_crtc(dev, intel_crtc) {
5078                 if (intel_crtc->new_enabled)
5079                         max_pixclk = max(max_pixclk,
5080                                          intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5081         }
5082
5083         return max_pixclk;
5084 }
5085
5086 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5087                                             unsigned *prepare_pipes)
5088 {
5089         struct drm_i915_private *dev_priv = dev->dev_private;
5090         struct intel_crtc *intel_crtc;
5091         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5092
5093         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5094             dev_priv->vlv_cdclk_freq)
5095                 return;
5096
5097         /* disable/enable all currently active pipes while we change cdclk */
5098         for_each_intel_crtc(dev, intel_crtc)
5099                 if (intel_crtc->base.state->enable)
5100                         *prepare_pipes |= (1 << intel_crtc->pipe);
5101 }
5102
5103 static void valleyview_modeset_global_resources(struct drm_device *dev)
5104 {
5105         struct drm_i915_private *dev_priv = dev->dev_private;
5106         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5107         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5108
5109         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5110                 /*
5111                  * FIXME: We can end up here with all power domains off, yet
5112                  * with a CDCLK frequency other than the minimum. To account
5113                  * for this take the PIPE-A power domain, which covers the HW
5114                  * blocks needed for the following programming. This can be
5115                  * removed once it's guaranteed that we get here either with
5116                  * the minimum CDCLK set, or the required power domains
5117                  * enabled.
5118                  */
5119                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5120
5121                 if (IS_CHERRYVIEW(dev))
5122                         cherryview_set_cdclk(dev, req_cdclk);
5123                 else
5124                         valleyview_set_cdclk(dev, req_cdclk);
5125
5126                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5127         }
5128 }
5129
5130 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5131 {
5132         struct drm_device *dev = crtc->dev;
5133         struct drm_i915_private *dev_priv = to_i915(dev);
5134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5135         struct intel_encoder *encoder;
5136         int pipe = intel_crtc->pipe;
5137         bool is_dsi;
5138
5139         WARN_ON(!crtc->state->enable);
5140
5141         if (intel_crtc->active)
5142                 return;
5143
5144         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5145
5146         if (!is_dsi) {
5147                 if (IS_CHERRYVIEW(dev))
5148                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5149                 else
5150                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5151         }
5152
5153         if (intel_crtc->config->has_dp_encoder)
5154                 intel_dp_set_m_n(intel_crtc, M1_N1);
5155
5156         intel_set_pipe_timings(intel_crtc);
5157
5158         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5159                 struct drm_i915_private *dev_priv = dev->dev_private;
5160
5161                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5162                 I915_WRITE(CHV_CANVAS(pipe), 0);
5163         }
5164
5165         i9xx_set_pipeconf(intel_crtc);
5166
5167         intel_crtc->active = true;
5168
5169         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5170
5171         for_each_encoder_on_crtc(dev, crtc, encoder)
5172                 if (encoder->pre_pll_enable)
5173                         encoder->pre_pll_enable(encoder);
5174
5175         if (!is_dsi) {
5176                 if (IS_CHERRYVIEW(dev))
5177                         chv_enable_pll(intel_crtc, intel_crtc->config);
5178                 else
5179                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5180         }
5181
5182         for_each_encoder_on_crtc(dev, crtc, encoder)
5183                 if (encoder->pre_enable)
5184                         encoder->pre_enable(encoder);
5185
5186         i9xx_pfit_enable(intel_crtc);
5187
5188         intel_crtc_load_lut(crtc);
5189
5190         intel_update_watermarks(crtc);
5191         intel_enable_pipe(intel_crtc);
5192
5193         assert_vblank_disabled(crtc);
5194         drm_crtc_vblank_on(crtc);
5195
5196         for_each_encoder_on_crtc(dev, crtc, encoder)
5197                 encoder->enable(encoder);
5198
5199         intel_crtc_enable_planes(crtc);
5200
5201         /* Underruns don't raise interrupts, so check manually. */
5202         i9xx_check_fifo_underruns(dev_priv);
5203 }
5204
5205 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5206 {
5207         struct drm_device *dev = crtc->base.dev;
5208         struct drm_i915_private *dev_priv = dev->dev_private;
5209
5210         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5211         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5212 }
5213
5214 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5215 {
5216         struct drm_device *dev = crtc->dev;
5217         struct drm_i915_private *dev_priv = to_i915(dev);
5218         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5219         struct intel_encoder *encoder;
5220         int pipe = intel_crtc->pipe;
5221
5222         WARN_ON(!crtc->state->enable);
5223
5224         if (intel_crtc->active)
5225                 return;
5226
5227         i9xx_set_pll_dividers(intel_crtc);
5228
5229         if (intel_crtc->config->has_dp_encoder)
5230                 intel_dp_set_m_n(intel_crtc, M1_N1);
5231
5232         intel_set_pipe_timings(intel_crtc);
5233
5234         i9xx_set_pipeconf(intel_crtc);
5235
5236         intel_crtc->active = true;
5237
5238         if (!IS_GEN2(dev))
5239                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5240
5241         for_each_encoder_on_crtc(dev, crtc, encoder)
5242                 if (encoder->pre_enable)
5243                         encoder->pre_enable(encoder);
5244
5245         i9xx_enable_pll(intel_crtc);
5246
5247         i9xx_pfit_enable(intel_crtc);
5248
5249         intel_crtc_load_lut(crtc);
5250
5251         intel_update_watermarks(crtc);
5252         intel_enable_pipe(intel_crtc);
5253
5254         assert_vblank_disabled(crtc);
5255         drm_crtc_vblank_on(crtc);
5256
5257         for_each_encoder_on_crtc(dev, crtc, encoder)
5258                 encoder->enable(encoder);
5259
5260         intel_crtc_enable_planes(crtc);
5261
5262         /*
5263          * Gen2 reports pipe underruns whenever all planes are disabled.
5264          * So don't enable underrun reporting before at least some planes
5265          * are enabled.
5266          * FIXME: Need to fix the logic to work when we turn off all planes
5267          * but leave the pipe running.
5268          */
5269         if (IS_GEN2(dev))
5270                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5271
5272         /* Underruns don't raise interrupts, so check manually. */
5273         i9xx_check_fifo_underruns(dev_priv);
5274 }
5275
5276 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5277 {
5278         struct drm_device *dev = crtc->base.dev;
5279         struct drm_i915_private *dev_priv = dev->dev_private;
5280
5281         if (!crtc->config->gmch_pfit.control)
5282                 return;
5283
5284         assert_pipe_disabled(dev_priv, crtc->pipe);
5285
5286         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5287                          I915_READ(PFIT_CONTROL));
5288         I915_WRITE(PFIT_CONTROL, 0);
5289 }
5290
5291 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5292 {
5293         struct drm_device *dev = crtc->dev;
5294         struct drm_i915_private *dev_priv = dev->dev_private;
5295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5296         struct intel_encoder *encoder;
5297         int pipe = intel_crtc->pipe;
5298
5299         if (!intel_crtc->active)
5300                 return;
5301
5302         /*
5303          * Gen2 reports pipe underruns whenever all planes are disabled.
5304          * So diasble underrun reporting before all the planes get disabled.
5305          * FIXME: Need to fix the logic to work when we turn off all planes
5306          * but leave the pipe running.
5307          */
5308         if (IS_GEN2(dev))
5309                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5310
5311         /*
5312          * Vblank time updates from the shadow to live plane control register
5313          * are blocked if the memory self-refresh mode is active at that
5314          * moment. So to make sure the plane gets truly disabled, disable
5315          * first the self-refresh mode. The self-refresh enable bit in turn
5316          * will be checked/applied by the HW only at the next frame start
5317          * event which is after the vblank start event, so we need to have a
5318          * wait-for-vblank between disabling the plane and the pipe.
5319          */
5320         intel_set_memory_cxsr(dev_priv, false);
5321         intel_crtc_disable_planes(crtc);
5322
5323         /*
5324          * On gen2 planes are double buffered but the pipe isn't, so we must
5325          * wait for planes to fully turn off before disabling the pipe.
5326          * We also need to wait on all gmch platforms because of the
5327          * self-refresh mode constraint explained above.
5328          */
5329         intel_wait_for_vblank(dev, pipe);
5330
5331         for_each_encoder_on_crtc(dev, crtc, encoder)
5332                 encoder->disable(encoder);
5333
5334         drm_crtc_vblank_off(crtc);
5335         assert_vblank_disabled(crtc);
5336
5337         intel_disable_pipe(intel_crtc);
5338
5339         i9xx_pfit_disable(intel_crtc);
5340
5341         for_each_encoder_on_crtc(dev, crtc, encoder)
5342                 if (encoder->post_disable)
5343                         encoder->post_disable(encoder);
5344
5345         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5346                 if (IS_CHERRYVIEW(dev))
5347                         chv_disable_pll(dev_priv, pipe);
5348                 else if (IS_VALLEYVIEW(dev))
5349                         vlv_disable_pll(dev_priv, pipe);
5350                 else
5351                         i9xx_disable_pll(intel_crtc);
5352         }
5353
5354         if (!IS_GEN2(dev))
5355                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5356
5357         intel_crtc->active = false;
5358         intel_update_watermarks(crtc);
5359
5360         mutex_lock(&dev->struct_mutex);
5361         intel_fbc_update(dev);
5362         mutex_unlock(&dev->struct_mutex);
5363 }
5364
5365 static void i9xx_crtc_off(struct drm_crtc *crtc)
5366 {
5367 }
5368
5369 /* Master function to enable/disable CRTC and corresponding power wells */
5370 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5371 {
5372         struct drm_device *dev = crtc->dev;
5373         struct drm_i915_private *dev_priv = dev->dev_private;
5374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5375         enum intel_display_power_domain domain;
5376         unsigned long domains;
5377
5378         if (enable) {
5379                 if (!intel_crtc->active) {
5380                         domains = get_crtc_power_domains(crtc);
5381                         for_each_power_domain(domain, domains)
5382                                 intel_display_power_get(dev_priv, domain);
5383                         intel_crtc->enabled_power_domains = domains;
5384
5385                         dev_priv->display.crtc_enable(crtc);
5386                 }
5387         } else {
5388                 if (intel_crtc->active) {
5389                         dev_priv->display.crtc_disable(crtc);
5390
5391                         domains = intel_crtc->enabled_power_domains;
5392                         for_each_power_domain(domain, domains)
5393                                 intel_display_power_put(dev_priv, domain);
5394                         intel_crtc->enabled_power_domains = 0;
5395                 }
5396         }
5397 }
5398
5399 /**
5400  * Sets the power management mode of the pipe and plane.
5401  */
5402 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5403 {
5404         struct drm_device *dev = crtc->dev;
5405         struct intel_encoder *intel_encoder;
5406         bool enable = false;
5407
5408         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5409                 enable |= intel_encoder->connectors_active;
5410
5411         intel_crtc_control(crtc, enable);
5412 }
5413
5414 static void intel_crtc_disable(struct drm_crtc *crtc)
5415 {
5416         struct drm_device *dev = crtc->dev;
5417         struct drm_connector *connector;
5418         struct drm_i915_private *dev_priv = dev->dev_private;
5419
5420         /* crtc should still be enabled when we disable it. */
5421         WARN_ON(!crtc->state->enable);
5422
5423         dev_priv->display.crtc_disable(crtc);
5424         dev_priv->display.off(crtc);
5425
5426         crtc->primary->funcs->disable_plane(crtc->primary);
5427
5428         /* Update computed state. */
5429         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5430                 if (!connector->encoder || !connector->encoder->crtc)
5431                         continue;
5432
5433                 if (connector->encoder->crtc != crtc)
5434                         continue;
5435
5436                 connector->dpms = DRM_MODE_DPMS_OFF;
5437                 to_intel_encoder(connector->encoder)->connectors_active = false;
5438         }
5439 }
5440
5441 void intel_encoder_destroy(struct drm_encoder *encoder)
5442 {
5443         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5444
5445         drm_encoder_cleanup(encoder);
5446         kfree(intel_encoder);
5447 }
5448
5449 /* Simple dpms helper for encoders with just one connector, no cloning and only
5450  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5451  * state of the entire output pipe. */
5452 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5453 {
5454         if (mode == DRM_MODE_DPMS_ON) {
5455                 encoder->connectors_active = true;
5456
5457                 intel_crtc_update_dpms(encoder->base.crtc);
5458         } else {
5459                 encoder->connectors_active = false;
5460
5461                 intel_crtc_update_dpms(encoder->base.crtc);
5462         }
5463 }
5464
5465 /* Cross check the actual hw state with our own modeset state tracking (and it's
5466  * internal consistency). */
5467 static void intel_connector_check_state(struct intel_connector *connector)
5468 {
5469         if (connector->get_hw_state(connector)) {
5470                 struct intel_encoder *encoder = connector->encoder;
5471                 struct drm_crtc *crtc;
5472                 bool encoder_enabled;
5473                 enum pipe pipe;
5474
5475                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5476                               connector->base.base.id,
5477                               connector->base.name);
5478
5479                 /* there is no real hw state for MST connectors */
5480                 if (connector->mst_port)
5481                         return;
5482
5483                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5484                      "wrong connector dpms state\n");
5485                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5486                      "active connector not linked to encoder\n");
5487
5488                 if (encoder) {
5489                         I915_STATE_WARN(!encoder->connectors_active,
5490                              "encoder->connectors_active not set\n");
5491
5492                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5493                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5494                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
5495                                 return;
5496
5497                         crtc = encoder->base.crtc;
5498
5499                         I915_STATE_WARN(!crtc->state->enable,
5500                                         "crtc not enabled\n");
5501                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5502                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5503                              "encoder active on the wrong pipe\n");
5504                 }
5505         }
5506 }
5507
5508 /* Even simpler default implementation, if there's really no special case to
5509  * consider. */
5510 void intel_connector_dpms(struct drm_connector *connector, int mode)
5511 {
5512         /* All the simple cases only support two dpms states. */
5513         if (mode != DRM_MODE_DPMS_ON)
5514                 mode = DRM_MODE_DPMS_OFF;
5515
5516         if (mode == connector->dpms)
5517                 return;
5518
5519         connector->dpms = mode;
5520
5521         /* Only need to change hw state when actually enabled */
5522         if (connector->encoder)
5523                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5524
5525         intel_modeset_check_state(connector->dev);
5526 }
5527
5528 /* Simple connector->get_hw_state implementation for encoders that support only
5529  * one connector and no cloning and hence the encoder state determines the state
5530  * of the connector. */
5531 bool intel_connector_get_hw_state(struct intel_connector *connector)
5532 {
5533         enum pipe pipe = 0;
5534         struct intel_encoder *encoder = connector->encoder;
5535
5536         return encoder->get_hw_state(encoder, &pipe);
5537 }
5538
5539 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5540                                      struct intel_crtc_state *pipe_config)
5541 {
5542         struct drm_i915_private *dev_priv = dev->dev_private;
5543         struct intel_crtc *pipe_B_crtc =
5544                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5545
5546         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5547                       pipe_name(pipe), pipe_config->fdi_lanes);
5548         if (pipe_config->fdi_lanes > 4) {
5549                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5550                               pipe_name(pipe), pipe_config->fdi_lanes);
5551                 return false;
5552         }
5553
5554         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5555                 if (pipe_config->fdi_lanes > 2) {
5556                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5557                                       pipe_config->fdi_lanes);
5558                         return false;
5559                 } else {
5560                         return true;
5561                 }
5562         }
5563
5564         if (INTEL_INFO(dev)->num_pipes == 2)
5565                 return true;
5566
5567         /* Ivybridge 3 pipe is really complicated */
5568         switch (pipe) {
5569         case PIPE_A:
5570                 return true;
5571         case PIPE_B:
5572                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5573                     pipe_config->fdi_lanes > 2) {
5574                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5575                                       pipe_name(pipe), pipe_config->fdi_lanes);
5576                         return false;
5577                 }
5578                 return true;
5579         case PIPE_C:
5580                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5581                     pipe_B_crtc->config->fdi_lanes <= 2) {
5582                         if (pipe_config->fdi_lanes > 2) {
5583                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5584                                               pipe_name(pipe), pipe_config->fdi_lanes);
5585                                 return false;
5586                         }
5587                 } else {
5588                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5589                         return false;
5590                 }
5591                 return true;
5592         default:
5593                 BUG();
5594         }
5595 }
5596
5597 #define RETRY 1
5598 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5599                                        struct intel_crtc_state *pipe_config)
5600 {
5601         struct drm_device *dev = intel_crtc->base.dev;
5602         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5603         int lane, link_bw, fdi_dotclock;
5604         bool setup_ok, needs_recompute = false;
5605
5606 retry:
5607         /* FDI is a binary signal running at ~2.7GHz, encoding
5608          * each output octet as 10 bits. The actual frequency
5609          * is stored as a divider into a 100MHz clock, and the
5610          * mode pixel clock is stored in units of 1KHz.
5611          * Hence the bw of each lane in terms of the mode signal
5612          * is:
5613          */
5614         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5615
5616         fdi_dotclock = adjusted_mode->crtc_clock;
5617
5618         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5619                                            pipe_config->pipe_bpp);
5620
5621         pipe_config->fdi_lanes = lane;
5622
5623         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5624                                link_bw, &pipe_config->fdi_m_n);
5625
5626         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5627                                             intel_crtc->pipe, pipe_config);
5628         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5629                 pipe_config->pipe_bpp -= 2*3;
5630                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5631                               pipe_config->pipe_bpp);
5632                 needs_recompute = true;
5633                 pipe_config->bw_constrained = true;
5634
5635                 goto retry;
5636         }
5637
5638         if (needs_recompute)
5639                 return RETRY;
5640
5641         return setup_ok ? 0 : -EINVAL;
5642 }
5643
5644 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5645                                    struct intel_crtc_state *pipe_config)
5646 {
5647         pipe_config->ips_enabled = i915.enable_ips &&
5648                                    hsw_crtc_supports_ips(crtc) &&
5649                                    pipe_config->pipe_bpp <= 24;
5650 }
5651
5652 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5653                                      struct intel_crtc_state *pipe_config)
5654 {
5655         struct drm_device *dev = crtc->base.dev;
5656         struct drm_i915_private *dev_priv = dev->dev_private;
5657         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5658
5659         /* FIXME should check pixel clock limits on all platforms */
5660         if (INTEL_INFO(dev)->gen < 4) {
5661                 int clock_limit =
5662                         dev_priv->display.get_display_clock_speed(dev);
5663
5664                 /*
5665                  * Enable pixel doubling when the dot clock
5666                  * is > 90% of the (display) core speed.
5667                  *
5668                  * GDG double wide on either pipe,
5669                  * otherwise pipe A only.
5670                  */
5671                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5672                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5673                         clock_limit *= 2;
5674                         pipe_config->double_wide = true;
5675                 }
5676
5677                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5678                         return -EINVAL;
5679         }
5680
5681         /*
5682          * Pipe horizontal size must be even in:
5683          * - DVO ganged mode
5684          * - LVDS dual channel mode
5685          * - Double wide pipe
5686          */
5687         if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5688              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5689                 pipe_config->pipe_src_w &= ~1;
5690
5691         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5692          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5693          */
5694         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5695                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5696                 return -EINVAL;
5697
5698         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5699                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5700         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5701                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5702                  * for lvds. */
5703                 pipe_config->pipe_bpp = 8*3;
5704         }
5705
5706         if (HAS_IPS(dev))
5707                 hsw_compute_ips_config(crtc, pipe_config);
5708
5709         if (pipe_config->has_pch_encoder)
5710                 return ironlake_fdi_compute_config(crtc, pipe_config);
5711
5712         return 0;
5713 }
5714
5715 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5716 {
5717         struct drm_i915_private *dev_priv = dev->dev_private;
5718         u32 val;
5719         int divider;
5720
5721         if (dev_priv->hpll_freq == 0)
5722                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5723
5724         mutex_lock(&dev_priv->dpio_lock);
5725         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5726         mutex_unlock(&dev_priv->dpio_lock);
5727
5728         divider = val & DISPLAY_FREQUENCY_VALUES;
5729
5730         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5731              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5732              "cdclk change in progress\n");
5733
5734         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5735 }
5736
5737 static int i945_get_display_clock_speed(struct drm_device *dev)
5738 {
5739         return 400000;
5740 }
5741
5742 static int i915_get_display_clock_speed(struct drm_device *dev)
5743 {
5744         return 333000;
5745 }
5746
5747 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5748 {
5749         return 200000;
5750 }
5751
5752 static int pnv_get_display_clock_speed(struct drm_device *dev)
5753 {
5754         u16 gcfgc = 0;
5755
5756         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5757
5758         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5759         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5760                 return 267000;
5761         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5762                 return 333000;
5763         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5764                 return 444000;
5765         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5766                 return 200000;
5767         default:
5768                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5769         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5770                 return 133000;
5771         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5772                 return 167000;
5773         }
5774 }
5775
5776 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5777 {
5778         u16 gcfgc = 0;
5779
5780         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5781
5782         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5783                 return 133000;
5784         else {
5785                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5786                 case GC_DISPLAY_CLOCK_333_MHZ:
5787                         return 333000;
5788                 default:
5789                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5790                         return 190000;
5791                 }
5792         }
5793 }
5794
5795 static int i865_get_display_clock_speed(struct drm_device *dev)
5796 {
5797         return 266000;
5798 }
5799
5800 static int i855_get_display_clock_speed(struct drm_device *dev)
5801 {
5802         u16 hpllcc = 0;
5803         /* Assume that the hardware is in the high speed state.  This
5804          * should be the default.
5805          */
5806         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5807         case GC_CLOCK_133_200:
5808         case GC_CLOCK_100_200:
5809                 return 200000;
5810         case GC_CLOCK_166_250:
5811                 return 250000;
5812         case GC_CLOCK_100_133:
5813                 return 133000;
5814         }
5815
5816         /* Shouldn't happen */
5817         return 0;
5818 }
5819
5820 static int i830_get_display_clock_speed(struct drm_device *dev)
5821 {
5822         return 133000;
5823 }
5824
5825 static void
5826 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5827 {
5828         while (*num > DATA_LINK_M_N_MASK ||
5829                *den > DATA_LINK_M_N_MASK) {
5830                 *num >>= 1;
5831                 *den >>= 1;
5832         }
5833 }
5834
5835 static void compute_m_n(unsigned int m, unsigned int n,
5836                         uint32_t *ret_m, uint32_t *ret_n)
5837 {
5838         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5839         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5840         intel_reduce_m_n_ratio(ret_m, ret_n);
5841 }
5842
5843 void
5844 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5845                        int pixel_clock, int link_clock,
5846                        struct intel_link_m_n *m_n)
5847 {
5848         m_n->tu = 64;
5849
5850         compute_m_n(bits_per_pixel * pixel_clock,
5851                     link_clock * nlanes * 8,
5852                     &m_n->gmch_m, &m_n->gmch_n);
5853
5854         compute_m_n(pixel_clock, link_clock,
5855                     &m_n->link_m, &m_n->link_n);
5856 }
5857
5858 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5859 {
5860         if (i915.panel_use_ssc >= 0)
5861                 return i915.panel_use_ssc != 0;
5862         return dev_priv->vbt.lvds_use_ssc
5863                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5864 }
5865
5866 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5867 {
5868         struct drm_device *dev = crtc->base.dev;
5869         struct drm_i915_private *dev_priv = dev->dev_private;
5870         int refclk;
5871
5872         if (IS_VALLEYVIEW(dev)) {
5873                 refclk = 100000;
5874         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5875             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5876                 refclk = dev_priv->vbt.lvds_ssc_freq;
5877                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5878         } else if (!IS_GEN2(dev)) {
5879                 refclk = 96000;
5880         } else {
5881                 refclk = 48000;
5882         }
5883
5884         return refclk;
5885 }
5886
5887 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5888 {
5889         return (1 << dpll->n) << 16 | dpll->m2;
5890 }
5891
5892 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5893 {
5894         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5895 }
5896
5897 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5898                                      struct intel_crtc_state *crtc_state,
5899                                      intel_clock_t *reduced_clock)
5900 {
5901         struct drm_device *dev = crtc->base.dev;
5902         u32 fp, fp2 = 0;
5903
5904         if (IS_PINEVIEW(dev)) {
5905                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5906                 if (reduced_clock)
5907                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5908         } else {
5909                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5910                 if (reduced_clock)
5911                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5912         }
5913
5914         crtc_state->dpll_hw_state.fp0 = fp;
5915
5916         crtc->lowfreq_avail = false;
5917         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5918             reduced_clock && i915.powersave) {
5919                 crtc_state->dpll_hw_state.fp1 = fp2;
5920                 crtc->lowfreq_avail = true;
5921         } else {
5922                 crtc_state->dpll_hw_state.fp1 = fp;
5923         }
5924 }
5925
5926 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5927                 pipe)
5928 {
5929         u32 reg_val;
5930
5931         /*
5932          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5933          * and set it to a reasonable value instead.
5934          */
5935         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5936         reg_val &= 0xffffff00;
5937         reg_val |= 0x00000030;
5938         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5939
5940         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5941         reg_val &= 0x8cffffff;
5942         reg_val = 0x8c000000;
5943         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5944
5945         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5946         reg_val &= 0xffffff00;
5947         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5948
5949         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5950         reg_val &= 0x00ffffff;
5951         reg_val |= 0xb0000000;
5952         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5953 }
5954
5955 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5956                                          struct intel_link_m_n *m_n)
5957 {
5958         struct drm_device *dev = crtc->base.dev;
5959         struct drm_i915_private *dev_priv = dev->dev_private;
5960         int pipe = crtc->pipe;
5961
5962         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5963         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5964         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5965         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5966 }
5967
5968 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5969                                          struct intel_link_m_n *m_n,
5970                                          struct intel_link_m_n *m2_n2)
5971 {
5972         struct drm_device *dev = crtc->base.dev;
5973         struct drm_i915_private *dev_priv = dev->dev_private;
5974         int pipe = crtc->pipe;
5975         enum transcoder transcoder = crtc->config->cpu_transcoder;
5976
5977         if (INTEL_INFO(dev)->gen >= 5) {
5978                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5979                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5980                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5981                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5982                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5983                  * for gen < 8) and if DRRS is supported (to make sure the
5984                  * registers are not unnecessarily accessed).
5985                  */
5986                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5987                         crtc->config->has_drrs) {
5988                         I915_WRITE(PIPE_DATA_M2(transcoder),
5989                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5990                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5991                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5992                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5993                 }
5994         } else {
5995                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5996                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5997                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5998                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5999         }
6000 }
6001
6002 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6003 {
6004         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6005
6006         if (m_n == M1_N1) {
6007                 dp_m_n = &crtc->config->dp_m_n;
6008                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6009         } else if (m_n == M2_N2) {
6010
6011                 /*
6012                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6013                  * needs to be programmed into M1_N1.
6014                  */
6015                 dp_m_n = &crtc->config->dp_m2_n2;
6016         } else {
6017                 DRM_ERROR("Unsupported divider value\n");
6018                 return;
6019         }
6020
6021         if (crtc->config->has_pch_encoder)
6022                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6023         else
6024                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6025 }
6026
6027 static void vlv_update_pll(struct intel_crtc *crtc,
6028                            struct intel_crtc_state *pipe_config)
6029 {
6030         u32 dpll, dpll_md;
6031
6032         /*
6033          * Enable DPIO clock input. We should never disable the reference
6034          * clock for pipe B, since VGA hotplug / manual detection depends
6035          * on it.
6036          */
6037         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6038                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6039         /* We should never disable this, set it here for state tracking */
6040         if (crtc->pipe == PIPE_B)
6041                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6042         dpll |= DPLL_VCO_ENABLE;
6043         pipe_config->dpll_hw_state.dpll = dpll;
6044
6045         dpll_md = (pipe_config->pixel_multiplier - 1)
6046                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6047         pipe_config->dpll_hw_state.dpll_md = dpll_md;
6048 }
6049
6050 static void vlv_prepare_pll(struct intel_crtc *crtc,
6051                             const struct intel_crtc_state *pipe_config)
6052 {
6053         struct drm_device *dev = crtc->base.dev;
6054         struct drm_i915_private *dev_priv = dev->dev_private;
6055         int pipe = crtc->pipe;
6056         u32 mdiv;
6057         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6058         u32 coreclk, reg_val;
6059
6060         mutex_lock(&dev_priv->dpio_lock);
6061
6062         bestn = pipe_config->dpll.n;
6063         bestm1 = pipe_config->dpll.m1;
6064         bestm2 = pipe_config->dpll.m2;
6065         bestp1 = pipe_config->dpll.p1;
6066         bestp2 = pipe_config->dpll.p2;
6067
6068         /* See eDP HDMI DPIO driver vbios notes doc */
6069
6070         /* PLL B needs special handling */
6071         if (pipe == PIPE_B)
6072                 vlv_pllb_recal_opamp(dev_priv, pipe);
6073
6074         /* Set up Tx target for periodic Rcomp update */
6075         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6076
6077         /* Disable target IRef on PLL */
6078         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6079         reg_val &= 0x00ffffff;
6080         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6081
6082         /* Disable fast lock */
6083         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6084
6085         /* Set idtafcrecal before PLL is enabled */
6086         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6087         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6088         mdiv |= ((bestn << DPIO_N_SHIFT));
6089         mdiv |= (1 << DPIO_K_SHIFT);
6090
6091         /*
6092          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6093          * but we don't support that).
6094          * Note: don't use the DAC post divider as it seems unstable.
6095          */
6096         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6097         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6098
6099         mdiv |= DPIO_ENABLE_CALIBRATION;
6100         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6101
6102         /* Set HBR and RBR LPF coefficients */
6103         if (pipe_config->port_clock == 162000 ||
6104             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6105             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6106                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6107                                  0x009f0003);
6108         else
6109                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6110                                  0x00d0000f);
6111
6112         if (pipe_config->has_dp_encoder) {
6113                 /* Use SSC source */
6114                 if (pipe == PIPE_A)
6115                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6116                                          0x0df40000);
6117                 else
6118                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6119                                          0x0df70000);
6120         } else { /* HDMI or VGA */
6121                 /* Use bend source */
6122                 if (pipe == PIPE_A)
6123                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6124                                          0x0df70000);
6125                 else
6126                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6127                                          0x0df40000);
6128         }
6129
6130         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6131         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6132         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6133             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6134                 coreclk |= 0x01000000;
6135         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6136
6137         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6138         mutex_unlock(&dev_priv->dpio_lock);
6139 }
6140
6141 static void chv_update_pll(struct intel_crtc *crtc,
6142                            struct intel_crtc_state *pipe_config)
6143 {
6144         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6145                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6146                 DPLL_VCO_ENABLE;
6147         if (crtc->pipe != PIPE_A)
6148                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6149
6150         pipe_config->dpll_hw_state.dpll_md =
6151                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6152 }
6153
6154 static void chv_prepare_pll(struct intel_crtc *crtc,
6155                             const struct intel_crtc_state *pipe_config)
6156 {
6157         struct drm_device *dev = crtc->base.dev;
6158         struct drm_i915_private *dev_priv = dev->dev_private;
6159         int pipe = crtc->pipe;
6160         int dpll_reg = DPLL(crtc->pipe);
6161         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6162         u32 loopfilter, intcoeff;
6163         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6164         u32 dpio_val;
6165         int refclk;
6166
6167         bestn = pipe_config->dpll.n;
6168         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6169         bestm1 = pipe_config->dpll.m1;
6170         bestm2 = pipe_config->dpll.m2 >> 22;
6171         bestp1 = pipe_config->dpll.p1;
6172         bestp2 = pipe_config->dpll.p2;
6173         dpio_val = 0;
6174
6175         /*
6176          * Enable Refclk and SSC
6177          */
6178         I915_WRITE(dpll_reg,
6179                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6180
6181         mutex_lock(&dev_priv->dpio_lock);
6182
6183         /* p1 and p2 divider */
6184         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6185                         5 << DPIO_CHV_S1_DIV_SHIFT |
6186                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6187                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6188                         1 << DPIO_CHV_K_DIV_SHIFT);
6189
6190         /* Feedback post-divider - m2 */
6191         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6192
6193         /* Feedback refclk divider - n and m1 */
6194         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6195                         DPIO_CHV_M1_DIV_BY_2 |
6196                         1 << DPIO_CHV_N_DIV_SHIFT);
6197
6198         /* M2 fraction division */
6199         if (bestm2_frac)
6200                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6201
6202         /* M2 fraction division enable */
6203         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6204         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6205         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6206         if (bestm2_frac)
6207                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6208         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6209
6210         /* Program digital lock detect threshold */
6211         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6212         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6213                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6214         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6215         if (!bestm2_frac)
6216                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6217         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6218
6219         /* Loop filter */
6220         refclk = i9xx_get_refclk(crtc, 0);
6221         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6222                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6223         if (refclk == 100000)
6224                 intcoeff = 11;
6225         else if (refclk == 38400)
6226                 intcoeff = 10;
6227         else
6228                 intcoeff = 9;
6229         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6230         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6231
6232         /* AFC Recal */
6233         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6234                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6235                         DPIO_AFC_RECAL);
6236
6237         mutex_unlock(&dev_priv->dpio_lock);
6238 }
6239
6240 /**
6241  * vlv_force_pll_on - forcibly enable just the PLL
6242  * @dev_priv: i915 private structure
6243  * @pipe: pipe PLL to enable
6244  * @dpll: PLL configuration
6245  *
6246  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6247  * in cases where we need the PLL enabled even when @pipe is not going to
6248  * be enabled.
6249  */
6250 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6251                       const struct dpll *dpll)
6252 {
6253         struct intel_crtc *crtc =
6254                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6255         struct intel_crtc_state pipe_config = {
6256                 .pixel_multiplier = 1,
6257                 .dpll = *dpll,
6258         };
6259
6260         if (IS_CHERRYVIEW(dev)) {
6261                 chv_update_pll(crtc, &pipe_config);
6262                 chv_prepare_pll(crtc, &pipe_config);
6263                 chv_enable_pll(crtc, &pipe_config);
6264         } else {
6265                 vlv_update_pll(crtc, &pipe_config);
6266                 vlv_prepare_pll(crtc, &pipe_config);
6267                 vlv_enable_pll(crtc, &pipe_config);
6268         }
6269 }
6270
6271 /**
6272  * vlv_force_pll_off - forcibly disable just the PLL
6273  * @dev_priv: i915 private structure
6274  * @pipe: pipe PLL to disable
6275  *
6276  * Disable the PLL for @pipe. To be used in cases where we need
6277  * the PLL enabled even when @pipe is not going to be enabled.
6278  */
6279 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6280 {
6281         if (IS_CHERRYVIEW(dev))
6282                 chv_disable_pll(to_i915(dev), pipe);
6283         else
6284                 vlv_disable_pll(to_i915(dev), pipe);
6285 }
6286
6287 static void i9xx_update_pll(struct intel_crtc *crtc,
6288                             struct intel_crtc_state *crtc_state,
6289                             intel_clock_t *reduced_clock,
6290                             int num_connectors)
6291 {
6292         struct drm_device *dev = crtc->base.dev;
6293         struct drm_i915_private *dev_priv = dev->dev_private;
6294         u32 dpll;
6295         bool is_sdvo;
6296         struct dpll *clock = &crtc_state->dpll;
6297
6298         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6299
6300         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6301                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6302
6303         dpll = DPLL_VGA_MODE_DIS;
6304
6305         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6306                 dpll |= DPLLB_MODE_LVDS;
6307         else
6308                 dpll |= DPLLB_MODE_DAC_SERIAL;
6309
6310         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6311                 dpll |= (crtc_state->pixel_multiplier - 1)
6312                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6313         }
6314
6315         if (is_sdvo)
6316                 dpll |= DPLL_SDVO_HIGH_SPEED;
6317
6318         if (crtc_state->has_dp_encoder)
6319                 dpll |= DPLL_SDVO_HIGH_SPEED;
6320
6321         /* compute bitmask from p1 value */
6322         if (IS_PINEVIEW(dev))
6323                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6324         else {
6325                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6326                 if (IS_G4X(dev) && reduced_clock)
6327                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6328         }
6329         switch (clock->p2) {
6330         case 5:
6331                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6332                 break;
6333         case 7:
6334                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6335                 break;
6336         case 10:
6337                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6338                 break;
6339         case 14:
6340                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6341                 break;
6342         }
6343         if (INTEL_INFO(dev)->gen >= 4)
6344                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6345
6346         if (crtc_state->sdvo_tv_clock)
6347                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6348         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6349                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6350                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6351         else
6352                 dpll |= PLL_REF_INPUT_DREFCLK;
6353
6354         dpll |= DPLL_VCO_ENABLE;
6355         crtc_state->dpll_hw_state.dpll = dpll;
6356
6357         if (INTEL_INFO(dev)->gen >= 4) {
6358                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6359                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6360                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6361         }
6362 }
6363
6364 static void i8xx_update_pll(struct intel_crtc *crtc,
6365                             struct intel_crtc_state *crtc_state,
6366                             intel_clock_t *reduced_clock,
6367                             int num_connectors)
6368 {
6369         struct drm_device *dev = crtc->base.dev;
6370         struct drm_i915_private *dev_priv = dev->dev_private;
6371         u32 dpll;
6372         struct dpll *clock = &crtc_state->dpll;
6373
6374         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6375
6376         dpll = DPLL_VGA_MODE_DIS;
6377
6378         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6379                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6380         } else {
6381                 if (clock->p1 == 2)
6382                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6383                 else
6384                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6385                 if (clock->p2 == 4)
6386                         dpll |= PLL_P2_DIVIDE_BY_4;
6387         }
6388
6389         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6390                 dpll |= DPLL_DVO_2X_MODE;
6391
6392         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6393                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6394                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6395         else
6396                 dpll |= PLL_REF_INPUT_DREFCLK;
6397
6398         dpll |= DPLL_VCO_ENABLE;
6399         crtc_state->dpll_hw_state.dpll = dpll;
6400 }
6401
6402 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6403 {
6404         struct drm_device *dev = intel_crtc->base.dev;
6405         struct drm_i915_private *dev_priv = dev->dev_private;
6406         enum pipe pipe = intel_crtc->pipe;
6407         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6408         struct drm_display_mode *adjusted_mode =
6409                 &intel_crtc->config->base.adjusted_mode;
6410         uint32_t crtc_vtotal, crtc_vblank_end;
6411         int vsyncshift = 0;
6412
6413         /* We need to be careful not to changed the adjusted mode, for otherwise
6414          * the hw state checker will get angry at the mismatch. */
6415         crtc_vtotal = adjusted_mode->crtc_vtotal;
6416         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6417
6418         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6419                 /* the chip adds 2 halflines automatically */
6420                 crtc_vtotal -= 1;
6421                 crtc_vblank_end -= 1;
6422
6423                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6424                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6425                 else
6426                         vsyncshift = adjusted_mode->crtc_hsync_start -
6427                                 adjusted_mode->crtc_htotal / 2;
6428                 if (vsyncshift < 0)
6429                         vsyncshift += adjusted_mode->crtc_htotal;
6430         }
6431
6432         if (INTEL_INFO(dev)->gen > 3)
6433                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6434
6435         I915_WRITE(HTOTAL(cpu_transcoder),
6436                    (adjusted_mode->crtc_hdisplay - 1) |
6437                    ((adjusted_mode->crtc_htotal - 1) << 16));
6438         I915_WRITE(HBLANK(cpu_transcoder),
6439                    (adjusted_mode->crtc_hblank_start - 1) |
6440                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6441         I915_WRITE(HSYNC(cpu_transcoder),
6442                    (adjusted_mode->crtc_hsync_start - 1) |
6443                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6444
6445         I915_WRITE(VTOTAL(cpu_transcoder),
6446                    (adjusted_mode->crtc_vdisplay - 1) |
6447                    ((crtc_vtotal - 1) << 16));
6448         I915_WRITE(VBLANK(cpu_transcoder),
6449                    (adjusted_mode->crtc_vblank_start - 1) |
6450                    ((crtc_vblank_end - 1) << 16));
6451         I915_WRITE(VSYNC(cpu_transcoder),
6452                    (adjusted_mode->crtc_vsync_start - 1) |
6453                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6454
6455         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6456          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6457          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6458          * bits. */
6459         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6460             (pipe == PIPE_B || pipe == PIPE_C))
6461                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6462
6463         /* pipesrc controls the size that is scaled from, which should
6464          * always be the user's requested size.
6465          */
6466         I915_WRITE(PIPESRC(pipe),
6467                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6468                    (intel_crtc->config->pipe_src_h - 1));
6469 }
6470
6471 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6472                                    struct intel_crtc_state *pipe_config)
6473 {
6474         struct drm_device *dev = crtc->base.dev;
6475         struct drm_i915_private *dev_priv = dev->dev_private;
6476         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6477         uint32_t tmp;
6478
6479         tmp = I915_READ(HTOTAL(cpu_transcoder));
6480         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6481         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6482         tmp = I915_READ(HBLANK(cpu_transcoder));
6483         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6484         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6485         tmp = I915_READ(HSYNC(cpu_transcoder));
6486         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6487         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6488
6489         tmp = I915_READ(VTOTAL(cpu_transcoder));
6490         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6491         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6492         tmp = I915_READ(VBLANK(cpu_transcoder));
6493         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6494         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6495         tmp = I915_READ(VSYNC(cpu_transcoder));
6496         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6497         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6498
6499         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6500                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6501                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6502                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6503         }
6504
6505         tmp = I915_READ(PIPESRC(crtc->pipe));
6506         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6507         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6508
6509         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6510         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6511 }
6512
6513 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6514                                  struct intel_crtc_state *pipe_config)
6515 {
6516         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6517         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6518         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6519         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6520
6521         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6522         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6523         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6524         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6525
6526         mode->flags = pipe_config->base.adjusted_mode.flags;
6527
6528         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6529         mode->flags |= pipe_config->base.adjusted_mode.flags;
6530 }
6531
6532 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6533 {
6534         struct drm_device *dev = intel_crtc->base.dev;
6535         struct drm_i915_private *dev_priv = dev->dev_private;
6536         uint32_t pipeconf;
6537
6538         pipeconf = 0;
6539
6540         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6541             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6542                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6543
6544         if (intel_crtc->config->double_wide)
6545                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6546
6547         /* only g4x and later have fancy bpc/dither controls */
6548         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6549                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6550                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6551                         pipeconf |= PIPECONF_DITHER_EN |
6552                                     PIPECONF_DITHER_TYPE_SP;
6553
6554                 switch (intel_crtc->config->pipe_bpp) {
6555                 case 18:
6556                         pipeconf |= PIPECONF_6BPC;
6557                         break;
6558                 case 24:
6559                         pipeconf |= PIPECONF_8BPC;
6560                         break;
6561                 case 30:
6562                         pipeconf |= PIPECONF_10BPC;
6563                         break;
6564                 default:
6565                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6566                         BUG();
6567                 }
6568         }
6569
6570         if (HAS_PIPE_CXSR(dev)) {
6571                 if (intel_crtc->lowfreq_avail) {
6572                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6573                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6574                 } else {
6575                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6576                 }
6577         }
6578
6579         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6580                 if (INTEL_INFO(dev)->gen < 4 ||
6581                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6582                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6583                 else
6584                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6585         } else
6586                 pipeconf |= PIPECONF_PROGRESSIVE;
6587
6588         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6589                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6590
6591         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6592         POSTING_READ(PIPECONF(intel_crtc->pipe));
6593 }
6594
6595 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6596                                    struct intel_crtc_state *crtc_state)
6597 {
6598         struct drm_device *dev = crtc->base.dev;
6599         struct drm_i915_private *dev_priv = dev->dev_private;
6600         int refclk, num_connectors = 0;
6601         intel_clock_t clock, reduced_clock;
6602         bool ok, has_reduced_clock = false;
6603         bool is_lvds = false, is_dsi = false;
6604         struct intel_encoder *encoder;
6605         const intel_limit_t *limit;
6606
6607         for_each_intel_encoder(dev, encoder) {
6608                 if (encoder->new_crtc != crtc)
6609                         continue;
6610
6611                 switch (encoder->type) {
6612                 case INTEL_OUTPUT_LVDS:
6613                         is_lvds = true;
6614                         break;
6615                 case INTEL_OUTPUT_DSI:
6616                         is_dsi = true;
6617                         break;
6618                 default:
6619                         break;
6620                 }
6621
6622                 num_connectors++;
6623         }
6624
6625         if (is_dsi)
6626                 return 0;
6627
6628         if (!crtc_state->clock_set) {
6629                 refclk = i9xx_get_refclk(crtc, num_connectors);
6630
6631                 /*
6632                  * Returns a set of divisors for the desired target clock with
6633                  * the given refclk, or FALSE.  The returned values represent
6634                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6635                  * 2) / p1 / p2.
6636                  */
6637                 limit = intel_limit(crtc, refclk);
6638                 ok = dev_priv->display.find_dpll(limit, crtc,
6639                                                  crtc_state->port_clock,
6640                                                  refclk, NULL, &clock);
6641                 if (!ok) {
6642                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6643                         return -EINVAL;
6644                 }
6645
6646                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6647                         /*
6648                          * Ensure we match the reduced clock's P to the target
6649                          * clock.  If the clocks don't match, we can't switch
6650                          * the display clock by using the FP0/FP1. In such case
6651                          * we will disable the LVDS downclock feature.
6652                          */
6653                         has_reduced_clock =
6654                                 dev_priv->display.find_dpll(limit, crtc,
6655                                                             dev_priv->lvds_downclock,
6656                                                             refclk, &clock,
6657                                                             &reduced_clock);
6658                 }
6659                 /* Compat-code for transition, will disappear. */
6660                 crtc_state->dpll.n = clock.n;
6661                 crtc_state->dpll.m1 = clock.m1;
6662                 crtc_state->dpll.m2 = clock.m2;
6663                 crtc_state->dpll.p1 = clock.p1;
6664                 crtc_state->dpll.p2 = clock.p2;
6665         }
6666
6667         if (IS_GEN2(dev)) {
6668                 i8xx_update_pll(crtc, crtc_state,
6669                                 has_reduced_clock ? &reduced_clock : NULL,
6670                                 num_connectors);
6671         } else if (IS_CHERRYVIEW(dev)) {
6672                 chv_update_pll(crtc, crtc_state);
6673         } else if (IS_VALLEYVIEW(dev)) {
6674                 vlv_update_pll(crtc, crtc_state);
6675         } else {
6676                 i9xx_update_pll(crtc, crtc_state,
6677                                 has_reduced_clock ? &reduced_clock : NULL,
6678                                 num_connectors);
6679         }
6680
6681         return 0;
6682 }
6683
6684 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6685                                  struct intel_crtc_state *pipe_config)
6686 {
6687         struct drm_device *dev = crtc->base.dev;
6688         struct drm_i915_private *dev_priv = dev->dev_private;
6689         uint32_t tmp;
6690
6691         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6692                 return;
6693
6694         tmp = I915_READ(PFIT_CONTROL);
6695         if (!(tmp & PFIT_ENABLE))
6696                 return;
6697
6698         /* Check whether the pfit is attached to our pipe. */
6699         if (INTEL_INFO(dev)->gen < 4) {
6700                 if (crtc->pipe != PIPE_B)
6701                         return;
6702         } else {
6703                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6704                         return;
6705         }
6706
6707         pipe_config->gmch_pfit.control = tmp;
6708         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6709         if (INTEL_INFO(dev)->gen < 5)
6710                 pipe_config->gmch_pfit.lvds_border_bits =
6711                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6712 }
6713
6714 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6715                                struct intel_crtc_state *pipe_config)
6716 {
6717         struct drm_device *dev = crtc->base.dev;
6718         struct drm_i915_private *dev_priv = dev->dev_private;
6719         int pipe = pipe_config->cpu_transcoder;
6720         intel_clock_t clock;
6721         u32 mdiv;
6722         int refclk = 100000;
6723
6724         /* In case of MIPI DPLL will not even be used */
6725         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6726                 return;
6727
6728         mutex_lock(&dev_priv->dpio_lock);
6729         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6730         mutex_unlock(&dev_priv->dpio_lock);
6731
6732         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6733         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6734         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6735         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6736         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6737
6738         vlv_clock(refclk, &clock);
6739
6740         /* clock.dot is the fast clock */
6741         pipe_config->port_clock = clock.dot / 5;
6742 }
6743
6744 static void
6745 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6746                               struct intel_initial_plane_config *plane_config)
6747 {
6748         struct drm_device *dev = crtc->base.dev;
6749         struct drm_i915_private *dev_priv = dev->dev_private;
6750         u32 val, base, offset;
6751         int pipe = crtc->pipe, plane = crtc->plane;
6752         int fourcc, pixel_format;
6753         int aligned_height;
6754         struct drm_framebuffer *fb;
6755         struct intel_framebuffer *intel_fb;
6756
6757         val = I915_READ(DSPCNTR(plane));
6758         if (!(val & DISPLAY_PLANE_ENABLE))
6759                 return;
6760
6761         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6762         if (!intel_fb) {
6763                 DRM_DEBUG_KMS("failed to alloc fb\n");
6764                 return;
6765         }
6766
6767         fb = &intel_fb->base;
6768
6769         if (INTEL_INFO(dev)->gen >= 4) {
6770                 if (val & DISPPLANE_TILED) {
6771                         plane_config->tiling = I915_TILING_X;
6772                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6773                 }
6774         }
6775
6776         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6777         fourcc = i9xx_format_to_fourcc(pixel_format);
6778         fb->pixel_format = fourcc;
6779         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6780
6781         if (INTEL_INFO(dev)->gen >= 4) {
6782                 if (plane_config->tiling)
6783                         offset = I915_READ(DSPTILEOFF(plane));
6784                 else
6785                         offset = I915_READ(DSPLINOFF(plane));
6786                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6787         } else {
6788                 base = I915_READ(DSPADDR(plane));
6789         }
6790         plane_config->base = base;
6791
6792         val = I915_READ(PIPESRC(pipe));
6793         fb->width = ((val >> 16) & 0xfff) + 1;
6794         fb->height = ((val >> 0) & 0xfff) + 1;
6795
6796         val = I915_READ(DSPSTRIDE(pipe));
6797         fb->pitches[0] = val & 0xffffffc0;
6798
6799         aligned_height = intel_fb_align_height(dev, fb->height,
6800                                                fb->pixel_format,
6801                                                fb->modifier[0]);
6802
6803         plane_config->size = fb->pitches[0] * aligned_height;
6804
6805         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6806                       pipe_name(pipe), plane, fb->width, fb->height,
6807                       fb->bits_per_pixel, base, fb->pitches[0],
6808                       plane_config->size);
6809
6810         plane_config->fb = intel_fb;
6811 }
6812
6813 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6814                                struct intel_crtc_state *pipe_config)
6815 {
6816         struct drm_device *dev = crtc->base.dev;
6817         struct drm_i915_private *dev_priv = dev->dev_private;
6818         int pipe = pipe_config->cpu_transcoder;
6819         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6820         intel_clock_t clock;
6821         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6822         int refclk = 100000;
6823
6824         mutex_lock(&dev_priv->dpio_lock);
6825         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6826         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6827         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6828         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6829         mutex_unlock(&dev_priv->dpio_lock);
6830
6831         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6832         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6833         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6834         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6835         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6836
6837         chv_clock(refclk, &clock);
6838
6839         /* clock.dot is the fast clock */
6840         pipe_config->port_clock = clock.dot / 5;
6841 }
6842
6843 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6844                                  struct intel_crtc_state *pipe_config)
6845 {
6846         struct drm_device *dev = crtc->base.dev;
6847         struct drm_i915_private *dev_priv = dev->dev_private;
6848         uint32_t tmp;
6849
6850         if (!intel_display_power_is_enabled(dev_priv,
6851                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6852                 return false;
6853
6854         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6855         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6856
6857         tmp = I915_READ(PIPECONF(crtc->pipe));
6858         if (!(tmp & PIPECONF_ENABLE))
6859                 return false;
6860
6861         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6862                 switch (tmp & PIPECONF_BPC_MASK) {
6863                 case PIPECONF_6BPC:
6864                         pipe_config->pipe_bpp = 18;
6865                         break;
6866                 case PIPECONF_8BPC:
6867                         pipe_config->pipe_bpp = 24;
6868                         break;
6869                 case PIPECONF_10BPC:
6870                         pipe_config->pipe_bpp = 30;
6871                         break;
6872                 default:
6873                         break;
6874                 }
6875         }
6876
6877         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6878                 pipe_config->limited_color_range = true;
6879
6880         if (INTEL_INFO(dev)->gen < 4)
6881                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6882
6883         intel_get_pipe_timings(crtc, pipe_config);
6884
6885         i9xx_get_pfit_config(crtc, pipe_config);
6886
6887         if (INTEL_INFO(dev)->gen >= 4) {
6888                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6889                 pipe_config->pixel_multiplier =
6890                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6891                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6892                 pipe_config->dpll_hw_state.dpll_md = tmp;
6893         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6894                 tmp = I915_READ(DPLL(crtc->pipe));
6895                 pipe_config->pixel_multiplier =
6896                         ((tmp & SDVO_MULTIPLIER_MASK)
6897                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6898         } else {
6899                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6900                  * port and will be fixed up in the encoder->get_config
6901                  * function. */
6902                 pipe_config->pixel_multiplier = 1;
6903         }
6904         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6905         if (!IS_VALLEYVIEW(dev)) {
6906                 /*
6907                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6908                  * on 830. Filter it out here so that we don't
6909                  * report errors due to that.
6910                  */
6911                 if (IS_I830(dev))
6912                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6913
6914                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6915                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6916         } else {
6917                 /* Mask out read-only status bits. */
6918                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6919                                                      DPLL_PORTC_READY_MASK |
6920                                                      DPLL_PORTB_READY_MASK);
6921         }
6922
6923         if (IS_CHERRYVIEW(dev))
6924                 chv_crtc_clock_get(crtc, pipe_config);
6925         else if (IS_VALLEYVIEW(dev))
6926                 vlv_crtc_clock_get(crtc, pipe_config);
6927         else
6928                 i9xx_crtc_clock_get(crtc, pipe_config);
6929
6930         return true;
6931 }
6932
6933 static void ironlake_init_pch_refclk(struct drm_device *dev)
6934 {
6935         struct drm_i915_private *dev_priv = dev->dev_private;
6936         struct intel_encoder *encoder;
6937         u32 val, final;
6938         bool has_lvds = false;
6939         bool has_cpu_edp = false;
6940         bool has_panel = false;
6941         bool has_ck505 = false;
6942         bool can_ssc = false;
6943
6944         /* We need to take the global config into account */
6945         for_each_intel_encoder(dev, encoder) {
6946                 switch (encoder->type) {
6947                 case INTEL_OUTPUT_LVDS:
6948                         has_panel = true;
6949                         has_lvds = true;
6950                         break;
6951                 case INTEL_OUTPUT_EDP:
6952                         has_panel = true;
6953                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6954                                 has_cpu_edp = true;
6955                         break;
6956                 default:
6957                         break;
6958                 }
6959         }
6960
6961         if (HAS_PCH_IBX(dev)) {
6962                 has_ck505 = dev_priv->vbt.display_clock_mode;
6963                 can_ssc = has_ck505;
6964         } else {
6965                 has_ck505 = false;
6966                 can_ssc = true;
6967         }
6968
6969         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6970                       has_panel, has_lvds, has_ck505);
6971
6972         /* Ironlake: try to setup display ref clock before DPLL
6973          * enabling. This is only under driver's control after
6974          * PCH B stepping, previous chipset stepping should be
6975          * ignoring this setting.
6976          */
6977         val = I915_READ(PCH_DREF_CONTROL);
6978
6979         /* As we must carefully and slowly disable/enable each source in turn,
6980          * compute the final state we want first and check if we need to
6981          * make any changes at all.
6982          */
6983         final = val;
6984         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6985         if (has_ck505)
6986                 final |= DREF_NONSPREAD_CK505_ENABLE;
6987         else
6988                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6989
6990         final &= ~DREF_SSC_SOURCE_MASK;
6991         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6992         final &= ~DREF_SSC1_ENABLE;
6993
6994         if (has_panel) {
6995                 final |= DREF_SSC_SOURCE_ENABLE;
6996
6997                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6998                         final |= DREF_SSC1_ENABLE;
6999
7000                 if (has_cpu_edp) {
7001                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7002                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7003                         else
7004                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7005                 } else
7006                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7007         } else {
7008                 final |= DREF_SSC_SOURCE_DISABLE;
7009                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7010         }
7011
7012         if (final == val)
7013                 return;
7014
7015         /* Always enable nonspread source */
7016         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7017
7018         if (has_ck505)
7019                 val |= DREF_NONSPREAD_CK505_ENABLE;
7020         else
7021                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7022
7023         if (has_panel) {
7024                 val &= ~DREF_SSC_SOURCE_MASK;
7025                 val |= DREF_SSC_SOURCE_ENABLE;
7026
7027                 /* SSC must be turned on before enabling the CPU output  */
7028                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7029                         DRM_DEBUG_KMS("Using SSC on panel\n");
7030                         val |= DREF_SSC1_ENABLE;
7031                 } else
7032                         val &= ~DREF_SSC1_ENABLE;
7033
7034                 /* Get SSC going before enabling the outputs */
7035                 I915_WRITE(PCH_DREF_CONTROL, val);
7036                 POSTING_READ(PCH_DREF_CONTROL);
7037                 udelay(200);
7038
7039                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7040
7041                 /* Enable CPU source on CPU attached eDP */
7042                 if (has_cpu_edp) {
7043                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7044                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7045                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7046                         } else
7047                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7048                 } else
7049                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7050
7051                 I915_WRITE(PCH_DREF_CONTROL, val);
7052                 POSTING_READ(PCH_DREF_CONTROL);
7053                 udelay(200);
7054         } else {
7055                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7056
7057                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7058
7059                 /* Turn off CPU output */
7060                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7061
7062                 I915_WRITE(PCH_DREF_CONTROL, val);
7063                 POSTING_READ(PCH_DREF_CONTROL);
7064                 udelay(200);
7065
7066                 /* Turn off the SSC source */
7067                 val &= ~DREF_SSC_SOURCE_MASK;
7068                 val |= DREF_SSC_SOURCE_DISABLE;
7069
7070                 /* Turn off SSC1 */
7071                 val &= ~DREF_SSC1_ENABLE;
7072
7073                 I915_WRITE(PCH_DREF_CONTROL, val);
7074                 POSTING_READ(PCH_DREF_CONTROL);
7075                 udelay(200);
7076         }
7077
7078         BUG_ON(val != final);
7079 }
7080
7081 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7082 {
7083         uint32_t tmp;
7084
7085         tmp = I915_READ(SOUTH_CHICKEN2);
7086         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7087         I915_WRITE(SOUTH_CHICKEN2, tmp);
7088
7089         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7090                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7091                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7092
7093         tmp = I915_READ(SOUTH_CHICKEN2);
7094         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7095         I915_WRITE(SOUTH_CHICKEN2, tmp);
7096
7097         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7098                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7099                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7100 }
7101
7102 /* WaMPhyProgramming:hsw */
7103 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7104 {
7105         uint32_t tmp;
7106
7107         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7108         tmp &= ~(0xFF << 24);
7109         tmp |= (0x12 << 24);
7110         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7111
7112         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7113         tmp |= (1 << 11);
7114         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7115
7116         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7117         tmp |= (1 << 11);
7118         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7119
7120         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7121         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7122         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7123
7124         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7125         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7126         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7127
7128         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7129         tmp &= ~(7 << 13);
7130         tmp |= (5 << 13);
7131         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7132
7133         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7134         tmp &= ~(7 << 13);
7135         tmp |= (5 << 13);
7136         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7137
7138         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7139         tmp &= ~0xFF;
7140         tmp |= 0x1C;
7141         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7142
7143         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7144         tmp &= ~0xFF;
7145         tmp |= 0x1C;
7146         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7147
7148         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7149         tmp &= ~(0xFF << 16);
7150         tmp |= (0x1C << 16);
7151         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7152
7153         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7154         tmp &= ~(0xFF << 16);
7155         tmp |= (0x1C << 16);
7156         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7157
7158         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7159         tmp |= (1 << 27);
7160         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7161
7162         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7163         tmp |= (1 << 27);
7164         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7165
7166         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7167         tmp &= ~(0xF << 28);
7168         tmp |= (4 << 28);
7169         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7170
7171         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7172         tmp &= ~(0xF << 28);
7173         tmp |= (4 << 28);
7174         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7175 }
7176
7177 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7178  * Programming" based on the parameters passed:
7179  * - Sequence to enable CLKOUT_DP
7180  * - Sequence to enable CLKOUT_DP without spread
7181  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7182  */
7183 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7184                                  bool with_fdi)
7185 {
7186         struct drm_i915_private *dev_priv = dev->dev_private;
7187         uint32_t reg, tmp;
7188
7189         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7190                 with_spread = true;
7191         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7192                  with_fdi, "LP PCH doesn't have FDI\n"))
7193                 with_fdi = false;
7194
7195         mutex_lock(&dev_priv->dpio_lock);
7196
7197         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7198         tmp &= ~SBI_SSCCTL_DISABLE;
7199         tmp |= SBI_SSCCTL_PATHALT;
7200         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7201
7202         udelay(24);
7203
7204         if (with_spread) {
7205                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7206                 tmp &= ~SBI_SSCCTL_PATHALT;
7207                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7208
7209                 if (with_fdi) {
7210                         lpt_reset_fdi_mphy(dev_priv);
7211                         lpt_program_fdi_mphy(dev_priv);
7212                 }
7213         }
7214
7215         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7216                SBI_GEN0 : SBI_DBUFF0;
7217         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7218         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7219         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7220
7221         mutex_unlock(&dev_priv->dpio_lock);
7222 }
7223
7224 /* Sequence to disable CLKOUT_DP */
7225 static void lpt_disable_clkout_dp(struct drm_device *dev)
7226 {
7227         struct drm_i915_private *dev_priv = dev->dev_private;
7228         uint32_t reg, tmp;
7229
7230         mutex_lock(&dev_priv->dpio_lock);
7231
7232         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7233                SBI_GEN0 : SBI_DBUFF0;
7234         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7235         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7236         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7237
7238         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7239         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7240                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7241                         tmp |= SBI_SSCCTL_PATHALT;
7242                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7243                         udelay(32);
7244                 }
7245                 tmp |= SBI_SSCCTL_DISABLE;
7246                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7247         }
7248
7249         mutex_unlock(&dev_priv->dpio_lock);
7250 }
7251
7252 static void lpt_init_pch_refclk(struct drm_device *dev)
7253 {
7254         struct intel_encoder *encoder;
7255         bool has_vga = false;
7256
7257         for_each_intel_encoder(dev, encoder) {
7258                 switch (encoder->type) {
7259                 case INTEL_OUTPUT_ANALOG:
7260                         has_vga = true;
7261                         break;
7262                 default:
7263                         break;
7264                 }
7265         }
7266
7267         if (has_vga)
7268                 lpt_enable_clkout_dp(dev, true, true);
7269         else
7270                 lpt_disable_clkout_dp(dev);
7271 }
7272
7273 /*
7274  * Initialize reference clocks when the driver loads
7275  */
7276 void intel_init_pch_refclk(struct drm_device *dev)
7277 {
7278         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7279                 ironlake_init_pch_refclk(dev);
7280         else if (HAS_PCH_LPT(dev))
7281                 lpt_init_pch_refclk(dev);
7282 }
7283
7284 static int ironlake_get_refclk(struct drm_crtc *crtc)
7285 {
7286         struct drm_device *dev = crtc->dev;
7287         struct drm_i915_private *dev_priv = dev->dev_private;
7288         struct intel_encoder *encoder;
7289         int num_connectors = 0;
7290         bool is_lvds = false;
7291
7292         for_each_intel_encoder(dev, encoder) {
7293                 if (encoder->new_crtc != to_intel_crtc(crtc))
7294                         continue;
7295
7296                 switch (encoder->type) {
7297                 case INTEL_OUTPUT_LVDS:
7298                         is_lvds = true;
7299                         break;
7300                 default:
7301                         break;
7302                 }
7303                 num_connectors++;
7304         }
7305
7306         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7307                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7308                               dev_priv->vbt.lvds_ssc_freq);
7309                 return dev_priv->vbt.lvds_ssc_freq;
7310         }
7311
7312         return 120000;
7313 }
7314
7315 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7316 {
7317         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7319         int pipe = intel_crtc->pipe;
7320         uint32_t val;
7321
7322         val = 0;
7323
7324         switch (intel_crtc->config->pipe_bpp) {
7325         case 18:
7326                 val |= PIPECONF_6BPC;
7327                 break;
7328         case 24:
7329                 val |= PIPECONF_8BPC;
7330                 break;
7331         case 30:
7332                 val |= PIPECONF_10BPC;
7333                 break;
7334         case 36:
7335                 val |= PIPECONF_12BPC;
7336                 break;
7337         default:
7338                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7339                 BUG();
7340         }
7341
7342         if (intel_crtc->config->dither)
7343                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7344
7345         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7346                 val |= PIPECONF_INTERLACED_ILK;
7347         else
7348                 val |= PIPECONF_PROGRESSIVE;
7349
7350         if (intel_crtc->config->limited_color_range)
7351                 val |= PIPECONF_COLOR_RANGE_SELECT;
7352
7353         I915_WRITE(PIPECONF(pipe), val);
7354         POSTING_READ(PIPECONF(pipe));
7355 }
7356
7357 /*
7358  * Set up the pipe CSC unit.
7359  *
7360  * Currently only full range RGB to limited range RGB conversion
7361  * is supported, but eventually this should handle various
7362  * RGB<->YCbCr scenarios as well.
7363  */
7364 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7365 {
7366         struct drm_device *dev = crtc->dev;
7367         struct drm_i915_private *dev_priv = dev->dev_private;
7368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7369         int pipe = intel_crtc->pipe;
7370         uint16_t coeff = 0x7800; /* 1.0 */
7371
7372         /*
7373          * TODO: Check what kind of values actually come out of the pipe
7374          * with these coeff/postoff values and adjust to get the best
7375          * accuracy. Perhaps we even need to take the bpc value into
7376          * consideration.
7377          */
7378
7379         if (intel_crtc->config->limited_color_range)
7380                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7381
7382         /*
7383          * GY/GU and RY/RU should be the other way around according
7384          * to BSpec, but reality doesn't agree. Just set them up in
7385          * a way that results in the correct picture.
7386          */
7387         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7388         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7389
7390         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7391         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7392
7393         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7394         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7395
7396         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7397         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7398         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7399
7400         if (INTEL_INFO(dev)->gen > 6) {
7401                 uint16_t postoff = 0;
7402
7403                 if (intel_crtc->config->limited_color_range)
7404                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7405
7406                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7407                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7408                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7409
7410                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7411         } else {
7412                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7413
7414                 if (intel_crtc->config->limited_color_range)
7415                         mode |= CSC_BLACK_SCREEN_OFFSET;
7416
7417                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7418         }
7419 }
7420
7421 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7422 {
7423         struct drm_device *dev = crtc->dev;
7424         struct drm_i915_private *dev_priv = dev->dev_private;
7425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7426         enum pipe pipe = intel_crtc->pipe;
7427         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7428         uint32_t val;
7429
7430         val = 0;
7431
7432         if (IS_HASWELL(dev) && intel_crtc->config->dither)
7433                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7434
7435         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7436                 val |= PIPECONF_INTERLACED_ILK;
7437         else
7438                 val |= PIPECONF_PROGRESSIVE;
7439
7440         I915_WRITE(PIPECONF(cpu_transcoder), val);
7441         POSTING_READ(PIPECONF(cpu_transcoder));
7442
7443         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7444         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7445
7446         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7447                 val = 0;
7448
7449                 switch (intel_crtc->config->pipe_bpp) {
7450                 case 18:
7451                         val |= PIPEMISC_DITHER_6_BPC;
7452                         break;
7453                 case 24:
7454                         val |= PIPEMISC_DITHER_8_BPC;
7455                         break;
7456                 case 30:
7457                         val |= PIPEMISC_DITHER_10_BPC;
7458                         break;
7459                 case 36:
7460                         val |= PIPEMISC_DITHER_12_BPC;
7461                         break;
7462                 default:
7463                         /* Case prevented by pipe_config_set_bpp. */
7464                         BUG();
7465                 }
7466
7467                 if (intel_crtc->config->dither)
7468                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7469
7470                 I915_WRITE(PIPEMISC(pipe), val);
7471         }
7472 }
7473
7474 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7475                                     struct intel_crtc_state *crtc_state,
7476                                     intel_clock_t *clock,
7477                                     bool *has_reduced_clock,
7478                                     intel_clock_t *reduced_clock)
7479 {
7480         struct drm_device *dev = crtc->dev;
7481         struct drm_i915_private *dev_priv = dev->dev_private;
7482         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7483         int refclk;
7484         const intel_limit_t *limit;
7485         bool ret, is_lvds = false;
7486
7487         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7488
7489         refclk = ironlake_get_refclk(crtc);
7490
7491         /*
7492          * Returns a set of divisors for the desired target clock with the given
7493          * refclk, or FALSE.  The returned values represent the clock equation:
7494          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7495          */
7496         limit = intel_limit(intel_crtc, refclk);
7497         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7498                                           crtc_state->port_clock,
7499                                           refclk, NULL, clock);
7500         if (!ret)
7501                 return false;
7502
7503         if (is_lvds && dev_priv->lvds_downclock_avail) {
7504                 /*
7505                  * Ensure we match the reduced clock's P to the target clock.
7506                  * If the clocks don't match, we can't switch the display clock
7507                  * by using the FP0/FP1. In such case we will disable the LVDS
7508                  * downclock feature.
7509                 */
7510                 *has_reduced_clock =
7511                         dev_priv->display.find_dpll(limit, intel_crtc,
7512                                                     dev_priv->lvds_downclock,
7513                                                     refclk, clock,
7514                                                     reduced_clock);
7515         }
7516
7517         return true;
7518 }
7519
7520 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7521 {
7522         /*
7523          * Account for spread spectrum to avoid
7524          * oversubscribing the link. Max center spread
7525          * is 2.5%; use 5% for safety's sake.
7526          */
7527         u32 bps = target_clock * bpp * 21 / 20;
7528         return DIV_ROUND_UP(bps, link_bw * 8);
7529 }
7530
7531 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7532 {
7533         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7534 }
7535
7536 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7537                                       struct intel_crtc_state *crtc_state,
7538                                       u32 *fp,
7539                                       intel_clock_t *reduced_clock, u32 *fp2)
7540 {
7541         struct drm_crtc *crtc = &intel_crtc->base;
7542         struct drm_device *dev = crtc->dev;
7543         struct drm_i915_private *dev_priv = dev->dev_private;
7544         struct intel_encoder *intel_encoder;
7545         uint32_t dpll;
7546         int factor, num_connectors = 0;
7547         bool is_lvds = false, is_sdvo = false;
7548
7549         for_each_intel_encoder(dev, intel_encoder) {
7550                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7551                         continue;
7552
7553                 switch (intel_encoder->type) {
7554                 case INTEL_OUTPUT_LVDS:
7555                         is_lvds = true;
7556                         break;
7557                 case INTEL_OUTPUT_SDVO:
7558                 case INTEL_OUTPUT_HDMI:
7559                         is_sdvo = true;
7560                         break;
7561                 default:
7562                         break;
7563                 }
7564
7565                 num_connectors++;
7566         }
7567
7568         /* Enable autotuning of the PLL clock (if permissible) */
7569         factor = 21;
7570         if (is_lvds) {
7571                 if ((intel_panel_use_ssc(dev_priv) &&
7572                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7573                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7574                         factor = 25;
7575         } else if (crtc_state->sdvo_tv_clock)
7576                 factor = 20;
7577
7578         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7579                 *fp |= FP_CB_TUNE;
7580
7581         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7582                 *fp2 |= FP_CB_TUNE;
7583
7584         dpll = 0;
7585
7586         if (is_lvds)
7587                 dpll |= DPLLB_MODE_LVDS;
7588         else
7589                 dpll |= DPLLB_MODE_DAC_SERIAL;
7590
7591         dpll |= (crtc_state->pixel_multiplier - 1)
7592                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7593
7594         if (is_sdvo)
7595                 dpll |= DPLL_SDVO_HIGH_SPEED;
7596         if (crtc_state->has_dp_encoder)
7597                 dpll |= DPLL_SDVO_HIGH_SPEED;
7598
7599         /* compute bitmask from p1 value */
7600         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7601         /* also FPA1 */
7602         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7603
7604         switch (crtc_state->dpll.p2) {
7605         case 5:
7606                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7607                 break;
7608         case 7:
7609                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7610                 break;
7611         case 10:
7612                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7613                 break;
7614         case 14:
7615                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7616                 break;
7617         }
7618
7619         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7620                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7621         else
7622                 dpll |= PLL_REF_INPUT_DREFCLK;
7623
7624         return dpll | DPLL_VCO_ENABLE;
7625 }
7626
7627 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7628                                        struct intel_crtc_state *crtc_state)
7629 {
7630         struct drm_device *dev = crtc->base.dev;
7631         intel_clock_t clock, reduced_clock;
7632         u32 dpll = 0, fp = 0, fp2 = 0;
7633         bool ok, has_reduced_clock = false;
7634         bool is_lvds = false;
7635         struct intel_shared_dpll *pll;
7636
7637         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7638
7639         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7640              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7641
7642         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7643                                      &has_reduced_clock, &reduced_clock);
7644         if (!ok && !crtc_state->clock_set) {
7645                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7646                 return -EINVAL;
7647         }
7648         /* Compat-code for transition, will disappear. */
7649         if (!crtc_state->clock_set) {
7650                 crtc_state->dpll.n = clock.n;
7651                 crtc_state->dpll.m1 = clock.m1;
7652                 crtc_state->dpll.m2 = clock.m2;
7653                 crtc_state->dpll.p1 = clock.p1;
7654                 crtc_state->dpll.p2 = clock.p2;
7655         }
7656
7657         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7658         if (crtc_state->has_pch_encoder) {
7659                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7660                 if (has_reduced_clock)
7661                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7662
7663                 dpll = ironlake_compute_dpll(crtc, crtc_state,
7664                                              &fp, &reduced_clock,
7665                                              has_reduced_clock ? &fp2 : NULL);
7666
7667                 crtc_state->dpll_hw_state.dpll = dpll;
7668                 crtc_state->dpll_hw_state.fp0 = fp;
7669                 if (has_reduced_clock)
7670                         crtc_state->dpll_hw_state.fp1 = fp2;
7671                 else
7672                         crtc_state->dpll_hw_state.fp1 = fp;
7673
7674                 pll = intel_get_shared_dpll(crtc, crtc_state);
7675                 if (pll == NULL) {
7676                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7677                                          pipe_name(crtc->pipe));
7678                         return -EINVAL;
7679                 }
7680         }
7681
7682         if (is_lvds && has_reduced_clock && i915.powersave)
7683                 crtc->lowfreq_avail = true;
7684         else
7685                 crtc->lowfreq_avail = false;
7686
7687         return 0;
7688 }
7689
7690 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7691                                          struct intel_link_m_n *m_n)
7692 {
7693         struct drm_device *dev = crtc->base.dev;
7694         struct drm_i915_private *dev_priv = dev->dev_private;
7695         enum pipe pipe = crtc->pipe;
7696
7697         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7698         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7699         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7700                 & ~TU_SIZE_MASK;
7701         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7702         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7703                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7704 }
7705
7706 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7707                                          enum transcoder transcoder,
7708                                          struct intel_link_m_n *m_n,
7709                                          struct intel_link_m_n *m2_n2)
7710 {
7711         struct drm_device *dev = crtc->base.dev;
7712         struct drm_i915_private *dev_priv = dev->dev_private;
7713         enum pipe pipe = crtc->pipe;
7714
7715         if (INTEL_INFO(dev)->gen >= 5) {
7716                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7717                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7718                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7719                         & ~TU_SIZE_MASK;
7720                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7721                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7722                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7723                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7724                  * gen < 8) and if DRRS is supported (to make sure the
7725                  * registers are not unnecessarily read).
7726                  */
7727                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7728                         crtc->config->has_drrs) {
7729                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7730                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7731                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7732                                         & ~TU_SIZE_MASK;
7733                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7734                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7735                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7736                 }
7737         } else {
7738                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7739                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7740                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7741                         & ~TU_SIZE_MASK;
7742                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7743                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7744                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7745         }
7746 }
7747
7748 void intel_dp_get_m_n(struct intel_crtc *crtc,
7749                       struct intel_crtc_state *pipe_config)
7750 {
7751         if (pipe_config->has_pch_encoder)
7752                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7753         else
7754                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7755                                              &pipe_config->dp_m_n,
7756                                              &pipe_config->dp_m2_n2);
7757 }
7758
7759 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7760                                         struct intel_crtc_state *pipe_config)
7761 {
7762         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7763                                      &pipe_config->fdi_m_n, NULL);
7764 }
7765
7766 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7767                                     struct intel_crtc_state *pipe_config)
7768 {
7769         struct drm_device *dev = crtc->base.dev;
7770         struct drm_i915_private *dev_priv = dev->dev_private;
7771         uint32_t tmp;
7772
7773         tmp = I915_READ(PS_CTL(crtc->pipe));
7774
7775         if (tmp & PS_ENABLE) {
7776                 pipe_config->pch_pfit.enabled = true;
7777                 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7778                 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7779         }
7780 }
7781
7782 static void
7783 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7784                                  struct intel_initial_plane_config *plane_config)
7785 {
7786         struct drm_device *dev = crtc->base.dev;
7787         struct drm_i915_private *dev_priv = dev->dev_private;
7788         u32 val, base, offset, stride_mult, tiling;
7789         int pipe = crtc->pipe;
7790         int fourcc, pixel_format;
7791         int aligned_height;
7792         struct drm_framebuffer *fb;
7793         struct intel_framebuffer *intel_fb;
7794
7795         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7796         if (!intel_fb) {
7797                 DRM_DEBUG_KMS("failed to alloc fb\n");
7798                 return;
7799         }
7800
7801         fb = &intel_fb->base;
7802
7803         val = I915_READ(PLANE_CTL(pipe, 0));
7804         if (!(val & PLANE_CTL_ENABLE))
7805                 goto error;
7806
7807         pixel_format = val & PLANE_CTL_FORMAT_MASK;
7808         fourcc = skl_format_to_fourcc(pixel_format,
7809                                       val & PLANE_CTL_ORDER_RGBX,
7810                                       val & PLANE_CTL_ALPHA_MASK);
7811         fb->pixel_format = fourcc;
7812         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7813
7814         tiling = val & PLANE_CTL_TILED_MASK;
7815         switch (tiling) {
7816         case PLANE_CTL_TILED_LINEAR:
7817                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7818                 break;
7819         case PLANE_CTL_TILED_X:
7820                 plane_config->tiling = I915_TILING_X;
7821                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7822                 break;
7823         case PLANE_CTL_TILED_Y:
7824                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7825                 break;
7826         case PLANE_CTL_TILED_YF:
7827                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7828                 break;
7829         default:
7830                 MISSING_CASE(tiling);
7831                 goto error;
7832         }
7833
7834         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7835         plane_config->base = base;
7836
7837         offset = I915_READ(PLANE_OFFSET(pipe, 0));
7838
7839         val = I915_READ(PLANE_SIZE(pipe, 0));
7840         fb->height = ((val >> 16) & 0xfff) + 1;
7841         fb->width = ((val >> 0) & 0x1fff) + 1;
7842
7843         val = I915_READ(PLANE_STRIDE(pipe, 0));
7844         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7845                                                 fb->pixel_format);
7846         fb->pitches[0] = (val & 0x3ff) * stride_mult;
7847
7848         aligned_height = intel_fb_align_height(dev, fb->height,
7849                                                fb->pixel_format,
7850                                                fb->modifier[0]);
7851
7852         plane_config->size = fb->pitches[0] * aligned_height;
7853
7854         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7855                       pipe_name(pipe), fb->width, fb->height,
7856                       fb->bits_per_pixel, base, fb->pitches[0],
7857                       plane_config->size);
7858
7859         plane_config->fb = intel_fb;
7860         return;
7861
7862 error:
7863         kfree(fb);
7864 }
7865
7866 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7867                                      struct intel_crtc_state *pipe_config)
7868 {
7869         struct drm_device *dev = crtc->base.dev;
7870         struct drm_i915_private *dev_priv = dev->dev_private;
7871         uint32_t tmp;
7872
7873         tmp = I915_READ(PF_CTL(crtc->pipe));
7874
7875         if (tmp & PF_ENABLE) {
7876                 pipe_config->pch_pfit.enabled = true;
7877                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7878                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7879
7880                 /* We currently do not free assignements of panel fitters on
7881                  * ivb/hsw (since we don't use the higher upscaling modes which
7882                  * differentiates them) so just WARN about this case for now. */
7883                 if (IS_GEN7(dev)) {
7884                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7885                                 PF_PIPE_SEL_IVB(crtc->pipe));
7886                 }
7887         }
7888 }
7889
7890 static void
7891 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7892                                   struct intel_initial_plane_config *plane_config)
7893 {
7894         struct drm_device *dev = crtc->base.dev;
7895         struct drm_i915_private *dev_priv = dev->dev_private;
7896         u32 val, base, offset;
7897         int pipe = crtc->pipe;
7898         int fourcc, pixel_format;
7899         int aligned_height;
7900         struct drm_framebuffer *fb;
7901         struct intel_framebuffer *intel_fb;
7902
7903         val = I915_READ(DSPCNTR(pipe));
7904         if (!(val & DISPLAY_PLANE_ENABLE))
7905                 return;
7906
7907         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7908         if (!intel_fb) {
7909                 DRM_DEBUG_KMS("failed to alloc fb\n");
7910                 return;
7911         }
7912
7913         fb = &intel_fb->base;
7914
7915         if (INTEL_INFO(dev)->gen >= 4) {
7916                 if (val & DISPPLANE_TILED) {
7917                         plane_config->tiling = I915_TILING_X;
7918                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7919                 }
7920         }
7921
7922         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7923         fourcc = i9xx_format_to_fourcc(pixel_format);
7924         fb->pixel_format = fourcc;
7925         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7926
7927         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7928         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7929                 offset = I915_READ(DSPOFFSET(pipe));
7930         } else {
7931                 if (plane_config->tiling)
7932                         offset = I915_READ(DSPTILEOFF(pipe));
7933                 else
7934                         offset = I915_READ(DSPLINOFF(pipe));
7935         }
7936         plane_config->base = base;
7937
7938         val = I915_READ(PIPESRC(pipe));
7939         fb->width = ((val >> 16) & 0xfff) + 1;
7940         fb->height = ((val >> 0) & 0xfff) + 1;
7941
7942         val = I915_READ(DSPSTRIDE(pipe));
7943         fb->pitches[0] = val & 0xffffffc0;
7944
7945         aligned_height = intel_fb_align_height(dev, fb->height,
7946                                                fb->pixel_format,
7947                                                fb->modifier[0]);
7948
7949         plane_config->size = fb->pitches[0] * aligned_height;
7950
7951         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7952                       pipe_name(pipe), fb->width, fb->height,
7953                       fb->bits_per_pixel, base, fb->pitches[0],
7954                       plane_config->size);
7955
7956         plane_config->fb = intel_fb;
7957 }
7958
7959 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7960                                      struct intel_crtc_state *pipe_config)
7961 {
7962         struct drm_device *dev = crtc->base.dev;
7963         struct drm_i915_private *dev_priv = dev->dev_private;
7964         uint32_t tmp;
7965
7966         if (!intel_display_power_is_enabled(dev_priv,
7967                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7968                 return false;
7969
7970         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7971         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7972
7973         tmp = I915_READ(PIPECONF(crtc->pipe));
7974         if (!(tmp & PIPECONF_ENABLE))
7975                 return false;
7976
7977         switch (tmp & PIPECONF_BPC_MASK) {
7978         case PIPECONF_6BPC:
7979                 pipe_config->pipe_bpp = 18;
7980                 break;
7981         case PIPECONF_8BPC:
7982                 pipe_config->pipe_bpp = 24;
7983                 break;
7984         case PIPECONF_10BPC:
7985                 pipe_config->pipe_bpp = 30;
7986                 break;
7987         case PIPECONF_12BPC:
7988                 pipe_config->pipe_bpp = 36;
7989                 break;
7990         default:
7991                 break;
7992         }
7993
7994         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7995                 pipe_config->limited_color_range = true;
7996
7997         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7998                 struct intel_shared_dpll *pll;
7999
8000                 pipe_config->has_pch_encoder = true;
8001
8002                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8003                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8004                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8005
8006                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8007
8008                 if (HAS_PCH_IBX(dev_priv->dev)) {
8009                         pipe_config->shared_dpll =
8010                                 (enum intel_dpll_id) crtc->pipe;
8011                 } else {
8012                         tmp = I915_READ(PCH_DPLL_SEL);
8013                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8014                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8015                         else
8016                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8017                 }
8018
8019                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8020
8021                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8022                                            &pipe_config->dpll_hw_state));
8023
8024                 tmp = pipe_config->dpll_hw_state.dpll;
8025                 pipe_config->pixel_multiplier =
8026                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8027                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8028
8029                 ironlake_pch_clock_get(crtc, pipe_config);
8030         } else {
8031                 pipe_config->pixel_multiplier = 1;
8032         }
8033
8034         intel_get_pipe_timings(crtc, pipe_config);
8035
8036         ironlake_get_pfit_config(crtc, pipe_config);
8037
8038         return true;
8039 }
8040
8041 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8042 {
8043         struct drm_device *dev = dev_priv->dev;
8044         struct intel_crtc *crtc;
8045
8046         for_each_intel_crtc(dev, crtc)
8047                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8048                      pipe_name(crtc->pipe));
8049
8050         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8051         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8052         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8053         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8054         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8055         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8056              "CPU PWM1 enabled\n");
8057         if (IS_HASWELL(dev))
8058                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8059                      "CPU PWM2 enabled\n");
8060         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8061              "PCH PWM1 enabled\n");
8062         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8063              "Utility pin enabled\n");
8064         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8065
8066         /*
8067          * In theory we can still leave IRQs enabled, as long as only the HPD
8068          * interrupts remain enabled. We used to check for that, but since it's
8069          * gen-specific and since we only disable LCPLL after we fully disable
8070          * the interrupts, the check below should be enough.
8071          */
8072         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8073 }
8074
8075 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8076 {
8077         struct drm_device *dev = dev_priv->dev;
8078
8079         if (IS_HASWELL(dev))
8080                 return I915_READ(D_COMP_HSW);
8081         else
8082                 return I915_READ(D_COMP_BDW);
8083 }
8084
8085 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8086 {
8087         struct drm_device *dev = dev_priv->dev;
8088
8089         if (IS_HASWELL(dev)) {
8090                 mutex_lock(&dev_priv->rps.hw_lock);
8091                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8092                                             val))
8093                         DRM_ERROR("Failed to write to D_COMP\n");
8094                 mutex_unlock(&dev_priv->rps.hw_lock);
8095         } else {
8096                 I915_WRITE(D_COMP_BDW, val);
8097                 POSTING_READ(D_COMP_BDW);
8098         }
8099 }
8100
8101 /*
8102  * This function implements pieces of two sequences from BSpec:
8103  * - Sequence for display software to disable LCPLL
8104  * - Sequence for display software to allow package C8+
8105  * The steps implemented here are just the steps that actually touch the LCPLL
8106  * register. Callers should take care of disabling all the display engine
8107  * functions, doing the mode unset, fixing interrupts, etc.
8108  */
8109 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8110                               bool switch_to_fclk, bool allow_power_down)
8111 {
8112         uint32_t val;
8113
8114         assert_can_disable_lcpll(dev_priv);
8115
8116         val = I915_READ(LCPLL_CTL);
8117
8118         if (switch_to_fclk) {
8119                 val |= LCPLL_CD_SOURCE_FCLK;
8120                 I915_WRITE(LCPLL_CTL, val);
8121
8122                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8123                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
8124                         DRM_ERROR("Switching to FCLK failed\n");
8125
8126                 val = I915_READ(LCPLL_CTL);
8127         }
8128
8129         val |= LCPLL_PLL_DISABLE;
8130         I915_WRITE(LCPLL_CTL, val);
8131         POSTING_READ(LCPLL_CTL);
8132
8133         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8134                 DRM_ERROR("LCPLL still locked\n");
8135
8136         val = hsw_read_dcomp(dev_priv);
8137         val |= D_COMP_COMP_DISABLE;
8138         hsw_write_dcomp(dev_priv, val);
8139         ndelay(100);
8140
8141         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8142                      1))
8143                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8144
8145         if (allow_power_down) {
8146                 val = I915_READ(LCPLL_CTL);
8147                 val |= LCPLL_POWER_DOWN_ALLOW;
8148                 I915_WRITE(LCPLL_CTL, val);
8149                 POSTING_READ(LCPLL_CTL);
8150         }
8151 }
8152
8153 /*
8154  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8155  * source.
8156  */
8157 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8158 {
8159         uint32_t val;
8160
8161         val = I915_READ(LCPLL_CTL);
8162
8163         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8164                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8165                 return;
8166
8167         /*
8168          * Make sure we're not on PC8 state before disabling PC8, otherwise
8169          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8170          */
8171         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8172
8173         if (val & LCPLL_POWER_DOWN_ALLOW) {
8174                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8175                 I915_WRITE(LCPLL_CTL, val);
8176                 POSTING_READ(LCPLL_CTL);
8177         }
8178
8179         val = hsw_read_dcomp(dev_priv);
8180         val |= D_COMP_COMP_FORCE;
8181         val &= ~D_COMP_COMP_DISABLE;
8182         hsw_write_dcomp(dev_priv, val);
8183
8184         val = I915_READ(LCPLL_CTL);
8185         val &= ~LCPLL_PLL_DISABLE;
8186         I915_WRITE(LCPLL_CTL, val);
8187
8188         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8189                 DRM_ERROR("LCPLL not locked yet\n");
8190
8191         if (val & LCPLL_CD_SOURCE_FCLK) {
8192                 val = I915_READ(LCPLL_CTL);
8193                 val &= ~LCPLL_CD_SOURCE_FCLK;
8194                 I915_WRITE(LCPLL_CTL, val);
8195
8196                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8197                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8198                         DRM_ERROR("Switching back to LCPLL failed\n");
8199         }
8200
8201         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8202 }
8203
8204 /*
8205  * Package states C8 and deeper are really deep PC states that can only be
8206  * reached when all the devices on the system allow it, so even if the graphics
8207  * device allows PC8+, it doesn't mean the system will actually get to these
8208  * states. Our driver only allows PC8+ when going into runtime PM.
8209  *
8210  * The requirements for PC8+ are that all the outputs are disabled, the power
8211  * well is disabled and most interrupts are disabled, and these are also
8212  * requirements for runtime PM. When these conditions are met, we manually do
8213  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8214  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8215  * hang the machine.
8216  *
8217  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8218  * the state of some registers, so when we come back from PC8+ we need to
8219  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8220  * need to take care of the registers kept by RC6. Notice that this happens even
8221  * if we don't put the device in PCI D3 state (which is what currently happens
8222  * because of the runtime PM support).
8223  *
8224  * For more, read "Display Sequences for Package C8" on the hardware
8225  * documentation.
8226  */
8227 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8228 {
8229         struct drm_device *dev = dev_priv->dev;
8230         uint32_t val;
8231
8232         DRM_DEBUG_KMS("Enabling package C8+\n");
8233
8234         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8235                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8236                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8237                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8238         }
8239
8240         lpt_disable_clkout_dp(dev);
8241         hsw_disable_lcpll(dev_priv, true, true);
8242 }
8243
8244 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8245 {
8246         struct drm_device *dev = dev_priv->dev;
8247         uint32_t val;
8248
8249         DRM_DEBUG_KMS("Disabling package C8+\n");
8250
8251         hsw_restore_lcpll(dev_priv);
8252         lpt_init_pch_refclk(dev);
8253
8254         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8255                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8256                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8257                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8258         }
8259
8260         intel_prepare_ddi(dev);
8261 }
8262
8263 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8264                                       struct intel_crtc_state *crtc_state)
8265 {
8266         if (!intel_ddi_pll_select(crtc, crtc_state))
8267                 return -EINVAL;
8268
8269         crtc->lowfreq_avail = false;
8270
8271         return 0;
8272 }
8273
8274 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8275                                 enum port port,
8276                                 struct intel_crtc_state *pipe_config)
8277 {
8278         u32 temp, dpll_ctl1;
8279
8280         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8281         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8282
8283         switch (pipe_config->ddi_pll_sel) {
8284         case SKL_DPLL0:
8285                 /*
8286                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8287                  * of the shared DPLL framework and thus needs to be read out
8288                  * separately
8289                  */
8290                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8291                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8292                 break;
8293         case SKL_DPLL1:
8294                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8295                 break;
8296         case SKL_DPLL2:
8297                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8298                 break;
8299         case SKL_DPLL3:
8300                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8301                 break;
8302         }
8303 }
8304
8305 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8306                                 enum port port,
8307                                 struct intel_crtc_state *pipe_config)
8308 {
8309         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8310
8311         switch (pipe_config->ddi_pll_sel) {
8312         case PORT_CLK_SEL_WRPLL1:
8313                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8314                 break;
8315         case PORT_CLK_SEL_WRPLL2:
8316                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8317                 break;
8318         }
8319 }
8320
8321 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8322                                        struct intel_crtc_state *pipe_config)
8323 {
8324         struct drm_device *dev = crtc->base.dev;
8325         struct drm_i915_private *dev_priv = dev->dev_private;
8326         struct intel_shared_dpll *pll;
8327         enum port port;
8328         uint32_t tmp;
8329
8330         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8331
8332         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8333
8334         if (IS_SKYLAKE(dev))
8335                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8336         else
8337                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8338
8339         if (pipe_config->shared_dpll >= 0) {
8340                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8341
8342                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8343                                            &pipe_config->dpll_hw_state));
8344         }
8345
8346         /*
8347          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8348          * DDI E. So just check whether this pipe is wired to DDI E and whether
8349          * the PCH transcoder is on.
8350          */
8351         if (INTEL_INFO(dev)->gen < 9 &&
8352             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8353                 pipe_config->has_pch_encoder = true;
8354
8355                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8356                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8357                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8358
8359                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8360         }
8361 }
8362
8363 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8364                                     struct intel_crtc_state *pipe_config)
8365 {
8366         struct drm_device *dev = crtc->base.dev;
8367         struct drm_i915_private *dev_priv = dev->dev_private;
8368         enum intel_display_power_domain pfit_domain;
8369         uint32_t tmp;
8370
8371         if (!intel_display_power_is_enabled(dev_priv,
8372                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8373                 return false;
8374
8375         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8376         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8377
8378         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8379         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8380                 enum pipe trans_edp_pipe;
8381                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8382                 default:
8383                         WARN(1, "unknown pipe linked to edp transcoder\n");
8384                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8385                 case TRANS_DDI_EDP_INPUT_A_ON:
8386                         trans_edp_pipe = PIPE_A;
8387                         break;
8388                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8389                         trans_edp_pipe = PIPE_B;
8390                         break;
8391                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8392                         trans_edp_pipe = PIPE_C;
8393                         break;
8394                 }
8395
8396                 if (trans_edp_pipe == crtc->pipe)
8397                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8398         }
8399
8400         if (!intel_display_power_is_enabled(dev_priv,
8401                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8402                 return false;
8403
8404         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8405         if (!(tmp & PIPECONF_ENABLE))
8406                 return false;
8407
8408         haswell_get_ddi_port_state(crtc, pipe_config);
8409
8410         intel_get_pipe_timings(crtc, pipe_config);
8411
8412         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8413         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8414                 if (IS_SKYLAKE(dev))
8415                         skylake_get_pfit_config(crtc, pipe_config);
8416                 else
8417                         ironlake_get_pfit_config(crtc, pipe_config);
8418         }
8419
8420         if (IS_HASWELL(dev))
8421                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8422                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8423
8424         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8425                 pipe_config->pixel_multiplier =
8426                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8427         } else {
8428                 pipe_config->pixel_multiplier = 1;
8429         }
8430
8431         return true;
8432 }
8433
8434 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8435 {
8436         struct drm_device *dev = crtc->dev;
8437         struct drm_i915_private *dev_priv = dev->dev_private;
8438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8439         uint32_t cntl = 0, size = 0;
8440
8441         if (base) {
8442                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8443                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8444                 unsigned int stride = roundup_pow_of_two(width) * 4;
8445
8446                 switch (stride) {
8447                 default:
8448                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8449                                   width, stride);
8450                         stride = 256;
8451                         /* fallthrough */
8452                 case 256:
8453                 case 512:
8454                 case 1024:
8455                 case 2048:
8456                         break;
8457                 }
8458
8459                 cntl |= CURSOR_ENABLE |
8460                         CURSOR_GAMMA_ENABLE |
8461                         CURSOR_FORMAT_ARGB |
8462                         CURSOR_STRIDE(stride);
8463
8464                 size = (height << 12) | width;
8465         }
8466
8467         if (intel_crtc->cursor_cntl != 0 &&
8468             (intel_crtc->cursor_base != base ||
8469              intel_crtc->cursor_size != size ||
8470              intel_crtc->cursor_cntl != cntl)) {
8471                 /* On these chipsets we can only modify the base/size/stride
8472                  * whilst the cursor is disabled.
8473                  */
8474                 I915_WRITE(_CURACNTR, 0);
8475                 POSTING_READ(_CURACNTR);
8476                 intel_crtc->cursor_cntl = 0;
8477         }
8478
8479         if (intel_crtc->cursor_base != base) {
8480                 I915_WRITE(_CURABASE, base);
8481                 intel_crtc->cursor_base = base;
8482         }
8483
8484         if (intel_crtc->cursor_size != size) {
8485                 I915_WRITE(CURSIZE, size);
8486                 intel_crtc->cursor_size = size;
8487         }
8488
8489         if (intel_crtc->cursor_cntl != cntl) {
8490                 I915_WRITE(_CURACNTR, cntl);
8491                 POSTING_READ(_CURACNTR);
8492                 intel_crtc->cursor_cntl = cntl;
8493         }
8494 }
8495
8496 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8497 {
8498         struct drm_device *dev = crtc->dev;
8499         struct drm_i915_private *dev_priv = dev->dev_private;
8500         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8501         int pipe = intel_crtc->pipe;
8502         uint32_t cntl;
8503
8504         cntl = 0;
8505         if (base) {
8506                 cntl = MCURSOR_GAMMA_ENABLE;
8507                 switch (intel_crtc->base.cursor->state->crtc_w) {
8508                         case 64:
8509                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8510                                 break;
8511                         case 128:
8512                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8513                                 break;
8514                         case 256:
8515                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8516                                 break;
8517                         default:
8518                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8519                                 return;
8520                 }
8521                 cntl |= pipe << 28; /* Connect to correct pipe */
8522
8523                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8524                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8525         }
8526
8527         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8528                 cntl |= CURSOR_ROTATE_180;
8529
8530         if (intel_crtc->cursor_cntl != cntl) {
8531                 I915_WRITE(CURCNTR(pipe), cntl);
8532                 POSTING_READ(CURCNTR(pipe));
8533                 intel_crtc->cursor_cntl = cntl;
8534         }
8535
8536         /* and commit changes on next vblank */
8537         I915_WRITE(CURBASE(pipe), base);
8538         POSTING_READ(CURBASE(pipe));
8539
8540         intel_crtc->cursor_base = base;
8541 }
8542
8543 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8544 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8545                                      bool on)
8546 {
8547         struct drm_device *dev = crtc->dev;
8548         struct drm_i915_private *dev_priv = dev->dev_private;
8549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8550         int pipe = intel_crtc->pipe;
8551         int x = crtc->cursor_x;
8552         int y = crtc->cursor_y;
8553         u32 base = 0, pos = 0;
8554
8555         if (on)
8556                 base = intel_crtc->cursor_addr;
8557
8558         if (x >= intel_crtc->config->pipe_src_w)
8559                 base = 0;
8560
8561         if (y >= intel_crtc->config->pipe_src_h)
8562                 base = 0;
8563
8564         if (x < 0) {
8565                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8566                         base = 0;
8567
8568                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8569                 x = -x;
8570         }
8571         pos |= x << CURSOR_X_SHIFT;
8572
8573         if (y < 0) {
8574                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8575                         base = 0;
8576
8577                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8578                 y = -y;
8579         }
8580         pos |= y << CURSOR_Y_SHIFT;
8581
8582         if (base == 0 && intel_crtc->cursor_base == 0)
8583                 return;
8584
8585         I915_WRITE(CURPOS(pipe), pos);
8586
8587         /* ILK+ do this automagically */
8588         if (HAS_GMCH_DISPLAY(dev) &&
8589             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8590                 base += (intel_crtc->base.cursor->state->crtc_h *
8591                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8592         }
8593
8594         if (IS_845G(dev) || IS_I865G(dev))
8595                 i845_update_cursor(crtc, base);
8596         else
8597                 i9xx_update_cursor(crtc, base);
8598 }
8599
8600 static bool cursor_size_ok(struct drm_device *dev,
8601                            uint32_t width, uint32_t height)
8602 {
8603         if (width == 0 || height == 0)
8604                 return false;
8605
8606         /*
8607          * 845g/865g are special in that they are only limited by
8608          * the width of their cursors, the height is arbitrary up to
8609          * the precision of the register. Everything else requires
8610          * square cursors, limited to a few power-of-two sizes.
8611          */
8612         if (IS_845G(dev) || IS_I865G(dev)) {
8613                 if ((width & 63) != 0)
8614                         return false;
8615
8616                 if (width > (IS_845G(dev) ? 64 : 512))
8617                         return false;
8618
8619                 if (height > 1023)
8620                         return false;
8621         } else {
8622                 switch (width | height) {
8623                 case 256:
8624                 case 128:
8625                         if (IS_GEN2(dev))
8626                                 return false;
8627                 case 64:
8628                         break;
8629                 default:
8630                         return false;
8631                 }
8632         }
8633
8634         return true;
8635 }
8636
8637 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8638                                  u16 *blue, uint32_t start, uint32_t size)
8639 {
8640         int end = (start + size > 256) ? 256 : start + size, i;
8641         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8642
8643         for (i = start; i < end; i++) {
8644                 intel_crtc->lut_r[i] = red[i] >> 8;
8645                 intel_crtc->lut_g[i] = green[i] >> 8;
8646                 intel_crtc->lut_b[i] = blue[i] >> 8;
8647         }
8648
8649         intel_crtc_load_lut(crtc);
8650 }
8651
8652 /* VESA 640x480x72Hz mode to set on the pipe */
8653 static struct drm_display_mode load_detect_mode = {
8654         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8655                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8656 };
8657
8658 struct drm_framebuffer *
8659 __intel_framebuffer_create(struct drm_device *dev,
8660                            struct drm_mode_fb_cmd2 *mode_cmd,
8661                            struct drm_i915_gem_object *obj)
8662 {
8663         struct intel_framebuffer *intel_fb;
8664         int ret;
8665
8666         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8667         if (!intel_fb) {
8668                 drm_gem_object_unreference(&obj->base);
8669                 return ERR_PTR(-ENOMEM);
8670         }
8671
8672         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8673         if (ret)
8674                 goto err;
8675
8676         return &intel_fb->base;
8677 err:
8678         drm_gem_object_unreference(&obj->base);
8679         kfree(intel_fb);
8680
8681         return ERR_PTR(ret);
8682 }
8683
8684 static struct drm_framebuffer *
8685 intel_framebuffer_create(struct drm_device *dev,
8686                          struct drm_mode_fb_cmd2 *mode_cmd,
8687                          struct drm_i915_gem_object *obj)
8688 {
8689         struct drm_framebuffer *fb;
8690         int ret;
8691
8692         ret = i915_mutex_lock_interruptible(dev);
8693         if (ret)
8694                 return ERR_PTR(ret);
8695         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8696         mutex_unlock(&dev->struct_mutex);
8697
8698         return fb;
8699 }
8700
8701 static u32
8702 intel_framebuffer_pitch_for_width(int width, int bpp)
8703 {
8704         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8705         return ALIGN(pitch, 64);
8706 }
8707
8708 static u32
8709 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8710 {
8711         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8712         return PAGE_ALIGN(pitch * mode->vdisplay);
8713 }
8714
8715 static struct drm_framebuffer *
8716 intel_framebuffer_create_for_mode(struct drm_device *dev,
8717                                   struct drm_display_mode *mode,
8718                                   int depth, int bpp)
8719 {
8720         struct drm_i915_gem_object *obj;
8721         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8722
8723         obj = i915_gem_alloc_object(dev,
8724                                     intel_framebuffer_size_for_mode(mode, bpp));
8725         if (obj == NULL)
8726                 return ERR_PTR(-ENOMEM);
8727
8728         mode_cmd.width = mode->hdisplay;
8729         mode_cmd.height = mode->vdisplay;
8730         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8731                                                                 bpp);
8732         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8733
8734         return intel_framebuffer_create(dev, &mode_cmd, obj);
8735 }
8736
8737 static struct drm_framebuffer *
8738 mode_fits_in_fbdev(struct drm_device *dev,
8739                    struct drm_display_mode *mode)
8740 {
8741 #ifdef CONFIG_DRM_I915_FBDEV
8742         struct drm_i915_private *dev_priv = dev->dev_private;
8743         struct drm_i915_gem_object *obj;
8744         struct drm_framebuffer *fb;
8745
8746         if (!dev_priv->fbdev)
8747                 return NULL;
8748
8749         if (!dev_priv->fbdev->fb)
8750                 return NULL;
8751
8752         obj = dev_priv->fbdev->fb->obj;
8753         BUG_ON(!obj);
8754
8755         fb = &dev_priv->fbdev->fb->base;
8756         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8757                                                                fb->bits_per_pixel))
8758                 return NULL;
8759
8760         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8761                 return NULL;
8762
8763         return fb;
8764 #else
8765         return NULL;
8766 #endif
8767 }
8768
8769 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8770                                 struct drm_display_mode *mode,
8771                                 struct intel_load_detect_pipe *old,
8772                                 struct drm_modeset_acquire_ctx *ctx)
8773 {
8774         struct intel_crtc *intel_crtc;
8775         struct intel_encoder *intel_encoder =
8776                 intel_attached_encoder(connector);
8777         struct drm_crtc *possible_crtc;
8778         struct drm_encoder *encoder = &intel_encoder->base;
8779         struct drm_crtc *crtc = NULL;
8780         struct drm_device *dev = encoder->dev;
8781         struct drm_framebuffer *fb;
8782         struct drm_mode_config *config = &dev->mode_config;
8783         int ret, i = -1;
8784
8785         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8786                       connector->base.id, connector->name,
8787                       encoder->base.id, encoder->name);
8788
8789 retry:
8790         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8791         if (ret)
8792                 goto fail_unlock;
8793
8794         /*
8795          * Algorithm gets a little messy:
8796          *
8797          *   - if the connector already has an assigned crtc, use it (but make
8798          *     sure it's on first)
8799          *
8800          *   - try to find the first unused crtc that can drive this connector,
8801          *     and use that if we find one
8802          */
8803
8804         /* See if we already have a CRTC for this connector */
8805         if (encoder->crtc) {
8806                 crtc = encoder->crtc;
8807
8808                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8809                 if (ret)
8810                         goto fail_unlock;
8811                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8812                 if (ret)
8813                         goto fail_unlock;
8814
8815                 old->dpms_mode = connector->dpms;
8816                 old->load_detect_temp = false;
8817
8818                 /* Make sure the crtc and connector are running */
8819                 if (connector->dpms != DRM_MODE_DPMS_ON)
8820                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8821
8822                 return true;
8823         }
8824
8825         /* Find an unused one (if possible) */
8826         for_each_crtc(dev, possible_crtc) {
8827                 i++;
8828                 if (!(encoder->possible_crtcs & (1 << i)))
8829                         continue;
8830                 if (possible_crtc->state->enable)
8831                         continue;
8832                 /* This can occur when applying the pipe A quirk on resume. */
8833                 if (to_intel_crtc(possible_crtc)->new_enabled)
8834                         continue;
8835
8836                 crtc = possible_crtc;
8837                 break;
8838         }
8839
8840         /*
8841          * If we didn't find an unused CRTC, don't use any.
8842          */
8843         if (!crtc) {
8844                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8845                 goto fail_unlock;
8846         }
8847
8848         ret = drm_modeset_lock(&crtc->mutex, ctx);
8849         if (ret)
8850                 goto fail_unlock;
8851         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8852         if (ret)
8853                 goto fail_unlock;
8854         intel_encoder->new_crtc = to_intel_crtc(crtc);
8855         to_intel_connector(connector)->new_encoder = intel_encoder;
8856
8857         intel_crtc = to_intel_crtc(crtc);
8858         intel_crtc->new_enabled = true;
8859         intel_crtc->new_config = intel_crtc->config;
8860         old->dpms_mode = connector->dpms;
8861         old->load_detect_temp = true;
8862         old->release_fb = NULL;
8863
8864         if (!mode)
8865                 mode = &load_detect_mode;
8866
8867         /* We need a framebuffer large enough to accommodate all accesses
8868          * that the plane may generate whilst we perform load detection.
8869          * We can not rely on the fbcon either being present (we get called
8870          * during its initialisation to detect all boot displays, or it may
8871          * not even exist) or that it is large enough to satisfy the
8872          * requested mode.
8873          */
8874         fb = mode_fits_in_fbdev(dev, mode);
8875         if (fb == NULL) {
8876                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8877                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8878                 old->release_fb = fb;
8879         } else
8880                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8881         if (IS_ERR(fb)) {
8882                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8883                 goto fail;
8884         }
8885
8886         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8887                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8888                 if (old->release_fb)
8889                         old->release_fb->funcs->destroy(old->release_fb);
8890                 goto fail;
8891         }
8892         crtc->primary->crtc = crtc;
8893
8894         /* let the connector get through one full cycle before testing */
8895         intel_wait_for_vblank(dev, intel_crtc->pipe);
8896         return true;
8897
8898  fail:
8899         intel_crtc->new_enabled = crtc->state->enable;
8900         if (intel_crtc->new_enabled)
8901                 intel_crtc->new_config = intel_crtc->config;
8902         else
8903                 intel_crtc->new_config = NULL;
8904 fail_unlock:
8905         if (ret == -EDEADLK) {
8906                 drm_modeset_backoff(ctx);
8907                 goto retry;
8908         }
8909
8910         return false;
8911 }
8912
8913 void intel_release_load_detect_pipe(struct drm_connector *connector,
8914                                     struct intel_load_detect_pipe *old)
8915 {
8916         struct intel_encoder *intel_encoder =
8917                 intel_attached_encoder(connector);
8918         struct drm_encoder *encoder = &intel_encoder->base;
8919         struct drm_crtc *crtc = encoder->crtc;
8920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8921
8922         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8923                       connector->base.id, connector->name,
8924                       encoder->base.id, encoder->name);
8925
8926         if (old->load_detect_temp) {
8927                 to_intel_connector(connector)->new_encoder = NULL;
8928                 intel_encoder->new_crtc = NULL;
8929                 intel_crtc->new_enabled = false;
8930                 intel_crtc->new_config = NULL;
8931                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8932
8933                 if (old->release_fb) {
8934                         drm_framebuffer_unregister_private(old->release_fb);
8935                         drm_framebuffer_unreference(old->release_fb);
8936                 }
8937
8938                 return;
8939         }
8940
8941         /* Switch crtc and encoder back off if necessary */
8942         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8943                 connector->funcs->dpms(connector, old->dpms_mode);
8944 }
8945
8946 static int i9xx_pll_refclk(struct drm_device *dev,
8947                            const struct intel_crtc_state *pipe_config)
8948 {
8949         struct drm_i915_private *dev_priv = dev->dev_private;
8950         u32 dpll = pipe_config->dpll_hw_state.dpll;
8951
8952         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8953                 return dev_priv->vbt.lvds_ssc_freq;
8954         else if (HAS_PCH_SPLIT(dev))
8955                 return 120000;
8956         else if (!IS_GEN2(dev))
8957                 return 96000;
8958         else
8959                 return 48000;
8960 }
8961
8962 /* Returns the clock of the currently programmed mode of the given pipe. */
8963 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8964                                 struct intel_crtc_state *pipe_config)
8965 {
8966         struct drm_device *dev = crtc->base.dev;
8967         struct drm_i915_private *dev_priv = dev->dev_private;
8968         int pipe = pipe_config->cpu_transcoder;
8969         u32 dpll = pipe_config->dpll_hw_state.dpll;
8970         u32 fp;
8971         intel_clock_t clock;
8972         int refclk = i9xx_pll_refclk(dev, pipe_config);
8973
8974         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8975                 fp = pipe_config->dpll_hw_state.fp0;
8976         else
8977                 fp = pipe_config->dpll_hw_state.fp1;
8978
8979         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8980         if (IS_PINEVIEW(dev)) {
8981                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8982                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8983         } else {
8984                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8985                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8986         }
8987
8988         if (!IS_GEN2(dev)) {
8989                 if (IS_PINEVIEW(dev))
8990                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8991                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8992                 else
8993                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8994                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8995
8996                 switch (dpll & DPLL_MODE_MASK) {
8997                 case DPLLB_MODE_DAC_SERIAL:
8998                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8999                                 5 : 10;
9000                         break;
9001                 case DPLLB_MODE_LVDS:
9002                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9003                                 7 : 14;
9004                         break;
9005                 default:
9006                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9007                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9008                         return;
9009                 }
9010
9011                 if (IS_PINEVIEW(dev))
9012                         pineview_clock(refclk, &clock);
9013                 else
9014                         i9xx_clock(refclk, &clock);
9015         } else {
9016                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9017                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9018
9019                 if (is_lvds) {
9020                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9021                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9022
9023                         if (lvds & LVDS_CLKB_POWER_UP)
9024                                 clock.p2 = 7;
9025                         else
9026                                 clock.p2 = 14;
9027                 } else {
9028                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9029                                 clock.p1 = 2;
9030                         else {
9031                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9032                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9033                         }
9034                         if (dpll & PLL_P2_DIVIDE_BY_4)
9035                                 clock.p2 = 4;
9036                         else
9037                                 clock.p2 = 2;
9038                 }
9039
9040                 i9xx_clock(refclk, &clock);
9041         }
9042
9043         /*
9044          * This value includes pixel_multiplier. We will use
9045          * port_clock to compute adjusted_mode.crtc_clock in the
9046          * encoder's get_config() function.
9047          */
9048         pipe_config->port_clock = clock.dot;
9049 }
9050
9051 int intel_dotclock_calculate(int link_freq,
9052                              const struct intel_link_m_n *m_n)
9053 {
9054         /*
9055          * The calculation for the data clock is:
9056          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9057          * But we want to avoid losing precison if possible, so:
9058          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9059          *
9060          * and the link clock is simpler:
9061          * link_clock = (m * link_clock) / n
9062          */
9063
9064         if (!m_n->link_n)
9065                 return 0;
9066
9067         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9068 }
9069
9070 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9071                                    struct intel_crtc_state *pipe_config)
9072 {
9073         struct drm_device *dev = crtc->base.dev;
9074
9075         /* read out port_clock from the DPLL */
9076         i9xx_crtc_clock_get(crtc, pipe_config);
9077
9078         /*
9079          * This value does not include pixel_multiplier.
9080          * We will check that port_clock and adjusted_mode.crtc_clock
9081          * agree once we know their relationship in the encoder's
9082          * get_config() function.
9083          */
9084         pipe_config->base.adjusted_mode.crtc_clock =
9085                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9086                                          &pipe_config->fdi_m_n);
9087 }
9088
9089 /** Returns the currently programmed mode of the given pipe. */
9090 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9091                                              struct drm_crtc *crtc)
9092 {
9093         struct drm_i915_private *dev_priv = dev->dev_private;
9094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9095         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9096         struct drm_display_mode *mode;
9097         struct intel_crtc_state pipe_config;
9098         int htot = I915_READ(HTOTAL(cpu_transcoder));
9099         int hsync = I915_READ(HSYNC(cpu_transcoder));
9100         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9101         int vsync = I915_READ(VSYNC(cpu_transcoder));
9102         enum pipe pipe = intel_crtc->pipe;
9103
9104         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9105         if (!mode)
9106                 return NULL;
9107
9108         /*
9109          * Construct a pipe_config sufficient for getting the clock info
9110          * back out of crtc_clock_get.
9111          *
9112          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9113          * to use a real value here instead.
9114          */
9115         pipe_config.cpu_transcoder = (enum transcoder) pipe;
9116         pipe_config.pixel_multiplier = 1;
9117         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9118         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9119         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9120         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9121
9122         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9123         mode->hdisplay = (htot & 0xffff) + 1;
9124         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9125         mode->hsync_start = (hsync & 0xffff) + 1;
9126         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9127         mode->vdisplay = (vtot & 0xffff) + 1;
9128         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9129         mode->vsync_start = (vsync & 0xffff) + 1;
9130         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9131
9132         drm_mode_set_name(mode);
9133
9134         return mode;
9135 }
9136
9137 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9138 {
9139         struct drm_device *dev = crtc->dev;
9140         struct drm_i915_private *dev_priv = dev->dev_private;
9141         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9142
9143         if (!HAS_GMCH_DISPLAY(dev))
9144                 return;
9145
9146         if (!dev_priv->lvds_downclock_avail)
9147                 return;
9148
9149         /*
9150          * Since this is called by a timer, we should never get here in
9151          * the manual case.
9152          */
9153         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9154                 int pipe = intel_crtc->pipe;
9155                 int dpll_reg = DPLL(pipe);
9156                 int dpll;
9157
9158                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9159
9160                 assert_panel_unlocked(dev_priv, pipe);
9161
9162                 dpll = I915_READ(dpll_reg);
9163                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9164                 I915_WRITE(dpll_reg, dpll);
9165                 intel_wait_for_vblank(dev, pipe);
9166                 dpll = I915_READ(dpll_reg);
9167                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9168                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9169         }
9170
9171 }
9172
9173 void intel_mark_busy(struct drm_device *dev)
9174 {
9175         struct drm_i915_private *dev_priv = dev->dev_private;
9176
9177         if (dev_priv->mm.busy)
9178                 return;
9179
9180         intel_runtime_pm_get(dev_priv);
9181         i915_update_gfx_val(dev_priv);
9182         dev_priv->mm.busy = true;
9183 }
9184
9185 void intel_mark_idle(struct drm_device *dev)
9186 {
9187         struct drm_i915_private *dev_priv = dev->dev_private;
9188         struct drm_crtc *crtc;
9189
9190         if (!dev_priv->mm.busy)
9191                 return;
9192
9193         dev_priv->mm.busy = false;
9194
9195         if (!i915.powersave)
9196                 goto out;
9197
9198         for_each_crtc(dev, crtc) {
9199                 if (!crtc->primary->fb)
9200                         continue;
9201
9202                 intel_decrease_pllclock(crtc);
9203         }
9204
9205         if (INTEL_INFO(dev)->gen >= 6)
9206                 gen6_rps_idle(dev->dev_private);
9207
9208 out:
9209         intel_runtime_pm_put(dev_priv);
9210 }
9211
9212 static void intel_crtc_set_state(struct intel_crtc *crtc,
9213                                  struct intel_crtc_state *crtc_state)
9214 {
9215         kfree(crtc->config);
9216         crtc->config = crtc_state;
9217         crtc->base.state = &crtc_state->base;
9218 }
9219
9220 static void intel_crtc_destroy(struct drm_crtc *crtc)
9221 {
9222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9223         struct drm_device *dev = crtc->dev;
9224         struct intel_unpin_work *work;
9225
9226         spin_lock_irq(&dev->event_lock);
9227         work = intel_crtc->unpin_work;
9228         intel_crtc->unpin_work = NULL;
9229         spin_unlock_irq(&dev->event_lock);
9230
9231         if (work) {
9232                 cancel_work_sync(&work->work);
9233                 kfree(work);
9234         }
9235
9236         intel_crtc_set_state(intel_crtc, NULL);
9237         drm_crtc_cleanup(crtc);
9238
9239         kfree(intel_crtc);
9240 }
9241
9242 static void intel_unpin_work_fn(struct work_struct *__work)
9243 {
9244         struct intel_unpin_work *work =
9245                 container_of(__work, struct intel_unpin_work, work);
9246         struct drm_device *dev = work->crtc->dev;
9247         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9248
9249         mutex_lock(&dev->struct_mutex);
9250         intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9251         drm_gem_object_unreference(&work->pending_flip_obj->base);
9252         drm_framebuffer_unreference(work->old_fb);
9253
9254         intel_fbc_update(dev);
9255
9256         if (work->flip_queued_req)
9257                 i915_gem_request_assign(&work->flip_queued_req, NULL);
9258         mutex_unlock(&dev->struct_mutex);
9259
9260         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9261
9262         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9263         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9264
9265         kfree(work);
9266 }
9267
9268 static void do_intel_finish_page_flip(struct drm_device *dev,
9269                                       struct drm_crtc *crtc)
9270 {
9271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9272         struct intel_unpin_work *work;
9273         unsigned long flags;
9274
9275         /* Ignore early vblank irqs */
9276         if (intel_crtc == NULL)
9277                 return;
9278
9279         /*
9280          * This is called both by irq handlers and the reset code (to complete
9281          * lost pageflips) so needs the full irqsave spinlocks.
9282          */
9283         spin_lock_irqsave(&dev->event_lock, flags);
9284         work = intel_crtc->unpin_work;
9285
9286         /* Ensure we don't miss a work->pending update ... */
9287         smp_rmb();
9288
9289         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9290                 spin_unlock_irqrestore(&dev->event_lock, flags);
9291                 return;
9292         }
9293
9294         page_flip_completed(intel_crtc);
9295
9296         spin_unlock_irqrestore(&dev->event_lock, flags);
9297 }
9298
9299 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9300 {
9301         struct drm_i915_private *dev_priv = dev->dev_private;
9302         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9303
9304         do_intel_finish_page_flip(dev, crtc);
9305 }
9306
9307 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9308 {
9309         struct drm_i915_private *dev_priv = dev->dev_private;
9310         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9311
9312         do_intel_finish_page_flip(dev, crtc);
9313 }
9314
9315 /* Is 'a' after or equal to 'b'? */
9316 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9317 {
9318         return !((a - b) & 0x80000000);
9319 }
9320
9321 static bool page_flip_finished(struct intel_crtc *crtc)
9322 {
9323         struct drm_device *dev = crtc->base.dev;
9324         struct drm_i915_private *dev_priv = dev->dev_private;
9325
9326         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9327             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9328                 return true;
9329
9330         /*
9331          * The relevant registers doen't exist on pre-ctg.
9332          * As the flip done interrupt doesn't trigger for mmio
9333          * flips on gmch platforms, a flip count check isn't
9334          * really needed there. But since ctg has the registers,
9335          * include it in the check anyway.
9336          */
9337         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9338                 return true;
9339
9340         /*
9341          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9342          * used the same base address. In that case the mmio flip might
9343          * have completed, but the CS hasn't even executed the flip yet.
9344          *
9345          * A flip count check isn't enough as the CS might have updated
9346          * the base address just after start of vblank, but before we
9347          * managed to process the interrupt. This means we'd complete the
9348          * CS flip too soon.
9349          *
9350          * Combining both checks should get us a good enough result. It may
9351          * still happen that the CS flip has been executed, but has not
9352          * yet actually completed. But in case the base address is the same
9353          * anyway, we don't really care.
9354          */
9355         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9356                 crtc->unpin_work->gtt_offset &&
9357                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9358                                     crtc->unpin_work->flip_count);
9359 }
9360
9361 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9362 {
9363         struct drm_i915_private *dev_priv = dev->dev_private;
9364         struct intel_crtc *intel_crtc =
9365                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9366         unsigned long flags;
9367
9368
9369         /*
9370          * This is called both by irq handlers and the reset code (to complete
9371          * lost pageflips) so needs the full irqsave spinlocks.
9372          *
9373          * NB: An MMIO update of the plane base pointer will also
9374          * generate a page-flip completion irq, i.e. every modeset
9375          * is also accompanied by a spurious intel_prepare_page_flip().
9376          */
9377         spin_lock_irqsave(&dev->event_lock, flags);
9378         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9379                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9380         spin_unlock_irqrestore(&dev->event_lock, flags);
9381 }
9382
9383 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9384 {
9385         /* Ensure that the work item is consistent when activating it ... */
9386         smp_wmb();
9387         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9388         /* and that it is marked active as soon as the irq could fire. */
9389         smp_wmb();
9390 }
9391
9392 static int intel_gen2_queue_flip(struct drm_device *dev,
9393                                  struct drm_crtc *crtc,
9394                                  struct drm_framebuffer *fb,
9395                                  struct drm_i915_gem_object *obj,
9396                                  struct intel_engine_cs *ring,
9397                                  uint32_t flags)
9398 {
9399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9400         u32 flip_mask;
9401         int ret;
9402
9403         ret = intel_ring_begin(ring, 6);
9404         if (ret)
9405                 return ret;
9406
9407         /* Can't queue multiple flips, so wait for the previous
9408          * one to finish before executing the next.
9409          */
9410         if (intel_crtc->plane)
9411                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9412         else
9413                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9414         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9415         intel_ring_emit(ring, MI_NOOP);
9416         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9417                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9418         intel_ring_emit(ring, fb->pitches[0]);
9419         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9420         intel_ring_emit(ring, 0); /* aux display base address, unused */
9421
9422         intel_mark_page_flip_active(intel_crtc);
9423         __intel_ring_advance(ring);
9424         return 0;
9425 }
9426
9427 static int intel_gen3_queue_flip(struct drm_device *dev,
9428                                  struct drm_crtc *crtc,
9429                                  struct drm_framebuffer *fb,
9430                                  struct drm_i915_gem_object *obj,
9431                                  struct intel_engine_cs *ring,
9432                                  uint32_t flags)
9433 {
9434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9435         u32 flip_mask;
9436         int ret;
9437
9438         ret = intel_ring_begin(ring, 6);
9439         if (ret)
9440                 return ret;
9441
9442         if (intel_crtc->plane)
9443                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9444         else
9445                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9446         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9447         intel_ring_emit(ring, MI_NOOP);
9448         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9449                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9450         intel_ring_emit(ring, fb->pitches[0]);
9451         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9452         intel_ring_emit(ring, MI_NOOP);
9453
9454         intel_mark_page_flip_active(intel_crtc);
9455         __intel_ring_advance(ring);
9456         return 0;
9457 }
9458
9459 static int intel_gen4_queue_flip(struct drm_device *dev,
9460                                  struct drm_crtc *crtc,
9461                                  struct drm_framebuffer *fb,
9462                                  struct drm_i915_gem_object *obj,
9463                                  struct intel_engine_cs *ring,
9464                                  uint32_t flags)
9465 {
9466         struct drm_i915_private *dev_priv = dev->dev_private;
9467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9468         uint32_t pf, pipesrc;
9469         int ret;
9470
9471         ret = intel_ring_begin(ring, 4);
9472         if (ret)
9473                 return ret;
9474
9475         /* i965+ uses the linear or tiled offsets from the
9476          * Display Registers (which do not change across a page-flip)
9477          * so we need only reprogram the base address.
9478          */
9479         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9480                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9481         intel_ring_emit(ring, fb->pitches[0]);
9482         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9483                         obj->tiling_mode);
9484
9485         /* XXX Enabling the panel-fitter across page-flip is so far
9486          * untested on non-native modes, so ignore it for now.
9487          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9488          */
9489         pf = 0;
9490         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9491         intel_ring_emit(ring, pf | pipesrc);
9492
9493         intel_mark_page_flip_active(intel_crtc);
9494         __intel_ring_advance(ring);
9495         return 0;
9496 }
9497
9498 static int intel_gen6_queue_flip(struct drm_device *dev,
9499                                  struct drm_crtc *crtc,
9500                                  struct drm_framebuffer *fb,
9501                                  struct drm_i915_gem_object *obj,
9502                                  struct intel_engine_cs *ring,
9503                                  uint32_t flags)
9504 {
9505         struct drm_i915_private *dev_priv = dev->dev_private;
9506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9507         uint32_t pf, pipesrc;
9508         int ret;
9509
9510         ret = intel_ring_begin(ring, 4);
9511         if (ret)
9512                 return ret;
9513
9514         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9515                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9516         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9517         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9518
9519         /* Contrary to the suggestions in the documentation,
9520          * "Enable Panel Fitter" does not seem to be required when page
9521          * flipping with a non-native mode, and worse causes a normal
9522          * modeset to fail.
9523          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9524          */
9525         pf = 0;
9526         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9527         intel_ring_emit(ring, pf | pipesrc);
9528
9529         intel_mark_page_flip_active(intel_crtc);
9530         __intel_ring_advance(ring);
9531         return 0;
9532 }
9533
9534 static int intel_gen7_queue_flip(struct drm_device *dev,
9535                                  struct drm_crtc *crtc,
9536                                  struct drm_framebuffer *fb,
9537                                  struct drm_i915_gem_object *obj,
9538                                  struct intel_engine_cs *ring,
9539                                  uint32_t flags)
9540 {
9541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9542         uint32_t plane_bit = 0;
9543         int len, ret;
9544
9545         switch (intel_crtc->plane) {
9546         case PLANE_A:
9547                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9548                 break;
9549         case PLANE_B:
9550                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9551                 break;
9552         case PLANE_C:
9553                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9554                 break;
9555         default:
9556                 WARN_ONCE(1, "unknown plane in flip command\n");
9557                 return -ENODEV;
9558         }
9559
9560         len = 4;
9561         if (ring->id == RCS) {
9562                 len += 6;
9563                 /*
9564                  * On Gen 8, SRM is now taking an extra dword to accommodate
9565                  * 48bits addresses, and we need a NOOP for the batch size to
9566                  * stay even.
9567                  */
9568                 if (IS_GEN8(dev))
9569                         len += 2;
9570         }
9571
9572         /*
9573          * BSpec MI_DISPLAY_FLIP for IVB:
9574          * "The full packet must be contained within the same cache line."
9575          *
9576          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9577          * cacheline, if we ever start emitting more commands before
9578          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9579          * then do the cacheline alignment, and finally emit the
9580          * MI_DISPLAY_FLIP.
9581          */
9582         ret = intel_ring_cacheline_align(ring);
9583         if (ret)
9584                 return ret;
9585
9586         ret = intel_ring_begin(ring, len);
9587         if (ret)
9588                 return ret;
9589
9590         /* Unmask the flip-done completion message. Note that the bspec says that
9591          * we should do this for both the BCS and RCS, and that we must not unmask
9592          * more than one flip event at any time (or ensure that one flip message
9593          * can be sent by waiting for flip-done prior to queueing new flips).
9594          * Experimentation says that BCS works despite DERRMR masking all
9595          * flip-done completion events and that unmasking all planes at once
9596          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9597          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9598          */
9599         if (ring->id == RCS) {
9600                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9601                 intel_ring_emit(ring, DERRMR);
9602                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9603                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9604                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9605                 if (IS_GEN8(dev))
9606                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9607                                               MI_SRM_LRM_GLOBAL_GTT);
9608                 else
9609                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9610                                               MI_SRM_LRM_GLOBAL_GTT);
9611                 intel_ring_emit(ring, DERRMR);
9612                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9613                 if (IS_GEN8(dev)) {
9614                         intel_ring_emit(ring, 0);
9615                         intel_ring_emit(ring, MI_NOOP);
9616                 }
9617         }
9618
9619         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9620         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9621         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9622         intel_ring_emit(ring, (MI_NOOP));
9623
9624         intel_mark_page_flip_active(intel_crtc);
9625         __intel_ring_advance(ring);
9626         return 0;
9627 }
9628
9629 static bool use_mmio_flip(struct intel_engine_cs *ring,
9630                           struct drm_i915_gem_object *obj)
9631 {
9632         /*
9633          * This is not being used for older platforms, because
9634          * non-availability of flip done interrupt forces us to use
9635          * CS flips. Older platforms derive flip done using some clever
9636          * tricks involving the flip_pending status bits and vblank irqs.
9637          * So using MMIO flips there would disrupt this mechanism.
9638          */
9639
9640         if (ring == NULL)
9641                 return true;
9642
9643         if (INTEL_INFO(ring->dev)->gen < 5)
9644                 return false;
9645
9646         if (i915.use_mmio_flip < 0)
9647                 return false;
9648         else if (i915.use_mmio_flip > 0)
9649                 return true;
9650         else if (i915.enable_execlists)
9651                 return true;
9652         else
9653                 return ring != i915_gem_request_get_ring(obj->last_read_req);
9654 }
9655
9656 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9657 {
9658         struct drm_device *dev = intel_crtc->base.dev;
9659         struct drm_i915_private *dev_priv = dev->dev_private;
9660         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9661         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9662         struct drm_i915_gem_object *obj = intel_fb->obj;
9663         const enum pipe pipe = intel_crtc->pipe;
9664         u32 ctl, stride;
9665
9666         ctl = I915_READ(PLANE_CTL(pipe, 0));
9667         ctl &= ~PLANE_CTL_TILED_MASK;
9668         if (obj->tiling_mode == I915_TILING_X)
9669                 ctl |= PLANE_CTL_TILED_X;
9670
9671         /*
9672          * The stride is either expressed as a multiple of 64 bytes chunks for
9673          * linear buffers or in number of tiles for tiled buffers.
9674          */
9675         stride = fb->pitches[0] >> 6;
9676         if (obj->tiling_mode == I915_TILING_X)
9677                 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9678
9679         /*
9680          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9681          * PLANE_SURF updates, the update is then guaranteed to be atomic.
9682          */
9683         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9684         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9685
9686         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9687         POSTING_READ(PLANE_SURF(pipe, 0));
9688 }
9689
9690 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9691 {
9692         struct drm_device *dev = intel_crtc->base.dev;
9693         struct drm_i915_private *dev_priv = dev->dev_private;
9694         struct intel_framebuffer *intel_fb =
9695                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9696         struct drm_i915_gem_object *obj = intel_fb->obj;
9697         u32 dspcntr;
9698         u32 reg;
9699
9700         reg = DSPCNTR(intel_crtc->plane);
9701         dspcntr = I915_READ(reg);
9702
9703         if (obj->tiling_mode != I915_TILING_NONE)
9704                 dspcntr |= DISPPLANE_TILED;
9705         else
9706                 dspcntr &= ~DISPPLANE_TILED;
9707
9708         I915_WRITE(reg, dspcntr);
9709
9710         I915_WRITE(DSPSURF(intel_crtc->plane),
9711                    intel_crtc->unpin_work->gtt_offset);
9712         POSTING_READ(DSPSURF(intel_crtc->plane));
9713
9714 }
9715
9716 /*
9717  * XXX: This is the temporary way to update the plane registers until we get
9718  * around to using the usual plane update functions for MMIO flips
9719  */
9720 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9721 {
9722         struct drm_device *dev = intel_crtc->base.dev;
9723         bool atomic_update;
9724         u32 start_vbl_count;
9725
9726         intel_mark_page_flip_active(intel_crtc);
9727
9728         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9729
9730         if (INTEL_INFO(dev)->gen >= 9)
9731                 skl_do_mmio_flip(intel_crtc);
9732         else
9733                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9734                 ilk_do_mmio_flip(intel_crtc);
9735
9736         if (atomic_update)
9737                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9738 }
9739
9740 static void intel_mmio_flip_work_func(struct work_struct *work)
9741 {
9742         struct intel_crtc *crtc =
9743                 container_of(work, struct intel_crtc, mmio_flip.work);
9744         struct intel_mmio_flip *mmio_flip;
9745
9746         mmio_flip = &crtc->mmio_flip;
9747         if (mmio_flip->req)
9748                 WARN_ON(__i915_wait_request(mmio_flip->req,
9749                                             crtc->reset_counter,
9750                                             false, NULL, NULL) != 0);
9751
9752         intel_do_mmio_flip(crtc);
9753         if (mmio_flip->req) {
9754                 mutex_lock(&crtc->base.dev->struct_mutex);
9755                 i915_gem_request_assign(&mmio_flip->req, NULL);
9756                 mutex_unlock(&crtc->base.dev->struct_mutex);
9757         }
9758 }
9759
9760 static int intel_queue_mmio_flip(struct drm_device *dev,
9761                                  struct drm_crtc *crtc,
9762                                  struct drm_framebuffer *fb,
9763                                  struct drm_i915_gem_object *obj,
9764                                  struct intel_engine_cs *ring,
9765                                  uint32_t flags)
9766 {
9767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9768
9769         i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9770                                 obj->last_write_req);
9771
9772         schedule_work(&intel_crtc->mmio_flip.work);
9773
9774         return 0;
9775 }
9776
9777 static int intel_default_queue_flip(struct drm_device *dev,
9778                                     struct drm_crtc *crtc,
9779                                     struct drm_framebuffer *fb,
9780                                     struct drm_i915_gem_object *obj,
9781                                     struct intel_engine_cs *ring,
9782                                     uint32_t flags)
9783 {
9784         return -ENODEV;
9785 }
9786
9787 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9788                                          struct drm_crtc *crtc)
9789 {
9790         struct drm_i915_private *dev_priv = dev->dev_private;
9791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9792         struct intel_unpin_work *work = intel_crtc->unpin_work;
9793         u32 addr;
9794
9795         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9796                 return true;
9797
9798         if (!work->enable_stall_check)
9799                 return false;
9800
9801         if (work->flip_ready_vblank == 0) {
9802                 if (work->flip_queued_req &&
9803                     !i915_gem_request_completed(work->flip_queued_req, true))
9804                         return false;
9805
9806                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9807         }
9808
9809         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9810                 return false;
9811
9812         /* Potential stall - if we see that the flip has happened,
9813          * assume a missed interrupt. */
9814         if (INTEL_INFO(dev)->gen >= 4)
9815                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9816         else
9817                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9818
9819         /* There is a potential issue here with a false positive after a flip
9820          * to the same address. We could address this by checking for a
9821          * non-incrementing frame counter.
9822          */
9823         return addr == work->gtt_offset;
9824 }
9825
9826 void intel_check_page_flip(struct drm_device *dev, int pipe)
9827 {
9828         struct drm_i915_private *dev_priv = dev->dev_private;
9829         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9831
9832         WARN_ON(!in_irq());
9833
9834         if (crtc == NULL)
9835                 return;
9836
9837         spin_lock(&dev->event_lock);
9838         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9839                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9840                          intel_crtc->unpin_work->flip_queued_vblank,
9841                          drm_vblank_count(dev, pipe));
9842                 page_flip_completed(intel_crtc);
9843         }
9844         spin_unlock(&dev->event_lock);
9845 }
9846
9847 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9848                                 struct drm_framebuffer *fb,
9849                                 struct drm_pending_vblank_event *event,
9850                                 uint32_t page_flip_flags)
9851 {
9852         struct drm_device *dev = crtc->dev;
9853         struct drm_i915_private *dev_priv = dev->dev_private;
9854         struct drm_framebuffer *old_fb = crtc->primary->fb;
9855         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9857         struct drm_plane *primary = crtc->primary;
9858         enum pipe pipe = intel_crtc->pipe;
9859         struct intel_unpin_work *work;
9860         struct intel_engine_cs *ring;
9861         int ret;
9862
9863         /*
9864          * drm_mode_page_flip_ioctl() should already catch this, but double
9865          * check to be safe.  In the future we may enable pageflipping from
9866          * a disabled primary plane.
9867          */
9868         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9869                 return -EBUSY;
9870
9871         /* Can't change pixel format via MI display flips. */
9872         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9873                 return -EINVAL;
9874
9875         /*
9876          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9877          * Note that pitch changes could also affect these register.
9878          */
9879         if (INTEL_INFO(dev)->gen > 3 &&
9880             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9881              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9882                 return -EINVAL;
9883
9884         if (i915_terminally_wedged(&dev_priv->gpu_error))
9885                 goto out_hang;
9886
9887         work = kzalloc(sizeof(*work), GFP_KERNEL);
9888         if (work == NULL)
9889                 return -ENOMEM;
9890
9891         work->event = event;
9892         work->crtc = crtc;
9893         work->old_fb = old_fb;
9894         INIT_WORK(&work->work, intel_unpin_work_fn);
9895
9896         ret = drm_crtc_vblank_get(crtc);
9897         if (ret)
9898                 goto free_work;
9899
9900         /* We borrow the event spin lock for protecting unpin_work */
9901         spin_lock_irq(&dev->event_lock);
9902         if (intel_crtc->unpin_work) {
9903                 /* Before declaring the flip queue wedged, check if
9904                  * the hardware completed the operation behind our backs.
9905                  */
9906                 if (__intel_pageflip_stall_check(dev, crtc)) {
9907                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9908                         page_flip_completed(intel_crtc);
9909                 } else {
9910                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9911                         spin_unlock_irq(&dev->event_lock);
9912
9913                         drm_crtc_vblank_put(crtc);
9914                         kfree(work);
9915                         return -EBUSY;
9916                 }
9917         }
9918         intel_crtc->unpin_work = work;
9919         spin_unlock_irq(&dev->event_lock);
9920
9921         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9922                 flush_workqueue(dev_priv->wq);
9923
9924         ret = i915_mutex_lock_interruptible(dev);
9925         if (ret)
9926                 goto cleanup;
9927
9928         /* Reference the objects for the scheduled work. */
9929         drm_framebuffer_reference(work->old_fb);
9930         drm_gem_object_reference(&obj->base);
9931
9932         crtc->primary->fb = fb;
9933         update_state_fb(crtc->primary);
9934
9935         work->pending_flip_obj = obj;
9936
9937         atomic_inc(&intel_crtc->unpin_work_count);
9938         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9939
9940         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9941                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9942
9943         if (IS_VALLEYVIEW(dev)) {
9944                 ring = &dev_priv->ring[BCS];
9945                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9946                         /* vlv: DISPLAY_FLIP fails to change tiling */
9947                         ring = NULL;
9948         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9949                 ring = &dev_priv->ring[BCS];
9950         } else if (INTEL_INFO(dev)->gen >= 7) {
9951                 ring = i915_gem_request_get_ring(obj->last_read_req);
9952                 if (ring == NULL || ring->id != RCS)
9953                         ring = &dev_priv->ring[BCS];
9954         } else {
9955                 ring = &dev_priv->ring[RCS];
9956         }
9957
9958         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9959         if (ret)
9960                 goto cleanup_pending;
9961
9962         work->gtt_offset =
9963                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9964
9965         if (use_mmio_flip(ring, obj)) {
9966                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9967                                             page_flip_flags);
9968                 if (ret)
9969                         goto cleanup_unpin;
9970
9971                 i915_gem_request_assign(&work->flip_queued_req,
9972                                         obj->last_write_req);
9973         } else {
9974                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9975                                                    page_flip_flags);
9976                 if (ret)
9977                         goto cleanup_unpin;
9978
9979                 i915_gem_request_assign(&work->flip_queued_req,
9980                                         intel_ring_get_request(ring));
9981         }
9982
9983         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
9984         work->enable_stall_check = true;
9985
9986         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9987                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9988
9989         intel_fbc_disable(dev);
9990         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9991         mutex_unlock(&dev->struct_mutex);
9992
9993         trace_i915_flip_request(intel_crtc->plane, obj);
9994
9995         return 0;
9996
9997 cleanup_unpin:
9998         intel_unpin_fb_obj(obj);
9999 cleanup_pending:
10000         atomic_dec(&intel_crtc->unpin_work_count);
10001         crtc->primary->fb = old_fb;
10002         update_state_fb(crtc->primary);
10003         drm_framebuffer_unreference(work->old_fb);
10004         drm_gem_object_unreference(&obj->base);
10005         mutex_unlock(&dev->struct_mutex);
10006
10007 cleanup:
10008         spin_lock_irq(&dev->event_lock);
10009         intel_crtc->unpin_work = NULL;
10010         spin_unlock_irq(&dev->event_lock);
10011
10012         drm_crtc_vblank_put(crtc);
10013 free_work:
10014         kfree(work);
10015
10016         if (ret == -EIO) {
10017 out_hang:
10018                 ret = intel_plane_restore(primary);
10019                 if (ret == 0 && event) {
10020                         spin_lock_irq(&dev->event_lock);
10021                         drm_send_vblank_event(dev, pipe, event);
10022                         spin_unlock_irq(&dev->event_lock);
10023                 }
10024         }
10025         return ret;
10026 }
10027
10028 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10029         .mode_set_base_atomic = intel_pipe_set_base_atomic,
10030         .load_lut = intel_crtc_load_lut,
10031         .atomic_begin = intel_begin_crtc_commit,
10032         .atomic_flush = intel_finish_crtc_commit,
10033 };
10034
10035 /**
10036  * intel_modeset_update_staged_output_state
10037  *
10038  * Updates the staged output configuration state, e.g. after we've read out the
10039  * current hw state.
10040  */
10041 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10042 {
10043         struct intel_crtc *crtc;
10044         struct intel_encoder *encoder;
10045         struct intel_connector *connector;
10046
10047         for_each_intel_connector(dev, connector) {
10048                 connector->new_encoder =
10049                         to_intel_encoder(connector->base.encoder);
10050         }
10051
10052         for_each_intel_encoder(dev, encoder) {
10053                 encoder->new_crtc =
10054                         to_intel_crtc(encoder->base.crtc);
10055         }
10056
10057         for_each_intel_crtc(dev, crtc) {
10058                 crtc->new_enabled = crtc->base.state->enable;
10059
10060                 if (crtc->new_enabled)
10061                         crtc->new_config = crtc->config;
10062                 else
10063                         crtc->new_config = NULL;
10064         }
10065 }
10066
10067 /**
10068  * intel_modeset_commit_output_state
10069  *
10070  * This function copies the stage display pipe configuration to the real one.
10071  */
10072 static void intel_modeset_commit_output_state(struct drm_device *dev)
10073 {
10074         struct intel_crtc *crtc;
10075         struct intel_encoder *encoder;
10076         struct intel_connector *connector;
10077
10078         for_each_intel_connector(dev, connector) {
10079                 connector->base.encoder = &connector->new_encoder->base;
10080         }
10081
10082         for_each_intel_encoder(dev, encoder) {
10083                 encoder->base.crtc = &encoder->new_crtc->base;
10084         }
10085
10086         for_each_intel_crtc(dev, crtc) {
10087                 crtc->base.state->enable = crtc->new_enabled;
10088                 crtc->base.enabled = crtc->new_enabled;
10089         }
10090 }
10091
10092 static void
10093 connected_sink_compute_bpp(struct intel_connector *connector,
10094                            struct intel_crtc_state *pipe_config)
10095 {
10096         int bpp = pipe_config->pipe_bpp;
10097
10098         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10099                 connector->base.base.id,
10100                 connector->base.name);
10101
10102         /* Don't use an invalid EDID bpc value */
10103         if (connector->base.display_info.bpc &&
10104             connector->base.display_info.bpc * 3 < bpp) {
10105                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10106                               bpp, connector->base.display_info.bpc*3);
10107                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10108         }
10109
10110         /* Clamp bpp to 8 on screens without EDID 1.4 */
10111         if (connector->base.display_info.bpc == 0 && bpp > 24) {
10112                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10113                               bpp);
10114                 pipe_config->pipe_bpp = 24;
10115         }
10116 }
10117
10118 static int
10119 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10120                           struct drm_framebuffer *fb,
10121                           struct intel_crtc_state *pipe_config)
10122 {
10123         struct drm_device *dev = crtc->base.dev;
10124         struct intel_connector *connector;
10125         int bpp;
10126
10127         switch (fb->pixel_format) {
10128         case DRM_FORMAT_C8:
10129                 bpp = 8*3; /* since we go through a colormap */
10130                 break;
10131         case DRM_FORMAT_XRGB1555:
10132         case DRM_FORMAT_ARGB1555:
10133                 /* checked in intel_framebuffer_init already */
10134                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10135                         return -EINVAL;
10136         case DRM_FORMAT_RGB565:
10137                 bpp = 6*3; /* min is 18bpp */
10138                 break;
10139         case DRM_FORMAT_XBGR8888:
10140         case DRM_FORMAT_ABGR8888:
10141                 /* checked in intel_framebuffer_init already */
10142                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10143                         return -EINVAL;
10144         case DRM_FORMAT_XRGB8888:
10145         case DRM_FORMAT_ARGB8888:
10146                 bpp = 8*3;
10147                 break;
10148         case DRM_FORMAT_XRGB2101010:
10149         case DRM_FORMAT_ARGB2101010:
10150         case DRM_FORMAT_XBGR2101010:
10151         case DRM_FORMAT_ABGR2101010:
10152                 /* checked in intel_framebuffer_init already */
10153                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10154                         return -EINVAL;
10155                 bpp = 10*3;
10156                 break;
10157         /* TODO: gen4+ supports 16 bpc floating point, too. */
10158         default:
10159                 DRM_DEBUG_KMS("unsupported depth\n");
10160                 return -EINVAL;
10161         }
10162
10163         pipe_config->pipe_bpp = bpp;
10164
10165         /* Clamp display bpp to EDID value */
10166         for_each_intel_connector(dev, connector) {
10167                 if (!connector->new_encoder ||
10168                     connector->new_encoder->new_crtc != crtc)
10169                         continue;
10170
10171                 connected_sink_compute_bpp(connector, pipe_config);
10172         }
10173
10174         return bpp;
10175 }
10176
10177 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10178 {
10179         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10180                         "type: 0x%x flags: 0x%x\n",
10181                 mode->crtc_clock,
10182                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10183                 mode->crtc_hsync_end, mode->crtc_htotal,
10184                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10185                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10186 }
10187
10188 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10189                                    struct intel_crtc_state *pipe_config,
10190                                    const char *context)
10191 {
10192         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10193                       context, pipe_name(crtc->pipe));
10194
10195         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10196         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10197                       pipe_config->pipe_bpp, pipe_config->dither);
10198         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10199                       pipe_config->has_pch_encoder,
10200                       pipe_config->fdi_lanes,
10201                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10202                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10203                       pipe_config->fdi_m_n.tu);
10204         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10205                       pipe_config->has_dp_encoder,
10206                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10207                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10208                       pipe_config->dp_m_n.tu);
10209
10210         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10211                       pipe_config->has_dp_encoder,
10212                       pipe_config->dp_m2_n2.gmch_m,
10213                       pipe_config->dp_m2_n2.gmch_n,
10214                       pipe_config->dp_m2_n2.link_m,
10215                       pipe_config->dp_m2_n2.link_n,
10216                       pipe_config->dp_m2_n2.tu);
10217
10218         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10219                       pipe_config->has_audio,
10220                       pipe_config->has_infoframe);
10221
10222         DRM_DEBUG_KMS("requested mode:\n");
10223         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10224         DRM_DEBUG_KMS("adjusted mode:\n");
10225         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10226         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10227         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10228         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10229                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10230         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10231                       pipe_config->gmch_pfit.control,
10232                       pipe_config->gmch_pfit.pgm_ratios,
10233                       pipe_config->gmch_pfit.lvds_border_bits);
10234         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10235                       pipe_config->pch_pfit.pos,
10236                       pipe_config->pch_pfit.size,
10237                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10238         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10239         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10240 }
10241
10242 static bool encoders_cloneable(const struct intel_encoder *a,
10243                                const struct intel_encoder *b)
10244 {
10245         /* masks could be asymmetric, so check both ways */
10246         return a == b || (a->cloneable & (1 << b->type) &&
10247                           b->cloneable & (1 << a->type));
10248 }
10249
10250 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10251                                          struct intel_encoder *encoder)
10252 {
10253         struct drm_device *dev = crtc->base.dev;
10254         struct intel_encoder *source_encoder;
10255
10256         for_each_intel_encoder(dev, source_encoder) {
10257                 if (source_encoder->new_crtc != crtc)
10258                         continue;
10259
10260                 if (!encoders_cloneable(encoder, source_encoder))
10261                         return false;
10262         }
10263
10264         return true;
10265 }
10266
10267 static bool check_encoder_cloning(struct intel_crtc *crtc)
10268 {
10269         struct drm_device *dev = crtc->base.dev;
10270         struct intel_encoder *encoder;
10271
10272         for_each_intel_encoder(dev, encoder) {
10273                 if (encoder->new_crtc != crtc)
10274                         continue;
10275
10276                 if (!check_single_encoder_cloning(crtc, encoder))
10277                         return false;
10278         }
10279
10280         return true;
10281 }
10282
10283 static bool check_digital_port_conflicts(struct drm_device *dev)
10284 {
10285         struct intel_connector *connector;
10286         unsigned int used_ports = 0;
10287
10288         /*
10289          * Walk the connector list instead of the encoder
10290          * list to detect the problem on ddi platforms
10291          * where there's just one encoder per digital port.
10292          */
10293         for_each_intel_connector(dev, connector) {
10294                 struct intel_encoder *encoder = connector->new_encoder;
10295
10296                 if (!encoder)
10297                         continue;
10298
10299                 WARN_ON(!encoder->new_crtc);
10300
10301                 switch (encoder->type) {
10302                         unsigned int port_mask;
10303                 case INTEL_OUTPUT_UNKNOWN:
10304                         if (WARN_ON(!HAS_DDI(dev)))
10305                                 break;
10306                 case INTEL_OUTPUT_DISPLAYPORT:
10307                 case INTEL_OUTPUT_HDMI:
10308                 case INTEL_OUTPUT_EDP:
10309                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10310
10311                         /* the same port mustn't appear more than once */
10312                         if (used_ports & port_mask)
10313                                 return false;
10314
10315                         used_ports |= port_mask;
10316                 default:
10317                         break;
10318                 }
10319         }
10320
10321         return true;
10322 }
10323
10324 static struct intel_crtc_state *
10325 intel_modeset_pipe_config(struct drm_crtc *crtc,
10326                           struct drm_framebuffer *fb,
10327                           struct drm_display_mode *mode)
10328 {
10329         struct drm_device *dev = crtc->dev;
10330         struct intel_encoder *encoder;
10331         struct intel_crtc_state *pipe_config;
10332         int plane_bpp, ret = -EINVAL;
10333         bool retry = true;
10334
10335         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10336                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10337                 return ERR_PTR(-EINVAL);
10338         }
10339
10340         if (!check_digital_port_conflicts(dev)) {
10341                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10342                 return ERR_PTR(-EINVAL);
10343         }
10344
10345         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10346         if (!pipe_config)
10347                 return ERR_PTR(-ENOMEM);
10348
10349         pipe_config->base.crtc = crtc;
10350         drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10351         drm_mode_copy(&pipe_config->base.mode, mode);
10352
10353         pipe_config->cpu_transcoder =
10354                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10355         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10356
10357         /*
10358          * Sanitize sync polarity flags based on requested ones. If neither
10359          * positive or negative polarity is requested, treat this as meaning
10360          * negative polarity.
10361          */
10362         if (!(pipe_config->base.adjusted_mode.flags &
10363               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10364                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10365
10366         if (!(pipe_config->base.adjusted_mode.flags &
10367               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10368                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10369
10370         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10371          * plane pixel format and any sink constraints into account. Returns the
10372          * source plane bpp so that dithering can be selected on mismatches
10373          * after encoders and crtc also have had their say. */
10374         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10375                                               fb, pipe_config);
10376         if (plane_bpp < 0)
10377                 goto fail;
10378
10379         /*
10380          * Determine the real pipe dimensions. Note that stereo modes can
10381          * increase the actual pipe size due to the frame doubling and
10382          * insertion of additional space for blanks between the frame. This
10383          * is stored in the crtc timings. We use the requested mode to do this
10384          * computation to clearly distinguish it from the adjusted mode, which
10385          * can be changed by the connectors in the below retry loop.
10386          */
10387         drm_crtc_get_hv_timing(&pipe_config->base.mode,
10388                                &pipe_config->pipe_src_w,
10389                                &pipe_config->pipe_src_h);
10390
10391 encoder_retry:
10392         /* Ensure the port clock defaults are reset when retrying. */
10393         pipe_config->port_clock = 0;
10394         pipe_config->pixel_multiplier = 1;
10395
10396         /* Fill in default crtc timings, allow encoders to overwrite them. */
10397         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10398                               CRTC_STEREO_DOUBLE);
10399
10400         /* Pass our mode to the connectors and the CRTC to give them a chance to
10401          * adjust it according to limitations or connector properties, and also
10402          * a chance to reject the mode entirely.
10403          */
10404         for_each_intel_encoder(dev, encoder) {
10405
10406                 if (&encoder->new_crtc->base != crtc)
10407                         continue;
10408
10409                 if (!(encoder->compute_config(encoder, pipe_config))) {
10410                         DRM_DEBUG_KMS("Encoder config failure\n");
10411                         goto fail;
10412                 }
10413         }
10414
10415         /* Set default port clock if not overwritten by the encoder. Needs to be
10416          * done afterwards in case the encoder adjusts the mode. */
10417         if (!pipe_config->port_clock)
10418                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10419                         * pipe_config->pixel_multiplier;
10420
10421         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10422         if (ret < 0) {
10423                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10424                 goto fail;
10425         }
10426
10427         if (ret == RETRY) {
10428                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10429                         ret = -EINVAL;
10430                         goto fail;
10431                 }
10432
10433                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10434                 retry = false;
10435                 goto encoder_retry;
10436         }
10437
10438         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10439         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10440                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10441
10442         return pipe_config;
10443 fail:
10444         kfree(pipe_config);
10445         return ERR_PTR(ret);
10446 }
10447
10448 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10449  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10450 static void
10451 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10452                              unsigned *prepare_pipes, unsigned *disable_pipes)
10453 {
10454         struct intel_crtc *intel_crtc;
10455         struct drm_device *dev = crtc->dev;
10456         struct intel_encoder *encoder;
10457         struct intel_connector *connector;
10458         struct drm_crtc *tmp_crtc;
10459
10460         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10461
10462         /* Check which crtcs have changed outputs connected to them, these need
10463          * to be part of the prepare_pipes mask. We don't (yet) support global
10464          * modeset across multiple crtcs, so modeset_pipes will only have one
10465          * bit set at most. */
10466         for_each_intel_connector(dev, connector) {
10467                 if (connector->base.encoder == &connector->new_encoder->base)
10468                         continue;
10469
10470                 if (connector->base.encoder) {
10471                         tmp_crtc = connector->base.encoder->crtc;
10472
10473                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10474                 }
10475
10476                 if (connector->new_encoder)
10477                         *prepare_pipes |=
10478                                 1 << connector->new_encoder->new_crtc->pipe;
10479         }
10480
10481         for_each_intel_encoder(dev, encoder) {
10482                 if (encoder->base.crtc == &encoder->new_crtc->base)
10483                         continue;
10484
10485                 if (encoder->base.crtc) {
10486                         tmp_crtc = encoder->base.crtc;
10487
10488                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10489                 }
10490
10491                 if (encoder->new_crtc)
10492                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10493         }
10494
10495         /* Check for pipes that will be enabled/disabled ... */
10496         for_each_intel_crtc(dev, intel_crtc) {
10497                 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10498                         continue;
10499
10500                 if (!intel_crtc->new_enabled)
10501                         *disable_pipes |= 1 << intel_crtc->pipe;
10502                 else
10503                         *prepare_pipes |= 1 << intel_crtc->pipe;
10504         }
10505
10506
10507         /* set_mode is also used to update properties on life display pipes. */
10508         intel_crtc = to_intel_crtc(crtc);
10509         if (intel_crtc->new_enabled)
10510                 *prepare_pipes |= 1 << intel_crtc->pipe;
10511
10512         /*
10513          * For simplicity do a full modeset on any pipe where the output routing
10514          * changed. We could be more clever, but that would require us to be
10515          * more careful with calling the relevant encoder->mode_set functions.
10516          */
10517         if (*prepare_pipes)
10518                 *modeset_pipes = *prepare_pipes;
10519
10520         /* ... and mask these out. */
10521         *modeset_pipes &= ~(*disable_pipes);
10522         *prepare_pipes &= ~(*disable_pipes);
10523
10524         /*
10525          * HACK: We don't (yet) fully support global modesets. intel_set_config
10526          * obies this rule, but the modeset restore mode of
10527          * intel_modeset_setup_hw_state does not.
10528          */
10529         *modeset_pipes &= 1 << intel_crtc->pipe;
10530         *prepare_pipes &= 1 << intel_crtc->pipe;
10531
10532         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10533                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10534 }
10535
10536 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10537 {
10538         struct drm_encoder *encoder;
10539         struct drm_device *dev = crtc->dev;
10540
10541         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10542                 if (encoder->crtc == crtc)
10543                         return true;
10544
10545         return false;
10546 }
10547
10548 static void
10549 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10550 {
10551         struct drm_i915_private *dev_priv = dev->dev_private;
10552         struct intel_encoder *intel_encoder;
10553         struct intel_crtc *intel_crtc;
10554         struct drm_connector *connector;
10555
10556         intel_shared_dpll_commit(dev_priv);
10557
10558         for_each_intel_encoder(dev, intel_encoder) {
10559                 if (!intel_encoder->base.crtc)
10560                         continue;
10561
10562                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10563
10564                 if (prepare_pipes & (1 << intel_crtc->pipe))
10565                         intel_encoder->connectors_active = false;
10566         }
10567
10568         intel_modeset_commit_output_state(dev);
10569
10570         /* Double check state. */
10571         for_each_intel_crtc(dev, intel_crtc) {
10572                 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10573                 WARN_ON(intel_crtc->new_config &&
10574                         intel_crtc->new_config != intel_crtc->config);
10575                 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10576         }
10577
10578         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10579                 if (!connector->encoder || !connector->encoder->crtc)
10580                         continue;
10581
10582                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10583
10584                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10585                         struct drm_property *dpms_property =
10586                                 dev->mode_config.dpms_property;
10587
10588                         connector->dpms = DRM_MODE_DPMS_ON;
10589                         drm_object_property_set_value(&connector->base,
10590                                                          dpms_property,
10591                                                          DRM_MODE_DPMS_ON);
10592
10593                         intel_encoder = to_intel_encoder(connector->encoder);
10594                         intel_encoder->connectors_active = true;
10595                 }
10596         }
10597
10598 }
10599
10600 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10601 {
10602         int diff;
10603
10604         if (clock1 == clock2)
10605                 return true;
10606
10607         if (!clock1 || !clock2)
10608                 return false;
10609
10610         diff = abs(clock1 - clock2);
10611
10612         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10613                 return true;
10614
10615         return false;
10616 }
10617
10618 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10619         list_for_each_entry((intel_crtc), \
10620                             &(dev)->mode_config.crtc_list, \
10621                             base.head) \
10622                 if (mask & (1 <<(intel_crtc)->pipe))
10623
10624 static bool
10625 intel_pipe_config_compare(struct drm_device *dev,
10626                           struct intel_crtc_state *current_config,
10627                           struct intel_crtc_state *pipe_config)
10628 {
10629 #define PIPE_CONF_CHECK_X(name) \
10630         if (current_config->name != pipe_config->name) { \
10631                 DRM_ERROR("mismatch in " #name " " \
10632                           "(expected 0x%08x, found 0x%08x)\n", \
10633                           current_config->name, \
10634                           pipe_config->name); \
10635                 return false; \
10636         }
10637
10638 #define PIPE_CONF_CHECK_I(name) \
10639         if (current_config->name != pipe_config->name) { \
10640                 DRM_ERROR("mismatch in " #name " " \
10641                           "(expected %i, found %i)\n", \
10642                           current_config->name, \
10643                           pipe_config->name); \
10644                 return false; \
10645         }
10646
10647 /* This is required for BDW+ where there is only one set of registers for
10648  * switching between high and low RR.
10649  * This macro can be used whenever a comparison has to be made between one
10650  * hw state and multiple sw state variables.
10651  */
10652 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10653         if ((current_config->name != pipe_config->name) && \
10654                 (current_config->alt_name != pipe_config->name)) { \
10655                         DRM_ERROR("mismatch in " #name " " \
10656                                   "(expected %i or %i, found %i)\n", \
10657                                   current_config->name, \
10658                                   current_config->alt_name, \
10659                                   pipe_config->name); \
10660                         return false; \
10661         }
10662
10663 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10664         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10665                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10666                           "(expected %i, found %i)\n", \
10667                           current_config->name & (mask), \
10668                           pipe_config->name & (mask)); \
10669                 return false; \
10670         }
10671
10672 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10673         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10674                 DRM_ERROR("mismatch in " #name " " \
10675                           "(expected %i, found %i)\n", \
10676                           current_config->name, \
10677                           pipe_config->name); \
10678                 return false; \
10679         }
10680
10681 #define PIPE_CONF_QUIRK(quirk)  \
10682         ((current_config->quirks | pipe_config->quirks) & (quirk))
10683
10684         PIPE_CONF_CHECK_I(cpu_transcoder);
10685
10686         PIPE_CONF_CHECK_I(has_pch_encoder);
10687         PIPE_CONF_CHECK_I(fdi_lanes);
10688         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10689         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10690         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10691         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10692         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10693
10694         PIPE_CONF_CHECK_I(has_dp_encoder);
10695
10696         if (INTEL_INFO(dev)->gen < 8) {
10697                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10698                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10699                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10700                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10701                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10702
10703                 if (current_config->has_drrs) {
10704                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10705                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10706                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10707                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10708                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10709                 }
10710         } else {
10711                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10712                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10713                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10714                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10715                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10716         }
10717
10718         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10719         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10720         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10721         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10722         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10723         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10724
10725         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10726         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10727         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10728         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10729         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10730         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10731
10732         PIPE_CONF_CHECK_I(pixel_multiplier);
10733         PIPE_CONF_CHECK_I(has_hdmi_sink);
10734         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10735             IS_VALLEYVIEW(dev))
10736                 PIPE_CONF_CHECK_I(limited_color_range);
10737         PIPE_CONF_CHECK_I(has_infoframe);
10738
10739         PIPE_CONF_CHECK_I(has_audio);
10740
10741         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10742                               DRM_MODE_FLAG_INTERLACE);
10743
10744         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10745                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10746                                       DRM_MODE_FLAG_PHSYNC);
10747                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10748                                       DRM_MODE_FLAG_NHSYNC);
10749                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10750                                       DRM_MODE_FLAG_PVSYNC);
10751                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10752                                       DRM_MODE_FLAG_NVSYNC);
10753         }
10754
10755         PIPE_CONF_CHECK_I(pipe_src_w);
10756         PIPE_CONF_CHECK_I(pipe_src_h);
10757
10758         /*
10759          * FIXME: BIOS likes to set up a cloned config with lvds+external
10760          * screen. Since we don't yet re-compute the pipe config when moving
10761          * just the lvds port away to another pipe the sw tracking won't match.
10762          *
10763          * Proper atomic modesets with recomputed global state will fix this.
10764          * Until then just don't check gmch state for inherited modes.
10765          */
10766         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10767                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10768                 /* pfit ratios are autocomputed by the hw on gen4+ */
10769                 if (INTEL_INFO(dev)->gen < 4)
10770                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10771                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10772         }
10773
10774         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10775         if (current_config->pch_pfit.enabled) {
10776                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10777                 PIPE_CONF_CHECK_I(pch_pfit.size);
10778         }
10779
10780         /* BDW+ don't expose a synchronous way to read the state */
10781         if (IS_HASWELL(dev))
10782                 PIPE_CONF_CHECK_I(ips_enabled);
10783
10784         PIPE_CONF_CHECK_I(double_wide);
10785
10786         PIPE_CONF_CHECK_X(ddi_pll_sel);
10787
10788         PIPE_CONF_CHECK_I(shared_dpll);
10789         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10790         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10791         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10792         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10793         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10794         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10795         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10796         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10797
10798         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10799                 PIPE_CONF_CHECK_I(pipe_bpp);
10800
10801         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10802         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10803
10804 #undef PIPE_CONF_CHECK_X
10805 #undef PIPE_CONF_CHECK_I
10806 #undef PIPE_CONF_CHECK_I_ALT
10807 #undef PIPE_CONF_CHECK_FLAGS
10808 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10809 #undef PIPE_CONF_QUIRK
10810
10811         return true;
10812 }
10813
10814 static void check_wm_state(struct drm_device *dev)
10815 {
10816         struct drm_i915_private *dev_priv = dev->dev_private;
10817         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10818         struct intel_crtc *intel_crtc;
10819         int plane;
10820
10821         if (INTEL_INFO(dev)->gen < 9)
10822                 return;
10823
10824         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10825         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10826
10827         for_each_intel_crtc(dev, intel_crtc) {
10828                 struct skl_ddb_entry *hw_entry, *sw_entry;
10829                 const enum pipe pipe = intel_crtc->pipe;
10830
10831                 if (!intel_crtc->active)
10832                         continue;
10833
10834                 /* planes */
10835                 for_each_plane(dev_priv, pipe, plane) {
10836                         hw_entry = &hw_ddb.plane[pipe][plane];
10837                         sw_entry = &sw_ddb->plane[pipe][plane];
10838
10839                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10840                                 continue;
10841
10842                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10843                                   "(expected (%u,%u), found (%u,%u))\n",
10844                                   pipe_name(pipe), plane + 1,
10845                                   sw_entry->start, sw_entry->end,
10846                                   hw_entry->start, hw_entry->end);
10847                 }
10848
10849                 /* cursor */
10850                 hw_entry = &hw_ddb.cursor[pipe];
10851                 sw_entry = &sw_ddb->cursor[pipe];
10852
10853                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10854                         continue;
10855
10856                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10857                           "(expected (%u,%u), found (%u,%u))\n",
10858                           pipe_name(pipe),
10859                           sw_entry->start, sw_entry->end,
10860                           hw_entry->start, hw_entry->end);
10861         }
10862 }
10863
10864 static void
10865 check_connector_state(struct drm_device *dev)
10866 {
10867         struct intel_connector *connector;
10868
10869         for_each_intel_connector(dev, connector) {
10870                 /* This also checks the encoder/connector hw state with the
10871                  * ->get_hw_state callbacks. */
10872                 intel_connector_check_state(connector);
10873
10874                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10875                      "connector's staged encoder doesn't match current encoder\n");
10876         }
10877 }
10878
10879 static void
10880 check_encoder_state(struct drm_device *dev)
10881 {
10882         struct intel_encoder *encoder;
10883         struct intel_connector *connector;
10884
10885         for_each_intel_encoder(dev, encoder) {
10886                 bool enabled = false;
10887                 bool active = false;
10888                 enum pipe pipe, tracked_pipe;
10889
10890                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10891                               encoder->base.base.id,
10892                               encoder->base.name);
10893
10894                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10895                      "encoder's stage crtc doesn't match current crtc\n");
10896                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10897                      "encoder's active_connectors set, but no crtc\n");
10898
10899                 for_each_intel_connector(dev, connector) {
10900                         if (connector->base.encoder != &encoder->base)
10901                                 continue;
10902                         enabled = true;
10903                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10904                                 active = true;
10905                 }
10906                 /*
10907                  * for MST connectors if we unplug the connector is gone
10908                  * away but the encoder is still connected to a crtc
10909                  * until a modeset happens in response to the hotplug.
10910                  */
10911                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10912                         continue;
10913
10914                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10915                      "encoder's enabled state mismatch "
10916                      "(expected %i, found %i)\n",
10917                      !!encoder->base.crtc, enabled);
10918                 I915_STATE_WARN(active && !encoder->base.crtc,
10919                      "active encoder with no crtc\n");
10920
10921                 I915_STATE_WARN(encoder->connectors_active != active,
10922                      "encoder's computed active state doesn't match tracked active state "
10923                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10924
10925                 active = encoder->get_hw_state(encoder, &pipe);
10926                 I915_STATE_WARN(active != encoder->connectors_active,
10927                      "encoder's hw state doesn't match sw tracking "
10928                      "(expected %i, found %i)\n",
10929                      encoder->connectors_active, active);
10930
10931                 if (!encoder->base.crtc)
10932                         continue;
10933
10934                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10935                 I915_STATE_WARN(active && pipe != tracked_pipe,
10936                      "active encoder's pipe doesn't match"
10937                      "(expected %i, found %i)\n",
10938                      tracked_pipe, pipe);
10939
10940         }
10941 }
10942
10943 static void
10944 check_crtc_state(struct drm_device *dev)
10945 {
10946         struct drm_i915_private *dev_priv = dev->dev_private;
10947         struct intel_crtc *crtc;
10948         struct intel_encoder *encoder;
10949         struct intel_crtc_state pipe_config;
10950
10951         for_each_intel_crtc(dev, crtc) {
10952                 bool enabled = false;
10953                 bool active = false;
10954
10955                 memset(&pipe_config, 0, sizeof(pipe_config));
10956
10957                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10958                               crtc->base.base.id);
10959
10960                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
10961                      "active crtc, but not enabled in sw tracking\n");
10962
10963                 for_each_intel_encoder(dev, encoder) {
10964                         if (encoder->base.crtc != &crtc->base)
10965                                 continue;
10966                         enabled = true;
10967                         if (encoder->connectors_active)
10968                                 active = true;
10969                 }
10970
10971                 I915_STATE_WARN(active != crtc->active,
10972                      "crtc's computed active state doesn't match tracked active state "
10973                      "(expected %i, found %i)\n", active, crtc->active);
10974                 I915_STATE_WARN(enabled != crtc->base.state->enable,
10975                      "crtc's computed enabled state doesn't match tracked enabled state "
10976                      "(expected %i, found %i)\n", enabled,
10977                                 crtc->base.state->enable);
10978
10979                 active = dev_priv->display.get_pipe_config(crtc,
10980                                                            &pipe_config);
10981
10982                 /* hw state is inconsistent with the pipe quirk */
10983                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10984                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10985                         active = crtc->active;
10986
10987                 for_each_intel_encoder(dev, encoder) {
10988                         enum pipe pipe;
10989                         if (encoder->base.crtc != &crtc->base)
10990                                 continue;
10991                         if (encoder->get_hw_state(encoder, &pipe))
10992                                 encoder->get_config(encoder, &pipe_config);
10993                 }
10994
10995                 I915_STATE_WARN(crtc->active != active,
10996                      "crtc active state doesn't match with hw state "
10997                      "(expected %i, found %i)\n", crtc->active, active);
10998
10999                 if (active &&
11000                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11001                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
11002                         intel_dump_pipe_config(crtc, &pipe_config,
11003                                                "[hw state]");
11004                         intel_dump_pipe_config(crtc, crtc->config,
11005                                                "[sw state]");
11006                 }
11007         }
11008 }
11009
11010 static void
11011 check_shared_dpll_state(struct drm_device *dev)
11012 {
11013         struct drm_i915_private *dev_priv = dev->dev_private;
11014         struct intel_crtc *crtc;
11015         struct intel_dpll_hw_state dpll_hw_state;
11016         int i;
11017
11018         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11019                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11020                 int enabled_crtcs = 0, active_crtcs = 0;
11021                 bool active;
11022
11023                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11024
11025                 DRM_DEBUG_KMS("%s\n", pll->name);
11026
11027                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11028
11029                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11030                      "more active pll users than references: %i vs %i\n",
11031                      pll->active, hweight32(pll->config.crtc_mask));
11032                 I915_STATE_WARN(pll->active && !pll->on,
11033                      "pll in active use but not on in sw tracking\n");
11034                 I915_STATE_WARN(pll->on && !pll->active,
11035                      "pll in on but not on in use in sw tracking\n");
11036                 I915_STATE_WARN(pll->on != active,
11037                      "pll on state mismatch (expected %i, found %i)\n",
11038                      pll->on, active);
11039
11040                 for_each_intel_crtc(dev, crtc) {
11041                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11042                                 enabled_crtcs++;
11043                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11044                                 active_crtcs++;
11045                 }
11046                 I915_STATE_WARN(pll->active != active_crtcs,
11047                      "pll active crtcs mismatch (expected %i, found %i)\n",
11048                      pll->active, active_crtcs);
11049                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11050                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
11051                      hweight32(pll->config.crtc_mask), enabled_crtcs);
11052
11053                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11054                                        sizeof(dpll_hw_state)),
11055                      "pll hw state mismatch\n");
11056         }
11057 }
11058
11059 void
11060 intel_modeset_check_state(struct drm_device *dev)
11061 {
11062         check_wm_state(dev);
11063         check_connector_state(dev);
11064         check_encoder_state(dev);
11065         check_crtc_state(dev);
11066         check_shared_dpll_state(dev);
11067 }
11068
11069 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11070                                      int dotclock)
11071 {
11072         /*
11073          * FDI already provided one idea for the dotclock.
11074          * Yell if the encoder disagrees.
11075          */
11076         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11077              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11078              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11079 }
11080
11081 static void update_scanline_offset(struct intel_crtc *crtc)
11082 {
11083         struct drm_device *dev = crtc->base.dev;
11084
11085         /*
11086          * The scanline counter increments at the leading edge of hsync.
11087          *
11088          * On most platforms it starts counting from vtotal-1 on the
11089          * first active line. That means the scanline counter value is
11090          * always one less than what we would expect. Ie. just after
11091          * start of vblank, which also occurs at start of hsync (on the
11092          * last active line), the scanline counter will read vblank_start-1.
11093          *
11094          * On gen2 the scanline counter starts counting from 1 instead
11095          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11096          * to keep the value positive), instead of adding one.
11097          *
11098          * On HSW+ the behaviour of the scanline counter depends on the output
11099          * type. For DP ports it behaves like most other platforms, but on HDMI
11100          * there's an extra 1 line difference. So we need to add two instead of
11101          * one to the value.
11102          */
11103         if (IS_GEN2(dev)) {
11104                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11105                 int vtotal;
11106
11107                 vtotal = mode->crtc_vtotal;
11108                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11109                         vtotal /= 2;
11110
11111                 crtc->scanline_offset = vtotal - 1;
11112         } else if (HAS_DDI(dev) &&
11113                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11114                 crtc->scanline_offset = 2;
11115         } else
11116                 crtc->scanline_offset = 1;
11117 }
11118
11119 static struct intel_crtc_state *
11120 intel_modeset_compute_config(struct drm_crtc *crtc,
11121                              struct drm_display_mode *mode,
11122                              struct drm_framebuffer *fb,
11123                              unsigned *modeset_pipes,
11124                              unsigned *prepare_pipes,
11125                              unsigned *disable_pipes)
11126 {
11127         struct intel_crtc_state *pipe_config = NULL;
11128
11129         intel_modeset_affected_pipes(crtc, modeset_pipes,
11130                                      prepare_pipes, disable_pipes);
11131
11132         if ((*modeset_pipes) == 0)
11133                 goto out;
11134
11135         /*
11136          * Note this needs changes when we start tracking multiple modes
11137          * and crtcs.  At that point we'll need to compute the whole config
11138          * (i.e. one pipe_config for each crtc) rather than just the one
11139          * for this crtc.
11140          */
11141         pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11142         if (IS_ERR(pipe_config)) {
11143                 goto out;
11144         }
11145         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11146                                "[modeset]");
11147
11148 out:
11149         return pipe_config;
11150 }
11151
11152 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11153                                        unsigned modeset_pipes,
11154                                        unsigned disable_pipes)
11155 {
11156         struct drm_i915_private *dev_priv = to_i915(dev);
11157         unsigned clear_pipes = modeset_pipes | disable_pipes;
11158         struct intel_crtc *intel_crtc;
11159         int ret = 0;
11160
11161         if (!dev_priv->display.crtc_compute_clock)
11162                 return 0;
11163
11164         ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11165         if (ret)
11166                 goto done;
11167
11168         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11169                 struct intel_crtc_state *state = intel_crtc->new_config;
11170                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11171                                                            state);
11172                 if (ret) {
11173                         intel_shared_dpll_abort_config(dev_priv);
11174                         goto done;
11175                 }
11176         }
11177
11178 done:
11179         return ret;
11180 }
11181
11182 static int __intel_set_mode(struct drm_crtc *crtc,
11183                             struct drm_display_mode *mode,
11184                             int x, int y, struct drm_framebuffer *fb,
11185                             struct intel_crtc_state *pipe_config,
11186                             unsigned modeset_pipes,
11187                             unsigned prepare_pipes,
11188                             unsigned disable_pipes)
11189 {
11190         struct drm_device *dev = crtc->dev;
11191         struct drm_i915_private *dev_priv = dev->dev_private;
11192         struct drm_display_mode *saved_mode;
11193         struct intel_crtc *intel_crtc;
11194         int ret = 0;
11195
11196         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11197         if (!saved_mode)
11198                 return -ENOMEM;
11199
11200         *saved_mode = crtc->mode;
11201
11202         if (modeset_pipes)
11203                 to_intel_crtc(crtc)->new_config = pipe_config;
11204
11205         /*
11206          * See if the config requires any additional preparation, e.g.
11207          * to adjust global state with pipes off.  We need to do this
11208          * here so we can get the modeset_pipe updated config for the new
11209          * mode set on this crtc.  For other crtcs we need to use the
11210          * adjusted_mode bits in the crtc directly.
11211          */
11212         if (IS_VALLEYVIEW(dev)) {
11213                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11214
11215                 /* may have added more to prepare_pipes than we should */
11216                 prepare_pipes &= ~disable_pipes;
11217         }
11218
11219         ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11220         if (ret)
11221                 goto done;
11222
11223         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11224                 intel_crtc_disable(&intel_crtc->base);
11225
11226         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11227                 if (intel_crtc->base.state->enable)
11228                         dev_priv->display.crtc_disable(&intel_crtc->base);
11229         }
11230
11231         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11232          * to set it here already despite that we pass it down the callchain.
11233          *
11234          * Note we'll need to fix this up when we start tracking multiple
11235          * pipes; here we assume a single modeset_pipe and only track the
11236          * single crtc and mode.
11237          */
11238         if (modeset_pipes) {
11239                 crtc->mode = *mode;
11240                 /* mode_set/enable/disable functions rely on a correct pipe
11241                  * config. */
11242                 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11243
11244                 /*
11245                  * Calculate and store various constants which
11246                  * are later needed by vblank and swap-completion
11247                  * timestamping. They are derived from true hwmode.
11248                  */
11249                 drm_calc_timestamping_constants(crtc,
11250                                                 &pipe_config->base.adjusted_mode);
11251         }
11252
11253         /* Only after disabling all output pipelines that will be changed can we
11254          * update the the output configuration. */
11255         intel_modeset_update_state(dev, prepare_pipes);
11256
11257         modeset_update_crtc_power_domains(dev);
11258
11259         /* Set up the DPLL and any encoders state that needs to adjust or depend
11260          * on the DPLL.
11261          */
11262         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11263                 struct drm_plane *primary = intel_crtc->base.primary;
11264                 int vdisplay, hdisplay;
11265
11266                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11267                 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11268                                                    fb, 0, 0,
11269                                                    hdisplay, vdisplay,
11270                                                    x << 16, y << 16,
11271                                                    hdisplay << 16, vdisplay << 16);
11272         }
11273
11274         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11275         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11276                 update_scanline_offset(intel_crtc);
11277
11278                 dev_priv->display.crtc_enable(&intel_crtc->base);
11279         }
11280
11281         /* FIXME: add subpixel order */
11282 done:
11283         if (ret && crtc->state->enable)
11284                 crtc->mode = *saved_mode;
11285
11286         kfree(saved_mode);
11287         return ret;
11288 }
11289
11290 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11291                                 struct drm_display_mode *mode,
11292                                 int x, int y, struct drm_framebuffer *fb,
11293                                 struct intel_crtc_state *pipe_config,
11294                                 unsigned modeset_pipes,
11295                                 unsigned prepare_pipes,
11296                                 unsigned disable_pipes)
11297 {
11298         int ret;
11299
11300         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11301                                prepare_pipes, disable_pipes);
11302
11303         if (ret == 0)
11304                 intel_modeset_check_state(crtc->dev);
11305
11306         return ret;
11307 }
11308
11309 static int intel_set_mode(struct drm_crtc *crtc,
11310                           struct drm_display_mode *mode,
11311                           int x, int y, struct drm_framebuffer *fb)
11312 {
11313         struct intel_crtc_state *pipe_config;
11314         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11315
11316         pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11317                                                    &modeset_pipes,
11318                                                    &prepare_pipes,
11319                                                    &disable_pipes);
11320
11321         if (IS_ERR(pipe_config))
11322                 return PTR_ERR(pipe_config);
11323
11324         return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11325                                     modeset_pipes, prepare_pipes,
11326                                     disable_pipes);
11327 }
11328
11329 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11330 {
11331         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11332 }
11333
11334 #undef for_each_intel_crtc_masked
11335
11336 static void intel_set_config_free(struct intel_set_config *config)
11337 {
11338         if (!config)
11339                 return;
11340
11341         kfree(config->save_connector_encoders);
11342         kfree(config->save_encoder_crtcs);
11343         kfree(config->save_crtc_enabled);
11344         kfree(config);
11345 }
11346
11347 static int intel_set_config_save_state(struct drm_device *dev,
11348                                        struct intel_set_config *config)
11349 {
11350         struct drm_crtc *crtc;
11351         struct drm_encoder *encoder;
11352         struct drm_connector *connector;
11353         int count;
11354
11355         config->save_crtc_enabled =
11356                 kcalloc(dev->mode_config.num_crtc,
11357                         sizeof(bool), GFP_KERNEL);
11358         if (!config->save_crtc_enabled)
11359                 return -ENOMEM;
11360
11361         config->save_encoder_crtcs =
11362                 kcalloc(dev->mode_config.num_encoder,
11363                         sizeof(struct drm_crtc *), GFP_KERNEL);
11364         if (!config->save_encoder_crtcs)
11365                 return -ENOMEM;
11366
11367         config->save_connector_encoders =
11368                 kcalloc(dev->mode_config.num_connector,
11369                         sizeof(struct drm_encoder *), GFP_KERNEL);
11370         if (!config->save_connector_encoders)
11371                 return -ENOMEM;
11372
11373         /* Copy data. Note that driver private data is not affected.
11374          * Should anything bad happen only the expected state is
11375          * restored, not the drivers personal bookkeeping.
11376          */
11377         count = 0;
11378         for_each_crtc(dev, crtc) {
11379                 config->save_crtc_enabled[count++] = crtc->state->enable;
11380         }
11381
11382         count = 0;
11383         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11384                 config->save_encoder_crtcs[count++] = encoder->crtc;
11385         }
11386
11387         count = 0;
11388         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11389                 config->save_connector_encoders[count++] = connector->encoder;
11390         }
11391
11392         return 0;
11393 }
11394
11395 static void intel_set_config_restore_state(struct drm_device *dev,
11396                                            struct intel_set_config *config)
11397 {
11398         struct intel_crtc *crtc;
11399         struct intel_encoder *encoder;
11400         struct intel_connector *connector;
11401         int count;
11402
11403         count = 0;
11404         for_each_intel_crtc(dev, crtc) {
11405                 crtc->new_enabled = config->save_crtc_enabled[count++];
11406
11407                 if (crtc->new_enabled)
11408                         crtc->new_config = crtc->config;
11409                 else
11410                         crtc->new_config = NULL;
11411         }
11412
11413         count = 0;
11414         for_each_intel_encoder(dev, encoder) {
11415                 encoder->new_crtc =
11416                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11417         }
11418
11419         count = 0;
11420         for_each_intel_connector(dev, connector) {
11421                 connector->new_encoder =
11422                         to_intel_encoder(config->save_connector_encoders[count++]);
11423         }
11424 }
11425
11426 static bool
11427 is_crtc_connector_off(struct drm_mode_set *set)
11428 {
11429         int i;
11430
11431         if (set->num_connectors == 0)
11432                 return false;
11433
11434         if (WARN_ON(set->connectors == NULL))
11435                 return false;
11436
11437         for (i = 0; i < set->num_connectors; i++)
11438                 if (set->connectors[i]->encoder &&
11439                     set->connectors[i]->encoder->crtc == set->crtc &&
11440                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11441                         return true;
11442
11443         return false;
11444 }
11445
11446 static void
11447 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11448                                       struct intel_set_config *config)
11449 {
11450
11451         /* We should be able to check here if the fb has the same properties
11452          * and then just flip_or_move it */
11453         if (is_crtc_connector_off(set)) {
11454                 config->mode_changed = true;
11455         } else if (set->crtc->primary->fb != set->fb) {
11456                 /*
11457                  * If we have no fb, we can only flip as long as the crtc is
11458                  * active, otherwise we need a full mode set.  The crtc may
11459                  * be active if we've only disabled the primary plane, or
11460                  * in fastboot situations.
11461                  */
11462                 if (set->crtc->primary->fb == NULL) {
11463                         struct intel_crtc *intel_crtc =
11464                                 to_intel_crtc(set->crtc);
11465
11466                         if (intel_crtc->active) {
11467                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11468                                 config->fb_changed = true;
11469                         } else {
11470                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11471                                 config->mode_changed = true;
11472                         }
11473                 } else if (set->fb == NULL) {
11474                         config->mode_changed = true;
11475                 } else if (set->fb->pixel_format !=
11476                            set->crtc->primary->fb->pixel_format) {
11477                         config->mode_changed = true;
11478                 } else {
11479                         config->fb_changed = true;
11480                 }
11481         }
11482
11483         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11484                 config->fb_changed = true;
11485
11486         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11487                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11488                 drm_mode_debug_printmodeline(&set->crtc->mode);
11489                 drm_mode_debug_printmodeline(set->mode);
11490                 config->mode_changed = true;
11491         }
11492
11493         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11494                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11495 }
11496
11497 static int
11498 intel_modeset_stage_output_state(struct drm_device *dev,
11499                                  struct drm_mode_set *set,
11500                                  struct intel_set_config *config)
11501 {
11502         struct intel_connector *connector;
11503         struct intel_encoder *encoder;
11504         struct intel_crtc *crtc;
11505         int ro;
11506
11507         /* The upper layers ensure that we either disable a crtc or have a list
11508          * of connectors. For paranoia, double-check this. */
11509         WARN_ON(!set->fb && (set->num_connectors != 0));
11510         WARN_ON(set->fb && (set->num_connectors == 0));
11511
11512         for_each_intel_connector(dev, connector) {
11513                 /* Otherwise traverse passed in connector list and get encoders
11514                  * for them. */
11515                 for (ro = 0; ro < set->num_connectors; ro++) {
11516                         if (set->connectors[ro] == &connector->base) {
11517                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11518                                 break;
11519                         }
11520                 }
11521
11522                 /* If we disable the crtc, disable all its connectors. Also, if
11523                  * the connector is on the changing crtc but not on the new
11524                  * connector list, disable it. */
11525                 if ((!set->fb || ro == set->num_connectors) &&
11526                     connector->base.encoder &&
11527                     connector->base.encoder->crtc == set->crtc) {
11528                         connector->new_encoder = NULL;
11529
11530                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11531                                 connector->base.base.id,
11532                                 connector->base.name);
11533                 }
11534
11535
11536                 if (&connector->new_encoder->base != connector->base.encoder) {
11537                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11538                                       connector->base.base.id,
11539                                       connector->base.name);
11540                         config->mode_changed = true;
11541                 }
11542         }
11543         /* connector->new_encoder is now updated for all connectors. */
11544
11545         /* Update crtc of enabled connectors. */
11546         for_each_intel_connector(dev, connector) {
11547                 struct drm_crtc *new_crtc;
11548
11549                 if (!connector->new_encoder)
11550                         continue;
11551
11552                 new_crtc = connector->new_encoder->base.crtc;
11553
11554                 for (ro = 0; ro < set->num_connectors; ro++) {
11555                         if (set->connectors[ro] == &connector->base)
11556                                 new_crtc = set->crtc;
11557                 }
11558
11559                 /* Make sure the new CRTC will work with the encoder */
11560                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11561                                          new_crtc)) {
11562                         return -EINVAL;
11563                 }
11564                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11565
11566                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11567                         connector->base.base.id,
11568                         connector->base.name,
11569                         new_crtc->base.id);
11570         }
11571
11572         /* Check for any encoders that needs to be disabled. */
11573         for_each_intel_encoder(dev, encoder) {
11574                 int num_connectors = 0;
11575                 for_each_intel_connector(dev, connector) {
11576                         if (connector->new_encoder == encoder) {
11577                                 WARN_ON(!connector->new_encoder->new_crtc);
11578                                 num_connectors++;
11579                         }
11580                 }
11581
11582                 if (num_connectors == 0)
11583                         encoder->new_crtc = NULL;
11584                 else if (num_connectors > 1)
11585                         return -EINVAL;
11586
11587                 /* Only now check for crtc changes so we don't miss encoders
11588                  * that will be disabled. */
11589                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11590                         DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11591                                       encoder->base.base.id,
11592                                       encoder->base.name);
11593                         config->mode_changed = true;
11594                 }
11595         }
11596         /* Now we've also updated encoder->new_crtc for all encoders. */
11597         for_each_intel_connector(dev, connector) {
11598                 if (connector->new_encoder)
11599                         if (connector->new_encoder != connector->encoder)
11600                                 connector->encoder = connector->new_encoder;
11601         }
11602         for_each_intel_crtc(dev, crtc) {
11603                 crtc->new_enabled = false;
11604
11605                 for_each_intel_encoder(dev, encoder) {
11606                         if (encoder->new_crtc == crtc) {
11607                                 crtc->new_enabled = true;
11608                                 break;
11609                         }
11610                 }
11611
11612                 if (crtc->new_enabled != crtc->base.state->enable) {
11613                         DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11614                                       crtc->base.base.id,
11615                                       crtc->new_enabled ? "en" : "dis");
11616                         config->mode_changed = true;
11617                 }
11618
11619                 if (crtc->new_enabled)
11620                         crtc->new_config = crtc->config;
11621                 else
11622                         crtc->new_config = NULL;
11623         }
11624
11625         return 0;
11626 }
11627
11628 static void disable_crtc_nofb(struct intel_crtc *crtc)
11629 {
11630         struct drm_device *dev = crtc->base.dev;
11631         struct intel_encoder *encoder;
11632         struct intel_connector *connector;
11633
11634         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11635                       pipe_name(crtc->pipe));
11636
11637         for_each_intel_connector(dev, connector) {
11638                 if (connector->new_encoder &&
11639                     connector->new_encoder->new_crtc == crtc)
11640                         connector->new_encoder = NULL;
11641         }
11642
11643         for_each_intel_encoder(dev, encoder) {
11644                 if (encoder->new_crtc == crtc)
11645                         encoder->new_crtc = NULL;
11646         }
11647
11648         crtc->new_enabled = false;
11649         crtc->new_config = NULL;
11650 }
11651
11652 static int intel_crtc_set_config(struct drm_mode_set *set)
11653 {
11654         struct drm_device *dev;
11655         struct drm_mode_set save_set;
11656         struct intel_set_config *config;
11657         struct intel_crtc_state *pipe_config;
11658         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11659         int ret;
11660
11661         BUG_ON(!set);
11662         BUG_ON(!set->crtc);
11663         BUG_ON(!set->crtc->helper_private);
11664
11665         /* Enforce sane interface api - has been abused by the fb helper. */
11666         BUG_ON(!set->mode && set->fb);
11667         BUG_ON(set->fb && set->num_connectors == 0);
11668
11669         if (set->fb) {
11670                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11671                                 set->crtc->base.id, set->fb->base.id,
11672                                 (int)set->num_connectors, set->x, set->y);
11673         } else {
11674                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11675         }
11676
11677         dev = set->crtc->dev;
11678
11679         ret = -ENOMEM;
11680         config = kzalloc(sizeof(*config), GFP_KERNEL);
11681         if (!config)
11682                 goto out_config;
11683
11684         ret = intel_set_config_save_state(dev, config);
11685         if (ret)
11686                 goto out_config;
11687
11688         save_set.crtc = set->crtc;
11689         save_set.mode = &set->crtc->mode;
11690         save_set.x = set->crtc->x;
11691         save_set.y = set->crtc->y;
11692         save_set.fb = set->crtc->primary->fb;
11693
11694         /* Compute whether we need a full modeset, only an fb base update or no
11695          * change at all. In the future we might also check whether only the
11696          * mode changed, e.g. for LVDS where we only change the panel fitter in
11697          * such cases. */
11698         intel_set_config_compute_mode_changes(set, config);
11699
11700         ret = intel_modeset_stage_output_state(dev, set, config);
11701         if (ret)
11702                 goto fail;
11703
11704         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11705                                                    set->fb,
11706                                                    &modeset_pipes,
11707                                                    &prepare_pipes,
11708                                                    &disable_pipes);
11709         if (IS_ERR(pipe_config)) {
11710                 ret = PTR_ERR(pipe_config);
11711                 goto fail;
11712         } else if (pipe_config) {
11713                 if (pipe_config->has_audio !=
11714                     to_intel_crtc(set->crtc)->config->has_audio)
11715                         config->mode_changed = true;
11716
11717                 /*
11718                  * Note we have an issue here with infoframes: current code
11719                  * only updates them on the full mode set path per hw
11720                  * requirements.  So here we should be checking for any
11721                  * required changes and forcing a mode set.
11722                  */
11723         }
11724
11725         /* set_mode will free it in the mode_changed case */
11726         if (!config->mode_changed)
11727                 kfree(pipe_config);
11728
11729         intel_update_pipe_size(to_intel_crtc(set->crtc));
11730
11731         if (config->mode_changed) {
11732                 ret = intel_set_mode_pipes(set->crtc, set->mode,
11733                                            set->x, set->y, set->fb, pipe_config,
11734                                            modeset_pipes, prepare_pipes,
11735                                            disable_pipes);
11736         } else if (config->fb_changed) {
11737                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11738                 struct drm_plane *primary = set->crtc->primary;
11739                 int vdisplay, hdisplay;
11740
11741                 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11742                 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11743                                                    0, 0, hdisplay, vdisplay,
11744                                                    set->x << 16, set->y << 16,
11745                                                    hdisplay << 16, vdisplay << 16);
11746
11747                 /*
11748                  * We need to make sure the primary plane is re-enabled if it
11749                  * has previously been turned off.
11750                  */
11751                 if (!intel_crtc->primary_enabled && ret == 0) {
11752                         WARN_ON(!intel_crtc->active);
11753                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11754                 }
11755
11756                 /*
11757                  * In the fastboot case this may be our only check of the
11758                  * state after boot.  It would be better to only do it on
11759                  * the first update, but we don't have a nice way of doing that
11760                  * (and really, set_config isn't used much for high freq page
11761                  * flipping, so increasing its cost here shouldn't be a big
11762                  * deal).
11763                  */
11764                 if (i915.fastboot && ret == 0)
11765                         intel_modeset_check_state(set->crtc->dev);
11766         }
11767
11768         if (ret) {
11769                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11770                               set->crtc->base.id, ret);
11771 fail:
11772                 intel_set_config_restore_state(dev, config);
11773
11774                 /*
11775                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11776                  * force the pipe off to avoid oopsing in the modeset code
11777                  * due to fb==NULL. This should only happen during boot since
11778                  * we don't yet reconstruct the FB from the hardware state.
11779                  */
11780                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11781                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11782
11783                 /* Try to restore the config */
11784                 if (config->mode_changed &&
11785                     intel_set_mode(save_set.crtc, save_set.mode,
11786                                    save_set.x, save_set.y, save_set.fb))
11787                         DRM_ERROR("failed to restore config after modeset failure\n");
11788         }
11789
11790 out_config:
11791         intel_set_config_free(config);
11792         return ret;
11793 }
11794
11795 static const struct drm_crtc_funcs intel_crtc_funcs = {
11796         .gamma_set = intel_crtc_gamma_set,
11797         .set_config = intel_crtc_set_config,
11798         .destroy = intel_crtc_destroy,
11799         .page_flip = intel_crtc_page_flip,
11800         .atomic_duplicate_state = intel_crtc_duplicate_state,
11801         .atomic_destroy_state = intel_crtc_destroy_state,
11802 };
11803
11804 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11805                                       struct intel_shared_dpll *pll,
11806                                       struct intel_dpll_hw_state *hw_state)
11807 {
11808         uint32_t val;
11809
11810         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11811                 return false;
11812
11813         val = I915_READ(PCH_DPLL(pll->id));
11814         hw_state->dpll = val;
11815         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11816         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11817
11818         return val & DPLL_VCO_ENABLE;
11819 }
11820
11821 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11822                                   struct intel_shared_dpll *pll)
11823 {
11824         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11825         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11826 }
11827
11828 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11829                                 struct intel_shared_dpll *pll)
11830 {
11831         /* PCH refclock must be enabled first */
11832         ibx_assert_pch_refclk_enabled(dev_priv);
11833
11834         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11835
11836         /* Wait for the clocks to stabilize. */
11837         POSTING_READ(PCH_DPLL(pll->id));
11838         udelay(150);
11839
11840         /* The pixel multiplier can only be updated once the
11841          * DPLL is enabled and the clocks are stable.
11842          *
11843          * So write it again.
11844          */
11845         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11846         POSTING_READ(PCH_DPLL(pll->id));
11847         udelay(200);
11848 }
11849
11850 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11851                                  struct intel_shared_dpll *pll)
11852 {
11853         struct drm_device *dev = dev_priv->dev;
11854         struct intel_crtc *crtc;
11855
11856         /* Make sure no transcoder isn't still depending on us. */
11857         for_each_intel_crtc(dev, crtc) {
11858                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11859                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11860         }
11861
11862         I915_WRITE(PCH_DPLL(pll->id), 0);
11863         POSTING_READ(PCH_DPLL(pll->id));
11864         udelay(200);
11865 }
11866
11867 static char *ibx_pch_dpll_names[] = {
11868         "PCH DPLL A",
11869         "PCH DPLL B",
11870 };
11871
11872 static void ibx_pch_dpll_init(struct drm_device *dev)
11873 {
11874         struct drm_i915_private *dev_priv = dev->dev_private;
11875         int i;
11876
11877         dev_priv->num_shared_dpll = 2;
11878
11879         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11880                 dev_priv->shared_dplls[i].id = i;
11881                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11882                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11883                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11884                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11885                 dev_priv->shared_dplls[i].get_hw_state =
11886                         ibx_pch_dpll_get_hw_state;
11887         }
11888 }
11889
11890 static void intel_shared_dpll_init(struct drm_device *dev)
11891 {
11892         struct drm_i915_private *dev_priv = dev->dev_private;
11893
11894         if (HAS_DDI(dev))
11895                 intel_ddi_pll_init(dev);
11896         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11897                 ibx_pch_dpll_init(dev);
11898         else
11899                 dev_priv->num_shared_dpll = 0;
11900
11901         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11902 }
11903
11904 /**
11905  * intel_prepare_plane_fb - Prepare fb for usage on plane
11906  * @plane: drm plane to prepare for
11907  * @fb: framebuffer to prepare for presentation
11908  *
11909  * Prepares a framebuffer for usage on a display plane.  Generally this
11910  * involves pinning the underlying object and updating the frontbuffer tracking
11911  * bits.  Some older platforms need special physical address handling for
11912  * cursor planes.
11913  *
11914  * Returns 0 on success, negative error code on failure.
11915  */
11916 int
11917 intel_prepare_plane_fb(struct drm_plane *plane,
11918                        struct drm_framebuffer *fb,
11919                        const struct drm_plane_state *new_state)
11920 {
11921         struct drm_device *dev = plane->dev;
11922         struct intel_plane *intel_plane = to_intel_plane(plane);
11923         enum pipe pipe = intel_plane->pipe;
11924         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11925         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11926         unsigned frontbuffer_bits = 0;
11927         int ret = 0;
11928
11929         if (!obj)
11930                 return 0;
11931
11932         switch (plane->type) {
11933         case DRM_PLANE_TYPE_PRIMARY:
11934                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11935                 break;
11936         case DRM_PLANE_TYPE_CURSOR:
11937                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11938                 break;
11939         case DRM_PLANE_TYPE_OVERLAY:
11940                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11941                 break;
11942         }
11943
11944         mutex_lock(&dev->struct_mutex);
11945
11946         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11947             INTEL_INFO(dev)->cursor_needs_physical) {
11948                 int align = IS_I830(dev) ? 16 * 1024 : 256;
11949                 ret = i915_gem_object_attach_phys(obj, align);
11950                 if (ret)
11951                         DRM_DEBUG_KMS("failed to attach phys object\n");
11952         } else {
11953                 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11954         }
11955
11956         if (ret == 0)
11957                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11958
11959         mutex_unlock(&dev->struct_mutex);
11960
11961         return ret;
11962 }
11963
11964 /**
11965  * intel_cleanup_plane_fb - Cleans up an fb after plane use
11966  * @plane: drm plane to clean up for
11967  * @fb: old framebuffer that was on plane
11968  *
11969  * Cleans up a framebuffer that has just been removed from a plane.
11970  */
11971 void
11972 intel_cleanup_plane_fb(struct drm_plane *plane,
11973                        struct drm_framebuffer *fb,
11974                        const struct drm_plane_state *old_state)
11975 {
11976         struct drm_device *dev = plane->dev;
11977         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11978
11979         if (WARN_ON(!obj))
11980                 return;
11981
11982         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11983             !INTEL_INFO(dev)->cursor_needs_physical) {
11984                 mutex_lock(&dev->struct_mutex);
11985                 intel_unpin_fb_obj(obj);
11986                 mutex_unlock(&dev->struct_mutex);
11987         }
11988 }
11989
11990 static int
11991 intel_check_primary_plane(struct drm_plane *plane,
11992                           struct intel_plane_state *state)
11993 {
11994         struct drm_device *dev = plane->dev;
11995         struct drm_i915_private *dev_priv = dev->dev_private;
11996         struct drm_crtc *crtc = state->base.crtc;
11997         struct intel_crtc *intel_crtc;
11998         struct drm_framebuffer *fb = state->base.fb;
11999         struct drm_rect *dest = &state->dst;
12000         struct drm_rect *src = &state->src;
12001         const struct drm_rect *clip = &state->clip;
12002         int ret;
12003
12004         crtc = crtc ? crtc : plane->crtc;
12005         intel_crtc = to_intel_crtc(crtc);
12006
12007         ret = drm_plane_helper_check_update(plane, crtc, fb,
12008                                             src, dest, clip,
12009                                             DRM_PLANE_HELPER_NO_SCALING,
12010                                             DRM_PLANE_HELPER_NO_SCALING,
12011                                             false, true, &state->visible);
12012         if (ret)
12013                 return ret;
12014
12015         if (intel_crtc->active) {
12016                 intel_crtc->atomic.wait_for_flips = true;
12017
12018                 /*
12019                  * FBC does not work on some platforms for rotated
12020                  * planes, so disable it when rotation is not 0 and
12021                  * update it when rotation is set back to 0.
12022                  *
12023                  * FIXME: This is redundant with the fbc update done in
12024                  * the primary plane enable function except that that
12025                  * one is done too late. We eventually need to unify
12026                  * this.
12027                  */
12028                 if (intel_crtc->primary_enabled &&
12029                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12030                     dev_priv->fbc.crtc == intel_crtc &&
12031                     state->base.rotation != BIT(DRM_ROTATE_0)) {
12032                         intel_crtc->atomic.disable_fbc = true;
12033                 }
12034
12035                 if (state->visible) {
12036                         /*
12037                          * BDW signals flip done immediately if the plane
12038                          * is disabled, even if the plane enable is already
12039                          * armed to occur at the next vblank :(
12040                          */
12041                         if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12042                                 intel_crtc->atomic.wait_vblank = true;
12043                 }
12044
12045                 intel_crtc->atomic.fb_bits |=
12046                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12047
12048                 intel_crtc->atomic.update_fbc = true;
12049
12050                 /* Update watermarks on tiling changes. */
12051                 if (!plane->state->fb || !state->base.fb ||
12052                     plane->state->fb->modifier[0] !=
12053                     state->base.fb->modifier[0])
12054                         intel_crtc->atomic.update_wm = true;
12055         }
12056
12057         return 0;
12058 }
12059
12060 static void
12061 intel_commit_primary_plane(struct drm_plane *plane,
12062                            struct intel_plane_state *state)
12063 {
12064         struct drm_crtc *crtc = state->base.crtc;
12065         struct drm_framebuffer *fb = state->base.fb;
12066         struct drm_device *dev = plane->dev;
12067         struct drm_i915_private *dev_priv = dev->dev_private;
12068         struct intel_crtc *intel_crtc;
12069         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12070         struct intel_plane *intel_plane = to_intel_plane(plane);
12071         struct drm_rect *src = &state->src;
12072
12073         crtc = crtc ? crtc : plane->crtc;
12074         intel_crtc = to_intel_crtc(crtc);
12075
12076         plane->fb = fb;
12077         crtc->x = src->x1 >> 16;
12078         crtc->y = src->y1 >> 16;
12079
12080         intel_plane->obj = obj;
12081
12082         if (intel_crtc->active) {
12083                 if (state->visible) {
12084                         /* FIXME: kill this fastboot hack */
12085                         intel_update_pipe_size(intel_crtc);
12086
12087                         intel_crtc->primary_enabled = true;
12088
12089                         dev_priv->display.update_primary_plane(crtc, plane->fb,
12090                                         crtc->x, crtc->y);
12091                 } else {
12092                         /*
12093                          * If clipping results in a non-visible primary plane,
12094                          * we'll disable the primary plane.  Note that this is
12095                          * a bit different than what happens if userspace
12096                          * explicitly disables the plane by passing fb=0
12097                          * because plane->fb still gets set and pinned.
12098                          */
12099                         intel_disable_primary_hw_plane(plane, crtc);
12100                 }
12101         }
12102 }
12103
12104 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12105 {
12106         struct drm_device *dev = crtc->dev;
12107         struct drm_i915_private *dev_priv = dev->dev_private;
12108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12109         struct intel_plane *intel_plane;
12110         struct drm_plane *p;
12111         unsigned fb_bits = 0;
12112
12113         /* Track fb's for any planes being disabled */
12114         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12115                 intel_plane = to_intel_plane(p);
12116
12117                 if (intel_crtc->atomic.disabled_planes &
12118                     (1 << drm_plane_index(p))) {
12119                         switch (p->type) {
12120                         case DRM_PLANE_TYPE_PRIMARY:
12121                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12122                                 break;
12123                         case DRM_PLANE_TYPE_CURSOR:
12124                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12125                                 break;
12126                         case DRM_PLANE_TYPE_OVERLAY:
12127                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12128                                 break;
12129                         }
12130
12131                         mutex_lock(&dev->struct_mutex);
12132                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12133                         mutex_unlock(&dev->struct_mutex);
12134                 }
12135         }
12136
12137         if (intel_crtc->atomic.wait_for_flips)
12138                 intel_crtc_wait_for_pending_flips(crtc);
12139
12140         if (intel_crtc->atomic.disable_fbc)
12141                 intel_fbc_disable(dev);
12142
12143         if (intel_crtc->atomic.pre_disable_primary)
12144                 intel_pre_disable_primary(crtc);
12145
12146         if (intel_crtc->atomic.update_wm)
12147                 intel_update_watermarks(crtc);
12148
12149         intel_runtime_pm_get(dev_priv);
12150
12151         /* Perform vblank evasion around commit operation */
12152         if (intel_crtc->active)
12153                 intel_crtc->atomic.evade =
12154                         intel_pipe_update_start(intel_crtc,
12155                                                 &intel_crtc->atomic.start_vbl_count);
12156 }
12157
12158 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12159 {
12160         struct drm_device *dev = crtc->dev;
12161         struct drm_i915_private *dev_priv = dev->dev_private;
12162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12163         struct drm_plane *p;
12164
12165         if (intel_crtc->atomic.evade)
12166                 intel_pipe_update_end(intel_crtc,
12167                                       intel_crtc->atomic.start_vbl_count);
12168
12169         intel_runtime_pm_put(dev_priv);
12170
12171         if (intel_crtc->atomic.wait_vblank)
12172                 intel_wait_for_vblank(dev, intel_crtc->pipe);
12173
12174         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12175
12176         if (intel_crtc->atomic.update_fbc) {
12177                 mutex_lock(&dev->struct_mutex);
12178                 intel_fbc_update(dev);
12179                 mutex_unlock(&dev->struct_mutex);
12180         }
12181
12182         if (intel_crtc->atomic.post_enable_primary)
12183                 intel_post_enable_primary(crtc);
12184
12185         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12186                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12187                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12188                                                        false, false);
12189
12190         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12191 }
12192
12193 /**
12194  * intel_plane_destroy - destroy a plane
12195  * @plane: plane to destroy
12196  *
12197  * Common destruction function for all types of planes (primary, cursor,
12198  * sprite).
12199  */
12200 void intel_plane_destroy(struct drm_plane *plane)
12201 {
12202         struct intel_plane *intel_plane = to_intel_plane(plane);
12203         drm_plane_cleanup(plane);
12204         kfree(intel_plane);
12205 }
12206
12207 const struct drm_plane_funcs intel_plane_funcs = {
12208         .update_plane = drm_plane_helper_update,
12209         .disable_plane = drm_plane_helper_disable,
12210         .destroy = intel_plane_destroy,
12211         .set_property = drm_atomic_helper_plane_set_property,
12212         .atomic_get_property = intel_plane_atomic_get_property,
12213         .atomic_set_property = intel_plane_atomic_set_property,
12214         .atomic_duplicate_state = intel_plane_duplicate_state,
12215         .atomic_destroy_state = intel_plane_destroy_state,
12216
12217 };
12218
12219 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12220                                                     int pipe)
12221 {
12222         struct intel_plane *primary;
12223         struct intel_plane_state *state;
12224         const uint32_t *intel_primary_formats;
12225         int num_formats;
12226
12227         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12228         if (primary == NULL)
12229                 return NULL;
12230
12231         state = intel_create_plane_state(&primary->base);
12232         if (!state) {
12233                 kfree(primary);
12234                 return NULL;
12235         }
12236         primary->base.state = &state->base;
12237
12238         primary->can_scale = false;
12239         primary->max_downscale = 1;
12240         primary->pipe = pipe;
12241         primary->plane = pipe;
12242         primary->check_plane = intel_check_primary_plane;
12243         primary->commit_plane = intel_commit_primary_plane;
12244         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12245                 primary->plane = !pipe;
12246
12247         if (INTEL_INFO(dev)->gen <= 3) {
12248                 intel_primary_formats = intel_primary_formats_gen2;
12249                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12250         } else {
12251                 intel_primary_formats = intel_primary_formats_gen4;
12252                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12253         }
12254
12255         drm_universal_plane_init(dev, &primary->base, 0,
12256                                  &intel_plane_funcs,
12257                                  intel_primary_formats, num_formats,
12258                                  DRM_PLANE_TYPE_PRIMARY);
12259
12260         if (INTEL_INFO(dev)->gen >= 4) {
12261                 if (!dev->mode_config.rotation_property)
12262                         dev->mode_config.rotation_property =
12263                                 drm_mode_create_rotation_property(dev,
12264                                                         BIT(DRM_ROTATE_0) |
12265                                                         BIT(DRM_ROTATE_180));
12266                 if (dev->mode_config.rotation_property)
12267                         drm_object_attach_property(&primary->base.base,
12268                                 dev->mode_config.rotation_property,
12269                                 state->base.rotation);
12270         }
12271
12272         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12273
12274         return &primary->base;
12275 }
12276
12277 static int
12278 intel_check_cursor_plane(struct drm_plane *plane,
12279                          struct intel_plane_state *state)
12280 {
12281         struct drm_crtc *crtc = state->base.crtc;
12282         struct drm_device *dev = plane->dev;
12283         struct drm_framebuffer *fb = state->base.fb;
12284         struct drm_rect *dest = &state->dst;
12285         struct drm_rect *src = &state->src;
12286         const struct drm_rect *clip = &state->clip;
12287         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12288         struct intel_crtc *intel_crtc;
12289         unsigned stride;
12290         int ret;
12291
12292         crtc = crtc ? crtc : plane->crtc;
12293         intel_crtc = to_intel_crtc(crtc);
12294
12295         ret = drm_plane_helper_check_update(plane, crtc, fb,
12296                                             src, dest, clip,
12297                                             DRM_PLANE_HELPER_NO_SCALING,
12298                                             DRM_PLANE_HELPER_NO_SCALING,
12299                                             true, true, &state->visible);
12300         if (ret)
12301                 return ret;
12302
12303
12304         /* if we want to turn off the cursor ignore width and height */
12305         if (!obj)
12306                 goto finish;
12307
12308         /* Check for which cursor types we support */
12309         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12310                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12311                           state->base.crtc_w, state->base.crtc_h);
12312                 return -EINVAL;
12313         }
12314
12315         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12316         if (obj->base.size < stride * state->base.crtc_h) {
12317                 DRM_DEBUG_KMS("buffer is too small\n");
12318                 return -ENOMEM;
12319         }
12320
12321         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12322                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12323                 ret = -EINVAL;
12324         }
12325
12326 finish:
12327         if (intel_crtc->active) {
12328                 if (intel_crtc->base.cursor->state->crtc_w != state->base.crtc_w)
12329                         intel_crtc->atomic.update_wm = true;
12330
12331                 intel_crtc->atomic.fb_bits |=
12332                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12333         }
12334
12335         return ret;
12336 }
12337
12338 static void
12339 intel_commit_cursor_plane(struct drm_plane *plane,
12340                           struct intel_plane_state *state)
12341 {
12342         struct drm_crtc *crtc = state->base.crtc;
12343         struct drm_device *dev = plane->dev;
12344         struct intel_crtc *intel_crtc;
12345         struct intel_plane *intel_plane = to_intel_plane(plane);
12346         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12347         uint32_t addr;
12348
12349         crtc = crtc ? crtc : plane->crtc;
12350         intel_crtc = to_intel_crtc(crtc);
12351
12352         plane->fb = state->base.fb;
12353         crtc->cursor_x = state->base.crtc_x;
12354         crtc->cursor_y = state->base.crtc_y;
12355
12356         intel_plane->obj = obj;
12357
12358         if (intel_crtc->cursor_bo == obj)
12359                 goto update;
12360
12361         if (!obj)
12362                 addr = 0;
12363         else if (!INTEL_INFO(dev)->cursor_needs_physical)
12364                 addr = i915_gem_obj_ggtt_offset(obj);
12365         else
12366                 addr = obj->phys_handle->busaddr;
12367
12368         intel_crtc->cursor_addr = addr;
12369         intel_crtc->cursor_bo = obj;
12370 update:
12371
12372         if (intel_crtc->active)
12373                 intel_crtc_update_cursor(crtc, state->visible);
12374 }
12375
12376 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12377                                                    int pipe)
12378 {
12379         struct intel_plane *cursor;
12380         struct intel_plane_state *state;
12381
12382         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12383         if (cursor == NULL)
12384                 return NULL;
12385
12386         state = intel_create_plane_state(&cursor->base);
12387         if (!state) {
12388                 kfree(cursor);
12389                 return NULL;
12390         }
12391         cursor->base.state = &state->base;
12392
12393         cursor->can_scale = false;
12394         cursor->max_downscale = 1;
12395         cursor->pipe = pipe;
12396         cursor->plane = pipe;
12397         cursor->check_plane = intel_check_cursor_plane;
12398         cursor->commit_plane = intel_commit_cursor_plane;
12399
12400         drm_universal_plane_init(dev, &cursor->base, 0,
12401                                  &intel_plane_funcs,
12402                                  intel_cursor_formats,
12403                                  ARRAY_SIZE(intel_cursor_formats),
12404                                  DRM_PLANE_TYPE_CURSOR);
12405
12406         if (INTEL_INFO(dev)->gen >= 4) {
12407                 if (!dev->mode_config.rotation_property)
12408                         dev->mode_config.rotation_property =
12409                                 drm_mode_create_rotation_property(dev,
12410                                                         BIT(DRM_ROTATE_0) |
12411                                                         BIT(DRM_ROTATE_180));
12412                 if (dev->mode_config.rotation_property)
12413                         drm_object_attach_property(&cursor->base.base,
12414                                 dev->mode_config.rotation_property,
12415                                 state->base.rotation);
12416         }
12417
12418         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12419
12420         return &cursor->base;
12421 }
12422
12423 static void intel_crtc_init(struct drm_device *dev, int pipe)
12424 {
12425         struct drm_i915_private *dev_priv = dev->dev_private;
12426         struct intel_crtc *intel_crtc;
12427         struct intel_crtc_state *crtc_state = NULL;
12428         struct drm_plane *primary = NULL;
12429         struct drm_plane *cursor = NULL;
12430         int i, ret;
12431
12432         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12433         if (intel_crtc == NULL)
12434                 return;
12435
12436         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12437         if (!crtc_state)
12438                 goto fail;
12439         intel_crtc_set_state(intel_crtc, crtc_state);
12440         crtc_state->base.crtc = &intel_crtc->base;
12441
12442         primary = intel_primary_plane_create(dev, pipe);
12443         if (!primary)
12444                 goto fail;
12445
12446         cursor = intel_cursor_plane_create(dev, pipe);
12447         if (!cursor)
12448                 goto fail;
12449
12450         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12451                                         cursor, &intel_crtc_funcs);
12452         if (ret)
12453                 goto fail;
12454
12455         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12456         for (i = 0; i < 256; i++) {
12457                 intel_crtc->lut_r[i] = i;
12458                 intel_crtc->lut_g[i] = i;
12459                 intel_crtc->lut_b[i] = i;
12460         }
12461
12462         /*
12463          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12464          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12465          */
12466         intel_crtc->pipe = pipe;
12467         intel_crtc->plane = pipe;
12468         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12469                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12470                 intel_crtc->plane = !pipe;
12471         }
12472
12473         intel_crtc->cursor_base = ~0;
12474         intel_crtc->cursor_cntl = ~0;
12475         intel_crtc->cursor_size = ~0;
12476
12477         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12478                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12479         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12480         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12481
12482         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12483
12484         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12485
12486         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12487         return;
12488
12489 fail:
12490         if (primary)
12491                 drm_plane_cleanup(primary);
12492         if (cursor)
12493                 drm_plane_cleanup(cursor);
12494         kfree(crtc_state);
12495         kfree(intel_crtc);
12496 }
12497
12498 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12499 {
12500         struct drm_encoder *encoder = connector->base.encoder;
12501         struct drm_device *dev = connector->base.dev;
12502
12503         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12504
12505         if (!encoder || WARN_ON(!encoder->crtc))
12506                 return INVALID_PIPE;
12507
12508         return to_intel_crtc(encoder->crtc)->pipe;
12509 }
12510
12511 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12512                                 struct drm_file *file)
12513 {
12514         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12515         struct drm_crtc *drmmode_crtc;
12516         struct intel_crtc *crtc;
12517
12518         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12519
12520         if (!drmmode_crtc) {
12521                 DRM_ERROR("no such CRTC id\n");
12522                 return -ENOENT;
12523         }
12524
12525         crtc = to_intel_crtc(drmmode_crtc);
12526         pipe_from_crtc_id->pipe = crtc->pipe;
12527
12528         return 0;
12529 }
12530
12531 static int intel_encoder_clones(struct intel_encoder *encoder)
12532 {
12533         struct drm_device *dev = encoder->base.dev;
12534         struct intel_encoder *source_encoder;
12535         int index_mask = 0;
12536         int entry = 0;
12537
12538         for_each_intel_encoder(dev, source_encoder) {
12539                 if (encoders_cloneable(encoder, source_encoder))
12540                         index_mask |= (1 << entry);
12541
12542                 entry++;
12543         }
12544
12545         return index_mask;
12546 }
12547
12548 static bool has_edp_a(struct drm_device *dev)
12549 {
12550         struct drm_i915_private *dev_priv = dev->dev_private;
12551
12552         if (!IS_MOBILE(dev))
12553                 return false;
12554
12555         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12556                 return false;
12557
12558         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12559                 return false;
12560
12561         return true;
12562 }
12563
12564 static bool intel_crt_present(struct drm_device *dev)
12565 {
12566         struct drm_i915_private *dev_priv = dev->dev_private;
12567
12568         if (INTEL_INFO(dev)->gen >= 9)
12569                 return false;
12570
12571         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12572                 return false;
12573
12574         if (IS_CHERRYVIEW(dev))
12575                 return false;
12576
12577         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12578                 return false;
12579
12580         return true;
12581 }
12582
12583 static void intel_setup_outputs(struct drm_device *dev)
12584 {
12585         struct drm_i915_private *dev_priv = dev->dev_private;
12586         struct intel_encoder *encoder;
12587         struct drm_connector *connector;
12588         bool dpd_is_edp = false;
12589
12590         intel_lvds_init(dev);
12591
12592         if (intel_crt_present(dev))
12593                 intel_crt_init(dev);
12594
12595         if (HAS_DDI(dev)) {
12596                 int found;
12597
12598                 /*
12599                  * Haswell uses DDI functions to detect digital outputs.
12600                  * On SKL pre-D0 the strap isn't connected, so we assume
12601                  * it's there.
12602                  */
12603                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12604                 /* WaIgnoreDDIAStrap: skl */
12605                 if (found ||
12606                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12607                         intel_ddi_init(dev, PORT_A);
12608
12609                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12610                  * register */
12611                 found = I915_READ(SFUSE_STRAP);
12612
12613                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12614                         intel_ddi_init(dev, PORT_B);
12615                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12616                         intel_ddi_init(dev, PORT_C);
12617                 if (found & SFUSE_STRAP_DDID_DETECTED)
12618                         intel_ddi_init(dev, PORT_D);
12619         } else if (HAS_PCH_SPLIT(dev)) {
12620                 int found;
12621                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12622
12623                 if (has_edp_a(dev))
12624                         intel_dp_init(dev, DP_A, PORT_A);
12625
12626                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12627                         /* PCH SDVOB multiplex with HDMIB */
12628                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12629                         if (!found)
12630                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12631                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12632                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12633                 }
12634
12635                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12636                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12637
12638                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12639                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12640
12641                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12642                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12643
12644                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12645                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12646         } else if (IS_VALLEYVIEW(dev)) {
12647                 /*
12648                  * The DP_DETECTED bit is the latched state of the DDC
12649                  * SDA pin at boot. However since eDP doesn't require DDC
12650                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12651                  * eDP ports may have been muxed to an alternate function.
12652                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12653                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12654                  * detect eDP ports.
12655                  */
12656                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12657                     !intel_dp_is_edp(dev, PORT_B))
12658                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12659                                         PORT_B);
12660                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12661                     intel_dp_is_edp(dev, PORT_B))
12662                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12663
12664                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12665                     !intel_dp_is_edp(dev, PORT_C))
12666                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12667                                         PORT_C);
12668                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12669                     intel_dp_is_edp(dev, PORT_C))
12670                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12671
12672                 if (IS_CHERRYVIEW(dev)) {
12673                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12674                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12675                                                 PORT_D);
12676                         /* eDP not supported on port D, so don't check VBT */
12677                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12678                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12679                 }
12680
12681                 intel_dsi_init(dev);
12682         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12683                 bool found = false;
12684
12685                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12686                         DRM_DEBUG_KMS("probing SDVOB\n");
12687                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12688                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12689                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12690                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12691                         }
12692
12693                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12694                                 intel_dp_init(dev, DP_B, PORT_B);
12695                 }
12696
12697                 /* Before G4X SDVOC doesn't have its own detect register */
12698
12699                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12700                         DRM_DEBUG_KMS("probing SDVOC\n");
12701                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12702                 }
12703
12704                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12705
12706                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12707                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12708                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12709                         }
12710                         if (SUPPORTS_INTEGRATED_DP(dev))
12711                                 intel_dp_init(dev, DP_C, PORT_C);
12712                 }
12713
12714                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12715                     (I915_READ(DP_D) & DP_DETECTED))
12716                         intel_dp_init(dev, DP_D, PORT_D);
12717         } else if (IS_GEN2(dev))
12718                 intel_dvo_init(dev);
12719
12720         if (SUPPORTS_TV(dev))
12721                 intel_tv_init(dev);
12722
12723         /*
12724          * FIXME:  We don't have full atomic support yet, but we want to be
12725          * able to enable/test plane updates via the atomic interface in the
12726          * meantime.  However as soon as we flip DRIVER_ATOMIC on, the DRM core
12727          * will take some atomic codepaths to lookup properties during
12728          * drmModeGetConnector() that unconditionally dereference
12729          * connector->state.
12730          *
12731          * We create a dummy connector state here for each connector to ensure
12732          * the DRM core doesn't try to dereference a NULL connector->state.
12733          * The actual connector properties will never be updated or contain
12734          * useful information, but since we're doing this specifically for
12735          * testing/debug of the plane operations (and only when a specific
12736          * kernel module option is given), that shouldn't really matter.
12737          *
12738          * Once atomic support for crtc's + connectors lands, this loop should
12739          * be removed since we'll be setting up real connector state, which
12740          * will contain Intel-specific properties.
12741          */
12742         if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12743                 list_for_each_entry(connector,
12744                                     &dev->mode_config.connector_list,
12745                                     head) {
12746                         if (!WARN_ON(connector->state)) {
12747                                 connector->state =
12748                                         kzalloc(sizeof(*connector->state),
12749                                                 GFP_KERNEL);
12750                         }
12751                 }
12752         }
12753
12754         intel_psr_init(dev);
12755
12756         for_each_intel_encoder(dev, encoder) {
12757                 encoder->base.possible_crtcs = encoder->crtc_mask;
12758                 encoder->base.possible_clones =
12759                         intel_encoder_clones(encoder);
12760         }
12761
12762         intel_init_pch_refclk(dev);
12763
12764         drm_helper_move_panel_connectors_to_head(dev);
12765 }
12766
12767 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12768 {
12769         struct drm_device *dev = fb->dev;
12770         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12771
12772         drm_framebuffer_cleanup(fb);
12773         mutex_lock(&dev->struct_mutex);
12774         WARN_ON(!intel_fb->obj->framebuffer_references--);
12775         drm_gem_object_unreference(&intel_fb->obj->base);
12776         mutex_unlock(&dev->struct_mutex);
12777         kfree(intel_fb);
12778 }
12779
12780 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12781                                                 struct drm_file *file,
12782                                                 unsigned int *handle)
12783 {
12784         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12785         struct drm_i915_gem_object *obj = intel_fb->obj;
12786
12787         return drm_gem_handle_create(file, &obj->base, handle);
12788 }
12789
12790 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12791         .destroy = intel_user_framebuffer_destroy,
12792         .create_handle = intel_user_framebuffer_create_handle,
12793 };
12794
12795 static
12796 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12797                          uint32_t pixel_format)
12798 {
12799         u32 gen = INTEL_INFO(dev)->gen;
12800
12801         if (gen >= 9) {
12802                 /* "The stride in bytes must not exceed the of the size of 8K
12803                  *  pixels and 32K bytes."
12804                  */
12805                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12806         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12807                 return 32*1024;
12808         } else if (gen >= 4) {
12809                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12810                         return 16*1024;
12811                 else
12812                         return 32*1024;
12813         } else if (gen >= 3) {
12814                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12815                         return 8*1024;
12816                 else
12817                         return 16*1024;
12818         } else {
12819                 /* XXX DSPC is limited to 4k tiled */
12820                 return 8*1024;
12821         }
12822 }
12823
12824 static int intel_framebuffer_init(struct drm_device *dev,
12825                                   struct intel_framebuffer *intel_fb,
12826                                   struct drm_mode_fb_cmd2 *mode_cmd,
12827                                   struct drm_i915_gem_object *obj)
12828 {
12829         int aligned_height;
12830         int ret;
12831         u32 pitch_limit, stride_alignment;
12832
12833         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12834
12835         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12836                 /* Enforce that fb modifier and tiling mode match, but only for
12837                  * X-tiled. This is needed for FBC. */
12838                 if (!!(obj->tiling_mode == I915_TILING_X) !=
12839                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12840                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12841                         return -EINVAL;
12842                 }
12843         } else {
12844                 if (obj->tiling_mode == I915_TILING_X)
12845                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12846                 else if (obj->tiling_mode == I915_TILING_Y) {
12847                         DRM_DEBUG("No Y tiling for legacy addfb\n");
12848                         return -EINVAL;
12849                 }
12850         }
12851
12852         /* Passed in modifier sanity checking. */
12853         switch (mode_cmd->modifier[0]) {
12854         case I915_FORMAT_MOD_Y_TILED:
12855         case I915_FORMAT_MOD_Yf_TILED:
12856                 if (INTEL_INFO(dev)->gen < 9) {
12857                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12858                                   mode_cmd->modifier[0]);
12859                         return -EINVAL;
12860                 }
12861         case DRM_FORMAT_MOD_NONE:
12862         case I915_FORMAT_MOD_X_TILED:
12863                 break;
12864         default:
12865                 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12866                                 mode_cmd->modifier[0]);
12867                 return -EINVAL;
12868         }
12869
12870         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12871                                                      mode_cmd->pixel_format);
12872         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12873                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12874                           mode_cmd->pitches[0], stride_alignment);
12875                 return -EINVAL;
12876         }
12877
12878         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12879                                            mode_cmd->pixel_format);
12880         if (mode_cmd->pitches[0] > pitch_limit) {
12881                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12882                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12883                           "tiled" : "linear",
12884                           mode_cmd->pitches[0], pitch_limit);
12885                 return -EINVAL;
12886         }
12887
12888         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12889             mode_cmd->pitches[0] != obj->stride) {
12890                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12891                           mode_cmd->pitches[0], obj->stride);
12892                 return -EINVAL;
12893         }
12894
12895         /* Reject formats not supported by any plane early. */
12896         switch (mode_cmd->pixel_format) {
12897         case DRM_FORMAT_C8:
12898         case DRM_FORMAT_RGB565:
12899         case DRM_FORMAT_XRGB8888:
12900         case DRM_FORMAT_ARGB8888:
12901                 break;
12902         case DRM_FORMAT_XRGB1555:
12903         case DRM_FORMAT_ARGB1555:
12904                 if (INTEL_INFO(dev)->gen > 3) {
12905                         DRM_DEBUG("unsupported pixel format: %s\n",
12906                                   drm_get_format_name(mode_cmd->pixel_format));
12907                         return -EINVAL;
12908                 }
12909                 break;
12910         case DRM_FORMAT_XBGR8888:
12911         case DRM_FORMAT_ABGR8888:
12912         case DRM_FORMAT_XRGB2101010:
12913         case DRM_FORMAT_ARGB2101010:
12914         case DRM_FORMAT_XBGR2101010:
12915         case DRM_FORMAT_ABGR2101010:
12916                 if (INTEL_INFO(dev)->gen < 4) {
12917                         DRM_DEBUG("unsupported pixel format: %s\n",
12918                                   drm_get_format_name(mode_cmd->pixel_format));
12919                         return -EINVAL;
12920                 }
12921                 break;
12922         case DRM_FORMAT_YUYV:
12923         case DRM_FORMAT_UYVY:
12924         case DRM_FORMAT_YVYU:
12925         case DRM_FORMAT_VYUY:
12926                 if (INTEL_INFO(dev)->gen < 5) {
12927                         DRM_DEBUG("unsupported pixel format: %s\n",
12928                                   drm_get_format_name(mode_cmd->pixel_format));
12929                         return -EINVAL;
12930                 }
12931                 break;
12932         default:
12933                 DRM_DEBUG("unsupported pixel format: %s\n",
12934                           drm_get_format_name(mode_cmd->pixel_format));
12935                 return -EINVAL;
12936         }
12937
12938         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12939         if (mode_cmd->offsets[0] != 0)
12940                 return -EINVAL;
12941
12942         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12943                                                mode_cmd->pixel_format,
12944                                                mode_cmd->modifier[0]);
12945         /* FIXME drm helper for size checks (especially planar formats)? */
12946         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12947                 return -EINVAL;
12948
12949         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12950         intel_fb->obj = obj;
12951         intel_fb->obj->framebuffer_references++;
12952
12953         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12954         if (ret) {
12955                 DRM_ERROR("framebuffer init failed %d\n", ret);
12956                 return ret;
12957         }
12958
12959         return 0;
12960 }
12961
12962 static struct drm_framebuffer *
12963 intel_user_framebuffer_create(struct drm_device *dev,
12964                               struct drm_file *filp,
12965                               struct drm_mode_fb_cmd2 *mode_cmd)
12966 {
12967         struct drm_i915_gem_object *obj;
12968
12969         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12970                                                 mode_cmd->handles[0]));
12971         if (&obj->base == NULL)
12972                 return ERR_PTR(-ENOENT);
12973
12974         return intel_framebuffer_create(dev, mode_cmd, obj);
12975 }
12976
12977 #ifndef CONFIG_DRM_I915_FBDEV
12978 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12979 {
12980 }
12981 #endif
12982
12983 static const struct drm_mode_config_funcs intel_mode_funcs = {
12984         .fb_create = intel_user_framebuffer_create,
12985         .output_poll_changed = intel_fbdev_output_poll_changed,
12986         .atomic_check = intel_atomic_check,
12987         .atomic_commit = intel_atomic_commit,
12988 };
12989
12990 /* Set up chip specific display functions */
12991 static void intel_init_display(struct drm_device *dev)
12992 {
12993         struct drm_i915_private *dev_priv = dev->dev_private;
12994
12995         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12996                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12997         else if (IS_CHERRYVIEW(dev))
12998                 dev_priv->display.find_dpll = chv_find_best_dpll;
12999         else if (IS_VALLEYVIEW(dev))
13000                 dev_priv->display.find_dpll = vlv_find_best_dpll;
13001         else if (IS_PINEVIEW(dev))
13002                 dev_priv->display.find_dpll = pnv_find_best_dpll;
13003         else
13004                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13005
13006         if (INTEL_INFO(dev)->gen >= 9) {
13007                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13008                 dev_priv->display.get_initial_plane_config =
13009                         skylake_get_initial_plane_config;
13010                 dev_priv->display.crtc_compute_clock =
13011                         haswell_crtc_compute_clock;
13012                 dev_priv->display.crtc_enable = haswell_crtc_enable;
13013                 dev_priv->display.crtc_disable = haswell_crtc_disable;
13014                 dev_priv->display.off = ironlake_crtc_off;
13015                 dev_priv->display.update_primary_plane =
13016                         skylake_update_primary_plane;
13017         } else if (HAS_DDI(dev)) {
13018                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13019                 dev_priv->display.get_initial_plane_config =
13020                         ironlake_get_initial_plane_config;
13021                 dev_priv->display.crtc_compute_clock =
13022                         haswell_crtc_compute_clock;
13023                 dev_priv->display.crtc_enable = haswell_crtc_enable;
13024                 dev_priv->display.crtc_disable = haswell_crtc_disable;
13025                 dev_priv->display.off = ironlake_crtc_off;
13026                 dev_priv->display.update_primary_plane =
13027                         ironlake_update_primary_plane;
13028         } else if (HAS_PCH_SPLIT(dev)) {
13029                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13030                 dev_priv->display.get_initial_plane_config =
13031                         ironlake_get_initial_plane_config;
13032                 dev_priv->display.crtc_compute_clock =
13033                         ironlake_crtc_compute_clock;
13034                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13035                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13036                 dev_priv->display.off = ironlake_crtc_off;
13037                 dev_priv->display.update_primary_plane =
13038                         ironlake_update_primary_plane;
13039         } else if (IS_VALLEYVIEW(dev)) {
13040                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13041                 dev_priv->display.get_initial_plane_config =
13042                         i9xx_get_initial_plane_config;
13043                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13044                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13045                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13046                 dev_priv->display.off = i9xx_crtc_off;
13047                 dev_priv->display.update_primary_plane =
13048                         i9xx_update_primary_plane;
13049         } else {
13050                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13051                 dev_priv->display.get_initial_plane_config =
13052                         i9xx_get_initial_plane_config;
13053                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13054                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13055                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13056                 dev_priv->display.off = i9xx_crtc_off;
13057                 dev_priv->display.update_primary_plane =
13058                         i9xx_update_primary_plane;
13059         }
13060
13061         /* Returns the core display clock speed */
13062         if (IS_VALLEYVIEW(dev))
13063                 dev_priv->display.get_display_clock_speed =
13064                         valleyview_get_display_clock_speed;
13065         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13066                 dev_priv->display.get_display_clock_speed =
13067                         i945_get_display_clock_speed;
13068         else if (IS_I915G(dev))
13069                 dev_priv->display.get_display_clock_speed =
13070                         i915_get_display_clock_speed;
13071         else if (IS_I945GM(dev) || IS_845G(dev))
13072                 dev_priv->display.get_display_clock_speed =
13073                         i9xx_misc_get_display_clock_speed;
13074         else if (IS_PINEVIEW(dev))
13075                 dev_priv->display.get_display_clock_speed =
13076                         pnv_get_display_clock_speed;
13077         else if (IS_I915GM(dev))
13078                 dev_priv->display.get_display_clock_speed =
13079                         i915gm_get_display_clock_speed;
13080         else if (IS_I865G(dev))
13081                 dev_priv->display.get_display_clock_speed =
13082                         i865_get_display_clock_speed;
13083         else if (IS_I85X(dev))
13084                 dev_priv->display.get_display_clock_speed =
13085                         i855_get_display_clock_speed;
13086         else /* 852, 830 */
13087                 dev_priv->display.get_display_clock_speed =
13088                         i830_get_display_clock_speed;
13089
13090         if (IS_GEN5(dev)) {
13091                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13092         } else if (IS_GEN6(dev)) {
13093                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13094         } else if (IS_IVYBRIDGE(dev)) {
13095                 /* FIXME: detect B0+ stepping and use auto training */
13096                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13097                 dev_priv->display.modeset_global_resources =
13098                         ivb_modeset_global_resources;
13099         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13100                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13101         } else if (IS_VALLEYVIEW(dev)) {
13102                 dev_priv->display.modeset_global_resources =
13103                         valleyview_modeset_global_resources;
13104         }
13105
13106         switch (INTEL_INFO(dev)->gen) {
13107         case 2:
13108                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13109                 break;
13110
13111         case 3:
13112                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13113                 break;
13114
13115         case 4:
13116         case 5:
13117                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13118                 break;
13119
13120         case 6:
13121                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13122                 break;
13123         case 7:
13124         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13125                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13126                 break;
13127         case 9:
13128                 /* Drop through - unsupported since execlist only. */
13129         default:
13130                 /* Default just returns -ENODEV to indicate unsupported */
13131                 dev_priv->display.queue_flip = intel_default_queue_flip;
13132         }
13133
13134         intel_panel_init_backlight_funcs(dev);
13135
13136         mutex_init(&dev_priv->pps_mutex);
13137 }
13138
13139 /*
13140  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13141  * resume, or other times.  This quirk makes sure that's the case for
13142  * affected systems.
13143  */
13144 static void quirk_pipea_force(struct drm_device *dev)
13145 {
13146         struct drm_i915_private *dev_priv = dev->dev_private;
13147
13148         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13149         DRM_INFO("applying pipe a force quirk\n");
13150 }
13151
13152 static void quirk_pipeb_force(struct drm_device *dev)
13153 {
13154         struct drm_i915_private *dev_priv = dev->dev_private;
13155
13156         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13157         DRM_INFO("applying pipe b force quirk\n");
13158 }
13159
13160 /*
13161  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13162  */
13163 static void quirk_ssc_force_disable(struct drm_device *dev)
13164 {
13165         struct drm_i915_private *dev_priv = dev->dev_private;
13166         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13167         DRM_INFO("applying lvds SSC disable quirk\n");
13168 }
13169
13170 /*
13171  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13172  * brightness value
13173  */
13174 static void quirk_invert_brightness(struct drm_device *dev)
13175 {
13176         struct drm_i915_private *dev_priv = dev->dev_private;
13177         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13178         DRM_INFO("applying inverted panel brightness quirk\n");
13179 }
13180
13181 /* Some VBT's incorrectly indicate no backlight is present */
13182 static void quirk_backlight_present(struct drm_device *dev)
13183 {
13184         struct drm_i915_private *dev_priv = dev->dev_private;
13185         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13186         DRM_INFO("applying backlight present quirk\n");
13187 }
13188
13189 struct intel_quirk {
13190         int device;
13191         int subsystem_vendor;
13192         int subsystem_device;
13193         void (*hook)(struct drm_device *dev);
13194 };
13195
13196 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13197 struct intel_dmi_quirk {
13198         void (*hook)(struct drm_device *dev);
13199         const struct dmi_system_id (*dmi_id_list)[];
13200 };
13201
13202 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13203 {
13204         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13205         return 1;
13206 }
13207
13208 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13209         {
13210                 .dmi_id_list = &(const struct dmi_system_id[]) {
13211                         {
13212                                 .callback = intel_dmi_reverse_brightness,
13213                                 .ident = "NCR Corporation",
13214                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13215                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
13216                                 },
13217                         },
13218                         { }  /* terminating entry */
13219                 },
13220                 .hook = quirk_invert_brightness,
13221         },
13222 };
13223
13224 static struct intel_quirk intel_quirks[] = {
13225         /* HP Mini needs pipe A force quirk (LP: #322104) */
13226         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13227
13228         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13229         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13230
13231         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13232         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13233
13234         /* 830 needs to leave pipe A & dpll A up */
13235         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13236
13237         /* 830 needs to leave pipe B & dpll B up */
13238         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13239
13240         /* Lenovo U160 cannot use SSC on LVDS */
13241         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13242
13243         /* Sony Vaio Y cannot use SSC on LVDS */
13244         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13245
13246         /* Acer Aspire 5734Z must invert backlight brightness */
13247         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13248
13249         /* Acer/eMachines G725 */
13250         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13251
13252         /* Acer/eMachines e725 */
13253         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13254
13255         /* Acer/Packard Bell NCL20 */
13256         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13257
13258         /* Acer Aspire 4736Z */
13259         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13260
13261         /* Acer Aspire 5336 */
13262         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13263
13264         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13265         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13266
13267         /* Acer C720 Chromebook (Core i3 4005U) */
13268         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13269
13270         /* Apple Macbook 2,1 (Core 2 T7400) */
13271         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13272
13273         /* Toshiba CB35 Chromebook (Celeron 2955U) */
13274         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13275
13276         /* HP Chromebook 14 (Celeron 2955U) */
13277         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13278
13279         /* Dell Chromebook 11 */
13280         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13281 };
13282
13283 static void intel_init_quirks(struct drm_device *dev)
13284 {
13285         struct pci_dev *d = dev->pdev;
13286         int i;
13287
13288         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13289                 struct intel_quirk *q = &intel_quirks[i];
13290
13291                 if (d->device == q->device &&
13292                     (d->subsystem_vendor == q->subsystem_vendor ||
13293                      q->subsystem_vendor == PCI_ANY_ID) &&
13294                     (d->subsystem_device == q->subsystem_device ||
13295                      q->subsystem_device == PCI_ANY_ID))
13296                         q->hook(dev);
13297         }
13298         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13299                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13300                         intel_dmi_quirks[i].hook(dev);
13301         }
13302 }
13303
13304 /* Disable the VGA plane that we never use */
13305 static void i915_disable_vga(struct drm_device *dev)
13306 {
13307         struct drm_i915_private *dev_priv = dev->dev_private;
13308         u8 sr1;
13309         u32 vga_reg = i915_vgacntrl_reg(dev);
13310
13311         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13312         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13313         outb(SR01, VGA_SR_INDEX);
13314         sr1 = inb(VGA_SR_DATA);
13315         outb(sr1 | 1<<5, VGA_SR_DATA);
13316         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13317         udelay(300);
13318
13319         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13320         POSTING_READ(vga_reg);
13321 }
13322
13323 void intel_modeset_init_hw(struct drm_device *dev)
13324 {
13325         intel_prepare_ddi(dev);
13326
13327         if (IS_VALLEYVIEW(dev))
13328                 vlv_update_cdclk(dev);
13329
13330         intel_init_clock_gating(dev);
13331
13332         intel_enable_gt_powersave(dev);
13333 }
13334
13335 void intel_modeset_init(struct drm_device *dev)
13336 {
13337         struct drm_i915_private *dev_priv = dev->dev_private;
13338         int sprite, ret;
13339         enum pipe pipe;
13340         struct intel_crtc *crtc;
13341
13342         drm_mode_config_init(dev);
13343
13344         dev->mode_config.min_width = 0;
13345         dev->mode_config.min_height = 0;
13346
13347         dev->mode_config.preferred_depth = 24;
13348         dev->mode_config.prefer_shadow = 1;
13349
13350         dev->mode_config.allow_fb_modifiers = true;
13351
13352         dev->mode_config.funcs = &intel_mode_funcs;
13353
13354         intel_init_quirks(dev);
13355
13356         intel_init_pm(dev);
13357
13358         if (INTEL_INFO(dev)->num_pipes == 0)
13359                 return;
13360
13361         intel_init_display(dev);
13362         intel_init_audio(dev);
13363
13364         if (IS_GEN2(dev)) {
13365                 dev->mode_config.max_width = 2048;
13366                 dev->mode_config.max_height = 2048;
13367         } else if (IS_GEN3(dev)) {
13368                 dev->mode_config.max_width = 4096;
13369                 dev->mode_config.max_height = 4096;
13370         } else {
13371                 dev->mode_config.max_width = 8192;
13372                 dev->mode_config.max_height = 8192;
13373         }
13374
13375         if (IS_845G(dev) || IS_I865G(dev)) {
13376                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13377                 dev->mode_config.cursor_height = 1023;
13378         } else if (IS_GEN2(dev)) {
13379                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13380                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13381         } else {
13382                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13383                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13384         }
13385
13386         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13387
13388         DRM_DEBUG_KMS("%d display pipe%s available.\n",
13389                       INTEL_INFO(dev)->num_pipes,
13390                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13391
13392         for_each_pipe(dev_priv, pipe) {
13393                 intel_crtc_init(dev, pipe);
13394                 for_each_sprite(dev_priv, pipe, sprite) {
13395                         ret = intel_plane_init(dev, pipe, sprite);
13396                         if (ret)
13397                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13398                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13399                 }
13400         }
13401
13402         intel_init_dpio(dev);
13403
13404         intel_shared_dpll_init(dev);
13405
13406         /* Just disable it once at startup */
13407         i915_disable_vga(dev);
13408         intel_setup_outputs(dev);
13409
13410         /* Just in case the BIOS is doing something questionable. */
13411         intel_fbc_disable(dev);
13412
13413         drm_modeset_lock_all(dev);
13414         intel_modeset_setup_hw_state(dev, false);
13415         drm_modeset_unlock_all(dev);
13416
13417         for_each_intel_crtc(dev, crtc) {
13418                 if (!crtc->active)
13419                         continue;
13420
13421                 /*
13422                  * Note that reserving the BIOS fb up front prevents us
13423                  * from stuffing other stolen allocations like the ring
13424                  * on top.  This prevents some ugliness at boot time, and
13425                  * can even allow for smooth boot transitions if the BIOS
13426                  * fb is large enough for the active pipe configuration.
13427                  */
13428                 if (dev_priv->display.get_initial_plane_config) {
13429                         dev_priv->display.get_initial_plane_config(crtc,
13430                                                            &crtc->plane_config);
13431                         /*
13432                          * If the fb is shared between multiple heads, we'll
13433                          * just get the first one.
13434                          */
13435                         intel_find_plane_obj(crtc, &crtc->plane_config);
13436                 }
13437         }
13438 }
13439
13440 static void intel_enable_pipe_a(struct drm_device *dev)
13441 {
13442         struct intel_connector *connector;
13443         struct drm_connector *crt = NULL;
13444         struct intel_load_detect_pipe load_detect_temp;
13445         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13446
13447         /* We can't just switch on the pipe A, we need to set things up with a
13448          * proper mode and output configuration. As a gross hack, enable pipe A
13449          * by enabling the load detect pipe once. */
13450         for_each_intel_connector(dev, connector) {
13451                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13452                         crt = &connector->base;
13453                         break;
13454                 }
13455         }
13456
13457         if (!crt)
13458                 return;
13459
13460         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13461                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13462 }
13463
13464 static bool
13465 intel_check_plane_mapping(struct intel_crtc *crtc)
13466 {
13467         struct drm_device *dev = crtc->base.dev;
13468         struct drm_i915_private *dev_priv = dev->dev_private;
13469         u32 reg, val;
13470
13471         if (INTEL_INFO(dev)->num_pipes == 1)
13472                 return true;
13473
13474         reg = DSPCNTR(!crtc->plane);
13475         val = I915_READ(reg);
13476
13477         if ((val & DISPLAY_PLANE_ENABLE) &&
13478             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13479                 return false;
13480
13481         return true;
13482 }
13483
13484 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13485 {
13486         struct drm_device *dev = crtc->base.dev;
13487         struct drm_i915_private *dev_priv = dev->dev_private;
13488         u32 reg;
13489
13490         /* Clear any frame start delays used for debugging left by the BIOS */
13491         reg = PIPECONF(crtc->config->cpu_transcoder);
13492         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13493
13494         /* restore vblank interrupts to correct state */
13495         drm_crtc_vblank_reset(&crtc->base);
13496         if (crtc->active) {
13497                 update_scanline_offset(crtc);
13498                 drm_crtc_vblank_on(&crtc->base);
13499         }
13500
13501         /* We need to sanitize the plane -> pipe mapping first because this will
13502          * disable the crtc (and hence change the state) if it is wrong. Note
13503          * that gen4+ has a fixed plane -> pipe mapping.  */
13504         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13505                 struct intel_connector *connector;
13506                 bool plane;
13507
13508                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13509                               crtc->base.base.id);
13510
13511                 /* Pipe has the wrong plane attached and the plane is active.
13512                  * Temporarily change the plane mapping and disable everything
13513                  * ...  */
13514                 plane = crtc->plane;
13515                 crtc->plane = !plane;
13516                 crtc->primary_enabled = true;
13517                 dev_priv->display.crtc_disable(&crtc->base);
13518                 crtc->plane = plane;
13519
13520                 /* ... and break all links. */
13521                 for_each_intel_connector(dev, connector) {
13522                         if (connector->encoder->base.crtc != &crtc->base)
13523                                 continue;
13524
13525                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13526                         connector->base.encoder = NULL;
13527                 }
13528                 /* multiple connectors may have the same encoder:
13529                  *  handle them and break crtc link separately */
13530                 for_each_intel_connector(dev, connector)
13531                         if (connector->encoder->base.crtc == &crtc->base) {
13532                                 connector->encoder->base.crtc = NULL;
13533                                 connector->encoder->connectors_active = false;
13534                         }
13535
13536                 WARN_ON(crtc->active);
13537                 crtc->base.state->enable = false;
13538                 crtc->base.enabled = false;
13539         }
13540
13541         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13542             crtc->pipe == PIPE_A && !crtc->active) {
13543                 /* BIOS forgot to enable pipe A, this mostly happens after
13544                  * resume. Force-enable the pipe to fix this, the update_dpms
13545                  * call below we restore the pipe to the right state, but leave
13546                  * the required bits on. */
13547                 intel_enable_pipe_a(dev);
13548         }
13549
13550         /* Adjust the state of the output pipe according to whether we
13551          * have active connectors/encoders. */
13552         intel_crtc_update_dpms(&crtc->base);
13553
13554         if (crtc->active != crtc->base.state->enable) {
13555                 struct intel_encoder *encoder;
13556
13557                 /* This can happen either due to bugs in the get_hw_state
13558                  * functions or because the pipe is force-enabled due to the
13559                  * pipe A quirk. */
13560                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13561                               crtc->base.base.id,
13562                               crtc->base.state->enable ? "enabled" : "disabled",
13563                               crtc->active ? "enabled" : "disabled");
13564
13565                 crtc->base.state->enable = crtc->active;
13566                 crtc->base.enabled = crtc->active;
13567
13568                 /* Because we only establish the connector -> encoder ->
13569                  * crtc links if something is active, this means the
13570                  * crtc is now deactivated. Break the links. connector
13571                  * -> encoder links are only establish when things are
13572                  *  actually up, hence no need to break them. */
13573                 WARN_ON(crtc->active);
13574
13575                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13576                         WARN_ON(encoder->connectors_active);
13577                         encoder->base.crtc = NULL;
13578                 }
13579         }
13580
13581         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13582                 /*
13583                  * We start out with underrun reporting disabled to avoid races.
13584                  * For correct bookkeeping mark this on active crtcs.
13585                  *
13586                  * Also on gmch platforms we dont have any hardware bits to
13587                  * disable the underrun reporting. Which means we need to start
13588                  * out with underrun reporting disabled also on inactive pipes,
13589                  * since otherwise we'll complain about the garbage we read when
13590                  * e.g. coming up after runtime pm.
13591                  *
13592                  * No protection against concurrent access is required - at
13593                  * worst a fifo underrun happens which also sets this to false.
13594                  */
13595                 crtc->cpu_fifo_underrun_disabled = true;
13596                 crtc->pch_fifo_underrun_disabled = true;
13597         }
13598 }
13599
13600 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13601 {
13602         struct intel_connector *connector;
13603         struct drm_device *dev = encoder->base.dev;
13604
13605         /* We need to check both for a crtc link (meaning that the
13606          * encoder is active and trying to read from a pipe) and the
13607          * pipe itself being active. */
13608         bool has_active_crtc = encoder->base.crtc &&
13609                 to_intel_crtc(encoder->base.crtc)->active;
13610
13611         if (encoder->connectors_active && !has_active_crtc) {
13612                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13613                               encoder->base.base.id,
13614                               encoder->base.name);
13615
13616                 /* Connector is active, but has no active pipe. This is
13617                  * fallout from our resume register restoring. Disable
13618                  * the encoder manually again. */
13619                 if (encoder->base.crtc) {
13620                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13621                                       encoder->base.base.id,
13622                                       encoder->base.name);
13623                         encoder->disable(encoder);
13624                         if (encoder->post_disable)
13625                                 encoder->post_disable(encoder);
13626                 }
13627                 encoder->base.crtc = NULL;
13628                 encoder->connectors_active = false;
13629
13630                 /* Inconsistent output/port/pipe state happens presumably due to
13631                  * a bug in one of the get_hw_state functions. Or someplace else
13632                  * in our code, like the register restore mess on resume. Clamp
13633                  * things to off as a safer default. */
13634                 for_each_intel_connector(dev, connector) {
13635                         if (connector->encoder != encoder)
13636                                 continue;
13637                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13638                         connector->base.encoder = NULL;
13639                 }
13640         }
13641         /* Enabled encoders without active connectors will be fixed in
13642          * the crtc fixup. */
13643 }
13644
13645 void i915_redisable_vga_power_on(struct drm_device *dev)
13646 {
13647         struct drm_i915_private *dev_priv = dev->dev_private;
13648         u32 vga_reg = i915_vgacntrl_reg(dev);
13649
13650         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13651                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13652                 i915_disable_vga(dev);
13653         }
13654 }
13655
13656 void i915_redisable_vga(struct drm_device *dev)
13657 {
13658         struct drm_i915_private *dev_priv = dev->dev_private;
13659
13660         /* This function can be called both from intel_modeset_setup_hw_state or
13661          * at a very early point in our resume sequence, where the power well
13662          * structures are not yet restored. Since this function is at a very
13663          * paranoid "someone might have enabled VGA while we were not looking"
13664          * level, just check if the power well is enabled instead of trying to
13665          * follow the "don't touch the power well if we don't need it" policy
13666          * the rest of the driver uses. */
13667         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13668                 return;
13669
13670         i915_redisable_vga_power_on(dev);
13671 }
13672
13673 static bool primary_get_hw_state(struct intel_crtc *crtc)
13674 {
13675         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13676
13677         if (!crtc->active)
13678                 return false;
13679
13680         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13681 }
13682
13683 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13684 {
13685         struct drm_i915_private *dev_priv = dev->dev_private;
13686         enum pipe pipe;
13687         struct intel_crtc *crtc;
13688         struct intel_encoder *encoder;
13689         struct intel_connector *connector;
13690         int i;
13691
13692         for_each_intel_crtc(dev, crtc) {
13693                 memset(crtc->config, 0, sizeof(*crtc->config));
13694
13695                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13696
13697                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13698                                                                  crtc->config);
13699
13700                 crtc->base.state->enable = crtc->active;
13701                 crtc->base.enabled = crtc->active;
13702                 crtc->primary_enabled = primary_get_hw_state(crtc);
13703
13704                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13705                               crtc->base.base.id,
13706                               crtc->active ? "enabled" : "disabled");
13707         }
13708
13709         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13710                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13711
13712                 pll->on = pll->get_hw_state(dev_priv, pll,
13713                                             &pll->config.hw_state);
13714                 pll->active = 0;
13715                 pll->config.crtc_mask = 0;
13716                 for_each_intel_crtc(dev, crtc) {
13717                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13718                                 pll->active++;
13719                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13720                         }
13721                 }
13722
13723                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13724                               pll->name, pll->config.crtc_mask, pll->on);
13725
13726                 if (pll->config.crtc_mask)
13727                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13728         }
13729
13730         for_each_intel_encoder(dev, encoder) {
13731                 pipe = 0;
13732
13733                 if (encoder->get_hw_state(encoder, &pipe)) {
13734                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13735                         encoder->base.crtc = &crtc->base;
13736                         encoder->get_config(encoder, crtc->config);
13737                 } else {
13738                         encoder->base.crtc = NULL;
13739                 }
13740
13741                 encoder->connectors_active = false;
13742                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13743                               encoder->base.base.id,
13744                               encoder->base.name,
13745                               encoder->base.crtc ? "enabled" : "disabled",
13746                               pipe_name(pipe));
13747         }
13748
13749         for_each_intel_connector(dev, connector) {
13750                 if (connector->get_hw_state(connector)) {
13751                         connector->base.dpms = DRM_MODE_DPMS_ON;
13752                         connector->encoder->connectors_active = true;
13753                         connector->base.encoder = &connector->encoder->base;
13754                 } else {
13755                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13756                         connector->base.encoder = NULL;
13757                 }
13758                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13759                               connector->base.base.id,
13760                               connector->base.name,
13761                               connector->base.encoder ? "enabled" : "disabled");
13762         }
13763 }
13764
13765 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13766  * and i915 state tracking structures. */
13767 void intel_modeset_setup_hw_state(struct drm_device *dev,
13768                                   bool force_restore)
13769 {
13770         struct drm_i915_private *dev_priv = dev->dev_private;
13771         enum pipe pipe;
13772         struct intel_crtc *crtc;
13773         struct intel_encoder *encoder;
13774         int i;
13775
13776         intel_modeset_readout_hw_state(dev);
13777
13778         /*
13779          * Now that we have the config, copy it to each CRTC struct
13780          * Note that this could go away if we move to using crtc_config
13781          * checking everywhere.
13782          */
13783         for_each_intel_crtc(dev, crtc) {
13784                 if (crtc->active && i915.fastboot) {
13785                         intel_mode_from_pipe_config(&crtc->base.mode,
13786                                                     crtc->config);
13787                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13788                                       crtc->base.base.id);
13789                         drm_mode_debug_printmodeline(&crtc->base.mode);
13790                 }
13791         }
13792
13793         /* HW state is read out, now we need to sanitize this mess. */
13794         for_each_intel_encoder(dev, encoder) {
13795                 intel_sanitize_encoder(encoder);
13796         }
13797
13798         for_each_pipe(dev_priv, pipe) {
13799                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13800                 intel_sanitize_crtc(crtc);
13801                 intel_dump_pipe_config(crtc, crtc->config,
13802                                        "[setup_hw_state]");
13803         }
13804
13805         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13806                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13807
13808                 if (!pll->on || pll->active)
13809                         continue;
13810
13811                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13812
13813                 pll->disable(dev_priv, pll);
13814                 pll->on = false;
13815         }
13816
13817         if (IS_GEN9(dev))
13818                 skl_wm_get_hw_state(dev);
13819         else if (HAS_PCH_SPLIT(dev))
13820                 ilk_wm_get_hw_state(dev);
13821
13822         if (force_restore) {
13823                 i915_redisable_vga(dev);
13824
13825                 /*
13826                  * We need to use raw interfaces for restoring state to avoid
13827                  * checking (bogus) intermediate states.
13828                  */
13829                 for_each_pipe(dev_priv, pipe) {
13830                         struct drm_crtc *crtc =
13831                                 dev_priv->pipe_to_crtc_mapping[pipe];
13832
13833                         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13834                                        crtc->primary->fb);
13835                 }
13836         } else {
13837                 intel_modeset_update_staged_output_state(dev);
13838         }
13839
13840         intel_modeset_check_state(dev);
13841 }
13842
13843 void intel_modeset_gem_init(struct drm_device *dev)
13844 {
13845         struct drm_i915_private *dev_priv = dev->dev_private;
13846         struct drm_crtc *c;
13847         struct drm_i915_gem_object *obj;
13848
13849         mutex_lock(&dev->struct_mutex);
13850         intel_init_gt_powersave(dev);
13851         mutex_unlock(&dev->struct_mutex);
13852
13853         /*
13854          * There may be no VBT; and if the BIOS enabled SSC we can
13855          * just keep using it to avoid unnecessary flicker.  Whereas if the
13856          * BIOS isn't using it, don't assume it will work even if the VBT
13857          * indicates as much.
13858          */
13859         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13860                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13861                                                 DREF_SSC1_ENABLE);
13862
13863         intel_modeset_init_hw(dev);
13864
13865         intel_setup_overlay(dev);
13866
13867         /*
13868          * Make sure any fbs we allocated at startup are properly
13869          * pinned & fenced.  When we do the allocation it's too early
13870          * for this.
13871          */
13872         mutex_lock(&dev->struct_mutex);
13873         for_each_crtc(dev, c) {
13874                 obj = intel_fb_obj(c->primary->fb);
13875                 if (obj == NULL)
13876                         continue;
13877
13878                 if (intel_pin_and_fence_fb_obj(c->primary,
13879                                                c->primary->fb,
13880                                                NULL)) {
13881                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13882                                   to_intel_crtc(c)->pipe);
13883                         drm_framebuffer_unreference(c->primary->fb);
13884                         c->primary->fb = NULL;
13885                         update_state_fb(c->primary);
13886                 }
13887         }
13888         mutex_unlock(&dev->struct_mutex);
13889
13890         intel_backlight_register(dev);
13891 }
13892
13893 void intel_connector_unregister(struct intel_connector *intel_connector)
13894 {
13895         struct drm_connector *connector = &intel_connector->base;
13896
13897         intel_panel_destroy_backlight(connector);
13898         drm_connector_unregister(connector);
13899 }
13900
13901 void intel_modeset_cleanup(struct drm_device *dev)
13902 {
13903         struct drm_i915_private *dev_priv = dev->dev_private;
13904         struct drm_connector *connector;
13905
13906         intel_disable_gt_powersave(dev);
13907
13908         intel_backlight_unregister(dev);
13909
13910         /*
13911          * Interrupts and polling as the first thing to avoid creating havoc.
13912          * Too much stuff here (turning of connectors, ...) would
13913          * experience fancy races otherwise.
13914          */
13915         intel_irq_uninstall(dev_priv);
13916
13917         /*
13918          * Due to the hpd irq storm handling the hotplug work can re-arm the
13919          * poll handlers. Hence disable polling after hpd handling is shut down.
13920          */
13921         drm_kms_helper_poll_fini(dev);
13922
13923         mutex_lock(&dev->struct_mutex);
13924
13925         intel_unregister_dsm_handler();
13926
13927         intel_fbc_disable(dev);
13928
13929         mutex_unlock(&dev->struct_mutex);
13930
13931         /* flush any delayed tasks or pending work */
13932         flush_scheduled_work();
13933
13934         /* destroy the backlight and sysfs files before encoders/connectors */
13935         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13936                 struct intel_connector *intel_connector;
13937
13938                 intel_connector = to_intel_connector(connector);
13939                 intel_connector->unregister(intel_connector);
13940         }
13941
13942         drm_mode_config_cleanup(dev);
13943
13944         intel_cleanup_overlay(dev);
13945
13946         mutex_lock(&dev->struct_mutex);
13947         intel_cleanup_gt_powersave(dev);
13948         mutex_unlock(&dev->struct_mutex);
13949 }
13950
13951 /*
13952  * Return which encoder is currently attached for connector.
13953  */
13954 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13955 {
13956         return &intel_attached_encoder(connector)->base;
13957 }
13958
13959 void intel_connector_attach_encoder(struct intel_connector *connector,
13960                                     struct intel_encoder *encoder)
13961 {
13962         connector->encoder = encoder;
13963         drm_mode_connector_attach_encoder(&connector->base,
13964                                           &encoder->base);
13965 }
13966
13967 /*
13968  * set vga decode state - true == enable VGA decode
13969  */
13970 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13971 {
13972         struct drm_i915_private *dev_priv = dev->dev_private;
13973         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13974         u16 gmch_ctrl;
13975
13976         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13977                 DRM_ERROR("failed to read control word\n");
13978                 return -EIO;
13979         }
13980
13981         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13982                 return 0;
13983
13984         if (state)
13985                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13986         else
13987                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13988
13989         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13990                 DRM_ERROR("failed to write control word\n");
13991                 return -EIO;
13992         }
13993
13994         return 0;
13995 }
13996
13997 struct intel_display_error_state {
13998
13999         u32 power_well_driver;
14000
14001         int num_transcoders;
14002
14003         struct intel_cursor_error_state {
14004                 u32 control;
14005                 u32 position;
14006                 u32 base;
14007                 u32 size;
14008         } cursor[I915_MAX_PIPES];
14009
14010         struct intel_pipe_error_state {
14011                 bool power_domain_on;
14012                 u32 source;
14013                 u32 stat;
14014         } pipe[I915_MAX_PIPES];
14015
14016         struct intel_plane_error_state {
14017                 u32 control;
14018                 u32 stride;
14019                 u32 size;
14020                 u32 pos;
14021                 u32 addr;
14022                 u32 surface;
14023                 u32 tile_offset;
14024         } plane[I915_MAX_PIPES];
14025
14026         struct intel_transcoder_error_state {
14027                 bool power_domain_on;
14028                 enum transcoder cpu_transcoder;
14029
14030                 u32 conf;
14031
14032                 u32 htotal;
14033                 u32 hblank;
14034                 u32 hsync;
14035                 u32 vtotal;
14036                 u32 vblank;
14037                 u32 vsync;
14038         } transcoder[4];
14039 };
14040
14041 struct intel_display_error_state *
14042 intel_display_capture_error_state(struct drm_device *dev)
14043 {
14044         struct drm_i915_private *dev_priv = dev->dev_private;
14045         struct intel_display_error_state *error;
14046         int transcoders[] = {
14047                 TRANSCODER_A,
14048                 TRANSCODER_B,
14049                 TRANSCODER_C,
14050                 TRANSCODER_EDP,
14051         };
14052         int i;
14053
14054         if (INTEL_INFO(dev)->num_pipes == 0)
14055                 return NULL;
14056
14057         error = kzalloc(sizeof(*error), GFP_ATOMIC);
14058         if (error == NULL)
14059                 return NULL;
14060
14061         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14062                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14063
14064         for_each_pipe(dev_priv, i) {
14065                 error->pipe[i].power_domain_on =
14066                         __intel_display_power_is_enabled(dev_priv,
14067                                                          POWER_DOMAIN_PIPE(i));
14068                 if (!error->pipe[i].power_domain_on)
14069                         continue;
14070
14071                 error->cursor[i].control = I915_READ(CURCNTR(i));
14072                 error->cursor[i].position = I915_READ(CURPOS(i));
14073                 error->cursor[i].base = I915_READ(CURBASE(i));
14074
14075                 error->plane[i].control = I915_READ(DSPCNTR(i));
14076                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14077                 if (INTEL_INFO(dev)->gen <= 3) {
14078                         error->plane[i].size = I915_READ(DSPSIZE(i));
14079                         error->plane[i].pos = I915_READ(DSPPOS(i));
14080                 }
14081                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14082                         error->plane[i].addr = I915_READ(DSPADDR(i));
14083                 if (INTEL_INFO(dev)->gen >= 4) {
14084                         error->plane[i].surface = I915_READ(DSPSURF(i));
14085                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14086                 }
14087
14088                 error->pipe[i].source = I915_READ(PIPESRC(i));
14089
14090                 if (HAS_GMCH_DISPLAY(dev))
14091                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
14092         }
14093
14094         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14095         if (HAS_DDI(dev_priv->dev))
14096                 error->num_transcoders++; /* Account for eDP. */
14097
14098         for (i = 0; i < error->num_transcoders; i++) {
14099                 enum transcoder cpu_transcoder = transcoders[i];
14100
14101                 error->transcoder[i].power_domain_on =
14102                         __intel_display_power_is_enabled(dev_priv,
14103                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14104                 if (!error->transcoder[i].power_domain_on)
14105                         continue;
14106
14107                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14108
14109                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14110                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14111                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14112                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14113                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14114                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14115                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14116         }
14117
14118         return error;
14119 }
14120
14121 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14122
14123 void
14124 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14125                                 struct drm_device *dev,
14126                                 struct intel_display_error_state *error)
14127 {
14128         struct drm_i915_private *dev_priv = dev->dev_private;
14129         int i;
14130
14131         if (!error)
14132                 return;
14133
14134         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14135         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14136                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14137                            error->power_well_driver);
14138         for_each_pipe(dev_priv, i) {
14139                 err_printf(m, "Pipe [%d]:\n", i);
14140                 err_printf(m, "  Power: %s\n",
14141                            error->pipe[i].power_domain_on ? "on" : "off");
14142                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
14143                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
14144
14145                 err_printf(m, "Plane [%d]:\n", i);
14146                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
14147                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
14148                 if (INTEL_INFO(dev)->gen <= 3) {
14149                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
14150                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
14151                 }
14152                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14153                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
14154                 if (INTEL_INFO(dev)->gen >= 4) {
14155                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
14156                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
14157                 }
14158
14159                 err_printf(m, "Cursor [%d]:\n", i);
14160                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
14161                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
14162                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
14163         }
14164
14165         for (i = 0; i < error->num_transcoders; i++) {
14166                 err_printf(m, "CPU transcoder: %c\n",
14167                            transcoder_name(error->transcoder[i].cpu_transcoder));
14168                 err_printf(m, "  Power: %s\n",
14169                            error->transcoder[i].power_domain_on ? "on" : "off");
14170                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
14171                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
14172                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
14173                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
14174                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
14175                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
14176                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
14177         }
14178 }
14179
14180 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14181 {
14182         struct intel_crtc *crtc;
14183
14184         for_each_intel_crtc(dev, crtc) {
14185                 struct intel_unpin_work *work;
14186
14187                 spin_lock_irq(&dev->event_lock);
14188
14189                 work = crtc->unpin_work;
14190
14191                 if (work && work->event &&
14192                     work->event->base.file_priv == file) {
14193                         kfree(work->event);
14194                         work->event = NULL;
14195                 }
14196
14197                 spin_unlock_irq(&dev->event_lock);
14198         }
14199 }