drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic_helper.h>
  41 #include <drm/drm_dp_helper.h>
  42 #include <drm/drm_crtc_helper.h>
  43 #include <drm/drm_plane_helper.h>
  44 #include <drm/drm_rect.h>
  45 #include <linux/dma_remapping.h>
  46
  47 /* Primary plane formats supported by all gen */
  48 #define COMMON_PRIMARY_FORMATS \
  49         DRM_FORMAT_C8, \
  50         DRM_FORMAT_RGB565, \
  51         DRM_FORMAT_XRGB8888, \
  52         DRM_FORMAT_ARGB8888
  53
  54 /* Primary plane formats for gen <= 3 */
  55 static const uint32_t intel_primary_formats_gen2[] = {
  56         COMMON_PRIMARY_FORMATS,
  57         DRM_FORMAT_XRGB1555,
  58         DRM_FORMAT_ARGB1555,
  59 };
  60
  61 /* Primary plane formats for gen >= 4 */
  62 static const uint32_t intel_primary_formats_gen4[] = {
  63         COMMON_PRIMARY_FORMATS, \
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_ABGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_ARGB2101010,
  68         DRM_FORMAT_XBGR2101010,
  69         DRM_FORMAT_ABGR2101010,
  70 };
  71
  72 /* Cursor formats */
  73 static const uint32_t intel_cursor_formats[] = {
  74         DRM_FORMAT_ARGB8888,
  75 };
  76
  77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  78
  79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  80                                 struct intel_crtc_state *pipe_config);
  81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  82                                    struct intel_crtc_state *pipe_config);
  83
  84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  85                           int x, int y, struct drm_framebuffer *old_fb);
  86 static int intel_framebuffer_init(struct drm_device *dev,
  87                                   struct intel_framebuffer *ifb,
  88                                   struct drm_mode_fb_cmd2 *mode_cmd,
  89                                   struct drm_i915_gem_object *obj);
  90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  93                                          struct intel_link_m_n *m_n,
  94                                          struct intel_link_m_n *m2_n2);
  95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  98 static void vlv_prepare_pll(struct intel_crtc *crtc,
  99                             const struct intel_crtc_state *pipe_config);
 100 static void chv_prepare_pll(struct intel_crtc *crtc,
 101                             const struct intel_crtc_state *pipe_config);
 102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 104
 105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 106 {
 107         if (!connector->mst_port)
 108                 return connector->encoder;
 109         else
 110                 return &connector->mst_port->mst_encoders[pipe]->base;
 111 }
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4800000, .max = 6480000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static void vlv_clock(int refclk, intel_clock_t *clock)
 402 {
 403         clock->m = clock->m1 * clock->m2;
 404         clock->p = clock->p1 * clock->p2;
 405         if (WARN_ON(clock->n == 0 || clock->p == 0))
 406                 return;
 407         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 408         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 409 }
 410
 411 /**
 412  * Returns whether any output on the specified pipe is of the specified type
 413  */
 414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 415 {
 416         struct drm_device *dev = crtc->base.dev;
 417         struct intel_encoder *encoder;
 418
 419         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 420                 if (encoder->type == type)
 421                         return true;
 422
 423         return false;
 424 }
 425
 426 /**
 427  * Returns whether any output on the specified pipe will have the specified
 428  * type after a staged modeset is complete, i.e., the same as
 429  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 430  * encoder->crtc.
 431  */
 432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 433 {
 434         struct drm_device *dev = crtc->base.dev;
 435         struct intel_encoder *encoder;
 436
 437         for_each_intel_encoder(dev, encoder)
 438                 if (encoder->new_crtc == crtc && encoder->type == type)
 439                         return true;
 440
 441         return false;
 442 }
 443
 444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 445                                                 int refclk)
 446 {
 447         struct drm_device *dev = crtc->base.dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev)) {
 452                         if (refclk == 100000)
 453                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 454                         else
 455                                 limit = &intel_limits_ironlake_dual_lvds;
 456                 } else {
 457                         if (refclk == 100000)
 458                                 limit = &intel_limits_ironlake_single_lvds_100m;
 459                         else
 460                                 limit = &intel_limits_ironlake_single_lvds;
 461                 }
 462         } else
 463                 limit = &intel_limits_ironlake_dac;
 464
 465         return limit;
 466 }
 467
 468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 469 {
 470         struct drm_device *dev = crtc->base.dev;
 471         const intel_limit_t *limit;
 472
 473         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 474                 if (intel_is_dual_link_lvds(dev))
 475                         limit = &intel_limits_g4x_dual_channel_lvds;
 476                 else
 477                         limit = &intel_limits_g4x_single_channel_lvds;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 479                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 480                 limit = &intel_limits_g4x_hdmi;
 481         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 482                 limit = &intel_limits_g4x_sdvo;
 483         } else /* The option is for other outputs */
 484                 limit = &intel_limits_i9xx_sdvo;
 485
 486         return limit;
 487 }
 488
 489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 490 {
 491         struct drm_device *dev = crtc->base.dev;
 492         const intel_limit_t *limit;
 493
 494         if (HAS_PCH_SPLIT(dev))
 495                 limit = intel_ironlake_limit(crtc, refclk);
 496         else if (IS_G4X(dev)) {
 497                 limit = intel_g4x_limit(crtc);
 498         } else if (IS_PINEVIEW(dev)) {
 499                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 500                         limit = &intel_limits_pineview_lvds;
 501                 else
 502                         limit = &intel_limits_pineview_sdvo;
 503         } else if (IS_CHERRYVIEW(dev)) {
 504                 limit = &intel_limits_chv;
 505         } else if (IS_VALLEYVIEW(dev)) {
 506                 limit = &intel_limits_vlv;
 507         } else if (!IS_GEN2(dev)) {
 508                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 509                         limit = &intel_limits_i9xx_lvds;
 510                 else
 511                         limit = &intel_limits_i9xx_sdvo;
 512         } else {
 513                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 514                         limit = &intel_limits_i8xx_lvds;
 515                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 516                         limit = &intel_limits_i8xx_dvo;
 517                 else
 518                         limit = &intel_limits_i8xx_dac;
 519         }
 520         return limit;
 521 }
 522
 523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 524 static void pineview_clock(int refclk, intel_clock_t *clock)
 525 {
 526         clock->m = clock->m2 + 2;
 527         clock->p = clock->p1 * clock->p2;
 528         if (WARN_ON(clock->n == 0 || clock->p == 0))
 529                 return;
 530         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 531         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 532 }
 533
 534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 535 {
 536         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 537 }
 538
 539 static void i9xx_clock(int refclk, intel_clock_t *clock)
 540 {
 541         clock->m = i9xx_dpll_compute_m(clock);
 542         clock->p = clock->p1 * clock->p2;
 543         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 544                 return;
 545         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 546         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 547 }
 548
 549 static void chv_clock(int refclk, intel_clock_t *clock)
 550 {
 551         clock->m = clock->m1 * clock->m2;
 552         clock->p = clock->p1 * clock->p2;
 553         if (WARN_ON(clock->n == 0 || clock->p == 0))
 554                 return;
 555         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 556                         clock->n << 22);
 557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 558 }
 559
 560 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 561 /**
 562  * Returns whether the given set of divisors are valid for a given refclk with
 563  * the given connectors.
 564  */
 565
 566 static bool intel_PLL_is_valid(struct drm_device *dev,
 567                                const intel_limit_t *limit,
 568                                const intel_clock_t *clock)
 569 {
 570         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 571                 INTELPllInvalid("n out of range\n");
 572         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 573                 INTELPllInvalid("p1 out of range\n");
 574         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 575                 INTELPllInvalid("m2 out of range\n");
 576         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 577                 INTELPllInvalid("m1 out of range\n");
 578
 579         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 580                 if (clock->m1 <= clock->m2)
 581                         INTELPllInvalid("m1 <= m2\n");
 582
 583         if (!IS_VALLEYVIEW(dev)) {
 584                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 585                         INTELPllInvalid("p out of range\n");
 586                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 587                         INTELPllInvalid("m out of range\n");
 588         }
 589
 590         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 591                 INTELPllInvalid("vco out of range\n");
 592         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 593          * connector, etc., rather than just a single range.
 594          */
 595         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 596                 INTELPllInvalid("dot out of range\n");
 597
 598         return true;
 599 }
 600
 601 static bool
 602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 603                     int target, int refclk, intel_clock_t *match_clock,
 604                     intel_clock_t *best_clock)
 605 {
 606         struct drm_device *dev = crtc->base.dev;
 607         intel_clock_t clock;
 608         int err = target;
 609
 610         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 611                 /*
 612                  * For LVDS just rely on its current settings for dual-channel.
 613                  * We haven't figured out how to reliably set up different
 614                  * single/dual channel state, if we even can.
 615                  */
 616                 if (intel_is_dual_link_lvds(dev))
 617                         clock.p2 = limit->p2.p2_fast;
 618                 else
 619                         clock.p2 = limit->p2.p2_slow;
 620         } else {
 621                 if (target < limit->p2.dot_limit)
 622                         clock.p2 = limit->p2.p2_slow;
 623                 else
 624                         clock.p2 = limit->p2.p2_fast;
 625         }
 626
 627         memset(best_clock, 0, sizeof(*best_clock));
 628
 629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 630              clock.m1++) {
 631                 for (clock.m2 = limit->m2.min;
 632                      clock.m2 <= limit->m2.max; clock.m2++) {
 633                         if (clock.m2 >= clock.m1)
 634                                 break;
 635                         for (clock.n = limit->n.min;
 636                              clock.n <= limit->n.max; clock.n++) {
 637                                 for (clock.p1 = limit->p1.min;
 638                                         clock.p1 <= limit->p1.max; clock.p1++) {
 639                                         int this_err;
 640
 641                                         i9xx_clock(refclk, &clock);
 642                                         if (!intel_PLL_is_valid(dev, limit,
 643                                                                 &clock))
 644                                                 continue;
 645                                         if (match_clock &&
 646                                             clock.p != match_clock->p)
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err) {
 651                                                 *best_clock = clock;
 652                                                 err = this_err;
 653                                         }
 654                                 }
 655                         }
 656                 }
 657         }
 658
 659         return (err != target);
 660 }
 661
 662 static bool
 663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 664                    int target, int refclk, intel_clock_t *match_clock,
 665                    intel_clock_t *best_clock)
 666 {
 667         struct drm_device *dev = crtc->base.dev;
 668         intel_clock_t clock;
 669         int err = target;
 670
 671         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 672                 /*
 673                  * For LVDS just rely on its current settings for dual-channel.
 674                  * We haven't figured out how to reliably set up different
 675                  * single/dual channel state, if we even can.
 676                  */
 677                 if (intel_is_dual_link_lvds(dev))
 678                         clock.p2 = limit->p2.p2_fast;
 679                 else
 680                         clock.p2 = limit->p2.p2_slow;
 681         } else {
 682                 if (target < limit->p2.dot_limit)
 683                         clock.p2 = limit->p2.p2_slow;
 684                 else
 685                         clock.p2 = limit->p2.p2_fast;
 686         }
 687
 688         memset(best_clock, 0, sizeof(*best_clock));
 689
 690         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 691              clock.m1++) {
 692                 for (clock.m2 = limit->m2.min;
 693                      clock.m2 <= limit->m2.max; clock.m2++) {
 694                         for (clock.n = limit->n.min;
 695                              clock.n <= limit->n.max; clock.n++) {
 696                                 for (clock.p1 = limit->p1.min;
 697                                         clock.p1 <= limit->p1.max; clock.p1++) {
 698                                         int this_err;
 699
 700                                         pineview_clock(refclk, &clock);
 701                                         if (!intel_PLL_is_valid(dev, limit,
 702                                                                 &clock))
 703                                                 continue;
 704                                         if (match_clock &&
 705                                             clock.p != match_clock->p)
 706                                                 continue;
 707
 708                                         this_err = abs(clock.dot - target);
 709                                         if (this_err < err) {
 710                                                 *best_clock = clock;
 711                                                 err = this_err;
 712                                         }
 713                                 }
 714                         }
 715                 }
 716         }
 717
 718         return (err != target);
 719 }
 720
 721 static bool
 722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 723                    int target, int refclk, intel_clock_t *match_clock,
 724                    intel_clock_t *best_clock)
 725 {
 726         struct drm_device *dev = crtc->base.dev;
 727         intel_clock_t clock;
 728         int max_n;
 729         bool found;
 730         /* approximately equals target * 0.00585 */
 731         int err_most = (target >> 8) + (target >> 9);
 732         found = false;
 733
 734         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 735                 if (intel_is_dual_link_lvds(dev))
 736                         clock.p2 = limit->p2.p2_fast;
 737                 else
 738                         clock.p2 = limit->p2.p2_slow;
 739         } else {
 740                 if (target < limit->p2.dot_limit)
 741                         clock.p2 = limit->p2.p2_slow;
 742                 else
 743                         clock.p2 = limit->p2.p2_fast;
 744         }
 745
 746         memset(best_clock, 0, sizeof(*best_clock));
 747         max_n = limit->n.max;
 748         /* based on hardware requirement, prefer smaller n to precision */
 749         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 750                 /* based on hardware requirement, prefere larger m1,m2 */
 751                 for (clock.m1 = limit->m1.max;
 752                      clock.m1 >= limit->m1.min; clock.m1--) {
 753                         for (clock.m2 = limit->m2.max;
 754                              clock.m2 >= limit->m2.min; clock.m2--) {
 755                                 for (clock.p1 = limit->p1.max;
 756                                      clock.p1 >= limit->p1.min; clock.p1--) {
 757                                         int this_err;
 758
 759                                         i9xx_clock(refclk, &clock);
 760                                         if (!intel_PLL_is_valid(dev, limit,
 761                                                                 &clock))
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err_most) {
 766                                                 *best_clock = clock;
 767                                                 err_most = this_err;
 768                                                 max_n = clock.n;
 769                                                 found = true;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775         return found;
 776 }
 777
 778 static bool
 779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 780                    int target, int refclk, intel_clock_t *match_clock,
 781                    intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->base.dev;
 784         intel_clock_t clock;
 785         unsigned int bestppm = 1000000;
 786         /* min update 19.2 MHz */
 787         int max_n = min(limit->n.max, refclk / 19200);
 788         bool found = false;
 789
 790         target *= 5; /* fast clock */
 791
 792         memset(best_clock, 0, sizeof(*best_clock));
 793
 794         /* based on hardware requirement, prefer smaller n to precision */
 795         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 796                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 797                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 798                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 799                                 clock.p = clock.p1 * clock.p2;
 800                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 801                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 802                                         unsigned int ppm, diff;
 803
 804                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 805                                                                      refclk * clock.m1);
 806
 807                                         vlv_clock(refclk, &clock);
 808
 809                                         if (!intel_PLL_is_valid(dev, limit,
 810                                                                 &clock))
 811                                                 continue;
 812
 813                                         diff = abs(clock.dot - target);
 814                                         ppm = div_u64(1000000ULL * diff, target);
 815
 816                                         if (ppm < 100 && clock.p > best_clock->p) {
 817                                                 bestppm = 0;
 818                                                 *best_clock = clock;
 819                                                 found = true;
 820                                         }
 821
 822                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 823                                                 bestppm = ppm;
 824                                                 *best_clock = clock;
 825                                                 found = true;
 826                                         }
 827                                 }
 828                         }
 829                 }
 830         }
 831
 832         return found;
 833 }
 834
 835 static bool
 836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 837                    int target, int refclk, intel_clock_t *match_clock,
 838                    intel_clock_t *best_clock)
 839 {
 840         struct drm_device *dev = crtc->base.dev;
 841         intel_clock_t clock;
 842         uint64_t m2;
 843         int found = false;
 844
 845         memset(best_clock, 0, sizeof(*best_clock));
 846
 847         /*
 848          * Based on hardware doc, the n always set to 1, and m1 always
 849          * set to 2.  If requires to support 200Mhz refclk, we need to
 850          * revisit this because n may not 1 anymore.
 851          */
 852         clock.n = 1, clock.m1 = 2;
 853         target *= 5;    /* fast clock */
 854
 855         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 856                 for (clock.p2 = limit->p2.p2_fast;
 857                                 clock.p2 >= limit->p2.p2_slow;
 858                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 859
 860                         clock.p = clock.p1 * clock.p2;
 861
 862                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 863                                         clock.n) << 22, refclk * clock.m1);
 864
 865                         if (m2 > INT_MAX/clock.m1)
 866                                 continue;
 867
 868                         clock.m2 = m2;
 869
 870                         chv_clock(refclk, &clock);
 871
 872                         if (!intel_PLL_is_valid(dev, limit, &clock))
 873                                 continue;
 874
 875                         /* based on hardware requirement, prefer bigger p
 876                          */
 877                         if (clock.p > best_clock->p) {
 878                                 *best_clock = clock;
 879                                 found = true;
 880                         }
 881                 }
 882         }
 883
 884         return found;
 885 }
 886
 887 bool intel_crtc_active(struct drm_crtc *crtc)
 888 {
 889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 890
 891         /* Be paranoid as we can arrive here with only partial
 892          * state retrieved from the hardware during setup.
 893          *
 894          * We can ditch the adjusted_mode.crtc_clock check as soon
 895          * as Haswell has gained clock readout/fastboot support.
 896          *
 897          * We can ditch the crtc->primary->fb check as soon as we can
 898          * properly reconstruct framebuffers.
 899          */
 900         return intel_crtc->active && crtc->primary->fb &&
 901                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 902 }
 903
 904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 905                                              enum pipe pipe)
 906 {
 907         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 909
 910         return intel_crtc->config->cpu_transcoder;
 911 }
 912
 913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 914 {
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         u32 reg = PIPEDSL(pipe);
 917         u32 line1, line2;
 918         u32 line_mask;
 919
 920         if (IS_GEN2(dev))
 921                 line_mask = DSL_LINEMASK_GEN2;
 922         else
 923                 line_mask = DSL_LINEMASK_GEN3;
 924
 925         line1 = I915_READ(reg) & line_mask;
 926         mdelay(5);
 927         line2 = I915_READ(reg) & line_mask;
 928
 929         return line1 == line2;
 930 }
 931
 932 /*
 933  * intel_wait_for_pipe_off - wait for pipe to turn off
 934  * @crtc: crtc whose pipe to wait for
 935  *
 936  * After disabling a pipe, we can't wait for vblank in the usual way,
 937  * spinning on the vblank interrupt status bit, since we won't actually
 938  * see an interrupt when the pipe is disabled.
 939  *
 940  * On Gen4 and above:
 941  *   wait for the pipe register state bit to turn off
 942  *
 943  * Otherwise:
 944  *   wait for the display line value to settle (it usually
 945  *   ends up stopping at the start of the next frame).
 946  *
 947  */
 948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 949 {
 950         struct drm_device *dev = crtc->base.dev;
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
 953         enum pipe pipe = crtc->pipe;
 954
 955         if (INTEL_INFO(dev)->gen >= 4) {
 956                 int reg = PIPECONF(cpu_transcoder);
 957
 958                 /* Wait for the Pipe State to go off */
 959                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 960                              100))
 961                         WARN(1, "pipe_off wait timed out\n");
 962         } else {
 963                 /* Wait for the display line to settle */
 964                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 965                         WARN(1, "pipe_off wait timed out\n");
 966         }
 967 }
 968
 969 /*
 970  * ibx_digital_port_connected - is the specified port connected?
 971  * @dev_priv: i915 private structure
 972  * @port: the port to test
 973  *
 974  * Returns true if @port is connected, false otherwise.
 975  */
 976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 977                                 struct intel_digital_port *port)
 978 {
 979         u32 bit;
 980
 981         if (HAS_PCH_IBX(dev_priv->dev)) {
 982                 switch (port->port) {
 983                 case PORT_B:
 984                         bit = SDE_PORTB_HOTPLUG;
 985                         break;
 986                 case PORT_C:
 987                         bit = SDE_PORTC_HOTPLUG;
 988                         break;
 989                 case PORT_D:
 990                         bit = SDE_PORTD_HOTPLUG;
 991                         break;
 992                 default:
 993                         return true;
 994                 }
 995         } else {
 996                 switch (port->port) {
 997                 case PORT_B:
 998                         bit = SDE_PORTB_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_C:
1001                         bit = SDE_PORTC_HOTPLUG_CPT;
1002                         break;
1003                 case PORT_D:
1004                         bit = SDE_PORTD_HOTPLUG_CPT;
1005                         break;
1006                 default:
1007                         return true;
1008                 }
1009         }
1010
1011         return I915_READ(SDEISR) & bit;
1012 }
1013
1014 static const char *state_string(bool enabled)
1015 {
1016         return enabled ? "on" : "off";
1017 }
1018
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021                 enum pipe pipe, bool state)
1022 {
1023         int reg;
1024         u32 val;
1025         bool cur_state;
1026
1027         reg = DPLL(pipe);
1028         val = I915_READ(reg);
1029         cur_state = !!(val & DPLL_VCO_ENABLE);
1030         I915_STATE_WARN(cur_state != state,
1031              "PLL state assertion failure (expected %s, current %s)\n",
1032              state_string(state), state_string(cur_state));
1033 }
1034
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037 {
1038         u32 val;
1039         bool cur_state;
1040
1041         mutex_lock(&dev_priv->dpio_lock);
1042         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043         mutex_unlock(&dev_priv->dpio_lock);
1044
1045         cur_state = val & DSI_PLL_VCO_EN;
1046         I915_STATE_WARN(cur_state != state,
1047              "DSI PLL state assertion failure (expected %s, current %s)\n",
1048              state_string(state), state_string(cur_state));
1049 }
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055 {
1056         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
1058         if (crtc->config->shared_dpll < 0)
1059                 return NULL;
1060
1061         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1062 }
1063
1064 /* For ILK+ */
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066                         struct intel_shared_dpll *pll,
1067                         bool state)
1068 {
1069         bool cur_state;
1070         struct intel_dpll_hw_state hw_state;
1071
1072         if (WARN (!pll,
1073                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1074                 return;
1075
1076         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077         I915_STATE_WARN(cur_state != state,
1078              "%s assertion failure (expected %s, current %s)\n",
1079              pll->name, state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083                           enum pipe pipe, bool state)
1084 {
1085         int reg;
1086         u32 val;
1087         bool cur_state;
1088         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089                                                                       pipe);
1090
1091         if (HAS_DDI(dev_priv->dev)) {
1092                 /* DDI does not have a specific FDI_TX register */
1093                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094                 val = I915_READ(reg);
1095                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1096         } else {
1097                 reg = FDI_TX_CTL(pipe);
1098                 val = I915_READ(reg);
1099                 cur_state = !!(val & FDI_TX_ENABLE);
1100         }
1101         I915_STATE_WARN(cur_state != state,
1102              "FDI TX state assertion failure (expected %s, current %s)\n",
1103              state_string(state), state_string(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109                           enum pipe pipe, bool state)
1110 {
1111         int reg;
1112         u32 val;
1113         bool cur_state;
1114
1115         reg = FDI_RX_CTL(pipe);
1116         val = I915_READ(reg);
1117         cur_state = !!(val & FDI_RX_ENABLE);
1118         I915_STATE_WARN(cur_state != state,
1119              "FDI RX state assertion failure (expected %s, current %s)\n",
1120              state_string(state), state_string(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126                                       enum pipe pipe)
1127 {
1128         int reg;
1129         u32 val;
1130
1131         /* ILK FDI PLL is always enabled */
1132         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1133                 return;
1134
1135         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136         if (HAS_DDI(dev_priv->dev))
1137                 return;
1138
1139         reg = FDI_TX_CTL(pipe);
1140         val = I915_READ(reg);
1141         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142 }
1143
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145                        enum pipe pipe, bool state)
1146 {
1147         int reg;
1148         u32 val;
1149         bool cur_state;
1150
1151         reg = FDI_RX_CTL(pipe);
1152         val = I915_READ(reg);
1153         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154         I915_STATE_WARN(cur_state != state,
1155              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156              state_string(state), state_string(cur_state));
1157 }
1158
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160                            enum pipe pipe)
1161 {
1162         struct drm_device *dev = dev_priv->dev;
1163         int pp_reg;
1164         u32 val;
1165         enum pipe panel_pipe = PIPE_A;
1166         bool locked = true;
1167
1168         if (WARN_ON(HAS_DDI(dev)))
1169                 return;
1170
1171         if (HAS_PCH_SPLIT(dev)) {
1172                 u32 port_sel;
1173
1174                 pp_reg = PCH_PP_CONTROL;
1175                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179                         panel_pipe = PIPE_B;
1180                 /* XXX: else fix for eDP */
1181         } else if (IS_VALLEYVIEW(dev)) {
1182                 /* presumably write lock depends on pipe, not port select */
1183                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184                 panel_pipe = pipe;
1185         } else {
1186                 pp_reg = PP_CONTROL;
1187                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188                         panel_pipe = PIPE_B;
1189         }
1190
1191         val = I915_READ(pp_reg);
1192         if (!(val & PANEL_POWER_ON) ||
1193             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1194                 locked = false;
1195
1196         I915_STATE_WARN(panel_pipe == pipe && locked,
1197              "panel assertion failure, pipe %c regs locked\n",
1198              pipe_name(pipe));
1199 }
1200
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202                           enum pipe pipe, bool state)
1203 {
1204         struct drm_device *dev = dev_priv->dev;
1205         bool cur_state;
1206
1207         if (IS_845G(dev) || IS_I865G(dev))
1208                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1209         else
1210                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1211
1212         I915_STATE_WARN(cur_state != state,
1213              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214              pipe_name(pipe), state_string(state), state_string(cur_state));
1215 }
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220                  enum pipe pipe, bool state)
1221 {
1222         int reg;
1223         u32 val;
1224         bool cur_state;
1225         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226                                                                       pipe);
1227
1228         /* if we need the pipe quirk it must be always on */
1229         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1231                 state = true;
1232
1233         if (!intel_display_power_is_enabled(dev_priv,
1234                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1235                 cur_state = false;
1236         } else {
1237                 reg = PIPECONF(cpu_transcoder);
1238                 val = I915_READ(reg);
1239                 cur_state = !!(val & PIPECONF_ENABLE);
1240         }
1241
1242         I915_STATE_WARN(cur_state != state,
1243              "pipe %c assertion failure (expected %s, current %s)\n",
1244              pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248                          enum plane plane, bool state)
1249 {
1250         int reg;
1251         u32 val;
1252         bool cur_state;
1253
1254         reg = DSPCNTR(plane);
1255         val = I915_READ(reg);
1256         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257         I915_STATE_WARN(cur_state != state,
1258              "plane %c assertion failure (expected %s, current %s)\n",
1259              plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266                                    enum pipe pipe)
1267 {
1268         struct drm_device *dev = dev_priv->dev;
1269         int reg, i;
1270         u32 val;
1271         int cur_pipe;
1272
1273         /* Primary planes are fixed to pipes on gen4+ */
1274         if (INTEL_INFO(dev)->gen >= 4) {
1275                 reg = DSPCNTR(pipe);
1276                 val = I915_READ(reg);
1277                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278                      "plane %c assertion failure, should be disabled but not\n",
1279                      plane_name(pipe));
1280                 return;
1281         }
1282
1283         /* Need to check both planes against the pipe */
1284         for_each_pipe(dev_priv, i) {
1285                 reg = DSPCNTR(i);
1286                 val = I915_READ(reg);
1287                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288                         DISPPLANE_SEL_PIPE_SHIFT;
1289                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291                      plane_name(i), pipe_name(pipe));
1292         }
1293 }
1294
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296                                     enum pipe pipe)
1297 {
1298         struct drm_device *dev = dev_priv->dev;
1299         int reg, sprite;
1300         u32 val;
1301
1302         if (INTEL_INFO(dev)->gen >= 9) {
1303                 for_each_sprite(dev_priv, pipe, sprite) {
1304                         val = I915_READ(PLANE_CTL(pipe, sprite));
1305                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307                              sprite, pipe_name(pipe));
1308                 }
1309         } else if (IS_VALLEYVIEW(dev)) {
1310                 for_each_sprite(dev_priv, pipe, sprite) {
1311                         reg = SPCNTR(pipe, sprite);
1312                         val = I915_READ(reg);
1313                         I915_STATE_WARN(val & SP_ENABLE,
1314                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315                              sprite_name(pipe, sprite), pipe_name(pipe));
1316                 }
1317         } else if (INTEL_INFO(dev)->gen >= 7) {
1318                 reg = SPRCTL(pipe);
1319                 val = I915_READ(reg);
1320                 I915_STATE_WARN(val & SPRITE_ENABLE,
1321                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322                      plane_name(pipe), pipe_name(pipe));
1323         } else if (INTEL_INFO(dev)->gen >= 5) {
1324                 reg = DVSCNTR(pipe);
1325                 val = I915_READ(reg);
1326                 I915_STATE_WARN(val & DVS_ENABLE,
1327                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328                      plane_name(pipe), pipe_name(pipe));
1329         }
1330 }
1331
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1333 {
1334         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335                 drm_crtc_vblank_put(crtc);
1336 }
1337
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1339 {
1340         u32 val;
1341         bool enabled;
1342
1343         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1344
1345         val = I915_READ(PCH_DREF_CONTROL);
1346         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347                             DREF_SUPERSPREAD_SOURCE_MASK));
1348         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1349 }
1350
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352                                            enum pipe pipe)
1353 {
1354         int reg;
1355         u32 val;
1356         bool enabled;
1357
1358         reg = PCH_TRANSCONF(pipe);
1359         val = I915_READ(reg);
1360         enabled = !!(val & TRANS_ENABLE);
1361         I915_STATE_WARN(enabled,
1362              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363              pipe_name(pipe));
1364 }
1365
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367                             enum pipe pipe, u32 port_sel, u32 val)
1368 {
1369         if ((val & DP_PORT_EN) == 0)
1370                 return false;
1371
1372         if (HAS_PCH_CPT(dev_priv->dev)) {
1373                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376                         return false;
1377         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379                         return false;
1380         } else {
1381                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382                         return false;
1383         }
1384         return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388                               enum pipe pipe, u32 val)
1389 {
1390         if ((val & SDVO_ENABLE) == 0)
1391                 return false;
1392
1393         if (HAS_PCH_CPT(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395                         return false;
1396         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398                         return false;
1399         } else {
1400                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401                         return false;
1402         }
1403         return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407                               enum pipe pipe, u32 val)
1408 {
1409         if ((val & LVDS_PORT_EN) == 0)
1410                 return false;
1411
1412         if (HAS_PCH_CPT(dev_priv->dev)) {
1413                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414                         return false;
1415         } else {
1416                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417                         return false;
1418         }
1419         return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423                               enum pipe pipe, u32 val)
1424 {
1425         if ((val & ADPA_DAC_ENABLE) == 0)
1426                 return false;
1427         if (HAS_PCH_CPT(dev_priv->dev)) {
1428                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429                         return false;
1430         } else {
1431                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432                         return false;
1433         }
1434         return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438                                    enum pipe pipe, int reg, u32 port_sel)
1439 {
1440         u32 val = I915_READ(reg);
1441         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443              reg, pipe_name(pipe));
1444
1445         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446              && (val & DP_PIPEB_SELECT),
1447              "IBX PCH dp port still using transcoder B\n");
1448 }
1449
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451                                      enum pipe pipe, int reg)
1452 {
1453         u32 val = I915_READ(reg);
1454         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456              reg, pipe_name(pipe));
1457
1458         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459              && (val & SDVO_PIPE_B_SELECT),
1460              "IBX PCH hdmi port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464                                       enum pipe pipe)
1465 {
1466         int reg;
1467         u32 val;
1468
1469         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473         reg = PCH_ADPA;
1474         val = I915_READ(reg);
1475         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476              "PCH VGA enabled on transcoder %c, should be disabled\n",
1477              pipe_name(pipe));
1478
1479         reg = PCH_LVDS;
1480         val = I915_READ(reg);
1481         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483              pipe_name(pipe));
1484
1485         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1488 }
1489
1490 static void intel_init_dpio(struct drm_device *dev)
1491 {
1492         struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494         if (!IS_VALLEYVIEW(dev))
1495                 return;
1496
1497         /*
1498          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499          * CHV x1 PHY (DP/HDMI D)
1500          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501          */
1502         if (IS_CHERRYVIEW(dev)) {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505         } else {
1506                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507         }
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511                            const struct intel_crtc_state *pipe_config)
1512 {
1513         struct drm_device *dev = crtc->base.dev;
1514         struct drm_i915_private *dev_priv = dev->dev_private;
1515         int reg = DPLL(crtc->pipe);
1516         u32 dpll = pipe_config->dpll_hw_state.dpll;
1517
1518         assert_pipe_disabled(dev_priv, crtc->pipe);
1519
1520         /* No really, not for ILK+ */
1521         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523         /* PLL is protected by panel, make sure we can write it */
1524         if (IS_MOBILE(dev_priv->dev))
1525                 assert_panel_unlocked(dev_priv, crtc->pipe);
1526
1527         I915_WRITE(reg, dpll);
1528         POSTING_READ(reg);
1529         udelay(150);
1530
1531         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
1534         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535         POSTING_READ(DPLL_MD(crtc->pipe));
1536
1537         /* We do this three times for luck */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544         I915_WRITE(reg, dpll);
1545         POSTING_READ(reg);
1546         udelay(150); /* wait for warmup */
1547 }
1548
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550                            const struct intel_crtc_state *pipe_config)
1551 {
1552         struct drm_device *dev = crtc->base.dev;
1553         struct drm_i915_private *dev_priv = dev->dev_private;
1554         int pipe = crtc->pipe;
1555         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1556         u32 tmp;
1557
1558         assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562         mutex_lock(&dev_priv->dpio_lock);
1563
1564         /* Enable back the 10bit clock to display controller */
1565         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566         tmp |= DPIO_DCLKP_EN;
1567         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569         /*
1570          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571          */
1572         udelay(1);
1573
1574         /* Enable PLL */
1575         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1576
1577         /* Check PLL is locked */
1578         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
1581         /* not sure when this should be written */
1582         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583         POSTING_READ(DPLL_MD(pipe));
1584
1585         mutex_unlock(&dev_priv->dpio_lock);
1586 }
1587
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1589 {
1590         struct intel_crtc *crtc;
1591         int count = 0;
1592
1593         for_each_intel_crtc(dev, crtc)
1594                 count += crtc->active &&
1595                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1596
1597         return count;
1598 }
1599
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1601 {
1602         struct drm_device *dev = crtc->base.dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         int reg = DPLL(crtc->pipe);
1605         u32 dpll = crtc->config->dpll_hw_state.dpll;
1606
1607         assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609         /* No really, not for ILK+ */
1610         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1611
1612         /* PLL is protected by panel, make sure we can write it */
1613         if (IS_MOBILE(dev) && !IS_I830(dev))
1614                 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616         /* Enable DVO 2x clock on both PLLs if necessary */
1617         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618                 /*
1619                  * It appears to be important that we don't enable this
1620                  * for the current pipe before otherwise configuring the
1621                  * PLL. No idea how this should be handled if multiple
1622                  * DVO outputs are enabled simultaneosly.
1623                  */
1624                 dpll |= DPLL_DVO_2X_MODE;
1625                 I915_WRITE(DPLL(!crtc->pipe),
1626                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627         }
1628
1629         /* Wait for the clocks to stabilize. */
1630         POSTING_READ(reg);
1631         udelay(150);
1632
1633         if (INTEL_INFO(dev)->gen >= 4) {
1634                 I915_WRITE(DPLL_MD(crtc->pipe),
1635                            crtc->config->dpll_hw_state.dpll_md);
1636         } else {
1637                 /* The pixel multiplier can only be updated once the
1638                  * DPLL is enabled and the clocks are stable.
1639                  *
1640                  * So write it again.
1641                  */
1642                 I915_WRITE(reg, dpll);
1643         }
1644
1645         /* We do this three times for luck */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652         I915_WRITE(reg, dpll);
1653         POSTING_READ(reg);
1654         udelay(150); /* wait for warmup */
1655 }
1656
1657 /**
1658  * i9xx_disable_pll - disable a PLL
1659  * @dev_priv: i915 private structure
1660  * @pipe: pipe PLL to disable
1661  *
1662  * Disable the PLL for @pipe, making sure the pipe is off first.
1663  *
1664  * Note!  This is for pre-ILK only.
1665  */
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1667 {
1668         struct drm_device *dev = crtc->base.dev;
1669         struct drm_i915_private *dev_priv = dev->dev_private;
1670         enum pipe pipe = crtc->pipe;
1671
1672         /* Disable DVO 2x clock on both PLLs if necessary */
1673         if (IS_I830(dev) &&
1674             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675             intel_num_dvo_pipes(dev) == 1) {
1676                 I915_WRITE(DPLL(PIPE_B),
1677                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678                 I915_WRITE(DPLL(PIPE_A),
1679                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680         }
1681
1682         /* Don't disable pipe or pipe PLLs if needed */
1683         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1685                 return;
1686
1687         /* Make sure the pipe isn't still relying on us */
1688         assert_pipe_disabled(dev_priv, pipe);
1689
1690         I915_WRITE(DPLL(pipe), 0);
1691         POSTING_READ(DPLL(pipe));
1692 }
1693
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696         u32 val = 0;
1697
1698         /* Make sure the pipe isn't still relying on us */
1699         assert_pipe_disabled(dev_priv, pipe);
1700
1701         /*
1702          * Leave integrated clock source and reference clock enabled for pipe B.
1703          * The latter is needed for VGA hotplug / manual detection.
1704          */
1705         if (pipe == PIPE_B)
1706                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707         I915_WRITE(DPLL(pipe), val);
1708         POSTING_READ(DPLL(pipe));
1709
1710 }
1711
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715         u32 val;
1716
1717         /* Make sure the pipe isn't still relying on us */
1718         assert_pipe_disabled(dev_priv, pipe);
1719
1720         /* Set PLL en = 0 */
1721         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1722         if (pipe != PIPE_A)
1723                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726
1727         mutex_lock(&dev_priv->dpio_lock);
1728
1729         /* Disable 10bit clock to display controller */
1730         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731         val &= ~DPIO_DCLKP_EN;
1732         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734         /* disable left/right clock distribution */
1735         if (pipe != PIPE_B) {
1736                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739         } else {
1740                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743         }
1744
1745         mutex_unlock(&dev_priv->dpio_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749                 struct intel_digital_port *dport)
1750 {
1751         u32 port_mask;
1752         int dpll_reg;
1753
1754         switch (dport->port) {
1755         case PORT_B:
1756                 port_mask = DPLL_PORTB_READY_MASK;
1757                 dpll_reg = DPLL(0);
1758                 break;
1759         case PORT_C:
1760                 port_mask = DPLL_PORTC_READY_MASK;
1761                 dpll_reg = DPLL(0);
1762                 break;
1763         case PORT_D:
1764                 port_mask = DPLL_PORTD_READY_MASK;
1765                 dpll_reg = DPIO_PHY_STATUS;
1766                 break;
1767         default:
1768                 BUG();
1769         }
1770
1771         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773                      port_name(dport->port), I915_READ(dpll_reg));
1774 }
1775
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777 {
1778         struct drm_device *dev = crtc->base.dev;
1779         struct drm_i915_private *dev_priv = dev->dev_private;
1780         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782         if (WARN_ON(pll == NULL))
1783                 return;
1784
1785         WARN_ON(!pll->config.crtc_mask);
1786         if (pll->active == 0) {
1787                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788                 WARN_ON(pll->on);
1789                 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791                 pll->mode_set(dev_priv, pll);
1792         }
1793 }
1794
1795 /**
1796  * intel_enable_shared_dpll - enable PCH PLL
1797  * @dev_priv: i915 private structure
1798  * @pipe: pipe PLL to enable
1799  *
1800  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801  * drives the transcoder clock.
1802  */
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804 {
1805         struct drm_device *dev = crtc->base.dev;
1806         struct drm_i915_private *dev_priv = dev->dev_private;
1807         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809         if (WARN_ON(pll == NULL))
1810                 return;
1811
1812         if (WARN_ON(pll->config.crtc_mask == 0))
1813                 return;
1814
1815         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816                       pll->name, pll->active, pll->on,
1817                       crtc->base.base.id);
1818
1819         if (pll->active++) {
1820                 WARN_ON(!pll->on);
1821                 assert_shared_dpll_enabled(dev_priv, pll);
1822                 return;
1823         }
1824         WARN_ON(pll->on);
1825
1826         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829         pll->enable(dev_priv, pll);
1830         pll->on = true;
1831 }
1832
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835         struct drm_device *dev = crtc->base.dev;
1836         struct drm_i915_private *dev_priv = dev->dev_private;
1837         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839         /* PCH only available on ILK+ */
1840         BUG_ON(INTEL_INFO(dev)->gen < 5);
1841         if (WARN_ON(pll == NULL))
1842                return;
1843
1844         if (WARN_ON(pll->config.crtc_mask == 0))
1845                 return;
1846
1847         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848                       pll->name, pll->active, pll->on,
1849                       crtc->base.base.id);
1850
1851         if (WARN_ON(pll->active == 0)) {
1852                 assert_shared_dpll_disabled(dev_priv, pll);
1853                 return;
1854         }
1855
1856         assert_shared_dpll_enabled(dev_priv, pll);
1857         WARN_ON(!pll->on);
1858         if (--pll->active)
1859                 return;
1860
1861         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862         pll->disable(dev_priv, pll);
1863         pll->on = false;
1864
1865         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866 }
1867
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869                                            enum pipe pipe)
1870 {
1871         struct drm_device *dev = dev_priv->dev;
1872         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874         uint32_t reg, val, pipeconf_val;
1875
1876         /* PCH only available on ILK+ */
1877         BUG_ON(!HAS_PCH_SPLIT(dev));
1878
1879         /* Make sure PCH DPLL is enabled */
1880         assert_shared_dpll_enabled(dev_priv,
1881                                    intel_crtc_to_shared_dpll(intel_crtc));
1882
1883         /* FDI must be feeding us bits for PCH ports */
1884         assert_fdi_tx_enabled(dev_priv, pipe);
1885         assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887         if (HAS_PCH_CPT(dev)) {
1888                 /* Workaround: Set the timing override bit before enabling the
1889                  * pch transcoder. */
1890                 reg = TRANS_CHICKEN2(pipe);
1891                 val = I915_READ(reg);
1892                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893                 I915_WRITE(reg, val);
1894         }
1895
1896         reg = PCH_TRANSCONF(pipe);
1897         val = I915_READ(reg);
1898         pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900         if (HAS_PCH_IBX(dev_priv->dev)) {
1901                 /*
1902                  * make the BPC in transcoder be consistent with
1903                  * that in pipeconf reg.
1904                  */
1905                 val &= ~PIPECONF_BPC_MASK;
1906                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907         }
1908
1909         val &= ~TRANS_INTERLACE_MASK;
1910         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911                 if (HAS_PCH_IBX(dev_priv->dev) &&
1912                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913                         val |= TRANS_LEGACY_INTERLACED_ILK;
1914                 else
1915                         val |= TRANS_INTERLACED;
1916         else
1917                 val |= TRANS_PROGRESSIVE;
1918
1919         I915_WRITE(reg, val | TRANS_ENABLE);
1920         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922 }
1923
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925                                       enum transcoder cpu_transcoder)
1926 {
1927         u32 val, pipeconf_val;
1928
1929         /* PCH only available on ILK+ */
1930         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1931
1932         /* FDI must be feeding us bits for PCH ports */
1933         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936         /* Workaround: set timing override bit. */
1937         val = I915_READ(_TRANSA_CHICKEN2);
1938         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939         I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941         val = TRANS_ENABLE;
1942         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945             PIPECONF_INTERLACED_ILK)
1946                 val |= TRANS_INTERLACED;
1947         else
1948                 val |= TRANS_PROGRESSIVE;
1949
1950         I915_WRITE(LPT_TRANSCONF, val);
1951         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952                 DRM_ERROR("Failed to enable PCH transcoder\n");
1953 }
1954
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956                                             enum pipe pipe)
1957 {
1958         struct drm_device *dev = dev_priv->dev;
1959         uint32_t reg, val;
1960
1961         /* FDI relies on the transcoder */
1962         assert_fdi_tx_disabled(dev_priv, pipe);
1963         assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965         /* Ports must be off as well */
1966         assert_pch_ports_disabled(dev_priv, pipe);
1967
1968         reg = PCH_TRANSCONF(pipe);
1969         val = I915_READ(reg);
1970         val &= ~TRANS_ENABLE;
1971         I915_WRITE(reg, val);
1972         /* wait for PCH transcoder off, transcoder state */
1973         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976         if (!HAS_PCH_IBX(dev)) {
1977                 /* Workaround: Clear the timing override chicken bit again. */
1978                 reg = TRANS_CHICKEN2(pipe);
1979                 val = I915_READ(reg);
1980                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981                 I915_WRITE(reg, val);
1982         }
1983 }
1984
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 {
1987         u32 val;
1988
1989         val = I915_READ(LPT_TRANSCONF);
1990         val &= ~TRANS_ENABLE;
1991         I915_WRITE(LPT_TRANSCONF, val);
1992         /* wait for PCH transcoder off, transcoder state */
1993         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994                 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996         /* Workaround: clear timing override bit. */
1997         val = I915_READ(_TRANSA_CHICKEN2);
1998         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999         I915_WRITE(_TRANSA_CHICKEN2, val);
2000 }
2001
2002 /**
2003  * intel_enable_pipe - enable a pipe, asserting requirements
2004  * @crtc: crtc responsible for the pipe
2005  *
2006  * Enable @crtc's pipe, making sure that various hardware specific requirements
2007  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008  */
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2010 {
2011         struct drm_device *dev = crtc->base.dev;
2012         struct drm_i915_private *dev_priv = dev->dev_private;
2013         enum pipe pipe = crtc->pipe;
2014         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015                                                                       pipe);
2016         enum pipe pch_transcoder;
2017         int reg;
2018         u32 val;
2019
2020         assert_planes_disabled(dev_priv, pipe);
2021         assert_cursor_disabled(dev_priv, pipe);
2022         assert_sprites_disabled(dev_priv, pipe);
2023
2024         if (HAS_PCH_LPT(dev_priv->dev))
2025                 pch_transcoder = TRANSCODER_A;
2026         else
2027                 pch_transcoder = pipe;
2028
2029         /*
2030          * A pipe without a PLL won't actually be able to drive bits from
2031          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2032          * need the check.
2033          */
2034         if (!HAS_PCH_SPLIT(dev_priv->dev))
2035                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036                         assert_dsi_pll_enabled(dev_priv);
2037                 else
2038                         assert_pll_enabled(dev_priv, pipe);
2039         else {
2040                 if (crtc->config->has_pch_encoder) {
2041                         /* if driving the PCH, we need FDI enabled */
2042                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043                         assert_fdi_tx_pll_enabled(dev_priv,
2044                                                   (enum pipe) cpu_transcoder);
2045                 }
2046                 /* FIXME: assert CPU port conditions for SNB+ */
2047         }
2048
2049         reg = PIPECONF(cpu_transcoder);
2050         val = I915_READ(reg);
2051         if (val & PIPECONF_ENABLE) {
2052                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054                 return;
2055         }
2056
2057         I915_WRITE(reg, val | PIPECONF_ENABLE);
2058         POSTING_READ(reg);
2059 }
2060
2061 /**
2062  * intel_disable_pipe - disable a pipe, asserting requirements
2063  * @crtc: crtc whose pipes is to be disabled
2064  *
2065  * Disable the pipe of @crtc, making sure that various hardware
2066  * specific requirements are met, if applicable, e.g. plane
2067  * disabled, panel fitter off, etc.
2068  *
2069  * Will wait until the pipe has shut down before returning.
2070  */
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2072 {
2073         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075         enum pipe pipe = crtc->pipe;
2076         int reg;
2077         u32 val;
2078
2079         /*
2080          * Make sure planes won't keep trying to pump pixels to us,
2081          * or we might hang the display.
2082          */
2083         assert_planes_disabled(dev_priv, pipe);
2084         assert_cursor_disabled(dev_priv, pipe);
2085         assert_sprites_disabled(dev_priv, pipe);
2086
2087         reg = PIPECONF(cpu_transcoder);
2088         val = I915_READ(reg);
2089         if ((val & PIPECONF_ENABLE) == 0)
2090                 return;
2091
2092         /*
2093          * Double wide has implications for planes
2094          * so best keep it disabled when not needed.
2095          */
2096         if (crtc->config->double_wide)
2097                 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099         /* Don't disable pipe or pipe PLLs if needed */
2100         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102                 val &= ~PIPECONF_ENABLE;
2103
2104         I915_WRITE(reg, val);
2105         if ((val & PIPECONF_ENABLE) == 0)
2106                 intel_wait_for_pipe_off(crtc);
2107 }
2108
2109 /*
2110  * Plane regs are double buffered, going from enabled->disabled needs a
2111  * trigger in order to latch.  The display address reg provides this.
2112  */
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114                                enum plane plane)
2115 {
2116         struct drm_device *dev = dev_priv->dev;
2117         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2118
2119         I915_WRITE(reg, I915_READ(reg));
2120         POSTING_READ(reg);
2121 }
2122
2123 /**
2124  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125  * @plane:  plane to be enabled
2126  * @crtc: crtc for the plane
2127  *
2128  * Enable @plane on @crtc, making sure that the pipe is running first.
2129  */
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131                                           struct drm_crtc *crtc)
2132 {
2133         struct drm_device *dev = plane->dev;
2134         struct drm_i915_private *dev_priv = dev->dev_private;
2135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2139
2140         if (intel_crtc->primary_enabled)
2141                 return;
2142
2143         intel_crtc->primary_enabled = true;
2144
2145         dev_priv->display.update_primary_plane(crtc, plane->fb,
2146                                                crtc->x, crtc->y);
2147
2148         /*
2149          * BDW signals flip done immediately if the plane
2150          * is disabled, even if the plane enable is already
2151          * armed to occur at the next vblank :(
2152          */
2153         if (IS_BROADWELL(dev))
2154                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 }
2156
2157 /**
2158  * intel_disable_primary_hw_plane - disable the primary hardware plane
2159  * @plane: plane to be disabled
2160  * @crtc: crtc for the plane
2161  *
2162  * Disable @plane on @crtc, making sure that the pipe is running first.
2163  */
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165                                            struct drm_crtc *crtc)
2166 {
2167         struct drm_device *dev = plane->dev;
2168         struct drm_i915_private *dev_priv = dev->dev_private;
2169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
2171         if (WARN_ON(!intel_crtc->active))
2172                 return;
2173
2174         if (!intel_crtc->primary_enabled)
2175                 return;
2176
2177         intel_crtc->primary_enabled = false;
2178
2179         dev_priv->display.update_primary_plane(crtc, plane->fb,
2180                                                crtc->x, crtc->y);
2181 }
2182
2183 static bool need_vtd_wa(struct drm_device *dev)
2184 {
2185 #ifdef CONFIG_INTEL_IOMMU
2186         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187                 return true;
2188 #endif
2189         return false;
2190 }
2191
2192 int
2193 intel_fb_align_height(struct drm_device *dev, int height,
2194                       uint32_t pixel_format,
2195                       uint64_t fb_format_modifier)
2196 {
2197         int tile_height;
2198         uint32_t bits_per_pixel;
2199
2200         switch (fb_format_modifier) {
2201         case DRM_FORMAT_MOD_NONE:
2202                 tile_height = 1;
2203                 break;
2204         case I915_FORMAT_MOD_X_TILED:
2205                 tile_height = IS_GEN2(dev) ? 16 : 8;
2206                 break;
2207         case I915_FORMAT_MOD_Y_TILED:
2208                 tile_height = 32;
2209                 break;
2210         case I915_FORMAT_MOD_Yf_TILED:
2211                 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2212                 switch (bits_per_pixel) {
2213                 default:
2214                 case 8:
2215                         tile_height = 64;
2216                         break;
2217                 case 16:
2218                 case 32:
2219                         tile_height = 32;
2220                         break;
2221                 case 64:
2222                         tile_height = 16;
2223                         break;
2224                 case 128:
2225                         WARN_ONCE(1,
2226                                   "128-bit pixels are not supported for display!");
2227                         tile_height = 16;
2228                         break;
2229                 }
2230                 break;
2231         default:
2232                 MISSING_CASE(fb_format_modifier);
2233                 tile_height = 1;
2234                 break;
2235         }
2236
2237         return ALIGN(height, tile_height);
2238 }
2239
2240 int
2241 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2242                            struct drm_framebuffer *fb,
2243                            struct intel_engine_cs *pipelined)
2244 {
2245         struct drm_device *dev = fb->dev;
2246         struct drm_i915_private *dev_priv = dev->dev_private;
2247         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248         u32 alignment;
2249         int ret;
2250
2251         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2252
2253         switch (fb->modifier[0]) {
2254         case DRM_FORMAT_MOD_NONE:
2255                 if (INTEL_INFO(dev)->gen >= 9)
2256                         alignment = 256 * 1024;
2257                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2258                         alignment = 128 * 1024;
2259                 else if (INTEL_INFO(dev)->gen >= 4)
2260                         alignment = 4 * 1024;
2261                 else
2262                         alignment = 64 * 1024;
2263                 break;
2264         case I915_FORMAT_MOD_X_TILED:
2265                 if (INTEL_INFO(dev)->gen >= 9)
2266                         alignment = 256 * 1024;
2267                 else {
2268                         /* pin() will align the object as required by fence */
2269                         alignment = 0;
2270                 }
2271                 break;
2272         case I915_FORMAT_MOD_Y_TILED:
2273         case I915_FORMAT_MOD_Yf_TILED:
2274                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2275                           "Y tiling bo slipped through, driver bug!\n"))
2276                         return -EINVAL;
2277                 alignment = 1 * 1024 * 1024;
2278                 break;
2279         default:
2280                 MISSING_CASE(fb->modifier[0]);
2281                 return -EINVAL;
2282         }
2283
2284         /* Note that the w/a also requires 64 PTE of padding following the
2285          * bo. We currently fill all unused PTE with the shadow page and so
2286          * we should always have valid PTE following the scanout preventing
2287          * the VT-d warning.
2288          */
2289         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2290                 alignment = 256 * 1024;
2291
2292         /*
2293          * Global gtt pte registers are special registers which actually forward
2294          * writes to a chunk of system memory. Which means that there is no risk
2295          * that the register values disappear as soon as we call
2296          * intel_runtime_pm_put(), so it is correct to wrap only the
2297          * pin/unpin/fence and not more.
2298          */
2299         intel_runtime_pm_get(dev_priv);
2300
2301         dev_priv->mm.interruptible = false;
2302         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2303         if (ret)
2304                 goto err_interruptible;
2305
2306         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2307          * fence, whereas 965+ only requires a fence if using
2308          * framebuffer compression.  For simplicity, we always install
2309          * a fence as the cost is not that onerous.
2310          */
2311         ret = i915_gem_object_get_fence(obj);
2312         if (ret)
2313                 goto err_unpin;
2314
2315         i915_gem_object_pin_fence(obj);
2316
2317         dev_priv->mm.interruptible = true;
2318         intel_runtime_pm_put(dev_priv);
2319         return 0;
2320
2321 err_unpin:
2322         i915_gem_object_unpin_from_display_plane(obj);
2323 err_interruptible:
2324         dev_priv->mm.interruptible = true;
2325         intel_runtime_pm_put(dev_priv);
2326         return ret;
2327 }
2328
2329 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2330 {
2331         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2332
2333         i915_gem_object_unpin_fence(obj);
2334         i915_gem_object_unpin_from_display_plane(obj);
2335 }
2336
2337 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2338  * is assumed to be a power-of-two. */
2339 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2340                                              unsigned int tiling_mode,
2341                                              unsigned int cpp,
2342                                              unsigned int pitch)
2343 {
2344         if (tiling_mode != I915_TILING_NONE) {
2345                 unsigned int tile_rows, tiles;
2346
2347                 tile_rows = *y / 8;
2348                 *y %= 8;
2349
2350                 tiles = *x / (512/cpp);
2351                 *x %= 512/cpp;
2352
2353                 return tile_rows * pitch * 8 + tiles * 4096;
2354         } else {
2355                 unsigned int offset;
2356
2357                 offset = *y * pitch + *x * cpp;
2358                 *y = 0;
2359                 *x = (offset & 4095) / cpp;
2360                 return offset & -4096;
2361         }
2362 }
2363
2364 static int i9xx_format_to_fourcc(int format)
2365 {
2366         switch (format) {
2367         case DISPPLANE_8BPP:
2368                 return DRM_FORMAT_C8;
2369         case DISPPLANE_BGRX555:
2370                 return DRM_FORMAT_XRGB1555;
2371         case DISPPLANE_BGRX565:
2372                 return DRM_FORMAT_RGB565;
2373         default:
2374         case DISPPLANE_BGRX888:
2375                 return DRM_FORMAT_XRGB8888;
2376         case DISPPLANE_RGBX888:
2377                 return DRM_FORMAT_XBGR8888;
2378         case DISPPLANE_BGRX101010:
2379                 return DRM_FORMAT_XRGB2101010;
2380         case DISPPLANE_RGBX101010:
2381                 return DRM_FORMAT_XBGR2101010;
2382         }
2383 }
2384
2385 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2386 {
2387         switch (format) {
2388         case PLANE_CTL_FORMAT_RGB_565:
2389                 return DRM_FORMAT_RGB565;
2390         default:
2391         case PLANE_CTL_FORMAT_XRGB_8888:
2392                 if (rgb_order) {
2393                         if (alpha)
2394                                 return DRM_FORMAT_ABGR8888;
2395                         else
2396                                 return DRM_FORMAT_XBGR8888;
2397                 } else {
2398                         if (alpha)
2399                                 return DRM_FORMAT_ARGB8888;
2400                         else
2401                                 return DRM_FORMAT_XRGB8888;
2402                 }
2403         case PLANE_CTL_FORMAT_XRGB_2101010:
2404                 if (rgb_order)
2405                         return DRM_FORMAT_XBGR2101010;
2406                 else
2407                         return DRM_FORMAT_XRGB2101010;
2408         }
2409 }
2410
2411 static bool
2412 intel_alloc_plane_obj(struct intel_crtc *crtc,
2413                       struct intel_initial_plane_config *plane_config)
2414 {
2415         struct drm_device *dev = crtc->base.dev;
2416         struct drm_i915_gem_object *obj = NULL;
2417         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2418         struct drm_framebuffer *fb = &plane_config->fb->base;
2419         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2420         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2421                                     PAGE_SIZE);
2422
2423         size_aligned -= base_aligned;
2424
2425         if (plane_config->size == 0)
2426                 return false;
2427
2428         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2429                                                              base_aligned,
2430                                                              base_aligned,
2431                                                              size_aligned);
2432         if (!obj)
2433                 return false;
2434
2435         obj->tiling_mode = plane_config->tiling;
2436         if (obj->tiling_mode == I915_TILING_X)
2437                 obj->stride = fb->pitches[0];
2438
2439         mode_cmd.pixel_format = fb->pixel_format;
2440         mode_cmd.width = fb->width;
2441         mode_cmd.height = fb->height;
2442         mode_cmd.pitches[0] = fb->pitches[0];
2443         mode_cmd.modifier[0] = fb->modifier[0];
2444         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2445
2446         mutex_lock(&dev->struct_mutex);
2447
2448         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2449                                    &mode_cmd, obj)) {
2450                 DRM_DEBUG_KMS("intel fb init failed\n");
2451                 goto out_unref_obj;
2452         }
2453
2454         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2455         mutex_unlock(&dev->struct_mutex);
2456
2457         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2458         return true;
2459
2460 out_unref_obj:
2461         drm_gem_object_unreference(&obj->base);
2462         mutex_unlock(&dev->struct_mutex);
2463         return false;
2464 }
2465
2466 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2467 static void
2468 update_state_fb(struct drm_plane *plane)
2469 {
2470         if (plane->fb == plane->state->fb)
2471                 return;
2472
2473         if (plane->state->fb)
2474                 drm_framebuffer_unreference(plane->state->fb);
2475         plane->state->fb = plane->fb;
2476         if (plane->state->fb)
2477                 drm_framebuffer_reference(plane->state->fb);
2478 }
2479
2480 static void
2481 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2482                      struct intel_initial_plane_config *plane_config)
2483 {
2484         struct drm_device *dev = intel_crtc->base.dev;
2485         struct drm_i915_private *dev_priv = dev->dev_private;
2486         struct drm_crtc *c;
2487         struct intel_crtc *i;
2488         struct drm_i915_gem_object *obj;
2489
2490         if (!plane_config->fb)
2491                 return;
2492
2493         if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2494                 struct drm_plane *primary = intel_crtc->base.primary;
2495
2496                 primary->fb = &plane_config->fb->base;
2497                 primary->state->crtc = &intel_crtc->base;
2498                 update_state_fb(primary);
2499
2500                 return;
2501         }
2502
2503         kfree(plane_config->fb);
2504
2505         /*
2506          * Failed to alloc the obj, check to see if we should share
2507          * an fb with another CRTC instead
2508          */
2509         for_each_crtc(dev, c) {
2510                 i = to_intel_crtc(c);
2511
2512                 if (c == &intel_crtc->base)
2513                         continue;
2514
2515                 if (!i->active)
2516                         continue;
2517
2518                 obj = intel_fb_obj(c->primary->fb);
2519                 if (obj == NULL)
2520                         continue;
2521
2522                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2523                         struct drm_plane *primary = intel_crtc->base.primary;
2524
2525                         if (obj->tiling_mode != I915_TILING_NONE)
2526                                 dev_priv->preserve_bios_swizzle = true;
2527
2528                         drm_framebuffer_reference(c->primary->fb);
2529                         primary->fb = c->primary->fb;
2530                         primary->state->crtc = &intel_crtc->base;
2531                         update_state_fb(intel_crtc->base.primary);
2532                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2533                         break;
2534                 }
2535         }
2536
2537 }
2538
2539 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2540                                       struct drm_framebuffer *fb,
2541                                       int x, int y)
2542 {
2543         struct drm_device *dev = crtc->dev;
2544         struct drm_i915_private *dev_priv = dev->dev_private;
2545         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2546         struct drm_i915_gem_object *obj;
2547         int plane = intel_crtc->plane;
2548         unsigned long linear_offset;
2549         u32 dspcntr;
2550         u32 reg = DSPCNTR(plane);
2551         int pixel_size;
2552
2553         if (!intel_crtc->primary_enabled) {
2554                 I915_WRITE(reg, 0);
2555                 if (INTEL_INFO(dev)->gen >= 4)
2556                         I915_WRITE(DSPSURF(plane), 0);
2557                 else
2558                         I915_WRITE(DSPADDR(plane), 0);
2559                 POSTING_READ(reg);
2560                 return;
2561         }
2562
2563         obj = intel_fb_obj(fb);
2564         if (WARN_ON(obj == NULL))
2565                 return;
2566
2567         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2568
2569         dspcntr = DISPPLANE_GAMMA_ENABLE;
2570
2571         dspcntr |= DISPLAY_PLANE_ENABLE;
2572
2573         if (INTEL_INFO(dev)->gen < 4) {
2574                 if (intel_crtc->pipe == PIPE_B)
2575                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2576
2577                 /* pipesrc and dspsize control the size that is scaled from,
2578                  * which should always be the user's requested size.
2579                  */
2580                 I915_WRITE(DSPSIZE(plane),
2581                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2582                            (intel_crtc->config->pipe_src_w - 1));
2583                 I915_WRITE(DSPPOS(plane), 0);
2584         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2585                 I915_WRITE(PRIMSIZE(plane),
2586                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2587                            (intel_crtc->config->pipe_src_w - 1));
2588                 I915_WRITE(PRIMPOS(plane), 0);
2589                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2590         }
2591
2592         switch (fb->pixel_format) {
2593         case DRM_FORMAT_C8:
2594                 dspcntr |= DISPPLANE_8BPP;
2595                 break;
2596         case DRM_FORMAT_XRGB1555:
2597         case DRM_FORMAT_ARGB1555:
2598                 dspcntr |= DISPPLANE_BGRX555;
2599                 break;
2600         case DRM_FORMAT_RGB565:
2601                 dspcntr |= DISPPLANE_BGRX565;
2602                 break;
2603         case DRM_FORMAT_XRGB8888:
2604         case DRM_FORMAT_ARGB8888:
2605                 dspcntr |= DISPPLANE_BGRX888;
2606                 break;
2607         case DRM_FORMAT_XBGR8888:
2608         case DRM_FORMAT_ABGR8888:
2609                 dspcntr |= DISPPLANE_RGBX888;
2610                 break;
2611         case DRM_FORMAT_XRGB2101010:
2612         case DRM_FORMAT_ARGB2101010:
2613                 dspcntr |= DISPPLANE_BGRX101010;
2614                 break;
2615         case DRM_FORMAT_XBGR2101010:
2616         case DRM_FORMAT_ABGR2101010:
2617                 dspcntr |= DISPPLANE_RGBX101010;
2618                 break;
2619         default:
2620                 BUG();
2621         }
2622
2623         if (INTEL_INFO(dev)->gen >= 4 &&
2624             obj->tiling_mode != I915_TILING_NONE)
2625                 dspcntr |= DISPPLANE_TILED;
2626
2627         if (IS_G4X(dev))
2628                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2629
2630         linear_offset = y * fb->pitches[0] + x * pixel_size;
2631
2632         if (INTEL_INFO(dev)->gen >= 4) {
2633                 intel_crtc->dspaddr_offset =
2634                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2635                                                        pixel_size,
2636                                                        fb->pitches[0]);
2637                 linear_offset -= intel_crtc->dspaddr_offset;
2638         } else {
2639                 intel_crtc->dspaddr_offset = linear_offset;
2640         }
2641
2642         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2643                 dspcntr |= DISPPLANE_ROTATE_180;
2644
2645                 x += (intel_crtc->config->pipe_src_w - 1);
2646                 y += (intel_crtc->config->pipe_src_h - 1);
2647
2648                 /* Finding the last pixel of the last line of the display
2649                 data and adding to linear_offset*/
2650                 linear_offset +=
2651                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2652                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2653         }
2654
2655         I915_WRITE(reg, dspcntr);
2656
2657         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2658                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2659                       fb->pitches[0]);
2660         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2661         if (INTEL_INFO(dev)->gen >= 4) {
2662                 I915_WRITE(DSPSURF(plane),
2663                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2664                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2665                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2666         } else
2667                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2668         POSTING_READ(reg);
2669 }
2670
2671 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2672                                           struct drm_framebuffer *fb,
2673                                           int x, int y)
2674 {
2675         struct drm_device *dev = crtc->dev;
2676         struct drm_i915_private *dev_priv = dev->dev_private;
2677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2678         struct drm_i915_gem_object *obj;
2679         int plane = intel_crtc->plane;
2680         unsigned long linear_offset;
2681         u32 dspcntr;
2682         u32 reg = DSPCNTR(plane);
2683         int pixel_size;
2684
2685         if (!intel_crtc->primary_enabled) {
2686                 I915_WRITE(reg, 0);
2687                 I915_WRITE(DSPSURF(plane), 0);
2688                 POSTING_READ(reg);
2689                 return;
2690         }
2691
2692         obj = intel_fb_obj(fb);
2693         if (WARN_ON(obj == NULL))
2694                 return;
2695
2696         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2697
2698         dspcntr = DISPPLANE_GAMMA_ENABLE;
2699
2700         dspcntr |= DISPLAY_PLANE_ENABLE;
2701
2702         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2703                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2704
2705         switch (fb->pixel_format) {
2706         case DRM_FORMAT_C8:
2707                 dspcntr |= DISPPLANE_8BPP;
2708                 break;
2709         case DRM_FORMAT_RGB565:
2710                 dspcntr |= DISPPLANE_BGRX565;
2711                 break;
2712         case DRM_FORMAT_XRGB8888:
2713         case DRM_FORMAT_ARGB8888:
2714                 dspcntr |= DISPPLANE_BGRX888;
2715                 break;
2716         case DRM_FORMAT_XBGR8888:
2717         case DRM_FORMAT_ABGR8888:
2718                 dspcntr |= DISPPLANE_RGBX888;
2719                 break;
2720         case DRM_FORMAT_XRGB2101010:
2721         case DRM_FORMAT_ARGB2101010:
2722                 dspcntr |= DISPPLANE_BGRX101010;
2723                 break;
2724         case DRM_FORMAT_XBGR2101010:
2725         case DRM_FORMAT_ABGR2101010:
2726                 dspcntr |= DISPPLANE_RGBX101010;
2727                 break;
2728         default:
2729                 BUG();
2730         }
2731
2732         if (obj->tiling_mode != I915_TILING_NONE)
2733                 dspcntr |= DISPPLANE_TILED;
2734
2735         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2736                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
2738         linear_offset = y * fb->pitches[0] + x * pixel_size;
2739         intel_crtc->dspaddr_offset =
2740                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2741                                                pixel_size,
2742                                                fb->pitches[0]);
2743         linear_offset -= intel_crtc->dspaddr_offset;
2744         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2745                 dspcntr |= DISPPLANE_ROTATE_180;
2746
2747                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2748                         x += (intel_crtc->config->pipe_src_w - 1);
2749                         y += (intel_crtc->config->pipe_src_h - 1);
2750
2751                         /* Finding the last pixel of the last line of the display
2752                         data and adding to linear_offset*/
2753                         linear_offset +=
2754                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2755                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2756                 }
2757         }
2758
2759         I915_WRITE(reg, dspcntr);
2760
2761         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2762                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2763                       fb->pitches[0]);
2764         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2765         I915_WRITE(DSPSURF(plane),
2766                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2767         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2768                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2769         } else {
2770                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2771                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2772         }
2773         POSTING_READ(reg);
2774 }
2775
2776 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2777                               uint32_t pixel_format)
2778 {
2779         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2780
2781         /*
2782          * The stride is either expressed as a multiple of 64 bytes
2783          * chunks for linear buffers or in number of tiles for tiled
2784          * buffers.
2785          */
2786         switch (fb_modifier) {
2787         case DRM_FORMAT_MOD_NONE:
2788                 return 64;
2789         case I915_FORMAT_MOD_X_TILED:
2790                 if (INTEL_INFO(dev)->gen == 2)
2791                         return 128;
2792                 return 512;
2793         case I915_FORMAT_MOD_Y_TILED:
2794                 /* No need to check for old gens and Y tiling since this is
2795                  * about the display engine and those will be blocked before
2796                  * we get here.
2797                  */
2798                 return 128;
2799         case I915_FORMAT_MOD_Yf_TILED:
2800                 if (bits_per_pixel == 8)
2801                         return 64;
2802                 else
2803                         return 128;
2804         default:
2805                 MISSING_CASE(fb_modifier);
2806                 return 64;
2807         }
2808 }
2809
2810 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2811                                          struct drm_framebuffer *fb,
2812                                          int x, int y)
2813 {
2814         struct drm_device *dev = crtc->dev;
2815         struct drm_i915_private *dev_priv = dev->dev_private;
2816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2817         struct drm_i915_gem_object *obj;
2818         int pipe = intel_crtc->pipe;
2819         u32 plane_ctl, stride_div;
2820
2821         if (!intel_crtc->primary_enabled) {
2822                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2823                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2824                 POSTING_READ(PLANE_CTL(pipe, 0));
2825                 return;
2826         }
2827
2828         plane_ctl = PLANE_CTL_ENABLE |
2829                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2830                     PLANE_CTL_PIPE_CSC_ENABLE;
2831
2832         switch (fb->pixel_format) {
2833         case DRM_FORMAT_RGB565:
2834                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2835                 break;
2836         case DRM_FORMAT_XRGB8888:
2837                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2838                 break;
2839         case DRM_FORMAT_ARGB8888:
2840                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2841                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2842                 break;
2843         case DRM_FORMAT_XBGR8888:
2844                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2845                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2846                 break;
2847         case DRM_FORMAT_ABGR8888:
2848                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2849                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2850                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2851                 break;
2852         case DRM_FORMAT_XRGB2101010:
2853                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2854                 break;
2855         case DRM_FORMAT_XBGR2101010:
2856                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2857                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2858                 break;
2859         default:
2860                 BUG();
2861         }
2862
2863         switch (fb->modifier[0]) {
2864         case DRM_FORMAT_MOD_NONE:
2865                 break;
2866         case I915_FORMAT_MOD_X_TILED:
2867                 plane_ctl |= PLANE_CTL_TILED_X;
2868                 break;
2869         case I915_FORMAT_MOD_Y_TILED:
2870                 plane_ctl |= PLANE_CTL_TILED_Y;
2871                 break;
2872         case I915_FORMAT_MOD_Yf_TILED:
2873                 plane_ctl |= PLANE_CTL_TILED_YF;
2874                 break;
2875         default:
2876                 MISSING_CASE(fb->modifier[0]);
2877         }
2878
2879         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2880         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2881                 plane_ctl |= PLANE_CTL_ROTATE_180;
2882
2883         obj = intel_fb_obj(fb);
2884         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2885                                                fb->pixel_format);
2886
2887         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2888
2889         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2890                       i915_gem_obj_ggtt_offset(obj),
2891                       x, y, fb->width, fb->height,
2892                       fb->pitches[0]);
2893
2894         I915_WRITE(PLANE_POS(pipe, 0), 0);
2895         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2896         I915_WRITE(PLANE_SIZE(pipe, 0),
2897                    (intel_crtc->config->pipe_src_h - 1) << 16 |
2898                    (intel_crtc->config->pipe_src_w - 1));
2899         I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2900         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2901
2902         POSTING_READ(PLANE_SURF(pipe, 0));
2903 }
2904
2905 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2906 static int
2907 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2908                            int x, int y, enum mode_set_atomic state)
2909 {
2910         struct drm_device *dev = crtc->dev;
2911         struct drm_i915_private *dev_priv = dev->dev_private;
2912
2913         if (dev_priv->display.disable_fbc)
2914                 dev_priv->display.disable_fbc(dev);
2915
2916         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2917
2918         return 0;
2919 }
2920
2921 static void intel_complete_page_flips(struct drm_device *dev)
2922 {
2923         struct drm_crtc *crtc;
2924
2925         for_each_crtc(dev, crtc) {
2926                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2927                 enum plane plane = intel_crtc->plane;
2928
2929                 intel_prepare_page_flip(dev, plane);
2930                 intel_finish_page_flip_plane(dev, plane);
2931         }
2932 }
2933
2934 static void intel_update_primary_planes(struct drm_device *dev)
2935 {
2936         struct drm_i915_private *dev_priv = dev->dev_private;
2937         struct drm_crtc *crtc;
2938
2939         for_each_crtc(dev, crtc) {
2940                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2941
2942                 drm_modeset_lock(&crtc->mutex, NULL);
2943                 /*
2944                  * FIXME: Once we have proper support for primary planes (and
2945                  * disabling them without disabling the entire crtc) allow again
2946                  * a NULL crtc->primary->fb.
2947                  */
2948                 if (intel_crtc->active && crtc->primary->fb)
2949                         dev_priv->display.update_primary_plane(crtc,
2950                                                                crtc->primary->fb,
2951                                                                crtc->x,
2952                                                                crtc->y);
2953                 drm_modeset_unlock(&crtc->mutex);
2954         }
2955 }
2956
2957 void intel_prepare_reset(struct drm_device *dev)
2958 {
2959         struct drm_i915_private *dev_priv = to_i915(dev);
2960         struct intel_crtc *crtc;
2961
2962         /* no reset support for gen2 */
2963         if (IS_GEN2(dev))
2964                 return;
2965
2966         /* reset doesn't touch the display */
2967         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2968                 return;
2969
2970         drm_modeset_lock_all(dev);
2971
2972         /*
2973          * Disabling the crtcs gracefully seems nicer. Also the
2974          * g33 docs say we should at least disable all the planes.
2975          */
2976         for_each_intel_crtc(dev, crtc) {
2977                 if (crtc->active)
2978                         dev_priv->display.crtc_disable(&crtc->base);
2979         }
2980 }
2981
2982 void intel_finish_reset(struct drm_device *dev)
2983 {
2984         struct drm_i915_private *dev_priv = to_i915(dev);
2985
2986         /*
2987          * Flips in the rings will be nuked by the reset,
2988          * so complete all pending flips so that user space
2989          * will get its events and not get stuck.
2990          */
2991         intel_complete_page_flips(dev);
2992
2993         /* no reset support for gen2 */
2994         if (IS_GEN2(dev))
2995                 return;
2996
2997         /* reset doesn't touch the display */
2998         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2999                 /*
3000                  * Flips in the rings have been nuked by the reset,
3001                  * so update the base address of all primary
3002                  * planes to the the last fb to make sure we're
3003                  * showing the correct fb after a reset.
3004                  */
3005                 intel_update_primary_planes(dev);
3006                 return;
3007         }
3008
3009         /*
3010          * The display has been reset as well,
3011          * so need a full re-initialization.
3012          */
3013         intel_runtime_pm_disable_interrupts(dev_priv);
3014         intel_runtime_pm_enable_interrupts(dev_priv);
3015
3016         intel_modeset_init_hw(dev);
3017
3018         spin_lock_irq(&dev_priv->irq_lock);
3019         if (dev_priv->display.hpd_irq_setup)
3020                 dev_priv->display.hpd_irq_setup(dev);
3021         spin_unlock_irq(&dev_priv->irq_lock);
3022
3023         intel_modeset_setup_hw_state(dev, true);
3024
3025         intel_hpd_init(dev_priv);
3026
3027         drm_modeset_unlock_all(dev);
3028 }
3029
3030 static int
3031 intel_finish_fb(struct drm_framebuffer *old_fb)
3032 {
3033         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3034         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3035         bool was_interruptible = dev_priv->mm.interruptible;
3036         int ret;
3037
3038         /* Big Hammer, we also need to ensure that any pending
3039          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3040          * current scanout is retired before unpinning the old
3041          * framebuffer.
3042          *
3043          * This should only fail upon a hung GPU, in which case we
3044          * can safely continue.
3045          */
3046         dev_priv->mm.interruptible = false;
3047         ret = i915_gem_object_finish_gpu(obj);
3048         dev_priv->mm.interruptible = was_interruptible;
3049
3050         return ret;
3051 }
3052
3053 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3054 {
3055         struct drm_device *dev = crtc->dev;
3056         struct drm_i915_private *dev_priv = dev->dev_private;
3057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3058         bool pending;
3059
3060         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3061             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3062                 return false;
3063
3064         spin_lock_irq(&dev->event_lock);
3065         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3066         spin_unlock_irq(&dev->event_lock);
3067
3068         return pending;
3069 }
3070
3071 static void intel_update_pipe_size(struct intel_crtc *crtc)
3072 {
3073         struct drm_device *dev = crtc->base.dev;
3074         struct drm_i915_private *dev_priv = dev->dev_private;
3075         const struct drm_display_mode *adjusted_mode;
3076
3077         if (!i915.fastboot)
3078                 return;
3079
3080         /*
3081          * Update pipe size and adjust fitter if needed: the reason for this is
3082          * that in compute_mode_changes we check the native mode (not the pfit
3083          * mode) to see if we can flip rather than do a full mode set. In the
3084          * fastboot case, we'll flip, but if we don't update the pipesrc and
3085          * pfit state, we'll end up with a big fb scanned out into the wrong
3086          * sized surface.
3087          *
3088          * To fix this properly, we need to hoist the checks up into
3089          * compute_mode_changes (or above), check the actual pfit state and
3090          * whether the platform allows pfit disable with pipe active, and only
3091          * then update the pipesrc and pfit state, even on the flip path.
3092          */
3093
3094         adjusted_mode = &crtc->config->base.adjusted_mode;
3095
3096         I915_WRITE(PIPESRC(crtc->pipe),
3097                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3098                    (adjusted_mode->crtc_vdisplay - 1));
3099         if (!crtc->config->pch_pfit.enabled &&
3100             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3101              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3102                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3103                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3104                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3105         }
3106         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3107         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3108 }
3109
3110 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3111 {
3112         struct drm_device *dev = crtc->dev;
3113         struct drm_i915_private *dev_priv = dev->dev_private;
3114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3115         int pipe = intel_crtc->pipe;
3116         u32 reg, temp;
3117
3118         /* enable normal train */
3119         reg = FDI_TX_CTL(pipe);
3120         temp = I915_READ(reg);
3121         if (IS_IVYBRIDGE(dev)) {
3122                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3123                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3124         } else {
3125                 temp &= ~FDI_LINK_TRAIN_NONE;
3126                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3127         }
3128         I915_WRITE(reg, temp);
3129
3130         reg = FDI_RX_CTL(pipe);
3131         temp = I915_READ(reg);
3132         if (HAS_PCH_CPT(dev)) {
3133                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3134                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3135         } else {
3136                 temp &= ~FDI_LINK_TRAIN_NONE;
3137                 temp |= FDI_LINK_TRAIN_NONE;
3138         }
3139         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3140
3141         /* wait one idle pattern time */
3142         POSTING_READ(reg);
3143         udelay(1000);
3144
3145         /* IVB wants error correction enabled */
3146         if (IS_IVYBRIDGE(dev))
3147                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3148                            FDI_FE_ERRC_ENABLE);
3149 }
3150
3151 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3152 {
3153         return crtc->base.state->enable && crtc->active &&
3154                 crtc->config->has_pch_encoder;
3155 }
3156
3157 static void ivb_modeset_global_resources(struct drm_device *dev)
3158 {
3159         struct drm_i915_private *dev_priv = dev->dev_private;
3160         struct intel_crtc *pipe_B_crtc =
3161                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3162         struct intel_crtc *pipe_C_crtc =
3163                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3164         uint32_t temp;
3165
3166         /*
3167          * When everything is off disable fdi C so that we could enable fdi B
3168          * with all lanes. Note that we don't care about enabled pipes without
3169          * an enabled pch encoder.
3170          */
3171         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3172             !pipe_has_enabled_pch(pipe_C_crtc)) {
3173                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3174                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3175
3176                 temp = I915_READ(SOUTH_CHICKEN1);
3177                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3178                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3179                 I915_WRITE(SOUTH_CHICKEN1, temp);
3180         }
3181 }
3182
3183 /* The FDI link training functions for ILK/Ibexpeak. */
3184 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3185 {
3186         struct drm_device *dev = crtc->dev;
3187         struct drm_i915_private *dev_priv = dev->dev_private;
3188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189         int pipe = intel_crtc->pipe;
3190         u32 reg, temp, tries;
3191
3192         /* FDI needs bits from pipe first */
3193         assert_pipe_enabled(dev_priv, pipe);
3194
3195         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3196            for train result */
3197         reg = FDI_RX_IMR(pipe);
3198         temp = I915_READ(reg);
3199         temp &= ~FDI_RX_SYMBOL_LOCK;
3200         temp &= ~FDI_RX_BIT_LOCK;
3201         I915_WRITE(reg, temp);
3202         I915_READ(reg);
3203         udelay(150);
3204
3205         /* enable CPU FDI TX and PCH FDI RX */
3206         reg = FDI_TX_CTL(pipe);
3207         temp = I915_READ(reg);
3208         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3209         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3210         temp &= ~FDI_LINK_TRAIN_NONE;
3211         temp |= FDI_LINK_TRAIN_PATTERN_1;
3212         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3213
3214         reg = FDI_RX_CTL(pipe);
3215         temp = I915_READ(reg);
3216         temp &= ~FDI_LINK_TRAIN_NONE;
3217         temp |= FDI_LINK_TRAIN_PATTERN_1;
3218         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3219
3220         POSTING_READ(reg);
3221         udelay(150);
3222
3223         /* Ironlake workaround, enable clock pointer after FDI enable*/
3224         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3225         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3226                    FDI_RX_PHASE_SYNC_POINTER_EN);
3227
3228         reg = FDI_RX_IIR(pipe);
3229         for (tries = 0; tries < 5; tries++) {
3230                 temp = I915_READ(reg);
3231                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3232
3233                 if ((temp & FDI_RX_BIT_LOCK)) {
3234                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3235                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3236                         break;
3237                 }
3238         }
3239         if (tries == 5)
3240                 DRM_ERROR("FDI train 1 fail!\n");
3241
3242         /* Train 2 */
3243         reg = FDI_TX_CTL(pipe);
3244         temp = I915_READ(reg);
3245         temp &= ~FDI_LINK_TRAIN_NONE;
3246         temp |= FDI_LINK_TRAIN_PATTERN_2;
3247         I915_WRITE(reg, temp);
3248
3249         reg = FDI_RX_CTL(pipe);
3250         temp = I915_READ(reg);
3251         temp &= ~FDI_LINK_TRAIN_NONE;
3252         temp |= FDI_LINK_TRAIN_PATTERN_2;
3253         I915_WRITE(reg, temp);
3254
3255         POSTING_READ(reg);
3256         udelay(150);
3257
3258         reg = FDI_RX_IIR(pipe);
3259         for (tries = 0; tries < 5; tries++) {
3260                 temp = I915_READ(reg);
3261                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3262
3263                 if (temp & FDI_RX_SYMBOL_LOCK) {
3264                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3265                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3266                         break;
3267                 }
3268         }
3269         if (tries == 5)
3270                 DRM_ERROR("FDI train 2 fail!\n");
3271
3272         DRM_DEBUG_KMS("FDI train done\n");
3273
3274 }
3275
3276 static const int snb_b_fdi_train_param[] = {
3277         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3278         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3279         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3280         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3281 };
3282
3283 /* The FDI link training functions for SNB/Cougarpoint. */
3284 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3285 {
3286         struct drm_device *dev = crtc->dev;
3287         struct drm_i915_private *dev_priv = dev->dev_private;
3288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3289         int pipe = intel_crtc->pipe;
3290         u32 reg, temp, i, retry;
3291
3292         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3293            for train result */
3294         reg = FDI_RX_IMR(pipe);
3295         temp = I915_READ(reg);
3296         temp &= ~FDI_RX_SYMBOL_LOCK;
3297         temp &= ~FDI_RX_BIT_LOCK;
3298         I915_WRITE(reg, temp);
3299
3300         POSTING_READ(reg);
3301         udelay(150);
3302
3303         /* enable CPU FDI TX and PCH FDI RX */
3304         reg = FDI_TX_CTL(pipe);
3305         temp = I915_READ(reg);
3306         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3307         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3308         temp &= ~FDI_LINK_TRAIN_NONE;
3309         temp |= FDI_LINK_TRAIN_PATTERN_1;
3310         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3311         /* SNB-B */
3312         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3313         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3314
3315         I915_WRITE(FDI_RX_MISC(pipe),
3316                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3317
3318         reg = FDI_RX_CTL(pipe);
3319         temp = I915_READ(reg);
3320         if (HAS_PCH_CPT(dev)) {
3321                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3322                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3323         } else {
3324                 temp &= ~FDI_LINK_TRAIN_NONE;
3325                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3326         }
3327         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3328
3329         POSTING_READ(reg);
3330         udelay(150);
3331
3332         for (i = 0; i < 4; i++) {
3333                 reg = FDI_TX_CTL(pipe);
3334                 temp = I915_READ(reg);
3335                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3336                 temp |= snb_b_fdi_train_param[i];
3337                 I915_WRITE(reg, temp);
3338
3339                 POSTING_READ(reg);
3340                 udelay(500);
3341
3342                 for (retry = 0; retry < 5; retry++) {
3343                         reg = FDI_RX_IIR(pipe);
3344                         temp = I915_READ(reg);
3345                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3346                         if (temp & FDI_RX_BIT_LOCK) {
3347                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3348                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3349                                 break;
3350                         }
3351                         udelay(50);
3352                 }
3353                 if (retry < 5)
3354                         break;
3355         }
3356         if (i == 4)
3357                 DRM_ERROR("FDI train 1 fail!\n");
3358
3359         /* Train 2 */
3360         reg = FDI_TX_CTL(pipe);
3361         temp = I915_READ(reg);
3362         temp &= ~FDI_LINK_TRAIN_NONE;
3363         temp |= FDI_LINK_TRAIN_PATTERN_2;
3364         if (IS_GEN6(dev)) {
3365                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3366                 /* SNB-B */
3367                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3368         }
3369         I915_WRITE(reg, temp);
3370
3371         reg = FDI_RX_CTL(pipe);
3372         temp = I915_READ(reg);
3373         if (HAS_PCH_CPT(dev)) {
3374                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3375                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3376         } else {
3377                 temp &= ~FDI_LINK_TRAIN_NONE;
3378                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3379         }
3380         I915_WRITE(reg, temp);
3381
3382         POSTING_READ(reg);
3383         udelay(150);
3384
3385         for (i = 0; i < 4; i++) {
3386                 reg = FDI_TX_CTL(pipe);
3387                 temp = I915_READ(reg);
3388                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3389                 temp |= snb_b_fdi_train_param[i];
3390                 I915_WRITE(reg, temp);
3391
3392                 POSTING_READ(reg);
3393                 udelay(500);
3394
3395                 for (retry = 0; retry < 5; retry++) {
3396                         reg = FDI_RX_IIR(pipe);
3397                         temp = I915_READ(reg);
3398                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3399                         if (temp & FDI_RX_SYMBOL_LOCK) {
3400                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3401                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3402                                 break;
3403                         }
3404                         udelay(50);
3405                 }
3406                 if (retry < 5)
3407                         break;
3408         }
3409         if (i == 4)
3410                 DRM_ERROR("FDI train 2 fail!\n");
3411
3412         DRM_DEBUG_KMS("FDI train done.\n");
3413 }
3414
3415 /* Manual link training for Ivy Bridge A0 parts */
3416 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3417 {
3418         struct drm_device *dev = crtc->dev;
3419         struct drm_i915_private *dev_priv = dev->dev_private;
3420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421         int pipe = intel_crtc->pipe;
3422         u32 reg, temp, i, j;
3423
3424         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3425            for train result */
3426         reg = FDI_RX_IMR(pipe);
3427         temp = I915_READ(reg);
3428         temp &= ~FDI_RX_SYMBOL_LOCK;
3429         temp &= ~FDI_RX_BIT_LOCK;
3430         I915_WRITE(reg, temp);
3431
3432         POSTING_READ(reg);
3433         udelay(150);
3434
3435         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3436                       I915_READ(FDI_RX_IIR(pipe)));
3437
3438         /* Try each vswing and preemphasis setting twice before moving on */
3439         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3440                 /* disable first in case we need to retry */
3441                 reg = FDI_TX_CTL(pipe);
3442                 temp = I915_READ(reg);
3443                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3444                 temp &= ~FDI_TX_ENABLE;
3445                 I915_WRITE(reg, temp);
3446
3447                 reg = FDI_RX_CTL(pipe);
3448                 temp = I915_READ(reg);
3449                 temp &= ~FDI_LINK_TRAIN_AUTO;
3450                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3451                 temp &= ~FDI_RX_ENABLE;
3452                 I915_WRITE(reg, temp);
3453
3454                 /* enable CPU FDI TX and PCH FDI RX */
3455                 reg = FDI_TX_CTL(pipe);
3456                 temp = I915_READ(reg);
3457                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3458                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3459                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3460                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3461                 temp |= snb_b_fdi_train_param[j/2];
3462                 temp |= FDI_COMPOSITE_SYNC;
3463                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3464
3465                 I915_WRITE(FDI_RX_MISC(pipe),
3466                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3467
3468                 reg = FDI_RX_CTL(pipe);
3469                 temp = I915_READ(reg);
3470                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3471                 temp |= FDI_COMPOSITE_SYNC;
3472                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3473
3474                 POSTING_READ(reg);
3475                 udelay(1); /* should be 0.5us */
3476
3477                 for (i = 0; i < 4; i++) {
3478                         reg = FDI_RX_IIR(pipe);
3479                         temp = I915_READ(reg);
3480                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3481
3482                         if (temp & FDI_RX_BIT_LOCK ||
3483                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3484                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3485                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3486                                               i);
3487                                 break;
3488                         }
3489                         udelay(1); /* should be 0.5us */
3490                 }
3491                 if (i == 4) {
3492                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3493                         continue;
3494                 }
3495
3496                 /* Train 2 */
3497                 reg = FDI_TX_CTL(pipe);
3498                 temp = I915_READ(reg);
3499                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3500                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3501                 I915_WRITE(reg, temp);
3502
3503                 reg = FDI_RX_CTL(pipe);
3504                 temp = I915_READ(reg);
3505                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3506                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3507                 I915_WRITE(reg, temp);
3508
3509                 POSTING_READ(reg);
3510                 udelay(2); /* should be 1.5us */
3511
3512                 for (i = 0; i < 4; i++) {
3513                         reg = FDI_RX_IIR(pipe);
3514                         temp = I915_READ(reg);
3515                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3516
3517                         if (temp & FDI_RX_SYMBOL_LOCK ||
3518                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3519                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3520                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3521                                               i);
3522                                 goto train_done;
3523                         }
3524                         udelay(2); /* should be 1.5us */
3525                 }
3526                 if (i == 4)
3527                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3528         }
3529
3530 train_done:
3531         DRM_DEBUG_KMS("FDI train done.\n");
3532 }
3533
3534 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3535 {
3536         struct drm_device *dev = intel_crtc->base.dev;
3537         struct drm_i915_private *dev_priv = dev->dev_private;
3538         int pipe = intel_crtc->pipe;
3539         u32 reg, temp;
3540
3541
3542         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3543         reg = FDI_RX_CTL(pipe);
3544         temp = I915_READ(reg);
3545         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3546         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3547         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3548         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3549
3550         POSTING_READ(reg);
3551         udelay(200);
3552
3553         /* Switch from Rawclk to PCDclk */
3554         temp = I915_READ(reg);
3555         I915_WRITE(reg, temp | FDI_PCDCLK);
3556
3557         POSTING_READ(reg);
3558         udelay(200);
3559
3560         /* Enable CPU FDI TX PLL, always on for Ironlake */
3561         reg = FDI_TX_CTL(pipe);
3562         temp = I915_READ(reg);
3563         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3564                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3565
3566                 POSTING_READ(reg);
3567                 udelay(100);
3568         }
3569 }
3570
3571 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3572 {
3573         struct drm_device *dev = intel_crtc->base.dev;
3574         struct drm_i915_private *dev_priv = dev->dev_private;
3575         int pipe = intel_crtc->pipe;
3576         u32 reg, temp;
3577
3578         /* Switch from PCDclk to Rawclk */
3579         reg = FDI_RX_CTL(pipe);
3580         temp = I915_READ(reg);
3581         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3582
3583         /* Disable CPU FDI TX PLL */
3584         reg = FDI_TX_CTL(pipe);
3585         temp = I915_READ(reg);
3586         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3587
3588         POSTING_READ(reg);
3589         udelay(100);
3590
3591         reg = FDI_RX_CTL(pipe);
3592         temp = I915_READ(reg);
3593         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3594
3595         /* Wait for the clocks to turn off. */
3596         POSTING_READ(reg);
3597         udelay(100);
3598 }
3599
3600 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3601 {
3602         struct drm_device *dev = crtc->dev;
3603         struct drm_i915_private *dev_priv = dev->dev_private;
3604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3605         int pipe = intel_crtc->pipe;
3606         u32 reg, temp;
3607
3608         /* disable CPU FDI tx and PCH FDI rx */
3609         reg = FDI_TX_CTL(pipe);
3610         temp = I915_READ(reg);
3611         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3612         POSTING_READ(reg);
3613
3614         reg = FDI_RX_CTL(pipe);
3615         temp = I915_READ(reg);
3616         temp &= ~(0x7 << 16);
3617         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3618         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3619
3620         POSTING_READ(reg);
3621         udelay(100);
3622
3623         /* Ironlake workaround, disable clock pointer after downing FDI */
3624         if (HAS_PCH_IBX(dev))
3625                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3626
3627         /* still set train pattern 1 */
3628         reg = FDI_TX_CTL(pipe);
3629         temp = I915_READ(reg);
3630         temp &= ~FDI_LINK_TRAIN_NONE;
3631         temp |= FDI_LINK_TRAIN_PATTERN_1;
3632         I915_WRITE(reg, temp);
3633
3634         reg = FDI_RX_CTL(pipe);
3635         temp = I915_READ(reg);
3636         if (HAS_PCH_CPT(dev)) {
3637                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3638                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3639         } else {
3640                 temp &= ~FDI_LINK_TRAIN_NONE;
3641                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3642         }
3643         /* BPC in FDI rx is consistent with that in PIPECONF */
3644         temp &= ~(0x07 << 16);
3645         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3646         I915_WRITE(reg, temp);
3647
3648         POSTING_READ(reg);
3649         udelay(100);
3650 }
3651
3652 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3653 {
3654         struct intel_crtc *crtc;
3655
3656         /* Note that we don't need to be called with mode_config.lock here
3657          * as our list of CRTC objects is static for the lifetime of the
3658          * device and so cannot disappear as we iterate. Similarly, we can
3659          * happily treat the predicates as racy, atomic checks as userspace
3660          * cannot claim and pin a new fb without at least acquring the
3661          * struct_mutex and so serialising with us.
3662          */
3663         for_each_intel_crtc(dev, crtc) {
3664                 if (atomic_read(&crtc->unpin_work_count) == 0)
3665                         continue;
3666
3667                 if (crtc->unpin_work)
3668                         intel_wait_for_vblank(dev, crtc->pipe);
3669
3670                 return true;
3671         }
3672
3673         return false;
3674 }
3675
3676 static void page_flip_completed(struct intel_crtc *intel_crtc)
3677 {
3678         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3679         struct intel_unpin_work *work = intel_crtc->unpin_work;
3680
3681         /* ensure that the unpin work is consistent wrt ->pending. */
3682         smp_rmb();
3683         intel_crtc->unpin_work = NULL;
3684
3685         if (work->event)
3686                 drm_send_vblank_event(intel_crtc->base.dev,
3687                                       intel_crtc->pipe,
3688                                       work->event);
3689
3690         drm_crtc_vblank_put(&intel_crtc->base);
3691
3692         wake_up_all(&dev_priv->pending_flip_queue);
3693         queue_work(dev_priv->wq, &work->work);
3694
3695         trace_i915_flip_complete(intel_crtc->plane,
3696                                  work->pending_flip_obj);
3697 }
3698
3699 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3700 {
3701         struct drm_device *dev = crtc->dev;
3702         struct drm_i915_private *dev_priv = dev->dev_private;
3703
3704         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3705         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3706                                        !intel_crtc_has_pending_flip(crtc),
3707                                        60*HZ) == 0)) {
3708                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3709
3710                 spin_lock_irq(&dev->event_lock);
3711                 if (intel_crtc->unpin_work) {
3712                         WARN_ONCE(1, "Removing stuck page flip\n");
3713                         page_flip_completed(intel_crtc);
3714                 }
3715                 spin_unlock_irq(&dev->event_lock);
3716         }
3717
3718         if (crtc->primary->fb) {
3719                 mutex_lock(&dev->struct_mutex);
3720                 intel_finish_fb(crtc->primary->fb);
3721                 mutex_unlock(&dev->struct_mutex);
3722         }
3723 }
3724
3725 /* Program iCLKIP clock to the desired frequency */
3726 static void lpt_program_iclkip(struct drm_crtc *crtc)
3727 {
3728         struct drm_device *dev = crtc->dev;
3729         struct drm_i915_private *dev_priv = dev->dev_private;
3730         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3731         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3732         u32 temp;
3733
3734         mutex_lock(&dev_priv->dpio_lock);
3735
3736         /* It is necessary to ungate the pixclk gate prior to programming
3737          * the divisors, and gate it back when it is done.
3738          */
3739         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3740
3741         /* Disable SSCCTL */
3742         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3743                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3744                                 SBI_SSCCTL_DISABLE,
3745                         SBI_ICLK);
3746
3747         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3748         if (clock == 20000) {
3749                 auxdiv = 1;
3750                 divsel = 0x41;
3751                 phaseinc = 0x20;
3752         } else {
3753                 /* The iCLK virtual clock root frequency is in MHz,
3754                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3755                  * divisors, it is necessary to divide one by another, so we
3756                  * convert the virtual clock precision to KHz here for higher
3757                  * precision.
3758                  */
3759                 u32 iclk_virtual_root_freq = 172800 * 1000;
3760                 u32 iclk_pi_range = 64;
3761                 u32 desired_divisor, msb_divisor_value, pi_value;
3762
3763                 desired_divisor = (iclk_virtual_root_freq / clock);
3764                 msb_divisor_value = desired_divisor / iclk_pi_range;
3765                 pi_value = desired_divisor % iclk_pi_range;
3766
3767                 auxdiv = 0;
3768                 divsel = msb_divisor_value - 2;
3769                 phaseinc = pi_value;
3770         }
3771
3772         /* This should not happen with any sane values */
3773         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3774                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3775         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3776                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3777
3778         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3779                         clock,
3780                         auxdiv,
3781                         divsel,
3782                         phasedir,
3783                         phaseinc);
3784
3785         /* Program SSCDIVINTPHASE6 */
3786         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3787         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3788         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3789         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3790         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3791         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3792         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3793         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3794
3795         /* Program SSCAUXDIV */
3796         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3797         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3798         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3799         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3800
3801         /* Enable modulator and associated divider */
3802         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3803         temp &= ~SBI_SSCCTL_DISABLE;
3804         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3805
3806         /* Wait for initialization time */
3807         udelay(24);
3808
3809         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3810
3811         mutex_unlock(&dev_priv->dpio_lock);
3812 }
3813
3814 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3815                                                 enum pipe pch_transcoder)
3816 {
3817         struct drm_device *dev = crtc->base.dev;
3818         struct drm_i915_private *dev_priv = dev->dev_private;
3819         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3820
3821         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3822                    I915_READ(HTOTAL(cpu_transcoder)));
3823         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3824                    I915_READ(HBLANK(cpu_transcoder)));
3825         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3826                    I915_READ(HSYNC(cpu_transcoder)));
3827
3828         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3829                    I915_READ(VTOTAL(cpu_transcoder)));
3830         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3831                    I915_READ(VBLANK(cpu_transcoder)));
3832         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3833                    I915_READ(VSYNC(cpu_transcoder)));
3834         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3835                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3836 }
3837
3838 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3839 {
3840         struct drm_i915_private *dev_priv = dev->dev_private;
3841         uint32_t temp;
3842
3843         temp = I915_READ(SOUTH_CHICKEN1);
3844         if (temp & FDI_BC_BIFURCATION_SELECT)
3845                 return;
3846
3847         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3848         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3849
3850         temp |= FDI_BC_BIFURCATION_SELECT;
3851         DRM_DEBUG_KMS("enabling fdi C rx\n");
3852         I915_WRITE(SOUTH_CHICKEN1, temp);
3853         POSTING_READ(SOUTH_CHICKEN1);
3854 }
3855
3856 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3857 {
3858         struct drm_device *dev = intel_crtc->base.dev;
3859         struct drm_i915_private *dev_priv = dev->dev_private;
3860
3861         switch (intel_crtc->pipe) {
3862         case PIPE_A:
3863                 break;
3864         case PIPE_B:
3865                 if (intel_crtc->config->fdi_lanes > 2)
3866                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3867                 else
3868                         cpt_enable_fdi_bc_bifurcation(dev);
3869
3870                 break;
3871         case PIPE_C:
3872                 cpt_enable_fdi_bc_bifurcation(dev);
3873
3874                 break;
3875         default:
3876                 BUG();
3877         }
3878 }
3879
3880 /*
3881  * Enable PCH resources required for PCH ports:
3882  *   - PCH PLLs
3883  *   - FDI training & RX/TX
3884  *   - update transcoder timings
3885  *   - DP transcoding bits
3886  *   - transcoder
3887  */
3888 static void ironlake_pch_enable(struct drm_crtc *crtc)
3889 {
3890         struct drm_device *dev = crtc->dev;
3891         struct drm_i915_private *dev_priv = dev->dev_private;
3892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893         int pipe = intel_crtc->pipe;
3894         u32 reg, temp;
3895
3896         assert_pch_transcoder_disabled(dev_priv, pipe);
3897
3898         if (IS_IVYBRIDGE(dev))
3899                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3900
3901         /* Write the TU size bits before fdi link training, so that error
3902          * detection works. */
3903         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3904                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3905
3906         /* For PCH output, training FDI link */
3907         dev_priv->display.fdi_link_train(crtc);
3908
3909         /* We need to program the right clock selection before writing the pixel
3910          * mutliplier into the DPLL. */
3911         if (HAS_PCH_CPT(dev)) {
3912                 u32 sel;
3913
3914                 temp = I915_READ(PCH_DPLL_SEL);
3915                 temp |= TRANS_DPLL_ENABLE(pipe);
3916                 sel = TRANS_DPLLB_SEL(pipe);
3917                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3918                         temp |= sel;
3919                 else
3920                         temp &= ~sel;
3921                 I915_WRITE(PCH_DPLL_SEL, temp);
3922         }
3923
3924         /* XXX: pch pll's can be enabled any time before we enable the PCH
3925          * transcoder, and we actually should do this to not upset any PCH
3926          * transcoder that already use the clock when we share it.
3927          *
3928          * Note that enable_shared_dpll tries to do the right thing, but
3929          * get_shared_dpll unconditionally resets the pll - we need that to have
3930          * the right LVDS enable sequence. */
3931         intel_enable_shared_dpll(intel_crtc);
3932
3933         /* set transcoder timing, panel must allow it */
3934         assert_panel_unlocked(dev_priv, pipe);
3935         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3936
3937         intel_fdi_normal_train(crtc);
3938
3939         /* For PCH DP, enable TRANS_DP_CTL */
3940         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3941                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3942                 reg = TRANS_DP_CTL(pipe);
3943                 temp = I915_READ(reg);
3944                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3945                           TRANS_DP_SYNC_MASK |
3946                           TRANS_DP_BPC_MASK);
3947                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3948                          TRANS_DP_ENH_FRAMING);
3949                 temp |= bpc << 9; /* same format but at 11:9 */
3950
3951                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3952                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3953                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3954                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3955
3956                 switch (intel_trans_dp_port_sel(crtc)) {
3957                 case PCH_DP_B:
3958                         temp |= TRANS_DP_PORT_SEL_B;
3959                         break;
3960                 case PCH_DP_C:
3961                         temp |= TRANS_DP_PORT_SEL_C;
3962                         break;
3963                 case PCH_DP_D:
3964                         temp |= TRANS_DP_PORT_SEL_D;
3965                         break;
3966                 default:
3967                         BUG();
3968                 }
3969
3970                 I915_WRITE(reg, temp);
3971         }
3972
3973         ironlake_enable_pch_transcoder(dev_priv, pipe);
3974 }
3975
3976 static void lpt_pch_enable(struct drm_crtc *crtc)
3977 {
3978         struct drm_device *dev = crtc->dev;
3979         struct drm_i915_private *dev_priv = dev->dev_private;
3980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3981         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3982
3983         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3984
3985         lpt_program_iclkip(crtc);
3986
3987         /* Set transcoder timing. */
3988         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3989
3990         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3991 }
3992
3993 void intel_put_shared_dpll(struct intel_crtc *crtc)
3994 {
3995         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3996
3997         if (pll == NULL)
3998                 return;
3999
4000         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4001                 WARN(1, "bad %s crtc mask\n", pll->name);
4002                 return;
4003         }
4004
4005         pll->config.crtc_mask &= ~(1 << crtc->pipe);
4006         if (pll->config.crtc_mask == 0) {
4007                 WARN_ON(pll->on);
4008                 WARN_ON(pll->active);
4009         }
4010
4011         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4012 }
4013
4014 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4015                                                 struct intel_crtc_state *crtc_state)
4016 {
4017         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4018         struct intel_shared_dpll *pll;
4019         enum intel_dpll_id i;
4020
4021         if (HAS_PCH_IBX(dev_priv->dev)) {
4022                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4023                 i = (enum intel_dpll_id) crtc->pipe;
4024                 pll = &dev_priv->shared_dplls[i];
4025
4026                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4027                               crtc->base.base.id, pll->name);
4028
4029                 WARN_ON(pll->new_config->crtc_mask);
4030
4031                 goto found;
4032         }
4033
4034         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4035                 pll = &dev_priv->shared_dplls[i];
4036
4037                 /* Only want to check enabled timings first */
4038                 if (pll->new_config->crtc_mask == 0)
4039                         continue;
4040
4041                 if (memcmp(&crtc_state->dpll_hw_state,
4042                            &pll->new_config->hw_state,
4043                            sizeof(pll->new_config->hw_state)) == 0) {
4044                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4045                                       crtc->base.base.id, pll->name,
4046                                       pll->new_config->crtc_mask,
4047                                       pll->active);
4048                         goto found;
4049                 }
4050         }
4051
4052         /* Ok no matching timings, maybe there's a free one? */
4053         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4054                 pll = &dev_priv->shared_dplls[i];
4055                 if (pll->new_config->crtc_mask == 0) {
4056                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4057                                       crtc->base.base.id, pll->name);
4058                         goto found;
4059                 }
4060         }
4061
4062         return NULL;
4063
4064 found:
4065         if (pll->new_config->crtc_mask == 0)
4066                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4067
4068         crtc_state->shared_dpll = i;
4069         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4070                          pipe_name(crtc->pipe));
4071
4072         pll->new_config->crtc_mask |= 1 << crtc->pipe;
4073
4074         return pll;
4075 }
4076
4077 /**
4078  * intel_shared_dpll_start_config - start a new PLL staged config
4079  * @dev_priv: DRM device
4080  * @clear_pipes: mask of pipes that will have their PLLs freed
4081  *
4082  * Starts a new PLL staged config, copying the current config but
4083  * releasing the references of pipes specified in clear_pipes.
4084  */
4085 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4086                                           unsigned clear_pipes)
4087 {
4088         struct intel_shared_dpll *pll;
4089         enum intel_dpll_id i;
4090
4091         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4092                 pll = &dev_priv->shared_dplls[i];
4093
4094                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4095                                           GFP_KERNEL);
4096                 if (!pll->new_config)
4097                         goto cleanup;
4098
4099                 pll->new_config->crtc_mask &= ~clear_pipes;
4100         }
4101
4102         return 0;
4103
4104 cleanup:
4105         while (--i >= 0) {
4106                 pll = &dev_priv->shared_dplls[i];
4107                 kfree(pll->new_config);
4108                 pll->new_config = NULL;
4109         }
4110
4111         return -ENOMEM;
4112 }
4113
4114 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4115 {
4116         struct intel_shared_dpll *pll;
4117         enum intel_dpll_id i;
4118
4119         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4120                 pll = &dev_priv->shared_dplls[i];
4121
4122                 WARN_ON(pll->new_config == &pll->config);
4123
4124                 pll->config = *pll->new_config;
4125                 kfree(pll->new_config);
4126                 pll->new_config = NULL;
4127         }
4128 }
4129
4130 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4131 {
4132         struct intel_shared_dpll *pll;
4133         enum intel_dpll_id i;
4134
4135         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4136                 pll = &dev_priv->shared_dplls[i];
4137
4138                 WARN_ON(pll->new_config == &pll->config);
4139
4140                 kfree(pll->new_config);
4141                 pll->new_config = NULL;
4142         }
4143 }
4144
4145 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4146 {
4147         struct drm_i915_private *dev_priv = dev->dev_private;
4148         int dslreg = PIPEDSL(pipe);
4149         u32 temp;
4150
4151         temp = I915_READ(dslreg);
4152         udelay(500);
4153         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4154                 if (wait_for(I915_READ(dslreg) != temp, 5))
4155                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4156         }
4157 }
4158
4159 static void skylake_pfit_enable(struct intel_crtc *crtc)
4160 {
4161         struct drm_device *dev = crtc->base.dev;
4162         struct drm_i915_private *dev_priv = dev->dev_private;
4163         int pipe = crtc->pipe;
4164
4165         if (crtc->config->pch_pfit.enabled) {
4166                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4167                 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4168                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4169         }
4170 }
4171
4172 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4173 {
4174         struct drm_device *dev = crtc->base.dev;
4175         struct drm_i915_private *dev_priv = dev->dev_private;
4176         int pipe = crtc->pipe;
4177
4178         if (crtc->config->pch_pfit.enabled) {
4179                 /* Force use of hard-coded filter coefficients
4180                  * as some pre-programmed values are broken,
4181                  * e.g. x201.
4182                  */
4183                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4184                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4185                                                  PF_PIPE_SEL_IVB(pipe));
4186                 else
4187                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4188                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4189                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4190         }
4191 }
4192
4193 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4194 {
4195         struct drm_device *dev = crtc->dev;
4196         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4197         struct drm_plane *plane;
4198         struct intel_plane *intel_plane;
4199
4200         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4201                 intel_plane = to_intel_plane(plane);
4202                 if (intel_plane->pipe == pipe)
4203                         intel_plane_restore(&intel_plane->base);
4204         }
4205 }
4206
4207 /*
4208  * Disable a plane internally without actually modifying the plane's state.
4209  * This will allow us to easily restore the plane later by just reprogramming
4210  * its state.
4211  */
4212 static void disable_plane_internal(struct drm_plane *plane)
4213 {
4214         struct intel_plane *intel_plane = to_intel_plane(plane);
4215         struct drm_plane_state *state =
4216                 plane->funcs->atomic_duplicate_state(plane);
4217         struct intel_plane_state *intel_state = to_intel_plane_state(state);
4218
4219         intel_state->visible = false;
4220         intel_plane->commit_plane(plane, intel_state);
4221
4222         intel_plane_destroy_state(plane, state);
4223 }
4224
4225 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4226 {
4227         struct drm_device *dev = crtc->dev;
4228         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4229         struct drm_plane *plane;
4230         struct intel_plane *intel_plane;
4231
4232         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4233                 intel_plane = to_intel_plane(plane);
4234                 if (plane->fb && intel_plane->pipe == pipe)
4235                         disable_plane_internal(plane);
4236         }
4237 }
4238
4239 void hsw_enable_ips(struct intel_crtc *crtc)
4240 {
4241         struct drm_device *dev = crtc->base.dev;
4242         struct drm_i915_private *dev_priv = dev->dev_private;
4243
4244         if (!crtc->config->ips_enabled)
4245                 return;
4246
4247         /* We can only enable IPS after we enable a plane and wait for a vblank */
4248         intel_wait_for_vblank(dev, crtc->pipe);
4249
4250         assert_plane_enabled(dev_priv, crtc->plane);
4251         if (IS_BROADWELL(dev)) {
4252                 mutex_lock(&dev_priv->rps.hw_lock);
4253                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4254                 mutex_unlock(&dev_priv->rps.hw_lock);
4255                 /* Quoting Art Runyan: "its not safe to expect any particular
4256                  * value in IPS_CTL bit 31 after enabling IPS through the
4257                  * mailbox." Moreover, the mailbox may return a bogus state,
4258                  * so we need to just enable it and continue on.
4259                  */
4260         } else {
4261                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4262                 /* The bit only becomes 1 in the next vblank, so this wait here
4263                  * is essentially intel_wait_for_vblank. If we don't have this
4264                  * and don't wait for vblanks until the end of crtc_enable, then
4265                  * the HW state readout code will complain that the expected
4266                  * IPS_CTL value is not the one we read. */
4267                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4268                         DRM_ERROR("Timed out waiting for IPS enable\n");
4269         }
4270 }
4271
4272 void hsw_disable_ips(struct intel_crtc *crtc)
4273 {
4274         struct drm_device *dev = crtc->base.dev;
4275         struct drm_i915_private *dev_priv = dev->dev_private;
4276
4277         if (!crtc->config->ips_enabled)
4278                 return;
4279
4280         assert_plane_enabled(dev_priv, crtc->plane);
4281         if (IS_BROADWELL(dev)) {
4282                 mutex_lock(&dev_priv->rps.hw_lock);
4283                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4284                 mutex_unlock(&dev_priv->rps.hw_lock);
4285                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4286                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4287                         DRM_ERROR("Timed out waiting for IPS disable\n");
4288         } else {
4289                 I915_WRITE(IPS_CTL, 0);
4290                 POSTING_READ(IPS_CTL);
4291         }
4292
4293         /* We need to wait for a vblank before we can disable the plane. */
4294         intel_wait_for_vblank(dev, crtc->pipe);
4295 }
4296
4297 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4298 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4299 {
4300         struct drm_device *dev = crtc->dev;
4301         struct drm_i915_private *dev_priv = dev->dev_private;
4302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4303         enum pipe pipe = intel_crtc->pipe;
4304         int palreg = PALETTE(pipe);
4305         int i;
4306         bool reenable_ips = false;
4307
4308         /* The clocks have to be on to load the palette. */
4309         if (!crtc->state->enable || !intel_crtc->active)
4310                 return;
4311
4312         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4313                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4314                         assert_dsi_pll_enabled(dev_priv);
4315                 else
4316                         assert_pll_enabled(dev_priv, pipe);
4317         }
4318
4319         /* use legacy palette for Ironlake */
4320         if (!HAS_GMCH_DISPLAY(dev))
4321                 palreg = LGC_PALETTE(pipe);
4322
4323         /* Workaround : Do not read or write the pipe palette/gamma data while
4324          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4325          */
4326         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4327             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4328              GAMMA_MODE_MODE_SPLIT)) {
4329                 hsw_disable_ips(intel_crtc);
4330                 reenable_ips = true;
4331         }
4332
4333         for (i = 0; i < 256; i++) {
4334                 I915_WRITE(palreg + 4 * i,
4335                            (intel_crtc->lut_r[i] << 16) |
4336                            (intel_crtc->lut_g[i] << 8) |
4337                            intel_crtc->lut_b[i]);
4338         }
4339
4340         if (reenable_ips)
4341                 hsw_enable_ips(intel_crtc);
4342 }
4343
4344 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4345 {
4346         if (!enable && intel_crtc->overlay) {
4347                 struct drm_device *dev = intel_crtc->base.dev;
4348                 struct drm_i915_private *dev_priv = dev->dev_private;
4349
4350                 mutex_lock(&dev->struct_mutex);
4351                 dev_priv->mm.interruptible = false;
4352                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4353                 dev_priv->mm.interruptible = true;
4354                 mutex_unlock(&dev->struct_mutex);
4355         }
4356
4357         /* Let userspace switch the overlay on again. In most cases userspace
4358          * has to recompute where to put it anyway.
4359          */
4360 }
4361
4362 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4363 {
4364         struct drm_device *dev = crtc->dev;
4365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4366         int pipe = intel_crtc->pipe;
4367
4368         intel_enable_primary_hw_plane(crtc->primary, crtc);
4369         intel_enable_sprite_planes(crtc);
4370         intel_crtc_update_cursor(crtc, true);
4371         intel_crtc_dpms_overlay(intel_crtc, true);
4372
4373         hsw_enable_ips(intel_crtc);
4374
4375         mutex_lock(&dev->struct_mutex);
4376         intel_fbc_update(dev);
4377         mutex_unlock(&dev->struct_mutex);
4378
4379         /*
4380          * FIXME: Once we grow proper nuclear flip support out of this we need
4381          * to compute the mask of flip planes precisely. For the time being
4382          * consider this a flip from a NULL plane.
4383          */
4384         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4385 }
4386
4387 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4388 {
4389         struct drm_device *dev = crtc->dev;
4390         struct drm_i915_private *dev_priv = dev->dev_private;
4391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4392         int pipe = intel_crtc->pipe;
4393
4394         intel_crtc_wait_for_pending_flips(crtc);
4395
4396         if (dev_priv->fbc.crtc == intel_crtc)
4397                 intel_fbc_disable(dev);
4398
4399         hsw_disable_ips(intel_crtc);
4400
4401         intel_crtc_dpms_overlay(intel_crtc, false);
4402         intel_crtc_update_cursor(crtc, false);
4403         intel_disable_sprite_planes(crtc);
4404         intel_disable_primary_hw_plane(crtc->primary, crtc);
4405
4406         /*
4407          * FIXME: Once we grow proper nuclear flip support out of this we need
4408          * to compute the mask of flip planes precisely. For the time being
4409          * consider this a flip to a NULL plane.
4410          */
4411         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4412 }
4413
4414 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4415 {
4416         struct drm_device *dev = crtc->dev;
4417         struct drm_i915_private *dev_priv = dev->dev_private;
4418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4419         struct intel_encoder *encoder;
4420         int pipe = intel_crtc->pipe;
4421
4422         WARN_ON(!crtc->state->enable);
4423
4424         if (intel_crtc->active)
4425                 return;
4426
4427         if (intel_crtc->config->has_pch_encoder)
4428                 intel_prepare_shared_dpll(intel_crtc);
4429
4430         if (intel_crtc->config->has_dp_encoder)
4431                 intel_dp_set_m_n(intel_crtc, M1_N1);
4432
4433         intel_set_pipe_timings(intel_crtc);
4434
4435         if (intel_crtc->config->has_pch_encoder) {
4436                 intel_cpu_transcoder_set_m_n(intel_crtc,
4437                                      &intel_crtc->config->fdi_m_n, NULL);
4438         }
4439
4440         ironlake_set_pipeconf(crtc);
4441
4442         intel_crtc->active = true;
4443
4444         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4445         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4446
4447         for_each_encoder_on_crtc(dev, crtc, encoder)
4448                 if (encoder->pre_enable)
4449                         encoder->pre_enable(encoder);
4450
4451         if (intel_crtc->config->has_pch_encoder) {
4452                 /* Note: FDI PLL enabling _must_ be done before we enable the
4453                  * cpu pipes, hence this is separate from all the other fdi/pch
4454                  * enabling. */
4455                 ironlake_fdi_pll_enable(intel_crtc);
4456         } else {
4457                 assert_fdi_tx_disabled(dev_priv, pipe);
4458                 assert_fdi_rx_disabled(dev_priv, pipe);
4459         }
4460
4461         ironlake_pfit_enable(intel_crtc);
4462
4463         /*
4464          * On ILK+ LUT must be loaded before the pipe is running but with
4465          * clocks enabled
4466          */
4467         intel_crtc_load_lut(crtc);
4468
4469         intel_update_watermarks(crtc);
4470         intel_enable_pipe(intel_crtc);
4471
4472         if (intel_crtc->config->has_pch_encoder)
4473                 ironlake_pch_enable(crtc);
4474
4475         assert_vblank_disabled(crtc);
4476         drm_crtc_vblank_on(crtc);
4477
4478         for_each_encoder_on_crtc(dev, crtc, encoder)
4479                 encoder->enable(encoder);
4480
4481         if (HAS_PCH_CPT(dev))
4482                 cpt_verify_modeset(dev, intel_crtc->pipe);
4483
4484         intel_crtc_enable_planes(crtc);
4485 }
4486
4487 /* IPS only exists on ULT machines and is tied to pipe A. */
4488 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4489 {
4490         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4491 }
4492
4493 /*
4494  * This implements the workaround described in the "notes" section of the mode
4495  * set sequence documentation. When going from no pipes or single pipe to
4496  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4497  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4498  */
4499 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4500 {
4501         struct drm_device *dev = crtc->base.dev;
4502         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4503
4504         /* We want to get the other_active_crtc only if there's only 1 other
4505          * active crtc. */
4506         for_each_intel_crtc(dev, crtc_it) {
4507                 if (!crtc_it->active || crtc_it == crtc)
4508                         continue;
4509
4510                 if (other_active_crtc)
4511                         return;
4512
4513                 other_active_crtc = crtc_it;
4514         }
4515         if (!other_active_crtc)
4516                 return;
4517
4518         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4519         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4520 }
4521
4522 static void haswell_crtc_enable(struct drm_crtc *crtc)
4523 {
4524         struct drm_device *dev = crtc->dev;
4525         struct drm_i915_private *dev_priv = dev->dev_private;
4526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4527         struct intel_encoder *encoder;
4528         int pipe = intel_crtc->pipe;
4529
4530         WARN_ON(!crtc->state->enable);
4531
4532         if (intel_crtc->active)
4533                 return;
4534
4535         if (intel_crtc_to_shared_dpll(intel_crtc))
4536                 intel_enable_shared_dpll(intel_crtc);
4537
4538         if (intel_crtc->config->has_dp_encoder)
4539                 intel_dp_set_m_n(intel_crtc, M1_N1);
4540
4541         intel_set_pipe_timings(intel_crtc);
4542
4543         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4544                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4545                            intel_crtc->config->pixel_multiplier - 1);
4546         }
4547
4548         if (intel_crtc->config->has_pch_encoder) {
4549                 intel_cpu_transcoder_set_m_n(intel_crtc,
4550                                      &intel_crtc->config->fdi_m_n, NULL);
4551         }
4552
4553         haswell_set_pipeconf(crtc);
4554
4555         intel_set_pipe_csc(crtc);
4556
4557         intel_crtc->active = true;
4558
4559         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4560         for_each_encoder_on_crtc(dev, crtc, encoder)
4561                 if (encoder->pre_enable)
4562                         encoder->pre_enable(encoder);
4563
4564         if (intel_crtc->config->has_pch_encoder) {
4565                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4566                                                       true);
4567                 dev_priv->display.fdi_link_train(crtc);
4568         }
4569
4570         intel_ddi_enable_pipe_clock(intel_crtc);
4571
4572         if (IS_SKYLAKE(dev))
4573                 skylake_pfit_enable(intel_crtc);
4574         else
4575                 ironlake_pfit_enable(intel_crtc);
4576
4577         /*
4578          * On ILK+ LUT must be loaded before the pipe is running but with
4579          * clocks enabled
4580          */
4581         intel_crtc_load_lut(crtc);
4582
4583         intel_ddi_set_pipe_settings(crtc);
4584         intel_ddi_enable_transcoder_func(crtc);
4585
4586         intel_update_watermarks(crtc);
4587         intel_enable_pipe(intel_crtc);
4588
4589         if (intel_crtc->config->has_pch_encoder)
4590                 lpt_pch_enable(crtc);
4591
4592         if (intel_crtc->config->dp_encoder_is_mst)
4593                 intel_ddi_set_vc_payload_alloc(crtc, true);
4594
4595         assert_vblank_disabled(crtc);
4596         drm_crtc_vblank_on(crtc);
4597
4598         for_each_encoder_on_crtc(dev, crtc, encoder) {
4599                 encoder->enable(encoder);
4600                 intel_opregion_notify_encoder(encoder, true);
4601         }
4602
4603         /* If we change the relative order between pipe/planes enabling, we need
4604          * to change the workaround. */
4605         haswell_mode_set_planes_workaround(intel_crtc);
4606         intel_crtc_enable_planes(crtc);
4607 }
4608
4609 static void skylake_pfit_disable(struct intel_crtc *crtc)
4610 {
4611         struct drm_device *dev = crtc->base.dev;
4612         struct drm_i915_private *dev_priv = dev->dev_private;
4613         int pipe = crtc->pipe;
4614
4615         /* To avoid upsetting the power well on haswell only disable the pfit if
4616          * it's in use. The hw state code will make sure we get this right. */
4617         if (crtc->config->pch_pfit.enabled) {
4618                 I915_WRITE(PS_CTL(pipe), 0);
4619                 I915_WRITE(PS_WIN_POS(pipe), 0);
4620                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4621         }
4622 }
4623
4624 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4625 {
4626         struct drm_device *dev = crtc->base.dev;
4627         struct drm_i915_private *dev_priv = dev->dev_private;
4628         int pipe = crtc->pipe;
4629
4630         /* To avoid upsetting the power well on haswell only disable the pfit if
4631          * it's in use. The hw state code will make sure we get this right. */
4632         if (crtc->config->pch_pfit.enabled) {
4633                 I915_WRITE(PF_CTL(pipe), 0);
4634                 I915_WRITE(PF_WIN_POS(pipe), 0);
4635                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4636         }
4637 }
4638
4639 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4640 {
4641         struct drm_device *dev = crtc->dev;
4642         struct drm_i915_private *dev_priv = dev->dev_private;
4643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4644         struct intel_encoder *encoder;
4645         int pipe = intel_crtc->pipe;
4646         u32 reg, temp;
4647
4648         if (!intel_crtc->active)
4649                 return;
4650
4651         intel_crtc_disable_planes(crtc);
4652
4653         for_each_encoder_on_crtc(dev, crtc, encoder)
4654                 encoder->disable(encoder);
4655
4656         drm_crtc_vblank_off(crtc);
4657         assert_vblank_disabled(crtc);
4658
4659         if (intel_crtc->config->has_pch_encoder)
4660                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4661
4662         intel_disable_pipe(intel_crtc);
4663
4664         ironlake_pfit_disable(intel_crtc);
4665
4666         for_each_encoder_on_crtc(dev, crtc, encoder)
4667                 if (encoder->post_disable)
4668                         encoder->post_disable(encoder);
4669
4670         if (intel_crtc->config->has_pch_encoder) {
4671                 ironlake_fdi_disable(crtc);
4672
4673                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4674
4675                 if (HAS_PCH_CPT(dev)) {
4676                         /* disable TRANS_DP_CTL */
4677                         reg = TRANS_DP_CTL(pipe);
4678                         temp = I915_READ(reg);
4679                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4680                                   TRANS_DP_PORT_SEL_MASK);
4681                         temp |= TRANS_DP_PORT_SEL_NONE;
4682                         I915_WRITE(reg, temp);
4683
4684                         /* disable DPLL_SEL */
4685                         temp = I915_READ(PCH_DPLL_SEL);
4686                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4687                         I915_WRITE(PCH_DPLL_SEL, temp);
4688                 }
4689
4690                 /* disable PCH DPLL */
4691                 intel_disable_shared_dpll(intel_crtc);
4692
4693                 ironlake_fdi_pll_disable(intel_crtc);
4694         }
4695
4696         intel_crtc->active = false;
4697         intel_update_watermarks(crtc);
4698
4699         mutex_lock(&dev->struct_mutex);
4700         intel_fbc_update(dev);
4701         mutex_unlock(&dev->struct_mutex);
4702 }
4703
4704 static void haswell_crtc_disable(struct drm_crtc *crtc)
4705 {
4706         struct drm_device *dev = crtc->dev;
4707         struct drm_i915_private *dev_priv = dev->dev_private;
4708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709         struct intel_encoder *encoder;
4710         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4711
4712         if (!intel_crtc->active)
4713                 return;
4714
4715         intel_crtc_disable_planes(crtc);
4716
4717         for_each_encoder_on_crtc(dev, crtc, encoder) {
4718                 intel_opregion_notify_encoder(encoder, false);
4719                 encoder->disable(encoder);
4720         }
4721
4722         drm_crtc_vblank_off(crtc);
4723         assert_vblank_disabled(crtc);
4724
4725         if (intel_crtc->config->has_pch_encoder)
4726                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4727                                                       false);
4728         intel_disable_pipe(intel_crtc);
4729
4730         if (intel_crtc->config->dp_encoder_is_mst)
4731                 intel_ddi_set_vc_payload_alloc(crtc, false);
4732
4733         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4734
4735         if (IS_SKYLAKE(dev))
4736                 skylake_pfit_disable(intel_crtc);
4737         else
4738                 ironlake_pfit_disable(intel_crtc);
4739
4740         intel_ddi_disable_pipe_clock(intel_crtc);
4741
4742         if (intel_crtc->config->has_pch_encoder) {
4743                 lpt_disable_pch_transcoder(dev_priv);
4744                 intel_ddi_fdi_disable(crtc);
4745         }
4746
4747         for_each_encoder_on_crtc(dev, crtc, encoder)
4748                 if (encoder->post_disable)
4749                         encoder->post_disable(encoder);
4750
4751         intel_crtc->active = false;
4752         intel_update_watermarks(crtc);
4753
4754         mutex_lock(&dev->struct_mutex);
4755         intel_fbc_update(dev);
4756         mutex_unlock(&dev->struct_mutex);
4757
4758         if (intel_crtc_to_shared_dpll(intel_crtc))
4759                 intel_disable_shared_dpll(intel_crtc);
4760 }
4761
4762 static void ironlake_crtc_off(struct drm_crtc *crtc)
4763 {
4764         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4765         intel_put_shared_dpll(intel_crtc);
4766 }
4767
4768
4769 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4770 {
4771         struct drm_device *dev = crtc->base.dev;
4772         struct drm_i915_private *dev_priv = dev->dev_private;
4773         struct intel_crtc_state *pipe_config = crtc->config;
4774
4775         if (!pipe_config->gmch_pfit.control)
4776                 return;
4777
4778         /*
4779          * The panel fitter should only be adjusted whilst the pipe is disabled,
4780          * according to register description and PRM.
4781          */
4782         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4783         assert_pipe_disabled(dev_priv, crtc->pipe);
4784
4785         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4786         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4787
4788         /* Border color in case we don't scale up to the full screen. Black by
4789          * default, change to something else for debugging. */
4790         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4791 }
4792
4793 static enum intel_display_power_domain port_to_power_domain(enum port port)
4794 {
4795         switch (port) {
4796         case PORT_A:
4797                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4798         case PORT_B:
4799                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4800         case PORT_C:
4801                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4802         case PORT_D:
4803                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4804         default:
4805                 WARN_ON_ONCE(1);
4806                 return POWER_DOMAIN_PORT_OTHER;
4807         }
4808 }
4809
4810 #define for_each_power_domain(domain, mask)                             \
4811         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4812                 if ((1 << (domain)) & (mask))
4813
4814 enum intel_display_power_domain
4815 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4816 {
4817         struct drm_device *dev = intel_encoder->base.dev;
4818         struct intel_digital_port *intel_dig_port;
4819
4820         switch (intel_encoder->type) {
4821         case INTEL_OUTPUT_UNKNOWN:
4822                 /* Only DDI platforms should ever use this output type */
4823                 WARN_ON_ONCE(!HAS_DDI(dev));
4824         case INTEL_OUTPUT_DISPLAYPORT:
4825         case INTEL_OUTPUT_HDMI:
4826         case INTEL_OUTPUT_EDP:
4827                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4828                 return port_to_power_domain(intel_dig_port->port);
4829         case INTEL_OUTPUT_DP_MST:
4830                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4831                 return port_to_power_domain(intel_dig_port->port);
4832         case INTEL_OUTPUT_ANALOG:
4833                 return POWER_DOMAIN_PORT_CRT;
4834         case INTEL_OUTPUT_DSI:
4835                 return POWER_DOMAIN_PORT_DSI;
4836         default:
4837                 return POWER_DOMAIN_PORT_OTHER;
4838         }
4839 }
4840
4841 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4842 {
4843         struct drm_device *dev = crtc->dev;
4844         struct intel_encoder *intel_encoder;
4845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4846         enum pipe pipe = intel_crtc->pipe;
4847         unsigned long mask;
4848         enum transcoder transcoder;
4849
4850         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4851
4852         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4853         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4854         if (intel_crtc->config->pch_pfit.enabled ||
4855             intel_crtc->config->pch_pfit.force_thru)
4856                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4857
4858         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4859                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4860
4861         return mask;
4862 }
4863
4864 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4865 {
4866         struct drm_i915_private *dev_priv = dev->dev_private;
4867         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4868         struct intel_crtc *crtc;
4869
4870         /*
4871          * First get all needed power domains, then put all unneeded, to avoid
4872          * any unnecessary toggling of the power wells.
4873          */
4874         for_each_intel_crtc(dev, crtc) {
4875                 enum intel_display_power_domain domain;
4876
4877                 if (!crtc->base.state->enable)
4878                         continue;
4879
4880                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4881
4882                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4883                         intel_display_power_get(dev_priv, domain);
4884         }
4885
4886         if (dev_priv->display.modeset_global_resources)
4887                 dev_priv->display.modeset_global_resources(dev);
4888
4889         for_each_intel_crtc(dev, crtc) {
4890                 enum intel_display_power_domain domain;
4891
4892                 for_each_power_domain(domain, crtc->enabled_power_domains)
4893                         intel_display_power_put(dev_priv, domain);
4894
4895                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4896         }
4897
4898         intel_display_set_init_power(dev_priv, false);
4899 }
4900
4901 /* returns HPLL frequency in kHz */
4902 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4903 {
4904         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4905
4906         /* Obtain SKU information */
4907         mutex_lock(&dev_priv->dpio_lock);
4908         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4909                 CCK_FUSE_HPLL_FREQ_MASK;
4910         mutex_unlock(&dev_priv->dpio_lock);
4911
4912         return vco_freq[hpll_freq] * 1000;
4913 }
4914
4915 static void vlv_update_cdclk(struct drm_device *dev)
4916 {
4917         struct drm_i915_private *dev_priv = dev->dev_private;
4918
4919         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4920         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4921                          dev_priv->vlv_cdclk_freq);
4922
4923         /*
4924          * Program the gmbus_freq based on the cdclk frequency.
4925          * BSpec erroneously claims we should aim for 4MHz, but
4926          * in fact 1MHz is the correct frequency.
4927          */
4928         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4929 }
4930
4931 /* Adjust CDclk dividers to allow high res or save power if possible */
4932 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4933 {
4934         struct drm_i915_private *dev_priv = dev->dev_private;
4935         u32 val, cmd;
4936
4937         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4938
4939         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4940                 cmd = 2;
4941         else if (cdclk == 266667)
4942                 cmd = 1;
4943         else
4944                 cmd = 0;
4945
4946         mutex_lock(&dev_priv->rps.hw_lock);
4947         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4948         val &= ~DSPFREQGUAR_MASK;
4949         val |= (cmd << DSPFREQGUAR_SHIFT);
4950         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4951         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4952                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4953                      50)) {
4954                 DRM_ERROR("timed out waiting for CDclk change\n");
4955         }
4956         mutex_unlock(&dev_priv->rps.hw_lock);
4957
4958         if (cdclk == 400000) {
4959                 u32 divider;
4960
4961                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4962
4963                 mutex_lock(&dev_priv->dpio_lock);
4964                 /* adjust cdclk divider */
4965                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4966                 val &= ~DISPLAY_FREQUENCY_VALUES;
4967                 val |= divider;
4968                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4969
4970                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4971                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4972                              50))
4973                         DRM_ERROR("timed out waiting for CDclk change\n");
4974                 mutex_unlock(&dev_priv->dpio_lock);
4975         }
4976
4977         mutex_lock(&dev_priv->dpio_lock);
4978         /* adjust self-refresh exit latency value */
4979         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4980         val &= ~0x7f;
4981
4982         /*
4983          * For high bandwidth configs, we set a higher latency in the bunit
4984          * so that the core display fetch happens in time to avoid underruns.
4985          */
4986         if (cdclk == 400000)
4987                 val |= 4500 / 250; /* 4.5 usec */
4988         else
4989                 val |= 3000 / 250; /* 3.0 usec */
4990         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4991         mutex_unlock(&dev_priv->dpio_lock);
4992
4993         vlv_update_cdclk(dev);
4994 }
4995
4996 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4997 {
4998         struct drm_i915_private *dev_priv = dev->dev_private;
4999         u32 val, cmd;
5000
5001         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5002
5003         switch (cdclk) {
5004         case 400000:
5005                 cmd = 3;
5006                 break;
5007         case 333333:
5008         case 320000:
5009                 cmd = 2;
5010                 break;
5011         case 266667:
5012                 cmd = 1;
5013                 break;
5014         case 200000:
5015                 cmd = 0;
5016                 break;
5017         default:
5018                 MISSING_CASE(cdclk);
5019                 return;
5020         }
5021
5022         mutex_lock(&dev_priv->rps.hw_lock);
5023         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5024         val &= ~DSPFREQGUAR_MASK_CHV;
5025         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5026         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5027         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5028                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5029                      50)) {
5030                 DRM_ERROR("timed out waiting for CDclk change\n");
5031         }
5032         mutex_unlock(&dev_priv->rps.hw_lock);
5033
5034         vlv_update_cdclk(dev);
5035 }
5036
5037 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5038                                  int max_pixclk)
5039 {
5040         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5041
5042         /* FIXME: Punit isn't quite ready yet */
5043         if (IS_CHERRYVIEW(dev_priv->dev))
5044                 return 400000;
5045
5046         /*
5047          * Really only a few cases to deal with, as only 4 CDclks are supported:
5048          *   200MHz
5049          *   267MHz
5050          *   320/333MHz (depends on HPLL freq)
5051          *   400MHz
5052          * So we check to see whether we're above 90% of the lower bin and
5053          * adjust if needed.
5054          *
5055          * We seem to get an unstable or solid color picture at 200MHz.
5056          * Not sure what's wrong. For now use 200MHz only when all pipes
5057          * are off.
5058          */
5059         if (max_pixclk > freq_320*9/10)
5060                 return 400000;
5061         else if (max_pixclk > 266667*9/10)
5062                 return freq_320;
5063         else if (max_pixclk > 0)
5064                 return 266667;
5065         else
5066                 return 200000;
5067 }
5068
5069 /* compute the max pixel clock for new configuration */
5070 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5071 {
5072         struct drm_device *dev = dev_priv->dev;
5073         struct intel_crtc *intel_crtc;
5074         int max_pixclk = 0;
5075
5076         for_each_intel_crtc(dev, intel_crtc) {
5077                 if (intel_crtc->new_enabled)
5078                         max_pixclk = max(max_pixclk,
5079                                          intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5080         }
5081
5082         return max_pixclk;
5083 }
5084
5085 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5086                                             unsigned *prepare_pipes)
5087 {
5088         struct drm_i915_private *dev_priv = dev->dev_private;
5089         struct intel_crtc *intel_crtc;
5090         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5091
5092         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5093             dev_priv->vlv_cdclk_freq)
5094                 return;
5095
5096         /* disable/enable all currently active pipes while we change cdclk */
5097         for_each_intel_crtc(dev, intel_crtc)
5098                 if (intel_crtc->base.state->enable)
5099                         *prepare_pipes |= (1 << intel_crtc->pipe);
5100 }
5101
5102 static void valleyview_modeset_global_resources(struct drm_device *dev)
5103 {
5104         struct drm_i915_private *dev_priv = dev->dev_private;
5105         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5106         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5107
5108         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5109                 /*
5110                  * FIXME: We can end up here with all power domains off, yet
5111                  * with a CDCLK frequency other than the minimum. To account
5112                  * for this take the PIPE-A power domain, which covers the HW
5113                  * blocks needed for the following programming. This can be
5114                  * removed once it's guaranteed that we get here either with
5115                  * the minimum CDCLK set, or the required power domains
5116                  * enabled.
5117                  */
5118                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5119
5120                 if (IS_CHERRYVIEW(dev))
5121                         cherryview_set_cdclk(dev, req_cdclk);
5122                 else
5123                         valleyview_set_cdclk(dev, req_cdclk);
5124
5125                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5126         }
5127 }
5128
5129 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5130 {
5131         struct drm_device *dev = crtc->dev;
5132         struct drm_i915_private *dev_priv = to_i915(dev);
5133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5134         struct intel_encoder *encoder;
5135         int pipe = intel_crtc->pipe;
5136         bool is_dsi;
5137
5138         WARN_ON(!crtc->state->enable);
5139
5140         if (intel_crtc->active)
5141                 return;
5142
5143         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5144
5145         if (!is_dsi) {
5146                 if (IS_CHERRYVIEW(dev))
5147                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5148                 else
5149                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5150         }
5151
5152         if (intel_crtc->config->has_dp_encoder)
5153                 intel_dp_set_m_n(intel_crtc, M1_N1);
5154
5155         intel_set_pipe_timings(intel_crtc);
5156
5157         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5158                 struct drm_i915_private *dev_priv = dev->dev_private;
5159
5160                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5161                 I915_WRITE(CHV_CANVAS(pipe), 0);
5162         }
5163
5164         i9xx_set_pipeconf(intel_crtc);
5165
5166         intel_crtc->active = true;
5167
5168         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5169
5170         for_each_encoder_on_crtc(dev, crtc, encoder)
5171                 if (encoder->pre_pll_enable)
5172                         encoder->pre_pll_enable(encoder);
5173
5174         if (!is_dsi) {
5175                 if (IS_CHERRYVIEW(dev))
5176                         chv_enable_pll(intel_crtc, intel_crtc->config);
5177                 else
5178                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5179         }
5180
5181         for_each_encoder_on_crtc(dev, crtc, encoder)
5182                 if (encoder->pre_enable)
5183                         encoder->pre_enable(encoder);
5184
5185         i9xx_pfit_enable(intel_crtc);
5186
5187         intel_crtc_load_lut(crtc);
5188
5189         intel_update_watermarks(crtc);
5190         intel_enable_pipe(intel_crtc);
5191
5192         assert_vblank_disabled(crtc);
5193         drm_crtc_vblank_on(crtc);
5194
5195         for_each_encoder_on_crtc(dev, crtc, encoder)
5196                 encoder->enable(encoder);
5197
5198         intel_crtc_enable_planes(crtc);
5199
5200         /* Underruns don't raise interrupts, so check manually. */
5201         i9xx_check_fifo_underruns(dev_priv);
5202 }
5203
5204 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5205 {
5206         struct drm_device *dev = crtc->base.dev;
5207         struct drm_i915_private *dev_priv = dev->dev_private;
5208
5209         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5210         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5211 }
5212
5213 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5214 {
5215         struct drm_device *dev = crtc->dev;
5216         struct drm_i915_private *dev_priv = to_i915(dev);
5217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5218         struct intel_encoder *encoder;
5219         int pipe = intel_crtc->pipe;
5220
5221         WARN_ON(!crtc->state->enable);
5222
5223         if (intel_crtc->active)
5224                 return;
5225
5226         i9xx_set_pll_dividers(intel_crtc);
5227
5228         if (intel_crtc->config->has_dp_encoder)
5229                 intel_dp_set_m_n(intel_crtc, M1_N1);
5230
5231         intel_set_pipe_timings(intel_crtc);
5232
5233         i9xx_set_pipeconf(intel_crtc);
5234
5235         intel_crtc->active = true;
5236
5237         if (!IS_GEN2(dev))
5238                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5239
5240         for_each_encoder_on_crtc(dev, crtc, encoder)
5241                 if (encoder->pre_enable)
5242                         encoder->pre_enable(encoder);
5243
5244         i9xx_enable_pll(intel_crtc);
5245
5246         i9xx_pfit_enable(intel_crtc);
5247
5248         intel_crtc_load_lut(crtc);
5249
5250         intel_update_watermarks(crtc);
5251         intel_enable_pipe(intel_crtc);
5252
5253         assert_vblank_disabled(crtc);
5254         drm_crtc_vblank_on(crtc);
5255
5256         for_each_encoder_on_crtc(dev, crtc, encoder)
5257                 encoder->enable(encoder);
5258
5259         intel_crtc_enable_planes(crtc);
5260
5261         /*
5262          * Gen2 reports pipe underruns whenever all planes are disabled.
5263          * So don't enable underrun reporting before at least some planes
5264          * are enabled.
5265          * FIXME: Need to fix the logic to work when we turn off all planes
5266          * but leave the pipe running.
5267          */
5268         if (IS_GEN2(dev))
5269                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5270
5271         /* Underruns don't raise interrupts, so check manually. */
5272         i9xx_check_fifo_underruns(dev_priv);
5273 }
5274
5275 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5276 {
5277         struct drm_device *dev = crtc->base.dev;
5278         struct drm_i915_private *dev_priv = dev->dev_private;
5279
5280         if (!crtc->config->gmch_pfit.control)
5281                 return;
5282
5283         assert_pipe_disabled(dev_priv, crtc->pipe);
5284
5285         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5286                          I915_READ(PFIT_CONTROL));
5287         I915_WRITE(PFIT_CONTROL, 0);
5288 }
5289
5290 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5291 {
5292         struct drm_device *dev = crtc->dev;
5293         struct drm_i915_private *dev_priv = dev->dev_private;
5294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5295         struct intel_encoder *encoder;
5296         int pipe = intel_crtc->pipe;
5297
5298         if (!intel_crtc->active)
5299                 return;
5300
5301         /*
5302          * Gen2 reports pipe underruns whenever all planes are disabled.
5303          * So diasble underrun reporting before all the planes get disabled.
5304          * FIXME: Need to fix the logic to work when we turn off all planes
5305          * but leave the pipe running.
5306          */
5307         if (IS_GEN2(dev))
5308                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5309
5310         /*
5311          * Vblank time updates from the shadow to live plane control register
5312          * are blocked if the memory self-refresh mode is active at that
5313          * moment. So to make sure the plane gets truly disabled, disable
5314          * first the self-refresh mode. The self-refresh enable bit in turn
5315          * will be checked/applied by the HW only at the next frame start
5316          * event which is after the vblank start event, so we need to have a
5317          * wait-for-vblank between disabling the plane and the pipe.
5318          */
5319         intel_set_memory_cxsr(dev_priv, false);
5320         intel_crtc_disable_planes(crtc);
5321
5322         /*
5323          * On gen2 planes are double buffered but the pipe isn't, so we must
5324          * wait for planes to fully turn off before disabling the pipe.
5325          * We also need to wait on all gmch platforms because of the
5326          * self-refresh mode constraint explained above.
5327          */
5328         intel_wait_for_vblank(dev, pipe);
5329
5330         for_each_encoder_on_crtc(dev, crtc, encoder)
5331                 encoder->disable(encoder);
5332
5333         drm_crtc_vblank_off(crtc);
5334         assert_vblank_disabled(crtc);
5335
5336         intel_disable_pipe(intel_crtc);
5337
5338         i9xx_pfit_disable(intel_crtc);
5339
5340         for_each_encoder_on_crtc(dev, crtc, encoder)
5341                 if (encoder->post_disable)
5342                         encoder->post_disable(encoder);
5343
5344         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5345                 if (IS_CHERRYVIEW(dev))
5346                         chv_disable_pll(dev_priv, pipe);
5347                 else if (IS_VALLEYVIEW(dev))
5348                         vlv_disable_pll(dev_priv, pipe);
5349                 else
5350                         i9xx_disable_pll(intel_crtc);
5351         }
5352
5353         if (!IS_GEN2(dev))
5354                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5355
5356         intel_crtc->active = false;
5357         intel_update_watermarks(crtc);
5358
5359         mutex_lock(&dev->struct_mutex);
5360         intel_fbc_update(dev);
5361         mutex_unlock(&dev->struct_mutex);
5362 }
5363
5364 static void i9xx_crtc_off(struct drm_crtc *crtc)
5365 {
5366 }
5367
5368 /* Master function to enable/disable CRTC and corresponding power wells */
5369 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5370 {
5371         struct drm_device *dev = crtc->dev;
5372         struct drm_i915_private *dev_priv = dev->dev_private;
5373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5374         enum intel_display_power_domain domain;
5375         unsigned long domains;
5376
5377         if (enable) {
5378                 if (!intel_crtc->active) {
5379                         domains = get_crtc_power_domains(crtc);
5380                         for_each_power_domain(domain, domains)
5381                                 intel_display_power_get(dev_priv, domain);
5382                         intel_crtc->enabled_power_domains = domains;
5383
5384                         dev_priv->display.crtc_enable(crtc);
5385                 }
5386         } else {
5387                 if (intel_crtc->active) {
5388                         dev_priv->display.crtc_disable(crtc);
5389
5390                         domains = intel_crtc->enabled_power_domains;
5391                         for_each_power_domain(domain, domains)
5392                                 intel_display_power_put(dev_priv, domain);
5393                         intel_crtc->enabled_power_domains = 0;
5394                 }
5395         }
5396 }
5397
5398 /**
5399  * Sets the power management mode of the pipe and plane.
5400  */
5401 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5402 {
5403         struct drm_device *dev = crtc->dev;
5404         struct intel_encoder *intel_encoder;
5405         bool enable = false;
5406
5407         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5408                 enable |= intel_encoder->connectors_active;
5409
5410         intel_crtc_control(crtc, enable);
5411 }
5412
5413 static void intel_crtc_disable(struct drm_crtc *crtc)
5414 {
5415         struct drm_device *dev = crtc->dev;
5416         struct drm_connector *connector;
5417         struct drm_i915_private *dev_priv = dev->dev_private;
5418
5419         /* crtc should still be enabled when we disable it. */
5420         WARN_ON(!crtc->state->enable);
5421
5422         dev_priv->display.crtc_disable(crtc);
5423         dev_priv->display.off(crtc);
5424
5425         crtc->primary->funcs->disable_plane(crtc->primary);
5426
5427         /* Update computed state. */
5428         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5429                 if (!connector->encoder || !connector->encoder->crtc)
5430                         continue;
5431
5432                 if (connector->encoder->crtc != crtc)
5433                         continue;
5434
5435                 connector->dpms = DRM_MODE_DPMS_OFF;
5436                 to_intel_encoder(connector->encoder)->connectors_active = false;
5437         }
5438 }
5439
5440 void intel_encoder_destroy(struct drm_encoder *encoder)
5441 {
5442         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5443
5444         drm_encoder_cleanup(encoder);
5445         kfree(intel_encoder);
5446 }
5447
5448 /* Simple dpms helper for encoders with just one connector, no cloning and only
5449  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5450  * state of the entire output pipe. */
5451 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5452 {
5453         if (mode == DRM_MODE_DPMS_ON) {
5454                 encoder->connectors_active = true;
5455
5456                 intel_crtc_update_dpms(encoder->base.crtc);
5457         } else {
5458                 encoder->connectors_active = false;
5459
5460                 intel_crtc_update_dpms(encoder->base.crtc);
5461         }
5462 }
5463
5464 /* Cross check the actual hw state with our own modeset state tracking (and it's
5465  * internal consistency). */
5466 static void intel_connector_check_state(struct intel_connector *connector)
5467 {
5468         if (connector->get_hw_state(connector)) {
5469                 struct intel_encoder *encoder = connector->encoder;
5470                 struct drm_crtc *crtc;
5471                 bool encoder_enabled;
5472                 enum pipe pipe;
5473
5474                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5475                               connector->base.base.id,
5476                               connector->base.name);
5477
5478                 /* there is no real hw state for MST connectors */
5479                 if (connector->mst_port)
5480                         return;
5481
5482                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5483                      "wrong connector dpms state\n");
5484                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5485                      "active connector not linked to encoder\n");
5486
5487                 if (encoder) {
5488                         I915_STATE_WARN(!encoder->connectors_active,
5489                              "encoder->connectors_active not set\n");
5490
5491                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5492                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5493                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
5494                                 return;
5495
5496                         crtc = encoder->base.crtc;
5497
5498                         I915_STATE_WARN(!crtc->state->enable,
5499                                         "crtc not enabled\n");
5500                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5501                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5502                              "encoder active on the wrong pipe\n");
5503                 }
5504         }
5505 }
5506
5507 /* Even simpler default implementation, if there's really no special case to
5508  * consider. */
5509 void intel_connector_dpms(struct drm_connector *connector, int mode)
5510 {
5511         /* All the simple cases only support two dpms states. */
5512         if (mode != DRM_MODE_DPMS_ON)
5513                 mode = DRM_MODE_DPMS_OFF;
5514
5515         if (mode == connector->dpms)
5516                 return;
5517
5518         connector->dpms = mode;
5519
5520         /* Only need to change hw state when actually enabled */
5521         if (connector->encoder)
5522                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5523
5524         intel_modeset_check_state(connector->dev);
5525 }
5526
5527 /* Simple connector->get_hw_state implementation for encoders that support only
5528  * one connector and no cloning and hence the encoder state determines the state
5529  * of the connector. */
5530 bool intel_connector_get_hw_state(struct intel_connector *connector)
5531 {
5532         enum pipe pipe = 0;
5533         struct intel_encoder *encoder = connector->encoder;
5534
5535         return encoder->get_hw_state(encoder, &pipe);
5536 }
5537
5538 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5539                                      struct intel_crtc_state *pipe_config)
5540 {
5541         struct drm_i915_private *dev_priv = dev->dev_private;
5542         struct intel_crtc *pipe_B_crtc =
5543                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5544
5545         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5546                       pipe_name(pipe), pipe_config->fdi_lanes);
5547         if (pipe_config->fdi_lanes > 4) {
5548                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5549                               pipe_name(pipe), pipe_config->fdi_lanes);
5550                 return false;
5551         }
5552
5553         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5554                 if (pipe_config->fdi_lanes > 2) {
5555                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5556                                       pipe_config->fdi_lanes);
5557                         return false;
5558                 } else {
5559                         return true;
5560                 }
5561         }
5562
5563         if (INTEL_INFO(dev)->num_pipes == 2)
5564                 return true;
5565
5566         /* Ivybridge 3 pipe is really complicated */
5567         switch (pipe) {
5568         case PIPE_A:
5569                 return true;
5570         case PIPE_B:
5571                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5572                     pipe_config->fdi_lanes > 2) {
5573                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5574                                       pipe_name(pipe), pipe_config->fdi_lanes);
5575                         return false;
5576                 }
5577                 return true;
5578         case PIPE_C:
5579                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5580                     pipe_B_crtc->config->fdi_lanes <= 2) {
5581                         if (pipe_config->fdi_lanes > 2) {
5582                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5583                                               pipe_name(pipe), pipe_config->fdi_lanes);
5584                                 return false;
5585                         }
5586                 } else {
5587                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5588                         return false;
5589                 }
5590                 return true;
5591         default:
5592                 BUG();
5593         }
5594 }
5595
5596 #define RETRY 1
5597 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5598                                        struct intel_crtc_state *pipe_config)
5599 {
5600         struct drm_device *dev = intel_crtc->base.dev;
5601         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5602         int lane, link_bw, fdi_dotclock;
5603         bool setup_ok, needs_recompute = false;
5604
5605 retry:
5606         /* FDI is a binary signal running at ~2.7GHz, encoding
5607          * each output octet as 10 bits. The actual frequency
5608          * is stored as a divider into a 100MHz clock, and the
5609          * mode pixel clock is stored in units of 1KHz.
5610          * Hence the bw of each lane in terms of the mode signal
5611          * is:
5612          */
5613         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5614
5615         fdi_dotclock = adjusted_mode->crtc_clock;
5616
5617         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5618                                            pipe_config->pipe_bpp);
5619
5620         pipe_config->fdi_lanes = lane;
5621
5622         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5623                                link_bw, &pipe_config->fdi_m_n);
5624
5625         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5626                                             intel_crtc->pipe, pipe_config);
5627         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5628                 pipe_config->pipe_bpp -= 2*3;
5629                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5630                               pipe_config->pipe_bpp);
5631                 needs_recompute = true;
5632                 pipe_config->bw_constrained = true;
5633
5634                 goto retry;
5635         }
5636
5637         if (needs_recompute)
5638                 return RETRY;
5639
5640         return setup_ok ? 0 : -EINVAL;
5641 }
5642
5643 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5644                                    struct intel_crtc_state *pipe_config)
5645 {
5646         pipe_config->ips_enabled = i915.enable_ips &&
5647                                    hsw_crtc_supports_ips(crtc) &&
5648                                    pipe_config->pipe_bpp <= 24;
5649 }
5650
5651 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5652                                      struct intel_crtc_state *pipe_config)
5653 {
5654         struct drm_device *dev = crtc->base.dev;
5655         struct drm_i915_private *dev_priv = dev->dev_private;
5656         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5657
5658         /* FIXME should check pixel clock limits on all platforms */
5659         if (INTEL_INFO(dev)->gen < 4) {
5660                 int clock_limit =
5661                         dev_priv->display.get_display_clock_speed(dev);
5662
5663                 /*
5664                  * Enable pixel doubling when the dot clock
5665                  * is > 90% of the (display) core speed.
5666                  *
5667                  * GDG double wide on either pipe,
5668                  * otherwise pipe A only.
5669                  */
5670                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5671                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5672                         clock_limit *= 2;
5673                         pipe_config->double_wide = true;
5674                 }
5675
5676                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5677                         return -EINVAL;
5678         }
5679
5680         /*
5681          * Pipe horizontal size must be even in:
5682          * - DVO ganged mode
5683          * - LVDS dual channel mode
5684          * - Double wide pipe
5685          */
5686         if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5687              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5688                 pipe_config->pipe_src_w &= ~1;
5689
5690         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5691          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5692          */
5693         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5694                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5695                 return -EINVAL;
5696
5697         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5698                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5699         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5700                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5701                  * for lvds. */
5702                 pipe_config->pipe_bpp = 8*3;
5703         }
5704
5705         if (HAS_IPS(dev))
5706                 hsw_compute_ips_config(crtc, pipe_config);
5707
5708         if (pipe_config->has_pch_encoder)
5709                 return ironlake_fdi_compute_config(crtc, pipe_config);
5710
5711         return 0;
5712 }
5713
5714 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5715 {
5716         struct drm_i915_private *dev_priv = dev->dev_private;
5717         u32 val;
5718         int divider;
5719
5720         /* FIXME: Punit isn't quite ready yet */
5721         if (IS_CHERRYVIEW(dev))
5722                 return 400000;
5723
5724         if (dev_priv->hpll_freq == 0)
5725                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5726
5727         mutex_lock(&dev_priv->dpio_lock);
5728         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5729         mutex_unlock(&dev_priv->dpio_lock);
5730
5731         divider = val & DISPLAY_FREQUENCY_VALUES;
5732
5733         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5734              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5735              "cdclk change in progress\n");
5736
5737         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5738 }
5739
5740 static int i945_get_display_clock_speed(struct drm_device *dev)
5741 {
5742         return 400000;
5743 }
5744
5745 static int i915_get_display_clock_speed(struct drm_device *dev)
5746 {
5747         return 333000;
5748 }
5749
5750 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5751 {
5752         return 200000;
5753 }
5754
5755 static int pnv_get_display_clock_speed(struct drm_device *dev)
5756 {
5757         u16 gcfgc = 0;
5758
5759         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5760
5761         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5762         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5763                 return 267000;
5764         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5765                 return 333000;
5766         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5767                 return 444000;
5768         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5769                 return 200000;
5770         default:
5771                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5772         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5773                 return 133000;
5774         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5775                 return 167000;
5776         }
5777 }
5778
5779 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5780 {
5781         u16 gcfgc = 0;
5782
5783         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5784
5785         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5786                 return 133000;
5787         else {
5788                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5789                 case GC_DISPLAY_CLOCK_333_MHZ:
5790                         return 333000;
5791                 default:
5792                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5793                         return 190000;
5794                 }
5795         }
5796 }
5797
5798 static int i865_get_display_clock_speed(struct drm_device *dev)
5799 {
5800         return 266000;
5801 }
5802
5803 static int i855_get_display_clock_speed(struct drm_device *dev)
5804 {
5805         u16 hpllcc = 0;
5806         /* Assume that the hardware is in the high speed state.  This
5807          * should be the default.
5808          */
5809         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5810         case GC_CLOCK_133_200:
5811         case GC_CLOCK_100_200:
5812                 return 200000;
5813         case GC_CLOCK_166_250:
5814                 return 250000;
5815         case GC_CLOCK_100_133:
5816                 return 133000;
5817         }
5818
5819         /* Shouldn't happen */
5820         return 0;
5821 }
5822
5823 static int i830_get_display_clock_speed(struct drm_device *dev)
5824 {
5825         return 133000;
5826 }
5827
5828 static void
5829 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5830 {
5831         while (*num > DATA_LINK_M_N_MASK ||
5832                *den > DATA_LINK_M_N_MASK) {
5833                 *num >>= 1;
5834                 *den >>= 1;
5835         }
5836 }
5837
5838 static void compute_m_n(unsigned int m, unsigned int n,
5839                         uint32_t *ret_m, uint32_t *ret_n)
5840 {
5841         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5842         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5843         intel_reduce_m_n_ratio(ret_m, ret_n);
5844 }
5845
5846 void
5847 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5848                        int pixel_clock, int link_clock,
5849                        struct intel_link_m_n *m_n)
5850 {
5851         m_n->tu = 64;
5852
5853         compute_m_n(bits_per_pixel * pixel_clock,
5854                     link_clock * nlanes * 8,
5855                     &m_n->gmch_m, &m_n->gmch_n);
5856
5857         compute_m_n(pixel_clock, link_clock,
5858                     &m_n->link_m, &m_n->link_n);
5859 }
5860
5861 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5862 {
5863         if (i915.panel_use_ssc >= 0)
5864                 return i915.panel_use_ssc != 0;
5865         return dev_priv->vbt.lvds_use_ssc
5866                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5867 }
5868
5869 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5870 {
5871         struct drm_device *dev = crtc->base.dev;
5872         struct drm_i915_private *dev_priv = dev->dev_private;
5873         int refclk;
5874
5875         if (IS_VALLEYVIEW(dev)) {
5876                 refclk = 100000;
5877         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5878             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5879                 refclk = dev_priv->vbt.lvds_ssc_freq;
5880                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5881         } else if (!IS_GEN2(dev)) {
5882                 refclk = 96000;
5883         } else {
5884                 refclk = 48000;
5885         }
5886
5887         return refclk;
5888 }
5889
5890 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5891 {
5892         return (1 << dpll->n) << 16 | dpll->m2;
5893 }
5894
5895 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5896 {
5897         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5898 }
5899
5900 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5901                                      struct intel_crtc_state *crtc_state,
5902                                      intel_clock_t *reduced_clock)
5903 {
5904         struct drm_device *dev = crtc->base.dev;
5905         u32 fp, fp2 = 0;
5906
5907         if (IS_PINEVIEW(dev)) {
5908                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5909                 if (reduced_clock)
5910                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5911         } else {
5912                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5913                 if (reduced_clock)
5914                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5915         }
5916
5917         crtc_state->dpll_hw_state.fp0 = fp;
5918
5919         crtc->lowfreq_avail = false;
5920         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5921             reduced_clock && i915.powersave) {
5922                 crtc_state->dpll_hw_state.fp1 = fp2;
5923                 crtc->lowfreq_avail = true;
5924         } else {
5925                 crtc_state->dpll_hw_state.fp1 = fp;
5926         }
5927 }
5928
5929 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5930                 pipe)
5931 {
5932         u32 reg_val;
5933
5934         /*
5935          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5936          * and set it to a reasonable value instead.
5937          */
5938         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5939         reg_val &= 0xffffff00;
5940         reg_val |= 0x00000030;
5941         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5942
5943         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5944         reg_val &= 0x8cffffff;
5945         reg_val = 0x8c000000;
5946         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5947
5948         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5949         reg_val &= 0xffffff00;
5950         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5951
5952         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5953         reg_val &= 0x00ffffff;
5954         reg_val |= 0xb0000000;
5955         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5956 }
5957
5958 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5959                                          struct intel_link_m_n *m_n)
5960 {
5961         struct drm_device *dev = crtc->base.dev;
5962         struct drm_i915_private *dev_priv = dev->dev_private;
5963         int pipe = crtc->pipe;
5964
5965         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5966         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5967         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5968         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5969 }
5970
5971 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5972                                          struct intel_link_m_n *m_n,
5973                                          struct intel_link_m_n *m2_n2)
5974 {
5975         struct drm_device *dev = crtc->base.dev;
5976         struct drm_i915_private *dev_priv = dev->dev_private;
5977         int pipe = crtc->pipe;
5978         enum transcoder transcoder = crtc->config->cpu_transcoder;
5979
5980         if (INTEL_INFO(dev)->gen >= 5) {
5981                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5982                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5983                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5984                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5985                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5986                  * for gen < 8) and if DRRS is supported (to make sure the
5987                  * registers are not unnecessarily accessed).
5988                  */
5989                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5990                         crtc->config->has_drrs) {
5991                         I915_WRITE(PIPE_DATA_M2(transcoder),
5992                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5993                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5994                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5995                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5996                 }
5997         } else {
5998                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5999                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6000                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6001                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6002         }
6003 }
6004
6005 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6006 {
6007         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6008
6009         if (m_n == M1_N1) {
6010                 dp_m_n = &crtc->config->dp_m_n;
6011                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6012         } else if (m_n == M2_N2) {
6013
6014                 /*
6015                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6016                  * needs to be programmed into M1_N1.
6017                  */
6018                 dp_m_n = &crtc->config->dp_m2_n2;
6019         } else {
6020                 DRM_ERROR("Unsupported divider value\n");
6021                 return;
6022         }
6023
6024         if (crtc->config->has_pch_encoder)
6025                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6026         else
6027                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6028 }
6029
6030 static void vlv_update_pll(struct intel_crtc *crtc,
6031                            struct intel_crtc_state *pipe_config)
6032 {
6033         u32 dpll, dpll_md;
6034
6035         /*
6036          * Enable DPIO clock input. We should never disable the reference
6037          * clock for pipe B, since VGA hotplug / manual detection depends
6038          * on it.
6039          */
6040         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6041                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6042         /* We should never disable this, set it here for state tracking */
6043         if (crtc->pipe == PIPE_B)
6044                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6045         dpll |= DPLL_VCO_ENABLE;
6046         pipe_config->dpll_hw_state.dpll = dpll;
6047
6048         dpll_md = (pipe_config->pixel_multiplier - 1)
6049                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6050         pipe_config->dpll_hw_state.dpll_md = dpll_md;
6051 }
6052
6053 static void vlv_prepare_pll(struct intel_crtc *crtc,
6054                             const struct intel_crtc_state *pipe_config)
6055 {
6056         struct drm_device *dev = crtc->base.dev;
6057         struct drm_i915_private *dev_priv = dev->dev_private;
6058         int pipe = crtc->pipe;
6059         u32 mdiv;
6060         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6061         u32 coreclk, reg_val;
6062
6063         mutex_lock(&dev_priv->dpio_lock);
6064
6065         bestn = pipe_config->dpll.n;
6066         bestm1 = pipe_config->dpll.m1;
6067         bestm2 = pipe_config->dpll.m2;
6068         bestp1 = pipe_config->dpll.p1;
6069         bestp2 = pipe_config->dpll.p2;
6070
6071         /* See eDP HDMI DPIO driver vbios notes doc */
6072
6073         /* PLL B needs special handling */
6074         if (pipe == PIPE_B)
6075                 vlv_pllb_recal_opamp(dev_priv, pipe);
6076
6077         /* Set up Tx target for periodic Rcomp update */
6078         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6079
6080         /* Disable target IRef on PLL */
6081         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6082         reg_val &= 0x00ffffff;
6083         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6084
6085         /* Disable fast lock */
6086         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6087
6088         /* Set idtafcrecal before PLL is enabled */
6089         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6090         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6091         mdiv |= ((bestn << DPIO_N_SHIFT));
6092         mdiv |= (1 << DPIO_K_SHIFT);
6093
6094         /*
6095          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6096          * but we don't support that).
6097          * Note: don't use the DAC post divider as it seems unstable.
6098          */
6099         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6100         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6101
6102         mdiv |= DPIO_ENABLE_CALIBRATION;
6103         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6104
6105         /* Set HBR and RBR LPF coefficients */
6106         if (pipe_config->port_clock == 162000 ||
6107             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6108             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6109                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6110                                  0x009f0003);
6111         else
6112                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6113                                  0x00d0000f);
6114
6115         if (pipe_config->has_dp_encoder) {
6116                 /* Use SSC source */
6117                 if (pipe == PIPE_A)
6118                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6119                                          0x0df40000);
6120                 else
6121                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6122                                          0x0df70000);
6123         } else { /* HDMI or VGA */
6124                 /* Use bend source */
6125                 if (pipe == PIPE_A)
6126                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6127                                          0x0df70000);
6128                 else
6129                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6130                                          0x0df40000);
6131         }
6132
6133         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6134         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6135         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6136             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6137                 coreclk |= 0x01000000;
6138         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6139
6140         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6141         mutex_unlock(&dev_priv->dpio_lock);
6142 }
6143
6144 static void chv_update_pll(struct intel_crtc *crtc,
6145                            struct intel_crtc_state *pipe_config)
6146 {
6147         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6148                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6149                 DPLL_VCO_ENABLE;
6150         if (crtc->pipe != PIPE_A)
6151                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6152
6153         pipe_config->dpll_hw_state.dpll_md =
6154                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6155 }
6156
6157 static void chv_prepare_pll(struct intel_crtc *crtc,
6158                             const struct intel_crtc_state *pipe_config)
6159 {
6160         struct drm_device *dev = crtc->base.dev;
6161         struct drm_i915_private *dev_priv = dev->dev_private;
6162         int pipe = crtc->pipe;
6163         int dpll_reg = DPLL(crtc->pipe);
6164         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6165         u32 loopfilter, intcoeff;
6166         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6167         int refclk;
6168
6169         bestn = pipe_config->dpll.n;
6170         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6171         bestm1 = pipe_config->dpll.m1;
6172         bestm2 = pipe_config->dpll.m2 >> 22;
6173         bestp1 = pipe_config->dpll.p1;
6174         bestp2 = pipe_config->dpll.p2;
6175
6176         /*
6177          * Enable Refclk and SSC
6178          */
6179         I915_WRITE(dpll_reg,
6180                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6181
6182         mutex_lock(&dev_priv->dpio_lock);
6183
6184         /* p1 and p2 divider */
6185         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6186                         5 << DPIO_CHV_S1_DIV_SHIFT |
6187                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6188                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6189                         1 << DPIO_CHV_K_DIV_SHIFT);
6190
6191         /* Feedback post-divider - m2 */
6192         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6193
6194         /* Feedback refclk divider - n and m1 */
6195         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6196                         DPIO_CHV_M1_DIV_BY_2 |
6197                         1 << DPIO_CHV_N_DIV_SHIFT);
6198
6199         /* M2 fraction division */
6200         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6201
6202         /* M2 fraction division enable */
6203         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6204                        DPIO_CHV_FRAC_DIV_EN |
6205                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6206
6207         /* Loop filter */
6208         refclk = i9xx_get_refclk(crtc, 0);
6209         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6210                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6211         if (refclk == 100000)
6212                 intcoeff = 11;
6213         else if (refclk == 38400)
6214                 intcoeff = 10;
6215         else
6216                 intcoeff = 9;
6217         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6218         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6219
6220         /* AFC Recal */
6221         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6222                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6223                         DPIO_AFC_RECAL);
6224
6225         mutex_unlock(&dev_priv->dpio_lock);
6226 }
6227
6228 /**
6229  * vlv_force_pll_on - forcibly enable just the PLL
6230  * @dev_priv: i915 private structure
6231  * @pipe: pipe PLL to enable
6232  * @dpll: PLL configuration
6233  *
6234  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6235  * in cases where we need the PLL enabled even when @pipe is not going to
6236  * be enabled.
6237  */
6238 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6239                       const struct dpll *dpll)
6240 {
6241         struct intel_crtc *crtc =
6242                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6243         struct intel_crtc_state pipe_config = {
6244                 .pixel_multiplier = 1,
6245                 .dpll = *dpll,
6246         };
6247
6248         if (IS_CHERRYVIEW(dev)) {
6249                 chv_update_pll(crtc, &pipe_config);
6250                 chv_prepare_pll(crtc, &pipe_config);
6251                 chv_enable_pll(crtc, &pipe_config);
6252         } else {
6253                 vlv_update_pll(crtc, &pipe_config);
6254                 vlv_prepare_pll(crtc, &pipe_config);
6255                 vlv_enable_pll(crtc, &pipe_config);
6256         }
6257 }
6258
6259 /**
6260  * vlv_force_pll_off - forcibly disable just the PLL
6261  * @dev_priv: i915 private structure
6262  * @pipe: pipe PLL to disable
6263  *
6264  * Disable the PLL for @pipe. To be used in cases where we need
6265  * the PLL enabled even when @pipe is not going to be enabled.
6266  */
6267 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6268 {
6269         if (IS_CHERRYVIEW(dev))
6270                 chv_disable_pll(to_i915(dev), pipe);
6271         else
6272                 vlv_disable_pll(to_i915(dev), pipe);
6273 }
6274
6275 static void i9xx_update_pll(struct intel_crtc *crtc,
6276                             struct intel_crtc_state *crtc_state,
6277                             intel_clock_t *reduced_clock,
6278                             int num_connectors)
6279 {
6280         struct drm_device *dev = crtc->base.dev;
6281         struct drm_i915_private *dev_priv = dev->dev_private;
6282         u32 dpll;
6283         bool is_sdvo;
6284         struct dpll *clock = &crtc_state->dpll;
6285
6286         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6287
6288         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6289                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6290
6291         dpll = DPLL_VGA_MODE_DIS;
6292
6293         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6294                 dpll |= DPLLB_MODE_LVDS;
6295         else
6296                 dpll |= DPLLB_MODE_DAC_SERIAL;
6297
6298         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6299                 dpll |= (crtc_state->pixel_multiplier - 1)
6300                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6301         }
6302
6303         if (is_sdvo)
6304                 dpll |= DPLL_SDVO_HIGH_SPEED;
6305
6306         if (crtc_state->has_dp_encoder)
6307                 dpll |= DPLL_SDVO_HIGH_SPEED;
6308
6309         /* compute bitmask from p1 value */
6310         if (IS_PINEVIEW(dev))
6311                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6312         else {
6313                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6314                 if (IS_G4X(dev) && reduced_clock)
6315                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6316         }
6317         switch (clock->p2) {
6318         case 5:
6319                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6320                 break;
6321         case 7:
6322                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6323                 break;
6324         case 10:
6325                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6326                 break;
6327         case 14:
6328                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6329                 break;
6330         }
6331         if (INTEL_INFO(dev)->gen >= 4)
6332                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6333
6334         if (crtc_state->sdvo_tv_clock)
6335                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6336         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6337                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6338                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6339         else
6340                 dpll |= PLL_REF_INPUT_DREFCLK;
6341
6342         dpll |= DPLL_VCO_ENABLE;
6343         crtc_state->dpll_hw_state.dpll = dpll;
6344
6345         if (INTEL_INFO(dev)->gen >= 4) {
6346                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6347                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6348                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6349         }
6350 }
6351
6352 static void i8xx_update_pll(struct intel_crtc *crtc,
6353                             struct intel_crtc_state *crtc_state,
6354                             intel_clock_t *reduced_clock,
6355                             int num_connectors)
6356 {
6357         struct drm_device *dev = crtc->base.dev;
6358         struct drm_i915_private *dev_priv = dev->dev_private;
6359         u32 dpll;
6360         struct dpll *clock = &crtc_state->dpll;
6361
6362         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6363
6364         dpll = DPLL_VGA_MODE_DIS;
6365
6366         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6367                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6368         } else {
6369                 if (clock->p1 == 2)
6370                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6371                 else
6372                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6373                 if (clock->p2 == 4)
6374                         dpll |= PLL_P2_DIVIDE_BY_4;
6375         }
6376
6377         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6378                 dpll |= DPLL_DVO_2X_MODE;
6379
6380         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6381                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6382                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6383         else
6384                 dpll |= PLL_REF_INPUT_DREFCLK;
6385
6386         dpll |= DPLL_VCO_ENABLE;
6387         crtc_state->dpll_hw_state.dpll = dpll;
6388 }
6389
6390 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6391 {
6392         struct drm_device *dev = intel_crtc->base.dev;
6393         struct drm_i915_private *dev_priv = dev->dev_private;
6394         enum pipe pipe = intel_crtc->pipe;
6395         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6396         struct drm_display_mode *adjusted_mode =
6397                 &intel_crtc->config->base.adjusted_mode;
6398         uint32_t crtc_vtotal, crtc_vblank_end;
6399         int vsyncshift = 0;
6400
6401         /* We need to be careful not to changed the adjusted mode, for otherwise
6402          * the hw state checker will get angry at the mismatch. */
6403         crtc_vtotal = adjusted_mode->crtc_vtotal;
6404         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6405
6406         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6407                 /* the chip adds 2 halflines automatically */
6408                 crtc_vtotal -= 1;
6409                 crtc_vblank_end -= 1;
6410
6411                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6412                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6413                 else
6414                         vsyncshift = adjusted_mode->crtc_hsync_start -
6415                                 adjusted_mode->crtc_htotal / 2;
6416                 if (vsyncshift < 0)
6417                         vsyncshift += adjusted_mode->crtc_htotal;
6418         }
6419
6420         if (INTEL_INFO(dev)->gen > 3)
6421                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6422
6423         I915_WRITE(HTOTAL(cpu_transcoder),
6424                    (adjusted_mode->crtc_hdisplay - 1) |
6425                    ((adjusted_mode->crtc_htotal - 1) << 16));
6426         I915_WRITE(HBLANK(cpu_transcoder),
6427                    (adjusted_mode->crtc_hblank_start - 1) |
6428                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6429         I915_WRITE(HSYNC(cpu_transcoder),
6430                    (adjusted_mode->crtc_hsync_start - 1) |
6431                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6432
6433         I915_WRITE(VTOTAL(cpu_transcoder),
6434                    (adjusted_mode->crtc_vdisplay - 1) |
6435                    ((crtc_vtotal - 1) << 16));
6436         I915_WRITE(VBLANK(cpu_transcoder),
6437                    (adjusted_mode->crtc_vblank_start - 1) |
6438                    ((crtc_vblank_end - 1) << 16));
6439         I915_WRITE(VSYNC(cpu_transcoder),
6440                    (adjusted_mode->crtc_vsync_start - 1) |
6441                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6442
6443         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6444          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6445          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6446          * bits. */
6447         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6448             (pipe == PIPE_B || pipe == PIPE_C))
6449                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6450
6451         /* pipesrc controls the size that is scaled from, which should
6452          * always be the user's requested size.
6453          */
6454         I915_WRITE(PIPESRC(pipe),
6455                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6456                    (intel_crtc->config->pipe_src_h - 1));
6457 }
6458
6459 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6460                                    struct intel_crtc_state *pipe_config)
6461 {
6462         struct drm_device *dev = crtc->base.dev;
6463         struct drm_i915_private *dev_priv = dev->dev_private;
6464         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6465         uint32_t tmp;
6466
6467         tmp = I915_READ(HTOTAL(cpu_transcoder));
6468         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6469         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6470         tmp = I915_READ(HBLANK(cpu_transcoder));
6471         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6472         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6473         tmp = I915_READ(HSYNC(cpu_transcoder));
6474         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6475         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6476
6477         tmp = I915_READ(VTOTAL(cpu_transcoder));
6478         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6479         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6480         tmp = I915_READ(VBLANK(cpu_transcoder));
6481         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6482         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6483         tmp = I915_READ(VSYNC(cpu_transcoder));
6484         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6485         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6486
6487         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6488                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6489                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6490                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6491         }
6492
6493         tmp = I915_READ(PIPESRC(crtc->pipe));
6494         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6495         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6496
6497         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6498         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6499 }
6500
6501 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6502                                  struct intel_crtc_state *pipe_config)
6503 {
6504         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6505         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6506         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6507         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6508
6509         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6510         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6511         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6512         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6513
6514         mode->flags = pipe_config->base.adjusted_mode.flags;
6515
6516         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6517         mode->flags |= pipe_config->base.adjusted_mode.flags;
6518 }
6519
6520 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6521 {
6522         struct drm_device *dev = intel_crtc->base.dev;
6523         struct drm_i915_private *dev_priv = dev->dev_private;
6524         uint32_t pipeconf;
6525
6526         pipeconf = 0;
6527
6528         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6529             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6530                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6531
6532         if (intel_crtc->config->double_wide)
6533                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6534
6535         /* only g4x and later have fancy bpc/dither controls */
6536         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6537                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6538                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6539                         pipeconf |= PIPECONF_DITHER_EN |
6540                                     PIPECONF_DITHER_TYPE_SP;
6541
6542                 switch (intel_crtc->config->pipe_bpp) {
6543                 case 18:
6544                         pipeconf |= PIPECONF_6BPC;
6545                         break;
6546                 case 24:
6547                         pipeconf |= PIPECONF_8BPC;
6548                         break;
6549                 case 30:
6550                         pipeconf |= PIPECONF_10BPC;
6551                         break;
6552                 default:
6553                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6554                         BUG();
6555                 }
6556         }
6557
6558         if (HAS_PIPE_CXSR(dev)) {
6559                 if (intel_crtc->lowfreq_avail) {
6560                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6561                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6562                 } else {
6563                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6564                 }
6565         }
6566
6567         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6568                 if (INTEL_INFO(dev)->gen < 4 ||
6569                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6570                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6571                 else
6572                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6573         } else
6574                 pipeconf |= PIPECONF_PROGRESSIVE;
6575
6576         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6577                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6578
6579         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6580         POSTING_READ(PIPECONF(intel_crtc->pipe));
6581 }
6582
6583 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6584                                    struct intel_crtc_state *crtc_state)
6585 {
6586         struct drm_device *dev = crtc->base.dev;
6587         struct drm_i915_private *dev_priv = dev->dev_private;
6588         int refclk, num_connectors = 0;
6589         intel_clock_t clock, reduced_clock;
6590         bool ok, has_reduced_clock = false;
6591         bool is_lvds = false, is_dsi = false;
6592         struct intel_encoder *encoder;
6593         const intel_limit_t *limit;
6594
6595         for_each_intel_encoder(dev, encoder) {
6596                 if (encoder->new_crtc != crtc)
6597                         continue;
6598
6599                 switch (encoder->type) {
6600                 case INTEL_OUTPUT_LVDS:
6601                         is_lvds = true;
6602                         break;
6603                 case INTEL_OUTPUT_DSI:
6604                         is_dsi = true;
6605                         break;
6606                 default:
6607                         break;
6608                 }
6609
6610                 num_connectors++;
6611         }
6612
6613         if (is_dsi)
6614                 return 0;
6615
6616         if (!crtc_state->clock_set) {
6617                 refclk = i9xx_get_refclk(crtc, num_connectors);
6618
6619                 /*
6620                  * Returns a set of divisors for the desired target clock with
6621                  * the given refclk, or FALSE.  The returned values represent
6622                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6623                  * 2) / p1 / p2.
6624                  */
6625                 limit = intel_limit(crtc, refclk);
6626                 ok = dev_priv->display.find_dpll(limit, crtc,
6627                                                  crtc_state->port_clock,
6628                                                  refclk, NULL, &clock);
6629                 if (!ok) {
6630                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6631                         return -EINVAL;
6632                 }
6633
6634                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6635                         /*
6636                          * Ensure we match the reduced clock's P to the target
6637                          * clock.  If the clocks don't match, we can't switch
6638                          * the display clock by using the FP0/FP1. In such case
6639                          * we will disable the LVDS downclock feature.
6640                          */
6641                         has_reduced_clock =
6642                                 dev_priv->display.find_dpll(limit, crtc,
6643                                                             dev_priv->lvds_downclock,
6644                                                             refclk, &clock,
6645                                                             &reduced_clock);
6646                 }
6647                 /* Compat-code for transition, will disappear. */
6648                 crtc_state->dpll.n = clock.n;
6649                 crtc_state->dpll.m1 = clock.m1;
6650                 crtc_state->dpll.m2 = clock.m2;
6651                 crtc_state->dpll.p1 = clock.p1;
6652                 crtc_state->dpll.p2 = clock.p2;
6653         }
6654
6655         if (IS_GEN2(dev)) {
6656                 i8xx_update_pll(crtc, crtc_state,
6657                                 has_reduced_clock ? &reduced_clock : NULL,
6658                                 num_connectors);
6659         } else if (IS_CHERRYVIEW(dev)) {
6660                 chv_update_pll(crtc, crtc_state);
6661         } else if (IS_VALLEYVIEW(dev)) {
6662                 vlv_update_pll(crtc, crtc_state);
6663         } else {
6664                 i9xx_update_pll(crtc, crtc_state,
6665                                 has_reduced_clock ? &reduced_clock : NULL,
6666                                 num_connectors);
6667         }
6668
6669         return 0;
6670 }
6671
6672 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6673                                  struct intel_crtc_state *pipe_config)
6674 {
6675         struct drm_device *dev = crtc->base.dev;
6676         struct drm_i915_private *dev_priv = dev->dev_private;
6677         uint32_t tmp;
6678
6679         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6680                 return;
6681
6682         tmp = I915_READ(PFIT_CONTROL);
6683         if (!(tmp & PFIT_ENABLE))
6684                 return;
6685
6686         /* Check whether the pfit is attached to our pipe. */
6687         if (INTEL_INFO(dev)->gen < 4) {
6688                 if (crtc->pipe != PIPE_B)
6689                         return;
6690         } else {
6691                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6692                         return;
6693         }
6694
6695         pipe_config->gmch_pfit.control = tmp;
6696         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6697         if (INTEL_INFO(dev)->gen < 5)
6698                 pipe_config->gmch_pfit.lvds_border_bits =
6699                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6700 }
6701
6702 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6703                                struct intel_crtc_state *pipe_config)
6704 {
6705         struct drm_device *dev = crtc->base.dev;
6706         struct drm_i915_private *dev_priv = dev->dev_private;
6707         int pipe = pipe_config->cpu_transcoder;
6708         intel_clock_t clock;
6709         u32 mdiv;
6710         int refclk = 100000;
6711
6712         /* In case of MIPI DPLL will not even be used */
6713         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6714                 return;
6715
6716         mutex_lock(&dev_priv->dpio_lock);
6717         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6718         mutex_unlock(&dev_priv->dpio_lock);
6719
6720         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6721         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6722         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6723         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6724         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6725
6726         vlv_clock(refclk, &clock);
6727
6728         /* clock.dot is the fast clock */
6729         pipe_config->port_clock = clock.dot / 5;
6730 }
6731
6732 static void
6733 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6734                               struct intel_initial_plane_config *plane_config)
6735 {
6736         struct drm_device *dev = crtc->base.dev;
6737         struct drm_i915_private *dev_priv = dev->dev_private;
6738         u32 val, base, offset;
6739         int pipe = crtc->pipe, plane = crtc->plane;
6740         int fourcc, pixel_format;
6741         int aligned_height;
6742         struct drm_framebuffer *fb;
6743         struct intel_framebuffer *intel_fb;
6744
6745         val = I915_READ(DSPCNTR(plane));
6746         if (!(val & DISPLAY_PLANE_ENABLE))
6747                 return;
6748
6749         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6750         if (!intel_fb) {
6751                 DRM_DEBUG_KMS("failed to alloc fb\n");
6752                 return;
6753         }
6754
6755         fb = &intel_fb->base;
6756
6757         if (INTEL_INFO(dev)->gen >= 4) {
6758                 if (val & DISPPLANE_TILED) {
6759                         plane_config->tiling = I915_TILING_X;
6760                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6761                 }
6762         }
6763
6764         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6765         fourcc = i9xx_format_to_fourcc(pixel_format);
6766         fb->pixel_format = fourcc;
6767         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6768
6769         if (INTEL_INFO(dev)->gen >= 4) {
6770                 if (plane_config->tiling)
6771                         offset = I915_READ(DSPTILEOFF(plane));
6772                 else
6773                         offset = I915_READ(DSPLINOFF(plane));
6774                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6775         } else {
6776                 base = I915_READ(DSPADDR(plane));
6777         }
6778         plane_config->base = base;
6779
6780         val = I915_READ(PIPESRC(pipe));
6781         fb->width = ((val >> 16) & 0xfff) + 1;
6782         fb->height = ((val >> 0) & 0xfff) + 1;
6783
6784         val = I915_READ(DSPSTRIDE(pipe));
6785         fb->pitches[0] = val & 0xffffffc0;
6786
6787         aligned_height = intel_fb_align_height(dev, fb->height,
6788                                                fb->pixel_format,
6789                                                fb->modifier[0]);
6790
6791         plane_config->size = fb->pitches[0] * aligned_height;
6792
6793         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6794                       pipe_name(pipe), plane, fb->width, fb->height,
6795                       fb->bits_per_pixel, base, fb->pitches[0],
6796                       plane_config->size);
6797
6798         plane_config->fb = intel_fb;
6799 }
6800
6801 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6802                                struct intel_crtc_state *pipe_config)
6803 {
6804         struct drm_device *dev = crtc->base.dev;
6805         struct drm_i915_private *dev_priv = dev->dev_private;
6806         int pipe = pipe_config->cpu_transcoder;
6807         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6808         intel_clock_t clock;
6809         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6810         int refclk = 100000;
6811
6812         mutex_lock(&dev_priv->dpio_lock);
6813         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6814         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6815         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6816         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6817         mutex_unlock(&dev_priv->dpio_lock);
6818
6819         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6820         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6821         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6822         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6823         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6824
6825         chv_clock(refclk, &clock);
6826
6827         /* clock.dot is the fast clock */
6828         pipe_config->port_clock = clock.dot / 5;
6829 }
6830
6831 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6832                                  struct intel_crtc_state *pipe_config)
6833 {
6834         struct drm_device *dev = crtc->base.dev;
6835         struct drm_i915_private *dev_priv = dev->dev_private;
6836         uint32_t tmp;
6837
6838         if (!intel_display_power_is_enabled(dev_priv,
6839                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6840                 return false;
6841
6842         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6843         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6844
6845         tmp = I915_READ(PIPECONF(crtc->pipe));
6846         if (!(tmp & PIPECONF_ENABLE))
6847                 return false;
6848
6849         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6850                 switch (tmp & PIPECONF_BPC_MASK) {
6851                 case PIPECONF_6BPC:
6852                         pipe_config->pipe_bpp = 18;
6853                         break;
6854                 case PIPECONF_8BPC:
6855                         pipe_config->pipe_bpp = 24;
6856                         break;
6857                 case PIPECONF_10BPC:
6858                         pipe_config->pipe_bpp = 30;
6859                         break;
6860                 default:
6861                         break;
6862                 }
6863         }
6864
6865         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6866                 pipe_config->limited_color_range = true;
6867
6868         if (INTEL_INFO(dev)->gen < 4)
6869                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6870
6871         intel_get_pipe_timings(crtc, pipe_config);
6872
6873         i9xx_get_pfit_config(crtc, pipe_config);
6874
6875         if (INTEL_INFO(dev)->gen >= 4) {
6876                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6877                 pipe_config->pixel_multiplier =
6878                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6879                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6880                 pipe_config->dpll_hw_state.dpll_md = tmp;
6881         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6882                 tmp = I915_READ(DPLL(crtc->pipe));
6883                 pipe_config->pixel_multiplier =
6884                         ((tmp & SDVO_MULTIPLIER_MASK)
6885                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6886         } else {
6887                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6888                  * port and will be fixed up in the encoder->get_config
6889                  * function. */
6890                 pipe_config->pixel_multiplier = 1;
6891         }
6892         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6893         if (!IS_VALLEYVIEW(dev)) {
6894                 /*
6895                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6896                  * on 830. Filter it out here so that we don't
6897                  * report errors due to that.
6898                  */
6899                 if (IS_I830(dev))
6900                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6901
6902                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6903                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6904         } else {
6905                 /* Mask out read-only status bits. */
6906                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6907                                                      DPLL_PORTC_READY_MASK |
6908                                                      DPLL_PORTB_READY_MASK);
6909         }
6910
6911         if (IS_CHERRYVIEW(dev))
6912                 chv_crtc_clock_get(crtc, pipe_config);
6913         else if (IS_VALLEYVIEW(dev))
6914                 vlv_crtc_clock_get(crtc, pipe_config);
6915         else
6916                 i9xx_crtc_clock_get(crtc, pipe_config);
6917
6918         return true;
6919 }
6920
6921 static void ironlake_init_pch_refclk(struct drm_device *dev)
6922 {
6923         struct drm_i915_private *dev_priv = dev->dev_private;
6924         struct intel_encoder *encoder;
6925         u32 val, final;
6926         bool has_lvds = false;
6927         bool has_cpu_edp = false;
6928         bool has_panel = false;
6929         bool has_ck505 = false;
6930         bool can_ssc = false;
6931
6932         /* We need to take the global config into account */
6933         for_each_intel_encoder(dev, encoder) {
6934                 switch (encoder->type) {
6935                 case INTEL_OUTPUT_LVDS:
6936                         has_panel = true;
6937                         has_lvds = true;
6938                         break;
6939                 case INTEL_OUTPUT_EDP:
6940                         has_panel = true;
6941                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6942                                 has_cpu_edp = true;
6943                         break;
6944                 default:
6945                         break;
6946                 }
6947         }
6948
6949         if (HAS_PCH_IBX(dev)) {
6950                 has_ck505 = dev_priv->vbt.display_clock_mode;
6951                 can_ssc = has_ck505;
6952         } else {
6953                 has_ck505 = false;
6954                 can_ssc = true;
6955         }
6956
6957         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6958                       has_panel, has_lvds, has_ck505);
6959
6960         /* Ironlake: try to setup display ref clock before DPLL
6961          * enabling. This is only under driver's control after
6962          * PCH B stepping, previous chipset stepping should be
6963          * ignoring this setting.
6964          */
6965         val = I915_READ(PCH_DREF_CONTROL);
6966
6967         /* As we must carefully and slowly disable/enable each source in turn,
6968          * compute the final state we want first and check if we need to
6969          * make any changes at all.
6970          */
6971         final = val;
6972         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6973         if (has_ck505)
6974                 final |= DREF_NONSPREAD_CK505_ENABLE;
6975         else
6976                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6977
6978         final &= ~DREF_SSC_SOURCE_MASK;
6979         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6980         final &= ~DREF_SSC1_ENABLE;
6981
6982         if (has_panel) {
6983                 final |= DREF_SSC_SOURCE_ENABLE;
6984
6985                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6986                         final |= DREF_SSC1_ENABLE;
6987
6988                 if (has_cpu_edp) {
6989                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6990                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6991                         else
6992                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6993                 } else
6994                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6995         } else {
6996                 final |= DREF_SSC_SOURCE_DISABLE;
6997                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6998         }
6999
7000         if (final == val)
7001                 return;
7002
7003         /* Always enable nonspread source */
7004         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7005
7006         if (has_ck505)
7007                 val |= DREF_NONSPREAD_CK505_ENABLE;
7008         else
7009                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7010
7011         if (has_panel) {
7012                 val &= ~DREF_SSC_SOURCE_MASK;
7013                 val |= DREF_SSC_SOURCE_ENABLE;
7014
7015                 /* SSC must be turned on before enabling the CPU output  */
7016                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7017                         DRM_DEBUG_KMS("Using SSC on panel\n");
7018                         val |= DREF_SSC1_ENABLE;
7019                 } else
7020                         val &= ~DREF_SSC1_ENABLE;
7021
7022                 /* Get SSC going before enabling the outputs */
7023                 I915_WRITE(PCH_DREF_CONTROL, val);
7024                 POSTING_READ(PCH_DREF_CONTROL);
7025                 udelay(200);
7026
7027                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7028
7029                 /* Enable CPU source on CPU attached eDP */
7030                 if (has_cpu_edp) {
7031                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7032                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7033                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7034                         } else
7035                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7036                 } else
7037                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7038
7039                 I915_WRITE(PCH_DREF_CONTROL, val);
7040                 POSTING_READ(PCH_DREF_CONTROL);
7041                 udelay(200);
7042         } else {
7043                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7044
7045                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7046
7047                 /* Turn off CPU output */
7048                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7049
7050                 I915_WRITE(PCH_DREF_CONTROL, val);
7051                 POSTING_READ(PCH_DREF_CONTROL);
7052                 udelay(200);
7053
7054                 /* Turn off the SSC source */
7055                 val &= ~DREF_SSC_SOURCE_MASK;
7056                 val |= DREF_SSC_SOURCE_DISABLE;
7057
7058                 /* Turn off SSC1 */
7059                 val &= ~DREF_SSC1_ENABLE;
7060
7061                 I915_WRITE(PCH_DREF_CONTROL, val);
7062                 POSTING_READ(PCH_DREF_CONTROL);
7063                 udelay(200);
7064         }
7065
7066         BUG_ON(val != final);
7067 }
7068
7069 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7070 {
7071         uint32_t tmp;
7072
7073         tmp = I915_READ(SOUTH_CHICKEN2);
7074         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7075         I915_WRITE(SOUTH_CHICKEN2, tmp);
7076
7077         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7078                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7079                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7080
7081         tmp = I915_READ(SOUTH_CHICKEN2);
7082         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7083         I915_WRITE(SOUTH_CHICKEN2, tmp);
7084
7085         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7086                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7087                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7088 }
7089
7090 /* WaMPhyProgramming:hsw */
7091 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7092 {
7093         uint32_t tmp;
7094
7095         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7096         tmp &= ~(0xFF << 24);
7097         tmp |= (0x12 << 24);
7098         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7099
7100         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7101         tmp |= (1 << 11);
7102         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7103
7104         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7105         tmp |= (1 << 11);
7106         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7107
7108         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7109         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7110         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7111
7112         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7113         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7114         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7115
7116         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7117         tmp &= ~(7 << 13);
7118         tmp |= (5 << 13);
7119         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7120
7121         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7122         tmp &= ~(7 << 13);
7123         tmp |= (5 << 13);
7124         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7125
7126         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7127         tmp &= ~0xFF;
7128         tmp |= 0x1C;
7129         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7130
7131         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7132         tmp &= ~0xFF;
7133         tmp |= 0x1C;
7134         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7135
7136         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7137         tmp &= ~(0xFF << 16);
7138         tmp |= (0x1C << 16);
7139         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7140
7141         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7142         tmp &= ~(0xFF << 16);
7143         tmp |= (0x1C << 16);
7144         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7145
7146         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7147         tmp |= (1 << 27);
7148         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7149
7150         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7151         tmp |= (1 << 27);
7152         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7153
7154         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7155         tmp &= ~(0xF << 28);
7156         tmp |= (4 << 28);
7157         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7158
7159         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7160         tmp &= ~(0xF << 28);
7161         tmp |= (4 << 28);
7162         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7163 }
7164
7165 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7166  * Programming" based on the parameters passed:
7167  * - Sequence to enable CLKOUT_DP
7168  * - Sequence to enable CLKOUT_DP without spread
7169  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7170  */
7171 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7172                                  bool with_fdi)
7173 {
7174         struct drm_i915_private *dev_priv = dev->dev_private;
7175         uint32_t reg, tmp;
7176
7177         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7178                 with_spread = true;
7179         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7180                  with_fdi, "LP PCH doesn't have FDI\n"))
7181                 with_fdi = false;
7182
7183         mutex_lock(&dev_priv->dpio_lock);
7184
7185         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7186         tmp &= ~SBI_SSCCTL_DISABLE;
7187         tmp |= SBI_SSCCTL_PATHALT;
7188         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7189
7190         udelay(24);
7191
7192         if (with_spread) {
7193                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7194                 tmp &= ~SBI_SSCCTL_PATHALT;
7195                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7196
7197                 if (with_fdi) {
7198                         lpt_reset_fdi_mphy(dev_priv);
7199                         lpt_program_fdi_mphy(dev_priv);
7200                 }
7201         }
7202
7203         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7204                SBI_GEN0 : SBI_DBUFF0;
7205         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7206         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7207         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7208
7209         mutex_unlock(&dev_priv->dpio_lock);
7210 }
7211
7212 /* Sequence to disable CLKOUT_DP */
7213 static void lpt_disable_clkout_dp(struct drm_device *dev)
7214 {
7215         struct drm_i915_private *dev_priv = dev->dev_private;
7216         uint32_t reg, tmp;
7217
7218         mutex_lock(&dev_priv->dpio_lock);
7219
7220         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7221                SBI_GEN0 : SBI_DBUFF0;
7222         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7223         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7224         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7225
7226         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7227         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7228                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7229                         tmp |= SBI_SSCCTL_PATHALT;
7230                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7231                         udelay(32);
7232                 }
7233                 tmp |= SBI_SSCCTL_DISABLE;
7234                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7235         }
7236
7237         mutex_unlock(&dev_priv->dpio_lock);
7238 }
7239
7240 static void lpt_init_pch_refclk(struct drm_device *dev)
7241 {
7242         struct intel_encoder *encoder;
7243         bool has_vga = false;
7244
7245         for_each_intel_encoder(dev, encoder) {
7246                 switch (encoder->type) {
7247                 case INTEL_OUTPUT_ANALOG:
7248                         has_vga = true;
7249                         break;
7250                 default:
7251                         break;
7252                 }
7253         }
7254
7255         if (has_vga)
7256                 lpt_enable_clkout_dp(dev, true, true);
7257         else
7258                 lpt_disable_clkout_dp(dev);
7259 }
7260
7261 /*
7262  * Initialize reference clocks when the driver loads
7263  */
7264 void intel_init_pch_refclk(struct drm_device *dev)
7265 {
7266         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7267                 ironlake_init_pch_refclk(dev);
7268         else if (HAS_PCH_LPT(dev))
7269                 lpt_init_pch_refclk(dev);
7270 }
7271
7272 static int ironlake_get_refclk(struct drm_crtc *crtc)
7273 {
7274         struct drm_device *dev = crtc->dev;
7275         struct drm_i915_private *dev_priv = dev->dev_private;
7276         struct intel_encoder *encoder;
7277         int num_connectors = 0;
7278         bool is_lvds = false;
7279
7280         for_each_intel_encoder(dev, encoder) {
7281                 if (encoder->new_crtc != to_intel_crtc(crtc))
7282                         continue;
7283
7284                 switch (encoder->type) {
7285                 case INTEL_OUTPUT_LVDS:
7286                         is_lvds = true;
7287                         break;
7288                 default:
7289                         break;
7290                 }
7291                 num_connectors++;
7292         }
7293
7294         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7295                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7296                               dev_priv->vbt.lvds_ssc_freq);
7297                 return dev_priv->vbt.lvds_ssc_freq;
7298         }
7299
7300         return 120000;
7301 }
7302
7303 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7304 {
7305         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7307         int pipe = intel_crtc->pipe;
7308         uint32_t val;
7309
7310         val = 0;
7311
7312         switch (intel_crtc->config->pipe_bpp) {
7313         case 18:
7314                 val |= PIPECONF_6BPC;
7315                 break;
7316         case 24:
7317                 val |= PIPECONF_8BPC;
7318                 break;
7319         case 30:
7320                 val |= PIPECONF_10BPC;
7321                 break;
7322         case 36:
7323                 val |= PIPECONF_12BPC;
7324                 break;
7325         default:
7326                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7327                 BUG();
7328         }
7329
7330         if (intel_crtc->config->dither)
7331                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7332
7333         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7334                 val |= PIPECONF_INTERLACED_ILK;
7335         else
7336                 val |= PIPECONF_PROGRESSIVE;
7337
7338         if (intel_crtc->config->limited_color_range)
7339                 val |= PIPECONF_COLOR_RANGE_SELECT;
7340
7341         I915_WRITE(PIPECONF(pipe), val);
7342         POSTING_READ(PIPECONF(pipe));
7343 }
7344
7345 /*
7346  * Set up the pipe CSC unit.
7347  *
7348  * Currently only full range RGB to limited range RGB conversion
7349  * is supported, but eventually this should handle various
7350  * RGB<->YCbCr scenarios as well.
7351  */
7352 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7353 {
7354         struct drm_device *dev = crtc->dev;
7355         struct drm_i915_private *dev_priv = dev->dev_private;
7356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7357         int pipe = intel_crtc->pipe;
7358         uint16_t coeff = 0x7800; /* 1.0 */
7359
7360         /*
7361          * TODO: Check what kind of values actually come out of the pipe
7362          * with these coeff/postoff values and adjust to get the best
7363          * accuracy. Perhaps we even need to take the bpc value into
7364          * consideration.
7365          */
7366
7367         if (intel_crtc->config->limited_color_range)
7368                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7369
7370         /*
7371          * GY/GU and RY/RU should be the other way around according
7372          * to BSpec, but reality doesn't agree. Just set them up in
7373          * a way that results in the correct picture.
7374          */
7375         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7376         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7377
7378         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7379         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7380
7381         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7382         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7383
7384         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7385         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7386         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7387
7388         if (INTEL_INFO(dev)->gen > 6) {
7389                 uint16_t postoff = 0;
7390
7391                 if (intel_crtc->config->limited_color_range)
7392                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7393
7394                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7395                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7396                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7397
7398                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7399         } else {
7400                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7401
7402                 if (intel_crtc->config->limited_color_range)
7403                         mode |= CSC_BLACK_SCREEN_OFFSET;
7404
7405                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7406         }
7407 }
7408
7409 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7410 {
7411         struct drm_device *dev = crtc->dev;
7412         struct drm_i915_private *dev_priv = dev->dev_private;
7413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7414         enum pipe pipe = intel_crtc->pipe;
7415         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7416         uint32_t val;
7417
7418         val = 0;
7419
7420         if (IS_HASWELL(dev) && intel_crtc->config->dither)
7421                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7422
7423         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7424                 val |= PIPECONF_INTERLACED_ILK;
7425         else
7426                 val |= PIPECONF_PROGRESSIVE;
7427
7428         I915_WRITE(PIPECONF(cpu_transcoder), val);
7429         POSTING_READ(PIPECONF(cpu_transcoder));
7430
7431         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7432         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7433
7434         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7435                 val = 0;
7436
7437                 switch (intel_crtc->config->pipe_bpp) {
7438                 case 18:
7439                         val |= PIPEMISC_DITHER_6_BPC;
7440                         break;
7441                 case 24:
7442                         val |= PIPEMISC_DITHER_8_BPC;
7443                         break;
7444                 case 30:
7445                         val |= PIPEMISC_DITHER_10_BPC;
7446                         break;
7447                 case 36:
7448                         val |= PIPEMISC_DITHER_12_BPC;
7449                         break;
7450                 default:
7451                         /* Case prevented by pipe_config_set_bpp. */
7452                         BUG();
7453                 }
7454
7455                 if (intel_crtc->config->dither)
7456                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7457
7458                 I915_WRITE(PIPEMISC(pipe), val);
7459         }
7460 }
7461
7462 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7463                                     struct intel_crtc_state *crtc_state,
7464                                     intel_clock_t *clock,
7465                                     bool *has_reduced_clock,
7466                                     intel_clock_t *reduced_clock)
7467 {
7468         struct drm_device *dev = crtc->dev;
7469         struct drm_i915_private *dev_priv = dev->dev_private;
7470         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7471         int refclk;
7472         const intel_limit_t *limit;
7473         bool ret, is_lvds = false;
7474
7475         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7476
7477         refclk = ironlake_get_refclk(crtc);
7478
7479         /*
7480          * Returns a set of divisors for the desired target clock with the given
7481          * refclk, or FALSE.  The returned values represent the clock equation:
7482          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7483          */
7484         limit = intel_limit(intel_crtc, refclk);
7485         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7486                                           crtc_state->port_clock,
7487                                           refclk, NULL, clock);
7488         if (!ret)
7489                 return false;
7490
7491         if (is_lvds && dev_priv->lvds_downclock_avail) {
7492                 /*
7493                  * Ensure we match the reduced clock's P to the target clock.
7494                  * If the clocks don't match, we can't switch the display clock
7495                  * by using the FP0/FP1. In such case we will disable the LVDS
7496                  * downclock feature.
7497                 */
7498                 *has_reduced_clock =
7499                         dev_priv->display.find_dpll(limit, intel_crtc,
7500                                                     dev_priv->lvds_downclock,
7501                                                     refclk, clock,
7502                                                     reduced_clock);
7503         }
7504
7505         return true;
7506 }
7507
7508 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7509 {
7510         /*
7511          * Account for spread spectrum to avoid
7512          * oversubscribing the link. Max center spread
7513          * is 2.5%; use 5% for safety's sake.
7514          */
7515         u32 bps = target_clock * bpp * 21 / 20;
7516         return DIV_ROUND_UP(bps, link_bw * 8);
7517 }
7518
7519 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7520 {
7521         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7522 }
7523
7524 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7525                                       struct intel_crtc_state *crtc_state,
7526                                       u32 *fp,
7527                                       intel_clock_t *reduced_clock, u32 *fp2)
7528 {
7529         struct drm_crtc *crtc = &intel_crtc->base;
7530         struct drm_device *dev = crtc->dev;
7531         struct drm_i915_private *dev_priv = dev->dev_private;
7532         struct intel_encoder *intel_encoder;
7533         uint32_t dpll;
7534         int factor, num_connectors = 0;
7535         bool is_lvds = false, is_sdvo = false;
7536
7537         for_each_intel_encoder(dev, intel_encoder) {
7538                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7539                         continue;
7540
7541                 switch (intel_encoder->type) {
7542                 case INTEL_OUTPUT_LVDS:
7543                         is_lvds = true;
7544                         break;
7545                 case INTEL_OUTPUT_SDVO:
7546                 case INTEL_OUTPUT_HDMI:
7547                         is_sdvo = true;
7548                         break;
7549                 default:
7550                         break;
7551                 }
7552
7553                 num_connectors++;
7554         }
7555
7556         /* Enable autotuning of the PLL clock (if permissible) */
7557         factor = 21;
7558         if (is_lvds) {
7559                 if ((intel_panel_use_ssc(dev_priv) &&
7560                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7561                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7562                         factor = 25;
7563         } else if (crtc_state->sdvo_tv_clock)
7564                 factor = 20;
7565
7566         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7567                 *fp |= FP_CB_TUNE;
7568
7569         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7570                 *fp2 |= FP_CB_TUNE;
7571
7572         dpll = 0;
7573
7574         if (is_lvds)
7575                 dpll |= DPLLB_MODE_LVDS;
7576         else
7577                 dpll |= DPLLB_MODE_DAC_SERIAL;
7578
7579         dpll |= (crtc_state->pixel_multiplier - 1)
7580                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7581
7582         if (is_sdvo)
7583                 dpll |= DPLL_SDVO_HIGH_SPEED;
7584         if (crtc_state->has_dp_encoder)
7585                 dpll |= DPLL_SDVO_HIGH_SPEED;
7586
7587         /* compute bitmask from p1 value */
7588         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7589         /* also FPA1 */
7590         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7591
7592         switch (crtc_state->dpll.p2) {
7593         case 5:
7594                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7595                 break;
7596         case 7:
7597                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7598                 break;
7599         case 10:
7600                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7601                 break;
7602         case 14:
7603                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7604                 break;
7605         }
7606
7607         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7608                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7609         else
7610                 dpll |= PLL_REF_INPUT_DREFCLK;
7611
7612         return dpll | DPLL_VCO_ENABLE;
7613 }
7614
7615 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7616                                        struct intel_crtc_state *crtc_state)
7617 {
7618         struct drm_device *dev = crtc->base.dev;
7619         intel_clock_t clock, reduced_clock;
7620         u32 dpll = 0, fp = 0, fp2 = 0;
7621         bool ok, has_reduced_clock = false;
7622         bool is_lvds = false;
7623         struct intel_shared_dpll *pll;
7624
7625         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7626
7627         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7628              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7629
7630         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7631                                      &has_reduced_clock, &reduced_clock);
7632         if (!ok && !crtc_state->clock_set) {
7633                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7634                 return -EINVAL;
7635         }
7636         /* Compat-code for transition, will disappear. */
7637         if (!crtc_state->clock_set) {
7638                 crtc_state->dpll.n = clock.n;
7639                 crtc_state->dpll.m1 = clock.m1;
7640                 crtc_state->dpll.m2 = clock.m2;
7641                 crtc_state->dpll.p1 = clock.p1;
7642                 crtc_state->dpll.p2 = clock.p2;
7643         }
7644
7645         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7646         if (crtc_state->has_pch_encoder) {
7647                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7648                 if (has_reduced_clock)
7649                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7650
7651                 dpll = ironlake_compute_dpll(crtc, crtc_state,
7652                                              &fp, &reduced_clock,
7653                                              has_reduced_clock ? &fp2 : NULL);
7654
7655                 crtc_state->dpll_hw_state.dpll = dpll;
7656                 crtc_state->dpll_hw_state.fp0 = fp;
7657                 if (has_reduced_clock)
7658                         crtc_state->dpll_hw_state.fp1 = fp2;
7659                 else
7660                         crtc_state->dpll_hw_state.fp1 = fp;
7661
7662                 pll = intel_get_shared_dpll(crtc, crtc_state);
7663                 if (pll == NULL) {
7664                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7665                                          pipe_name(crtc->pipe));
7666                         return -EINVAL;
7667                 }
7668         }
7669
7670         if (is_lvds && has_reduced_clock && i915.powersave)
7671                 crtc->lowfreq_avail = true;
7672         else
7673                 crtc->lowfreq_avail = false;
7674
7675         return 0;
7676 }
7677
7678 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7679                                          struct intel_link_m_n *m_n)
7680 {
7681         struct drm_device *dev = crtc->base.dev;
7682         struct drm_i915_private *dev_priv = dev->dev_private;
7683         enum pipe pipe = crtc->pipe;
7684
7685         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7686         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7687         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7688                 & ~TU_SIZE_MASK;
7689         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7690         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7691                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7692 }
7693
7694 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7695                                          enum transcoder transcoder,
7696                                          struct intel_link_m_n *m_n,
7697                                          struct intel_link_m_n *m2_n2)
7698 {
7699         struct drm_device *dev = crtc->base.dev;
7700         struct drm_i915_private *dev_priv = dev->dev_private;
7701         enum pipe pipe = crtc->pipe;
7702
7703         if (INTEL_INFO(dev)->gen >= 5) {
7704                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7705                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7706                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7707                         & ~TU_SIZE_MASK;
7708                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7709                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7710                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7711                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7712                  * gen < 8) and if DRRS is supported (to make sure the
7713                  * registers are not unnecessarily read).
7714                  */
7715                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7716                         crtc->config->has_drrs) {
7717                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7718                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7719                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7720                                         & ~TU_SIZE_MASK;
7721                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7722                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7723                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7724                 }
7725         } else {
7726                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7727                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7728                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7729                         & ~TU_SIZE_MASK;
7730                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7731                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7732                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7733         }
7734 }
7735
7736 void intel_dp_get_m_n(struct intel_crtc *crtc,
7737                       struct intel_crtc_state *pipe_config)
7738 {
7739         if (pipe_config->has_pch_encoder)
7740                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7741         else
7742                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7743                                              &pipe_config->dp_m_n,
7744                                              &pipe_config->dp_m2_n2);
7745 }
7746
7747 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7748                                         struct intel_crtc_state *pipe_config)
7749 {
7750         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7751                                      &pipe_config->fdi_m_n, NULL);
7752 }
7753
7754 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7755                                     struct intel_crtc_state *pipe_config)
7756 {
7757         struct drm_device *dev = crtc->base.dev;
7758         struct drm_i915_private *dev_priv = dev->dev_private;
7759         uint32_t tmp;
7760
7761         tmp = I915_READ(PS_CTL(crtc->pipe));
7762
7763         if (tmp & PS_ENABLE) {
7764                 pipe_config->pch_pfit.enabled = true;
7765                 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7766                 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7767         }
7768 }
7769
7770 static void
7771 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7772                                  struct intel_initial_plane_config *plane_config)
7773 {
7774         struct drm_device *dev = crtc->base.dev;
7775         struct drm_i915_private *dev_priv = dev->dev_private;
7776         u32 val, base, offset, stride_mult, tiling;
7777         int pipe = crtc->pipe;
7778         int fourcc, pixel_format;
7779         int aligned_height;
7780         struct drm_framebuffer *fb;
7781         struct intel_framebuffer *intel_fb;
7782
7783         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7784         if (!intel_fb) {
7785                 DRM_DEBUG_KMS("failed to alloc fb\n");
7786                 return;
7787         }
7788
7789         fb = &intel_fb->base;
7790
7791         val = I915_READ(PLANE_CTL(pipe, 0));
7792         if (!(val & PLANE_CTL_ENABLE))
7793                 goto error;
7794
7795         pixel_format = val & PLANE_CTL_FORMAT_MASK;
7796         fourcc = skl_format_to_fourcc(pixel_format,
7797                                       val & PLANE_CTL_ORDER_RGBX,
7798                                       val & PLANE_CTL_ALPHA_MASK);
7799         fb->pixel_format = fourcc;
7800         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7801
7802         tiling = val & PLANE_CTL_TILED_MASK;
7803         switch (tiling) {
7804         case PLANE_CTL_TILED_LINEAR:
7805                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7806                 break;
7807         case PLANE_CTL_TILED_X:
7808                 plane_config->tiling = I915_TILING_X;
7809                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7810                 break;
7811         case PLANE_CTL_TILED_Y:
7812                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7813                 break;
7814         case PLANE_CTL_TILED_YF:
7815                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7816                 break;
7817         default:
7818                 MISSING_CASE(tiling);
7819                 goto error;
7820         }
7821
7822         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7823         plane_config->base = base;
7824
7825         offset = I915_READ(PLANE_OFFSET(pipe, 0));
7826
7827         val = I915_READ(PLANE_SIZE(pipe, 0));
7828         fb->height = ((val >> 16) & 0xfff) + 1;
7829         fb->width = ((val >> 0) & 0x1fff) + 1;
7830
7831         val = I915_READ(PLANE_STRIDE(pipe, 0));
7832         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7833                                                 fb->pixel_format);
7834         fb->pitches[0] = (val & 0x3ff) * stride_mult;
7835
7836         aligned_height = intel_fb_align_height(dev, fb->height,
7837                                                fb->pixel_format,
7838                                                fb->modifier[0]);
7839
7840         plane_config->size = fb->pitches[0] * aligned_height;
7841
7842         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7843                       pipe_name(pipe), fb->width, fb->height,
7844                       fb->bits_per_pixel, base, fb->pitches[0],
7845                       plane_config->size);
7846
7847         plane_config->fb = intel_fb;
7848         return;
7849
7850 error:
7851         kfree(fb);
7852 }
7853
7854 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7855                                      struct intel_crtc_state *pipe_config)
7856 {
7857         struct drm_device *dev = crtc->base.dev;
7858         struct drm_i915_private *dev_priv = dev->dev_private;
7859         uint32_t tmp;
7860
7861         tmp = I915_READ(PF_CTL(crtc->pipe));
7862
7863         if (tmp & PF_ENABLE) {
7864                 pipe_config->pch_pfit.enabled = true;
7865                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7866                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7867
7868                 /* We currently do not free assignements of panel fitters on
7869                  * ivb/hsw (since we don't use the higher upscaling modes which
7870                  * differentiates them) so just WARN about this case for now. */
7871                 if (IS_GEN7(dev)) {
7872                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7873                                 PF_PIPE_SEL_IVB(crtc->pipe));
7874                 }
7875         }
7876 }
7877
7878 static void
7879 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7880                                   struct intel_initial_plane_config *plane_config)
7881 {
7882         struct drm_device *dev = crtc->base.dev;
7883         struct drm_i915_private *dev_priv = dev->dev_private;
7884         u32 val, base, offset;
7885         int pipe = crtc->pipe;
7886         int fourcc, pixel_format;
7887         int aligned_height;
7888         struct drm_framebuffer *fb;
7889         struct intel_framebuffer *intel_fb;
7890
7891         val = I915_READ(DSPCNTR(pipe));
7892         if (!(val & DISPLAY_PLANE_ENABLE))
7893                 return;
7894
7895         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7896         if (!intel_fb) {
7897                 DRM_DEBUG_KMS("failed to alloc fb\n");
7898                 return;
7899         }
7900
7901         fb = &intel_fb->base;
7902
7903         if (INTEL_INFO(dev)->gen >= 4) {
7904                 if (val & DISPPLANE_TILED) {
7905                         plane_config->tiling = I915_TILING_X;
7906                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7907                 }
7908         }
7909
7910         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7911         fourcc = i9xx_format_to_fourcc(pixel_format);
7912         fb->pixel_format = fourcc;
7913         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7914
7915         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7916         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7917                 offset = I915_READ(DSPOFFSET(pipe));
7918         } else {
7919                 if (plane_config->tiling)
7920                         offset = I915_READ(DSPTILEOFF(pipe));
7921                 else
7922                         offset = I915_READ(DSPLINOFF(pipe));
7923         }
7924         plane_config->base = base;
7925
7926         val = I915_READ(PIPESRC(pipe));
7927         fb->width = ((val >> 16) & 0xfff) + 1;
7928         fb->height = ((val >> 0) & 0xfff) + 1;
7929
7930         val = I915_READ(DSPSTRIDE(pipe));
7931         fb->pitches[0] = val & 0xffffffc0;
7932
7933         aligned_height = intel_fb_align_height(dev, fb->height,
7934                                                fb->pixel_format,
7935                                                fb->modifier[0]);
7936
7937         plane_config->size = fb->pitches[0] * aligned_height;
7938
7939         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7940                       pipe_name(pipe), fb->width, fb->height,
7941                       fb->bits_per_pixel, base, fb->pitches[0],
7942                       plane_config->size);
7943
7944         plane_config->fb = intel_fb;
7945 }
7946
7947 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7948                                      struct intel_crtc_state *pipe_config)
7949 {
7950         struct drm_device *dev = crtc->base.dev;
7951         struct drm_i915_private *dev_priv = dev->dev_private;
7952         uint32_t tmp;
7953
7954         if (!intel_display_power_is_enabled(dev_priv,
7955                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7956                 return false;
7957
7958         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7959         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7960
7961         tmp = I915_READ(PIPECONF(crtc->pipe));
7962         if (!(tmp & PIPECONF_ENABLE))
7963                 return false;
7964
7965         switch (tmp & PIPECONF_BPC_MASK) {
7966         case PIPECONF_6BPC:
7967                 pipe_config->pipe_bpp = 18;
7968                 break;
7969         case PIPECONF_8BPC:
7970                 pipe_config->pipe_bpp = 24;
7971                 break;
7972         case PIPECONF_10BPC:
7973                 pipe_config->pipe_bpp = 30;
7974                 break;
7975         case PIPECONF_12BPC:
7976                 pipe_config->pipe_bpp = 36;
7977                 break;
7978         default:
7979                 break;
7980         }
7981
7982         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7983                 pipe_config->limited_color_range = true;
7984
7985         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7986                 struct intel_shared_dpll *pll;
7987
7988                 pipe_config->has_pch_encoder = true;
7989
7990                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7991                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7992                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7993
7994                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7995
7996                 if (HAS_PCH_IBX(dev_priv->dev)) {
7997                         pipe_config->shared_dpll =
7998                                 (enum intel_dpll_id) crtc->pipe;
7999                 } else {
8000                         tmp = I915_READ(PCH_DPLL_SEL);
8001                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8002                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8003                         else
8004                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8005                 }
8006
8007                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8008
8009                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8010                                            &pipe_config->dpll_hw_state));
8011
8012                 tmp = pipe_config->dpll_hw_state.dpll;
8013                 pipe_config->pixel_multiplier =
8014                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8015                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8016
8017                 ironlake_pch_clock_get(crtc, pipe_config);
8018         } else {
8019                 pipe_config->pixel_multiplier = 1;
8020         }
8021
8022         intel_get_pipe_timings(crtc, pipe_config);
8023
8024         ironlake_get_pfit_config(crtc, pipe_config);
8025
8026         return true;
8027 }
8028
8029 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8030 {
8031         struct drm_device *dev = dev_priv->dev;
8032         struct intel_crtc *crtc;
8033
8034         for_each_intel_crtc(dev, crtc)
8035                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8036                      pipe_name(crtc->pipe));
8037
8038         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8039         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8040         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8041         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8042         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8043         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8044              "CPU PWM1 enabled\n");
8045         if (IS_HASWELL(dev))
8046                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8047                      "CPU PWM2 enabled\n");
8048         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8049              "PCH PWM1 enabled\n");
8050         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8051              "Utility pin enabled\n");
8052         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8053
8054         /*
8055          * In theory we can still leave IRQs enabled, as long as only the HPD
8056          * interrupts remain enabled. We used to check for that, but since it's
8057          * gen-specific and since we only disable LCPLL after we fully disable
8058          * the interrupts, the check below should be enough.
8059          */
8060         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8061 }
8062
8063 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8064 {
8065         struct drm_device *dev = dev_priv->dev;
8066
8067         if (IS_HASWELL(dev))
8068                 return I915_READ(D_COMP_HSW);
8069         else
8070                 return I915_READ(D_COMP_BDW);
8071 }
8072
8073 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8074 {
8075         struct drm_device *dev = dev_priv->dev;
8076
8077         if (IS_HASWELL(dev)) {
8078                 mutex_lock(&dev_priv->rps.hw_lock);
8079                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8080                                             val))
8081                         DRM_ERROR("Failed to write to D_COMP\n");
8082                 mutex_unlock(&dev_priv->rps.hw_lock);
8083         } else {
8084                 I915_WRITE(D_COMP_BDW, val);
8085                 POSTING_READ(D_COMP_BDW);
8086         }
8087 }
8088
8089 /*
8090  * This function implements pieces of two sequences from BSpec:
8091  * - Sequence for display software to disable LCPLL
8092  * - Sequence for display software to allow package C8+
8093  * The steps implemented here are just the steps that actually touch the LCPLL
8094  * register. Callers should take care of disabling all the display engine
8095  * functions, doing the mode unset, fixing interrupts, etc.
8096  */
8097 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8098                               bool switch_to_fclk, bool allow_power_down)
8099 {
8100         uint32_t val;
8101
8102         assert_can_disable_lcpll(dev_priv);
8103
8104         val = I915_READ(LCPLL_CTL);
8105
8106         if (switch_to_fclk) {
8107                 val |= LCPLL_CD_SOURCE_FCLK;
8108                 I915_WRITE(LCPLL_CTL, val);
8109
8110                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8111                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
8112                         DRM_ERROR("Switching to FCLK failed\n");
8113
8114                 val = I915_READ(LCPLL_CTL);
8115         }
8116
8117         val |= LCPLL_PLL_DISABLE;
8118         I915_WRITE(LCPLL_CTL, val);
8119         POSTING_READ(LCPLL_CTL);
8120
8121         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8122                 DRM_ERROR("LCPLL still locked\n");
8123
8124         val = hsw_read_dcomp(dev_priv);
8125         val |= D_COMP_COMP_DISABLE;
8126         hsw_write_dcomp(dev_priv, val);
8127         ndelay(100);
8128
8129         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8130                      1))
8131                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8132
8133         if (allow_power_down) {
8134                 val = I915_READ(LCPLL_CTL);
8135                 val |= LCPLL_POWER_DOWN_ALLOW;
8136                 I915_WRITE(LCPLL_CTL, val);
8137                 POSTING_READ(LCPLL_CTL);
8138         }
8139 }
8140
8141 /*
8142  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8143  * source.
8144  */
8145 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8146 {
8147         uint32_t val;
8148
8149         val = I915_READ(LCPLL_CTL);
8150
8151         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8152                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8153                 return;
8154
8155         /*
8156          * Make sure we're not on PC8 state before disabling PC8, otherwise
8157          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8158          */
8159         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8160
8161         if (val & LCPLL_POWER_DOWN_ALLOW) {
8162                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8163                 I915_WRITE(LCPLL_CTL, val);
8164                 POSTING_READ(LCPLL_CTL);
8165         }
8166
8167         val = hsw_read_dcomp(dev_priv);
8168         val |= D_COMP_COMP_FORCE;
8169         val &= ~D_COMP_COMP_DISABLE;
8170         hsw_write_dcomp(dev_priv, val);
8171
8172         val = I915_READ(LCPLL_CTL);
8173         val &= ~LCPLL_PLL_DISABLE;
8174         I915_WRITE(LCPLL_CTL, val);
8175
8176         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8177                 DRM_ERROR("LCPLL not locked yet\n");
8178
8179         if (val & LCPLL_CD_SOURCE_FCLK) {
8180                 val = I915_READ(LCPLL_CTL);
8181                 val &= ~LCPLL_CD_SOURCE_FCLK;
8182                 I915_WRITE(LCPLL_CTL, val);
8183
8184                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8185                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8186                         DRM_ERROR("Switching back to LCPLL failed\n");
8187         }
8188
8189         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8190 }
8191
8192 /*
8193  * Package states C8 and deeper are really deep PC states that can only be
8194  * reached when all the devices on the system allow it, so even if the graphics
8195  * device allows PC8+, it doesn't mean the system will actually get to these
8196  * states. Our driver only allows PC8+ when going into runtime PM.
8197  *
8198  * The requirements for PC8+ are that all the outputs are disabled, the power
8199  * well is disabled and most interrupts are disabled, and these are also
8200  * requirements for runtime PM. When these conditions are met, we manually do
8201  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8202  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8203  * hang the machine.
8204  *
8205  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8206  * the state of some registers, so when we come back from PC8+ we need to
8207  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8208  * need to take care of the registers kept by RC6. Notice that this happens even
8209  * if we don't put the device in PCI D3 state (which is what currently happens
8210  * because of the runtime PM support).
8211  *
8212  * For more, read "Display Sequences for Package C8" on the hardware
8213  * documentation.
8214  */
8215 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8216 {
8217         struct drm_device *dev = dev_priv->dev;
8218         uint32_t val;
8219
8220         DRM_DEBUG_KMS("Enabling package C8+\n");
8221
8222         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8223                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8224                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8225                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8226         }
8227
8228         lpt_disable_clkout_dp(dev);
8229         hsw_disable_lcpll(dev_priv, true, true);
8230 }
8231
8232 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8233 {
8234         struct drm_device *dev = dev_priv->dev;
8235         uint32_t val;
8236
8237         DRM_DEBUG_KMS("Disabling package C8+\n");
8238
8239         hsw_restore_lcpll(dev_priv);
8240         lpt_init_pch_refclk(dev);
8241
8242         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8243                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8244                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8245                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8246         }
8247
8248         intel_prepare_ddi(dev);
8249 }
8250
8251 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8252                                       struct intel_crtc_state *crtc_state)
8253 {
8254         if (!intel_ddi_pll_select(crtc, crtc_state))
8255                 return -EINVAL;
8256
8257         crtc->lowfreq_avail = false;
8258
8259         return 0;
8260 }
8261
8262 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8263                                 enum port port,
8264                                 struct intel_crtc_state *pipe_config)
8265 {
8266         u32 temp, dpll_ctl1;
8267
8268         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8269         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8270
8271         switch (pipe_config->ddi_pll_sel) {
8272         case SKL_DPLL0:
8273                 /*
8274                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8275                  * of the shared DPLL framework and thus needs to be read out
8276                  * separately
8277                  */
8278                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8279                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8280                 break;
8281         case SKL_DPLL1:
8282                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8283                 break;
8284         case SKL_DPLL2:
8285                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8286                 break;
8287         case SKL_DPLL3:
8288                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8289                 break;
8290         }
8291 }
8292
8293 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8294                                 enum port port,
8295                                 struct intel_crtc_state *pipe_config)
8296 {
8297         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8298
8299         switch (pipe_config->ddi_pll_sel) {
8300         case PORT_CLK_SEL_WRPLL1:
8301                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8302                 break;
8303         case PORT_CLK_SEL_WRPLL2:
8304                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8305                 break;
8306         }
8307 }
8308
8309 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8310                                        struct intel_crtc_state *pipe_config)
8311 {
8312         struct drm_device *dev = crtc->base.dev;
8313         struct drm_i915_private *dev_priv = dev->dev_private;
8314         struct intel_shared_dpll *pll;
8315         enum port port;
8316         uint32_t tmp;
8317
8318         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8319
8320         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8321
8322         if (IS_SKYLAKE(dev))
8323                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8324         else
8325                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8326
8327         if (pipe_config->shared_dpll >= 0) {
8328                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8329
8330                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8331                                            &pipe_config->dpll_hw_state));
8332         }
8333
8334         /*
8335          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8336          * DDI E. So just check whether this pipe is wired to DDI E and whether
8337          * the PCH transcoder is on.
8338          */
8339         if (INTEL_INFO(dev)->gen < 9 &&
8340             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8341                 pipe_config->has_pch_encoder = true;
8342
8343                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8344                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8345                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8346
8347                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8348         }
8349 }
8350
8351 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8352                                     struct intel_crtc_state *pipe_config)
8353 {
8354         struct drm_device *dev = crtc->base.dev;
8355         struct drm_i915_private *dev_priv = dev->dev_private;
8356         enum intel_display_power_domain pfit_domain;
8357         uint32_t tmp;
8358
8359         if (!intel_display_power_is_enabled(dev_priv,
8360                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8361                 return false;
8362
8363         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8364         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8365
8366         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8367         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8368                 enum pipe trans_edp_pipe;
8369                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8370                 default:
8371                         WARN(1, "unknown pipe linked to edp transcoder\n");
8372                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8373                 case TRANS_DDI_EDP_INPUT_A_ON:
8374                         trans_edp_pipe = PIPE_A;
8375                         break;
8376                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8377                         trans_edp_pipe = PIPE_B;
8378                         break;
8379                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8380                         trans_edp_pipe = PIPE_C;
8381                         break;
8382                 }
8383
8384                 if (trans_edp_pipe == crtc->pipe)
8385                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8386         }
8387
8388         if (!intel_display_power_is_enabled(dev_priv,
8389                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8390                 return false;
8391
8392         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8393         if (!(tmp & PIPECONF_ENABLE))
8394                 return false;
8395
8396         haswell_get_ddi_port_state(crtc, pipe_config);
8397
8398         intel_get_pipe_timings(crtc, pipe_config);
8399
8400         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8401         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8402                 if (IS_SKYLAKE(dev))
8403                         skylake_get_pfit_config(crtc, pipe_config);
8404                 else
8405                         ironlake_get_pfit_config(crtc, pipe_config);
8406         }
8407
8408         if (IS_HASWELL(dev))
8409                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8410                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8411
8412         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8413                 pipe_config->pixel_multiplier =
8414                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8415         } else {
8416                 pipe_config->pixel_multiplier = 1;
8417         }
8418
8419         return true;
8420 }
8421
8422 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8423 {
8424         struct drm_device *dev = crtc->dev;
8425         struct drm_i915_private *dev_priv = dev->dev_private;
8426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8427         uint32_t cntl = 0, size = 0;
8428
8429         if (base) {
8430                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8431                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8432                 unsigned int stride = roundup_pow_of_two(width) * 4;
8433
8434                 switch (stride) {
8435                 default:
8436                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8437                                   width, stride);
8438                         stride = 256;
8439                         /* fallthrough */
8440                 case 256:
8441                 case 512:
8442                 case 1024:
8443                 case 2048:
8444                         break;
8445                 }
8446
8447                 cntl |= CURSOR_ENABLE |
8448                         CURSOR_GAMMA_ENABLE |
8449                         CURSOR_FORMAT_ARGB |
8450                         CURSOR_STRIDE(stride);
8451
8452                 size = (height << 12) | width;
8453         }
8454
8455         if (intel_crtc->cursor_cntl != 0 &&
8456             (intel_crtc->cursor_base != base ||
8457              intel_crtc->cursor_size != size ||
8458              intel_crtc->cursor_cntl != cntl)) {
8459                 /* On these chipsets we can only modify the base/size/stride
8460                  * whilst the cursor is disabled.
8461                  */
8462                 I915_WRITE(_CURACNTR, 0);
8463                 POSTING_READ(_CURACNTR);
8464                 intel_crtc->cursor_cntl = 0;
8465         }
8466
8467         if (intel_crtc->cursor_base != base) {
8468                 I915_WRITE(_CURABASE, base);
8469                 intel_crtc->cursor_base = base;
8470         }
8471
8472         if (intel_crtc->cursor_size != size) {
8473                 I915_WRITE(CURSIZE, size);
8474                 intel_crtc->cursor_size = size;
8475         }
8476
8477         if (intel_crtc->cursor_cntl != cntl) {
8478                 I915_WRITE(_CURACNTR, cntl);
8479                 POSTING_READ(_CURACNTR);
8480                 intel_crtc->cursor_cntl = cntl;
8481         }
8482 }
8483
8484 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8485 {
8486         struct drm_device *dev = crtc->dev;
8487         struct drm_i915_private *dev_priv = dev->dev_private;
8488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8489         int pipe = intel_crtc->pipe;
8490         uint32_t cntl;
8491
8492         cntl = 0;
8493         if (base) {
8494                 cntl = MCURSOR_GAMMA_ENABLE;
8495                 switch (intel_crtc->base.cursor->state->crtc_w) {
8496                         case 64:
8497                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8498                                 break;
8499                         case 128:
8500                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8501                                 break;
8502                         case 256:
8503                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8504                                 break;
8505                         default:
8506                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8507                                 return;
8508                 }
8509                 cntl |= pipe << 28; /* Connect to correct pipe */
8510
8511                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8512                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8513         }
8514
8515         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8516                 cntl |= CURSOR_ROTATE_180;
8517
8518         if (intel_crtc->cursor_cntl != cntl) {
8519                 I915_WRITE(CURCNTR(pipe), cntl);
8520                 POSTING_READ(CURCNTR(pipe));
8521                 intel_crtc->cursor_cntl = cntl;
8522         }
8523
8524         /* and commit changes on next vblank */
8525         I915_WRITE(CURBASE(pipe), base);
8526         POSTING_READ(CURBASE(pipe));
8527
8528         intel_crtc->cursor_base = base;
8529 }
8530
8531 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8532 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8533                                      bool on)
8534 {
8535         struct drm_device *dev = crtc->dev;
8536         struct drm_i915_private *dev_priv = dev->dev_private;
8537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8538         int pipe = intel_crtc->pipe;
8539         int x = crtc->cursor_x;
8540         int y = crtc->cursor_y;
8541         u32 base = 0, pos = 0;
8542
8543         if (on)
8544                 base = intel_crtc->cursor_addr;
8545
8546         if (x >= intel_crtc->config->pipe_src_w)
8547                 base = 0;
8548
8549         if (y >= intel_crtc->config->pipe_src_h)
8550                 base = 0;
8551
8552         if (x < 0) {
8553                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8554                         base = 0;
8555
8556                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8557                 x = -x;
8558         }
8559         pos |= x << CURSOR_X_SHIFT;
8560
8561         if (y < 0) {
8562                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8563                         base = 0;
8564
8565                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8566                 y = -y;
8567         }
8568         pos |= y << CURSOR_Y_SHIFT;
8569
8570         if (base == 0 && intel_crtc->cursor_base == 0)
8571                 return;
8572
8573         I915_WRITE(CURPOS(pipe), pos);
8574
8575         /* ILK+ do this automagically */
8576         if (HAS_GMCH_DISPLAY(dev) &&
8577             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8578                 base += (intel_crtc->base.cursor->state->crtc_h *
8579                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8580         }
8581
8582         if (IS_845G(dev) || IS_I865G(dev))
8583                 i845_update_cursor(crtc, base);
8584         else
8585                 i9xx_update_cursor(crtc, base);
8586 }
8587
8588 static bool cursor_size_ok(struct drm_device *dev,
8589                            uint32_t width, uint32_t height)
8590 {
8591         if (width == 0 || height == 0)
8592                 return false;
8593
8594         /*
8595          * 845g/865g are special in that they are only limited by
8596          * the width of their cursors, the height is arbitrary up to
8597          * the precision of the register. Everything else requires
8598          * square cursors, limited to a few power-of-two sizes.
8599          */
8600         if (IS_845G(dev) || IS_I865G(dev)) {
8601                 if ((width & 63) != 0)
8602                         return false;
8603
8604                 if (width > (IS_845G(dev) ? 64 : 512))
8605                         return false;
8606
8607                 if (height > 1023)
8608                         return false;
8609         } else {
8610                 switch (width | height) {
8611                 case 256:
8612                 case 128:
8613                         if (IS_GEN2(dev))
8614                                 return false;
8615                 case 64:
8616                         break;
8617                 default:
8618                         return false;
8619                 }
8620         }
8621
8622         return true;
8623 }
8624
8625 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8626                                  u16 *blue, uint32_t start, uint32_t size)
8627 {
8628         int end = (start + size > 256) ? 256 : start + size, i;
8629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8630
8631         for (i = start; i < end; i++) {
8632                 intel_crtc->lut_r[i] = red[i] >> 8;
8633                 intel_crtc->lut_g[i] = green[i] >> 8;
8634                 intel_crtc->lut_b[i] = blue[i] >> 8;
8635         }
8636
8637         intel_crtc_load_lut(crtc);
8638 }
8639
8640 /* VESA 640x480x72Hz mode to set on the pipe */
8641 static struct drm_display_mode load_detect_mode = {
8642         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8643                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8644 };
8645
8646 struct drm_framebuffer *
8647 __intel_framebuffer_create(struct drm_device *dev,
8648                            struct drm_mode_fb_cmd2 *mode_cmd,
8649                            struct drm_i915_gem_object *obj)
8650 {
8651         struct intel_framebuffer *intel_fb;
8652         int ret;
8653
8654         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8655         if (!intel_fb) {
8656                 drm_gem_object_unreference(&obj->base);
8657                 return ERR_PTR(-ENOMEM);
8658         }
8659
8660         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8661         if (ret)
8662                 goto err;
8663
8664         return &intel_fb->base;
8665 err:
8666         drm_gem_object_unreference(&obj->base);
8667         kfree(intel_fb);
8668
8669         return ERR_PTR(ret);
8670 }
8671
8672 static struct drm_framebuffer *
8673 intel_framebuffer_create(struct drm_device *dev,
8674                          struct drm_mode_fb_cmd2 *mode_cmd,
8675                          struct drm_i915_gem_object *obj)
8676 {
8677         struct drm_framebuffer *fb;
8678         int ret;
8679
8680         ret = i915_mutex_lock_interruptible(dev);
8681         if (ret)
8682                 return ERR_PTR(ret);
8683         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8684         mutex_unlock(&dev->struct_mutex);
8685
8686         return fb;
8687 }
8688
8689 static u32
8690 intel_framebuffer_pitch_for_width(int width, int bpp)
8691 {
8692         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8693         return ALIGN(pitch, 64);
8694 }
8695
8696 static u32
8697 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8698 {
8699         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8700         return PAGE_ALIGN(pitch * mode->vdisplay);
8701 }
8702
8703 static struct drm_framebuffer *
8704 intel_framebuffer_create_for_mode(struct drm_device *dev,
8705                                   struct drm_display_mode *mode,
8706                                   int depth, int bpp)
8707 {
8708         struct drm_i915_gem_object *obj;
8709         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8710
8711         obj = i915_gem_alloc_object(dev,
8712                                     intel_framebuffer_size_for_mode(mode, bpp));
8713         if (obj == NULL)
8714                 return ERR_PTR(-ENOMEM);
8715
8716         mode_cmd.width = mode->hdisplay;
8717         mode_cmd.height = mode->vdisplay;
8718         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8719                                                                 bpp);
8720         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8721
8722         return intel_framebuffer_create(dev, &mode_cmd, obj);
8723 }
8724
8725 static struct drm_framebuffer *
8726 mode_fits_in_fbdev(struct drm_device *dev,
8727                    struct drm_display_mode *mode)
8728 {
8729 #ifdef CONFIG_DRM_I915_FBDEV
8730         struct drm_i915_private *dev_priv = dev->dev_private;
8731         struct drm_i915_gem_object *obj;
8732         struct drm_framebuffer *fb;
8733
8734         if (!dev_priv->fbdev)
8735                 return NULL;
8736
8737         if (!dev_priv->fbdev->fb)
8738                 return NULL;
8739
8740         obj = dev_priv->fbdev->fb->obj;
8741         BUG_ON(!obj);
8742
8743         fb = &dev_priv->fbdev->fb->base;
8744         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8745                                                                fb->bits_per_pixel))
8746                 return NULL;
8747
8748         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8749                 return NULL;
8750
8751         return fb;
8752 #else
8753         return NULL;
8754 #endif
8755 }
8756
8757 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8758                                 struct drm_display_mode *mode,
8759                                 struct intel_load_detect_pipe *old,
8760                                 struct drm_modeset_acquire_ctx *ctx)
8761 {
8762         struct intel_crtc *intel_crtc;
8763         struct intel_encoder *intel_encoder =
8764                 intel_attached_encoder(connector);
8765         struct drm_crtc *possible_crtc;
8766         struct drm_encoder *encoder = &intel_encoder->base;
8767         struct drm_crtc *crtc = NULL;
8768         struct drm_device *dev = encoder->dev;
8769         struct drm_framebuffer *fb;
8770         struct drm_mode_config *config = &dev->mode_config;
8771         int ret, i = -1;
8772
8773         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8774                       connector->base.id, connector->name,
8775                       encoder->base.id, encoder->name);
8776
8777 retry:
8778         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8779         if (ret)
8780                 goto fail_unlock;
8781
8782         /*
8783          * Algorithm gets a little messy:
8784          *
8785          *   - if the connector already has an assigned crtc, use it (but make
8786          *     sure it's on first)
8787          *
8788          *   - try to find the first unused crtc that can drive this connector,
8789          *     and use that if we find one
8790          */
8791
8792         /* See if we already have a CRTC for this connector */
8793         if (encoder->crtc) {
8794                 crtc = encoder->crtc;
8795
8796                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8797                 if (ret)
8798                         goto fail_unlock;
8799                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8800                 if (ret)
8801                         goto fail_unlock;
8802
8803                 old->dpms_mode = connector->dpms;
8804                 old->load_detect_temp = false;
8805
8806                 /* Make sure the crtc and connector are running */
8807                 if (connector->dpms != DRM_MODE_DPMS_ON)
8808                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8809
8810                 return true;
8811         }
8812
8813         /* Find an unused one (if possible) */
8814         for_each_crtc(dev, possible_crtc) {
8815                 i++;
8816                 if (!(encoder->possible_crtcs & (1 << i)))
8817                         continue;
8818                 if (possible_crtc->state->enable)
8819                         continue;
8820                 /* This can occur when applying the pipe A quirk on resume. */
8821                 if (to_intel_crtc(possible_crtc)->new_enabled)
8822                         continue;
8823
8824                 crtc = possible_crtc;
8825                 break;
8826         }
8827
8828         /*
8829          * If we didn't find an unused CRTC, don't use any.
8830          */
8831         if (!crtc) {
8832                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8833                 goto fail_unlock;
8834         }
8835
8836         ret = drm_modeset_lock(&crtc->mutex, ctx);
8837         if (ret)
8838                 goto fail_unlock;
8839         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8840         if (ret)
8841                 goto fail_unlock;
8842         intel_encoder->new_crtc = to_intel_crtc(crtc);
8843         to_intel_connector(connector)->new_encoder = intel_encoder;
8844
8845         intel_crtc = to_intel_crtc(crtc);
8846         intel_crtc->new_enabled = true;
8847         intel_crtc->new_config = intel_crtc->config;
8848         old->dpms_mode = connector->dpms;
8849         old->load_detect_temp = true;
8850         old->release_fb = NULL;
8851
8852         if (!mode)
8853                 mode = &load_detect_mode;
8854
8855         /* We need a framebuffer large enough to accommodate all accesses
8856          * that the plane may generate whilst we perform load detection.
8857          * We can not rely on the fbcon either being present (we get called
8858          * during its initialisation to detect all boot displays, or it may
8859          * not even exist) or that it is large enough to satisfy the
8860          * requested mode.
8861          */
8862         fb = mode_fits_in_fbdev(dev, mode);
8863         if (fb == NULL) {
8864                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8865                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8866                 old->release_fb = fb;
8867         } else
8868                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8869         if (IS_ERR(fb)) {
8870                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8871                 goto fail;
8872         }
8873
8874         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8875                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8876                 if (old->release_fb)
8877                         old->release_fb->funcs->destroy(old->release_fb);
8878                 goto fail;
8879         }
8880         crtc->primary->crtc = crtc;
8881
8882         /* let the connector get through one full cycle before testing */
8883         intel_wait_for_vblank(dev, intel_crtc->pipe);
8884         return true;
8885
8886  fail:
8887         intel_crtc->new_enabled = crtc->state->enable;
8888         if (intel_crtc->new_enabled)
8889                 intel_crtc->new_config = intel_crtc->config;
8890         else
8891                 intel_crtc->new_config = NULL;
8892 fail_unlock:
8893         if (ret == -EDEADLK) {
8894                 drm_modeset_backoff(ctx);
8895                 goto retry;
8896         }
8897
8898         return false;
8899 }
8900
8901 void intel_release_load_detect_pipe(struct drm_connector *connector,
8902                                     struct intel_load_detect_pipe *old)
8903 {
8904         struct intel_encoder *intel_encoder =
8905                 intel_attached_encoder(connector);
8906         struct drm_encoder *encoder = &intel_encoder->base;
8907         struct drm_crtc *crtc = encoder->crtc;
8908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8909
8910         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8911                       connector->base.id, connector->name,
8912                       encoder->base.id, encoder->name);
8913
8914         if (old->load_detect_temp) {
8915                 to_intel_connector(connector)->new_encoder = NULL;
8916                 intel_encoder->new_crtc = NULL;
8917                 intel_crtc->new_enabled = false;
8918                 intel_crtc->new_config = NULL;
8919                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8920
8921                 if (old->release_fb) {
8922                         drm_framebuffer_unregister_private(old->release_fb);
8923                         drm_framebuffer_unreference(old->release_fb);
8924                 }
8925
8926                 return;
8927         }
8928
8929         /* Switch crtc and encoder back off if necessary */
8930         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8931                 connector->funcs->dpms(connector, old->dpms_mode);
8932 }
8933
8934 static int i9xx_pll_refclk(struct drm_device *dev,
8935                            const struct intel_crtc_state *pipe_config)
8936 {
8937         struct drm_i915_private *dev_priv = dev->dev_private;
8938         u32 dpll = pipe_config->dpll_hw_state.dpll;
8939
8940         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8941                 return dev_priv->vbt.lvds_ssc_freq;
8942         else if (HAS_PCH_SPLIT(dev))
8943                 return 120000;
8944         else if (!IS_GEN2(dev))
8945                 return 96000;
8946         else
8947                 return 48000;
8948 }
8949
8950 /* Returns the clock of the currently programmed mode of the given pipe. */
8951 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8952                                 struct intel_crtc_state *pipe_config)
8953 {
8954         struct drm_device *dev = crtc->base.dev;
8955         struct drm_i915_private *dev_priv = dev->dev_private;
8956         int pipe = pipe_config->cpu_transcoder;
8957         u32 dpll = pipe_config->dpll_hw_state.dpll;
8958         u32 fp;
8959         intel_clock_t clock;
8960         int refclk = i9xx_pll_refclk(dev, pipe_config);
8961
8962         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8963                 fp = pipe_config->dpll_hw_state.fp0;
8964         else
8965                 fp = pipe_config->dpll_hw_state.fp1;
8966
8967         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8968         if (IS_PINEVIEW(dev)) {
8969                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8970                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8971         } else {
8972                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8973                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8974         }
8975
8976         if (!IS_GEN2(dev)) {
8977                 if (IS_PINEVIEW(dev))
8978                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8979                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8980                 else
8981                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8982                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8983
8984                 switch (dpll & DPLL_MODE_MASK) {
8985                 case DPLLB_MODE_DAC_SERIAL:
8986                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8987                                 5 : 10;
8988                         break;
8989                 case DPLLB_MODE_LVDS:
8990                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8991                                 7 : 14;
8992                         break;
8993                 default:
8994                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8995                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8996                         return;
8997                 }
8998
8999                 if (IS_PINEVIEW(dev))
9000                         pineview_clock(refclk, &clock);
9001                 else
9002                         i9xx_clock(refclk, &clock);
9003         } else {
9004                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9005                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9006
9007                 if (is_lvds) {
9008                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9009                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9010
9011                         if (lvds & LVDS_CLKB_POWER_UP)
9012                                 clock.p2 = 7;
9013                         else
9014                                 clock.p2 = 14;
9015                 } else {
9016                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9017                                 clock.p1 = 2;
9018                         else {
9019                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9020                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9021                         }
9022                         if (dpll & PLL_P2_DIVIDE_BY_4)
9023                                 clock.p2 = 4;
9024                         else
9025                                 clock.p2 = 2;
9026                 }
9027
9028                 i9xx_clock(refclk, &clock);
9029         }
9030
9031         /*
9032          * This value includes pixel_multiplier. We will use
9033          * port_clock to compute adjusted_mode.crtc_clock in the
9034          * encoder's get_config() function.
9035          */
9036         pipe_config->port_clock = clock.dot;
9037 }
9038
9039 int intel_dotclock_calculate(int link_freq,
9040                              const struct intel_link_m_n *m_n)
9041 {
9042         /*
9043          * The calculation for the data clock is:
9044          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9045          * But we want to avoid losing precison if possible, so:
9046          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9047          *
9048          * and the link clock is simpler:
9049          * link_clock = (m * link_clock) / n
9050          */
9051
9052         if (!m_n->link_n)
9053                 return 0;
9054
9055         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9056 }
9057
9058 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9059                                    struct intel_crtc_state *pipe_config)
9060 {
9061         struct drm_device *dev = crtc->base.dev;
9062
9063         /* read out port_clock from the DPLL */
9064         i9xx_crtc_clock_get(crtc, pipe_config);
9065
9066         /*
9067          * This value does not include pixel_multiplier.
9068          * We will check that port_clock and adjusted_mode.crtc_clock
9069          * agree once we know their relationship in the encoder's
9070          * get_config() function.
9071          */
9072         pipe_config->base.adjusted_mode.crtc_clock =
9073                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9074                                          &pipe_config->fdi_m_n);
9075 }
9076
9077 /** Returns the currently programmed mode of the given pipe. */
9078 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9079                                              struct drm_crtc *crtc)
9080 {
9081         struct drm_i915_private *dev_priv = dev->dev_private;
9082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9083         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9084         struct drm_display_mode *mode;
9085         struct intel_crtc_state pipe_config;
9086         int htot = I915_READ(HTOTAL(cpu_transcoder));
9087         int hsync = I915_READ(HSYNC(cpu_transcoder));
9088         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9089         int vsync = I915_READ(VSYNC(cpu_transcoder));
9090         enum pipe pipe = intel_crtc->pipe;
9091
9092         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9093         if (!mode)
9094                 return NULL;
9095
9096         /*
9097          * Construct a pipe_config sufficient for getting the clock info
9098          * back out of crtc_clock_get.
9099          *
9100          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9101          * to use a real value here instead.
9102          */
9103         pipe_config.cpu_transcoder = (enum transcoder) pipe;
9104         pipe_config.pixel_multiplier = 1;
9105         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9106         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9107         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9108         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9109
9110         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9111         mode->hdisplay = (htot & 0xffff) + 1;
9112         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9113         mode->hsync_start = (hsync & 0xffff) + 1;
9114         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9115         mode->vdisplay = (vtot & 0xffff) + 1;
9116         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9117         mode->vsync_start = (vsync & 0xffff) + 1;
9118         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9119
9120         drm_mode_set_name(mode);
9121
9122         return mode;
9123 }
9124
9125 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9126 {
9127         struct drm_device *dev = crtc->dev;
9128         struct drm_i915_private *dev_priv = dev->dev_private;
9129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9130
9131         if (!HAS_GMCH_DISPLAY(dev))
9132                 return;
9133
9134         if (!dev_priv->lvds_downclock_avail)
9135                 return;
9136
9137         /*
9138          * Since this is called by a timer, we should never get here in
9139          * the manual case.
9140          */
9141         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9142                 int pipe = intel_crtc->pipe;
9143                 int dpll_reg = DPLL(pipe);
9144                 int dpll;
9145
9146                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9147
9148                 assert_panel_unlocked(dev_priv, pipe);
9149
9150                 dpll = I915_READ(dpll_reg);
9151                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9152                 I915_WRITE(dpll_reg, dpll);
9153                 intel_wait_for_vblank(dev, pipe);
9154                 dpll = I915_READ(dpll_reg);
9155                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9156                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9157         }
9158
9159 }
9160
9161 void intel_mark_busy(struct drm_device *dev)
9162 {
9163         struct drm_i915_private *dev_priv = dev->dev_private;
9164
9165         if (dev_priv->mm.busy)
9166                 return;
9167
9168         intel_runtime_pm_get(dev_priv);
9169         i915_update_gfx_val(dev_priv);
9170         dev_priv->mm.busy = true;
9171 }
9172
9173 void intel_mark_idle(struct drm_device *dev)
9174 {
9175         struct drm_i915_private *dev_priv = dev->dev_private;
9176         struct drm_crtc *crtc;
9177
9178         if (!dev_priv->mm.busy)
9179                 return;
9180
9181         dev_priv->mm.busy = false;
9182
9183         if (!i915.powersave)
9184                 goto out;
9185
9186         for_each_crtc(dev, crtc) {
9187                 if (!crtc->primary->fb)
9188                         continue;
9189
9190                 intel_decrease_pllclock(crtc);
9191         }
9192
9193         if (INTEL_INFO(dev)->gen >= 6)
9194                 gen6_rps_idle(dev->dev_private);
9195
9196 out:
9197         intel_runtime_pm_put(dev_priv);
9198 }
9199
9200 static void intel_crtc_set_state(struct intel_crtc *crtc,
9201                                  struct intel_crtc_state *crtc_state)
9202 {
9203         kfree(crtc->config);
9204         crtc->config = crtc_state;
9205         crtc->base.state = &crtc_state->base;
9206 }
9207
9208 static void intel_crtc_destroy(struct drm_crtc *crtc)
9209 {
9210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9211         struct drm_device *dev = crtc->dev;
9212         struct intel_unpin_work *work;
9213
9214         spin_lock_irq(&dev->event_lock);
9215         work = intel_crtc->unpin_work;
9216         intel_crtc->unpin_work = NULL;
9217         spin_unlock_irq(&dev->event_lock);
9218
9219         if (work) {
9220                 cancel_work_sync(&work->work);
9221                 kfree(work);
9222         }
9223
9224         intel_crtc_set_state(intel_crtc, NULL);
9225         drm_crtc_cleanup(crtc);
9226
9227         kfree(intel_crtc);
9228 }
9229
9230 static void intel_unpin_work_fn(struct work_struct *__work)
9231 {
9232         struct intel_unpin_work *work =
9233                 container_of(__work, struct intel_unpin_work, work);
9234         struct drm_device *dev = work->crtc->dev;
9235         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9236
9237         mutex_lock(&dev->struct_mutex);
9238         intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9239         drm_gem_object_unreference(&work->pending_flip_obj->base);
9240         drm_framebuffer_unreference(work->old_fb);
9241
9242         intel_fbc_update(dev);
9243
9244         if (work->flip_queued_req)
9245                 i915_gem_request_assign(&work->flip_queued_req, NULL);
9246         mutex_unlock(&dev->struct_mutex);
9247
9248         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9249
9250         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9251         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9252
9253         kfree(work);
9254 }
9255
9256 static void do_intel_finish_page_flip(struct drm_device *dev,
9257                                       struct drm_crtc *crtc)
9258 {
9259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9260         struct intel_unpin_work *work;
9261         unsigned long flags;
9262
9263         /* Ignore early vblank irqs */
9264         if (intel_crtc == NULL)
9265                 return;
9266
9267         /*
9268          * This is called both by irq handlers and the reset code (to complete
9269          * lost pageflips) so needs the full irqsave spinlocks.
9270          */
9271         spin_lock_irqsave(&dev->event_lock, flags);
9272         work = intel_crtc->unpin_work;
9273
9274         /* Ensure we don't miss a work->pending update ... */
9275         smp_rmb();
9276
9277         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9278                 spin_unlock_irqrestore(&dev->event_lock, flags);
9279                 return;
9280         }
9281
9282         page_flip_completed(intel_crtc);
9283
9284         spin_unlock_irqrestore(&dev->event_lock, flags);
9285 }
9286
9287 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9288 {
9289         struct drm_i915_private *dev_priv = dev->dev_private;
9290         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9291
9292         do_intel_finish_page_flip(dev, crtc);
9293 }
9294
9295 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9296 {
9297         struct drm_i915_private *dev_priv = dev->dev_private;
9298         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9299
9300         do_intel_finish_page_flip(dev, crtc);
9301 }
9302
9303 /* Is 'a' after or equal to 'b'? */
9304 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9305 {
9306         return !((a - b) & 0x80000000);
9307 }
9308
9309 static bool page_flip_finished(struct intel_crtc *crtc)
9310 {
9311         struct drm_device *dev = crtc->base.dev;
9312         struct drm_i915_private *dev_priv = dev->dev_private;
9313
9314         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9315             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9316                 return true;
9317
9318         /*
9319          * The relevant registers doen't exist on pre-ctg.
9320          * As the flip done interrupt doesn't trigger for mmio
9321          * flips on gmch platforms, a flip count check isn't
9322          * really needed there. But since ctg has the registers,
9323          * include it in the check anyway.
9324          */
9325         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9326                 return true;
9327
9328         /*
9329          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9330          * used the same base address. In that case the mmio flip might
9331          * have completed, but the CS hasn't even executed the flip yet.
9332          *
9333          * A flip count check isn't enough as the CS might have updated
9334          * the base address just after start of vblank, but before we
9335          * managed to process the interrupt. This means we'd complete the
9336          * CS flip too soon.
9337          *
9338          * Combining both checks should get us a good enough result. It may
9339          * still happen that the CS flip has been executed, but has not
9340          * yet actually completed. But in case the base address is the same
9341          * anyway, we don't really care.
9342          */
9343         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9344                 crtc->unpin_work->gtt_offset &&
9345                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9346                                     crtc->unpin_work->flip_count);
9347 }
9348
9349 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9350 {
9351         struct drm_i915_private *dev_priv = dev->dev_private;
9352         struct intel_crtc *intel_crtc =
9353                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9354         unsigned long flags;
9355
9356
9357         /*
9358          * This is called both by irq handlers and the reset code (to complete
9359          * lost pageflips) so needs the full irqsave spinlocks.
9360          *
9361          * NB: An MMIO update of the plane base pointer will also
9362          * generate a page-flip completion irq, i.e. every modeset
9363          * is also accompanied by a spurious intel_prepare_page_flip().
9364          */
9365         spin_lock_irqsave(&dev->event_lock, flags);
9366         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9367                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9368         spin_unlock_irqrestore(&dev->event_lock, flags);
9369 }
9370
9371 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9372 {
9373         /* Ensure that the work item is consistent when activating it ... */
9374         smp_wmb();
9375         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9376         /* and that it is marked active as soon as the irq could fire. */
9377         smp_wmb();
9378 }
9379
9380 static int intel_gen2_queue_flip(struct drm_device *dev,
9381                                  struct drm_crtc *crtc,
9382                                  struct drm_framebuffer *fb,
9383                                  struct drm_i915_gem_object *obj,
9384                                  struct intel_engine_cs *ring,
9385                                  uint32_t flags)
9386 {
9387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9388         u32 flip_mask;
9389         int ret;
9390
9391         ret = intel_ring_begin(ring, 6);
9392         if (ret)
9393                 return ret;
9394
9395         /* Can't queue multiple flips, so wait for the previous
9396          * one to finish before executing the next.
9397          */
9398         if (intel_crtc->plane)
9399                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9400         else
9401                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9402         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9403         intel_ring_emit(ring, MI_NOOP);
9404         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9405                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9406         intel_ring_emit(ring, fb->pitches[0]);
9407         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9408         intel_ring_emit(ring, 0); /* aux display base address, unused */
9409
9410         intel_mark_page_flip_active(intel_crtc);
9411         __intel_ring_advance(ring);
9412         return 0;
9413 }
9414
9415 static int intel_gen3_queue_flip(struct drm_device *dev,
9416                                  struct drm_crtc *crtc,
9417                                  struct drm_framebuffer *fb,
9418                                  struct drm_i915_gem_object *obj,
9419                                  struct intel_engine_cs *ring,
9420                                  uint32_t flags)
9421 {
9422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9423         u32 flip_mask;
9424         int ret;
9425
9426         ret = intel_ring_begin(ring, 6);
9427         if (ret)
9428                 return ret;
9429
9430         if (intel_crtc->plane)
9431                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9432         else
9433                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9434         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9435         intel_ring_emit(ring, MI_NOOP);
9436         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9437                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9438         intel_ring_emit(ring, fb->pitches[0]);
9439         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9440         intel_ring_emit(ring, MI_NOOP);
9441
9442         intel_mark_page_flip_active(intel_crtc);
9443         __intel_ring_advance(ring);
9444         return 0;
9445 }
9446
9447 static int intel_gen4_queue_flip(struct drm_device *dev,
9448                                  struct drm_crtc *crtc,
9449                                  struct drm_framebuffer *fb,
9450                                  struct drm_i915_gem_object *obj,
9451                                  struct intel_engine_cs *ring,
9452                                  uint32_t flags)
9453 {
9454         struct drm_i915_private *dev_priv = dev->dev_private;
9455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9456         uint32_t pf, pipesrc;
9457         int ret;
9458
9459         ret = intel_ring_begin(ring, 4);
9460         if (ret)
9461                 return ret;
9462
9463         /* i965+ uses the linear or tiled offsets from the
9464          * Display Registers (which do not change across a page-flip)
9465          * so we need only reprogram the base address.
9466          */
9467         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9468                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9469         intel_ring_emit(ring, fb->pitches[0]);
9470         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9471                         obj->tiling_mode);
9472
9473         /* XXX Enabling the panel-fitter across page-flip is so far
9474          * untested on non-native modes, so ignore it for now.
9475          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9476          */
9477         pf = 0;
9478         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9479         intel_ring_emit(ring, pf | pipesrc);
9480
9481         intel_mark_page_flip_active(intel_crtc);
9482         __intel_ring_advance(ring);
9483         return 0;
9484 }
9485
9486 static int intel_gen6_queue_flip(struct drm_device *dev,
9487                                  struct drm_crtc *crtc,
9488                                  struct drm_framebuffer *fb,
9489                                  struct drm_i915_gem_object *obj,
9490                                  struct intel_engine_cs *ring,
9491                                  uint32_t flags)
9492 {
9493         struct drm_i915_private *dev_priv = dev->dev_private;
9494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9495         uint32_t pf, pipesrc;
9496         int ret;
9497
9498         ret = intel_ring_begin(ring, 4);
9499         if (ret)
9500                 return ret;
9501
9502         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9503                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9504         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9505         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9506
9507         /* Contrary to the suggestions in the documentation,
9508          * "Enable Panel Fitter" does not seem to be required when page
9509          * flipping with a non-native mode, and worse causes a normal
9510          * modeset to fail.
9511          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9512          */
9513         pf = 0;
9514         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9515         intel_ring_emit(ring, pf | pipesrc);
9516
9517         intel_mark_page_flip_active(intel_crtc);
9518         __intel_ring_advance(ring);
9519         return 0;
9520 }
9521
9522 static int intel_gen7_queue_flip(struct drm_device *dev,
9523                                  struct drm_crtc *crtc,
9524                                  struct drm_framebuffer *fb,
9525                                  struct drm_i915_gem_object *obj,
9526                                  struct intel_engine_cs *ring,
9527                                  uint32_t flags)
9528 {
9529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9530         uint32_t plane_bit = 0;
9531         int len, ret;
9532
9533         switch (intel_crtc->plane) {
9534         case PLANE_A:
9535                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9536                 break;
9537         case PLANE_B:
9538                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9539                 break;
9540         case PLANE_C:
9541                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9542                 break;
9543         default:
9544                 WARN_ONCE(1, "unknown plane in flip command\n");
9545                 return -ENODEV;
9546         }
9547
9548         len = 4;
9549         if (ring->id == RCS) {
9550                 len += 6;
9551                 /*
9552                  * On Gen 8, SRM is now taking an extra dword to accommodate
9553                  * 48bits addresses, and we need a NOOP for the batch size to
9554                  * stay even.
9555                  */
9556                 if (IS_GEN8(dev))
9557                         len += 2;
9558         }
9559
9560         /*
9561          * BSpec MI_DISPLAY_FLIP for IVB:
9562          * "The full packet must be contained within the same cache line."
9563          *
9564          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9565          * cacheline, if we ever start emitting more commands before
9566          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9567          * then do the cacheline alignment, and finally emit the
9568          * MI_DISPLAY_FLIP.
9569          */
9570         ret = intel_ring_cacheline_align(ring);
9571         if (ret)
9572                 return ret;
9573
9574         ret = intel_ring_begin(ring, len);
9575         if (ret)
9576                 return ret;
9577
9578         /* Unmask the flip-done completion message. Note that the bspec says that
9579          * we should do this for both the BCS and RCS, and that we must not unmask
9580          * more than one flip event at any time (or ensure that one flip message
9581          * can be sent by waiting for flip-done prior to queueing new flips).
9582          * Experimentation says that BCS works despite DERRMR masking all
9583          * flip-done completion events and that unmasking all planes at once
9584          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9585          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9586          */
9587         if (ring->id == RCS) {
9588                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9589                 intel_ring_emit(ring, DERRMR);
9590                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9591                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9592                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9593                 if (IS_GEN8(dev))
9594                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9595                                               MI_SRM_LRM_GLOBAL_GTT);
9596                 else
9597                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9598                                               MI_SRM_LRM_GLOBAL_GTT);
9599                 intel_ring_emit(ring, DERRMR);
9600                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9601                 if (IS_GEN8(dev)) {
9602                         intel_ring_emit(ring, 0);
9603                         intel_ring_emit(ring, MI_NOOP);
9604                 }
9605         }
9606
9607         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9608         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9609         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9610         intel_ring_emit(ring, (MI_NOOP));
9611
9612         intel_mark_page_flip_active(intel_crtc);
9613         __intel_ring_advance(ring);
9614         return 0;
9615 }
9616
9617 static bool use_mmio_flip(struct intel_engine_cs *ring,
9618                           struct drm_i915_gem_object *obj)
9619 {
9620         /*
9621          * This is not being used for older platforms, because
9622          * non-availability of flip done interrupt forces us to use
9623          * CS flips. Older platforms derive flip done using some clever
9624          * tricks involving the flip_pending status bits and vblank irqs.
9625          * So using MMIO flips there would disrupt this mechanism.
9626          */
9627
9628         if (ring == NULL)
9629                 return true;
9630
9631         if (INTEL_INFO(ring->dev)->gen < 5)
9632                 return false;
9633
9634         if (i915.use_mmio_flip < 0)
9635                 return false;
9636         else if (i915.use_mmio_flip > 0)
9637                 return true;
9638         else if (i915.enable_execlists)
9639                 return true;
9640         else
9641                 return ring != i915_gem_request_get_ring(obj->last_read_req);
9642 }
9643
9644 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9645 {
9646         struct drm_device *dev = intel_crtc->base.dev;
9647         struct drm_i915_private *dev_priv = dev->dev_private;
9648         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9649         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9650         struct drm_i915_gem_object *obj = intel_fb->obj;
9651         const enum pipe pipe = intel_crtc->pipe;
9652         u32 ctl, stride;
9653
9654         ctl = I915_READ(PLANE_CTL(pipe, 0));
9655         ctl &= ~PLANE_CTL_TILED_MASK;
9656         if (obj->tiling_mode == I915_TILING_X)
9657                 ctl |= PLANE_CTL_TILED_X;
9658
9659         /*
9660          * The stride is either expressed as a multiple of 64 bytes chunks for
9661          * linear buffers or in number of tiles for tiled buffers.
9662          */
9663         stride = fb->pitches[0] >> 6;
9664         if (obj->tiling_mode == I915_TILING_X)
9665                 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9666
9667         /*
9668          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9669          * PLANE_SURF updates, the update is then guaranteed to be atomic.
9670          */
9671         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9672         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9673
9674         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9675         POSTING_READ(PLANE_SURF(pipe, 0));
9676 }
9677
9678 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9679 {
9680         struct drm_device *dev = intel_crtc->base.dev;
9681         struct drm_i915_private *dev_priv = dev->dev_private;
9682         struct intel_framebuffer *intel_fb =
9683                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9684         struct drm_i915_gem_object *obj = intel_fb->obj;
9685         u32 dspcntr;
9686         u32 reg;
9687
9688         reg = DSPCNTR(intel_crtc->plane);
9689         dspcntr = I915_READ(reg);
9690
9691         if (obj->tiling_mode != I915_TILING_NONE)
9692                 dspcntr |= DISPPLANE_TILED;
9693         else
9694                 dspcntr &= ~DISPPLANE_TILED;
9695
9696         I915_WRITE(reg, dspcntr);
9697
9698         I915_WRITE(DSPSURF(intel_crtc->plane),
9699                    intel_crtc->unpin_work->gtt_offset);
9700         POSTING_READ(DSPSURF(intel_crtc->plane));
9701
9702 }
9703
9704 /*
9705  * XXX: This is the temporary way to update the plane registers until we get
9706  * around to using the usual plane update functions for MMIO flips
9707  */
9708 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9709 {
9710         struct drm_device *dev = intel_crtc->base.dev;
9711         bool atomic_update;
9712         u32 start_vbl_count;
9713
9714         intel_mark_page_flip_active(intel_crtc);
9715
9716         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9717
9718         if (INTEL_INFO(dev)->gen >= 9)
9719                 skl_do_mmio_flip(intel_crtc);
9720         else
9721                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9722                 ilk_do_mmio_flip(intel_crtc);
9723
9724         if (atomic_update)
9725                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9726 }
9727
9728 static void intel_mmio_flip_work_func(struct work_struct *work)
9729 {
9730         struct intel_crtc *crtc =
9731                 container_of(work, struct intel_crtc, mmio_flip.work);
9732         struct intel_mmio_flip *mmio_flip;
9733
9734         mmio_flip = &crtc->mmio_flip;
9735         if (mmio_flip->req)
9736                 WARN_ON(__i915_wait_request(mmio_flip->req,
9737                                             crtc->reset_counter,
9738                                             false, NULL, NULL) != 0);
9739
9740         intel_do_mmio_flip(crtc);
9741         if (mmio_flip->req) {
9742                 mutex_lock(&crtc->base.dev->struct_mutex);
9743                 i915_gem_request_assign(&mmio_flip->req, NULL);
9744                 mutex_unlock(&crtc->base.dev->struct_mutex);
9745         }
9746 }
9747
9748 static int intel_queue_mmio_flip(struct drm_device *dev,
9749                                  struct drm_crtc *crtc,
9750                                  struct drm_framebuffer *fb,
9751                                  struct drm_i915_gem_object *obj,
9752                                  struct intel_engine_cs *ring,
9753                                  uint32_t flags)
9754 {
9755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9756
9757         i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9758                                 obj->last_write_req);
9759
9760         schedule_work(&intel_crtc->mmio_flip.work);
9761
9762         return 0;
9763 }
9764
9765 static int intel_default_queue_flip(struct drm_device *dev,
9766                                     struct drm_crtc *crtc,
9767                                     struct drm_framebuffer *fb,
9768                                     struct drm_i915_gem_object *obj,
9769                                     struct intel_engine_cs *ring,
9770                                     uint32_t flags)
9771 {
9772         return -ENODEV;
9773 }
9774
9775 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9776                                          struct drm_crtc *crtc)
9777 {
9778         struct drm_i915_private *dev_priv = dev->dev_private;
9779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9780         struct intel_unpin_work *work = intel_crtc->unpin_work;
9781         u32 addr;
9782
9783         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9784                 return true;
9785
9786         if (!work->enable_stall_check)
9787                 return false;
9788
9789         if (work->flip_ready_vblank == 0) {
9790                 if (work->flip_queued_req &&
9791                     !i915_gem_request_completed(work->flip_queued_req, true))
9792                         return false;
9793
9794                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9795         }
9796
9797         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9798                 return false;
9799
9800         /* Potential stall - if we see that the flip has happened,
9801          * assume a missed interrupt. */
9802         if (INTEL_INFO(dev)->gen >= 4)
9803                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9804         else
9805                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9806
9807         /* There is a potential issue here with a false positive after a flip
9808          * to the same address. We could address this by checking for a
9809          * non-incrementing frame counter.
9810          */
9811         return addr == work->gtt_offset;
9812 }
9813
9814 void intel_check_page_flip(struct drm_device *dev, int pipe)
9815 {
9816         struct drm_i915_private *dev_priv = dev->dev_private;
9817         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9819
9820         WARN_ON(!in_irq());
9821
9822         if (crtc == NULL)
9823                 return;
9824
9825         spin_lock(&dev->event_lock);
9826         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9827                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9828                          intel_crtc->unpin_work->flip_queued_vblank,
9829                          drm_vblank_count(dev, pipe));
9830                 page_flip_completed(intel_crtc);
9831         }
9832         spin_unlock(&dev->event_lock);
9833 }
9834
9835 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9836                                 struct drm_framebuffer *fb,
9837                                 struct drm_pending_vblank_event *event,
9838                                 uint32_t page_flip_flags)
9839 {
9840         struct drm_device *dev = crtc->dev;
9841         struct drm_i915_private *dev_priv = dev->dev_private;
9842         struct drm_framebuffer *old_fb = crtc->primary->fb;
9843         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9845         struct drm_plane *primary = crtc->primary;
9846         enum pipe pipe = intel_crtc->pipe;
9847         struct intel_unpin_work *work;
9848         struct intel_engine_cs *ring;
9849         int ret;
9850
9851         /*
9852          * drm_mode_page_flip_ioctl() should already catch this, but double
9853          * check to be safe.  In the future we may enable pageflipping from
9854          * a disabled primary plane.
9855          */
9856         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9857                 return -EBUSY;
9858
9859         /* Can't change pixel format via MI display flips. */
9860         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9861                 return -EINVAL;
9862
9863         /*
9864          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9865          * Note that pitch changes could also affect these register.
9866          */
9867         if (INTEL_INFO(dev)->gen > 3 &&
9868             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9869              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9870                 return -EINVAL;
9871
9872         if (i915_terminally_wedged(&dev_priv->gpu_error))
9873                 goto out_hang;
9874
9875         work = kzalloc(sizeof(*work), GFP_KERNEL);
9876         if (work == NULL)
9877                 return -ENOMEM;
9878
9879         work->event = event;
9880         work->crtc = crtc;
9881         work->old_fb = old_fb;
9882         INIT_WORK(&work->work, intel_unpin_work_fn);
9883
9884         ret = drm_crtc_vblank_get(crtc);
9885         if (ret)
9886                 goto free_work;
9887
9888         /* We borrow the event spin lock for protecting unpin_work */
9889         spin_lock_irq(&dev->event_lock);
9890         if (intel_crtc->unpin_work) {
9891                 /* Before declaring the flip queue wedged, check if
9892                  * the hardware completed the operation behind our backs.
9893                  */
9894                 if (__intel_pageflip_stall_check(dev, crtc)) {
9895                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9896                         page_flip_completed(intel_crtc);
9897                 } else {
9898                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9899                         spin_unlock_irq(&dev->event_lock);
9900
9901                         drm_crtc_vblank_put(crtc);
9902                         kfree(work);
9903                         return -EBUSY;
9904                 }
9905         }
9906         intel_crtc->unpin_work = work;
9907         spin_unlock_irq(&dev->event_lock);
9908
9909         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9910                 flush_workqueue(dev_priv->wq);
9911
9912         ret = i915_mutex_lock_interruptible(dev);
9913         if (ret)
9914                 goto cleanup;
9915
9916         /* Reference the objects for the scheduled work. */
9917         drm_framebuffer_reference(work->old_fb);
9918         drm_gem_object_reference(&obj->base);
9919
9920         crtc->primary->fb = fb;
9921         update_state_fb(crtc->primary);
9922
9923         work->pending_flip_obj = obj;
9924
9925         atomic_inc(&intel_crtc->unpin_work_count);
9926         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9927
9928         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9929                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9930
9931         if (IS_VALLEYVIEW(dev)) {
9932                 ring = &dev_priv->ring[BCS];
9933                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9934                         /* vlv: DISPLAY_FLIP fails to change tiling */
9935                         ring = NULL;
9936         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9937                 ring = &dev_priv->ring[BCS];
9938         } else if (INTEL_INFO(dev)->gen >= 7) {
9939                 ring = i915_gem_request_get_ring(obj->last_read_req);
9940                 if (ring == NULL || ring->id != RCS)
9941                         ring = &dev_priv->ring[BCS];
9942         } else {
9943                 ring = &dev_priv->ring[RCS];
9944         }
9945
9946         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9947         if (ret)
9948                 goto cleanup_pending;
9949
9950         work->gtt_offset =
9951                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9952
9953         if (use_mmio_flip(ring, obj)) {
9954                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9955                                             page_flip_flags);
9956                 if (ret)
9957                         goto cleanup_unpin;
9958
9959                 i915_gem_request_assign(&work->flip_queued_req,
9960                                         obj->last_write_req);
9961         } else {
9962                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9963                                                    page_flip_flags);
9964                 if (ret)
9965                         goto cleanup_unpin;
9966
9967                 i915_gem_request_assign(&work->flip_queued_req,
9968                                         intel_ring_get_request(ring));
9969         }
9970
9971         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
9972         work->enable_stall_check = true;
9973
9974         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9975                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9976
9977         intel_fbc_disable(dev);
9978         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9979         mutex_unlock(&dev->struct_mutex);
9980
9981         trace_i915_flip_request(intel_crtc->plane, obj);
9982
9983         return 0;
9984
9985 cleanup_unpin:
9986         intel_unpin_fb_obj(obj);
9987 cleanup_pending:
9988         atomic_dec(&intel_crtc->unpin_work_count);
9989         crtc->primary->fb = old_fb;
9990         update_state_fb(crtc->primary);
9991         drm_framebuffer_unreference(work->old_fb);
9992         drm_gem_object_unreference(&obj->base);
9993         mutex_unlock(&dev->struct_mutex);
9994
9995 cleanup:
9996         spin_lock_irq(&dev->event_lock);
9997         intel_crtc->unpin_work = NULL;
9998         spin_unlock_irq(&dev->event_lock);
9999
10000         drm_crtc_vblank_put(crtc);
10001 free_work:
10002         kfree(work);
10003
10004         if (ret == -EIO) {
10005 out_hang:
10006                 ret = intel_plane_restore(primary);
10007                 if (ret == 0 && event) {
10008                         spin_lock_irq(&dev->event_lock);
10009                         drm_send_vblank_event(dev, pipe, event);
10010                         spin_unlock_irq(&dev->event_lock);
10011                 }
10012         }
10013         return ret;
10014 }
10015
10016 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10017         .mode_set_base_atomic = intel_pipe_set_base_atomic,
10018         .load_lut = intel_crtc_load_lut,
10019         .atomic_begin = intel_begin_crtc_commit,
10020         .atomic_flush = intel_finish_crtc_commit,
10021 };
10022
10023 /**
10024  * intel_modeset_update_staged_output_state
10025  *
10026  * Updates the staged output configuration state, e.g. after we've read out the
10027  * current hw state.
10028  */
10029 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10030 {
10031         struct intel_crtc *crtc;
10032         struct intel_encoder *encoder;
10033         struct intel_connector *connector;
10034
10035         for_each_intel_connector(dev, connector) {
10036                 connector->new_encoder =
10037                         to_intel_encoder(connector->base.encoder);
10038         }
10039
10040         for_each_intel_encoder(dev, encoder) {
10041                 encoder->new_crtc =
10042                         to_intel_crtc(encoder->base.crtc);
10043         }
10044
10045         for_each_intel_crtc(dev, crtc) {
10046                 crtc->new_enabled = crtc->base.state->enable;
10047
10048                 if (crtc->new_enabled)
10049                         crtc->new_config = crtc->config;
10050                 else
10051                         crtc->new_config = NULL;
10052         }
10053 }
10054
10055 /**
10056  * intel_modeset_commit_output_state
10057  *
10058  * This function copies the stage display pipe configuration to the real one.
10059  */
10060 static void intel_modeset_commit_output_state(struct drm_device *dev)
10061 {
10062         struct intel_crtc *crtc;
10063         struct intel_encoder *encoder;
10064         struct intel_connector *connector;
10065
10066         for_each_intel_connector(dev, connector) {
10067                 connector->base.encoder = &connector->new_encoder->base;
10068         }
10069
10070         for_each_intel_encoder(dev, encoder) {
10071                 encoder->base.crtc = &encoder->new_crtc->base;
10072         }
10073
10074         for_each_intel_crtc(dev, crtc) {
10075                 crtc->base.state->enable = crtc->new_enabled;
10076                 crtc->base.enabled = crtc->new_enabled;
10077         }
10078 }
10079
10080 static void
10081 connected_sink_compute_bpp(struct intel_connector *connector,
10082                            struct intel_crtc_state *pipe_config)
10083 {
10084         int bpp = pipe_config->pipe_bpp;
10085
10086         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10087                 connector->base.base.id,
10088                 connector->base.name);
10089
10090         /* Don't use an invalid EDID bpc value */
10091         if (connector->base.display_info.bpc &&
10092             connector->base.display_info.bpc * 3 < bpp) {
10093                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10094                               bpp, connector->base.display_info.bpc*3);
10095                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10096         }
10097
10098         /* Clamp bpp to 8 on screens without EDID 1.4 */
10099         if (connector->base.display_info.bpc == 0 && bpp > 24) {
10100                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10101                               bpp);
10102                 pipe_config->pipe_bpp = 24;
10103         }
10104 }
10105
10106 static int
10107 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10108                           struct drm_framebuffer *fb,
10109                           struct intel_crtc_state *pipe_config)
10110 {
10111         struct drm_device *dev = crtc->base.dev;
10112         struct intel_connector *connector;
10113         int bpp;
10114
10115         switch (fb->pixel_format) {
10116         case DRM_FORMAT_C8:
10117                 bpp = 8*3; /* since we go through a colormap */
10118                 break;
10119         case DRM_FORMAT_XRGB1555:
10120         case DRM_FORMAT_ARGB1555:
10121                 /* checked in intel_framebuffer_init already */
10122                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10123                         return -EINVAL;
10124         case DRM_FORMAT_RGB565:
10125                 bpp = 6*3; /* min is 18bpp */
10126                 break;
10127         case DRM_FORMAT_XBGR8888:
10128         case DRM_FORMAT_ABGR8888:
10129                 /* checked in intel_framebuffer_init already */
10130                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10131                         return -EINVAL;
10132         case DRM_FORMAT_XRGB8888:
10133         case DRM_FORMAT_ARGB8888:
10134                 bpp = 8*3;
10135                 break;
10136         case DRM_FORMAT_XRGB2101010:
10137         case DRM_FORMAT_ARGB2101010:
10138         case DRM_FORMAT_XBGR2101010:
10139         case DRM_FORMAT_ABGR2101010:
10140                 /* checked in intel_framebuffer_init already */
10141                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10142                         return -EINVAL;
10143                 bpp = 10*3;
10144                 break;
10145         /* TODO: gen4+ supports 16 bpc floating point, too. */
10146         default:
10147                 DRM_DEBUG_KMS("unsupported depth\n");
10148                 return -EINVAL;
10149         }
10150
10151         pipe_config->pipe_bpp = bpp;
10152
10153         /* Clamp display bpp to EDID value */
10154         for_each_intel_connector(dev, connector) {
10155                 if (!connector->new_encoder ||
10156                     connector->new_encoder->new_crtc != crtc)
10157                         continue;
10158
10159                 connected_sink_compute_bpp(connector, pipe_config);
10160         }
10161
10162         return bpp;
10163 }
10164
10165 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10166 {
10167         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10168                         "type: 0x%x flags: 0x%x\n",
10169                 mode->crtc_clock,
10170                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10171                 mode->crtc_hsync_end, mode->crtc_htotal,
10172                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10173                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10174 }
10175
10176 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10177                                    struct intel_crtc_state *pipe_config,
10178                                    const char *context)
10179 {
10180         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10181                       context, pipe_name(crtc->pipe));
10182
10183         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10184         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10185                       pipe_config->pipe_bpp, pipe_config->dither);
10186         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10187                       pipe_config->has_pch_encoder,
10188                       pipe_config->fdi_lanes,
10189                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10190                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10191                       pipe_config->fdi_m_n.tu);
10192         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10193                       pipe_config->has_dp_encoder,
10194                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10195                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10196                       pipe_config->dp_m_n.tu);
10197
10198         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10199                       pipe_config->has_dp_encoder,
10200                       pipe_config->dp_m2_n2.gmch_m,
10201                       pipe_config->dp_m2_n2.gmch_n,
10202                       pipe_config->dp_m2_n2.link_m,
10203                       pipe_config->dp_m2_n2.link_n,
10204                       pipe_config->dp_m2_n2.tu);
10205
10206         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10207                       pipe_config->has_audio,
10208                       pipe_config->has_infoframe);
10209
10210         DRM_DEBUG_KMS("requested mode:\n");
10211         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10212         DRM_DEBUG_KMS("adjusted mode:\n");
10213         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10214         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10215         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10216         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10217                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10218         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10219                       pipe_config->gmch_pfit.control,
10220                       pipe_config->gmch_pfit.pgm_ratios,
10221                       pipe_config->gmch_pfit.lvds_border_bits);
10222         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10223                       pipe_config->pch_pfit.pos,
10224                       pipe_config->pch_pfit.size,
10225                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10226         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10227         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10228 }
10229
10230 static bool encoders_cloneable(const struct intel_encoder *a,
10231                                const struct intel_encoder *b)
10232 {
10233         /* masks could be asymmetric, so check both ways */
10234         return a == b || (a->cloneable & (1 << b->type) &&
10235                           b->cloneable & (1 << a->type));
10236 }
10237
10238 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10239                                          struct intel_encoder *encoder)
10240 {
10241         struct drm_device *dev = crtc->base.dev;
10242         struct intel_encoder *source_encoder;
10243
10244         for_each_intel_encoder(dev, source_encoder) {
10245                 if (source_encoder->new_crtc != crtc)
10246                         continue;
10247
10248                 if (!encoders_cloneable(encoder, source_encoder))
10249                         return false;
10250         }
10251
10252         return true;
10253 }
10254
10255 static bool check_encoder_cloning(struct intel_crtc *crtc)
10256 {
10257         struct drm_device *dev = crtc->base.dev;
10258         struct intel_encoder *encoder;
10259
10260         for_each_intel_encoder(dev, encoder) {
10261                 if (encoder->new_crtc != crtc)
10262                         continue;
10263
10264                 if (!check_single_encoder_cloning(crtc, encoder))
10265                         return false;
10266         }
10267
10268         return true;
10269 }
10270
10271 static bool check_digital_port_conflicts(struct drm_device *dev)
10272 {
10273         struct intel_connector *connector;
10274         unsigned int used_ports = 0;
10275
10276         /*
10277          * Walk the connector list instead of the encoder
10278          * list to detect the problem on ddi platforms
10279          * where there's just one encoder per digital port.
10280          */
10281         for_each_intel_connector(dev, connector) {
10282                 struct intel_encoder *encoder = connector->new_encoder;
10283
10284                 if (!encoder)
10285                         continue;
10286
10287                 WARN_ON(!encoder->new_crtc);
10288
10289                 switch (encoder->type) {
10290                         unsigned int port_mask;
10291                 case INTEL_OUTPUT_UNKNOWN:
10292                         if (WARN_ON(!HAS_DDI(dev)))
10293                                 break;
10294                 case INTEL_OUTPUT_DISPLAYPORT:
10295                 case INTEL_OUTPUT_HDMI:
10296                 case INTEL_OUTPUT_EDP:
10297                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10298
10299                         /* the same port mustn't appear more than once */
10300                         if (used_ports & port_mask)
10301                                 return false;
10302
10303                         used_ports |= port_mask;
10304                 default:
10305                         break;
10306                 }
10307         }
10308
10309         return true;
10310 }
10311
10312 static struct intel_crtc_state *
10313 intel_modeset_pipe_config(struct drm_crtc *crtc,
10314                           struct drm_framebuffer *fb,
10315                           struct drm_display_mode *mode)
10316 {
10317         struct drm_device *dev = crtc->dev;
10318         struct intel_encoder *encoder;
10319         struct intel_crtc_state *pipe_config;
10320         int plane_bpp, ret = -EINVAL;
10321         bool retry = true;
10322
10323         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10324                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10325                 return ERR_PTR(-EINVAL);
10326         }
10327
10328         if (!check_digital_port_conflicts(dev)) {
10329                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10330                 return ERR_PTR(-EINVAL);
10331         }
10332
10333         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10334         if (!pipe_config)
10335                 return ERR_PTR(-ENOMEM);
10336
10337         pipe_config->base.crtc = crtc;
10338         drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10339         drm_mode_copy(&pipe_config->base.mode, mode);
10340
10341         pipe_config->cpu_transcoder =
10342                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10343         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10344
10345         /*
10346          * Sanitize sync polarity flags based on requested ones. If neither
10347          * positive or negative polarity is requested, treat this as meaning
10348          * negative polarity.
10349          */
10350         if (!(pipe_config->base.adjusted_mode.flags &
10351               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10352                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10353
10354         if (!(pipe_config->base.adjusted_mode.flags &
10355               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10356                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10357
10358         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10359          * plane pixel format and any sink constraints into account. Returns the
10360          * source plane bpp so that dithering can be selected on mismatches
10361          * after encoders and crtc also have had their say. */
10362         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10363                                               fb, pipe_config);
10364         if (plane_bpp < 0)
10365                 goto fail;
10366
10367         /*
10368          * Determine the real pipe dimensions. Note that stereo modes can
10369          * increase the actual pipe size due to the frame doubling and
10370          * insertion of additional space for blanks between the frame. This
10371          * is stored in the crtc timings. We use the requested mode to do this
10372          * computation to clearly distinguish it from the adjusted mode, which
10373          * can be changed by the connectors in the below retry loop.
10374          */
10375         drm_crtc_get_hv_timing(&pipe_config->base.mode,
10376                                &pipe_config->pipe_src_w,
10377                                &pipe_config->pipe_src_h);
10378
10379 encoder_retry:
10380         /* Ensure the port clock defaults are reset when retrying. */
10381         pipe_config->port_clock = 0;
10382         pipe_config->pixel_multiplier = 1;
10383
10384         /* Fill in default crtc timings, allow encoders to overwrite them. */
10385         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10386                               CRTC_STEREO_DOUBLE);
10387
10388         /* Pass our mode to the connectors and the CRTC to give them a chance to
10389          * adjust it according to limitations or connector properties, and also
10390          * a chance to reject the mode entirely.
10391          */
10392         for_each_intel_encoder(dev, encoder) {
10393
10394                 if (&encoder->new_crtc->base != crtc)
10395                         continue;
10396
10397                 if (!(encoder->compute_config(encoder, pipe_config))) {
10398                         DRM_DEBUG_KMS("Encoder config failure\n");
10399                         goto fail;
10400                 }
10401         }
10402
10403         /* Set default port clock if not overwritten by the encoder. Needs to be
10404          * done afterwards in case the encoder adjusts the mode. */
10405         if (!pipe_config->port_clock)
10406                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10407                         * pipe_config->pixel_multiplier;
10408
10409         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10410         if (ret < 0) {
10411                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10412                 goto fail;
10413         }
10414
10415         if (ret == RETRY) {
10416                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10417                         ret = -EINVAL;
10418                         goto fail;
10419                 }
10420
10421                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10422                 retry = false;
10423                 goto encoder_retry;
10424         }
10425
10426         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10427         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10428                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10429
10430         return pipe_config;
10431 fail:
10432         kfree(pipe_config);
10433         return ERR_PTR(ret);
10434 }
10435
10436 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10437  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10438 static void
10439 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10440                              unsigned *prepare_pipes, unsigned *disable_pipes)
10441 {
10442         struct intel_crtc *intel_crtc;
10443         struct drm_device *dev = crtc->dev;
10444         struct intel_encoder *encoder;
10445         struct intel_connector *connector;
10446         struct drm_crtc *tmp_crtc;
10447
10448         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10449
10450         /* Check which crtcs have changed outputs connected to them, these need
10451          * to be part of the prepare_pipes mask. We don't (yet) support global
10452          * modeset across multiple crtcs, so modeset_pipes will only have one
10453          * bit set at most. */
10454         for_each_intel_connector(dev, connector) {
10455                 if (connector->base.encoder == &connector->new_encoder->base)
10456                         continue;
10457
10458                 if (connector->base.encoder) {
10459                         tmp_crtc = connector->base.encoder->crtc;
10460
10461                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10462                 }
10463
10464                 if (connector->new_encoder)
10465                         *prepare_pipes |=
10466                                 1 << connector->new_encoder->new_crtc->pipe;
10467         }
10468
10469         for_each_intel_encoder(dev, encoder) {
10470                 if (encoder->base.crtc == &encoder->new_crtc->base)
10471                         continue;
10472
10473                 if (encoder->base.crtc) {
10474                         tmp_crtc = encoder->base.crtc;
10475
10476                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10477                 }
10478
10479                 if (encoder->new_crtc)
10480                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10481         }
10482
10483         /* Check for pipes that will be enabled/disabled ... */
10484         for_each_intel_crtc(dev, intel_crtc) {
10485                 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10486                         continue;
10487
10488                 if (!intel_crtc->new_enabled)
10489                         *disable_pipes |= 1 << intel_crtc->pipe;
10490                 else
10491                         *prepare_pipes |= 1 << intel_crtc->pipe;
10492         }
10493
10494
10495         /* set_mode is also used to update properties on life display pipes. */
10496         intel_crtc = to_intel_crtc(crtc);
10497         if (intel_crtc->new_enabled)
10498                 *prepare_pipes |= 1 << intel_crtc->pipe;
10499
10500         /*
10501          * For simplicity do a full modeset on any pipe where the output routing
10502          * changed. We could be more clever, but that would require us to be
10503          * more careful with calling the relevant encoder->mode_set functions.
10504          */
10505         if (*prepare_pipes)
10506                 *modeset_pipes = *prepare_pipes;
10507
10508         /* ... and mask these out. */
10509         *modeset_pipes &= ~(*disable_pipes);
10510         *prepare_pipes &= ~(*disable_pipes);
10511
10512         /*
10513          * HACK: We don't (yet) fully support global modesets. intel_set_config
10514          * obies this rule, but the modeset restore mode of
10515          * intel_modeset_setup_hw_state does not.
10516          */
10517         *modeset_pipes &= 1 << intel_crtc->pipe;
10518         *prepare_pipes &= 1 << intel_crtc->pipe;
10519
10520         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10521                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10522 }
10523
10524 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10525 {
10526         struct drm_encoder *encoder;
10527         struct drm_device *dev = crtc->dev;
10528
10529         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10530                 if (encoder->crtc == crtc)
10531                         return true;
10532
10533         return false;
10534 }
10535
10536 static void
10537 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10538 {
10539         struct drm_i915_private *dev_priv = dev->dev_private;
10540         struct intel_encoder *intel_encoder;
10541         struct intel_crtc *intel_crtc;
10542         struct drm_connector *connector;
10543
10544         intel_shared_dpll_commit(dev_priv);
10545
10546         for_each_intel_encoder(dev, intel_encoder) {
10547                 if (!intel_encoder->base.crtc)
10548                         continue;
10549
10550                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10551
10552                 if (prepare_pipes & (1 << intel_crtc->pipe))
10553                         intel_encoder->connectors_active = false;
10554         }
10555
10556         intel_modeset_commit_output_state(dev);
10557
10558         /* Double check state. */
10559         for_each_intel_crtc(dev, intel_crtc) {
10560                 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10561                 WARN_ON(intel_crtc->new_config &&
10562                         intel_crtc->new_config != intel_crtc->config);
10563                 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10564         }
10565
10566         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10567                 if (!connector->encoder || !connector->encoder->crtc)
10568                         continue;
10569
10570                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10571
10572                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10573                         struct drm_property *dpms_property =
10574                                 dev->mode_config.dpms_property;
10575
10576                         connector->dpms = DRM_MODE_DPMS_ON;
10577                         drm_object_property_set_value(&connector->base,
10578                                                          dpms_property,
10579                                                          DRM_MODE_DPMS_ON);
10580
10581                         intel_encoder = to_intel_encoder(connector->encoder);
10582                         intel_encoder->connectors_active = true;
10583                 }
10584         }
10585
10586 }
10587
10588 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10589 {
10590         int diff;
10591
10592         if (clock1 == clock2)
10593                 return true;
10594
10595         if (!clock1 || !clock2)
10596                 return false;
10597
10598         diff = abs(clock1 - clock2);
10599
10600         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10601                 return true;
10602
10603         return false;
10604 }
10605
10606 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10607         list_for_each_entry((intel_crtc), \
10608                             &(dev)->mode_config.crtc_list, \
10609                             base.head) \
10610                 if (mask & (1 <<(intel_crtc)->pipe))
10611
10612 static bool
10613 intel_pipe_config_compare(struct drm_device *dev,
10614                           struct intel_crtc_state *current_config,
10615                           struct intel_crtc_state *pipe_config)
10616 {
10617 #define PIPE_CONF_CHECK_X(name) \
10618         if (current_config->name != pipe_config->name) { \
10619                 DRM_ERROR("mismatch in " #name " " \
10620                           "(expected 0x%08x, found 0x%08x)\n", \
10621                           current_config->name, \
10622                           pipe_config->name); \
10623                 return false; \
10624         }
10625
10626 #define PIPE_CONF_CHECK_I(name) \
10627         if (current_config->name != pipe_config->name) { \
10628                 DRM_ERROR("mismatch in " #name " " \
10629                           "(expected %i, found %i)\n", \
10630                           current_config->name, \
10631                           pipe_config->name); \
10632                 return false; \
10633         }
10634
10635 /* This is required for BDW+ where there is only one set of registers for
10636  * switching between high and low RR.
10637  * This macro can be used whenever a comparison has to be made between one
10638  * hw state and multiple sw state variables.
10639  */
10640 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10641         if ((current_config->name != pipe_config->name) && \
10642                 (current_config->alt_name != pipe_config->name)) { \
10643                         DRM_ERROR("mismatch in " #name " " \
10644                                   "(expected %i or %i, found %i)\n", \
10645                                   current_config->name, \
10646                                   current_config->alt_name, \
10647                                   pipe_config->name); \
10648                         return false; \
10649         }
10650
10651 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10652         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10653                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10654                           "(expected %i, found %i)\n", \
10655                           current_config->name & (mask), \
10656                           pipe_config->name & (mask)); \
10657                 return false; \
10658         }
10659
10660 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10661         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10662                 DRM_ERROR("mismatch in " #name " " \
10663                           "(expected %i, found %i)\n", \
10664                           current_config->name, \
10665                           pipe_config->name); \
10666                 return false; \
10667         }
10668
10669 #define PIPE_CONF_QUIRK(quirk)  \
10670         ((current_config->quirks | pipe_config->quirks) & (quirk))
10671
10672         PIPE_CONF_CHECK_I(cpu_transcoder);
10673
10674         PIPE_CONF_CHECK_I(has_pch_encoder);
10675         PIPE_CONF_CHECK_I(fdi_lanes);
10676         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10677         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10678         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10679         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10680         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10681
10682         PIPE_CONF_CHECK_I(has_dp_encoder);
10683
10684         if (INTEL_INFO(dev)->gen < 8) {
10685                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10686                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10687                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10688                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10689                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10690
10691                 if (current_config->has_drrs) {
10692                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10693                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10694                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10695                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10696                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10697                 }
10698         } else {
10699                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10700                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10701                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10702                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10703                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10704         }
10705
10706         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10707         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10708         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10709         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10710         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10711         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10712
10713         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10714         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10715         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10716         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10717         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10718         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10719
10720         PIPE_CONF_CHECK_I(pixel_multiplier);
10721         PIPE_CONF_CHECK_I(has_hdmi_sink);
10722         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10723             IS_VALLEYVIEW(dev))
10724                 PIPE_CONF_CHECK_I(limited_color_range);
10725         PIPE_CONF_CHECK_I(has_infoframe);
10726
10727         PIPE_CONF_CHECK_I(has_audio);
10728
10729         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10730                               DRM_MODE_FLAG_INTERLACE);
10731
10732         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10733                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10734                                       DRM_MODE_FLAG_PHSYNC);
10735                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10736                                       DRM_MODE_FLAG_NHSYNC);
10737                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10738                                       DRM_MODE_FLAG_PVSYNC);
10739                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10740                                       DRM_MODE_FLAG_NVSYNC);
10741         }
10742
10743         PIPE_CONF_CHECK_I(pipe_src_w);
10744         PIPE_CONF_CHECK_I(pipe_src_h);
10745
10746         /*
10747          * FIXME: BIOS likes to set up a cloned config with lvds+external
10748          * screen. Since we don't yet re-compute the pipe config when moving
10749          * just the lvds port away to another pipe the sw tracking won't match.
10750          *
10751          * Proper atomic modesets with recomputed global state will fix this.
10752          * Until then just don't check gmch state for inherited modes.
10753          */
10754         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10755                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10756                 /* pfit ratios are autocomputed by the hw on gen4+ */
10757                 if (INTEL_INFO(dev)->gen < 4)
10758                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10759                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10760         }
10761
10762         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10763         if (current_config->pch_pfit.enabled) {
10764                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10765                 PIPE_CONF_CHECK_I(pch_pfit.size);
10766         }
10767
10768         /* BDW+ don't expose a synchronous way to read the state */
10769         if (IS_HASWELL(dev))
10770                 PIPE_CONF_CHECK_I(ips_enabled);
10771
10772         PIPE_CONF_CHECK_I(double_wide);
10773
10774         PIPE_CONF_CHECK_X(ddi_pll_sel);
10775
10776         PIPE_CONF_CHECK_I(shared_dpll);
10777         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10778         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10779         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10780         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10781         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10782         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10783         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10784         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10785
10786         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10787                 PIPE_CONF_CHECK_I(pipe_bpp);
10788
10789         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10790         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10791
10792 #undef PIPE_CONF_CHECK_X
10793 #undef PIPE_CONF_CHECK_I
10794 #undef PIPE_CONF_CHECK_I_ALT
10795 #undef PIPE_CONF_CHECK_FLAGS
10796 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10797 #undef PIPE_CONF_QUIRK
10798
10799         return true;
10800 }
10801
10802 static void check_wm_state(struct drm_device *dev)
10803 {
10804         struct drm_i915_private *dev_priv = dev->dev_private;
10805         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10806         struct intel_crtc *intel_crtc;
10807         int plane;
10808
10809         if (INTEL_INFO(dev)->gen < 9)
10810                 return;
10811
10812         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10813         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10814
10815         for_each_intel_crtc(dev, intel_crtc) {
10816                 struct skl_ddb_entry *hw_entry, *sw_entry;
10817                 const enum pipe pipe = intel_crtc->pipe;
10818
10819                 if (!intel_crtc->active)
10820                         continue;
10821
10822                 /* planes */
10823                 for_each_plane(dev_priv, pipe, plane) {
10824                         hw_entry = &hw_ddb.plane[pipe][plane];
10825                         sw_entry = &sw_ddb->plane[pipe][plane];
10826
10827                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10828                                 continue;
10829
10830                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10831                                   "(expected (%u,%u), found (%u,%u))\n",
10832                                   pipe_name(pipe), plane + 1,
10833                                   sw_entry->start, sw_entry->end,
10834                                   hw_entry->start, hw_entry->end);
10835                 }
10836
10837                 /* cursor */
10838                 hw_entry = &hw_ddb.cursor[pipe];
10839                 sw_entry = &sw_ddb->cursor[pipe];
10840
10841                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10842                         continue;
10843
10844                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10845                           "(expected (%u,%u), found (%u,%u))\n",
10846                           pipe_name(pipe),
10847                           sw_entry->start, sw_entry->end,
10848                           hw_entry->start, hw_entry->end);
10849         }
10850 }
10851
10852 static void
10853 check_connector_state(struct drm_device *dev)
10854 {
10855         struct intel_connector *connector;
10856
10857         for_each_intel_connector(dev, connector) {
10858                 /* This also checks the encoder/connector hw state with the
10859                  * ->get_hw_state callbacks. */
10860                 intel_connector_check_state(connector);
10861
10862                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10863                      "connector's staged encoder doesn't match current encoder\n");
10864         }
10865 }
10866
10867 static void
10868 check_encoder_state(struct drm_device *dev)
10869 {
10870         struct intel_encoder *encoder;
10871         struct intel_connector *connector;
10872
10873         for_each_intel_encoder(dev, encoder) {
10874                 bool enabled = false;
10875                 bool active = false;
10876                 enum pipe pipe, tracked_pipe;
10877
10878                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10879                               encoder->base.base.id,
10880                               encoder->base.name);
10881
10882                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10883                      "encoder's stage crtc doesn't match current crtc\n");
10884                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10885                      "encoder's active_connectors set, but no crtc\n");
10886
10887                 for_each_intel_connector(dev, connector) {
10888                         if (connector->base.encoder != &encoder->base)
10889                                 continue;
10890                         enabled = true;
10891                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10892                                 active = true;
10893                 }
10894                 /*
10895                  * for MST connectors if we unplug the connector is gone
10896                  * away but the encoder is still connected to a crtc
10897                  * until a modeset happens in response to the hotplug.
10898                  */
10899                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10900                         continue;
10901
10902                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10903                      "encoder's enabled state mismatch "
10904                      "(expected %i, found %i)\n",
10905                      !!encoder->base.crtc, enabled);
10906                 I915_STATE_WARN(active && !encoder->base.crtc,
10907                      "active encoder with no crtc\n");
10908
10909                 I915_STATE_WARN(encoder->connectors_active != active,
10910                      "encoder's computed active state doesn't match tracked active state "
10911                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10912
10913                 active = encoder->get_hw_state(encoder, &pipe);
10914                 I915_STATE_WARN(active != encoder->connectors_active,
10915                      "encoder's hw state doesn't match sw tracking "
10916                      "(expected %i, found %i)\n",
10917                      encoder->connectors_active, active);
10918
10919                 if (!encoder->base.crtc)
10920                         continue;
10921
10922                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10923                 I915_STATE_WARN(active && pipe != tracked_pipe,
10924                      "active encoder's pipe doesn't match"
10925                      "(expected %i, found %i)\n",
10926                      tracked_pipe, pipe);
10927
10928         }
10929 }
10930
10931 static void
10932 check_crtc_state(struct drm_device *dev)
10933 {
10934         struct drm_i915_private *dev_priv = dev->dev_private;
10935         struct intel_crtc *crtc;
10936         struct intel_encoder *encoder;
10937         struct intel_crtc_state pipe_config;
10938
10939         for_each_intel_crtc(dev, crtc) {
10940                 bool enabled = false;
10941                 bool active = false;
10942
10943                 memset(&pipe_config, 0, sizeof(pipe_config));
10944
10945                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10946                               crtc->base.base.id);
10947
10948                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
10949                      "active crtc, but not enabled in sw tracking\n");
10950
10951                 for_each_intel_encoder(dev, encoder) {
10952                         if (encoder->base.crtc != &crtc->base)
10953                                 continue;
10954                         enabled = true;
10955                         if (encoder->connectors_active)
10956                                 active = true;
10957                 }
10958
10959                 I915_STATE_WARN(active != crtc->active,
10960                      "crtc's computed active state doesn't match tracked active state "
10961                      "(expected %i, found %i)\n", active, crtc->active);
10962                 I915_STATE_WARN(enabled != crtc->base.state->enable,
10963                      "crtc's computed enabled state doesn't match tracked enabled state "
10964                      "(expected %i, found %i)\n", enabled,
10965                                 crtc->base.state->enable);
10966
10967                 active = dev_priv->display.get_pipe_config(crtc,
10968                                                            &pipe_config);
10969
10970                 /* hw state is inconsistent with the pipe quirk */
10971                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10972                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10973                         active = crtc->active;
10974
10975                 for_each_intel_encoder(dev, encoder) {
10976                         enum pipe pipe;
10977                         if (encoder->base.crtc != &crtc->base)
10978                                 continue;
10979                         if (encoder->get_hw_state(encoder, &pipe))
10980                                 encoder->get_config(encoder, &pipe_config);
10981                 }
10982
10983                 I915_STATE_WARN(crtc->active != active,
10984                      "crtc active state doesn't match with hw state "
10985                      "(expected %i, found %i)\n", crtc->active, active);
10986
10987                 if (active &&
10988                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10989                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
10990                         intel_dump_pipe_config(crtc, &pipe_config,
10991                                                "[hw state]");
10992                         intel_dump_pipe_config(crtc, crtc->config,
10993                                                "[sw state]");
10994                 }
10995         }
10996 }
10997
10998 static void
10999 check_shared_dpll_state(struct drm_device *dev)
11000 {
11001         struct drm_i915_private *dev_priv = dev->dev_private;
11002         struct intel_crtc *crtc;
11003         struct intel_dpll_hw_state dpll_hw_state;
11004         int i;
11005
11006         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11007                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11008                 int enabled_crtcs = 0, active_crtcs = 0;
11009                 bool active;
11010
11011                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11012
11013                 DRM_DEBUG_KMS("%s\n", pll->name);
11014
11015                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11016
11017                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11018                      "more active pll users than references: %i vs %i\n",
11019                      pll->active, hweight32(pll->config.crtc_mask));
11020                 I915_STATE_WARN(pll->active && !pll->on,
11021                      "pll in active use but not on in sw tracking\n");
11022                 I915_STATE_WARN(pll->on && !pll->active,
11023                      "pll in on but not on in use in sw tracking\n");
11024                 I915_STATE_WARN(pll->on != active,
11025                      "pll on state mismatch (expected %i, found %i)\n",
11026                      pll->on, active);
11027
11028                 for_each_intel_crtc(dev, crtc) {
11029                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11030                                 enabled_crtcs++;
11031                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11032                                 active_crtcs++;
11033                 }
11034                 I915_STATE_WARN(pll->active != active_crtcs,
11035                      "pll active crtcs mismatch (expected %i, found %i)\n",
11036                      pll->active, active_crtcs);
11037                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11038                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
11039                      hweight32(pll->config.crtc_mask), enabled_crtcs);
11040
11041                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11042                                        sizeof(dpll_hw_state)),
11043                      "pll hw state mismatch\n");
11044         }
11045 }
11046
11047 void
11048 intel_modeset_check_state(struct drm_device *dev)
11049 {
11050         check_wm_state(dev);
11051         check_connector_state(dev);
11052         check_encoder_state(dev);
11053         check_crtc_state(dev);
11054         check_shared_dpll_state(dev);
11055 }
11056
11057 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11058                                      int dotclock)
11059 {
11060         /*
11061          * FDI already provided one idea for the dotclock.
11062          * Yell if the encoder disagrees.
11063          */
11064         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11065              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11066              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11067 }
11068
11069 static void update_scanline_offset(struct intel_crtc *crtc)
11070 {
11071         struct drm_device *dev = crtc->base.dev;
11072
11073         /*
11074          * The scanline counter increments at the leading edge of hsync.
11075          *
11076          * On most platforms it starts counting from vtotal-1 on the
11077          * first active line. That means the scanline counter value is
11078          * always one less than what we would expect. Ie. just after
11079          * start of vblank, which also occurs at start of hsync (on the
11080          * last active line), the scanline counter will read vblank_start-1.
11081          *
11082          * On gen2 the scanline counter starts counting from 1 instead
11083          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11084          * to keep the value positive), instead of adding one.
11085          *
11086          * On HSW+ the behaviour of the scanline counter depends on the output
11087          * type. For DP ports it behaves like most other platforms, but on HDMI
11088          * there's an extra 1 line difference. So we need to add two instead of
11089          * one to the value.
11090          */
11091         if (IS_GEN2(dev)) {
11092                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11093                 int vtotal;
11094
11095                 vtotal = mode->crtc_vtotal;
11096                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11097                         vtotal /= 2;
11098
11099                 crtc->scanline_offset = vtotal - 1;
11100         } else if (HAS_DDI(dev) &&
11101                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11102                 crtc->scanline_offset = 2;
11103         } else
11104                 crtc->scanline_offset = 1;
11105 }
11106
11107 static struct intel_crtc_state *
11108 intel_modeset_compute_config(struct drm_crtc *crtc,
11109                              struct drm_display_mode *mode,
11110                              struct drm_framebuffer *fb,
11111                              unsigned *modeset_pipes,
11112                              unsigned *prepare_pipes,
11113                              unsigned *disable_pipes)
11114 {
11115         struct intel_crtc_state *pipe_config = NULL;
11116
11117         intel_modeset_affected_pipes(crtc, modeset_pipes,
11118                                      prepare_pipes, disable_pipes);
11119
11120         if ((*modeset_pipes) == 0)
11121                 goto out;
11122
11123         /*
11124          * Note this needs changes when we start tracking multiple modes
11125          * and crtcs.  At that point we'll need to compute the whole config
11126          * (i.e. one pipe_config for each crtc) rather than just the one
11127          * for this crtc.
11128          */
11129         pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11130         if (IS_ERR(pipe_config)) {
11131                 goto out;
11132         }
11133         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11134                                "[modeset]");
11135
11136 out:
11137         return pipe_config;
11138 }
11139
11140 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11141                                        unsigned modeset_pipes,
11142                                        unsigned disable_pipes)
11143 {
11144         struct drm_i915_private *dev_priv = to_i915(dev);
11145         unsigned clear_pipes = modeset_pipes | disable_pipes;
11146         struct intel_crtc *intel_crtc;
11147         int ret = 0;
11148
11149         if (!dev_priv->display.crtc_compute_clock)
11150                 return 0;
11151
11152         ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11153         if (ret)
11154                 goto done;
11155
11156         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11157                 struct intel_crtc_state *state = intel_crtc->new_config;
11158                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11159                                                            state);
11160                 if (ret) {
11161                         intel_shared_dpll_abort_config(dev_priv);
11162                         goto done;
11163                 }
11164         }
11165
11166 done:
11167         return ret;
11168 }
11169
11170 static int __intel_set_mode(struct drm_crtc *crtc,
11171                             struct drm_display_mode *mode,
11172                             int x, int y, struct drm_framebuffer *fb,
11173                             struct intel_crtc_state *pipe_config,
11174                             unsigned modeset_pipes,
11175                             unsigned prepare_pipes,
11176                             unsigned disable_pipes)
11177 {
11178         struct drm_device *dev = crtc->dev;
11179         struct drm_i915_private *dev_priv = dev->dev_private;
11180         struct drm_display_mode *saved_mode;
11181         struct intel_crtc *intel_crtc;
11182         int ret = 0;
11183
11184         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11185         if (!saved_mode)
11186                 return -ENOMEM;
11187
11188         *saved_mode = crtc->mode;
11189
11190         if (modeset_pipes)
11191                 to_intel_crtc(crtc)->new_config = pipe_config;
11192
11193         /*
11194          * See if the config requires any additional preparation, e.g.
11195          * to adjust global state with pipes off.  We need to do this
11196          * here so we can get the modeset_pipe updated config for the new
11197          * mode set on this crtc.  For other crtcs we need to use the
11198          * adjusted_mode bits in the crtc directly.
11199          */
11200         if (IS_VALLEYVIEW(dev)) {
11201                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11202
11203                 /* may have added more to prepare_pipes than we should */
11204                 prepare_pipes &= ~disable_pipes;
11205         }
11206
11207         ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11208         if (ret)
11209                 goto done;
11210
11211         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11212                 intel_crtc_disable(&intel_crtc->base);
11213
11214         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11215                 if (intel_crtc->base.state->enable)
11216                         dev_priv->display.crtc_disable(&intel_crtc->base);
11217         }
11218
11219         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11220          * to set it here already despite that we pass it down the callchain.
11221          *
11222          * Note we'll need to fix this up when we start tracking multiple
11223          * pipes; here we assume a single modeset_pipe and only track the
11224          * single crtc and mode.
11225          */
11226         if (modeset_pipes) {
11227                 crtc->mode = *mode;
11228                 /* mode_set/enable/disable functions rely on a correct pipe
11229                  * config. */
11230                 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11231
11232                 /*
11233                  * Calculate and store various constants which
11234                  * are later needed by vblank and swap-completion
11235                  * timestamping. They are derived from true hwmode.
11236                  */
11237                 drm_calc_timestamping_constants(crtc,
11238                                                 &pipe_config->base.adjusted_mode);
11239         }
11240
11241         /* Only after disabling all output pipelines that will be changed can we
11242          * update the the output configuration. */
11243         intel_modeset_update_state(dev, prepare_pipes);
11244
11245         modeset_update_crtc_power_domains(dev);
11246
11247         /* Set up the DPLL and any encoders state that needs to adjust or depend
11248          * on the DPLL.
11249          */
11250         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11251                 struct drm_plane *primary = intel_crtc->base.primary;
11252                 int vdisplay, hdisplay;
11253
11254                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11255                 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11256                                                    fb, 0, 0,
11257                                                    hdisplay, vdisplay,
11258                                                    x << 16, y << 16,
11259                                                    hdisplay << 16, vdisplay << 16);
11260         }
11261
11262         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11263         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11264                 update_scanline_offset(intel_crtc);
11265
11266                 dev_priv->display.crtc_enable(&intel_crtc->base);
11267         }
11268
11269         /* FIXME: add subpixel order */
11270 done:
11271         if (ret && crtc->state->enable)
11272                 crtc->mode = *saved_mode;
11273
11274         kfree(saved_mode);
11275         return ret;
11276 }
11277
11278 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11279                                 struct drm_display_mode *mode,
11280                                 int x, int y, struct drm_framebuffer *fb,
11281                                 struct intel_crtc_state *pipe_config,
11282                                 unsigned modeset_pipes,
11283                                 unsigned prepare_pipes,
11284                                 unsigned disable_pipes)
11285 {
11286         int ret;
11287
11288         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11289                                prepare_pipes, disable_pipes);
11290
11291         if (ret == 0)
11292                 intel_modeset_check_state(crtc->dev);
11293
11294         return ret;
11295 }
11296
11297 static int intel_set_mode(struct drm_crtc *crtc,
11298                           struct drm_display_mode *mode,
11299                           int x, int y, struct drm_framebuffer *fb)
11300 {
11301         struct intel_crtc_state *pipe_config;
11302         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11303
11304         pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11305                                                    &modeset_pipes,
11306                                                    &prepare_pipes,
11307                                                    &disable_pipes);
11308
11309         if (IS_ERR(pipe_config))
11310                 return PTR_ERR(pipe_config);
11311
11312         return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11313                                     modeset_pipes, prepare_pipes,
11314                                     disable_pipes);
11315 }
11316
11317 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11318 {
11319         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11320 }
11321
11322 #undef for_each_intel_crtc_masked
11323
11324 static void intel_set_config_free(struct intel_set_config *config)
11325 {
11326         if (!config)
11327                 return;
11328
11329         kfree(config->save_connector_encoders);
11330         kfree(config->save_encoder_crtcs);
11331         kfree(config->save_crtc_enabled);
11332         kfree(config);
11333 }
11334
11335 static int intel_set_config_save_state(struct drm_device *dev,
11336                                        struct intel_set_config *config)
11337 {
11338         struct drm_crtc *crtc;
11339         struct drm_encoder *encoder;
11340         struct drm_connector *connector;
11341         int count;
11342
11343         config->save_crtc_enabled =
11344                 kcalloc(dev->mode_config.num_crtc,
11345                         sizeof(bool), GFP_KERNEL);
11346         if (!config->save_crtc_enabled)
11347                 return -ENOMEM;
11348
11349         config->save_encoder_crtcs =
11350                 kcalloc(dev->mode_config.num_encoder,
11351                         sizeof(struct drm_crtc *), GFP_KERNEL);
11352         if (!config->save_encoder_crtcs)
11353                 return -ENOMEM;
11354
11355         config->save_connector_encoders =
11356                 kcalloc(dev->mode_config.num_connector,
11357                         sizeof(struct drm_encoder *), GFP_KERNEL);
11358         if (!config->save_connector_encoders)
11359                 return -ENOMEM;
11360
11361         /* Copy data. Note that driver private data is not affected.
11362          * Should anything bad happen only the expected state is
11363          * restored, not the drivers personal bookkeeping.
11364          */
11365         count = 0;
11366         for_each_crtc(dev, crtc) {
11367                 config->save_crtc_enabled[count++] = crtc->state->enable;
11368         }
11369
11370         count = 0;
11371         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11372                 config->save_encoder_crtcs[count++] = encoder->crtc;
11373         }
11374
11375         count = 0;
11376         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11377                 config->save_connector_encoders[count++] = connector->encoder;
11378         }
11379
11380         return 0;
11381 }
11382
11383 static void intel_set_config_restore_state(struct drm_device *dev,
11384                                            struct intel_set_config *config)
11385 {
11386         struct intel_crtc *crtc;
11387         struct intel_encoder *encoder;
11388         struct intel_connector *connector;
11389         int count;
11390
11391         count = 0;
11392         for_each_intel_crtc(dev, crtc) {
11393                 crtc->new_enabled = config->save_crtc_enabled[count++];
11394
11395                 if (crtc->new_enabled)
11396                         crtc->new_config = crtc->config;
11397                 else
11398                         crtc->new_config = NULL;
11399         }
11400
11401         count = 0;
11402         for_each_intel_encoder(dev, encoder) {
11403                 encoder->new_crtc =
11404                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11405         }
11406
11407         count = 0;
11408         for_each_intel_connector(dev, connector) {
11409                 connector->new_encoder =
11410                         to_intel_encoder(config->save_connector_encoders[count++]);
11411         }
11412 }
11413
11414 static bool
11415 is_crtc_connector_off(struct drm_mode_set *set)
11416 {
11417         int i;
11418
11419         if (set->num_connectors == 0)
11420                 return false;
11421
11422         if (WARN_ON(set->connectors == NULL))
11423                 return false;
11424
11425         for (i = 0; i < set->num_connectors; i++)
11426                 if (set->connectors[i]->encoder &&
11427                     set->connectors[i]->encoder->crtc == set->crtc &&
11428                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11429                         return true;
11430
11431         return false;
11432 }
11433
11434 static void
11435 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11436                                       struct intel_set_config *config)
11437 {
11438
11439         /* We should be able to check here if the fb has the same properties
11440          * and then just flip_or_move it */
11441         if (is_crtc_connector_off(set)) {
11442                 config->mode_changed = true;
11443         } else if (set->crtc->primary->fb != set->fb) {
11444                 /*
11445                  * If we have no fb, we can only flip as long as the crtc is
11446                  * active, otherwise we need a full mode set.  The crtc may
11447                  * be active if we've only disabled the primary plane, or
11448                  * in fastboot situations.
11449                  */
11450                 if (set->crtc->primary->fb == NULL) {
11451                         struct intel_crtc *intel_crtc =
11452                                 to_intel_crtc(set->crtc);
11453
11454                         if (intel_crtc->active) {
11455                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11456                                 config->fb_changed = true;
11457                         } else {
11458                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11459                                 config->mode_changed = true;
11460                         }
11461                 } else if (set->fb == NULL) {
11462                         config->mode_changed = true;
11463                 } else if (set->fb->pixel_format !=
11464                            set->crtc->primary->fb->pixel_format) {
11465                         config->mode_changed = true;
11466                 } else {
11467                         config->fb_changed = true;
11468                 }
11469         }
11470
11471         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11472                 config->fb_changed = true;
11473
11474         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11475                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11476                 drm_mode_debug_printmodeline(&set->crtc->mode);
11477                 drm_mode_debug_printmodeline(set->mode);
11478                 config->mode_changed = true;
11479         }
11480
11481         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11482                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11483 }
11484
11485 static int
11486 intel_modeset_stage_output_state(struct drm_device *dev,
11487                                  struct drm_mode_set *set,
11488                                  struct intel_set_config *config)
11489 {
11490         struct intel_connector *connector;
11491         struct intel_encoder *encoder;
11492         struct intel_crtc *crtc;
11493         int ro;
11494
11495         /* The upper layers ensure that we either disable a crtc or have a list
11496          * of connectors. For paranoia, double-check this. */
11497         WARN_ON(!set->fb && (set->num_connectors != 0));
11498         WARN_ON(set->fb && (set->num_connectors == 0));
11499
11500         for_each_intel_connector(dev, connector) {
11501                 /* Otherwise traverse passed in connector list and get encoders
11502                  * for them. */
11503                 for (ro = 0; ro < set->num_connectors; ro++) {
11504                         if (set->connectors[ro] == &connector->base) {
11505                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11506                                 break;
11507                         }
11508                 }
11509
11510                 /* If we disable the crtc, disable all its connectors. Also, if
11511                  * the connector is on the changing crtc but not on the new
11512                  * connector list, disable it. */
11513                 if ((!set->fb || ro == set->num_connectors) &&
11514                     connector->base.encoder &&
11515                     connector->base.encoder->crtc == set->crtc) {
11516                         connector->new_encoder = NULL;
11517
11518                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11519                                 connector->base.base.id,
11520                                 connector->base.name);
11521                 }
11522
11523
11524                 if (&connector->new_encoder->base != connector->base.encoder) {
11525                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11526                                       connector->base.base.id,
11527                                       connector->base.name);
11528                         config->mode_changed = true;
11529                 }
11530         }
11531         /* connector->new_encoder is now updated for all connectors. */
11532
11533         /* Update crtc of enabled connectors. */
11534         for_each_intel_connector(dev, connector) {
11535                 struct drm_crtc *new_crtc;
11536
11537                 if (!connector->new_encoder)
11538                         continue;
11539
11540                 new_crtc = connector->new_encoder->base.crtc;
11541
11542                 for (ro = 0; ro < set->num_connectors; ro++) {
11543                         if (set->connectors[ro] == &connector->base)
11544                                 new_crtc = set->crtc;
11545                 }
11546
11547                 /* Make sure the new CRTC will work with the encoder */
11548                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11549                                          new_crtc)) {
11550                         return -EINVAL;
11551                 }
11552                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11553
11554                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11555                         connector->base.base.id,
11556                         connector->base.name,
11557                         new_crtc->base.id);
11558         }
11559
11560         /* Check for any encoders that needs to be disabled. */
11561         for_each_intel_encoder(dev, encoder) {
11562                 int num_connectors = 0;
11563                 for_each_intel_connector(dev, connector) {
11564                         if (connector->new_encoder == encoder) {
11565                                 WARN_ON(!connector->new_encoder->new_crtc);
11566                                 num_connectors++;
11567                         }
11568                 }
11569
11570                 if (num_connectors == 0)
11571                         encoder->new_crtc = NULL;
11572                 else if (num_connectors > 1)
11573                         return -EINVAL;
11574
11575                 /* Only now check for crtc changes so we don't miss encoders
11576                  * that will be disabled. */
11577                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11578                         DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11579                                       encoder->base.base.id,
11580                                       encoder->base.name);
11581                         config->mode_changed = true;
11582                 }
11583         }
11584         /* Now we've also updated encoder->new_crtc for all encoders. */
11585         for_each_intel_connector(dev, connector) {
11586                 if (connector->new_encoder)
11587                         if (connector->new_encoder != connector->encoder)
11588                                 connector->encoder = connector->new_encoder;
11589         }
11590         for_each_intel_crtc(dev, crtc) {
11591                 crtc->new_enabled = false;
11592
11593                 for_each_intel_encoder(dev, encoder) {
11594                         if (encoder->new_crtc == crtc) {
11595                                 crtc->new_enabled = true;
11596                                 break;
11597                         }
11598                 }
11599
11600                 if (crtc->new_enabled != crtc->base.state->enable) {
11601                         DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11602                                       crtc->base.base.id,
11603                                       crtc->new_enabled ? "en" : "dis");
11604                         config->mode_changed = true;
11605                 }
11606
11607                 if (crtc->new_enabled)
11608                         crtc->new_config = crtc->config;
11609                 else
11610                         crtc->new_config = NULL;
11611         }
11612
11613         return 0;
11614 }
11615
11616 static void disable_crtc_nofb(struct intel_crtc *crtc)
11617 {
11618         struct drm_device *dev = crtc->base.dev;
11619         struct intel_encoder *encoder;
11620         struct intel_connector *connector;
11621
11622         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11623                       pipe_name(crtc->pipe));
11624
11625         for_each_intel_connector(dev, connector) {
11626                 if (connector->new_encoder &&
11627                     connector->new_encoder->new_crtc == crtc)
11628                         connector->new_encoder = NULL;
11629         }
11630
11631         for_each_intel_encoder(dev, encoder) {
11632                 if (encoder->new_crtc == crtc)
11633                         encoder->new_crtc = NULL;
11634         }
11635
11636         crtc->new_enabled = false;
11637         crtc->new_config = NULL;
11638 }
11639
11640 static int intel_crtc_set_config(struct drm_mode_set *set)
11641 {
11642         struct drm_device *dev;
11643         struct drm_mode_set save_set;
11644         struct intel_set_config *config;
11645         struct intel_crtc_state *pipe_config;
11646         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11647         int ret;
11648
11649         BUG_ON(!set);
11650         BUG_ON(!set->crtc);
11651         BUG_ON(!set->crtc->helper_private);
11652
11653         /* Enforce sane interface api - has been abused by the fb helper. */
11654         BUG_ON(!set->mode && set->fb);
11655         BUG_ON(set->fb && set->num_connectors == 0);
11656
11657         if (set->fb) {
11658                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11659                                 set->crtc->base.id, set->fb->base.id,
11660                                 (int)set->num_connectors, set->x, set->y);
11661         } else {
11662                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11663         }
11664
11665         dev = set->crtc->dev;
11666
11667         ret = -ENOMEM;
11668         config = kzalloc(sizeof(*config), GFP_KERNEL);
11669         if (!config)
11670                 goto out_config;
11671
11672         ret = intel_set_config_save_state(dev, config);
11673         if (ret)
11674                 goto out_config;
11675
11676         save_set.crtc = set->crtc;
11677         save_set.mode = &set->crtc->mode;
11678         save_set.x = set->crtc->x;
11679         save_set.y = set->crtc->y;
11680         save_set.fb = set->crtc->primary->fb;
11681
11682         /* Compute whether we need a full modeset, only an fb base update or no
11683          * change at all. In the future we might also check whether only the
11684          * mode changed, e.g. for LVDS where we only change the panel fitter in
11685          * such cases. */
11686         intel_set_config_compute_mode_changes(set, config);
11687
11688         ret = intel_modeset_stage_output_state(dev, set, config);
11689         if (ret)
11690                 goto fail;
11691
11692         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11693                                                    set->fb,
11694                                                    &modeset_pipes,
11695                                                    &prepare_pipes,
11696                                                    &disable_pipes);
11697         if (IS_ERR(pipe_config)) {
11698                 ret = PTR_ERR(pipe_config);
11699                 goto fail;
11700         } else if (pipe_config) {
11701                 if (pipe_config->has_audio !=
11702                     to_intel_crtc(set->crtc)->config->has_audio)
11703                         config->mode_changed = true;
11704
11705                 /*
11706                  * Note we have an issue here with infoframes: current code
11707                  * only updates them on the full mode set path per hw
11708                  * requirements.  So here we should be checking for any
11709                  * required changes and forcing a mode set.
11710                  */
11711         }
11712
11713         /* set_mode will free it in the mode_changed case */
11714         if (!config->mode_changed)
11715                 kfree(pipe_config);
11716
11717         intel_update_pipe_size(to_intel_crtc(set->crtc));
11718
11719         if (config->mode_changed) {
11720                 ret = intel_set_mode_pipes(set->crtc, set->mode,
11721                                            set->x, set->y, set->fb, pipe_config,
11722                                            modeset_pipes, prepare_pipes,
11723                                            disable_pipes);
11724         } else if (config->fb_changed) {
11725                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11726                 struct drm_plane *primary = set->crtc->primary;
11727                 int vdisplay, hdisplay;
11728
11729                 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11730                 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11731                                                    0, 0, hdisplay, vdisplay,
11732                                                    set->x << 16, set->y << 16,
11733                                                    hdisplay << 16, vdisplay << 16);
11734
11735                 /*
11736                  * We need to make sure the primary plane is re-enabled if it
11737                  * has previously been turned off.
11738                  */
11739                 if (!intel_crtc->primary_enabled && ret == 0) {
11740                         WARN_ON(!intel_crtc->active);
11741                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11742                 }
11743
11744                 /*
11745                  * In the fastboot case this may be our only check of the
11746                  * state after boot.  It would be better to only do it on
11747                  * the first update, but we don't have a nice way of doing that
11748                  * (and really, set_config isn't used much for high freq page
11749                  * flipping, so increasing its cost here shouldn't be a big
11750                  * deal).
11751                  */
11752                 if (i915.fastboot && ret == 0)
11753                         intel_modeset_check_state(set->crtc->dev);
11754         }
11755
11756         if (ret) {
11757                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11758                               set->crtc->base.id, ret);
11759 fail:
11760                 intel_set_config_restore_state(dev, config);
11761
11762                 /*
11763                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11764                  * force the pipe off to avoid oopsing in the modeset code
11765                  * due to fb==NULL. This should only happen during boot since
11766                  * we don't yet reconstruct the FB from the hardware state.
11767                  */
11768                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11769                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11770
11771                 /* Try to restore the config */
11772                 if (config->mode_changed &&
11773                     intel_set_mode(save_set.crtc, save_set.mode,
11774                                    save_set.x, save_set.y, save_set.fb))
11775                         DRM_ERROR("failed to restore config after modeset failure\n");
11776         }
11777
11778 out_config:
11779         intel_set_config_free(config);
11780         return ret;
11781 }
11782
11783 static const struct drm_crtc_funcs intel_crtc_funcs = {
11784         .gamma_set = intel_crtc_gamma_set,
11785         .set_config = intel_crtc_set_config,
11786         .destroy = intel_crtc_destroy,
11787         .page_flip = intel_crtc_page_flip,
11788         .atomic_duplicate_state = intel_crtc_duplicate_state,
11789         .atomic_destroy_state = intel_crtc_destroy_state,
11790 };
11791
11792 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11793                                       struct intel_shared_dpll *pll,
11794                                       struct intel_dpll_hw_state *hw_state)
11795 {
11796         uint32_t val;
11797
11798         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11799                 return false;
11800
11801         val = I915_READ(PCH_DPLL(pll->id));
11802         hw_state->dpll = val;
11803         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11804         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11805
11806         return val & DPLL_VCO_ENABLE;
11807 }
11808
11809 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11810                                   struct intel_shared_dpll *pll)
11811 {
11812         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11813         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11814 }
11815
11816 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11817                                 struct intel_shared_dpll *pll)
11818 {
11819         /* PCH refclock must be enabled first */
11820         ibx_assert_pch_refclk_enabled(dev_priv);
11821
11822         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11823
11824         /* Wait for the clocks to stabilize. */
11825         POSTING_READ(PCH_DPLL(pll->id));
11826         udelay(150);
11827
11828         /* The pixel multiplier can only be updated once the
11829          * DPLL is enabled and the clocks are stable.
11830          *
11831          * So write it again.
11832          */
11833         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11834         POSTING_READ(PCH_DPLL(pll->id));
11835         udelay(200);
11836 }
11837
11838 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11839                                  struct intel_shared_dpll *pll)
11840 {
11841         struct drm_device *dev = dev_priv->dev;
11842         struct intel_crtc *crtc;
11843
11844         /* Make sure no transcoder isn't still depending on us. */
11845         for_each_intel_crtc(dev, crtc) {
11846                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11847                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11848         }
11849
11850         I915_WRITE(PCH_DPLL(pll->id), 0);
11851         POSTING_READ(PCH_DPLL(pll->id));
11852         udelay(200);
11853 }
11854
11855 static char *ibx_pch_dpll_names[] = {
11856         "PCH DPLL A",
11857         "PCH DPLL B",
11858 };
11859
11860 static void ibx_pch_dpll_init(struct drm_device *dev)
11861 {
11862         struct drm_i915_private *dev_priv = dev->dev_private;
11863         int i;
11864
11865         dev_priv->num_shared_dpll = 2;
11866
11867         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11868                 dev_priv->shared_dplls[i].id = i;
11869                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11870                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11871                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11872                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11873                 dev_priv->shared_dplls[i].get_hw_state =
11874                         ibx_pch_dpll_get_hw_state;
11875         }
11876 }
11877
11878 static void intel_shared_dpll_init(struct drm_device *dev)
11879 {
11880         struct drm_i915_private *dev_priv = dev->dev_private;
11881
11882         if (HAS_DDI(dev))
11883                 intel_ddi_pll_init(dev);
11884         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11885                 ibx_pch_dpll_init(dev);
11886         else
11887                 dev_priv->num_shared_dpll = 0;
11888
11889         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11890 }
11891
11892 /**
11893  * intel_prepare_plane_fb - Prepare fb for usage on plane
11894  * @plane: drm plane to prepare for
11895  * @fb: framebuffer to prepare for presentation
11896  *
11897  * Prepares a framebuffer for usage on a display plane.  Generally this
11898  * involves pinning the underlying object and updating the frontbuffer tracking
11899  * bits.  Some older platforms need special physical address handling for
11900  * cursor planes.
11901  *
11902  * Returns 0 on success, negative error code on failure.
11903  */
11904 int
11905 intel_prepare_plane_fb(struct drm_plane *plane,
11906                        struct drm_framebuffer *fb,
11907                        const struct drm_plane_state *new_state)
11908 {
11909         struct drm_device *dev = plane->dev;
11910         struct intel_plane *intel_plane = to_intel_plane(plane);
11911         enum pipe pipe = intel_plane->pipe;
11912         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11913         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11914         unsigned frontbuffer_bits = 0;
11915         int ret = 0;
11916
11917         if (!obj)
11918                 return 0;
11919
11920         switch (plane->type) {
11921         case DRM_PLANE_TYPE_PRIMARY:
11922                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11923                 break;
11924         case DRM_PLANE_TYPE_CURSOR:
11925                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11926                 break;
11927         case DRM_PLANE_TYPE_OVERLAY:
11928                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11929                 break;
11930         }
11931
11932         mutex_lock(&dev->struct_mutex);
11933
11934         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11935             INTEL_INFO(dev)->cursor_needs_physical) {
11936                 int align = IS_I830(dev) ? 16 * 1024 : 256;
11937                 ret = i915_gem_object_attach_phys(obj, align);
11938                 if (ret)
11939                         DRM_DEBUG_KMS("failed to attach phys object\n");
11940         } else {
11941                 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11942         }
11943
11944         if (ret == 0)
11945                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11946
11947         mutex_unlock(&dev->struct_mutex);
11948
11949         return ret;
11950 }
11951
11952 /**
11953  * intel_cleanup_plane_fb - Cleans up an fb after plane use
11954  * @plane: drm plane to clean up for
11955  * @fb: old framebuffer that was on plane
11956  *
11957  * Cleans up a framebuffer that has just been removed from a plane.
11958  */
11959 void
11960 intel_cleanup_plane_fb(struct drm_plane *plane,
11961                        struct drm_framebuffer *fb,
11962                        const struct drm_plane_state *old_state)
11963 {
11964         struct drm_device *dev = plane->dev;
11965         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11966
11967         if (WARN_ON(!obj))
11968                 return;
11969
11970         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11971             !INTEL_INFO(dev)->cursor_needs_physical) {
11972                 mutex_lock(&dev->struct_mutex);
11973                 intel_unpin_fb_obj(obj);
11974                 mutex_unlock(&dev->struct_mutex);
11975         }
11976 }
11977
11978 static int
11979 intel_check_primary_plane(struct drm_plane *plane,
11980                           struct intel_plane_state *state)
11981 {
11982         struct drm_device *dev = plane->dev;
11983         struct drm_i915_private *dev_priv = dev->dev_private;
11984         struct drm_crtc *crtc = state->base.crtc;
11985         struct intel_crtc *intel_crtc;
11986         struct drm_framebuffer *fb = state->base.fb;
11987         struct drm_rect *dest = &state->dst;
11988         struct drm_rect *src = &state->src;
11989         const struct drm_rect *clip = &state->clip;
11990         int ret;
11991
11992         crtc = crtc ? crtc : plane->crtc;
11993         intel_crtc = to_intel_crtc(crtc);
11994
11995         ret = drm_plane_helper_check_update(plane, crtc, fb,
11996                                             src, dest, clip,
11997                                             DRM_PLANE_HELPER_NO_SCALING,
11998                                             DRM_PLANE_HELPER_NO_SCALING,
11999                                             false, true, &state->visible);
12000         if (ret)
12001                 return ret;
12002
12003         if (intel_crtc->active) {
12004                 intel_crtc->atomic.wait_for_flips = true;
12005
12006                 /*
12007                  * FBC does not work on some platforms for rotated
12008                  * planes, so disable it when rotation is not 0 and
12009                  * update it when rotation is set back to 0.
12010                  *
12011                  * FIXME: This is redundant with the fbc update done in
12012                  * the primary plane enable function except that that
12013                  * one is done too late. We eventually need to unify
12014                  * this.
12015                  */
12016                 if (intel_crtc->primary_enabled &&
12017                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12018                     dev_priv->fbc.crtc == intel_crtc &&
12019                     state->base.rotation != BIT(DRM_ROTATE_0)) {
12020                         intel_crtc->atomic.disable_fbc = true;
12021                 }
12022
12023                 if (state->visible) {
12024                         /*
12025                          * BDW signals flip done immediately if the plane
12026                          * is disabled, even if the plane enable is already
12027                          * armed to occur at the next vblank :(
12028                          */
12029                         if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12030                                 intel_crtc->atomic.wait_vblank = true;
12031                 }
12032
12033                 intel_crtc->atomic.fb_bits |=
12034                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12035
12036                 intel_crtc->atomic.update_fbc = true;
12037
12038                 /* Update watermarks on tiling changes. */
12039                 if (!plane->state->fb || !state->base.fb ||
12040                     plane->state->fb->modifier[0] !=
12041                     state->base.fb->modifier[0])
12042                         intel_crtc->atomic.update_wm = true;
12043         }
12044
12045         return 0;
12046 }
12047
12048 static void
12049 intel_commit_primary_plane(struct drm_plane *plane,
12050                            struct intel_plane_state *state)
12051 {
12052         struct drm_crtc *crtc = state->base.crtc;
12053         struct drm_framebuffer *fb = state->base.fb;
12054         struct drm_device *dev = plane->dev;
12055         struct drm_i915_private *dev_priv = dev->dev_private;
12056         struct intel_crtc *intel_crtc;
12057         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12058         struct intel_plane *intel_plane = to_intel_plane(plane);
12059         struct drm_rect *src = &state->src;
12060
12061         crtc = crtc ? crtc : plane->crtc;
12062         intel_crtc = to_intel_crtc(crtc);
12063
12064         plane->fb = fb;
12065         crtc->x = src->x1 >> 16;
12066         crtc->y = src->y1 >> 16;
12067
12068         intel_plane->obj = obj;
12069
12070         if (intel_crtc->active) {
12071                 if (state->visible) {
12072                         /* FIXME: kill this fastboot hack */
12073                         intel_update_pipe_size(intel_crtc);
12074
12075                         intel_crtc->primary_enabled = true;
12076
12077                         dev_priv->display.update_primary_plane(crtc, plane->fb,
12078                                         crtc->x, crtc->y);
12079                 } else {
12080                         /*
12081                          * If clipping results in a non-visible primary plane,
12082                          * we'll disable the primary plane.  Note that this is
12083                          * a bit different than what happens if userspace
12084                          * explicitly disables the plane by passing fb=0
12085                          * because plane->fb still gets set and pinned.
12086                          */
12087                         intel_disable_primary_hw_plane(plane, crtc);
12088                 }
12089         }
12090 }
12091
12092 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12093 {
12094         struct drm_device *dev = crtc->dev;
12095         struct drm_i915_private *dev_priv = dev->dev_private;
12096         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12097         struct intel_plane *intel_plane;
12098         struct drm_plane *p;
12099         unsigned fb_bits = 0;
12100
12101         /* Track fb's for any planes being disabled */
12102         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12103                 intel_plane = to_intel_plane(p);
12104
12105                 if (intel_crtc->atomic.disabled_planes &
12106                     (1 << drm_plane_index(p))) {
12107                         switch (p->type) {
12108                         case DRM_PLANE_TYPE_PRIMARY:
12109                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12110                                 break;
12111                         case DRM_PLANE_TYPE_CURSOR:
12112                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12113                                 break;
12114                         case DRM_PLANE_TYPE_OVERLAY:
12115                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12116                                 break;
12117                         }
12118
12119                         mutex_lock(&dev->struct_mutex);
12120                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12121                         mutex_unlock(&dev->struct_mutex);
12122                 }
12123         }
12124
12125         if (intel_crtc->atomic.wait_for_flips)
12126                 intel_crtc_wait_for_pending_flips(crtc);
12127
12128         if (intel_crtc->atomic.disable_fbc)
12129                 intel_fbc_disable(dev);
12130
12131         if (intel_crtc->atomic.pre_disable_primary)
12132                 intel_pre_disable_primary(crtc);
12133
12134         if (intel_crtc->atomic.update_wm)
12135                 intel_update_watermarks(crtc);
12136
12137         intel_runtime_pm_get(dev_priv);
12138
12139         /* Perform vblank evasion around commit operation */
12140         if (intel_crtc->active)
12141                 intel_crtc->atomic.evade =
12142                         intel_pipe_update_start(intel_crtc,
12143                                                 &intel_crtc->atomic.start_vbl_count);
12144 }
12145
12146 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12147 {
12148         struct drm_device *dev = crtc->dev;
12149         struct drm_i915_private *dev_priv = dev->dev_private;
12150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12151         struct drm_plane *p;
12152
12153         if (intel_crtc->atomic.evade)
12154                 intel_pipe_update_end(intel_crtc,
12155                                       intel_crtc->atomic.start_vbl_count);
12156
12157         intel_runtime_pm_put(dev_priv);
12158
12159         if (intel_crtc->atomic.wait_vblank)
12160                 intel_wait_for_vblank(dev, intel_crtc->pipe);
12161
12162         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12163
12164         if (intel_crtc->atomic.update_fbc) {
12165                 mutex_lock(&dev->struct_mutex);
12166                 intel_fbc_update(dev);
12167                 mutex_unlock(&dev->struct_mutex);
12168         }
12169
12170         if (intel_crtc->atomic.post_enable_primary)
12171                 intel_post_enable_primary(crtc);
12172
12173         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12174                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12175                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12176                                                        false, false);
12177
12178         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12179 }
12180
12181 /**
12182  * intel_plane_destroy - destroy a plane
12183  * @plane: plane to destroy
12184  *
12185  * Common destruction function for all types of planes (primary, cursor,
12186  * sprite).
12187  */
12188 void intel_plane_destroy(struct drm_plane *plane)
12189 {
12190         struct intel_plane *intel_plane = to_intel_plane(plane);
12191         drm_plane_cleanup(plane);
12192         kfree(intel_plane);
12193 }
12194
12195 const struct drm_plane_funcs intel_plane_funcs = {
12196         .update_plane = drm_plane_helper_update,
12197         .disable_plane = drm_plane_helper_disable,
12198         .destroy = intel_plane_destroy,
12199         .set_property = drm_atomic_helper_plane_set_property,
12200         .atomic_get_property = intel_plane_atomic_get_property,
12201         .atomic_set_property = intel_plane_atomic_set_property,
12202         .atomic_duplicate_state = intel_plane_duplicate_state,
12203         .atomic_destroy_state = intel_plane_destroy_state,
12204
12205 };
12206
12207 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12208                                                     int pipe)
12209 {
12210         struct intel_plane *primary;
12211         struct intel_plane_state *state;
12212         const uint32_t *intel_primary_formats;
12213         int num_formats;
12214
12215         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12216         if (primary == NULL)
12217                 return NULL;
12218
12219         state = intel_create_plane_state(&primary->base);
12220         if (!state) {
12221                 kfree(primary);
12222                 return NULL;
12223         }
12224         primary->base.state = &state->base;
12225
12226         primary->can_scale = false;
12227         primary->max_downscale = 1;
12228         primary->pipe = pipe;
12229         primary->plane = pipe;
12230         primary->check_plane = intel_check_primary_plane;
12231         primary->commit_plane = intel_commit_primary_plane;
12232         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12233                 primary->plane = !pipe;
12234
12235         if (INTEL_INFO(dev)->gen <= 3) {
12236                 intel_primary_formats = intel_primary_formats_gen2;
12237                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12238         } else {
12239                 intel_primary_formats = intel_primary_formats_gen4;
12240                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12241         }
12242
12243         drm_universal_plane_init(dev, &primary->base, 0,
12244                                  &intel_plane_funcs,
12245                                  intel_primary_formats, num_formats,
12246                                  DRM_PLANE_TYPE_PRIMARY);
12247
12248         if (INTEL_INFO(dev)->gen >= 4) {
12249                 if (!dev->mode_config.rotation_property)
12250                         dev->mode_config.rotation_property =
12251                                 drm_mode_create_rotation_property(dev,
12252                                                         BIT(DRM_ROTATE_0) |
12253                                                         BIT(DRM_ROTATE_180));
12254                 if (dev->mode_config.rotation_property)
12255                         drm_object_attach_property(&primary->base.base,
12256                                 dev->mode_config.rotation_property,
12257                                 state->base.rotation);
12258         }
12259
12260         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12261
12262         return &primary->base;
12263 }
12264
12265 static int
12266 intel_check_cursor_plane(struct drm_plane *plane,
12267                          struct intel_plane_state *state)
12268 {
12269         struct drm_crtc *crtc = state->base.crtc;
12270         struct drm_device *dev = plane->dev;
12271         struct drm_framebuffer *fb = state->base.fb;
12272         struct drm_rect *dest = &state->dst;
12273         struct drm_rect *src = &state->src;
12274         const struct drm_rect *clip = &state->clip;
12275         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12276         struct intel_crtc *intel_crtc;
12277         unsigned stride;
12278         int ret;
12279
12280         crtc = crtc ? crtc : plane->crtc;
12281         intel_crtc = to_intel_crtc(crtc);
12282
12283         ret = drm_plane_helper_check_update(plane, crtc, fb,
12284                                             src, dest, clip,
12285                                             DRM_PLANE_HELPER_NO_SCALING,
12286                                             DRM_PLANE_HELPER_NO_SCALING,
12287                                             true, true, &state->visible);
12288         if (ret)
12289                 return ret;
12290
12291
12292         /* if we want to turn off the cursor ignore width and height */
12293         if (!obj)
12294                 goto finish;
12295
12296         /* Check for which cursor types we support */
12297         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12298                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12299                           state->base.crtc_w, state->base.crtc_h);
12300                 return -EINVAL;
12301         }
12302
12303         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12304         if (obj->base.size < stride * state->base.crtc_h) {
12305                 DRM_DEBUG_KMS("buffer is too small\n");
12306                 return -ENOMEM;
12307         }
12308
12309         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12310                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12311                 ret = -EINVAL;
12312         }
12313
12314 finish:
12315         if (intel_crtc->active) {
12316                 if (intel_crtc->base.cursor->state->crtc_w != state->base.crtc_w)
12317                         intel_crtc->atomic.update_wm = true;
12318
12319                 intel_crtc->atomic.fb_bits |=
12320                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12321         }
12322
12323         return ret;
12324 }
12325
12326 static void
12327 intel_commit_cursor_plane(struct drm_plane *plane,
12328                           struct intel_plane_state *state)
12329 {
12330         struct drm_crtc *crtc = state->base.crtc;
12331         struct drm_device *dev = plane->dev;
12332         struct intel_crtc *intel_crtc;
12333         struct intel_plane *intel_plane = to_intel_plane(plane);
12334         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12335         uint32_t addr;
12336
12337         crtc = crtc ? crtc : plane->crtc;
12338         intel_crtc = to_intel_crtc(crtc);
12339
12340         plane->fb = state->base.fb;
12341         crtc->cursor_x = state->base.crtc_x;
12342         crtc->cursor_y = state->base.crtc_y;
12343
12344         intel_plane->obj = obj;
12345
12346         if (intel_crtc->cursor_bo == obj)
12347                 goto update;
12348
12349         if (!obj)
12350                 addr = 0;
12351         else if (!INTEL_INFO(dev)->cursor_needs_physical)
12352                 addr = i915_gem_obj_ggtt_offset(obj);
12353         else
12354                 addr = obj->phys_handle->busaddr;
12355
12356         intel_crtc->cursor_addr = addr;
12357         intel_crtc->cursor_bo = obj;
12358 update:
12359
12360         if (intel_crtc->active)
12361                 intel_crtc_update_cursor(crtc, state->visible);
12362 }
12363
12364 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12365                                                    int pipe)
12366 {
12367         struct intel_plane *cursor;
12368         struct intel_plane_state *state;
12369
12370         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12371         if (cursor == NULL)
12372                 return NULL;
12373
12374         state = intel_create_plane_state(&cursor->base);
12375         if (!state) {
12376                 kfree(cursor);
12377                 return NULL;
12378         }
12379         cursor->base.state = &state->base;
12380
12381         cursor->can_scale = false;
12382         cursor->max_downscale = 1;
12383         cursor->pipe = pipe;
12384         cursor->plane = pipe;
12385         cursor->check_plane = intel_check_cursor_plane;
12386         cursor->commit_plane = intel_commit_cursor_plane;
12387
12388         drm_universal_plane_init(dev, &cursor->base, 0,
12389                                  &intel_plane_funcs,
12390                                  intel_cursor_formats,
12391                                  ARRAY_SIZE(intel_cursor_formats),
12392                                  DRM_PLANE_TYPE_CURSOR);
12393
12394         if (INTEL_INFO(dev)->gen >= 4) {
12395                 if (!dev->mode_config.rotation_property)
12396                         dev->mode_config.rotation_property =
12397                                 drm_mode_create_rotation_property(dev,
12398                                                         BIT(DRM_ROTATE_0) |
12399                                                         BIT(DRM_ROTATE_180));
12400                 if (dev->mode_config.rotation_property)
12401                         drm_object_attach_property(&cursor->base.base,
12402                                 dev->mode_config.rotation_property,
12403                                 state->base.rotation);
12404         }
12405
12406         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12407
12408         return &cursor->base;
12409 }
12410
12411 static void intel_crtc_init(struct drm_device *dev, int pipe)
12412 {
12413         struct drm_i915_private *dev_priv = dev->dev_private;
12414         struct intel_crtc *intel_crtc;
12415         struct intel_crtc_state *crtc_state = NULL;
12416         struct drm_plane *primary = NULL;
12417         struct drm_plane *cursor = NULL;
12418         int i, ret;
12419
12420         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12421         if (intel_crtc == NULL)
12422                 return;
12423
12424         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12425         if (!crtc_state)
12426                 goto fail;
12427         intel_crtc_set_state(intel_crtc, crtc_state);
12428         crtc_state->base.crtc = &intel_crtc->base;
12429
12430         primary = intel_primary_plane_create(dev, pipe);
12431         if (!primary)
12432                 goto fail;
12433
12434         cursor = intel_cursor_plane_create(dev, pipe);
12435         if (!cursor)
12436                 goto fail;
12437
12438         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12439                                         cursor, &intel_crtc_funcs);
12440         if (ret)
12441                 goto fail;
12442
12443         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12444         for (i = 0; i < 256; i++) {
12445                 intel_crtc->lut_r[i] = i;
12446                 intel_crtc->lut_g[i] = i;
12447                 intel_crtc->lut_b[i] = i;
12448         }
12449
12450         /*
12451          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12452          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12453          */
12454         intel_crtc->pipe = pipe;
12455         intel_crtc->plane = pipe;
12456         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12457                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12458                 intel_crtc->plane = !pipe;
12459         }
12460
12461         intel_crtc->cursor_base = ~0;
12462         intel_crtc->cursor_cntl = ~0;
12463         intel_crtc->cursor_size = ~0;
12464
12465         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12466                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12467         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12468         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12469
12470         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12471
12472         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12473
12474         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12475         return;
12476
12477 fail:
12478         if (primary)
12479                 drm_plane_cleanup(primary);
12480         if (cursor)
12481                 drm_plane_cleanup(cursor);
12482         kfree(crtc_state);
12483         kfree(intel_crtc);
12484 }
12485
12486 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12487 {
12488         struct drm_encoder *encoder = connector->base.encoder;
12489         struct drm_device *dev = connector->base.dev;
12490
12491         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12492
12493         if (!encoder || WARN_ON(!encoder->crtc))
12494                 return INVALID_PIPE;
12495
12496         return to_intel_crtc(encoder->crtc)->pipe;
12497 }
12498
12499 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12500                                 struct drm_file *file)
12501 {
12502         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12503         struct drm_crtc *drmmode_crtc;
12504         struct intel_crtc *crtc;
12505
12506         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12507
12508         if (!drmmode_crtc) {
12509                 DRM_ERROR("no such CRTC id\n");
12510                 return -ENOENT;
12511         }
12512
12513         crtc = to_intel_crtc(drmmode_crtc);
12514         pipe_from_crtc_id->pipe = crtc->pipe;
12515
12516         return 0;
12517 }
12518
12519 static int intel_encoder_clones(struct intel_encoder *encoder)
12520 {
12521         struct drm_device *dev = encoder->base.dev;
12522         struct intel_encoder *source_encoder;
12523         int index_mask = 0;
12524         int entry = 0;
12525
12526         for_each_intel_encoder(dev, source_encoder) {
12527                 if (encoders_cloneable(encoder, source_encoder))
12528                         index_mask |= (1 << entry);
12529
12530                 entry++;
12531         }
12532
12533         return index_mask;
12534 }
12535
12536 static bool has_edp_a(struct drm_device *dev)
12537 {
12538         struct drm_i915_private *dev_priv = dev->dev_private;
12539
12540         if (!IS_MOBILE(dev))
12541                 return false;
12542
12543         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12544                 return false;
12545
12546         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12547                 return false;
12548
12549         return true;
12550 }
12551
12552 static bool intel_crt_present(struct drm_device *dev)
12553 {
12554         struct drm_i915_private *dev_priv = dev->dev_private;
12555
12556         if (INTEL_INFO(dev)->gen >= 9)
12557                 return false;
12558
12559         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12560                 return false;
12561
12562         if (IS_CHERRYVIEW(dev))
12563                 return false;
12564
12565         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12566                 return false;
12567
12568         return true;
12569 }
12570
12571 static void intel_setup_outputs(struct drm_device *dev)
12572 {
12573         struct drm_i915_private *dev_priv = dev->dev_private;
12574         struct intel_encoder *encoder;
12575         struct drm_connector *connector;
12576         bool dpd_is_edp = false;
12577
12578         intel_lvds_init(dev);
12579
12580         if (intel_crt_present(dev))
12581                 intel_crt_init(dev);
12582
12583         if (HAS_DDI(dev)) {
12584                 int found;
12585
12586                 /*
12587                  * Haswell uses DDI functions to detect digital outputs.
12588                  * On SKL pre-D0 the strap isn't connected, so we assume
12589                  * it's there.
12590                  */
12591                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12592                 /* WaIgnoreDDIAStrap: skl */
12593                 if (found ||
12594                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12595                         intel_ddi_init(dev, PORT_A);
12596
12597                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12598                  * register */
12599                 found = I915_READ(SFUSE_STRAP);
12600
12601                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12602                         intel_ddi_init(dev, PORT_B);
12603                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12604                         intel_ddi_init(dev, PORT_C);
12605                 if (found & SFUSE_STRAP_DDID_DETECTED)
12606                         intel_ddi_init(dev, PORT_D);
12607         } else if (HAS_PCH_SPLIT(dev)) {
12608                 int found;
12609                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12610
12611                 if (has_edp_a(dev))
12612                         intel_dp_init(dev, DP_A, PORT_A);
12613
12614                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12615                         /* PCH SDVOB multiplex with HDMIB */
12616                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12617                         if (!found)
12618                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12619                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12620                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12621                 }
12622
12623                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12624                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12625
12626                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12627                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12628
12629                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12630                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12631
12632                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12633                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12634         } else if (IS_VALLEYVIEW(dev)) {
12635                 /*
12636                  * The DP_DETECTED bit is the latched state of the DDC
12637                  * SDA pin at boot. However since eDP doesn't require DDC
12638                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12639                  * eDP ports may have been muxed to an alternate function.
12640                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12641                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12642                  * detect eDP ports.
12643                  */
12644                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12645                     !intel_dp_is_edp(dev, PORT_B))
12646                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12647                                         PORT_B);
12648                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12649                     intel_dp_is_edp(dev, PORT_B))
12650                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12651
12652                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12653                     !intel_dp_is_edp(dev, PORT_C))
12654                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12655                                         PORT_C);
12656                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12657                     intel_dp_is_edp(dev, PORT_C))
12658                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12659
12660                 if (IS_CHERRYVIEW(dev)) {
12661                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12662                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12663                                                 PORT_D);
12664                         /* eDP not supported on port D, so don't check VBT */
12665                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12666                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12667                 }
12668
12669                 intel_dsi_init(dev);
12670         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12671                 bool found = false;
12672
12673                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12674                         DRM_DEBUG_KMS("probing SDVOB\n");
12675                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12676                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12677                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12678                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12679                         }
12680
12681                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12682                                 intel_dp_init(dev, DP_B, PORT_B);
12683                 }
12684
12685                 /* Before G4X SDVOC doesn't have its own detect register */
12686
12687                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12688                         DRM_DEBUG_KMS("probing SDVOC\n");
12689                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12690                 }
12691
12692                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12693
12694                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12695                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12696                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12697                         }
12698                         if (SUPPORTS_INTEGRATED_DP(dev))
12699                                 intel_dp_init(dev, DP_C, PORT_C);
12700                 }
12701
12702                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12703                     (I915_READ(DP_D) & DP_DETECTED))
12704                         intel_dp_init(dev, DP_D, PORT_D);
12705         } else if (IS_GEN2(dev))
12706                 intel_dvo_init(dev);
12707
12708         if (SUPPORTS_TV(dev))
12709                 intel_tv_init(dev);
12710
12711         /*
12712          * FIXME:  We don't have full atomic support yet, but we want to be
12713          * able to enable/test plane updates via the atomic interface in the
12714          * meantime.  However as soon as we flip DRIVER_ATOMIC on, the DRM core
12715          * will take some atomic codepaths to lookup properties during
12716          * drmModeGetConnector() that unconditionally dereference
12717          * connector->state.
12718          *
12719          * We create a dummy connector state here for each connector to ensure
12720          * the DRM core doesn't try to dereference a NULL connector->state.
12721          * The actual connector properties will never be updated or contain
12722          * useful information, but since we're doing this specifically for
12723          * testing/debug of the plane operations (and only when a specific
12724          * kernel module option is given), that shouldn't really matter.
12725          *
12726          * Once atomic support for crtc's + connectors lands, this loop should
12727          * be removed since we'll be setting up real connector state, which
12728          * will contain Intel-specific properties.
12729          */
12730         if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12731                 list_for_each_entry(connector,
12732                                     &dev->mode_config.connector_list,
12733                                     head) {
12734                         if (!WARN_ON(connector->state)) {
12735                                 connector->state =
12736                                         kzalloc(sizeof(*connector->state),
12737                                                 GFP_KERNEL);
12738                         }
12739                 }
12740         }
12741
12742         intel_psr_init(dev);
12743
12744         for_each_intel_encoder(dev, encoder) {
12745                 encoder->base.possible_crtcs = encoder->crtc_mask;
12746                 encoder->base.possible_clones =
12747                         intel_encoder_clones(encoder);
12748         }
12749
12750         intel_init_pch_refclk(dev);
12751
12752         drm_helper_move_panel_connectors_to_head(dev);
12753 }
12754
12755 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12756 {
12757         struct drm_device *dev = fb->dev;
12758         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12759
12760         drm_framebuffer_cleanup(fb);
12761         mutex_lock(&dev->struct_mutex);
12762         WARN_ON(!intel_fb->obj->framebuffer_references--);
12763         drm_gem_object_unreference(&intel_fb->obj->base);
12764         mutex_unlock(&dev->struct_mutex);
12765         kfree(intel_fb);
12766 }
12767
12768 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12769                                                 struct drm_file *file,
12770                                                 unsigned int *handle)
12771 {
12772         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12773         struct drm_i915_gem_object *obj = intel_fb->obj;
12774
12775         return drm_gem_handle_create(file, &obj->base, handle);
12776 }
12777
12778 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12779         .destroy = intel_user_framebuffer_destroy,
12780         .create_handle = intel_user_framebuffer_create_handle,
12781 };
12782
12783 static
12784 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12785                          uint32_t pixel_format)
12786 {
12787         u32 gen = INTEL_INFO(dev)->gen;
12788
12789         if (gen >= 9) {
12790                 /* "The stride in bytes must not exceed the of the size of 8K
12791                  *  pixels and 32K bytes."
12792                  */
12793                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12794         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12795                 return 32*1024;
12796         } else if (gen >= 4) {
12797                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12798                         return 16*1024;
12799                 else
12800                         return 32*1024;
12801         } else if (gen >= 3) {
12802                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12803                         return 8*1024;
12804                 else
12805                         return 16*1024;
12806         } else {
12807                 /* XXX DSPC is limited to 4k tiled */
12808                 return 8*1024;
12809         }
12810 }
12811
12812 static int intel_framebuffer_init(struct drm_device *dev,
12813                                   struct intel_framebuffer *intel_fb,
12814                                   struct drm_mode_fb_cmd2 *mode_cmd,
12815                                   struct drm_i915_gem_object *obj)
12816 {
12817         int aligned_height;
12818         int ret;
12819         u32 pitch_limit, stride_alignment;
12820
12821         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12822
12823         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12824                 /* Enforce that fb modifier and tiling mode match, but only for
12825                  * X-tiled. This is needed for FBC. */
12826                 if (!!(obj->tiling_mode == I915_TILING_X) !=
12827                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12828                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12829                         return -EINVAL;
12830                 }
12831         } else {
12832                 if (obj->tiling_mode == I915_TILING_X)
12833                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12834                 else if (obj->tiling_mode == I915_TILING_Y) {
12835                         DRM_DEBUG("No Y tiling for legacy addfb\n");
12836                         return -EINVAL;
12837                 }
12838         }
12839
12840         /* Passed in modifier sanity checking. */
12841         switch (mode_cmd->modifier[0]) {
12842         case I915_FORMAT_MOD_Y_TILED:
12843         case I915_FORMAT_MOD_Yf_TILED:
12844                 if (INTEL_INFO(dev)->gen < 9) {
12845                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12846                                   mode_cmd->modifier[0]);
12847                         return -EINVAL;
12848                 }
12849         case DRM_FORMAT_MOD_NONE:
12850         case I915_FORMAT_MOD_X_TILED:
12851                 break;
12852         default:
12853                 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12854                                 mode_cmd->modifier[0]);
12855                 return -EINVAL;
12856         }
12857
12858         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12859                                                      mode_cmd->pixel_format);
12860         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12861                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12862                           mode_cmd->pitches[0], stride_alignment);
12863                 return -EINVAL;
12864         }
12865
12866         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12867                                            mode_cmd->pixel_format);
12868         if (mode_cmd->pitches[0] > pitch_limit) {
12869                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12870                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12871                           "tiled" : "linear",
12872                           mode_cmd->pitches[0], pitch_limit);
12873                 return -EINVAL;
12874         }
12875
12876         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12877             mode_cmd->pitches[0] != obj->stride) {
12878                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12879                           mode_cmd->pitches[0], obj->stride);
12880                 return -EINVAL;
12881         }
12882
12883         /* Reject formats not supported by any plane early. */
12884         switch (mode_cmd->pixel_format) {
12885         case DRM_FORMAT_C8:
12886         case DRM_FORMAT_RGB565:
12887         case DRM_FORMAT_XRGB8888:
12888         case DRM_FORMAT_ARGB8888:
12889                 break;
12890         case DRM_FORMAT_XRGB1555:
12891         case DRM_FORMAT_ARGB1555:
12892                 if (INTEL_INFO(dev)->gen > 3) {
12893                         DRM_DEBUG("unsupported pixel format: %s\n",
12894                                   drm_get_format_name(mode_cmd->pixel_format));
12895                         return -EINVAL;
12896                 }
12897                 break;
12898         case DRM_FORMAT_XBGR8888:
12899         case DRM_FORMAT_ABGR8888:
12900         case DRM_FORMAT_XRGB2101010:
12901         case DRM_FORMAT_ARGB2101010:
12902         case DRM_FORMAT_XBGR2101010:
12903         case DRM_FORMAT_ABGR2101010:
12904                 if (INTEL_INFO(dev)->gen < 4) {
12905                         DRM_DEBUG("unsupported pixel format: %s\n",
12906                                   drm_get_format_name(mode_cmd->pixel_format));
12907                         return -EINVAL;
12908                 }
12909                 break;
12910         case DRM_FORMAT_YUYV:
12911         case DRM_FORMAT_UYVY:
12912         case DRM_FORMAT_YVYU:
12913         case DRM_FORMAT_VYUY:
12914                 if (INTEL_INFO(dev)->gen < 5) {
12915                         DRM_DEBUG("unsupported pixel format: %s\n",
12916                                   drm_get_format_name(mode_cmd->pixel_format));
12917                         return -EINVAL;
12918                 }
12919                 break;
12920         default:
12921                 DRM_DEBUG("unsupported pixel format: %s\n",
12922                           drm_get_format_name(mode_cmd->pixel_format));
12923                 return -EINVAL;
12924         }
12925
12926         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12927         if (mode_cmd->offsets[0] != 0)
12928                 return -EINVAL;
12929
12930         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12931                                                mode_cmd->pixel_format,
12932                                                mode_cmd->modifier[0]);
12933         /* FIXME drm helper for size checks (especially planar formats)? */
12934         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12935                 return -EINVAL;
12936
12937         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12938         intel_fb->obj = obj;
12939         intel_fb->obj->framebuffer_references++;
12940
12941         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12942         if (ret) {
12943                 DRM_ERROR("framebuffer init failed %d\n", ret);
12944                 return ret;
12945         }
12946
12947         return 0;
12948 }
12949
12950 static struct drm_framebuffer *
12951 intel_user_framebuffer_create(struct drm_device *dev,
12952                               struct drm_file *filp,
12953                               struct drm_mode_fb_cmd2 *mode_cmd)
12954 {
12955         struct drm_i915_gem_object *obj;
12956
12957         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12958                                                 mode_cmd->handles[0]));
12959         if (&obj->base == NULL)
12960                 return ERR_PTR(-ENOENT);
12961
12962         return intel_framebuffer_create(dev, mode_cmd, obj);
12963 }
12964
12965 #ifndef CONFIG_DRM_I915_FBDEV
12966 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12967 {
12968 }
12969 #endif
12970
12971 static const struct drm_mode_config_funcs intel_mode_funcs = {
12972         .fb_create = intel_user_framebuffer_create,
12973         .output_poll_changed = intel_fbdev_output_poll_changed,
12974         .atomic_check = intel_atomic_check,
12975         .atomic_commit = intel_atomic_commit,
12976 };
12977
12978 /* Set up chip specific display functions */
12979 static void intel_init_display(struct drm_device *dev)
12980 {
12981         struct drm_i915_private *dev_priv = dev->dev_private;
12982
12983         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12984                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12985         else if (IS_CHERRYVIEW(dev))
12986                 dev_priv->display.find_dpll = chv_find_best_dpll;
12987         else if (IS_VALLEYVIEW(dev))
12988                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12989         else if (IS_PINEVIEW(dev))
12990                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12991         else
12992                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12993
12994         if (INTEL_INFO(dev)->gen >= 9) {
12995                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12996                 dev_priv->display.get_initial_plane_config =
12997                         skylake_get_initial_plane_config;
12998                 dev_priv->display.crtc_compute_clock =
12999                         haswell_crtc_compute_clock;
13000                 dev_priv->display.crtc_enable = haswell_crtc_enable;
13001                 dev_priv->display.crtc_disable = haswell_crtc_disable;
13002                 dev_priv->display.off = ironlake_crtc_off;
13003                 dev_priv->display.update_primary_plane =
13004                         skylake_update_primary_plane;
13005         } else if (HAS_DDI(dev)) {
13006                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13007                 dev_priv->display.get_initial_plane_config =
13008                         ironlake_get_initial_plane_config;
13009                 dev_priv->display.crtc_compute_clock =
13010                         haswell_crtc_compute_clock;
13011                 dev_priv->display.crtc_enable = haswell_crtc_enable;
13012                 dev_priv->display.crtc_disable = haswell_crtc_disable;
13013                 dev_priv->display.off = ironlake_crtc_off;
13014                 dev_priv->display.update_primary_plane =
13015                         ironlake_update_primary_plane;
13016         } else if (HAS_PCH_SPLIT(dev)) {
13017                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13018                 dev_priv->display.get_initial_plane_config =
13019                         ironlake_get_initial_plane_config;
13020                 dev_priv->display.crtc_compute_clock =
13021                         ironlake_crtc_compute_clock;
13022                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13023                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13024                 dev_priv->display.off = ironlake_crtc_off;
13025                 dev_priv->display.update_primary_plane =
13026                         ironlake_update_primary_plane;
13027         } else if (IS_VALLEYVIEW(dev)) {
13028                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13029                 dev_priv->display.get_initial_plane_config =
13030                         i9xx_get_initial_plane_config;
13031                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13032                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13033                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13034                 dev_priv->display.off = i9xx_crtc_off;
13035                 dev_priv->display.update_primary_plane =
13036                         i9xx_update_primary_plane;
13037         } else {
13038                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13039                 dev_priv->display.get_initial_plane_config =
13040                         i9xx_get_initial_plane_config;
13041                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13042                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13043                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13044                 dev_priv->display.off = i9xx_crtc_off;
13045                 dev_priv->display.update_primary_plane =
13046                         i9xx_update_primary_plane;
13047         }
13048
13049         /* Returns the core display clock speed */
13050         if (IS_VALLEYVIEW(dev))
13051                 dev_priv->display.get_display_clock_speed =
13052                         valleyview_get_display_clock_speed;
13053         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13054                 dev_priv->display.get_display_clock_speed =
13055                         i945_get_display_clock_speed;
13056         else if (IS_I915G(dev))
13057                 dev_priv->display.get_display_clock_speed =
13058                         i915_get_display_clock_speed;
13059         else if (IS_I945GM(dev) || IS_845G(dev))
13060                 dev_priv->display.get_display_clock_speed =
13061                         i9xx_misc_get_display_clock_speed;
13062         else if (IS_PINEVIEW(dev))
13063                 dev_priv->display.get_display_clock_speed =
13064                         pnv_get_display_clock_speed;
13065         else if (IS_I915GM(dev))
13066                 dev_priv->display.get_display_clock_speed =
13067                         i915gm_get_display_clock_speed;
13068         else if (IS_I865G(dev))
13069                 dev_priv->display.get_display_clock_speed =
13070                         i865_get_display_clock_speed;
13071         else if (IS_I85X(dev))
13072                 dev_priv->display.get_display_clock_speed =
13073                         i855_get_display_clock_speed;
13074         else /* 852, 830 */
13075                 dev_priv->display.get_display_clock_speed =
13076                         i830_get_display_clock_speed;
13077
13078         if (IS_GEN5(dev)) {
13079                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13080         } else if (IS_GEN6(dev)) {
13081                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13082         } else if (IS_IVYBRIDGE(dev)) {
13083                 /* FIXME: detect B0+ stepping and use auto training */
13084                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13085                 dev_priv->display.modeset_global_resources =
13086                         ivb_modeset_global_resources;
13087         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13088                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13089         } else if (IS_VALLEYVIEW(dev)) {
13090                 dev_priv->display.modeset_global_resources =
13091                         valleyview_modeset_global_resources;
13092         }
13093
13094         switch (INTEL_INFO(dev)->gen) {
13095         case 2:
13096                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13097                 break;
13098
13099         case 3:
13100                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13101                 break;
13102
13103         case 4:
13104         case 5:
13105                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13106                 break;
13107
13108         case 6:
13109                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13110                 break;
13111         case 7:
13112         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13113                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13114                 break;
13115         case 9:
13116                 /* Drop through - unsupported since execlist only. */
13117         default:
13118                 /* Default just returns -ENODEV to indicate unsupported */
13119                 dev_priv->display.queue_flip = intel_default_queue_flip;
13120         }
13121
13122         intel_panel_init_backlight_funcs(dev);
13123
13124         mutex_init(&dev_priv->pps_mutex);
13125 }
13126
13127 /*
13128  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13129  * resume, or other times.  This quirk makes sure that's the case for
13130  * affected systems.
13131  */
13132 static void quirk_pipea_force(struct drm_device *dev)
13133 {
13134         struct drm_i915_private *dev_priv = dev->dev_private;
13135
13136         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13137         DRM_INFO("applying pipe a force quirk\n");
13138 }
13139
13140 static void quirk_pipeb_force(struct drm_device *dev)
13141 {
13142         struct drm_i915_private *dev_priv = dev->dev_private;
13143
13144         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13145         DRM_INFO("applying pipe b force quirk\n");
13146 }
13147
13148 /*
13149  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13150  */
13151 static void quirk_ssc_force_disable(struct drm_device *dev)
13152 {
13153         struct drm_i915_private *dev_priv = dev->dev_private;
13154         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13155         DRM_INFO("applying lvds SSC disable quirk\n");
13156 }
13157
13158 /*
13159  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13160  * brightness value
13161  */
13162 static void quirk_invert_brightness(struct drm_device *dev)
13163 {
13164         struct drm_i915_private *dev_priv = dev->dev_private;
13165         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13166         DRM_INFO("applying inverted panel brightness quirk\n");
13167 }
13168
13169 /* Some VBT's incorrectly indicate no backlight is present */
13170 static void quirk_backlight_present(struct drm_device *dev)
13171 {
13172         struct drm_i915_private *dev_priv = dev->dev_private;
13173         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13174         DRM_INFO("applying backlight present quirk\n");
13175 }
13176
13177 struct intel_quirk {
13178         int device;
13179         int subsystem_vendor;
13180         int subsystem_device;
13181         void (*hook)(struct drm_device *dev);
13182 };
13183
13184 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13185 struct intel_dmi_quirk {
13186         void (*hook)(struct drm_device *dev);
13187         const struct dmi_system_id (*dmi_id_list)[];
13188 };
13189
13190 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13191 {
13192         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13193         return 1;
13194 }
13195
13196 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13197         {
13198                 .dmi_id_list = &(const struct dmi_system_id[]) {
13199                         {
13200                                 .callback = intel_dmi_reverse_brightness,
13201                                 .ident = "NCR Corporation",
13202                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13203                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
13204                                 },
13205                         },
13206                         { }  /* terminating entry */
13207                 },
13208                 .hook = quirk_invert_brightness,
13209         },
13210 };
13211
13212 static struct intel_quirk intel_quirks[] = {
13213         /* HP Mini needs pipe A force quirk (LP: #322104) */
13214         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13215
13216         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13217         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13218
13219         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13220         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13221
13222         /* 830 needs to leave pipe A & dpll A up */
13223         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13224
13225         /* 830 needs to leave pipe B & dpll B up */
13226         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13227
13228         /* Lenovo U160 cannot use SSC on LVDS */
13229         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13230
13231         /* Sony Vaio Y cannot use SSC on LVDS */
13232         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13233
13234         /* Acer Aspire 5734Z must invert backlight brightness */
13235         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13236
13237         /* Acer/eMachines G725 */
13238         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13239
13240         /* Acer/eMachines e725 */
13241         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13242
13243         /* Acer/Packard Bell NCL20 */
13244         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13245
13246         /* Acer Aspire 4736Z */
13247         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13248
13249         /* Acer Aspire 5336 */
13250         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13251
13252         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13253         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13254
13255         /* Acer C720 Chromebook (Core i3 4005U) */
13256         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13257
13258         /* Apple Macbook 2,1 (Core 2 T7400) */
13259         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13260
13261         /* Toshiba CB35 Chromebook (Celeron 2955U) */
13262         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13263
13264         /* HP Chromebook 14 (Celeron 2955U) */
13265         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13266
13267         /* Dell Chromebook 11 */
13268         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13269 };
13270
13271 static void intel_init_quirks(struct drm_device *dev)
13272 {
13273         struct pci_dev *d = dev->pdev;
13274         int i;
13275
13276         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13277                 struct intel_quirk *q = &intel_quirks[i];
13278
13279                 if (d->device == q->device &&
13280                     (d->subsystem_vendor == q->subsystem_vendor ||
13281                      q->subsystem_vendor == PCI_ANY_ID) &&
13282                     (d->subsystem_device == q->subsystem_device ||
13283                      q->subsystem_device == PCI_ANY_ID))
13284                         q->hook(dev);
13285         }
13286         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13287                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13288                         intel_dmi_quirks[i].hook(dev);
13289         }
13290 }
13291
13292 /* Disable the VGA plane that we never use */
13293 static void i915_disable_vga(struct drm_device *dev)
13294 {
13295         struct drm_i915_private *dev_priv = dev->dev_private;
13296         u8 sr1;
13297         u32 vga_reg = i915_vgacntrl_reg(dev);
13298
13299         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13300         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13301         outb(SR01, VGA_SR_INDEX);
13302         sr1 = inb(VGA_SR_DATA);
13303         outb(sr1 | 1<<5, VGA_SR_DATA);
13304         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13305         udelay(300);
13306
13307         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13308         POSTING_READ(vga_reg);
13309 }
13310
13311 void intel_modeset_init_hw(struct drm_device *dev)
13312 {
13313         intel_prepare_ddi(dev);
13314
13315         if (IS_VALLEYVIEW(dev))
13316                 vlv_update_cdclk(dev);
13317
13318         intel_init_clock_gating(dev);
13319
13320         intel_enable_gt_powersave(dev);
13321 }
13322
13323 void intel_modeset_init(struct drm_device *dev)
13324 {
13325         struct drm_i915_private *dev_priv = dev->dev_private;
13326         int sprite, ret;
13327         enum pipe pipe;
13328         struct intel_crtc *crtc;
13329
13330         drm_mode_config_init(dev);
13331
13332         dev->mode_config.min_width = 0;
13333         dev->mode_config.min_height = 0;
13334
13335         dev->mode_config.preferred_depth = 24;
13336         dev->mode_config.prefer_shadow = 1;
13337
13338         dev->mode_config.allow_fb_modifiers = true;
13339
13340         dev->mode_config.funcs = &intel_mode_funcs;
13341
13342         intel_init_quirks(dev);
13343
13344         intel_init_pm(dev);
13345
13346         if (INTEL_INFO(dev)->num_pipes == 0)
13347                 return;
13348
13349         intel_init_display(dev);
13350         intel_init_audio(dev);
13351
13352         if (IS_GEN2(dev)) {
13353                 dev->mode_config.max_width = 2048;
13354                 dev->mode_config.max_height = 2048;
13355         } else if (IS_GEN3(dev)) {
13356                 dev->mode_config.max_width = 4096;
13357                 dev->mode_config.max_height = 4096;
13358         } else {
13359                 dev->mode_config.max_width = 8192;
13360                 dev->mode_config.max_height = 8192;
13361         }
13362
13363         if (IS_845G(dev) || IS_I865G(dev)) {
13364                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13365                 dev->mode_config.cursor_height = 1023;
13366         } else if (IS_GEN2(dev)) {
13367                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13368                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13369         } else {
13370                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13371                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13372         }
13373
13374         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13375
13376         DRM_DEBUG_KMS("%d display pipe%s available.\n",
13377                       INTEL_INFO(dev)->num_pipes,
13378                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13379
13380         for_each_pipe(dev_priv, pipe) {
13381                 intel_crtc_init(dev, pipe);
13382                 for_each_sprite(dev_priv, pipe, sprite) {
13383                         ret = intel_plane_init(dev, pipe, sprite);
13384                         if (ret)
13385                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13386                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13387                 }
13388         }
13389
13390         intel_init_dpio(dev);
13391
13392         intel_shared_dpll_init(dev);
13393
13394         /* Just disable it once at startup */
13395         i915_disable_vga(dev);
13396         intel_setup_outputs(dev);
13397
13398         /* Just in case the BIOS is doing something questionable. */
13399         intel_fbc_disable(dev);
13400
13401         drm_modeset_lock_all(dev);
13402         intel_modeset_setup_hw_state(dev, false);
13403         drm_modeset_unlock_all(dev);
13404
13405         for_each_intel_crtc(dev, crtc) {
13406                 if (!crtc->active)
13407                         continue;
13408
13409                 /*
13410                  * Note that reserving the BIOS fb up front prevents us
13411                  * from stuffing other stolen allocations like the ring
13412                  * on top.  This prevents some ugliness at boot time, and
13413                  * can even allow for smooth boot transitions if the BIOS
13414                  * fb is large enough for the active pipe configuration.
13415                  */
13416                 if (dev_priv->display.get_initial_plane_config) {
13417                         dev_priv->display.get_initial_plane_config(crtc,
13418                                                            &crtc->plane_config);
13419                         /*
13420                          * If the fb is shared between multiple heads, we'll
13421                          * just get the first one.
13422                          */
13423                         intel_find_plane_obj(crtc, &crtc->plane_config);
13424                 }
13425         }
13426 }
13427
13428 static void intel_enable_pipe_a(struct drm_device *dev)
13429 {
13430         struct intel_connector *connector;
13431         struct drm_connector *crt = NULL;
13432         struct intel_load_detect_pipe load_detect_temp;
13433         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13434
13435         /* We can't just switch on the pipe A, we need to set things up with a
13436          * proper mode and output configuration. As a gross hack, enable pipe A
13437          * by enabling the load detect pipe once. */
13438         for_each_intel_connector(dev, connector) {
13439                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13440                         crt = &connector->base;
13441                         break;
13442                 }
13443         }
13444
13445         if (!crt)
13446                 return;
13447
13448         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13449                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13450 }
13451
13452 static bool
13453 intel_check_plane_mapping(struct intel_crtc *crtc)
13454 {
13455         struct drm_device *dev = crtc->base.dev;
13456         struct drm_i915_private *dev_priv = dev->dev_private;
13457         u32 reg, val;
13458
13459         if (INTEL_INFO(dev)->num_pipes == 1)
13460                 return true;
13461
13462         reg = DSPCNTR(!crtc->plane);
13463         val = I915_READ(reg);
13464
13465         if ((val & DISPLAY_PLANE_ENABLE) &&
13466             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13467                 return false;
13468
13469         return true;
13470 }
13471
13472 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13473 {
13474         struct drm_device *dev = crtc->base.dev;
13475         struct drm_i915_private *dev_priv = dev->dev_private;
13476         u32 reg;
13477
13478         /* Clear any frame start delays used for debugging left by the BIOS */
13479         reg = PIPECONF(crtc->config->cpu_transcoder);
13480         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13481
13482         /* restore vblank interrupts to correct state */
13483         drm_crtc_vblank_reset(&crtc->base);
13484         if (crtc->active) {
13485                 update_scanline_offset(crtc);
13486                 drm_crtc_vblank_on(&crtc->base);
13487         }
13488
13489         /* We need to sanitize the plane -> pipe mapping first because this will
13490          * disable the crtc (and hence change the state) if it is wrong. Note
13491          * that gen4+ has a fixed plane -> pipe mapping.  */
13492         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13493                 struct intel_connector *connector;
13494                 bool plane;
13495
13496                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13497                               crtc->base.base.id);
13498
13499                 /* Pipe has the wrong plane attached and the plane is active.
13500                  * Temporarily change the plane mapping and disable everything
13501                  * ...  */
13502                 plane = crtc->plane;
13503                 crtc->plane = !plane;
13504                 crtc->primary_enabled = true;
13505                 dev_priv->display.crtc_disable(&crtc->base);
13506                 crtc->plane = plane;
13507
13508                 /* ... and break all links. */
13509                 for_each_intel_connector(dev, connector) {
13510                         if (connector->encoder->base.crtc != &crtc->base)
13511                                 continue;
13512
13513                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13514                         connector->base.encoder = NULL;
13515                 }
13516                 /* multiple connectors may have the same encoder:
13517                  *  handle them and break crtc link separately */
13518                 for_each_intel_connector(dev, connector)
13519                         if (connector->encoder->base.crtc == &crtc->base) {
13520                                 connector->encoder->base.crtc = NULL;
13521                                 connector->encoder->connectors_active = false;
13522                         }
13523
13524                 WARN_ON(crtc->active);
13525                 crtc->base.state->enable = false;
13526                 crtc->base.enabled = false;
13527         }
13528
13529         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13530             crtc->pipe == PIPE_A && !crtc->active) {
13531                 /* BIOS forgot to enable pipe A, this mostly happens after
13532                  * resume. Force-enable the pipe to fix this, the update_dpms
13533                  * call below we restore the pipe to the right state, but leave
13534                  * the required bits on. */
13535                 intel_enable_pipe_a(dev);
13536         }
13537
13538         /* Adjust the state of the output pipe according to whether we
13539          * have active connectors/encoders. */
13540         intel_crtc_update_dpms(&crtc->base);
13541
13542         if (crtc->active != crtc->base.state->enable) {
13543                 struct intel_encoder *encoder;
13544
13545                 /* This can happen either due to bugs in the get_hw_state
13546                  * functions or because the pipe is force-enabled due to the
13547                  * pipe A quirk. */
13548                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13549                               crtc->base.base.id,
13550                               crtc->base.state->enable ? "enabled" : "disabled",
13551                               crtc->active ? "enabled" : "disabled");
13552
13553                 crtc->base.state->enable = crtc->active;
13554                 crtc->base.enabled = crtc->active;
13555
13556                 /* Because we only establish the connector -> encoder ->
13557                  * crtc links if something is active, this means the
13558                  * crtc is now deactivated. Break the links. connector
13559                  * -> encoder links are only establish when things are
13560                  *  actually up, hence no need to break them. */
13561                 WARN_ON(crtc->active);
13562
13563                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13564                         WARN_ON(encoder->connectors_active);
13565                         encoder->base.crtc = NULL;
13566                 }
13567         }
13568
13569         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13570                 /*
13571                  * We start out with underrun reporting disabled to avoid races.
13572                  * For correct bookkeeping mark this on active crtcs.
13573                  *
13574                  * Also on gmch platforms we dont have any hardware bits to
13575                  * disable the underrun reporting. Which means we need to start
13576                  * out with underrun reporting disabled also on inactive pipes,
13577                  * since otherwise we'll complain about the garbage we read when
13578                  * e.g. coming up after runtime pm.
13579                  *
13580                  * No protection against concurrent access is required - at
13581                  * worst a fifo underrun happens which also sets this to false.
13582                  */
13583                 crtc->cpu_fifo_underrun_disabled = true;
13584                 crtc->pch_fifo_underrun_disabled = true;
13585         }
13586 }
13587
13588 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13589 {
13590         struct intel_connector *connector;
13591         struct drm_device *dev = encoder->base.dev;
13592
13593         /* We need to check both for a crtc link (meaning that the
13594          * encoder is active and trying to read from a pipe) and the
13595          * pipe itself being active. */
13596         bool has_active_crtc = encoder->base.crtc &&
13597                 to_intel_crtc(encoder->base.crtc)->active;
13598
13599         if (encoder->connectors_active && !has_active_crtc) {
13600                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13601                               encoder->base.base.id,
13602                               encoder->base.name);
13603
13604                 /* Connector is active, but has no active pipe. This is
13605                  * fallout from our resume register restoring. Disable
13606                  * the encoder manually again. */
13607                 if (encoder->base.crtc) {
13608                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13609                                       encoder->base.base.id,
13610                                       encoder->base.name);
13611                         encoder->disable(encoder);
13612                         if (encoder->post_disable)
13613                                 encoder->post_disable(encoder);
13614                 }
13615                 encoder->base.crtc = NULL;
13616                 encoder->connectors_active = false;
13617
13618                 /* Inconsistent output/port/pipe state happens presumably due to
13619                  * a bug in one of the get_hw_state functions. Or someplace else
13620                  * in our code, like the register restore mess on resume. Clamp
13621                  * things to off as a safer default. */
13622                 for_each_intel_connector(dev, connector) {
13623                         if (connector->encoder != encoder)
13624                                 continue;
13625                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13626                         connector->base.encoder = NULL;
13627                 }
13628         }
13629         /* Enabled encoders without active connectors will be fixed in
13630          * the crtc fixup. */
13631 }
13632
13633 void i915_redisable_vga_power_on(struct drm_device *dev)
13634 {
13635         struct drm_i915_private *dev_priv = dev->dev_private;
13636         u32 vga_reg = i915_vgacntrl_reg(dev);
13637
13638         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13639                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13640                 i915_disable_vga(dev);
13641         }
13642 }
13643
13644 void i915_redisable_vga(struct drm_device *dev)
13645 {
13646         struct drm_i915_private *dev_priv = dev->dev_private;
13647
13648         /* This function can be called both from intel_modeset_setup_hw_state or
13649          * at a very early point in our resume sequence, where the power well
13650          * structures are not yet restored. Since this function is at a very
13651          * paranoid "someone might have enabled VGA while we were not looking"
13652          * level, just check if the power well is enabled instead of trying to
13653          * follow the "don't touch the power well if we don't need it" policy
13654          * the rest of the driver uses. */
13655         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13656                 return;
13657
13658         i915_redisable_vga_power_on(dev);
13659 }
13660
13661 static bool primary_get_hw_state(struct intel_crtc *crtc)
13662 {
13663         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13664
13665         if (!crtc->active)
13666                 return false;
13667
13668         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13669 }
13670
13671 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13672 {
13673         struct drm_i915_private *dev_priv = dev->dev_private;
13674         enum pipe pipe;
13675         struct intel_crtc *crtc;
13676         struct intel_encoder *encoder;
13677         struct intel_connector *connector;
13678         int i;
13679
13680         for_each_intel_crtc(dev, crtc) {
13681                 memset(crtc->config, 0, sizeof(*crtc->config));
13682
13683                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13684
13685                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13686                                                                  crtc->config);
13687
13688                 crtc->base.state->enable = crtc->active;
13689                 crtc->base.enabled = crtc->active;
13690                 crtc->primary_enabled = primary_get_hw_state(crtc);
13691
13692                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13693                               crtc->base.base.id,
13694                               crtc->active ? "enabled" : "disabled");
13695         }
13696
13697         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13698                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13699
13700                 pll->on = pll->get_hw_state(dev_priv, pll,
13701                                             &pll->config.hw_state);
13702                 pll->active = 0;
13703                 pll->config.crtc_mask = 0;
13704                 for_each_intel_crtc(dev, crtc) {
13705                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13706                                 pll->active++;
13707                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13708                         }
13709                 }
13710
13711                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13712                               pll->name, pll->config.crtc_mask, pll->on);
13713
13714                 if (pll->config.crtc_mask)
13715                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13716         }
13717
13718         for_each_intel_encoder(dev, encoder) {
13719                 pipe = 0;
13720
13721                 if (encoder->get_hw_state(encoder, &pipe)) {
13722                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13723                         encoder->base.crtc = &crtc->base;
13724                         encoder->get_config(encoder, crtc->config);
13725                 } else {
13726                         encoder->base.crtc = NULL;
13727                 }
13728
13729                 encoder->connectors_active = false;
13730                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13731                               encoder->base.base.id,
13732                               encoder->base.name,
13733                               encoder->base.crtc ? "enabled" : "disabled",
13734                               pipe_name(pipe));
13735         }
13736
13737         for_each_intel_connector(dev, connector) {
13738                 if (connector->get_hw_state(connector)) {
13739                         connector->base.dpms = DRM_MODE_DPMS_ON;
13740                         connector->encoder->connectors_active = true;
13741                         connector->base.encoder = &connector->encoder->base;
13742                 } else {
13743                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13744                         connector->base.encoder = NULL;
13745                 }
13746                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13747                               connector->base.base.id,
13748                               connector->base.name,
13749                               connector->base.encoder ? "enabled" : "disabled");
13750         }
13751 }
13752
13753 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13754  * and i915 state tracking structures. */
13755 void intel_modeset_setup_hw_state(struct drm_device *dev,
13756                                   bool force_restore)
13757 {
13758         struct drm_i915_private *dev_priv = dev->dev_private;
13759         enum pipe pipe;
13760         struct intel_crtc *crtc;
13761         struct intel_encoder *encoder;
13762         int i;
13763
13764         intel_modeset_readout_hw_state(dev);
13765
13766         /*
13767          * Now that we have the config, copy it to each CRTC struct
13768          * Note that this could go away if we move to using crtc_config
13769          * checking everywhere.
13770          */
13771         for_each_intel_crtc(dev, crtc) {
13772                 if (crtc->active && i915.fastboot) {
13773                         intel_mode_from_pipe_config(&crtc->base.mode,
13774                                                     crtc->config);
13775                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13776                                       crtc->base.base.id);
13777                         drm_mode_debug_printmodeline(&crtc->base.mode);
13778                 }
13779         }
13780
13781         /* HW state is read out, now we need to sanitize this mess. */
13782         for_each_intel_encoder(dev, encoder) {
13783                 intel_sanitize_encoder(encoder);
13784         }
13785
13786         for_each_pipe(dev_priv, pipe) {
13787                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13788                 intel_sanitize_crtc(crtc);
13789                 intel_dump_pipe_config(crtc, crtc->config,
13790                                        "[setup_hw_state]");
13791         }
13792
13793         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13794                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13795
13796                 if (!pll->on || pll->active)
13797                         continue;
13798
13799                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13800
13801                 pll->disable(dev_priv, pll);
13802                 pll->on = false;
13803         }
13804
13805         if (IS_GEN9(dev))
13806                 skl_wm_get_hw_state(dev);
13807         else if (HAS_PCH_SPLIT(dev))
13808                 ilk_wm_get_hw_state(dev);
13809
13810         if (force_restore) {
13811                 i915_redisable_vga(dev);
13812
13813                 /*
13814                  * We need to use raw interfaces for restoring state to avoid
13815                  * checking (bogus) intermediate states.
13816                  */
13817                 for_each_pipe(dev_priv, pipe) {
13818                         struct drm_crtc *crtc =
13819                                 dev_priv->pipe_to_crtc_mapping[pipe];
13820
13821                         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13822                                        crtc->primary->fb);
13823                 }
13824         } else {
13825                 intel_modeset_update_staged_output_state(dev);
13826         }
13827
13828         intel_modeset_check_state(dev);
13829 }
13830
13831 void intel_modeset_gem_init(struct drm_device *dev)
13832 {
13833         struct drm_i915_private *dev_priv = dev->dev_private;
13834         struct drm_crtc *c;
13835         struct drm_i915_gem_object *obj;
13836
13837         mutex_lock(&dev->struct_mutex);
13838         intel_init_gt_powersave(dev);
13839         mutex_unlock(&dev->struct_mutex);
13840
13841         /*
13842          * There may be no VBT; and if the BIOS enabled SSC we can
13843          * just keep using it to avoid unnecessary flicker.  Whereas if the
13844          * BIOS isn't using it, don't assume it will work even if the VBT
13845          * indicates as much.
13846          */
13847         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13848                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13849                                                 DREF_SSC1_ENABLE);
13850
13851         intel_modeset_init_hw(dev);
13852
13853         intel_setup_overlay(dev);
13854
13855         /*
13856          * Make sure any fbs we allocated at startup are properly
13857          * pinned & fenced.  When we do the allocation it's too early
13858          * for this.
13859          */
13860         mutex_lock(&dev->struct_mutex);
13861         for_each_crtc(dev, c) {
13862                 obj = intel_fb_obj(c->primary->fb);
13863                 if (obj == NULL)
13864                         continue;
13865
13866                 if (intel_pin_and_fence_fb_obj(c->primary,
13867                                                c->primary->fb,
13868                                                NULL)) {
13869                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13870                                   to_intel_crtc(c)->pipe);
13871                         drm_framebuffer_unreference(c->primary->fb);
13872                         c->primary->fb = NULL;
13873                         update_state_fb(c->primary);
13874                 }
13875         }
13876         mutex_unlock(&dev->struct_mutex);
13877
13878         intel_backlight_register(dev);
13879 }
13880
13881 void intel_connector_unregister(struct intel_connector *intel_connector)
13882 {
13883         struct drm_connector *connector = &intel_connector->base;
13884
13885         intel_panel_destroy_backlight(connector);
13886         drm_connector_unregister(connector);
13887 }
13888
13889 void intel_modeset_cleanup(struct drm_device *dev)
13890 {
13891         struct drm_i915_private *dev_priv = dev->dev_private;
13892         struct drm_connector *connector;
13893
13894         intel_disable_gt_powersave(dev);
13895
13896         intel_backlight_unregister(dev);
13897
13898         /*
13899          * Interrupts and polling as the first thing to avoid creating havoc.
13900          * Too much stuff here (turning of connectors, ...) would
13901          * experience fancy races otherwise.
13902          */
13903         intel_irq_uninstall(dev_priv);
13904
13905         /*
13906          * Due to the hpd irq storm handling the hotplug work can re-arm the
13907          * poll handlers. Hence disable polling after hpd handling is shut down.
13908          */
13909         drm_kms_helper_poll_fini(dev);
13910
13911         mutex_lock(&dev->struct_mutex);
13912
13913         intel_unregister_dsm_handler();
13914
13915         intel_fbc_disable(dev);
13916
13917         mutex_unlock(&dev->struct_mutex);
13918
13919         /* flush any delayed tasks or pending work */
13920         flush_scheduled_work();
13921
13922         /* destroy the backlight and sysfs files before encoders/connectors */
13923         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13924                 struct intel_connector *intel_connector;
13925
13926                 intel_connector = to_intel_connector(connector);
13927                 intel_connector->unregister(intel_connector);
13928         }
13929
13930         drm_mode_config_cleanup(dev);
13931
13932         intel_cleanup_overlay(dev);
13933
13934         mutex_lock(&dev->struct_mutex);
13935         intel_cleanup_gt_powersave(dev);
13936         mutex_unlock(&dev->struct_mutex);
13937 }
13938
13939 /*
13940  * Return which encoder is currently attached for connector.
13941  */
13942 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13943 {
13944         return &intel_attached_encoder(connector)->base;
13945 }
13946
13947 void intel_connector_attach_encoder(struct intel_connector *connector,
13948                                     struct intel_encoder *encoder)
13949 {
13950         connector->encoder = encoder;
13951         drm_mode_connector_attach_encoder(&connector->base,
13952                                           &encoder->base);
13953 }
13954
13955 /*
13956  * set vga decode state - true == enable VGA decode
13957  */
13958 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13959 {
13960         struct drm_i915_private *dev_priv = dev->dev_private;
13961         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13962         u16 gmch_ctrl;
13963
13964         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13965                 DRM_ERROR("failed to read control word\n");
13966                 return -EIO;
13967         }
13968
13969         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13970                 return 0;
13971
13972         if (state)
13973                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13974         else
13975                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13976
13977         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13978                 DRM_ERROR("failed to write control word\n");
13979                 return -EIO;
13980         }
13981
13982         return 0;
13983 }
13984
13985 struct intel_display_error_state {
13986
13987         u32 power_well_driver;
13988
13989         int num_transcoders;
13990
13991         struct intel_cursor_error_state {
13992                 u32 control;
13993                 u32 position;
13994                 u32 base;
13995                 u32 size;
13996         } cursor[I915_MAX_PIPES];
13997
13998         struct intel_pipe_error_state {
13999                 bool power_domain_on;
14000                 u32 source;
14001                 u32 stat;
14002         } pipe[I915_MAX_PIPES];
14003
14004         struct intel_plane_error_state {
14005                 u32 control;
14006                 u32 stride;
14007                 u32 size;
14008                 u32 pos;
14009                 u32 addr;
14010                 u32 surface;
14011                 u32 tile_offset;
14012         } plane[I915_MAX_PIPES];
14013
14014         struct intel_transcoder_error_state {
14015                 bool power_domain_on;
14016                 enum transcoder cpu_transcoder;
14017
14018                 u32 conf;
14019
14020                 u32 htotal;
14021                 u32 hblank;
14022                 u32 hsync;
14023                 u32 vtotal;
14024                 u32 vblank;
14025                 u32 vsync;
14026         } transcoder[4];
14027 };
14028
14029 struct intel_display_error_state *
14030 intel_display_capture_error_state(struct drm_device *dev)
14031 {
14032         struct drm_i915_private *dev_priv = dev->dev_private;
14033         struct intel_display_error_state *error;
14034         int transcoders[] = {
14035                 TRANSCODER_A,
14036                 TRANSCODER_B,
14037                 TRANSCODER_C,
14038                 TRANSCODER_EDP,
14039         };
14040         int i;
14041
14042         if (INTEL_INFO(dev)->num_pipes == 0)
14043                 return NULL;
14044
14045         error = kzalloc(sizeof(*error), GFP_ATOMIC);
14046         if (error == NULL)
14047                 return NULL;
14048
14049         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14050                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14051
14052         for_each_pipe(dev_priv, i) {
14053                 error->pipe[i].power_domain_on =
14054                         __intel_display_power_is_enabled(dev_priv,
14055                                                          POWER_DOMAIN_PIPE(i));
14056                 if (!error->pipe[i].power_domain_on)
14057                         continue;
14058
14059                 error->cursor[i].control = I915_READ(CURCNTR(i));
14060                 error->cursor[i].position = I915_READ(CURPOS(i));
14061                 error->cursor[i].base = I915_READ(CURBASE(i));
14062
14063                 error->plane[i].control = I915_READ(DSPCNTR(i));
14064                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14065                 if (INTEL_INFO(dev)->gen <= 3) {
14066                         error->plane[i].size = I915_READ(DSPSIZE(i));
14067                         error->plane[i].pos = I915_READ(DSPPOS(i));
14068                 }
14069                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14070                         error->plane[i].addr = I915_READ(DSPADDR(i));
14071                 if (INTEL_INFO(dev)->gen >= 4) {
14072                         error->plane[i].surface = I915_READ(DSPSURF(i));
14073                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14074                 }
14075
14076                 error->pipe[i].source = I915_READ(PIPESRC(i));
14077
14078                 if (HAS_GMCH_DISPLAY(dev))
14079                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
14080         }
14081
14082         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14083         if (HAS_DDI(dev_priv->dev))
14084                 error->num_transcoders++; /* Account for eDP. */
14085
14086         for (i = 0; i < error->num_transcoders; i++) {
14087                 enum transcoder cpu_transcoder = transcoders[i];
14088
14089                 error->transcoder[i].power_domain_on =
14090                         __intel_display_power_is_enabled(dev_priv,
14091                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14092                 if (!error->transcoder[i].power_domain_on)
14093                         continue;
14094
14095                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14096
14097                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14098                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14099                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14100                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14101                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14102                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14103                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14104         }
14105
14106         return error;
14107 }
14108
14109 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14110
14111 void
14112 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14113                                 struct drm_device *dev,
14114                                 struct intel_display_error_state *error)
14115 {
14116         struct drm_i915_private *dev_priv = dev->dev_private;
14117         int i;
14118
14119         if (!error)
14120                 return;
14121
14122         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14123         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14124                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14125                            error->power_well_driver);
14126         for_each_pipe(dev_priv, i) {
14127                 err_printf(m, "Pipe [%d]:\n", i);
14128                 err_printf(m, "  Power: %s\n",
14129                            error->pipe[i].power_domain_on ? "on" : "off");
14130                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
14131                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
14132
14133                 err_printf(m, "Plane [%d]:\n", i);
14134                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
14135                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
14136                 if (INTEL_INFO(dev)->gen <= 3) {
14137                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
14138                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
14139                 }
14140                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14141                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
14142                 if (INTEL_INFO(dev)->gen >= 4) {
14143                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
14144                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
14145                 }
14146
14147                 err_printf(m, "Cursor [%d]:\n", i);
14148                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
14149                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
14150                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
14151         }
14152
14153         for (i = 0; i < error->num_transcoders; i++) {
14154                 err_printf(m, "CPU transcoder: %c\n",
14155                            transcoder_name(error->transcoder[i].cpu_transcoder));
14156                 err_printf(m, "  Power: %s\n",
14157                            error->transcoder[i].power_domain_on ? "on" : "off");
14158                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
14159                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
14160                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
14161                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
14162                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
14163                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
14164                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
14165         }
14166 }
14167
14168 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14169 {
14170         struct intel_crtc *crtc;
14171
14172         for_each_intel_crtc(dev, crtc) {
14173                 struct intel_unpin_work *work;
14174
14175                 spin_lock_irq(&dev->event_lock);
14176
14177                 work = crtc->unpin_work;
14178
14179                 if (work && work->event &&
14180                     work->event->base.file_priv == file) {
14181                         kfree(work->event);
14182                         work->event = NULL;
14183                 }
14184
14185                 spin_unlock_irq(&dev->event_lock);
14186         }
14187 }