2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
106 static inline u32 /* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device *dev)
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
116 static const intel_limit_t intel_limits_i8xx_dvo = {
117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
127 .find_pll = intel_find_best_PLL,
130 static const intel_limit_t intel_limits_i8xx_lvds = {
131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
141 .find_pll = intel_find_best_PLL,
144 static const intel_limit_t intel_limits_i9xx_sdvo = {
145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
155 .find_pll = intel_find_best_PLL,
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 .find_pll = intel_find_best_PLL,
173 static const intel_limit_t intel_limits_g4x_sdvo = {
174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
186 .find_pll = intel_g4x_find_best_PLL,
189 static const intel_limit_t intel_limits_g4x_hdmi = {
190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
200 .find_pll = intel_g4x_find_best_PLL,
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
215 .find_pll = intel_g4x_find_best_PLL,
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
230 .find_pll = intel_g4x_find_best_PLL,
233 static const intel_limit_t intel_limits_g4x_display_port = {
234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 10, .p2_fast = 10 },
244 .find_pll = intel_find_pll_g4x_dp,
247 static const intel_limit_t intel_limits_pineview_sdvo = {
248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
260 .find_pll = intel_find_best_PLL,
263 static const intel_limit_t intel_limits_pineview_lvds = {
264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
274 .find_pll = intel_find_best_PLL,
277 /* Ironlake / Sandybridge
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
282 static const intel_limit_t intel_limits_ironlake_dac = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
293 .find_pll = intel_g4x_find_best_PLL,
296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
307 .find_pll = intel_g4x_find_best_PLL,
310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
321 .find_pll = intel_g4x_find_best_PLL,
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
333 .p1 = { .min = 2, .max = 8 },
334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
336 .find_pll = intel_g4x_find_best_PLL,
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
347 .p1 = { .min = 2, .max = 6 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 .find_pll = intel_g4x_find_best_PLL,
353 static const intel_limit_t intel_limits_ironlake_display_port = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
363 .p2_slow = 10, .p2_fast = 10 },
364 .find_pll = intel_find_pll_ironlake_dp,
367 static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
381 static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 4000000, .max = 5994000},
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
395 static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 25000, .max = 270000 },
397 .vco = { .min = 4000000, .max = 6000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 22, .max = 450 },
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
427 val = I915_READ(DPIO_DATA);
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
456 static void vlv_init_dpio(struct drm_device *dev)
458 struct drm_i915_private *dev_priv = dev->dev_private;
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
473 static const struct dmi_system_id intel_dual_link_lvds[] = {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
482 { } /* terminating entry */
485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
494 if (dmi_check_system(intel_dual_link_lvds))
497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
505 val = I915_READ(reg);
506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
518 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522 /* LVDS dual channel */
523 if (refclk == 100000)
524 limit = &intel_limits_ironlake_dual_lvds_100m;
526 limit = &intel_limits_ironlake_dual_lvds;
528 if (refclk == 100000)
529 limit = &intel_limits_ironlake_single_lvds_100m;
531 limit = &intel_limits_ironlake_single_lvds;
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
535 limit = &intel_limits_ironlake_display_port;
537 limit = &intel_limits_ironlake_dac;
542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549 if (is_dual_link_lvds(dev_priv, LVDS))
550 /* LVDS with dual channel */
551 limit = &intel_limits_g4x_dual_channel_lvds;
553 /* LVDS with dual channel */
554 limit = &intel_limits_g4x_single_channel_lvds;
555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
557 limit = &intel_limits_g4x_hdmi;
558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559 limit = &intel_limits_g4x_sdvo;
560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561 limit = &intel_limits_g4x_display_port;
562 } else /* The option is for other outputs */
563 limit = &intel_limits_i9xx_sdvo;
568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
573 if (HAS_PCH_SPLIT(dev))
574 limit = intel_ironlake_limit(crtc, refclk);
575 else if (IS_G4X(dev)) {
576 limit = intel_g4x_limit(crtc);
577 } else if (IS_PINEVIEW(dev)) {
578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_pineview_lvds;
581 limit = &intel_limits_pineview_sdvo;
582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
588 limit = &intel_limits_vlv_dp;
589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
593 limit = &intel_limits_i9xx_sdvo;
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
596 limit = &intel_limits_i8xx_lvds;
598 limit = &intel_limits_i8xx_dvo;
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk, intel_clock_t *clock)
606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
625 * Returns whether any output on the specified pipe is of the specified type
627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
629 struct drm_device *dev = crtc->dev;
630 struct intel_encoder *encoder;
632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->p < limit->p.min || limit->p.max < clock->p)
652 INTELPllInvalid("p out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock->m < limit->m.min || limit->m.max < clock->m)
660 INTELPllInvalid("m out of range\n");
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669 INTELPllInvalid("dot out of range\n");
675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
686 (I915_READ(LVDS)) != 0) {
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
693 if (is_dual_link_lvds(dev_priv, LVDS))
694 clock.p2 = limit->p2.p2_fast;
696 clock.p2 = limit->p2.p2_slow;
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
701 clock.p2 = limit->p2.p2_fast;
704 memset(best_clock, 0, sizeof(*best_clock));
706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
719 intel_clock(dev, refclk, &clock);
720 if (!intel_PLL_is_valid(dev, limit,
724 clock.p != match_clock->p)
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
737 return (err != target);
741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
757 if (HAS_PCH_SPLIT(dev))
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
763 clock.p2 = limit->p2.p2_fast;
765 clock.p2 = limit->p2.p2_slow;
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
770 clock.p2 = limit->p2.p2_fast;
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
786 intel_clock(dev, refclk, &clock);
787 if (!intel_PLL_is_valid(dev, limit,
791 clock.p != match_clock->p)
794 this_err = abs(clock.dot - target);
795 if (this_err < err_most) {
809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
813 struct drm_device *dev = crtc->dev;
816 if (target < 200000) {
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
841 if (target < 200000) {
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
873 dotclk = target * 1000;
876 fastclk = dotclk / (2*100);
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
904 if (absppm < bestppm - 10) {
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
935 frame = I915_READ(frame_reg);
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
942 * intel_wait_for_vblank - wait for vblank on a given pipe
944 * @pipe: pipe to wait for
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 int pipestat_reg = PIPESTAT(pipe);
954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
979 DRM_DEBUG_KMS("vblank wait timed out\n");
983 * intel_wait_for_pipe_off - wait for pipe to turn off
985 * @pipe: pipe to wait for
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
992 * wait for the pipe register state bit to turn off
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1003 if (INTEL_INFO(dev)->gen >= 4) {
1004 int reg = PIPECONF(pipe);
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1009 WARN(1, "pipe_off wait timed out\n");
1011 u32 last_line, line_mask;
1012 int reg = PIPEDSL(pipe);
1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1016 line_mask = DSL_LINEMASK_GEN2;
1018 line_mask = DSL_LINEMASK_GEN3;
1020 /* Wait for the display line to settle */
1022 last_line = I915_READ(reg) & line_mask;
1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 WARN(1, "pipe_off wait timed out\n");
1031 static const char *state_string(bool enabled)
1033 return enabled ? "on" : "off";
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1183 int pp_reg, lvds_reg;
1185 enum pipe panel_pipe = PIPE_A;
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1192 pp_reg = PP_CONTROL;
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe), state_string(state), state_string(cur_state));
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
1309 if ((val & DP_PORT_EN) == 0)
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1327 if ((val & PORT_ENABLE) == 0)
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1343 if ((val & LVDS_PORT_EN) == 0)
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372 enum pipe pipe, int reg, u32 port_sel)
1374 u32 val = I915_READ(reg);
1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg, pipe_name(pipe));
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380 && (val & DP_PIPEB_SELECT),
1381 "IBX PCH dp port still using transcoder B\n");
1384 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, int reg)
1387 u32 val = I915_READ(reg);
1388 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390 reg, pipe_name(pipe));
1392 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393 && (val & SDVO_PIPE_B_SELECT),
1394 "IBX PCH hdmi port still using transcoder B\n");
1397 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1408 val = I915_READ(reg);
1409 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410 "PCH VGA enabled on transcoder %c, should be disabled\n",
1414 val = I915_READ(reg);
1415 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1416 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1425 * intel_enable_pll - enable a PLL
1426 * @dev_priv: i915 private structure
1427 * @pipe: pipe PLL to enable
1429 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1430 * make sure the PLL reg is writable first though, since the panel write
1431 * protect mechanism may be enabled.
1433 * Note! This is for pre-ILK only.
1435 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1437 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1442 /* No really, not for ILK+ */
1443 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1445 /* PLL is protected by panel, make sure we can write it */
1446 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447 assert_panel_unlocked(dev_priv, pipe);
1450 val = I915_READ(reg);
1451 val |= DPLL_VCO_ENABLE;
1453 /* We do this three times for luck */
1454 I915_WRITE(reg, val);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg, val);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1462 udelay(150); /* wait for warmup */
1466 * intel_disable_pll - disable a PLL
1467 * @dev_priv: i915 private structure
1468 * @pipe: pipe PLL to disable
1470 * Disable the PLL for @pipe, making sure the pipe is off first.
1472 * Note! This is for pre-ILK only.
1474 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1479 /* Don't disable pipe A or pipe A PLLs if needed */
1480 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1483 /* Make sure the pipe isn't still relying on us */
1484 assert_pipe_disabled(dev_priv, pipe);
1487 val = I915_READ(reg);
1488 val &= ~DPLL_VCO_ENABLE;
1489 I915_WRITE(reg, val);
1495 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1497 unsigned long flags;
1499 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1500 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1502 DRM_ERROR("timeout waiting for SBI to become ready\n");
1506 I915_WRITE(SBI_ADDR,
1508 I915_WRITE(SBI_DATA,
1510 I915_WRITE(SBI_CTL_STAT,
1514 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1516 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1521 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1525 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1527 unsigned long flags;
1530 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1531 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1533 DRM_ERROR("timeout waiting for SBI to become ready\n");
1537 I915_WRITE(SBI_ADDR,
1539 I915_WRITE(SBI_CTL_STAT,
1543 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1545 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1549 value = I915_READ(SBI_DATA);
1552 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1557 * intel_enable_pch_pll - enable PCH PLL
1558 * @dev_priv: i915 private structure
1559 * @pipe: pipe PLL to enable
1561 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1562 * drives the transcoder clock.
1564 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1566 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1567 struct intel_pch_pll *pll;
1571 /* PCH PLLs only available on ILK, SNB and IVB */
1572 BUG_ON(dev_priv->info->gen < 5);
1573 pll = intel_crtc->pch_pll;
1577 if (WARN_ON(pll->refcount == 0))
1580 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581 pll->pll_reg, pll->active, pll->on,
1582 intel_crtc->base.base.id);
1584 /* PCH refclock must be enabled first */
1585 assert_pch_refclk_enabled(dev_priv);
1587 if (pll->active++ && pll->on) {
1588 assert_pch_pll_enabled(dev_priv, pll, NULL);
1592 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1595 val = I915_READ(reg);
1596 val |= DPLL_VCO_ENABLE;
1597 I915_WRITE(reg, val);
1604 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1606 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1607 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1611 /* PCH only available on ILK+ */
1612 BUG_ON(dev_priv->info->gen < 5);
1616 if (WARN_ON(pll->refcount == 0))
1619 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620 pll->pll_reg, pll->active, pll->on,
1621 intel_crtc->base.base.id);
1623 if (WARN_ON(pll->active == 0)) {
1624 assert_pch_pll_disabled(dev_priv, pll, NULL);
1628 if (--pll->active) {
1629 assert_pch_pll_enabled(dev_priv, pll, NULL);
1633 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1635 /* Make sure transcoder isn't still depending on us */
1636 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1639 val = I915_READ(reg);
1640 val &= ~DPLL_VCO_ENABLE;
1641 I915_WRITE(reg, val);
1648 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1652 u32 val, pipeconf_val;
1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1655 /* PCH only available on ILK+ */
1656 BUG_ON(dev_priv->info->gen < 5);
1658 /* Make sure PCH DPLL is enabled */
1659 assert_pch_pll_enabled(dev_priv,
1660 to_intel_crtc(crtc)->pch_pll,
1661 to_intel_crtc(crtc));
1663 /* FDI must be feeding us bits for PCH ports */
1664 assert_fdi_tx_enabled(dev_priv, pipe);
1665 assert_fdi_rx_enabled(dev_priv, pipe);
1667 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1668 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1671 reg = TRANSCONF(pipe);
1672 val = I915_READ(reg);
1673 pipeconf_val = I915_READ(PIPECONF(pipe));
1675 if (HAS_PCH_IBX(dev_priv->dev)) {
1677 * make the BPC in transcoder be consistent with
1678 * that in pipeconf reg.
1680 val &= ~PIPE_BPC_MASK;
1681 val |= pipeconf_val & PIPE_BPC_MASK;
1684 val &= ~TRANS_INTERLACE_MASK;
1685 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1686 if (HAS_PCH_IBX(dev_priv->dev) &&
1687 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688 val |= TRANS_LEGACY_INTERLACED_ILK;
1690 val |= TRANS_INTERLACED;
1692 val |= TRANS_PROGRESSIVE;
1694 I915_WRITE(reg, val | TRANS_ENABLE);
1695 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1699 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1705 /* FDI relies on the transcoder */
1706 assert_fdi_tx_disabled(dev_priv, pipe);
1707 assert_fdi_rx_disabled(dev_priv, pipe);
1709 /* Ports must be off as well */
1710 assert_pch_ports_disabled(dev_priv, pipe);
1712 reg = TRANSCONF(pipe);
1713 val = I915_READ(reg);
1714 val &= ~TRANS_ENABLE;
1715 I915_WRITE(reg, val);
1716 /* wait for PCH transcoder off, transcoder state */
1717 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1718 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1722 * intel_enable_pipe - enable a pipe, asserting requirements
1723 * @dev_priv: i915 private structure
1724 * @pipe: pipe to enable
1725 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1727 * Enable @pipe, making sure that various hardware specific requirements
1728 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1730 * @pipe should be %PIPE_A or %PIPE_B.
1732 * Will wait until the pipe is actually running (i.e. first vblank) before
1735 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1742 * A pipe without a PLL won't actually be able to drive bits from
1743 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1746 if (!HAS_PCH_SPLIT(dev_priv->dev))
1747 assert_pll_enabled(dev_priv, pipe);
1750 /* if driving the PCH, we need FDI enabled */
1751 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1752 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1754 /* FIXME: assert CPU port conditions for SNB+ */
1757 reg = PIPECONF(pipe);
1758 val = I915_READ(reg);
1759 if (val & PIPECONF_ENABLE)
1762 I915_WRITE(reg, val | PIPECONF_ENABLE);
1763 intel_wait_for_vblank(dev_priv->dev, pipe);
1767 * intel_disable_pipe - disable a pipe, asserting requirements
1768 * @dev_priv: i915 private structure
1769 * @pipe: pipe to disable
1771 * Disable @pipe, making sure that various hardware specific requirements
1772 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1774 * @pipe should be %PIPE_A or %PIPE_B.
1776 * Will wait until the pipe has shut down before returning.
1778 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1785 * Make sure planes won't keep trying to pump pixels to us,
1786 * or we might hang the display.
1788 assert_planes_disabled(dev_priv, pipe);
1790 /* Don't disable pipe A or pipe A PLLs if needed */
1791 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1794 reg = PIPECONF(pipe);
1795 val = I915_READ(reg);
1796 if ((val & PIPECONF_ENABLE) == 0)
1799 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1800 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1804 * Plane regs are double buffered, going from enabled->disabled needs a
1805 * trigger in order to latch. The display address reg provides this.
1807 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1810 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1811 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1815 * intel_enable_plane - enable a display plane on a given pipe
1816 * @dev_priv: i915 private structure
1817 * @plane: plane to enable
1818 * @pipe: pipe being fed
1820 * Enable @plane on @pipe, making sure that @pipe is running first.
1822 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1823 enum plane plane, enum pipe pipe)
1828 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829 assert_pipe_enabled(dev_priv, pipe);
1831 reg = DSPCNTR(plane);
1832 val = I915_READ(reg);
1833 if (val & DISPLAY_PLANE_ENABLE)
1836 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1837 intel_flush_display_plane(dev_priv, plane);
1838 intel_wait_for_vblank(dev_priv->dev, pipe);
1842 * intel_disable_plane - disable a display plane
1843 * @dev_priv: i915 private structure
1844 * @plane: plane to disable
1845 * @pipe: pipe consuming the data
1847 * Disable @plane; should be an independent operation.
1849 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1850 enum plane plane, enum pipe pipe)
1855 reg = DSPCNTR(plane);
1856 val = I915_READ(reg);
1857 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1860 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1861 intel_flush_display_plane(dev_priv, plane);
1862 intel_wait_for_vblank(dev_priv->dev, pipe);
1866 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1867 struct drm_i915_gem_object *obj,
1868 struct intel_ring_buffer *pipelined)
1870 struct drm_i915_private *dev_priv = dev->dev_private;
1874 switch (obj->tiling_mode) {
1875 case I915_TILING_NONE:
1876 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1877 alignment = 128 * 1024;
1878 else if (INTEL_INFO(dev)->gen >= 4)
1879 alignment = 4 * 1024;
1881 alignment = 64 * 1024;
1884 /* pin() will align the object as required by fence */
1888 /* FIXME: Is this true? */
1889 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1895 dev_priv->mm.interruptible = false;
1896 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1898 goto err_interruptible;
1900 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901 * fence, whereas 965+ only requires a fence if using
1902 * framebuffer compression. For simplicity, we always install
1903 * a fence as the cost is not that onerous.
1905 ret = i915_gem_object_get_fence(obj);
1909 i915_gem_object_pin_fence(obj);
1911 dev_priv->mm.interruptible = true;
1915 i915_gem_object_unpin(obj);
1917 dev_priv->mm.interruptible = true;
1921 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1923 i915_gem_object_unpin_fence(obj);
1924 i915_gem_object_unpin(obj);
1927 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928 * is assumed to be a power-of-two. */
1929 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1933 int tile_rows, tiles;
1937 tiles = *x / (512/bpp);
1940 return tile_rows * pitch * 8 + tiles * 4096;
1943 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 struct intel_framebuffer *intel_fb;
1950 struct drm_i915_gem_object *obj;
1951 int plane = intel_crtc->plane;
1952 unsigned long linear_offset;
1961 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1965 intel_fb = to_intel_framebuffer(fb);
1966 obj = intel_fb->obj;
1968 reg = DSPCNTR(plane);
1969 dspcntr = I915_READ(reg);
1970 /* Mask out pixel format bits in case we change it */
1971 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972 switch (fb->bits_per_pixel) {
1974 dspcntr |= DISPPLANE_8BPP;
1977 if (fb->depth == 15)
1978 dspcntr |= DISPPLANE_15_16BPP;
1980 dspcntr |= DISPPLANE_16BPP;
1984 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1987 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1990 if (INTEL_INFO(dev)->gen >= 4) {
1991 if (obj->tiling_mode != I915_TILING_NONE)
1992 dspcntr |= DISPPLANE_TILED;
1994 dspcntr &= ~DISPPLANE_TILED;
1997 I915_WRITE(reg, dspcntr);
1999 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2001 if (INTEL_INFO(dev)->gen >= 4) {
2002 intel_crtc->dspaddr_offset =
2003 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2004 fb->bits_per_pixel / 8,
2006 linear_offset -= intel_crtc->dspaddr_offset;
2008 intel_crtc->dspaddr_offset = linear_offset;
2011 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2013 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2014 if (INTEL_INFO(dev)->gen >= 4) {
2015 I915_MODIFY_DISPBASE(DSPSURF(plane),
2016 obj->gtt_offset + intel_crtc->dspaddr_offset);
2017 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2018 I915_WRITE(DSPLINOFF(plane), linear_offset);
2020 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2026 static int ironlake_update_plane(struct drm_crtc *crtc,
2027 struct drm_framebuffer *fb, int x, int y)
2029 struct drm_device *dev = crtc->dev;
2030 struct drm_i915_private *dev_priv = dev->dev_private;
2031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032 struct intel_framebuffer *intel_fb;
2033 struct drm_i915_gem_object *obj;
2034 int plane = intel_crtc->plane;
2035 unsigned long linear_offset;
2045 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2049 intel_fb = to_intel_framebuffer(fb);
2050 obj = intel_fb->obj;
2052 reg = DSPCNTR(plane);
2053 dspcntr = I915_READ(reg);
2054 /* Mask out pixel format bits in case we change it */
2055 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056 switch (fb->bits_per_pixel) {
2058 dspcntr |= DISPPLANE_8BPP;
2061 if (fb->depth != 16)
2064 dspcntr |= DISPPLANE_16BPP;
2068 if (fb->depth == 24)
2069 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2070 else if (fb->depth == 30)
2071 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2076 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2080 if (obj->tiling_mode != I915_TILING_NONE)
2081 dspcntr |= DISPPLANE_TILED;
2083 dspcntr &= ~DISPPLANE_TILED;
2086 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2088 I915_WRITE(reg, dspcntr);
2090 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2091 intel_crtc->dspaddr_offset =
2092 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2095 linear_offset -= intel_crtc->dspaddr_offset;
2097 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2099 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2100 I915_MODIFY_DISPBASE(DSPSURF(plane),
2101 obj->gtt_offset + intel_crtc->dspaddr_offset);
2102 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103 I915_WRITE(DSPLINOFF(plane), linear_offset);
2109 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2111 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112 int x, int y, enum mode_set_atomic state)
2114 struct drm_device *dev = crtc->dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
2117 if (dev_priv->display.disable_fbc)
2118 dev_priv->display.disable_fbc(dev);
2119 intel_increase_pllclock(crtc);
2121 return dev_priv->display.update_plane(crtc, fb, x, y);
2125 intel_finish_fb(struct drm_framebuffer *old_fb)
2127 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2128 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129 bool was_interruptible = dev_priv->mm.interruptible;
2132 wait_event(dev_priv->pending_flip_queue,
2133 atomic_read(&dev_priv->mm.wedged) ||
2134 atomic_read(&obj->pending_flip) == 0);
2136 /* Big Hammer, we also need to ensure that any pending
2137 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138 * current scanout is retired before unpinning the old
2141 * This should only fail upon a hung GPU, in which case we
2142 * can safely continue.
2144 dev_priv->mm.interruptible = false;
2145 ret = i915_gem_object_finish_gpu(obj);
2146 dev_priv->mm.interruptible = was_interruptible;
2152 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2153 struct drm_framebuffer *fb)
2155 struct drm_device *dev = crtc->dev;
2156 struct drm_i915_private *dev_priv = dev->dev_private;
2157 struct drm_i915_master_private *master_priv;
2158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2159 struct drm_framebuffer *old_fb;
2164 DRM_ERROR("No FB bound\n");
2168 if(intel_crtc->plane > dev_priv->num_pipe) {
2169 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2171 dev_priv->num_pipe);
2175 mutex_lock(&dev->struct_mutex);
2176 ret = intel_pin_and_fence_fb_obj(dev,
2177 to_intel_framebuffer(fb)->obj,
2180 mutex_unlock(&dev->struct_mutex);
2181 DRM_ERROR("pin & fence failed\n");
2186 intel_finish_fb(crtc->fb);
2188 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2190 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2191 mutex_unlock(&dev->struct_mutex);
2192 DRM_ERROR("failed to update base address\n");
2202 intel_wait_for_vblank(dev, intel_crtc->pipe);
2203 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2206 intel_update_fbc(dev);
2207 mutex_unlock(&dev->struct_mutex);
2209 if (!dev->primary->master)
2212 master_priv = dev->primary->master->driver_priv;
2213 if (!master_priv->sarea_priv)
2216 if (intel_crtc->pipe) {
2217 master_priv->sarea_priv->pipeB_x = x;
2218 master_priv->sarea_priv->pipeB_y = y;
2220 master_priv->sarea_priv->pipeA_x = x;
2221 master_priv->sarea_priv->pipeA_y = y;
2227 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2229 struct drm_device *dev = crtc->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2233 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2234 dpa_ctl = I915_READ(DP_A);
2235 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2237 if (clock < 200000) {
2239 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2240 /* workaround for 160Mhz:
2241 1) program 0x4600c bits 15:0 = 0x8124
2242 2) program 0x46010 bit 0 = 1
2243 3) program 0x46034 bit 24 = 1
2244 4) program 0x64000 bit 14 = 1
2246 temp = I915_READ(0x4600c);
2248 I915_WRITE(0x4600c, temp | 0x8124);
2250 temp = I915_READ(0x46010);
2251 I915_WRITE(0x46010, temp | 1);
2253 temp = I915_READ(0x46034);
2254 I915_WRITE(0x46034, temp | (1 << 24));
2256 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2258 I915_WRITE(DP_A, dpa_ctl);
2264 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2266 struct drm_device *dev = crtc->dev;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269 int pipe = intel_crtc->pipe;
2272 /* enable normal train */
2273 reg = FDI_TX_CTL(pipe);
2274 temp = I915_READ(reg);
2275 if (IS_IVYBRIDGE(dev)) {
2276 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2277 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2279 temp &= ~FDI_LINK_TRAIN_NONE;
2280 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2282 I915_WRITE(reg, temp);
2284 reg = FDI_RX_CTL(pipe);
2285 temp = I915_READ(reg);
2286 if (HAS_PCH_CPT(dev)) {
2287 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2288 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2290 temp &= ~FDI_LINK_TRAIN_NONE;
2291 temp |= FDI_LINK_TRAIN_NONE;
2293 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2295 /* wait one idle pattern time */
2299 /* IVB wants error correction enabled */
2300 if (IS_IVYBRIDGE(dev))
2301 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2302 FDI_FE_ERRC_ENABLE);
2305 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 u32 flags = I915_READ(SOUTH_CHICKEN1);
2310 flags |= FDI_PHASE_SYNC_OVR(pipe);
2311 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2312 flags |= FDI_PHASE_SYNC_EN(pipe);
2313 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2314 POSTING_READ(SOUTH_CHICKEN1);
2317 /* The FDI link training functions for ILK/Ibexpeak. */
2318 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 int pipe = intel_crtc->pipe;
2324 int plane = intel_crtc->plane;
2325 u32 reg, temp, tries;
2327 /* FDI needs bits from pipe & plane first */
2328 assert_pipe_enabled(dev_priv, pipe);
2329 assert_plane_enabled(dev_priv, plane);
2331 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2333 reg = FDI_RX_IMR(pipe);
2334 temp = I915_READ(reg);
2335 temp &= ~FDI_RX_SYMBOL_LOCK;
2336 temp &= ~FDI_RX_BIT_LOCK;
2337 I915_WRITE(reg, temp);
2341 /* enable CPU FDI TX and PCH FDI RX */
2342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
2345 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_PATTERN_1;
2348 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
2352 temp &= ~FDI_LINK_TRAIN_NONE;
2353 temp |= FDI_LINK_TRAIN_PATTERN_1;
2354 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2359 /* Ironlake workaround, enable clock pointer after FDI enable*/
2360 if (HAS_PCH_IBX(dev)) {
2361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363 FDI_RX_PHASE_SYNC_POINTER_EN);
2366 reg = FDI_RX_IIR(pipe);
2367 for (tries = 0; tries < 5; tries++) {
2368 temp = I915_READ(reg);
2369 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2371 if ((temp & FDI_RX_BIT_LOCK)) {
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
2373 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2378 DRM_ERROR("FDI train 1 fail!\n");
2381 reg = FDI_TX_CTL(pipe);
2382 temp = I915_READ(reg);
2383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_PATTERN_2;
2385 I915_WRITE(reg, temp);
2387 reg = FDI_RX_CTL(pipe);
2388 temp = I915_READ(reg);
2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_2;
2391 I915_WRITE(reg, temp);
2396 reg = FDI_RX_IIR(pipe);
2397 for (tries = 0; tries < 5; tries++) {
2398 temp = I915_READ(reg);
2399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2401 if (temp & FDI_RX_SYMBOL_LOCK) {
2402 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2403 DRM_DEBUG_KMS("FDI train 2 done.\n");
2408 DRM_ERROR("FDI train 2 fail!\n");
2410 DRM_DEBUG_KMS("FDI train done\n");
2414 static const int snb_b_fdi_train_param[] = {
2415 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2416 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2417 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2418 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2421 /* The FDI link training functions for SNB/Cougarpoint. */
2422 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2424 struct drm_device *dev = crtc->dev;
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427 int pipe = intel_crtc->pipe;
2428 u32 reg, temp, i, retry;
2430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2432 reg = FDI_RX_IMR(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_RX_SYMBOL_LOCK;
2435 temp &= ~FDI_RX_BIT_LOCK;
2436 I915_WRITE(reg, temp);
2441 /* enable CPU FDI TX and PCH FDI RX */
2442 reg = FDI_TX_CTL(pipe);
2443 temp = I915_READ(reg);
2445 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2450 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2451 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2453 reg = FDI_RX_CTL(pipe);
2454 temp = I915_READ(reg);
2455 if (HAS_PCH_CPT(dev)) {
2456 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2457 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_1;
2462 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2467 if (HAS_PCH_CPT(dev))
2468 cpt_phase_pointer_enable(dev, pipe);
2470 for (i = 0; i < 4; i++) {
2471 reg = FDI_TX_CTL(pipe);
2472 temp = I915_READ(reg);
2473 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474 temp |= snb_b_fdi_train_param[i];
2475 I915_WRITE(reg, temp);
2480 for (retry = 0; retry < 5; retry++) {
2481 reg = FDI_RX_IIR(pipe);
2482 temp = I915_READ(reg);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484 if (temp & FDI_RX_BIT_LOCK) {
2485 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486 DRM_DEBUG_KMS("FDI train 1 done.\n");
2495 DRM_ERROR("FDI train 1 fail!\n");
2498 reg = FDI_TX_CTL(pipe);
2499 temp = I915_READ(reg);
2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_2;
2503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2505 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2507 I915_WRITE(reg, temp);
2509 reg = FDI_RX_CTL(pipe);
2510 temp = I915_READ(reg);
2511 if (HAS_PCH_CPT(dev)) {
2512 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2513 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2515 temp &= ~FDI_LINK_TRAIN_NONE;
2516 temp |= FDI_LINK_TRAIN_PATTERN_2;
2518 I915_WRITE(reg, temp);
2523 for (i = 0; i < 4; i++) {
2524 reg = FDI_TX_CTL(pipe);
2525 temp = I915_READ(reg);
2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 temp |= snb_b_fdi_train_param[i];
2528 I915_WRITE(reg, temp);
2533 for (retry = 0; retry < 5; retry++) {
2534 reg = FDI_RX_IIR(pipe);
2535 temp = I915_READ(reg);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537 if (temp & FDI_RX_SYMBOL_LOCK) {
2538 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539 DRM_DEBUG_KMS("FDI train 2 done.\n");
2548 DRM_ERROR("FDI train 2 fail!\n");
2550 DRM_DEBUG_KMS("FDI train done.\n");
2553 /* Manual link training for Ivy Bridge A0 parts */
2554 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559 int pipe = intel_crtc->pipe;
2562 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2564 reg = FDI_RX_IMR(pipe);
2565 temp = I915_READ(reg);
2566 temp &= ~FDI_RX_SYMBOL_LOCK;
2567 temp &= ~FDI_RX_BIT_LOCK;
2568 I915_WRITE(reg, temp);
2573 /* enable CPU FDI TX and PCH FDI RX */
2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
2577 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2578 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2580 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582 temp |= FDI_COMPOSITE_SYNC;
2583 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
2587 temp &= ~FDI_LINK_TRAIN_AUTO;
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2590 temp |= FDI_COMPOSITE_SYNC;
2591 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2596 if (HAS_PCH_CPT(dev))
2597 cpt_phase_pointer_enable(dev, pipe);
2599 for (i = 0; i < 4; i++) {
2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
2604 I915_WRITE(reg, temp);
2609 reg = FDI_RX_IIR(pipe);
2610 temp = I915_READ(reg);
2611 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2613 if (temp & FDI_RX_BIT_LOCK ||
2614 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2615 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616 DRM_DEBUG_KMS("FDI train 1 done.\n");
2621 DRM_ERROR("FDI train 1 fail!\n");
2624 reg = FDI_TX_CTL(pipe);
2625 temp = I915_READ(reg);
2626 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2627 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630 I915_WRITE(reg, temp);
2632 reg = FDI_RX_CTL(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636 I915_WRITE(reg, temp);
2641 for (i = 0; i < 4; i++) {
2642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645 temp |= snb_b_fdi_train_param[i];
2646 I915_WRITE(reg, temp);
2651 reg = FDI_RX_IIR(pipe);
2652 temp = I915_READ(reg);
2653 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2655 if (temp & FDI_RX_SYMBOL_LOCK) {
2656 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657 DRM_DEBUG_KMS("FDI train 2 done.\n");
2662 DRM_ERROR("FDI train 2 fail!\n");
2664 DRM_DEBUG_KMS("FDI train done.\n");
2667 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2669 struct drm_device *dev = intel_crtc->base.dev;
2670 struct drm_i915_private *dev_priv = dev->dev_private;
2671 int pipe = intel_crtc->pipe;
2674 /* Write the TU size bits so error detection works */
2675 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2676 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2678 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2679 reg = FDI_RX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~((0x7 << 19) | (0x7 << 16));
2682 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2683 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2684 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2689 /* Switch from Rawclk to PCDclk */
2690 temp = I915_READ(reg);
2691 I915_WRITE(reg, temp | FDI_PCDCLK);
2696 /* On Haswell, the PLL configuration for ports and pipes is handled
2697 * separately, as part of DDI setup */
2698 if (!IS_HASWELL(dev)) {
2699 /* Enable CPU FDI TX PLL, always on for Ironlake */
2700 reg = FDI_TX_CTL(pipe);
2701 temp = I915_READ(reg);
2702 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2703 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2711 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2713 struct drm_device *dev = intel_crtc->base.dev;
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 int pipe = intel_crtc->pipe;
2718 /* Switch from PCDclk to Rawclk */
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2723 /* Disable CPU FDI TX PLL */
2724 reg = FDI_TX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2731 reg = FDI_RX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2735 /* Wait for the clocks to turn off. */
2740 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 u32 flags = I915_READ(SOUTH_CHICKEN1);
2745 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2749 POSTING_READ(SOUTH_CHICKEN1);
2751 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2753 struct drm_device *dev = crtc->dev;
2754 struct drm_i915_private *dev_priv = dev->dev_private;
2755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756 int pipe = intel_crtc->pipe;
2759 /* disable CPU FDI tx and PCH FDI rx */
2760 reg = FDI_TX_CTL(pipe);
2761 temp = I915_READ(reg);
2762 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~(0x7 << 16);
2768 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2774 /* Ironlake workaround, disable clock pointer after downing FDI */
2775 if (HAS_PCH_IBX(dev)) {
2776 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2777 I915_WRITE(FDI_RX_CHICKEN(pipe),
2778 I915_READ(FDI_RX_CHICKEN(pipe) &
2779 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2780 } else if (HAS_PCH_CPT(dev)) {
2781 cpt_phase_pointer_disable(dev, pipe);
2784 /* still set train pattern 1 */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_PATTERN_1;
2789 I915_WRITE(reg, temp);
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 if (HAS_PCH_CPT(dev)) {
2794 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2797 temp &= ~FDI_LINK_TRAIN_NONE;
2798 temp |= FDI_LINK_TRAIN_PATTERN_1;
2800 /* BPC in FDI rx is consistent with that in PIPECONF */
2801 temp &= ~(0x07 << 16);
2802 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803 I915_WRITE(reg, temp);
2809 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2811 struct drm_device *dev = crtc->dev;
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 unsigned long flags;
2816 if (atomic_read(&dev_priv->mm.wedged))
2819 spin_lock_irqsave(&dev->event_lock, flags);
2820 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2821 spin_unlock_irqrestore(&dev->event_lock, flags);
2826 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2828 struct drm_device *dev = crtc->dev;
2829 struct drm_i915_private *dev_priv = dev->dev_private;
2831 if (crtc->fb == NULL)
2834 wait_event(dev_priv->pending_flip_queue,
2835 !intel_crtc_has_pending_flip(crtc));
2837 mutex_lock(&dev->struct_mutex);
2838 intel_finish_fb(crtc->fb);
2839 mutex_unlock(&dev->struct_mutex);
2842 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2844 struct drm_device *dev = crtc->dev;
2845 struct intel_encoder *intel_encoder;
2848 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2849 * must be driven by its own crtc; no sharing is possible.
2851 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2853 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2854 * CPU handles all others */
2855 if (IS_HASWELL(dev)) {
2856 /* It is still unclear how this will work on PPT, so throw up a warning */
2857 WARN_ON(!HAS_PCH_LPT(dev));
2859 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2860 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2863 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2864 intel_encoder->type);
2869 switch (intel_encoder->type) {
2870 case INTEL_OUTPUT_EDP:
2871 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2880 /* Program iCLKIP clock to the desired frequency */
2881 static void lpt_program_iclkip(struct drm_crtc *crtc)
2883 struct drm_device *dev = crtc->dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2888 /* It is necessary to ungate the pixclk gate prior to programming
2889 * the divisors, and gate it back when it is done.
2891 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2893 /* Disable SSCCTL */
2894 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2895 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2896 SBI_SSCCTL_DISABLE);
2898 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2899 if (crtc->mode.clock == 20000) {
2904 /* The iCLK virtual clock root frequency is in MHz,
2905 * but the crtc->mode.clock in in KHz. To get the divisors,
2906 * it is necessary to divide one by another, so we
2907 * convert the virtual clock precision to KHz here for higher
2910 u32 iclk_virtual_root_freq = 172800 * 1000;
2911 u32 iclk_pi_range = 64;
2912 u32 desired_divisor, msb_divisor_value, pi_value;
2914 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2915 msb_divisor_value = desired_divisor / iclk_pi_range;
2916 pi_value = desired_divisor % iclk_pi_range;
2919 divsel = msb_divisor_value - 2;
2920 phaseinc = pi_value;
2923 /* This should not happen with any sane values */
2924 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2925 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2926 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2927 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2929 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2936 /* Program SSCDIVINTPHASE6 */
2937 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2938 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2939 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2940 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2941 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2942 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2943 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2945 intel_sbi_write(dev_priv,
2946 SBI_SSCDIVINTPHASE6,
2949 /* Program SSCAUXDIV */
2950 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2951 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2952 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2953 intel_sbi_write(dev_priv,
2958 /* Enable modulator and associated divider */
2959 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2960 temp &= ~SBI_SSCCTL_DISABLE;
2961 intel_sbi_write(dev_priv,
2965 /* Wait for initialization time */
2968 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2972 * Enable PCH resources required for PCH ports:
2974 * - FDI training & RX/TX
2975 * - update transcoder timings
2976 * - DP transcoding bits
2979 static void ironlake_pch_enable(struct drm_crtc *crtc)
2981 struct drm_device *dev = crtc->dev;
2982 struct drm_i915_private *dev_priv = dev->dev_private;
2983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2984 int pipe = intel_crtc->pipe;
2987 assert_transcoder_disabled(dev_priv, pipe);
2989 /* For PCH output, training FDI link */
2990 dev_priv->display.fdi_link_train(crtc);
2992 intel_enable_pch_pll(intel_crtc);
2994 if (HAS_PCH_LPT(dev)) {
2995 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2996 lpt_program_iclkip(crtc);
2997 } else if (HAS_PCH_CPT(dev)) {
3000 temp = I915_READ(PCH_DPLL_SEL);
3004 temp |= TRANSA_DPLL_ENABLE;
3005 sel = TRANSA_DPLLB_SEL;
3008 temp |= TRANSB_DPLL_ENABLE;
3009 sel = TRANSB_DPLLB_SEL;
3012 temp |= TRANSC_DPLL_ENABLE;
3013 sel = TRANSC_DPLLB_SEL;
3016 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3020 I915_WRITE(PCH_DPLL_SEL, temp);
3023 /* set transcoder timing, panel must allow it */
3024 assert_panel_unlocked(dev_priv, pipe);
3025 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3026 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3027 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3029 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3030 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3031 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3032 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3034 if (!IS_HASWELL(dev))
3035 intel_fdi_normal_train(crtc);
3037 /* For PCH DP, enable TRANS_DP_CTL */
3038 if (HAS_PCH_CPT(dev) &&
3039 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3040 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3041 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3042 reg = TRANS_DP_CTL(pipe);
3043 temp = I915_READ(reg);
3044 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3045 TRANS_DP_SYNC_MASK |
3047 temp |= (TRANS_DP_OUTPUT_ENABLE |
3048 TRANS_DP_ENH_FRAMING);
3049 temp |= bpc << 9; /* same format but at 11:9 */
3051 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3052 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3053 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3054 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3056 switch (intel_trans_dp_port_sel(crtc)) {
3058 temp |= TRANS_DP_PORT_SEL_B;
3061 temp |= TRANS_DP_PORT_SEL_C;
3064 temp |= TRANS_DP_PORT_SEL_D;
3067 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3068 temp |= TRANS_DP_PORT_SEL_B;
3072 I915_WRITE(reg, temp);
3075 intel_enable_transcoder(dev_priv, pipe);
3078 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3080 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3085 if (pll->refcount == 0) {
3086 WARN(1, "bad PCH PLL refcount\n");
3091 intel_crtc->pch_pll = NULL;
3094 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3096 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3097 struct intel_pch_pll *pll;
3100 pll = intel_crtc->pch_pll;
3102 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3103 intel_crtc->base.base.id, pll->pll_reg);
3107 if (HAS_PCH_IBX(dev_priv->dev)) {
3108 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3109 i = intel_crtc->pipe;
3110 pll = &dev_priv->pch_plls[i];
3112 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3113 intel_crtc->base.base.id, pll->pll_reg);
3118 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3119 pll = &dev_priv->pch_plls[i];
3121 /* Only want to check enabled timings first */
3122 if (pll->refcount == 0)
3125 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3126 fp == I915_READ(pll->fp0_reg)) {
3127 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3128 intel_crtc->base.base.id,
3129 pll->pll_reg, pll->refcount, pll->active);
3135 /* Ok no matching timings, maybe there's a free one? */
3136 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3137 pll = &dev_priv->pch_plls[i];
3138 if (pll->refcount == 0) {
3139 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3140 intel_crtc->base.base.id, pll->pll_reg);
3148 intel_crtc->pch_pll = pll;
3150 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3151 prepare: /* separate function? */
3152 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3154 /* Wait for the clocks to stabilize before rewriting the regs */
3155 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3156 POSTING_READ(pll->pll_reg);
3159 I915_WRITE(pll->fp0_reg, fp);
3160 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3165 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3167 struct drm_i915_private *dev_priv = dev->dev_private;
3168 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3171 temp = I915_READ(dslreg);
3173 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3174 /* Without this, mode sets may fail silently on FDI */
3175 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3177 I915_WRITE(tc2reg, 0);
3178 if (wait_for(I915_READ(dslreg) != temp, 5))
3179 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3183 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3185 struct drm_device *dev = crtc->dev;
3186 struct drm_i915_private *dev_priv = dev->dev_private;
3187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188 struct intel_encoder *encoder;
3189 int pipe = intel_crtc->pipe;
3190 int plane = intel_crtc->plane;
3194 WARN_ON(!crtc->enabled);
3196 if (intel_crtc->active)
3199 intel_crtc->active = true;
3200 intel_update_watermarks(dev);
3202 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3203 temp = I915_READ(PCH_LVDS);
3204 if ((temp & LVDS_PORT_EN) == 0)
3205 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3208 is_pch_port = intel_crtc_driving_pch(crtc);
3211 ironlake_fdi_pll_enable(intel_crtc);
3213 assert_fdi_tx_disabled(dev_priv, pipe);
3214 assert_fdi_rx_disabled(dev_priv, pipe);
3217 for_each_encoder_on_crtc(dev, crtc, encoder)
3218 if (encoder->pre_enable)
3219 encoder->pre_enable(encoder);
3221 if (IS_HASWELL(dev))
3222 intel_ddi_enable_pipe_clock(intel_crtc);
3224 /* Enable panel fitting for LVDS */
3225 if (dev_priv->pch_pf_size &&
3226 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3227 /* Force use of hard-coded filter coefficients
3228 * as some pre-programmed values are broken,
3231 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3232 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3233 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3237 * On ILK+ LUT must be loaded before the pipe is running but with
3240 intel_crtc_load_lut(crtc);
3242 if (IS_HASWELL(dev)) {
3243 intel_ddi_set_pipe_settings(crtc);
3244 intel_ddi_enable_pipe_func(crtc);
3247 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3248 intel_enable_plane(dev_priv, plane, pipe);
3251 ironlake_pch_enable(crtc);
3253 mutex_lock(&dev->struct_mutex);
3254 intel_update_fbc(dev);
3255 mutex_unlock(&dev->struct_mutex);
3257 intel_crtc_update_cursor(crtc, true);
3259 for_each_encoder_on_crtc(dev, crtc, encoder)
3260 encoder->enable(encoder);
3262 if (HAS_PCH_CPT(dev))
3263 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3266 * There seems to be a race in PCH platform hw (at least on some
3267 * outputs) where an enabled pipe still completes any pageflip right
3268 * away (as if the pipe is off) instead of waiting for vblank. As soon
3269 * as the first vblank happend, everything works as expected. Hence just
3270 * wait for one vblank before returning to avoid strange things
3273 intel_wait_for_vblank(dev, intel_crtc->pipe);
3276 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3278 struct drm_device *dev = crtc->dev;
3279 struct drm_i915_private *dev_priv = dev->dev_private;
3280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3281 struct intel_encoder *encoder;
3282 int pipe = intel_crtc->pipe;
3283 int plane = intel_crtc->plane;
3287 if (!intel_crtc->active)
3290 for_each_encoder_on_crtc(dev, crtc, encoder)
3291 encoder->disable(encoder);
3293 intel_crtc_wait_for_pending_flips(crtc);
3294 drm_vblank_off(dev, pipe);
3295 intel_crtc_update_cursor(crtc, false);
3297 intel_disable_plane(dev_priv, plane, pipe);
3299 if (dev_priv->cfb_plane == plane)
3300 intel_disable_fbc(dev);
3302 intel_disable_pipe(dev_priv, pipe);
3304 if (IS_HASWELL(dev))
3305 intel_ddi_disable_pipe_func(dev_priv, pipe);
3308 I915_WRITE(PF_CTL(pipe), 0);
3309 I915_WRITE(PF_WIN_SZ(pipe), 0);
3311 if (IS_HASWELL(dev))
3312 intel_ddi_disable_pipe_clock(intel_crtc);
3314 for_each_encoder_on_crtc(dev, crtc, encoder)
3315 if (encoder->post_disable)
3316 encoder->post_disable(encoder);
3318 ironlake_fdi_disable(crtc);
3320 intel_disable_transcoder(dev_priv, pipe);
3322 if (HAS_PCH_CPT(dev)) {
3323 /* disable TRANS_DP_CTL */
3324 reg = TRANS_DP_CTL(pipe);
3325 temp = I915_READ(reg);
3326 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3327 temp |= TRANS_DP_PORT_SEL_NONE;
3328 I915_WRITE(reg, temp);
3330 /* disable DPLL_SEL */
3331 temp = I915_READ(PCH_DPLL_SEL);
3334 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3337 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3340 /* C shares PLL A or B */
3341 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3346 I915_WRITE(PCH_DPLL_SEL, temp);
3349 /* disable PCH DPLL */
3350 intel_disable_pch_pll(intel_crtc);
3352 ironlake_fdi_pll_disable(intel_crtc);
3354 intel_crtc->active = false;
3355 intel_update_watermarks(dev);
3357 mutex_lock(&dev->struct_mutex);
3358 intel_update_fbc(dev);
3359 mutex_unlock(&dev->struct_mutex);
3362 static void ironlake_crtc_off(struct drm_crtc *crtc)
3364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365 intel_put_pch_pll(intel_crtc);
3368 static void haswell_crtc_off(struct drm_crtc *crtc)
3370 intel_ddi_put_crtc_pll(crtc);
3373 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3375 if (!enable && intel_crtc->overlay) {
3376 struct drm_device *dev = intel_crtc->base.dev;
3377 struct drm_i915_private *dev_priv = dev->dev_private;
3379 mutex_lock(&dev->struct_mutex);
3380 dev_priv->mm.interruptible = false;
3381 (void) intel_overlay_switch_off(intel_crtc->overlay);
3382 dev_priv->mm.interruptible = true;
3383 mutex_unlock(&dev->struct_mutex);
3386 /* Let userspace switch the overlay on again. In most cases userspace
3387 * has to recompute where to put it anyway.
3391 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3393 struct drm_device *dev = crtc->dev;
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396 struct intel_encoder *encoder;
3397 int pipe = intel_crtc->pipe;
3398 int plane = intel_crtc->plane;
3400 WARN_ON(!crtc->enabled);
3402 if (intel_crtc->active)
3405 intel_crtc->active = true;
3406 intel_update_watermarks(dev);
3408 intel_enable_pll(dev_priv, pipe);
3409 intel_enable_pipe(dev_priv, pipe, false);
3410 intel_enable_plane(dev_priv, plane, pipe);
3412 intel_crtc_load_lut(crtc);
3413 intel_update_fbc(dev);
3415 /* Give the overlay scaler a chance to enable if it's on this pipe */
3416 intel_crtc_dpms_overlay(intel_crtc, true);
3417 intel_crtc_update_cursor(crtc, true);
3419 for_each_encoder_on_crtc(dev, crtc, encoder)
3420 encoder->enable(encoder);
3423 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3425 struct drm_device *dev = crtc->dev;
3426 struct drm_i915_private *dev_priv = dev->dev_private;
3427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3428 struct intel_encoder *encoder;
3429 int pipe = intel_crtc->pipe;
3430 int plane = intel_crtc->plane;
3433 if (!intel_crtc->active)
3436 for_each_encoder_on_crtc(dev, crtc, encoder)
3437 encoder->disable(encoder);
3439 /* Give the overlay scaler a chance to disable if it's on this pipe */
3440 intel_crtc_wait_for_pending_flips(crtc);
3441 drm_vblank_off(dev, pipe);
3442 intel_crtc_dpms_overlay(intel_crtc, false);
3443 intel_crtc_update_cursor(crtc, false);
3445 if (dev_priv->cfb_plane == plane)
3446 intel_disable_fbc(dev);
3448 intel_disable_plane(dev_priv, plane, pipe);
3449 intel_disable_pipe(dev_priv, pipe);
3450 intel_disable_pll(dev_priv, pipe);
3452 intel_crtc->active = false;
3453 intel_update_fbc(dev);
3454 intel_update_watermarks(dev);
3457 static void i9xx_crtc_off(struct drm_crtc *crtc)
3461 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3464 struct drm_device *dev = crtc->dev;
3465 struct drm_i915_master_private *master_priv;
3466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3467 int pipe = intel_crtc->pipe;
3469 if (!dev->primary->master)
3472 master_priv = dev->primary->master->driver_priv;
3473 if (!master_priv->sarea_priv)
3478 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3479 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3482 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3483 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3486 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3492 * Sets the power management mode of the pipe and plane.
3494 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3496 struct drm_device *dev = crtc->dev;
3497 struct drm_i915_private *dev_priv = dev->dev_private;
3498 struct intel_encoder *intel_encoder;
3499 bool enable = false;
3501 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3502 enable |= intel_encoder->connectors_active;
3505 dev_priv->display.crtc_enable(crtc);
3507 dev_priv->display.crtc_disable(crtc);
3509 intel_crtc_update_sarea(crtc, enable);
3512 static void intel_crtc_noop(struct drm_crtc *crtc)
3516 static void intel_crtc_disable(struct drm_crtc *crtc)
3518 struct drm_device *dev = crtc->dev;
3519 struct drm_connector *connector;
3520 struct drm_i915_private *dev_priv = dev->dev_private;
3522 /* crtc should still be enabled when we disable it. */
3523 WARN_ON(!crtc->enabled);
3525 dev_priv->display.crtc_disable(crtc);
3526 intel_crtc_update_sarea(crtc, false);
3527 dev_priv->display.off(crtc);
3529 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3530 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3533 mutex_lock(&dev->struct_mutex);
3534 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3535 mutex_unlock(&dev->struct_mutex);
3539 /* Update computed state. */
3540 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3541 if (!connector->encoder || !connector->encoder->crtc)
3544 if (connector->encoder->crtc != crtc)
3547 connector->dpms = DRM_MODE_DPMS_OFF;
3548 to_intel_encoder(connector->encoder)->connectors_active = false;
3552 void intel_modeset_disable(struct drm_device *dev)
3554 struct drm_crtc *crtc;
3556 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3558 intel_crtc_disable(crtc);
3562 void intel_encoder_noop(struct drm_encoder *encoder)
3566 void intel_encoder_destroy(struct drm_encoder *encoder)
3568 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3570 drm_encoder_cleanup(encoder);
3571 kfree(intel_encoder);
3574 /* Simple dpms helper for encodres with just one connector, no cloning and only
3575 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3576 * state of the entire output pipe. */
3577 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3579 if (mode == DRM_MODE_DPMS_ON) {
3580 encoder->connectors_active = true;
3582 intel_crtc_update_dpms(encoder->base.crtc);
3584 encoder->connectors_active = false;
3586 intel_crtc_update_dpms(encoder->base.crtc);
3590 /* Cross check the actual hw state with our own modeset state tracking (and it's
3591 * internal consistency). */
3592 static void intel_connector_check_state(struct intel_connector *connector)
3594 if (connector->get_hw_state(connector)) {
3595 struct intel_encoder *encoder = connector->encoder;
3596 struct drm_crtc *crtc;
3597 bool encoder_enabled;
3600 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3601 connector->base.base.id,
3602 drm_get_connector_name(&connector->base));
3604 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3605 "wrong connector dpms state\n");
3606 WARN(connector->base.encoder != &encoder->base,
3607 "active connector not linked to encoder\n");
3608 WARN(!encoder->connectors_active,
3609 "encoder->connectors_active not set\n");
3611 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3612 WARN(!encoder_enabled, "encoder not enabled\n");
3613 if (WARN_ON(!encoder->base.crtc))
3616 crtc = encoder->base.crtc;
3618 WARN(!crtc->enabled, "crtc not enabled\n");
3619 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3620 WARN(pipe != to_intel_crtc(crtc)->pipe,
3621 "encoder active on the wrong pipe\n");
3625 /* Even simpler default implementation, if there's really no special case to
3627 void intel_connector_dpms(struct drm_connector *connector, int mode)
3629 struct intel_encoder *encoder = intel_attached_encoder(connector);
3631 /* All the simple cases only support two dpms states. */
3632 if (mode != DRM_MODE_DPMS_ON)
3633 mode = DRM_MODE_DPMS_OFF;
3635 if (mode == connector->dpms)
3638 connector->dpms = mode;
3640 /* Only need to change hw state when actually enabled */
3641 if (encoder->base.crtc)
3642 intel_encoder_dpms(encoder, mode);
3644 WARN_ON(encoder->connectors_active != false);
3646 intel_modeset_check_state(connector->dev);
3649 /* Simple connector->get_hw_state implementation for encoders that support only
3650 * one connector and no cloning and hence the encoder state determines the state
3651 * of the connector. */
3652 bool intel_connector_get_hw_state(struct intel_connector *connector)
3655 struct intel_encoder *encoder = connector->encoder;
3657 return encoder->get_hw_state(encoder, &pipe);
3660 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3661 const struct drm_display_mode *mode,
3662 struct drm_display_mode *adjusted_mode)
3664 struct drm_device *dev = crtc->dev;
3666 if (HAS_PCH_SPLIT(dev)) {
3667 /* FDI link clock is fixed at 2.7G */
3668 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3672 /* All interlaced capable intel hw wants timings in frames. Note though
3673 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3674 * timings, so we need to be careful not to clobber these.*/
3675 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3676 drm_mode_set_crtcinfo(adjusted_mode, 0);
3678 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3679 * with a hsync front porch of 0.
3681 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3682 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3688 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3690 return 400000; /* FIXME */
3693 static int i945_get_display_clock_speed(struct drm_device *dev)
3698 static int i915_get_display_clock_speed(struct drm_device *dev)
3703 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3708 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3712 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3714 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3717 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3718 case GC_DISPLAY_CLOCK_333_MHZ:
3721 case GC_DISPLAY_CLOCK_190_200_MHZ:
3727 static int i865_get_display_clock_speed(struct drm_device *dev)
3732 static int i855_get_display_clock_speed(struct drm_device *dev)
3735 /* Assume that the hardware is in the high speed state. This
3736 * should be the default.
3738 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3739 case GC_CLOCK_133_200:
3740 case GC_CLOCK_100_200:
3742 case GC_CLOCK_166_250:
3744 case GC_CLOCK_100_133:
3748 /* Shouldn't happen */
3752 static int i830_get_display_clock_speed(struct drm_device *dev)
3766 fdi_reduce_ratio(u32 *num, u32 *den)
3768 while (*num > 0xffffff || *den > 0xffffff) {
3775 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3776 int link_clock, struct fdi_m_n *m_n)
3778 m_n->tu = 64; /* default size */
3780 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3781 m_n->gmch_m = bits_per_pixel * pixel_clock;
3782 m_n->gmch_n = link_clock * nlanes * 8;
3783 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3785 m_n->link_m = pixel_clock;
3786 m_n->link_n = link_clock;
3787 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3790 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3792 if (i915_panel_use_ssc >= 0)
3793 return i915_panel_use_ssc != 0;
3794 return dev_priv->lvds_use_ssc
3795 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3799 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3800 * @crtc: CRTC structure
3801 * @mode: requested mode
3803 * A pipe may be connected to one or more outputs. Based on the depth of the
3804 * attached framebuffer, choose a good color depth to use on the pipe.
3806 * If possible, match the pipe depth to the fb depth. In some cases, this
3807 * isn't ideal, because the connected output supports a lesser or restricted
3808 * set of depths. Resolve that here:
3809 * LVDS typically supports only 6bpc, so clamp down in that case
3810 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3811 * Displays may support a restricted set as well, check EDID and clamp as
3813 * DP may want to dither down to 6bpc to fit larger modes
3816 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3817 * true if they don't match).
3819 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3820 struct drm_framebuffer *fb,
3821 unsigned int *pipe_bpp,
3822 struct drm_display_mode *mode)
3824 struct drm_device *dev = crtc->dev;
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 struct drm_connector *connector;
3827 struct intel_encoder *intel_encoder;
3828 unsigned int display_bpc = UINT_MAX, bpc;
3830 /* Walk the encoders & connectors on this crtc, get min bpc */
3831 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3833 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3834 unsigned int lvds_bpc;
3836 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3842 if (lvds_bpc < display_bpc) {
3843 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3844 display_bpc = lvds_bpc;
3849 /* Not one of the known troublemakers, check the EDID */
3850 list_for_each_entry(connector, &dev->mode_config.connector_list,
3852 if (connector->encoder != &intel_encoder->base)
3855 /* Don't use an invalid EDID bpc value */
3856 if (connector->display_info.bpc &&
3857 connector->display_info.bpc < display_bpc) {
3858 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3859 display_bpc = connector->display_info.bpc;
3864 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3865 * through, clamp it down. (Note: >12bpc will be caught below.)
3867 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3868 if (display_bpc > 8 && display_bpc < 12) {
3869 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3872 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3878 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3879 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3884 * We could just drive the pipe at the highest bpc all the time and
3885 * enable dithering as needed, but that costs bandwidth. So choose
3886 * the minimum value that expresses the full color range of the fb but
3887 * also stays within the max display bpc discovered above.
3890 switch (fb->depth) {
3892 bpc = 8; /* since we go through a colormap */
3896 bpc = 6; /* min is 18bpp */
3908 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3909 bpc = min((unsigned int)8, display_bpc);
3913 display_bpc = min(display_bpc, bpc);
3915 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3918 *pipe_bpp = display_bpc * 3;
3920 return display_bpc != bpc;
3923 static int vlv_get_refclk(struct drm_crtc *crtc)
3925 struct drm_device *dev = crtc->dev;
3926 struct drm_i915_private *dev_priv = dev->dev_private;
3927 int refclk = 27000; /* for DP & HDMI */
3929 return 100000; /* only one validated so far */
3931 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3933 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3934 if (intel_panel_use_ssc(dev_priv))
3938 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3945 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3947 struct drm_device *dev = crtc->dev;
3948 struct drm_i915_private *dev_priv = dev->dev_private;
3951 if (IS_VALLEYVIEW(dev)) {
3952 refclk = vlv_get_refclk(crtc);
3953 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3954 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3955 refclk = dev_priv->lvds_ssc_freq * 1000;
3956 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3958 } else if (!IS_GEN2(dev)) {
3967 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3968 intel_clock_t *clock)
3970 /* SDVO TV has fixed PLL values depend on its clock range,
3971 this mirrors vbios setting. */
3972 if (adjusted_mode->clock >= 100000
3973 && adjusted_mode->clock < 140500) {
3979 } else if (adjusted_mode->clock >= 140500
3980 && adjusted_mode->clock <= 200000) {
3989 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3990 intel_clock_t *clock,
3991 intel_clock_t *reduced_clock)
3993 struct drm_device *dev = crtc->dev;
3994 struct drm_i915_private *dev_priv = dev->dev_private;
3995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3996 int pipe = intel_crtc->pipe;
3999 if (IS_PINEVIEW(dev)) {
4000 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4002 fp2 = (1 << reduced_clock->n) << 16 |
4003 reduced_clock->m1 << 8 | reduced_clock->m2;
4005 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4007 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4011 I915_WRITE(FP0(pipe), fp);
4013 intel_crtc->lowfreq_avail = false;
4014 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4015 reduced_clock && i915_powersave) {
4016 I915_WRITE(FP1(pipe), fp2);
4017 intel_crtc->lowfreq_avail = true;
4019 I915_WRITE(FP1(pipe), fp);
4023 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4024 struct drm_display_mode *adjusted_mode)
4026 struct drm_device *dev = crtc->dev;
4027 struct drm_i915_private *dev_priv = dev->dev_private;
4028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4029 int pipe = intel_crtc->pipe;
4032 temp = I915_READ(LVDS);
4033 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4035 temp |= LVDS_PIPEB_SELECT;
4037 temp &= ~LVDS_PIPEB_SELECT;
4039 /* set the corresponsding LVDS_BORDER bit */
4040 temp |= dev_priv->lvds_border_bits;
4041 /* Set the B0-B3 data pairs corresponding to whether we're going to
4042 * set the DPLLs for dual-channel mode or not.
4045 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4047 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4049 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4050 * appropriately here, but we need to look more thoroughly into how
4051 * panels behave in the two modes.
4053 /* set the dithering flag on LVDS as needed */
4054 if (INTEL_INFO(dev)->gen >= 4) {
4055 if (dev_priv->lvds_dither)
4056 temp |= LVDS_ENABLE_DITHER;
4058 temp &= ~LVDS_ENABLE_DITHER;
4060 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4061 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4062 temp |= LVDS_HSYNC_POLARITY;
4063 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4064 temp |= LVDS_VSYNC_POLARITY;
4065 I915_WRITE(LVDS, temp);
4068 static void vlv_update_pll(struct drm_crtc *crtc,
4069 struct drm_display_mode *mode,
4070 struct drm_display_mode *adjusted_mode,
4071 intel_clock_t *clock, intel_clock_t *reduced_clock,
4074 struct drm_device *dev = crtc->dev;
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4077 int pipe = intel_crtc->pipe;
4078 u32 dpll, mdiv, pdiv;
4079 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4083 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4084 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4086 dpll = DPLL_VGA_MODE_DIS;
4087 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4088 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4089 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4091 I915_WRITE(DPLL(pipe), dpll);
4092 POSTING_READ(DPLL(pipe));
4101 * In Valleyview PLL and program lane counter registers are exposed
4102 * through DPIO interface
4104 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4105 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4106 mdiv |= ((bestn << DPIO_N_SHIFT));
4107 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4108 mdiv |= (1 << DPIO_K_SHIFT);
4109 mdiv |= DPIO_ENABLE_CALIBRATION;
4110 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4112 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4114 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4115 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4116 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4117 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4118 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4120 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4122 dpll |= DPLL_VCO_ENABLE;
4123 I915_WRITE(DPLL(pipe), dpll);
4124 POSTING_READ(DPLL(pipe));
4125 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4126 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4128 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4130 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4131 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4133 I915_WRITE(DPLL(pipe), dpll);
4135 /* Wait for the clocks to stabilize. */
4136 POSTING_READ(DPLL(pipe));
4141 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4143 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4147 I915_WRITE(DPLL_MD(pipe), temp);
4148 POSTING_READ(DPLL_MD(pipe));
4150 /* Now program lane control registers */
4151 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4152 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4157 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4159 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4164 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4168 static void i9xx_update_pll(struct drm_crtc *crtc,
4169 struct drm_display_mode *mode,
4170 struct drm_display_mode *adjusted_mode,
4171 intel_clock_t *clock, intel_clock_t *reduced_clock,
4174 struct drm_device *dev = crtc->dev;
4175 struct drm_i915_private *dev_priv = dev->dev_private;
4176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4177 int pipe = intel_crtc->pipe;
4181 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4183 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4184 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4186 dpll = DPLL_VGA_MODE_DIS;
4188 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4189 dpll |= DPLLB_MODE_LVDS;
4191 dpll |= DPLLB_MODE_DAC_SERIAL;
4193 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4194 if (pixel_multiplier > 1) {
4195 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4196 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4198 dpll |= DPLL_DVO_HIGH_SPEED;
4200 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4201 dpll |= DPLL_DVO_HIGH_SPEED;
4203 /* compute bitmask from p1 value */
4204 if (IS_PINEVIEW(dev))
4205 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4207 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4208 if (IS_G4X(dev) && reduced_clock)
4209 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4211 switch (clock->p2) {
4213 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4216 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4219 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4222 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4225 if (INTEL_INFO(dev)->gen >= 4)
4226 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4228 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4229 dpll |= PLL_REF_INPUT_TVCLKINBC;
4230 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4231 /* XXX: just matching BIOS for now */
4232 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4234 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4235 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4236 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4238 dpll |= PLL_REF_INPUT_DREFCLK;
4240 dpll |= DPLL_VCO_ENABLE;
4241 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4242 POSTING_READ(DPLL(pipe));
4245 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4246 * This is an exception to the general rule that mode_set doesn't turn
4249 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4250 intel_update_lvds(crtc, clock, adjusted_mode);
4252 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4253 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4255 I915_WRITE(DPLL(pipe), dpll);
4257 /* Wait for the clocks to stabilize. */
4258 POSTING_READ(DPLL(pipe));
4261 if (INTEL_INFO(dev)->gen >= 4) {
4264 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4266 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4270 I915_WRITE(DPLL_MD(pipe), temp);
4272 /* The pixel multiplier can only be updated once the
4273 * DPLL is enabled and the clocks are stable.
4275 * So write it again.
4277 I915_WRITE(DPLL(pipe), dpll);
4281 static void i8xx_update_pll(struct drm_crtc *crtc,
4282 struct drm_display_mode *adjusted_mode,
4283 intel_clock_t *clock, intel_clock_t *reduced_clock,
4286 struct drm_device *dev = crtc->dev;
4287 struct drm_i915_private *dev_priv = dev->dev_private;
4288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4289 int pipe = intel_crtc->pipe;
4292 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4294 dpll = DPLL_VGA_MODE_DIS;
4296 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4297 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4300 dpll |= PLL_P1_DIVIDE_BY_TWO;
4302 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4304 dpll |= PLL_P2_DIVIDE_BY_4;
4307 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4308 /* XXX: just matching BIOS for now */
4309 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4311 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4312 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4313 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4315 dpll |= PLL_REF_INPUT_DREFCLK;
4317 dpll |= DPLL_VCO_ENABLE;
4318 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4319 POSTING_READ(DPLL(pipe));
4322 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4323 * This is an exception to the general rule that mode_set doesn't turn
4326 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4327 intel_update_lvds(crtc, clock, adjusted_mode);
4329 I915_WRITE(DPLL(pipe), dpll);
4331 /* Wait for the clocks to stabilize. */
4332 POSTING_READ(DPLL(pipe));
4335 /* The pixel multiplier can only be updated once the
4336 * DPLL is enabled and the clocks are stable.
4338 * So write it again.
4340 I915_WRITE(DPLL(pipe), dpll);
4343 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4344 struct drm_display_mode *mode,
4345 struct drm_display_mode *adjusted_mode)
4347 struct drm_device *dev = intel_crtc->base.dev;
4348 struct drm_i915_private *dev_priv = dev->dev_private;
4349 enum pipe pipe = intel_crtc->pipe;
4350 uint32_t vsyncshift;
4352 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4353 /* the chip adds 2 halflines automatically */
4354 adjusted_mode->crtc_vtotal -= 1;
4355 adjusted_mode->crtc_vblank_end -= 1;
4356 vsyncshift = adjusted_mode->crtc_hsync_start
4357 - adjusted_mode->crtc_htotal / 2;
4362 if (INTEL_INFO(dev)->gen > 3)
4363 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4365 I915_WRITE(HTOTAL(pipe),
4366 (adjusted_mode->crtc_hdisplay - 1) |
4367 ((adjusted_mode->crtc_htotal - 1) << 16));
4368 I915_WRITE(HBLANK(pipe),
4369 (adjusted_mode->crtc_hblank_start - 1) |
4370 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4371 I915_WRITE(HSYNC(pipe),
4372 (adjusted_mode->crtc_hsync_start - 1) |
4373 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4375 I915_WRITE(VTOTAL(pipe),
4376 (adjusted_mode->crtc_vdisplay - 1) |
4377 ((adjusted_mode->crtc_vtotal - 1) << 16));
4378 I915_WRITE(VBLANK(pipe),
4379 (adjusted_mode->crtc_vblank_start - 1) |
4380 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4381 I915_WRITE(VSYNC(pipe),
4382 (adjusted_mode->crtc_vsync_start - 1) |
4383 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4385 /* pipesrc controls the size that is scaled from, which should
4386 * always be the user's requested size.
4388 I915_WRITE(PIPESRC(pipe),
4389 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4392 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4393 struct drm_display_mode *mode,
4394 struct drm_display_mode *adjusted_mode,
4396 struct drm_framebuffer *fb)
4398 struct drm_device *dev = crtc->dev;
4399 struct drm_i915_private *dev_priv = dev->dev_private;
4400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4401 int pipe = intel_crtc->pipe;
4402 int plane = intel_crtc->plane;
4403 int refclk, num_connectors = 0;
4404 intel_clock_t clock, reduced_clock;
4405 u32 dspcntr, pipeconf;
4406 bool ok, has_reduced_clock = false, is_sdvo = false;
4407 bool is_lvds = false, is_tv = false, is_dp = false;
4408 struct intel_encoder *encoder;
4409 const intel_limit_t *limit;
4412 for_each_encoder_on_crtc(dev, crtc, encoder) {
4413 switch (encoder->type) {
4414 case INTEL_OUTPUT_LVDS:
4417 case INTEL_OUTPUT_SDVO:
4418 case INTEL_OUTPUT_HDMI:
4420 if (encoder->needs_tv_clock)
4423 case INTEL_OUTPUT_TVOUT:
4426 case INTEL_OUTPUT_DISPLAYPORT:
4434 refclk = i9xx_get_refclk(crtc, num_connectors);
4437 * Returns a set of divisors for the desired target clock with the given
4438 * refclk, or FALSE. The returned values represent the clock equation:
4439 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4441 limit = intel_limit(crtc, refclk);
4442 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4445 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4449 /* Ensure that the cursor is valid for the new mode before changing... */
4450 intel_crtc_update_cursor(crtc, true);
4452 if (is_lvds && dev_priv->lvds_downclock_avail) {
4454 * Ensure we match the reduced clock's P to the target clock.
4455 * If the clocks don't match, we can't switch the display clock
4456 * by using the FP0/FP1. In such case we will disable the LVDS
4457 * downclock feature.
4459 has_reduced_clock = limit->find_pll(limit, crtc,
4460 dev_priv->lvds_downclock,
4466 if (is_sdvo && is_tv)
4467 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4470 i8xx_update_pll(crtc, adjusted_mode, &clock,
4471 has_reduced_clock ? &reduced_clock : NULL,
4473 else if (IS_VALLEYVIEW(dev))
4474 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4475 has_reduced_clock ? &reduced_clock : NULL,
4478 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4479 has_reduced_clock ? &reduced_clock : NULL,
4482 /* setup pipeconf */
4483 pipeconf = I915_READ(PIPECONF(pipe));
4485 /* Set up the display plane register */
4486 dspcntr = DISPPLANE_GAMMA_ENABLE;
4489 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4491 dspcntr |= DISPPLANE_SEL_PIPE_B;
4493 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4494 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4497 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4501 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4502 pipeconf |= PIPECONF_DOUBLE_WIDE;
4504 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4507 /* default to 8bpc */
4508 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4510 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4511 pipeconf |= PIPECONF_BPP_6 |
4512 PIPECONF_DITHER_EN |
4513 PIPECONF_DITHER_TYPE_SP;
4517 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4518 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4519 pipeconf |= PIPECONF_BPP_6 |
4521 I965_PIPECONF_ACTIVE;
4525 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4526 drm_mode_debug_printmodeline(mode);
4528 if (HAS_PIPE_CXSR(dev)) {
4529 if (intel_crtc->lowfreq_avail) {
4530 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4531 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4533 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4534 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4538 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4539 if (!IS_GEN2(dev) &&
4540 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4541 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4543 pipeconf |= PIPECONF_PROGRESSIVE;
4545 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4547 /* pipesrc and dspsize control the size that is scaled from,
4548 * which should always be the user's requested size.
4550 I915_WRITE(DSPSIZE(plane),
4551 ((mode->vdisplay - 1) << 16) |
4552 (mode->hdisplay - 1));
4553 I915_WRITE(DSPPOS(plane), 0);
4555 I915_WRITE(PIPECONF(pipe), pipeconf);
4556 POSTING_READ(PIPECONF(pipe));
4557 intel_enable_pipe(dev_priv, pipe, false);
4559 intel_wait_for_vblank(dev, pipe);
4561 I915_WRITE(DSPCNTR(plane), dspcntr);
4562 POSTING_READ(DSPCNTR(plane));
4564 ret = intel_pipe_set_base(crtc, x, y, fb);
4566 intel_update_watermarks(dev);
4572 * Initialize reference clocks when the driver loads
4574 void ironlake_init_pch_refclk(struct drm_device *dev)
4576 struct drm_i915_private *dev_priv = dev->dev_private;
4577 struct drm_mode_config *mode_config = &dev->mode_config;
4578 struct intel_encoder *encoder;
4580 bool has_lvds = false;
4581 bool has_cpu_edp = false;
4582 bool has_pch_edp = false;
4583 bool has_panel = false;
4584 bool has_ck505 = false;
4585 bool can_ssc = false;
4587 /* We need to take the global config into account */
4588 list_for_each_entry(encoder, &mode_config->encoder_list,
4590 switch (encoder->type) {
4591 case INTEL_OUTPUT_LVDS:
4595 case INTEL_OUTPUT_EDP:
4597 if (intel_encoder_is_pch_edp(&encoder->base))
4605 if (HAS_PCH_IBX(dev)) {
4606 has_ck505 = dev_priv->display_clock_mode;
4607 can_ssc = has_ck505;
4613 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4614 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4617 /* Ironlake: try to setup display ref clock before DPLL
4618 * enabling. This is only under driver's control after
4619 * PCH B stepping, previous chipset stepping should be
4620 * ignoring this setting.
4622 temp = I915_READ(PCH_DREF_CONTROL);
4623 /* Always enable nonspread source */
4624 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4627 temp |= DREF_NONSPREAD_CK505_ENABLE;
4629 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4632 temp &= ~DREF_SSC_SOURCE_MASK;
4633 temp |= DREF_SSC_SOURCE_ENABLE;
4635 /* SSC must be turned on before enabling the CPU output */
4636 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4637 DRM_DEBUG_KMS("Using SSC on panel\n");
4638 temp |= DREF_SSC1_ENABLE;
4640 temp &= ~DREF_SSC1_ENABLE;
4642 /* Get SSC going before enabling the outputs */
4643 I915_WRITE(PCH_DREF_CONTROL, temp);
4644 POSTING_READ(PCH_DREF_CONTROL);
4647 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4649 /* Enable CPU source on CPU attached eDP */
4651 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4652 DRM_DEBUG_KMS("Using SSC on eDP\n");
4653 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4656 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4658 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4660 I915_WRITE(PCH_DREF_CONTROL, temp);
4661 POSTING_READ(PCH_DREF_CONTROL);
4664 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4666 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4668 /* Turn off CPU output */
4669 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4671 I915_WRITE(PCH_DREF_CONTROL, temp);
4672 POSTING_READ(PCH_DREF_CONTROL);
4675 /* Turn off the SSC source */
4676 temp &= ~DREF_SSC_SOURCE_MASK;
4677 temp |= DREF_SSC_SOURCE_DISABLE;
4680 temp &= ~ DREF_SSC1_ENABLE;
4682 I915_WRITE(PCH_DREF_CONTROL, temp);
4683 POSTING_READ(PCH_DREF_CONTROL);
4688 static int ironlake_get_refclk(struct drm_crtc *crtc)
4690 struct drm_device *dev = crtc->dev;
4691 struct drm_i915_private *dev_priv = dev->dev_private;
4692 struct intel_encoder *encoder;
4693 struct intel_encoder *edp_encoder = NULL;
4694 int num_connectors = 0;
4695 bool is_lvds = false;
4697 for_each_encoder_on_crtc(dev, crtc, encoder) {
4698 switch (encoder->type) {
4699 case INTEL_OUTPUT_LVDS:
4702 case INTEL_OUTPUT_EDP:
4703 edp_encoder = encoder;
4709 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4710 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4711 dev_priv->lvds_ssc_freq);
4712 return dev_priv->lvds_ssc_freq * 1000;
4718 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4719 struct drm_display_mode *adjusted_mode,
4722 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4724 int pipe = intel_crtc->pipe;
4727 val = I915_READ(PIPECONF(pipe));
4729 val &= ~PIPE_BPC_MASK;
4730 switch (intel_crtc->bpp) {
4744 /* Case prevented by intel_choose_pipe_bpp_dither. */
4748 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4750 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4752 val &= ~PIPECONF_INTERLACE_MASK;
4753 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4754 val |= PIPECONF_INTERLACED_ILK;
4756 val |= PIPECONF_PROGRESSIVE;
4758 I915_WRITE(PIPECONF(pipe), val);
4759 POSTING_READ(PIPECONF(pipe));
4762 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4763 struct drm_display_mode *adjusted_mode,
4766 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4768 int pipe = intel_crtc->pipe;
4771 val = I915_READ(PIPECONF(pipe));
4773 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4775 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4777 val &= ~PIPECONF_INTERLACE_MASK_HSW;
4778 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4779 val |= PIPECONF_INTERLACED_ILK;
4781 val |= PIPECONF_PROGRESSIVE;
4783 I915_WRITE(PIPECONF(pipe), val);
4784 POSTING_READ(PIPECONF(pipe));
4787 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4788 struct drm_display_mode *adjusted_mode,
4789 intel_clock_t *clock,
4790 bool *has_reduced_clock,
4791 intel_clock_t *reduced_clock)
4793 struct drm_device *dev = crtc->dev;
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795 struct intel_encoder *intel_encoder;
4797 const intel_limit_t *limit;
4798 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4800 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4801 switch (intel_encoder->type) {
4802 case INTEL_OUTPUT_LVDS:
4805 case INTEL_OUTPUT_SDVO:
4806 case INTEL_OUTPUT_HDMI:
4808 if (intel_encoder->needs_tv_clock)
4811 case INTEL_OUTPUT_TVOUT:
4817 refclk = ironlake_get_refclk(crtc);
4820 * Returns a set of divisors for the desired target clock with the given
4821 * refclk, or FALSE. The returned values represent the clock equation:
4822 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4824 limit = intel_limit(crtc, refclk);
4825 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4830 if (is_lvds && dev_priv->lvds_downclock_avail) {
4832 * Ensure we match the reduced clock's P to the target clock.
4833 * If the clocks don't match, we can't switch the display clock
4834 * by using the FP0/FP1. In such case we will disable the LVDS
4835 * downclock feature.
4837 *has_reduced_clock = limit->find_pll(limit, crtc,
4838 dev_priv->lvds_downclock,
4844 if (is_sdvo && is_tv)
4845 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4850 static void ironlake_set_m_n(struct drm_crtc *crtc,
4851 struct drm_display_mode *mode,
4852 struct drm_display_mode *adjusted_mode)
4854 struct drm_device *dev = crtc->dev;
4855 struct drm_i915_private *dev_priv = dev->dev_private;
4856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4857 enum pipe pipe = intel_crtc->pipe;
4858 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4859 struct fdi_m_n m_n = {0};
4860 int target_clock, pixel_multiplier, lane, link_bw;
4861 bool is_dp = false, is_cpu_edp = false;
4863 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4864 switch (intel_encoder->type) {
4865 case INTEL_OUTPUT_DISPLAYPORT:
4868 case INTEL_OUTPUT_EDP:
4870 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4872 edp_encoder = intel_encoder;
4878 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4880 /* CPU eDP doesn't require FDI link, so just set DP M/N
4881 according to current link config */
4883 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4885 /* FDI is a binary signal running at ~2.7GHz, encoding
4886 * each output octet as 10 bits. The actual frequency
4887 * is stored as a divider into a 100MHz clock, and the
4888 * mode pixel clock is stored in units of 1KHz.
4889 * Hence the bw of each lane in terms of the mode signal
4892 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4895 /* [e]DP over FDI requires target mode clock instead of link clock. */
4897 target_clock = intel_edp_target_clock(edp_encoder, mode);
4899 target_clock = mode->clock;
4901 target_clock = adjusted_mode->clock;
4905 * Account for spread spectrum to avoid
4906 * oversubscribing the link. Max center spread
4907 * is 2.5%; use 5% for safety's sake.
4909 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4910 lane = bps / (link_bw * 8) + 1;
4913 intel_crtc->fdi_lanes = lane;
4915 if (pixel_multiplier > 1)
4916 link_bw *= pixel_multiplier;
4917 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4920 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4921 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4922 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4923 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4926 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4927 struct drm_display_mode *adjusted_mode,
4928 intel_clock_t *clock, u32 fp)
4930 struct drm_crtc *crtc = &intel_crtc->base;
4931 struct drm_device *dev = crtc->dev;
4932 struct drm_i915_private *dev_priv = dev->dev_private;
4933 struct intel_encoder *intel_encoder;
4935 int factor, pixel_multiplier, num_connectors = 0;
4936 bool is_lvds = false, is_sdvo = false, is_tv = false;
4937 bool is_dp = false, is_cpu_edp = false;
4939 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4940 switch (intel_encoder->type) {
4941 case INTEL_OUTPUT_LVDS:
4944 case INTEL_OUTPUT_SDVO:
4945 case INTEL_OUTPUT_HDMI:
4947 if (intel_encoder->needs_tv_clock)
4950 case INTEL_OUTPUT_TVOUT:
4953 case INTEL_OUTPUT_DISPLAYPORT:
4956 case INTEL_OUTPUT_EDP:
4958 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4966 /* Enable autotuning of the PLL clock (if permissible) */
4969 if ((intel_panel_use_ssc(dev_priv) &&
4970 dev_priv->lvds_ssc_freq == 100) ||
4971 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4973 } else if (is_sdvo && is_tv)
4976 if (clock->m < factor * clock->n)
4982 dpll |= DPLLB_MODE_LVDS;
4984 dpll |= DPLLB_MODE_DAC_SERIAL;
4986 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4987 if (pixel_multiplier > 1) {
4988 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4990 dpll |= DPLL_DVO_HIGH_SPEED;
4992 if (is_dp && !is_cpu_edp)
4993 dpll |= DPLL_DVO_HIGH_SPEED;
4995 /* compute bitmask from p1 value */
4996 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4998 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5000 switch (clock->p2) {
5002 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5005 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5008 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5011 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5015 if (is_sdvo && is_tv)
5016 dpll |= PLL_REF_INPUT_TVCLKINBC;
5018 /* XXX: just matching BIOS for now */
5019 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5021 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5022 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5024 dpll |= PLL_REF_INPUT_DREFCLK;
5029 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5030 struct drm_display_mode *mode,
5031 struct drm_display_mode *adjusted_mode,
5033 struct drm_framebuffer *fb)
5035 struct drm_device *dev = crtc->dev;
5036 struct drm_i915_private *dev_priv = dev->dev_private;
5037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5038 int pipe = intel_crtc->pipe;
5039 int plane = intel_crtc->plane;
5040 int num_connectors = 0;
5041 intel_clock_t clock, reduced_clock;
5042 u32 dpll, fp = 0, fp2 = 0;
5043 bool ok, has_reduced_clock = false;
5044 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5045 struct intel_encoder *encoder;
5050 for_each_encoder_on_crtc(dev, crtc, encoder) {
5051 switch (encoder->type) {
5052 case INTEL_OUTPUT_LVDS:
5055 case INTEL_OUTPUT_DISPLAYPORT:
5058 case INTEL_OUTPUT_EDP:
5060 if (!intel_encoder_is_pch_edp(&encoder->base))
5068 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5069 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5071 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5072 &has_reduced_clock, &reduced_clock);
5074 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5078 /* Ensure that the cursor is valid for the new mode before changing... */
5079 intel_crtc_update_cursor(crtc, true);
5081 /* determine panel color depth */
5082 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5083 if (is_lvds && dev_priv->lvds_dither)
5086 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5087 if (has_reduced_clock)
5088 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5091 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5093 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5094 drm_mode_debug_printmodeline(mode);
5096 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5098 struct intel_pch_pll *pll;
5100 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5102 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5107 intel_put_pch_pll(intel_crtc);
5109 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5110 * This is an exception to the general rule that mode_set doesn't turn
5114 temp = I915_READ(PCH_LVDS);
5115 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5116 if (HAS_PCH_CPT(dev)) {
5117 temp &= ~PORT_TRANS_SEL_MASK;
5118 temp |= PORT_TRANS_SEL_CPT(pipe);
5121 temp |= LVDS_PIPEB_SELECT;
5123 temp &= ~LVDS_PIPEB_SELECT;
5126 /* set the corresponsding LVDS_BORDER bit */
5127 temp |= dev_priv->lvds_border_bits;
5128 /* Set the B0-B3 data pairs corresponding to whether we're going to
5129 * set the DPLLs for dual-channel mode or not.
5132 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5134 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5136 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5137 * appropriately here, but we need to look more thoroughly into how
5138 * panels behave in the two modes.
5140 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5141 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5142 temp |= LVDS_HSYNC_POLARITY;
5143 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5144 temp |= LVDS_VSYNC_POLARITY;
5145 I915_WRITE(PCH_LVDS, temp);
5148 if (is_dp && !is_cpu_edp) {
5149 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5151 /* For non-DP output, clear any trans DP clock recovery setting.*/
5152 I915_WRITE(TRANSDATA_M1(pipe), 0);
5153 I915_WRITE(TRANSDATA_N1(pipe), 0);
5154 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5155 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5158 if (intel_crtc->pch_pll) {
5159 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5161 /* Wait for the clocks to stabilize. */
5162 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5165 /* The pixel multiplier can only be updated once the
5166 * DPLL is enabled and the clocks are stable.
5168 * So write it again.
5170 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5173 intel_crtc->lowfreq_avail = false;
5174 if (intel_crtc->pch_pll) {
5175 if (is_lvds && has_reduced_clock && i915_powersave) {
5176 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5177 intel_crtc->lowfreq_avail = true;
5179 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5183 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5185 ironlake_set_m_n(crtc, mode, adjusted_mode);
5188 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5190 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5192 intel_wait_for_vblank(dev, pipe);
5194 /* Set up the display plane register */
5195 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5196 POSTING_READ(DSPCNTR(plane));
5198 ret = intel_pipe_set_base(crtc, x, y, fb);
5200 intel_update_watermarks(dev);
5202 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5207 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5208 struct drm_display_mode *mode,
5209 struct drm_display_mode *adjusted_mode,
5211 struct drm_framebuffer *fb)
5213 struct drm_device *dev = crtc->dev;
5214 struct drm_i915_private *dev_priv = dev->dev_private;
5215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5216 int pipe = intel_crtc->pipe;
5217 int plane = intel_crtc->plane;
5218 int num_connectors = 0;
5219 intel_clock_t clock, reduced_clock;
5220 u32 dpll = 0, fp = 0, fp2 = 0;
5221 bool ok, has_reduced_clock = false;
5222 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5223 struct intel_encoder *encoder;
5228 for_each_encoder_on_crtc(dev, crtc, encoder) {
5229 switch (encoder->type) {
5230 case INTEL_OUTPUT_LVDS:
5233 case INTEL_OUTPUT_DISPLAYPORT:
5236 case INTEL_OUTPUT_EDP:
5238 if (!intel_encoder_is_pch_edp(&encoder->base))
5246 /* We are not sure yet this won't happen. */
5247 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5248 INTEL_PCH_TYPE(dev));
5250 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5251 num_connectors, pipe_name(pipe));
5253 WARN_ON(I915_READ(PIPECONF(pipe)) &
5254 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5256 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5258 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5261 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5262 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5266 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5271 /* Ensure that the cursor is valid for the new mode before changing... */
5272 intel_crtc_update_cursor(crtc, true);
5274 /* determine panel color depth */
5275 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5276 if (is_lvds && dev_priv->lvds_dither)
5279 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5280 drm_mode_debug_printmodeline(mode);
5282 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5283 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5284 if (has_reduced_clock)
5285 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5288 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5291 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5292 * own on pre-Haswell/LPT generation */
5294 struct intel_pch_pll *pll;
5296 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5298 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5303 intel_put_pch_pll(intel_crtc);
5305 /* The LVDS pin pair needs to be on before the DPLLs are
5306 * enabled. This is an exception to the general rule that
5307 * mode_set doesn't turn things on.
5310 temp = I915_READ(PCH_LVDS);
5311 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5312 if (HAS_PCH_CPT(dev)) {
5313 temp &= ~PORT_TRANS_SEL_MASK;
5314 temp |= PORT_TRANS_SEL_CPT(pipe);
5317 temp |= LVDS_PIPEB_SELECT;
5319 temp &= ~LVDS_PIPEB_SELECT;
5322 /* set the corresponsding LVDS_BORDER bit */
5323 temp |= dev_priv->lvds_border_bits;
5324 /* Set the B0-B3 data pairs corresponding to whether
5325 * we're going to set the DPLLs for dual-channel mode or
5329 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5331 temp &= ~(LVDS_B0B3_POWER_UP |
5332 LVDS_CLKB_POWER_UP);
5334 /* It would be nice to set 24 vs 18-bit mode
5335 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5336 * look more thoroughly into how panels behave in the
5339 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5340 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5341 temp |= LVDS_HSYNC_POLARITY;
5342 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5343 temp |= LVDS_VSYNC_POLARITY;
5344 I915_WRITE(PCH_LVDS, temp);
5348 if (is_dp && !is_cpu_edp) {
5349 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5351 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5352 /* For non-DP output, clear any trans DP clock recovery
5354 I915_WRITE(TRANSDATA_M1(pipe), 0);
5355 I915_WRITE(TRANSDATA_N1(pipe), 0);
5356 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5357 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5361 intel_crtc->lowfreq_avail = false;
5362 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5363 if (intel_crtc->pch_pll) {
5364 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5366 /* Wait for the clocks to stabilize. */
5367 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5370 /* The pixel multiplier can only be updated once the
5371 * DPLL is enabled and the clocks are stable.
5373 * So write it again.
5375 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5378 if (intel_crtc->pch_pll) {
5379 if (is_lvds && has_reduced_clock && i915_powersave) {
5380 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5381 intel_crtc->lowfreq_avail = true;
5383 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5388 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5390 if (!is_dp || is_cpu_edp)
5391 ironlake_set_m_n(crtc, mode, adjusted_mode);
5393 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5395 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5397 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5399 /* Set up the display plane register */
5400 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5401 POSTING_READ(DSPCNTR(plane));
5403 ret = intel_pipe_set_base(crtc, x, y, fb);
5405 intel_update_watermarks(dev);
5407 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5412 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5413 struct drm_display_mode *mode,
5414 struct drm_display_mode *adjusted_mode,
5416 struct drm_framebuffer *fb)
5418 struct drm_device *dev = crtc->dev;
5419 struct drm_i915_private *dev_priv = dev->dev_private;
5420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5421 int pipe = intel_crtc->pipe;
5424 drm_vblank_pre_modeset(dev, pipe);
5426 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5428 drm_vblank_post_modeset(dev, pipe);
5433 static bool intel_eld_uptodate(struct drm_connector *connector,
5434 int reg_eldv, uint32_t bits_eldv,
5435 int reg_elda, uint32_t bits_elda,
5438 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5439 uint8_t *eld = connector->eld;
5442 i = I915_READ(reg_eldv);
5451 i = I915_READ(reg_elda);
5453 I915_WRITE(reg_elda, i);
5455 for (i = 0; i < eld[2]; i++)
5456 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5462 static void g4x_write_eld(struct drm_connector *connector,
5463 struct drm_crtc *crtc)
5465 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5466 uint8_t *eld = connector->eld;
5471 i = I915_READ(G4X_AUD_VID_DID);
5473 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5474 eldv = G4X_ELDV_DEVCL_DEVBLC;
5476 eldv = G4X_ELDV_DEVCTG;
5478 if (intel_eld_uptodate(connector,
5479 G4X_AUD_CNTL_ST, eldv,
5480 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5481 G4X_HDMIW_HDMIEDID))
5484 i = I915_READ(G4X_AUD_CNTL_ST);
5485 i &= ~(eldv | G4X_ELD_ADDR);
5486 len = (i >> 9) & 0x1f; /* ELD buffer size */
5487 I915_WRITE(G4X_AUD_CNTL_ST, i);
5492 len = min_t(uint8_t, eld[2], len);
5493 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5494 for (i = 0; i < len; i++)
5495 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5497 i = I915_READ(G4X_AUD_CNTL_ST);
5499 I915_WRITE(G4X_AUD_CNTL_ST, i);
5502 static void haswell_write_eld(struct drm_connector *connector,
5503 struct drm_crtc *crtc)
5505 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5506 uint8_t *eld = connector->eld;
5507 struct drm_device *dev = crtc->dev;
5511 int pipe = to_intel_crtc(crtc)->pipe;
5514 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5515 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5516 int aud_config = HSW_AUD_CFG(pipe);
5517 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5520 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5522 /* Audio output enable */
5523 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5524 tmp = I915_READ(aud_cntrl_st2);
5525 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5526 I915_WRITE(aud_cntrl_st2, tmp);
5528 /* Wait for 1 vertical blank */
5529 intel_wait_for_vblank(dev, pipe);
5531 /* Set ELD valid state */
5532 tmp = I915_READ(aud_cntrl_st2);
5533 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5534 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5535 I915_WRITE(aud_cntrl_st2, tmp);
5536 tmp = I915_READ(aud_cntrl_st2);
5537 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5539 /* Enable HDMI mode */
5540 tmp = I915_READ(aud_config);
5541 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5542 /* clear N_programing_enable and N_value_index */
5543 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5544 I915_WRITE(aud_config, tmp);
5546 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5548 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5551 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5552 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5553 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5555 I915_WRITE(aud_config, 0);
5557 if (intel_eld_uptodate(connector,
5558 aud_cntrl_st2, eldv,
5559 aud_cntl_st, IBX_ELD_ADDRESS,
5563 i = I915_READ(aud_cntrl_st2);
5565 I915_WRITE(aud_cntrl_st2, i);
5570 i = I915_READ(aud_cntl_st);
5571 i &= ~IBX_ELD_ADDRESS;
5572 I915_WRITE(aud_cntl_st, i);
5573 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5574 DRM_DEBUG_DRIVER("port num:%d\n", i);
5576 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5577 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5578 for (i = 0; i < len; i++)
5579 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5581 i = I915_READ(aud_cntrl_st2);
5583 I915_WRITE(aud_cntrl_st2, i);
5587 static void ironlake_write_eld(struct drm_connector *connector,
5588 struct drm_crtc *crtc)
5590 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5591 uint8_t *eld = connector->eld;
5599 int pipe = to_intel_crtc(crtc)->pipe;
5601 if (HAS_PCH_IBX(connector->dev)) {
5602 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5603 aud_config = IBX_AUD_CFG(pipe);
5604 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5605 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5607 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5608 aud_config = CPT_AUD_CFG(pipe);
5609 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5610 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5613 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5615 i = I915_READ(aud_cntl_st);
5616 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5618 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5619 /* operate blindly on all ports */
5620 eldv = IBX_ELD_VALIDB;
5621 eldv |= IBX_ELD_VALIDB << 4;
5622 eldv |= IBX_ELD_VALIDB << 8;
5624 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5625 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5628 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5629 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5630 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5631 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5633 I915_WRITE(aud_config, 0);
5635 if (intel_eld_uptodate(connector,
5636 aud_cntrl_st2, eldv,
5637 aud_cntl_st, IBX_ELD_ADDRESS,
5641 i = I915_READ(aud_cntrl_st2);
5643 I915_WRITE(aud_cntrl_st2, i);
5648 i = I915_READ(aud_cntl_st);
5649 i &= ~IBX_ELD_ADDRESS;
5650 I915_WRITE(aud_cntl_st, i);
5652 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5653 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5654 for (i = 0; i < len; i++)
5655 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5657 i = I915_READ(aud_cntrl_st2);
5659 I915_WRITE(aud_cntrl_st2, i);
5662 void intel_write_eld(struct drm_encoder *encoder,
5663 struct drm_display_mode *mode)
5665 struct drm_crtc *crtc = encoder->crtc;
5666 struct drm_connector *connector;
5667 struct drm_device *dev = encoder->dev;
5668 struct drm_i915_private *dev_priv = dev->dev_private;
5670 connector = drm_select_eld(encoder, mode);
5674 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5676 drm_get_connector_name(connector),
5677 connector->encoder->base.id,
5678 drm_get_encoder_name(connector->encoder));
5680 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5682 if (dev_priv->display.write_eld)
5683 dev_priv->display.write_eld(connector, crtc);
5686 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5687 void intel_crtc_load_lut(struct drm_crtc *crtc)
5689 struct drm_device *dev = crtc->dev;
5690 struct drm_i915_private *dev_priv = dev->dev_private;
5691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5692 int palreg = PALETTE(intel_crtc->pipe);
5695 /* The clocks have to be on to load the palette. */
5696 if (!crtc->enabled || !intel_crtc->active)
5699 /* use legacy palette for Ironlake */
5700 if (HAS_PCH_SPLIT(dev))
5701 palreg = LGC_PALETTE(intel_crtc->pipe);
5703 for (i = 0; i < 256; i++) {
5704 I915_WRITE(palreg + 4 * i,
5705 (intel_crtc->lut_r[i] << 16) |
5706 (intel_crtc->lut_g[i] << 8) |
5707 intel_crtc->lut_b[i]);
5711 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5713 struct drm_device *dev = crtc->dev;
5714 struct drm_i915_private *dev_priv = dev->dev_private;
5715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5716 bool visible = base != 0;
5719 if (intel_crtc->cursor_visible == visible)
5722 cntl = I915_READ(_CURACNTR);
5724 /* On these chipsets we can only modify the base whilst
5725 * the cursor is disabled.
5727 I915_WRITE(_CURABASE, base);
5729 cntl &= ~(CURSOR_FORMAT_MASK);
5730 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5731 cntl |= CURSOR_ENABLE |
5732 CURSOR_GAMMA_ENABLE |
5735 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5736 I915_WRITE(_CURACNTR, cntl);
5738 intel_crtc->cursor_visible = visible;
5741 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5743 struct drm_device *dev = crtc->dev;
5744 struct drm_i915_private *dev_priv = dev->dev_private;
5745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5746 int pipe = intel_crtc->pipe;
5747 bool visible = base != 0;
5749 if (intel_crtc->cursor_visible != visible) {
5750 uint32_t cntl = I915_READ(CURCNTR(pipe));
5752 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5753 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5754 cntl |= pipe << 28; /* Connect to correct pipe */
5756 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5757 cntl |= CURSOR_MODE_DISABLE;
5759 I915_WRITE(CURCNTR(pipe), cntl);
5761 intel_crtc->cursor_visible = visible;
5763 /* and commit changes on next vblank */
5764 I915_WRITE(CURBASE(pipe), base);
5767 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5769 struct drm_device *dev = crtc->dev;
5770 struct drm_i915_private *dev_priv = dev->dev_private;
5771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5772 int pipe = intel_crtc->pipe;
5773 bool visible = base != 0;
5775 if (intel_crtc->cursor_visible != visible) {
5776 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5778 cntl &= ~CURSOR_MODE;
5779 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5781 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5782 cntl |= CURSOR_MODE_DISABLE;
5784 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5786 intel_crtc->cursor_visible = visible;
5788 /* and commit changes on next vblank */
5789 I915_WRITE(CURBASE_IVB(pipe), base);
5792 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5793 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5796 struct drm_device *dev = crtc->dev;
5797 struct drm_i915_private *dev_priv = dev->dev_private;
5798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5799 int pipe = intel_crtc->pipe;
5800 int x = intel_crtc->cursor_x;
5801 int y = intel_crtc->cursor_y;
5807 if (on && crtc->enabled && crtc->fb) {
5808 base = intel_crtc->cursor_addr;
5809 if (x > (int) crtc->fb->width)
5812 if (y > (int) crtc->fb->height)
5818 if (x + intel_crtc->cursor_width < 0)
5821 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5824 pos |= x << CURSOR_X_SHIFT;
5827 if (y + intel_crtc->cursor_height < 0)
5830 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5833 pos |= y << CURSOR_Y_SHIFT;
5835 visible = base != 0;
5836 if (!visible && !intel_crtc->cursor_visible)
5839 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5840 I915_WRITE(CURPOS_IVB(pipe), pos);
5841 ivb_update_cursor(crtc, base);
5843 I915_WRITE(CURPOS(pipe), pos);
5844 if (IS_845G(dev) || IS_I865G(dev))
5845 i845_update_cursor(crtc, base);
5847 i9xx_update_cursor(crtc, base);
5851 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5852 struct drm_file *file,
5854 uint32_t width, uint32_t height)
5856 struct drm_device *dev = crtc->dev;
5857 struct drm_i915_private *dev_priv = dev->dev_private;
5858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5859 struct drm_i915_gem_object *obj;
5863 /* if we want to turn off the cursor ignore width and height */
5865 DRM_DEBUG_KMS("cursor off\n");
5868 mutex_lock(&dev->struct_mutex);
5872 /* Currently we only support 64x64 cursors */
5873 if (width != 64 || height != 64) {
5874 DRM_ERROR("we currently only support 64x64 cursors\n");
5878 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5879 if (&obj->base == NULL)
5882 if (obj->base.size < width * height * 4) {
5883 DRM_ERROR("buffer is to small\n");
5888 /* we only need to pin inside GTT if cursor is non-phy */
5889 mutex_lock(&dev->struct_mutex);
5890 if (!dev_priv->info->cursor_needs_physical) {
5891 if (obj->tiling_mode) {
5892 DRM_ERROR("cursor cannot be tiled\n");
5897 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5899 DRM_ERROR("failed to move cursor bo into the GTT\n");
5903 ret = i915_gem_object_put_fence(obj);
5905 DRM_ERROR("failed to release fence for cursor");
5909 addr = obj->gtt_offset;
5911 int align = IS_I830(dev) ? 16 * 1024 : 256;
5912 ret = i915_gem_attach_phys_object(dev, obj,
5913 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5916 DRM_ERROR("failed to attach phys object\n");
5919 addr = obj->phys_obj->handle->busaddr;
5923 I915_WRITE(CURSIZE, (height << 12) | width);
5926 if (intel_crtc->cursor_bo) {
5927 if (dev_priv->info->cursor_needs_physical) {
5928 if (intel_crtc->cursor_bo != obj)
5929 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5931 i915_gem_object_unpin(intel_crtc->cursor_bo);
5932 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5935 mutex_unlock(&dev->struct_mutex);
5937 intel_crtc->cursor_addr = addr;
5938 intel_crtc->cursor_bo = obj;
5939 intel_crtc->cursor_width = width;
5940 intel_crtc->cursor_height = height;
5942 intel_crtc_update_cursor(crtc, true);
5946 i915_gem_object_unpin(obj);
5948 mutex_unlock(&dev->struct_mutex);
5950 drm_gem_object_unreference_unlocked(&obj->base);
5954 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5958 intel_crtc->cursor_x = x;
5959 intel_crtc->cursor_y = y;
5961 intel_crtc_update_cursor(crtc, true);
5966 /** Sets the color ramps on behalf of RandR */
5967 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5968 u16 blue, int regno)
5970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5972 intel_crtc->lut_r[regno] = red >> 8;
5973 intel_crtc->lut_g[regno] = green >> 8;
5974 intel_crtc->lut_b[regno] = blue >> 8;
5977 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5978 u16 *blue, int regno)
5980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5982 *red = intel_crtc->lut_r[regno] << 8;
5983 *green = intel_crtc->lut_g[regno] << 8;
5984 *blue = intel_crtc->lut_b[regno] << 8;
5987 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5988 u16 *blue, uint32_t start, uint32_t size)
5990 int end = (start + size > 256) ? 256 : start + size, i;
5991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5993 for (i = start; i < end; i++) {
5994 intel_crtc->lut_r[i] = red[i] >> 8;
5995 intel_crtc->lut_g[i] = green[i] >> 8;
5996 intel_crtc->lut_b[i] = blue[i] >> 8;
5999 intel_crtc_load_lut(crtc);
6003 * Get a pipe with a simple mode set on it for doing load-based monitor
6006 * It will be up to the load-detect code to adjust the pipe as appropriate for
6007 * its requirements. The pipe will be connected to no other encoders.
6009 * Currently this code will only succeed if there is a pipe with no encoders
6010 * configured for it. In the future, it could choose to temporarily disable
6011 * some outputs to free up a pipe for its use.
6013 * \return crtc, or NULL if no pipes are available.
6016 /* VESA 640x480x72Hz mode to set on the pipe */
6017 static struct drm_display_mode load_detect_mode = {
6018 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6019 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6022 static struct drm_framebuffer *
6023 intel_framebuffer_create(struct drm_device *dev,
6024 struct drm_mode_fb_cmd2 *mode_cmd,
6025 struct drm_i915_gem_object *obj)
6027 struct intel_framebuffer *intel_fb;
6030 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6032 drm_gem_object_unreference_unlocked(&obj->base);
6033 return ERR_PTR(-ENOMEM);
6036 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6038 drm_gem_object_unreference_unlocked(&obj->base);
6040 return ERR_PTR(ret);
6043 return &intel_fb->base;
6047 intel_framebuffer_pitch_for_width(int width, int bpp)
6049 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6050 return ALIGN(pitch, 64);
6054 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6056 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6057 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6060 static struct drm_framebuffer *
6061 intel_framebuffer_create_for_mode(struct drm_device *dev,
6062 struct drm_display_mode *mode,
6065 struct drm_i915_gem_object *obj;
6066 struct drm_mode_fb_cmd2 mode_cmd;
6068 obj = i915_gem_alloc_object(dev,
6069 intel_framebuffer_size_for_mode(mode, bpp));
6071 return ERR_PTR(-ENOMEM);
6073 mode_cmd.width = mode->hdisplay;
6074 mode_cmd.height = mode->vdisplay;
6075 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6077 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6079 return intel_framebuffer_create(dev, &mode_cmd, obj);
6082 static struct drm_framebuffer *
6083 mode_fits_in_fbdev(struct drm_device *dev,
6084 struct drm_display_mode *mode)
6086 struct drm_i915_private *dev_priv = dev->dev_private;
6087 struct drm_i915_gem_object *obj;
6088 struct drm_framebuffer *fb;
6090 if (dev_priv->fbdev == NULL)
6093 obj = dev_priv->fbdev->ifb.obj;
6097 fb = &dev_priv->fbdev->ifb.base;
6098 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6099 fb->bits_per_pixel))
6102 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6108 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6109 struct drm_display_mode *mode,
6110 struct intel_load_detect_pipe *old)
6112 struct intel_crtc *intel_crtc;
6113 struct intel_encoder *intel_encoder =
6114 intel_attached_encoder(connector);
6115 struct drm_crtc *possible_crtc;
6116 struct drm_encoder *encoder = &intel_encoder->base;
6117 struct drm_crtc *crtc = NULL;
6118 struct drm_device *dev = encoder->dev;
6119 struct drm_framebuffer *fb;
6122 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6123 connector->base.id, drm_get_connector_name(connector),
6124 encoder->base.id, drm_get_encoder_name(encoder));
6127 * Algorithm gets a little messy:
6129 * - if the connector already has an assigned crtc, use it (but make
6130 * sure it's on first)
6132 * - try to find the first unused crtc that can drive this connector,
6133 * and use that if we find one
6136 /* See if we already have a CRTC for this connector */
6137 if (encoder->crtc) {
6138 crtc = encoder->crtc;
6140 old->dpms_mode = connector->dpms;
6141 old->load_detect_temp = false;
6143 /* Make sure the crtc and connector are running */
6144 if (connector->dpms != DRM_MODE_DPMS_ON)
6145 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6150 /* Find an unused one (if possible) */
6151 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6153 if (!(encoder->possible_crtcs & (1 << i)))
6155 if (!possible_crtc->enabled) {
6156 crtc = possible_crtc;
6162 * If we didn't find an unused CRTC, don't use any.
6165 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6169 intel_encoder->new_crtc = to_intel_crtc(crtc);
6170 to_intel_connector(connector)->new_encoder = intel_encoder;
6172 intel_crtc = to_intel_crtc(crtc);
6173 old->dpms_mode = connector->dpms;
6174 old->load_detect_temp = true;
6175 old->release_fb = NULL;
6178 mode = &load_detect_mode;
6180 /* We need a framebuffer large enough to accommodate all accesses
6181 * that the plane may generate whilst we perform load detection.
6182 * We can not rely on the fbcon either being present (we get called
6183 * during its initialisation to detect all boot displays, or it may
6184 * not even exist) or that it is large enough to satisfy the
6187 fb = mode_fits_in_fbdev(dev, mode);
6189 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6190 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6191 old->release_fb = fb;
6193 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6195 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6199 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6200 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6201 if (old->release_fb)
6202 old->release_fb->funcs->destroy(old->release_fb);
6206 /* let the connector get through one full cycle before testing */
6207 intel_wait_for_vblank(dev, intel_crtc->pipe);
6211 connector->encoder = NULL;
6212 encoder->crtc = NULL;
6216 void intel_release_load_detect_pipe(struct drm_connector *connector,
6217 struct intel_load_detect_pipe *old)
6219 struct intel_encoder *intel_encoder =
6220 intel_attached_encoder(connector);
6221 struct drm_encoder *encoder = &intel_encoder->base;
6223 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6224 connector->base.id, drm_get_connector_name(connector),
6225 encoder->base.id, drm_get_encoder_name(encoder));
6227 if (old->load_detect_temp) {
6228 struct drm_crtc *crtc = encoder->crtc;
6230 to_intel_connector(connector)->new_encoder = NULL;
6231 intel_encoder->new_crtc = NULL;
6232 intel_set_mode(crtc, NULL, 0, 0, NULL);
6234 if (old->release_fb)
6235 old->release_fb->funcs->destroy(old->release_fb);
6240 /* Switch crtc and encoder back off if necessary */
6241 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6242 connector->funcs->dpms(connector, old->dpms_mode);
6245 /* Returns the clock of the currently programmed mode of the given pipe. */
6246 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6248 struct drm_i915_private *dev_priv = dev->dev_private;
6249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6250 int pipe = intel_crtc->pipe;
6251 u32 dpll = I915_READ(DPLL(pipe));
6253 intel_clock_t clock;
6255 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6256 fp = I915_READ(FP0(pipe));
6258 fp = I915_READ(FP1(pipe));
6260 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6261 if (IS_PINEVIEW(dev)) {
6262 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6263 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6265 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6266 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6269 if (!IS_GEN2(dev)) {
6270 if (IS_PINEVIEW(dev))
6271 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6272 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6274 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6275 DPLL_FPA01_P1_POST_DIV_SHIFT);
6277 switch (dpll & DPLL_MODE_MASK) {
6278 case DPLLB_MODE_DAC_SERIAL:
6279 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6282 case DPLLB_MODE_LVDS:
6283 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6287 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6288 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6292 /* XXX: Handle the 100Mhz refclk */
6293 intel_clock(dev, 96000, &clock);
6295 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6298 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6299 DPLL_FPA01_P1_POST_DIV_SHIFT);
6302 if ((dpll & PLL_REF_INPUT_MASK) ==
6303 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6304 /* XXX: might not be 66MHz */
6305 intel_clock(dev, 66000, &clock);
6307 intel_clock(dev, 48000, &clock);
6309 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6312 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6313 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6315 if (dpll & PLL_P2_DIVIDE_BY_4)
6320 intel_clock(dev, 48000, &clock);
6324 /* XXX: It would be nice to validate the clocks, but we can't reuse
6325 * i830PllIsValid() because it relies on the xf86_config connector
6326 * configuration being accurate, which it isn't necessarily.
6332 /** Returns the currently programmed mode of the given pipe. */
6333 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6334 struct drm_crtc *crtc)
6336 struct drm_i915_private *dev_priv = dev->dev_private;
6337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6338 int pipe = intel_crtc->pipe;
6339 struct drm_display_mode *mode;
6340 int htot = I915_READ(HTOTAL(pipe));
6341 int hsync = I915_READ(HSYNC(pipe));
6342 int vtot = I915_READ(VTOTAL(pipe));
6343 int vsync = I915_READ(VSYNC(pipe));
6345 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6349 mode->clock = intel_crtc_clock_get(dev, crtc);
6350 mode->hdisplay = (htot & 0xffff) + 1;
6351 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6352 mode->hsync_start = (hsync & 0xffff) + 1;
6353 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6354 mode->vdisplay = (vtot & 0xffff) + 1;
6355 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6356 mode->vsync_start = (vsync & 0xffff) + 1;
6357 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6359 drm_mode_set_name(mode);
6364 static void intel_increase_pllclock(struct drm_crtc *crtc)
6366 struct drm_device *dev = crtc->dev;
6367 drm_i915_private_t *dev_priv = dev->dev_private;
6368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6369 int pipe = intel_crtc->pipe;
6370 int dpll_reg = DPLL(pipe);
6373 if (HAS_PCH_SPLIT(dev))
6376 if (!dev_priv->lvds_downclock_avail)
6379 dpll = I915_READ(dpll_reg);
6380 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6381 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6383 assert_panel_unlocked(dev_priv, pipe);
6385 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6386 I915_WRITE(dpll_reg, dpll);
6387 intel_wait_for_vblank(dev, pipe);
6389 dpll = I915_READ(dpll_reg);
6390 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6391 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6395 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6397 struct drm_device *dev = crtc->dev;
6398 drm_i915_private_t *dev_priv = dev->dev_private;
6399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6401 if (HAS_PCH_SPLIT(dev))
6404 if (!dev_priv->lvds_downclock_avail)
6408 * Since this is called by a timer, we should never get here in
6411 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6412 int pipe = intel_crtc->pipe;
6413 int dpll_reg = DPLL(pipe);
6416 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6418 assert_panel_unlocked(dev_priv, pipe);
6420 dpll = I915_READ(dpll_reg);
6421 dpll |= DISPLAY_RATE_SELECT_FPA1;
6422 I915_WRITE(dpll_reg, dpll);
6423 intel_wait_for_vblank(dev, pipe);
6424 dpll = I915_READ(dpll_reg);
6425 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6426 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6431 void intel_mark_busy(struct drm_device *dev)
6433 i915_update_gfx_val(dev->dev_private);
6436 void intel_mark_idle(struct drm_device *dev)
6440 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6442 struct drm_device *dev = obj->base.dev;
6443 struct drm_crtc *crtc;
6445 if (!i915_powersave)
6448 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6452 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6453 intel_increase_pllclock(crtc);
6457 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6459 struct drm_device *dev = obj->base.dev;
6460 struct drm_crtc *crtc;
6462 if (!i915_powersave)
6465 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6469 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6470 intel_decrease_pllclock(crtc);
6474 static void intel_crtc_destroy(struct drm_crtc *crtc)
6476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6477 struct drm_device *dev = crtc->dev;
6478 struct intel_unpin_work *work;
6479 unsigned long flags;
6481 spin_lock_irqsave(&dev->event_lock, flags);
6482 work = intel_crtc->unpin_work;
6483 intel_crtc->unpin_work = NULL;
6484 spin_unlock_irqrestore(&dev->event_lock, flags);
6487 cancel_work_sync(&work->work);
6491 drm_crtc_cleanup(crtc);
6496 static void intel_unpin_work_fn(struct work_struct *__work)
6498 struct intel_unpin_work *work =
6499 container_of(__work, struct intel_unpin_work, work);
6501 mutex_lock(&work->dev->struct_mutex);
6502 intel_unpin_fb_obj(work->old_fb_obj);
6503 drm_gem_object_unreference(&work->pending_flip_obj->base);
6504 drm_gem_object_unreference(&work->old_fb_obj->base);
6506 intel_update_fbc(work->dev);
6507 mutex_unlock(&work->dev->struct_mutex);
6511 static void do_intel_finish_page_flip(struct drm_device *dev,
6512 struct drm_crtc *crtc)
6514 drm_i915_private_t *dev_priv = dev->dev_private;
6515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6516 struct intel_unpin_work *work;
6517 struct drm_i915_gem_object *obj;
6518 struct drm_pending_vblank_event *e;
6519 struct timeval tvbl;
6520 unsigned long flags;
6522 /* Ignore early vblank irqs */
6523 if (intel_crtc == NULL)
6526 spin_lock_irqsave(&dev->event_lock, flags);
6527 work = intel_crtc->unpin_work;
6528 if (work == NULL || !work->pending) {
6529 spin_unlock_irqrestore(&dev->event_lock, flags);
6533 intel_crtc->unpin_work = NULL;
6537 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6539 e->event.tv_sec = tvbl.tv_sec;
6540 e->event.tv_usec = tvbl.tv_usec;
6542 list_add_tail(&e->base.link,
6543 &e->base.file_priv->event_list);
6544 wake_up_interruptible(&e->base.file_priv->event_wait);
6547 drm_vblank_put(dev, intel_crtc->pipe);
6549 spin_unlock_irqrestore(&dev->event_lock, flags);
6551 obj = work->old_fb_obj;
6553 atomic_clear_mask(1 << intel_crtc->plane,
6554 &obj->pending_flip.counter);
6556 wake_up(&dev_priv->pending_flip_queue);
6557 schedule_work(&work->work);
6559 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6562 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6564 drm_i915_private_t *dev_priv = dev->dev_private;
6565 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6567 do_intel_finish_page_flip(dev, crtc);
6570 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6572 drm_i915_private_t *dev_priv = dev->dev_private;
6573 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6575 do_intel_finish_page_flip(dev, crtc);
6578 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6580 drm_i915_private_t *dev_priv = dev->dev_private;
6581 struct intel_crtc *intel_crtc =
6582 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6583 unsigned long flags;
6585 spin_lock_irqsave(&dev->event_lock, flags);
6586 if (intel_crtc->unpin_work) {
6587 if ((++intel_crtc->unpin_work->pending) > 1)
6588 DRM_ERROR("Prepared flip multiple times\n");
6590 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6592 spin_unlock_irqrestore(&dev->event_lock, flags);
6595 static int intel_gen2_queue_flip(struct drm_device *dev,
6596 struct drm_crtc *crtc,
6597 struct drm_framebuffer *fb,
6598 struct drm_i915_gem_object *obj)
6600 struct drm_i915_private *dev_priv = dev->dev_private;
6601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6603 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6606 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6610 ret = intel_ring_begin(ring, 6);
6614 /* Can't queue multiple flips, so wait for the previous
6615 * one to finish before executing the next.
6617 if (intel_crtc->plane)
6618 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6620 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6621 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6622 intel_ring_emit(ring, MI_NOOP);
6623 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6624 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6625 intel_ring_emit(ring, fb->pitches[0]);
6626 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6627 intel_ring_emit(ring, 0); /* aux display base address, unused */
6628 intel_ring_advance(ring);
6632 intel_unpin_fb_obj(obj);
6637 static int intel_gen3_queue_flip(struct drm_device *dev,
6638 struct drm_crtc *crtc,
6639 struct drm_framebuffer *fb,
6640 struct drm_i915_gem_object *obj)
6642 struct drm_i915_private *dev_priv = dev->dev_private;
6643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6645 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6648 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6652 ret = intel_ring_begin(ring, 6);
6656 if (intel_crtc->plane)
6657 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6659 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6660 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6661 intel_ring_emit(ring, MI_NOOP);
6662 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6663 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6664 intel_ring_emit(ring, fb->pitches[0]);
6665 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6666 intel_ring_emit(ring, MI_NOOP);
6668 intel_ring_advance(ring);
6672 intel_unpin_fb_obj(obj);
6677 static int intel_gen4_queue_flip(struct drm_device *dev,
6678 struct drm_crtc *crtc,
6679 struct drm_framebuffer *fb,
6680 struct drm_i915_gem_object *obj)
6682 struct drm_i915_private *dev_priv = dev->dev_private;
6683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6684 uint32_t pf, pipesrc;
6685 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6688 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6692 ret = intel_ring_begin(ring, 4);
6696 /* i965+ uses the linear or tiled offsets from the
6697 * Display Registers (which do not change across a page-flip)
6698 * so we need only reprogram the base address.
6700 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6701 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6702 intel_ring_emit(ring, fb->pitches[0]);
6703 intel_ring_emit(ring,
6704 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6707 /* XXX Enabling the panel-fitter across page-flip is so far
6708 * untested on non-native modes, so ignore it for now.
6709 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6712 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6713 intel_ring_emit(ring, pf | pipesrc);
6714 intel_ring_advance(ring);
6718 intel_unpin_fb_obj(obj);
6723 static int intel_gen6_queue_flip(struct drm_device *dev,
6724 struct drm_crtc *crtc,
6725 struct drm_framebuffer *fb,
6726 struct drm_i915_gem_object *obj)
6728 struct drm_i915_private *dev_priv = dev->dev_private;
6729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6730 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6731 uint32_t pf, pipesrc;
6734 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6738 ret = intel_ring_begin(ring, 4);
6742 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6743 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6744 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6745 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6747 /* Contrary to the suggestions in the documentation,
6748 * "Enable Panel Fitter" does not seem to be required when page
6749 * flipping with a non-native mode, and worse causes a normal
6751 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6754 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6755 intel_ring_emit(ring, pf | pipesrc);
6756 intel_ring_advance(ring);
6760 intel_unpin_fb_obj(obj);
6766 * On gen7 we currently use the blit ring because (in early silicon at least)
6767 * the render ring doesn't give us interrpts for page flip completion, which
6768 * means clients will hang after the first flip is queued. Fortunately the
6769 * blit ring generates interrupts properly, so use it instead.
6771 static int intel_gen7_queue_flip(struct drm_device *dev,
6772 struct drm_crtc *crtc,
6773 struct drm_framebuffer *fb,
6774 struct drm_i915_gem_object *obj)
6776 struct drm_i915_private *dev_priv = dev->dev_private;
6777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6778 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6779 uint32_t plane_bit = 0;
6782 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6786 switch(intel_crtc->plane) {
6788 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6791 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6794 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6797 WARN_ONCE(1, "unknown plane in flip command\n");
6802 ret = intel_ring_begin(ring, 4);
6806 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6807 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6808 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6809 intel_ring_emit(ring, (MI_NOOP));
6810 intel_ring_advance(ring);
6814 intel_unpin_fb_obj(obj);
6819 static int intel_default_queue_flip(struct drm_device *dev,
6820 struct drm_crtc *crtc,
6821 struct drm_framebuffer *fb,
6822 struct drm_i915_gem_object *obj)
6827 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6828 struct drm_framebuffer *fb,
6829 struct drm_pending_vblank_event *event)
6831 struct drm_device *dev = crtc->dev;
6832 struct drm_i915_private *dev_priv = dev->dev_private;
6833 struct intel_framebuffer *intel_fb;
6834 struct drm_i915_gem_object *obj;
6835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6836 struct intel_unpin_work *work;
6837 unsigned long flags;
6840 /* Can't change pixel format via MI display flips. */
6841 if (fb->pixel_format != crtc->fb->pixel_format)
6845 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6846 * Note that pitch changes could also affect these register.
6848 if (INTEL_INFO(dev)->gen > 3 &&
6849 (fb->offsets[0] != crtc->fb->offsets[0] ||
6850 fb->pitches[0] != crtc->fb->pitches[0]))
6853 work = kzalloc(sizeof *work, GFP_KERNEL);
6857 work->event = event;
6858 work->dev = crtc->dev;
6859 intel_fb = to_intel_framebuffer(crtc->fb);
6860 work->old_fb_obj = intel_fb->obj;
6861 INIT_WORK(&work->work, intel_unpin_work_fn);
6863 ret = drm_vblank_get(dev, intel_crtc->pipe);
6867 /* We borrow the event spin lock for protecting unpin_work */
6868 spin_lock_irqsave(&dev->event_lock, flags);
6869 if (intel_crtc->unpin_work) {
6870 spin_unlock_irqrestore(&dev->event_lock, flags);
6872 drm_vblank_put(dev, intel_crtc->pipe);
6874 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6877 intel_crtc->unpin_work = work;
6878 spin_unlock_irqrestore(&dev->event_lock, flags);
6880 intel_fb = to_intel_framebuffer(fb);
6881 obj = intel_fb->obj;
6883 ret = i915_mutex_lock_interruptible(dev);
6887 /* Reference the objects for the scheduled work. */
6888 drm_gem_object_reference(&work->old_fb_obj->base);
6889 drm_gem_object_reference(&obj->base);
6893 work->pending_flip_obj = obj;
6895 work->enable_stall_check = true;
6897 /* Block clients from rendering to the new back buffer until
6898 * the flip occurs and the object is no longer visible.
6900 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6902 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6904 goto cleanup_pending;
6906 intel_disable_fbc(dev);
6907 intel_mark_fb_busy(obj);
6908 mutex_unlock(&dev->struct_mutex);
6910 trace_i915_flip_request(intel_crtc->plane, obj);
6915 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6916 drm_gem_object_unreference(&work->old_fb_obj->base);
6917 drm_gem_object_unreference(&obj->base);
6918 mutex_unlock(&dev->struct_mutex);
6921 spin_lock_irqsave(&dev->event_lock, flags);
6922 intel_crtc->unpin_work = NULL;
6923 spin_unlock_irqrestore(&dev->event_lock, flags);
6925 drm_vblank_put(dev, intel_crtc->pipe);
6932 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6933 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6934 .load_lut = intel_crtc_load_lut,
6935 .disable = intel_crtc_noop,
6938 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6940 struct intel_encoder *other_encoder;
6941 struct drm_crtc *crtc = &encoder->new_crtc->base;
6946 list_for_each_entry(other_encoder,
6947 &crtc->dev->mode_config.encoder_list,
6950 if (&other_encoder->new_crtc->base != crtc ||
6951 encoder == other_encoder)
6960 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6961 struct drm_crtc *crtc)
6963 struct drm_device *dev;
6964 struct drm_crtc *tmp;
6967 WARN(!crtc, "checking null crtc?\n");
6971 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6977 if (encoder->possible_crtcs & crtc_mask)
6983 * intel_modeset_update_staged_output_state
6985 * Updates the staged output configuration state, e.g. after we've read out the
6988 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6990 struct intel_encoder *encoder;
6991 struct intel_connector *connector;
6993 list_for_each_entry(connector, &dev->mode_config.connector_list,
6995 connector->new_encoder =
6996 to_intel_encoder(connector->base.encoder);
6999 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7002 to_intel_crtc(encoder->base.crtc);
7007 * intel_modeset_commit_output_state
7009 * This function copies the stage display pipe configuration to the real one.
7011 static void intel_modeset_commit_output_state(struct drm_device *dev)
7013 struct intel_encoder *encoder;
7014 struct intel_connector *connector;
7016 list_for_each_entry(connector, &dev->mode_config.connector_list,
7018 connector->base.encoder = &connector->new_encoder->base;
7021 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7023 encoder->base.crtc = &encoder->new_crtc->base;
7027 static struct drm_display_mode *
7028 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7029 struct drm_display_mode *mode)
7031 struct drm_device *dev = crtc->dev;
7032 struct drm_display_mode *adjusted_mode;
7033 struct drm_encoder_helper_funcs *encoder_funcs;
7034 struct intel_encoder *encoder;
7036 adjusted_mode = drm_mode_duplicate(dev, mode);
7038 return ERR_PTR(-ENOMEM);
7040 /* Pass our mode to the connectors and the CRTC to give them a chance to
7041 * adjust it according to limitations or connector properties, and also
7042 * a chance to reject the mode entirely.
7044 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7047 if (&encoder->new_crtc->base != crtc)
7049 encoder_funcs = encoder->base.helper_private;
7050 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7052 DRM_DEBUG_KMS("Encoder fixup failed\n");
7057 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7058 DRM_DEBUG_KMS("CRTC fixup failed\n");
7061 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7063 return adjusted_mode;
7065 drm_mode_destroy(dev, adjusted_mode);
7066 return ERR_PTR(-EINVAL);
7069 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7070 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7072 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7073 unsigned *prepare_pipes, unsigned *disable_pipes)
7075 struct intel_crtc *intel_crtc;
7076 struct drm_device *dev = crtc->dev;
7077 struct intel_encoder *encoder;
7078 struct intel_connector *connector;
7079 struct drm_crtc *tmp_crtc;
7081 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7083 /* Check which crtcs have changed outputs connected to them, these need
7084 * to be part of the prepare_pipes mask. We don't (yet) support global
7085 * modeset across multiple crtcs, so modeset_pipes will only have one
7086 * bit set at most. */
7087 list_for_each_entry(connector, &dev->mode_config.connector_list,
7089 if (connector->base.encoder == &connector->new_encoder->base)
7092 if (connector->base.encoder) {
7093 tmp_crtc = connector->base.encoder->crtc;
7095 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7098 if (connector->new_encoder)
7100 1 << connector->new_encoder->new_crtc->pipe;
7103 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7105 if (encoder->base.crtc == &encoder->new_crtc->base)
7108 if (encoder->base.crtc) {
7109 tmp_crtc = encoder->base.crtc;
7111 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7114 if (encoder->new_crtc)
7115 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7118 /* Check for any pipes that will be fully disabled ... */
7119 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7123 /* Don't try to disable disabled crtcs. */
7124 if (!intel_crtc->base.enabled)
7127 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7129 if (encoder->new_crtc == intel_crtc)
7134 *disable_pipes |= 1 << intel_crtc->pipe;
7138 /* set_mode is also used to update properties on life display pipes. */
7139 intel_crtc = to_intel_crtc(crtc);
7141 *prepare_pipes |= 1 << intel_crtc->pipe;
7143 /* We only support modeset on one single crtc, hence we need to do that
7144 * only for the passed in crtc iff we change anything else than just
7147 * This is actually not true, to be fully compatible with the old crtc
7148 * helper we automatically disable _any_ output (i.e. doesn't need to be
7149 * connected to the crtc we're modesetting on) if it's disconnected.
7150 * Which is a rather nutty api (since changed the output configuration
7151 * without userspace's explicit request can lead to confusion), but
7152 * alas. Hence we currently need to modeset on all pipes we prepare. */
7154 *modeset_pipes = *prepare_pipes;
7156 /* ... and mask these out. */
7157 *modeset_pipes &= ~(*disable_pipes);
7158 *prepare_pipes &= ~(*disable_pipes);
7161 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7163 struct drm_encoder *encoder;
7164 struct drm_device *dev = crtc->dev;
7166 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7167 if (encoder->crtc == crtc)
7174 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7176 struct intel_encoder *intel_encoder;
7177 struct intel_crtc *intel_crtc;
7178 struct drm_connector *connector;
7180 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7182 if (!intel_encoder->base.crtc)
7185 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7187 if (prepare_pipes & (1 << intel_crtc->pipe))
7188 intel_encoder->connectors_active = false;
7191 intel_modeset_commit_output_state(dev);
7193 /* Update computed state. */
7194 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7196 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7199 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7200 if (!connector->encoder || !connector->encoder->crtc)
7203 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7205 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7206 struct drm_property *dpms_property =
7207 dev->mode_config.dpms_property;
7209 connector->dpms = DRM_MODE_DPMS_ON;
7210 drm_connector_property_set_value(connector,
7214 intel_encoder = to_intel_encoder(connector->encoder);
7215 intel_encoder->connectors_active = true;
7221 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7222 list_for_each_entry((intel_crtc), \
7223 &(dev)->mode_config.crtc_list, \
7225 if (mask & (1 <<(intel_crtc)->pipe)) \
7228 intel_modeset_check_state(struct drm_device *dev)
7230 struct intel_crtc *crtc;
7231 struct intel_encoder *encoder;
7232 struct intel_connector *connector;
7234 list_for_each_entry(connector, &dev->mode_config.connector_list,
7236 /* This also checks the encoder/connector hw state with the
7237 * ->get_hw_state callbacks. */
7238 intel_connector_check_state(connector);
7240 WARN(&connector->new_encoder->base != connector->base.encoder,
7241 "connector's staged encoder doesn't match current encoder\n");
7244 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7246 bool enabled = false;
7247 bool active = false;
7248 enum pipe pipe, tracked_pipe;
7250 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7251 encoder->base.base.id,
7252 drm_get_encoder_name(&encoder->base));
7254 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7255 "encoder's stage crtc doesn't match current crtc\n");
7256 WARN(encoder->connectors_active && !encoder->base.crtc,
7257 "encoder's active_connectors set, but no crtc\n");
7259 list_for_each_entry(connector, &dev->mode_config.connector_list,
7261 if (connector->base.encoder != &encoder->base)
7264 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7267 WARN(!!encoder->base.crtc != enabled,
7268 "encoder's enabled state mismatch "
7269 "(expected %i, found %i)\n",
7270 !!encoder->base.crtc, enabled);
7271 WARN(active && !encoder->base.crtc,
7272 "active encoder with no crtc\n");
7274 WARN(encoder->connectors_active != active,
7275 "encoder's computed active state doesn't match tracked active state "
7276 "(expected %i, found %i)\n", active, encoder->connectors_active);
7278 active = encoder->get_hw_state(encoder, &pipe);
7279 WARN(active != encoder->connectors_active,
7280 "encoder's hw state doesn't match sw tracking "
7281 "(expected %i, found %i)\n",
7282 encoder->connectors_active, active);
7284 if (!encoder->base.crtc)
7287 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7288 WARN(active && pipe != tracked_pipe,
7289 "active encoder's pipe doesn't match"
7290 "(expected %i, found %i)\n",
7291 tracked_pipe, pipe);
7295 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7297 bool enabled = false;
7298 bool active = false;
7300 DRM_DEBUG_KMS("[CRTC:%d]\n",
7301 crtc->base.base.id);
7303 WARN(crtc->active && !crtc->base.enabled,
7304 "active crtc, but not enabled in sw tracking\n");
7306 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7308 if (encoder->base.crtc != &crtc->base)
7311 if (encoder->connectors_active)
7314 WARN(active != crtc->active,
7315 "crtc's computed active state doesn't match tracked active state "
7316 "(expected %i, found %i)\n", active, crtc->active);
7317 WARN(enabled != crtc->base.enabled,
7318 "crtc's computed enabled state doesn't match tracked enabled state "
7319 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7321 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7325 bool intel_set_mode(struct drm_crtc *crtc,
7326 struct drm_display_mode *mode,
7327 int x, int y, struct drm_framebuffer *fb)
7329 struct drm_device *dev = crtc->dev;
7330 drm_i915_private_t *dev_priv = dev->dev_private;
7331 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7332 struct drm_encoder_helper_funcs *encoder_funcs;
7333 struct drm_encoder *encoder;
7334 struct intel_crtc *intel_crtc;
7335 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7338 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7339 &prepare_pipes, &disable_pipes);
7341 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7342 modeset_pipes, prepare_pipes, disable_pipes);
7344 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7345 intel_crtc_disable(&intel_crtc->base);
7347 saved_hwmode = crtc->hwmode;
7348 saved_mode = crtc->mode;
7350 /* Hack: Because we don't (yet) support global modeset on multiple
7351 * crtcs, we don't keep track of the new mode for more than one crtc.
7352 * Hence simply check whether any bit is set in modeset_pipes in all the
7353 * pieces of code that are not yet converted to deal with mutliple crtcs
7354 * changing their mode at the same time. */
7355 adjusted_mode = NULL;
7356 if (modeset_pipes) {
7357 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7358 if (IS_ERR(adjusted_mode)) {
7363 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7364 if (intel_crtc->base.enabled)
7365 dev_priv->display.crtc_disable(&intel_crtc->base);
7368 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7369 * to set it here already despite that we pass it down the callchain.
7374 /* Only after disabling all output pipelines that will be changed can we
7375 * update the the output configuration. */
7376 intel_modeset_update_state(dev, prepare_pipes);
7378 /* Set up the DPLL and any encoders state that needs to adjust or depend
7381 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7382 ret = !intel_crtc_mode_set(&intel_crtc->base,
7383 mode, adjusted_mode,
7388 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7390 if (encoder->crtc != &intel_crtc->base)
7393 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7394 encoder->base.id, drm_get_encoder_name(encoder),
7395 mode->base.id, mode->name);
7396 encoder_funcs = encoder->helper_private;
7397 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7401 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7402 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7403 dev_priv->display.crtc_enable(&intel_crtc->base);
7405 if (modeset_pipes) {
7406 /* Store real post-adjustment hardware mode. */
7407 crtc->hwmode = *adjusted_mode;
7409 /* Calculate and store various constants which
7410 * are later needed by vblank and swap-completion
7411 * timestamping. They are derived from true hwmode.
7413 drm_calc_timestamping_constants(crtc);
7416 /* FIXME: add subpixel order */
7418 drm_mode_destroy(dev, adjusted_mode);
7419 if (!ret && crtc->enabled) {
7420 crtc->hwmode = saved_hwmode;
7421 crtc->mode = saved_mode;
7423 intel_modeset_check_state(dev);
7429 #undef for_each_intel_crtc_masked
7431 static void intel_set_config_free(struct intel_set_config *config)
7436 kfree(config->save_connector_encoders);
7437 kfree(config->save_encoder_crtcs);
7441 static int intel_set_config_save_state(struct drm_device *dev,
7442 struct intel_set_config *config)
7444 struct drm_encoder *encoder;
7445 struct drm_connector *connector;
7448 config->save_encoder_crtcs =
7449 kcalloc(dev->mode_config.num_encoder,
7450 sizeof(struct drm_crtc *), GFP_KERNEL);
7451 if (!config->save_encoder_crtcs)
7454 config->save_connector_encoders =
7455 kcalloc(dev->mode_config.num_connector,
7456 sizeof(struct drm_encoder *), GFP_KERNEL);
7457 if (!config->save_connector_encoders)
7460 /* Copy data. Note that driver private data is not affected.
7461 * Should anything bad happen only the expected state is
7462 * restored, not the drivers personal bookkeeping.
7465 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7466 config->save_encoder_crtcs[count++] = encoder->crtc;
7470 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7471 config->save_connector_encoders[count++] = connector->encoder;
7477 static void intel_set_config_restore_state(struct drm_device *dev,
7478 struct intel_set_config *config)
7480 struct intel_encoder *encoder;
7481 struct intel_connector *connector;
7485 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7487 to_intel_crtc(config->save_encoder_crtcs[count++]);
7491 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7492 connector->new_encoder =
7493 to_intel_encoder(config->save_connector_encoders[count++]);
7498 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7499 struct intel_set_config *config)
7502 /* We should be able to check here if the fb has the same properties
7503 * and then just flip_or_move it */
7504 if (set->crtc->fb != set->fb) {
7505 /* If we have no fb then treat it as a full mode set */
7506 if (set->crtc->fb == NULL) {
7507 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7508 config->mode_changed = true;
7509 } else if (set->fb == NULL) {
7510 config->mode_changed = true;
7511 } else if (set->fb->depth != set->crtc->fb->depth) {
7512 config->mode_changed = true;
7513 } else if (set->fb->bits_per_pixel !=
7514 set->crtc->fb->bits_per_pixel) {
7515 config->mode_changed = true;
7517 config->fb_changed = true;
7520 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7521 config->fb_changed = true;
7523 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7524 DRM_DEBUG_KMS("modes are different, full mode set\n");
7525 drm_mode_debug_printmodeline(&set->crtc->mode);
7526 drm_mode_debug_printmodeline(set->mode);
7527 config->mode_changed = true;
7532 intel_modeset_stage_output_state(struct drm_device *dev,
7533 struct drm_mode_set *set,
7534 struct intel_set_config *config)
7536 struct drm_crtc *new_crtc;
7537 struct intel_connector *connector;
7538 struct intel_encoder *encoder;
7541 /* The upper layers ensure that we either disabl a crtc or have a list
7542 * of connectors. For paranoia, double-check this. */
7543 WARN_ON(!set->fb && (set->num_connectors != 0));
7544 WARN_ON(set->fb && (set->num_connectors == 0));
7547 list_for_each_entry(connector, &dev->mode_config.connector_list,
7549 /* Otherwise traverse passed in connector list and get encoders
7551 for (ro = 0; ro < set->num_connectors; ro++) {
7552 if (set->connectors[ro] == &connector->base) {
7553 connector->new_encoder = connector->encoder;
7558 /* If we disable the crtc, disable all its connectors. Also, if
7559 * the connector is on the changing crtc but not on the new
7560 * connector list, disable it. */
7561 if ((!set->fb || ro == set->num_connectors) &&
7562 connector->base.encoder &&
7563 connector->base.encoder->crtc == set->crtc) {
7564 connector->new_encoder = NULL;
7566 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7567 connector->base.base.id,
7568 drm_get_connector_name(&connector->base));
7572 if (&connector->new_encoder->base != connector->base.encoder) {
7573 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7574 config->mode_changed = true;
7577 /* Disable all disconnected encoders. */
7578 if (connector->base.status == connector_status_disconnected)
7579 connector->new_encoder = NULL;
7581 /* connector->new_encoder is now updated for all connectors. */
7583 /* Update crtc of enabled connectors. */
7585 list_for_each_entry(connector, &dev->mode_config.connector_list,
7587 if (!connector->new_encoder)
7590 new_crtc = connector->new_encoder->base.crtc;
7592 for (ro = 0; ro < set->num_connectors; ro++) {
7593 if (set->connectors[ro] == &connector->base)
7594 new_crtc = set->crtc;
7597 /* Make sure the new CRTC will work with the encoder */
7598 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7602 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7604 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7605 connector->base.base.id,
7606 drm_get_connector_name(&connector->base),
7610 /* Check for any encoders that needs to be disabled. */
7611 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7613 list_for_each_entry(connector,
7614 &dev->mode_config.connector_list,
7616 if (connector->new_encoder == encoder) {
7617 WARN_ON(!connector->new_encoder->new_crtc);
7622 encoder->new_crtc = NULL;
7624 /* Only now check for crtc changes so we don't miss encoders
7625 * that will be disabled. */
7626 if (&encoder->new_crtc->base != encoder->base.crtc) {
7627 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7628 config->mode_changed = true;
7631 /* Now we've also updated encoder->new_crtc for all encoders. */
7636 static int intel_crtc_set_config(struct drm_mode_set *set)
7638 struct drm_device *dev;
7639 struct drm_mode_set save_set;
7640 struct intel_set_config *config;
7645 BUG_ON(!set->crtc->helper_private);
7650 /* The fb helper likes to play gross jokes with ->mode_set_config.
7651 * Unfortunately the crtc helper doesn't do much at all for this case,
7652 * so we have to cope with this madness until the fb helper is fixed up. */
7653 if (set->fb && set->num_connectors == 0)
7657 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7658 set->crtc->base.id, set->fb->base.id,
7659 (int)set->num_connectors, set->x, set->y);
7661 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7664 dev = set->crtc->dev;
7667 config = kzalloc(sizeof(*config), GFP_KERNEL);
7671 ret = intel_set_config_save_state(dev, config);
7675 save_set.crtc = set->crtc;
7676 save_set.mode = &set->crtc->mode;
7677 save_set.x = set->crtc->x;
7678 save_set.y = set->crtc->y;
7679 save_set.fb = set->crtc->fb;
7681 /* Compute whether we need a full modeset, only an fb base update or no
7682 * change at all. In the future we might also check whether only the
7683 * mode changed, e.g. for LVDS where we only change the panel fitter in
7685 intel_set_config_compute_mode_changes(set, config);
7687 ret = intel_modeset_stage_output_state(dev, set, config);
7691 if (config->mode_changed) {
7693 DRM_DEBUG_KMS("attempting to set mode from"
7695 drm_mode_debug_printmodeline(set->mode);
7698 if (!intel_set_mode(set->crtc, set->mode,
7699 set->x, set->y, set->fb)) {
7700 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7701 set->crtc->base.id);
7705 } else if (config->fb_changed) {
7706 ret = intel_pipe_set_base(set->crtc,
7707 set->x, set->y, set->fb);
7710 intel_set_config_free(config);
7715 intel_set_config_restore_state(dev, config);
7717 /* Try to restore the config */
7718 if (config->mode_changed &&
7719 !intel_set_mode(save_set.crtc, save_set.mode,
7720 save_set.x, save_set.y, save_set.fb))
7721 DRM_ERROR("failed to restore config after modeset failure\n");
7724 intel_set_config_free(config);
7728 static const struct drm_crtc_funcs intel_crtc_funcs = {
7729 .cursor_set = intel_crtc_cursor_set,
7730 .cursor_move = intel_crtc_cursor_move,
7731 .gamma_set = intel_crtc_gamma_set,
7732 .set_config = intel_crtc_set_config,
7733 .destroy = intel_crtc_destroy,
7734 .page_flip = intel_crtc_page_flip,
7737 static void intel_cpu_pll_init(struct drm_device *dev)
7739 if (IS_HASWELL(dev))
7740 intel_ddi_pll_init(dev);
7743 static void intel_pch_pll_init(struct drm_device *dev)
7745 drm_i915_private_t *dev_priv = dev->dev_private;
7748 if (dev_priv->num_pch_pll == 0) {
7749 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7753 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7754 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7755 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7756 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7760 static void intel_crtc_init(struct drm_device *dev, int pipe)
7762 drm_i915_private_t *dev_priv = dev->dev_private;
7763 struct intel_crtc *intel_crtc;
7766 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7767 if (intel_crtc == NULL)
7770 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7772 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7773 for (i = 0; i < 256; i++) {
7774 intel_crtc->lut_r[i] = i;
7775 intel_crtc->lut_g[i] = i;
7776 intel_crtc->lut_b[i] = i;
7779 /* Swap pipes & planes for FBC on pre-965 */
7780 intel_crtc->pipe = pipe;
7781 intel_crtc->plane = pipe;
7782 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7783 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7784 intel_crtc->plane = !pipe;
7787 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7788 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7789 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7790 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7792 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7794 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7797 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7798 struct drm_file *file)
7800 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7801 struct drm_mode_object *drmmode_obj;
7802 struct intel_crtc *crtc;
7804 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7807 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7808 DRM_MODE_OBJECT_CRTC);
7811 DRM_ERROR("no such CRTC id\n");
7815 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7816 pipe_from_crtc_id->pipe = crtc->pipe;
7821 static int intel_encoder_clones(struct intel_encoder *encoder)
7823 struct drm_device *dev = encoder->base.dev;
7824 struct intel_encoder *source_encoder;
7828 list_for_each_entry(source_encoder,
7829 &dev->mode_config.encoder_list, base.head) {
7831 if (encoder == source_encoder)
7832 index_mask |= (1 << entry);
7834 /* Intel hw has only one MUX where enocoders could be cloned. */
7835 if (encoder->cloneable && source_encoder->cloneable)
7836 index_mask |= (1 << entry);
7844 static bool has_edp_a(struct drm_device *dev)
7846 struct drm_i915_private *dev_priv = dev->dev_private;
7848 if (!IS_MOBILE(dev))
7851 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7855 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7861 static void intel_setup_outputs(struct drm_device *dev)
7863 struct drm_i915_private *dev_priv = dev->dev_private;
7864 struct intel_encoder *encoder;
7865 bool dpd_is_edp = false;
7868 has_lvds = intel_lvds_init(dev);
7869 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7870 /* disable the panel fitter on everything but LVDS */
7871 I915_WRITE(PFIT_CONTROL, 0);
7874 if (HAS_PCH_SPLIT(dev)) {
7875 dpd_is_edp = intel_dpd_is_edp(dev);
7878 intel_dp_init(dev, DP_A, PORT_A);
7880 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7881 intel_dp_init(dev, PCH_DP_D, PORT_D);
7884 intel_crt_init(dev);
7886 if (IS_HASWELL(dev)) {
7889 /* Haswell uses DDI functions to detect digital outputs */
7890 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7891 /* DDI A only supports eDP */
7893 intel_ddi_init(dev, PORT_A);
7895 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7897 found = I915_READ(SFUSE_STRAP);
7899 if (found & SFUSE_STRAP_DDIB_DETECTED)
7900 intel_ddi_init(dev, PORT_B);
7901 if (found & SFUSE_STRAP_DDIC_DETECTED)
7902 intel_ddi_init(dev, PORT_C);
7903 if (found & SFUSE_STRAP_DDID_DETECTED)
7904 intel_ddi_init(dev, PORT_D);
7905 } else if (HAS_PCH_SPLIT(dev)) {
7908 if (I915_READ(HDMIB) & PORT_DETECTED) {
7909 /* PCH SDVOB multiplex with HDMIB */
7910 found = intel_sdvo_init(dev, PCH_SDVOB, true);
7912 intel_hdmi_init(dev, HDMIB, PORT_B);
7913 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7914 intel_dp_init(dev, PCH_DP_B, PORT_B);
7917 if (I915_READ(HDMIC) & PORT_DETECTED)
7918 intel_hdmi_init(dev, HDMIC, PORT_C);
7920 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7921 intel_hdmi_init(dev, HDMID, PORT_D);
7923 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7924 intel_dp_init(dev, PCH_DP_C, PORT_C);
7926 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7927 intel_dp_init(dev, PCH_DP_D, PORT_D);
7928 } else if (IS_VALLEYVIEW(dev)) {
7931 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
7932 if (I915_READ(DP_C) & DP_DETECTED)
7933 intel_dp_init(dev, DP_C, PORT_C);
7935 if (I915_READ(SDVOB) & PORT_DETECTED) {
7936 /* SDVOB multiplex with HDMIB */
7937 found = intel_sdvo_init(dev, SDVOB, true);
7939 intel_hdmi_init(dev, SDVOB, PORT_B);
7940 if (!found && (I915_READ(DP_B) & DP_DETECTED))
7941 intel_dp_init(dev, DP_B, PORT_B);
7944 if (I915_READ(SDVOC) & PORT_DETECTED)
7945 intel_hdmi_init(dev, SDVOC, PORT_C);
7947 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7950 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7951 DRM_DEBUG_KMS("probing SDVOB\n");
7952 found = intel_sdvo_init(dev, SDVOB, true);
7953 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7954 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7955 intel_hdmi_init(dev, SDVOB, PORT_B);
7958 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7959 DRM_DEBUG_KMS("probing DP_B\n");
7960 intel_dp_init(dev, DP_B, PORT_B);
7964 /* Before G4X SDVOC doesn't have its own detect register */
7966 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7967 DRM_DEBUG_KMS("probing SDVOC\n");
7968 found = intel_sdvo_init(dev, SDVOC, false);
7971 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7973 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7974 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7975 intel_hdmi_init(dev, SDVOC, PORT_C);
7977 if (SUPPORTS_INTEGRATED_DP(dev)) {
7978 DRM_DEBUG_KMS("probing DP_C\n");
7979 intel_dp_init(dev, DP_C, PORT_C);
7983 if (SUPPORTS_INTEGRATED_DP(dev) &&
7984 (I915_READ(DP_D) & DP_DETECTED)) {
7985 DRM_DEBUG_KMS("probing DP_D\n");
7986 intel_dp_init(dev, DP_D, PORT_D);
7988 } else if (IS_GEN2(dev))
7989 intel_dvo_init(dev);
7991 if (SUPPORTS_TV(dev))
7994 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7995 encoder->base.possible_crtcs = encoder->crtc_mask;
7996 encoder->base.possible_clones =
7997 intel_encoder_clones(encoder);
8000 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8001 ironlake_init_pch_refclk(dev);
8004 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8006 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8008 drm_framebuffer_cleanup(fb);
8009 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8014 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8015 struct drm_file *file,
8016 unsigned int *handle)
8018 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8019 struct drm_i915_gem_object *obj = intel_fb->obj;
8021 return drm_gem_handle_create(file, &obj->base, handle);
8024 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8025 .destroy = intel_user_framebuffer_destroy,
8026 .create_handle = intel_user_framebuffer_create_handle,
8029 int intel_framebuffer_init(struct drm_device *dev,
8030 struct intel_framebuffer *intel_fb,
8031 struct drm_mode_fb_cmd2 *mode_cmd,
8032 struct drm_i915_gem_object *obj)
8036 if (obj->tiling_mode == I915_TILING_Y)
8039 if (mode_cmd->pitches[0] & 63)
8042 switch (mode_cmd->pixel_format) {
8043 case DRM_FORMAT_RGB332:
8044 case DRM_FORMAT_RGB565:
8045 case DRM_FORMAT_XRGB8888:
8046 case DRM_FORMAT_XBGR8888:
8047 case DRM_FORMAT_ARGB8888:
8048 case DRM_FORMAT_XRGB2101010:
8049 case DRM_FORMAT_ARGB2101010:
8050 /* RGB formats are common across chipsets */
8052 case DRM_FORMAT_YUYV:
8053 case DRM_FORMAT_UYVY:
8054 case DRM_FORMAT_YVYU:
8055 case DRM_FORMAT_VYUY:
8058 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8059 mode_cmd->pixel_format);
8063 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8065 DRM_ERROR("framebuffer init failed %d\n", ret);
8069 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8070 intel_fb->obj = obj;
8074 static struct drm_framebuffer *
8075 intel_user_framebuffer_create(struct drm_device *dev,
8076 struct drm_file *filp,
8077 struct drm_mode_fb_cmd2 *mode_cmd)
8079 struct drm_i915_gem_object *obj;
8081 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8082 mode_cmd->handles[0]));
8083 if (&obj->base == NULL)
8084 return ERR_PTR(-ENOENT);
8086 return intel_framebuffer_create(dev, mode_cmd, obj);
8089 static const struct drm_mode_config_funcs intel_mode_funcs = {
8090 .fb_create = intel_user_framebuffer_create,
8091 .output_poll_changed = intel_fb_output_poll_changed,
8094 /* Set up chip specific display functions */
8095 static void intel_init_display(struct drm_device *dev)
8097 struct drm_i915_private *dev_priv = dev->dev_private;
8099 /* We always want a DPMS function */
8100 if (IS_HASWELL(dev)) {
8101 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8102 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8103 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8104 dev_priv->display.off = haswell_crtc_off;
8105 dev_priv->display.update_plane = ironlake_update_plane;
8106 } else if (HAS_PCH_SPLIT(dev)) {
8107 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8108 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8109 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8110 dev_priv->display.off = ironlake_crtc_off;
8111 dev_priv->display.update_plane = ironlake_update_plane;
8113 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8114 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8115 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8116 dev_priv->display.off = i9xx_crtc_off;
8117 dev_priv->display.update_plane = i9xx_update_plane;
8120 /* Returns the core display clock speed */
8121 if (IS_VALLEYVIEW(dev))
8122 dev_priv->display.get_display_clock_speed =
8123 valleyview_get_display_clock_speed;
8124 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8125 dev_priv->display.get_display_clock_speed =
8126 i945_get_display_clock_speed;
8127 else if (IS_I915G(dev))
8128 dev_priv->display.get_display_clock_speed =
8129 i915_get_display_clock_speed;
8130 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8131 dev_priv->display.get_display_clock_speed =
8132 i9xx_misc_get_display_clock_speed;
8133 else if (IS_I915GM(dev))
8134 dev_priv->display.get_display_clock_speed =
8135 i915gm_get_display_clock_speed;
8136 else if (IS_I865G(dev))
8137 dev_priv->display.get_display_clock_speed =
8138 i865_get_display_clock_speed;
8139 else if (IS_I85X(dev))
8140 dev_priv->display.get_display_clock_speed =
8141 i855_get_display_clock_speed;
8143 dev_priv->display.get_display_clock_speed =
8144 i830_get_display_clock_speed;
8146 if (HAS_PCH_SPLIT(dev)) {
8148 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8149 dev_priv->display.write_eld = ironlake_write_eld;
8150 } else if (IS_GEN6(dev)) {
8151 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8152 dev_priv->display.write_eld = ironlake_write_eld;
8153 } else if (IS_IVYBRIDGE(dev)) {
8154 /* FIXME: detect B0+ stepping and use auto training */
8155 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8156 dev_priv->display.write_eld = ironlake_write_eld;
8157 } else if (IS_HASWELL(dev)) {
8158 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8159 dev_priv->display.write_eld = haswell_write_eld;
8161 dev_priv->display.update_wm = NULL;
8162 } else if (IS_G4X(dev)) {
8163 dev_priv->display.write_eld = g4x_write_eld;
8166 /* Default just returns -ENODEV to indicate unsupported */
8167 dev_priv->display.queue_flip = intel_default_queue_flip;
8169 switch (INTEL_INFO(dev)->gen) {
8171 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8175 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8180 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8184 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8187 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8193 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8194 * resume, or other times. This quirk makes sure that's the case for
8197 static void quirk_pipea_force(struct drm_device *dev)
8199 struct drm_i915_private *dev_priv = dev->dev_private;
8201 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8202 DRM_INFO("applying pipe a force quirk\n");
8206 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8208 static void quirk_ssc_force_disable(struct drm_device *dev)
8210 struct drm_i915_private *dev_priv = dev->dev_private;
8211 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8212 DRM_INFO("applying lvds SSC disable quirk\n");
8216 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8219 static void quirk_invert_brightness(struct drm_device *dev)
8221 struct drm_i915_private *dev_priv = dev->dev_private;
8222 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8223 DRM_INFO("applying inverted panel brightness quirk\n");
8226 struct intel_quirk {
8228 int subsystem_vendor;
8229 int subsystem_device;
8230 void (*hook)(struct drm_device *dev);
8233 static struct intel_quirk intel_quirks[] = {
8234 /* HP Mini needs pipe A force quirk (LP: #322104) */
8235 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8237 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8238 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8240 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8241 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8243 /* 830/845 need to leave pipe A & dpll A up */
8244 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8245 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8247 /* Lenovo U160 cannot use SSC on LVDS */
8248 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8250 /* Sony Vaio Y cannot use SSC on LVDS */
8251 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8253 /* Acer Aspire 5734Z must invert backlight brightness */
8254 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8257 static void intel_init_quirks(struct drm_device *dev)
8259 struct pci_dev *d = dev->pdev;
8262 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8263 struct intel_quirk *q = &intel_quirks[i];
8265 if (d->device == q->device &&
8266 (d->subsystem_vendor == q->subsystem_vendor ||
8267 q->subsystem_vendor == PCI_ANY_ID) &&
8268 (d->subsystem_device == q->subsystem_device ||
8269 q->subsystem_device == PCI_ANY_ID))
8274 /* Disable the VGA plane that we never use */
8275 static void i915_disable_vga(struct drm_device *dev)
8277 struct drm_i915_private *dev_priv = dev->dev_private;
8281 if (HAS_PCH_SPLIT(dev))
8282 vga_reg = CPU_VGACNTRL;
8286 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8287 outb(SR01, VGA_SR_INDEX);
8288 sr1 = inb(VGA_SR_DATA);
8289 outb(sr1 | 1<<5, VGA_SR_DATA);
8290 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8293 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8294 POSTING_READ(vga_reg);
8297 void intel_modeset_init_hw(struct drm_device *dev)
8299 /* We attempt to init the necessary power wells early in the initialization
8300 * time, so the subsystems that expect power to be enabled can work.
8302 intel_init_power_wells(dev);
8304 intel_prepare_ddi(dev);
8306 intel_init_clock_gating(dev);
8308 mutex_lock(&dev->struct_mutex);
8309 intel_enable_gt_powersave(dev);
8310 mutex_unlock(&dev->struct_mutex);
8313 void intel_modeset_init(struct drm_device *dev)
8315 struct drm_i915_private *dev_priv = dev->dev_private;
8318 drm_mode_config_init(dev);
8320 dev->mode_config.min_width = 0;
8321 dev->mode_config.min_height = 0;
8323 dev->mode_config.preferred_depth = 24;
8324 dev->mode_config.prefer_shadow = 1;
8326 dev->mode_config.funcs = &intel_mode_funcs;
8328 intel_init_quirks(dev);
8332 intel_init_display(dev);
8335 dev->mode_config.max_width = 2048;
8336 dev->mode_config.max_height = 2048;
8337 } else if (IS_GEN3(dev)) {
8338 dev->mode_config.max_width = 4096;
8339 dev->mode_config.max_height = 4096;
8341 dev->mode_config.max_width = 8192;
8342 dev->mode_config.max_height = 8192;
8344 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8346 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8347 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8349 for (i = 0; i < dev_priv->num_pipe; i++) {
8350 intel_crtc_init(dev, i);
8351 ret = intel_plane_init(dev, i);
8353 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8356 intel_cpu_pll_init(dev);
8357 intel_pch_pll_init(dev);
8359 /* Just disable it once at startup */
8360 i915_disable_vga(dev);
8361 intel_setup_outputs(dev);
8365 intel_connector_break_all_links(struct intel_connector *connector)
8367 connector->base.dpms = DRM_MODE_DPMS_OFF;
8368 connector->base.encoder = NULL;
8369 connector->encoder->connectors_active = false;
8370 connector->encoder->base.crtc = NULL;
8373 static void intel_enable_pipe_a(struct drm_device *dev)
8375 struct intel_connector *connector;
8376 struct drm_connector *crt = NULL;
8377 struct intel_load_detect_pipe load_detect_temp;
8379 /* We can't just switch on the pipe A, we need to set things up with a
8380 * proper mode and output configuration. As a gross hack, enable pipe A
8381 * by enabling the load detect pipe once. */
8382 list_for_each_entry(connector,
8383 &dev->mode_config.connector_list,
8385 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8386 crt = &connector->base;
8394 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8395 intel_release_load_detect_pipe(crt, &load_detect_temp);
8401 intel_check_plane_mapping(struct intel_crtc *crtc)
8403 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8406 if (dev_priv->num_pipe == 1)
8409 reg = DSPCNTR(!crtc->plane);
8410 val = I915_READ(reg);
8412 if ((val & DISPLAY_PLANE_ENABLE) &&
8413 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8419 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8421 struct drm_device *dev = crtc->base.dev;
8422 struct drm_i915_private *dev_priv = dev->dev_private;
8425 /* Clear any frame start delays used for debugging left by the BIOS */
8426 reg = PIPECONF(crtc->pipe);
8427 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8429 /* We need to sanitize the plane -> pipe mapping first because this will
8430 * disable the crtc (and hence change the state) if it is wrong. Note
8431 * that gen4+ has a fixed plane -> pipe mapping. */
8432 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8433 struct intel_connector *connector;
8436 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8437 crtc->base.base.id);
8439 /* Pipe has the wrong plane attached and the plane is active.
8440 * Temporarily change the plane mapping and disable everything
8442 plane = crtc->plane;
8443 crtc->plane = !plane;
8444 dev_priv->display.crtc_disable(&crtc->base);
8445 crtc->plane = plane;
8447 /* ... and break all links. */
8448 list_for_each_entry(connector, &dev->mode_config.connector_list,
8450 if (connector->encoder->base.crtc != &crtc->base)
8453 intel_connector_break_all_links(connector);
8456 WARN_ON(crtc->active);
8457 crtc->base.enabled = false;
8460 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8461 crtc->pipe == PIPE_A && !crtc->active) {
8462 /* BIOS forgot to enable pipe A, this mostly happens after
8463 * resume. Force-enable the pipe to fix this, the update_dpms
8464 * call below we restore the pipe to the right state, but leave
8465 * the required bits on. */
8466 intel_enable_pipe_a(dev);
8469 /* Adjust the state of the output pipe according to whether we
8470 * have active connectors/encoders. */
8471 intel_crtc_update_dpms(&crtc->base);
8473 if (crtc->active != crtc->base.enabled) {
8474 struct intel_encoder *encoder;
8476 /* This can happen either due to bugs in the get_hw_state
8477 * functions or because the pipe is force-enabled due to the
8479 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8481 crtc->base.enabled ? "enabled" : "disabled",
8482 crtc->active ? "enabled" : "disabled");
8484 crtc->base.enabled = crtc->active;
8486 /* Because we only establish the connector -> encoder ->
8487 * crtc links if something is active, this means the
8488 * crtc is now deactivated. Break the links. connector
8489 * -> encoder links are only establish when things are
8490 * actually up, hence no need to break them. */
8491 WARN_ON(crtc->active);
8493 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8494 WARN_ON(encoder->connectors_active);
8495 encoder->base.crtc = NULL;
8500 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8502 struct intel_connector *connector;
8503 struct drm_device *dev = encoder->base.dev;
8505 /* We need to check both for a crtc link (meaning that the
8506 * encoder is active and trying to read from a pipe) and the
8507 * pipe itself being active. */
8508 bool has_active_crtc = encoder->base.crtc &&
8509 to_intel_crtc(encoder->base.crtc)->active;
8511 if (encoder->connectors_active && !has_active_crtc) {
8512 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8513 encoder->base.base.id,
8514 drm_get_encoder_name(&encoder->base));
8516 /* Connector is active, but has no active pipe. This is
8517 * fallout from our resume register restoring. Disable
8518 * the encoder manually again. */
8519 if (encoder->base.crtc) {
8520 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8521 encoder->base.base.id,
8522 drm_get_encoder_name(&encoder->base));
8523 encoder->disable(encoder);
8526 /* Inconsistent output/port/pipe state happens presumably due to
8527 * a bug in one of the get_hw_state functions. Or someplace else
8528 * in our code, like the register restore mess on resume. Clamp
8529 * things to off as a safer default. */
8530 list_for_each_entry(connector,
8531 &dev->mode_config.connector_list,
8533 if (connector->encoder != encoder)
8536 intel_connector_break_all_links(connector);
8539 /* Enabled encoders without active connectors will be fixed in
8540 * the crtc fixup. */
8543 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8544 * and i915 state tracking structures. */
8545 void intel_modeset_setup_hw_state(struct drm_device *dev)
8547 struct drm_i915_private *dev_priv = dev->dev_private;
8550 struct intel_crtc *crtc;
8551 struct intel_encoder *encoder;
8552 struct intel_connector *connector;
8554 for_each_pipe(pipe) {
8555 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8557 tmp = I915_READ(PIPECONF(pipe));
8558 if (tmp & PIPECONF_ENABLE)
8559 crtc->active = true;
8561 crtc->active = false;
8563 crtc->base.enabled = crtc->active;
8565 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8567 crtc->active ? "enabled" : "disabled");
8570 if (IS_HASWELL(dev))
8571 intel_ddi_setup_hw_pll_state(dev);
8573 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8577 if (encoder->get_hw_state(encoder, &pipe)) {
8578 encoder->base.crtc =
8579 dev_priv->pipe_to_crtc_mapping[pipe];
8581 encoder->base.crtc = NULL;
8584 encoder->connectors_active = false;
8585 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8586 encoder->base.base.id,
8587 drm_get_encoder_name(&encoder->base),
8588 encoder->base.crtc ? "enabled" : "disabled",
8592 list_for_each_entry(connector, &dev->mode_config.connector_list,
8594 if (connector->get_hw_state(connector)) {
8595 connector->base.dpms = DRM_MODE_DPMS_ON;
8596 connector->encoder->connectors_active = true;
8597 connector->base.encoder = &connector->encoder->base;
8599 connector->base.dpms = DRM_MODE_DPMS_OFF;
8600 connector->base.encoder = NULL;
8602 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8603 connector->base.base.id,
8604 drm_get_connector_name(&connector->base),
8605 connector->base.encoder ? "enabled" : "disabled");
8608 /* HW state is read out, now we need to sanitize this mess. */
8609 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8611 intel_sanitize_encoder(encoder);
8614 for_each_pipe(pipe) {
8615 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8616 intel_sanitize_crtc(crtc);
8619 intel_modeset_update_staged_output_state(dev);
8621 intel_modeset_check_state(dev);
8623 drm_mode_config_reset(dev);
8626 void intel_modeset_gem_init(struct drm_device *dev)
8628 intel_modeset_init_hw(dev);
8630 intel_setup_overlay(dev);
8632 intel_modeset_setup_hw_state(dev);
8635 void intel_modeset_cleanup(struct drm_device *dev)
8637 struct drm_i915_private *dev_priv = dev->dev_private;
8638 struct drm_crtc *crtc;
8639 struct intel_crtc *intel_crtc;
8641 drm_kms_helper_poll_fini(dev);
8642 mutex_lock(&dev->struct_mutex);
8644 intel_unregister_dsm_handler();
8647 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8648 /* Skip inactive CRTCs */
8652 intel_crtc = to_intel_crtc(crtc);
8653 intel_increase_pllclock(crtc);
8656 intel_disable_fbc(dev);
8658 intel_disable_gt_powersave(dev);
8660 ironlake_teardown_rc6(dev);
8662 if (IS_VALLEYVIEW(dev))
8665 mutex_unlock(&dev->struct_mutex);
8667 /* Disable the irq before mode object teardown, for the irq might
8668 * enqueue unpin/hotplug work. */
8669 drm_irq_uninstall(dev);
8670 cancel_work_sync(&dev_priv->hotplug_work);
8671 cancel_work_sync(&dev_priv->rps.work);
8673 /* flush any delayed tasks or pending work */
8674 flush_scheduled_work();
8676 drm_mode_config_cleanup(dev);
8680 * Return which encoder is currently attached for connector.
8682 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8684 return &intel_attached_encoder(connector)->base;
8687 void intel_connector_attach_encoder(struct intel_connector *connector,
8688 struct intel_encoder *encoder)
8690 connector->encoder = encoder;
8691 drm_mode_connector_attach_encoder(&connector->base,
8696 * set vga decode state - true == enable VGA decode
8698 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8700 struct drm_i915_private *dev_priv = dev->dev_private;
8703 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8705 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8707 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8708 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8712 #ifdef CONFIG_DEBUG_FS
8713 #include <linux/seq_file.h>
8715 struct intel_display_error_state {
8716 struct intel_cursor_error_state {
8721 } cursor[I915_MAX_PIPES];
8723 struct intel_pipe_error_state {
8733 } pipe[I915_MAX_PIPES];
8735 struct intel_plane_error_state {
8743 } plane[I915_MAX_PIPES];
8746 struct intel_display_error_state *
8747 intel_display_capture_error_state(struct drm_device *dev)
8749 drm_i915_private_t *dev_priv = dev->dev_private;
8750 struct intel_display_error_state *error;
8753 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8758 error->cursor[i].control = I915_READ(CURCNTR(i));
8759 error->cursor[i].position = I915_READ(CURPOS(i));
8760 error->cursor[i].base = I915_READ(CURBASE(i));
8762 error->plane[i].control = I915_READ(DSPCNTR(i));
8763 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8764 error->plane[i].size = I915_READ(DSPSIZE(i));
8765 error->plane[i].pos = I915_READ(DSPPOS(i));
8766 error->plane[i].addr = I915_READ(DSPADDR(i));
8767 if (INTEL_INFO(dev)->gen >= 4) {
8768 error->plane[i].surface = I915_READ(DSPSURF(i));
8769 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8772 error->pipe[i].conf = I915_READ(PIPECONF(i));
8773 error->pipe[i].source = I915_READ(PIPESRC(i));
8774 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8775 error->pipe[i].hblank = I915_READ(HBLANK(i));
8776 error->pipe[i].hsync = I915_READ(HSYNC(i));
8777 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8778 error->pipe[i].vblank = I915_READ(VBLANK(i));
8779 error->pipe[i].vsync = I915_READ(VSYNC(i));
8786 intel_display_print_error_state(struct seq_file *m,
8787 struct drm_device *dev,
8788 struct intel_display_error_state *error)
8790 drm_i915_private_t *dev_priv = dev->dev_private;
8793 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8795 seq_printf(m, "Pipe [%d]:\n", i);
8796 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8797 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8798 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8799 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8800 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8801 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8802 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8803 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8805 seq_printf(m, "Plane [%d]:\n", i);
8806 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8807 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8808 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8809 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8810 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8811 if (INTEL_INFO(dev)->gen >= 4) {
8812 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8813 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8816 seq_printf(m, "Cursor [%d]:\n", i);
8817 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8818 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8819 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);