2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
51 DRM_FORMAT_XRGB8888, \
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
73 static const uint32_t intel_cursor_formats[] = {
77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86 static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
98 static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100 static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
107 if (!connector->mst_port)
108 return connector->encoder;
110 return &connector->mst_port->mst_encoders[pipe]->base;
119 int p2_slow, p2_fast;
122 typedef struct intel_limit intel_limit_t;
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
129 intel_pch_rawclk(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
133 WARN_ON(!HAS_PCH_SPLIT(dev));
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
369 static const intel_limit_t intel_limits_vlv = {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv = {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401 static void vlv_clock(int refclk, intel_clock_t *clock)
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
412 * Returns whether any output on the specified pipe is of the specified type
414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
455 limit = &intel_limits_ironlake_dual_lvds;
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
460 limit = &intel_limits_ironlake_single_lvds;
463 limit = &intel_limits_ironlake_dac;
468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
511 limit = &intel_limits_i9xx_sdvo;
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
518 limit = &intel_limits_i8xx_dac;
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk, intel_clock_t *clock)
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
539 static void i9xx_clock(int refclk, intel_clock_t *clock)
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
549 static void chv_clock(int refclk, intel_clock_t *clock)
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
566 static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
606 struct drm_device *dev = crtc->base.dev;
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
619 clock.p2 = limit->p2.p2_slow;
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
624 clock.p2 = limit->p2.p2_fast;
627 memset(best_clock, 0, sizeof(*best_clock));
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
646 clock.p != match_clock->p)
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
659 return (err != target);
663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
667 struct drm_device *dev = crtc->base.dev;
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
680 clock.p2 = limit->p2.p2_slow;
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
685 clock.p2 = limit->p2.p2_fast;
688 memset(best_clock, 0, sizeof(*best_clock));
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
705 clock.p != match_clock->p)
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
718 return (err != target);
722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
726 struct drm_device *dev = crtc->base.dev;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
738 clock.p2 = limit->p2.p2_slow;
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
743 clock.p2 = limit->p2.p2_fast;
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
783 struct drm_device *dev = crtc->base.dev;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
790 target *= 5; /* fast clock */
792 memset(best_clock, 0, sizeof(*best_clock));
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
807 vlv_clock(refclk, &clock);
809 if (!intel_PLL_is_valid(dev, limit,
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
816 if (ppm < 100 && clock.p > best_clock->p) {
822 if (bestppm >= 10 && ppm < bestppm - 10) {
836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
840 struct drm_device *dev = crtc->base.dev;
845 memset(best_clock, 0, sizeof(*best_clock));
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
860 clock.p = clock.p1 * clock.p2;
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
865 if (m2 > INT_MAX/clock.m1)
870 chv_clock(refclk, &clock);
872 if (!intel_PLL_is_valid(dev, limit, &clock))
875 /* based on hardware requirement, prefer bigger p
877 if (clock.p > best_clock->p) {
887 bool intel_crtc_active(struct drm_crtc *crtc)
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
900 return intel_crtc->active && crtc->primary->fb &&
901 intel_crtc->config->base.adjusted_mode.crtc_clock;
904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
910 return intel_crtc->config->cpu_transcoder;
913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 u32 reg = PIPEDSL(pipe);
921 line_mask = DSL_LINEMASK_GEN2;
923 line_mask = DSL_LINEMASK_GEN3;
925 line1 = I915_READ(reg) & line_mask;
927 line2 = I915_READ(reg) & line_mask;
929 return line1 == line2;
933 * intel_wait_for_pipe_off - wait for pipe to turn off
934 * @crtc: crtc whose pipe to wait for
936 * After disabling a pipe, we can't wait for vblank in the usual way,
937 * spinning on the vblank interrupt status bit, since we won't actually
938 * see an interrupt when the pipe is disabled.
941 * wait for the pipe register state bit to turn off
944 * wait for the display line value to settle (it usually
945 * ends up stopping at the start of the next frame).
948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
950 struct drm_device *dev = crtc->base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
953 enum pipe pipe = crtc->pipe;
955 if (INTEL_INFO(dev)->gen >= 4) {
956 int reg = PIPECONF(cpu_transcoder);
958 /* Wait for the Pipe State to go off */
959 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
961 WARN(1, "pipe_off wait timed out\n");
963 /* Wait for the display line to settle */
964 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
965 WARN(1, "pipe_off wait timed out\n");
970 * ibx_digital_port_connected - is the specified port connected?
971 * @dev_priv: i915 private structure
972 * @port: the port to test
974 * Returns true if @port is connected, false otherwise.
976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
977 struct intel_digital_port *port)
981 if (HAS_PCH_IBX(dev_priv->dev)) {
982 switch (port->port) {
984 bit = SDE_PORTB_HOTPLUG;
987 bit = SDE_PORTC_HOTPLUG;
990 bit = SDE_PORTD_HOTPLUG;
996 switch (port->port) {
998 bit = SDE_PORTB_HOTPLUG_CPT;
1001 bit = SDE_PORTC_HOTPLUG_CPT;
1004 bit = SDE_PORTD_HOTPLUG_CPT;
1011 return I915_READ(SDEISR) & bit;
1014 static const char *state_string(bool enabled)
1016 return enabled ? "on" : "off";
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, bool state)
1028 val = I915_READ(reg);
1029 cur_state = !!(val & DPLL_VCO_ENABLE);
1030 I915_STATE_WARN(cur_state != state,
1031 "PLL state assertion failure (expected %s, current %s)\n",
1032 state_string(state), state_string(cur_state));
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1041 mutex_lock(&dev_priv->dpio_lock);
1042 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043 mutex_unlock(&dev_priv->dpio_lock);
1045 cur_state = val & DSI_PLL_VCO_EN;
1046 I915_STATE_WARN(cur_state != state,
1047 "DSI PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state), state_string(cur_state));
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1056 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1058 if (crtc->config->shared_dpll < 0)
1061 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066 struct intel_shared_dpll *pll,
1070 struct intel_dpll_hw_state hw_state;
1073 "asserting DPLL %s with no DPLL\n", state_string(state)))
1076 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077 I915_STATE_WARN(cur_state != state,
1078 "%s assertion failure (expected %s, current %s)\n",
1079 pll->name, state_string(state), state_string(cur_state));
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083 enum pipe pipe, bool state)
1088 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1091 if (HAS_DDI(dev_priv->dev)) {
1092 /* DDI does not have a specific FDI_TX register */
1093 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094 val = I915_READ(reg);
1095 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1097 reg = FDI_TX_CTL(pipe);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & FDI_TX_ENABLE);
1101 I915_STATE_WARN(cur_state != state,
1102 "FDI TX state assertion failure (expected %s, current %s)\n",
1103 state_string(state), state_string(cur_state));
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109 enum pipe pipe, bool state)
1115 reg = FDI_RX_CTL(pipe);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 state_string(state), state_string(cur_state));
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1131 /* ILK FDI PLL is always enabled */
1132 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1135 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136 if (HAS_DDI(dev_priv->dev))
1139 reg = FDI_TX_CTL(pipe);
1140 val = I915_READ(reg);
1141 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154 I915_STATE_WARN(cur_state != state,
1155 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1162 struct drm_device *dev = dev_priv->dev;
1165 enum pipe panel_pipe = PIPE_A;
1168 if (WARN_ON(HAS_DDI(dev)))
1171 if (HAS_PCH_SPLIT(dev)) {
1174 pp_reg = PCH_PP_CONTROL;
1175 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1177 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179 panel_pipe = PIPE_B;
1180 /* XXX: else fix for eDP */
1181 } else if (IS_VALLEYVIEW(dev)) {
1182 /* presumably write lock depends on pipe, not port select */
1183 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1186 pp_reg = PP_CONTROL;
1187 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188 panel_pipe = PIPE_B;
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1196 I915_STATE_WARN(panel_pipe == pipe && locked,
1197 "panel assertion failure, pipe %c regs locked\n",
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state)
1204 struct drm_device *dev = dev_priv->dev;
1207 if (IS_845G(dev) || IS_I865G(dev))
1208 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1210 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1212 I915_STATE_WARN(cur_state != state,
1213 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214 pipe_name(pipe), state_string(state), state_string(cur_state));
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228 /* if we need the pipe quirk it must be always on */
1229 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1233 if (!intel_display_power_is_enabled(dev_priv,
1234 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1237 reg = PIPECONF(cpu_transcoder);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & PIPECONF_ENABLE);
1242 I915_STATE_WARN(cur_state != state,
1243 "pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe), state_string(state), state_string(cur_state));
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248 enum plane plane, bool state)
1254 reg = DSPCNTR(plane);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "plane %c assertion failure (expected %s, current %s)\n",
1259 plane_name(plane), state_string(state), state_string(cur_state));
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1268 struct drm_device *dev = dev_priv->dev;
1273 /* Primary planes are fixed to pipes on gen4+ */
1274 if (INTEL_INFO(dev)->gen >= 4) {
1275 reg = DSPCNTR(pipe);
1276 val = I915_READ(reg);
1277 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278 "plane %c assertion failure, should be disabled but not\n",
1283 /* Need to check both planes against the pipe */
1284 for_each_pipe(dev_priv, i) {
1286 val = I915_READ(reg);
1287 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288 DISPPLANE_SEL_PIPE_SHIFT;
1289 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(i), pipe_name(pipe));
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1298 struct drm_device *dev = dev_priv->dev;
1302 if (INTEL_INFO(dev)->gen >= 9) {
1303 for_each_sprite(dev_priv, pipe, sprite) {
1304 val = I915_READ(PLANE_CTL(pipe, sprite));
1305 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307 sprite, pipe_name(pipe));
1309 } else if (IS_VALLEYVIEW(dev)) {
1310 for_each_sprite(dev_priv, pipe, sprite) {
1311 reg = SPCNTR(pipe, sprite);
1312 val = I915_READ(reg);
1313 I915_STATE_WARN(val & SP_ENABLE,
1314 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315 sprite_name(pipe, sprite), pipe_name(pipe));
1317 } else if (INTEL_INFO(dev)->gen >= 7) {
1319 val = I915_READ(reg);
1320 I915_STATE_WARN(val & SPRITE_ENABLE,
1321 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322 plane_name(pipe), pipe_name(pipe));
1323 } else if (INTEL_INFO(dev)->gen >= 5) {
1324 reg = DVSCNTR(pipe);
1325 val = I915_READ(reg);
1326 I915_STATE_WARN(val & DVS_ENABLE,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 plane_name(pipe), pipe_name(pipe));
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1334 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335 drm_crtc_vblank_put(crtc);
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1343 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1345 val = I915_READ(PCH_DREF_CONTROL);
1346 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347 DREF_SUPERSPREAD_SOURCE_MASK));
1348 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1358 reg = PCH_TRANSCONF(pipe);
1359 val = I915_READ(reg);
1360 enabled = !!(val & TRANS_ENABLE);
1361 I915_STATE_WARN(enabled,
1362 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367 enum pipe pipe, u32 port_sel, u32 val)
1369 if ((val & DP_PORT_EN) == 0)
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1377 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1390 if ((val & SDVO_ENABLE) == 0)
1393 if (HAS_PCH_CPT(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1396 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1409 if ((val & LVDS_PORT_EN) == 0)
1412 if (HAS_PCH_CPT(dev_priv->dev)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1427 if (HAS_PCH_CPT(dev_priv->dev)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, int reg, u32 port_sel)
1440 u32 val = I915_READ(reg);
1441 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443 reg, pipe_name(pipe));
1445 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446 && (val & DP_PIPEB_SELECT),
1447 "IBX PCH dp port still using transcoder B\n");
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, int reg)
1453 u32 val = I915_READ(reg);
1454 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456 reg, pipe_name(pipe));
1458 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459 && (val & SDVO_PIPE_B_SELECT),
1460 "IBX PCH hdmi port still using transcoder B\n");
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1474 val = I915_READ(reg);
1475 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476 "PCH VGA enabled on transcoder %c, should be disabled\n",
1480 val = I915_READ(reg);
1481 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1490 static void intel_init_dpio(struct drm_device *dev)
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1494 if (!IS_VALLEYVIEW(dev))
1498 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499 * CHV x1 PHY (DP/HDMI D)
1500 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1502 if (IS_CHERRYVIEW(dev)) {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511 const struct intel_crtc_state *pipe_config)
1513 struct drm_device *dev = crtc->base.dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 int reg = DPLL(crtc->pipe);
1516 u32 dpll = pipe_config->dpll_hw_state.dpll;
1518 assert_pipe_disabled(dev_priv, crtc->pipe);
1520 /* No really, not for ILK+ */
1521 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1523 /* PLL is protected by panel, make sure we can write it */
1524 if (IS_MOBILE(dev_priv->dev))
1525 assert_panel_unlocked(dev_priv, crtc->pipe);
1527 I915_WRITE(reg, dpll);
1531 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1534 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535 POSTING_READ(DPLL_MD(crtc->pipe));
1537 /* We do this three times for luck */
1538 I915_WRITE(reg, dpll);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1543 udelay(150); /* wait for warmup */
1544 I915_WRITE(reg, dpll);
1546 udelay(150); /* wait for warmup */
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550 const struct intel_crtc_state *pipe_config)
1552 struct drm_device *dev = crtc->base.dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 int pipe = crtc->pipe;
1555 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1558 assert_pipe_disabled(dev_priv, crtc->pipe);
1560 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1562 mutex_lock(&dev_priv->dpio_lock);
1564 /* Enable back the 10bit clock to display controller */
1565 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566 tmp |= DPIO_DCLKP_EN;
1567 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1570 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1575 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1577 /* Check PLL is locked */
1578 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579 DRM_ERROR("PLL %d failed to lock\n", pipe);
1581 /* not sure when this should be written */
1582 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583 POSTING_READ(DPLL_MD(pipe));
1585 mutex_unlock(&dev_priv->dpio_lock);
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1590 struct intel_crtc *crtc;
1593 for_each_intel_crtc(dev, crtc)
1594 count += crtc->active &&
1595 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1602 struct drm_device *dev = crtc->base.dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 int reg = DPLL(crtc->pipe);
1605 u32 dpll = crtc->config->dpll_hw_state.dpll;
1607 assert_pipe_disabled(dev_priv, crtc->pipe);
1609 /* No really, not for ILK+ */
1610 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1612 /* PLL is protected by panel, make sure we can write it */
1613 if (IS_MOBILE(dev) && !IS_I830(dev))
1614 assert_panel_unlocked(dev_priv, crtc->pipe);
1616 /* Enable DVO 2x clock on both PLLs if necessary */
1617 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1619 * It appears to be important that we don't enable this
1620 * for the current pipe before otherwise configuring the
1621 * PLL. No idea how this should be handled if multiple
1622 * DVO outputs are enabled simultaneosly.
1624 dpll |= DPLL_DVO_2X_MODE;
1625 I915_WRITE(DPLL(!crtc->pipe),
1626 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1629 /* Wait for the clocks to stabilize. */
1633 if (INTEL_INFO(dev)->gen >= 4) {
1634 I915_WRITE(DPLL_MD(crtc->pipe),
1635 crtc->config->dpll_hw_state.dpll_md);
1637 /* The pixel multiplier can only be updated once the
1638 * DPLL is enabled and the clocks are stable.
1640 * So write it again.
1642 I915_WRITE(reg, dpll);
1645 /* We do this three times for luck */
1646 I915_WRITE(reg, dpll);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1651 udelay(150); /* wait for warmup */
1652 I915_WRITE(reg, dpll);
1654 udelay(150); /* wait for warmup */
1658 * i9xx_disable_pll - disable a PLL
1659 * @dev_priv: i915 private structure
1660 * @pipe: pipe PLL to disable
1662 * Disable the PLL for @pipe, making sure the pipe is off first.
1664 * Note! This is for pre-ILK only.
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1668 struct drm_device *dev = crtc->base.dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 enum pipe pipe = crtc->pipe;
1672 /* Disable DVO 2x clock on both PLLs if necessary */
1674 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675 intel_num_dvo_pipes(dev) == 1) {
1676 I915_WRITE(DPLL(PIPE_B),
1677 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678 I915_WRITE(DPLL(PIPE_A),
1679 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1682 /* Don't disable pipe or pipe PLLs if needed */
1683 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1687 /* Make sure the pipe isn't still relying on us */
1688 assert_pipe_disabled(dev_priv, pipe);
1690 I915_WRITE(DPLL(pipe), 0);
1691 POSTING_READ(DPLL(pipe));
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1702 * Leave integrated clock source and reference clock enabled for pipe B.
1703 * The latter is needed for VGA hotplug / manual detection.
1706 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1714 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv, pipe);
1720 /* Set PLL en = 0 */
1721 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1723 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1727 mutex_lock(&dev_priv->dpio_lock);
1729 /* Disable 10bit clock to display controller */
1730 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731 val &= ~DPIO_DCLKP_EN;
1732 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1734 /* disable left/right clock distribution */
1735 if (pipe != PIPE_B) {
1736 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1745 mutex_unlock(&dev_priv->dpio_lock);
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749 struct intel_digital_port *dport)
1754 switch (dport->port) {
1756 port_mask = DPLL_PORTB_READY_MASK;
1760 port_mask = DPLL_PORTC_READY_MASK;
1764 port_mask = DPLL_PORTD_READY_MASK;
1765 dpll_reg = DPIO_PHY_STATUS;
1771 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773 port_name(dport->port), I915_READ(dpll_reg));
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1782 if (WARN_ON(pll == NULL))
1785 WARN_ON(!pll->config.crtc_mask);
1786 if (pll->active == 0) {
1787 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1789 assert_shared_dpll_disabled(dev_priv, pll);
1791 pll->mode_set(dev_priv, pll);
1796 * intel_enable_shared_dpll - enable PCH PLL
1797 * @dev_priv: i915 private structure
1798 * @pipe: pipe PLL to enable
1800 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801 * drives the transcoder clock.
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1809 if (WARN_ON(pll == NULL))
1812 if (WARN_ON(pll->config.crtc_mask == 0))
1815 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816 pll->name, pll->active, pll->on,
1817 crtc->base.base.id);
1819 if (pll->active++) {
1821 assert_shared_dpll_enabled(dev_priv, pll);
1826 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1828 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829 pll->enable(dev_priv, pll);
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1835 struct drm_device *dev = crtc->base.dev;
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1837 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev)->gen < 5);
1841 if (WARN_ON(pll == NULL))
1844 if (WARN_ON(pll->config.crtc_mask == 0))
1847 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848 pll->name, pll->active, pll->on,
1849 crtc->base.base.id);
1851 if (WARN_ON(pll->active == 0)) {
1852 assert_shared_dpll_disabled(dev_priv, pll);
1856 assert_shared_dpll_enabled(dev_priv, pll);
1861 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862 pll->disable(dev_priv, pll);
1865 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1871 struct drm_device *dev = dev_priv->dev;
1872 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874 uint32_t reg, val, pipeconf_val;
1876 /* PCH only available on ILK+ */
1877 BUG_ON(!HAS_PCH_SPLIT(dev));
1879 /* Make sure PCH DPLL is enabled */
1880 assert_shared_dpll_enabled(dev_priv,
1881 intel_crtc_to_shared_dpll(intel_crtc));
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, pipe);
1885 assert_fdi_rx_enabled(dev_priv, pipe);
1887 if (HAS_PCH_CPT(dev)) {
1888 /* Workaround: Set the timing override bit before enabling the
1889 * pch transcoder. */
1890 reg = TRANS_CHICKEN2(pipe);
1891 val = I915_READ(reg);
1892 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893 I915_WRITE(reg, val);
1896 reg = PCH_TRANSCONF(pipe);
1897 val = I915_READ(reg);
1898 pipeconf_val = I915_READ(PIPECONF(pipe));
1900 if (HAS_PCH_IBX(dev_priv->dev)) {
1902 * make the BPC in transcoder be consistent with
1903 * that in pipeconf reg.
1905 val &= ~PIPECONF_BPC_MASK;
1906 val |= pipeconf_val & PIPECONF_BPC_MASK;
1909 val &= ~TRANS_INTERLACE_MASK;
1910 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911 if (HAS_PCH_IBX(dev_priv->dev) &&
1912 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913 val |= TRANS_LEGACY_INTERLACED_ILK;
1915 val |= TRANS_INTERLACED;
1917 val |= TRANS_PROGRESSIVE;
1919 I915_WRITE(reg, val | TRANS_ENABLE);
1920 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925 enum transcoder cpu_transcoder)
1927 u32 val, pipeconf_val;
1929 /* PCH only available on ILK+ */
1930 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1932 /* FDI must be feeding us bits for PCH ports */
1933 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1936 /* Workaround: set timing override bit. */
1937 val = I915_READ(_TRANSA_CHICKEN2);
1938 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939 I915_WRITE(_TRANSA_CHICKEN2, val);
1942 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1944 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945 PIPECONF_INTERLACED_ILK)
1946 val |= TRANS_INTERLACED;
1948 val |= TRANS_PROGRESSIVE;
1950 I915_WRITE(LPT_TRANSCONF, val);
1951 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952 DRM_ERROR("Failed to enable PCH transcoder\n");
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1958 struct drm_device *dev = dev_priv->dev;
1961 /* FDI relies on the transcoder */
1962 assert_fdi_tx_disabled(dev_priv, pipe);
1963 assert_fdi_rx_disabled(dev_priv, pipe);
1965 /* Ports must be off as well */
1966 assert_pch_ports_disabled(dev_priv, pipe);
1968 reg = PCH_TRANSCONF(pipe);
1969 val = I915_READ(reg);
1970 val &= ~TRANS_ENABLE;
1971 I915_WRITE(reg, val);
1972 /* wait for PCH transcoder off, transcoder state */
1973 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1976 if (!HAS_PCH_IBX(dev)) {
1977 /* Workaround: Clear the timing override chicken bit again. */
1978 reg = TRANS_CHICKEN2(pipe);
1979 val = I915_READ(reg);
1980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981 I915_WRITE(reg, val);
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1989 val = I915_READ(LPT_TRANSCONF);
1990 val &= ~TRANS_ENABLE;
1991 I915_WRITE(LPT_TRANSCONF, val);
1992 /* wait for PCH transcoder off, transcoder state */
1993 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994 DRM_ERROR("Failed to disable PCH transcoder\n");
1996 /* Workaround: clear timing override bit. */
1997 val = I915_READ(_TRANSA_CHICKEN2);
1998 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999 I915_WRITE(_TRANSA_CHICKEN2, val);
2003 * intel_enable_pipe - enable a pipe, asserting requirements
2004 * @crtc: crtc responsible for the pipe
2006 * Enable @crtc's pipe, making sure that various hardware specific requirements
2007 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2011 struct drm_device *dev = crtc->base.dev;
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2013 enum pipe pipe = crtc->pipe;
2014 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2016 enum pipe pch_transcoder;
2020 assert_planes_disabled(dev_priv, pipe);
2021 assert_cursor_disabled(dev_priv, pipe);
2022 assert_sprites_disabled(dev_priv, pipe);
2024 if (HAS_PCH_LPT(dev_priv->dev))
2025 pch_transcoder = TRANSCODER_A;
2027 pch_transcoder = pipe;
2030 * A pipe without a PLL won't actually be able to drive bits from
2031 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2034 if (!HAS_PCH_SPLIT(dev_priv->dev))
2035 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036 assert_dsi_pll_enabled(dev_priv);
2038 assert_pll_enabled(dev_priv, pipe);
2040 if (crtc->config->has_pch_encoder) {
2041 /* if driving the PCH, we need FDI enabled */
2042 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043 assert_fdi_tx_pll_enabled(dev_priv,
2044 (enum pipe) cpu_transcoder);
2046 /* FIXME: assert CPU port conditions for SNB+ */
2049 reg = PIPECONF(cpu_transcoder);
2050 val = I915_READ(reg);
2051 if (val & PIPECONF_ENABLE) {
2052 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2057 I915_WRITE(reg, val | PIPECONF_ENABLE);
2062 * intel_disable_pipe - disable a pipe, asserting requirements
2063 * @crtc: crtc whose pipes is to be disabled
2065 * Disable the pipe of @crtc, making sure that various hardware
2066 * specific requirements are met, if applicable, e.g. plane
2067 * disabled, panel fitter off, etc.
2069 * Will wait until the pipe has shut down before returning.
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2073 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075 enum pipe pipe = crtc->pipe;
2080 * Make sure planes won't keep trying to pump pixels to us,
2081 * or we might hang the display.
2083 assert_planes_disabled(dev_priv, pipe);
2084 assert_cursor_disabled(dev_priv, pipe);
2085 assert_sprites_disabled(dev_priv, pipe);
2087 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0)
2093 * Double wide has implications for planes
2094 * so best keep it disabled when not needed.
2096 if (crtc->config->double_wide)
2097 val &= ~PIPECONF_DOUBLE_WIDE;
2099 /* Don't disable pipe or pipe PLLs if needed */
2100 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102 val &= ~PIPECONF_ENABLE;
2104 I915_WRITE(reg, val);
2105 if ((val & PIPECONF_ENABLE) == 0)
2106 intel_wait_for_pipe_off(crtc);
2110 * Plane regs are double buffered, going from enabled->disabled needs a
2111 * trigger in order to latch. The display address reg provides this.
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2116 struct drm_device *dev = dev_priv->dev;
2117 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2119 I915_WRITE(reg, I915_READ(reg));
2124 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125 * @plane: plane to be enabled
2126 * @crtc: crtc for the plane
2128 * Enable @plane on @crtc, making sure that the pipe is running first.
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131 struct drm_crtc *crtc)
2133 struct drm_device *dev = plane->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2137 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2140 if (intel_crtc->primary_enabled)
2143 intel_crtc->primary_enabled = true;
2145 dev_priv->display.update_primary_plane(crtc, plane->fb,
2149 * BDW signals flip done immediately if the plane
2150 * is disabled, even if the plane enable is already
2151 * armed to occur at the next vblank :(
2153 if (IS_BROADWELL(dev))
2154 intel_wait_for_vblank(dev, intel_crtc->pipe);
2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
2159 * @plane: plane to be disabled
2160 * @crtc: crtc for the plane
2162 * Disable @plane on @crtc, making sure that the pipe is running first.
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165 struct drm_crtc *crtc)
2167 struct drm_device *dev = plane->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2171 if (WARN_ON(!intel_crtc->active))
2174 if (!intel_crtc->primary_enabled)
2177 intel_crtc->primary_enabled = false;
2179 dev_priv->display.update_primary_plane(crtc, plane->fb,
2183 static bool need_vtd_wa(struct drm_device *dev)
2185 #ifdef CONFIG_INTEL_IOMMU
2186 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2193 intel_fb_align_height(struct drm_device *dev, int height,
2194 uint32_t pixel_format,
2195 uint64_t fb_format_modifier)
2198 uint32_t bits_per_pixel;
2200 switch (fb_format_modifier) {
2201 case DRM_FORMAT_MOD_NONE:
2204 case I915_FORMAT_MOD_X_TILED:
2205 tile_height = IS_GEN2(dev) ? 16 : 8;
2207 case I915_FORMAT_MOD_Y_TILED:
2210 case I915_FORMAT_MOD_Yf_TILED:
2211 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2212 switch (bits_per_pixel) {
2226 "128-bit pixels are not supported for display!");
2232 MISSING_CASE(fb_format_modifier);
2237 return ALIGN(height, tile_height);
2241 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2242 struct drm_framebuffer *fb,
2243 struct intel_engine_cs *pipelined)
2245 struct drm_device *dev = fb->dev;
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2251 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2253 switch (fb->modifier[0]) {
2254 case DRM_FORMAT_MOD_NONE:
2255 if (INTEL_INFO(dev)->gen >= 9)
2256 alignment = 256 * 1024;
2257 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2258 alignment = 128 * 1024;
2259 else if (INTEL_INFO(dev)->gen >= 4)
2260 alignment = 4 * 1024;
2262 alignment = 64 * 1024;
2264 case I915_FORMAT_MOD_X_TILED:
2265 if (INTEL_INFO(dev)->gen >= 9)
2266 alignment = 256 * 1024;
2268 /* pin() will align the object as required by fence */
2272 case I915_FORMAT_MOD_Y_TILED:
2273 case I915_FORMAT_MOD_Yf_TILED:
2274 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2275 "Y tiling bo slipped through, driver bug!\n"))
2277 alignment = 1 * 1024 * 1024;
2280 MISSING_CASE(fb->modifier[0]);
2284 /* Note that the w/a also requires 64 PTE of padding following the
2285 * bo. We currently fill all unused PTE with the shadow page and so
2286 * we should always have valid PTE following the scanout preventing
2289 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2290 alignment = 256 * 1024;
2293 * Global gtt pte registers are special registers which actually forward
2294 * writes to a chunk of system memory. Which means that there is no risk
2295 * that the register values disappear as soon as we call
2296 * intel_runtime_pm_put(), so it is correct to wrap only the
2297 * pin/unpin/fence and not more.
2299 intel_runtime_pm_get(dev_priv);
2301 dev_priv->mm.interruptible = false;
2302 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2304 goto err_interruptible;
2306 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2307 * fence, whereas 965+ only requires a fence if using
2308 * framebuffer compression. For simplicity, we always install
2309 * a fence as the cost is not that onerous.
2311 ret = i915_gem_object_get_fence(obj);
2315 i915_gem_object_pin_fence(obj);
2317 dev_priv->mm.interruptible = true;
2318 intel_runtime_pm_put(dev_priv);
2322 i915_gem_object_unpin_from_display_plane(obj);
2324 dev_priv->mm.interruptible = true;
2325 intel_runtime_pm_put(dev_priv);
2329 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2331 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2333 i915_gem_object_unpin_fence(obj);
2334 i915_gem_object_unpin_from_display_plane(obj);
2337 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2338 * is assumed to be a power-of-two. */
2339 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2340 unsigned int tiling_mode,
2344 if (tiling_mode != I915_TILING_NONE) {
2345 unsigned int tile_rows, tiles;
2350 tiles = *x / (512/cpp);
2353 return tile_rows * pitch * 8 + tiles * 4096;
2355 unsigned int offset;
2357 offset = *y * pitch + *x * cpp;
2359 *x = (offset & 4095) / cpp;
2360 return offset & -4096;
2364 static int i9xx_format_to_fourcc(int format)
2367 case DISPPLANE_8BPP:
2368 return DRM_FORMAT_C8;
2369 case DISPPLANE_BGRX555:
2370 return DRM_FORMAT_XRGB1555;
2371 case DISPPLANE_BGRX565:
2372 return DRM_FORMAT_RGB565;
2374 case DISPPLANE_BGRX888:
2375 return DRM_FORMAT_XRGB8888;
2376 case DISPPLANE_RGBX888:
2377 return DRM_FORMAT_XBGR8888;
2378 case DISPPLANE_BGRX101010:
2379 return DRM_FORMAT_XRGB2101010;
2380 case DISPPLANE_RGBX101010:
2381 return DRM_FORMAT_XBGR2101010;
2385 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2388 case PLANE_CTL_FORMAT_RGB_565:
2389 return DRM_FORMAT_RGB565;
2391 case PLANE_CTL_FORMAT_XRGB_8888:
2394 return DRM_FORMAT_ABGR8888;
2396 return DRM_FORMAT_XBGR8888;
2399 return DRM_FORMAT_ARGB8888;
2401 return DRM_FORMAT_XRGB8888;
2403 case PLANE_CTL_FORMAT_XRGB_2101010:
2405 return DRM_FORMAT_XBGR2101010;
2407 return DRM_FORMAT_XRGB2101010;
2412 intel_alloc_plane_obj(struct intel_crtc *crtc,
2413 struct intel_initial_plane_config *plane_config)
2415 struct drm_device *dev = crtc->base.dev;
2416 struct drm_i915_gem_object *obj = NULL;
2417 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2418 struct drm_framebuffer *fb = &plane_config->fb->base;
2419 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2420 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2423 size_aligned -= base_aligned;
2425 if (plane_config->size == 0)
2428 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2435 obj->tiling_mode = plane_config->tiling;
2436 if (obj->tiling_mode == I915_TILING_X)
2437 obj->stride = fb->pitches[0];
2439 mode_cmd.pixel_format = fb->pixel_format;
2440 mode_cmd.width = fb->width;
2441 mode_cmd.height = fb->height;
2442 mode_cmd.pitches[0] = fb->pitches[0];
2443 mode_cmd.modifier[0] = fb->modifier[0];
2444 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2446 mutex_lock(&dev->struct_mutex);
2448 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2450 DRM_DEBUG_KMS("intel fb init failed\n");
2454 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2455 mutex_unlock(&dev->struct_mutex);
2457 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2461 drm_gem_object_unreference(&obj->base);
2462 mutex_unlock(&dev->struct_mutex);
2466 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2468 update_state_fb(struct drm_plane *plane)
2470 if (plane->fb == plane->state->fb)
2473 if (plane->state->fb)
2474 drm_framebuffer_unreference(plane->state->fb);
2475 plane->state->fb = plane->fb;
2476 if (plane->state->fb)
2477 drm_framebuffer_reference(plane->state->fb);
2481 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2482 struct intel_initial_plane_config *plane_config)
2484 struct drm_device *dev = intel_crtc->base.dev;
2485 struct drm_i915_private *dev_priv = dev->dev_private;
2487 struct intel_crtc *i;
2488 struct drm_i915_gem_object *obj;
2490 if (!plane_config->fb)
2493 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2494 struct drm_plane *primary = intel_crtc->base.primary;
2496 primary->fb = &plane_config->fb->base;
2497 primary->state->crtc = &intel_crtc->base;
2498 update_state_fb(primary);
2503 kfree(plane_config->fb);
2506 * Failed to alloc the obj, check to see if we should share
2507 * an fb with another CRTC instead
2509 for_each_crtc(dev, c) {
2510 i = to_intel_crtc(c);
2512 if (c == &intel_crtc->base)
2518 obj = intel_fb_obj(c->primary->fb);
2522 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2523 struct drm_plane *primary = intel_crtc->base.primary;
2525 if (obj->tiling_mode != I915_TILING_NONE)
2526 dev_priv->preserve_bios_swizzle = true;
2528 drm_framebuffer_reference(c->primary->fb);
2529 primary->fb = c->primary->fb;
2530 primary->state->crtc = &intel_crtc->base;
2531 update_state_fb(intel_crtc->base.primary);
2532 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2539 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2540 struct drm_framebuffer *fb,
2543 struct drm_device *dev = crtc->dev;
2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2546 struct drm_i915_gem_object *obj;
2547 int plane = intel_crtc->plane;
2548 unsigned long linear_offset;
2550 u32 reg = DSPCNTR(plane);
2553 if (!intel_crtc->primary_enabled) {
2555 if (INTEL_INFO(dev)->gen >= 4)
2556 I915_WRITE(DSPSURF(plane), 0);
2558 I915_WRITE(DSPADDR(plane), 0);
2563 obj = intel_fb_obj(fb);
2564 if (WARN_ON(obj == NULL))
2567 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2569 dspcntr = DISPPLANE_GAMMA_ENABLE;
2571 dspcntr |= DISPLAY_PLANE_ENABLE;
2573 if (INTEL_INFO(dev)->gen < 4) {
2574 if (intel_crtc->pipe == PIPE_B)
2575 dspcntr |= DISPPLANE_SEL_PIPE_B;
2577 /* pipesrc and dspsize control the size that is scaled from,
2578 * which should always be the user's requested size.
2580 I915_WRITE(DSPSIZE(plane),
2581 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2582 (intel_crtc->config->pipe_src_w - 1));
2583 I915_WRITE(DSPPOS(plane), 0);
2584 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2585 I915_WRITE(PRIMSIZE(plane),
2586 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2587 (intel_crtc->config->pipe_src_w - 1));
2588 I915_WRITE(PRIMPOS(plane), 0);
2589 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2592 switch (fb->pixel_format) {
2594 dspcntr |= DISPPLANE_8BPP;
2596 case DRM_FORMAT_XRGB1555:
2597 case DRM_FORMAT_ARGB1555:
2598 dspcntr |= DISPPLANE_BGRX555;
2600 case DRM_FORMAT_RGB565:
2601 dspcntr |= DISPPLANE_BGRX565;
2603 case DRM_FORMAT_XRGB8888:
2604 case DRM_FORMAT_ARGB8888:
2605 dspcntr |= DISPPLANE_BGRX888;
2607 case DRM_FORMAT_XBGR8888:
2608 case DRM_FORMAT_ABGR8888:
2609 dspcntr |= DISPPLANE_RGBX888;
2611 case DRM_FORMAT_XRGB2101010:
2612 case DRM_FORMAT_ARGB2101010:
2613 dspcntr |= DISPPLANE_BGRX101010;
2615 case DRM_FORMAT_XBGR2101010:
2616 case DRM_FORMAT_ABGR2101010:
2617 dspcntr |= DISPPLANE_RGBX101010;
2623 if (INTEL_INFO(dev)->gen >= 4 &&
2624 obj->tiling_mode != I915_TILING_NONE)
2625 dspcntr |= DISPPLANE_TILED;
2628 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2630 linear_offset = y * fb->pitches[0] + x * pixel_size;
2632 if (INTEL_INFO(dev)->gen >= 4) {
2633 intel_crtc->dspaddr_offset =
2634 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2637 linear_offset -= intel_crtc->dspaddr_offset;
2639 intel_crtc->dspaddr_offset = linear_offset;
2642 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2643 dspcntr |= DISPPLANE_ROTATE_180;
2645 x += (intel_crtc->config->pipe_src_w - 1);
2646 y += (intel_crtc->config->pipe_src_h - 1);
2648 /* Finding the last pixel of the last line of the display
2649 data and adding to linear_offset*/
2651 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2652 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2655 I915_WRITE(reg, dspcntr);
2657 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2658 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2660 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2661 if (INTEL_INFO(dev)->gen >= 4) {
2662 I915_WRITE(DSPSURF(plane),
2663 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2664 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2665 I915_WRITE(DSPLINOFF(plane), linear_offset);
2667 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2671 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2672 struct drm_framebuffer *fb,
2675 struct drm_device *dev = crtc->dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2678 struct drm_i915_gem_object *obj;
2679 int plane = intel_crtc->plane;
2680 unsigned long linear_offset;
2682 u32 reg = DSPCNTR(plane);
2685 if (!intel_crtc->primary_enabled) {
2687 I915_WRITE(DSPSURF(plane), 0);
2692 obj = intel_fb_obj(fb);
2693 if (WARN_ON(obj == NULL))
2696 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2698 dspcntr = DISPPLANE_GAMMA_ENABLE;
2700 dspcntr |= DISPLAY_PLANE_ENABLE;
2702 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2703 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2705 switch (fb->pixel_format) {
2707 dspcntr |= DISPPLANE_8BPP;
2709 case DRM_FORMAT_RGB565:
2710 dspcntr |= DISPPLANE_BGRX565;
2712 case DRM_FORMAT_XRGB8888:
2713 case DRM_FORMAT_ARGB8888:
2714 dspcntr |= DISPPLANE_BGRX888;
2716 case DRM_FORMAT_XBGR8888:
2717 case DRM_FORMAT_ABGR8888:
2718 dspcntr |= DISPPLANE_RGBX888;
2720 case DRM_FORMAT_XRGB2101010:
2721 case DRM_FORMAT_ARGB2101010:
2722 dspcntr |= DISPPLANE_BGRX101010;
2724 case DRM_FORMAT_XBGR2101010:
2725 case DRM_FORMAT_ABGR2101010:
2726 dspcntr |= DISPPLANE_RGBX101010;
2732 if (obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
2735 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2738 linear_offset = y * fb->pitches[0] + x * pixel_size;
2739 intel_crtc->dspaddr_offset =
2740 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2743 linear_offset -= intel_crtc->dspaddr_offset;
2744 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2745 dspcntr |= DISPPLANE_ROTATE_180;
2747 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2748 x += (intel_crtc->config->pipe_src_w - 1);
2749 y += (intel_crtc->config->pipe_src_h - 1);
2751 /* Finding the last pixel of the last line of the display
2752 data and adding to linear_offset*/
2754 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2755 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2759 I915_WRITE(reg, dspcntr);
2761 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2762 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2764 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2765 I915_WRITE(DSPSURF(plane),
2766 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2767 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2768 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2770 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2771 I915_WRITE(DSPLINOFF(plane), linear_offset);
2776 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2777 uint32_t pixel_format)
2779 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2782 * The stride is either expressed as a multiple of 64 bytes
2783 * chunks for linear buffers or in number of tiles for tiled
2786 switch (fb_modifier) {
2787 case DRM_FORMAT_MOD_NONE:
2789 case I915_FORMAT_MOD_X_TILED:
2790 if (INTEL_INFO(dev)->gen == 2)
2793 case I915_FORMAT_MOD_Y_TILED:
2794 /* No need to check for old gens and Y tiling since this is
2795 * about the display engine and those will be blocked before
2799 case I915_FORMAT_MOD_Yf_TILED:
2800 if (bits_per_pixel == 8)
2805 MISSING_CASE(fb_modifier);
2810 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2811 struct drm_framebuffer *fb,
2814 struct drm_device *dev = crtc->dev;
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2817 struct drm_i915_gem_object *obj;
2818 int pipe = intel_crtc->pipe;
2819 u32 plane_ctl, stride_div;
2821 if (!intel_crtc->primary_enabled) {
2822 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2823 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2824 POSTING_READ(PLANE_CTL(pipe, 0));
2828 plane_ctl = PLANE_CTL_ENABLE |
2829 PLANE_CTL_PIPE_GAMMA_ENABLE |
2830 PLANE_CTL_PIPE_CSC_ENABLE;
2832 switch (fb->pixel_format) {
2833 case DRM_FORMAT_RGB565:
2834 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2836 case DRM_FORMAT_XRGB8888:
2837 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2839 case DRM_FORMAT_ARGB8888:
2840 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2841 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2843 case DRM_FORMAT_XBGR8888:
2844 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2845 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2847 case DRM_FORMAT_ABGR8888:
2848 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2849 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2850 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2852 case DRM_FORMAT_XRGB2101010:
2853 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2855 case DRM_FORMAT_XBGR2101010:
2856 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2857 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2863 switch (fb->modifier[0]) {
2864 case DRM_FORMAT_MOD_NONE:
2866 case I915_FORMAT_MOD_X_TILED:
2867 plane_ctl |= PLANE_CTL_TILED_X;
2869 case I915_FORMAT_MOD_Y_TILED:
2870 plane_ctl |= PLANE_CTL_TILED_Y;
2872 case I915_FORMAT_MOD_Yf_TILED:
2873 plane_ctl |= PLANE_CTL_TILED_YF;
2876 MISSING_CASE(fb->modifier[0]);
2879 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2880 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2881 plane_ctl |= PLANE_CTL_ROTATE_180;
2883 obj = intel_fb_obj(fb);
2884 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2887 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2889 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2890 i915_gem_obj_ggtt_offset(obj),
2891 x, y, fb->width, fb->height,
2894 I915_WRITE(PLANE_POS(pipe, 0), 0);
2895 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2896 I915_WRITE(PLANE_SIZE(pipe, 0),
2897 (intel_crtc->config->pipe_src_h - 1) << 16 |
2898 (intel_crtc->config->pipe_src_w - 1));
2899 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2900 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2902 POSTING_READ(PLANE_SURF(pipe, 0));
2905 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2907 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2908 int x, int y, enum mode_set_atomic state)
2910 struct drm_device *dev = crtc->dev;
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2913 if (dev_priv->display.disable_fbc)
2914 dev_priv->display.disable_fbc(dev);
2916 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2921 static void intel_complete_page_flips(struct drm_device *dev)
2923 struct drm_crtc *crtc;
2925 for_each_crtc(dev, crtc) {
2926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2927 enum plane plane = intel_crtc->plane;
2929 intel_prepare_page_flip(dev, plane);
2930 intel_finish_page_flip_plane(dev, plane);
2934 static void intel_update_primary_planes(struct drm_device *dev)
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 struct drm_crtc *crtc;
2939 for_each_crtc(dev, crtc) {
2940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2942 drm_modeset_lock(&crtc->mutex, NULL);
2944 * FIXME: Once we have proper support for primary planes (and
2945 * disabling them without disabling the entire crtc) allow again
2946 * a NULL crtc->primary->fb.
2948 if (intel_crtc->active && crtc->primary->fb)
2949 dev_priv->display.update_primary_plane(crtc,
2953 drm_modeset_unlock(&crtc->mutex);
2957 void intel_prepare_reset(struct drm_device *dev)
2959 struct drm_i915_private *dev_priv = to_i915(dev);
2960 struct intel_crtc *crtc;
2962 /* no reset support for gen2 */
2966 /* reset doesn't touch the display */
2967 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2970 drm_modeset_lock_all(dev);
2973 * Disabling the crtcs gracefully seems nicer. Also the
2974 * g33 docs say we should at least disable all the planes.
2976 for_each_intel_crtc(dev, crtc) {
2978 dev_priv->display.crtc_disable(&crtc->base);
2982 void intel_finish_reset(struct drm_device *dev)
2984 struct drm_i915_private *dev_priv = to_i915(dev);
2987 * Flips in the rings will be nuked by the reset,
2988 * so complete all pending flips so that user space
2989 * will get its events and not get stuck.
2991 intel_complete_page_flips(dev);
2993 /* no reset support for gen2 */
2997 /* reset doesn't touch the display */
2998 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3000 * Flips in the rings have been nuked by the reset,
3001 * so update the base address of all primary
3002 * planes to the the last fb to make sure we're
3003 * showing the correct fb after a reset.
3005 intel_update_primary_planes(dev);
3010 * The display has been reset as well,
3011 * so need a full re-initialization.
3013 intel_runtime_pm_disable_interrupts(dev_priv);
3014 intel_runtime_pm_enable_interrupts(dev_priv);
3016 intel_modeset_init_hw(dev);
3018 spin_lock_irq(&dev_priv->irq_lock);
3019 if (dev_priv->display.hpd_irq_setup)
3020 dev_priv->display.hpd_irq_setup(dev);
3021 spin_unlock_irq(&dev_priv->irq_lock);
3023 intel_modeset_setup_hw_state(dev, true);
3025 intel_hpd_init(dev_priv);
3027 drm_modeset_unlock_all(dev);
3031 intel_finish_fb(struct drm_framebuffer *old_fb)
3033 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3034 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3035 bool was_interruptible = dev_priv->mm.interruptible;
3038 /* Big Hammer, we also need to ensure that any pending
3039 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3040 * current scanout is retired before unpinning the old
3043 * This should only fail upon a hung GPU, in which case we
3044 * can safely continue.
3046 dev_priv->mm.interruptible = false;
3047 ret = i915_gem_object_finish_gpu(obj);
3048 dev_priv->mm.interruptible = was_interruptible;
3053 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3055 struct drm_device *dev = crtc->dev;
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3060 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3061 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3064 spin_lock_irq(&dev->event_lock);
3065 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3066 spin_unlock_irq(&dev->event_lock);
3071 static void intel_update_pipe_size(struct intel_crtc *crtc)
3073 struct drm_device *dev = crtc->base.dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 const struct drm_display_mode *adjusted_mode;
3081 * Update pipe size and adjust fitter if needed: the reason for this is
3082 * that in compute_mode_changes we check the native mode (not the pfit
3083 * mode) to see if we can flip rather than do a full mode set. In the
3084 * fastboot case, we'll flip, but if we don't update the pipesrc and
3085 * pfit state, we'll end up with a big fb scanned out into the wrong
3088 * To fix this properly, we need to hoist the checks up into
3089 * compute_mode_changes (or above), check the actual pfit state and
3090 * whether the platform allows pfit disable with pipe active, and only
3091 * then update the pipesrc and pfit state, even on the flip path.
3094 adjusted_mode = &crtc->config->base.adjusted_mode;
3096 I915_WRITE(PIPESRC(crtc->pipe),
3097 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3098 (adjusted_mode->crtc_vdisplay - 1));
3099 if (!crtc->config->pch_pfit.enabled &&
3100 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3101 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3102 I915_WRITE(PF_CTL(crtc->pipe), 0);
3103 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3104 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3106 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3107 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3110 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3112 struct drm_device *dev = crtc->dev;
3113 struct drm_i915_private *dev_priv = dev->dev_private;
3114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3115 int pipe = intel_crtc->pipe;
3118 /* enable normal train */
3119 reg = FDI_TX_CTL(pipe);
3120 temp = I915_READ(reg);
3121 if (IS_IVYBRIDGE(dev)) {
3122 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3123 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3125 temp &= ~FDI_LINK_TRAIN_NONE;
3126 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3128 I915_WRITE(reg, temp);
3130 reg = FDI_RX_CTL(pipe);
3131 temp = I915_READ(reg);
3132 if (HAS_PCH_CPT(dev)) {
3133 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3134 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3136 temp &= ~FDI_LINK_TRAIN_NONE;
3137 temp |= FDI_LINK_TRAIN_NONE;
3139 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3141 /* wait one idle pattern time */
3145 /* IVB wants error correction enabled */
3146 if (IS_IVYBRIDGE(dev))
3147 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3148 FDI_FE_ERRC_ENABLE);
3151 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3153 return crtc->base.state->enable && crtc->active &&
3154 crtc->config->has_pch_encoder;
3157 static void ivb_modeset_global_resources(struct drm_device *dev)
3159 struct drm_i915_private *dev_priv = dev->dev_private;
3160 struct intel_crtc *pipe_B_crtc =
3161 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3162 struct intel_crtc *pipe_C_crtc =
3163 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3167 * When everything is off disable fdi C so that we could enable fdi B
3168 * with all lanes. Note that we don't care about enabled pipes without
3169 * an enabled pch encoder.
3171 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3172 !pipe_has_enabled_pch(pipe_C_crtc)) {
3173 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3174 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3176 temp = I915_READ(SOUTH_CHICKEN1);
3177 temp &= ~FDI_BC_BIFURCATION_SELECT;
3178 DRM_DEBUG_KMS("disabling fdi C rx\n");
3179 I915_WRITE(SOUTH_CHICKEN1, temp);
3183 /* The FDI link training functions for ILK/Ibexpeak. */
3184 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189 int pipe = intel_crtc->pipe;
3190 u32 reg, temp, tries;
3192 /* FDI needs bits from pipe first */
3193 assert_pipe_enabled(dev_priv, pipe);
3195 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3197 reg = FDI_RX_IMR(pipe);
3198 temp = I915_READ(reg);
3199 temp &= ~FDI_RX_SYMBOL_LOCK;
3200 temp &= ~FDI_RX_BIT_LOCK;
3201 I915_WRITE(reg, temp);
3205 /* enable CPU FDI TX and PCH FDI RX */
3206 reg = FDI_TX_CTL(pipe);
3207 temp = I915_READ(reg);
3208 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3209 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3210 temp &= ~FDI_LINK_TRAIN_NONE;
3211 temp |= FDI_LINK_TRAIN_PATTERN_1;
3212 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3214 reg = FDI_RX_CTL(pipe);
3215 temp = I915_READ(reg);
3216 temp &= ~FDI_LINK_TRAIN_NONE;
3217 temp |= FDI_LINK_TRAIN_PATTERN_1;
3218 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3223 /* Ironlake workaround, enable clock pointer after FDI enable*/
3224 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3225 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3226 FDI_RX_PHASE_SYNC_POINTER_EN);
3228 reg = FDI_RX_IIR(pipe);
3229 for (tries = 0; tries < 5; tries++) {
3230 temp = I915_READ(reg);
3231 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3233 if ((temp & FDI_RX_BIT_LOCK)) {
3234 DRM_DEBUG_KMS("FDI train 1 done.\n");
3235 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3240 DRM_ERROR("FDI train 1 fail!\n");
3243 reg = FDI_TX_CTL(pipe);
3244 temp = I915_READ(reg);
3245 temp &= ~FDI_LINK_TRAIN_NONE;
3246 temp |= FDI_LINK_TRAIN_PATTERN_2;
3247 I915_WRITE(reg, temp);
3249 reg = FDI_RX_CTL(pipe);
3250 temp = I915_READ(reg);
3251 temp &= ~FDI_LINK_TRAIN_NONE;
3252 temp |= FDI_LINK_TRAIN_PATTERN_2;
3253 I915_WRITE(reg, temp);
3258 reg = FDI_RX_IIR(pipe);
3259 for (tries = 0; tries < 5; tries++) {
3260 temp = I915_READ(reg);
3261 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3263 if (temp & FDI_RX_SYMBOL_LOCK) {
3264 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3265 DRM_DEBUG_KMS("FDI train 2 done.\n");
3270 DRM_ERROR("FDI train 2 fail!\n");
3272 DRM_DEBUG_KMS("FDI train done\n");
3276 static const int snb_b_fdi_train_param[] = {
3277 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3278 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3279 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3280 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3283 /* The FDI link training functions for SNB/Cougarpoint. */
3284 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3286 struct drm_device *dev = crtc->dev;
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3289 int pipe = intel_crtc->pipe;
3290 u32 reg, temp, i, retry;
3292 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3294 reg = FDI_RX_IMR(pipe);
3295 temp = I915_READ(reg);
3296 temp &= ~FDI_RX_SYMBOL_LOCK;
3297 temp &= ~FDI_RX_BIT_LOCK;
3298 I915_WRITE(reg, temp);
3303 /* enable CPU FDI TX and PCH FDI RX */
3304 reg = FDI_TX_CTL(pipe);
3305 temp = I915_READ(reg);
3306 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3307 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3308 temp &= ~FDI_LINK_TRAIN_NONE;
3309 temp |= FDI_LINK_TRAIN_PATTERN_1;
3310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3312 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3313 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3315 I915_WRITE(FDI_RX_MISC(pipe),
3316 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3318 reg = FDI_RX_CTL(pipe);
3319 temp = I915_READ(reg);
3320 if (HAS_PCH_CPT(dev)) {
3321 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3322 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3324 temp &= ~FDI_LINK_TRAIN_NONE;
3325 temp |= FDI_LINK_TRAIN_PATTERN_1;
3327 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3332 for (i = 0; i < 4; i++) {
3333 reg = FDI_TX_CTL(pipe);
3334 temp = I915_READ(reg);
3335 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3336 temp |= snb_b_fdi_train_param[i];
3337 I915_WRITE(reg, temp);
3342 for (retry = 0; retry < 5; retry++) {
3343 reg = FDI_RX_IIR(pipe);
3344 temp = I915_READ(reg);
3345 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3346 if (temp & FDI_RX_BIT_LOCK) {
3347 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3348 DRM_DEBUG_KMS("FDI train 1 done.\n");
3357 DRM_ERROR("FDI train 1 fail!\n");
3360 reg = FDI_TX_CTL(pipe);
3361 temp = I915_READ(reg);
3362 temp &= ~FDI_LINK_TRAIN_NONE;
3363 temp |= FDI_LINK_TRAIN_PATTERN_2;
3365 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3367 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3369 I915_WRITE(reg, temp);
3371 reg = FDI_RX_CTL(pipe);
3372 temp = I915_READ(reg);
3373 if (HAS_PCH_CPT(dev)) {
3374 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3375 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_PATTERN_2;
3380 I915_WRITE(reg, temp);
3385 for (i = 0; i < 4; i++) {
3386 reg = FDI_TX_CTL(pipe);
3387 temp = I915_READ(reg);
3388 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3389 temp |= snb_b_fdi_train_param[i];
3390 I915_WRITE(reg, temp);
3395 for (retry = 0; retry < 5; retry++) {
3396 reg = FDI_RX_IIR(pipe);
3397 temp = I915_READ(reg);
3398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3399 if (temp & FDI_RX_SYMBOL_LOCK) {
3400 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3401 DRM_DEBUG_KMS("FDI train 2 done.\n");
3410 DRM_ERROR("FDI train 2 fail!\n");
3412 DRM_DEBUG_KMS("FDI train done.\n");
3415 /* Manual link training for Ivy Bridge A0 parts */
3416 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 int pipe = intel_crtc->pipe;
3422 u32 reg, temp, i, j;
3424 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3426 reg = FDI_RX_IMR(pipe);
3427 temp = I915_READ(reg);
3428 temp &= ~FDI_RX_SYMBOL_LOCK;
3429 temp &= ~FDI_RX_BIT_LOCK;
3430 I915_WRITE(reg, temp);
3435 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3436 I915_READ(FDI_RX_IIR(pipe)));
3438 /* Try each vswing and preemphasis setting twice before moving on */
3439 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3440 /* disable first in case we need to retry */
3441 reg = FDI_TX_CTL(pipe);
3442 temp = I915_READ(reg);
3443 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3444 temp &= ~FDI_TX_ENABLE;
3445 I915_WRITE(reg, temp);
3447 reg = FDI_RX_CTL(pipe);
3448 temp = I915_READ(reg);
3449 temp &= ~FDI_LINK_TRAIN_AUTO;
3450 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3451 temp &= ~FDI_RX_ENABLE;
3452 I915_WRITE(reg, temp);
3454 /* enable CPU FDI TX and PCH FDI RX */
3455 reg = FDI_TX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3458 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3459 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3460 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3461 temp |= snb_b_fdi_train_param[j/2];
3462 temp |= FDI_COMPOSITE_SYNC;
3463 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3465 I915_WRITE(FDI_RX_MISC(pipe),
3466 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3468 reg = FDI_RX_CTL(pipe);
3469 temp = I915_READ(reg);
3470 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3471 temp |= FDI_COMPOSITE_SYNC;
3472 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3475 udelay(1); /* should be 0.5us */
3477 for (i = 0; i < 4; i++) {
3478 reg = FDI_RX_IIR(pipe);
3479 temp = I915_READ(reg);
3480 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3482 if (temp & FDI_RX_BIT_LOCK ||
3483 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3484 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3485 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3489 udelay(1); /* should be 0.5us */
3492 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3497 reg = FDI_TX_CTL(pipe);
3498 temp = I915_READ(reg);
3499 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3500 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3501 I915_WRITE(reg, temp);
3503 reg = FDI_RX_CTL(pipe);
3504 temp = I915_READ(reg);
3505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3506 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3507 I915_WRITE(reg, temp);
3510 udelay(2); /* should be 1.5us */
3512 for (i = 0; i < 4; i++) {
3513 reg = FDI_RX_IIR(pipe);
3514 temp = I915_READ(reg);
3515 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3517 if (temp & FDI_RX_SYMBOL_LOCK ||
3518 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3519 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3520 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3524 udelay(2); /* should be 1.5us */
3527 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3531 DRM_DEBUG_KMS("FDI train done.\n");
3534 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3536 struct drm_device *dev = intel_crtc->base.dev;
3537 struct drm_i915_private *dev_priv = dev->dev_private;
3538 int pipe = intel_crtc->pipe;
3542 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3543 reg = FDI_RX_CTL(pipe);
3544 temp = I915_READ(reg);
3545 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3547 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3548 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3553 /* Switch from Rawclk to PCDclk */
3554 temp = I915_READ(reg);
3555 I915_WRITE(reg, temp | FDI_PCDCLK);
3560 /* Enable CPU FDI TX PLL, always on for Ironlake */
3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3564 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3571 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3573 struct drm_device *dev = intel_crtc->base.dev;
3574 struct drm_i915_private *dev_priv = dev->dev_private;
3575 int pipe = intel_crtc->pipe;
3578 /* Switch from PCDclk to Rawclk */
3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
3581 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3583 /* Disable CPU FDI TX PLL */
3584 reg = FDI_TX_CTL(pipe);
3585 temp = I915_READ(reg);
3586 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3591 reg = FDI_RX_CTL(pipe);
3592 temp = I915_READ(reg);
3593 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3595 /* Wait for the clocks to turn off. */
3600 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3602 struct drm_device *dev = crtc->dev;
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3605 int pipe = intel_crtc->pipe;
3608 /* disable CPU FDI tx and PCH FDI rx */
3609 reg = FDI_TX_CTL(pipe);
3610 temp = I915_READ(reg);
3611 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3614 reg = FDI_RX_CTL(pipe);
3615 temp = I915_READ(reg);
3616 temp &= ~(0x7 << 16);
3617 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3618 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3623 /* Ironlake workaround, disable clock pointer after downing FDI */
3624 if (HAS_PCH_IBX(dev))
3625 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3627 /* still set train pattern 1 */
3628 reg = FDI_TX_CTL(pipe);
3629 temp = I915_READ(reg);
3630 temp &= ~FDI_LINK_TRAIN_NONE;
3631 temp |= FDI_LINK_TRAIN_PATTERN_1;
3632 I915_WRITE(reg, temp);
3634 reg = FDI_RX_CTL(pipe);
3635 temp = I915_READ(reg);
3636 if (HAS_PCH_CPT(dev)) {
3637 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3638 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3640 temp &= ~FDI_LINK_TRAIN_NONE;
3641 temp |= FDI_LINK_TRAIN_PATTERN_1;
3643 /* BPC in FDI rx is consistent with that in PIPECONF */
3644 temp &= ~(0x07 << 16);
3645 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3646 I915_WRITE(reg, temp);
3652 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3654 struct intel_crtc *crtc;
3656 /* Note that we don't need to be called with mode_config.lock here
3657 * as our list of CRTC objects is static for the lifetime of the
3658 * device and so cannot disappear as we iterate. Similarly, we can
3659 * happily treat the predicates as racy, atomic checks as userspace
3660 * cannot claim and pin a new fb without at least acquring the
3661 * struct_mutex and so serialising with us.
3663 for_each_intel_crtc(dev, crtc) {
3664 if (atomic_read(&crtc->unpin_work_count) == 0)
3667 if (crtc->unpin_work)
3668 intel_wait_for_vblank(dev, crtc->pipe);
3676 static void page_flip_completed(struct intel_crtc *intel_crtc)
3678 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3679 struct intel_unpin_work *work = intel_crtc->unpin_work;
3681 /* ensure that the unpin work is consistent wrt ->pending. */
3683 intel_crtc->unpin_work = NULL;
3686 drm_send_vblank_event(intel_crtc->base.dev,
3690 drm_crtc_vblank_put(&intel_crtc->base);
3692 wake_up_all(&dev_priv->pending_flip_queue);
3693 queue_work(dev_priv->wq, &work->work);
3695 trace_i915_flip_complete(intel_crtc->plane,
3696 work->pending_flip_obj);
3699 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3701 struct drm_device *dev = crtc->dev;
3702 struct drm_i915_private *dev_priv = dev->dev_private;
3704 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3705 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3706 !intel_crtc_has_pending_flip(crtc),
3708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3710 spin_lock_irq(&dev->event_lock);
3711 if (intel_crtc->unpin_work) {
3712 WARN_ONCE(1, "Removing stuck page flip\n");
3713 page_flip_completed(intel_crtc);
3715 spin_unlock_irq(&dev->event_lock);
3718 if (crtc->primary->fb) {
3719 mutex_lock(&dev->struct_mutex);
3720 intel_finish_fb(crtc->primary->fb);
3721 mutex_unlock(&dev->struct_mutex);
3725 /* Program iCLKIP clock to the desired frequency */
3726 static void lpt_program_iclkip(struct drm_crtc *crtc)
3728 struct drm_device *dev = crtc->dev;
3729 struct drm_i915_private *dev_priv = dev->dev_private;
3730 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3731 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3734 mutex_lock(&dev_priv->dpio_lock);
3736 /* It is necessary to ungate the pixclk gate prior to programming
3737 * the divisors, and gate it back when it is done.
3739 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3741 /* Disable SSCCTL */
3742 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3743 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3747 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3748 if (clock == 20000) {
3753 /* The iCLK virtual clock root frequency is in MHz,
3754 * but the adjusted_mode->crtc_clock in in KHz. To get the
3755 * divisors, it is necessary to divide one by another, so we
3756 * convert the virtual clock precision to KHz here for higher
3759 u32 iclk_virtual_root_freq = 172800 * 1000;
3760 u32 iclk_pi_range = 64;
3761 u32 desired_divisor, msb_divisor_value, pi_value;
3763 desired_divisor = (iclk_virtual_root_freq / clock);
3764 msb_divisor_value = desired_divisor / iclk_pi_range;
3765 pi_value = desired_divisor % iclk_pi_range;
3768 divsel = msb_divisor_value - 2;
3769 phaseinc = pi_value;
3772 /* This should not happen with any sane values */
3773 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3774 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3775 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3776 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3778 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3785 /* Program SSCDIVINTPHASE6 */
3786 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3787 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3788 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3789 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3790 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3791 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3792 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3793 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3795 /* Program SSCAUXDIV */
3796 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3797 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3798 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3799 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3801 /* Enable modulator and associated divider */
3802 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3803 temp &= ~SBI_SSCCTL_DISABLE;
3804 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3806 /* Wait for initialization time */
3809 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3811 mutex_unlock(&dev_priv->dpio_lock);
3814 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3815 enum pipe pch_transcoder)
3817 struct drm_device *dev = crtc->base.dev;
3818 struct drm_i915_private *dev_priv = dev->dev_private;
3819 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3821 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3822 I915_READ(HTOTAL(cpu_transcoder)));
3823 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3824 I915_READ(HBLANK(cpu_transcoder)));
3825 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3826 I915_READ(HSYNC(cpu_transcoder)));
3828 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3829 I915_READ(VTOTAL(cpu_transcoder)));
3830 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3831 I915_READ(VBLANK(cpu_transcoder)));
3832 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3833 I915_READ(VSYNC(cpu_transcoder)));
3834 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3835 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3838 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3843 temp = I915_READ(SOUTH_CHICKEN1);
3844 if (temp & FDI_BC_BIFURCATION_SELECT)
3847 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3848 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3850 temp |= FDI_BC_BIFURCATION_SELECT;
3851 DRM_DEBUG_KMS("enabling fdi C rx\n");
3852 I915_WRITE(SOUTH_CHICKEN1, temp);
3853 POSTING_READ(SOUTH_CHICKEN1);
3856 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3858 struct drm_device *dev = intel_crtc->base.dev;
3859 struct drm_i915_private *dev_priv = dev->dev_private;
3861 switch (intel_crtc->pipe) {
3865 if (intel_crtc->config->fdi_lanes > 2)
3866 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3868 cpt_enable_fdi_bc_bifurcation(dev);
3872 cpt_enable_fdi_bc_bifurcation(dev);
3881 * Enable PCH resources required for PCH ports:
3883 * - FDI training & RX/TX
3884 * - update transcoder timings
3885 * - DP transcoding bits
3888 static void ironlake_pch_enable(struct drm_crtc *crtc)
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893 int pipe = intel_crtc->pipe;
3896 assert_pch_transcoder_disabled(dev_priv, pipe);
3898 if (IS_IVYBRIDGE(dev))
3899 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3901 /* Write the TU size bits before fdi link training, so that error
3902 * detection works. */
3903 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3904 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3906 /* For PCH output, training FDI link */
3907 dev_priv->display.fdi_link_train(crtc);
3909 /* We need to program the right clock selection before writing the pixel
3910 * mutliplier into the DPLL. */
3911 if (HAS_PCH_CPT(dev)) {
3914 temp = I915_READ(PCH_DPLL_SEL);
3915 temp |= TRANS_DPLL_ENABLE(pipe);
3916 sel = TRANS_DPLLB_SEL(pipe);
3917 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3921 I915_WRITE(PCH_DPLL_SEL, temp);
3924 /* XXX: pch pll's can be enabled any time before we enable the PCH
3925 * transcoder, and we actually should do this to not upset any PCH
3926 * transcoder that already use the clock when we share it.
3928 * Note that enable_shared_dpll tries to do the right thing, but
3929 * get_shared_dpll unconditionally resets the pll - we need that to have
3930 * the right LVDS enable sequence. */
3931 intel_enable_shared_dpll(intel_crtc);
3933 /* set transcoder timing, panel must allow it */
3934 assert_panel_unlocked(dev_priv, pipe);
3935 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3937 intel_fdi_normal_train(crtc);
3939 /* For PCH DP, enable TRANS_DP_CTL */
3940 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3941 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3942 reg = TRANS_DP_CTL(pipe);
3943 temp = I915_READ(reg);
3944 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3945 TRANS_DP_SYNC_MASK |
3947 temp |= (TRANS_DP_OUTPUT_ENABLE |
3948 TRANS_DP_ENH_FRAMING);
3949 temp |= bpc << 9; /* same format but at 11:9 */
3951 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3952 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3953 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3954 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3956 switch (intel_trans_dp_port_sel(crtc)) {
3958 temp |= TRANS_DP_PORT_SEL_B;
3961 temp |= TRANS_DP_PORT_SEL_C;
3964 temp |= TRANS_DP_PORT_SEL_D;
3970 I915_WRITE(reg, temp);
3973 ironlake_enable_pch_transcoder(dev_priv, pipe);
3976 static void lpt_pch_enable(struct drm_crtc *crtc)
3978 struct drm_device *dev = crtc->dev;
3979 struct drm_i915_private *dev_priv = dev->dev_private;
3980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3981 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3983 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3985 lpt_program_iclkip(crtc);
3987 /* Set transcoder timing. */
3988 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3990 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3993 void intel_put_shared_dpll(struct intel_crtc *crtc)
3995 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4000 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4001 WARN(1, "bad %s crtc mask\n", pll->name);
4005 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4006 if (pll->config.crtc_mask == 0) {
4008 WARN_ON(pll->active);
4011 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4014 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4015 struct intel_crtc_state *crtc_state)
4017 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4018 struct intel_shared_dpll *pll;
4019 enum intel_dpll_id i;
4021 if (HAS_PCH_IBX(dev_priv->dev)) {
4022 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4023 i = (enum intel_dpll_id) crtc->pipe;
4024 pll = &dev_priv->shared_dplls[i];
4026 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4027 crtc->base.base.id, pll->name);
4029 WARN_ON(pll->new_config->crtc_mask);
4034 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4035 pll = &dev_priv->shared_dplls[i];
4037 /* Only want to check enabled timings first */
4038 if (pll->new_config->crtc_mask == 0)
4041 if (memcmp(&crtc_state->dpll_hw_state,
4042 &pll->new_config->hw_state,
4043 sizeof(pll->new_config->hw_state)) == 0) {
4044 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4045 crtc->base.base.id, pll->name,
4046 pll->new_config->crtc_mask,
4052 /* Ok no matching timings, maybe there's a free one? */
4053 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4054 pll = &dev_priv->shared_dplls[i];
4055 if (pll->new_config->crtc_mask == 0) {
4056 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4057 crtc->base.base.id, pll->name);
4065 if (pll->new_config->crtc_mask == 0)
4066 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4068 crtc_state->shared_dpll = i;
4069 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4070 pipe_name(crtc->pipe));
4072 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4078 * intel_shared_dpll_start_config - start a new PLL staged config
4079 * @dev_priv: DRM device
4080 * @clear_pipes: mask of pipes that will have their PLLs freed
4082 * Starts a new PLL staged config, copying the current config but
4083 * releasing the references of pipes specified in clear_pipes.
4085 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4086 unsigned clear_pipes)
4088 struct intel_shared_dpll *pll;
4089 enum intel_dpll_id i;
4091 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4092 pll = &dev_priv->shared_dplls[i];
4094 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4096 if (!pll->new_config)
4099 pll->new_config->crtc_mask &= ~clear_pipes;
4106 pll = &dev_priv->shared_dplls[i];
4107 kfree(pll->new_config);
4108 pll->new_config = NULL;
4114 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4116 struct intel_shared_dpll *pll;
4117 enum intel_dpll_id i;
4119 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4120 pll = &dev_priv->shared_dplls[i];
4122 WARN_ON(pll->new_config == &pll->config);
4124 pll->config = *pll->new_config;
4125 kfree(pll->new_config);
4126 pll->new_config = NULL;
4130 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4132 struct intel_shared_dpll *pll;
4133 enum intel_dpll_id i;
4135 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4136 pll = &dev_priv->shared_dplls[i];
4138 WARN_ON(pll->new_config == &pll->config);
4140 kfree(pll->new_config);
4141 pll->new_config = NULL;
4145 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 int dslreg = PIPEDSL(pipe);
4151 temp = I915_READ(dslreg);
4153 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4154 if (wait_for(I915_READ(dslreg) != temp, 5))
4155 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4159 static void skylake_pfit_enable(struct intel_crtc *crtc)
4161 struct drm_device *dev = crtc->base.dev;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 int pipe = crtc->pipe;
4165 if (crtc->config->pch_pfit.enabled) {
4166 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4167 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4168 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4172 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4174 struct drm_device *dev = crtc->base.dev;
4175 struct drm_i915_private *dev_priv = dev->dev_private;
4176 int pipe = crtc->pipe;
4178 if (crtc->config->pch_pfit.enabled) {
4179 /* Force use of hard-coded filter coefficients
4180 * as some pre-programmed values are broken,
4183 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4184 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4185 PF_PIPE_SEL_IVB(pipe));
4187 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4188 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4189 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4193 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4195 struct drm_device *dev = crtc->dev;
4196 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4197 struct drm_plane *plane;
4198 struct intel_plane *intel_plane;
4200 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4201 intel_plane = to_intel_plane(plane);
4202 if (intel_plane->pipe == pipe)
4203 intel_plane_restore(&intel_plane->base);
4208 * Disable a plane internally without actually modifying the plane's state.
4209 * This will allow us to easily restore the plane later by just reprogramming
4212 static void disable_plane_internal(struct drm_plane *plane)
4214 struct intel_plane *intel_plane = to_intel_plane(plane);
4215 struct drm_plane_state *state =
4216 plane->funcs->atomic_duplicate_state(plane);
4217 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4219 intel_state->visible = false;
4220 intel_plane->commit_plane(plane, intel_state);
4222 intel_plane_destroy_state(plane, state);
4225 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4227 struct drm_device *dev = crtc->dev;
4228 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4229 struct drm_plane *plane;
4230 struct intel_plane *intel_plane;
4232 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4233 intel_plane = to_intel_plane(plane);
4234 if (plane->fb && intel_plane->pipe == pipe)
4235 disable_plane_internal(plane);
4239 void hsw_enable_ips(struct intel_crtc *crtc)
4241 struct drm_device *dev = crtc->base.dev;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4244 if (!crtc->config->ips_enabled)
4247 /* We can only enable IPS after we enable a plane and wait for a vblank */
4248 intel_wait_for_vblank(dev, crtc->pipe);
4250 assert_plane_enabled(dev_priv, crtc->plane);
4251 if (IS_BROADWELL(dev)) {
4252 mutex_lock(&dev_priv->rps.hw_lock);
4253 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4254 mutex_unlock(&dev_priv->rps.hw_lock);
4255 /* Quoting Art Runyan: "its not safe to expect any particular
4256 * value in IPS_CTL bit 31 after enabling IPS through the
4257 * mailbox." Moreover, the mailbox may return a bogus state,
4258 * so we need to just enable it and continue on.
4261 I915_WRITE(IPS_CTL, IPS_ENABLE);
4262 /* The bit only becomes 1 in the next vblank, so this wait here
4263 * is essentially intel_wait_for_vblank. If we don't have this
4264 * and don't wait for vblanks until the end of crtc_enable, then
4265 * the HW state readout code will complain that the expected
4266 * IPS_CTL value is not the one we read. */
4267 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4268 DRM_ERROR("Timed out waiting for IPS enable\n");
4272 void hsw_disable_ips(struct intel_crtc *crtc)
4274 struct drm_device *dev = crtc->base.dev;
4275 struct drm_i915_private *dev_priv = dev->dev_private;
4277 if (!crtc->config->ips_enabled)
4280 assert_plane_enabled(dev_priv, crtc->plane);
4281 if (IS_BROADWELL(dev)) {
4282 mutex_lock(&dev_priv->rps.hw_lock);
4283 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4284 mutex_unlock(&dev_priv->rps.hw_lock);
4285 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4286 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4287 DRM_ERROR("Timed out waiting for IPS disable\n");
4289 I915_WRITE(IPS_CTL, 0);
4290 POSTING_READ(IPS_CTL);
4293 /* We need to wait for a vblank before we can disable the plane. */
4294 intel_wait_for_vblank(dev, crtc->pipe);
4297 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4298 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4300 struct drm_device *dev = crtc->dev;
4301 struct drm_i915_private *dev_priv = dev->dev_private;
4302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4303 enum pipe pipe = intel_crtc->pipe;
4304 int palreg = PALETTE(pipe);
4306 bool reenable_ips = false;
4308 /* The clocks have to be on to load the palette. */
4309 if (!crtc->state->enable || !intel_crtc->active)
4312 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4313 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4314 assert_dsi_pll_enabled(dev_priv);
4316 assert_pll_enabled(dev_priv, pipe);
4319 /* use legacy palette for Ironlake */
4320 if (!HAS_GMCH_DISPLAY(dev))
4321 palreg = LGC_PALETTE(pipe);
4323 /* Workaround : Do not read or write the pipe palette/gamma data while
4324 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4326 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4327 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4328 GAMMA_MODE_MODE_SPLIT)) {
4329 hsw_disable_ips(intel_crtc);
4330 reenable_ips = true;
4333 for (i = 0; i < 256; i++) {
4334 I915_WRITE(palreg + 4 * i,
4335 (intel_crtc->lut_r[i] << 16) |
4336 (intel_crtc->lut_g[i] << 8) |
4337 intel_crtc->lut_b[i]);
4341 hsw_enable_ips(intel_crtc);
4344 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4346 if (!enable && intel_crtc->overlay) {
4347 struct drm_device *dev = intel_crtc->base.dev;
4348 struct drm_i915_private *dev_priv = dev->dev_private;
4350 mutex_lock(&dev->struct_mutex);
4351 dev_priv->mm.interruptible = false;
4352 (void) intel_overlay_switch_off(intel_crtc->overlay);
4353 dev_priv->mm.interruptible = true;
4354 mutex_unlock(&dev->struct_mutex);
4357 /* Let userspace switch the overlay on again. In most cases userspace
4358 * has to recompute where to put it anyway.
4362 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4364 struct drm_device *dev = crtc->dev;
4365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4366 int pipe = intel_crtc->pipe;
4368 intel_enable_primary_hw_plane(crtc->primary, crtc);
4369 intel_enable_sprite_planes(crtc);
4370 intel_crtc_update_cursor(crtc, true);
4371 intel_crtc_dpms_overlay(intel_crtc, true);
4373 hsw_enable_ips(intel_crtc);
4375 mutex_lock(&dev->struct_mutex);
4376 intel_fbc_update(dev);
4377 mutex_unlock(&dev->struct_mutex);
4380 * FIXME: Once we grow proper nuclear flip support out of this we need
4381 * to compute the mask of flip planes precisely. For the time being
4382 * consider this a flip from a NULL plane.
4384 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4387 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4389 struct drm_device *dev = crtc->dev;
4390 struct drm_i915_private *dev_priv = dev->dev_private;
4391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4392 int pipe = intel_crtc->pipe;
4394 intel_crtc_wait_for_pending_flips(crtc);
4396 if (dev_priv->fbc.crtc == intel_crtc)
4397 intel_fbc_disable(dev);
4399 hsw_disable_ips(intel_crtc);
4401 intel_crtc_dpms_overlay(intel_crtc, false);
4402 intel_crtc_update_cursor(crtc, false);
4403 intel_disable_sprite_planes(crtc);
4404 intel_disable_primary_hw_plane(crtc->primary, crtc);
4407 * FIXME: Once we grow proper nuclear flip support out of this we need
4408 * to compute the mask of flip planes precisely. For the time being
4409 * consider this a flip to a NULL plane.
4411 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4414 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4416 struct drm_device *dev = crtc->dev;
4417 struct drm_i915_private *dev_priv = dev->dev_private;
4418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4419 struct intel_encoder *encoder;
4420 int pipe = intel_crtc->pipe;
4422 WARN_ON(!crtc->state->enable);
4424 if (intel_crtc->active)
4427 if (intel_crtc->config->has_pch_encoder)
4428 intel_prepare_shared_dpll(intel_crtc);
4430 if (intel_crtc->config->has_dp_encoder)
4431 intel_dp_set_m_n(intel_crtc, M1_N1);
4433 intel_set_pipe_timings(intel_crtc);
4435 if (intel_crtc->config->has_pch_encoder) {
4436 intel_cpu_transcoder_set_m_n(intel_crtc,
4437 &intel_crtc->config->fdi_m_n, NULL);
4440 ironlake_set_pipeconf(crtc);
4442 intel_crtc->active = true;
4444 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4445 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4447 for_each_encoder_on_crtc(dev, crtc, encoder)
4448 if (encoder->pre_enable)
4449 encoder->pre_enable(encoder);
4451 if (intel_crtc->config->has_pch_encoder) {
4452 /* Note: FDI PLL enabling _must_ be done before we enable the
4453 * cpu pipes, hence this is separate from all the other fdi/pch
4455 ironlake_fdi_pll_enable(intel_crtc);
4457 assert_fdi_tx_disabled(dev_priv, pipe);
4458 assert_fdi_rx_disabled(dev_priv, pipe);
4461 ironlake_pfit_enable(intel_crtc);
4464 * On ILK+ LUT must be loaded before the pipe is running but with
4467 intel_crtc_load_lut(crtc);
4469 intel_update_watermarks(crtc);
4470 intel_enable_pipe(intel_crtc);
4472 if (intel_crtc->config->has_pch_encoder)
4473 ironlake_pch_enable(crtc);
4475 assert_vblank_disabled(crtc);
4476 drm_crtc_vblank_on(crtc);
4478 for_each_encoder_on_crtc(dev, crtc, encoder)
4479 encoder->enable(encoder);
4481 if (HAS_PCH_CPT(dev))
4482 cpt_verify_modeset(dev, intel_crtc->pipe);
4484 intel_crtc_enable_planes(crtc);
4487 /* IPS only exists on ULT machines and is tied to pipe A. */
4488 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4490 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4494 * This implements the workaround described in the "notes" section of the mode
4495 * set sequence documentation. When going from no pipes or single pipe to
4496 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4497 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4499 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4501 struct drm_device *dev = crtc->base.dev;
4502 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4504 /* We want to get the other_active_crtc only if there's only 1 other
4506 for_each_intel_crtc(dev, crtc_it) {
4507 if (!crtc_it->active || crtc_it == crtc)
4510 if (other_active_crtc)
4513 other_active_crtc = crtc_it;
4515 if (!other_active_crtc)
4518 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4519 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4522 static void haswell_crtc_enable(struct drm_crtc *crtc)
4524 struct drm_device *dev = crtc->dev;
4525 struct drm_i915_private *dev_priv = dev->dev_private;
4526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4527 struct intel_encoder *encoder;
4528 int pipe = intel_crtc->pipe;
4530 WARN_ON(!crtc->state->enable);
4532 if (intel_crtc->active)
4535 if (intel_crtc_to_shared_dpll(intel_crtc))
4536 intel_enable_shared_dpll(intel_crtc);
4538 if (intel_crtc->config->has_dp_encoder)
4539 intel_dp_set_m_n(intel_crtc, M1_N1);
4541 intel_set_pipe_timings(intel_crtc);
4543 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4544 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4545 intel_crtc->config->pixel_multiplier - 1);
4548 if (intel_crtc->config->has_pch_encoder) {
4549 intel_cpu_transcoder_set_m_n(intel_crtc,
4550 &intel_crtc->config->fdi_m_n, NULL);
4553 haswell_set_pipeconf(crtc);
4555 intel_set_pipe_csc(crtc);
4557 intel_crtc->active = true;
4559 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4560 for_each_encoder_on_crtc(dev, crtc, encoder)
4561 if (encoder->pre_enable)
4562 encoder->pre_enable(encoder);
4564 if (intel_crtc->config->has_pch_encoder) {
4565 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4567 dev_priv->display.fdi_link_train(crtc);
4570 intel_ddi_enable_pipe_clock(intel_crtc);
4572 if (IS_SKYLAKE(dev))
4573 skylake_pfit_enable(intel_crtc);
4575 ironlake_pfit_enable(intel_crtc);
4578 * On ILK+ LUT must be loaded before the pipe is running but with
4581 intel_crtc_load_lut(crtc);
4583 intel_ddi_set_pipe_settings(crtc);
4584 intel_ddi_enable_transcoder_func(crtc);
4586 intel_update_watermarks(crtc);
4587 intel_enable_pipe(intel_crtc);
4589 if (intel_crtc->config->has_pch_encoder)
4590 lpt_pch_enable(crtc);
4592 if (intel_crtc->config->dp_encoder_is_mst)
4593 intel_ddi_set_vc_payload_alloc(crtc, true);
4595 assert_vblank_disabled(crtc);
4596 drm_crtc_vblank_on(crtc);
4598 for_each_encoder_on_crtc(dev, crtc, encoder) {
4599 encoder->enable(encoder);
4600 intel_opregion_notify_encoder(encoder, true);
4603 /* If we change the relative order between pipe/planes enabling, we need
4604 * to change the workaround. */
4605 haswell_mode_set_planes_workaround(intel_crtc);
4606 intel_crtc_enable_planes(crtc);
4609 static void skylake_pfit_disable(struct intel_crtc *crtc)
4611 struct drm_device *dev = crtc->base.dev;
4612 struct drm_i915_private *dev_priv = dev->dev_private;
4613 int pipe = crtc->pipe;
4615 /* To avoid upsetting the power well on haswell only disable the pfit if
4616 * it's in use. The hw state code will make sure we get this right. */
4617 if (crtc->config->pch_pfit.enabled) {
4618 I915_WRITE(PS_CTL(pipe), 0);
4619 I915_WRITE(PS_WIN_POS(pipe), 0);
4620 I915_WRITE(PS_WIN_SZ(pipe), 0);
4624 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4626 struct drm_device *dev = crtc->base.dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 int pipe = crtc->pipe;
4630 /* To avoid upsetting the power well on haswell only disable the pfit if
4631 * it's in use. The hw state code will make sure we get this right. */
4632 if (crtc->config->pch_pfit.enabled) {
4633 I915_WRITE(PF_CTL(pipe), 0);
4634 I915_WRITE(PF_WIN_POS(pipe), 0);
4635 I915_WRITE(PF_WIN_SZ(pipe), 0);
4639 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4641 struct drm_device *dev = crtc->dev;
4642 struct drm_i915_private *dev_priv = dev->dev_private;
4643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4644 struct intel_encoder *encoder;
4645 int pipe = intel_crtc->pipe;
4648 if (!intel_crtc->active)
4651 intel_crtc_disable_planes(crtc);
4653 for_each_encoder_on_crtc(dev, crtc, encoder)
4654 encoder->disable(encoder);
4656 drm_crtc_vblank_off(crtc);
4657 assert_vblank_disabled(crtc);
4659 if (intel_crtc->config->has_pch_encoder)
4660 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4662 intel_disable_pipe(intel_crtc);
4664 ironlake_pfit_disable(intel_crtc);
4666 for_each_encoder_on_crtc(dev, crtc, encoder)
4667 if (encoder->post_disable)
4668 encoder->post_disable(encoder);
4670 if (intel_crtc->config->has_pch_encoder) {
4671 ironlake_fdi_disable(crtc);
4673 ironlake_disable_pch_transcoder(dev_priv, pipe);
4675 if (HAS_PCH_CPT(dev)) {
4676 /* disable TRANS_DP_CTL */
4677 reg = TRANS_DP_CTL(pipe);
4678 temp = I915_READ(reg);
4679 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4680 TRANS_DP_PORT_SEL_MASK);
4681 temp |= TRANS_DP_PORT_SEL_NONE;
4682 I915_WRITE(reg, temp);
4684 /* disable DPLL_SEL */
4685 temp = I915_READ(PCH_DPLL_SEL);
4686 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4687 I915_WRITE(PCH_DPLL_SEL, temp);
4690 /* disable PCH DPLL */
4691 intel_disable_shared_dpll(intel_crtc);
4693 ironlake_fdi_pll_disable(intel_crtc);
4696 intel_crtc->active = false;
4697 intel_update_watermarks(crtc);
4699 mutex_lock(&dev->struct_mutex);
4700 intel_fbc_update(dev);
4701 mutex_unlock(&dev->struct_mutex);
4704 static void haswell_crtc_disable(struct drm_crtc *crtc)
4706 struct drm_device *dev = crtc->dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709 struct intel_encoder *encoder;
4710 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4712 if (!intel_crtc->active)
4715 intel_crtc_disable_planes(crtc);
4717 for_each_encoder_on_crtc(dev, crtc, encoder) {
4718 intel_opregion_notify_encoder(encoder, false);
4719 encoder->disable(encoder);
4722 drm_crtc_vblank_off(crtc);
4723 assert_vblank_disabled(crtc);
4725 if (intel_crtc->config->has_pch_encoder)
4726 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4728 intel_disable_pipe(intel_crtc);
4730 if (intel_crtc->config->dp_encoder_is_mst)
4731 intel_ddi_set_vc_payload_alloc(crtc, false);
4733 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4735 if (IS_SKYLAKE(dev))
4736 skylake_pfit_disable(intel_crtc);
4738 ironlake_pfit_disable(intel_crtc);
4740 intel_ddi_disable_pipe_clock(intel_crtc);
4742 if (intel_crtc->config->has_pch_encoder) {
4743 lpt_disable_pch_transcoder(dev_priv);
4744 intel_ddi_fdi_disable(crtc);
4747 for_each_encoder_on_crtc(dev, crtc, encoder)
4748 if (encoder->post_disable)
4749 encoder->post_disable(encoder);
4751 intel_crtc->active = false;
4752 intel_update_watermarks(crtc);
4754 mutex_lock(&dev->struct_mutex);
4755 intel_fbc_update(dev);
4756 mutex_unlock(&dev->struct_mutex);
4758 if (intel_crtc_to_shared_dpll(intel_crtc))
4759 intel_disable_shared_dpll(intel_crtc);
4762 static void ironlake_crtc_off(struct drm_crtc *crtc)
4764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4765 intel_put_shared_dpll(intel_crtc);
4769 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4771 struct drm_device *dev = crtc->base.dev;
4772 struct drm_i915_private *dev_priv = dev->dev_private;
4773 struct intel_crtc_state *pipe_config = crtc->config;
4775 if (!pipe_config->gmch_pfit.control)
4779 * The panel fitter should only be adjusted whilst the pipe is disabled,
4780 * according to register description and PRM.
4782 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4783 assert_pipe_disabled(dev_priv, crtc->pipe);
4785 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4786 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4788 /* Border color in case we don't scale up to the full screen. Black by
4789 * default, change to something else for debugging. */
4790 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4793 static enum intel_display_power_domain port_to_power_domain(enum port port)
4797 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4799 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4801 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4803 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4806 return POWER_DOMAIN_PORT_OTHER;
4810 #define for_each_power_domain(domain, mask) \
4811 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4812 if ((1 << (domain)) & (mask))
4814 enum intel_display_power_domain
4815 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4817 struct drm_device *dev = intel_encoder->base.dev;
4818 struct intel_digital_port *intel_dig_port;
4820 switch (intel_encoder->type) {
4821 case INTEL_OUTPUT_UNKNOWN:
4822 /* Only DDI platforms should ever use this output type */
4823 WARN_ON_ONCE(!HAS_DDI(dev));
4824 case INTEL_OUTPUT_DISPLAYPORT:
4825 case INTEL_OUTPUT_HDMI:
4826 case INTEL_OUTPUT_EDP:
4827 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4828 return port_to_power_domain(intel_dig_port->port);
4829 case INTEL_OUTPUT_DP_MST:
4830 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4831 return port_to_power_domain(intel_dig_port->port);
4832 case INTEL_OUTPUT_ANALOG:
4833 return POWER_DOMAIN_PORT_CRT;
4834 case INTEL_OUTPUT_DSI:
4835 return POWER_DOMAIN_PORT_DSI;
4837 return POWER_DOMAIN_PORT_OTHER;
4841 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4843 struct drm_device *dev = crtc->dev;
4844 struct intel_encoder *intel_encoder;
4845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4846 enum pipe pipe = intel_crtc->pipe;
4848 enum transcoder transcoder;
4850 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4852 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4853 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4854 if (intel_crtc->config->pch_pfit.enabled ||
4855 intel_crtc->config->pch_pfit.force_thru)
4856 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4858 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4859 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4864 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4866 struct drm_i915_private *dev_priv = dev->dev_private;
4867 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4868 struct intel_crtc *crtc;
4871 * First get all needed power domains, then put all unneeded, to avoid
4872 * any unnecessary toggling of the power wells.
4874 for_each_intel_crtc(dev, crtc) {
4875 enum intel_display_power_domain domain;
4877 if (!crtc->base.state->enable)
4880 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4882 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4883 intel_display_power_get(dev_priv, domain);
4886 if (dev_priv->display.modeset_global_resources)
4887 dev_priv->display.modeset_global_resources(dev);
4889 for_each_intel_crtc(dev, crtc) {
4890 enum intel_display_power_domain domain;
4892 for_each_power_domain(domain, crtc->enabled_power_domains)
4893 intel_display_power_put(dev_priv, domain);
4895 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4898 intel_display_set_init_power(dev_priv, false);
4901 /* returns HPLL frequency in kHz */
4902 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4904 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4906 /* Obtain SKU information */
4907 mutex_lock(&dev_priv->dpio_lock);
4908 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4909 CCK_FUSE_HPLL_FREQ_MASK;
4910 mutex_unlock(&dev_priv->dpio_lock);
4912 return vco_freq[hpll_freq] * 1000;
4915 static void vlv_update_cdclk(struct drm_device *dev)
4917 struct drm_i915_private *dev_priv = dev->dev_private;
4919 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4920 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4921 dev_priv->vlv_cdclk_freq);
4924 * Program the gmbus_freq based on the cdclk frequency.
4925 * BSpec erroneously claims we should aim for 4MHz, but
4926 * in fact 1MHz is the correct frequency.
4928 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4931 /* Adjust CDclk dividers to allow high res or save power if possible */
4932 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4934 struct drm_i915_private *dev_priv = dev->dev_private;
4937 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4939 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4941 else if (cdclk == 266667)
4946 mutex_lock(&dev_priv->rps.hw_lock);
4947 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4948 val &= ~DSPFREQGUAR_MASK;
4949 val |= (cmd << DSPFREQGUAR_SHIFT);
4950 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4951 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4952 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4954 DRM_ERROR("timed out waiting for CDclk change\n");
4956 mutex_unlock(&dev_priv->rps.hw_lock);
4958 if (cdclk == 400000) {
4961 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4963 mutex_lock(&dev_priv->dpio_lock);
4964 /* adjust cdclk divider */
4965 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4966 val &= ~DISPLAY_FREQUENCY_VALUES;
4968 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4970 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4971 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4973 DRM_ERROR("timed out waiting for CDclk change\n");
4974 mutex_unlock(&dev_priv->dpio_lock);
4977 mutex_lock(&dev_priv->dpio_lock);
4978 /* adjust self-refresh exit latency value */
4979 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4983 * For high bandwidth configs, we set a higher latency in the bunit
4984 * so that the core display fetch happens in time to avoid underruns.
4986 if (cdclk == 400000)
4987 val |= 4500 / 250; /* 4.5 usec */
4989 val |= 3000 / 250; /* 3.0 usec */
4990 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4991 mutex_unlock(&dev_priv->dpio_lock);
4993 vlv_update_cdclk(dev);
4996 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4998 struct drm_i915_private *dev_priv = dev->dev_private;
5001 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5018 MISSING_CASE(cdclk);
5022 mutex_lock(&dev_priv->rps.hw_lock);
5023 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5024 val &= ~DSPFREQGUAR_MASK_CHV;
5025 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5026 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5027 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5028 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5030 DRM_ERROR("timed out waiting for CDclk change\n");
5032 mutex_unlock(&dev_priv->rps.hw_lock);
5034 vlv_update_cdclk(dev);
5037 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5040 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5042 /* FIXME: Punit isn't quite ready yet */
5043 if (IS_CHERRYVIEW(dev_priv->dev))
5047 * Really only a few cases to deal with, as only 4 CDclks are supported:
5050 * 320/333MHz (depends on HPLL freq)
5052 * So we check to see whether we're above 90% of the lower bin and
5055 * We seem to get an unstable or solid color picture at 200MHz.
5056 * Not sure what's wrong. For now use 200MHz only when all pipes
5059 if (max_pixclk > freq_320*9/10)
5061 else if (max_pixclk > 266667*9/10)
5063 else if (max_pixclk > 0)
5069 /* compute the max pixel clock for new configuration */
5070 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5072 struct drm_device *dev = dev_priv->dev;
5073 struct intel_crtc *intel_crtc;
5076 for_each_intel_crtc(dev, intel_crtc) {
5077 if (intel_crtc->new_enabled)
5078 max_pixclk = max(max_pixclk,
5079 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5085 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5086 unsigned *prepare_pipes)
5088 struct drm_i915_private *dev_priv = dev->dev_private;
5089 struct intel_crtc *intel_crtc;
5090 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5092 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5093 dev_priv->vlv_cdclk_freq)
5096 /* disable/enable all currently active pipes while we change cdclk */
5097 for_each_intel_crtc(dev, intel_crtc)
5098 if (intel_crtc->base.state->enable)
5099 *prepare_pipes |= (1 << intel_crtc->pipe);
5102 static void valleyview_modeset_global_resources(struct drm_device *dev)
5104 struct drm_i915_private *dev_priv = dev->dev_private;
5105 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5106 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5108 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5110 * FIXME: We can end up here with all power domains off, yet
5111 * with a CDCLK frequency other than the minimum. To account
5112 * for this take the PIPE-A power domain, which covers the HW
5113 * blocks needed for the following programming. This can be
5114 * removed once it's guaranteed that we get here either with
5115 * the minimum CDCLK set, or the required power domains
5118 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5120 if (IS_CHERRYVIEW(dev))
5121 cherryview_set_cdclk(dev, req_cdclk);
5123 valleyview_set_cdclk(dev, req_cdclk);
5125 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5129 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5131 struct drm_device *dev = crtc->dev;
5132 struct drm_i915_private *dev_priv = to_i915(dev);
5133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5134 struct intel_encoder *encoder;
5135 int pipe = intel_crtc->pipe;
5138 WARN_ON(!crtc->state->enable);
5140 if (intel_crtc->active)
5143 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5146 if (IS_CHERRYVIEW(dev))
5147 chv_prepare_pll(intel_crtc, intel_crtc->config);
5149 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5152 if (intel_crtc->config->has_dp_encoder)
5153 intel_dp_set_m_n(intel_crtc, M1_N1);
5155 intel_set_pipe_timings(intel_crtc);
5157 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5158 struct drm_i915_private *dev_priv = dev->dev_private;
5160 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5161 I915_WRITE(CHV_CANVAS(pipe), 0);
5164 i9xx_set_pipeconf(intel_crtc);
5166 intel_crtc->active = true;
5168 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5170 for_each_encoder_on_crtc(dev, crtc, encoder)
5171 if (encoder->pre_pll_enable)
5172 encoder->pre_pll_enable(encoder);
5175 if (IS_CHERRYVIEW(dev))
5176 chv_enable_pll(intel_crtc, intel_crtc->config);
5178 vlv_enable_pll(intel_crtc, intel_crtc->config);
5181 for_each_encoder_on_crtc(dev, crtc, encoder)
5182 if (encoder->pre_enable)
5183 encoder->pre_enable(encoder);
5185 i9xx_pfit_enable(intel_crtc);
5187 intel_crtc_load_lut(crtc);
5189 intel_update_watermarks(crtc);
5190 intel_enable_pipe(intel_crtc);
5192 assert_vblank_disabled(crtc);
5193 drm_crtc_vblank_on(crtc);
5195 for_each_encoder_on_crtc(dev, crtc, encoder)
5196 encoder->enable(encoder);
5198 intel_crtc_enable_planes(crtc);
5200 /* Underruns don't raise interrupts, so check manually. */
5201 i9xx_check_fifo_underruns(dev_priv);
5204 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5206 struct drm_device *dev = crtc->base.dev;
5207 struct drm_i915_private *dev_priv = dev->dev_private;
5209 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5210 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5213 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5215 struct drm_device *dev = crtc->dev;
5216 struct drm_i915_private *dev_priv = to_i915(dev);
5217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5218 struct intel_encoder *encoder;
5219 int pipe = intel_crtc->pipe;
5221 WARN_ON(!crtc->state->enable);
5223 if (intel_crtc->active)
5226 i9xx_set_pll_dividers(intel_crtc);
5228 if (intel_crtc->config->has_dp_encoder)
5229 intel_dp_set_m_n(intel_crtc, M1_N1);
5231 intel_set_pipe_timings(intel_crtc);
5233 i9xx_set_pipeconf(intel_crtc);
5235 intel_crtc->active = true;
5238 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5240 for_each_encoder_on_crtc(dev, crtc, encoder)
5241 if (encoder->pre_enable)
5242 encoder->pre_enable(encoder);
5244 i9xx_enable_pll(intel_crtc);
5246 i9xx_pfit_enable(intel_crtc);
5248 intel_crtc_load_lut(crtc);
5250 intel_update_watermarks(crtc);
5251 intel_enable_pipe(intel_crtc);
5253 assert_vblank_disabled(crtc);
5254 drm_crtc_vblank_on(crtc);
5256 for_each_encoder_on_crtc(dev, crtc, encoder)
5257 encoder->enable(encoder);
5259 intel_crtc_enable_planes(crtc);
5262 * Gen2 reports pipe underruns whenever all planes are disabled.
5263 * So don't enable underrun reporting before at least some planes
5265 * FIXME: Need to fix the logic to work when we turn off all planes
5266 * but leave the pipe running.
5269 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5271 /* Underruns don't raise interrupts, so check manually. */
5272 i9xx_check_fifo_underruns(dev_priv);
5275 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5277 struct drm_device *dev = crtc->base.dev;
5278 struct drm_i915_private *dev_priv = dev->dev_private;
5280 if (!crtc->config->gmch_pfit.control)
5283 assert_pipe_disabled(dev_priv, crtc->pipe);
5285 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5286 I915_READ(PFIT_CONTROL));
5287 I915_WRITE(PFIT_CONTROL, 0);
5290 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5292 struct drm_device *dev = crtc->dev;
5293 struct drm_i915_private *dev_priv = dev->dev_private;
5294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5295 struct intel_encoder *encoder;
5296 int pipe = intel_crtc->pipe;
5298 if (!intel_crtc->active)
5302 * Gen2 reports pipe underruns whenever all planes are disabled.
5303 * So diasble underrun reporting before all the planes get disabled.
5304 * FIXME: Need to fix the logic to work when we turn off all planes
5305 * but leave the pipe running.
5308 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5311 * Vblank time updates from the shadow to live plane control register
5312 * are blocked if the memory self-refresh mode is active at that
5313 * moment. So to make sure the plane gets truly disabled, disable
5314 * first the self-refresh mode. The self-refresh enable bit in turn
5315 * will be checked/applied by the HW only at the next frame start
5316 * event which is after the vblank start event, so we need to have a
5317 * wait-for-vblank between disabling the plane and the pipe.
5319 intel_set_memory_cxsr(dev_priv, false);
5320 intel_crtc_disable_planes(crtc);
5323 * On gen2 planes are double buffered but the pipe isn't, so we must
5324 * wait for planes to fully turn off before disabling the pipe.
5325 * We also need to wait on all gmch platforms because of the
5326 * self-refresh mode constraint explained above.
5328 intel_wait_for_vblank(dev, pipe);
5330 for_each_encoder_on_crtc(dev, crtc, encoder)
5331 encoder->disable(encoder);
5333 drm_crtc_vblank_off(crtc);
5334 assert_vblank_disabled(crtc);
5336 intel_disable_pipe(intel_crtc);
5338 i9xx_pfit_disable(intel_crtc);
5340 for_each_encoder_on_crtc(dev, crtc, encoder)
5341 if (encoder->post_disable)
5342 encoder->post_disable(encoder);
5344 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5345 if (IS_CHERRYVIEW(dev))
5346 chv_disable_pll(dev_priv, pipe);
5347 else if (IS_VALLEYVIEW(dev))
5348 vlv_disable_pll(dev_priv, pipe);
5350 i9xx_disable_pll(intel_crtc);
5354 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5356 intel_crtc->active = false;
5357 intel_update_watermarks(crtc);
5359 mutex_lock(&dev->struct_mutex);
5360 intel_fbc_update(dev);
5361 mutex_unlock(&dev->struct_mutex);
5364 static void i9xx_crtc_off(struct drm_crtc *crtc)
5368 /* Master function to enable/disable CRTC and corresponding power wells */
5369 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5371 struct drm_device *dev = crtc->dev;
5372 struct drm_i915_private *dev_priv = dev->dev_private;
5373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5374 enum intel_display_power_domain domain;
5375 unsigned long domains;
5378 if (!intel_crtc->active) {
5379 domains = get_crtc_power_domains(crtc);
5380 for_each_power_domain(domain, domains)
5381 intel_display_power_get(dev_priv, domain);
5382 intel_crtc->enabled_power_domains = domains;
5384 dev_priv->display.crtc_enable(crtc);
5387 if (intel_crtc->active) {
5388 dev_priv->display.crtc_disable(crtc);
5390 domains = intel_crtc->enabled_power_domains;
5391 for_each_power_domain(domain, domains)
5392 intel_display_power_put(dev_priv, domain);
5393 intel_crtc->enabled_power_domains = 0;
5399 * Sets the power management mode of the pipe and plane.
5401 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5403 struct drm_device *dev = crtc->dev;
5404 struct intel_encoder *intel_encoder;
5405 bool enable = false;
5407 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5408 enable |= intel_encoder->connectors_active;
5410 intel_crtc_control(crtc, enable);
5413 static void intel_crtc_disable(struct drm_crtc *crtc)
5415 struct drm_device *dev = crtc->dev;
5416 struct drm_connector *connector;
5417 struct drm_i915_private *dev_priv = dev->dev_private;
5419 /* crtc should still be enabled when we disable it. */
5420 WARN_ON(!crtc->state->enable);
5422 dev_priv->display.crtc_disable(crtc);
5423 dev_priv->display.off(crtc);
5425 crtc->primary->funcs->disable_plane(crtc->primary);
5427 /* Update computed state. */
5428 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5429 if (!connector->encoder || !connector->encoder->crtc)
5432 if (connector->encoder->crtc != crtc)
5435 connector->dpms = DRM_MODE_DPMS_OFF;
5436 to_intel_encoder(connector->encoder)->connectors_active = false;
5440 void intel_encoder_destroy(struct drm_encoder *encoder)
5442 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5444 drm_encoder_cleanup(encoder);
5445 kfree(intel_encoder);
5448 /* Simple dpms helper for encoders with just one connector, no cloning and only
5449 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5450 * state of the entire output pipe. */
5451 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5453 if (mode == DRM_MODE_DPMS_ON) {
5454 encoder->connectors_active = true;
5456 intel_crtc_update_dpms(encoder->base.crtc);
5458 encoder->connectors_active = false;
5460 intel_crtc_update_dpms(encoder->base.crtc);
5464 /* Cross check the actual hw state with our own modeset state tracking (and it's
5465 * internal consistency). */
5466 static void intel_connector_check_state(struct intel_connector *connector)
5468 if (connector->get_hw_state(connector)) {
5469 struct intel_encoder *encoder = connector->encoder;
5470 struct drm_crtc *crtc;
5471 bool encoder_enabled;
5474 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5475 connector->base.base.id,
5476 connector->base.name);
5478 /* there is no real hw state for MST connectors */
5479 if (connector->mst_port)
5482 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5483 "wrong connector dpms state\n");
5484 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5485 "active connector not linked to encoder\n");
5488 I915_STATE_WARN(!encoder->connectors_active,
5489 "encoder->connectors_active not set\n");
5491 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5492 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5493 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5496 crtc = encoder->base.crtc;
5498 I915_STATE_WARN(!crtc->state->enable,
5499 "crtc not enabled\n");
5500 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5501 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5502 "encoder active on the wrong pipe\n");
5507 /* Even simpler default implementation, if there's really no special case to
5509 void intel_connector_dpms(struct drm_connector *connector, int mode)
5511 /* All the simple cases only support two dpms states. */
5512 if (mode != DRM_MODE_DPMS_ON)
5513 mode = DRM_MODE_DPMS_OFF;
5515 if (mode == connector->dpms)
5518 connector->dpms = mode;
5520 /* Only need to change hw state when actually enabled */
5521 if (connector->encoder)
5522 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5524 intel_modeset_check_state(connector->dev);
5527 /* Simple connector->get_hw_state implementation for encoders that support only
5528 * one connector and no cloning and hence the encoder state determines the state
5529 * of the connector. */
5530 bool intel_connector_get_hw_state(struct intel_connector *connector)
5533 struct intel_encoder *encoder = connector->encoder;
5535 return encoder->get_hw_state(encoder, &pipe);
5538 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5539 struct intel_crtc_state *pipe_config)
5541 struct drm_i915_private *dev_priv = dev->dev_private;
5542 struct intel_crtc *pipe_B_crtc =
5543 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5545 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5546 pipe_name(pipe), pipe_config->fdi_lanes);
5547 if (pipe_config->fdi_lanes > 4) {
5548 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5549 pipe_name(pipe), pipe_config->fdi_lanes);
5553 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5554 if (pipe_config->fdi_lanes > 2) {
5555 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5556 pipe_config->fdi_lanes);
5563 if (INTEL_INFO(dev)->num_pipes == 2)
5566 /* Ivybridge 3 pipe is really complicated */
5571 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5572 pipe_config->fdi_lanes > 2) {
5573 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5574 pipe_name(pipe), pipe_config->fdi_lanes);
5579 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5580 pipe_B_crtc->config->fdi_lanes <= 2) {
5581 if (pipe_config->fdi_lanes > 2) {
5582 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5583 pipe_name(pipe), pipe_config->fdi_lanes);
5587 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5597 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5598 struct intel_crtc_state *pipe_config)
5600 struct drm_device *dev = intel_crtc->base.dev;
5601 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5602 int lane, link_bw, fdi_dotclock;
5603 bool setup_ok, needs_recompute = false;
5606 /* FDI is a binary signal running at ~2.7GHz, encoding
5607 * each output octet as 10 bits. The actual frequency
5608 * is stored as a divider into a 100MHz clock, and the
5609 * mode pixel clock is stored in units of 1KHz.
5610 * Hence the bw of each lane in terms of the mode signal
5613 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5615 fdi_dotclock = adjusted_mode->crtc_clock;
5617 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5618 pipe_config->pipe_bpp);
5620 pipe_config->fdi_lanes = lane;
5622 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5623 link_bw, &pipe_config->fdi_m_n);
5625 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5626 intel_crtc->pipe, pipe_config);
5627 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5628 pipe_config->pipe_bpp -= 2*3;
5629 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5630 pipe_config->pipe_bpp);
5631 needs_recompute = true;
5632 pipe_config->bw_constrained = true;
5637 if (needs_recompute)
5640 return setup_ok ? 0 : -EINVAL;
5643 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5644 struct intel_crtc_state *pipe_config)
5646 pipe_config->ips_enabled = i915.enable_ips &&
5647 hsw_crtc_supports_ips(crtc) &&
5648 pipe_config->pipe_bpp <= 24;
5651 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5652 struct intel_crtc_state *pipe_config)
5654 struct drm_device *dev = crtc->base.dev;
5655 struct drm_i915_private *dev_priv = dev->dev_private;
5656 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5658 /* FIXME should check pixel clock limits on all platforms */
5659 if (INTEL_INFO(dev)->gen < 4) {
5661 dev_priv->display.get_display_clock_speed(dev);
5664 * Enable pixel doubling when the dot clock
5665 * is > 90% of the (display) core speed.
5667 * GDG double wide on either pipe,
5668 * otherwise pipe A only.
5670 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5671 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5673 pipe_config->double_wide = true;
5676 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5681 * Pipe horizontal size must be even in:
5683 * - LVDS dual channel mode
5684 * - Double wide pipe
5686 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5687 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5688 pipe_config->pipe_src_w &= ~1;
5690 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5691 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5693 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5694 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5697 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5698 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5699 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5700 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5702 pipe_config->pipe_bpp = 8*3;
5706 hsw_compute_ips_config(crtc, pipe_config);
5708 if (pipe_config->has_pch_encoder)
5709 return ironlake_fdi_compute_config(crtc, pipe_config);
5714 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5716 struct drm_i915_private *dev_priv = dev->dev_private;
5720 /* FIXME: Punit isn't quite ready yet */
5721 if (IS_CHERRYVIEW(dev))
5724 if (dev_priv->hpll_freq == 0)
5725 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5727 mutex_lock(&dev_priv->dpio_lock);
5728 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5729 mutex_unlock(&dev_priv->dpio_lock);
5731 divider = val & DISPLAY_FREQUENCY_VALUES;
5733 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5734 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5735 "cdclk change in progress\n");
5737 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5740 static int i945_get_display_clock_speed(struct drm_device *dev)
5745 static int i915_get_display_clock_speed(struct drm_device *dev)
5750 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5755 static int pnv_get_display_clock_speed(struct drm_device *dev)
5759 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5761 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5762 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5764 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5766 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5768 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5771 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5772 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5774 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5779 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5783 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5785 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5788 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5789 case GC_DISPLAY_CLOCK_333_MHZ:
5792 case GC_DISPLAY_CLOCK_190_200_MHZ:
5798 static int i865_get_display_clock_speed(struct drm_device *dev)
5803 static int i855_get_display_clock_speed(struct drm_device *dev)
5806 /* Assume that the hardware is in the high speed state. This
5807 * should be the default.
5809 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5810 case GC_CLOCK_133_200:
5811 case GC_CLOCK_100_200:
5813 case GC_CLOCK_166_250:
5815 case GC_CLOCK_100_133:
5819 /* Shouldn't happen */
5823 static int i830_get_display_clock_speed(struct drm_device *dev)
5829 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5831 while (*num > DATA_LINK_M_N_MASK ||
5832 *den > DATA_LINK_M_N_MASK) {
5838 static void compute_m_n(unsigned int m, unsigned int n,
5839 uint32_t *ret_m, uint32_t *ret_n)
5841 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5842 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5843 intel_reduce_m_n_ratio(ret_m, ret_n);
5847 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5848 int pixel_clock, int link_clock,
5849 struct intel_link_m_n *m_n)
5853 compute_m_n(bits_per_pixel * pixel_clock,
5854 link_clock * nlanes * 8,
5855 &m_n->gmch_m, &m_n->gmch_n);
5857 compute_m_n(pixel_clock, link_clock,
5858 &m_n->link_m, &m_n->link_n);
5861 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5863 if (i915.panel_use_ssc >= 0)
5864 return i915.panel_use_ssc != 0;
5865 return dev_priv->vbt.lvds_use_ssc
5866 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5869 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5871 struct drm_device *dev = crtc->base.dev;
5872 struct drm_i915_private *dev_priv = dev->dev_private;
5875 if (IS_VALLEYVIEW(dev)) {
5877 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5878 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5879 refclk = dev_priv->vbt.lvds_ssc_freq;
5880 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5881 } else if (!IS_GEN2(dev)) {
5890 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5892 return (1 << dpll->n) << 16 | dpll->m2;
5895 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5897 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5900 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5901 struct intel_crtc_state *crtc_state,
5902 intel_clock_t *reduced_clock)
5904 struct drm_device *dev = crtc->base.dev;
5907 if (IS_PINEVIEW(dev)) {
5908 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5910 fp2 = pnv_dpll_compute_fp(reduced_clock);
5912 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5914 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5917 crtc_state->dpll_hw_state.fp0 = fp;
5919 crtc->lowfreq_avail = false;
5920 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5921 reduced_clock && i915.powersave) {
5922 crtc_state->dpll_hw_state.fp1 = fp2;
5923 crtc->lowfreq_avail = true;
5925 crtc_state->dpll_hw_state.fp1 = fp;
5929 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5935 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5936 * and set it to a reasonable value instead.
5938 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5939 reg_val &= 0xffffff00;
5940 reg_val |= 0x00000030;
5941 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5943 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5944 reg_val &= 0x8cffffff;
5945 reg_val = 0x8c000000;
5946 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5948 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5949 reg_val &= 0xffffff00;
5950 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5952 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5953 reg_val &= 0x00ffffff;
5954 reg_val |= 0xb0000000;
5955 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5958 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5959 struct intel_link_m_n *m_n)
5961 struct drm_device *dev = crtc->base.dev;
5962 struct drm_i915_private *dev_priv = dev->dev_private;
5963 int pipe = crtc->pipe;
5965 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5966 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5967 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5968 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5971 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5972 struct intel_link_m_n *m_n,
5973 struct intel_link_m_n *m2_n2)
5975 struct drm_device *dev = crtc->base.dev;
5976 struct drm_i915_private *dev_priv = dev->dev_private;
5977 int pipe = crtc->pipe;
5978 enum transcoder transcoder = crtc->config->cpu_transcoder;
5980 if (INTEL_INFO(dev)->gen >= 5) {
5981 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5982 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5983 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5984 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5985 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5986 * for gen < 8) and if DRRS is supported (to make sure the
5987 * registers are not unnecessarily accessed).
5989 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5990 crtc->config->has_drrs) {
5991 I915_WRITE(PIPE_DATA_M2(transcoder),
5992 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5993 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5994 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5995 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5998 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5999 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6000 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6001 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6005 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6007 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6010 dp_m_n = &crtc->config->dp_m_n;
6011 dp_m2_n2 = &crtc->config->dp_m2_n2;
6012 } else if (m_n == M2_N2) {
6015 * M2_N2 registers are not supported. Hence m2_n2 divider value
6016 * needs to be programmed into M1_N1.
6018 dp_m_n = &crtc->config->dp_m2_n2;
6020 DRM_ERROR("Unsupported divider value\n");
6024 if (crtc->config->has_pch_encoder)
6025 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6027 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6030 static void vlv_update_pll(struct intel_crtc *crtc,
6031 struct intel_crtc_state *pipe_config)
6036 * Enable DPIO clock input. We should never disable the reference
6037 * clock for pipe B, since VGA hotplug / manual detection depends
6040 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6041 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6042 /* We should never disable this, set it here for state tracking */
6043 if (crtc->pipe == PIPE_B)
6044 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6045 dpll |= DPLL_VCO_ENABLE;
6046 pipe_config->dpll_hw_state.dpll = dpll;
6048 dpll_md = (pipe_config->pixel_multiplier - 1)
6049 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6050 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6053 static void vlv_prepare_pll(struct intel_crtc *crtc,
6054 const struct intel_crtc_state *pipe_config)
6056 struct drm_device *dev = crtc->base.dev;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 int pipe = crtc->pipe;
6060 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6061 u32 coreclk, reg_val;
6063 mutex_lock(&dev_priv->dpio_lock);
6065 bestn = pipe_config->dpll.n;
6066 bestm1 = pipe_config->dpll.m1;
6067 bestm2 = pipe_config->dpll.m2;
6068 bestp1 = pipe_config->dpll.p1;
6069 bestp2 = pipe_config->dpll.p2;
6071 /* See eDP HDMI DPIO driver vbios notes doc */
6073 /* PLL B needs special handling */
6075 vlv_pllb_recal_opamp(dev_priv, pipe);
6077 /* Set up Tx target for periodic Rcomp update */
6078 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6080 /* Disable target IRef on PLL */
6081 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6082 reg_val &= 0x00ffffff;
6083 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6085 /* Disable fast lock */
6086 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6088 /* Set idtafcrecal before PLL is enabled */
6089 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6090 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6091 mdiv |= ((bestn << DPIO_N_SHIFT));
6092 mdiv |= (1 << DPIO_K_SHIFT);
6095 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6096 * but we don't support that).
6097 * Note: don't use the DAC post divider as it seems unstable.
6099 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6100 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6102 mdiv |= DPIO_ENABLE_CALIBRATION;
6103 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6105 /* Set HBR and RBR LPF coefficients */
6106 if (pipe_config->port_clock == 162000 ||
6107 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6108 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6109 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6112 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6115 if (pipe_config->has_dp_encoder) {
6116 /* Use SSC source */
6118 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6121 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6123 } else { /* HDMI or VGA */
6124 /* Use bend source */
6126 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6129 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6133 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6134 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6136 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6137 coreclk |= 0x01000000;
6138 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6140 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6141 mutex_unlock(&dev_priv->dpio_lock);
6144 static void chv_update_pll(struct intel_crtc *crtc,
6145 struct intel_crtc_state *pipe_config)
6147 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6148 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6150 if (crtc->pipe != PIPE_A)
6151 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6153 pipe_config->dpll_hw_state.dpll_md =
6154 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6157 static void chv_prepare_pll(struct intel_crtc *crtc,
6158 const struct intel_crtc_state *pipe_config)
6160 struct drm_device *dev = crtc->base.dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 int pipe = crtc->pipe;
6163 int dpll_reg = DPLL(crtc->pipe);
6164 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6165 u32 loopfilter, intcoeff;
6166 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6169 bestn = pipe_config->dpll.n;
6170 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6171 bestm1 = pipe_config->dpll.m1;
6172 bestm2 = pipe_config->dpll.m2 >> 22;
6173 bestp1 = pipe_config->dpll.p1;
6174 bestp2 = pipe_config->dpll.p2;
6177 * Enable Refclk and SSC
6179 I915_WRITE(dpll_reg,
6180 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6182 mutex_lock(&dev_priv->dpio_lock);
6184 /* p1 and p2 divider */
6185 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6186 5 << DPIO_CHV_S1_DIV_SHIFT |
6187 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6188 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6189 1 << DPIO_CHV_K_DIV_SHIFT);
6191 /* Feedback post-divider - m2 */
6192 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6194 /* Feedback refclk divider - n and m1 */
6195 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6196 DPIO_CHV_M1_DIV_BY_2 |
6197 1 << DPIO_CHV_N_DIV_SHIFT);
6199 /* M2 fraction division */
6200 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6202 /* M2 fraction division enable */
6203 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6204 DPIO_CHV_FRAC_DIV_EN |
6205 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6208 refclk = i9xx_get_refclk(crtc, 0);
6209 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6210 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6211 if (refclk == 100000)
6213 else if (refclk == 38400)
6217 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6218 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6221 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6222 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6225 mutex_unlock(&dev_priv->dpio_lock);
6229 * vlv_force_pll_on - forcibly enable just the PLL
6230 * @dev_priv: i915 private structure
6231 * @pipe: pipe PLL to enable
6232 * @dpll: PLL configuration
6234 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6235 * in cases where we need the PLL enabled even when @pipe is not going to
6238 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6239 const struct dpll *dpll)
6241 struct intel_crtc *crtc =
6242 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6243 struct intel_crtc_state pipe_config = {
6244 .pixel_multiplier = 1,
6248 if (IS_CHERRYVIEW(dev)) {
6249 chv_update_pll(crtc, &pipe_config);
6250 chv_prepare_pll(crtc, &pipe_config);
6251 chv_enable_pll(crtc, &pipe_config);
6253 vlv_update_pll(crtc, &pipe_config);
6254 vlv_prepare_pll(crtc, &pipe_config);
6255 vlv_enable_pll(crtc, &pipe_config);
6260 * vlv_force_pll_off - forcibly disable just the PLL
6261 * @dev_priv: i915 private structure
6262 * @pipe: pipe PLL to disable
6264 * Disable the PLL for @pipe. To be used in cases where we need
6265 * the PLL enabled even when @pipe is not going to be enabled.
6267 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6269 if (IS_CHERRYVIEW(dev))
6270 chv_disable_pll(to_i915(dev), pipe);
6272 vlv_disable_pll(to_i915(dev), pipe);
6275 static void i9xx_update_pll(struct intel_crtc *crtc,
6276 struct intel_crtc_state *crtc_state,
6277 intel_clock_t *reduced_clock,
6280 struct drm_device *dev = crtc->base.dev;
6281 struct drm_i915_private *dev_priv = dev->dev_private;
6284 struct dpll *clock = &crtc_state->dpll;
6286 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6288 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6289 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6291 dpll = DPLL_VGA_MODE_DIS;
6293 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6294 dpll |= DPLLB_MODE_LVDS;
6296 dpll |= DPLLB_MODE_DAC_SERIAL;
6298 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6299 dpll |= (crtc_state->pixel_multiplier - 1)
6300 << SDVO_MULTIPLIER_SHIFT_HIRES;
6304 dpll |= DPLL_SDVO_HIGH_SPEED;
6306 if (crtc_state->has_dp_encoder)
6307 dpll |= DPLL_SDVO_HIGH_SPEED;
6309 /* compute bitmask from p1 value */
6310 if (IS_PINEVIEW(dev))
6311 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6313 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6314 if (IS_G4X(dev) && reduced_clock)
6315 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6317 switch (clock->p2) {
6319 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6322 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6325 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6328 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6331 if (INTEL_INFO(dev)->gen >= 4)
6332 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6334 if (crtc_state->sdvo_tv_clock)
6335 dpll |= PLL_REF_INPUT_TVCLKINBC;
6336 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6337 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6338 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6340 dpll |= PLL_REF_INPUT_DREFCLK;
6342 dpll |= DPLL_VCO_ENABLE;
6343 crtc_state->dpll_hw_state.dpll = dpll;
6345 if (INTEL_INFO(dev)->gen >= 4) {
6346 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6347 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6348 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6352 static void i8xx_update_pll(struct intel_crtc *crtc,
6353 struct intel_crtc_state *crtc_state,
6354 intel_clock_t *reduced_clock,
6357 struct drm_device *dev = crtc->base.dev;
6358 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct dpll *clock = &crtc_state->dpll;
6362 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6364 dpll = DPLL_VGA_MODE_DIS;
6366 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6367 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6370 dpll |= PLL_P1_DIVIDE_BY_TWO;
6372 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6374 dpll |= PLL_P2_DIVIDE_BY_4;
6377 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6378 dpll |= DPLL_DVO_2X_MODE;
6380 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6381 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6382 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6384 dpll |= PLL_REF_INPUT_DREFCLK;
6386 dpll |= DPLL_VCO_ENABLE;
6387 crtc_state->dpll_hw_state.dpll = dpll;
6390 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6392 struct drm_device *dev = intel_crtc->base.dev;
6393 struct drm_i915_private *dev_priv = dev->dev_private;
6394 enum pipe pipe = intel_crtc->pipe;
6395 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6396 struct drm_display_mode *adjusted_mode =
6397 &intel_crtc->config->base.adjusted_mode;
6398 uint32_t crtc_vtotal, crtc_vblank_end;
6401 /* We need to be careful not to changed the adjusted mode, for otherwise
6402 * the hw state checker will get angry at the mismatch. */
6403 crtc_vtotal = adjusted_mode->crtc_vtotal;
6404 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6406 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6407 /* the chip adds 2 halflines automatically */
6409 crtc_vblank_end -= 1;
6411 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6412 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6414 vsyncshift = adjusted_mode->crtc_hsync_start -
6415 adjusted_mode->crtc_htotal / 2;
6417 vsyncshift += adjusted_mode->crtc_htotal;
6420 if (INTEL_INFO(dev)->gen > 3)
6421 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6423 I915_WRITE(HTOTAL(cpu_transcoder),
6424 (adjusted_mode->crtc_hdisplay - 1) |
6425 ((adjusted_mode->crtc_htotal - 1) << 16));
6426 I915_WRITE(HBLANK(cpu_transcoder),
6427 (adjusted_mode->crtc_hblank_start - 1) |
6428 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6429 I915_WRITE(HSYNC(cpu_transcoder),
6430 (adjusted_mode->crtc_hsync_start - 1) |
6431 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6433 I915_WRITE(VTOTAL(cpu_transcoder),
6434 (adjusted_mode->crtc_vdisplay - 1) |
6435 ((crtc_vtotal - 1) << 16));
6436 I915_WRITE(VBLANK(cpu_transcoder),
6437 (adjusted_mode->crtc_vblank_start - 1) |
6438 ((crtc_vblank_end - 1) << 16));
6439 I915_WRITE(VSYNC(cpu_transcoder),
6440 (adjusted_mode->crtc_vsync_start - 1) |
6441 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6443 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6444 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6445 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6447 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6448 (pipe == PIPE_B || pipe == PIPE_C))
6449 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6451 /* pipesrc controls the size that is scaled from, which should
6452 * always be the user's requested size.
6454 I915_WRITE(PIPESRC(pipe),
6455 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6456 (intel_crtc->config->pipe_src_h - 1));
6459 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6460 struct intel_crtc_state *pipe_config)
6462 struct drm_device *dev = crtc->base.dev;
6463 struct drm_i915_private *dev_priv = dev->dev_private;
6464 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6467 tmp = I915_READ(HTOTAL(cpu_transcoder));
6468 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6469 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6470 tmp = I915_READ(HBLANK(cpu_transcoder));
6471 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6472 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6473 tmp = I915_READ(HSYNC(cpu_transcoder));
6474 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6475 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6477 tmp = I915_READ(VTOTAL(cpu_transcoder));
6478 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6479 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6480 tmp = I915_READ(VBLANK(cpu_transcoder));
6481 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6482 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6483 tmp = I915_READ(VSYNC(cpu_transcoder));
6484 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6485 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6487 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6488 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6489 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6490 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6493 tmp = I915_READ(PIPESRC(crtc->pipe));
6494 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6495 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6497 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6498 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6501 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6502 struct intel_crtc_state *pipe_config)
6504 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6505 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6506 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6507 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6509 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6510 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6511 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6512 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6514 mode->flags = pipe_config->base.adjusted_mode.flags;
6516 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6517 mode->flags |= pipe_config->base.adjusted_mode.flags;
6520 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6522 struct drm_device *dev = intel_crtc->base.dev;
6523 struct drm_i915_private *dev_priv = dev->dev_private;
6528 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6529 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6530 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6532 if (intel_crtc->config->double_wide)
6533 pipeconf |= PIPECONF_DOUBLE_WIDE;
6535 /* only g4x and later have fancy bpc/dither controls */
6536 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6537 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6538 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6539 pipeconf |= PIPECONF_DITHER_EN |
6540 PIPECONF_DITHER_TYPE_SP;
6542 switch (intel_crtc->config->pipe_bpp) {
6544 pipeconf |= PIPECONF_6BPC;
6547 pipeconf |= PIPECONF_8BPC;
6550 pipeconf |= PIPECONF_10BPC;
6553 /* Case prevented by intel_choose_pipe_bpp_dither. */
6558 if (HAS_PIPE_CXSR(dev)) {
6559 if (intel_crtc->lowfreq_avail) {
6560 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6561 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6563 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6567 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6568 if (INTEL_INFO(dev)->gen < 4 ||
6569 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6570 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6572 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6574 pipeconf |= PIPECONF_PROGRESSIVE;
6576 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6577 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6579 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6580 POSTING_READ(PIPECONF(intel_crtc->pipe));
6583 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6584 struct intel_crtc_state *crtc_state)
6586 struct drm_device *dev = crtc->base.dev;
6587 struct drm_i915_private *dev_priv = dev->dev_private;
6588 int refclk, num_connectors = 0;
6589 intel_clock_t clock, reduced_clock;
6590 bool ok, has_reduced_clock = false;
6591 bool is_lvds = false, is_dsi = false;
6592 struct intel_encoder *encoder;
6593 const intel_limit_t *limit;
6595 for_each_intel_encoder(dev, encoder) {
6596 if (encoder->new_crtc != crtc)
6599 switch (encoder->type) {
6600 case INTEL_OUTPUT_LVDS:
6603 case INTEL_OUTPUT_DSI:
6616 if (!crtc_state->clock_set) {
6617 refclk = i9xx_get_refclk(crtc, num_connectors);
6620 * Returns a set of divisors for the desired target clock with
6621 * the given refclk, or FALSE. The returned values represent
6622 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6625 limit = intel_limit(crtc, refclk);
6626 ok = dev_priv->display.find_dpll(limit, crtc,
6627 crtc_state->port_clock,
6628 refclk, NULL, &clock);
6630 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6634 if (is_lvds && dev_priv->lvds_downclock_avail) {
6636 * Ensure we match the reduced clock's P to the target
6637 * clock. If the clocks don't match, we can't switch
6638 * the display clock by using the FP0/FP1. In such case
6639 * we will disable the LVDS downclock feature.
6642 dev_priv->display.find_dpll(limit, crtc,
6643 dev_priv->lvds_downclock,
6647 /* Compat-code for transition, will disappear. */
6648 crtc_state->dpll.n = clock.n;
6649 crtc_state->dpll.m1 = clock.m1;
6650 crtc_state->dpll.m2 = clock.m2;
6651 crtc_state->dpll.p1 = clock.p1;
6652 crtc_state->dpll.p2 = clock.p2;
6656 i8xx_update_pll(crtc, crtc_state,
6657 has_reduced_clock ? &reduced_clock : NULL,
6659 } else if (IS_CHERRYVIEW(dev)) {
6660 chv_update_pll(crtc, crtc_state);
6661 } else if (IS_VALLEYVIEW(dev)) {
6662 vlv_update_pll(crtc, crtc_state);
6664 i9xx_update_pll(crtc, crtc_state,
6665 has_reduced_clock ? &reduced_clock : NULL,
6672 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6673 struct intel_crtc_state *pipe_config)
6675 struct drm_device *dev = crtc->base.dev;
6676 struct drm_i915_private *dev_priv = dev->dev_private;
6679 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6682 tmp = I915_READ(PFIT_CONTROL);
6683 if (!(tmp & PFIT_ENABLE))
6686 /* Check whether the pfit is attached to our pipe. */
6687 if (INTEL_INFO(dev)->gen < 4) {
6688 if (crtc->pipe != PIPE_B)
6691 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6695 pipe_config->gmch_pfit.control = tmp;
6696 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6697 if (INTEL_INFO(dev)->gen < 5)
6698 pipe_config->gmch_pfit.lvds_border_bits =
6699 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6702 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6703 struct intel_crtc_state *pipe_config)
6705 struct drm_device *dev = crtc->base.dev;
6706 struct drm_i915_private *dev_priv = dev->dev_private;
6707 int pipe = pipe_config->cpu_transcoder;
6708 intel_clock_t clock;
6710 int refclk = 100000;
6712 /* In case of MIPI DPLL will not even be used */
6713 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6716 mutex_lock(&dev_priv->dpio_lock);
6717 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6718 mutex_unlock(&dev_priv->dpio_lock);
6720 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6721 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6722 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6723 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6724 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6726 vlv_clock(refclk, &clock);
6728 /* clock.dot is the fast clock */
6729 pipe_config->port_clock = clock.dot / 5;
6733 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6734 struct intel_initial_plane_config *plane_config)
6736 struct drm_device *dev = crtc->base.dev;
6737 struct drm_i915_private *dev_priv = dev->dev_private;
6738 u32 val, base, offset;
6739 int pipe = crtc->pipe, plane = crtc->plane;
6740 int fourcc, pixel_format;
6742 struct drm_framebuffer *fb;
6743 struct intel_framebuffer *intel_fb;
6745 val = I915_READ(DSPCNTR(plane));
6746 if (!(val & DISPLAY_PLANE_ENABLE))
6749 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6751 DRM_DEBUG_KMS("failed to alloc fb\n");
6755 fb = &intel_fb->base;
6757 if (INTEL_INFO(dev)->gen >= 4) {
6758 if (val & DISPPLANE_TILED) {
6759 plane_config->tiling = I915_TILING_X;
6760 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6764 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6765 fourcc = i9xx_format_to_fourcc(pixel_format);
6766 fb->pixel_format = fourcc;
6767 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6769 if (INTEL_INFO(dev)->gen >= 4) {
6770 if (plane_config->tiling)
6771 offset = I915_READ(DSPTILEOFF(plane));
6773 offset = I915_READ(DSPLINOFF(plane));
6774 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6776 base = I915_READ(DSPADDR(plane));
6778 plane_config->base = base;
6780 val = I915_READ(PIPESRC(pipe));
6781 fb->width = ((val >> 16) & 0xfff) + 1;
6782 fb->height = ((val >> 0) & 0xfff) + 1;
6784 val = I915_READ(DSPSTRIDE(pipe));
6785 fb->pitches[0] = val & 0xffffffc0;
6787 aligned_height = intel_fb_align_height(dev, fb->height,
6791 plane_config->size = fb->pitches[0] * aligned_height;
6793 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6794 pipe_name(pipe), plane, fb->width, fb->height,
6795 fb->bits_per_pixel, base, fb->pitches[0],
6796 plane_config->size);
6798 plane_config->fb = intel_fb;
6801 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6802 struct intel_crtc_state *pipe_config)
6804 struct drm_device *dev = crtc->base.dev;
6805 struct drm_i915_private *dev_priv = dev->dev_private;
6806 int pipe = pipe_config->cpu_transcoder;
6807 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6808 intel_clock_t clock;
6809 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6810 int refclk = 100000;
6812 mutex_lock(&dev_priv->dpio_lock);
6813 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6814 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6815 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6816 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6817 mutex_unlock(&dev_priv->dpio_lock);
6819 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6820 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6821 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6822 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6823 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6825 chv_clock(refclk, &clock);
6827 /* clock.dot is the fast clock */
6828 pipe_config->port_clock = clock.dot / 5;
6831 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6832 struct intel_crtc_state *pipe_config)
6834 struct drm_device *dev = crtc->base.dev;
6835 struct drm_i915_private *dev_priv = dev->dev_private;
6838 if (!intel_display_power_is_enabled(dev_priv,
6839 POWER_DOMAIN_PIPE(crtc->pipe)))
6842 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6843 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6845 tmp = I915_READ(PIPECONF(crtc->pipe));
6846 if (!(tmp & PIPECONF_ENABLE))
6849 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6850 switch (tmp & PIPECONF_BPC_MASK) {
6852 pipe_config->pipe_bpp = 18;
6855 pipe_config->pipe_bpp = 24;
6857 case PIPECONF_10BPC:
6858 pipe_config->pipe_bpp = 30;
6865 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6866 pipe_config->limited_color_range = true;
6868 if (INTEL_INFO(dev)->gen < 4)
6869 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6871 intel_get_pipe_timings(crtc, pipe_config);
6873 i9xx_get_pfit_config(crtc, pipe_config);
6875 if (INTEL_INFO(dev)->gen >= 4) {
6876 tmp = I915_READ(DPLL_MD(crtc->pipe));
6877 pipe_config->pixel_multiplier =
6878 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6879 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6880 pipe_config->dpll_hw_state.dpll_md = tmp;
6881 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6882 tmp = I915_READ(DPLL(crtc->pipe));
6883 pipe_config->pixel_multiplier =
6884 ((tmp & SDVO_MULTIPLIER_MASK)
6885 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6887 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6888 * port and will be fixed up in the encoder->get_config
6890 pipe_config->pixel_multiplier = 1;
6892 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6893 if (!IS_VALLEYVIEW(dev)) {
6895 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6896 * on 830. Filter it out here so that we don't
6897 * report errors due to that.
6900 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6902 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6903 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6905 /* Mask out read-only status bits. */
6906 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6907 DPLL_PORTC_READY_MASK |
6908 DPLL_PORTB_READY_MASK);
6911 if (IS_CHERRYVIEW(dev))
6912 chv_crtc_clock_get(crtc, pipe_config);
6913 else if (IS_VALLEYVIEW(dev))
6914 vlv_crtc_clock_get(crtc, pipe_config);
6916 i9xx_crtc_clock_get(crtc, pipe_config);
6921 static void ironlake_init_pch_refclk(struct drm_device *dev)
6923 struct drm_i915_private *dev_priv = dev->dev_private;
6924 struct intel_encoder *encoder;
6926 bool has_lvds = false;
6927 bool has_cpu_edp = false;
6928 bool has_panel = false;
6929 bool has_ck505 = false;
6930 bool can_ssc = false;
6932 /* We need to take the global config into account */
6933 for_each_intel_encoder(dev, encoder) {
6934 switch (encoder->type) {
6935 case INTEL_OUTPUT_LVDS:
6939 case INTEL_OUTPUT_EDP:
6941 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6949 if (HAS_PCH_IBX(dev)) {
6950 has_ck505 = dev_priv->vbt.display_clock_mode;
6951 can_ssc = has_ck505;
6957 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6958 has_panel, has_lvds, has_ck505);
6960 /* Ironlake: try to setup display ref clock before DPLL
6961 * enabling. This is only under driver's control after
6962 * PCH B stepping, previous chipset stepping should be
6963 * ignoring this setting.
6965 val = I915_READ(PCH_DREF_CONTROL);
6967 /* As we must carefully and slowly disable/enable each source in turn,
6968 * compute the final state we want first and check if we need to
6969 * make any changes at all.
6972 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6974 final |= DREF_NONSPREAD_CK505_ENABLE;
6976 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6978 final &= ~DREF_SSC_SOURCE_MASK;
6979 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6980 final &= ~DREF_SSC1_ENABLE;
6983 final |= DREF_SSC_SOURCE_ENABLE;
6985 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6986 final |= DREF_SSC1_ENABLE;
6989 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6990 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6992 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6994 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6996 final |= DREF_SSC_SOURCE_DISABLE;
6997 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7003 /* Always enable nonspread source */
7004 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7007 val |= DREF_NONSPREAD_CK505_ENABLE;
7009 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7012 val &= ~DREF_SSC_SOURCE_MASK;
7013 val |= DREF_SSC_SOURCE_ENABLE;
7015 /* SSC must be turned on before enabling the CPU output */
7016 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7017 DRM_DEBUG_KMS("Using SSC on panel\n");
7018 val |= DREF_SSC1_ENABLE;
7020 val &= ~DREF_SSC1_ENABLE;
7022 /* Get SSC going before enabling the outputs */
7023 I915_WRITE(PCH_DREF_CONTROL, val);
7024 POSTING_READ(PCH_DREF_CONTROL);
7027 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7029 /* Enable CPU source on CPU attached eDP */
7031 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7032 DRM_DEBUG_KMS("Using SSC on eDP\n");
7033 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7035 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7037 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7039 I915_WRITE(PCH_DREF_CONTROL, val);
7040 POSTING_READ(PCH_DREF_CONTROL);
7043 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7045 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7047 /* Turn off CPU output */
7048 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7050 I915_WRITE(PCH_DREF_CONTROL, val);
7051 POSTING_READ(PCH_DREF_CONTROL);
7054 /* Turn off the SSC source */
7055 val &= ~DREF_SSC_SOURCE_MASK;
7056 val |= DREF_SSC_SOURCE_DISABLE;
7059 val &= ~DREF_SSC1_ENABLE;
7061 I915_WRITE(PCH_DREF_CONTROL, val);
7062 POSTING_READ(PCH_DREF_CONTROL);
7066 BUG_ON(val != final);
7069 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7073 tmp = I915_READ(SOUTH_CHICKEN2);
7074 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7075 I915_WRITE(SOUTH_CHICKEN2, tmp);
7077 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7078 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7079 DRM_ERROR("FDI mPHY reset assert timeout\n");
7081 tmp = I915_READ(SOUTH_CHICKEN2);
7082 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7083 I915_WRITE(SOUTH_CHICKEN2, tmp);
7085 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7086 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7087 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7090 /* WaMPhyProgramming:hsw */
7091 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7095 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7096 tmp &= ~(0xFF << 24);
7097 tmp |= (0x12 << 24);
7098 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7100 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7102 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7104 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7106 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7108 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7109 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7110 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7112 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7113 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7114 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7116 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7119 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7121 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7124 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7126 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7129 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7131 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7134 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7136 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7137 tmp &= ~(0xFF << 16);
7138 tmp |= (0x1C << 16);
7139 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7141 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7142 tmp &= ~(0xFF << 16);
7143 tmp |= (0x1C << 16);
7144 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7146 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7148 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7150 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7152 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7154 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7155 tmp &= ~(0xF << 28);
7157 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7159 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7160 tmp &= ~(0xF << 28);
7162 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7165 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7166 * Programming" based on the parameters passed:
7167 * - Sequence to enable CLKOUT_DP
7168 * - Sequence to enable CLKOUT_DP without spread
7169 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7171 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7174 struct drm_i915_private *dev_priv = dev->dev_private;
7177 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7179 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7180 with_fdi, "LP PCH doesn't have FDI\n"))
7183 mutex_lock(&dev_priv->dpio_lock);
7185 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7186 tmp &= ~SBI_SSCCTL_DISABLE;
7187 tmp |= SBI_SSCCTL_PATHALT;
7188 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7193 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7194 tmp &= ~SBI_SSCCTL_PATHALT;
7195 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7198 lpt_reset_fdi_mphy(dev_priv);
7199 lpt_program_fdi_mphy(dev_priv);
7203 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7204 SBI_GEN0 : SBI_DBUFF0;
7205 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7206 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7207 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7209 mutex_unlock(&dev_priv->dpio_lock);
7212 /* Sequence to disable CLKOUT_DP */
7213 static void lpt_disable_clkout_dp(struct drm_device *dev)
7215 struct drm_i915_private *dev_priv = dev->dev_private;
7218 mutex_lock(&dev_priv->dpio_lock);
7220 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7221 SBI_GEN0 : SBI_DBUFF0;
7222 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7223 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7224 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7226 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7227 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7228 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7229 tmp |= SBI_SSCCTL_PATHALT;
7230 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7233 tmp |= SBI_SSCCTL_DISABLE;
7234 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7237 mutex_unlock(&dev_priv->dpio_lock);
7240 static void lpt_init_pch_refclk(struct drm_device *dev)
7242 struct intel_encoder *encoder;
7243 bool has_vga = false;
7245 for_each_intel_encoder(dev, encoder) {
7246 switch (encoder->type) {
7247 case INTEL_OUTPUT_ANALOG:
7256 lpt_enable_clkout_dp(dev, true, true);
7258 lpt_disable_clkout_dp(dev);
7262 * Initialize reference clocks when the driver loads
7264 void intel_init_pch_refclk(struct drm_device *dev)
7266 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7267 ironlake_init_pch_refclk(dev);
7268 else if (HAS_PCH_LPT(dev))
7269 lpt_init_pch_refclk(dev);
7272 static int ironlake_get_refclk(struct drm_crtc *crtc)
7274 struct drm_device *dev = crtc->dev;
7275 struct drm_i915_private *dev_priv = dev->dev_private;
7276 struct intel_encoder *encoder;
7277 int num_connectors = 0;
7278 bool is_lvds = false;
7280 for_each_intel_encoder(dev, encoder) {
7281 if (encoder->new_crtc != to_intel_crtc(crtc))
7284 switch (encoder->type) {
7285 case INTEL_OUTPUT_LVDS:
7294 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7295 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7296 dev_priv->vbt.lvds_ssc_freq);
7297 return dev_priv->vbt.lvds_ssc_freq;
7303 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7305 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7307 int pipe = intel_crtc->pipe;
7312 switch (intel_crtc->config->pipe_bpp) {
7314 val |= PIPECONF_6BPC;
7317 val |= PIPECONF_8BPC;
7320 val |= PIPECONF_10BPC;
7323 val |= PIPECONF_12BPC;
7326 /* Case prevented by intel_choose_pipe_bpp_dither. */
7330 if (intel_crtc->config->dither)
7331 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7333 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7334 val |= PIPECONF_INTERLACED_ILK;
7336 val |= PIPECONF_PROGRESSIVE;
7338 if (intel_crtc->config->limited_color_range)
7339 val |= PIPECONF_COLOR_RANGE_SELECT;
7341 I915_WRITE(PIPECONF(pipe), val);
7342 POSTING_READ(PIPECONF(pipe));
7346 * Set up the pipe CSC unit.
7348 * Currently only full range RGB to limited range RGB conversion
7349 * is supported, but eventually this should handle various
7350 * RGB<->YCbCr scenarios as well.
7352 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7354 struct drm_device *dev = crtc->dev;
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7357 int pipe = intel_crtc->pipe;
7358 uint16_t coeff = 0x7800; /* 1.0 */
7361 * TODO: Check what kind of values actually come out of the pipe
7362 * with these coeff/postoff values and adjust to get the best
7363 * accuracy. Perhaps we even need to take the bpc value into
7367 if (intel_crtc->config->limited_color_range)
7368 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7371 * GY/GU and RY/RU should be the other way around according
7372 * to BSpec, but reality doesn't agree. Just set them up in
7373 * a way that results in the correct picture.
7375 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7376 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7378 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7379 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7381 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7382 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7384 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7385 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7386 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7388 if (INTEL_INFO(dev)->gen > 6) {
7389 uint16_t postoff = 0;
7391 if (intel_crtc->config->limited_color_range)
7392 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7394 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7395 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7396 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7398 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7400 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7402 if (intel_crtc->config->limited_color_range)
7403 mode |= CSC_BLACK_SCREEN_OFFSET;
7405 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7409 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7411 struct drm_device *dev = crtc->dev;
7412 struct drm_i915_private *dev_priv = dev->dev_private;
7413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7414 enum pipe pipe = intel_crtc->pipe;
7415 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7420 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7421 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7423 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7424 val |= PIPECONF_INTERLACED_ILK;
7426 val |= PIPECONF_PROGRESSIVE;
7428 I915_WRITE(PIPECONF(cpu_transcoder), val);
7429 POSTING_READ(PIPECONF(cpu_transcoder));
7431 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7432 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7434 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7437 switch (intel_crtc->config->pipe_bpp) {
7439 val |= PIPEMISC_DITHER_6_BPC;
7442 val |= PIPEMISC_DITHER_8_BPC;
7445 val |= PIPEMISC_DITHER_10_BPC;
7448 val |= PIPEMISC_DITHER_12_BPC;
7451 /* Case prevented by pipe_config_set_bpp. */
7455 if (intel_crtc->config->dither)
7456 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7458 I915_WRITE(PIPEMISC(pipe), val);
7462 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7463 struct intel_crtc_state *crtc_state,
7464 intel_clock_t *clock,
7465 bool *has_reduced_clock,
7466 intel_clock_t *reduced_clock)
7468 struct drm_device *dev = crtc->dev;
7469 struct drm_i915_private *dev_priv = dev->dev_private;
7470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7472 const intel_limit_t *limit;
7473 bool ret, is_lvds = false;
7475 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7477 refclk = ironlake_get_refclk(crtc);
7480 * Returns a set of divisors for the desired target clock with the given
7481 * refclk, or FALSE. The returned values represent the clock equation:
7482 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7484 limit = intel_limit(intel_crtc, refclk);
7485 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7486 crtc_state->port_clock,
7487 refclk, NULL, clock);
7491 if (is_lvds && dev_priv->lvds_downclock_avail) {
7493 * Ensure we match the reduced clock's P to the target clock.
7494 * If the clocks don't match, we can't switch the display clock
7495 * by using the FP0/FP1. In such case we will disable the LVDS
7496 * downclock feature.
7498 *has_reduced_clock =
7499 dev_priv->display.find_dpll(limit, intel_crtc,
7500 dev_priv->lvds_downclock,
7508 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7511 * Account for spread spectrum to avoid
7512 * oversubscribing the link. Max center spread
7513 * is 2.5%; use 5% for safety's sake.
7515 u32 bps = target_clock * bpp * 21 / 20;
7516 return DIV_ROUND_UP(bps, link_bw * 8);
7519 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7521 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7524 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7525 struct intel_crtc_state *crtc_state,
7527 intel_clock_t *reduced_clock, u32 *fp2)
7529 struct drm_crtc *crtc = &intel_crtc->base;
7530 struct drm_device *dev = crtc->dev;
7531 struct drm_i915_private *dev_priv = dev->dev_private;
7532 struct intel_encoder *intel_encoder;
7534 int factor, num_connectors = 0;
7535 bool is_lvds = false, is_sdvo = false;
7537 for_each_intel_encoder(dev, intel_encoder) {
7538 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7541 switch (intel_encoder->type) {
7542 case INTEL_OUTPUT_LVDS:
7545 case INTEL_OUTPUT_SDVO:
7546 case INTEL_OUTPUT_HDMI:
7556 /* Enable autotuning of the PLL clock (if permissible) */
7559 if ((intel_panel_use_ssc(dev_priv) &&
7560 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7561 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7563 } else if (crtc_state->sdvo_tv_clock)
7566 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7569 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7575 dpll |= DPLLB_MODE_LVDS;
7577 dpll |= DPLLB_MODE_DAC_SERIAL;
7579 dpll |= (crtc_state->pixel_multiplier - 1)
7580 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7583 dpll |= DPLL_SDVO_HIGH_SPEED;
7584 if (crtc_state->has_dp_encoder)
7585 dpll |= DPLL_SDVO_HIGH_SPEED;
7587 /* compute bitmask from p1 value */
7588 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7590 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7592 switch (crtc_state->dpll.p2) {
7594 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7597 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7600 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7603 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7607 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7608 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7610 dpll |= PLL_REF_INPUT_DREFCLK;
7612 return dpll | DPLL_VCO_ENABLE;
7615 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7616 struct intel_crtc_state *crtc_state)
7618 struct drm_device *dev = crtc->base.dev;
7619 intel_clock_t clock, reduced_clock;
7620 u32 dpll = 0, fp = 0, fp2 = 0;
7621 bool ok, has_reduced_clock = false;
7622 bool is_lvds = false;
7623 struct intel_shared_dpll *pll;
7625 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7627 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7628 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7630 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7631 &has_reduced_clock, &reduced_clock);
7632 if (!ok && !crtc_state->clock_set) {
7633 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7636 /* Compat-code for transition, will disappear. */
7637 if (!crtc_state->clock_set) {
7638 crtc_state->dpll.n = clock.n;
7639 crtc_state->dpll.m1 = clock.m1;
7640 crtc_state->dpll.m2 = clock.m2;
7641 crtc_state->dpll.p1 = clock.p1;
7642 crtc_state->dpll.p2 = clock.p2;
7645 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7646 if (crtc_state->has_pch_encoder) {
7647 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7648 if (has_reduced_clock)
7649 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7651 dpll = ironlake_compute_dpll(crtc, crtc_state,
7652 &fp, &reduced_clock,
7653 has_reduced_clock ? &fp2 : NULL);
7655 crtc_state->dpll_hw_state.dpll = dpll;
7656 crtc_state->dpll_hw_state.fp0 = fp;
7657 if (has_reduced_clock)
7658 crtc_state->dpll_hw_state.fp1 = fp2;
7660 crtc_state->dpll_hw_state.fp1 = fp;
7662 pll = intel_get_shared_dpll(crtc, crtc_state);
7664 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7665 pipe_name(crtc->pipe));
7670 if (is_lvds && has_reduced_clock && i915.powersave)
7671 crtc->lowfreq_avail = true;
7673 crtc->lowfreq_avail = false;
7678 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7679 struct intel_link_m_n *m_n)
7681 struct drm_device *dev = crtc->base.dev;
7682 struct drm_i915_private *dev_priv = dev->dev_private;
7683 enum pipe pipe = crtc->pipe;
7685 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7686 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7687 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7689 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7690 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7691 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7694 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7695 enum transcoder transcoder,
7696 struct intel_link_m_n *m_n,
7697 struct intel_link_m_n *m2_n2)
7699 struct drm_device *dev = crtc->base.dev;
7700 struct drm_i915_private *dev_priv = dev->dev_private;
7701 enum pipe pipe = crtc->pipe;
7703 if (INTEL_INFO(dev)->gen >= 5) {
7704 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7705 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7706 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7708 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7709 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7710 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7711 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7712 * gen < 8) and if DRRS is supported (to make sure the
7713 * registers are not unnecessarily read).
7715 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7716 crtc->config->has_drrs) {
7717 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7718 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7719 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7721 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7722 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7723 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7726 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7727 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7728 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7730 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7731 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7732 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7736 void intel_dp_get_m_n(struct intel_crtc *crtc,
7737 struct intel_crtc_state *pipe_config)
7739 if (pipe_config->has_pch_encoder)
7740 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7742 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7743 &pipe_config->dp_m_n,
7744 &pipe_config->dp_m2_n2);
7747 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7748 struct intel_crtc_state *pipe_config)
7750 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7751 &pipe_config->fdi_m_n, NULL);
7754 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7755 struct intel_crtc_state *pipe_config)
7757 struct drm_device *dev = crtc->base.dev;
7758 struct drm_i915_private *dev_priv = dev->dev_private;
7761 tmp = I915_READ(PS_CTL(crtc->pipe));
7763 if (tmp & PS_ENABLE) {
7764 pipe_config->pch_pfit.enabled = true;
7765 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7766 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7771 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7772 struct intel_initial_plane_config *plane_config)
7774 struct drm_device *dev = crtc->base.dev;
7775 struct drm_i915_private *dev_priv = dev->dev_private;
7776 u32 val, base, offset, stride_mult, tiling;
7777 int pipe = crtc->pipe;
7778 int fourcc, pixel_format;
7780 struct drm_framebuffer *fb;
7781 struct intel_framebuffer *intel_fb;
7783 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7785 DRM_DEBUG_KMS("failed to alloc fb\n");
7789 fb = &intel_fb->base;
7791 val = I915_READ(PLANE_CTL(pipe, 0));
7792 if (!(val & PLANE_CTL_ENABLE))
7795 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7796 fourcc = skl_format_to_fourcc(pixel_format,
7797 val & PLANE_CTL_ORDER_RGBX,
7798 val & PLANE_CTL_ALPHA_MASK);
7799 fb->pixel_format = fourcc;
7800 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7802 tiling = val & PLANE_CTL_TILED_MASK;
7804 case PLANE_CTL_TILED_LINEAR:
7805 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7807 case PLANE_CTL_TILED_X:
7808 plane_config->tiling = I915_TILING_X;
7809 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7811 case PLANE_CTL_TILED_Y:
7812 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7814 case PLANE_CTL_TILED_YF:
7815 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7818 MISSING_CASE(tiling);
7822 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7823 plane_config->base = base;
7825 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7827 val = I915_READ(PLANE_SIZE(pipe, 0));
7828 fb->height = ((val >> 16) & 0xfff) + 1;
7829 fb->width = ((val >> 0) & 0x1fff) + 1;
7831 val = I915_READ(PLANE_STRIDE(pipe, 0));
7832 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7834 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7836 aligned_height = intel_fb_align_height(dev, fb->height,
7840 plane_config->size = fb->pitches[0] * aligned_height;
7842 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7843 pipe_name(pipe), fb->width, fb->height,
7844 fb->bits_per_pixel, base, fb->pitches[0],
7845 plane_config->size);
7847 plane_config->fb = intel_fb;
7854 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7855 struct intel_crtc_state *pipe_config)
7857 struct drm_device *dev = crtc->base.dev;
7858 struct drm_i915_private *dev_priv = dev->dev_private;
7861 tmp = I915_READ(PF_CTL(crtc->pipe));
7863 if (tmp & PF_ENABLE) {
7864 pipe_config->pch_pfit.enabled = true;
7865 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7866 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7868 /* We currently do not free assignements of panel fitters on
7869 * ivb/hsw (since we don't use the higher upscaling modes which
7870 * differentiates them) so just WARN about this case for now. */
7872 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7873 PF_PIPE_SEL_IVB(crtc->pipe));
7879 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7880 struct intel_initial_plane_config *plane_config)
7882 struct drm_device *dev = crtc->base.dev;
7883 struct drm_i915_private *dev_priv = dev->dev_private;
7884 u32 val, base, offset;
7885 int pipe = crtc->pipe;
7886 int fourcc, pixel_format;
7888 struct drm_framebuffer *fb;
7889 struct intel_framebuffer *intel_fb;
7891 val = I915_READ(DSPCNTR(pipe));
7892 if (!(val & DISPLAY_PLANE_ENABLE))
7895 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7897 DRM_DEBUG_KMS("failed to alloc fb\n");
7901 fb = &intel_fb->base;
7903 if (INTEL_INFO(dev)->gen >= 4) {
7904 if (val & DISPPLANE_TILED) {
7905 plane_config->tiling = I915_TILING_X;
7906 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7910 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7911 fourcc = i9xx_format_to_fourcc(pixel_format);
7912 fb->pixel_format = fourcc;
7913 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7915 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7916 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7917 offset = I915_READ(DSPOFFSET(pipe));
7919 if (plane_config->tiling)
7920 offset = I915_READ(DSPTILEOFF(pipe));
7922 offset = I915_READ(DSPLINOFF(pipe));
7924 plane_config->base = base;
7926 val = I915_READ(PIPESRC(pipe));
7927 fb->width = ((val >> 16) & 0xfff) + 1;
7928 fb->height = ((val >> 0) & 0xfff) + 1;
7930 val = I915_READ(DSPSTRIDE(pipe));
7931 fb->pitches[0] = val & 0xffffffc0;
7933 aligned_height = intel_fb_align_height(dev, fb->height,
7937 plane_config->size = fb->pitches[0] * aligned_height;
7939 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7940 pipe_name(pipe), fb->width, fb->height,
7941 fb->bits_per_pixel, base, fb->pitches[0],
7942 plane_config->size);
7944 plane_config->fb = intel_fb;
7947 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7948 struct intel_crtc_state *pipe_config)
7950 struct drm_device *dev = crtc->base.dev;
7951 struct drm_i915_private *dev_priv = dev->dev_private;
7954 if (!intel_display_power_is_enabled(dev_priv,
7955 POWER_DOMAIN_PIPE(crtc->pipe)))
7958 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7959 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7961 tmp = I915_READ(PIPECONF(crtc->pipe));
7962 if (!(tmp & PIPECONF_ENABLE))
7965 switch (tmp & PIPECONF_BPC_MASK) {
7967 pipe_config->pipe_bpp = 18;
7970 pipe_config->pipe_bpp = 24;
7972 case PIPECONF_10BPC:
7973 pipe_config->pipe_bpp = 30;
7975 case PIPECONF_12BPC:
7976 pipe_config->pipe_bpp = 36;
7982 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7983 pipe_config->limited_color_range = true;
7985 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7986 struct intel_shared_dpll *pll;
7988 pipe_config->has_pch_encoder = true;
7990 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7991 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7992 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7994 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7996 if (HAS_PCH_IBX(dev_priv->dev)) {
7997 pipe_config->shared_dpll =
7998 (enum intel_dpll_id) crtc->pipe;
8000 tmp = I915_READ(PCH_DPLL_SEL);
8001 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8002 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8004 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8007 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8009 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8010 &pipe_config->dpll_hw_state));
8012 tmp = pipe_config->dpll_hw_state.dpll;
8013 pipe_config->pixel_multiplier =
8014 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8015 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8017 ironlake_pch_clock_get(crtc, pipe_config);
8019 pipe_config->pixel_multiplier = 1;
8022 intel_get_pipe_timings(crtc, pipe_config);
8024 ironlake_get_pfit_config(crtc, pipe_config);
8029 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8031 struct drm_device *dev = dev_priv->dev;
8032 struct intel_crtc *crtc;
8034 for_each_intel_crtc(dev, crtc)
8035 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8036 pipe_name(crtc->pipe));
8038 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8039 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8040 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8041 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8042 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8043 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8044 "CPU PWM1 enabled\n");
8045 if (IS_HASWELL(dev))
8046 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8047 "CPU PWM2 enabled\n");
8048 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8049 "PCH PWM1 enabled\n");
8050 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8051 "Utility pin enabled\n");
8052 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8055 * In theory we can still leave IRQs enabled, as long as only the HPD
8056 * interrupts remain enabled. We used to check for that, but since it's
8057 * gen-specific and since we only disable LCPLL after we fully disable
8058 * the interrupts, the check below should be enough.
8060 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8063 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8065 struct drm_device *dev = dev_priv->dev;
8067 if (IS_HASWELL(dev))
8068 return I915_READ(D_COMP_HSW);
8070 return I915_READ(D_COMP_BDW);
8073 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8075 struct drm_device *dev = dev_priv->dev;
8077 if (IS_HASWELL(dev)) {
8078 mutex_lock(&dev_priv->rps.hw_lock);
8079 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8081 DRM_ERROR("Failed to write to D_COMP\n");
8082 mutex_unlock(&dev_priv->rps.hw_lock);
8084 I915_WRITE(D_COMP_BDW, val);
8085 POSTING_READ(D_COMP_BDW);
8090 * This function implements pieces of two sequences from BSpec:
8091 * - Sequence for display software to disable LCPLL
8092 * - Sequence for display software to allow package C8+
8093 * The steps implemented here are just the steps that actually touch the LCPLL
8094 * register. Callers should take care of disabling all the display engine
8095 * functions, doing the mode unset, fixing interrupts, etc.
8097 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8098 bool switch_to_fclk, bool allow_power_down)
8102 assert_can_disable_lcpll(dev_priv);
8104 val = I915_READ(LCPLL_CTL);
8106 if (switch_to_fclk) {
8107 val |= LCPLL_CD_SOURCE_FCLK;
8108 I915_WRITE(LCPLL_CTL, val);
8110 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8111 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8112 DRM_ERROR("Switching to FCLK failed\n");
8114 val = I915_READ(LCPLL_CTL);
8117 val |= LCPLL_PLL_DISABLE;
8118 I915_WRITE(LCPLL_CTL, val);
8119 POSTING_READ(LCPLL_CTL);
8121 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8122 DRM_ERROR("LCPLL still locked\n");
8124 val = hsw_read_dcomp(dev_priv);
8125 val |= D_COMP_COMP_DISABLE;
8126 hsw_write_dcomp(dev_priv, val);
8129 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8131 DRM_ERROR("D_COMP RCOMP still in progress\n");
8133 if (allow_power_down) {
8134 val = I915_READ(LCPLL_CTL);
8135 val |= LCPLL_POWER_DOWN_ALLOW;
8136 I915_WRITE(LCPLL_CTL, val);
8137 POSTING_READ(LCPLL_CTL);
8142 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8145 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8149 val = I915_READ(LCPLL_CTL);
8151 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8152 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8156 * Make sure we're not on PC8 state before disabling PC8, otherwise
8157 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8159 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8161 if (val & LCPLL_POWER_DOWN_ALLOW) {
8162 val &= ~LCPLL_POWER_DOWN_ALLOW;
8163 I915_WRITE(LCPLL_CTL, val);
8164 POSTING_READ(LCPLL_CTL);
8167 val = hsw_read_dcomp(dev_priv);
8168 val |= D_COMP_COMP_FORCE;
8169 val &= ~D_COMP_COMP_DISABLE;
8170 hsw_write_dcomp(dev_priv, val);
8172 val = I915_READ(LCPLL_CTL);
8173 val &= ~LCPLL_PLL_DISABLE;
8174 I915_WRITE(LCPLL_CTL, val);
8176 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8177 DRM_ERROR("LCPLL not locked yet\n");
8179 if (val & LCPLL_CD_SOURCE_FCLK) {
8180 val = I915_READ(LCPLL_CTL);
8181 val &= ~LCPLL_CD_SOURCE_FCLK;
8182 I915_WRITE(LCPLL_CTL, val);
8184 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8185 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8186 DRM_ERROR("Switching back to LCPLL failed\n");
8189 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8193 * Package states C8 and deeper are really deep PC states that can only be
8194 * reached when all the devices on the system allow it, so even if the graphics
8195 * device allows PC8+, it doesn't mean the system will actually get to these
8196 * states. Our driver only allows PC8+ when going into runtime PM.
8198 * The requirements for PC8+ are that all the outputs are disabled, the power
8199 * well is disabled and most interrupts are disabled, and these are also
8200 * requirements for runtime PM. When these conditions are met, we manually do
8201 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8202 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8205 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8206 * the state of some registers, so when we come back from PC8+ we need to
8207 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8208 * need to take care of the registers kept by RC6. Notice that this happens even
8209 * if we don't put the device in PCI D3 state (which is what currently happens
8210 * because of the runtime PM support).
8212 * For more, read "Display Sequences for Package C8" on the hardware
8215 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8217 struct drm_device *dev = dev_priv->dev;
8220 DRM_DEBUG_KMS("Enabling package C8+\n");
8222 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8223 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8224 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8225 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8228 lpt_disable_clkout_dp(dev);
8229 hsw_disable_lcpll(dev_priv, true, true);
8232 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8234 struct drm_device *dev = dev_priv->dev;
8237 DRM_DEBUG_KMS("Disabling package C8+\n");
8239 hsw_restore_lcpll(dev_priv);
8240 lpt_init_pch_refclk(dev);
8242 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8243 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8244 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8245 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8248 intel_prepare_ddi(dev);
8251 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8252 struct intel_crtc_state *crtc_state)
8254 if (!intel_ddi_pll_select(crtc, crtc_state))
8257 crtc->lowfreq_avail = false;
8262 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8264 struct intel_crtc_state *pipe_config)
8266 u32 temp, dpll_ctl1;
8268 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8269 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8271 switch (pipe_config->ddi_pll_sel) {
8274 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8275 * of the shared DPLL framework and thus needs to be read out
8278 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8279 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8282 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8285 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8288 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8293 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8295 struct intel_crtc_state *pipe_config)
8297 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8299 switch (pipe_config->ddi_pll_sel) {
8300 case PORT_CLK_SEL_WRPLL1:
8301 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8303 case PORT_CLK_SEL_WRPLL2:
8304 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8309 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8310 struct intel_crtc_state *pipe_config)
8312 struct drm_device *dev = crtc->base.dev;
8313 struct drm_i915_private *dev_priv = dev->dev_private;
8314 struct intel_shared_dpll *pll;
8318 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8320 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8322 if (IS_SKYLAKE(dev))
8323 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8325 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8327 if (pipe_config->shared_dpll >= 0) {
8328 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8330 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8331 &pipe_config->dpll_hw_state));
8335 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8336 * DDI E. So just check whether this pipe is wired to DDI E and whether
8337 * the PCH transcoder is on.
8339 if (INTEL_INFO(dev)->gen < 9 &&
8340 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8341 pipe_config->has_pch_encoder = true;
8343 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8344 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8345 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8347 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8351 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8352 struct intel_crtc_state *pipe_config)
8354 struct drm_device *dev = crtc->base.dev;
8355 struct drm_i915_private *dev_priv = dev->dev_private;
8356 enum intel_display_power_domain pfit_domain;
8359 if (!intel_display_power_is_enabled(dev_priv,
8360 POWER_DOMAIN_PIPE(crtc->pipe)))
8363 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8364 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8366 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8367 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8368 enum pipe trans_edp_pipe;
8369 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8371 WARN(1, "unknown pipe linked to edp transcoder\n");
8372 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8373 case TRANS_DDI_EDP_INPUT_A_ON:
8374 trans_edp_pipe = PIPE_A;
8376 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8377 trans_edp_pipe = PIPE_B;
8379 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8380 trans_edp_pipe = PIPE_C;
8384 if (trans_edp_pipe == crtc->pipe)
8385 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8388 if (!intel_display_power_is_enabled(dev_priv,
8389 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8392 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8393 if (!(tmp & PIPECONF_ENABLE))
8396 haswell_get_ddi_port_state(crtc, pipe_config);
8398 intel_get_pipe_timings(crtc, pipe_config);
8400 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8401 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8402 if (IS_SKYLAKE(dev))
8403 skylake_get_pfit_config(crtc, pipe_config);
8405 ironlake_get_pfit_config(crtc, pipe_config);
8408 if (IS_HASWELL(dev))
8409 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8410 (I915_READ(IPS_CTL) & IPS_ENABLE);
8412 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8413 pipe_config->pixel_multiplier =
8414 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8416 pipe_config->pixel_multiplier = 1;
8422 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8424 struct drm_device *dev = crtc->dev;
8425 struct drm_i915_private *dev_priv = dev->dev_private;
8426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8427 uint32_t cntl = 0, size = 0;
8430 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8431 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8432 unsigned int stride = roundup_pow_of_two(width) * 4;
8436 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8447 cntl |= CURSOR_ENABLE |
8448 CURSOR_GAMMA_ENABLE |
8449 CURSOR_FORMAT_ARGB |
8450 CURSOR_STRIDE(stride);
8452 size = (height << 12) | width;
8455 if (intel_crtc->cursor_cntl != 0 &&
8456 (intel_crtc->cursor_base != base ||
8457 intel_crtc->cursor_size != size ||
8458 intel_crtc->cursor_cntl != cntl)) {
8459 /* On these chipsets we can only modify the base/size/stride
8460 * whilst the cursor is disabled.
8462 I915_WRITE(_CURACNTR, 0);
8463 POSTING_READ(_CURACNTR);
8464 intel_crtc->cursor_cntl = 0;
8467 if (intel_crtc->cursor_base != base) {
8468 I915_WRITE(_CURABASE, base);
8469 intel_crtc->cursor_base = base;
8472 if (intel_crtc->cursor_size != size) {
8473 I915_WRITE(CURSIZE, size);
8474 intel_crtc->cursor_size = size;
8477 if (intel_crtc->cursor_cntl != cntl) {
8478 I915_WRITE(_CURACNTR, cntl);
8479 POSTING_READ(_CURACNTR);
8480 intel_crtc->cursor_cntl = cntl;
8484 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8486 struct drm_device *dev = crtc->dev;
8487 struct drm_i915_private *dev_priv = dev->dev_private;
8488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8489 int pipe = intel_crtc->pipe;
8494 cntl = MCURSOR_GAMMA_ENABLE;
8495 switch (intel_crtc->base.cursor->state->crtc_w) {
8497 cntl |= CURSOR_MODE_64_ARGB_AX;
8500 cntl |= CURSOR_MODE_128_ARGB_AX;
8503 cntl |= CURSOR_MODE_256_ARGB_AX;
8506 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8509 cntl |= pipe << 28; /* Connect to correct pipe */
8511 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8512 cntl |= CURSOR_PIPE_CSC_ENABLE;
8515 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8516 cntl |= CURSOR_ROTATE_180;
8518 if (intel_crtc->cursor_cntl != cntl) {
8519 I915_WRITE(CURCNTR(pipe), cntl);
8520 POSTING_READ(CURCNTR(pipe));
8521 intel_crtc->cursor_cntl = cntl;
8524 /* and commit changes on next vblank */
8525 I915_WRITE(CURBASE(pipe), base);
8526 POSTING_READ(CURBASE(pipe));
8528 intel_crtc->cursor_base = base;
8531 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8532 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8535 struct drm_device *dev = crtc->dev;
8536 struct drm_i915_private *dev_priv = dev->dev_private;
8537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8538 int pipe = intel_crtc->pipe;
8539 int x = crtc->cursor_x;
8540 int y = crtc->cursor_y;
8541 u32 base = 0, pos = 0;
8544 base = intel_crtc->cursor_addr;
8546 if (x >= intel_crtc->config->pipe_src_w)
8549 if (y >= intel_crtc->config->pipe_src_h)
8553 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8556 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8559 pos |= x << CURSOR_X_SHIFT;
8562 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8565 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8568 pos |= y << CURSOR_Y_SHIFT;
8570 if (base == 0 && intel_crtc->cursor_base == 0)
8573 I915_WRITE(CURPOS(pipe), pos);
8575 /* ILK+ do this automagically */
8576 if (HAS_GMCH_DISPLAY(dev) &&
8577 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8578 base += (intel_crtc->base.cursor->state->crtc_h *
8579 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8582 if (IS_845G(dev) || IS_I865G(dev))
8583 i845_update_cursor(crtc, base);
8585 i9xx_update_cursor(crtc, base);
8588 static bool cursor_size_ok(struct drm_device *dev,
8589 uint32_t width, uint32_t height)
8591 if (width == 0 || height == 0)
8595 * 845g/865g are special in that they are only limited by
8596 * the width of their cursors, the height is arbitrary up to
8597 * the precision of the register. Everything else requires
8598 * square cursors, limited to a few power-of-two sizes.
8600 if (IS_845G(dev) || IS_I865G(dev)) {
8601 if ((width & 63) != 0)
8604 if (width > (IS_845G(dev) ? 64 : 512))
8610 switch (width | height) {
8625 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8626 u16 *blue, uint32_t start, uint32_t size)
8628 int end = (start + size > 256) ? 256 : start + size, i;
8629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8631 for (i = start; i < end; i++) {
8632 intel_crtc->lut_r[i] = red[i] >> 8;
8633 intel_crtc->lut_g[i] = green[i] >> 8;
8634 intel_crtc->lut_b[i] = blue[i] >> 8;
8637 intel_crtc_load_lut(crtc);
8640 /* VESA 640x480x72Hz mode to set on the pipe */
8641 static struct drm_display_mode load_detect_mode = {
8642 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8643 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8646 struct drm_framebuffer *
8647 __intel_framebuffer_create(struct drm_device *dev,
8648 struct drm_mode_fb_cmd2 *mode_cmd,
8649 struct drm_i915_gem_object *obj)
8651 struct intel_framebuffer *intel_fb;
8654 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8656 drm_gem_object_unreference(&obj->base);
8657 return ERR_PTR(-ENOMEM);
8660 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8664 return &intel_fb->base;
8666 drm_gem_object_unreference(&obj->base);
8669 return ERR_PTR(ret);
8672 static struct drm_framebuffer *
8673 intel_framebuffer_create(struct drm_device *dev,
8674 struct drm_mode_fb_cmd2 *mode_cmd,
8675 struct drm_i915_gem_object *obj)
8677 struct drm_framebuffer *fb;
8680 ret = i915_mutex_lock_interruptible(dev);
8682 return ERR_PTR(ret);
8683 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8684 mutex_unlock(&dev->struct_mutex);
8690 intel_framebuffer_pitch_for_width(int width, int bpp)
8692 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8693 return ALIGN(pitch, 64);
8697 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8699 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8700 return PAGE_ALIGN(pitch * mode->vdisplay);
8703 static struct drm_framebuffer *
8704 intel_framebuffer_create_for_mode(struct drm_device *dev,
8705 struct drm_display_mode *mode,
8708 struct drm_i915_gem_object *obj;
8709 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8711 obj = i915_gem_alloc_object(dev,
8712 intel_framebuffer_size_for_mode(mode, bpp));
8714 return ERR_PTR(-ENOMEM);
8716 mode_cmd.width = mode->hdisplay;
8717 mode_cmd.height = mode->vdisplay;
8718 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8720 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8722 return intel_framebuffer_create(dev, &mode_cmd, obj);
8725 static struct drm_framebuffer *
8726 mode_fits_in_fbdev(struct drm_device *dev,
8727 struct drm_display_mode *mode)
8729 #ifdef CONFIG_DRM_I915_FBDEV
8730 struct drm_i915_private *dev_priv = dev->dev_private;
8731 struct drm_i915_gem_object *obj;
8732 struct drm_framebuffer *fb;
8734 if (!dev_priv->fbdev)
8737 if (!dev_priv->fbdev->fb)
8740 obj = dev_priv->fbdev->fb->obj;
8743 fb = &dev_priv->fbdev->fb->base;
8744 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8745 fb->bits_per_pixel))
8748 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8757 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8758 struct drm_display_mode *mode,
8759 struct intel_load_detect_pipe *old,
8760 struct drm_modeset_acquire_ctx *ctx)
8762 struct intel_crtc *intel_crtc;
8763 struct intel_encoder *intel_encoder =
8764 intel_attached_encoder(connector);
8765 struct drm_crtc *possible_crtc;
8766 struct drm_encoder *encoder = &intel_encoder->base;
8767 struct drm_crtc *crtc = NULL;
8768 struct drm_device *dev = encoder->dev;
8769 struct drm_framebuffer *fb;
8770 struct drm_mode_config *config = &dev->mode_config;
8773 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8774 connector->base.id, connector->name,
8775 encoder->base.id, encoder->name);
8778 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8783 * Algorithm gets a little messy:
8785 * - if the connector already has an assigned crtc, use it (but make
8786 * sure it's on first)
8788 * - try to find the first unused crtc that can drive this connector,
8789 * and use that if we find one
8792 /* See if we already have a CRTC for this connector */
8793 if (encoder->crtc) {
8794 crtc = encoder->crtc;
8796 ret = drm_modeset_lock(&crtc->mutex, ctx);
8799 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8803 old->dpms_mode = connector->dpms;
8804 old->load_detect_temp = false;
8806 /* Make sure the crtc and connector are running */
8807 if (connector->dpms != DRM_MODE_DPMS_ON)
8808 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8813 /* Find an unused one (if possible) */
8814 for_each_crtc(dev, possible_crtc) {
8816 if (!(encoder->possible_crtcs & (1 << i)))
8818 if (possible_crtc->state->enable)
8820 /* This can occur when applying the pipe A quirk on resume. */
8821 if (to_intel_crtc(possible_crtc)->new_enabled)
8824 crtc = possible_crtc;
8829 * If we didn't find an unused CRTC, don't use any.
8832 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8836 ret = drm_modeset_lock(&crtc->mutex, ctx);
8839 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8842 intel_encoder->new_crtc = to_intel_crtc(crtc);
8843 to_intel_connector(connector)->new_encoder = intel_encoder;
8845 intel_crtc = to_intel_crtc(crtc);
8846 intel_crtc->new_enabled = true;
8847 intel_crtc->new_config = intel_crtc->config;
8848 old->dpms_mode = connector->dpms;
8849 old->load_detect_temp = true;
8850 old->release_fb = NULL;
8853 mode = &load_detect_mode;
8855 /* We need a framebuffer large enough to accommodate all accesses
8856 * that the plane may generate whilst we perform load detection.
8857 * We can not rely on the fbcon either being present (we get called
8858 * during its initialisation to detect all boot displays, or it may
8859 * not even exist) or that it is large enough to satisfy the
8862 fb = mode_fits_in_fbdev(dev, mode);
8864 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8865 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8866 old->release_fb = fb;
8868 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8870 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8874 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8875 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8876 if (old->release_fb)
8877 old->release_fb->funcs->destroy(old->release_fb);
8880 crtc->primary->crtc = crtc;
8882 /* let the connector get through one full cycle before testing */
8883 intel_wait_for_vblank(dev, intel_crtc->pipe);
8887 intel_crtc->new_enabled = crtc->state->enable;
8888 if (intel_crtc->new_enabled)
8889 intel_crtc->new_config = intel_crtc->config;
8891 intel_crtc->new_config = NULL;
8893 if (ret == -EDEADLK) {
8894 drm_modeset_backoff(ctx);
8901 void intel_release_load_detect_pipe(struct drm_connector *connector,
8902 struct intel_load_detect_pipe *old)
8904 struct intel_encoder *intel_encoder =
8905 intel_attached_encoder(connector);
8906 struct drm_encoder *encoder = &intel_encoder->base;
8907 struct drm_crtc *crtc = encoder->crtc;
8908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8910 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8911 connector->base.id, connector->name,
8912 encoder->base.id, encoder->name);
8914 if (old->load_detect_temp) {
8915 to_intel_connector(connector)->new_encoder = NULL;
8916 intel_encoder->new_crtc = NULL;
8917 intel_crtc->new_enabled = false;
8918 intel_crtc->new_config = NULL;
8919 intel_set_mode(crtc, NULL, 0, 0, NULL);
8921 if (old->release_fb) {
8922 drm_framebuffer_unregister_private(old->release_fb);
8923 drm_framebuffer_unreference(old->release_fb);
8929 /* Switch crtc and encoder back off if necessary */
8930 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8931 connector->funcs->dpms(connector, old->dpms_mode);
8934 static int i9xx_pll_refclk(struct drm_device *dev,
8935 const struct intel_crtc_state *pipe_config)
8937 struct drm_i915_private *dev_priv = dev->dev_private;
8938 u32 dpll = pipe_config->dpll_hw_state.dpll;
8940 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8941 return dev_priv->vbt.lvds_ssc_freq;
8942 else if (HAS_PCH_SPLIT(dev))
8944 else if (!IS_GEN2(dev))
8950 /* Returns the clock of the currently programmed mode of the given pipe. */
8951 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8952 struct intel_crtc_state *pipe_config)
8954 struct drm_device *dev = crtc->base.dev;
8955 struct drm_i915_private *dev_priv = dev->dev_private;
8956 int pipe = pipe_config->cpu_transcoder;
8957 u32 dpll = pipe_config->dpll_hw_state.dpll;
8959 intel_clock_t clock;
8960 int refclk = i9xx_pll_refclk(dev, pipe_config);
8962 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8963 fp = pipe_config->dpll_hw_state.fp0;
8965 fp = pipe_config->dpll_hw_state.fp1;
8967 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8968 if (IS_PINEVIEW(dev)) {
8969 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8970 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8972 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8973 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8976 if (!IS_GEN2(dev)) {
8977 if (IS_PINEVIEW(dev))
8978 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8979 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8981 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8982 DPLL_FPA01_P1_POST_DIV_SHIFT);
8984 switch (dpll & DPLL_MODE_MASK) {
8985 case DPLLB_MODE_DAC_SERIAL:
8986 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8989 case DPLLB_MODE_LVDS:
8990 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8994 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8995 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8999 if (IS_PINEVIEW(dev))
9000 pineview_clock(refclk, &clock);
9002 i9xx_clock(refclk, &clock);
9004 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9005 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9008 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9009 DPLL_FPA01_P1_POST_DIV_SHIFT);
9011 if (lvds & LVDS_CLKB_POWER_UP)
9016 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9019 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9020 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9022 if (dpll & PLL_P2_DIVIDE_BY_4)
9028 i9xx_clock(refclk, &clock);
9032 * This value includes pixel_multiplier. We will use
9033 * port_clock to compute adjusted_mode.crtc_clock in the
9034 * encoder's get_config() function.
9036 pipe_config->port_clock = clock.dot;
9039 int intel_dotclock_calculate(int link_freq,
9040 const struct intel_link_m_n *m_n)
9043 * The calculation for the data clock is:
9044 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9045 * But we want to avoid losing precison if possible, so:
9046 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9048 * and the link clock is simpler:
9049 * link_clock = (m * link_clock) / n
9055 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9058 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9059 struct intel_crtc_state *pipe_config)
9061 struct drm_device *dev = crtc->base.dev;
9063 /* read out port_clock from the DPLL */
9064 i9xx_crtc_clock_get(crtc, pipe_config);
9067 * This value does not include pixel_multiplier.
9068 * We will check that port_clock and adjusted_mode.crtc_clock
9069 * agree once we know their relationship in the encoder's
9070 * get_config() function.
9072 pipe_config->base.adjusted_mode.crtc_clock =
9073 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9074 &pipe_config->fdi_m_n);
9077 /** Returns the currently programmed mode of the given pipe. */
9078 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9079 struct drm_crtc *crtc)
9081 struct drm_i915_private *dev_priv = dev->dev_private;
9082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9083 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9084 struct drm_display_mode *mode;
9085 struct intel_crtc_state pipe_config;
9086 int htot = I915_READ(HTOTAL(cpu_transcoder));
9087 int hsync = I915_READ(HSYNC(cpu_transcoder));
9088 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9089 int vsync = I915_READ(VSYNC(cpu_transcoder));
9090 enum pipe pipe = intel_crtc->pipe;
9092 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9097 * Construct a pipe_config sufficient for getting the clock info
9098 * back out of crtc_clock_get.
9100 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9101 * to use a real value here instead.
9103 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9104 pipe_config.pixel_multiplier = 1;
9105 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9106 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9107 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9108 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9110 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9111 mode->hdisplay = (htot & 0xffff) + 1;
9112 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9113 mode->hsync_start = (hsync & 0xffff) + 1;
9114 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9115 mode->vdisplay = (vtot & 0xffff) + 1;
9116 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9117 mode->vsync_start = (vsync & 0xffff) + 1;
9118 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9120 drm_mode_set_name(mode);
9125 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9127 struct drm_device *dev = crtc->dev;
9128 struct drm_i915_private *dev_priv = dev->dev_private;
9129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9131 if (!HAS_GMCH_DISPLAY(dev))
9134 if (!dev_priv->lvds_downclock_avail)
9138 * Since this is called by a timer, we should never get here in
9141 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9142 int pipe = intel_crtc->pipe;
9143 int dpll_reg = DPLL(pipe);
9146 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9148 assert_panel_unlocked(dev_priv, pipe);
9150 dpll = I915_READ(dpll_reg);
9151 dpll |= DISPLAY_RATE_SELECT_FPA1;
9152 I915_WRITE(dpll_reg, dpll);
9153 intel_wait_for_vblank(dev, pipe);
9154 dpll = I915_READ(dpll_reg);
9155 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9156 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9161 void intel_mark_busy(struct drm_device *dev)
9163 struct drm_i915_private *dev_priv = dev->dev_private;
9165 if (dev_priv->mm.busy)
9168 intel_runtime_pm_get(dev_priv);
9169 i915_update_gfx_val(dev_priv);
9170 dev_priv->mm.busy = true;
9173 void intel_mark_idle(struct drm_device *dev)
9175 struct drm_i915_private *dev_priv = dev->dev_private;
9176 struct drm_crtc *crtc;
9178 if (!dev_priv->mm.busy)
9181 dev_priv->mm.busy = false;
9183 if (!i915.powersave)
9186 for_each_crtc(dev, crtc) {
9187 if (!crtc->primary->fb)
9190 intel_decrease_pllclock(crtc);
9193 if (INTEL_INFO(dev)->gen >= 6)
9194 gen6_rps_idle(dev->dev_private);
9197 intel_runtime_pm_put(dev_priv);
9200 static void intel_crtc_set_state(struct intel_crtc *crtc,
9201 struct intel_crtc_state *crtc_state)
9203 kfree(crtc->config);
9204 crtc->config = crtc_state;
9205 crtc->base.state = &crtc_state->base;
9208 static void intel_crtc_destroy(struct drm_crtc *crtc)
9210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9211 struct drm_device *dev = crtc->dev;
9212 struct intel_unpin_work *work;
9214 spin_lock_irq(&dev->event_lock);
9215 work = intel_crtc->unpin_work;
9216 intel_crtc->unpin_work = NULL;
9217 spin_unlock_irq(&dev->event_lock);
9220 cancel_work_sync(&work->work);
9224 intel_crtc_set_state(intel_crtc, NULL);
9225 drm_crtc_cleanup(crtc);
9230 static void intel_unpin_work_fn(struct work_struct *__work)
9232 struct intel_unpin_work *work =
9233 container_of(__work, struct intel_unpin_work, work);
9234 struct drm_device *dev = work->crtc->dev;
9235 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9237 mutex_lock(&dev->struct_mutex);
9238 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9239 drm_gem_object_unreference(&work->pending_flip_obj->base);
9240 drm_framebuffer_unreference(work->old_fb);
9242 intel_fbc_update(dev);
9244 if (work->flip_queued_req)
9245 i915_gem_request_assign(&work->flip_queued_req, NULL);
9246 mutex_unlock(&dev->struct_mutex);
9248 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9250 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9251 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9256 static void do_intel_finish_page_flip(struct drm_device *dev,
9257 struct drm_crtc *crtc)
9259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9260 struct intel_unpin_work *work;
9261 unsigned long flags;
9263 /* Ignore early vblank irqs */
9264 if (intel_crtc == NULL)
9268 * This is called both by irq handlers and the reset code (to complete
9269 * lost pageflips) so needs the full irqsave spinlocks.
9271 spin_lock_irqsave(&dev->event_lock, flags);
9272 work = intel_crtc->unpin_work;
9274 /* Ensure we don't miss a work->pending update ... */
9277 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9278 spin_unlock_irqrestore(&dev->event_lock, flags);
9282 page_flip_completed(intel_crtc);
9284 spin_unlock_irqrestore(&dev->event_lock, flags);
9287 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9289 struct drm_i915_private *dev_priv = dev->dev_private;
9290 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9292 do_intel_finish_page_flip(dev, crtc);
9295 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9297 struct drm_i915_private *dev_priv = dev->dev_private;
9298 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9300 do_intel_finish_page_flip(dev, crtc);
9303 /* Is 'a' after or equal to 'b'? */
9304 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9306 return !((a - b) & 0x80000000);
9309 static bool page_flip_finished(struct intel_crtc *crtc)
9311 struct drm_device *dev = crtc->base.dev;
9312 struct drm_i915_private *dev_priv = dev->dev_private;
9314 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9315 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9319 * The relevant registers doen't exist on pre-ctg.
9320 * As the flip done interrupt doesn't trigger for mmio
9321 * flips on gmch platforms, a flip count check isn't
9322 * really needed there. But since ctg has the registers,
9323 * include it in the check anyway.
9325 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9329 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9330 * used the same base address. In that case the mmio flip might
9331 * have completed, but the CS hasn't even executed the flip yet.
9333 * A flip count check isn't enough as the CS might have updated
9334 * the base address just after start of vblank, but before we
9335 * managed to process the interrupt. This means we'd complete the
9338 * Combining both checks should get us a good enough result. It may
9339 * still happen that the CS flip has been executed, but has not
9340 * yet actually completed. But in case the base address is the same
9341 * anyway, we don't really care.
9343 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9344 crtc->unpin_work->gtt_offset &&
9345 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9346 crtc->unpin_work->flip_count);
9349 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9351 struct drm_i915_private *dev_priv = dev->dev_private;
9352 struct intel_crtc *intel_crtc =
9353 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9354 unsigned long flags;
9358 * This is called both by irq handlers and the reset code (to complete
9359 * lost pageflips) so needs the full irqsave spinlocks.
9361 * NB: An MMIO update of the plane base pointer will also
9362 * generate a page-flip completion irq, i.e. every modeset
9363 * is also accompanied by a spurious intel_prepare_page_flip().
9365 spin_lock_irqsave(&dev->event_lock, flags);
9366 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9367 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9368 spin_unlock_irqrestore(&dev->event_lock, flags);
9371 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9373 /* Ensure that the work item is consistent when activating it ... */
9375 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9376 /* and that it is marked active as soon as the irq could fire. */
9380 static int intel_gen2_queue_flip(struct drm_device *dev,
9381 struct drm_crtc *crtc,
9382 struct drm_framebuffer *fb,
9383 struct drm_i915_gem_object *obj,
9384 struct intel_engine_cs *ring,
9387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9391 ret = intel_ring_begin(ring, 6);
9395 /* Can't queue multiple flips, so wait for the previous
9396 * one to finish before executing the next.
9398 if (intel_crtc->plane)
9399 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9401 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9402 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9403 intel_ring_emit(ring, MI_NOOP);
9404 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9405 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9406 intel_ring_emit(ring, fb->pitches[0]);
9407 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9408 intel_ring_emit(ring, 0); /* aux display base address, unused */
9410 intel_mark_page_flip_active(intel_crtc);
9411 __intel_ring_advance(ring);
9415 static int intel_gen3_queue_flip(struct drm_device *dev,
9416 struct drm_crtc *crtc,
9417 struct drm_framebuffer *fb,
9418 struct drm_i915_gem_object *obj,
9419 struct intel_engine_cs *ring,
9422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9426 ret = intel_ring_begin(ring, 6);
9430 if (intel_crtc->plane)
9431 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9433 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9434 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9435 intel_ring_emit(ring, MI_NOOP);
9436 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9437 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9438 intel_ring_emit(ring, fb->pitches[0]);
9439 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9440 intel_ring_emit(ring, MI_NOOP);
9442 intel_mark_page_flip_active(intel_crtc);
9443 __intel_ring_advance(ring);
9447 static int intel_gen4_queue_flip(struct drm_device *dev,
9448 struct drm_crtc *crtc,
9449 struct drm_framebuffer *fb,
9450 struct drm_i915_gem_object *obj,
9451 struct intel_engine_cs *ring,
9454 struct drm_i915_private *dev_priv = dev->dev_private;
9455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9456 uint32_t pf, pipesrc;
9459 ret = intel_ring_begin(ring, 4);
9463 /* i965+ uses the linear or tiled offsets from the
9464 * Display Registers (which do not change across a page-flip)
9465 * so we need only reprogram the base address.
9467 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9468 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9469 intel_ring_emit(ring, fb->pitches[0]);
9470 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9473 /* XXX Enabling the panel-fitter across page-flip is so far
9474 * untested on non-native modes, so ignore it for now.
9475 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9478 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9479 intel_ring_emit(ring, pf | pipesrc);
9481 intel_mark_page_flip_active(intel_crtc);
9482 __intel_ring_advance(ring);
9486 static int intel_gen6_queue_flip(struct drm_device *dev,
9487 struct drm_crtc *crtc,
9488 struct drm_framebuffer *fb,
9489 struct drm_i915_gem_object *obj,
9490 struct intel_engine_cs *ring,
9493 struct drm_i915_private *dev_priv = dev->dev_private;
9494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9495 uint32_t pf, pipesrc;
9498 ret = intel_ring_begin(ring, 4);
9502 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9503 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9504 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9505 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9507 /* Contrary to the suggestions in the documentation,
9508 * "Enable Panel Fitter" does not seem to be required when page
9509 * flipping with a non-native mode, and worse causes a normal
9511 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9514 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9515 intel_ring_emit(ring, pf | pipesrc);
9517 intel_mark_page_flip_active(intel_crtc);
9518 __intel_ring_advance(ring);
9522 static int intel_gen7_queue_flip(struct drm_device *dev,
9523 struct drm_crtc *crtc,
9524 struct drm_framebuffer *fb,
9525 struct drm_i915_gem_object *obj,
9526 struct intel_engine_cs *ring,
9529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9530 uint32_t plane_bit = 0;
9533 switch (intel_crtc->plane) {
9535 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9538 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9541 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9544 WARN_ONCE(1, "unknown plane in flip command\n");
9549 if (ring->id == RCS) {
9552 * On Gen 8, SRM is now taking an extra dword to accommodate
9553 * 48bits addresses, and we need a NOOP for the batch size to
9561 * BSpec MI_DISPLAY_FLIP for IVB:
9562 * "The full packet must be contained within the same cache line."
9564 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9565 * cacheline, if we ever start emitting more commands before
9566 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9567 * then do the cacheline alignment, and finally emit the
9570 ret = intel_ring_cacheline_align(ring);
9574 ret = intel_ring_begin(ring, len);
9578 /* Unmask the flip-done completion message. Note that the bspec says that
9579 * we should do this for both the BCS and RCS, and that we must not unmask
9580 * more than one flip event at any time (or ensure that one flip message
9581 * can be sent by waiting for flip-done prior to queueing new flips).
9582 * Experimentation says that BCS works despite DERRMR masking all
9583 * flip-done completion events and that unmasking all planes at once
9584 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9585 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9587 if (ring->id == RCS) {
9588 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9589 intel_ring_emit(ring, DERRMR);
9590 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9591 DERRMR_PIPEB_PRI_FLIP_DONE |
9592 DERRMR_PIPEC_PRI_FLIP_DONE));
9594 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9595 MI_SRM_LRM_GLOBAL_GTT);
9597 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9598 MI_SRM_LRM_GLOBAL_GTT);
9599 intel_ring_emit(ring, DERRMR);
9600 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9602 intel_ring_emit(ring, 0);
9603 intel_ring_emit(ring, MI_NOOP);
9607 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9608 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9609 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9610 intel_ring_emit(ring, (MI_NOOP));
9612 intel_mark_page_flip_active(intel_crtc);
9613 __intel_ring_advance(ring);
9617 static bool use_mmio_flip(struct intel_engine_cs *ring,
9618 struct drm_i915_gem_object *obj)
9621 * This is not being used for older platforms, because
9622 * non-availability of flip done interrupt forces us to use
9623 * CS flips. Older platforms derive flip done using some clever
9624 * tricks involving the flip_pending status bits and vblank irqs.
9625 * So using MMIO flips there would disrupt this mechanism.
9631 if (INTEL_INFO(ring->dev)->gen < 5)
9634 if (i915.use_mmio_flip < 0)
9636 else if (i915.use_mmio_flip > 0)
9638 else if (i915.enable_execlists)
9641 return ring != i915_gem_request_get_ring(obj->last_read_req);
9644 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9646 struct drm_device *dev = intel_crtc->base.dev;
9647 struct drm_i915_private *dev_priv = dev->dev_private;
9648 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9649 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9650 struct drm_i915_gem_object *obj = intel_fb->obj;
9651 const enum pipe pipe = intel_crtc->pipe;
9654 ctl = I915_READ(PLANE_CTL(pipe, 0));
9655 ctl &= ~PLANE_CTL_TILED_MASK;
9656 if (obj->tiling_mode == I915_TILING_X)
9657 ctl |= PLANE_CTL_TILED_X;
9660 * The stride is either expressed as a multiple of 64 bytes chunks for
9661 * linear buffers or in number of tiles for tiled buffers.
9663 stride = fb->pitches[0] >> 6;
9664 if (obj->tiling_mode == I915_TILING_X)
9665 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9668 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9669 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9671 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9672 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9674 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9675 POSTING_READ(PLANE_SURF(pipe, 0));
9678 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9680 struct drm_device *dev = intel_crtc->base.dev;
9681 struct drm_i915_private *dev_priv = dev->dev_private;
9682 struct intel_framebuffer *intel_fb =
9683 to_intel_framebuffer(intel_crtc->base.primary->fb);
9684 struct drm_i915_gem_object *obj = intel_fb->obj;
9688 reg = DSPCNTR(intel_crtc->plane);
9689 dspcntr = I915_READ(reg);
9691 if (obj->tiling_mode != I915_TILING_NONE)
9692 dspcntr |= DISPPLANE_TILED;
9694 dspcntr &= ~DISPPLANE_TILED;
9696 I915_WRITE(reg, dspcntr);
9698 I915_WRITE(DSPSURF(intel_crtc->plane),
9699 intel_crtc->unpin_work->gtt_offset);
9700 POSTING_READ(DSPSURF(intel_crtc->plane));
9705 * XXX: This is the temporary way to update the plane registers until we get
9706 * around to using the usual plane update functions for MMIO flips
9708 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9710 struct drm_device *dev = intel_crtc->base.dev;
9712 u32 start_vbl_count;
9714 intel_mark_page_flip_active(intel_crtc);
9716 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9718 if (INTEL_INFO(dev)->gen >= 9)
9719 skl_do_mmio_flip(intel_crtc);
9721 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9722 ilk_do_mmio_flip(intel_crtc);
9725 intel_pipe_update_end(intel_crtc, start_vbl_count);
9728 static void intel_mmio_flip_work_func(struct work_struct *work)
9730 struct intel_crtc *crtc =
9731 container_of(work, struct intel_crtc, mmio_flip.work);
9732 struct intel_mmio_flip *mmio_flip;
9734 mmio_flip = &crtc->mmio_flip;
9736 WARN_ON(__i915_wait_request(mmio_flip->req,
9737 crtc->reset_counter,
9738 false, NULL, NULL) != 0);
9740 intel_do_mmio_flip(crtc);
9741 if (mmio_flip->req) {
9742 mutex_lock(&crtc->base.dev->struct_mutex);
9743 i915_gem_request_assign(&mmio_flip->req, NULL);
9744 mutex_unlock(&crtc->base.dev->struct_mutex);
9748 static int intel_queue_mmio_flip(struct drm_device *dev,
9749 struct drm_crtc *crtc,
9750 struct drm_framebuffer *fb,
9751 struct drm_i915_gem_object *obj,
9752 struct intel_engine_cs *ring,
9755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9757 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9758 obj->last_write_req);
9760 schedule_work(&intel_crtc->mmio_flip.work);
9765 static int intel_default_queue_flip(struct drm_device *dev,
9766 struct drm_crtc *crtc,
9767 struct drm_framebuffer *fb,
9768 struct drm_i915_gem_object *obj,
9769 struct intel_engine_cs *ring,
9775 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9776 struct drm_crtc *crtc)
9778 struct drm_i915_private *dev_priv = dev->dev_private;
9779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9780 struct intel_unpin_work *work = intel_crtc->unpin_work;
9783 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9786 if (!work->enable_stall_check)
9789 if (work->flip_ready_vblank == 0) {
9790 if (work->flip_queued_req &&
9791 !i915_gem_request_completed(work->flip_queued_req, true))
9794 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9797 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9800 /* Potential stall - if we see that the flip has happened,
9801 * assume a missed interrupt. */
9802 if (INTEL_INFO(dev)->gen >= 4)
9803 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9805 addr = I915_READ(DSPADDR(intel_crtc->plane));
9807 /* There is a potential issue here with a false positive after a flip
9808 * to the same address. We could address this by checking for a
9809 * non-incrementing frame counter.
9811 return addr == work->gtt_offset;
9814 void intel_check_page_flip(struct drm_device *dev, int pipe)
9816 struct drm_i915_private *dev_priv = dev->dev_private;
9817 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9825 spin_lock(&dev->event_lock);
9826 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9827 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9828 intel_crtc->unpin_work->flip_queued_vblank,
9829 drm_vblank_count(dev, pipe));
9830 page_flip_completed(intel_crtc);
9832 spin_unlock(&dev->event_lock);
9835 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9836 struct drm_framebuffer *fb,
9837 struct drm_pending_vblank_event *event,
9838 uint32_t page_flip_flags)
9840 struct drm_device *dev = crtc->dev;
9841 struct drm_i915_private *dev_priv = dev->dev_private;
9842 struct drm_framebuffer *old_fb = crtc->primary->fb;
9843 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9845 struct drm_plane *primary = crtc->primary;
9846 enum pipe pipe = intel_crtc->pipe;
9847 struct intel_unpin_work *work;
9848 struct intel_engine_cs *ring;
9852 * drm_mode_page_flip_ioctl() should already catch this, but double
9853 * check to be safe. In the future we may enable pageflipping from
9854 * a disabled primary plane.
9856 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9859 /* Can't change pixel format via MI display flips. */
9860 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9864 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9865 * Note that pitch changes could also affect these register.
9867 if (INTEL_INFO(dev)->gen > 3 &&
9868 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9869 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9872 if (i915_terminally_wedged(&dev_priv->gpu_error))
9875 work = kzalloc(sizeof(*work), GFP_KERNEL);
9879 work->event = event;
9881 work->old_fb = old_fb;
9882 INIT_WORK(&work->work, intel_unpin_work_fn);
9884 ret = drm_crtc_vblank_get(crtc);
9888 /* We borrow the event spin lock for protecting unpin_work */
9889 spin_lock_irq(&dev->event_lock);
9890 if (intel_crtc->unpin_work) {
9891 /* Before declaring the flip queue wedged, check if
9892 * the hardware completed the operation behind our backs.
9894 if (__intel_pageflip_stall_check(dev, crtc)) {
9895 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9896 page_flip_completed(intel_crtc);
9898 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9899 spin_unlock_irq(&dev->event_lock);
9901 drm_crtc_vblank_put(crtc);
9906 intel_crtc->unpin_work = work;
9907 spin_unlock_irq(&dev->event_lock);
9909 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9910 flush_workqueue(dev_priv->wq);
9912 ret = i915_mutex_lock_interruptible(dev);
9916 /* Reference the objects for the scheduled work. */
9917 drm_framebuffer_reference(work->old_fb);
9918 drm_gem_object_reference(&obj->base);
9920 crtc->primary->fb = fb;
9921 update_state_fb(crtc->primary);
9923 work->pending_flip_obj = obj;
9925 atomic_inc(&intel_crtc->unpin_work_count);
9926 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9928 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9929 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9931 if (IS_VALLEYVIEW(dev)) {
9932 ring = &dev_priv->ring[BCS];
9933 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9934 /* vlv: DISPLAY_FLIP fails to change tiling */
9936 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9937 ring = &dev_priv->ring[BCS];
9938 } else if (INTEL_INFO(dev)->gen >= 7) {
9939 ring = i915_gem_request_get_ring(obj->last_read_req);
9940 if (ring == NULL || ring->id != RCS)
9941 ring = &dev_priv->ring[BCS];
9943 ring = &dev_priv->ring[RCS];
9946 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9948 goto cleanup_pending;
9951 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9953 if (use_mmio_flip(ring, obj)) {
9954 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9959 i915_gem_request_assign(&work->flip_queued_req,
9960 obj->last_write_req);
9962 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9967 i915_gem_request_assign(&work->flip_queued_req,
9968 intel_ring_get_request(ring));
9971 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
9972 work->enable_stall_check = true;
9974 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9975 INTEL_FRONTBUFFER_PRIMARY(pipe));
9977 intel_fbc_disable(dev);
9978 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9979 mutex_unlock(&dev->struct_mutex);
9981 trace_i915_flip_request(intel_crtc->plane, obj);
9986 intel_unpin_fb_obj(obj);
9988 atomic_dec(&intel_crtc->unpin_work_count);
9989 crtc->primary->fb = old_fb;
9990 update_state_fb(crtc->primary);
9991 drm_framebuffer_unreference(work->old_fb);
9992 drm_gem_object_unreference(&obj->base);
9993 mutex_unlock(&dev->struct_mutex);
9996 spin_lock_irq(&dev->event_lock);
9997 intel_crtc->unpin_work = NULL;
9998 spin_unlock_irq(&dev->event_lock);
10000 drm_crtc_vblank_put(crtc);
10006 ret = intel_plane_restore(primary);
10007 if (ret == 0 && event) {
10008 spin_lock_irq(&dev->event_lock);
10009 drm_send_vblank_event(dev, pipe, event);
10010 spin_unlock_irq(&dev->event_lock);
10016 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10017 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10018 .load_lut = intel_crtc_load_lut,
10019 .atomic_begin = intel_begin_crtc_commit,
10020 .atomic_flush = intel_finish_crtc_commit,
10024 * intel_modeset_update_staged_output_state
10026 * Updates the staged output configuration state, e.g. after we've read out the
10027 * current hw state.
10029 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10031 struct intel_crtc *crtc;
10032 struct intel_encoder *encoder;
10033 struct intel_connector *connector;
10035 for_each_intel_connector(dev, connector) {
10036 connector->new_encoder =
10037 to_intel_encoder(connector->base.encoder);
10040 for_each_intel_encoder(dev, encoder) {
10041 encoder->new_crtc =
10042 to_intel_crtc(encoder->base.crtc);
10045 for_each_intel_crtc(dev, crtc) {
10046 crtc->new_enabled = crtc->base.state->enable;
10048 if (crtc->new_enabled)
10049 crtc->new_config = crtc->config;
10051 crtc->new_config = NULL;
10056 * intel_modeset_commit_output_state
10058 * This function copies the stage display pipe configuration to the real one.
10060 static void intel_modeset_commit_output_state(struct drm_device *dev)
10062 struct intel_crtc *crtc;
10063 struct intel_encoder *encoder;
10064 struct intel_connector *connector;
10066 for_each_intel_connector(dev, connector) {
10067 connector->base.encoder = &connector->new_encoder->base;
10070 for_each_intel_encoder(dev, encoder) {
10071 encoder->base.crtc = &encoder->new_crtc->base;
10074 for_each_intel_crtc(dev, crtc) {
10075 crtc->base.state->enable = crtc->new_enabled;
10076 crtc->base.enabled = crtc->new_enabled;
10081 connected_sink_compute_bpp(struct intel_connector *connector,
10082 struct intel_crtc_state *pipe_config)
10084 int bpp = pipe_config->pipe_bpp;
10086 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10087 connector->base.base.id,
10088 connector->base.name);
10090 /* Don't use an invalid EDID bpc value */
10091 if (connector->base.display_info.bpc &&
10092 connector->base.display_info.bpc * 3 < bpp) {
10093 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10094 bpp, connector->base.display_info.bpc*3);
10095 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10098 /* Clamp bpp to 8 on screens without EDID 1.4 */
10099 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10100 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10102 pipe_config->pipe_bpp = 24;
10107 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10108 struct drm_framebuffer *fb,
10109 struct intel_crtc_state *pipe_config)
10111 struct drm_device *dev = crtc->base.dev;
10112 struct intel_connector *connector;
10115 switch (fb->pixel_format) {
10116 case DRM_FORMAT_C8:
10117 bpp = 8*3; /* since we go through a colormap */
10119 case DRM_FORMAT_XRGB1555:
10120 case DRM_FORMAT_ARGB1555:
10121 /* checked in intel_framebuffer_init already */
10122 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10124 case DRM_FORMAT_RGB565:
10125 bpp = 6*3; /* min is 18bpp */
10127 case DRM_FORMAT_XBGR8888:
10128 case DRM_FORMAT_ABGR8888:
10129 /* checked in intel_framebuffer_init already */
10130 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10132 case DRM_FORMAT_XRGB8888:
10133 case DRM_FORMAT_ARGB8888:
10136 case DRM_FORMAT_XRGB2101010:
10137 case DRM_FORMAT_ARGB2101010:
10138 case DRM_FORMAT_XBGR2101010:
10139 case DRM_FORMAT_ABGR2101010:
10140 /* checked in intel_framebuffer_init already */
10141 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10145 /* TODO: gen4+ supports 16 bpc floating point, too. */
10147 DRM_DEBUG_KMS("unsupported depth\n");
10151 pipe_config->pipe_bpp = bpp;
10153 /* Clamp display bpp to EDID value */
10154 for_each_intel_connector(dev, connector) {
10155 if (!connector->new_encoder ||
10156 connector->new_encoder->new_crtc != crtc)
10159 connected_sink_compute_bpp(connector, pipe_config);
10165 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10167 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10168 "type: 0x%x flags: 0x%x\n",
10170 mode->crtc_hdisplay, mode->crtc_hsync_start,
10171 mode->crtc_hsync_end, mode->crtc_htotal,
10172 mode->crtc_vdisplay, mode->crtc_vsync_start,
10173 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10176 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10177 struct intel_crtc_state *pipe_config,
10178 const char *context)
10180 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10181 context, pipe_name(crtc->pipe));
10183 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10184 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10185 pipe_config->pipe_bpp, pipe_config->dither);
10186 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10187 pipe_config->has_pch_encoder,
10188 pipe_config->fdi_lanes,
10189 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10190 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10191 pipe_config->fdi_m_n.tu);
10192 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10193 pipe_config->has_dp_encoder,
10194 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10195 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10196 pipe_config->dp_m_n.tu);
10198 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10199 pipe_config->has_dp_encoder,
10200 pipe_config->dp_m2_n2.gmch_m,
10201 pipe_config->dp_m2_n2.gmch_n,
10202 pipe_config->dp_m2_n2.link_m,
10203 pipe_config->dp_m2_n2.link_n,
10204 pipe_config->dp_m2_n2.tu);
10206 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10207 pipe_config->has_audio,
10208 pipe_config->has_infoframe);
10210 DRM_DEBUG_KMS("requested mode:\n");
10211 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10212 DRM_DEBUG_KMS("adjusted mode:\n");
10213 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10214 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10215 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10216 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10217 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10218 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10219 pipe_config->gmch_pfit.control,
10220 pipe_config->gmch_pfit.pgm_ratios,
10221 pipe_config->gmch_pfit.lvds_border_bits);
10222 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10223 pipe_config->pch_pfit.pos,
10224 pipe_config->pch_pfit.size,
10225 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10226 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10227 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10230 static bool encoders_cloneable(const struct intel_encoder *a,
10231 const struct intel_encoder *b)
10233 /* masks could be asymmetric, so check both ways */
10234 return a == b || (a->cloneable & (1 << b->type) &&
10235 b->cloneable & (1 << a->type));
10238 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10239 struct intel_encoder *encoder)
10241 struct drm_device *dev = crtc->base.dev;
10242 struct intel_encoder *source_encoder;
10244 for_each_intel_encoder(dev, source_encoder) {
10245 if (source_encoder->new_crtc != crtc)
10248 if (!encoders_cloneable(encoder, source_encoder))
10255 static bool check_encoder_cloning(struct intel_crtc *crtc)
10257 struct drm_device *dev = crtc->base.dev;
10258 struct intel_encoder *encoder;
10260 for_each_intel_encoder(dev, encoder) {
10261 if (encoder->new_crtc != crtc)
10264 if (!check_single_encoder_cloning(crtc, encoder))
10271 static bool check_digital_port_conflicts(struct drm_device *dev)
10273 struct intel_connector *connector;
10274 unsigned int used_ports = 0;
10277 * Walk the connector list instead of the encoder
10278 * list to detect the problem on ddi platforms
10279 * where there's just one encoder per digital port.
10281 for_each_intel_connector(dev, connector) {
10282 struct intel_encoder *encoder = connector->new_encoder;
10287 WARN_ON(!encoder->new_crtc);
10289 switch (encoder->type) {
10290 unsigned int port_mask;
10291 case INTEL_OUTPUT_UNKNOWN:
10292 if (WARN_ON(!HAS_DDI(dev)))
10294 case INTEL_OUTPUT_DISPLAYPORT:
10295 case INTEL_OUTPUT_HDMI:
10296 case INTEL_OUTPUT_EDP:
10297 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10299 /* the same port mustn't appear more than once */
10300 if (used_ports & port_mask)
10303 used_ports |= port_mask;
10312 static struct intel_crtc_state *
10313 intel_modeset_pipe_config(struct drm_crtc *crtc,
10314 struct drm_framebuffer *fb,
10315 struct drm_display_mode *mode)
10317 struct drm_device *dev = crtc->dev;
10318 struct intel_encoder *encoder;
10319 struct intel_crtc_state *pipe_config;
10320 int plane_bpp, ret = -EINVAL;
10323 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10324 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10325 return ERR_PTR(-EINVAL);
10328 if (!check_digital_port_conflicts(dev)) {
10329 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10330 return ERR_PTR(-EINVAL);
10333 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10335 return ERR_PTR(-ENOMEM);
10337 pipe_config->base.crtc = crtc;
10338 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10339 drm_mode_copy(&pipe_config->base.mode, mode);
10341 pipe_config->cpu_transcoder =
10342 (enum transcoder) to_intel_crtc(crtc)->pipe;
10343 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10346 * Sanitize sync polarity flags based on requested ones. If neither
10347 * positive or negative polarity is requested, treat this as meaning
10348 * negative polarity.
10350 if (!(pipe_config->base.adjusted_mode.flags &
10351 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10352 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10354 if (!(pipe_config->base.adjusted_mode.flags &
10355 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10356 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10358 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10359 * plane pixel format and any sink constraints into account. Returns the
10360 * source plane bpp so that dithering can be selected on mismatches
10361 * after encoders and crtc also have had their say. */
10362 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10368 * Determine the real pipe dimensions. Note that stereo modes can
10369 * increase the actual pipe size due to the frame doubling and
10370 * insertion of additional space for blanks between the frame. This
10371 * is stored in the crtc timings. We use the requested mode to do this
10372 * computation to clearly distinguish it from the adjusted mode, which
10373 * can be changed by the connectors in the below retry loop.
10375 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10376 &pipe_config->pipe_src_w,
10377 &pipe_config->pipe_src_h);
10380 /* Ensure the port clock defaults are reset when retrying. */
10381 pipe_config->port_clock = 0;
10382 pipe_config->pixel_multiplier = 1;
10384 /* Fill in default crtc timings, allow encoders to overwrite them. */
10385 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10386 CRTC_STEREO_DOUBLE);
10388 /* Pass our mode to the connectors and the CRTC to give them a chance to
10389 * adjust it according to limitations or connector properties, and also
10390 * a chance to reject the mode entirely.
10392 for_each_intel_encoder(dev, encoder) {
10394 if (&encoder->new_crtc->base != crtc)
10397 if (!(encoder->compute_config(encoder, pipe_config))) {
10398 DRM_DEBUG_KMS("Encoder config failure\n");
10403 /* Set default port clock if not overwritten by the encoder. Needs to be
10404 * done afterwards in case the encoder adjusts the mode. */
10405 if (!pipe_config->port_clock)
10406 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10407 * pipe_config->pixel_multiplier;
10409 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10411 DRM_DEBUG_KMS("CRTC fixup failed\n");
10415 if (ret == RETRY) {
10416 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10421 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10423 goto encoder_retry;
10426 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10427 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10428 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10430 return pipe_config;
10432 kfree(pipe_config);
10433 return ERR_PTR(ret);
10436 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10437 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10439 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10440 unsigned *prepare_pipes, unsigned *disable_pipes)
10442 struct intel_crtc *intel_crtc;
10443 struct drm_device *dev = crtc->dev;
10444 struct intel_encoder *encoder;
10445 struct intel_connector *connector;
10446 struct drm_crtc *tmp_crtc;
10448 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10450 /* Check which crtcs have changed outputs connected to them, these need
10451 * to be part of the prepare_pipes mask. We don't (yet) support global
10452 * modeset across multiple crtcs, so modeset_pipes will only have one
10453 * bit set at most. */
10454 for_each_intel_connector(dev, connector) {
10455 if (connector->base.encoder == &connector->new_encoder->base)
10458 if (connector->base.encoder) {
10459 tmp_crtc = connector->base.encoder->crtc;
10461 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10464 if (connector->new_encoder)
10466 1 << connector->new_encoder->new_crtc->pipe;
10469 for_each_intel_encoder(dev, encoder) {
10470 if (encoder->base.crtc == &encoder->new_crtc->base)
10473 if (encoder->base.crtc) {
10474 tmp_crtc = encoder->base.crtc;
10476 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10479 if (encoder->new_crtc)
10480 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10483 /* Check for pipes that will be enabled/disabled ... */
10484 for_each_intel_crtc(dev, intel_crtc) {
10485 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10488 if (!intel_crtc->new_enabled)
10489 *disable_pipes |= 1 << intel_crtc->pipe;
10491 *prepare_pipes |= 1 << intel_crtc->pipe;
10495 /* set_mode is also used to update properties on life display pipes. */
10496 intel_crtc = to_intel_crtc(crtc);
10497 if (intel_crtc->new_enabled)
10498 *prepare_pipes |= 1 << intel_crtc->pipe;
10501 * For simplicity do a full modeset on any pipe where the output routing
10502 * changed. We could be more clever, but that would require us to be
10503 * more careful with calling the relevant encoder->mode_set functions.
10505 if (*prepare_pipes)
10506 *modeset_pipes = *prepare_pipes;
10508 /* ... and mask these out. */
10509 *modeset_pipes &= ~(*disable_pipes);
10510 *prepare_pipes &= ~(*disable_pipes);
10513 * HACK: We don't (yet) fully support global modesets. intel_set_config
10514 * obies this rule, but the modeset restore mode of
10515 * intel_modeset_setup_hw_state does not.
10517 *modeset_pipes &= 1 << intel_crtc->pipe;
10518 *prepare_pipes &= 1 << intel_crtc->pipe;
10520 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10521 *modeset_pipes, *prepare_pipes, *disable_pipes);
10524 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10526 struct drm_encoder *encoder;
10527 struct drm_device *dev = crtc->dev;
10529 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10530 if (encoder->crtc == crtc)
10537 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10539 struct drm_i915_private *dev_priv = dev->dev_private;
10540 struct intel_encoder *intel_encoder;
10541 struct intel_crtc *intel_crtc;
10542 struct drm_connector *connector;
10544 intel_shared_dpll_commit(dev_priv);
10546 for_each_intel_encoder(dev, intel_encoder) {
10547 if (!intel_encoder->base.crtc)
10550 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10552 if (prepare_pipes & (1 << intel_crtc->pipe))
10553 intel_encoder->connectors_active = false;
10556 intel_modeset_commit_output_state(dev);
10558 /* Double check state. */
10559 for_each_intel_crtc(dev, intel_crtc) {
10560 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10561 WARN_ON(intel_crtc->new_config &&
10562 intel_crtc->new_config != intel_crtc->config);
10563 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10566 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10567 if (!connector->encoder || !connector->encoder->crtc)
10570 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10572 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10573 struct drm_property *dpms_property =
10574 dev->mode_config.dpms_property;
10576 connector->dpms = DRM_MODE_DPMS_ON;
10577 drm_object_property_set_value(&connector->base,
10581 intel_encoder = to_intel_encoder(connector->encoder);
10582 intel_encoder->connectors_active = true;
10588 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10592 if (clock1 == clock2)
10595 if (!clock1 || !clock2)
10598 diff = abs(clock1 - clock2);
10600 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10606 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10607 list_for_each_entry((intel_crtc), \
10608 &(dev)->mode_config.crtc_list, \
10610 if (mask & (1 <<(intel_crtc)->pipe))
10613 intel_pipe_config_compare(struct drm_device *dev,
10614 struct intel_crtc_state *current_config,
10615 struct intel_crtc_state *pipe_config)
10617 #define PIPE_CONF_CHECK_X(name) \
10618 if (current_config->name != pipe_config->name) { \
10619 DRM_ERROR("mismatch in " #name " " \
10620 "(expected 0x%08x, found 0x%08x)\n", \
10621 current_config->name, \
10622 pipe_config->name); \
10626 #define PIPE_CONF_CHECK_I(name) \
10627 if (current_config->name != pipe_config->name) { \
10628 DRM_ERROR("mismatch in " #name " " \
10629 "(expected %i, found %i)\n", \
10630 current_config->name, \
10631 pipe_config->name); \
10635 /* This is required for BDW+ where there is only one set of registers for
10636 * switching between high and low RR.
10637 * This macro can be used whenever a comparison has to be made between one
10638 * hw state and multiple sw state variables.
10640 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10641 if ((current_config->name != pipe_config->name) && \
10642 (current_config->alt_name != pipe_config->name)) { \
10643 DRM_ERROR("mismatch in " #name " " \
10644 "(expected %i or %i, found %i)\n", \
10645 current_config->name, \
10646 current_config->alt_name, \
10647 pipe_config->name); \
10651 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10652 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10653 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10654 "(expected %i, found %i)\n", \
10655 current_config->name & (mask), \
10656 pipe_config->name & (mask)); \
10660 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10661 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10662 DRM_ERROR("mismatch in " #name " " \
10663 "(expected %i, found %i)\n", \
10664 current_config->name, \
10665 pipe_config->name); \
10669 #define PIPE_CONF_QUIRK(quirk) \
10670 ((current_config->quirks | pipe_config->quirks) & (quirk))
10672 PIPE_CONF_CHECK_I(cpu_transcoder);
10674 PIPE_CONF_CHECK_I(has_pch_encoder);
10675 PIPE_CONF_CHECK_I(fdi_lanes);
10676 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10677 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10678 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10679 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10680 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10682 PIPE_CONF_CHECK_I(has_dp_encoder);
10684 if (INTEL_INFO(dev)->gen < 8) {
10685 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10686 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10687 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10688 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10689 PIPE_CONF_CHECK_I(dp_m_n.tu);
10691 if (current_config->has_drrs) {
10692 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10693 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10694 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10695 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10696 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10699 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10700 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10701 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10702 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10703 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10706 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10707 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10708 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10709 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10710 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10711 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10713 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10714 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10715 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10716 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10717 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10718 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10720 PIPE_CONF_CHECK_I(pixel_multiplier);
10721 PIPE_CONF_CHECK_I(has_hdmi_sink);
10722 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10723 IS_VALLEYVIEW(dev))
10724 PIPE_CONF_CHECK_I(limited_color_range);
10725 PIPE_CONF_CHECK_I(has_infoframe);
10727 PIPE_CONF_CHECK_I(has_audio);
10729 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10730 DRM_MODE_FLAG_INTERLACE);
10732 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10733 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10734 DRM_MODE_FLAG_PHSYNC);
10735 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10736 DRM_MODE_FLAG_NHSYNC);
10737 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10738 DRM_MODE_FLAG_PVSYNC);
10739 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10740 DRM_MODE_FLAG_NVSYNC);
10743 PIPE_CONF_CHECK_I(pipe_src_w);
10744 PIPE_CONF_CHECK_I(pipe_src_h);
10747 * FIXME: BIOS likes to set up a cloned config with lvds+external
10748 * screen. Since we don't yet re-compute the pipe config when moving
10749 * just the lvds port away to another pipe the sw tracking won't match.
10751 * Proper atomic modesets with recomputed global state will fix this.
10752 * Until then just don't check gmch state for inherited modes.
10754 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10755 PIPE_CONF_CHECK_I(gmch_pfit.control);
10756 /* pfit ratios are autocomputed by the hw on gen4+ */
10757 if (INTEL_INFO(dev)->gen < 4)
10758 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10759 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10762 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10763 if (current_config->pch_pfit.enabled) {
10764 PIPE_CONF_CHECK_I(pch_pfit.pos);
10765 PIPE_CONF_CHECK_I(pch_pfit.size);
10768 /* BDW+ don't expose a synchronous way to read the state */
10769 if (IS_HASWELL(dev))
10770 PIPE_CONF_CHECK_I(ips_enabled);
10772 PIPE_CONF_CHECK_I(double_wide);
10774 PIPE_CONF_CHECK_X(ddi_pll_sel);
10776 PIPE_CONF_CHECK_I(shared_dpll);
10777 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10778 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10779 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10780 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10781 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10782 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10783 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10784 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10786 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10787 PIPE_CONF_CHECK_I(pipe_bpp);
10789 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10790 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10792 #undef PIPE_CONF_CHECK_X
10793 #undef PIPE_CONF_CHECK_I
10794 #undef PIPE_CONF_CHECK_I_ALT
10795 #undef PIPE_CONF_CHECK_FLAGS
10796 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10797 #undef PIPE_CONF_QUIRK
10802 static void check_wm_state(struct drm_device *dev)
10804 struct drm_i915_private *dev_priv = dev->dev_private;
10805 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10806 struct intel_crtc *intel_crtc;
10809 if (INTEL_INFO(dev)->gen < 9)
10812 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10813 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10815 for_each_intel_crtc(dev, intel_crtc) {
10816 struct skl_ddb_entry *hw_entry, *sw_entry;
10817 const enum pipe pipe = intel_crtc->pipe;
10819 if (!intel_crtc->active)
10823 for_each_plane(dev_priv, pipe, plane) {
10824 hw_entry = &hw_ddb.plane[pipe][plane];
10825 sw_entry = &sw_ddb->plane[pipe][plane];
10827 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10830 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10831 "(expected (%u,%u), found (%u,%u))\n",
10832 pipe_name(pipe), plane + 1,
10833 sw_entry->start, sw_entry->end,
10834 hw_entry->start, hw_entry->end);
10838 hw_entry = &hw_ddb.cursor[pipe];
10839 sw_entry = &sw_ddb->cursor[pipe];
10841 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10844 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10845 "(expected (%u,%u), found (%u,%u))\n",
10847 sw_entry->start, sw_entry->end,
10848 hw_entry->start, hw_entry->end);
10853 check_connector_state(struct drm_device *dev)
10855 struct intel_connector *connector;
10857 for_each_intel_connector(dev, connector) {
10858 /* This also checks the encoder/connector hw state with the
10859 * ->get_hw_state callbacks. */
10860 intel_connector_check_state(connector);
10862 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10863 "connector's staged encoder doesn't match current encoder\n");
10868 check_encoder_state(struct drm_device *dev)
10870 struct intel_encoder *encoder;
10871 struct intel_connector *connector;
10873 for_each_intel_encoder(dev, encoder) {
10874 bool enabled = false;
10875 bool active = false;
10876 enum pipe pipe, tracked_pipe;
10878 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10879 encoder->base.base.id,
10880 encoder->base.name);
10882 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10883 "encoder's stage crtc doesn't match current crtc\n");
10884 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10885 "encoder's active_connectors set, but no crtc\n");
10887 for_each_intel_connector(dev, connector) {
10888 if (connector->base.encoder != &encoder->base)
10891 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10895 * for MST connectors if we unplug the connector is gone
10896 * away but the encoder is still connected to a crtc
10897 * until a modeset happens in response to the hotplug.
10899 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10902 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10903 "encoder's enabled state mismatch "
10904 "(expected %i, found %i)\n",
10905 !!encoder->base.crtc, enabled);
10906 I915_STATE_WARN(active && !encoder->base.crtc,
10907 "active encoder with no crtc\n");
10909 I915_STATE_WARN(encoder->connectors_active != active,
10910 "encoder's computed active state doesn't match tracked active state "
10911 "(expected %i, found %i)\n", active, encoder->connectors_active);
10913 active = encoder->get_hw_state(encoder, &pipe);
10914 I915_STATE_WARN(active != encoder->connectors_active,
10915 "encoder's hw state doesn't match sw tracking "
10916 "(expected %i, found %i)\n",
10917 encoder->connectors_active, active);
10919 if (!encoder->base.crtc)
10922 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10923 I915_STATE_WARN(active && pipe != tracked_pipe,
10924 "active encoder's pipe doesn't match"
10925 "(expected %i, found %i)\n",
10926 tracked_pipe, pipe);
10932 check_crtc_state(struct drm_device *dev)
10934 struct drm_i915_private *dev_priv = dev->dev_private;
10935 struct intel_crtc *crtc;
10936 struct intel_encoder *encoder;
10937 struct intel_crtc_state pipe_config;
10939 for_each_intel_crtc(dev, crtc) {
10940 bool enabled = false;
10941 bool active = false;
10943 memset(&pipe_config, 0, sizeof(pipe_config));
10945 DRM_DEBUG_KMS("[CRTC:%d]\n",
10946 crtc->base.base.id);
10948 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
10949 "active crtc, but not enabled in sw tracking\n");
10951 for_each_intel_encoder(dev, encoder) {
10952 if (encoder->base.crtc != &crtc->base)
10955 if (encoder->connectors_active)
10959 I915_STATE_WARN(active != crtc->active,
10960 "crtc's computed active state doesn't match tracked active state "
10961 "(expected %i, found %i)\n", active, crtc->active);
10962 I915_STATE_WARN(enabled != crtc->base.state->enable,
10963 "crtc's computed enabled state doesn't match tracked enabled state "
10964 "(expected %i, found %i)\n", enabled,
10965 crtc->base.state->enable);
10967 active = dev_priv->display.get_pipe_config(crtc,
10970 /* hw state is inconsistent with the pipe quirk */
10971 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10972 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10973 active = crtc->active;
10975 for_each_intel_encoder(dev, encoder) {
10977 if (encoder->base.crtc != &crtc->base)
10979 if (encoder->get_hw_state(encoder, &pipe))
10980 encoder->get_config(encoder, &pipe_config);
10983 I915_STATE_WARN(crtc->active != active,
10984 "crtc active state doesn't match with hw state "
10985 "(expected %i, found %i)\n", crtc->active, active);
10988 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10989 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10990 intel_dump_pipe_config(crtc, &pipe_config,
10992 intel_dump_pipe_config(crtc, crtc->config,
10999 check_shared_dpll_state(struct drm_device *dev)
11001 struct drm_i915_private *dev_priv = dev->dev_private;
11002 struct intel_crtc *crtc;
11003 struct intel_dpll_hw_state dpll_hw_state;
11006 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11007 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11008 int enabled_crtcs = 0, active_crtcs = 0;
11011 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11013 DRM_DEBUG_KMS("%s\n", pll->name);
11015 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11017 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11018 "more active pll users than references: %i vs %i\n",
11019 pll->active, hweight32(pll->config.crtc_mask));
11020 I915_STATE_WARN(pll->active && !pll->on,
11021 "pll in active use but not on in sw tracking\n");
11022 I915_STATE_WARN(pll->on && !pll->active,
11023 "pll in on but not on in use in sw tracking\n");
11024 I915_STATE_WARN(pll->on != active,
11025 "pll on state mismatch (expected %i, found %i)\n",
11028 for_each_intel_crtc(dev, crtc) {
11029 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11031 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11034 I915_STATE_WARN(pll->active != active_crtcs,
11035 "pll active crtcs mismatch (expected %i, found %i)\n",
11036 pll->active, active_crtcs);
11037 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11038 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11039 hweight32(pll->config.crtc_mask), enabled_crtcs);
11041 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11042 sizeof(dpll_hw_state)),
11043 "pll hw state mismatch\n");
11048 intel_modeset_check_state(struct drm_device *dev)
11050 check_wm_state(dev);
11051 check_connector_state(dev);
11052 check_encoder_state(dev);
11053 check_crtc_state(dev);
11054 check_shared_dpll_state(dev);
11057 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11061 * FDI already provided one idea for the dotclock.
11062 * Yell if the encoder disagrees.
11064 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11065 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11066 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11069 static void update_scanline_offset(struct intel_crtc *crtc)
11071 struct drm_device *dev = crtc->base.dev;
11074 * The scanline counter increments at the leading edge of hsync.
11076 * On most platforms it starts counting from vtotal-1 on the
11077 * first active line. That means the scanline counter value is
11078 * always one less than what we would expect. Ie. just after
11079 * start of vblank, which also occurs at start of hsync (on the
11080 * last active line), the scanline counter will read vblank_start-1.
11082 * On gen2 the scanline counter starts counting from 1 instead
11083 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11084 * to keep the value positive), instead of adding one.
11086 * On HSW+ the behaviour of the scanline counter depends on the output
11087 * type. For DP ports it behaves like most other platforms, but on HDMI
11088 * there's an extra 1 line difference. So we need to add two instead of
11089 * one to the value.
11091 if (IS_GEN2(dev)) {
11092 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11095 vtotal = mode->crtc_vtotal;
11096 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11099 crtc->scanline_offset = vtotal - 1;
11100 } else if (HAS_DDI(dev) &&
11101 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11102 crtc->scanline_offset = 2;
11104 crtc->scanline_offset = 1;
11107 static struct intel_crtc_state *
11108 intel_modeset_compute_config(struct drm_crtc *crtc,
11109 struct drm_display_mode *mode,
11110 struct drm_framebuffer *fb,
11111 unsigned *modeset_pipes,
11112 unsigned *prepare_pipes,
11113 unsigned *disable_pipes)
11115 struct intel_crtc_state *pipe_config = NULL;
11117 intel_modeset_affected_pipes(crtc, modeset_pipes,
11118 prepare_pipes, disable_pipes);
11120 if ((*modeset_pipes) == 0)
11124 * Note this needs changes when we start tracking multiple modes
11125 * and crtcs. At that point we'll need to compute the whole config
11126 * (i.e. one pipe_config for each crtc) rather than just the one
11129 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11130 if (IS_ERR(pipe_config)) {
11133 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11137 return pipe_config;
11140 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11141 unsigned modeset_pipes,
11142 unsigned disable_pipes)
11144 struct drm_i915_private *dev_priv = to_i915(dev);
11145 unsigned clear_pipes = modeset_pipes | disable_pipes;
11146 struct intel_crtc *intel_crtc;
11149 if (!dev_priv->display.crtc_compute_clock)
11152 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11156 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11157 struct intel_crtc_state *state = intel_crtc->new_config;
11158 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11161 intel_shared_dpll_abort_config(dev_priv);
11170 static int __intel_set_mode(struct drm_crtc *crtc,
11171 struct drm_display_mode *mode,
11172 int x, int y, struct drm_framebuffer *fb,
11173 struct intel_crtc_state *pipe_config,
11174 unsigned modeset_pipes,
11175 unsigned prepare_pipes,
11176 unsigned disable_pipes)
11178 struct drm_device *dev = crtc->dev;
11179 struct drm_i915_private *dev_priv = dev->dev_private;
11180 struct drm_display_mode *saved_mode;
11181 struct intel_crtc *intel_crtc;
11184 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11188 *saved_mode = crtc->mode;
11191 to_intel_crtc(crtc)->new_config = pipe_config;
11194 * See if the config requires any additional preparation, e.g.
11195 * to adjust global state with pipes off. We need to do this
11196 * here so we can get the modeset_pipe updated config for the new
11197 * mode set on this crtc. For other crtcs we need to use the
11198 * adjusted_mode bits in the crtc directly.
11200 if (IS_VALLEYVIEW(dev)) {
11201 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11203 /* may have added more to prepare_pipes than we should */
11204 prepare_pipes &= ~disable_pipes;
11207 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11211 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11212 intel_crtc_disable(&intel_crtc->base);
11214 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11215 if (intel_crtc->base.state->enable)
11216 dev_priv->display.crtc_disable(&intel_crtc->base);
11219 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11220 * to set it here already despite that we pass it down the callchain.
11222 * Note we'll need to fix this up when we start tracking multiple
11223 * pipes; here we assume a single modeset_pipe and only track the
11224 * single crtc and mode.
11226 if (modeset_pipes) {
11227 crtc->mode = *mode;
11228 /* mode_set/enable/disable functions rely on a correct pipe
11230 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11233 * Calculate and store various constants which
11234 * are later needed by vblank and swap-completion
11235 * timestamping. They are derived from true hwmode.
11237 drm_calc_timestamping_constants(crtc,
11238 &pipe_config->base.adjusted_mode);
11241 /* Only after disabling all output pipelines that will be changed can we
11242 * update the the output configuration. */
11243 intel_modeset_update_state(dev, prepare_pipes);
11245 modeset_update_crtc_power_domains(dev);
11247 /* Set up the DPLL and any encoders state that needs to adjust or depend
11250 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11251 struct drm_plane *primary = intel_crtc->base.primary;
11252 int vdisplay, hdisplay;
11254 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11255 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11257 hdisplay, vdisplay,
11259 hdisplay << 16, vdisplay << 16);
11262 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11263 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11264 update_scanline_offset(intel_crtc);
11266 dev_priv->display.crtc_enable(&intel_crtc->base);
11269 /* FIXME: add subpixel order */
11271 if (ret && crtc->state->enable)
11272 crtc->mode = *saved_mode;
11278 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11279 struct drm_display_mode *mode,
11280 int x, int y, struct drm_framebuffer *fb,
11281 struct intel_crtc_state *pipe_config,
11282 unsigned modeset_pipes,
11283 unsigned prepare_pipes,
11284 unsigned disable_pipes)
11288 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11289 prepare_pipes, disable_pipes);
11292 intel_modeset_check_state(crtc->dev);
11297 static int intel_set_mode(struct drm_crtc *crtc,
11298 struct drm_display_mode *mode,
11299 int x, int y, struct drm_framebuffer *fb)
11301 struct intel_crtc_state *pipe_config;
11302 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11304 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11309 if (IS_ERR(pipe_config))
11310 return PTR_ERR(pipe_config);
11312 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11313 modeset_pipes, prepare_pipes,
11317 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11319 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11322 #undef for_each_intel_crtc_masked
11324 static void intel_set_config_free(struct intel_set_config *config)
11329 kfree(config->save_connector_encoders);
11330 kfree(config->save_encoder_crtcs);
11331 kfree(config->save_crtc_enabled);
11335 static int intel_set_config_save_state(struct drm_device *dev,
11336 struct intel_set_config *config)
11338 struct drm_crtc *crtc;
11339 struct drm_encoder *encoder;
11340 struct drm_connector *connector;
11343 config->save_crtc_enabled =
11344 kcalloc(dev->mode_config.num_crtc,
11345 sizeof(bool), GFP_KERNEL);
11346 if (!config->save_crtc_enabled)
11349 config->save_encoder_crtcs =
11350 kcalloc(dev->mode_config.num_encoder,
11351 sizeof(struct drm_crtc *), GFP_KERNEL);
11352 if (!config->save_encoder_crtcs)
11355 config->save_connector_encoders =
11356 kcalloc(dev->mode_config.num_connector,
11357 sizeof(struct drm_encoder *), GFP_KERNEL);
11358 if (!config->save_connector_encoders)
11361 /* Copy data. Note that driver private data is not affected.
11362 * Should anything bad happen only the expected state is
11363 * restored, not the drivers personal bookkeeping.
11366 for_each_crtc(dev, crtc) {
11367 config->save_crtc_enabled[count++] = crtc->state->enable;
11371 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11372 config->save_encoder_crtcs[count++] = encoder->crtc;
11376 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11377 config->save_connector_encoders[count++] = connector->encoder;
11383 static void intel_set_config_restore_state(struct drm_device *dev,
11384 struct intel_set_config *config)
11386 struct intel_crtc *crtc;
11387 struct intel_encoder *encoder;
11388 struct intel_connector *connector;
11392 for_each_intel_crtc(dev, crtc) {
11393 crtc->new_enabled = config->save_crtc_enabled[count++];
11395 if (crtc->new_enabled)
11396 crtc->new_config = crtc->config;
11398 crtc->new_config = NULL;
11402 for_each_intel_encoder(dev, encoder) {
11403 encoder->new_crtc =
11404 to_intel_crtc(config->save_encoder_crtcs[count++]);
11408 for_each_intel_connector(dev, connector) {
11409 connector->new_encoder =
11410 to_intel_encoder(config->save_connector_encoders[count++]);
11415 is_crtc_connector_off(struct drm_mode_set *set)
11419 if (set->num_connectors == 0)
11422 if (WARN_ON(set->connectors == NULL))
11425 for (i = 0; i < set->num_connectors; i++)
11426 if (set->connectors[i]->encoder &&
11427 set->connectors[i]->encoder->crtc == set->crtc &&
11428 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11435 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11436 struct intel_set_config *config)
11439 /* We should be able to check here if the fb has the same properties
11440 * and then just flip_or_move it */
11441 if (is_crtc_connector_off(set)) {
11442 config->mode_changed = true;
11443 } else if (set->crtc->primary->fb != set->fb) {
11445 * If we have no fb, we can only flip as long as the crtc is
11446 * active, otherwise we need a full mode set. The crtc may
11447 * be active if we've only disabled the primary plane, or
11448 * in fastboot situations.
11450 if (set->crtc->primary->fb == NULL) {
11451 struct intel_crtc *intel_crtc =
11452 to_intel_crtc(set->crtc);
11454 if (intel_crtc->active) {
11455 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11456 config->fb_changed = true;
11458 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11459 config->mode_changed = true;
11461 } else if (set->fb == NULL) {
11462 config->mode_changed = true;
11463 } else if (set->fb->pixel_format !=
11464 set->crtc->primary->fb->pixel_format) {
11465 config->mode_changed = true;
11467 config->fb_changed = true;
11471 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11472 config->fb_changed = true;
11474 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11475 DRM_DEBUG_KMS("modes are different, full mode set\n");
11476 drm_mode_debug_printmodeline(&set->crtc->mode);
11477 drm_mode_debug_printmodeline(set->mode);
11478 config->mode_changed = true;
11481 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11482 set->crtc->base.id, config->mode_changed, config->fb_changed);
11486 intel_modeset_stage_output_state(struct drm_device *dev,
11487 struct drm_mode_set *set,
11488 struct intel_set_config *config)
11490 struct intel_connector *connector;
11491 struct intel_encoder *encoder;
11492 struct intel_crtc *crtc;
11495 /* The upper layers ensure that we either disable a crtc or have a list
11496 * of connectors. For paranoia, double-check this. */
11497 WARN_ON(!set->fb && (set->num_connectors != 0));
11498 WARN_ON(set->fb && (set->num_connectors == 0));
11500 for_each_intel_connector(dev, connector) {
11501 /* Otherwise traverse passed in connector list and get encoders
11503 for (ro = 0; ro < set->num_connectors; ro++) {
11504 if (set->connectors[ro] == &connector->base) {
11505 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11510 /* If we disable the crtc, disable all its connectors. Also, if
11511 * the connector is on the changing crtc but not on the new
11512 * connector list, disable it. */
11513 if ((!set->fb || ro == set->num_connectors) &&
11514 connector->base.encoder &&
11515 connector->base.encoder->crtc == set->crtc) {
11516 connector->new_encoder = NULL;
11518 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11519 connector->base.base.id,
11520 connector->base.name);
11524 if (&connector->new_encoder->base != connector->base.encoder) {
11525 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11526 connector->base.base.id,
11527 connector->base.name);
11528 config->mode_changed = true;
11531 /* connector->new_encoder is now updated for all connectors. */
11533 /* Update crtc of enabled connectors. */
11534 for_each_intel_connector(dev, connector) {
11535 struct drm_crtc *new_crtc;
11537 if (!connector->new_encoder)
11540 new_crtc = connector->new_encoder->base.crtc;
11542 for (ro = 0; ro < set->num_connectors; ro++) {
11543 if (set->connectors[ro] == &connector->base)
11544 new_crtc = set->crtc;
11547 /* Make sure the new CRTC will work with the encoder */
11548 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11552 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11554 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11555 connector->base.base.id,
11556 connector->base.name,
11557 new_crtc->base.id);
11560 /* Check for any encoders that needs to be disabled. */
11561 for_each_intel_encoder(dev, encoder) {
11562 int num_connectors = 0;
11563 for_each_intel_connector(dev, connector) {
11564 if (connector->new_encoder == encoder) {
11565 WARN_ON(!connector->new_encoder->new_crtc);
11570 if (num_connectors == 0)
11571 encoder->new_crtc = NULL;
11572 else if (num_connectors > 1)
11575 /* Only now check for crtc changes so we don't miss encoders
11576 * that will be disabled. */
11577 if (&encoder->new_crtc->base != encoder->base.crtc) {
11578 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11579 encoder->base.base.id,
11580 encoder->base.name);
11581 config->mode_changed = true;
11584 /* Now we've also updated encoder->new_crtc for all encoders. */
11585 for_each_intel_connector(dev, connector) {
11586 if (connector->new_encoder)
11587 if (connector->new_encoder != connector->encoder)
11588 connector->encoder = connector->new_encoder;
11590 for_each_intel_crtc(dev, crtc) {
11591 crtc->new_enabled = false;
11593 for_each_intel_encoder(dev, encoder) {
11594 if (encoder->new_crtc == crtc) {
11595 crtc->new_enabled = true;
11600 if (crtc->new_enabled != crtc->base.state->enable) {
11601 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11602 crtc->base.base.id,
11603 crtc->new_enabled ? "en" : "dis");
11604 config->mode_changed = true;
11607 if (crtc->new_enabled)
11608 crtc->new_config = crtc->config;
11610 crtc->new_config = NULL;
11616 static void disable_crtc_nofb(struct intel_crtc *crtc)
11618 struct drm_device *dev = crtc->base.dev;
11619 struct intel_encoder *encoder;
11620 struct intel_connector *connector;
11622 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11623 pipe_name(crtc->pipe));
11625 for_each_intel_connector(dev, connector) {
11626 if (connector->new_encoder &&
11627 connector->new_encoder->new_crtc == crtc)
11628 connector->new_encoder = NULL;
11631 for_each_intel_encoder(dev, encoder) {
11632 if (encoder->new_crtc == crtc)
11633 encoder->new_crtc = NULL;
11636 crtc->new_enabled = false;
11637 crtc->new_config = NULL;
11640 static int intel_crtc_set_config(struct drm_mode_set *set)
11642 struct drm_device *dev;
11643 struct drm_mode_set save_set;
11644 struct intel_set_config *config;
11645 struct intel_crtc_state *pipe_config;
11646 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11650 BUG_ON(!set->crtc);
11651 BUG_ON(!set->crtc->helper_private);
11653 /* Enforce sane interface api - has been abused by the fb helper. */
11654 BUG_ON(!set->mode && set->fb);
11655 BUG_ON(set->fb && set->num_connectors == 0);
11658 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11659 set->crtc->base.id, set->fb->base.id,
11660 (int)set->num_connectors, set->x, set->y);
11662 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11665 dev = set->crtc->dev;
11668 config = kzalloc(sizeof(*config), GFP_KERNEL);
11672 ret = intel_set_config_save_state(dev, config);
11676 save_set.crtc = set->crtc;
11677 save_set.mode = &set->crtc->mode;
11678 save_set.x = set->crtc->x;
11679 save_set.y = set->crtc->y;
11680 save_set.fb = set->crtc->primary->fb;
11682 /* Compute whether we need a full modeset, only an fb base update or no
11683 * change at all. In the future we might also check whether only the
11684 * mode changed, e.g. for LVDS where we only change the panel fitter in
11686 intel_set_config_compute_mode_changes(set, config);
11688 ret = intel_modeset_stage_output_state(dev, set, config);
11692 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11697 if (IS_ERR(pipe_config)) {
11698 ret = PTR_ERR(pipe_config);
11700 } else if (pipe_config) {
11701 if (pipe_config->has_audio !=
11702 to_intel_crtc(set->crtc)->config->has_audio)
11703 config->mode_changed = true;
11706 * Note we have an issue here with infoframes: current code
11707 * only updates them on the full mode set path per hw
11708 * requirements. So here we should be checking for any
11709 * required changes and forcing a mode set.
11713 /* set_mode will free it in the mode_changed case */
11714 if (!config->mode_changed)
11715 kfree(pipe_config);
11717 intel_update_pipe_size(to_intel_crtc(set->crtc));
11719 if (config->mode_changed) {
11720 ret = intel_set_mode_pipes(set->crtc, set->mode,
11721 set->x, set->y, set->fb, pipe_config,
11722 modeset_pipes, prepare_pipes,
11724 } else if (config->fb_changed) {
11725 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11726 struct drm_plane *primary = set->crtc->primary;
11727 int vdisplay, hdisplay;
11729 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11730 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11731 0, 0, hdisplay, vdisplay,
11732 set->x << 16, set->y << 16,
11733 hdisplay << 16, vdisplay << 16);
11736 * We need to make sure the primary plane is re-enabled if it
11737 * has previously been turned off.
11739 if (!intel_crtc->primary_enabled && ret == 0) {
11740 WARN_ON(!intel_crtc->active);
11741 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11745 * In the fastboot case this may be our only check of the
11746 * state after boot. It would be better to only do it on
11747 * the first update, but we don't have a nice way of doing that
11748 * (and really, set_config isn't used much for high freq page
11749 * flipping, so increasing its cost here shouldn't be a big
11752 if (i915.fastboot && ret == 0)
11753 intel_modeset_check_state(set->crtc->dev);
11757 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11758 set->crtc->base.id, ret);
11760 intel_set_config_restore_state(dev, config);
11763 * HACK: if the pipe was on, but we didn't have a framebuffer,
11764 * force the pipe off to avoid oopsing in the modeset code
11765 * due to fb==NULL. This should only happen during boot since
11766 * we don't yet reconstruct the FB from the hardware state.
11768 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11769 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11771 /* Try to restore the config */
11772 if (config->mode_changed &&
11773 intel_set_mode(save_set.crtc, save_set.mode,
11774 save_set.x, save_set.y, save_set.fb))
11775 DRM_ERROR("failed to restore config after modeset failure\n");
11779 intel_set_config_free(config);
11783 static const struct drm_crtc_funcs intel_crtc_funcs = {
11784 .gamma_set = intel_crtc_gamma_set,
11785 .set_config = intel_crtc_set_config,
11786 .destroy = intel_crtc_destroy,
11787 .page_flip = intel_crtc_page_flip,
11788 .atomic_duplicate_state = intel_crtc_duplicate_state,
11789 .atomic_destroy_state = intel_crtc_destroy_state,
11792 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11793 struct intel_shared_dpll *pll,
11794 struct intel_dpll_hw_state *hw_state)
11798 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11801 val = I915_READ(PCH_DPLL(pll->id));
11802 hw_state->dpll = val;
11803 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11804 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11806 return val & DPLL_VCO_ENABLE;
11809 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11810 struct intel_shared_dpll *pll)
11812 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11813 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11816 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11817 struct intel_shared_dpll *pll)
11819 /* PCH refclock must be enabled first */
11820 ibx_assert_pch_refclk_enabled(dev_priv);
11822 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11824 /* Wait for the clocks to stabilize. */
11825 POSTING_READ(PCH_DPLL(pll->id));
11828 /* The pixel multiplier can only be updated once the
11829 * DPLL is enabled and the clocks are stable.
11831 * So write it again.
11833 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11834 POSTING_READ(PCH_DPLL(pll->id));
11838 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11839 struct intel_shared_dpll *pll)
11841 struct drm_device *dev = dev_priv->dev;
11842 struct intel_crtc *crtc;
11844 /* Make sure no transcoder isn't still depending on us. */
11845 for_each_intel_crtc(dev, crtc) {
11846 if (intel_crtc_to_shared_dpll(crtc) == pll)
11847 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11850 I915_WRITE(PCH_DPLL(pll->id), 0);
11851 POSTING_READ(PCH_DPLL(pll->id));
11855 static char *ibx_pch_dpll_names[] = {
11860 static void ibx_pch_dpll_init(struct drm_device *dev)
11862 struct drm_i915_private *dev_priv = dev->dev_private;
11865 dev_priv->num_shared_dpll = 2;
11867 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11868 dev_priv->shared_dplls[i].id = i;
11869 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11870 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11871 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11872 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11873 dev_priv->shared_dplls[i].get_hw_state =
11874 ibx_pch_dpll_get_hw_state;
11878 static void intel_shared_dpll_init(struct drm_device *dev)
11880 struct drm_i915_private *dev_priv = dev->dev_private;
11883 intel_ddi_pll_init(dev);
11884 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11885 ibx_pch_dpll_init(dev);
11887 dev_priv->num_shared_dpll = 0;
11889 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11893 * intel_prepare_plane_fb - Prepare fb for usage on plane
11894 * @plane: drm plane to prepare for
11895 * @fb: framebuffer to prepare for presentation
11897 * Prepares a framebuffer for usage on a display plane. Generally this
11898 * involves pinning the underlying object and updating the frontbuffer tracking
11899 * bits. Some older platforms need special physical address handling for
11902 * Returns 0 on success, negative error code on failure.
11905 intel_prepare_plane_fb(struct drm_plane *plane,
11906 struct drm_framebuffer *fb,
11907 const struct drm_plane_state *new_state)
11909 struct drm_device *dev = plane->dev;
11910 struct intel_plane *intel_plane = to_intel_plane(plane);
11911 enum pipe pipe = intel_plane->pipe;
11912 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11913 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11914 unsigned frontbuffer_bits = 0;
11920 switch (plane->type) {
11921 case DRM_PLANE_TYPE_PRIMARY:
11922 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11924 case DRM_PLANE_TYPE_CURSOR:
11925 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11927 case DRM_PLANE_TYPE_OVERLAY:
11928 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11932 mutex_lock(&dev->struct_mutex);
11934 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11935 INTEL_INFO(dev)->cursor_needs_physical) {
11936 int align = IS_I830(dev) ? 16 * 1024 : 256;
11937 ret = i915_gem_object_attach_phys(obj, align);
11939 DRM_DEBUG_KMS("failed to attach phys object\n");
11941 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11945 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11947 mutex_unlock(&dev->struct_mutex);
11953 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11954 * @plane: drm plane to clean up for
11955 * @fb: old framebuffer that was on plane
11957 * Cleans up a framebuffer that has just been removed from a plane.
11960 intel_cleanup_plane_fb(struct drm_plane *plane,
11961 struct drm_framebuffer *fb,
11962 const struct drm_plane_state *old_state)
11964 struct drm_device *dev = plane->dev;
11965 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11970 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11971 !INTEL_INFO(dev)->cursor_needs_physical) {
11972 mutex_lock(&dev->struct_mutex);
11973 intel_unpin_fb_obj(obj);
11974 mutex_unlock(&dev->struct_mutex);
11979 intel_check_primary_plane(struct drm_plane *plane,
11980 struct intel_plane_state *state)
11982 struct drm_device *dev = plane->dev;
11983 struct drm_i915_private *dev_priv = dev->dev_private;
11984 struct drm_crtc *crtc = state->base.crtc;
11985 struct intel_crtc *intel_crtc;
11986 struct drm_framebuffer *fb = state->base.fb;
11987 struct drm_rect *dest = &state->dst;
11988 struct drm_rect *src = &state->src;
11989 const struct drm_rect *clip = &state->clip;
11992 crtc = crtc ? crtc : plane->crtc;
11993 intel_crtc = to_intel_crtc(crtc);
11995 ret = drm_plane_helper_check_update(plane, crtc, fb,
11997 DRM_PLANE_HELPER_NO_SCALING,
11998 DRM_PLANE_HELPER_NO_SCALING,
11999 false, true, &state->visible);
12003 if (intel_crtc->active) {
12004 intel_crtc->atomic.wait_for_flips = true;
12007 * FBC does not work on some platforms for rotated
12008 * planes, so disable it when rotation is not 0 and
12009 * update it when rotation is set back to 0.
12011 * FIXME: This is redundant with the fbc update done in
12012 * the primary plane enable function except that that
12013 * one is done too late. We eventually need to unify
12016 if (intel_crtc->primary_enabled &&
12017 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12018 dev_priv->fbc.crtc == intel_crtc &&
12019 state->base.rotation != BIT(DRM_ROTATE_0)) {
12020 intel_crtc->atomic.disable_fbc = true;
12023 if (state->visible) {
12025 * BDW signals flip done immediately if the plane
12026 * is disabled, even if the plane enable is already
12027 * armed to occur at the next vblank :(
12029 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12030 intel_crtc->atomic.wait_vblank = true;
12033 intel_crtc->atomic.fb_bits |=
12034 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12036 intel_crtc->atomic.update_fbc = true;
12038 /* Update watermarks on tiling changes. */
12039 if (!plane->state->fb || !state->base.fb ||
12040 plane->state->fb->modifier[0] !=
12041 state->base.fb->modifier[0])
12042 intel_crtc->atomic.update_wm = true;
12049 intel_commit_primary_plane(struct drm_plane *plane,
12050 struct intel_plane_state *state)
12052 struct drm_crtc *crtc = state->base.crtc;
12053 struct drm_framebuffer *fb = state->base.fb;
12054 struct drm_device *dev = plane->dev;
12055 struct drm_i915_private *dev_priv = dev->dev_private;
12056 struct intel_crtc *intel_crtc;
12057 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12058 struct intel_plane *intel_plane = to_intel_plane(plane);
12059 struct drm_rect *src = &state->src;
12061 crtc = crtc ? crtc : plane->crtc;
12062 intel_crtc = to_intel_crtc(crtc);
12065 crtc->x = src->x1 >> 16;
12066 crtc->y = src->y1 >> 16;
12068 intel_plane->obj = obj;
12070 if (intel_crtc->active) {
12071 if (state->visible) {
12072 /* FIXME: kill this fastboot hack */
12073 intel_update_pipe_size(intel_crtc);
12075 intel_crtc->primary_enabled = true;
12077 dev_priv->display.update_primary_plane(crtc, plane->fb,
12081 * If clipping results in a non-visible primary plane,
12082 * we'll disable the primary plane. Note that this is
12083 * a bit different than what happens if userspace
12084 * explicitly disables the plane by passing fb=0
12085 * because plane->fb still gets set and pinned.
12087 intel_disable_primary_hw_plane(plane, crtc);
12092 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12094 struct drm_device *dev = crtc->dev;
12095 struct drm_i915_private *dev_priv = dev->dev_private;
12096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12097 struct intel_plane *intel_plane;
12098 struct drm_plane *p;
12099 unsigned fb_bits = 0;
12101 /* Track fb's for any planes being disabled */
12102 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12103 intel_plane = to_intel_plane(p);
12105 if (intel_crtc->atomic.disabled_planes &
12106 (1 << drm_plane_index(p))) {
12108 case DRM_PLANE_TYPE_PRIMARY:
12109 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12111 case DRM_PLANE_TYPE_CURSOR:
12112 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12114 case DRM_PLANE_TYPE_OVERLAY:
12115 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12119 mutex_lock(&dev->struct_mutex);
12120 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12121 mutex_unlock(&dev->struct_mutex);
12125 if (intel_crtc->atomic.wait_for_flips)
12126 intel_crtc_wait_for_pending_flips(crtc);
12128 if (intel_crtc->atomic.disable_fbc)
12129 intel_fbc_disable(dev);
12131 if (intel_crtc->atomic.pre_disable_primary)
12132 intel_pre_disable_primary(crtc);
12134 if (intel_crtc->atomic.update_wm)
12135 intel_update_watermarks(crtc);
12137 intel_runtime_pm_get(dev_priv);
12139 /* Perform vblank evasion around commit operation */
12140 if (intel_crtc->active)
12141 intel_crtc->atomic.evade =
12142 intel_pipe_update_start(intel_crtc,
12143 &intel_crtc->atomic.start_vbl_count);
12146 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12148 struct drm_device *dev = crtc->dev;
12149 struct drm_i915_private *dev_priv = dev->dev_private;
12150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12151 struct drm_plane *p;
12153 if (intel_crtc->atomic.evade)
12154 intel_pipe_update_end(intel_crtc,
12155 intel_crtc->atomic.start_vbl_count);
12157 intel_runtime_pm_put(dev_priv);
12159 if (intel_crtc->atomic.wait_vblank)
12160 intel_wait_for_vblank(dev, intel_crtc->pipe);
12162 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12164 if (intel_crtc->atomic.update_fbc) {
12165 mutex_lock(&dev->struct_mutex);
12166 intel_fbc_update(dev);
12167 mutex_unlock(&dev->struct_mutex);
12170 if (intel_crtc->atomic.post_enable_primary)
12171 intel_post_enable_primary(crtc);
12173 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12174 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12175 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12178 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12182 * intel_plane_destroy - destroy a plane
12183 * @plane: plane to destroy
12185 * Common destruction function for all types of planes (primary, cursor,
12188 void intel_plane_destroy(struct drm_plane *plane)
12190 struct intel_plane *intel_plane = to_intel_plane(plane);
12191 drm_plane_cleanup(plane);
12192 kfree(intel_plane);
12195 const struct drm_plane_funcs intel_plane_funcs = {
12196 .update_plane = drm_plane_helper_update,
12197 .disable_plane = drm_plane_helper_disable,
12198 .destroy = intel_plane_destroy,
12199 .set_property = drm_atomic_helper_plane_set_property,
12200 .atomic_get_property = intel_plane_atomic_get_property,
12201 .atomic_set_property = intel_plane_atomic_set_property,
12202 .atomic_duplicate_state = intel_plane_duplicate_state,
12203 .atomic_destroy_state = intel_plane_destroy_state,
12207 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12210 struct intel_plane *primary;
12211 struct intel_plane_state *state;
12212 const uint32_t *intel_primary_formats;
12215 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12216 if (primary == NULL)
12219 state = intel_create_plane_state(&primary->base);
12224 primary->base.state = &state->base;
12226 primary->can_scale = false;
12227 primary->max_downscale = 1;
12228 primary->pipe = pipe;
12229 primary->plane = pipe;
12230 primary->check_plane = intel_check_primary_plane;
12231 primary->commit_plane = intel_commit_primary_plane;
12232 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12233 primary->plane = !pipe;
12235 if (INTEL_INFO(dev)->gen <= 3) {
12236 intel_primary_formats = intel_primary_formats_gen2;
12237 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12239 intel_primary_formats = intel_primary_formats_gen4;
12240 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12243 drm_universal_plane_init(dev, &primary->base, 0,
12244 &intel_plane_funcs,
12245 intel_primary_formats, num_formats,
12246 DRM_PLANE_TYPE_PRIMARY);
12248 if (INTEL_INFO(dev)->gen >= 4) {
12249 if (!dev->mode_config.rotation_property)
12250 dev->mode_config.rotation_property =
12251 drm_mode_create_rotation_property(dev,
12252 BIT(DRM_ROTATE_0) |
12253 BIT(DRM_ROTATE_180));
12254 if (dev->mode_config.rotation_property)
12255 drm_object_attach_property(&primary->base.base,
12256 dev->mode_config.rotation_property,
12257 state->base.rotation);
12260 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12262 return &primary->base;
12266 intel_check_cursor_plane(struct drm_plane *plane,
12267 struct intel_plane_state *state)
12269 struct drm_crtc *crtc = state->base.crtc;
12270 struct drm_device *dev = plane->dev;
12271 struct drm_framebuffer *fb = state->base.fb;
12272 struct drm_rect *dest = &state->dst;
12273 struct drm_rect *src = &state->src;
12274 const struct drm_rect *clip = &state->clip;
12275 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12276 struct intel_crtc *intel_crtc;
12280 crtc = crtc ? crtc : plane->crtc;
12281 intel_crtc = to_intel_crtc(crtc);
12283 ret = drm_plane_helper_check_update(plane, crtc, fb,
12285 DRM_PLANE_HELPER_NO_SCALING,
12286 DRM_PLANE_HELPER_NO_SCALING,
12287 true, true, &state->visible);
12292 /* if we want to turn off the cursor ignore width and height */
12296 /* Check for which cursor types we support */
12297 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12298 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12299 state->base.crtc_w, state->base.crtc_h);
12303 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12304 if (obj->base.size < stride * state->base.crtc_h) {
12305 DRM_DEBUG_KMS("buffer is too small\n");
12309 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12310 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12315 if (intel_crtc->active) {
12316 if (intel_crtc->base.cursor->state->crtc_w != state->base.crtc_w)
12317 intel_crtc->atomic.update_wm = true;
12319 intel_crtc->atomic.fb_bits |=
12320 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12327 intel_commit_cursor_plane(struct drm_plane *plane,
12328 struct intel_plane_state *state)
12330 struct drm_crtc *crtc = state->base.crtc;
12331 struct drm_device *dev = plane->dev;
12332 struct intel_crtc *intel_crtc;
12333 struct intel_plane *intel_plane = to_intel_plane(plane);
12334 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12337 crtc = crtc ? crtc : plane->crtc;
12338 intel_crtc = to_intel_crtc(crtc);
12340 plane->fb = state->base.fb;
12341 crtc->cursor_x = state->base.crtc_x;
12342 crtc->cursor_y = state->base.crtc_y;
12344 intel_plane->obj = obj;
12346 if (intel_crtc->cursor_bo == obj)
12351 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12352 addr = i915_gem_obj_ggtt_offset(obj);
12354 addr = obj->phys_handle->busaddr;
12356 intel_crtc->cursor_addr = addr;
12357 intel_crtc->cursor_bo = obj;
12360 if (intel_crtc->active)
12361 intel_crtc_update_cursor(crtc, state->visible);
12364 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12367 struct intel_plane *cursor;
12368 struct intel_plane_state *state;
12370 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12371 if (cursor == NULL)
12374 state = intel_create_plane_state(&cursor->base);
12379 cursor->base.state = &state->base;
12381 cursor->can_scale = false;
12382 cursor->max_downscale = 1;
12383 cursor->pipe = pipe;
12384 cursor->plane = pipe;
12385 cursor->check_plane = intel_check_cursor_plane;
12386 cursor->commit_plane = intel_commit_cursor_plane;
12388 drm_universal_plane_init(dev, &cursor->base, 0,
12389 &intel_plane_funcs,
12390 intel_cursor_formats,
12391 ARRAY_SIZE(intel_cursor_formats),
12392 DRM_PLANE_TYPE_CURSOR);
12394 if (INTEL_INFO(dev)->gen >= 4) {
12395 if (!dev->mode_config.rotation_property)
12396 dev->mode_config.rotation_property =
12397 drm_mode_create_rotation_property(dev,
12398 BIT(DRM_ROTATE_0) |
12399 BIT(DRM_ROTATE_180));
12400 if (dev->mode_config.rotation_property)
12401 drm_object_attach_property(&cursor->base.base,
12402 dev->mode_config.rotation_property,
12403 state->base.rotation);
12406 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12408 return &cursor->base;
12411 static void intel_crtc_init(struct drm_device *dev, int pipe)
12413 struct drm_i915_private *dev_priv = dev->dev_private;
12414 struct intel_crtc *intel_crtc;
12415 struct intel_crtc_state *crtc_state = NULL;
12416 struct drm_plane *primary = NULL;
12417 struct drm_plane *cursor = NULL;
12420 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12421 if (intel_crtc == NULL)
12424 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12427 intel_crtc_set_state(intel_crtc, crtc_state);
12428 crtc_state->base.crtc = &intel_crtc->base;
12430 primary = intel_primary_plane_create(dev, pipe);
12434 cursor = intel_cursor_plane_create(dev, pipe);
12438 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12439 cursor, &intel_crtc_funcs);
12443 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12444 for (i = 0; i < 256; i++) {
12445 intel_crtc->lut_r[i] = i;
12446 intel_crtc->lut_g[i] = i;
12447 intel_crtc->lut_b[i] = i;
12451 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12452 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12454 intel_crtc->pipe = pipe;
12455 intel_crtc->plane = pipe;
12456 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12457 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12458 intel_crtc->plane = !pipe;
12461 intel_crtc->cursor_base = ~0;
12462 intel_crtc->cursor_cntl = ~0;
12463 intel_crtc->cursor_size = ~0;
12465 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12466 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12467 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12468 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12470 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12472 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12474 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12479 drm_plane_cleanup(primary);
12481 drm_plane_cleanup(cursor);
12486 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12488 struct drm_encoder *encoder = connector->base.encoder;
12489 struct drm_device *dev = connector->base.dev;
12491 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12493 if (!encoder || WARN_ON(!encoder->crtc))
12494 return INVALID_PIPE;
12496 return to_intel_crtc(encoder->crtc)->pipe;
12499 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12500 struct drm_file *file)
12502 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12503 struct drm_crtc *drmmode_crtc;
12504 struct intel_crtc *crtc;
12506 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12508 if (!drmmode_crtc) {
12509 DRM_ERROR("no such CRTC id\n");
12513 crtc = to_intel_crtc(drmmode_crtc);
12514 pipe_from_crtc_id->pipe = crtc->pipe;
12519 static int intel_encoder_clones(struct intel_encoder *encoder)
12521 struct drm_device *dev = encoder->base.dev;
12522 struct intel_encoder *source_encoder;
12523 int index_mask = 0;
12526 for_each_intel_encoder(dev, source_encoder) {
12527 if (encoders_cloneable(encoder, source_encoder))
12528 index_mask |= (1 << entry);
12536 static bool has_edp_a(struct drm_device *dev)
12538 struct drm_i915_private *dev_priv = dev->dev_private;
12540 if (!IS_MOBILE(dev))
12543 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12546 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12552 static bool intel_crt_present(struct drm_device *dev)
12554 struct drm_i915_private *dev_priv = dev->dev_private;
12556 if (INTEL_INFO(dev)->gen >= 9)
12559 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12562 if (IS_CHERRYVIEW(dev))
12565 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12571 static void intel_setup_outputs(struct drm_device *dev)
12573 struct drm_i915_private *dev_priv = dev->dev_private;
12574 struct intel_encoder *encoder;
12575 struct drm_connector *connector;
12576 bool dpd_is_edp = false;
12578 intel_lvds_init(dev);
12580 if (intel_crt_present(dev))
12581 intel_crt_init(dev);
12583 if (HAS_DDI(dev)) {
12586 /* Haswell uses DDI functions to detect digital outputs */
12587 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12588 /* DDI A only supports eDP */
12590 intel_ddi_init(dev, PORT_A);
12592 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12594 found = I915_READ(SFUSE_STRAP);
12596 if (found & SFUSE_STRAP_DDIB_DETECTED)
12597 intel_ddi_init(dev, PORT_B);
12598 if (found & SFUSE_STRAP_DDIC_DETECTED)
12599 intel_ddi_init(dev, PORT_C);
12600 if (found & SFUSE_STRAP_DDID_DETECTED)
12601 intel_ddi_init(dev, PORT_D);
12602 } else if (HAS_PCH_SPLIT(dev)) {
12604 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12606 if (has_edp_a(dev))
12607 intel_dp_init(dev, DP_A, PORT_A);
12609 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12610 /* PCH SDVOB multiplex with HDMIB */
12611 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12613 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12614 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12615 intel_dp_init(dev, PCH_DP_B, PORT_B);
12618 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12619 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12621 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12622 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12624 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12625 intel_dp_init(dev, PCH_DP_C, PORT_C);
12627 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12628 intel_dp_init(dev, PCH_DP_D, PORT_D);
12629 } else if (IS_VALLEYVIEW(dev)) {
12631 * The DP_DETECTED bit is the latched state of the DDC
12632 * SDA pin at boot. However since eDP doesn't require DDC
12633 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12634 * eDP ports may have been muxed to an alternate function.
12635 * Thus we can't rely on the DP_DETECTED bit alone to detect
12636 * eDP ports. Consult the VBT as well as DP_DETECTED to
12637 * detect eDP ports.
12639 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12640 !intel_dp_is_edp(dev, PORT_B))
12641 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12643 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12644 intel_dp_is_edp(dev, PORT_B))
12645 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12647 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12648 !intel_dp_is_edp(dev, PORT_C))
12649 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12651 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12652 intel_dp_is_edp(dev, PORT_C))
12653 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12655 if (IS_CHERRYVIEW(dev)) {
12656 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12657 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12659 /* eDP not supported on port D, so don't check VBT */
12660 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12661 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12664 intel_dsi_init(dev);
12665 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12666 bool found = false;
12668 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12669 DRM_DEBUG_KMS("probing SDVOB\n");
12670 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12671 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12672 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12673 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12676 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12677 intel_dp_init(dev, DP_B, PORT_B);
12680 /* Before G4X SDVOC doesn't have its own detect register */
12682 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12683 DRM_DEBUG_KMS("probing SDVOC\n");
12684 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12687 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12689 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12690 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12691 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12693 if (SUPPORTS_INTEGRATED_DP(dev))
12694 intel_dp_init(dev, DP_C, PORT_C);
12697 if (SUPPORTS_INTEGRATED_DP(dev) &&
12698 (I915_READ(DP_D) & DP_DETECTED))
12699 intel_dp_init(dev, DP_D, PORT_D);
12700 } else if (IS_GEN2(dev))
12701 intel_dvo_init(dev);
12703 if (SUPPORTS_TV(dev))
12704 intel_tv_init(dev);
12707 * FIXME: We don't have full atomic support yet, but we want to be
12708 * able to enable/test plane updates via the atomic interface in the
12709 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12710 * will take some atomic codepaths to lookup properties during
12711 * drmModeGetConnector() that unconditionally dereference
12712 * connector->state.
12714 * We create a dummy connector state here for each connector to ensure
12715 * the DRM core doesn't try to dereference a NULL connector->state.
12716 * The actual connector properties will never be updated or contain
12717 * useful information, but since we're doing this specifically for
12718 * testing/debug of the plane operations (and only when a specific
12719 * kernel module option is given), that shouldn't really matter.
12721 * Once atomic support for crtc's + connectors lands, this loop should
12722 * be removed since we'll be setting up real connector state, which
12723 * will contain Intel-specific properties.
12725 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12726 list_for_each_entry(connector,
12727 &dev->mode_config.connector_list,
12729 if (!WARN_ON(connector->state)) {
12731 kzalloc(sizeof(*connector->state),
12737 intel_psr_init(dev);
12739 for_each_intel_encoder(dev, encoder) {
12740 encoder->base.possible_crtcs = encoder->crtc_mask;
12741 encoder->base.possible_clones =
12742 intel_encoder_clones(encoder);
12745 intel_init_pch_refclk(dev);
12747 drm_helper_move_panel_connectors_to_head(dev);
12750 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12752 struct drm_device *dev = fb->dev;
12753 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12755 drm_framebuffer_cleanup(fb);
12756 mutex_lock(&dev->struct_mutex);
12757 WARN_ON(!intel_fb->obj->framebuffer_references--);
12758 drm_gem_object_unreference(&intel_fb->obj->base);
12759 mutex_unlock(&dev->struct_mutex);
12763 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12764 struct drm_file *file,
12765 unsigned int *handle)
12767 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12768 struct drm_i915_gem_object *obj = intel_fb->obj;
12770 return drm_gem_handle_create(file, &obj->base, handle);
12773 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12774 .destroy = intel_user_framebuffer_destroy,
12775 .create_handle = intel_user_framebuffer_create_handle,
12779 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12780 uint32_t pixel_format)
12782 u32 gen = INTEL_INFO(dev)->gen;
12785 /* "The stride in bytes must not exceed the of the size of 8K
12786 * pixels and 32K bytes."
12788 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12789 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12791 } else if (gen >= 4) {
12792 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12796 } else if (gen >= 3) {
12797 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12802 /* XXX DSPC is limited to 4k tiled */
12807 static int intel_framebuffer_init(struct drm_device *dev,
12808 struct intel_framebuffer *intel_fb,
12809 struct drm_mode_fb_cmd2 *mode_cmd,
12810 struct drm_i915_gem_object *obj)
12812 int aligned_height;
12814 u32 pitch_limit, stride_alignment;
12816 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12818 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12819 /* Enforce that fb modifier and tiling mode match, but only for
12820 * X-tiled. This is needed for FBC. */
12821 if (!!(obj->tiling_mode == I915_TILING_X) !=
12822 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12823 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12827 if (obj->tiling_mode == I915_TILING_X)
12828 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12829 else if (obj->tiling_mode == I915_TILING_Y) {
12830 DRM_DEBUG("No Y tiling for legacy addfb\n");
12835 /* Passed in modifier sanity checking. */
12836 switch (mode_cmd->modifier[0]) {
12837 case I915_FORMAT_MOD_Y_TILED:
12838 case I915_FORMAT_MOD_Yf_TILED:
12839 if (INTEL_INFO(dev)->gen < 9) {
12840 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12841 mode_cmd->modifier[0]);
12844 case DRM_FORMAT_MOD_NONE:
12845 case I915_FORMAT_MOD_X_TILED:
12848 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12849 mode_cmd->modifier[0]);
12853 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12854 mode_cmd->pixel_format);
12855 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12856 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12857 mode_cmd->pitches[0], stride_alignment);
12861 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12862 mode_cmd->pixel_format);
12863 if (mode_cmd->pitches[0] > pitch_limit) {
12864 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12865 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12866 "tiled" : "linear",
12867 mode_cmd->pitches[0], pitch_limit);
12871 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12872 mode_cmd->pitches[0] != obj->stride) {
12873 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12874 mode_cmd->pitches[0], obj->stride);
12878 /* Reject formats not supported by any plane early. */
12879 switch (mode_cmd->pixel_format) {
12880 case DRM_FORMAT_C8:
12881 case DRM_FORMAT_RGB565:
12882 case DRM_FORMAT_XRGB8888:
12883 case DRM_FORMAT_ARGB8888:
12885 case DRM_FORMAT_XRGB1555:
12886 case DRM_FORMAT_ARGB1555:
12887 if (INTEL_INFO(dev)->gen > 3) {
12888 DRM_DEBUG("unsupported pixel format: %s\n",
12889 drm_get_format_name(mode_cmd->pixel_format));
12893 case DRM_FORMAT_XBGR8888:
12894 case DRM_FORMAT_ABGR8888:
12895 case DRM_FORMAT_XRGB2101010:
12896 case DRM_FORMAT_ARGB2101010:
12897 case DRM_FORMAT_XBGR2101010:
12898 case DRM_FORMAT_ABGR2101010:
12899 if (INTEL_INFO(dev)->gen < 4) {
12900 DRM_DEBUG("unsupported pixel format: %s\n",
12901 drm_get_format_name(mode_cmd->pixel_format));
12905 case DRM_FORMAT_YUYV:
12906 case DRM_FORMAT_UYVY:
12907 case DRM_FORMAT_YVYU:
12908 case DRM_FORMAT_VYUY:
12909 if (INTEL_INFO(dev)->gen < 5) {
12910 DRM_DEBUG("unsupported pixel format: %s\n",
12911 drm_get_format_name(mode_cmd->pixel_format));
12916 DRM_DEBUG("unsupported pixel format: %s\n",
12917 drm_get_format_name(mode_cmd->pixel_format));
12921 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12922 if (mode_cmd->offsets[0] != 0)
12925 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12926 mode_cmd->pixel_format,
12927 mode_cmd->modifier[0]);
12928 /* FIXME drm helper for size checks (especially planar formats)? */
12929 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12932 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12933 intel_fb->obj = obj;
12934 intel_fb->obj->framebuffer_references++;
12936 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12938 DRM_ERROR("framebuffer init failed %d\n", ret);
12945 static struct drm_framebuffer *
12946 intel_user_framebuffer_create(struct drm_device *dev,
12947 struct drm_file *filp,
12948 struct drm_mode_fb_cmd2 *mode_cmd)
12950 struct drm_i915_gem_object *obj;
12952 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12953 mode_cmd->handles[0]));
12954 if (&obj->base == NULL)
12955 return ERR_PTR(-ENOENT);
12957 return intel_framebuffer_create(dev, mode_cmd, obj);
12960 #ifndef CONFIG_DRM_I915_FBDEV
12961 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12966 static const struct drm_mode_config_funcs intel_mode_funcs = {
12967 .fb_create = intel_user_framebuffer_create,
12968 .output_poll_changed = intel_fbdev_output_poll_changed,
12969 .atomic_check = intel_atomic_check,
12970 .atomic_commit = intel_atomic_commit,
12973 /* Set up chip specific display functions */
12974 static void intel_init_display(struct drm_device *dev)
12976 struct drm_i915_private *dev_priv = dev->dev_private;
12978 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12979 dev_priv->display.find_dpll = g4x_find_best_dpll;
12980 else if (IS_CHERRYVIEW(dev))
12981 dev_priv->display.find_dpll = chv_find_best_dpll;
12982 else if (IS_VALLEYVIEW(dev))
12983 dev_priv->display.find_dpll = vlv_find_best_dpll;
12984 else if (IS_PINEVIEW(dev))
12985 dev_priv->display.find_dpll = pnv_find_best_dpll;
12987 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12989 if (INTEL_INFO(dev)->gen >= 9) {
12990 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12991 dev_priv->display.get_initial_plane_config =
12992 skylake_get_initial_plane_config;
12993 dev_priv->display.crtc_compute_clock =
12994 haswell_crtc_compute_clock;
12995 dev_priv->display.crtc_enable = haswell_crtc_enable;
12996 dev_priv->display.crtc_disable = haswell_crtc_disable;
12997 dev_priv->display.off = ironlake_crtc_off;
12998 dev_priv->display.update_primary_plane =
12999 skylake_update_primary_plane;
13000 } else if (HAS_DDI(dev)) {
13001 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13002 dev_priv->display.get_initial_plane_config =
13003 ironlake_get_initial_plane_config;
13004 dev_priv->display.crtc_compute_clock =
13005 haswell_crtc_compute_clock;
13006 dev_priv->display.crtc_enable = haswell_crtc_enable;
13007 dev_priv->display.crtc_disable = haswell_crtc_disable;
13008 dev_priv->display.off = ironlake_crtc_off;
13009 dev_priv->display.update_primary_plane =
13010 ironlake_update_primary_plane;
13011 } else if (HAS_PCH_SPLIT(dev)) {
13012 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13013 dev_priv->display.get_initial_plane_config =
13014 ironlake_get_initial_plane_config;
13015 dev_priv->display.crtc_compute_clock =
13016 ironlake_crtc_compute_clock;
13017 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13018 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13019 dev_priv->display.off = ironlake_crtc_off;
13020 dev_priv->display.update_primary_plane =
13021 ironlake_update_primary_plane;
13022 } else if (IS_VALLEYVIEW(dev)) {
13023 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13024 dev_priv->display.get_initial_plane_config =
13025 i9xx_get_initial_plane_config;
13026 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13027 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13028 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13029 dev_priv->display.off = i9xx_crtc_off;
13030 dev_priv->display.update_primary_plane =
13031 i9xx_update_primary_plane;
13033 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13034 dev_priv->display.get_initial_plane_config =
13035 i9xx_get_initial_plane_config;
13036 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13037 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13038 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13039 dev_priv->display.off = i9xx_crtc_off;
13040 dev_priv->display.update_primary_plane =
13041 i9xx_update_primary_plane;
13044 /* Returns the core display clock speed */
13045 if (IS_VALLEYVIEW(dev))
13046 dev_priv->display.get_display_clock_speed =
13047 valleyview_get_display_clock_speed;
13048 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13049 dev_priv->display.get_display_clock_speed =
13050 i945_get_display_clock_speed;
13051 else if (IS_I915G(dev))
13052 dev_priv->display.get_display_clock_speed =
13053 i915_get_display_clock_speed;
13054 else if (IS_I945GM(dev) || IS_845G(dev))
13055 dev_priv->display.get_display_clock_speed =
13056 i9xx_misc_get_display_clock_speed;
13057 else if (IS_PINEVIEW(dev))
13058 dev_priv->display.get_display_clock_speed =
13059 pnv_get_display_clock_speed;
13060 else if (IS_I915GM(dev))
13061 dev_priv->display.get_display_clock_speed =
13062 i915gm_get_display_clock_speed;
13063 else if (IS_I865G(dev))
13064 dev_priv->display.get_display_clock_speed =
13065 i865_get_display_clock_speed;
13066 else if (IS_I85X(dev))
13067 dev_priv->display.get_display_clock_speed =
13068 i855_get_display_clock_speed;
13069 else /* 852, 830 */
13070 dev_priv->display.get_display_clock_speed =
13071 i830_get_display_clock_speed;
13073 if (IS_GEN5(dev)) {
13074 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13075 } else if (IS_GEN6(dev)) {
13076 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13077 } else if (IS_IVYBRIDGE(dev)) {
13078 /* FIXME: detect B0+ stepping and use auto training */
13079 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13080 dev_priv->display.modeset_global_resources =
13081 ivb_modeset_global_resources;
13082 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13083 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13084 } else if (IS_VALLEYVIEW(dev)) {
13085 dev_priv->display.modeset_global_resources =
13086 valleyview_modeset_global_resources;
13089 switch (INTEL_INFO(dev)->gen) {
13091 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13095 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13100 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13104 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13107 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13108 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13111 /* Drop through - unsupported since execlist only. */
13113 /* Default just returns -ENODEV to indicate unsupported */
13114 dev_priv->display.queue_flip = intel_default_queue_flip;
13117 intel_panel_init_backlight_funcs(dev);
13119 mutex_init(&dev_priv->pps_mutex);
13123 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13124 * resume, or other times. This quirk makes sure that's the case for
13125 * affected systems.
13127 static void quirk_pipea_force(struct drm_device *dev)
13129 struct drm_i915_private *dev_priv = dev->dev_private;
13131 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13132 DRM_INFO("applying pipe a force quirk\n");
13135 static void quirk_pipeb_force(struct drm_device *dev)
13137 struct drm_i915_private *dev_priv = dev->dev_private;
13139 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13140 DRM_INFO("applying pipe b force quirk\n");
13144 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13146 static void quirk_ssc_force_disable(struct drm_device *dev)
13148 struct drm_i915_private *dev_priv = dev->dev_private;
13149 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13150 DRM_INFO("applying lvds SSC disable quirk\n");
13154 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13157 static void quirk_invert_brightness(struct drm_device *dev)
13159 struct drm_i915_private *dev_priv = dev->dev_private;
13160 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13161 DRM_INFO("applying inverted panel brightness quirk\n");
13164 /* Some VBT's incorrectly indicate no backlight is present */
13165 static void quirk_backlight_present(struct drm_device *dev)
13167 struct drm_i915_private *dev_priv = dev->dev_private;
13168 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13169 DRM_INFO("applying backlight present quirk\n");
13172 struct intel_quirk {
13174 int subsystem_vendor;
13175 int subsystem_device;
13176 void (*hook)(struct drm_device *dev);
13179 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13180 struct intel_dmi_quirk {
13181 void (*hook)(struct drm_device *dev);
13182 const struct dmi_system_id (*dmi_id_list)[];
13185 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13187 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13191 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13193 .dmi_id_list = &(const struct dmi_system_id[]) {
13195 .callback = intel_dmi_reverse_brightness,
13196 .ident = "NCR Corporation",
13197 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13198 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13201 { } /* terminating entry */
13203 .hook = quirk_invert_brightness,
13207 static struct intel_quirk intel_quirks[] = {
13208 /* HP Mini needs pipe A force quirk (LP: #322104) */
13209 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13211 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13212 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13214 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13215 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13217 /* 830 needs to leave pipe A & dpll A up */
13218 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13220 /* 830 needs to leave pipe B & dpll B up */
13221 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13223 /* Lenovo U160 cannot use SSC on LVDS */
13224 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13226 /* Sony Vaio Y cannot use SSC on LVDS */
13227 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13229 /* Acer Aspire 5734Z must invert backlight brightness */
13230 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13232 /* Acer/eMachines G725 */
13233 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13235 /* Acer/eMachines e725 */
13236 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13238 /* Acer/Packard Bell NCL20 */
13239 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13241 /* Acer Aspire 4736Z */
13242 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13244 /* Acer Aspire 5336 */
13245 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13247 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13248 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13250 /* Acer C720 Chromebook (Core i3 4005U) */
13251 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13253 /* Apple Macbook 2,1 (Core 2 T7400) */
13254 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13256 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13257 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13259 /* HP Chromebook 14 (Celeron 2955U) */
13260 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13262 /* Dell Chromebook 11 */
13263 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13266 static void intel_init_quirks(struct drm_device *dev)
13268 struct pci_dev *d = dev->pdev;
13271 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13272 struct intel_quirk *q = &intel_quirks[i];
13274 if (d->device == q->device &&
13275 (d->subsystem_vendor == q->subsystem_vendor ||
13276 q->subsystem_vendor == PCI_ANY_ID) &&
13277 (d->subsystem_device == q->subsystem_device ||
13278 q->subsystem_device == PCI_ANY_ID))
13281 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13282 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13283 intel_dmi_quirks[i].hook(dev);
13287 /* Disable the VGA plane that we never use */
13288 static void i915_disable_vga(struct drm_device *dev)
13290 struct drm_i915_private *dev_priv = dev->dev_private;
13292 u32 vga_reg = i915_vgacntrl_reg(dev);
13294 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13295 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13296 outb(SR01, VGA_SR_INDEX);
13297 sr1 = inb(VGA_SR_DATA);
13298 outb(sr1 | 1<<5, VGA_SR_DATA);
13299 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13302 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13303 POSTING_READ(vga_reg);
13306 void intel_modeset_init_hw(struct drm_device *dev)
13308 intel_prepare_ddi(dev);
13310 if (IS_VALLEYVIEW(dev))
13311 vlv_update_cdclk(dev);
13313 intel_init_clock_gating(dev);
13315 intel_enable_gt_powersave(dev);
13318 void intel_modeset_init(struct drm_device *dev)
13320 struct drm_i915_private *dev_priv = dev->dev_private;
13323 struct intel_crtc *crtc;
13325 drm_mode_config_init(dev);
13327 dev->mode_config.min_width = 0;
13328 dev->mode_config.min_height = 0;
13330 dev->mode_config.preferred_depth = 24;
13331 dev->mode_config.prefer_shadow = 1;
13333 dev->mode_config.allow_fb_modifiers = true;
13335 dev->mode_config.funcs = &intel_mode_funcs;
13337 intel_init_quirks(dev);
13339 intel_init_pm(dev);
13341 if (INTEL_INFO(dev)->num_pipes == 0)
13344 intel_init_display(dev);
13345 intel_init_audio(dev);
13347 if (IS_GEN2(dev)) {
13348 dev->mode_config.max_width = 2048;
13349 dev->mode_config.max_height = 2048;
13350 } else if (IS_GEN3(dev)) {
13351 dev->mode_config.max_width = 4096;
13352 dev->mode_config.max_height = 4096;
13354 dev->mode_config.max_width = 8192;
13355 dev->mode_config.max_height = 8192;
13358 if (IS_845G(dev) || IS_I865G(dev)) {
13359 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13360 dev->mode_config.cursor_height = 1023;
13361 } else if (IS_GEN2(dev)) {
13362 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13363 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13365 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13366 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13369 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13371 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13372 INTEL_INFO(dev)->num_pipes,
13373 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13375 for_each_pipe(dev_priv, pipe) {
13376 intel_crtc_init(dev, pipe);
13377 for_each_sprite(dev_priv, pipe, sprite) {
13378 ret = intel_plane_init(dev, pipe, sprite);
13380 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13381 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13385 intel_init_dpio(dev);
13387 intel_shared_dpll_init(dev);
13389 /* Just disable it once at startup */
13390 i915_disable_vga(dev);
13391 intel_setup_outputs(dev);
13393 /* Just in case the BIOS is doing something questionable. */
13394 intel_fbc_disable(dev);
13396 drm_modeset_lock_all(dev);
13397 intel_modeset_setup_hw_state(dev, false);
13398 drm_modeset_unlock_all(dev);
13400 for_each_intel_crtc(dev, crtc) {
13405 * Note that reserving the BIOS fb up front prevents us
13406 * from stuffing other stolen allocations like the ring
13407 * on top. This prevents some ugliness at boot time, and
13408 * can even allow for smooth boot transitions if the BIOS
13409 * fb is large enough for the active pipe configuration.
13411 if (dev_priv->display.get_initial_plane_config) {
13412 dev_priv->display.get_initial_plane_config(crtc,
13413 &crtc->plane_config);
13415 * If the fb is shared between multiple heads, we'll
13416 * just get the first one.
13418 intel_find_plane_obj(crtc, &crtc->plane_config);
13423 static void intel_enable_pipe_a(struct drm_device *dev)
13425 struct intel_connector *connector;
13426 struct drm_connector *crt = NULL;
13427 struct intel_load_detect_pipe load_detect_temp;
13428 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13430 /* We can't just switch on the pipe A, we need to set things up with a
13431 * proper mode and output configuration. As a gross hack, enable pipe A
13432 * by enabling the load detect pipe once. */
13433 for_each_intel_connector(dev, connector) {
13434 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13435 crt = &connector->base;
13443 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13444 intel_release_load_detect_pipe(crt, &load_detect_temp);
13448 intel_check_plane_mapping(struct intel_crtc *crtc)
13450 struct drm_device *dev = crtc->base.dev;
13451 struct drm_i915_private *dev_priv = dev->dev_private;
13454 if (INTEL_INFO(dev)->num_pipes == 1)
13457 reg = DSPCNTR(!crtc->plane);
13458 val = I915_READ(reg);
13460 if ((val & DISPLAY_PLANE_ENABLE) &&
13461 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13467 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13469 struct drm_device *dev = crtc->base.dev;
13470 struct drm_i915_private *dev_priv = dev->dev_private;
13473 /* Clear any frame start delays used for debugging left by the BIOS */
13474 reg = PIPECONF(crtc->config->cpu_transcoder);
13475 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13477 /* restore vblank interrupts to correct state */
13478 drm_crtc_vblank_reset(&crtc->base);
13479 if (crtc->active) {
13480 update_scanline_offset(crtc);
13481 drm_crtc_vblank_on(&crtc->base);
13484 /* We need to sanitize the plane -> pipe mapping first because this will
13485 * disable the crtc (and hence change the state) if it is wrong. Note
13486 * that gen4+ has a fixed plane -> pipe mapping. */
13487 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13488 struct intel_connector *connector;
13491 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13492 crtc->base.base.id);
13494 /* Pipe has the wrong plane attached and the plane is active.
13495 * Temporarily change the plane mapping and disable everything
13497 plane = crtc->plane;
13498 crtc->plane = !plane;
13499 crtc->primary_enabled = true;
13500 dev_priv->display.crtc_disable(&crtc->base);
13501 crtc->plane = plane;
13503 /* ... and break all links. */
13504 for_each_intel_connector(dev, connector) {
13505 if (connector->encoder->base.crtc != &crtc->base)
13508 connector->base.dpms = DRM_MODE_DPMS_OFF;
13509 connector->base.encoder = NULL;
13511 /* multiple connectors may have the same encoder:
13512 * handle them and break crtc link separately */
13513 for_each_intel_connector(dev, connector)
13514 if (connector->encoder->base.crtc == &crtc->base) {
13515 connector->encoder->base.crtc = NULL;
13516 connector->encoder->connectors_active = false;
13519 WARN_ON(crtc->active);
13520 crtc->base.state->enable = false;
13521 crtc->base.enabled = false;
13524 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13525 crtc->pipe == PIPE_A && !crtc->active) {
13526 /* BIOS forgot to enable pipe A, this mostly happens after
13527 * resume. Force-enable the pipe to fix this, the update_dpms
13528 * call below we restore the pipe to the right state, but leave
13529 * the required bits on. */
13530 intel_enable_pipe_a(dev);
13533 /* Adjust the state of the output pipe according to whether we
13534 * have active connectors/encoders. */
13535 intel_crtc_update_dpms(&crtc->base);
13537 if (crtc->active != crtc->base.state->enable) {
13538 struct intel_encoder *encoder;
13540 /* This can happen either due to bugs in the get_hw_state
13541 * functions or because the pipe is force-enabled due to the
13543 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13544 crtc->base.base.id,
13545 crtc->base.state->enable ? "enabled" : "disabled",
13546 crtc->active ? "enabled" : "disabled");
13548 crtc->base.state->enable = crtc->active;
13549 crtc->base.enabled = crtc->active;
13551 /* Because we only establish the connector -> encoder ->
13552 * crtc links if something is active, this means the
13553 * crtc is now deactivated. Break the links. connector
13554 * -> encoder links are only establish when things are
13555 * actually up, hence no need to break them. */
13556 WARN_ON(crtc->active);
13558 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13559 WARN_ON(encoder->connectors_active);
13560 encoder->base.crtc = NULL;
13564 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13566 * We start out with underrun reporting disabled to avoid races.
13567 * For correct bookkeeping mark this on active crtcs.
13569 * Also on gmch platforms we dont have any hardware bits to
13570 * disable the underrun reporting. Which means we need to start
13571 * out with underrun reporting disabled also on inactive pipes,
13572 * since otherwise we'll complain about the garbage we read when
13573 * e.g. coming up after runtime pm.
13575 * No protection against concurrent access is required - at
13576 * worst a fifo underrun happens which also sets this to false.
13578 crtc->cpu_fifo_underrun_disabled = true;
13579 crtc->pch_fifo_underrun_disabled = true;
13583 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13585 struct intel_connector *connector;
13586 struct drm_device *dev = encoder->base.dev;
13588 /* We need to check both for a crtc link (meaning that the
13589 * encoder is active and trying to read from a pipe) and the
13590 * pipe itself being active. */
13591 bool has_active_crtc = encoder->base.crtc &&
13592 to_intel_crtc(encoder->base.crtc)->active;
13594 if (encoder->connectors_active && !has_active_crtc) {
13595 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13596 encoder->base.base.id,
13597 encoder->base.name);
13599 /* Connector is active, but has no active pipe. This is
13600 * fallout from our resume register restoring. Disable
13601 * the encoder manually again. */
13602 if (encoder->base.crtc) {
13603 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13604 encoder->base.base.id,
13605 encoder->base.name);
13606 encoder->disable(encoder);
13607 if (encoder->post_disable)
13608 encoder->post_disable(encoder);
13610 encoder->base.crtc = NULL;
13611 encoder->connectors_active = false;
13613 /* Inconsistent output/port/pipe state happens presumably due to
13614 * a bug in one of the get_hw_state functions. Or someplace else
13615 * in our code, like the register restore mess on resume. Clamp
13616 * things to off as a safer default. */
13617 for_each_intel_connector(dev, connector) {
13618 if (connector->encoder != encoder)
13620 connector->base.dpms = DRM_MODE_DPMS_OFF;
13621 connector->base.encoder = NULL;
13624 /* Enabled encoders without active connectors will be fixed in
13625 * the crtc fixup. */
13628 void i915_redisable_vga_power_on(struct drm_device *dev)
13630 struct drm_i915_private *dev_priv = dev->dev_private;
13631 u32 vga_reg = i915_vgacntrl_reg(dev);
13633 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13634 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13635 i915_disable_vga(dev);
13639 void i915_redisable_vga(struct drm_device *dev)
13641 struct drm_i915_private *dev_priv = dev->dev_private;
13643 /* This function can be called both from intel_modeset_setup_hw_state or
13644 * at a very early point in our resume sequence, where the power well
13645 * structures are not yet restored. Since this function is at a very
13646 * paranoid "someone might have enabled VGA while we were not looking"
13647 * level, just check if the power well is enabled instead of trying to
13648 * follow the "don't touch the power well if we don't need it" policy
13649 * the rest of the driver uses. */
13650 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13653 i915_redisable_vga_power_on(dev);
13656 static bool primary_get_hw_state(struct intel_crtc *crtc)
13658 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13663 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13666 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13668 struct drm_i915_private *dev_priv = dev->dev_private;
13670 struct intel_crtc *crtc;
13671 struct intel_encoder *encoder;
13672 struct intel_connector *connector;
13675 for_each_intel_crtc(dev, crtc) {
13676 memset(crtc->config, 0, sizeof(*crtc->config));
13678 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13680 crtc->active = dev_priv->display.get_pipe_config(crtc,
13683 crtc->base.state->enable = crtc->active;
13684 crtc->base.enabled = crtc->active;
13685 crtc->primary_enabled = primary_get_hw_state(crtc);
13687 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13688 crtc->base.base.id,
13689 crtc->active ? "enabled" : "disabled");
13692 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13693 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13695 pll->on = pll->get_hw_state(dev_priv, pll,
13696 &pll->config.hw_state);
13698 pll->config.crtc_mask = 0;
13699 for_each_intel_crtc(dev, crtc) {
13700 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13702 pll->config.crtc_mask |= 1 << crtc->pipe;
13706 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13707 pll->name, pll->config.crtc_mask, pll->on);
13709 if (pll->config.crtc_mask)
13710 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13713 for_each_intel_encoder(dev, encoder) {
13716 if (encoder->get_hw_state(encoder, &pipe)) {
13717 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13718 encoder->base.crtc = &crtc->base;
13719 encoder->get_config(encoder, crtc->config);
13721 encoder->base.crtc = NULL;
13724 encoder->connectors_active = false;
13725 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13726 encoder->base.base.id,
13727 encoder->base.name,
13728 encoder->base.crtc ? "enabled" : "disabled",
13732 for_each_intel_connector(dev, connector) {
13733 if (connector->get_hw_state(connector)) {
13734 connector->base.dpms = DRM_MODE_DPMS_ON;
13735 connector->encoder->connectors_active = true;
13736 connector->base.encoder = &connector->encoder->base;
13738 connector->base.dpms = DRM_MODE_DPMS_OFF;
13739 connector->base.encoder = NULL;
13741 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13742 connector->base.base.id,
13743 connector->base.name,
13744 connector->base.encoder ? "enabled" : "disabled");
13748 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13749 * and i915 state tracking structures. */
13750 void intel_modeset_setup_hw_state(struct drm_device *dev,
13751 bool force_restore)
13753 struct drm_i915_private *dev_priv = dev->dev_private;
13755 struct intel_crtc *crtc;
13756 struct intel_encoder *encoder;
13759 intel_modeset_readout_hw_state(dev);
13762 * Now that we have the config, copy it to each CRTC struct
13763 * Note that this could go away if we move to using crtc_config
13764 * checking everywhere.
13766 for_each_intel_crtc(dev, crtc) {
13767 if (crtc->active && i915.fastboot) {
13768 intel_mode_from_pipe_config(&crtc->base.mode,
13770 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13771 crtc->base.base.id);
13772 drm_mode_debug_printmodeline(&crtc->base.mode);
13776 /* HW state is read out, now we need to sanitize this mess. */
13777 for_each_intel_encoder(dev, encoder) {
13778 intel_sanitize_encoder(encoder);
13781 for_each_pipe(dev_priv, pipe) {
13782 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13783 intel_sanitize_crtc(crtc);
13784 intel_dump_pipe_config(crtc, crtc->config,
13785 "[setup_hw_state]");
13788 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13789 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13791 if (!pll->on || pll->active)
13794 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13796 pll->disable(dev_priv, pll);
13801 skl_wm_get_hw_state(dev);
13802 else if (HAS_PCH_SPLIT(dev))
13803 ilk_wm_get_hw_state(dev);
13805 if (force_restore) {
13806 i915_redisable_vga(dev);
13809 * We need to use raw interfaces for restoring state to avoid
13810 * checking (bogus) intermediate states.
13812 for_each_pipe(dev_priv, pipe) {
13813 struct drm_crtc *crtc =
13814 dev_priv->pipe_to_crtc_mapping[pipe];
13816 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13817 crtc->primary->fb);
13820 intel_modeset_update_staged_output_state(dev);
13823 intel_modeset_check_state(dev);
13826 void intel_modeset_gem_init(struct drm_device *dev)
13828 struct drm_i915_private *dev_priv = dev->dev_private;
13829 struct drm_crtc *c;
13830 struct drm_i915_gem_object *obj;
13832 mutex_lock(&dev->struct_mutex);
13833 intel_init_gt_powersave(dev);
13834 mutex_unlock(&dev->struct_mutex);
13837 * There may be no VBT; and if the BIOS enabled SSC we can
13838 * just keep using it to avoid unnecessary flicker. Whereas if the
13839 * BIOS isn't using it, don't assume it will work even if the VBT
13840 * indicates as much.
13842 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13843 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13846 intel_modeset_init_hw(dev);
13848 intel_setup_overlay(dev);
13851 * Make sure any fbs we allocated at startup are properly
13852 * pinned & fenced. When we do the allocation it's too early
13855 mutex_lock(&dev->struct_mutex);
13856 for_each_crtc(dev, c) {
13857 obj = intel_fb_obj(c->primary->fb);
13861 if (intel_pin_and_fence_fb_obj(c->primary,
13864 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13865 to_intel_crtc(c)->pipe);
13866 drm_framebuffer_unreference(c->primary->fb);
13867 c->primary->fb = NULL;
13868 update_state_fb(c->primary);
13871 mutex_unlock(&dev->struct_mutex);
13873 intel_backlight_register(dev);
13876 void intel_connector_unregister(struct intel_connector *intel_connector)
13878 struct drm_connector *connector = &intel_connector->base;
13880 intel_panel_destroy_backlight(connector);
13881 drm_connector_unregister(connector);
13884 void intel_modeset_cleanup(struct drm_device *dev)
13886 struct drm_i915_private *dev_priv = dev->dev_private;
13887 struct drm_connector *connector;
13889 intel_disable_gt_powersave(dev);
13891 intel_backlight_unregister(dev);
13894 * Interrupts and polling as the first thing to avoid creating havoc.
13895 * Too much stuff here (turning of connectors, ...) would
13896 * experience fancy races otherwise.
13898 intel_irq_uninstall(dev_priv);
13901 * Due to the hpd irq storm handling the hotplug work can re-arm the
13902 * poll handlers. Hence disable polling after hpd handling is shut down.
13904 drm_kms_helper_poll_fini(dev);
13906 mutex_lock(&dev->struct_mutex);
13908 intel_unregister_dsm_handler();
13910 intel_fbc_disable(dev);
13912 mutex_unlock(&dev->struct_mutex);
13914 /* flush any delayed tasks or pending work */
13915 flush_scheduled_work();
13917 /* destroy the backlight and sysfs files before encoders/connectors */
13918 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13919 struct intel_connector *intel_connector;
13921 intel_connector = to_intel_connector(connector);
13922 intel_connector->unregister(intel_connector);
13925 drm_mode_config_cleanup(dev);
13927 intel_cleanup_overlay(dev);
13929 mutex_lock(&dev->struct_mutex);
13930 intel_cleanup_gt_powersave(dev);
13931 mutex_unlock(&dev->struct_mutex);
13935 * Return which encoder is currently attached for connector.
13937 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13939 return &intel_attached_encoder(connector)->base;
13942 void intel_connector_attach_encoder(struct intel_connector *connector,
13943 struct intel_encoder *encoder)
13945 connector->encoder = encoder;
13946 drm_mode_connector_attach_encoder(&connector->base,
13951 * set vga decode state - true == enable VGA decode
13953 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13955 struct drm_i915_private *dev_priv = dev->dev_private;
13956 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13959 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13960 DRM_ERROR("failed to read control word\n");
13964 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13968 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13970 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13972 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13973 DRM_ERROR("failed to write control word\n");
13980 struct intel_display_error_state {
13982 u32 power_well_driver;
13984 int num_transcoders;
13986 struct intel_cursor_error_state {
13991 } cursor[I915_MAX_PIPES];
13993 struct intel_pipe_error_state {
13994 bool power_domain_on;
13997 } pipe[I915_MAX_PIPES];
13999 struct intel_plane_error_state {
14007 } plane[I915_MAX_PIPES];
14009 struct intel_transcoder_error_state {
14010 bool power_domain_on;
14011 enum transcoder cpu_transcoder;
14024 struct intel_display_error_state *
14025 intel_display_capture_error_state(struct drm_device *dev)
14027 struct drm_i915_private *dev_priv = dev->dev_private;
14028 struct intel_display_error_state *error;
14029 int transcoders[] = {
14037 if (INTEL_INFO(dev)->num_pipes == 0)
14040 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14044 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14045 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14047 for_each_pipe(dev_priv, i) {
14048 error->pipe[i].power_domain_on =
14049 __intel_display_power_is_enabled(dev_priv,
14050 POWER_DOMAIN_PIPE(i));
14051 if (!error->pipe[i].power_domain_on)
14054 error->cursor[i].control = I915_READ(CURCNTR(i));
14055 error->cursor[i].position = I915_READ(CURPOS(i));
14056 error->cursor[i].base = I915_READ(CURBASE(i));
14058 error->plane[i].control = I915_READ(DSPCNTR(i));
14059 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14060 if (INTEL_INFO(dev)->gen <= 3) {
14061 error->plane[i].size = I915_READ(DSPSIZE(i));
14062 error->plane[i].pos = I915_READ(DSPPOS(i));
14064 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14065 error->plane[i].addr = I915_READ(DSPADDR(i));
14066 if (INTEL_INFO(dev)->gen >= 4) {
14067 error->plane[i].surface = I915_READ(DSPSURF(i));
14068 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14071 error->pipe[i].source = I915_READ(PIPESRC(i));
14073 if (HAS_GMCH_DISPLAY(dev))
14074 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14077 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14078 if (HAS_DDI(dev_priv->dev))
14079 error->num_transcoders++; /* Account for eDP. */
14081 for (i = 0; i < error->num_transcoders; i++) {
14082 enum transcoder cpu_transcoder = transcoders[i];
14084 error->transcoder[i].power_domain_on =
14085 __intel_display_power_is_enabled(dev_priv,
14086 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14087 if (!error->transcoder[i].power_domain_on)
14090 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14092 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14093 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14094 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14095 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14096 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14097 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14098 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14104 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14107 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14108 struct drm_device *dev,
14109 struct intel_display_error_state *error)
14111 struct drm_i915_private *dev_priv = dev->dev_private;
14117 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14118 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14119 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14120 error->power_well_driver);
14121 for_each_pipe(dev_priv, i) {
14122 err_printf(m, "Pipe [%d]:\n", i);
14123 err_printf(m, " Power: %s\n",
14124 error->pipe[i].power_domain_on ? "on" : "off");
14125 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14126 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14128 err_printf(m, "Plane [%d]:\n", i);
14129 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14130 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14131 if (INTEL_INFO(dev)->gen <= 3) {
14132 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14133 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14135 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14136 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14137 if (INTEL_INFO(dev)->gen >= 4) {
14138 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14139 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14142 err_printf(m, "Cursor [%d]:\n", i);
14143 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14144 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14145 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14148 for (i = 0; i < error->num_transcoders; i++) {
14149 err_printf(m, "CPU transcoder: %c\n",
14150 transcoder_name(error->transcoder[i].cpu_transcoder));
14151 err_printf(m, " Power: %s\n",
14152 error->transcoder[i].power_domain_on ? "on" : "off");
14153 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14154 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14155 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14156 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14157 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14158 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14159 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14163 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14165 struct intel_crtc *crtc;
14167 for_each_intel_crtc(dev, crtc) {
14168 struct intel_unpin_work *work;
14170 spin_lock_irq(&dev->event_lock);
14172 work = crtc->unpin_work;
14174 if (work && work->event &&
14175 work->event->base.file_priv == file) {
14176 kfree(work->event);
14177 work->event = NULL;
14180 spin_unlock_irq(&dev->event_lock);