drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static inline u32 /* units of 100MHz */
 102 intel_fdi_link_freq(struct drm_device *dev)
 103 {
 104         if (IS_GEN5(dev)) {
 105                 struct drm_i915_private *dev_priv = dev->dev_private;
 106                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 107         } else
 108                 return 27;
 109 }
 110
 111 static const intel_limit_t intel_limits_i8xx_dvo = {
 112         .dot = { .min = 25000, .max = 350000 },
 113         .vco = { .min = 930000, .max = 1400000 },
 114         .n = { .min = 3, .max = 16 },
 115         .m = { .min = 96, .max = 140 },
 116         .m1 = { .min = 18, .max = 26 },
 117         .m2 = { .min = 6, .max = 16 },
 118         .p = { .min = 4, .max = 128 },
 119         .p1 = { .min = 2, .max = 33 },
 120         .p2 = { .dot_limit = 165000,
 121                 .p2_slow = 4, .p2_fast = 2 },
 122         .find_pll = intel_find_best_PLL,
 123 };
 124
 125 static const intel_limit_t intel_limits_i8xx_lvds = {
 126         .dot = { .min = 25000, .max = 350000 },
 127         .vco = { .min = 930000, .max = 1400000 },
 128         .n = { .min = 3, .max = 16 },
 129         .m = { .min = 96, .max = 140 },
 130         .m1 = { .min = 18, .max = 26 },
 131         .m2 = { .min = 6, .max = 16 },
 132         .p = { .min = 4, .max = 128 },
 133         .p1 = { .min = 1, .max = 6 },
 134         .p2 = { .dot_limit = 165000,
 135                 .p2_slow = 14, .p2_fast = 7 },
 136         .find_pll = intel_find_best_PLL,
 137 };
 138
 139 static const intel_limit_t intel_limits_i9xx_sdvo = {
 140         .dot = { .min = 20000, .max = 400000 },
 141         .vco = { .min = 1400000, .max = 2800000 },
 142         .n = { .min = 1, .max = 6 },
 143         .m = { .min = 70, .max = 120 },
 144         .m1 = { .min = 10, .max = 22 },
 145         .m2 = { .min = 5, .max = 9 },
 146         .p = { .min = 5, .max = 80 },
 147         .p1 = { .min = 1, .max = 8 },
 148         .p2 = { .dot_limit = 200000,
 149                 .p2_slow = 10, .p2_fast = 5 },
 150         .find_pll = intel_find_best_PLL,
 151 };
 152
 153 static const intel_limit_t intel_limits_i9xx_lvds = {
 154         .dot = { .min = 20000, .max = 400000 },
 155         .vco = { .min = 1400000, .max = 2800000 },
 156         .n = { .min = 1, .max = 6 },
 157         .m = { .min = 70, .max = 120 },
 158         .m1 = { .min = 10, .max = 22 },
 159         .m2 = { .min = 5, .max = 9 },
 160         .p = { .min = 7, .max = 98 },
 161         .p1 = { .min = 1, .max = 8 },
 162         .p2 = { .dot_limit = 112000,
 163                 .p2_slow = 14, .p2_fast = 7 },
 164         .find_pll = intel_find_best_PLL,
 165 };
 166
 167
 168 static const intel_limit_t intel_limits_g4x_sdvo = {
 169         .dot = { .min = 25000, .max = 270000 },
 170         .vco = { .min = 1750000, .max = 3500000},
 171         .n = { .min = 1, .max = 4 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 10, .max = 30 },
 176         .p1 = { .min = 1, .max = 3},
 177         .p2 = { .dot_limit = 270000,
 178                 .p2_slow = 10,
 179                 .p2_fast = 10
 180         },
 181         .find_pll = intel_g4x_find_best_PLL,
 182 };
 183
 184 static const intel_limit_t intel_limits_g4x_hdmi = {
 185         .dot = { .min = 22000, .max = 400000 },
 186         .vco = { .min = 1750000, .max = 3500000},
 187         .n = { .min = 1, .max = 4 },
 188         .m = { .min = 104, .max = 138 },
 189         .m1 = { .min = 16, .max = 23 },
 190         .m2 = { .min = 5, .max = 11 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8},
 193         .p2 = { .dot_limit = 165000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195         .find_pll = intel_g4x_find_best_PLL,
 196 };
 197
 198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 199         .dot = { .min = 20000, .max = 115000 },
 200         .vco = { .min = 1750000, .max = 3500000 },
 201         .n = { .min = 1, .max = 3 },
 202         .m = { .min = 104, .max = 138 },
 203         .m1 = { .min = 17, .max = 23 },
 204         .m2 = { .min = 5, .max = 11 },
 205         .p = { .min = 28, .max = 112 },
 206         .p1 = { .min = 2, .max = 8 },
 207         .p2 = { .dot_limit = 0,
 208                 .p2_slow = 14, .p2_fast = 14
 209         },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 214         .dot = { .min = 80000, .max = 224000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 14, .max = 42 },
 221         .p1 = { .min = 2, .max = 6 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 7, .p2_fast = 7
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_display_port = {
 229         .dot = { .min = 161670, .max = 227000 },
 230         .vco = { .min = 1750000, .max = 3500000},
 231         .n = { .min = 1, .max = 2 },
 232         .m = { .min = 97, .max = 108 },
 233         .m1 = { .min = 0x10, .max = 0x12 },
 234         .m2 = { .min = 0x05, .max = 0x06 },
 235         .p = { .min = 10, .max = 20 },
 236         .p1 = { .min = 1, .max = 2},
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 10, .p2_fast = 10 },
 239         .find_pll = intel_find_pll_g4x_dp,
 240 };
 241
 242 static const intel_limit_t intel_limits_pineview_sdvo = {
 243         .dot = { .min = 20000, .max = 400000},
 244         .vco = { .min = 1700000, .max = 3500000 },
 245         /* Pineview's Ncounter is a ring counter */
 246         .n = { .min = 3, .max = 6 },
 247         .m = { .min = 2, .max = 256 },
 248         /* Pineview only has one combined m divider, which we treat as m2. */
 249         .m1 = { .min = 0, .max = 0 },
 250         .m2 = { .min = 0, .max = 254 },
 251         .p = { .min = 5, .max = 80 },
 252         .p1 = { .min = 1, .max = 8 },
 253         .p2 = { .dot_limit = 200000,
 254                 .p2_slow = 10, .p2_fast = 5 },
 255         .find_pll = intel_find_best_PLL,
 256 };
 257
 258 static const intel_limit_t intel_limits_pineview_lvds = {
 259         .dot = { .min = 20000, .max = 400000 },
 260         .vco = { .min = 1700000, .max = 3500000 },
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         .m1 = { .min = 0, .max = 0 },
 264         .m2 = { .min = 0, .max = 254 },
 265         .p = { .min = 7, .max = 112 },
 266         .p1 = { .min = 1, .max = 8 },
 267         .p2 = { .dot_limit = 112000,
 268                 .p2_slow = 14, .p2_fast = 14 },
 269         .find_pll = intel_find_best_PLL,
 270 };
 271
 272 /* Ironlake / Sandybridge
 273  *
 274  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 275  * the range value for them is (actual_value - 2).
 276  */
 277 static const intel_limit_t intel_limits_ironlake_dac = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 1760000, .max = 3510000 },
 280         .n = { .min = 1, .max = 5 },
 281         .m = { .min = 79, .max = 127 },
 282         .m1 = { .min = 12, .max = 22 },
 283         .m2 = { .min = 5, .max = 9 },
 284         .p = { .min = 5, .max = 80 },
 285         .p1 = { .min = 1, .max = 8 },
 286         .p2 = { .dot_limit = 225000,
 287                 .p2_slow = 10, .p2_fast = 5 },
 288         .find_pll = intel_g4x_find_best_PLL,
 289 };
 290
 291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 292         .dot = { .min = 25000, .max = 350000 },
 293         .vco = { .min = 1760000, .max = 3510000 },
 294         .n = { .min = 1, .max = 3 },
 295         .m = { .min = 79, .max = 118 },
 296         .m1 = { .min = 12, .max = 22 },
 297         .m2 = { .min = 5, .max = 9 },
 298         .p = { .min = 28, .max = 112 },
 299         .p1 = { .min = 2, .max = 8 },
 300         .p2 = { .dot_limit = 225000,
 301                 .p2_slow = 14, .p2_fast = 14 },
 302         .find_pll = intel_g4x_find_best_PLL,
 303 };
 304
 305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 3 },
 309         .m = { .min = 79, .max = 127 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 14, .max = 56 },
 313         .p1 = { .min = 2, .max = 8 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 7, .p2_fast = 7 },
 316         .find_pll = intel_g4x_find_best_PLL,
 317 };
 318
 319 /* LVDS 100mhz refclk limits. */
 320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 2 },
 324         .m = { .min = 79, .max = 126 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 14, .p2_fast = 14 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 335         .dot = { .min = 25000, .max = 350000 },
 336         .vco = { .min = 1760000, .max = 3510000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 79, .max = 126 },
 339         .m1 = { .min = 12, .max = 22 },
 340         .m2 = { .min = 5, .max = 9 },
 341         .p = { .min = 14, .max = 42 },
 342         .p1 = { .min = 2, .max = 6 },
 343         .p2 = { .dot_limit = 225000,
 344                 .p2_slow = 7, .p2_fast = 7 },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 static const intel_limit_t intel_limits_ironlake_display_port = {
 349         .dot = { .min = 25000, .max = 350000 },
 350         .vco = { .min = 1760000, .max = 3510000},
 351         .n = { .min = 1, .max = 2 },
 352         .m = { .min = 81, .max = 90 },
 353         .m1 = { .min = 12, .max = 22 },
 354         .m2 = { .min = 5, .max = 9 },
 355         .p = { .min = 10, .max = 20 },
 356         .p1 = { .min = 1, .max = 2},
 357         .p2 = { .dot_limit = 0,
 358                 .p2_slow = 10, .p2_fast = 10 },
 359         .find_pll = intel_find_pll_ironlake_dp,
 360 };
 361
 362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 363 {
 364         unsigned long flags;
 365         u32 val = 0;
 366
 367         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 368         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 369                 DRM_ERROR("DPIO idle wait timed out\n");
 370                 goto out_unlock;
 371         }
 372
 373         I915_WRITE(DPIO_REG, reg);
 374         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 375                    DPIO_BYTE);
 376         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 377                 DRM_ERROR("DPIO read wait timed out\n");
 378                 goto out_unlock;
 379         }
 380         val = I915_READ(DPIO_DATA);
 381
 382 out_unlock:
 383         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 384         return val;
 385 }
 386
 387 static void vlv_init_dpio(struct drm_device *dev)
 388 {
 389         struct drm_i915_private *dev_priv = dev->dev_private;
 390
 391         /* Reset the DPIO config */
 392         I915_WRITE(DPIO_CTL, 0);
 393         POSTING_READ(DPIO_CTL);
 394         I915_WRITE(DPIO_CTL, 1);
 395         POSTING_READ(DPIO_CTL);
 396 }
 397
 398 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 399 {
 400         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 401         return 1;
 402 }
 403
 404 static const struct dmi_system_id intel_dual_link_lvds[] = {
 405         {
 406                 .callback = intel_dual_link_lvds_callback,
 407                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 408                 .matches = {
 409                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 410                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 411                 },
 412         },
 413         { }     /* terminating entry */
 414 };
 415
 416 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 417                               unsigned int reg)
 418 {
 419         unsigned int val;
 420
 421         /* use the module option value if specified */
 422         if (i915_lvds_channel_mode > 0)
 423                 return i915_lvds_channel_mode == 2;
 424
 425         if (dmi_check_system(intel_dual_link_lvds))
 426                 return true;
 427
 428         if (dev_priv->lvds_val)
 429                 val = dev_priv->lvds_val;
 430         else {
 431                 /* BIOS should set the proper LVDS register value at boot, but
 432                  * in reality, it doesn't set the value when the lid is closed;
 433                  * we need to check "the value to be set" in VBT when LVDS
 434                  * register is uninitialized.
 435                  */
 436                 val = I915_READ(reg);
 437                 if (!(val & ~LVDS_DETECTED))
 438                         val = dev_priv->bios_lvds_val;
 439                 dev_priv->lvds_val = val;
 440         }
 441         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 442 }
 443
 444 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 445                                                 int refclk)
 446 {
 447         struct drm_device *dev = crtc->dev;
 448         struct drm_i915_private *dev_priv = dev->dev_private;
 449         const intel_limit_t *limit;
 450
 451         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 452                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 453                         /* LVDS dual channel */
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_dual_lvds;
 458                 } else {
 459                         if (refclk == 100000)
 460                                 limit = &intel_limits_ironlake_single_lvds_100m;
 461                         else
 462                                 limit = &intel_limits_ironlake_single_lvds;
 463                 }
 464         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 465                         HAS_eDP)
 466                 limit = &intel_limits_ironlake_display_port;
 467         else
 468                 limit = &intel_limits_ironlake_dac;
 469
 470         return limit;
 471 }
 472
 473 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 474 {
 475         struct drm_device *dev = crtc->dev;
 476         struct drm_i915_private *dev_priv = dev->dev_private;
 477         const intel_limit_t *limit;
 478
 479         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 480                 if (is_dual_link_lvds(dev_priv, LVDS))
 481                         /* LVDS with dual channel */
 482                         limit = &intel_limits_g4x_dual_channel_lvds;
 483                 else
 484                         /* LVDS with dual channel */
 485                         limit = &intel_limits_g4x_single_channel_lvds;
 486         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 487                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 488                 limit = &intel_limits_g4x_hdmi;
 489         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 490                 limit = &intel_limits_g4x_sdvo;
 491         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 492                 limit = &intel_limits_g4x_display_port;
 493         } else /* The option is for other outputs */
 494                 limit = &intel_limits_i9xx_sdvo;
 495
 496         return limit;
 497 }
 498
 499 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 500 {
 501         struct drm_device *dev = crtc->dev;
 502         const intel_limit_t *limit;
 503
 504         if (HAS_PCH_SPLIT(dev))
 505                 limit = intel_ironlake_limit(crtc, refclk);
 506         else if (IS_G4X(dev)) {
 507                 limit = intel_g4x_limit(crtc);
 508         } else if (IS_PINEVIEW(dev)) {
 509                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 510                         limit = &intel_limits_pineview_lvds;
 511                 else
 512                         limit = &intel_limits_pineview_sdvo;
 513         } else if (!IS_GEN2(dev)) {
 514                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 515                         limit = &intel_limits_i9xx_lvds;
 516                 else
 517                         limit = &intel_limits_i9xx_sdvo;
 518         } else {
 519                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 520                         limit = &intel_limits_i8xx_lvds;
 521                 else
 522                         limit = &intel_limits_i8xx_dvo;
 523         }
 524         return limit;
 525 }
 526
 527 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 528 static void pineview_clock(int refclk, intel_clock_t *clock)
 529 {
 530         clock->m = clock->m2 + 2;
 531         clock->p = clock->p1 * clock->p2;
 532         clock->vco = refclk * clock->m / clock->n;
 533         clock->dot = clock->vco / clock->p;
 534 }
 535
 536 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 537 {
 538         if (IS_PINEVIEW(dev)) {
 539                 pineview_clock(refclk, clock);
 540                 return;
 541         }
 542         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 543         clock->p = clock->p1 * clock->p2;
 544         clock->vco = refclk * clock->m / (clock->n + 2);
 545         clock->dot = clock->vco / clock->p;
 546 }
 547
 548 /**
 549  * Returns whether any output on the specified pipe is of the specified type
 550  */
 551 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 552 {
 553         struct drm_device *dev = crtc->dev;
 554         struct drm_mode_config *mode_config = &dev->mode_config;
 555         struct intel_encoder *encoder;
 556
 557         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 558                 if (encoder->base.crtc == crtc && encoder->type == type)
 559                         return true;
 560
 561         return false;
 562 }
 563
 564 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 565 /**
 566  * Returns whether the given set of divisors are valid for a given refclk with
 567  * the given connectors.
 568  */
 569
 570 static bool intel_PLL_is_valid(struct drm_device *dev,
 571                                const intel_limit_t *limit,
 572                                const intel_clock_t *clock)
 573 {
 574         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 575                 INTELPllInvalid("p1 out of range\n");
 576         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 577                 INTELPllInvalid("p out of range\n");
 578         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 579                 INTELPllInvalid("m2 out of range\n");
 580         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 581                 INTELPllInvalid("m1 out of range\n");
 582         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 583                 INTELPllInvalid("m1 <= m2\n");
 584         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 585                 INTELPllInvalid("m out of range\n");
 586         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 587                 INTELPllInvalid("n out of range\n");
 588         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 589                 INTELPllInvalid("vco out of range\n");
 590         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 591          * connector, etc., rather than just a single range.
 592          */
 593         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 594                 INTELPllInvalid("dot out of range\n");
 595
 596         return true;
 597 }
 598
 599 static bool
 600 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 601                     int target, int refclk, intel_clock_t *match_clock,
 602                     intel_clock_t *best_clock)
 603
 604 {
 605         struct drm_device *dev = crtc->dev;
 606         struct drm_i915_private *dev_priv = dev->dev_private;
 607         intel_clock_t clock;
 608         int err = target;
 609
 610         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 611             (I915_READ(LVDS)) != 0) {
 612                 /*
 613                  * For LVDS, if the panel is on, just rely on its current
 614                  * settings for dual-channel.  We haven't figured out how to
 615                  * reliably set up different single/dual channel state, if we
 616                  * even can.
 617                  */
 618                 if (is_dual_link_lvds(dev_priv, LVDS))
 619                         clock.p2 = limit->p2.p2_fast;
 620                 else
 621                         clock.p2 = limit->p2.p2_slow;
 622         } else {
 623                 if (target < limit->p2.dot_limit)
 624                         clock.p2 = limit->p2.p2_slow;
 625                 else
 626                         clock.p2 = limit->p2.p2_fast;
 627         }
 628
 629         memset(best_clock, 0, sizeof(*best_clock));
 630
 631         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 632              clock.m1++) {
 633                 for (clock.m2 = limit->m2.min;
 634                      clock.m2 <= limit->m2.max; clock.m2++) {
 635                         /* m1 is always 0 in Pineview */
 636                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 637                                 break;
 638                         for (clock.n = limit->n.min;
 639                              clock.n <= limit->n.max; clock.n++) {
 640                                 for (clock.p1 = limit->p1.min;
 641                                         clock.p1 <= limit->p1.max; clock.p1++) {
 642                                         int this_err;
 643
 644                                         intel_clock(dev, refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648                                         if (match_clock &&
 649                                             clock.p != match_clock->p)
 650                                                 continue;
 651
 652                                         this_err = abs(clock.dot - target);
 653                                         if (this_err < err) {
 654                                                 *best_clock = clock;
 655                                                 err = this_err;
 656                                         }
 657                                 }
 658                         }
 659                 }
 660         }
 661
 662         return (err != target);
 663 }
 664
 665 static bool
 666 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 667                         int target, int refclk, intel_clock_t *match_clock,
 668                         intel_clock_t *best_clock)
 669 {
 670         struct drm_device *dev = crtc->dev;
 671         struct drm_i915_private *dev_priv = dev->dev_private;
 672         intel_clock_t clock;
 673         int max_n;
 674         bool found;
 675         /* approximately equals target * 0.00585 */
 676         int err_most = (target >> 8) + (target >> 9);
 677         found = false;
 678
 679         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 680                 int lvds_reg;
 681
 682                 if (HAS_PCH_SPLIT(dev))
 683                         lvds_reg = PCH_LVDS;
 684                 else
 685                         lvds_reg = LVDS;
 686                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 687                     LVDS_CLKB_POWER_UP)
 688                         clock.p2 = limit->p2.p2_fast;
 689                 else
 690                         clock.p2 = limit->p2.p2_slow;
 691         } else {
 692                 if (target < limit->p2.dot_limit)
 693                         clock.p2 = limit->p2.p2_slow;
 694                 else
 695                         clock.p2 = limit->p2.p2_fast;
 696         }
 697
 698         memset(best_clock, 0, sizeof(*best_clock));
 699         max_n = limit->n.max;
 700         /* based on hardware requirement, prefer smaller n to precision */
 701         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 702                 /* based on hardware requirement, prefere larger m1,m2 */
 703                 for (clock.m1 = limit->m1.max;
 704                      clock.m1 >= limit->m1.min; clock.m1--) {
 705                         for (clock.m2 = limit->m2.max;
 706                              clock.m2 >= limit->m2.min; clock.m2--) {
 707                                 for (clock.p1 = limit->p1.max;
 708                                      clock.p1 >= limit->p1.min; clock.p1--) {
 709                                         int this_err;
 710
 711                                         intel_clock(dev, refclk, &clock);
 712                                         if (!intel_PLL_is_valid(dev, limit,
 713                                                                 &clock))
 714                                                 continue;
 715                                         if (match_clock &&
 716                                             clock.p != match_clock->p)
 717                                                 continue;
 718
 719                                         this_err = abs(clock.dot - target);
 720                                         if (this_err < err_most) {
 721                                                 *best_clock = clock;
 722                                                 err_most = this_err;
 723                                                 max_n = clock.n;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730         return found;
 731 }
 732
 733 static bool
 734 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 735                            int target, int refclk, intel_clock_t *match_clock,
 736                            intel_clock_t *best_clock)
 737 {
 738         struct drm_device *dev = crtc->dev;
 739         intel_clock_t clock;
 740
 741         if (target < 200000) {
 742                 clock.n = 1;
 743                 clock.p1 = 2;
 744                 clock.p2 = 10;
 745                 clock.m1 = 12;
 746                 clock.m2 = 9;
 747         } else {
 748                 clock.n = 2;
 749                 clock.p1 = 1;
 750                 clock.p2 = 10;
 751                 clock.m1 = 14;
 752                 clock.m2 = 8;
 753         }
 754         intel_clock(dev, refclk, &clock);
 755         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 756         return true;
 757 }
 758
 759 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 760 static bool
 761 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 762                       int target, int refclk, intel_clock_t *match_clock,
 763                       intel_clock_t *best_clock)
 764 {
 765         intel_clock_t clock;
 766         if (target < 200000) {
 767                 clock.p1 = 2;
 768                 clock.p2 = 10;
 769                 clock.n = 2;
 770                 clock.m1 = 23;
 771                 clock.m2 = 8;
 772         } else {
 773                 clock.p1 = 1;
 774                 clock.p2 = 10;
 775                 clock.n = 1;
 776                 clock.m1 = 14;
 777                 clock.m2 = 2;
 778         }
 779         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 780         clock.p = (clock.p1 * clock.p2);
 781         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 782         clock.vco = 0;
 783         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 784         return true;
 785 }
 786
 787 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 788 {
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790         u32 frame, frame_reg = PIPEFRAME(pipe);
 791
 792         frame = I915_READ(frame_reg);
 793
 794         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 795                 DRM_DEBUG_KMS("vblank wait timed out\n");
 796 }
 797
 798 /**
 799  * intel_wait_for_vblank - wait for vblank on a given pipe
 800  * @dev: drm device
 801  * @pipe: pipe to wait for
 802  *
 803  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 804  * mode setting code.
 805  */
 806 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 807 {
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         int pipestat_reg = PIPESTAT(pipe);
 810
 811         if (INTEL_INFO(dev)->gen >= 5) {
 812                 ironlake_wait_for_vblank(dev, pipe);
 813                 return;
 814         }
 815
 816         /* Clear existing vblank status. Note this will clear any other
 817          * sticky status fields as well.
 818          *
 819          * This races with i915_driver_irq_handler() with the result
 820          * that either function could miss a vblank event.  Here it is not
 821          * fatal, as we will either wait upon the next vblank interrupt or
 822          * timeout.  Generally speaking intel_wait_for_vblank() is only
 823          * called during modeset at which time the GPU should be idle and
 824          * should *not* be performing page flips and thus not waiting on
 825          * vblanks...
 826          * Currently, the result of us stealing a vblank from the irq
 827          * handler is that a single frame will be skipped during swapbuffers.
 828          */
 829         I915_WRITE(pipestat_reg,
 830                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 831
 832         /* Wait for vblank interrupt bit to set */
 833         if (wait_for(I915_READ(pipestat_reg) &
 834                      PIPE_VBLANK_INTERRUPT_STATUS,
 835                      50))
 836                 DRM_DEBUG_KMS("vblank wait timed out\n");
 837 }
 838
 839 /*
 840  * intel_wait_for_pipe_off - wait for pipe to turn off
 841  * @dev: drm device
 842  * @pipe: pipe to wait for
 843  *
 844  * After disabling a pipe, we can't wait for vblank in the usual way,
 845  * spinning on the vblank interrupt status bit, since we won't actually
 846  * see an interrupt when the pipe is disabled.
 847  *
 848  * On Gen4 and above:
 849  *   wait for the pipe register state bit to turn off
 850  *
 851  * Otherwise:
 852  *   wait for the display line value to settle (it usually
 853  *   ends up stopping at the start of the next frame).
 854  *
 855  */
 856 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 857 {
 858         struct drm_i915_private *dev_priv = dev->dev_private;
 859
 860         if (INTEL_INFO(dev)->gen >= 4) {
 861                 int reg = PIPECONF(pipe);
 862
 863                 /* Wait for the Pipe State to go off */
 864                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 865                              100))
 866                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 867         } else {
 868                 u32 last_line, line_mask;
 869                 int reg = PIPEDSL(pipe);
 870                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 871
 872                 if (IS_GEN2(dev))
 873                         line_mask = DSL_LINEMASK_GEN2;
 874                 else
 875                         line_mask = DSL_LINEMASK_GEN3;
 876
 877                 /* Wait for the display line to settle */
 878                 do {
 879                         last_line = I915_READ(reg) & line_mask;
 880                         mdelay(5);
 881                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 882                          time_after(timeout, jiffies));
 883                 if (time_after(jiffies, timeout))
 884                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 885         }
 886 }
 887
 888 static const char *state_string(bool enabled)
 889 {
 890         return enabled ? "on" : "off";
 891 }
 892
 893 /* Only for pre-ILK configs */
 894 static void assert_pll(struct drm_i915_private *dev_priv,
 895                        enum pipe pipe, bool state)
 896 {
 897         int reg;
 898         u32 val;
 899         bool cur_state;
 900
 901         reg = DPLL(pipe);
 902         val = I915_READ(reg);
 903         cur_state = !!(val & DPLL_VCO_ENABLE);
 904         WARN(cur_state != state,
 905              "PLL state assertion failure (expected %s, current %s)\n",
 906              state_string(state), state_string(cur_state));
 907 }
 908 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 909 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 910
 911 /* For ILK+ */
 912 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 913                            struct intel_crtc *intel_crtc, bool state)
 914 {
 915         int reg;
 916         u32 val;
 917         bool cur_state;
 918
 919         if (!intel_crtc->pch_pll) {
 920                 WARN(1, "asserting PCH PLL enabled with no PLL\n");
 921                 return;
 922         }
 923
 924         if (HAS_PCH_CPT(dev_priv->dev)) {
 925                 u32 pch_dpll;
 926
 927                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 928
 929                 /* Make sure the selected PLL is enabled to the transcoder */
 930                 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
 931                      "transcoder %d PLL not enabled\n", intel_crtc->pipe);
 932         }
 933
 934         reg = intel_crtc->pch_pll->pll_reg;
 935         val = I915_READ(reg);
 936         cur_state = !!(val & DPLL_VCO_ENABLE);
 937         WARN(cur_state != state,
 938              "PCH PLL state assertion failure (expected %s, current %s)\n",
 939              state_string(state), state_string(cur_state));
 940 }
 941 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 942 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 943
 944 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 945                           enum pipe pipe, bool state)
 946 {
 947         int reg;
 948         u32 val;
 949         bool cur_state;
 950
 951         reg = FDI_TX_CTL(pipe);
 952         val = I915_READ(reg);
 953         cur_state = !!(val & FDI_TX_ENABLE);
 954         WARN(cur_state != state,
 955              "FDI TX state assertion failure (expected %s, current %s)\n",
 956              state_string(state), state_string(cur_state));
 957 }
 958 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 959 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 960
 961 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 962                           enum pipe pipe, bool state)
 963 {
 964         int reg;
 965         u32 val;
 966         bool cur_state;
 967
 968         reg = FDI_RX_CTL(pipe);
 969         val = I915_READ(reg);
 970         cur_state = !!(val & FDI_RX_ENABLE);
 971         WARN(cur_state != state,
 972              "FDI RX state assertion failure (expected %s, current %s)\n",
 973              state_string(state), state_string(cur_state));
 974 }
 975 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 976 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 977
 978 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 979                                       enum pipe pipe)
 980 {
 981         int reg;
 982         u32 val;
 983
 984         /* ILK FDI PLL is always enabled */
 985         if (dev_priv->info->gen == 5)
 986                 return;
 987
 988         reg = FDI_TX_CTL(pipe);
 989         val = I915_READ(reg);
 990         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 991 }
 992
 993 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 994                                       enum pipe pipe)
 995 {
 996         int reg;
 997         u32 val;
 998
 999         reg = FDI_RX_CTL(pipe);
1000         val = I915_READ(reg);
1001         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1002 }
1003
1004 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1005                                   enum pipe pipe)
1006 {
1007         int pp_reg, lvds_reg;
1008         u32 val;
1009         enum pipe panel_pipe = PIPE_A;
1010         bool locked = true;
1011
1012         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1013                 pp_reg = PCH_PP_CONTROL;
1014                 lvds_reg = PCH_LVDS;
1015         } else {
1016                 pp_reg = PP_CONTROL;
1017                 lvds_reg = LVDS;
1018         }
1019
1020         val = I915_READ(pp_reg);
1021         if (!(val & PANEL_POWER_ON) ||
1022             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1023                 locked = false;
1024
1025         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1026                 panel_pipe = PIPE_B;
1027
1028         WARN(panel_pipe == pipe && locked,
1029              "panel assertion failure, pipe %c regs locked\n",
1030              pipe_name(pipe));
1031 }
1032
1033 void assert_pipe(struct drm_i915_private *dev_priv,
1034                  enum pipe pipe, bool state)
1035 {
1036         int reg;
1037         u32 val;
1038         bool cur_state;
1039
1040         /* if we need the pipe A quirk it must be always on */
1041         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1042                 state = true;
1043
1044         reg = PIPECONF(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & PIPECONF_ENABLE);
1047         WARN(cur_state != state,
1048              "pipe %c assertion failure (expected %s, current %s)\n",
1049              pipe_name(pipe), state_string(state), state_string(cur_state));
1050 }
1051
1052 static void assert_plane(struct drm_i915_private *dev_priv,
1053                          enum plane plane, bool state)
1054 {
1055         int reg;
1056         u32 val;
1057         bool cur_state;
1058
1059         reg = DSPCNTR(plane);
1060         val = I915_READ(reg);
1061         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1062         WARN(cur_state != state,
1063              "plane %c assertion failure (expected %s, current %s)\n",
1064              plane_name(plane), state_string(state), state_string(cur_state));
1065 }
1066
1067 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1068 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1069
1070 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1071                                    enum pipe pipe)
1072 {
1073         int reg, i;
1074         u32 val;
1075         int cur_pipe;
1076
1077         /* Planes are fixed to pipes on ILK+ */
1078         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1079                 reg = DSPCNTR(pipe);
1080                 val = I915_READ(reg);
1081                 WARN((val & DISPLAY_PLANE_ENABLE),
1082                      "plane %c assertion failure, should be disabled but not\n",
1083                      plane_name(pipe));
1084                 return;
1085         }
1086
1087         /* Need to check both planes against the pipe */
1088         for (i = 0; i < 2; i++) {
1089                 reg = DSPCNTR(i);
1090                 val = I915_READ(reg);
1091                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1092                         DISPPLANE_SEL_PIPE_SHIFT;
1093                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1094                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1095                      plane_name(i), pipe_name(pipe));
1096         }
1097 }
1098
1099 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1100 {
1101         u32 val;
1102         bool enabled;
1103
1104         val = I915_READ(PCH_DREF_CONTROL);
1105         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1106                             DREF_SUPERSPREAD_SOURCE_MASK));
1107         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1108 }
1109
1110 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1111                                        enum pipe pipe)
1112 {
1113         int reg;
1114         u32 val;
1115         bool enabled;
1116
1117         reg = TRANSCONF(pipe);
1118         val = I915_READ(reg);
1119         enabled = !!(val & TRANS_ENABLE);
1120         WARN(enabled,
1121              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1122              pipe_name(pipe));
1123 }
1124
1125 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1126                             enum pipe pipe, u32 port_sel, u32 val)
1127 {
1128         if ((val & DP_PORT_EN) == 0)
1129                 return false;
1130
1131         if (HAS_PCH_CPT(dev_priv->dev)) {
1132                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1133                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1134                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1135                         return false;
1136         } else {
1137                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1138                         return false;
1139         }
1140         return true;
1141 }
1142
1143 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1144                               enum pipe pipe, u32 val)
1145 {
1146         if ((val & PORT_ENABLE) == 0)
1147                 return false;
1148
1149         if (HAS_PCH_CPT(dev_priv->dev)) {
1150                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1151                         return false;
1152         } else {
1153                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1154                         return false;
1155         }
1156         return true;
1157 }
1158
1159 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1160                               enum pipe pipe, u32 val)
1161 {
1162         if ((val & LVDS_PORT_EN) == 0)
1163                 return false;
1164
1165         if (HAS_PCH_CPT(dev_priv->dev)) {
1166                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1167                         return false;
1168         } else {
1169                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1170                         return false;
1171         }
1172         return true;
1173 }
1174
1175 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1176                               enum pipe pipe, u32 val)
1177 {
1178         if ((val & ADPA_DAC_ENABLE) == 0)
1179                 return false;
1180         if (HAS_PCH_CPT(dev_priv->dev)) {
1181                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1182                         return false;
1183         } else {
1184                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1185                         return false;
1186         }
1187         return true;
1188 }
1189
1190 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1191                                    enum pipe pipe, int reg, u32 port_sel)
1192 {
1193         u32 val = I915_READ(reg);
1194         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1195              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1196              reg, pipe_name(pipe));
1197 }
1198
1199 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1200                                      enum pipe pipe, int reg)
1201 {
1202         u32 val = I915_READ(reg);
1203         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1204              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1205              reg, pipe_name(pipe));
1206 }
1207
1208 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1209                                       enum pipe pipe)
1210 {
1211         int reg;
1212         u32 val;
1213
1214         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1215         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1216         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1217
1218         reg = PCH_ADPA;
1219         val = I915_READ(reg);
1220         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1221              "PCH VGA enabled on transcoder %c, should be disabled\n",
1222              pipe_name(pipe));
1223
1224         reg = PCH_LVDS;
1225         val = I915_READ(reg);
1226         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1227              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1228              pipe_name(pipe));
1229
1230         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1231         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1232         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1233 }
1234
1235 /**
1236  * intel_enable_pll - enable a PLL
1237  * @dev_priv: i915 private structure
1238  * @pipe: pipe PLL to enable
1239  *
1240  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1241  * make sure the PLL reg is writable first though, since the panel write
1242  * protect mechanism may be enabled.
1243  *
1244  * Note!  This is for pre-ILK only.
1245  */
1246 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1247 {
1248         int reg;
1249         u32 val;
1250
1251         /* No really, not for ILK+ */
1252         BUG_ON(dev_priv->info->gen >= 5);
1253
1254         /* PLL is protected by panel, make sure we can write it */
1255         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1256                 assert_panel_unlocked(dev_priv, pipe);
1257
1258         reg = DPLL(pipe);
1259         val = I915_READ(reg);
1260         val |= DPLL_VCO_ENABLE;
1261
1262         /* We do this three times for luck */
1263         I915_WRITE(reg, val);
1264         POSTING_READ(reg);
1265         udelay(150); /* wait for warmup */
1266         I915_WRITE(reg, val);
1267         POSTING_READ(reg);
1268         udelay(150); /* wait for warmup */
1269         I915_WRITE(reg, val);
1270         POSTING_READ(reg);
1271         udelay(150); /* wait for warmup */
1272 }
1273
1274 /**
1275  * intel_disable_pll - disable a PLL
1276  * @dev_priv: i915 private structure
1277  * @pipe: pipe PLL to disable
1278  *
1279  * Disable the PLL for @pipe, making sure the pipe is off first.
1280  *
1281  * Note!  This is for pre-ILK only.
1282  */
1283 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1284 {
1285         int reg;
1286         u32 val;
1287
1288         /* Don't disable pipe A or pipe A PLLs if needed */
1289         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1290                 return;
1291
1292         /* Make sure the pipe isn't still relying on us */
1293         assert_pipe_disabled(dev_priv, pipe);
1294
1295         reg = DPLL(pipe);
1296         val = I915_READ(reg);
1297         val &= ~DPLL_VCO_ENABLE;
1298         I915_WRITE(reg, val);
1299         POSTING_READ(reg);
1300 }
1301
1302 /* SBI access */
1303 static void
1304 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1305 {
1306         unsigned long flags;
1307
1308         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1309         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1310                                 100)) {
1311                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1312                 goto out_unlock;
1313         }
1314
1315         I915_WRITE(SBI_ADDR,
1316                         (reg << 16));
1317         I915_WRITE(SBI_DATA,
1318                         value);
1319         I915_WRITE(SBI_CTL_STAT,
1320                         SBI_BUSY |
1321                         SBI_CTL_OP_CRWR);
1322
1323         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1324                                 100)) {
1325                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1326                 goto out_unlock;
1327         }
1328
1329 out_unlock:
1330         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1331 }
1332
1333 static u32
1334 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1335 {
1336         unsigned long flags;
1337         u32 value;
1338
1339         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1340         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1341                                 100)) {
1342                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1343                 goto out_unlock;
1344         }
1345
1346         I915_WRITE(SBI_ADDR,
1347                         (reg << 16));
1348         I915_WRITE(SBI_CTL_STAT,
1349                         SBI_BUSY |
1350                         SBI_CTL_OP_CRRD);
1351
1352         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1353                                 100)) {
1354                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1355                 goto out_unlock;
1356         }
1357
1358         value = I915_READ(SBI_DATA);
1359
1360 out_unlock:
1361         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1362         return value;
1363 }
1364
1365 /**
1366  * intel_enable_pch_pll - enable PCH PLL
1367  * @dev_priv: i915 private structure
1368  * @pipe: pipe PLL to enable
1369  *
1370  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1371  * drives the transcoder clock.
1372  */
1373 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1374 {
1375         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1376         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1377         int reg;
1378         u32 val;
1379
1380         /* PCH only available on ILK+ */
1381         BUG_ON(dev_priv->info->gen < 5);
1382         BUG_ON(pll == NULL);
1383         BUG_ON(pll->refcount == 0);
1384
1385         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1386                       pll->pll_reg, pll->active, pll->on,
1387                       intel_crtc->base.base.id);
1388
1389         /* PCH refclock must be enabled first */
1390         assert_pch_refclk_enabled(dev_priv);
1391
1392         if (pll->active++ && pll->on) {
1393                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1394                 return;
1395         }
1396
1397         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1398
1399         reg = pll->pll_reg;
1400         val = I915_READ(reg);
1401         val |= DPLL_VCO_ENABLE;
1402         I915_WRITE(reg, val);
1403         POSTING_READ(reg);
1404         udelay(200);
1405
1406         pll->on = true;
1407 }
1408
1409 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1410 {
1411         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1412         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1413         int reg;
1414         u32 val;
1415
1416         /* PCH only available on ILK+ */
1417         BUG_ON(dev_priv->info->gen < 5);
1418         if (pll == NULL)
1419                return;
1420
1421         BUG_ON(pll->refcount == 0);
1422
1423         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1424                       pll->pll_reg, pll->active, pll->on,
1425                       intel_crtc->base.base.id);
1426
1427         BUG_ON(pll->active == 0);
1428         if (--pll->active) {
1429                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1430                 return;
1431         }
1432
1433         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1434
1435         /* Make sure transcoder isn't still depending on us */
1436         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1437
1438         reg = pll->pll_reg;
1439         val = I915_READ(reg);
1440         val &= ~DPLL_VCO_ENABLE;
1441         I915_WRITE(reg, val);
1442         POSTING_READ(reg);
1443         udelay(200);
1444
1445         pll->on = false;
1446 }
1447
1448 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1449                                     enum pipe pipe)
1450 {
1451         int reg;
1452         u32 val, pipeconf_val;
1453         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1454
1455         /* PCH only available on ILK+ */
1456         BUG_ON(dev_priv->info->gen < 5);
1457
1458         /* Make sure PCH DPLL is enabled */
1459         assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
1460
1461         /* FDI must be feeding us bits for PCH ports */
1462         assert_fdi_tx_enabled(dev_priv, pipe);
1463         assert_fdi_rx_enabled(dev_priv, pipe);
1464
1465         reg = TRANSCONF(pipe);
1466         val = I915_READ(reg);
1467         pipeconf_val = I915_READ(PIPECONF(pipe));
1468
1469         if (HAS_PCH_IBX(dev_priv->dev)) {
1470                 /*
1471                  * make the BPC in transcoder be consistent with
1472                  * that in pipeconf reg.
1473                  */
1474                 val &= ~PIPE_BPC_MASK;
1475                 val |= pipeconf_val & PIPE_BPC_MASK;
1476         }
1477
1478         val &= ~TRANS_INTERLACE_MASK;
1479         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1480                 if (HAS_PCH_IBX(dev_priv->dev) &&
1481                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1482                         val |= TRANS_LEGACY_INTERLACED_ILK;
1483                 else
1484                         val |= TRANS_INTERLACED;
1485         else
1486                 val |= TRANS_PROGRESSIVE;
1487
1488         I915_WRITE(reg, val | TRANS_ENABLE);
1489         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1490                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1491 }
1492
1493 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1494                                      enum pipe pipe)
1495 {
1496         int reg;
1497         u32 val;
1498
1499         /* FDI relies on the transcoder */
1500         assert_fdi_tx_disabled(dev_priv, pipe);
1501         assert_fdi_rx_disabled(dev_priv, pipe);
1502
1503         /* Ports must be off as well */
1504         assert_pch_ports_disabled(dev_priv, pipe);
1505
1506         reg = TRANSCONF(pipe);
1507         val = I915_READ(reg);
1508         val &= ~TRANS_ENABLE;
1509         I915_WRITE(reg, val);
1510         /* wait for PCH transcoder off, transcoder state */
1511         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1512                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1513 }
1514
1515 /**
1516  * intel_enable_pipe - enable a pipe, asserting requirements
1517  * @dev_priv: i915 private structure
1518  * @pipe: pipe to enable
1519  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1520  *
1521  * Enable @pipe, making sure that various hardware specific requirements
1522  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1523  *
1524  * @pipe should be %PIPE_A or %PIPE_B.
1525  *
1526  * Will wait until the pipe is actually running (i.e. first vblank) before
1527  * returning.
1528  */
1529 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1530                               bool pch_port)
1531 {
1532         int reg;
1533         u32 val;
1534
1535         /*
1536          * A pipe without a PLL won't actually be able to drive bits from
1537          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1538          * need the check.
1539          */
1540         if (!HAS_PCH_SPLIT(dev_priv->dev))
1541                 assert_pll_enabled(dev_priv, pipe);
1542         else {
1543                 if (pch_port) {
1544                         /* if driving the PCH, we need FDI enabled */
1545                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1546                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1547                 }
1548                 /* FIXME: assert CPU port conditions for SNB+ */
1549         }
1550
1551         reg = PIPECONF(pipe);
1552         val = I915_READ(reg);
1553         if (val & PIPECONF_ENABLE)
1554                 return;
1555
1556         I915_WRITE(reg, val | PIPECONF_ENABLE);
1557         intel_wait_for_vblank(dev_priv->dev, pipe);
1558 }
1559
1560 /**
1561  * intel_disable_pipe - disable a pipe, asserting requirements
1562  * @dev_priv: i915 private structure
1563  * @pipe: pipe to disable
1564  *
1565  * Disable @pipe, making sure that various hardware specific requirements
1566  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1567  *
1568  * @pipe should be %PIPE_A or %PIPE_B.
1569  *
1570  * Will wait until the pipe has shut down before returning.
1571  */
1572 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1573                                enum pipe pipe)
1574 {
1575         int reg;
1576         u32 val;
1577
1578         /*
1579          * Make sure planes won't keep trying to pump pixels to us,
1580          * or we might hang the display.
1581          */
1582         assert_planes_disabled(dev_priv, pipe);
1583
1584         /* Don't disable pipe A or pipe A PLLs if needed */
1585         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1586                 return;
1587
1588         reg = PIPECONF(pipe);
1589         val = I915_READ(reg);
1590         if ((val & PIPECONF_ENABLE) == 0)
1591                 return;
1592
1593         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1594         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1595 }
1596
1597 /*
1598  * Plane regs are double buffered, going from enabled->disabled needs a
1599  * trigger in order to latch.  The display address reg provides this.
1600  */
1601 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1602                                       enum plane plane)
1603 {
1604         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1605         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1606 }
1607
1608 /**
1609  * intel_enable_plane - enable a display plane on a given pipe
1610  * @dev_priv: i915 private structure
1611  * @plane: plane to enable
1612  * @pipe: pipe being fed
1613  *
1614  * Enable @plane on @pipe, making sure that @pipe is running first.
1615  */
1616 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1617                                enum plane plane, enum pipe pipe)
1618 {
1619         int reg;
1620         u32 val;
1621
1622         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1623         assert_pipe_enabled(dev_priv, pipe);
1624
1625         reg = DSPCNTR(plane);
1626         val = I915_READ(reg);
1627         if (val & DISPLAY_PLANE_ENABLE)
1628                 return;
1629
1630         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1631         intel_flush_display_plane(dev_priv, plane);
1632         intel_wait_for_vblank(dev_priv->dev, pipe);
1633 }
1634
1635 /**
1636  * intel_disable_plane - disable a display plane
1637  * @dev_priv: i915 private structure
1638  * @plane: plane to disable
1639  * @pipe: pipe consuming the data
1640  *
1641  * Disable @plane; should be an independent operation.
1642  */
1643 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1644                                 enum plane plane, enum pipe pipe)
1645 {
1646         int reg;
1647         u32 val;
1648
1649         reg = DSPCNTR(plane);
1650         val = I915_READ(reg);
1651         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1652                 return;
1653
1654         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1655         intel_flush_display_plane(dev_priv, plane);
1656         intel_wait_for_vblank(dev_priv->dev, pipe);
1657 }
1658
1659 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1660                            enum pipe pipe, int reg, u32 port_sel)
1661 {
1662         u32 val = I915_READ(reg);
1663         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1664                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1665                 I915_WRITE(reg, val & ~DP_PORT_EN);
1666         }
1667 }
1668
1669 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1670                              enum pipe pipe, int reg)
1671 {
1672         u32 val = I915_READ(reg);
1673         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1674                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1675                               reg, pipe);
1676                 I915_WRITE(reg, val & ~PORT_ENABLE);
1677         }
1678 }
1679
1680 /* Disable any ports connected to this transcoder */
1681 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1682                                     enum pipe pipe)
1683 {
1684         u32 reg, val;
1685
1686         val = I915_READ(PCH_PP_CONTROL);
1687         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1688
1689         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1690         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1691         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1692
1693         reg = PCH_ADPA;
1694         val = I915_READ(reg);
1695         if (adpa_pipe_enabled(dev_priv, val, pipe))
1696                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1697
1698         reg = PCH_LVDS;
1699         val = I915_READ(reg);
1700         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1701                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1702                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1703                 POSTING_READ(reg);
1704                 udelay(100);
1705         }
1706
1707         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1708         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1709         disable_pch_hdmi(dev_priv, pipe, HDMID);
1710 }
1711
1712 int
1713 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1714                            struct drm_i915_gem_object *obj,
1715                            struct intel_ring_buffer *pipelined)
1716 {
1717         struct drm_i915_private *dev_priv = dev->dev_private;
1718         u32 alignment;
1719         int ret;
1720
1721         switch (obj->tiling_mode) {
1722         case I915_TILING_NONE:
1723                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1724                         alignment = 128 * 1024;
1725                 else if (INTEL_INFO(dev)->gen >= 4)
1726                         alignment = 4 * 1024;
1727                 else
1728                         alignment = 64 * 1024;
1729                 break;
1730         case I915_TILING_X:
1731                 /* pin() will align the object as required by fence */
1732                 alignment = 0;
1733                 break;
1734         case I915_TILING_Y:
1735                 /* FIXME: Is this true? */
1736                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1737                 return -EINVAL;
1738         default:
1739                 BUG();
1740         }
1741
1742         dev_priv->mm.interruptible = false;
1743         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1744         if (ret)
1745                 goto err_interruptible;
1746
1747         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1748          * fence, whereas 965+ only requires a fence if using
1749          * framebuffer compression.  For simplicity, we always install
1750          * a fence as the cost is not that onerous.
1751          */
1752         ret = i915_gem_object_get_fence(obj);
1753         if (ret)
1754                 goto err_unpin;
1755
1756         i915_gem_object_pin_fence(obj);
1757
1758         dev_priv->mm.interruptible = true;
1759         return 0;
1760
1761 err_unpin:
1762         i915_gem_object_unpin(obj);
1763 err_interruptible:
1764         dev_priv->mm.interruptible = true;
1765         return ret;
1766 }
1767
1768 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1769 {
1770         i915_gem_object_unpin_fence(obj);
1771         i915_gem_object_unpin(obj);
1772 }
1773
1774 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1775                              int x, int y)
1776 {
1777         struct drm_device *dev = crtc->dev;
1778         struct drm_i915_private *dev_priv = dev->dev_private;
1779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1780         struct intel_framebuffer *intel_fb;
1781         struct drm_i915_gem_object *obj;
1782         int plane = intel_crtc->plane;
1783         unsigned long Start, Offset;
1784         u32 dspcntr;
1785         u32 reg;
1786
1787         switch (plane) {
1788         case 0:
1789         case 1:
1790                 break;
1791         default:
1792                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1793                 return -EINVAL;
1794         }
1795
1796         intel_fb = to_intel_framebuffer(fb);
1797         obj = intel_fb->obj;
1798
1799         reg = DSPCNTR(plane);
1800         dspcntr = I915_READ(reg);
1801         /* Mask out pixel format bits in case we change it */
1802         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1803         switch (fb->bits_per_pixel) {
1804         case 8:
1805                 dspcntr |= DISPPLANE_8BPP;
1806                 break;
1807         case 16:
1808                 if (fb->depth == 15)
1809                         dspcntr |= DISPPLANE_15_16BPP;
1810                 else
1811                         dspcntr |= DISPPLANE_16BPP;
1812                 break;
1813         case 24:
1814         case 32:
1815                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1816                 break;
1817         default:
1818                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1819                 return -EINVAL;
1820         }
1821         if (INTEL_INFO(dev)->gen >= 4) {
1822                 if (obj->tiling_mode != I915_TILING_NONE)
1823                         dspcntr |= DISPPLANE_TILED;
1824                 else
1825                         dspcntr &= ~DISPPLANE_TILED;
1826         }
1827
1828         I915_WRITE(reg, dspcntr);
1829
1830         Start = obj->gtt_offset;
1831         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1832
1833         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1834                       Start, Offset, x, y, fb->pitches[0]);
1835         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1836         if (INTEL_INFO(dev)->gen >= 4) {
1837                 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1838                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1839                 I915_WRITE(DSPADDR(plane), Offset);
1840         } else
1841                 I915_WRITE(DSPADDR(plane), Start + Offset);
1842         POSTING_READ(reg);
1843
1844         return 0;
1845 }
1846
1847 static int ironlake_update_plane(struct drm_crtc *crtc,
1848                                  struct drm_framebuffer *fb, int x, int y)
1849 {
1850         struct drm_device *dev = crtc->dev;
1851         struct drm_i915_private *dev_priv = dev->dev_private;
1852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1853         struct intel_framebuffer *intel_fb;
1854         struct drm_i915_gem_object *obj;
1855         int plane = intel_crtc->plane;
1856         unsigned long Start, Offset;
1857         u32 dspcntr;
1858         u32 reg;
1859
1860         switch (plane) {
1861         case 0:
1862         case 1:
1863         case 2:
1864                 break;
1865         default:
1866                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1867                 return -EINVAL;
1868         }
1869
1870         intel_fb = to_intel_framebuffer(fb);
1871         obj = intel_fb->obj;
1872
1873         reg = DSPCNTR(plane);
1874         dspcntr = I915_READ(reg);
1875         /* Mask out pixel format bits in case we change it */
1876         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1877         switch (fb->bits_per_pixel) {
1878         case 8:
1879                 dspcntr |= DISPPLANE_8BPP;
1880                 break;
1881         case 16:
1882                 if (fb->depth != 16)
1883                         return -EINVAL;
1884
1885                 dspcntr |= DISPPLANE_16BPP;
1886                 break;
1887         case 24:
1888         case 32:
1889                 if (fb->depth == 24)
1890                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1891                 else if (fb->depth == 30)
1892                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1893                 else
1894                         return -EINVAL;
1895                 break;
1896         default:
1897                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1898                 return -EINVAL;
1899         }
1900
1901         if (obj->tiling_mode != I915_TILING_NONE)
1902                 dspcntr |= DISPPLANE_TILED;
1903         else
1904                 dspcntr &= ~DISPPLANE_TILED;
1905
1906         /* must disable */
1907         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1908
1909         I915_WRITE(reg, dspcntr);
1910
1911         Start = obj->gtt_offset;
1912         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1913
1914         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1915                       Start, Offset, x, y, fb->pitches[0]);
1916         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1917         I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1918         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1919         I915_WRITE(DSPADDR(plane), Offset);
1920         POSTING_READ(reg);
1921
1922         return 0;
1923 }
1924
1925 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1926 static int
1927 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1928                            int x, int y, enum mode_set_atomic state)
1929 {
1930         struct drm_device *dev = crtc->dev;
1931         struct drm_i915_private *dev_priv = dev->dev_private;
1932
1933         if (dev_priv->display.disable_fbc)
1934                 dev_priv->display.disable_fbc(dev);
1935         intel_increase_pllclock(crtc);
1936
1937         return dev_priv->display.update_plane(crtc, fb, x, y);
1938 }
1939
1940 static int
1941 intel_finish_fb(struct drm_framebuffer *old_fb)
1942 {
1943         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1944         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1945         bool was_interruptible = dev_priv->mm.interruptible;
1946         int ret;
1947
1948         wait_event(dev_priv->pending_flip_queue,
1949                    atomic_read(&dev_priv->mm.wedged) ||
1950                    atomic_read(&obj->pending_flip) == 0);
1951
1952         /* Big Hammer, we also need to ensure that any pending
1953          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1954          * current scanout is retired before unpinning the old
1955          * framebuffer.
1956          *
1957          * This should only fail upon a hung GPU, in which case we
1958          * can safely continue.
1959          */
1960         dev_priv->mm.interruptible = false;
1961         ret = i915_gem_object_finish_gpu(obj);
1962         dev_priv->mm.interruptible = was_interruptible;
1963
1964         return ret;
1965 }
1966
1967 static int
1968 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1969                     struct drm_framebuffer *old_fb)
1970 {
1971         struct drm_device *dev = crtc->dev;
1972         struct drm_i915_private *dev_priv = dev->dev_private;
1973         struct drm_i915_master_private *master_priv;
1974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1975         int ret;
1976
1977         /* no fb bound */
1978         if (!crtc->fb) {
1979                 DRM_ERROR("No FB bound\n");
1980                 return 0;
1981         }
1982
1983         switch (intel_crtc->plane) {
1984         case 0:
1985         case 1:
1986                 break;
1987         case 2:
1988                 if (IS_IVYBRIDGE(dev))
1989                         break;
1990                 /* fall through otherwise */
1991         default:
1992                 DRM_ERROR("no plane for crtc\n");
1993                 return -EINVAL;
1994         }
1995
1996         mutex_lock(&dev->struct_mutex);
1997         ret = intel_pin_and_fence_fb_obj(dev,
1998                                          to_intel_framebuffer(crtc->fb)->obj,
1999                                          NULL);
2000         if (ret != 0) {
2001                 mutex_unlock(&dev->struct_mutex);
2002                 DRM_ERROR("pin & fence failed\n");
2003                 return ret;
2004         }
2005
2006         if (old_fb)
2007                 intel_finish_fb(old_fb);
2008
2009         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2010         if (ret) {
2011                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2012                 mutex_unlock(&dev->struct_mutex);
2013                 DRM_ERROR("failed to update base address\n");
2014                 return ret;
2015         }
2016
2017         if (old_fb) {
2018                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2019                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2020         }
2021
2022         intel_update_fbc(dev);
2023         mutex_unlock(&dev->struct_mutex);
2024
2025         if (!dev->primary->master)
2026                 return 0;
2027
2028         master_priv = dev->primary->master->driver_priv;
2029         if (!master_priv->sarea_priv)
2030                 return 0;
2031
2032         if (intel_crtc->pipe) {
2033                 master_priv->sarea_priv->pipeB_x = x;
2034                 master_priv->sarea_priv->pipeB_y = y;
2035         } else {
2036                 master_priv->sarea_priv->pipeA_x = x;
2037                 master_priv->sarea_priv->pipeA_y = y;
2038         }
2039
2040         return 0;
2041 }
2042
2043 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2044 {
2045         struct drm_device *dev = crtc->dev;
2046         struct drm_i915_private *dev_priv = dev->dev_private;
2047         u32 dpa_ctl;
2048
2049         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2050         dpa_ctl = I915_READ(DP_A);
2051         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2052
2053         if (clock < 200000) {
2054                 u32 temp;
2055                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2056                 /* workaround for 160Mhz:
2057                    1) program 0x4600c bits 15:0 = 0x8124
2058                    2) program 0x46010 bit 0 = 1
2059                    3) program 0x46034 bit 24 = 1
2060                    4) program 0x64000 bit 14 = 1
2061                    */
2062                 temp = I915_READ(0x4600c);
2063                 temp &= 0xffff0000;
2064                 I915_WRITE(0x4600c, temp | 0x8124);
2065
2066                 temp = I915_READ(0x46010);
2067                 I915_WRITE(0x46010, temp | 1);
2068
2069                 temp = I915_READ(0x46034);
2070                 I915_WRITE(0x46034, temp | (1 << 24));
2071         } else {
2072                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2073         }
2074         I915_WRITE(DP_A, dpa_ctl);
2075
2076         POSTING_READ(DP_A);
2077         udelay(500);
2078 }
2079
2080 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2081 {
2082         struct drm_device *dev = crtc->dev;
2083         struct drm_i915_private *dev_priv = dev->dev_private;
2084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085         int pipe = intel_crtc->pipe;
2086         u32 reg, temp;
2087
2088         /* enable normal train */
2089         reg = FDI_TX_CTL(pipe);
2090         temp = I915_READ(reg);
2091         if (IS_IVYBRIDGE(dev)) {
2092                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2093                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2094         } else {
2095                 temp &= ~FDI_LINK_TRAIN_NONE;
2096                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2097         }
2098         I915_WRITE(reg, temp);
2099
2100         reg = FDI_RX_CTL(pipe);
2101         temp = I915_READ(reg);
2102         if (HAS_PCH_CPT(dev)) {
2103                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2104                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2105         } else {
2106                 temp &= ~FDI_LINK_TRAIN_NONE;
2107                 temp |= FDI_LINK_TRAIN_NONE;
2108         }
2109         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2110
2111         /* wait one idle pattern time */
2112         POSTING_READ(reg);
2113         udelay(1000);
2114
2115         /* IVB wants error correction enabled */
2116         if (IS_IVYBRIDGE(dev))
2117                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2118                            FDI_FE_ERRC_ENABLE);
2119 }
2120
2121 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2122 {
2123         struct drm_i915_private *dev_priv = dev->dev_private;
2124         u32 flags = I915_READ(SOUTH_CHICKEN1);
2125
2126         flags |= FDI_PHASE_SYNC_OVR(pipe);
2127         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2128         flags |= FDI_PHASE_SYNC_EN(pipe);
2129         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2130         POSTING_READ(SOUTH_CHICKEN1);
2131 }
2132
2133 /* The FDI link training functions for ILK/Ibexpeak. */
2134 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2135 {
2136         struct drm_device *dev = crtc->dev;
2137         struct drm_i915_private *dev_priv = dev->dev_private;
2138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2139         int pipe = intel_crtc->pipe;
2140         int plane = intel_crtc->plane;
2141         u32 reg, temp, tries;
2142
2143         /* FDI needs bits from pipe & plane first */
2144         assert_pipe_enabled(dev_priv, pipe);
2145         assert_plane_enabled(dev_priv, plane);
2146
2147         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2148            for train result */
2149         reg = FDI_RX_IMR(pipe);
2150         temp = I915_READ(reg);
2151         temp &= ~FDI_RX_SYMBOL_LOCK;
2152         temp &= ~FDI_RX_BIT_LOCK;
2153         I915_WRITE(reg, temp);
2154         I915_READ(reg);
2155         udelay(150);
2156
2157         /* enable CPU FDI TX and PCH FDI RX */
2158         reg = FDI_TX_CTL(pipe);
2159         temp = I915_READ(reg);
2160         temp &= ~(7 << 19);
2161         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2162         temp &= ~FDI_LINK_TRAIN_NONE;
2163         temp |= FDI_LINK_TRAIN_PATTERN_1;
2164         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2165
2166         reg = FDI_RX_CTL(pipe);
2167         temp = I915_READ(reg);
2168         temp &= ~FDI_LINK_TRAIN_NONE;
2169         temp |= FDI_LINK_TRAIN_PATTERN_1;
2170         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2171
2172         POSTING_READ(reg);
2173         udelay(150);
2174
2175         /* Ironlake workaround, enable clock pointer after FDI enable*/
2176         if (HAS_PCH_IBX(dev)) {
2177                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2178                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2179                            FDI_RX_PHASE_SYNC_POINTER_EN);
2180         }
2181
2182         reg = FDI_RX_IIR(pipe);
2183         for (tries = 0; tries < 5; tries++) {
2184                 temp = I915_READ(reg);
2185                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2186
2187                 if ((temp & FDI_RX_BIT_LOCK)) {
2188                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2189                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2190                         break;
2191                 }
2192         }
2193         if (tries == 5)
2194                 DRM_ERROR("FDI train 1 fail!\n");
2195
2196         /* Train 2 */
2197         reg = FDI_TX_CTL(pipe);
2198         temp = I915_READ(reg);
2199         temp &= ~FDI_LINK_TRAIN_NONE;
2200         temp |= FDI_LINK_TRAIN_PATTERN_2;
2201         I915_WRITE(reg, temp);
2202
2203         reg = FDI_RX_CTL(pipe);
2204         temp = I915_READ(reg);
2205         temp &= ~FDI_LINK_TRAIN_NONE;
2206         temp |= FDI_LINK_TRAIN_PATTERN_2;
2207         I915_WRITE(reg, temp);
2208
2209         POSTING_READ(reg);
2210         udelay(150);
2211
2212         reg = FDI_RX_IIR(pipe);
2213         for (tries = 0; tries < 5; tries++) {
2214                 temp = I915_READ(reg);
2215                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2216
2217                 if (temp & FDI_RX_SYMBOL_LOCK) {
2218                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2219                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2220                         break;
2221                 }
2222         }
2223         if (tries == 5)
2224                 DRM_ERROR("FDI train 2 fail!\n");
2225
2226         DRM_DEBUG_KMS("FDI train done\n");
2227
2228 }
2229
2230 static const int snb_b_fdi_train_param[] = {
2231         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2232         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2233         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2234         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2235 };
2236
2237 /* The FDI link training functions for SNB/Cougarpoint. */
2238 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2239 {
2240         struct drm_device *dev = crtc->dev;
2241         struct drm_i915_private *dev_priv = dev->dev_private;
2242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2243         int pipe = intel_crtc->pipe;
2244         u32 reg, temp, i, retry;
2245
2246         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2247            for train result */
2248         reg = FDI_RX_IMR(pipe);
2249         temp = I915_READ(reg);
2250         temp &= ~FDI_RX_SYMBOL_LOCK;
2251         temp &= ~FDI_RX_BIT_LOCK;
2252         I915_WRITE(reg, temp);
2253
2254         POSTING_READ(reg);
2255         udelay(150);
2256
2257         /* enable CPU FDI TX and PCH FDI RX */
2258         reg = FDI_TX_CTL(pipe);
2259         temp = I915_READ(reg);
2260         temp &= ~(7 << 19);
2261         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2262         temp &= ~FDI_LINK_TRAIN_NONE;
2263         temp |= FDI_LINK_TRAIN_PATTERN_1;
2264         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2265         /* SNB-B */
2266         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2267         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2268
2269         reg = FDI_RX_CTL(pipe);
2270         temp = I915_READ(reg);
2271         if (HAS_PCH_CPT(dev)) {
2272                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2273                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2274         } else {
2275                 temp &= ~FDI_LINK_TRAIN_NONE;
2276                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2277         }
2278         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2279
2280         POSTING_READ(reg);
2281         udelay(150);
2282
2283         if (HAS_PCH_CPT(dev))
2284                 cpt_phase_pointer_enable(dev, pipe);
2285
2286         for (i = 0; i < 4; i++) {
2287                 reg = FDI_TX_CTL(pipe);
2288                 temp = I915_READ(reg);
2289                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2290                 temp |= snb_b_fdi_train_param[i];
2291                 I915_WRITE(reg, temp);
2292
2293                 POSTING_READ(reg);
2294                 udelay(500);
2295
2296                 for (retry = 0; retry < 5; retry++) {
2297                         reg = FDI_RX_IIR(pipe);
2298                         temp = I915_READ(reg);
2299                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2300                         if (temp & FDI_RX_BIT_LOCK) {
2301                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2302                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2303                                 break;
2304                         }
2305                         udelay(50);
2306                 }
2307                 if (retry < 5)
2308                         break;
2309         }
2310         if (i == 4)
2311                 DRM_ERROR("FDI train 1 fail!\n");
2312
2313         /* Train 2 */
2314         reg = FDI_TX_CTL(pipe);
2315         temp = I915_READ(reg);
2316         temp &= ~FDI_LINK_TRAIN_NONE;
2317         temp |= FDI_LINK_TRAIN_PATTERN_2;
2318         if (IS_GEN6(dev)) {
2319                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2320                 /* SNB-B */
2321                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2322         }
2323         I915_WRITE(reg, temp);
2324
2325         reg = FDI_RX_CTL(pipe);
2326         temp = I915_READ(reg);
2327         if (HAS_PCH_CPT(dev)) {
2328                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2329                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2330         } else {
2331                 temp &= ~FDI_LINK_TRAIN_NONE;
2332                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2333         }
2334         I915_WRITE(reg, temp);
2335
2336         POSTING_READ(reg);
2337         udelay(150);
2338
2339         for (i = 0; i < 4; i++) {
2340                 reg = FDI_TX_CTL(pipe);
2341                 temp = I915_READ(reg);
2342                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2343                 temp |= snb_b_fdi_train_param[i];
2344                 I915_WRITE(reg, temp);
2345
2346                 POSTING_READ(reg);
2347                 udelay(500);
2348
2349                 for (retry = 0; retry < 5; retry++) {
2350                         reg = FDI_RX_IIR(pipe);
2351                         temp = I915_READ(reg);
2352                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2353                         if (temp & FDI_RX_SYMBOL_LOCK) {
2354                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2355                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2356                                 break;
2357                         }
2358                         udelay(50);
2359                 }
2360                 if (retry < 5)
2361                         break;
2362         }
2363         if (i == 4)
2364                 DRM_ERROR("FDI train 2 fail!\n");
2365
2366         DRM_DEBUG_KMS("FDI train done.\n");
2367 }
2368
2369 /* Manual link training for Ivy Bridge A0 parts */
2370 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2371 {
2372         struct drm_device *dev = crtc->dev;
2373         struct drm_i915_private *dev_priv = dev->dev_private;
2374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2375         int pipe = intel_crtc->pipe;
2376         u32 reg, temp, i;
2377
2378         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2379            for train result */
2380         reg = FDI_RX_IMR(pipe);
2381         temp = I915_READ(reg);
2382         temp &= ~FDI_RX_SYMBOL_LOCK;
2383         temp &= ~FDI_RX_BIT_LOCK;
2384         I915_WRITE(reg, temp);
2385
2386         POSTING_READ(reg);
2387         udelay(150);
2388
2389         /* enable CPU FDI TX and PCH FDI RX */
2390         reg = FDI_TX_CTL(pipe);
2391         temp = I915_READ(reg);
2392         temp &= ~(7 << 19);
2393         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2394         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2395         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2396         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2397         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2398         temp |= FDI_COMPOSITE_SYNC;
2399         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2400
2401         reg = FDI_RX_CTL(pipe);
2402         temp = I915_READ(reg);
2403         temp &= ~FDI_LINK_TRAIN_AUTO;
2404         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2405         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2406         temp |= FDI_COMPOSITE_SYNC;
2407         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2408
2409         POSTING_READ(reg);
2410         udelay(150);
2411
2412         if (HAS_PCH_CPT(dev))
2413                 cpt_phase_pointer_enable(dev, pipe);
2414
2415         for (i = 0; i < 4; i++) {
2416                 reg = FDI_TX_CTL(pipe);
2417                 temp = I915_READ(reg);
2418                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2419                 temp |= snb_b_fdi_train_param[i];
2420                 I915_WRITE(reg, temp);
2421
2422                 POSTING_READ(reg);
2423                 udelay(500);
2424
2425                 reg = FDI_RX_IIR(pipe);
2426                 temp = I915_READ(reg);
2427                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2428
2429                 if (temp & FDI_RX_BIT_LOCK ||
2430                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2431                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2432                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2433                         break;
2434                 }
2435         }
2436         if (i == 4)
2437                 DRM_ERROR("FDI train 1 fail!\n");
2438
2439         /* Train 2 */
2440         reg = FDI_TX_CTL(pipe);
2441         temp = I915_READ(reg);
2442         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2443         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2444         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2445         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2446         I915_WRITE(reg, temp);
2447
2448         reg = FDI_RX_CTL(pipe);
2449         temp = I915_READ(reg);
2450         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2451         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2452         I915_WRITE(reg, temp);
2453
2454         POSTING_READ(reg);
2455         udelay(150);
2456
2457         for (i = 0; i < 4; i++) {
2458                 reg = FDI_TX_CTL(pipe);
2459                 temp = I915_READ(reg);
2460                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2461                 temp |= snb_b_fdi_train_param[i];
2462                 I915_WRITE(reg, temp);
2463
2464                 POSTING_READ(reg);
2465                 udelay(500);
2466
2467                 reg = FDI_RX_IIR(pipe);
2468                 temp = I915_READ(reg);
2469                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2470
2471                 if (temp & FDI_RX_SYMBOL_LOCK) {
2472                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2473                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2474                         break;
2475                 }
2476         }
2477         if (i == 4)
2478                 DRM_ERROR("FDI train 2 fail!\n");
2479
2480         DRM_DEBUG_KMS("FDI train done.\n");
2481 }
2482
2483 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2484 {
2485         struct drm_device *dev = crtc->dev;
2486         struct drm_i915_private *dev_priv = dev->dev_private;
2487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2488         int pipe = intel_crtc->pipe;
2489         u32 reg, temp;
2490
2491         /* Write the TU size bits so error detection works */
2492         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2493                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2494
2495         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2496         reg = FDI_RX_CTL(pipe);
2497         temp = I915_READ(reg);
2498         temp &= ~((0x7 << 19) | (0x7 << 16));
2499         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2500         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2501         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2502
2503         POSTING_READ(reg);
2504         udelay(200);
2505
2506         /* Switch from Rawclk to PCDclk */
2507         temp = I915_READ(reg);
2508         I915_WRITE(reg, temp | FDI_PCDCLK);
2509
2510         POSTING_READ(reg);
2511         udelay(200);
2512
2513         /* Enable CPU FDI TX PLL, always on for Ironlake */
2514         reg = FDI_TX_CTL(pipe);
2515         temp = I915_READ(reg);
2516         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2517                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2518
2519                 POSTING_READ(reg);
2520                 udelay(100);
2521         }
2522 }
2523
2524 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2525 {
2526         struct drm_i915_private *dev_priv = dev->dev_private;
2527         u32 flags = I915_READ(SOUTH_CHICKEN1);
2528
2529         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2530         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2531         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2532         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2533         POSTING_READ(SOUTH_CHICKEN1);
2534 }
2535 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2536 {
2537         struct drm_device *dev = crtc->dev;
2538         struct drm_i915_private *dev_priv = dev->dev_private;
2539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2540         int pipe = intel_crtc->pipe;
2541         u32 reg, temp;
2542
2543         /* disable CPU FDI tx and PCH FDI rx */
2544         reg = FDI_TX_CTL(pipe);
2545         temp = I915_READ(reg);
2546         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2547         POSTING_READ(reg);
2548
2549         reg = FDI_RX_CTL(pipe);
2550         temp = I915_READ(reg);
2551         temp &= ~(0x7 << 16);
2552         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2553         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2554
2555         POSTING_READ(reg);
2556         udelay(100);
2557
2558         /* Ironlake workaround, disable clock pointer after downing FDI */
2559         if (HAS_PCH_IBX(dev)) {
2560                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2561                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2562                            I915_READ(FDI_RX_CHICKEN(pipe) &
2563                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2564         } else if (HAS_PCH_CPT(dev)) {
2565                 cpt_phase_pointer_disable(dev, pipe);
2566         }
2567
2568         /* still set train pattern 1 */
2569         reg = FDI_TX_CTL(pipe);
2570         temp = I915_READ(reg);
2571         temp &= ~FDI_LINK_TRAIN_NONE;
2572         temp |= FDI_LINK_TRAIN_PATTERN_1;
2573         I915_WRITE(reg, temp);
2574
2575         reg = FDI_RX_CTL(pipe);
2576         temp = I915_READ(reg);
2577         if (HAS_PCH_CPT(dev)) {
2578                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2579                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2580         } else {
2581                 temp &= ~FDI_LINK_TRAIN_NONE;
2582                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2583         }
2584         /* BPC in FDI rx is consistent with that in PIPECONF */
2585         temp &= ~(0x07 << 16);
2586         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2587         I915_WRITE(reg, temp);
2588
2589         POSTING_READ(reg);
2590         udelay(100);
2591 }
2592
2593 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2594 {
2595         struct drm_device *dev = crtc->dev;
2596
2597         if (crtc->fb == NULL)
2598                 return;
2599
2600         mutex_lock(&dev->struct_mutex);
2601         intel_finish_fb(crtc->fb);
2602         mutex_unlock(&dev->struct_mutex);
2603 }
2604
2605 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2606 {
2607         struct drm_device *dev = crtc->dev;
2608         struct drm_mode_config *mode_config = &dev->mode_config;
2609         struct intel_encoder *encoder;
2610
2611         /*
2612          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2613          * must be driven by its own crtc; no sharing is possible.
2614          */
2615         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2616                 if (encoder->base.crtc != crtc)
2617                         continue;
2618
2619                 switch (encoder->type) {
2620                 case INTEL_OUTPUT_EDP:
2621                         if (!intel_encoder_is_pch_edp(&encoder->base))
2622                                 return false;
2623                         continue;
2624                 }
2625         }
2626
2627         return true;
2628 }
2629
2630 /*
2631  * Enable PCH resources required for PCH ports:
2632  *   - PCH PLLs
2633  *   - FDI training & RX/TX
2634  *   - update transcoder timings
2635  *   - DP transcoding bits
2636  *   - transcoder
2637  */
2638 static void ironlake_pch_enable(struct drm_crtc *crtc)
2639 {
2640         struct drm_device *dev = crtc->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643         int pipe = intel_crtc->pipe;
2644         u32 reg, temp;
2645
2646         /* For PCH output, training FDI link */
2647         dev_priv->display.fdi_link_train(crtc);
2648
2649         intel_enable_pch_pll(intel_crtc);
2650
2651         if (HAS_PCH_CPT(dev)) {
2652                 u32 sel;
2653
2654                 temp = I915_READ(PCH_DPLL_SEL);
2655                 switch (pipe) {
2656                 default:
2657                 case 0:
2658                         temp |= TRANSA_DPLL_ENABLE;
2659                         sel = TRANSA_DPLLB_SEL;
2660                         break;
2661                 case 1:
2662                         temp |= TRANSB_DPLL_ENABLE;
2663                         sel = TRANSB_DPLLB_SEL;
2664                         break;
2665                 case 2:
2666                         temp |= TRANSC_DPLL_ENABLE;
2667                         sel = TRANSC_DPLLB_SEL;
2668                         break;
2669                 }
2670                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2671                         temp |= sel;
2672                 else
2673                         temp &= ~sel;
2674                 I915_WRITE(PCH_DPLL_SEL, temp);
2675         }
2676
2677         /* set transcoder timing, panel must allow it */
2678         assert_panel_unlocked(dev_priv, pipe);
2679         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2680         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2681         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2682
2683         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2684         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2685         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2686         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
2687
2688         intel_fdi_normal_train(crtc);
2689
2690         /* For PCH DP, enable TRANS_DP_CTL */
2691         if (HAS_PCH_CPT(dev) &&
2692             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2693              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2694                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2695                 reg = TRANS_DP_CTL(pipe);
2696                 temp = I915_READ(reg);
2697                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2698                           TRANS_DP_SYNC_MASK |
2699                           TRANS_DP_BPC_MASK);
2700                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2701                          TRANS_DP_ENH_FRAMING);
2702                 temp |= bpc << 9; /* same format but at 11:9 */
2703
2704                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2705                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2706                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2707                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2708
2709                 switch (intel_trans_dp_port_sel(crtc)) {
2710                 case PCH_DP_B:
2711                         temp |= TRANS_DP_PORT_SEL_B;
2712                         break;
2713                 case PCH_DP_C:
2714                         temp |= TRANS_DP_PORT_SEL_C;
2715                         break;
2716                 case PCH_DP_D:
2717                         temp |= TRANS_DP_PORT_SEL_D;
2718                         break;
2719                 default:
2720                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2721                         temp |= TRANS_DP_PORT_SEL_B;
2722                         break;
2723                 }
2724
2725                 I915_WRITE(reg, temp);
2726         }
2727
2728         intel_enable_transcoder(dev_priv, pipe);
2729 }
2730
2731 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2732 {
2733         struct intel_pch_pll *pll = intel_crtc->pch_pll;
2734
2735         if (pll == NULL)
2736                 return;
2737
2738         if (pll->refcount == 0) {
2739                 WARN(1, "bad PCH PLL refcount\n");
2740                 return;
2741         }
2742
2743         --pll->refcount;
2744         intel_crtc->pch_pll = NULL;
2745 }
2746
2747 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2748 {
2749         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2750         struct intel_pch_pll *pll;
2751         int i;
2752
2753         pll = intel_crtc->pch_pll;
2754         if (pll) {
2755                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2756                               intel_crtc->base.base.id, pll->pll_reg);
2757                 goto prepare;
2758         }
2759
2760         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2761                 pll = &dev_priv->pch_plls[i];
2762
2763                 /* Only want to check enabled timings first */
2764                 if (pll->refcount == 0)
2765                         continue;
2766
2767                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2768                     fp == I915_READ(pll->fp0_reg)) {
2769                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2770                                       intel_crtc->base.base.id,
2771                                       pll->pll_reg, pll->refcount, pll->active);
2772
2773                         goto found;
2774                 }
2775         }
2776
2777         /* Ok no matching timings, maybe there's a free one? */
2778         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2779                 pll = &dev_priv->pch_plls[i];
2780                 if (pll->refcount == 0) {
2781                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2782                                       intel_crtc->base.base.id, pll->pll_reg);
2783                         goto found;
2784                 }
2785         }
2786
2787         return NULL;
2788
2789 found:
2790         intel_crtc->pch_pll = pll;
2791         pll->refcount++;
2792         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2793 prepare: /* separate function? */
2794         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2795
2796         /* Wait for the clocks to stabilize before rewriting the regs */
2797         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2798         POSTING_READ(pll->pll_reg);
2799         udelay(150);
2800
2801         I915_WRITE(pll->fp0_reg, fp);
2802         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2803         pll->on = false;
2804         return pll;
2805 }
2806
2807 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2808 {
2809         struct drm_i915_private *dev_priv = dev->dev_private;
2810         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2811         u32 temp;
2812
2813         temp = I915_READ(dslreg);
2814         udelay(500);
2815         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2816                 /* Without this, mode sets may fail silently on FDI */
2817                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2818                 udelay(250);
2819                 I915_WRITE(tc2reg, 0);
2820                 if (wait_for(I915_READ(dslreg) != temp, 5))
2821                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2822         }
2823 }
2824
2825 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2826 {
2827         struct drm_device *dev = crtc->dev;
2828         struct drm_i915_private *dev_priv = dev->dev_private;
2829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2830         int pipe = intel_crtc->pipe;
2831         int plane = intel_crtc->plane;
2832         u32 temp;
2833         bool is_pch_port;
2834
2835         if (intel_crtc->active)
2836                 return;
2837
2838         intel_crtc->active = true;
2839         intel_update_watermarks(dev);
2840
2841         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2842                 temp = I915_READ(PCH_LVDS);
2843                 if ((temp & LVDS_PORT_EN) == 0)
2844                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2845         }
2846
2847         is_pch_port = intel_crtc_driving_pch(crtc);
2848
2849         if (is_pch_port)
2850                 ironlake_fdi_pll_enable(crtc);
2851         else
2852                 ironlake_fdi_disable(crtc);
2853
2854         /* Enable panel fitting for LVDS */
2855         if (dev_priv->pch_pf_size &&
2856             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2857                 /* Force use of hard-coded filter coefficients
2858                  * as some pre-programmed values are broken,
2859                  * e.g. x201.
2860                  */
2861                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2862                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2863                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2864         }
2865
2866         /*
2867          * On ILK+ LUT must be loaded before the pipe is running but with
2868          * clocks enabled
2869          */
2870         intel_crtc_load_lut(crtc);
2871
2872         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2873         intel_enable_plane(dev_priv, plane, pipe);
2874
2875         if (is_pch_port)
2876                 ironlake_pch_enable(crtc);
2877
2878         mutex_lock(&dev->struct_mutex);
2879         intel_update_fbc(dev);
2880         mutex_unlock(&dev->struct_mutex);
2881
2882         intel_crtc_update_cursor(crtc, true);
2883 }
2884
2885 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2886 {
2887         struct drm_device *dev = crtc->dev;
2888         struct drm_i915_private *dev_priv = dev->dev_private;
2889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2890         int pipe = intel_crtc->pipe;
2891         int plane = intel_crtc->plane;
2892         u32 reg, temp;
2893
2894         if (!intel_crtc->active)
2895                 return;
2896
2897         intel_crtc_wait_for_pending_flips(crtc);
2898         drm_vblank_off(dev, pipe);
2899         intel_crtc_update_cursor(crtc, false);
2900
2901         intel_disable_plane(dev_priv, plane, pipe);
2902
2903         if (dev_priv->cfb_plane == plane)
2904                 intel_disable_fbc(dev);
2905
2906         intel_disable_pipe(dev_priv, pipe);
2907
2908         /* Disable PF */
2909         I915_WRITE(PF_CTL(pipe), 0);
2910         I915_WRITE(PF_WIN_SZ(pipe), 0);
2911
2912         ironlake_fdi_disable(crtc);
2913
2914         /* This is a horrible layering violation; we should be doing this in
2915          * the connector/encoder ->prepare instead, but we don't always have
2916          * enough information there about the config to know whether it will
2917          * actually be necessary or just cause undesired flicker.
2918          */
2919         intel_disable_pch_ports(dev_priv, pipe);
2920
2921         intel_disable_transcoder(dev_priv, pipe);
2922
2923         if (HAS_PCH_CPT(dev)) {
2924                 /* disable TRANS_DP_CTL */
2925                 reg = TRANS_DP_CTL(pipe);
2926                 temp = I915_READ(reg);
2927                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2928                 temp |= TRANS_DP_PORT_SEL_NONE;
2929                 I915_WRITE(reg, temp);
2930
2931                 /* disable DPLL_SEL */
2932                 temp = I915_READ(PCH_DPLL_SEL);
2933                 switch (pipe) {
2934                 case 0:
2935                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2936                         break;
2937                 case 1:
2938                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2939                         break;
2940                 case 2:
2941                         /* C shares PLL A or B */
2942                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2943                         break;
2944                 default:
2945                         BUG(); /* wtf */
2946                 }
2947                 I915_WRITE(PCH_DPLL_SEL, temp);
2948         }
2949
2950         /* disable PCH DPLL */
2951         intel_disable_pch_pll(intel_crtc);
2952
2953         /* Switch from PCDclk to Rawclk */
2954         reg = FDI_RX_CTL(pipe);
2955         temp = I915_READ(reg);
2956         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2957
2958         /* Disable CPU FDI TX PLL */
2959         reg = FDI_TX_CTL(pipe);
2960         temp = I915_READ(reg);
2961         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2962
2963         POSTING_READ(reg);
2964         udelay(100);
2965
2966         reg = FDI_RX_CTL(pipe);
2967         temp = I915_READ(reg);
2968         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2969
2970         /* Wait for the clocks to turn off. */
2971         POSTING_READ(reg);
2972         udelay(100);
2973
2974         intel_crtc->active = false;
2975         intel_update_watermarks(dev);
2976
2977         mutex_lock(&dev->struct_mutex);
2978         intel_update_fbc(dev);
2979         mutex_unlock(&dev->struct_mutex);
2980 }
2981
2982 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2983 {
2984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2985         int pipe = intel_crtc->pipe;
2986         int plane = intel_crtc->plane;
2987
2988         /* XXX: When our outputs are all unaware of DPMS modes other than off
2989          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2990          */
2991         switch (mode) {
2992         case DRM_MODE_DPMS_ON:
2993         case DRM_MODE_DPMS_STANDBY:
2994         case DRM_MODE_DPMS_SUSPEND:
2995                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2996                 ironlake_crtc_enable(crtc);
2997                 break;
2998
2999         case DRM_MODE_DPMS_OFF:
3000                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3001                 ironlake_crtc_disable(crtc);
3002                 break;
3003         }
3004 }
3005
3006 static void ironlake_crtc_off(struct drm_crtc *crtc)
3007 {
3008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3009         intel_put_pch_pll(intel_crtc);
3010 }
3011
3012 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3013 {
3014         if (!enable && intel_crtc->overlay) {
3015                 struct drm_device *dev = intel_crtc->base.dev;
3016                 struct drm_i915_private *dev_priv = dev->dev_private;
3017
3018                 mutex_lock(&dev->struct_mutex);
3019                 dev_priv->mm.interruptible = false;
3020                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3021                 dev_priv->mm.interruptible = true;
3022                 mutex_unlock(&dev->struct_mutex);
3023         }
3024
3025         /* Let userspace switch the overlay on again. In most cases userspace
3026          * has to recompute where to put it anyway.
3027          */
3028 }
3029
3030 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3031 {
3032         struct drm_device *dev = crtc->dev;
3033         struct drm_i915_private *dev_priv = dev->dev_private;
3034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035         int pipe = intel_crtc->pipe;
3036         int plane = intel_crtc->plane;
3037
3038         if (intel_crtc->active)
3039                 return;
3040
3041         intel_crtc->active = true;
3042         intel_update_watermarks(dev);
3043
3044         intel_enable_pll(dev_priv, pipe);
3045         intel_enable_pipe(dev_priv, pipe, false);
3046         intel_enable_plane(dev_priv, plane, pipe);
3047
3048         intel_crtc_load_lut(crtc);
3049         intel_update_fbc(dev);
3050
3051         /* Give the overlay scaler a chance to enable if it's on this pipe */
3052         intel_crtc_dpms_overlay(intel_crtc, true);
3053         intel_crtc_update_cursor(crtc, true);
3054 }
3055
3056 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3057 {
3058         struct drm_device *dev = crtc->dev;
3059         struct drm_i915_private *dev_priv = dev->dev_private;
3060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3061         int pipe = intel_crtc->pipe;
3062         int plane = intel_crtc->plane;
3063
3064         if (!intel_crtc->active)
3065                 return;
3066
3067         /* Give the overlay scaler a chance to disable if it's on this pipe */
3068         intel_crtc_wait_for_pending_flips(crtc);
3069         drm_vblank_off(dev, pipe);
3070         intel_crtc_dpms_overlay(intel_crtc, false);
3071         intel_crtc_update_cursor(crtc, false);
3072
3073         if (dev_priv->cfb_plane == plane)
3074                 intel_disable_fbc(dev);
3075
3076         intel_disable_plane(dev_priv, plane, pipe);
3077         intel_disable_pipe(dev_priv, pipe);
3078         intel_disable_pll(dev_priv, pipe);
3079
3080         intel_crtc->active = false;
3081         intel_update_fbc(dev);
3082         intel_update_watermarks(dev);
3083 }
3084
3085 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3086 {
3087         /* XXX: When our outputs are all unaware of DPMS modes other than off
3088          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3089          */
3090         switch (mode) {
3091         case DRM_MODE_DPMS_ON:
3092         case DRM_MODE_DPMS_STANDBY:
3093         case DRM_MODE_DPMS_SUSPEND:
3094                 i9xx_crtc_enable(crtc);
3095                 break;
3096         case DRM_MODE_DPMS_OFF:
3097                 i9xx_crtc_disable(crtc);
3098                 break;
3099         }
3100 }
3101
3102 static void i9xx_crtc_off(struct drm_crtc *crtc)
3103 {
3104 }
3105
3106 /**
3107  * Sets the power management mode of the pipe and plane.
3108  */
3109 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3110 {
3111         struct drm_device *dev = crtc->dev;
3112         struct drm_i915_private *dev_priv = dev->dev_private;
3113         struct drm_i915_master_private *master_priv;
3114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3115         int pipe = intel_crtc->pipe;
3116         bool enabled;
3117
3118         if (intel_crtc->dpms_mode == mode)
3119                 return;
3120
3121         intel_crtc->dpms_mode = mode;
3122
3123         dev_priv->display.dpms(crtc, mode);
3124
3125         if (!dev->primary->master)
3126                 return;
3127
3128         master_priv = dev->primary->master->driver_priv;
3129         if (!master_priv->sarea_priv)
3130                 return;
3131
3132         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3133
3134         switch (pipe) {
3135         case 0:
3136                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3137                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3138                 break;
3139         case 1:
3140                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3141                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3142                 break;
3143         default:
3144                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3145                 break;
3146         }
3147 }
3148
3149 static void intel_crtc_disable(struct drm_crtc *crtc)
3150 {
3151         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3152         struct drm_device *dev = crtc->dev;
3153         struct drm_i915_private *dev_priv = dev->dev_private;
3154
3155         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3156         dev_priv->display.off(crtc);
3157
3158         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3159         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3160
3161         if (crtc->fb) {
3162                 mutex_lock(&dev->struct_mutex);
3163                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3164                 mutex_unlock(&dev->struct_mutex);
3165         }
3166 }
3167
3168 /* Prepare for a mode set.
3169  *
3170  * Note we could be a lot smarter here.  We need to figure out which outputs
3171  * will be enabled, which disabled (in short, how the config will changes)
3172  * and perform the minimum necessary steps to accomplish that, e.g. updating
3173  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3174  * panel fitting is in the proper state, etc.
3175  */
3176 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3177 {
3178         i9xx_crtc_disable(crtc);
3179 }
3180
3181 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3182 {
3183         i9xx_crtc_enable(crtc);
3184 }
3185
3186 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3187 {
3188         ironlake_crtc_disable(crtc);
3189 }
3190
3191 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3192 {
3193         ironlake_crtc_enable(crtc);
3194 }
3195
3196 void intel_encoder_prepare(struct drm_encoder *encoder)
3197 {
3198         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3199         /* lvds has its own version of prepare see intel_lvds_prepare */
3200         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3201 }
3202
3203 void intel_encoder_commit(struct drm_encoder *encoder)
3204 {
3205         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3206         struct drm_device *dev = encoder->dev;
3207         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3208
3209         /* lvds has its own version of commit see intel_lvds_commit */
3210         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3211
3212         if (HAS_PCH_CPT(dev))
3213                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3214 }
3215
3216 void intel_encoder_destroy(struct drm_encoder *encoder)
3217 {
3218         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3219
3220         drm_encoder_cleanup(encoder);
3221         kfree(intel_encoder);
3222 }
3223
3224 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3225                                   struct drm_display_mode *mode,
3226                                   struct drm_display_mode *adjusted_mode)
3227 {
3228         struct drm_device *dev = crtc->dev;
3229
3230         if (HAS_PCH_SPLIT(dev)) {
3231                 /* FDI link clock is fixed at 2.7G */
3232                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3233                         return false;
3234         }
3235
3236         /* All interlaced capable intel hw wants timings in frames. Note though
3237          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3238          * timings, so we need to be careful not to clobber these.*/
3239         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3240                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3241
3242         return true;
3243 }
3244
3245 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3246 {
3247         return 400000; /* FIXME */
3248 }
3249
3250 static int i945_get_display_clock_speed(struct drm_device *dev)
3251 {
3252         return 400000;
3253 }
3254
3255 static int i915_get_display_clock_speed(struct drm_device *dev)
3256 {
3257         return 333000;
3258 }
3259
3260 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3261 {
3262         return 200000;
3263 }
3264
3265 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3266 {
3267         u16 gcfgc = 0;
3268
3269         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3270
3271         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3272                 return 133000;
3273         else {
3274                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3275                 case GC_DISPLAY_CLOCK_333_MHZ:
3276                         return 333000;
3277                 default:
3278                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3279                         return 190000;
3280                 }
3281         }
3282 }
3283
3284 static int i865_get_display_clock_speed(struct drm_device *dev)
3285 {
3286         return 266000;
3287 }
3288
3289 static int i855_get_display_clock_speed(struct drm_device *dev)
3290 {
3291         u16 hpllcc = 0;
3292         /* Assume that the hardware is in the high speed state.  This
3293          * should be the default.
3294          */
3295         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3296         case GC_CLOCK_133_200:
3297         case GC_CLOCK_100_200:
3298                 return 200000;
3299         case GC_CLOCK_166_250:
3300                 return 250000;
3301         case GC_CLOCK_100_133:
3302                 return 133000;
3303         }
3304
3305         /* Shouldn't happen */
3306         return 0;
3307 }
3308
3309 static int i830_get_display_clock_speed(struct drm_device *dev)
3310 {
3311         return 133000;
3312 }
3313
3314 struct fdi_m_n {
3315         u32        tu;
3316         u32        gmch_m;
3317         u32        gmch_n;
3318         u32        link_m;
3319         u32        link_n;
3320 };
3321
3322 static void
3323 fdi_reduce_ratio(u32 *num, u32 *den)
3324 {
3325         while (*num > 0xffffff || *den > 0xffffff) {
3326                 *num >>= 1;
3327                 *den >>= 1;
3328         }
3329 }
3330
3331 static void
3332 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3333                      int link_clock, struct fdi_m_n *m_n)
3334 {
3335         m_n->tu = 64; /* default size */
3336
3337         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3338         m_n->gmch_m = bits_per_pixel * pixel_clock;
3339         m_n->gmch_n = link_clock * nlanes * 8;
3340         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3341
3342         m_n->link_m = pixel_clock;
3343         m_n->link_n = link_clock;
3344         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3345 }
3346
3347 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3348 {
3349         if (i915_panel_use_ssc >= 0)
3350                 return i915_panel_use_ssc != 0;
3351         return dev_priv->lvds_use_ssc
3352                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3353 }
3354
3355 /**
3356  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3357  * @crtc: CRTC structure
3358  * @mode: requested mode
3359  *
3360  * A pipe may be connected to one or more outputs.  Based on the depth of the
3361  * attached framebuffer, choose a good color depth to use on the pipe.
3362  *
3363  * If possible, match the pipe depth to the fb depth.  In some cases, this
3364  * isn't ideal, because the connected output supports a lesser or restricted
3365  * set of depths.  Resolve that here:
3366  *    LVDS typically supports only 6bpc, so clamp down in that case
3367  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3368  *    Displays may support a restricted set as well, check EDID and clamp as
3369  *      appropriate.
3370  *    DP may want to dither down to 6bpc to fit larger modes
3371  *
3372  * RETURNS:
3373  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3374  * true if they don't match).
3375  */
3376 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3377                                          unsigned int *pipe_bpp,
3378                                          struct drm_display_mode *mode)
3379 {
3380         struct drm_device *dev = crtc->dev;
3381         struct drm_i915_private *dev_priv = dev->dev_private;
3382         struct drm_encoder *encoder;
3383         struct drm_connector *connector;
3384         unsigned int display_bpc = UINT_MAX, bpc;
3385
3386         /* Walk the encoders & connectors on this crtc, get min bpc */
3387         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3388                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3389
3390                 if (encoder->crtc != crtc)
3391                         continue;
3392
3393                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3394                         unsigned int lvds_bpc;
3395
3396                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3397                             LVDS_A3_POWER_UP)
3398                                 lvds_bpc = 8;
3399                         else
3400                                 lvds_bpc = 6;
3401
3402                         if (lvds_bpc < display_bpc) {
3403                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3404                                 display_bpc = lvds_bpc;
3405                         }
3406                         continue;
3407                 }
3408
3409                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3410                         /* Use VBT settings if we have an eDP panel */
3411                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3412
3413                         if (edp_bpc < display_bpc) {
3414                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3415                                 display_bpc = edp_bpc;
3416                         }
3417                         continue;
3418                 }
3419
3420                 /* Not one of the known troublemakers, check the EDID */
3421                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3422                                     head) {
3423                         if (connector->encoder != encoder)
3424                                 continue;
3425
3426                         /* Don't use an invalid EDID bpc value */
3427                         if (connector->display_info.bpc &&
3428                             connector->display_info.bpc < display_bpc) {
3429                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3430                                 display_bpc = connector->display_info.bpc;
3431                         }
3432                 }
3433
3434                 /*
3435                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3436                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3437                  */
3438                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3439                         if (display_bpc > 8 && display_bpc < 12) {
3440                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3441                                 display_bpc = 12;
3442                         } else {
3443                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3444                                 display_bpc = 8;
3445                         }
3446                 }
3447         }
3448
3449         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3450                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3451                 display_bpc = 6;
3452         }
3453
3454         /*
3455          * We could just drive the pipe at the highest bpc all the time and
3456          * enable dithering as needed, but that costs bandwidth.  So choose
3457          * the minimum value that expresses the full color range of the fb but
3458          * also stays within the max display bpc discovered above.
3459          */
3460
3461         switch (crtc->fb->depth) {
3462         case 8:
3463                 bpc = 8; /* since we go through a colormap */
3464                 break;
3465         case 15:
3466         case 16:
3467                 bpc = 6; /* min is 18bpp */
3468                 break;
3469         case 24:
3470                 bpc = 8;
3471                 break;
3472         case 30:
3473                 bpc = 10;
3474                 break;
3475         case 48:
3476                 bpc = 12;
3477                 break;
3478         default:
3479                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3480                 bpc = min((unsigned int)8, display_bpc);
3481                 break;
3482         }
3483
3484         display_bpc = min(display_bpc, bpc);
3485
3486         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3487                       bpc, display_bpc);
3488
3489         *pipe_bpp = display_bpc * 3;
3490
3491         return display_bpc != bpc;
3492 }
3493
3494 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3495 {
3496         struct drm_device *dev = crtc->dev;
3497         struct drm_i915_private *dev_priv = dev->dev_private;
3498         int refclk;
3499
3500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3501             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3502                 refclk = dev_priv->lvds_ssc_freq * 1000;
3503                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3504                               refclk / 1000);
3505         } else if (!IS_GEN2(dev)) {
3506                 refclk = 96000;
3507         } else {
3508                 refclk = 48000;
3509         }
3510
3511         return refclk;
3512 }
3513
3514 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3515                                       intel_clock_t *clock)
3516 {
3517         /* SDVO TV has fixed PLL values depend on its clock range,
3518            this mirrors vbios setting. */
3519         if (adjusted_mode->clock >= 100000
3520             && adjusted_mode->clock < 140500) {
3521                 clock->p1 = 2;
3522                 clock->p2 = 10;
3523                 clock->n = 3;
3524                 clock->m1 = 16;
3525                 clock->m2 = 8;
3526         } else if (adjusted_mode->clock >= 140500
3527                    && adjusted_mode->clock <= 200000) {
3528                 clock->p1 = 1;
3529                 clock->p2 = 10;
3530                 clock->n = 6;
3531                 clock->m1 = 12;
3532                 clock->m2 = 8;
3533         }
3534 }
3535
3536 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3537                                      intel_clock_t *clock,
3538                                      intel_clock_t *reduced_clock)
3539 {
3540         struct drm_device *dev = crtc->dev;
3541         struct drm_i915_private *dev_priv = dev->dev_private;
3542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3543         int pipe = intel_crtc->pipe;
3544         u32 fp, fp2 = 0;
3545
3546         if (IS_PINEVIEW(dev)) {
3547                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3548                 if (reduced_clock)
3549                         fp2 = (1 << reduced_clock->n) << 16 |
3550                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3551         } else {
3552                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3553                 if (reduced_clock)
3554                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3555                                 reduced_clock->m2;
3556         }
3557
3558         I915_WRITE(FP0(pipe), fp);
3559
3560         intel_crtc->lowfreq_avail = false;
3561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3562             reduced_clock && i915_powersave) {
3563                 I915_WRITE(FP1(pipe), fp2);
3564                 intel_crtc->lowfreq_avail = true;
3565         } else {
3566                 I915_WRITE(FP1(pipe), fp);
3567         }
3568 }
3569
3570 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3571                               struct drm_display_mode *adjusted_mode)
3572 {
3573         struct drm_device *dev = crtc->dev;
3574         struct drm_i915_private *dev_priv = dev->dev_private;
3575         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3576         int pipe = intel_crtc->pipe;
3577         u32 temp;
3578
3579         temp = I915_READ(LVDS);
3580         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3581         if (pipe == 1) {
3582                 temp |= LVDS_PIPEB_SELECT;
3583         } else {
3584                 temp &= ~LVDS_PIPEB_SELECT;
3585         }
3586         /* set the corresponsding LVDS_BORDER bit */
3587         temp |= dev_priv->lvds_border_bits;
3588         /* Set the B0-B3 data pairs corresponding to whether we're going to
3589          * set the DPLLs for dual-channel mode or not.
3590          */
3591         if (clock->p2 == 7)
3592                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3593         else
3594                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3595
3596         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3597          * appropriately here, but we need to look more thoroughly into how
3598          * panels behave in the two modes.
3599          */
3600         /* set the dithering flag on LVDS as needed */
3601         if (INTEL_INFO(dev)->gen >= 4) {
3602                 if (dev_priv->lvds_dither)
3603                         temp |= LVDS_ENABLE_DITHER;
3604                 else
3605                         temp &= ~LVDS_ENABLE_DITHER;
3606         }
3607         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3608         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3609                 temp |= LVDS_HSYNC_POLARITY;
3610         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3611                 temp |= LVDS_VSYNC_POLARITY;
3612         I915_WRITE(LVDS, temp);
3613 }
3614
3615 static void i9xx_update_pll(struct drm_crtc *crtc,
3616                             struct drm_display_mode *mode,
3617                             struct drm_display_mode *adjusted_mode,
3618                             intel_clock_t *clock, intel_clock_t *reduced_clock,
3619                             int num_connectors)
3620 {
3621         struct drm_device *dev = crtc->dev;
3622         struct drm_i915_private *dev_priv = dev->dev_private;
3623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3624         int pipe = intel_crtc->pipe;
3625         u32 dpll;
3626         bool is_sdvo;
3627
3628         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3629                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3630
3631         dpll = DPLL_VGA_MODE_DIS;
3632
3633         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3634                 dpll |= DPLLB_MODE_LVDS;
3635         else
3636                 dpll |= DPLLB_MODE_DAC_SERIAL;
3637         if (is_sdvo) {
3638                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3639                 if (pixel_multiplier > 1) {
3640                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3641                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3642                 }
3643                 dpll |= DPLL_DVO_HIGH_SPEED;
3644         }
3645         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3646                 dpll |= DPLL_DVO_HIGH_SPEED;
3647
3648         /* compute bitmask from p1 value */
3649         if (IS_PINEVIEW(dev))
3650                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3651         else {
3652                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3653                 if (IS_G4X(dev) && reduced_clock)
3654                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3655         }
3656         switch (clock->p2) {
3657         case 5:
3658                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3659                 break;
3660         case 7:
3661                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3662                 break;
3663         case 10:
3664                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3665                 break;
3666         case 14:
3667                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3668                 break;
3669         }
3670         if (INTEL_INFO(dev)->gen >= 4)
3671                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3672
3673         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3674                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3675         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3676                 /* XXX: just matching BIOS for now */
3677                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3678                 dpll |= 3;
3679         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3680                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3681                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3682         else
3683                 dpll |= PLL_REF_INPUT_DREFCLK;
3684
3685         dpll |= DPLL_VCO_ENABLE;
3686         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3687         POSTING_READ(DPLL(pipe));
3688         udelay(150);
3689
3690         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3691          * This is an exception to the general rule that mode_set doesn't turn
3692          * things on.
3693          */
3694         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3695                 intel_update_lvds(crtc, clock, adjusted_mode);
3696
3697         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3698                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3699
3700         I915_WRITE(DPLL(pipe), dpll);
3701
3702         /* Wait for the clocks to stabilize. */
3703         POSTING_READ(DPLL(pipe));
3704         udelay(150);
3705
3706         if (INTEL_INFO(dev)->gen >= 4) {
3707                 u32 temp = 0;
3708                 if (is_sdvo) {
3709                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3710                         if (temp > 1)
3711                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3712                         else
3713                                 temp = 0;
3714                 }
3715                 I915_WRITE(DPLL_MD(pipe), temp);
3716         } else {
3717                 /* The pixel multiplier can only be updated once the
3718                  * DPLL is enabled and the clocks are stable.
3719                  *
3720                  * So write it again.
3721                  */
3722                 I915_WRITE(DPLL(pipe), dpll);
3723         }
3724 }
3725
3726 static void i8xx_update_pll(struct drm_crtc *crtc,
3727                             struct drm_display_mode *adjusted_mode,
3728                             intel_clock_t *clock,
3729                             int num_connectors)
3730 {
3731         struct drm_device *dev = crtc->dev;
3732         struct drm_i915_private *dev_priv = dev->dev_private;
3733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3734         int pipe = intel_crtc->pipe;
3735         u32 dpll;
3736
3737         dpll = DPLL_VGA_MODE_DIS;
3738
3739         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3740                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3741         } else {
3742                 if (clock->p1 == 2)
3743                         dpll |= PLL_P1_DIVIDE_BY_TWO;
3744                 else
3745                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3746                 if (clock->p2 == 4)
3747                         dpll |= PLL_P2_DIVIDE_BY_4;
3748         }
3749
3750         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3751                 /* XXX: just matching BIOS for now */
3752                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3753                 dpll |= 3;
3754         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3755                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3756                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3757         else
3758                 dpll |= PLL_REF_INPUT_DREFCLK;
3759
3760         dpll |= DPLL_VCO_ENABLE;
3761         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3762         POSTING_READ(DPLL(pipe));
3763         udelay(150);
3764
3765         I915_WRITE(DPLL(pipe), dpll);
3766
3767         /* Wait for the clocks to stabilize. */
3768         POSTING_READ(DPLL(pipe));
3769         udelay(150);
3770
3771         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3772          * This is an exception to the general rule that mode_set doesn't turn
3773          * things on.
3774          */
3775         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3776                 intel_update_lvds(crtc, clock, adjusted_mode);
3777
3778         /* The pixel multiplier can only be updated once the
3779          * DPLL is enabled and the clocks are stable.
3780          *
3781          * So write it again.
3782          */
3783         I915_WRITE(DPLL(pipe), dpll);
3784 }
3785
3786 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3787                               struct drm_display_mode *mode,
3788                               struct drm_display_mode *adjusted_mode,
3789                               int x, int y,
3790                               struct drm_framebuffer *old_fb)
3791 {
3792         struct drm_device *dev = crtc->dev;
3793         struct drm_i915_private *dev_priv = dev->dev_private;
3794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3795         int pipe = intel_crtc->pipe;
3796         int plane = intel_crtc->plane;
3797         int refclk, num_connectors = 0;
3798         intel_clock_t clock, reduced_clock;
3799         u32 dspcntr, pipeconf, vsyncshift;
3800         bool ok, has_reduced_clock = false, is_sdvo = false;
3801         bool is_lvds = false, is_tv = false, is_dp = false;
3802         struct drm_mode_config *mode_config = &dev->mode_config;
3803         struct intel_encoder *encoder;
3804         const intel_limit_t *limit;
3805         int ret;
3806
3807         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3808                 if (encoder->base.crtc != crtc)
3809                         continue;
3810
3811                 switch (encoder->type) {
3812                 case INTEL_OUTPUT_LVDS:
3813                         is_lvds = true;
3814                         break;
3815                 case INTEL_OUTPUT_SDVO:
3816                 case INTEL_OUTPUT_HDMI:
3817                         is_sdvo = true;
3818                         if (encoder->needs_tv_clock)
3819                                 is_tv = true;
3820                         break;
3821                 case INTEL_OUTPUT_TVOUT:
3822                         is_tv = true;
3823                         break;
3824                 case INTEL_OUTPUT_DISPLAYPORT:
3825                         is_dp = true;
3826                         break;
3827                 }
3828
3829                 num_connectors++;
3830         }
3831
3832         refclk = i9xx_get_refclk(crtc, num_connectors);
3833
3834         /*
3835          * Returns a set of divisors for the desired target clock with the given
3836          * refclk, or FALSE.  The returned values represent the clock equation:
3837          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3838          */
3839         limit = intel_limit(crtc, refclk);
3840         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3841                              &clock);
3842         if (!ok) {
3843                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3844                 return -EINVAL;
3845         }
3846
3847         /* Ensure that the cursor is valid for the new mode before changing... */
3848         intel_crtc_update_cursor(crtc, true);
3849
3850         if (is_lvds && dev_priv->lvds_downclock_avail) {
3851                 /*
3852                  * Ensure we match the reduced clock's P to the target clock.
3853                  * If the clocks don't match, we can't switch the display clock
3854                  * by using the FP0/FP1. In such case we will disable the LVDS
3855                  * downclock feature.
3856                 */
3857                 has_reduced_clock = limit->find_pll(limit, crtc,
3858                                                     dev_priv->lvds_downclock,
3859                                                     refclk,
3860                                                     &clock,
3861                                                     &reduced_clock);
3862         }
3863
3864         if (is_sdvo && is_tv)
3865                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
3866
3867         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3868                                  &reduced_clock : NULL);
3869
3870         if (IS_GEN2(dev))
3871                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
3872         else
3873                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3874                                 has_reduced_clock ? &reduced_clock : NULL,
3875                                 num_connectors);
3876
3877         /* setup pipeconf */
3878         pipeconf = I915_READ(PIPECONF(pipe));
3879
3880         /* Set up the display plane register */
3881         dspcntr = DISPPLANE_GAMMA_ENABLE;
3882
3883         if (pipe == 0)
3884                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3885         else
3886                 dspcntr |= DISPPLANE_SEL_PIPE_B;
3887
3888         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3889                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3890                  * core speed.
3891                  *
3892                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3893                  * pipe == 0 check?
3894                  */
3895                 if (mode->clock >
3896                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3897                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3898                 else
3899                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3900         }
3901
3902         /* default to 8bpc */
3903         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3904         if (is_dp) {
3905                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3906                         pipeconf |= PIPECONF_BPP_6 |
3907                                     PIPECONF_DITHER_EN |
3908                                     PIPECONF_DITHER_TYPE_SP;
3909                 }
3910         }
3911
3912         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3913         drm_mode_debug_printmodeline(mode);
3914
3915         if (HAS_PIPE_CXSR(dev)) {
3916                 if (intel_crtc->lowfreq_avail) {
3917                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3918                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3919                 } else {
3920                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3921                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3922                 }
3923         }
3924
3925         pipeconf &= ~PIPECONF_INTERLACE_MASK;
3926         if (!IS_GEN2(dev) &&
3927             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3928                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3929                 /* the chip adds 2 halflines automatically */
3930                 adjusted_mode->crtc_vtotal -= 1;
3931                 adjusted_mode->crtc_vblank_end -= 1;
3932                 vsyncshift = adjusted_mode->crtc_hsync_start
3933                              - adjusted_mode->crtc_htotal/2;
3934         } else {
3935                 pipeconf |= PIPECONF_PROGRESSIVE;
3936                 vsyncshift = 0;
3937         }
3938
3939         if (!IS_GEN3(dev))
3940                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
3941
3942         I915_WRITE(HTOTAL(pipe),
3943                    (adjusted_mode->crtc_hdisplay - 1) |
3944                    ((adjusted_mode->crtc_htotal - 1) << 16));
3945         I915_WRITE(HBLANK(pipe),
3946                    (adjusted_mode->crtc_hblank_start - 1) |
3947                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3948         I915_WRITE(HSYNC(pipe),
3949                    (adjusted_mode->crtc_hsync_start - 1) |
3950                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3951
3952         I915_WRITE(VTOTAL(pipe),
3953                    (adjusted_mode->crtc_vdisplay - 1) |
3954                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3955         I915_WRITE(VBLANK(pipe),
3956                    (adjusted_mode->crtc_vblank_start - 1) |
3957                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3958         I915_WRITE(VSYNC(pipe),
3959                    (adjusted_mode->crtc_vsync_start - 1) |
3960                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3961
3962         /* pipesrc and dspsize control the size that is scaled from,
3963          * which should always be the user's requested size.
3964          */
3965         I915_WRITE(DSPSIZE(plane),
3966                    ((mode->vdisplay - 1) << 16) |
3967                    (mode->hdisplay - 1));
3968         I915_WRITE(DSPPOS(plane), 0);
3969         I915_WRITE(PIPESRC(pipe),
3970                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3971
3972         I915_WRITE(PIPECONF(pipe), pipeconf);
3973         POSTING_READ(PIPECONF(pipe));
3974         intel_enable_pipe(dev_priv, pipe, false);
3975
3976         intel_wait_for_vblank(dev, pipe);
3977
3978         I915_WRITE(DSPCNTR(plane), dspcntr);
3979         POSTING_READ(DSPCNTR(plane));
3980
3981         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3982
3983         intel_update_watermarks(dev);
3984
3985         return ret;
3986 }
3987
3988 /*
3989  * Initialize reference clocks when the driver loads
3990  */
3991 void ironlake_init_pch_refclk(struct drm_device *dev)
3992 {
3993         struct drm_i915_private *dev_priv = dev->dev_private;
3994         struct drm_mode_config *mode_config = &dev->mode_config;
3995         struct intel_encoder *encoder;
3996         u32 temp;
3997         bool has_lvds = false;
3998         bool has_cpu_edp = false;
3999         bool has_pch_edp = false;
4000         bool has_panel = false;
4001         bool has_ck505 = false;
4002         bool can_ssc = false;
4003
4004         /* We need to take the global config into account */
4005         list_for_each_entry(encoder, &mode_config->encoder_list,
4006                             base.head) {
4007                 switch (encoder->type) {
4008                 case INTEL_OUTPUT_LVDS:
4009                         has_panel = true;
4010                         has_lvds = true;
4011                         break;
4012                 case INTEL_OUTPUT_EDP:
4013                         has_panel = true;
4014                         if (intel_encoder_is_pch_edp(&encoder->base))
4015                                 has_pch_edp = true;
4016                         else
4017                                 has_cpu_edp = true;
4018                         break;
4019                 }
4020         }
4021
4022         if (HAS_PCH_IBX(dev)) {
4023                 has_ck505 = dev_priv->display_clock_mode;
4024                 can_ssc = has_ck505;
4025         } else {
4026                 has_ck505 = false;
4027                 can_ssc = true;
4028         }
4029
4030         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4031                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4032                       has_ck505);
4033
4034         /* Ironlake: try to setup display ref clock before DPLL
4035          * enabling. This is only under driver's control after
4036          * PCH B stepping, previous chipset stepping should be
4037          * ignoring this setting.
4038          */
4039         temp = I915_READ(PCH_DREF_CONTROL);
4040         /* Always enable nonspread source */
4041         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4042
4043         if (has_ck505)
4044                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4045         else
4046                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4047
4048         if (has_panel) {
4049                 temp &= ~DREF_SSC_SOURCE_MASK;
4050                 temp |= DREF_SSC_SOURCE_ENABLE;
4051
4052                 /* SSC must be turned on before enabling the CPU output  */
4053                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4054                         DRM_DEBUG_KMS("Using SSC on panel\n");
4055                         temp |= DREF_SSC1_ENABLE;
4056                 } else
4057                         temp &= ~DREF_SSC1_ENABLE;
4058
4059                 /* Get SSC going before enabling the outputs */
4060                 I915_WRITE(PCH_DREF_CONTROL, temp);
4061                 POSTING_READ(PCH_DREF_CONTROL);
4062                 udelay(200);
4063
4064                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4065
4066                 /* Enable CPU source on CPU attached eDP */
4067                 if (has_cpu_edp) {
4068                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4069                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4070                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4071                         }
4072                         else
4073                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4074                 } else
4075                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4076
4077                 I915_WRITE(PCH_DREF_CONTROL, temp);
4078                 POSTING_READ(PCH_DREF_CONTROL);
4079                 udelay(200);
4080         } else {
4081                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4082
4083                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4084
4085                 /* Turn off CPU output */
4086                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4087
4088                 I915_WRITE(PCH_DREF_CONTROL, temp);
4089                 POSTING_READ(PCH_DREF_CONTROL);
4090                 udelay(200);
4091
4092                 /* Turn off the SSC source */
4093                 temp &= ~DREF_SSC_SOURCE_MASK;
4094                 temp |= DREF_SSC_SOURCE_DISABLE;
4095
4096                 /* Turn off SSC1 */
4097                 temp &= ~ DREF_SSC1_ENABLE;
4098
4099                 I915_WRITE(PCH_DREF_CONTROL, temp);
4100                 POSTING_READ(PCH_DREF_CONTROL);
4101                 udelay(200);
4102         }
4103 }
4104
4105 static int ironlake_get_refclk(struct drm_crtc *crtc)
4106 {
4107         struct drm_device *dev = crtc->dev;
4108         struct drm_i915_private *dev_priv = dev->dev_private;
4109         struct intel_encoder *encoder;
4110         struct drm_mode_config *mode_config = &dev->mode_config;
4111         struct intel_encoder *edp_encoder = NULL;
4112         int num_connectors = 0;
4113         bool is_lvds = false;
4114
4115         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4116                 if (encoder->base.crtc != crtc)
4117                         continue;
4118
4119                 switch (encoder->type) {
4120                 case INTEL_OUTPUT_LVDS:
4121                         is_lvds = true;
4122                         break;
4123                 case INTEL_OUTPUT_EDP:
4124                         edp_encoder = encoder;
4125                         break;
4126                 }
4127                 num_connectors++;
4128         }
4129
4130         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4131                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4132                               dev_priv->lvds_ssc_freq);
4133                 return dev_priv->lvds_ssc_freq * 1000;
4134         }
4135
4136         return 120000;
4137 }
4138
4139 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4140                                   struct drm_display_mode *mode,
4141                                   struct drm_display_mode *adjusted_mode,
4142                                   int x, int y,
4143                                   struct drm_framebuffer *old_fb)
4144 {
4145         struct drm_device *dev = crtc->dev;
4146         struct drm_i915_private *dev_priv = dev->dev_private;
4147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4148         int pipe = intel_crtc->pipe;
4149         int plane = intel_crtc->plane;
4150         int refclk, num_connectors = 0;
4151         intel_clock_t clock, reduced_clock;
4152         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4153         bool ok, has_reduced_clock = false, is_sdvo = false;
4154         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4155         struct drm_mode_config *mode_config = &dev->mode_config;
4156         struct intel_encoder *encoder, *edp_encoder = NULL;
4157         const intel_limit_t *limit;
4158         int ret;
4159         struct fdi_m_n m_n = {0};
4160         u32 temp;
4161         int target_clock, pixel_multiplier, lane, link_bw, factor;
4162         unsigned int pipe_bpp;
4163         bool dither;
4164         bool is_cpu_edp = false, is_pch_edp = false;
4165
4166         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4167                 if (encoder->base.crtc != crtc)
4168                         continue;
4169
4170                 switch (encoder->type) {
4171                 case INTEL_OUTPUT_LVDS:
4172                         is_lvds = true;
4173                         break;
4174                 case INTEL_OUTPUT_SDVO:
4175                 case INTEL_OUTPUT_HDMI:
4176                         is_sdvo = true;
4177                         if (encoder->needs_tv_clock)
4178                                 is_tv = true;
4179                         break;
4180                 case INTEL_OUTPUT_TVOUT:
4181                         is_tv = true;
4182                         break;
4183                 case INTEL_OUTPUT_ANALOG:
4184                         is_crt = true;
4185                         break;
4186                 case INTEL_OUTPUT_DISPLAYPORT:
4187                         is_dp = true;
4188                         break;
4189                 case INTEL_OUTPUT_EDP:
4190                         is_dp = true;
4191                         if (intel_encoder_is_pch_edp(&encoder->base))
4192                                 is_pch_edp = true;
4193                         else
4194                                 is_cpu_edp = true;
4195                         edp_encoder = encoder;
4196                         break;
4197                 }
4198
4199                 num_connectors++;
4200         }
4201
4202         refclk = ironlake_get_refclk(crtc);
4203
4204         /*
4205          * Returns a set of divisors for the desired target clock with the given
4206          * refclk, or FALSE.  The returned values represent the clock equation:
4207          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4208          */
4209         limit = intel_limit(crtc, refclk);
4210         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4211                              &clock);
4212         if (!ok) {
4213                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4214                 return -EINVAL;
4215         }
4216
4217         /* Ensure that the cursor is valid for the new mode before changing... */
4218         intel_crtc_update_cursor(crtc, true);
4219
4220         if (is_lvds && dev_priv->lvds_downclock_avail) {
4221                 /*
4222                  * Ensure we match the reduced clock's P to the target clock.
4223                  * If the clocks don't match, we can't switch the display clock
4224                  * by using the FP0/FP1. In such case we will disable the LVDS
4225                  * downclock feature.
4226                 */
4227                 has_reduced_clock = limit->find_pll(limit, crtc,
4228                                                     dev_priv->lvds_downclock,
4229                                                     refclk,
4230                                                     &clock,
4231                                                     &reduced_clock);
4232         }
4233         /* SDVO TV has fixed PLL values depend on its clock range,
4234            this mirrors vbios setting. */
4235         if (is_sdvo && is_tv) {
4236                 if (adjusted_mode->clock >= 100000
4237                     && adjusted_mode->clock < 140500) {
4238                         clock.p1 = 2;
4239                         clock.p2 = 10;
4240                         clock.n = 3;
4241                         clock.m1 = 16;
4242                         clock.m2 = 8;
4243                 } else if (adjusted_mode->clock >= 140500
4244                            && adjusted_mode->clock <= 200000) {
4245                         clock.p1 = 1;
4246                         clock.p2 = 10;
4247                         clock.n = 6;
4248                         clock.m1 = 12;
4249                         clock.m2 = 8;
4250                 }
4251         }
4252
4253         /* FDI link */
4254         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4255         lane = 0;
4256         /* CPU eDP doesn't require FDI link, so just set DP M/N
4257            according to current link config */
4258         if (is_cpu_edp) {
4259                 target_clock = mode->clock;
4260                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4261         } else {
4262                 /* [e]DP over FDI requires target mode clock
4263                    instead of link clock */
4264                 if (is_dp)
4265                         target_clock = mode->clock;
4266                 else
4267                         target_clock = adjusted_mode->clock;
4268
4269                 /* FDI is a binary signal running at ~2.7GHz, encoding
4270                  * each output octet as 10 bits. The actual frequency
4271                  * is stored as a divider into a 100MHz clock, and the
4272                  * mode pixel clock is stored in units of 1KHz.
4273                  * Hence the bw of each lane in terms of the mode signal
4274                  * is:
4275                  */
4276                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4277         }
4278
4279         /* determine panel color depth */
4280         temp = I915_READ(PIPECONF(pipe));
4281         temp &= ~PIPE_BPC_MASK;
4282         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4283         switch (pipe_bpp) {
4284         case 18:
4285                 temp |= PIPE_6BPC;
4286                 break;
4287         case 24:
4288                 temp |= PIPE_8BPC;
4289                 break;
4290         case 30:
4291                 temp |= PIPE_10BPC;
4292                 break;
4293         case 36:
4294                 temp |= PIPE_12BPC;
4295                 break;
4296         default:
4297                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4298                         pipe_bpp);
4299                 temp |= PIPE_8BPC;
4300                 pipe_bpp = 24;
4301                 break;
4302         }
4303
4304         intel_crtc->bpp = pipe_bpp;
4305         I915_WRITE(PIPECONF(pipe), temp);
4306
4307         if (!lane) {
4308                 /*
4309                  * Account for spread spectrum to avoid
4310                  * oversubscribing the link. Max center spread
4311                  * is 2.5%; use 5% for safety's sake.
4312                  */
4313                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4314                 lane = bps / (link_bw * 8) + 1;
4315         }
4316
4317         intel_crtc->fdi_lanes = lane;
4318
4319         if (pixel_multiplier > 1)
4320                 link_bw *= pixel_multiplier;
4321         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4322                              &m_n);
4323
4324         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4325         if (has_reduced_clock)
4326                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4327                         reduced_clock.m2;
4328
4329         /* Enable autotuning of the PLL clock (if permissible) */
4330         factor = 21;
4331         if (is_lvds) {
4332                 if ((intel_panel_use_ssc(dev_priv) &&
4333                      dev_priv->lvds_ssc_freq == 100) ||
4334                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4335                         factor = 25;
4336         } else if (is_sdvo && is_tv)
4337                 factor = 20;
4338
4339         if (clock.m < factor * clock.n)
4340                 fp |= FP_CB_TUNE;
4341
4342         dpll = 0;
4343
4344         if (is_lvds)
4345                 dpll |= DPLLB_MODE_LVDS;
4346         else
4347                 dpll |= DPLLB_MODE_DAC_SERIAL;
4348         if (is_sdvo) {
4349                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4350                 if (pixel_multiplier > 1) {
4351                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4352                 }
4353                 dpll |= DPLL_DVO_HIGH_SPEED;
4354         }
4355         if (is_dp && !is_cpu_edp)
4356                 dpll |= DPLL_DVO_HIGH_SPEED;
4357
4358         /* compute bitmask from p1 value */
4359         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4360         /* also FPA1 */
4361         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4362
4363         switch (clock.p2) {
4364         case 5:
4365                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4366                 break;
4367         case 7:
4368                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4369                 break;
4370         case 10:
4371                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4372                 break;
4373         case 14:
4374                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4375                 break;
4376         }
4377
4378         if (is_sdvo && is_tv)
4379                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4380         else if (is_tv)
4381                 /* XXX: just matching BIOS for now */
4382                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4383                 dpll |= 3;
4384         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4385                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4386         else
4387                 dpll |= PLL_REF_INPUT_DREFCLK;
4388
4389         /* setup pipeconf */
4390         pipeconf = I915_READ(PIPECONF(pipe));
4391
4392         /* Set up the display plane register */
4393         dspcntr = DISPPLANE_GAMMA_ENABLE;
4394
4395         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4396         drm_mode_debug_printmodeline(mode);
4397
4398         /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
4399         if (!is_cpu_edp) {
4400                 struct intel_pch_pll *pll;
4401
4402                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4403                 if (pll == NULL) {
4404                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4405                                          pipe);
4406                         return -EINVAL;
4407                 }
4408         } else
4409                 intel_put_pch_pll(intel_crtc);
4410
4411         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4412          * This is an exception to the general rule that mode_set doesn't turn
4413          * things on.
4414          */
4415         if (is_lvds) {
4416                 temp = I915_READ(PCH_LVDS);
4417                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4418                 if (HAS_PCH_CPT(dev)) {
4419                         temp &= ~PORT_TRANS_SEL_MASK;
4420                         temp |= PORT_TRANS_SEL_CPT(pipe);
4421                 } else {
4422                         if (pipe == 1)
4423                                 temp |= LVDS_PIPEB_SELECT;
4424                         else
4425                                 temp &= ~LVDS_PIPEB_SELECT;
4426                 }
4427
4428                 /* set the corresponsding LVDS_BORDER bit */
4429                 temp |= dev_priv->lvds_border_bits;
4430                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4431                  * set the DPLLs for dual-channel mode or not.
4432                  */
4433                 if (clock.p2 == 7)
4434                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4435                 else
4436                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4437
4438                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4439                  * appropriately here, but we need to look more thoroughly into how
4440                  * panels behave in the two modes.
4441                  */
4442                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4443                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4444                         temp |= LVDS_HSYNC_POLARITY;
4445                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4446                         temp |= LVDS_VSYNC_POLARITY;
4447                 I915_WRITE(PCH_LVDS, temp);
4448         }
4449
4450         pipeconf &= ~PIPECONF_DITHER_EN;
4451         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4452         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4453                 pipeconf |= PIPECONF_DITHER_EN;
4454                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4455         }
4456         if (is_dp && !is_cpu_edp) {
4457                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4458         } else {
4459                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4460                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4461                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4462                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4463                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4464         }
4465
4466         if (intel_crtc->pch_pll) {
4467                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4468
4469                 /* Wait for the clocks to stabilize. */
4470                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4471                 udelay(150);
4472
4473                 /* The pixel multiplier can only be updated once the
4474                  * DPLL is enabled and the clocks are stable.
4475                  *
4476                  * So write it again.
4477                  */
4478                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4479         }
4480
4481         intel_crtc->lowfreq_avail = false;
4482         if (intel_crtc->pch_pll) {
4483                 if (is_lvds && has_reduced_clock && i915_powersave) {
4484                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4485                         intel_crtc->lowfreq_avail = true;
4486                         if (HAS_PIPE_CXSR(dev)) {
4487                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4488                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4489                         }
4490                 } else {
4491                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4492                         if (HAS_PIPE_CXSR(dev)) {
4493                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4494                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4495                         }
4496                 }
4497         }
4498
4499         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4500         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4501                 pipeconf |= PIPECONF_INTERLACED_ILK;
4502                 /* the chip adds 2 halflines automatically */
4503                 adjusted_mode->crtc_vtotal -= 1;
4504                 adjusted_mode->crtc_vblank_end -= 1;
4505                 I915_WRITE(VSYNCSHIFT(pipe),
4506                            adjusted_mode->crtc_hsync_start
4507                            - adjusted_mode->crtc_htotal/2);
4508         } else {
4509                 pipeconf |= PIPECONF_PROGRESSIVE;
4510                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4511         }
4512
4513         I915_WRITE(HTOTAL(pipe),
4514                    (adjusted_mode->crtc_hdisplay - 1) |
4515                    ((adjusted_mode->crtc_htotal - 1) << 16));
4516         I915_WRITE(HBLANK(pipe),
4517                    (adjusted_mode->crtc_hblank_start - 1) |
4518                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4519         I915_WRITE(HSYNC(pipe),
4520                    (adjusted_mode->crtc_hsync_start - 1) |
4521                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4522
4523         I915_WRITE(VTOTAL(pipe),
4524                    (adjusted_mode->crtc_vdisplay - 1) |
4525                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4526         I915_WRITE(VBLANK(pipe),
4527                    (adjusted_mode->crtc_vblank_start - 1) |
4528                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4529         I915_WRITE(VSYNC(pipe),
4530                    (adjusted_mode->crtc_vsync_start - 1) |
4531                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4532
4533         /* pipesrc controls the size that is scaled from, which should
4534          * always be the user's requested size.
4535          */
4536         I915_WRITE(PIPESRC(pipe),
4537                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4538
4539         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4540         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4541         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4542         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4543
4544         if (is_cpu_edp)
4545                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4546
4547         I915_WRITE(PIPECONF(pipe), pipeconf);
4548         POSTING_READ(PIPECONF(pipe));
4549
4550         intel_wait_for_vblank(dev, pipe);
4551
4552         I915_WRITE(DSPCNTR(plane), dspcntr);
4553         POSTING_READ(DSPCNTR(plane));
4554
4555         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4556
4557         intel_update_watermarks(dev);
4558
4559         return ret;
4560 }
4561
4562 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4563                                struct drm_display_mode *mode,
4564                                struct drm_display_mode *adjusted_mode,
4565                                int x, int y,
4566                                struct drm_framebuffer *old_fb)
4567 {
4568         struct drm_device *dev = crtc->dev;
4569         struct drm_i915_private *dev_priv = dev->dev_private;
4570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4571         int pipe = intel_crtc->pipe;
4572         int ret;
4573
4574         drm_vblank_pre_modeset(dev, pipe);
4575
4576         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4577                                               x, y, old_fb);
4578         drm_vblank_post_modeset(dev, pipe);
4579
4580         if (ret)
4581                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4582         else
4583                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4584
4585         return ret;
4586 }
4587
4588 static bool intel_eld_uptodate(struct drm_connector *connector,
4589                                int reg_eldv, uint32_t bits_eldv,
4590                                int reg_elda, uint32_t bits_elda,
4591                                int reg_edid)
4592 {
4593         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4594         uint8_t *eld = connector->eld;
4595         uint32_t i;
4596
4597         i = I915_READ(reg_eldv);
4598         i &= bits_eldv;
4599
4600         if (!eld[0])
4601                 return !i;
4602
4603         if (!i)
4604                 return false;
4605
4606         i = I915_READ(reg_elda);
4607         i &= ~bits_elda;
4608         I915_WRITE(reg_elda, i);
4609
4610         for (i = 0; i < eld[2]; i++)
4611                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4612                         return false;
4613
4614         return true;
4615 }
4616
4617 static void g4x_write_eld(struct drm_connector *connector,
4618                           struct drm_crtc *crtc)
4619 {
4620         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4621         uint8_t *eld = connector->eld;
4622         uint32_t eldv;
4623         uint32_t len;
4624         uint32_t i;
4625
4626         i = I915_READ(G4X_AUD_VID_DID);
4627
4628         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4629                 eldv = G4X_ELDV_DEVCL_DEVBLC;
4630         else
4631                 eldv = G4X_ELDV_DEVCTG;
4632
4633         if (intel_eld_uptodate(connector,
4634                                G4X_AUD_CNTL_ST, eldv,
4635                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4636                                G4X_HDMIW_HDMIEDID))
4637                 return;
4638
4639         i = I915_READ(G4X_AUD_CNTL_ST);
4640         i &= ~(eldv | G4X_ELD_ADDR);
4641         len = (i >> 9) & 0x1f;          /* ELD buffer size */
4642         I915_WRITE(G4X_AUD_CNTL_ST, i);
4643
4644         if (!eld[0])
4645                 return;
4646
4647         len = min_t(uint8_t, eld[2], len);
4648         DRM_DEBUG_DRIVER("ELD size %d\n", len);
4649         for (i = 0; i < len; i++)
4650                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4651
4652         i = I915_READ(G4X_AUD_CNTL_ST);
4653         i |= eldv;
4654         I915_WRITE(G4X_AUD_CNTL_ST, i);
4655 }
4656
4657 static void ironlake_write_eld(struct drm_connector *connector,
4658                                      struct drm_crtc *crtc)
4659 {
4660         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4661         uint8_t *eld = connector->eld;
4662         uint32_t eldv;
4663         uint32_t i;
4664         int len;
4665         int hdmiw_hdmiedid;
4666         int aud_config;
4667         int aud_cntl_st;
4668         int aud_cntrl_st2;
4669
4670         if (HAS_PCH_IBX(connector->dev)) {
4671                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4672                 aud_config = IBX_AUD_CONFIG_A;
4673                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4674                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4675         } else {
4676                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4677                 aud_config = CPT_AUD_CONFIG_A;
4678                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4679                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4680         }
4681
4682         i = to_intel_crtc(crtc)->pipe;
4683         hdmiw_hdmiedid += i * 0x100;
4684         aud_cntl_st += i * 0x100;
4685         aud_config += i * 0x100;
4686
4687         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4688
4689         i = I915_READ(aud_cntl_st);
4690         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
4691         if (!i) {
4692                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4693                 /* operate blindly on all ports */
4694                 eldv = IBX_ELD_VALIDB;
4695                 eldv |= IBX_ELD_VALIDB << 4;
4696                 eldv |= IBX_ELD_VALIDB << 8;
4697         } else {
4698                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4699                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4700         }
4701
4702         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4703                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4704                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
4705                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4706         } else
4707                 I915_WRITE(aud_config, 0);
4708
4709         if (intel_eld_uptodate(connector,
4710                                aud_cntrl_st2, eldv,
4711                                aud_cntl_st, IBX_ELD_ADDRESS,
4712                                hdmiw_hdmiedid))
4713                 return;
4714
4715         i = I915_READ(aud_cntrl_st2);
4716         i &= ~eldv;
4717         I915_WRITE(aud_cntrl_st2, i);
4718
4719         if (!eld[0])
4720                 return;
4721
4722         i = I915_READ(aud_cntl_st);
4723         i &= ~IBX_ELD_ADDRESS;
4724         I915_WRITE(aud_cntl_st, i);
4725
4726         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
4727         DRM_DEBUG_DRIVER("ELD size %d\n", len);
4728         for (i = 0; i < len; i++)
4729                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4730
4731         i = I915_READ(aud_cntrl_st2);
4732         i |= eldv;
4733         I915_WRITE(aud_cntrl_st2, i);
4734 }
4735
4736 void intel_write_eld(struct drm_encoder *encoder,
4737                      struct drm_display_mode *mode)
4738 {
4739         struct drm_crtc *crtc = encoder->crtc;
4740         struct drm_connector *connector;
4741         struct drm_device *dev = encoder->dev;
4742         struct drm_i915_private *dev_priv = dev->dev_private;
4743
4744         connector = drm_select_eld(encoder, mode);
4745         if (!connector)
4746                 return;
4747
4748         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4749                          connector->base.id,
4750                          drm_get_connector_name(connector),
4751                          connector->encoder->base.id,
4752                          drm_get_encoder_name(connector->encoder));
4753
4754         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4755
4756         if (dev_priv->display.write_eld)
4757                 dev_priv->display.write_eld(connector, crtc);
4758 }
4759
4760 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4761 void intel_crtc_load_lut(struct drm_crtc *crtc)
4762 {
4763         struct drm_device *dev = crtc->dev;
4764         struct drm_i915_private *dev_priv = dev->dev_private;
4765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4766         int palreg = PALETTE(intel_crtc->pipe);
4767         int i;
4768
4769         /* The clocks have to be on to load the palette. */
4770         if (!crtc->enabled || !intel_crtc->active)
4771                 return;
4772
4773         /* use legacy palette for Ironlake */
4774         if (HAS_PCH_SPLIT(dev))
4775                 palreg = LGC_PALETTE(intel_crtc->pipe);
4776
4777         for (i = 0; i < 256; i++) {
4778                 I915_WRITE(palreg + 4 * i,
4779                            (intel_crtc->lut_r[i] << 16) |
4780                            (intel_crtc->lut_g[i] << 8) |
4781                            intel_crtc->lut_b[i]);
4782         }
4783 }
4784
4785 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4786 {
4787         struct drm_device *dev = crtc->dev;
4788         struct drm_i915_private *dev_priv = dev->dev_private;
4789         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4790         bool visible = base != 0;
4791         u32 cntl;
4792
4793         if (intel_crtc->cursor_visible == visible)
4794                 return;
4795
4796         cntl = I915_READ(_CURACNTR);
4797         if (visible) {
4798                 /* On these chipsets we can only modify the base whilst
4799                  * the cursor is disabled.
4800                  */
4801                 I915_WRITE(_CURABASE, base);
4802
4803                 cntl &= ~(CURSOR_FORMAT_MASK);
4804                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4805                 cntl |= CURSOR_ENABLE |
4806                         CURSOR_GAMMA_ENABLE |
4807                         CURSOR_FORMAT_ARGB;
4808         } else
4809                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4810         I915_WRITE(_CURACNTR, cntl);
4811
4812         intel_crtc->cursor_visible = visible;
4813 }
4814
4815 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4816 {
4817         struct drm_device *dev = crtc->dev;
4818         struct drm_i915_private *dev_priv = dev->dev_private;
4819         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4820         int pipe = intel_crtc->pipe;
4821         bool visible = base != 0;
4822
4823         if (intel_crtc->cursor_visible != visible) {
4824                 uint32_t cntl = I915_READ(CURCNTR(pipe));
4825                 if (base) {
4826                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4827                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4828                         cntl |= pipe << 28; /* Connect to correct pipe */
4829                 } else {
4830                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4831                         cntl |= CURSOR_MODE_DISABLE;
4832                 }
4833                 I915_WRITE(CURCNTR(pipe), cntl);
4834
4835                 intel_crtc->cursor_visible = visible;
4836         }
4837         /* and commit changes on next vblank */
4838         I915_WRITE(CURBASE(pipe), base);
4839 }
4840
4841 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4842 {
4843         struct drm_device *dev = crtc->dev;
4844         struct drm_i915_private *dev_priv = dev->dev_private;
4845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4846         int pipe = intel_crtc->pipe;
4847         bool visible = base != 0;
4848
4849         if (intel_crtc->cursor_visible != visible) {
4850                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4851                 if (base) {
4852                         cntl &= ~CURSOR_MODE;
4853                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4854                 } else {
4855                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4856                         cntl |= CURSOR_MODE_DISABLE;
4857                 }
4858                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4859
4860                 intel_crtc->cursor_visible = visible;
4861         }
4862         /* and commit changes on next vblank */
4863         I915_WRITE(CURBASE_IVB(pipe), base);
4864 }
4865
4866 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4867 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4868                                      bool on)
4869 {
4870         struct drm_device *dev = crtc->dev;
4871         struct drm_i915_private *dev_priv = dev->dev_private;
4872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4873         int pipe = intel_crtc->pipe;
4874         int x = intel_crtc->cursor_x;
4875         int y = intel_crtc->cursor_y;
4876         u32 base, pos;
4877         bool visible;
4878
4879         pos = 0;
4880
4881         if (on && crtc->enabled && crtc->fb) {
4882                 base = intel_crtc->cursor_addr;
4883                 if (x > (int) crtc->fb->width)
4884                         base = 0;
4885
4886                 if (y > (int) crtc->fb->height)
4887                         base = 0;
4888         } else
4889                 base = 0;
4890
4891         if (x < 0) {
4892                 if (x + intel_crtc->cursor_width < 0)
4893                         base = 0;
4894
4895                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4896                 x = -x;
4897         }
4898         pos |= x << CURSOR_X_SHIFT;
4899
4900         if (y < 0) {
4901                 if (y + intel_crtc->cursor_height < 0)
4902                         base = 0;
4903
4904                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4905                 y = -y;
4906         }
4907         pos |= y << CURSOR_Y_SHIFT;
4908
4909         visible = base != 0;
4910         if (!visible && !intel_crtc->cursor_visible)
4911                 return;
4912
4913         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4914                 I915_WRITE(CURPOS_IVB(pipe), pos);
4915                 ivb_update_cursor(crtc, base);
4916         } else {
4917                 I915_WRITE(CURPOS(pipe), pos);
4918                 if (IS_845G(dev) || IS_I865G(dev))
4919                         i845_update_cursor(crtc, base);
4920                 else
4921                         i9xx_update_cursor(crtc, base);
4922         }
4923 }
4924
4925 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4926                                  struct drm_file *file,
4927                                  uint32_t handle,
4928                                  uint32_t width, uint32_t height)
4929 {
4930         struct drm_device *dev = crtc->dev;
4931         struct drm_i915_private *dev_priv = dev->dev_private;
4932         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4933         struct drm_i915_gem_object *obj;
4934         uint32_t addr;
4935         int ret;
4936
4937         DRM_DEBUG_KMS("\n");
4938
4939         /* if we want to turn off the cursor ignore width and height */
4940         if (!handle) {
4941                 DRM_DEBUG_KMS("cursor off\n");
4942                 addr = 0;
4943                 obj = NULL;
4944                 mutex_lock(&dev->struct_mutex);
4945                 goto finish;
4946         }
4947
4948         /* Currently we only support 64x64 cursors */
4949         if (width != 64 || height != 64) {
4950                 DRM_ERROR("we currently only support 64x64 cursors\n");
4951                 return -EINVAL;
4952         }
4953
4954         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4955         if (&obj->base == NULL)
4956                 return -ENOENT;
4957
4958         if (obj->base.size < width * height * 4) {
4959                 DRM_ERROR("buffer is to small\n");
4960                 ret = -ENOMEM;
4961                 goto fail;
4962         }
4963
4964         /* we only need to pin inside GTT if cursor is non-phy */
4965         mutex_lock(&dev->struct_mutex);
4966         if (!dev_priv->info->cursor_needs_physical) {
4967                 if (obj->tiling_mode) {
4968                         DRM_ERROR("cursor cannot be tiled\n");
4969                         ret = -EINVAL;
4970                         goto fail_locked;
4971                 }
4972
4973                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
4974                 if (ret) {
4975                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4976                         goto fail_locked;
4977                 }
4978
4979                 ret = i915_gem_object_put_fence(obj);
4980                 if (ret) {
4981                         DRM_ERROR("failed to release fence for cursor");
4982                         goto fail_unpin;
4983                 }
4984
4985                 addr = obj->gtt_offset;
4986         } else {
4987                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4988                 ret = i915_gem_attach_phys_object(dev, obj,
4989                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4990                                                   align);
4991                 if (ret) {
4992                         DRM_ERROR("failed to attach phys object\n");
4993                         goto fail_locked;
4994                 }
4995                 addr = obj->phys_obj->handle->busaddr;
4996         }
4997
4998         if (IS_GEN2(dev))
4999                 I915_WRITE(CURSIZE, (height << 12) | width);
5000
5001  finish:
5002         if (intel_crtc->cursor_bo) {
5003                 if (dev_priv->info->cursor_needs_physical) {
5004                         if (intel_crtc->cursor_bo != obj)
5005                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5006                 } else
5007                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5008                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5009         }
5010
5011         mutex_unlock(&dev->struct_mutex);
5012
5013         intel_crtc->cursor_addr = addr;
5014         intel_crtc->cursor_bo = obj;
5015         intel_crtc->cursor_width = width;
5016         intel_crtc->cursor_height = height;
5017
5018         intel_crtc_update_cursor(crtc, true);
5019
5020         return 0;
5021 fail_unpin:
5022         i915_gem_object_unpin(obj);
5023 fail_locked:
5024         mutex_unlock(&dev->struct_mutex);
5025 fail:
5026         drm_gem_object_unreference_unlocked(&obj->base);
5027         return ret;
5028 }
5029
5030 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5031 {
5032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5033
5034         intel_crtc->cursor_x = x;
5035         intel_crtc->cursor_y = y;
5036
5037         intel_crtc_update_cursor(crtc, true);
5038
5039         return 0;
5040 }
5041
5042 /** Sets the color ramps on behalf of RandR */
5043 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5044                                  u16 blue, int regno)
5045 {
5046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5047
5048         intel_crtc->lut_r[regno] = red >> 8;
5049         intel_crtc->lut_g[regno] = green >> 8;
5050         intel_crtc->lut_b[regno] = blue >> 8;
5051 }
5052
5053 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5054                              u16 *blue, int regno)
5055 {
5056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5057
5058         *red = intel_crtc->lut_r[regno] << 8;
5059         *green = intel_crtc->lut_g[regno] << 8;
5060         *blue = intel_crtc->lut_b[regno] << 8;
5061 }
5062
5063 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5064                                  u16 *blue, uint32_t start, uint32_t size)
5065 {
5066         int end = (start + size > 256) ? 256 : start + size, i;
5067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5068
5069         for (i = start; i < end; i++) {
5070                 intel_crtc->lut_r[i] = red[i] >> 8;
5071                 intel_crtc->lut_g[i] = green[i] >> 8;
5072                 intel_crtc->lut_b[i] = blue[i] >> 8;
5073         }
5074
5075         intel_crtc_load_lut(crtc);
5076 }
5077
5078 /**
5079  * Get a pipe with a simple mode set on it for doing load-based monitor
5080  * detection.
5081  *
5082  * It will be up to the load-detect code to adjust the pipe as appropriate for
5083  * its requirements.  The pipe will be connected to no other encoders.
5084  *
5085  * Currently this code will only succeed if there is a pipe with no encoders
5086  * configured for it.  In the future, it could choose to temporarily disable
5087  * some outputs to free up a pipe for its use.
5088  *
5089  * \return crtc, or NULL if no pipes are available.
5090  */
5091
5092 /* VESA 640x480x72Hz mode to set on the pipe */
5093 static struct drm_display_mode load_detect_mode = {
5094         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5095                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5096 };
5097
5098 static struct drm_framebuffer *
5099 intel_framebuffer_create(struct drm_device *dev,
5100                          struct drm_mode_fb_cmd2 *mode_cmd,
5101                          struct drm_i915_gem_object *obj)
5102 {
5103         struct intel_framebuffer *intel_fb;
5104         int ret;
5105
5106         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5107         if (!intel_fb) {
5108                 drm_gem_object_unreference_unlocked(&obj->base);
5109                 return ERR_PTR(-ENOMEM);
5110         }
5111
5112         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5113         if (ret) {
5114                 drm_gem_object_unreference_unlocked(&obj->base);
5115                 kfree(intel_fb);
5116                 return ERR_PTR(ret);
5117         }
5118
5119         return &intel_fb->base;
5120 }
5121
5122 static u32
5123 intel_framebuffer_pitch_for_width(int width, int bpp)
5124 {
5125         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5126         return ALIGN(pitch, 64);
5127 }
5128
5129 static u32
5130 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5131 {
5132         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5133         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5134 }
5135
5136 static struct drm_framebuffer *
5137 intel_framebuffer_create_for_mode(struct drm_device *dev,
5138                                   struct drm_display_mode *mode,
5139                                   int depth, int bpp)
5140 {
5141         struct drm_i915_gem_object *obj;
5142         struct drm_mode_fb_cmd2 mode_cmd;
5143
5144         obj = i915_gem_alloc_object(dev,
5145                                     intel_framebuffer_size_for_mode(mode, bpp));
5146         if (obj == NULL)
5147                 return ERR_PTR(-ENOMEM);
5148
5149         mode_cmd.width = mode->hdisplay;
5150         mode_cmd.height = mode->vdisplay;
5151         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5152                                                                 bpp);
5153         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5154
5155         return intel_framebuffer_create(dev, &mode_cmd, obj);
5156 }
5157
5158 static struct drm_framebuffer *
5159 mode_fits_in_fbdev(struct drm_device *dev,
5160                    struct drm_display_mode *mode)
5161 {
5162         struct drm_i915_private *dev_priv = dev->dev_private;
5163         struct drm_i915_gem_object *obj;
5164         struct drm_framebuffer *fb;
5165
5166         if (dev_priv->fbdev == NULL)
5167                 return NULL;
5168
5169         obj = dev_priv->fbdev->ifb.obj;
5170         if (obj == NULL)
5171                 return NULL;
5172
5173         fb = &dev_priv->fbdev->ifb.base;
5174         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5175                                                                fb->bits_per_pixel))
5176                 return NULL;
5177
5178         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5179                 return NULL;
5180
5181         return fb;
5182 }
5183
5184 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5185                                 struct drm_connector *connector,
5186                                 struct drm_display_mode *mode,
5187                                 struct intel_load_detect_pipe *old)
5188 {
5189         struct intel_crtc *intel_crtc;
5190         struct drm_crtc *possible_crtc;
5191         struct drm_encoder *encoder = &intel_encoder->base;
5192         struct drm_crtc *crtc = NULL;
5193         struct drm_device *dev = encoder->dev;
5194         struct drm_framebuffer *old_fb;
5195         int i = -1;
5196
5197         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5198                       connector->base.id, drm_get_connector_name(connector),
5199                       encoder->base.id, drm_get_encoder_name(encoder));
5200
5201         /*
5202          * Algorithm gets a little messy:
5203          *
5204          *   - if the connector already has an assigned crtc, use it (but make
5205          *     sure it's on first)
5206          *
5207          *   - try to find the first unused crtc that can drive this connector,
5208          *     and use that if we find one
5209          */
5210
5211         /* See if we already have a CRTC for this connector */
5212         if (encoder->crtc) {
5213                 crtc = encoder->crtc;
5214
5215                 intel_crtc = to_intel_crtc(crtc);
5216                 old->dpms_mode = intel_crtc->dpms_mode;
5217                 old->load_detect_temp = false;
5218
5219                 /* Make sure the crtc and connector are running */
5220                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5221                         struct drm_encoder_helper_funcs *encoder_funcs;
5222                         struct drm_crtc_helper_funcs *crtc_funcs;
5223
5224                         crtc_funcs = crtc->helper_private;
5225                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5226
5227                         encoder_funcs = encoder->helper_private;
5228                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5229                 }
5230
5231                 return true;
5232         }
5233
5234         /* Find an unused one (if possible) */
5235         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5236                 i++;
5237                 if (!(encoder->possible_crtcs & (1 << i)))
5238                         continue;
5239                 if (!possible_crtc->enabled) {
5240                         crtc = possible_crtc;
5241                         break;
5242                 }
5243         }
5244
5245         /*
5246          * If we didn't find an unused CRTC, don't use any.
5247          */
5248         if (!crtc) {
5249                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5250                 return false;
5251         }
5252
5253         encoder->crtc = crtc;
5254         connector->encoder = encoder;
5255
5256         intel_crtc = to_intel_crtc(crtc);
5257         old->dpms_mode = intel_crtc->dpms_mode;
5258         old->load_detect_temp = true;
5259         old->release_fb = NULL;
5260
5261         if (!mode)
5262                 mode = &load_detect_mode;
5263
5264         old_fb = crtc->fb;
5265
5266         /* We need a framebuffer large enough to accommodate all accesses
5267          * that the plane may generate whilst we perform load detection.
5268          * We can not rely on the fbcon either being present (we get called
5269          * during its initialisation to detect all boot displays, or it may
5270          * not even exist) or that it is large enough to satisfy the
5271          * requested mode.
5272          */
5273         crtc->fb = mode_fits_in_fbdev(dev, mode);
5274         if (crtc->fb == NULL) {
5275                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5276                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5277                 old->release_fb = crtc->fb;
5278         } else
5279                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5280         if (IS_ERR(crtc->fb)) {
5281                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5282                 crtc->fb = old_fb;
5283                 return false;
5284         }
5285
5286         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5287                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5288                 if (old->release_fb)
5289                         old->release_fb->funcs->destroy(old->release_fb);
5290                 crtc->fb = old_fb;
5291                 return false;
5292         }
5293
5294         /* let the connector get through one full cycle before testing */
5295         intel_wait_for_vblank(dev, intel_crtc->pipe);
5296
5297         return true;
5298 }
5299
5300 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5301                                     struct drm_connector *connector,
5302                                     struct intel_load_detect_pipe *old)
5303 {
5304         struct drm_encoder *encoder = &intel_encoder->base;
5305         struct drm_device *dev = encoder->dev;
5306         struct drm_crtc *crtc = encoder->crtc;
5307         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5308         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5309
5310         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5311                       connector->base.id, drm_get_connector_name(connector),
5312                       encoder->base.id, drm_get_encoder_name(encoder));
5313
5314         if (old->load_detect_temp) {
5315                 connector->encoder = NULL;
5316                 drm_helper_disable_unused_functions(dev);
5317
5318                 if (old->release_fb)
5319                         old->release_fb->funcs->destroy(old->release_fb);
5320
5321                 return;
5322         }
5323
5324         /* Switch crtc and encoder back off if necessary */
5325         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5326                 encoder_funcs->dpms(encoder, old->dpms_mode);
5327                 crtc_funcs->dpms(crtc, old->dpms_mode);
5328         }
5329 }
5330
5331 /* Returns the clock of the currently programmed mode of the given pipe. */
5332 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5333 {
5334         struct drm_i915_private *dev_priv = dev->dev_private;
5335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5336         int pipe = intel_crtc->pipe;
5337         u32 dpll = I915_READ(DPLL(pipe));
5338         u32 fp;
5339         intel_clock_t clock;
5340
5341         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5342                 fp = I915_READ(FP0(pipe));
5343         else
5344                 fp = I915_READ(FP1(pipe));
5345
5346         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5347         if (IS_PINEVIEW(dev)) {
5348                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5349                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5350         } else {
5351                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5352                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5353         }
5354
5355         if (!IS_GEN2(dev)) {
5356                 if (IS_PINEVIEW(dev))
5357                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5358                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5359                 else
5360                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5361                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5362
5363                 switch (dpll & DPLL_MODE_MASK) {
5364                 case DPLLB_MODE_DAC_SERIAL:
5365                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5366                                 5 : 10;
5367                         break;
5368                 case DPLLB_MODE_LVDS:
5369                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5370                                 7 : 14;
5371                         break;
5372                 default:
5373                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5374                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5375                         return 0;
5376                 }
5377
5378                 /* XXX: Handle the 100Mhz refclk */
5379                 intel_clock(dev, 96000, &clock);
5380         } else {
5381                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5382
5383                 if (is_lvds) {
5384                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5385                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5386                         clock.p2 = 14;
5387
5388                         if ((dpll & PLL_REF_INPUT_MASK) ==
5389                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5390                                 /* XXX: might not be 66MHz */
5391                                 intel_clock(dev, 66000, &clock);
5392                         } else
5393                                 intel_clock(dev, 48000, &clock);
5394                 } else {
5395                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5396                                 clock.p1 = 2;
5397                         else {
5398                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5399                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5400                         }
5401                         if (dpll & PLL_P2_DIVIDE_BY_4)
5402                                 clock.p2 = 4;
5403                         else
5404                                 clock.p2 = 2;
5405
5406                         intel_clock(dev, 48000, &clock);
5407                 }
5408         }
5409
5410         /* XXX: It would be nice to validate the clocks, but we can't reuse
5411          * i830PllIsValid() because it relies on the xf86_config connector
5412          * configuration being accurate, which it isn't necessarily.
5413          */
5414
5415         return clock.dot;
5416 }
5417
5418 /** Returns the currently programmed mode of the given pipe. */
5419 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5420                                              struct drm_crtc *crtc)
5421 {
5422         struct drm_i915_private *dev_priv = dev->dev_private;
5423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5424         int pipe = intel_crtc->pipe;
5425         struct drm_display_mode *mode;
5426         int htot = I915_READ(HTOTAL(pipe));
5427         int hsync = I915_READ(HSYNC(pipe));
5428         int vtot = I915_READ(VTOTAL(pipe));
5429         int vsync = I915_READ(VSYNC(pipe));
5430
5431         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5432         if (!mode)
5433                 return NULL;
5434
5435         mode->clock = intel_crtc_clock_get(dev, crtc);
5436         mode->hdisplay = (htot & 0xffff) + 1;
5437         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5438         mode->hsync_start = (hsync & 0xffff) + 1;
5439         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5440         mode->vdisplay = (vtot & 0xffff) + 1;
5441         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5442         mode->vsync_start = (vsync & 0xffff) + 1;
5443         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5444
5445         drm_mode_set_name(mode);
5446
5447         return mode;
5448 }
5449
5450 #define GPU_IDLE_TIMEOUT 500 /* ms */
5451
5452 /* When this timer fires, we've been idle for awhile */
5453 static void intel_gpu_idle_timer(unsigned long arg)
5454 {
5455         struct drm_device *dev = (struct drm_device *)arg;
5456         drm_i915_private_t *dev_priv = dev->dev_private;
5457
5458         if (!list_empty(&dev_priv->mm.active_list)) {
5459                 /* Still processing requests, so just re-arm the timer. */
5460                 mod_timer(&dev_priv->idle_timer, jiffies +
5461                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5462                 return;
5463         }
5464
5465         dev_priv->busy = false;
5466         queue_work(dev_priv->wq, &dev_priv->idle_work);
5467 }
5468
5469 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5470
5471 static void intel_crtc_idle_timer(unsigned long arg)
5472 {
5473         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5474         struct drm_crtc *crtc = &intel_crtc->base;
5475         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5476         struct intel_framebuffer *intel_fb;
5477
5478         intel_fb = to_intel_framebuffer(crtc->fb);
5479         if (intel_fb && intel_fb->obj->active) {
5480                 /* The framebuffer is still being accessed by the GPU. */
5481                 mod_timer(&intel_crtc->idle_timer, jiffies +
5482                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5483                 return;
5484         }
5485
5486         intel_crtc->busy = false;
5487         queue_work(dev_priv->wq, &dev_priv->idle_work);
5488 }
5489
5490 static void intel_increase_pllclock(struct drm_crtc *crtc)
5491 {
5492         struct drm_device *dev = crtc->dev;
5493         drm_i915_private_t *dev_priv = dev->dev_private;
5494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5495         int pipe = intel_crtc->pipe;
5496         int dpll_reg = DPLL(pipe);
5497         int dpll;
5498
5499         if (HAS_PCH_SPLIT(dev))
5500                 return;
5501
5502         if (!dev_priv->lvds_downclock_avail)
5503                 return;
5504
5505         dpll = I915_READ(dpll_reg);
5506         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5507                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5508
5509                 assert_panel_unlocked(dev_priv, pipe);
5510
5511                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5512                 I915_WRITE(dpll_reg, dpll);
5513                 intel_wait_for_vblank(dev, pipe);
5514
5515                 dpll = I915_READ(dpll_reg);
5516                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5517                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5518         }
5519
5520         /* Schedule downclock */
5521         mod_timer(&intel_crtc->idle_timer, jiffies +
5522                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5523 }
5524
5525 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5526 {
5527         struct drm_device *dev = crtc->dev;
5528         drm_i915_private_t *dev_priv = dev->dev_private;
5529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5530
5531         if (HAS_PCH_SPLIT(dev))
5532                 return;
5533
5534         if (!dev_priv->lvds_downclock_avail)
5535                 return;
5536
5537         /*
5538          * Since this is called by a timer, we should never get here in
5539          * the manual case.
5540          */
5541         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5542                 int pipe = intel_crtc->pipe;
5543                 int dpll_reg = DPLL(pipe);
5544                 int dpll;
5545
5546                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5547
5548                 assert_panel_unlocked(dev_priv, pipe);
5549
5550                 dpll = I915_READ(dpll_reg);
5551                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5552                 I915_WRITE(dpll_reg, dpll);
5553                 intel_wait_for_vblank(dev, pipe);
5554                 dpll = I915_READ(dpll_reg);
5555                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5556                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5557         }
5558
5559 }
5560
5561 /**
5562  * intel_idle_update - adjust clocks for idleness
5563  * @work: work struct
5564  *
5565  * Either the GPU or display (or both) went idle.  Check the busy status
5566  * here and adjust the CRTC and GPU clocks as necessary.
5567  */
5568 static void intel_idle_update(struct work_struct *work)
5569 {
5570         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5571                                                     idle_work);
5572         struct drm_device *dev = dev_priv->dev;
5573         struct drm_crtc *crtc;
5574         struct intel_crtc *intel_crtc;
5575
5576         if (!i915_powersave)
5577                 return;
5578
5579         mutex_lock(&dev->struct_mutex);
5580
5581         i915_update_gfx_val(dev_priv);
5582
5583         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5584                 /* Skip inactive CRTCs */
5585                 if (!crtc->fb)
5586                         continue;
5587
5588                 intel_crtc = to_intel_crtc(crtc);
5589                 if (!intel_crtc->busy)
5590                         intel_decrease_pllclock(crtc);
5591         }
5592
5593
5594         mutex_unlock(&dev->struct_mutex);
5595 }
5596
5597 /**
5598  * intel_mark_busy - mark the GPU and possibly the display busy
5599  * @dev: drm device
5600  * @obj: object we're operating on
5601  *
5602  * Callers can use this function to indicate that the GPU is busy processing
5603  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5604  * buffer), we'll also mark the display as busy, so we know to increase its
5605  * clock frequency.
5606  */
5607 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5608 {
5609         drm_i915_private_t *dev_priv = dev->dev_private;
5610         struct drm_crtc *crtc = NULL;
5611         struct intel_framebuffer *intel_fb;
5612         struct intel_crtc *intel_crtc;
5613
5614         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5615                 return;
5616
5617         if (!dev_priv->busy) {
5618                 intel_sanitize_pm(dev);
5619                 dev_priv->busy = true;
5620         } else
5621                 mod_timer(&dev_priv->idle_timer, jiffies +
5622                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5623
5624         if (obj == NULL)
5625                 return;
5626
5627         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5628                 if (!crtc->fb)
5629                         continue;
5630
5631                 intel_crtc = to_intel_crtc(crtc);
5632                 intel_fb = to_intel_framebuffer(crtc->fb);
5633                 if (intel_fb->obj == obj) {
5634                         if (!intel_crtc->busy) {
5635                                 /* Non-busy -> busy, upclock */
5636                                 intel_increase_pllclock(crtc);
5637                                 intel_crtc->busy = true;
5638                         } else {
5639                                 /* Busy -> busy, put off timer */
5640                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5641                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5642                         }
5643                 }
5644         }
5645 }
5646
5647 static void intel_crtc_destroy(struct drm_crtc *crtc)
5648 {
5649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5650         struct drm_device *dev = crtc->dev;
5651         struct intel_unpin_work *work;
5652         unsigned long flags;
5653
5654         spin_lock_irqsave(&dev->event_lock, flags);
5655         work = intel_crtc->unpin_work;
5656         intel_crtc->unpin_work = NULL;
5657         spin_unlock_irqrestore(&dev->event_lock, flags);
5658
5659         if (work) {
5660                 cancel_work_sync(&work->work);
5661                 kfree(work);
5662         }
5663
5664         drm_crtc_cleanup(crtc);
5665
5666         kfree(intel_crtc);
5667 }
5668
5669 static void intel_unpin_work_fn(struct work_struct *__work)
5670 {
5671         struct intel_unpin_work *work =
5672                 container_of(__work, struct intel_unpin_work, work);
5673
5674         mutex_lock(&work->dev->struct_mutex);
5675         intel_unpin_fb_obj(work->old_fb_obj);
5676         drm_gem_object_unreference(&work->pending_flip_obj->base);
5677         drm_gem_object_unreference(&work->old_fb_obj->base);
5678
5679         intel_update_fbc(work->dev);
5680         mutex_unlock(&work->dev->struct_mutex);
5681         kfree(work);
5682 }
5683
5684 static void do_intel_finish_page_flip(struct drm_device *dev,
5685                                       struct drm_crtc *crtc)
5686 {
5687         drm_i915_private_t *dev_priv = dev->dev_private;
5688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5689         struct intel_unpin_work *work;
5690         struct drm_i915_gem_object *obj;
5691         struct drm_pending_vblank_event *e;
5692         struct timeval tnow, tvbl;
5693         unsigned long flags;
5694
5695         /* Ignore early vblank irqs */
5696         if (intel_crtc == NULL)
5697                 return;
5698
5699         do_gettimeofday(&tnow);
5700
5701         spin_lock_irqsave(&dev->event_lock, flags);
5702         work = intel_crtc->unpin_work;
5703         if (work == NULL || !work->pending) {
5704                 spin_unlock_irqrestore(&dev->event_lock, flags);
5705                 return;
5706         }
5707
5708         intel_crtc->unpin_work = NULL;
5709
5710         if (work->event) {
5711                 e = work->event;
5712                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5713
5714                 /* Called before vblank count and timestamps have
5715                  * been updated for the vblank interval of flip
5716                  * completion? Need to increment vblank count and
5717                  * add one videorefresh duration to returned timestamp
5718                  * to account for this. We assume this happened if we
5719                  * get called over 0.9 frame durations after the last
5720                  * timestamped vblank.
5721                  *
5722                  * This calculation can not be used with vrefresh rates
5723                  * below 5Hz (10Hz to be on the safe side) without
5724                  * promoting to 64 integers.
5725                  */
5726                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5727                     9 * crtc->framedur_ns) {
5728                         e->event.sequence++;
5729                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5730                                              crtc->framedur_ns);
5731                 }
5732
5733                 e->event.tv_sec = tvbl.tv_sec;
5734                 e->event.tv_usec = tvbl.tv_usec;
5735
5736                 list_add_tail(&e->base.link,
5737                               &e->base.file_priv->event_list);
5738                 wake_up_interruptible(&e->base.file_priv->event_wait);
5739         }
5740
5741         drm_vblank_put(dev, intel_crtc->pipe);
5742
5743         spin_unlock_irqrestore(&dev->event_lock, flags);
5744
5745         obj = work->old_fb_obj;
5746
5747         atomic_clear_mask(1 << intel_crtc->plane,
5748                           &obj->pending_flip.counter);
5749         if (atomic_read(&obj->pending_flip) == 0)
5750                 wake_up(&dev_priv->pending_flip_queue);
5751
5752         schedule_work(&work->work);
5753
5754         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5755 }
5756
5757 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5758 {
5759         drm_i915_private_t *dev_priv = dev->dev_private;
5760         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5761
5762         do_intel_finish_page_flip(dev, crtc);
5763 }
5764
5765 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5766 {
5767         drm_i915_private_t *dev_priv = dev->dev_private;
5768         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5769
5770         do_intel_finish_page_flip(dev, crtc);
5771 }
5772
5773 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5774 {
5775         drm_i915_private_t *dev_priv = dev->dev_private;
5776         struct intel_crtc *intel_crtc =
5777                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5778         unsigned long flags;
5779
5780         spin_lock_irqsave(&dev->event_lock, flags);
5781         if (intel_crtc->unpin_work) {
5782                 if ((++intel_crtc->unpin_work->pending) > 1)
5783                         DRM_ERROR("Prepared flip multiple times\n");
5784         } else {
5785                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5786         }
5787         spin_unlock_irqrestore(&dev->event_lock, flags);
5788 }
5789
5790 static int intel_gen2_queue_flip(struct drm_device *dev,
5791                                  struct drm_crtc *crtc,
5792                                  struct drm_framebuffer *fb,
5793                                  struct drm_i915_gem_object *obj)
5794 {
5795         struct drm_i915_private *dev_priv = dev->dev_private;
5796         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5797         unsigned long offset;
5798         u32 flip_mask;
5799         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5800         int ret;
5801
5802         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5803         if (ret)
5804                 goto err;
5805
5806         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5807         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5808
5809         ret = intel_ring_begin(ring, 6);
5810         if (ret)
5811                 goto err_unpin;
5812
5813         /* Can't queue multiple flips, so wait for the previous
5814          * one to finish before executing the next.
5815          */
5816         if (intel_crtc->plane)
5817                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5818         else
5819                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5820         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5821         intel_ring_emit(ring, MI_NOOP);
5822         intel_ring_emit(ring, MI_DISPLAY_FLIP |
5823                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5824         intel_ring_emit(ring, fb->pitches[0]);
5825         intel_ring_emit(ring, obj->gtt_offset + offset);
5826         intel_ring_emit(ring, 0); /* aux display base address, unused */
5827         intel_ring_advance(ring);
5828         return 0;
5829
5830 err_unpin:
5831         intel_unpin_fb_obj(obj);
5832 err:
5833         return ret;
5834 }
5835
5836 static int intel_gen3_queue_flip(struct drm_device *dev,
5837                                  struct drm_crtc *crtc,
5838                                  struct drm_framebuffer *fb,
5839                                  struct drm_i915_gem_object *obj)
5840 {
5841         struct drm_i915_private *dev_priv = dev->dev_private;
5842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5843         unsigned long offset;
5844         u32 flip_mask;
5845         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5846         int ret;
5847
5848         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5849         if (ret)
5850                 goto err;
5851
5852         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5853         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5854
5855         ret = intel_ring_begin(ring, 6);
5856         if (ret)
5857                 goto err_unpin;
5858
5859         if (intel_crtc->plane)
5860                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5861         else
5862                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5863         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5864         intel_ring_emit(ring, MI_NOOP);
5865         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
5866                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5867         intel_ring_emit(ring, fb->pitches[0]);
5868         intel_ring_emit(ring, obj->gtt_offset + offset);
5869         intel_ring_emit(ring, MI_NOOP);
5870
5871         intel_ring_advance(ring);
5872         return 0;
5873
5874 err_unpin:
5875         intel_unpin_fb_obj(obj);
5876 err:
5877         return ret;
5878 }
5879
5880 static int intel_gen4_queue_flip(struct drm_device *dev,
5881                                  struct drm_crtc *crtc,
5882                                  struct drm_framebuffer *fb,
5883                                  struct drm_i915_gem_object *obj)
5884 {
5885         struct drm_i915_private *dev_priv = dev->dev_private;
5886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5887         uint32_t pf, pipesrc;
5888         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5889         int ret;
5890
5891         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5892         if (ret)
5893                 goto err;
5894
5895         ret = intel_ring_begin(ring, 4);
5896         if (ret)
5897                 goto err_unpin;
5898
5899         /* i965+ uses the linear or tiled offsets from the
5900          * Display Registers (which do not change across a page-flip)
5901          * so we need only reprogram the base address.
5902          */
5903         intel_ring_emit(ring, MI_DISPLAY_FLIP |
5904                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5905         intel_ring_emit(ring, fb->pitches[0]);
5906         intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
5907
5908         /* XXX Enabling the panel-fitter across page-flip is so far
5909          * untested on non-native modes, so ignore it for now.
5910          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5911          */
5912         pf = 0;
5913         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5914         intel_ring_emit(ring, pf | pipesrc);
5915         intel_ring_advance(ring);
5916         return 0;
5917
5918 err_unpin:
5919         intel_unpin_fb_obj(obj);
5920 err:
5921         return ret;
5922 }
5923
5924 static int intel_gen6_queue_flip(struct drm_device *dev,
5925                                  struct drm_crtc *crtc,
5926                                  struct drm_framebuffer *fb,
5927                                  struct drm_i915_gem_object *obj)
5928 {
5929         struct drm_i915_private *dev_priv = dev->dev_private;
5930         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5931         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5932         uint32_t pf, pipesrc;
5933         int ret;
5934
5935         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5936         if (ret)
5937                 goto err;
5938
5939         ret = intel_ring_begin(ring, 4);
5940         if (ret)
5941                 goto err_unpin;
5942
5943         intel_ring_emit(ring, MI_DISPLAY_FLIP |
5944                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5945         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
5946         intel_ring_emit(ring, obj->gtt_offset);
5947
5948         /* Contrary to the suggestions in the documentation,
5949          * "Enable Panel Fitter" does not seem to be required when page
5950          * flipping with a non-native mode, and worse causes a normal
5951          * modeset to fail.
5952          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5953          */
5954         pf = 0;
5955         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5956         intel_ring_emit(ring, pf | pipesrc);
5957         intel_ring_advance(ring);
5958         return 0;
5959
5960 err_unpin:
5961         intel_unpin_fb_obj(obj);
5962 err:
5963         return ret;
5964 }
5965
5966 /*
5967  * On gen7 we currently use the blit ring because (in early silicon at least)
5968  * the render ring doesn't give us interrpts for page flip completion, which
5969  * means clients will hang after the first flip is queued.  Fortunately the
5970  * blit ring generates interrupts properly, so use it instead.
5971  */
5972 static int intel_gen7_queue_flip(struct drm_device *dev,
5973                                  struct drm_crtc *crtc,
5974                                  struct drm_framebuffer *fb,
5975                                  struct drm_i915_gem_object *obj)
5976 {
5977         struct drm_i915_private *dev_priv = dev->dev_private;
5978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5979         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5980         int ret;
5981
5982         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5983         if (ret)
5984                 goto err;
5985
5986         ret = intel_ring_begin(ring, 4);
5987         if (ret)
5988                 goto err_unpin;
5989
5990         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
5991         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
5992         intel_ring_emit(ring, (obj->gtt_offset));
5993         intel_ring_emit(ring, (MI_NOOP));
5994         intel_ring_advance(ring);
5995         return 0;
5996
5997 err_unpin:
5998         intel_unpin_fb_obj(obj);
5999 err:
6000         return ret;
6001 }
6002
6003 static int intel_default_queue_flip(struct drm_device *dev,
6004                                     struct drm_crtc *crtc,
6005                                     struct drm_framebuffer *fb,
6006                                     struct drm_i915_gem_object *obj)
6007 {
6008         return -ENODEV;
6009 }
6010
6011 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6012                                 struct drm_framebuffer *fb,
6013                                 struct drm_pending_vblank_event *event)
6014 {
6015         struct drm_device *dev = crtc->dev;
6016         struct drm_i915_private *dev_priv = dev->dev_private;
6017         struct intel_framebuffer *intel_fb;
6018         struct drm_i915_gem_object *obj;
6019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6020         struct intel_unpin_work *work;
6021         unsigned long flags;
6022         int ret;
6023
6024         work = kzalloc(sizeof *work, GFP_KERNEL);
6025         if (work == NULL)
6026                 return -ENOMEM;
6027
6028         work->event = event;
6029         work->dev = crtc->dev;
6030         intel_fb = to_intel_framebuffer(crtc->fb);
6031         work->old_fb_obj = intel_fb->obj;
6032         INIT_WORK(&work->work, intel_unpin_work_fn);
6033
6034         ret = drm_vblank_get(dev, intel_crtc->pipe);
6035         if (ret)
6036                 goto free_work;
6037
6038         /* We borrow the event spin lock for protecting unpin_work */
6039         spin_lock_irqsave(&dev->event_lock, flags);
6040         if (intel_crtc->unpin_work) {
6041                 spin_unlock_irqrestore(&dev->event_lock, flags);
6042                 kfree(work);
6043                 drm_vblank_put(dev, intel_crtc->pipe);
6044
6045                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6046                 return -EBUSY;
6047         }
6048         intel_crtc->unpin_work = work;
6049         spin_unlock_irqrestore(&dev->event_lock, flags);
6050
6051         intel_fb = to_intel_framebuffer(fb);
6052         obj = intel_fb->obj;
6053
6054         mutex_lock(&dev->struct_mutex);
6055
6056         /* Reference the objects for the scheduled work. */
6057         drm_gem_object_reference(&work->old_fb_obj->base);
6058         drm_gem_object_reference(&obj->base);
6059
6060         crtc->fb = fb;
6061
6062         work->pending_flip_obj = obj;
6063
6064         work->enable_stall_check = true;
6065
6066         /* Block clients from rendering to the new back buffer until
6067          * the flip occurs and the object is no longer visible.
6068          */
6069         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6070
6071         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6072         if (ret)
6073                 goto cleanup_pending;
6074
6075         intel_disable_fbc(dev);
6076         intel_mark_busy(dev, obj);
6077         mutex_unlock(&dev->struct_mutex);
6078
6079         trace_i915_flip_request(intel_crtc->plane, obj);
6080
6081         return 0;
6082
6083 cleanup_pending:
6084         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6085         drm_gem_object_unreference(&work->old_fb_obj->base);
6086         drm_gem_object_unreference(&obj->base);
6087         mutex_unlock(&dev->struct_mutex);
6088
6089         spin_lock_irqsave(&dev->event_lock, flags);
6090         intel_crtc->unpin_work = NULL;
6091         spin_unlock_irqrestore(&dev->event_lock, flags);
6092
6093         drm_vblank_put(dev, intel_crtc->pipe);
6094 free_work:
6095         kfree(work);
6096
6097         return ret;
6098 }
6099
6100 static void intel_sanitize_modesetting(struct drm_device *dev,
6101                                        int pipe, int plane)
6102 {
6103         struct drm_i915_private *dev_priv = dev->dev_private;
6104         u32 reg, val;
6105
6106         /* Clear any frame start delays used for debugging left by the BIOS */
6107         for_each_pipe(pipe) {
6108                 reg = PIPECONF(pipe);
6109                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6110         }
6111
6112         if (HAS_PCH_SPLIT(dev))
6113                 return;
6114
6115         /* Who knows what state these registers were left in by the BIOS or
6116          * grub?
6117          *
6118          * If we leave the registers in a conflicting state (e.g. with the
6119          * display plane reading from the other pipe than the one we intend
6120          * to use) then when we attempt to teardown the active mode, we will
6121          * not disable the pipes and planes in the correct order -- leaving
6122          * a plane reading from a disabled pipe and possibly leading to
6123          * undefined behaviour.
6124          */
6125
6126         reg = DSPCNTR(plane);
6127         val = I915_READ(reg);
6128
6129         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6130                 return;
6131         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6132                 return;
6133
6134         /* This display plane is active and attached to the other CPU pipe. */
6135         pipe = !pipe;
6136
6137         /* Disable the plane and wait for it to stop reading from the pipe. */
6138         intel_disable_plane(dev_priv, plane, pipe);
6139         intel_disable_pipe(dev_priv, pipe);
6140 }
6141
6142 static void intel_crtc_reset(struct drm_crtc *crtc)
6143 {
6144         struct drm_device *dev = crtc->dev;
6145         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6146
6147         /* Reset flags back to the 'unknown' status so that they
6148          * will be correctly set on the initial modeset.
6149          */
6150         intel_crtc->dpms_mode = -1;
6151
6152         /* We need to fix up any BIOS configuration that conflicts with
6153          * our expectations.
6154          */
6155         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6156 }
6157
6158 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6159         .dpms = intel_crtc_dpms,
6160         .mode_fixup = intel_crtc_mode_fixup,
6161         .mode_set = intel_crtc_mode_set,
6162         .mode_set_base = intel_pipe_set_base,
6163         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6164         .load_lut = intel_crtc_load_lut,
6165         .disable = intel_crtc_disable,
6166 };
6167
6168 static const struct drm_crtc_funcs intel_crtc_funcs = {
6169         .reset = intel_crtc_reset,
6170         .cursor_set = intel_crtc_cursor_set,
6171         .cursor_move = intel_crtc_cursor_move,
6172         .gamma_set = intel_crtc_gamma_set,
6173         .set_config = drm_crtc_helper_set_config,
6174         .destroy = intel_crtc_destroy,
6175         .page_flip = intel_crtc_page_flip,
6176 };
6177
6178 static void intel_pch_pll_init(struct drm_device *dev)
6179 {
6180         drm_i915_private_t *dev_priv = dev->dev_private;
6181         int i;
6182
6183         if (dev_priv->num_pch_pll == 0) {
6184                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6185                 return;
6186         }
6187
6188         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6189                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6190                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6191                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6192         }
6193 }
6194
6195 static void intel_crtc_init(struct drm_device *dev, int pipe)
6196 {
6197         drm_i915_private_t *dev_priv = dev->dev_private;
6198         struct intel_crtc *intel_crtc;
6199         int i;
6200
6201         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6202         if (intel_crtc == NULL)
6203                 return;
6204
6205         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6206
6207         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6208         for (i = 0; i < 256; i++) {
6209                 intel_crtc->lut_r[i] = i;
6210                 intel_crtc->lut_g[i] = i;
6211                 intel_crtc->lut_b[i] = i;
6212         }
6213
6214         /* Swap pipes & planes for FBC on pre-965 */
6215         intel_crtc->pipe = pipe;
6216         intel_crtc->plane = pipe;
6217         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6218                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6219                 intel_crtc->plane = !pipe;
6220         }
6221
6222         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6223                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6224         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6225         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6226
6227         intel_crtc_reset(&intel_crtc->base);
6228         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6229         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6230
6231         if (HAS_PCH_SPLIT(dev)) {
6232                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6233                 intel_helper_funcs.commit = ironlake_crtc_commit;
6234         } else {
6235                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6236                 intel_helper_funcs.commit = i9xx_crtc_commit;
6237         }
6238
6239         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6240
6241         intel_crtc->busy = false;
6242
6243         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6244                     (unsigned long)intel_crtc);
6245 }
6246
6247 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6248                                 struct drm_file *file)
6249 {
6250         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6251         struct drm_mode_object *drmmode_obj;
6252         struct intel_crtc *crtc;
6253
6254         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6255                 return -ENODEV;
6256
6257         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6258                         DRM_MODE_OBJECT_CRTC);
6259
6260         if (!drmmode_obj) {
6261                 DRM_ERROR("no such CRTC id\n");
6262                 return -EINVAL;
6263         }
6264
6265         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6266         pipe_from_crtc_id->pipe = crtc->pipe;
6267
6268         return 0;
6269 }
6270
6271 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6272 {
6273         struct intel_encoder *encoder;
6274         int index_mask = 0;
6275         int entry = 0;
6276
6277         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6278                 if (type_mask & encoder->clone_mask)
6279                         index_mask |= (1 << entry);
6280                 entry++;
6281         }
6282
6283         return index_mask;
6284 }
6285
6286 static bool has_edp_a(struct drm_device *dev)
6287 {
6288         struct drm_i915_private *dev_priv = dev->dev_private;
6289
6290         if (!IS_MOBILE(dev))
6291                 return false;
6292
6293         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6294                 return false;
6295
6296         if (IS_GEN5(dev) &&
6297             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6298                 return false;
6299
6300         return true;
6301 }
6302
6303 static void intel_setup_outputs(struct drm_device *dev)
6304 {
6305         struct drm_i915_private *dev_priv = dev->dev_private;
6306         struct intel_encoder *encoder;
6307         bool dpd_is_edp = false;
6308         bool has_lvds;
6309
6310         has_lvds = intel_lvds_init(dev);
6311         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6312                 /* disable the panel fitter on everything but LVDS */
6313                 I915_WRITE(PFIT_CONTROL, 0);
6314         }
6315
6316         if (HAS_PCH_SPLIT(dev)) {
6317                 dpd_is_edp = intel_dpd_is_edp(dev);
6318
6319                 if (has_edp_a(dev))
6320                         intel_dp_init(dev, DP_A);
6321
6322                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6323                         intel_dp_init(dev, PCH_DP_D);
6324         }
6325
6326         intel_crt_init(dev);
6327
6328         if (HAS_PCH_SPLIT(dev)) {
6329                 int found;
6330
6331                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6332                         /* PCH SDVOB multiplex with HDMIB */
6333                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
6334                         if (!found)
6335                                 intel_hdmi_init(dev, HDMIB);
6336                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6337                                 intel_dp_init(dev, PCH_DP_B);
6338                 }
6339
6340                 if (I915_READ(HDMIC) & PORT_DETECTED)
6341                         intel_hdmi_init(dev, HDMIC);
6342
6343                 if (I915_READ(HDMID) & PORT_DETECTED)
6344                         intel_hdmi_init(dev, HDMID);
6345
6346                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6347                         intel_dp_init(dev, PCH_DP_C);
6348
6349                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6350                         intel_dp_init(dev, PCH_DP_D);
6351
6352         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6353                 bool found = false;
6354
6355                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6356                         DRM_DEBUG_KMS("probing SDVOB\n");
6357                         found = intel_sdvo_init(dev, SDVOB, true);
6358                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6359                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6360                                 intel_hdmi_init(dev, SDVOB);
6361                         }
6362
6363                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6364                                 DRM_DEBUG_KMS("probing DP_B\n");
6365                                 intel_dp_init(dev, DP_B);
6366                         }
6367                 }
6368
6369                 /* Before G4X SDVOC doesn't have its own detect register */
6370
6371                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6372                         DRM_DEBUG_KMS("probing SDVOC\n");
6373                         found = intel_sdvo_init(dev, SDVOC, false);
6374                 }
6375
6376                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6377
6378                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6379                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6380                                 intel_hdmi_init(dev, SDVOC);
6381                         }
6382                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6383                                 DRM_DEBUG_KMS("probing DP_C\n");
6384                                 intel_dp_init(dev, DP_C);
6385                         }
6386                 }
6387
6388                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6389                     (I915_READ(DP_D) & DP_DETECTED)) {
6390                         DRM_DEBUG_KMS("probing DP_D\n");
6391                         intel_dp_init(dev, DP_D);
6392                 }
6393         } else if (IS_GEN2(dev))
6394                 intel_dvo_init(dev);
6395
6396         if (SUPPORTS_TV(dev))
6397                 intel_tv_init(dev);
6398
6399         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6400                 encoder->base.possible_crtcs = encoder->crtc_mask;
6401                 encoder->base.possible_clones =
6402                         intel_encoder_clones(dev, encoder->clone_mask);
6403         }
6404
6405         /* disable all the possible outputs/crtcs before entering KMS mode */
6406         drm_helper_disable_unused_functions(dev);
6407
6408         if (HAS_PCH_SPLIT(dev))
6409                 ironlake_init_pch_refclk(dev);
6410 }
6411
6412 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6413 {
6414         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6415
6416         drm_framebuffer_cleanup(fb);
6417         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6418
6419         kfree(intel_fb);
6420 }
6421
6422 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6423                                                 struct drm_file *file,
6424                                                 unsigned int *handle)
6425 {
6426         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6427         struct drm_i915_gem_object *obj = intel_fb->obj;
6428
6429         return drm_gem_handle_create(file, &obj->base, handle);
6430 }
6431
6432 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6433         .destroy = intel_user_framebuffer_destroy,
6434         .create_handle = intel_user_framebuffer_create_handle,
6435 };
6436
6437 int intel_framebuffer_init(struct drm_device *dev,
6438                            struct intel_framebuffer *intel_fb,
6439                            struct drm_mode_fb_cmd2 *mode_cmd,
6440                            struct drm_i915_gem_object *obj)
6441 {
6442         int ret;
6443
6444         if (obj->tiling_mode == I915_TILING_Y)
6445                 return -EINVAL;
6446
6447         if (mode_cmd->pitches[0] & 63)
6448                 return -EINVAL;
6449
6450         switch (mode_cmd->pixel_format) {
6451         case DRM_FORMAT_RGB332:
6452         case DRM_FORMAT_RGB565:
6453         case DRM_FORMAT_XRGB8888:
6454         case DRM_FORMAT_XBGR8888:
6455         case DRM_FORMAT_ARGB8888:
6456         case DRM_FORMAT_XRGB2101010:
6457         case DRM_FORMAT_ARGB2101010:
6458                 /* RGB formats are common across chipsets */
6459                 break;
6460         case DRM_FORMAT_YUYV:
6461         case DRM_FORMAT_UYVY:
6462         case DRM_FORMAT_YVYU:
6463         case DRM_FORMAT_VYUY:
6464                 break;
6465         default:
6466                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6467                                 mode_cmd->pixel_format);
6468                 return -EINVAL;
6469         }
6470
6471         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6472         if (ret) {
6473                 DRM_ERROR("framebuffer init failed %d\n", ret);
6474                 return ret;
6475         }
6476
6477         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6478         intel_fb->obj = obj;
6479         return 0;
6480 }
6481
6482 static struct drm_framebuffer *
6483 intel_user_framebuffer_create(struct drm_device *dev,
6484                               struct drm_file *filp,
6485                               struct drm_mode_fb_cmd2 *mode_cmd)
6486 {
6487         struct drm_i915_gem_object *obj;
6488
6489         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6490                                                 mode_cmd->handles[0]));
6491         if (&obj->base == NULL)
6492                 return ERR_PTR(-ENOENT);
6493
6494         return intel_framebuffer_create(dev, mode_cmd, obj);
6495 }
6496
6497 static const struct drm_mode_config_funcs intel_mode_funcs = {
6498         .fb_create = intel_user_framebuffer_create,
6499         .output_poll_changed = intel_fb_output_poll_changed,
6500 };
6501
6502 /* Set up chip specific display functions */
6503 static void intel_init_display(struct drm_device *dev)
6504 {
6505         struct drm_i915_private *dev_priv = dev->dev_private;
6506
6507         /* We always want a DPMS function */
6508         if (HAS_PCH_SPLIT(dev)) {
6509                 dev_priv->display.dpms = ironlake_crtc_dpms;
6510                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6511                 dev_priv->display.off = ironlake_crtc_off;
6512                 dev_priv->display.update_plane = ironlake_update_plane;
6513         } else {
6514                 dev_priv->display.dpms = i9xx_crtc_dpms;
6515                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6516                 dev_priv->display.off = i9xx_crtc_off;
6517                 dev_priv->display.update_plane = i9xx_update_plane;
6518         }
6519
6520         /* Returns the core display clock speed */
6521         if (IS_VALLEYVIEW(dev))
6522                 dev_priv->display.get_display_clock_speed =
6523                         valleyview_get_display_clock_speed;
6524         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6525                 dev_priv->display.get_display_clock_speed =
6526                         i945_get_display_clock_speed;
6527         else if (IS_I915G(dev))
6528                 dev_priv->display.get_display_clock_speed =
6529                         i915_get_display_clock_speed;
6530         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6531                 dev_priv->display.get_display_clock_speed =
6532                         i9xx_misc_get_display_clock_speed;
6533         else if (IS_I915GM(dev))
6534                 dev_priv->display.get_display_clock_speed =
6535                         i915gm_get_display_clock_speed;
6536         else if (IS_I865G(dev))
6537                 dev_priv->display.get_display_clock_speed =
6538                         i865_get_display_clock_speed;
6539         else if (IS_I85X(dev))
6540                 dev_priv->display.get_display_clock_speed =
6541                         i855_get_display_clock_speed;
6542         else /* 852, 830 */
6543                 dev_priv->display.get_display_clock_speed =
6544                         i830_get_display_clock_speed;
6545
6546         if (HAS_PCH_SPLIT(dev)) {
6547                 if (IS_GEN5(dev)) {
6548                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6549                         dev_priv->display.write_eld = ironlake_write_eld;
6550                 } else if (IS_GEN6(dev)) {
6551                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6552                         dev_priv->display.write_eld = ironlake_write_eld;
6553                 } else if (IS_IVYBRIDGE(dev)) {
6554                         /* FIXME: detect B0+ stepping and use auto training */
6555                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6556                         dev_priv->display.write_eld = ironlake_write_eld;
6557                 } else
6558                         dev_priv->display.update_wm = NULL;
6559         } else if (IS_VALLEYVIEW(dev)) {
6560                 dev_priv->display.force_wake_get = vlv_force_wake_get;
6561                 dev_priv->display.force_wake_put = vlv_force_wake_put;
6562         } else if (IS_G4X(dev)) {
6563                 dev_priv->display.write_eld = g4x_write_eld;
6564         }
6565
6566         /* Default just returns -ENODEV to indicate unsupported */
6567         dev_priv->display.queue_flip = intel_default_queue_flip;
6568
6569         switch (INTEL_INFO(dev)->gen) {
6570         case 2:
6571                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6572                 break;
6573
6574         case 3:
6575                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6576                 break;
6577
6578         case 4:
6579         case 5:
6580                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6581                 break;
6582
6583         case 6:
6584                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6585                 break;
6586         case 7:
6587                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6588                 break;
6589         }
6590 }
6591
6592 /*
6593  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6594  * resume, or other times.  This quirk makes sure that's the case for
6595  * affected systems.
6596  */
6597 static void quirk_pipea_force(struct drm_device *dev)
6598 {
6599         struct drm_i915_private *dev_priv = dev->dev_private;
6600
6601         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6602         DRM_INFO("applying pipe a force quirk\n");
6603 }
6604
6605 /*
6606  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6607  */
6608 static void quirk_ssc_force_disable(struct drm_device *dev)
6609 {
6610         struct drm_i915_private *dev_priv = dev->dev_private;
6611         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6612         DRM_INFO("applying lvds SSC disable quirk\n");
6613 }
6614
6615 /*
6616  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6617  * brightness value
6618  */
6619 static void quirk_invert_brightness(struct drm_device *dev)
6620 {
6621         struct drm_i915_private *dev_priv = dev->dev_private;
6622         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6623         DRM_INFO("applying inverted panel brightness quirk\n");
6624 }
6625
6626 struct intel_quirk {
6627         int device;
6628         int subsystem_vendor;
6629         int subsystem_device;
6630         void (*hook)(struct drm_device *dev);
6631 };
6632
6633 static struct intel_quirk intel_quirks[] = {
6634         /* HP Mini needs pipe A force quirk (LP: #322104) */
6635         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6636
6637         /* Thinkpad R31 needs pipe A force quirk */
6638         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6639         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6640         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6641
6642         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6643         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6644         /* ThinkPad X40 needs pipe A force quirk */
6645
6646         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6647         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6648
6649         /* 855 & before need to leave pipe A & dpll A up */
6650         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6651         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6652
6653         /* Lenovo U160 cannot use SSC on LVDS */
6654         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6655
6656         /* Sony Vaio Y cannot use SSC on LVDS */
6657         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6658
6659         /* Acer Aspire 5734Z must invert backlight brightness */
6660         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6661 };
6662
6663 static void intel_init_quirks(struct drm_device *dev)
6664 {
6665         struct pci_dev *d = dev->pdev;
6666         int i;
6667
6668         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6669                 struct intel_quirk *q = &intel_quirks[i];
6670
6671                 if (d->device == q->device &&
6672                     (d->subsystem_vendor == q->subsystem_vendor ||
6673                      q->subsystem_vendor == PCI_ANY_ID) &&
6674                     (d->subsystem_device == q->subsystem_device ||
6675                      q->subsystem_device == PCI_ANY_ID))
6676                         q->hook(dev);
6677         }
6678 }
6679
6680 /* Disable the VGA plane that we never use */
6681 static void i915_disable_vga(struct drm_device *dev)
6682 {
6683         struct drm_i915_private *dev_priv = dev->dev_private;
6684         u8 sr1;
6685         u32 vga_reg;
6686
6687         if (HAS_PCH_SPLIT(dev))
6688                 vga_reg = CPU_VGACNTRL;
6689         else
6690                 vga_reg = VGACNTRL;
6691
6692         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6693         outb(SR01, VGA_SR_INDEX);
6694         sr1 = inb(VGA_SR_DATA);
6695         outb(sr1 | 1<<5, VGA_SR_DATA);
6696         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6697         udelay(300);
6698
6699         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6700         POSTING_READ(vga_reg);
6701 }
6702
6703 static void ivb_pch_pwm_override(struct drm_device *dev)
6704 {
6705         struct drm_i915_private *dev_priv = dev->dev_private;
6706
6707         /*
6708          * IVB has CPU eDP backlight regs too, set things up to let the
6709          * PCH regs control the backlight
6710          */
6711         I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6712         I915_WRITE(BLC_PWM_CPU_CTL, 0);
6713         I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6714 }
6715
6716 void intel_modeset_init_hw(struct drm_device *dev)
6717 {
6718         struct drm_i915_private *dev_priv = dev->dev_private;
6719
6720         intel_init_clock_gating(dev);
6721
6722         if (IS_IRONLAKE_M(dev)) {
6723                 ironlake_enable_drps(dev);
6724                 ironlake_enable_rc6(dev);
6725                 intel_init_emon(dev);
6726         }
6727
6728         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6729                 gen6_enable_rps(dev_priv);
6730                 gen6_update_ring_freq(dev_priv);
6731         }
6732
6733         if (IS_IVYBRIDGE(dev))
6734                 ivb_pch_pwm_override(dev);
6735 }
6736
6737 void intel_modeset_init(struct drm_device *dev)
6738 {
6739         struct drm_i915_private *dev_priv = dev->dev_private;
6740         int i, ret;
6741
6742         drm_mode_config_init(dev);
6743
6744         dev->mode_config.min_width = 0;
6745         dev->mode_config.min_height = 0;
6746
6747         dev->mode_config.preferred_depth = 24;
6748         dev->mode_config.prefer_shadow = 1;
6749
6750         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6751
6752         intel_init_quirks(dev);
6753
6754         intel_init_pm(dev);
6755
6756         intel_init_display(dev);
6757
6758         if (IS_GEN2(dev)) {
6759                 dev->mode_config.max_width = 2048;
6760                 dev->mode_config.max_height = 2048;
6761         } else if (IS_GEN3(dev)) {
6762                 dev->mode_config.max_width = 4096;
6763                 dev->mode_config.max_height = 4096;
6764         } else {
6765                 dev->mode_config.max_width = 8192;
6766                 dev->mode_config.max_height = 8192;
6767         }
6768         dev->mode_config.fb_base = dev->agp->base;
6769
6770         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6771                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6772
6773         for (i = 0; i < dev_priv->num_pipe; i++) {
6774                 intel_crtc_init(dev, i);
6775                 ret = intel_plane_init(dev, i);
6776                 if (ret)
6777                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6778         }
6779
6780         intel_pch_pll_init(dev);
6781
6782         /* Just disable it once at startup */
6783         i915_disable_vga(dev);
6784         intel_setup_outputs(dev);
6785
6786         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6787         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6788                     (unsigned long)dev);
6789 }
6790
6791 void intel_modeset_gem_init(struct drm_device *dev)
6792 {
6793         intel_modeset_init_hw(dev);
6794
6795         intel_setup_overlay(dev);
6796 }
6797
6798 void intel_modeset_cleanup(struct drm_device *dev)
6799 {
6800         struct drm_i915_private *dev_priv = dev->dev_private;
6801         struct drm_crtc *crtc;
6802         struct intel_crtc *intel_crtc;
6803
6804         drm_kms_helper_poll_fini(dev);
6805         mutex_lock(&dev->struct_mutex);
6806
6807         intel_unregister_dsm_handler();
6808
6809
6810         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6811                 /* Skip inactive CRTCs */
6812                 if (!crtc->fb)
6813                         continue;
6814
6815                 intel_crtc = to_intel_crtc(crtc);
6816                 intel_increase_pllclock(crtc);
6817         }
6818
6819         intel_disable_fbc(dev);
6820
6821         if (IS_IRONLAKE_M(dev))
6822                 ironlake_disable_drps(dev);
6823         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
6824                 gen6_disable_rps(dev);
6825
6826         if (IS_IRONLAKE_M(dev))
6827                 ironlake_disable_rc6(dev);
6828
6829         if (IS_VALLEYVIEW(dev))
6830                 vlv_init_dpio(dev);
6831
6832         mutex_unlock(&dev->struct_mutex);
6833
6834         /* Disable the irq before mode object teardown, for the irq might
6835          * enqueue unpin/hotplug work. */
6836         drm_irq_uninstall(dev);
6837         cancel_work_sync(&dev_priv->hotplug_work);
6838         cancel_work_sync(&dev_priv->rps_work);
6839
6840         /* flush any delayed tasks or pending work */
6841         flush_scheduled_work();
6842
6843         /* Shut off idle work before the crtcs get freed. */
6844         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6845                 intel_crtc = to_intel_crtc(crtc);
6846                 del_timer_sync(&intel_crtc->idle_timer);
6847         }
6848         del_timer_sync(&dev_priv->idle_timer);
6849         cancel_work_sync(&dev_priv->idle_work);
6850
6851         drm_mode_config_cleanup(dev);
6852 }
6853
6854 /*
6855  * Return which encoder is currently attached for connector.
6856  */
6857 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6858 {
6859         return &intel_attached_encoder(connector)->base;
6860 }
6861
6862 void intel_connector_attach_encoder(struct intel_connector *connector,
6863                                     struct intel_encoder *encoder)
6864 {
6865         connector->encoder = encoder;
6866         drm_mode_connector_attach_encoder(&connector->base,
6867                                           &encoder->base);
6868 }
6869
6870 /*
6871  * set vga decode state - true == enable VGA decode
6872  */
6873 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6874 {
6875         struct drm_i915_private *dev_priv = dev->dev_private;
6876         u16 gmch_ctrl;
6877
6878         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6879         if (state)
6880                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6881         else
6882                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6883         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6884         return 0;
6885 }
6886
6887 #ifdef CONFIG_DEBUG_FS
6888 #include <linux/seq_file.h>
6889
6890 struct intel_display_error_state {
6891         struct intel_cursor_error_state {
6892                 u32 control;
6893                 u32 position;
6894                 u32 base;
6895                 u32 size;
6896         } cursor[2];
6897
6898         struct intel_pipe_error_state {
6899                 u32 conf;
6900                 u32 source;
6901
6902                 u32 htotal;
6903                 u32 hblank;
6904                 u32 hsync;
6905                 u32 vtotal;
6906                 u32 vblank;
6907                 u32 vsync;
6908         } pipe[2];
6909
6910         struct intel_plane_error_state {
6911                 u32 control;
6912                 u32 stride;
6913                 u32 size;
6914                 u32 pos;
6915                 u32 addr;
6916                 u32 surface;
6917                 u32 tile_offset;
6918         } plane[2];
6919 };
6920
6921 struct intel_display_error_state *
6922 intel_display_capture_error_state(struct drm_device *dev)
6923 {
6924         drm_i915_private_t *dev_priv = dev->dev_private;
6925         struct intel_display_error_state *error;
6926         int i;
6927
6928         error = kmalloc(sizeof(*error), GFP_ATOMIC);
6929         if (error == NULL)
6930                 return NULL;
6931
6932         for (i = 0; i < 2; i++) {
6933                 error->cursor[i].control = I915_READ(CURCNTR(i));
6934                 error->cursor[i].position = I915_READ(CURPOS(i));
6935                 error->cursor[i].base = I915_READ(CURBASE(i));
6936
6937                 error->plane[i].control = I915_READ(DSPCNTR(i));
6938                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6939                 error->plane[i].size = I915_READ(DSPSIZE(i));
6940                 error->plane[i].pos = I915_READ(DSPPOS(i));
6941                 error->plane[i].addr = I915_READ(DSPADDR(i));
6942                 if (INTEL_INFO(dev)->gen >= 4) {
6943                         error->plane[i].surface = I915_READ(DSPSURF(i));
6944                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6945                 }
6946
6947                 error->pipe[i].conf = I915_READ(PIPECONF(i));
6948                 error->pipe[i].source = I915_READ(PIPESRC(i));
6949                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6950                 error->pipe[i].hblank = I915_READ(HBLANK(i));
6951                 error->pipe[i].hsync = I915_READ(HSYNC(i));
6952                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6953                 error->pipe[i].vblank = I915_READ(VBLANK(i));
6954                 error->pipe[i].vsync = I915_READ(VSYNC(i));
6955         }
6956
6957         return error;
6958 }
6959
6960 void
6961 intel_display_print_error_state(struct seq_file *m,
6962                                 struct drm_device *dev,
6963                                 struct intel_display_error_state *error)
6964 {
6965         int i;
6966
6967         for (i = 0; i < 2; i++) {
6968                 seq_printf(m, "Pipe [%d]:\n", i);
6969                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
6970                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
6971                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
6972                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
6973                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
6974                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
6975                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
6976                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
6977
6978                 seq_printf(m, "Plane [%d]:\n", i);
6979                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
6980                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
6981                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
6982                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
6983                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
6984                 if (INTEL_INFO(dev)->gen >= 4) {
6985                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
6986                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
6987                 }
6988
6989                 seq_printf(m, "Cursor [%d]:\n", i);
6990                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
6991                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
6992                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
6993         }
6994 }
6995 #endif