drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_set_mode(struct drm_crtc *crtc,
  90                           struct drm_atomic_state *state);
  91 static int intel_framebuffer_init(struct drm_device *dev,
  92                                   struct intel_framebuffer *ifb,
  93                                   struct drm_mode_fb_cmd2 *mode_cmd,
  94                                   struct drm_i915_gem_object *obj);
  95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  98                                          struct intel_link_m_n *m_n,
  99                                          struct intel_link_m_n *m2_n2);
 100 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 101 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 102 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 103 static void vlv_prepare_pll(struct intel_crtc *crtc,
 104                             const struct intel_crtc_state *pipe_config);
 105 static void chv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 108 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 109 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 110         struct intel_crtc_state *crtc_state);
 111 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 112                            int num_connectors);
 113 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
 114 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
 115
 116 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 117 {
 118         if (!connector->mst_port)
 119                 return connector->encoder;
 120         else
 121                 return &connector->mst_port->mst_encoders[pipe]->base;
 122 }
 123
 124 typedef struct {
 125         int     min, max;
 126 } intel_range_t;
 127
 128 typedef struct {
 129         int     dot_limit;
 130         int     p2_slow, p2_fast;
 131 } intel_p2_t;
 132
 133 typedef struct intel_limit intel_limit_t;
 134 struct intel_limit {
 135         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 136         intel_p2_t          p2;
 137 };
 138
 139 int
 140 intel_pch_rawclk(struct drm_device *dev)
 141 {
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143
 144         WARN_ON(!HAS_PCH_SPLIT(dev));
 145
 146         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 147 }
 148
 149 static inline u32 /* units of 100MHz */
 150 intel_fdi_link_freq(struct drm_device *dev)
 151 {
 152         if (IS_GEN5(dev)) {
 153                 struct drm_i915_private *dev_priv = dev->dev_private;
 154                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 155         } else
 156                 return 27;
 157 }
 158
 159 static const intel_limit_t intel_limits_i8xx_dac = {
 160         .dot = { .min = 25000, .max = 350000 },
 161         .vco = { .min = 908000, .max = 1512000 },
 162         .n = { .min = 2, .max = 16 },
 163         .m = { .min = 96, .max = 140 },
 164         .m1 = { .min = 18, .max = 26 },
 165         .m2 = { .min = 6, .max = 16 },
 166         .p = { .min = 4, .max = 128 },
 167         .p1 = { .min = 2, .max = 33 },
 168         .p2 = { .dot_limit = 165000,
 169                 .p2_slow = 4, .p2_fast = 2 },
 170 };
 171
 172 static const intel_limit_t intel_limits_i8xx_dvo = {
 173         .dot = { .min = 25000, .max = 350000 },
 174         .vco = { .min = 908000, .max = 1512000 },
 175         .n = { .min = 2, .max = 16 },
 176         .m = { .min = 96, .max = 140 },
 177         .m1 = { .min = 18, .max = 26 },
 178         .m2 = { .min = 6, .max = 16 },
 179         .p = { .min = 4, .max = 128 },
 180         .p1 = { .min = 2, .max = 33 },
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 4, .p2_fast = 4 },
 183 };
 184
 185 static const intel_limit_t intel_limits_i8xx_lvds = {
 186         .dot = { .min = 25000, .max = 350000 },
 187         .vco = { .min = 908000, .max = 1512000 },
 188         .n = { .min = 2, .max = 16 },
 189         .m = { .min = 96, .max = 140 },
 190         .m1 = { .min = 18, .max = 26 },
 191         .m2 = { .min = 6, .max = 16 },
 192         .p = { .min = 4, .max = 128 },
 193         .p1 = { .min = 1, .max = 6 },
 194         .p2 = { .dot_limit = 165000,
 195                 .p2_slow = 14, .p2_fast = 7 },
 196 };
 197
 198 static const intel_limit_t intel_limits_i9xx_sdvo = {
 199         .dot = { .min = 20000, .max = 400000 },
 200         .vco = { .min = 1400000, .max = 2800000 },
 201         .n = { .min = 1, .max = 6 },
 202         .m = { .min = 70, .max = 120 },
 203         .m1 = { .min = 8, .max = 18 },
 204         .m2 = { .min = 3, .max = 7 },
 205         .p = { .min = 5, .max = 80 },
 206         .p1 = { .min = 1, .max = 8 },
 207         .p2 = { .dot_limit = 200000,
 208                 .p2_slow = 10, .p2_fast = 5 },
 209 };
 210
 211 static const intel_limit_t intel_limits_i9xx_lvds = {
 212         .dot = { .min = 20000, .max = 400000 },
 213         .vco = { .min = 1400000, .max = 2800000 },
 214         .n = { .min = 1, .max = 6 },
 215         .m = { .min = 70, .max = 120 },
 216         .m1 = { .min = 8, .max = 18 },
 217         .m2 = { .min = 3, .max = 7 },
 218         .p = { .min = 7, .max = 98 },
 219         .p1 = { .min = 1, .max = 8 },
 220         .p2 = { .dot_limit = 112000,
 221                 .p2_slow = 14, .p2_fast = 7 },
 222 };
 223
 224
 225 static const intel_limit_t intel_limits_g4x_sdvo = {
 226         .dot = { .min = 25000, .max = 270000 },
 227         .vco = { .min = 1750000, .max = 3500000},
 228         .n = { .min = 1, .max = 4 },
 229         .m = { .min = 104, .max = 138 },
 230         .m1 = { .min = 17, .max = 23 },
 231         .m2 = { .min = 5, .max = 11 },
 232         .p = { .min = 10, .max = 30 },
 233         .p1 = { .min = 1, .max = 3},
 234         .p2 = { .dot_limit = 270000,
 235                 .p2_slow = 10,
 236                 .p2_fast = 10
 237         },
 238 };
 239
 240 static const intel_limit_t intel_limits_g4x_hdmi = {
 241         .dot = { .min = 22000, .max = 400000 },
 242         .vco = { .min = 1750000, .max = 3500000},
 243         .n = { .min = 1, .max = 4 },
 244         .m = { .min = 104, .max = 138 },
 245         .m1 = { .min = 16, .max = 23 },
 246         .m2 = { .min = 5, .max = 11 },
 247         .p = { .min = 5, .max = 80 },
 248         .p1 = { .min = 1, .max = 8},
 249         .p2 = { .dot_limit = 165000,
 250                 .p2_slow = 10, .p2_fast = 5 },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 254         .dot = { .min = 20000, .max = 115000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 28, .max = 112 },
 261         .p1 = { .min = 2, .max = 8 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 14, .p2_fast = 14
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 268         .dot = { .min = 80000, .max = 224000 },
 269         .vco = { .min = 1750000, .max = 3500000 },
 270         .n = { .min = 1, .max = 3 },
 271         .m = { .min = 104, .max = 138 },
 272         .m1 = { .min = 17, .max = 23 },
 273         .m2 = { .min = 5, .max = 11 },
 274         .p = { .min = 14, .max = 42 },
 275         .p1 = { .min = 2, .max = 6 },
 276         .p2 = { .dot_limit = 0,
 277                 .p2_slow = 7, .p2_fast = 7
 278         },
 279 };
 280
 281 static const intel_limit_t intel_limits_pineview_sdvo = {
 282         .dot = { .min = 20000, .max = 400000},
 283         .vco = { .min = 1700000, .max = 3500000 },
 284         /* Pineview's Ncounter is a ring counter */
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         /* Pineview only has one combined m divider, which we treat as m2. */
 288         .m1 = { .min = 0, .max = 0 },
 289         .m2 = { .min = 0, .max = 254 },
 290         .p = { .min = 5, .max = 80 },
 291         .p1 = { .min = 1, .max = 8 },
 292         .p2 = { .dot_limit = 200000,
 293                 .p2_slow = 10, .p2_fast = 5 },
 294 };
 295
 296 static const intel_limit_t intel_limits_pineview_lvds = {
 297         .dot = { .min = 20000, .max = 400000 },
 298         .vco = { .min = 1700000, .max = 3500000 },
 299         .n = { .min = 3, .max = 6 },
 300         .m = { .min = 2, .max = 256 },
 301         .m1 = { .min = 0, .max = 0 },
 302         .m2 = { .min = 0, .max = 254 },
 303         .p = { .min = 7, .max = 112 },
 304         .p1 = { .min = 1, .max = 8 },
 305         .p2 = { .dot_limit = 112000,
 306                 .p2_slow = 14, .p2_fast = 14 },
 307 };
 308
 309 /* Ironlake / Sandybridge
 310  *
 311  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 312  * the range value for them is (actual_value - 2).
 313  */
 314 static const intel_limit_t intel_limits_ironlake_dac = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 5 },
 318         .m = { .min = 79, .max = 127 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 5, .max = 80 },
 322         .p1 = { .min = 1, .max = 8 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 10, .p2_fast = 5 },
 325 };
 326
 327 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 328         .dot = { .min = 25000, .max = 350000 },
 329         .vco = { .min = 1760000, .max = 3510000 },
 330         .n = { .min = 1, .max = 3 },
 331         .m = { .min = 79, .max = 118 },
 332         .m1 = { .min = 12, .max = 22 },
 333         .m2 = { .min = 5, .max = 9 },
 334         .p = { .min = 28, .max = 112 },
 335         .p1 = { .min = 2, .max = 8 },
 336         .p2 = { .dot_limit = 225000,
 337                 .p2_slow = 14, .p2_fast = 14 },
 338 };
 339
 340 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 3 },
 344         .m = { .min = 79, .max = 127 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 14, .max = 56 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 7, .p2_fast = 7 },
 351 };
 352
 353 /* LVDS 100mhz refclk limits. */
 354 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 355         .dot = { .min = 25000, .max = 350000 },
 356         .vco = { .min = 1760000, .max = 3510000 },
 357         .n = { .min = 1, .max = 2 },
 358         .m = { .min = 79, .max = 126 },
 359         .m1 = { .min = 12, .max = 22 },
 360         .m2 = { .min = 5, .max = 9 },
 361         .p = { .min = 28, .max = 112 },
 362         .p1 = { .min = 2, .max = 8 },
 363         .p2 = { .dot_limit = 225000,
 364                 .p2_slow = 14, .p2_fast = 14 },
 365 };
 366
 367 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 368         .dot = { .min = 25000, .max = 350000 },
 369         .vco = { .min = 1760000, .max = 3510000 },
 370         .n = { .min = 1, .max = 3 },
 371         .m = { .min = 79, .max = 126 },
 372         .m1 = { .min = 12, .max = 22 },
 373         .m2 = { .min = 5, .max = 9 },
 374         .p = { .min = 14, .max = 42 },
 375         .p1 = { .min = 2, .max = 6 },
 376         .p2 = { .dot_limit = 225000,
 377                 .p2_slow = 7, .p2_fast = 7 },
 378 };
 379
 380 static const intel_limit_t intel_limits_vlv = {
 381          /*
 382           * These are the data rate limits (measured in fast clocks)
 383           * since those are the strictest limits we have. The fast
 384           * clock and actual rate limits are more relaxed, so checking
 385           * them would make no difference.
 386           */
 387         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 388         .vco = { .min = 4000000, .max = 6000000 },
 389         .n = { .min = 1, .max = 7 },
 390         .m1 = { .min = 2, .max = 3 },
 391         .m2 = { .min = 11, .max = 156 },
 392         .p1 = { .min = 2, .max = 3 },
 393         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 394 };
 395
 396 static const intel_limit_t intel_limits_chv = {
 397         /*
 398          * These are the data rate limits (measured in fast clocks)
 399          * since those are the strictest limits we have.  The fast
 400          * clock and actual rate limits are more relaxed, so checking
 401          * them would make no difference.
 402          */
 403         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 404         .vco = { .min = 4800000, .max = 6480000 },
 405         .n = { .min = 1, .max = 1 },
 406         .m1 = { .min = 2, .max = 2 },
 407         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 408         .p1 = { .min = 2, .max = 4 },
 409         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 410 };
 411
 412 static const intel_limit_t intel_limits_bxt = {
 413         /* FIXME: find real dot limits */
 414         .dot = { .min = 0, .max = INT_MAX },
 415         .vco = { .min = 4800000, .max = 6480000 },
 416         .n = { .min = 1, .max = 1 },
 417         .m1 = { .min = 2, .max = 2 },
 418         /* FIXME: find real m2 limits */
 419         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 420         .p1 = { .min = 2, .max = 4 },
 421         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 422 };
 423
 424 static void vlv_clock(int refclk, intel_clock_t *clock)
 425 {
 426         clock->m = clock->m1 * clock->m2;
 427         clock->p = clock->p1 * clock->p2;
 428         if (WARN_ON(clock->n == 0 || clock->p == 0))
 429                 return;
 430         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 431         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 432 }
 433
 434 /**
 435  * Returns whether any output on the specified pipe is of the specified type
 436  */
 437 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 438 {
 439         struct drm_device *dev = crtc->base.dev;
 440         struct intel_encoder *encoder;
 441
 442         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 443                 if (encoder->type == type)
 444                         return true;
 445
 446         return false;
 447 }
 448
 449 /**
 450  * Returns whether any output on the specified pipe will have the specified
 451  * type after a staged modeset is complete, i.e., the same as
 452  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 453  * encoder->crtc.
 454  */
 455 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 456                                       int type)
 457 {
 458         struct drm_atomic_state *state = crtc_state->base.state;
 459         struct drm_connector *connector;
 460         struct drm_connector_state *connector_state;
 461         struct intel_encoder *encoder;
 462         int i, num_connectors = 0;
 463
 464         for_each_connector_in_state(state, connector, connector_state, i) {
 465                 if (connector_state->crtc != crtc_state->base.crtc)
 466                         continue;
 467
 468                 num_connectors++;
 469
 470                 encoder = to_intel_encoder(connector_state->best_encoder);
 471                 if (encoder->type == type)
 472                         return true;
 473         }
 474
 475         WARN_ON(num_connectors == 0);
 476
 477         return false;
 478 }
 479
 480 static const intel_limit_t *
 481 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 482 {
 483         struct drm_device *dev = crtc_state->base.crtc->dev;
 484         const intel_limit_t *limit;
 485
 486         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 487                 if (intel_is_dual_link_lvds(dev)) {
 488                         if (refclk == 100000)
 489                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 490                         else
 491                                 limit = &intel_limits_ironlake_dual_lvds;
 492                 } else {
 493                         if (refclk == 100000)
 494                                 limit = &intel_limits_ironlake_single_lvds_100m;
 495                         else
 496                                 limit = &intel_limits_ironlake_single_lvds;
 497                 }
 498         } else
 499                 limit = &intel_limits_ironlake_dac;
 500
 501         return limit;
 502 }
 503
 504 static const intel_limit_t *
 505 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 506 {
 507         struct drm_device *dev = crtc_state->base.crtc->dev;
 508         const intel_limit_t *limit;
 509
 510         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 511                 if (intel_is_dual_link_lvds(dev))
 512                         limit = &intel_limits_g4x_dual_channel_lvds;
 513                 else
 514                         limit = &intel_limits_g4x_single_channel_lvds;
 515         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 516                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 517                 limit = &intel_limits_g4x_hdmi;
 518         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 519                 limit = &intel_limits_g4x_sdvo;
 520         } else /* The option is for other outputs */
 521                 limit = &intel_limits_i9xx_sdvo;
 522
 523         return limit;
 524 }
 525
 526 static const intel_limit_t *
 527 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 528 {
 529         struct drm_device *dev = crtc_state->base.crtc->dev;
 530         const intel_limit_t *limit;
 531
 532         if (IS_BROXTON(dev))
 533                 limit = &intel_limits_bxt;
 534         else if (HAS_PCH_SPLIT(dev))
 535                 limit = intel_ironlake_limit(crtc_state, refclk);
 536         else if (IS_G4X(dev)) {
 537                 limit = intel_g4x_limit(crtc_state);
 538         } else if (IS_PINEVIEW(dev)) {
 539                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 540                         limit = &intel_limits_pineview_lvds;
 541                 else
 542                         limit = &intel_limits_pineview_sdvo;
 543         } else if (IS_CHERRYVIEW(dev)) {
 544                 limit = &intel_limits_chv;
 545         } else if (IS_VALLEYVIEW(dev)) {
 546                 limit = &intel_limits_vlv;
 547         } else if (!IS_GEN2(dev)) {
 548                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 549                         limit = &intel_limits_i9xx_lvds;
 550                 else
 551                         limit = &intel_limits_i9xx_sdvo;
 552         } else {
 553                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 554                         limit = &intel_limits_i8xx_lvds;
 555                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 556                         limit = &intel_limits_i8xx_dvo;
 557                 else
 558                         limit = &intel_limits_i8xx_dac;
 559         }
 560         return limit;
 561 }
 562
 563 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 564 static void pineview_clock(int refclk, intel_clock_t *clock)
 565 {
 566         clock->m = clock->m2 + 2;
 567         clock->p = clock->p1 * clock->p2;
 568         if (WARN_ON(clock->n == 0 || clock->p == 0))
 569                 return;
 570         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 571         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 572 }
 573
 574 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 575 {
 576         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 577 }
 578
 579 static void i9xx_clock(int refclk, intel_clock_t *clock)
 580 {
 581         clock->m = i9xx_dpll_compute_m(clock);
 582         clock->p = clock->p1 * clock->p2;
 583         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 584                 return;
 585         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 586         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 587 }
 588
 589 static void chv_clock(int refclk, intel_clock_t *clock)
 590 {
 591         clock->m = clock->m1 * clock->m2;
 592         clock->p = clock->p1 * clock->p2;
 593         if (WARN_ON(clock->n == 0 || clock->p == 0))
 594                 return;
 595         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 596                         clock->n << 22);
 597         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 598 }
 599
 600 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 601 /**
 602  * Returns whether the given set of divisors are valid for a given refclk with
 603  * the given connectors.
 604  */
 605
 606 static bool intel_PLL_is_valid(struct drm_device *dev,
 607                                const intel_limit_t *limit,
 608                                const intel_clock_t *clock)
 609 {
 610         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 611                 INTELPllInvalid("n out of range\n");
 612         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 613                 INTELPllInvalid("p1 out of range\n");
 614         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 615                 INTELPllInvalid("m2 out of range\n");
 616         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 617                 INTELPllInvalid("m1 out of range\n");
 618
 619         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 620                 if (clock->m1 <= clock->m2)
 621                         INTELPllInvalid("m1 <= m2\n");
 622
 623         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 624                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 625                         INTELPllInvalid("p out of range\n");
 626                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 627                         INTELPllInvalid("m out of range\n");
 628         }
 629
 630         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 631                 INTELPllInvalid("vco out of range\n");
 632         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 633          * connector, etc., rather than just a single range.
 634          */
 635         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 636                 INTELPllInvalid("dot out of range\n");
 637
 638         return true;
 639 }
 640
 641 static bool
 642 i9xx_find_best_dpll(const intel_limit_t *limit,
 643                     struct intel_crtc_state *crtc_state,
 644                     int target, int refclk, intel_clock_t *match_clock,
 645                     intel_clock_t *best_clock)
 646 {
 647         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 648         struct drm_device *dev = crtc->base.dev;
 649         intel_clock_t clock;
 650         int err = target;
 651
 652         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 653                 /*
 654                  * For LVDS just rely on its current settings for dual-channel.
 655                  * We haven't figured out how to reliably set up different
 656                  * single/dual channel state, if we even can.
 657                  */
 658                 if (intel_is_dual_link_lvds(dev))
 659                         clock.p2 = limit->p2.p2_fast;
 660                 else
 661                         clock.p2 = limit->p2.p2_slow;
 662         } else {
 663                 if (target < limit->p2.dot_limit)
 664                         clock.p2 = limit->p2.p2_slow;
 665                 else
 666                         clock.p2 = limit->p2.p2_fast;
 667         }
 668
 669         memset(best_clock, 0, sizeof(*best_clock));
 670
 671         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 672              clock.m1++) {
 673                 for (clock.m2 = limit->m2.min;
 674                      clock.m2 <= limit->m2.max; clock.m2++) {
 675                         if (clock.m2 >= clock.m1)
 676                                 break;
 677                         for (clock.n = limit->n.min;
 678                              clock.n <= limit->n.max; clock.n++) {
 679                                 for (clock.p1 = limit->p1.min;
 680                                         clock.p1 <= limit->p1.max; clock.p1++) {
 681                                         int this_err;
 682
 683                                         i9xx_clock(refclk, &clock);
 684                                         if (!intel_PLL_is_valid(dev, limit,
 685                                                                 &clock))
 686                                                 continue;
 687                                         if (match_clock &&
 688                                             clock.p != match_clock->p)
 689                                                 continue;
 690
 691                                         this_err = abs(clock.dot - target);
 692                                         if (this_err < err) {
 693                                                 *best_clock = clock;
 694                                                 err = this_err;
 695                                         }
 696                                 }
 697                         }
 698                 }
 699         }
 700
 701         return (err != target);
 702 }
 703
 704 static bool
 705 pnv_find_best_dpll(const intel_limit_t *limit,
 706                    struct intel_crtc_state *crtc_state,
 707                    int target, int refclk, intel_clock_t *match_clock,
 708                    intel_clock_t *best_clock)
 709 {
 710         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 711         struct drm_device *dev = crtc->base.dev;
 712         intel_clock_t clock;
 713         int err = target;
 714
 715         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 716                 /*
 717                  * For LVDS just rely on its current settings for dual-channel.
 718                  * We haven't figured out how to reliably set up different
 719                  * single/dual channel state, if we even can.
 720                  */
 721                 if (intel_is_dual_link_lvds(dev))
 722                         clock.p2 = limit->p2.p2_fast;
 723                 else
 724                         clock.p2 = limit->p2.p2_slow;
 725         } else {
 726                 if (target < limit->p2.dot_limit)
 727                         clock.p2 = limit->p2.p2_slow;
 728                 else
 729                         clock.p2 = limit->p2.p2_fast;
 730         }
 731
 732         memset(best_clock, 0, sizeof(*best_clock));
 733
 734         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 735              clock.m1++) {
 736                 for (clock.m2 = limit->m2.min;
 737                      clock.m2 <= limit->m2.max; clock.m2++) {
 738                         for (clock.n = limit->n.min;
 739                              clock.n <= limit->n.max; clock.n++) {
 740                                 for (clock.p1 = limit->p1.min;
 741                                         clock.p1 <= limit->p1.max; clock.p1++) {
 742                                         int this_err;
 743
 744                                         pineview_clock(refclk, &clock);
 745                                         if (!intel_PLL_is_valid(dev, limit,
 746                                                                 &clock))
 747                                                 continue;
 748                                         if (match_clock &&
 749                                             clock.p != match_clock->p)
 750                                                 continue;
 751
 752                                         this_err = abs(clock.dot - target);
 753                                         if (this_err < err) {
 754                                                 *best_clock = clock;
 755                                                 err = this_err;
 756                                         }
 757                                 }
 758                         }
 759                 }
 760         }
 761
 762         return (err != target);
 763 }
 764
 765 static bool
 766 g4x_find_best_dpll(const intel_limit_t *limit,
 767                    struct intel_crtc_state *crtc_state,
 768                    int target, int refclk, intel_clock_t *match_clock,
 769                    intel_clock_t *best_clock)
 770 {
 771         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 772         struct drm_device *dev = crtc->base.dev;
 773         intel_clock_t clock;
 774         int max_n;
 775         bool found;
 776         /* approximately equals target * 0.00585 */
 777         int err_most = (target >> 8) + (target >> 9);
 778         found = false;
 779
 780         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 781                 if (intel_is_dual_link_lvds(dev))
 782                         clock.p2 = limit->p2.p2_fast;
 783                 else
 784                         clock.p2 = limit->p2.p2_slow;
 785         } else {
 786                 if (target < limit->p2.dot_limit)
 787                         clock.p2 = limit->p2.p2_slow;
 788                 else
 789                         clock.p2 = limit->p2.p2_fast;
 790         }
 791
 792         memset(best_clock, 0, sizeof(*best_clock));
 793         max_n = limit->n.max;
 794         /* based on hardware requirement, prefer smaller n to precision */
 795         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 796                 /* based on hardware requirement, prefere larger m1,m2 */
 797                 for (clock.m1 = limit->m1.max;
 798                      clock.m1 >= limit->m1.min; clock.m1--) {
 799                         for (clock.m2 = limit->m2.max;
 800                              clock.m2 >= limit->m2.min; clock.m2--) {
 801                                 for (clock.p1 = limit->p1.max;
 802                                      clock.p1 >= limit->p1.min; clock.p1--) {
 803                                         int this_err;
 804
 805                                         i9xx_clock(refclk, &clock);
 806                                         if (!intel_PLL_is_valid(dev, limit,
 807                                                                 &clock))
 808                                                 continue;
 809
 810                                         this_err = abs(clock.dot - target);
 811                                         if (this_err < err_most) {
 812                                                 *best_clock = clock;
 813                                                 err_most = this_err;
 814                                                 max_n = clock.n;
 815                                                 found = true;
 816                                         }
 817                                 }
 818                         }
 819                 }
 820         }
 821         return found;
 822 }
 823
 824 /*
 825  * Check if the calculated PLL configuration is more optimal compared to the
 826  * best configuration and error found so far. Return the calculated error.
 827  */
 828 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 829                                const intel_clock_t *calculated_clock,
 830                                const intel_clock_t *best_clock,
 831                                unsigned int best_error_ppm,
 832                                unsigned int *error_ppm)
 833 {
 834         /*
 835          * For CHV ignore the error and consider only the P value.
 836          * Prefer a bigger P value based on HW requirements.
 837          */
 838         if (IS_CHERRYVIEW(dev)) {
 839                 *error_ppm = 0;
 840
 841                 return calculated_clock->p > best_clock->p;
 842         }
 843
 844         if (WARN_ON_ONCE(!target_freq))
 845                 return false;
 846
 847         *error_ppm = div_u64(1000000ULL *
 848                                 abs(target_freq - calculated_clock->dot),
 849                              target_freq);
 850         /*
 851          * Prefer a better P value over a better (smaller) error if the error
 852          * is small. Ensure this preference for future configurations too by
 853          * setting the error to 0.
 854          */
 855         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 856                 *error_ppm = 0;
 857
 858                 return true;
 859         }
 860
 861         return *error_ppm + 10 < best_error_ppm;
 862 }
 863
 864 static bool
 865 vlv_find_best_dpll(const intel_limit_t *limit,
 866                    struct intel_crtc_state *crtc_state,
 867                    int target, int refclk, intel_clock_t *match_clock,
 868                    intel_clock_t *best_clock)
 869 {
 870         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 871         struct drm_device *dev = crtc->base.dev;
 872         intel_clock_t clock;
 873         unsigned int bestppm = 1000000;
 874         /* min update 19.2 MHz */
 875         int max_n = min(limit->n.max, refclk / 19200);
 876         bool found = false;
 877
 878         target *= 5; /* fast clock */
 879
 880         memset(best_clock, 0, sizeof(*best_clock));
 881
 882         /* based on hardware requirement, prefer smaller n to precision */
 883         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 884                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 885                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 886                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 887                                 clock.p = clock.p1 * clock.p2;
 888                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 889                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 890                                         unsigned int ppm;
 891
 892                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 893                                                                      refclk * clock.m1);
 894
 895                                         vlv_clock(refclk, &clock);
 896
 897                                         if (!intel_PLL_is_valid(dev, limit,
 898                                                                 &clock))
 899                                                 continue;
 900
 901                                         if (!vlv_PLL_is_optimal(dev, target,
 902                                                                 &clock,
 903                                                                 best_clock,
 904                                                                 bestppm, &ppm))
 905                                                 continue;
 906
 907                                         *best_clock = clock;
 908                                         bestppm = ppm;
 909                                         found = true;
 910                                 }
 911                         }
 912                 }
 913         }
 914
 915         return found;
 916 }
 917
 918 static bool
 919 chv_find_best_dpll(const intel_limit_t *limit,
 920                    struct intel_crtc_state *crtc_state,
 921                    int target, int refclk, intel_clock_t *match_clock,
 922                    intel_clock_t *best_clock)
 923 {
 924         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 925         struct drm_device *dev = crtc->base.dev;
 926         unsigned int best_error_ppm;
 927         intel_clock_t clock;
 928         uint64_t m2;
 929         int found = false;
 930
 931         memset(best_clock, 0, sizeof(*best_clock));
 932         best_error_ppm = 1000000;
 933
 934         /*
 935          * Based on hardware doc, the n always set to 1, and m1 always
 936          * set to 2.  If requires to support 200Mhz refclk, we need to
 937          * revisit this because n may not 1 anymore.
 938          */
 939         clock.n = 1, clock.m1 = 2;
 940         target *= 5;    /* fast clock */
 941
 942         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 943                 for (clock.p2 = limit->p2.p2_fast;
 944                                 clock.p2 >= limit->p2.p2_slow;
 945                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 946                         unsigned int error_ppm;
 947
 948                         clock.p = clock.p1 * clock.p2;
 949
 950                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 951                                         clock.n) << 22, refclk * clock.m1);
 952
 953                         if (m2 > INT_MAX/clock.m1)
 954                                 continue;
 955
 956                         clock.m2 = m2;
 957
 958                         chv_clock(refclk, &clock);
 959
 960                         if (!intel_PLL_is_valid(dev, limit, &clock))
 961                                 continue;
 962
 963                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 964                                                 best_error_ppm, &error_ppm))
 965                                 continue;
 966
 967                         *best_clock = clock;
 968                         best_error_ppm = error_ppm;
 969                         found = true;
 970                 }
 971         }
 972
 973         return found;
 974 }
 975
 976 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 977                         intel_clock_t *best_clock)
 978 {
 979         int refclk = i9xx_get_refclk(crtc_state, 0);
 980
 981         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 982                                   target_clock, refclk, NULL, best_clock);
 983 }
 984
 985 bool intel_crtc_active(struct drm_crtc *crtc)
 986 {
 987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 988
 989         /* Be paranoid as we can arrive here with only partial
 990          * state retrieved from the hardware during setup.
 991          *
 992          * We can ditch the adjusted_mode.crtc_clock check as soon
 993          * as Haswell has gained clock readout/fastboot support.
 994          *
 995          * We can ditch the crtc->primary->fb check as soon as we can
 996          * properly reconstruct framebuffers.
 997          *
 998          * FIXME: The intel_crtc->active here should be switched to
 999          * crtc->state->active once we have proper CRTC states wired up
1000          * for atomic.
1001          */
1002         return intel_crtc->active && crtc->primary->state->fb &&
1003                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1004 }
1005
1006 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007                                              enum pipe pipe)
1008 {
1009         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
1012         return intel_crtc->config->cpu_transcoder;
1013 }
1014
1015 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016 {
1017         struct drm_i915_private *dev_priv = dev->dev_private;
1018         u32 reg = PIPEDSL(pipe);
1019         u32 line1, line2;
1020         u32 line_mask;
1021
1022         if (IS_GEN2(dev))
1023                 line_mask = DSL_LINEMASK_GEN2;
1024         else
1025                 line_mask = DSL_LINEMASK_GEN3;
1026
1027         line1 = I915_READ(reg) & line_mask;
1028         mdelay(5);
1029         line2 = I915_READ(reg) & line_mask;
1030
1031         return line1 == line2;
1032 }
1033
1034 /*
1035  * intel_wait_for_pipe_off - wait for pipe to turn off
1036  * @crtc: crtc whose pipe to wait for
1037  *
1038  * After disabling a pipe, we can't wait for vblank in the usual way,
1039  * spinning on the vblank interrupt status bit, since we won't actually
1040  * see an interrupt when the pipe is disabled.
1041  *
1042  * On Gen4 and above:
1043  *   wait for the pipe register state bit to turn off
1044  *
1045  * Otherwise:
1046  *   wait for the display line value to settle (it usually
1047  *   ends up stopping at the start of the next frame).
1048  *
1049  */
1050 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1051 {
1052         struct drm_device *dev = crtc->base.dev;
1053         struct drm_i915_private *dev_priv = dev->dev_private;
1054         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1055         enum pipe pipe = crtc->pipe;
1056
1057         if (INTEL_INFO(dev)->gen >= 4) {
1058                 int reg = PIPECONF(cpu_transcoder);
1059
1060                 /* Wait for the Pipe State to go off */
1061                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062                              100))
1063                         WARN(1, "pipe_off wait timed out\n");
1064         } else {
1065                 /* Wait for the display line to settle */
1066                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1067                         WARN(1, "pipe_off wait timed out\n");
1068         }
1069 }
1070
1071 /*
1072  * ibx_digital_port_connected - is the specified port connected?
1073  * @dev_priv: i915 private structure
1074  * @port: the port to test
1075  *
1076  * Returns true if @port is connected, false otherwise.
1077  */
1078 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079                                 struct intel_digital_port *port)
1080 {
1081         u32 bit;
1082
1083         if (HAS_PCH_IBX(dev_priv->dev)) {
1084                 switch (port->port) {
1085                 case PORT_B:
1086                         bit = SDE_PORTB_HOTPLUG;
1087                         break;
1088                 case PORT_C:
1089                         bit = SDE_PORTC_HOTPLUG;
1090                         break;
1091                 case PORT_D:
1092                         bit = SDE_PORTD_HOTPLUG;
1093                         break;
1094                 default:
1095                         return true;
1096                 }
1097         } else {
1098                 switch (port->port) {
1099                 case PORT_B:
1100                         bit = SDE_PORTB_HOTPLUG_CPT;
1101                         break;
1102                 case PORT_C:
1103                         bit = SDE_PORTC_HOTPLUG_CPT;
1104                         break;
1105                 case PORT_D:
1106                         bit = SDE_PORTD_HOTPLUG_CPT;
1107                         break;
1108                 default:
1109                         return true;
1110                 }
1111         }
1112
1113         return I915_READ(SDEISR) & bit;
1114 }
1115
1116 static const char *state_string(bool enabled)
1117 {
1118         return enabled ? "on" : "off";
1119 }
1120
1121 /* Only for pre-ILK configs */
1122 void assert_pll(struct drm_i915_private *dev_priv,
1123                 enum pipe pipe, bool state)
1124 {
1125         int reg;
1126         u32 val;
1127         bool cur_state;
1128
1129         reg = DPLL(pipe);
1130         val = I915_READ(reg);
1131         cur_state = !!(val & DPLL_VCO_ENABLE);
1132         I915_STATE_WARN(cur_state != state,
1133              "PLL state assertion failure (expected %s, current %s)\n",
1134              state_string(state), state_string(cur_state));
1135 }
1136
1137 /* XXX: the dsi pll is shared between MIPI DSI ports */
1138 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139 {
1140         u32 val;
1141         bool cur_state;
1142
1143         mutex_lock(&dev_priv->dpio_lock);
1144         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1145         mutex_unlock(&dev_priv->dpio_lock);
1146
1147         cur_state = val & DSI_PLL_VCO_EN;
1148         I915_STATE_WARN(cur_state != state,
1149              "DSI PLL state assertion failure (expected %s, current %s)\n",
1150              state_string(state), state_string(cur_state));
1151 }
1152 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
1155 struct intel_shared_dpll *
1156 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157 {
1158         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
1160         if (crtc->config->shared_dpll < 0)
1161                 return NULL;
1162
1163         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1164 }
1165
1166 /* For ILK+ */
1167 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168                         struct intel_shared_dpll *pll,
1169                         bool state)
1170 {
1171         bool cur_state;
1172         struct intel_dpll_hw_state hw_state;
1173
1174         if (WARN (!pll,
1175                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1176                 return;
1177
1178         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1179         I915_STATE_WARN(cur_state != state,
1180              "%s assertion failure (expected %s, current %s)\n",
1181              pll->name, state_string(state), state_string(cur_state));
1182 }
1183
1184 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185                           enum pipe pipe, bool state)
1186 {
1187         int reg;
1188         u32 val;
1189         bool cur_state;
1190         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191                                                                       pipe);
1192
1193         if (HAS_DDI(dev_priv->dev)) {
1194                 /* DDI does not have a specific FDI_TX register */
1195                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1196                 val = I915_READ(reg);
1197                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1198         } else {
1199                 reg = FDI_TX_CTL(pipe);
1200                 val = I915_READ(reg);
1201                 cur_state = !!(val & FDI_TX_ENABLE);
1202         }
1203         I915_STATE_WARN(cur_state != state,
1204              "FDI TX state assertion failure (expected %s, current %s)\n",
1205              state_string(state), state_string(cur_state));
1206 }
1207 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211                           enum pipe pipe, bool state)
1212 {
1213         int reg;
1214         u32 val;
1215         bool cur_state;
1216
1217         reg = FDI_RX_CTL(pipe);
1218         val = I915_READ(reg);
1219         cur_state = !!(val & FDI_RX_ENABLE);
1220         I915_STATE_WARN(cur_state != state,
1221              "FDI RX state assertion failure (expected %s, current %s)\n",
1222              state_string(state), state_string(cur_state));
1223 }
1224 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228                                       enum pipe pipe)
1229 {
1230         int reg;
1231         u32 val;
1232
1233         /* ILK FDI PLL is always enabled */
1234         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1235                 return;
1236
1237         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1238         if (HAS_DDI(dev_priv->dev))
1239                 return;
1240
1241         reg = FDI_TX_CTL(pipe);
1242         val = I915_READ(reg);
1243         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1244 }
1245
1246 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247                        enum pipe pipe, bool state)
1248 {
1249         int reg;
1250         u32 val;
1251         bool cur_state;
1252
1253         reg = FDI_RX_CTL(pipe);
1254         val = I915_READ(reg);
1255         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1256         I915_STATE_WARN(cur_state != state,
1257              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258              state_string(state), state_string(cur_state));
1259 }
1260
1261 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262                            enum pipe pipe)
1263 {
1264         struct drm_device *dev = dev_priv->dev;
1265         int pp_reg;
1266         u32 val;
1267         enum pipe panel_pipe = PIPE_A;
1268         bool locked = true;
1269
1270         if (WARN_ON(HAS_DDI(dev)))
1271                 return;
1272
1273         if (HAS_PCH_SPLIT(dev)) {
1274                 u32 port_sel;
1275
1276                 pp_reg = PCH_PP_CONTROL;
1277                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281                         panel_pipe = PIPE_B;
1282                 /* XXX: else fix for eDP */
1283         } else if (IS_VALLEYVIEW(dev)) {
1284                 /* presumably write lock depends on pipe, not port select */
1285                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286                 panel_pipe = pipe;
1287         } else {
1288                 pp_reg = PP_CONTROL;
1289                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290                         panel_pipe = PIPE_B;
1291         }
1292
1293         val = I915_READ(pp_reg);
1294         if (!(val & PANEL_POWER_ON) ||
1295             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1296                 locked = false;
1297
1298         I915_STATE_WARN(panel_pipe == pipe && locked,
1299              "panel assertion failure, pipe %c regs locked\n",
1300              pipe_name(pipe));
1301 }
1302
1303 static void assert_cursor(struct drm_i915_private *dev_priv,
1304                           enum pipe pipe, bool state)
1305 {
1306         struct drm_device *dev = dev_priv->dev;
1307         bool cur_state;
1308
1309         if (IS_845G(dev) || IS_I865G(dev))
1310                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1311         else
1312                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1313
1314         I915_STATE_WARN(cur_state != state,
1315              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316              pipe_name(pipe), state_string(state), state_string(cur_state));
1317 }
1318 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
1321 void assert_pipe(struct drm_i915_private *dev_priv,
1322                  enum pipe pipe, bool state)
1323 {
1324         int reg;
1325         u32 val;
1326         bool cur_state;
1327         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328                                                                       pipe);
1329
1330         /* if we need the pipe quirk it must be always on */
1331         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1333                 state = true;
1334
1335         if (!intel_display_power_is_enabled(dev_priv,
1336                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1337                 cur_state = false;
1338         } else {
1339                 reg = PIPECONF(cpu_transcoder);
1340                 val = I915_READ(reg);
1341                 cur_state = !!(val & PIPECONF_ENABLE);
1342         }
1343
1344         I915_STATE_WARN(cur_state != state,
1345              "pipe %c assertion failure (expected %s, current %s)\n",
1346              pipe_name(pipe), state_string(state), state_string(cur_state));
1347 }
1348
1349 static void assert_plane(struct drm_i915_private *dev_priv,
1350                          enum plane plane, bool state)
1351 {
1352         int reg;
1353         u32 val;
1354         bool cur_state;
1355
1356         reg = DSPCNTR(plane);
1357         val = I915_READ(reg);
1358         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1359         I915_STATE_WARN(cur_state != state,
1360              "plane %c assertion failure (expected %s, current %s)\n",
1361              plane_name(plane), state_string(state), state_string(cur_state));
1362 }
1363
1364 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
1367 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368                                    enum pipe pipe)
1369 {
1370         struct drm_device *dev = dev_priv->dev;
1371         int reg, i;
1372         u32 val;
1373         int cur_pipe;
1374
1375         /* Primary planes are fixed to pipes on gen4+ */
1376         if (INTEL_INFO(dev)->gen >= 4) {
1377                 reg = DSPCNTR(pipe);
1378                 val = I915_READ(reg);
1379                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1380                      "plane %c assertion failure, should be disabled but not\n",
1381                      plane_name(pipe));
1382                 return;
1383         }
1384
1385         /* Need to check both planes against the pipe */
1386         for_each_pipe(dev_priv, i) {
1387                 reg = DSPCNTR(i);
1388                 val = I915_READ(reg);
1389                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390                         DISPPLANE_SEL_PIPE_SHIFT;
1391                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1392                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393                      plane_name(i), pipe_name(pipe));
1394         }
1395 }
1396
1397 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398                                     enum pipe pipe)
1399 {
1400         struct drm_device *dev = dev_priv->dev;
1401         int reg, sprite;
1402         u32 val;
1403
1404         if (INTEL_INFO(dev)->gen >= 9) {
1405                 for_each_sprite(dev_priv, pipe, sprite) {
1406                         val = I915_READ(PLANE_CTL(pipe, sprite));
1407                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1408                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409                              sprite, pipe_name(pipe));
1410                 }
1411         } else if (IS_VALLEYVIEW(dev)) {
1412                 for_each_sprite(dev_priv, pipe, sprite) {
1413                         reg = SPCNTR(pipe, sprite);
1414                         val = I915_READ(reg);
1415                         I915_STATE_WARN(val & SP_ENABLE,
1416                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417                              sprite_name(pipe, sprite), pipe_name(pipe));
1418                 }
1419         } else if (INTEL_INFO(dev)->gen >= 7) {
1420                 reg = SPRCTL(pipe);
1421                 val = I915_READ(reg);
1422                 I915_STATE_WARN(val & SPRITE_ENABLE,
1423                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1424                      plane_name(pipe), pipe_name(pipe));
1425         } else if (INTEL_INFO(dev)->gen >= 5) {
1426                 reg = DVSCNTR(pipe);
1427                 val = I915_READ(reg);
1428                 I915_STATE_WARN(val & DVS_ENABLE,
1429                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1430                      plane_name(pipe), pipe_name(pipe));
1431         }
1432 }
1433
1434 static void assert_vblank_disabled(struct drm_crtc *crtc)
1435 {
1436         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1437                 drm_crtc_vblank_put(crtc);
1438 }
1439
1440 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1441 {
1442         u32 val;
1443         bool enabled;
1444
1445         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1446
1447         val = I915_READ(PCH_DREF_CONTROL);
1448         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449                             DREF_SUPERSPREAD_SOURCE_MASK));
1450         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1451 }
1452
1453 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454                                            enum pipe pipe)
1455 {
1456         int reg;
1457         u32 val;
1458         bool enabled;
1459
1460         reg = PCH_TRANSCONF(pipe);
1461         val = I915_READ(reg);
1462         enabled = !!(val & TRANS_ENABLE);
1463         I915_STATE_WARN(enabled,
1464              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465              pipe_name(pipe));
1466 }
1467
1468 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469                             enum pipe pipe, u32 port_sel, u32 val)
1470 {
1471         if ((val & DP_PORT_EN) == 0)
1472                 return false;
1473
1474         if (HAS_PCH_CPT(dev_priv->dev)) {
1475                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478                         return false;
1479         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481                         return false;
1482         } else {
1483                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484                         return false;
1485         }
1486         return true;
1487 }
1488
1489 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490                               enum pipe pipe, u32 val)
1491 {
1492         if ((val & SDVO_ENABLE) == 0)
1493                 return false;
1494
1495         if (HAS_PCH_CPT(dev_priv->dev)) {
1496                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1497                         return false;
1498         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500                         return false;
1501         } else {
1502                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1503                         return false;
1504         }
1505         return true;
1506 }
1507
1508 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509                               enum pipe pipe, u32 val)
1510 {
1511         if ((val & LVDS_PORT_EN) == 0)
1512                 return false;
1513
1514         if (HAS_PCH_CPT(dev_priv->dev)) {
1515                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516                         return false;
1517         } else {
1518                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519                         return false;
1520         }
1521         return true;
1522 }
1523
1524 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525                               enum pipe pipe, u32 val)
1526 {
1527         if ((val & ADPA_DAC_ENABLE) == 0)
1528                 return false;
1529         if (HAS_PCH_CPT(dev_priv->dev)) {
1530                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531                         return false;
1532         } else {
1533                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534                         return false;
1535         }
1536         return true;
1537 }
1538
1539 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1540                                    enum pipe pipe, int reg, u32 port_sel)
1541 {
1542         u32 val = I915_READ(reg);
1543         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1544              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1545              reg, pipe_name(pipe));
1546
1547         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1548              && (val & DP_PIPEB_SELECT),
1549              "IBX PCH dp port still using transcoder B\n");
1550 }
1551
1552 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553                                      enum pipe pipe, int reg)
1554 {
1555         u32 val = I915_READ(reg);
1556         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1557              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1558              reg, pipe_name(pipe));
1559
1560         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1561              && (val & SDVO_PIPE_B_SELECT),
1562              "IBX PCH hdmi port still using transcoder B\n");
1563 }
1564
1565 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566                                       enum pipe pipe)
1567 {
1568         int reg;
1569         u32 val;
1570
1571         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1574
1575         reg = PCH_ADPA;
1576         val = I915_READ(reg);
1577         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1578              "PCH VGA enabled on transcoder %c, should be disabled\n",
1579              pipe_name(pipe));
1580
1581         reg = PCH_LVDS;
1582         val = I915_READ(reg);
1583         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1584              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1585              pipe_name(pipe));
1586
1587         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1590 }
1591
1592 static void intel_init_dpio(struct drm_device *dev)
1593 {
1594         struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596         if (!IS_VALLEYVIEW(dev))
1597                 return;
1598
1599         /*
1600          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601          * CHV x1 PHY (DP/HDMI D)
1602          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603          */
1604         if (IS_CHERRYVIEW(dev)) {
1605                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607         } else {
1608                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609         }
1610 }
1611
1612 static void vlv_enable_pll(struct intel_crtc *crtc,
1613                            const struct intel_crtc_state *pipe_config)
1614 {
1615         struct drm_device *dev = crtc->base.dev;
1616         struct drm_i915_private *dev_priv = dev->dev_private;
1617         int reg = DPLL(crtc->pipe);
1618         u32 dpll = pipe_config->dpll_hw_state.dpll;
1619
1620         assert_pipe_disabled(dev_priv, crtc->pipe);
1621
1622         /* No really, not for ILK+ */
1623         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625         /* PLL is protected by panel, make sure we can write it */
1626         if (IS_MOBILE(dev_priv->dev))
1627                 assert_panel_unlocked(dev_priv, crtc->pipe);
1628
1629         I915_WRITE(reg, dpll);
1630         POSTING_READ(reg);
1631         udelay(150);
1632
1633         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
1636         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1637         POSTING_READ(DPLL_MD(crtc->pipe));
1638
1639         /* We do this three times for luck */
1640         I915_WRITE(reg, dpll);
1641         POSTING_READ(reg);
1642         udelay(150); /* wait for warmup */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649 }
1650
1651 static void chv_enable_pll(struct intel_crtc *crtc,
1652                            const struct intel_crtc_state *pipe_config)
1653 {
1654         struct drm_device *dev = crtc->base.dev;
1655         struct drm_i915_private *dev_priv = dev->dev_private;
1656         int pipe = crtc->pipe;
1657         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1658         u32 tmp;
1659
1660         assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
1664         mutex_lock(&dev_priv->dpio_lock);
1665
1666         /* Enable back the 10bit clock to display controller */
1667         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668         tmp |= DPIO_DCLKP_EN;
1669         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
1671         /*
1672          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1673          */
1674         udelay(1);
1675
1676         /* Enable PLL */
1677         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1678
1679         /* Check PLL is locked */
1680         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1681                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1682
1683         /* not sure when this should be written */
1684         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1685         POSTING_READ(DPLL_MD(pipe));
1686
1687         mutex_unlock(&dev_priv->dpio_lock);
1688 }
1689
1690 static int intel_num_dvo_pipes(struct drm_device *dev)
1691 {
1692         struct intel_crtc *crtc;
1693         int count = 0;
1694
1695         for_each_intel_crtc(dev, crtc)
1696                 count += crtc->active &&
1697                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1698
1699         return count;
1700 }
1701
1702 static void i9xx_enable_pll(struct intel_crtc *crtc)
1703 {
1704         struct drm_device *dev = crtc->base.dev;
1705         struct drm_i915_private *dev_priv = dev->dev_private;
1706         int reg = DPLL(crtc->pipe);
1707         u32 dpll = crtc->config->dpll_hw_state.dpll;
1708
1709         assert_pipe_disabled(dev_priv, crtc->pipe);
1710
1711         /* No really, not for ILK+ */
1712         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1713
1714         /* PLL is protected by panel, make sure we can write it */
1715         if (IS_MOBILE(dev) && !IS_I830(dev))
1716                 assert_panel_unlocked(dev_priv, crtc->pipe);
1717
1718         /* Enable DVO 2x clock on both PLLs if necessary */
1719         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720                 /*
1721                  * It appears to be important that we don't enable this
1722                  * for the current pipe before otherwise configuring the
1723                  * PLL. No idea how this should be handled if multiple
1724                  * DVO outputs are enabled simultaneosly.
1725                  */
1726                 dpll |= DPLL_DVO_2X_MODE;
1727                 I915_WRITE(DPLL(!crtc->pipe),
1728                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729         }
1730
1731         /* Wait for the clocks to stabilize. */
1732         POSTING_READ(reg);
1733         udelay(150);
1734
1735         if (INTEL_INFO(dev)->gen >= 4) {
1736                 I915_WRITE(DPLL_MD(crtc->pipe),
1737                            crtc->config->dpll_hw_state.dpll_md);
1738         } else {
1739                 /* The pixel multiplier can only be updated once the
1740                  * DPLL is enabled and the clocks are stable.
1741                  *
1742                  * So write it again.
1743                  */
1744                 I915_WRITE(reg, dpll);
1745         }
1746
1747         /* We do this three times for luck */
1748         I915_WRITE(reg, dpll);
1749         POSTING_READ(reg);
1750         udelay(150); /* wait for warmup */
1751         I915_WRITE(reg, dpll);
1752         POSTING_READ(reg);
1753         udelay(150); /* wait for warmup */
1754         I915_WRITE(reg, dpll);
1755         POSTING_READ(reg);
1756         udelay(150); /* wait for warmup */
1757 }
1758
1759 /**
1760  * i9xx_disable_pll - disable a PLL
1761  * @dev_priv: i915 private structure
1762  * @pipe: pipe PLL to disable
1763  *
1764  * Disable the PLL for @pipe, making sure the pipe is off first.
1765  *
1766  * Note!  This is for pre-ILK only.
1767  */
1768 static void i9xx_disable_pll(struct intel_crtc *crtc)
1769 {
1770         struct drm_device *dev = crtc->base.dev;
1771         struct drm_i915_private *dev_priv = dev->dev_private;
1772         enum pipe pipe = crtc->pipe;
1773
1774         /* Disable DVO 2x clock on both PLLs if necessary */
1775         if (IS_I830(dev) &&
1776             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1777             intel_num_dvo_pipes(dev) == 1) {
1778                 I915_WRITE(DPLL(PIPE_B),
1779                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780                 I915_WRITE(DPLL(PIPE_A),
1781                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782         }
1783
1784         /* Don't disable pipe or pipe PLLs if needed */
1785         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1787                 return;
1788
1789         /* Make sure the pipe isn't still relying on us */
1790         assert_pipe_disabled(dev_priv, pipe);
1791
1792         I915_WRITE(DPLL(pipe), 0);
1793         POSTING_READ(DPLL(pipe));
1794 }
1795
1796 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797 {
1798         u32 val = 0;
1799
1800         /* Make sure the pipe isn't still relying on us */
1801         assert_pipe_disabled(dev_priv, pipe);
1802
1803         /*
1804          * Leave integrated clock source and reference clock enabled for pipe B.
1805          * The latter is needed for VGA hotplug / manual detection.
1806          */
1807         if (pipe == PIPE_B)
1808                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1809         I915_WRITE(DPLL(pipe), val);
1810         POSTING_READ(DPLL(pipe));
1811
1812 }
1813
1814 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815 {
1816         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1817         u32 val;
1818
1819         /* Make sure the pipe isn't still relying on us */
1820         assert_pipe_disabled(dev_priv, pipe);
1821
1822         /* Set PLL en = 0 */
1823         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1824         if (pipe != PIPE_A)
1825                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826         I915_WRITE(DPLL(pipe), val);
1827         POSTING_READ(DPLL(pipe));
1828
1829         mutex_lock(&dev_priv->dpio_lock);
1830
1831         /* Disable 10bit clock to display controller */
1832         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833         val &= ~DPIO_DCLKP_EN;
1834         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
1836         /* disable left/right clock distribution */
1837         if (pipe != PIPE_B) {
1838                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841         } else {
1842                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845         }
1846
1847         mutex_unlock(&dev_priv->dpio_lock);
1848 }
1849
1850 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1851                          struct intel_digital_port *dport,
1852                          unsigned int expected_mask)
1853 {
1854         u32 port_mask;
1855         int dpll_reg;
1856
1857         switch (dport->port) {
1858         case PORT_B:
1859                 port_mask = DPLL_PORTB_READY_MASK;
1860                 dpll_reg = DPLL(0);
1861                 break;
1862         case PORT_C:
1863                 port_mask = DPLL_PORTC_READY_MASK;
1864                 dpll_reg = DPLL(0);
1865                 expected_mask <<= 4;
1866                 break;
1867         case PORT_D:
1868                 port_mask = DPLL_PORTD_READY_MASK;
1869                 dpll_reg = DPIO_PHY_STATUS;
1870                 break;
1871         default:
1872                 BUG();
1873         }
1874
1875         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1878 }
1879
1880 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881 {
1882         struct drm_device *dev = crtc->base.dev;
1883         struct drm_i915_private *dev_priv = dev->dev_private;
1884         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
1886         if (WARN_ON(pll == NULL))
1887                 return;
1888
1889         WARN_ON(!pll->config.crtc_mask);
1890         if (pll->active == 0) {
1891                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892                 WARN_ON(pll->on);
1893                 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895                 pll->mode_set(dev_priv, pll);
1896         }
1897 }
1898
1899 /**
1900  * intel_enable_shared_dpll - enable PCH PLL
1901  * @dev_priv: i915 private structure
1902  * @pipe: pipe PLL to enable
1903  *
1904  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905  * drives the transcoder clock.
1906  */
1907 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1908 {
1909         struct drm_device *dev = crtc->base.dev;
1910         struct drm_i915_private *dev_priv = dev->dev_private;
1911         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1912
1913         if (WARN_ON(pll == NULL))
1914                 return;
1915
1916         if (WARN_ON(pll->config.crtc_mask == 0))
1917                 return;
1918
1919         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1920                       pll->name, pll->active, pll->on,
1921                       crtc->base.base.id);
1922
1923         if (pll->active++) {
1924                 WARN_ON(!pll->on);
1925                 assert_shared_dpll_enabled(dev_priv, pll);
1926                 return;
1927         }
1928         WARN_ON(pll->on);
1929
1930         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
1932         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1933         pll->enable(dev_priv, pll);
1934         pll->on = true;
1935 }
1936
1937 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1938 {
1939         struct drm_device *dev = crtc->base.dev;
1940         struct drm_i915_private *dev_priv = dev->dev_private;
1941         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1942
1943         /* PCH only available on ILK+ */
1944         BUG_ON(INTEL_INFO(dev)->gen < 5);
1945         if (WARN_ON(pll == NULL))
1946                return;
1947
1948         if (WARN_ON(pll->config.crtc_mask == 0))
1949                 return;
1950
1951         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952                       pll->name, pll->active, pll->on,
1953                       crtc->base.base.id);
1954
1955         if (WARN_ON(pll->active == 0)) {
1956                 assert_shared_dpll_disabled(dev_priv, pll);
1957                 return;
1958         }
1959
1960         assert_shared_dpll_enabled(dev_priv, pll);
1961         WARN_ON(!pll->on);
1962         if (--pll->active)
1963                 return;
1964
1965         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1966         pll->disable(dev_priv, pll);
1967         pll->on = false;
1968
1969         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1970 }
1971
1972 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973                                            enum pipe pipe)
1974 {
1975         struct drm_device *dev = dev_priv->dev;
1976         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978         uint32_t reg, val, pipeconf_val;
1979
1980         /* PCH only available on ILK+ */
1981         BUG_ON(!HAS_PCH_SPLIT(dev));
1982
1983         /* Make sure PCH DPLL is enabled */
1984         assert_shared_dpll_enabled(dev_priv,
1985                                    intel_crtc_to_shared_dpll(intel_crtc));
1986
1987         /* FDI must be feeding us bits for PCH ports */
1988         assert_fdi_tx_enabled(dev_priv, pipe);
1989         assert_fdi_rx_enabled(dev_priv, pipe);
1990
1991         if (HAS_PCH_CPT(dev)) {
1992                 /* Workaround: Set the timing override bit before enabling the
1993                  * pch transcoder. */
1994                 reg = TRANS_CHICKEN2(pipe);
1995                 val = I915_READ(reg);
1996                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997                 I915_WRITE(reg, val);
1998         }
1999
2000         reg = PCH_TRANSCONF(pipe);
2001         val = I915_READ(reg);
2002         pipeconf_val = I915_READ(PIPECONF(pipe));
2003
2004         if (HAS_PCH_IBX(dev_priv->dev)) {
2005                 /*
2006                  * make the BPC in transcoder be consistent with
2007                  * that in pipeconf reg.
2008                  */
2009                 val &= ~PIPECONF_BPC_MASK;
2010                 val |= pipeconf_val & PIPECONF_BPC_MASK;
2011         }
2012
2013         val &= ~TRANS_INTERLACE_MASK;
2014         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2015                 if (HAS_PCH_IBX(dev_priv->dev) &&
2016                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2017                         val |= TRANS_LEGACY_INTERLACED_ILK;
2018                 else
2019                         val |= TRANS_INTERLACED;
2020         else
2021                 val |= TRANS_PROGRESSIVE;
2022
2023         I915_WRITE(reg, val | TRANS_ENABLE);
2024         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2025                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2026 }
2027
2028 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2029                                       enum transcoder cpu_transcoder)
2030 {
2031         u32 val, pipeconf_val;
2032
2033         /* PCH only available on ILK+ */
2034         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2035
2036         /* FDI must be feeding us bits for PCH ports */
2037         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2038         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2039
2040         /* Workaround: set timing override bit. */
2041         val = I915_READ(_TRANSA_CHICKEN2);
2042         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2043         I915_WRITE(_TRANSA_CHICKEN2, val);
2044
2045         val = TRANS_ENABLE;
2046         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2047
2048         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049             PIPECONF_INTERLACED_ILK)
2050                 val |= TRANS_INTERLACED;
2051         else
2052                 val |= TRANS_PROGRESSIVE;
2053
2054         I915_WRITE(LPT_TRANSCONF, val);
2055         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2056                 DRM_ERROR("Failed to enable PCH transcoder\n");
2057 }
2058
2059 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060                                             enum pipe pipe)
2061 {
2062         struct drm_device *dev = dev_priv->dev;
2063         uint32_t reg, val;
2064
2065         /* FDI relies on the transcoder */
2066         assert_fdi_tx_disabled(dev_priv, pipe);
2067         assert_fdi_rx_disabled(dev_priv, pipe);
2068
2069         /* Ports must be off as well */
2070         assert_pch_ports_disabled(dev_priv, pipe);
2071
2072         reg = PCH_TRANSCONF(pipe);
2073         val = I915_READ(reg);
2074         val &= ~TRANS_ENABLE;
2075         I915_WRITE(reg, val);
2076         /* wait for PCH transcoder off, transcoder state */
2077         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2078                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2079
2080         if (!HAS_PCH_IBX(dev)) {
2081                 /* Workaround: Clear the timing override chicken bit again. */
2082                 reg = TRANS_CHICKEN2(pipe);
2083                 val = I915_READ(reg);
2084                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085                 I915_WRITE(reg, val);
2086         }
2087 }
2088
2089 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2090 {
2091         u32 val;
2092
2093         val = I915_READ(LPT_TRANSCONF);
2094         val &= ~TRANS_ENABLE;
2095         I915_WRITE(LPT_TRANSCONF, val);
2096         /* wait for PCH transcoder off, transcoder state */
2097         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2098                 DRM_ERROR("Failed to disable PCH transcoder\n");
2099
2100         /* Workaround: clear timing override bit. */
2101         val = I915_READ(_TRANSA_CHICKEN2);
2102         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2103         I915_WRITE(_TRANSA_CHICKEN2, val);
2104 }
2105
2106 /**
2107  * intel_enable_pipe - enable a pipe, asserting requirements
2108  * @crtc: crtc responsible for the pipe
2109  *
2110  * Enable @crtc's pipe, making sure that various hardware specific requirements
2111  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2112  */
2113 static void intel_enable_pipe(struct intel_crtc *crtc)
2114 {
2115         struct drm_device *dev = crtc->base.dev;
2116         struct drm_i915_private *dev_priv = dev->dev_private;
2117         enum pipe pipe = crtc->pipe;
2118         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119                                                                       pipe);
2120         enum pipe pch_transcoder;
2121         int reg;
2122         u32 val;
2123
2124         assert_planes_disabled(dev_priv, pipe);
2125         assert_cursor_disabled(dev_priv, pipe);
2126         assert_sprites_disabled(dev_priv, pipe);
2127
2128         if (HAS_PCH_LPT(dev_priv->dev))
2129                 pch_transcoder = TRANSCODER_A;
2130         else
2131                 pch_transcoder = pipe;
2132
2133         /*
2134          * A pipe without a PLL won't actually be able to drive bits from
2135          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2136          * need the check.
2137          */
2138         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2139                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2140                         assert_dsi_pll_enabled(dev_priv);
2141                 else
2142                         assert_pll_enabled(dev_priv, pipe);
2143         else {
2144                 if (crtc->config->has_pch_encoder) {
2145                         /* if driving the PCH, we need FDI enabled */
2146                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2147                         assert_fdi_tx_pll_enabled(dev_priv,
2148                                                   (enum pipe) cpu_transcoder);
2149                 }
2150                 /* FIXME: assert CPU port conditions for SNB+ */
2151         }
2152
2153         reg = PIPECONF(cpu_transcoder);
2154         val = I915_READ(reg);
2155         if (val & PIPECONF_ENABLE) {
2156                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2158                 return;
2159         }
2160
2161         I915_WRITE(reg, val | PIPECONF_ENABLE);
2162         POSTING_READ(reg);
2163 }
2164
2165 /**
2166  * intel_disable_pipe - disable a pipe, asserting requirements
2167  * @crtc: crtc whose pipes is to be disabled
2168  *
2169  * Disable the pipe of @crtc, making sure that various hardware
2170  * specific requirements are met, if applicable, e.g. plane
2171  * disabled, panel fitter off, etc.
2172  *
2173  * Will wait until the pipe has shut down before returning.
2174  */
2175 static void intel_disable_pipe(struct intel_crtc *crtc)
2176 {
2177         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2178         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2179         enum pipe pipe = crtc->pipe;
2180         int reg;
2181         u32 val;
2182
2183         /*
2184          * Make sure planes won't keep trying to pump pixels to us,
2185          * or we might hang the display.
2186          */
2187         assert_planes_disabled(dev_priv, pipe);
2188         assert_cursor_disabled(dev_priv, pipe);
2189         assert_sprites_disabled(dev_priv, pipe);
2190
2191         reg = PIPECONF(cpu_transcoder);
2192         val = I915_READ(reg);
2193         if ((val & PIPECONF_ENABLE) == 0)
2194                 return;
2195
2196         /*
2197          * Double wide has implications for planes
2198          * so best keep it disabled when not needed.
2199          */
2200         if (crtc->config->double_wide)
2201                 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203         /* Don't disable pipe or pipe PLLs if needed */
2204         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2206                 val &= ~PIPECONF_ENABLE;
2207
2208         I915_WRITE(reg, val);
2209         if ((val & PIPECONF_ENABLE) == 0)
2210                 intel_wait_for_pipe_off(crtc);
2211 }
2212
2213 /*
2214  * Plane regs are double buffered, going from enabled->disabled needs a
2215  * trigger in order to latch.  The display address reg provides this.
2216  */
2217 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2218                                enum plane plane)
2219 {
2220         struct drm_device *dev = dev_priv->dev;
2221         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2222
2223         I915_WRITE(reg, I915_READ(reg));
2224         POSTING_READ(reg);
2225 }
2226
2227 /**
2228  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2229  * @plane:  plane to be enabled
2230  * @crtc: crtc for the plane
2231  *
2232  * Enable @plane on @crtc, making sure that the pipe is running first.
2233  */
2234 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2235                                           struct drm_crtc *crtc)
2236 {
2237         struct drm_device *dev = plane->dev;
2238         struct drm_i915_private *dev_priv = dev->dev_private;
2239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2240
2241         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2242         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2243         to_intel_plane_state(plane->state)->visible = true;
2244
2245         dev_priv->display.update_primary_plane(crtc, plane->fb,
2246                                                crtc->x, crtc->y);
2247 }
2248
2249 static bool need_vtd_wa(struct drm_device *dev)
2250 {
2251 #ifdef CONFIG_INTEL_IOMMU
2252         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2253                 return true;
2254 #endif
2255         return false;
2256 }
2257
2258 unsigned int
2259 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2260                   uint64_t fb_format_modifier)
2261 {
2262         unsigned int tile_height;
2263         uint32_t pixel_bytes;
2264
2265         switch (fb_format_modifier) {
2266         case DRM_FORMAT_MOD_NONE:
2267                 tile_height = 1;
2268                 break;
2269         case I915_FORMAT_MOD_X_TILED:
2270                 tile_height = IS_GEN2(dev) ? 16 : 8;
2271                 break;
2272         case I915_FORMAT_MOD_Y_TILED:
2273                 tile_height = 32;
2274                 break;
2275         case I915_FORMAT_MOD_Yf_TILED:
2276                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2277                 switch (pixel_bytes) {
2278                 default:
2279                 case 1:
2280                         tile_height = 64;
2281                         break;
2282                 case 2:
2283                 case 4:
2284                         tile_height = 32;
2285                         break;
2286                 case 8:
2287                         tile_height = 16;
2288                         break;
2289                 case 16:
2290                         WARN_ONCE(1,
2291                                   "128-bit pixels are not supported for display!");
2292                         tile_height = 16;
2293                         break;
2294                 }
2295                 break;
2296         default:
2297                 MISSING_CASE(fb_format_modifier);
2298                 tile_height = 1;
2299                 break;
2300         }
2301
2302         return tile_height;
2303 }
2304
2305 unsigned int
2306 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2307                       uint32_t pixel_format, uint64_t fb_format_modifier)
2308 {
2309         return ALIGN(height, intel_tile_height(dev, pixel_format,
2310                                                fb_format_modifier));
2311 }
2312
2313 static int
2314 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2315                         const struct drm_plane_state *plane_state)
2316 {
2317         struct intel_rotation_info *info = &view->rotation_info;
2318
2319         *view = i915_ggtt_view_normal;
2320
2321         if (!plane_state)
2322                 return 0;
2323
2324         if (!intel_rotation_90_or_270(plane_state->rotation))
2325                 return 0;
2326
2327         *view = i915_ggtt_view_rotated;
2328
2329         info->height = fb->height;
2330         info->pixel_format = fb->pixel_format;
2331         info->pitch = fb->pitches[0];
2332         info->fb_modifier = fb->modifier[0];
2333
2334         return 0;
2335 }
2336
2337 int
2338 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2339                            struct drm_framebuffer *fb,
2340                            const struct drm_plane_state *plane_state,
2341                            struct intel_engine_cs *pipelined)
2342 {
2343         struct drm_device *dev = fb->dev;
2344         struct drm_i915_private *dev_priv = dev->dev_private;
2345         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2346         struct i915_ggtt_view view;
2347         u32 alignment;
2348         int ret;
2349
2350         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2351
2352         switch (fb->modifier[0]) {
2353         case DRM_FORMAT_MOD_NONE:
2354                 if (INTEL_INFO(dev)->gen >= 9)
2355                         alignment = 256 * 1024;
2356                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2357                         alignment = 128 * 1024;
2358                 else if (INTEL_INFO(dev)->gen >= 4)
2359                         alignment = 4 * 1024;
2360                 else
2361                         alignment = 64 * 1024;
2362                 break;
2363         case I915_FORMAT_MOD_X_TILED:
2364                 if (INTEL_INFO(dev)->gen >= 9)
2365                         alignment = 256 * 1024;
2366                 else {
2367                         /* pin() will align the object as required by fence */
2368                         alignment = 0;
2369                 }
2370                 break;
2371         case I915_FORMAT_MOD_Y_TILED:
2372         case I915_FORMAT_MOD_Yf_TILED:
2373                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2374                           "Y tiling bo slipped through, driver bug!\n"))
2375                         return -EINVAL;
2376                 alignment = 1 * 1024 * 1024;
2377                 break;
2378         default:
2379                 MISSING_CASE(fb->modifier[0]);
2380                 return -EINVAL;
2381         }
2382
2383         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2384         if (ret)
2385                 return ret;
2386
2387         /* Note that the w/a also requires 64 PTE of padding following the
2388          * bo. We currently fill all unused PTE with the shadow page and so
2389          * we should always have valid PTE following the scanout preventing
2390          * the VT-d warning.
2391          */
2392         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2393                 alignment = 256 * 1024;
2394
2395         /*
2396          * Global gtt pte registers are special registers which actually forward
2397          * writes to a chunk of system memory. Which means that there is no risk
2398          * that the register values disappear as soon as we call
2399          * intel_runtime_pm_put(), so it is correct to wrap only the
2400          * pin/unpin/fence and not more.
2401          */
2402         intel_runtime_pm_get(dev_priv);
2403
2404         dev_priv->mm.interruptible = false;
2405         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2406                                                    &view);
2407         if (ret)
2408                 goto err_interruptible;
2409
2410         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2411          * fence, whereas 965+ only requires a fence if using
2412          * framebuffer compression.  For simplicity, we always install
2413          * a fence as the cost is not that onerous.
2414          */
2415         ret = i915_gem_object_get_fence(obj);
2416         if (ret)
2417                 goto err_unpin;
2418
2419         i915_gem_object_pin_fence(obj);
2420
2421         dev_priv->mm.interruptible = true;
2422         intel_runtime_pm_put(dev_priv);
2423         return 0;
2424
2425 err_unpin:
2426         i915_gem_object_unpin_from_display_plane(obj, &view);
2427 err_interruptible:
2428         dev_priv->mm.interruptible = true;
2429         intel_runtime_pm_put(dev_priv);
2430         return ret;
2431 }
2432
2433 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2434                                const struct drm_plane_state *plane_state)
2435 {
2436         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2437         struct i915_ggtt_view view;
2438         int ret;
2439
2440         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2441
2442         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2443         WARN_ONCE(ret, "Couldn't get view from plane state!");
2444
2445         i915_gem_object_unpin_fence(obj);
2446         i915_gem_object_unpin_from_display_plane(obj, &view);
2447 }
2448
2449 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2450  * is assumed to be a power-of-two. */
2451 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2452                                              unsigned int tiling_mode,
2453                                              unsigned int cpp,
2454                                              unsigned int pitch)
2455 {
2456         if (tiling_mode != I915_TILING_NONE) {
2457                 unsigned int tile_rows, tiles;
2458
2459                 tile_rows = *y / 8;
2460                 *y %= 8;
2461
2462                 tiles = *x / (512/cpp);
2463                 *x %= 512/cpp;
2464
2465                 return tile_rows * pitch * 8 + tiles * 4096;
2466         } else {
2467                 unsigned int offset;
2468
2469                 offset = *y * pitch + *x * cpp;
2470                 *y = 0;
2471                 *x = (offset & 4095) / cpp;
2472                 return offset & -4096;
2473         }
2474 }
2475
2476 static int i9xx_format_to_fourcc(int format)
2477 {
2478         switch (format) {
2479         case DISPPLANE_8BPP:
2480                 return DRM_FORMAT_C8;
2481         case DISPPLANE_BGRX555:
2482                 return DRM_FORMAT_XRGB1555;
2483         case DISPPLANE_BGRX565:
2484                 return DRM_FORMAT_RGB565;
2485         default:
2486         case DISPPLANE_BGRX888:
2487                 return DRM_FORMAT_XRGB8888;
2488         case DISPPLANE_RGBX888:
2489                 return DRM_FORMAT_XBGR8888;
2490         case DISPPLANE_BGRX101010:
2491                 return DRM_FORMAT_XRGB2101010;
2492         case DISPPLANE_RGBX101010:
2493                 return DRM_FORMAT_XBGR2101010;
2494         }
2495 }
2496
2497 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2498 {
2499         switch (format) {
2500         case PLANE_CTL_FORMAT_RGB_565:
2501                 return DRM_FORMAT_RGB565;
2502         default:
2503         case PLANE_CTL_FORMAT_XRGB_8888:
2504                 if (rgb_order) {
2505                         if (alpha)
2506                                 return DRM_FORMAT_ABGR8888;
2507                         else
2508                                 return DRM_FORMAT_XBGR8888;
2509                 } else {
2510                         if (alpha)
2511                                 return DRM_FORMAT_ARGB8888;
2512                         else
2513                                 return DRM_FORMAT_XRGB8888;
2514                 }
2515         case PLANE_CTL_FORMAT_XRGB_2101010:
2516                 if (rgb_order)
2517                         return DRM_FORMAT_XBGR2101010;
2518                 else
2519                         return DRM_FORMAT_XRGB2101010;
2520         }
2521 }
2522
2523 static bool
2524 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2525                               struct intel_initial_plane_config *plane_config)
2526 {
2527         struct drm_device *dev = crtc->base.dev;
2528         struct drm_i915_gem_object *obj = NULL;
2529         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2530         struct drm_framebuffer *fb = &plane_config->fb->base;
2531         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2532         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2533                                     PAGE_SIZE);
2534
2535         size_aligned -= base_aligned;
2536
2537         if (plane_config->size == 0)
2538                 return false;
2539
2540         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2541                                                              base_aligned,
2542                                                              base_aligned,
2543                                                              size_aligned);
2544         if (!obj)
2545                 return false;
2546
2547         obj->tiling_mode = plane_config->tiling;
2548         if (obj->tiling_mode == I915_TILING_X)
2549                 obj->stride = fb->pitches[0];
2550
2551         mode_cmd.pixel_format = fb->pixel_format;
2552         mode_cmd.width = fb->width;
2553         mode_cmd.height = fb->height;
2554         mode_cmd.pitches[0] = fb->pitches[0];
2555         mode_cmd.modifier[0] = fb->modifier[0];
2556         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2557
2558         mutex_lock(&dev->struct_mutex);
2559         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2560                                    &mode_cmd, obj)) {
2561                 DRM_DEBUG_KMS("intel fb init failed\n");
2562                 goto out_unref_obj;
2563         }
2564         mutex_unlock(&dev->struct_mutex);
2565
2566         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2567         return true;
2568
2569 out_unref_obj:
2570         drm_gem_object_unreference(&obj->base);
2571         mutex_unlock(&dev->struct_mutex);
2572         return false;
2573 }
2574
2575 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2576 static void
2577 update_state_fb(struct drm_plane *plane)
2578 {
2579         if (plane->fb == plane->state->fb)
2580                 return;
2581
2582         if (plane->state->fb)
2583                 drm_framebuffer_unreference(plane->state->fb);
2584         plane->state->fb = plane->fb;
2585         if (plane->state->fb)
2586                 drm_framebuffer_reference(plane->state->fb);
2587 }
2588
2589 static void
2590 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591                              struct intel_initial_plane_config *plane_config)
2592 {
2593         struct drm_device *dev = intel_crtc->base.dev;
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         struct drm_crtc *c;
2596         struct intel_crtc *i;
2597         struct drm_i915_gem_object *obj;
2598         struct drm_plane *primary = intel_crtc->base.primary;
2599         struct drm_framebuffer *fb;
2600
2601         if (!plane_config->fb)
2602                 return;
2603
2604         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2605                 fb = &plane_config->fb->base;
2606                 goto valid_fb;
2607         }
2608
2609         kfree(plane_config->fb);
2610
2611         /*
2612          * Failed to alloc the obj, check to see if we should share
2613          * an fb with another CRTC instead
2614          */
2615         for_each_crtc(dev, c) {
2616                 i = to_intel_crtc(c);
2617
2618                 if (c == &intel_crtc->base)
2619                         continue;
2620
2621                 if (!i->active)
2622                         continue;
2623
2624                 fb = c->primary->fb;
2625                 if (!fb)
2626                         continue;
2627
2628                 obj = intel_fb_obj(fb);
2629                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2630                         drm_framebuffer_reference(fb);
2631                         goto valid_fb;
2632                 }
2633         }
2634
2635         return;
2636
2637 valid_fb:
2638         obj = intel_fb_obj(fb);
2639         if (obj->tiling_mode != I915_TILING_NONE)
2640                 dev_priv->preserve_bios_swizzle = true;
2641
2642         primary->fb = fb;
2643         primary->state->crtc = &intel_crtc->base;
2644         primary->crtc = &intel_crtc->base;
2645         update_state_fb(primary);
2646         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2647 }
2648
2649 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2650                                       struct drm_framebuffer *fb,
2651                                       int x, int y)
2652 {
2653         struct drm_device *dev = crtc->dev;
2654         struct drm_i915_private *dev_priv = dev->dev_private;
2655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2656         struct drm_plane *primary = crtc->primary;
2657         bool visible = to_intel_plane_state(primary->state)->visible;
2658         struct drm_i915_gem_object *obj;
2659         int plane = intel_crtc->plane;
2660         unsigned long linear_offset;
2661         u32 dspcntr;
2662         u32 reg = DSPCNTR(plane);
2663         int pixel_size;
2664
2665         if (!visible || !fb) {
2666                 I915_WRITE(reg, 0);
2667                 if (INTEL_INFO(dev)->gen >= 4)
2668                         I915_WRITE(DSPSURF(plane), 0);
2669                 else
2670                         I915_WRITE(DSPADDR(plane), 0);
2671                 POSTING_READ(reg);
2672                 return;
2673         }
2674
2675         obj = intel_fb_obj(fb);
2676         if (WARN_ON(obj == NULL))
2677                 return;
2678
2679         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2680
2681         dspcntr = DISPPLANE_GAMMA_ENABLE;
2682
2683         dspcntr |= DISPLAY_PLANE_ENABLE;
2684
2685         if (INTEL_INFO(dev)->gen < 4) {
2686                 if (intel_crtc->pipe == PIPE_B)
2687                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2688
2689                 /* pipesrc and dspsize control the size that is scaled from,
2690                  * which should always be the user's requested size.
2691                  */
2692                 I915_WRITE(DSPSIZE(plane),
2693                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694                            (intel_crtc->config->pipe_src_w - 1));
2695                 I915_WRITE(DSPPOS(plane), 0);
2696         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2697                 I915_WRITE(PRIMSIZE(plane),
2698                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2699                            (intel_crtc->config->pipe_src_w - 1));
2700                 I915_WRITE(PRIMPOS(plane), 0);
2701                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2702         }
2703
2704         switch (fb->pixel_format) {
2705         case DRM_FORMAT_C8:
2706                 dspcntr |= DISPPLANE_8BPP;
2707                 break;
2708         case DRM_FORMAT_XRGB1555:
2709                 dspcntr |= DISPPLANE_BGRX555;
2710                 break;
2711         case DRM_FORMAT_RGB565:
2712                 dspcntr |= DISPPLANE_BGRX565;
2713                 break;
2714         case DRM_FORMAT_XRGB8888:
2715                 dspcntr |= DISPPLANE_BGRX888;
2716                 break;
2717         case DRM_FORMAT_XBGR8888:
2718                 dspcntr |= DISPPLANE_RGBX888;
2719                 break;
2720         case DRM_FORMAT_XRGB2101010:
2721                 dspcntr |= DISPPLANE_BGRX101010;
2722                 break;
2723         case DRM_FORMAT_XBGR2101010:
2724                 dspcntr |= DISPPLANE_RGBX101010;
2725                 break;
2726         default:
2727                 BUG();
2728         }
2729
2730         if (INTEL_INFO(dev)->gen >= 4 &&
2731             obj->tiling_mode != I915_TILING_NONE)
2732                 dspcntr |= DISPPLANE_TILED;
2733
2734         if (IS_G4X(dev))
2735                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2736
2737         linear_offset = y * fb->pitches[0] + x * pixel_size;
2738
2739         if (INTEL_INFO(dev)->gen >= 4) {
2740                 intel_crtc->dspaddr_offset =
2741                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2742                                                        pixel_size,
2743                                                        fb->pitches[0]);
2744                 linear_offset -= intel_crtc->dspaddr_offset;
2745         } else {
2746                 intel_crtc->dspaddr_offset = linear_offset;
2747         }
2748
2749         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2750                 dspcntr |= DISPPLANE_ROTATE_180;
2751
2752                 x += (intel_crtc->config->pipe_src_w - 1);
2753                 y += (intel_crtc->config->pipe_src_h - 1);
2754
2755                 /* Finding the last pixel of the last line of the display
2756                 data and adding to linear_offset*/
2757                 linear_offset +=
2758                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2759                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2760         }
2761
2762         I915_WRITE(reg, dspcntr);
2763
2764         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2765         if (INTEL_INFO(dev)->gen >= 4) {
2766                 I915_WRITE(DSPSURF(plane),
2767                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2768                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2769                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2770         } else
2771                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2772         POSTING_READ(reg);
2773 }
2774
2775 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2776                                           struct drm_framebuffer *fb,
2777                                           int x, int y)
2778 {
2779         struct drm_device *dev = crtc->dev;
2780         struct drm_i915_private *dev_priv = dev->dev_private;
2781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782         struct drm_plane *primary = crtc->primary;
2783         bool visible = to_intel_plane_state(primary->state)->visible;
2784         struct drm_i915_gem_object *obj;
2785         int plane = intel_crtc->plane;
2786         unsigned long linear_offset;
2787         u32 dspcntr;
2788         u32 reg = DSPCNTR(plane);
2789         int pixel_size;
2790
2791         if (!visible || !fb) {
2792                 I915_WRITE(reg, 0);
2793                 I915_WRITE(DSPSURF(plane), 0);
2794                 POSTING_READ(reg);
2795                 return;
2796         }
2797
2798         obj = intel_fb_obj(fb);
2799         if (WARN_ON(obj == NULL))
2800                 return;
2801
2802         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2803
2804         dspcntr = DISPPLANE_GAMMA_ENABLE;
2805
2806         dspcntr |= DISPLAY_PLANE_ENABLE;
2807
2808         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2809                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2810
2811         switch (fb->pixel_format) {
2812         case DRM_FORMAT_C8:
2813                 dspcntr |= DISPPLANE_8BPP;
2814                 break;
2815         case DRM_FORMAT_RGB565:
2816                 dspcntr |= DISPPLANE_BGRX565;
2817                 break;
2818         case DRM_FORMAT_XRGB8888:
2819                 dspcntr |= DISPPLANE_BGRX888;
2820                 break;
2821         case DRM_FORMAT_XBGR8888:
2822                 dspcntr |= DISPPLANE_RGBX888;
2823                 break;
2824         case DRM_FORMAT_XRGB2101010:
2825                 dspcntr |= DISPPLANE_BGRX101010;
2826                 break;
2827         case DRM_FORMAT_XBGR2101010:
2828                 dspcntr |= DISPPLANE_RGBX101010;
2829                 break;
2830         default:
2831                 BUG();
2832         }
2833
2834         if (obj->tiling_mode != I915_TILING_NONE)
2835                 dspcntr |= DISPPLANE_TILED;
2836
2837         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2838                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2839
2840         linear_offset = y * fb->pitches[0] + x * pixel_size;
2841         intel_crtc->dspaddr_offset =
2842                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2843                                                pixel_size,
2844                                                fb->pitches[0]);
2845         linear_offset -= intel_crtc->dspaddr_offset;
2846         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2847                 dspcntr |= DISPPLANE_ROTATE_180;
2848
2849                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2850                         x += (intel_crtc->config->pipe_src_w - 1);
2851                         y += (intel_crtc->config->pipe_src_h - 1);
2852
2853                         /* Finding the last pixel of the last line of the display
2854                         data and adding to linear_offset*/
2855                         linear_offset +=
2856                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2857                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2858                 }
2859         }
2860
2861         I915_WRITE(reg, dspcntr);
2862
2863         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2864         I915_WRITE(DSPSURF(plane),
2865                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2866         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2867                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2868         } else {
2869                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2870                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2871         }
2872         POSTING_READ(reg);
2873 }
2874
2875 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2876                               uint32_t pixel_format)
2877 {
2878         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2879
2880         /*
2881          * The stride is either expressed as a multiple of 64 bytes
2882          * chunks for linear buffers or in number of tiles for tiled
2883          * buffers.
2884          */
2885         switch (fb_modifier) {
2886         case DRM_FORMAT_MOD_NONE:
2887                 return 64;
2888         case I915_FORMAT_MOD_X_TILED:
2889                 if (INTEL_INFO(dev)->gen == 2)
2890                         return 128;
2891                 return 512;
2892         case I915_FORMAT_MOD_Y_TILED:
2893                 /* No need to check for old gens and Y tiling since this is
2894                  * about the display engine and those will be blocked before
2895                  * we get here.
2896                  */
2897                 return 128;
2898         case I915_FORMAT_MOD_Yf_TILED:
2899                 if (bits_per_pixel == 8)
2900                         return 64;
2901                 else
2902                         return 128;
2903         default:
2904                 MISSING_CASE(fb_modifier);
2905                 return 64;
2906         }
2907 }
2908
2909 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2910                                      struct drm_i915_gem_object *obj)
2911 {
2912         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2913
2914         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2915                 view = &i915_ggtt_view_rotated;
2916
2917         return i915_gem_obj_ggtt_offset_view(obj, view);
2918 }
2919
2920 /*
2921  * This function detaches (aka. unbinds) unused scalers in hardware
2922  */
2923 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2924 {
2925         struct drm_device *dev;
2926         struct drm_i915_private *dev_priv;
2927         struct intel_crtc_scaler_state *scaler_state;
2928         int i;
2929
2930         if (!intel_crtc || !intel_crtc->config)
2931                 return;
2932
2933         dev = intel_crtc->base.dev;
2934         dev_priv = dev->dev_private;
2935         scaler_state = &intel_crtc->config->scaler_state;
2936
2937         /* loop through and disable scalers that aren't in use */
2938         for (i = 0; i < intel_crtc->num_scalers; i++) {
2939                 if (!scaler_state->scalers[i].in_use) {
2940                         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2941                         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2942                         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2943                         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2944                                 intel_crtc->base.base.id, intel_crtc->pipe, i);
2945                 }
2946         }
2947 }
2948
2949 u32 skl_plane_ctl_format(uint32_t pixel_format)
2950 {
2951         switch (pixel_format) {
2952         case DRM_FORMAT_C8:
2953                 return PLANE_CTL_FORMAT_INDEXED;
2954         case DRM_FORMAT_RGB565:
2955                 return PLANE_CTL_FORMAT_RGB_565;
2956         case DRM_FORMAT_XBGR8888:
2957                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2958         case DRM_FORMAT_XRGB8888:
2959                 return PLANE_CTL_FORMAT_XRGB_8888;
2960         /*
2961          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2962          * to be already pre-multiplied. We need to add a knob (or a different
2963          * DRM_FORMAT) for user-space to configure that.
2964          */
2965         case DRM_FORMAT_ABGR8888:
2966                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2967                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2968         case DRM_FORMAT_ARGB8888:
2969                 return PLANE_CTL_FORMAT_XRGB_8888 |
2970                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2971         case DRM_FORMAT_XRGB2101010:
2972                 return PLANE_CTL_FORMAT_XRGB_2101010;
2973         case DRM_FORMAT_XBGR2101010:
2974                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2975         case DRM_FORMAT_YUYV:
2976                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2977         case DRM_FORMAT_YVYU:
2978                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2979         case DRM_FORMAT_UYVY:
2980                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2981         case DRM_FORMAT_VYUY:
2982                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2983         default:
2984                 MISSING_CASE(pixel_format);
2985         }
2986
2987         return 0;
2988 }
2989
2990 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2991 {
2992         switch (fb_modifier) {
2993         case DRM_FORMAT_MOD_NONE:
2994                 break;
2995         case I915_FORMAT_MOD_X_TILED:
2996                 return PLANE_CTL_TILED_X;
2997         case I915_FORMAT_MOD_Y_TILED:
2998                 return PLANE_CTL_TILED_Y;
2999         case I915_FORMAT_MOD_Yf_TILED:
3000                 return PLANE_CTL_TILED_YF;
3001         default:
3002                 MISSING_CASE(fb_modifier);
3003         }
3004
3005         return 0;
3006 }
3007
3008 u32 skl_plane_ctl_rotation(unsigned int rotation)
3009 {
3010         switch (rotation) {
3011         case BIT(DRM_ROTATE_0):
3012                 break;
3013         case BIT(DRM_ROTATE_90):
3014                 return PLANE_CTL_ROTATE_90;
3015         case BIT(DRM_ROTATE_180):
3016                 return PLANE_CTL_ROTATE_180;
3017         case BIT(DRM_ROTATE_270):
3018                 return PLANE_CTL_ROTATE_270;
3019         default:
3020                 MISSING_CASE(rotation);
3021         }
3022
3023         return 0;
3024 }
3025
3026 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3027                                          struct drm_framebuffer *fb,
3028                                          int x, int y)
3029 {
3030         struct drm_device *dev = crtc->dev;
3031         struct drm_i915_private *dev_priv = dev->dev_private;
3032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3033         struct drm_plane *plane = crtc->primary;
3034         bool visible = to_intel_plane_state(plane->state)->visible;
3035         struct drm_i915_gem_object *obj;
3036         int pipe = intel_crtc->pipe;
3037         u32 plane_ctl, stride_div, stride;
3038         u32 tile_height, plane_offset, plane_size;
3039         unsigned int rotation;
3040         int x_offset, y_offset;
3041         unsigned long surf_addr;
3042         struct intel_crtc_state *crtc_state = intel_crtc->config;
3043         struct intel_plane_state *plane_state;
3044         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3045         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3046         int scaler_id = -1;
3047
3048         plane_state = to_intel_plane_state(plane->state);
3049
3050         if (!visible || !fb) {
3051                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3052                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3053                 POSTING_READ(PLANE_CTL(pipe, 0));
3054                 return;
3055         }
3056
3057         plane_ctl = PLANE_CTL_ENABLE |
3058                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3059                     PLANE_CTL_PIPE_CSC_ENABLE;
3060
3061         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3062         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3063         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3064
3065         rotation = plane->state->rotation;
3066         plane_ctl |= skl_plane_ctl_rotation(rotation);
3067
3068         obj = intel_fb_obj(fb);
3069         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3070                                                fb->pixel_format);
3071         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3072
3073         /*
3074          * FIXME: intel_plane_state->src, dst aren't set when transitional
3075          * update_plane helpers are called from legacy paths.
3076          * Once full atomic crtc is available, below check can be avoided.
3077          */
3078         if (drm_rect_width(&plane_state->src)) {
3079                 scaler_id = plane_state->scaler_id;
3080                 src_x = plane_state->src.x1 >> 16;
3081                 src_y = plane_state->src.y1 >> 16;
3082                 src_w = drm_rect_width(&plane_state->src) >> 16;
3083                 src_h = drm_rect_height(&plane_state->src) >> 16;
3084                 dst_x = plane_state->dst.x1;
3085                 dst_y = plane_state->dst.y1;
3086                 dst_w = drm_rect_width(&plane_state->dst);
3087                 dst_h = drm_rect_height(&plane_state->dst);
3088
3089                 WARN_ON(x != src_x || y != src_y);
3090         } else {
3091                 src_w = intel_crtc->config->pipe_src_w;
3092                 src_h = intel_crtc->config->pipe_src_h;
3093         }
3094
3095         if (intel_rotation_90_or_270(rotation)) {
3096                 /* stride = Surface height in tiles */
3097                 tile_height = intel_tile_height(dev, fb->pixel_format,
3098                                                 fb->modifier[0]);
3099                 stride = DIV_ROUND_UP(fb->height, tile_height);
3100                 x_offset = stride * tile_height - y - src_h;
3101                 y_offset = x;
3102                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3103         } else {
3104                 stride = fb->pitches[0] / stride_div;
3105                 x_offset = x;
3106                 y_offset = y;
3107                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3108         }
3109         plane_offset = y_offset << 16 | x_offset;
3110
3111         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3112         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3113         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3114         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3115
3116         if (scaler_id >= 0) {
3117                 uint32_t ps_ctrl = 0;
3118
3119                 WARN_ON(!dst_w || !dst_h);
3120                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3121                         crtc_state->scaler_state.scalers[scaler_id].mode;
3122                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3123                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3124                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3125                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3126                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3127         } else {
3128                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3129         }
3130
3131         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3132
3133         POSTING_READ(PLANE_SURF(pipe, 0));
3134 }
3135
3136 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3137 static int
3138 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3139                            int x, int y, enum mode_set_atomic state)
3140 {
3141         struct drm_device *dev = crtc->dev;
3142         struct drm_i915_private *dev_priv = dev->dev_private;
3143
3144         if (dev_priv->display.disable_fbc)
3145                 dev_priv->display.disable_fbc(dev);
3146
3147         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3148
3149         return 0;
3150 }
3151
3152 static void intel_complete_page_flips(struct drm_device *dev)
3153 {
3154         struct drm_crtc *crtc;
3155
3156         for_each_crtc(dev, crtc) {
3157                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3158                 enum plane plane = intel_crtc->plane;
3159
3160                 intel_prepare_page_flip(dev, plane);
3161                 intel_finish_page_flip_plane(dev, plane);
3162         }
3163 }
3164
3165 static void intel_update_primary_planes(struct drm_device *dev)
3166 {
3167         struct drm_i915_private *dev_priv = dev->dev_private;
3168         struct drm_crtc *crtc;
3169
3170         for_each_crtc(dev, crtc) {
3171                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172
3173                 drm_modeset_lock(&crtc->mutex, NULL);
3174                 /*
3175                  * FIXME: Once we have proper support for primary planes (and
3176                  * disabling them without disabling the entire crtc) allow again
3177                  * a NULL crtc->primary->fb.
3178                  */
3179                 if (intel_crtc->active && crtc->primary->fb)
3180                         dev_priv->display.update_primary_plane(crtc,
3181                                                                crtc->primary->fb,
3182                                                                crtc->x,
3183                                                                crtc->y);
3184                 drm_modeset_unlock(&crtc->mutex);
3185         }
3186 }
3187
3188 void intel_crtc_reset(struct intel_crtc *crtc)
3189 {
3190         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3191
3192         if (!crtc->active)
3193                 return;
3194
3195         intel_crtc_disable_planes(&crtc->base);
3196         dev_priv->display.crtc_disable(&crtc->base);
3197         dev_priv->display.crtc_enable(&crtc->base);
3198         intel_crtc_enable_planes(&crtc->base);
3199 }
3200
3201 void intel_prepare_reset(struct drm_device *dev)
3202 {
3203         struct drm_i915_private *dev_priv = to_i915(dev);
3204         struct intel_crtc *crtc;
3205
3206         /* no reset support for gen2 */
3207         if (IS_GEN2(dev))
3208                 return;
3209
3210         /* reset doesn't touch the display */
3211         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3212                 return;
3213
3214         drm_modeset_lock_all(dev);
3215
3216         /*
3217          * Disabling the crtcs gracefully seems nicer. Also the
3218          * g33 docs say we should at least disable all the planes.
3219          */
3220         for_each_intel_crtc(dev, crtc) {
3221                 if (!crtc->active)
3222                         continue;
3223
3224                 intel_crtc_disable_planes(&crtc->base);
3225                 dev_priv->display.crtc_disable(&crtc->base);
3226         }
3227 }
3228
3229 void intel_finish_reset(struct drm_device *dev)
3230 {
3231         struct drm_i915_private *dev_priv = to_i915(dev);
3232
3233         /*
3234          * Flips in the rings will be nuked by the reset,
3235          * so complete all pending flips so that user space
3236          * will get its events and not get stuck.
3237          */
3238         intel_complete_page_flips(dev);
3239
3240         /* no reset support for gen2 */
3241         if (IS_GEN2(dev))
3242                 return;
3243
3244         /* reset doesn't touch the display */
3245         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3246                 /*
3247                  * Flips in the rings have been nuked by the reset,
3248                  * so update the base address of all primary
3249                  * planes to the the last fb to make sure we're
3250                  * showing the correct fb after a reset.
3251                  */
3252                 intel_update_primary_planes(dev);
3253                 return;
3254         }
3255
3256         /*
3257          * The display has been reset as well,
3258          * so need a full re-initialization.
3259          */
3260         intel_runtime_pm_disable_interrupts(dev_priv);
3261         intel_runtime_pm_enable_interrupts(dev_priv);
3262
3263         intel_modeset_init_hw(dev);
3264
3265         spin_lock_irq(&dev_priv->irq_lock);
3266         if (dev_priv->display.hpd_irq_setup)
3267                 dev_priv->display.hpd_irq_setup(dev);
3268         spin_unlock_irq(&dev_priv->irq_lock);
3269
3270         intel_modeset_setup_hw_state(dev, true);
3271
3272         intel_hpd_init(dev_priv);
3273
3274         drm_modeset_unlock_all(dev);
3275 }
3276
3277 static void
3278 intel_finish_fb(struct drm_framebuffer *old_fb)
3279 {
3280         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3281         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3282         bool was_interruptible = dev_priv->mm.interruptible;
3283         int ret;
3284
3285         /* Big Hammer, we also need to ensure that any pending
3286          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3287          * current scanout is retired before unpinning the old
3288          * framebuffer. Note that we rely on userspace rendering
3289          * into the buffer attached to the pipe they are waiting
3290          * on. If not, userspace generates a GPU hang with IPEHR
3291          * point to the MI_WAIT_FOR_EVENT.
3292          *
3293          * This should only fail upon a hung GPU, in which case we
3294          * can safely continue.
3295          */
3296         dev_priv->mm.interruptible = false;
3297         ret = i915_gem_object_wait_rendering(obj, true);
3298         dev_priv->mm.interruptible = was_interruptible;
3299
3300         WARN_ON(ret);
3301 }
3302
3303 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3304 {
3305         struct drm_device *dev = crtc->dev;
3306         struct drm_i915_private *dev_priv = dev->dev_private;
3307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3308         bool pending;
3309
3310         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3311             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3312                 return false;
3313
3314         spin_lock_irq(&dev->event_lock);
3315         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3316         spin_unlock_irq(&dev->event_lock);
3317
3318         return pending;
3319 }
3320
3321 static void intel_update_pipe_size(struct intel_crtc *crtc)
3322 {
3323         struct drm_device *dev = crtc->base.dev;
3324         struct drm_i915_private *dev_priv = dev->dev_private;
3325         const struct drm_display_mode *adjusted_mode;
3326
3327         if (!i915.fastboot)
3328                 return;
3329
3330         /*
3331          * Update pipe size and adjust fitter if needed: the reason for this is
3332          * that in compute_mode_changes we check the native mode (not the pfit
3333          * mode) to see if we can flip rather than do a full mode set. In the
3334          * fastboot case, we'll flip, but if we don't update the pipesrc and
3335          * pfit state, we'll end up with a big fb scanned out into the wrong
3336          * sized surface.
3337          *
3338          * To fix this properly, we need to hoist the checks up into
3339          * compute_mode_changes (or above), check the actual pfit state and
3340          * whether the platform allows pfit disable with pipe active, and only
3341          * then update the pipesrc and pfit state, even on the flip path.
3342          */
3343
3344         adjusted_mode = &crtc->config->base.adjusted_mode;
3345
3346         I915_WRITE(PIPESRC(crtc->pipe),
3347                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3348                    (adjusted_mode->crtc_vdisplay - 1));
3349         if (!crtc->config->pch_pfit.enabled &&
3350             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3351              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3352                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3353                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3354                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3355         }
3356         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3357         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3358 }
3359
3360 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3361 {
3362         struct drm_device *dev = crtc->dev;
3363         struct drm_i915_private *dev_priv = dev->dev_private;
3364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365         int pipe = intel_crtc->pipe;
3366         u32 reg, temp;
3367
3368         /* enable normal train */
3369         reg = FDI_TX_CTL(pipe);
3370         temp = I915_READ(reg);
3371         if (IS_IVYBRIDGE(dev)) {
3372                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3373                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3374         } else {
3375                 temp &= ~FDI_LINK_TRAIN_NONE;
3376                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3377         }
3378         I915_WRITE(reg, temp);
3379
3380         reg = FDI_RX_CTL(pipe);
3381         temp = I915_READ(reg);
3382         if (HAS_PCH_CPT(dev)) {
3383                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3384                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3385         } else {
3386                 temp &= ~FDI_LINK_TRAIN_NONE;
3387                 temp |= FDI_LINK_TRAIN_NONE;
3388         }
3389         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3390
3391         /* wait one idle pattern time */
3392         POSTING_READ(reg);
3393         udelay(1000);
3394
3395         /* IVB wants error correction enabled */
3396         if (IS_IVYBRIDGE(dev))
3397                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3398                            FDI_FE_ERRC_ENABLE);
3399 }
3400
3401 /* The FDI link training functions for ILK/Ibexpeak. */
3402 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3403 {
3404         struct drm_device *dev = crtc->dev;
3405         struct drm_i915_private *dev_priv = dev->dev_private;
3406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407         int pipe = intel_crtc->pipe;
3408         u32 reg, temp, tries;
3409
3410         /* FDI needs bits from pipe first */
3411         assert_pipe_enabled(dev_priv, pipe);
3412
3413         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3414            for train result */
3415         reg = FDI_RX_IMR(pipe);
3416         temp = I915_READ(reg);
3417         temp &= ~FDI_RX_SYMBOL_LOCK;
3418         temp &= ~FDI_RX_BIT_LOCK;
3419         I915_WRITE(reg, temp);
3420         I915_READ(reg);
3421         udelay(150);
3422
3423         /* enable CPU FDI TX and PCH FDI RX */
3424         reg = FDI_TX_CTL(pipe);
3425         temp = I915_READ(reg);
3426         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3427         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3428         temp &= ~FDI_LINK_TRAIN_NONE;
3429         temp |= FDI_LINK_TRAIN_PATTERN_1;
3430         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3431
3432         reg = FDI_RX_CTL(pipe);
3433         temp = I915_READ(reg);
3434         temp &= ~FDI_LINK_TRAIN_NONE;
3435         temp |= FDI_LINK_TRAIN_PATTERN_1;
3436         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3437
3438         POSTING_READ(reg);
3439         udelay(150);
3440
3441         /* Ironlake workaround, enable clock pointer after FDI enable*/
3442         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3443         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3444                    FDI_RX_PHASE_SYNC_POINTER_EN);
3445
3446         reg = FDI_RX_IIR(pipe);
3447         for (tries = 0; tries < 5; tries++) {
3448                 temp = I915_READ(reg);
3449                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3450
3451                 if ((temp & FDI_RX_BIT_LOCK)) {
3452                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3453                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3454                         break;
3455                 }
3456         }
3457         if (tries == 5)
3458                 DRM_ERROR("FDI train 1 fail!\n");
3459
3460         /* Train 2 */
3461         reg = FDI_TX_CTL(pipe);
3462         temp = I915_READ(reg);
3463         temp &= ~FDI_LINK_TRAIN_NONE;
3464         temp |= FDI_LINK_TRAIN_PATTERN_2;
3465         I915_WRITE(reg, temp);
3466
3467         reg = FDI_RX_CTL(pipe);
3468         temp = I915_READ(reg);
3469         temp &= ~FDI_LINK_TRAIN_NONE;
3470         temp |= FDI_LINK_TRAIN_PATTERN_2;
3471         I915_WRITE(reg, temp);
3472
3473         POSTING_READ(reg);
3474         udelay(150);
3475
3476         reg = FDI_RX_IIR(pipe);
3477         for (tries = 0; tries < 5; tries++) {
3478                 temp = I915_READ(reg);
3479                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3480
3481                 if (temp & FDI_RX_SYMBOL_LOCK) {
3482                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3483                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3484                         break;
3485                 }
3486         }
3487         if (tries == 5)
3488                 DRM_ERROR("FDI train 2 fail!\n");
3489
3490         DRM_DEBUG_KMS("FDI train done\n");
3491
3492 }
3493
3494 static const int snb_b_fdi_train_param[] = {
3495         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3496         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3497         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3498         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3499 };
3500
3501 /* The FDI link training functions for SNB/Cougarpoint. */
3502 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3503 {
3504         struct drm_device *dev = crtc->dev;
3505         struct drm_i915_private *dev_priv = dev->dev_private;
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         int pipe = intel_crtc->pipe;
3508         u32 reg, temp, i, retry;
3509
3510         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3511            for train result */
3512         reg = FDI_RX_IMR(pipe);
3513         temp = I915_READ(reg);
3514         temp &= ~FDI_RX_SYMBOL_LOCK;
3515         temp &= ~FDI_RX_BIT_LOCK;
3516         I915_WRITE(reg, temp);
3517
3518         POSTING_READ(reg);
3519         udelay(150);
3520
3521         /* enable CPU FDI TX and PCH FDI RX */
3522         reg = FDI_TX_CTL(pipe);
3523         temp = I915_READ(reg);
3524         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3525         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3526         temp &= ~FDI_LINK_TRAIN_NONE;
3527         temp |= FDI_LINK_TRAIN_PATTERN_1;
3528         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3529         /* SNB-B */
3530         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3531         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3532
3533         I915_WRITE(FDI_RX_MISC(pipe),
3534                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3535
3536         reg = FDI_RX_CTL(pipe);
3537         temp = I915_READ(reg);
3538         if (HAS_PCH_CPT(dev)) {
3539                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3540                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3541         } else {
3542                 temp &= ~FDI_LINK_TRAIN_NONE;
3543                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3544         }
3545         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3546
3547         POSTING_READ(reg);
3548         udelay(150);
3549
3550         for (i = 0; i < 4; i++) {
3551                 reg = FDI_TX_CTL(pipe);
3552                 temp = I915_READ(reg);
3553                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3554                 temp |= snb_b_fdi_train_param[i];
3555                 I915_WRITE(reg, temp);
3556
3557                 POSTING_READ(reg);
3558                 udelay(500);
3559
3560                 for (retry = 0; retry < 5; retry++) {
3561                         reg = FDI_RX_IIR(pipe);
3562                         temp = I915_READ(reg);
3563                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3564                         if (temp & FDI_RX_BIT_LOCK) {
3565                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3566                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3567                                 break;
3568                         }
3569                         udelay(50);
3570                 }
3571                 if (retry < 5)
3572                         break;
3573         }
3574         if (i == 4)
3575                 DRM_ERROR("FDI train 1 fail!\n");
3576
3577         /* Train 2 */
3578         reg = FDI_TX_CTL(pipe);
3579         temp = I915_READ(reg);
3580         temp &= ~FDI_LINK_TRAIN_NONE;
3581         temp |= FDI_LINK_TRAIN_PATTERN_2;
3582         if (IS_GEN6(dev)) {
3583                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3584                 /* SNB-B */
3585                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3586         }
3587         I915_WRITE(reg, temp);
3588
3589         reg = FDI_RX_CTL(pipe);
3590         temp = I915_READ(reg);
3591         if (HAS_PCH_CPT(dev)) {
3592                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3593                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3594         } else {
3595                 temp &= ~FDI_LINK_TRAIN_NONE;
3596                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3597         }
3598         I915_WRITE(reg, temp);
3599
3600         POSTING_READ(reg);
3601         udelay(150);
3602
3603         for (i = 0; i < 4; i++) {
3604                 reg = FDI_TX_CTL(pipe);
3605                 temp = I915_READ(reg);
3606                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3607                 temp |= snb_b_fdi_train_param[i];
3608                 I915_WRITE(reg, temp);
3609
3610                 POSTING_READ(reg);
3611                 udelay(500);
3612
3613                 for (retry = 0; retry < 5; retry++) {
3614                         reg = FDI_RX_IIR(pipe);
3615                         temp = I915_READ(reg);
3616                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3617                         if (temp & FDI_RX_SYMBOL_LOCK) {
3618                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3619                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3620                                 break;
3621                         }
3622                         udelay(50);
3623                 }
3624                 if (retry < 5)
3625                         break;
3626         }
3627         if (i == 4)
3628                 DRM_ERROR("FDI train 2 fail!\n");
3629
3630         DRM_DEBUG_KMS("FDI train done.\n");
3631 }
3632
3633 /* Manual link training for Ivy Bridge A0 parts */
3634 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3635 {
3636         struct drm_device *dev = crtc->dev;
3637         struct drm_i915_private *dev_priv = dev->dev_private;
3638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3639         int pipe = intel_crtc->pipe;
3640         u32 reg, temp, i, j;
3641
3642         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3643            for train result */
3644         reg = FDI_RX_IMR(pipe);
3645         temp = I915_READ(reg);
3646         temp &= ~FDI_RX_SYMBOL_LOCK;
3647         temp &= ~FDI_RX_BIT_LOCK;
3648         I915_WRITE(reg, temp);
3649
3650         POSTING_READ(reg);
3651         udelay(150);
3652
3653         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3654                       I915_READ(FDI_RX_IIR(pipe)));
3655
3656         /* Try each vswing and preemphasis setting twice before moving on */
3657         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3658                 /* disable first in case we need to retry */
3659                 reg = FDI_TX_CTL(pipe);
3660                 temp = I915_READ(reg);
3661                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3662                 temp &= ~FDI_TX_ENABLE;
3663                 I915_WRITE(reg, temp);
3664
3665                 reg = FDI_RX_CTL(pipe);
3666                 temp = I915_READ(reg);
3667                 temp &= ~FDI_LINK_TRAIN_AUTO;
3668                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3669                 temp &= ~FDI_RX_ENABLE;
3670                 I915_WRITE(reg, temp);
3671
3672                 /* enable CPU FDI TX and PCH FDI RX */
3673                 reg = FDI_TX_CTL(pipe);
3674                 temp = I915_READ(reg);
3675                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3676                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3677                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3678                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3679                 temp |= snb_b_fdi_train_param[j/2];
3680                 temp |= FDI_COMPOSITE_SYNC;
3681                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3682
3683                 I915_WRITE(FDI_RX_MISC(pipe),
3684                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3685
3686                 reg = FDI_RX_CTL(pipe);
3687                 temp = I915_READ(reg);
3688                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3689                 temp |= FDI_COMPOSITE_SYNC;
3690                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3691
3692                 POSTING_READ(reg);
3693                 udelay(1); /* should be 0.5us */
3694
3695                 for (i = 0; i < 4; i++) {
3696                         reg = FDI_RX_IIR(pipe);
3697                         temp = I915_READ(reg);
3698                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3699
3700                         if (temp & FDI_RX_BIT_LOCK ||
3701                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3702                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3703                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3704                                               i);
3705                                 break;
3706                         }
3707                         udelay(1); /* should be 0.5us */
3708                 }
3709                 if (i == 4) {
3710                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3711                         continue;
3712                 }
3713
3714                 /* Train 2 */
3715                 reg = FDI_TX_CTL(pipe);
3716                 temp = I915_READ(reg);
3717                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3718                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3719                 I915_WRITE(reg, temp);
3720
3721                 reg = FDI_RX_CTL(pipe);
3722                 temp = I915_READ(reg);
3723                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3724                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3725                 I915_WRITE(reg, temp);
3726
3727                 POSTING_READ(reg);
3728                 udelay(2); /* should be 1.5us */
3729
3730                 for (i = 0; i < 4; i++) {
3731                         reg = FDI_RX_IIR(pipe);
3732                         temp = I915_READ(reg);
3733                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3734
3735                         if (temp & FDI_RX_SYMBOL_LOCK ||
3736                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3737                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3738                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3739                                               i);
3740                                 goto train_done;
3741                         }
3742                         udelay(2); /* should be 1.5us */
3743                 }
3744                 if (i == 4)
3745                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3746         }
3747
3748 train_done:
3749         DRM_DEBUG_KMS("FDI train done.\n");
3750 }
3751
3752 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3753 {
3754         struct drm_device *dev = intel_crtc->base.dev;
3755         struct drm_i915_private *dev_priv = dev->dev_private;
3756         int pipe = intel_crtc->pipe;
3757         u32 reg, temp;
3758
3759
3760         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3761         reg = FDI_RX_CTL(pipe);
3762         temp = I915_READ(reg);
3763         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3764         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3765         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3766         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3767
3768         POSTING_READ(reg);
3769         udelay(200);
3770
3771         /* Switch from Rawclk to PCDclk */
3772         temp = I915_READ(reg);
3773         I915_WRITE(reg, temp | FDI_PCDCLK);
3774
3775         POSTING_READ(reg);
3776         udelay(200);
3777
3778         /* Enable CPU FDI TX PLL, always on for Ironlake */
3779         reg = FDI_TX_CTL(pipe);
3780         temp = I915_READ(reg);
3781         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3782                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3783
3784                 POSTING_READ(reg);
3785                 udelay(100);
3786         }
3787 }
3788
3789 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3790 {
3791         struct drm_device *dev = intel_crtc->base.dev;
3792         struct drm_i915_private *dev_priv = dev->dev_private;
3793         int pipe = intel_crtc->pipe;
3794         u32 reg, temp;
3795
3796         /* Switch from PCDclk to Rawclk */
3797         reg = FDI_RX_CTL(pipe);
3798         temp = I915_READ(reg);
3799         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3800
3801         /* Disable CPU FDI TX PLL */
3802         reg = FDI_TX_CTL(pipe);
3803         temp = I915_READ(reg);
3804         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3805
3806         POSTING_READ(reg);
3807         udelay(100);
3808
3809         reg = FDI_RX_CTL(pipe);
3810         temp = I915_READ(reg);
3811         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3812
3813         /* Wait for the clocks to turn off. */
3814         POSTING_READ(reg);
3815         udelay(100);
3816 }
3817
3818 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3819 {
3820         struct drm_device *dev = crtc->dev;
3821         struct drm_i915_private *dev_priv = dev->dev_private;
3822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3823         int pipe = intel_crtc->pipe;
3824         u32 reg, temp;
3825
3826         /* disable CPU FDI tx and PCH FDI rx */
3827         reg = FDI_TX_CTL(pipe);
3828         temp = I915_READ(reg);
3829         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3830         POSTING_READ(reg);
3831
3832         reg = FDI_RX_CTL(pipe);
3833         temp = I915_READ(reg);
3834         temp &= ~(0x7 << 16);
3835         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3836         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3837
3838         POSTING_READ(reg);
3839         udelay(100);
3840
3841         /* Ironlake workaround, disable clock pointer after downing FDI */
3842         if (HAS_PCH_IBX(dev))
3843                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3844
3845         /* still set train pattern 1 */
3846         reg = FDI_TX_CTL(pipe);
3847         temp = I915_READ(reg);
3848         temp &= ~FDI_LINK_TRAIN_NONE;
3849         temp |= FDI_LINK_TRAIN_PATTERN_1;
3850         I915_WRITE(reg, temp);
3851
3852         reg = FDI_RX_CTL(pipe);
3853         temp = I915_READ(reg);
3854         if (HAS_PCH_CPT(dev)) {
3855                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3856                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3857         } else {
3858                 temp &= ~FDI_LINK_TRAIN_NONE;
3859                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3860         }
3861         /* BPC in FDI rx is consistent with that in PIPECONF */
3862         temp &= ~(0x07 << 16);
3863         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3864         I915_WRITE(reg, temp);
3865
3866         POSTING_READ(reg);
3867         udelay(100);
3868 }
3869
3870 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3871 {
3872         struct intel_crtc *crtc;
3873
3874         /* Note that we don't need to be called with mode_config.lock here
3875          * as our list of CRTC objects is static for the lifetime of the
3876          * device and so cannot disappear as we iterate. Similarly, we can
3877          * happily treat the predicates as racy, atomic checks as userspace
3878          * cannot claim and pin a new fb without at least acquring the
3879          * struct_mutex and so serialising with us.
3880          */
3881         for_each_intel_crtc(dev, crtc) {
3882                 if (atomic_read(&crtc->unpin_work_count) == 0)
3883                         continue;
3884
3885                 if (crtc->unpin_work)
3886                         intel_wait_for_vblank(dev, crtc->pipe);
3887
3888                 return true;
3889         }
3890
3891         return false;
3892 }
3893
3894 static void page_flip_completed(struct intel_crtc *intel_crtc)
3895 {
3896         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3897         struct intel_unpin_work *work = intel_crtc->unpin_work;
3898
3899         /* ensure that the unpin work is consistent wrt ->pending. */
3900         smp_rmb();
3901         intel_crtc->unpin_work = NULL;
3902
3903         if (work->event)
3904                 drm_send_vblank_event(intel_crtc->base.dev,
3905                                       intel_crtc->pipe,
3906                                       work->event);
3907
3908         drm_crtc_vblank_put(&intel_crtc->base);
3909
3910         wake_up_all(&dev_priv->pending_flip_queue);
3911         queue_work(dev_priv->wq, &work->work);
3912
3913         trace_i915_flip_complete(intel_crtc->plane,
3914                                  work->pending_flip_obj);
3915 }
3916
3917 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3918 {
3919         struct drm_device *dev = crtc->dev;
3920         struct drm_i915_private *dev_priv = dev->dev_private;
3921
3922         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3923         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3924                                        !intel_crtc_has_pending_flip(crtc),
3925                                        60*HZ) == 0)) {
3926                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3927
3928                 spin_lock_irq(&dev->event_lock);
3929                 if (intel_crtc->unpin_work) {
3930                         WARN_ONCE(1, "Removing stuck page flip\n");
3931                         page_flip_completed(intel_crtc);
3932                 }
3933                 spin_unlock_irq(&dev->event_lock);
3934         }
3935
3936         if (crtc->primary->fb) {
3937                 mutex_lock(&dev->struct_mutex);
3938                 intel_finish_fb(crtc->primary->fb);
3939                 mutex_unlock(&dev->struct_mutex);
3940         }
3941 }
3942
3943 /* Program iCLKIP clock to the desired frequency */
3944 static void lpt_program_iclkip(struct drm_crtc *crtc)
3945 {
3946         struct drm_device *dev = crtc->dev;
3947         struct drm_i915_private *dev_priv = dev->dev_private;
3948         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3949         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3950         u32 temp;
3951
3952         mutex_lock(&dev_priv->dpio_lock);
3953
3954         /* It is necessary to ungate the pixclk gate prior to programming
3955          * the divisors, and gate it back when it is done.
3956          */
3957         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3958
3959         /* Disable SSCCTL */
3960         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3961                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3962                                 SBI_SSCCTL_DISABLE,
3963                         SBI_ICLK);
3964
3965         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3966         if (clock == 20000) {
3967                 auxdiv = 1;
3968                 divsel = 0x41;
3969                 phaseinc = 0x20;
3970         } else {
3971                 /* The iCLK virtual clock root frequency is in MHz,
3972                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3973                  * divisors, it is necessary to divide one by another, so we
3974                  * convert the virtual clock precision to KHz here for higher
3975                  * precision.
3976                  */
3977                 u32 iclk_virtual_root_freq = 172800 * 1000;
3978                 u32 iclk_pi_range = 64;
3979                 u32 desired_divisor, msb_divisor_value, pi_value;
3980
3981                 desired_divisor = (iclk_virtual_root_freq / clock);
3982                 msb_divisor_value = desired_divisor / iclk_pi_range;
3983                 pi_value = desired_divisor % iclk_pi_range;
3984
3985                 auxdiv = 0;
3986                 divsel = msb_divisor_value - 2;
3987                 phaseinc = pi_value;
3988         }
3989
3990         /* This should not happen with any sane values */
3991         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3992                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3993         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3994                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3995
3996         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3997                         clock,
3998                         auxdiv,
3999                         divsel,
4000                         phasedir,
4001                         phaseinc);
4002
4003         /* Program SSCDIVINTPHASE6 */
4004         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4005         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4006         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4007         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4008         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4009         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4010         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4011         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4012
4013         /* Program SSCAUXDIV */
4014         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4015         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4016         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4017         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4018
4019         /* Enable modulator and associated divider */
4020         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4021         temp &= ~SBI_SSCCTL_DISABLE;
4022         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4023
4024         /* Wait for initialization time */
4025         udelay(24);
4026
4027         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4028
4029         mutex_unlock(&dev_priv->dpio_lock);
4030 }
4031
4032 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4033                                                 enum pipe pch_transcoder)
4034 {
4035         struct drm_device *dev = crtc->base.dev;
4036         struct drm_i915_private *dev_priv = dev->dev_private;
4037         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4038
4039         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4040                    I915_READ(HTOTAL(cpu_transcoder)));
4041         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4042                    I915_READ(HBLANK(cpu_transcoder)));
4043         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4044                    I915_READ(HSYNC(cpu_transcoder)));
4045
4046         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4047                    I915_READ(VTOTAL(cpu_transcoder)));
4048         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4049                    I915_READ(VBLANK(cpu_transcoder)));
4050         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4051                    I915_READ(VSYNC(cpu_transcoder)));
4052         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4053                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4054 }
4055
4056 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4057 {
4058         struct drm_i915_private *dev_priv = dev->dev_private;
4059         uint32_t temp;
4060
4061         temp = I915_READ(SOUTH_CHICKEN1);
4062         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4063                 return;
4064
4065         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4066         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4067
4068         temp &= ~FDI_BC_BIFURCATION_SELECT;
4069         if (enable)
4070                 temp |= FDI_BC_BIFURCATION_SELECT;
4071
4072         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4073         I915_WRITE(SOUTH_CHICKEN1, temp);
4074         POSTING_READ(SOUTH_CHICKEN1);
4075 }
4076
4077 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4078 {
4079         struct drm_device *dev = intel_crtc->base.dev;
4080
4081         switch (intel_crtc->pipe) {
4082         case PIPE_A:
4083                 break;
4084         case PIPE_B:
4085                 if (intel_crtc->config->fdi_lanes > 2)
4086                         cpt_set_fdi_bc_bifurcation(dev, false);
4087                 else
4088                         cpt_set_fdi_bc_bifurcation(dev, true);
4089
4090                 break;
4091         case PIPE_C:
4092                 cpt_set_fdi_bc_bifurcation(dev, true);
4093
4094                 break;
4095         default:
4096                 BUG();
4097         }
4098 }
4099
4100 /*
4101  * Enable PCH resources required for PCH ports:
4102  *   - PCH PLLs
4103  *   - FDI training & RX/TX
4104  *   - update transcoder timings
4105  *   - DP transcoding bits
4106  *   - transcoder
4107  */
4108 static void ironlake_pch_enable(struct drm_crtc *crtc)
4109 {
4110         struct drm_device *dev = crtc->dev;
4111         struct drm_i915_private *dev_priv = dev->dev_private;
4112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4113         int pipe = intel_crtc->pipe;
4114         u32 reg, temp;
4115
4116         assert_pch_transcoder_disabled(dev_priv, pipe);
4117
4118         if (IS_IVYBRIDGE(dev))
4119                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4120
4121         /* Write the TU size bits before fdi link training, so that error
4122          * detection works. */
4123         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4124                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4125
4126         /* For PCH output, training FDI link */
4127         dev_priv->display.fdi_link_train(crtc);
4128
4129         /* We need to program the right clock selection before writing the pixel
4130          * mutliplier into the DPLL. */
4131         if (HAS_PCH_CPT(dev)) {
4132                 u32 sel;
4133
4134                 temp = I915_READ(PCH_DPLL_SEL);
4135                 temp |= TRANS_DPLL_ENABLE(pipe);
4136                 sel = TRANS_DPLLB_SEL(pipe);
4137                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4138                         temp |= sel;
4139                 else
4140                         temp &= ~sel;
4141                 I915_WRITE(PCH_DPLL_SEL, temp);
4142         }
4143
4144         /* XXX: pch pll's can be enabled any time before we enable the PCH
4145          * transcoder, and we actually should do this to not upset any PCH
4146          * transcoder that already use the clock when we share it.
4147          *
4148          * Note that enable_shared_dpll tries to do the right thing, but
4149          * get_shared_dpll unconditionally resets the pll - we need that to have
4150          * the right LVDS enable sequence. */
4151         intel_enable_shared_dpll(intel_crtc);
4152
4153         /* set transcoder timing, panel must allow it */
4154         assert_panel_unlocked(dev_priv, pipe);
4155         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4156
4157         intel_fdi_normal_train(crtc);
4158
4159         /* For PCH DP, enable TRANS_DP_CTL */
4160         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4161                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4162                 reg = TRANS_DP_CTL(pipe);
4163                 temp = I915_READ(reg);
4164                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4165                           TRANS_DP_SYNC_MASK |
4166                           TRANS_DP_BPC_MASK);
4167                 temp |= (TRANS_DP_OUTPUT_ENABLE |
4168                          TRANS_DP_ENH_FRAMING);
4169                 temp |= bpc << 9; /* same format but at 11:9 */
4170
4171                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4172                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4173                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4174                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4175
4176                 switch (intel_trans_dp_port_sel(crtc)) {
4177                 case PCH_DP_B:
4178                         temp |= TRANS_DP_PORT_SEL_B;
4179                         break;
4180                 case PCH_DP_C:
4181                         temp |= TRANS_DP_PORT_SEL_C;
4182                         break;
4183                 case PCH_DP_D:
4184                         temp |= TRANS_DP_PORT_SEL_D;
4185                         break;
4186                 default:
4187                         BUG();
4188                 }
4189
4190                 I915_WRITE(reg, temp);
4191         }
4192
4193         ironlake_enable_pch_transcoder(dev_priv, pipe);
4194 }
4195
4196 static void lpt_pch_enable(struct drm_crtc *crtc)
4197 {
4198         struct drm_device *dev = crtc->dev;
4199         struct drm_i915_private *dev_priv = dev->dev_private;
4200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4201         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4202
4203         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4204
4205         lpt_program_iclkip(crtc);
4206
4207         /* Set transcoder timing. */
4208         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4209
4210         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4211 }
4212
4213 void intel_put_shared_dpll(struct intel_crtc *crtc)
4214 {
4215         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4216
4217         if (pll == NULL)
4218                 return;
4219
4220         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4221                 WARN(1, "bad %s crtc mask\n", pll->name);
4222                 return;
4223         }
4224
4225         pll->config.crtc_mask &= ~(1 << crtc->pipe);
4226         if (pll->config.crtc_mask == 0) {
4227                 WARN_ON(pll->on);
4228                 WARN_ON(pll->active);
4229         }
4230
4231         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4232 }
4233
4234 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4235                                                 struct intel_crtc_state *crtc_state)
4236 {
4237         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4238         struct intel_shared_dpll *pll;
4239         enum intel_dpll_id i;
4240
4241         if (HAS_PCH_IBX(dev_priv->dev)) {
4242                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4243                 i = (enum intel_dpll_id) crtc->pipe;
4244                 pll = &dev_priv->shared_dplls[i];
4245
4246                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4247                               crtc->base.base.id, pll->name);
4248
4249                 WARN_ON(pll->new_config->crtc_mask);
4250
4251                 goto found;
4252         }
4253
4254         if (IS_BROXTON(dev_priv->dev)) {
4255                 /* PLL is attached to port in bxt */
4256                 struct intel_encoder *encoder;
4257                 struct intel_digital_port *intel_dig_port;
4258
4259                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4260                 if (WARN_ON(!encoder))
4261                         return NULL;
4262
4263                 intel_dig_port = enc_to_dig_port(&encoder->base);
4264                 /* 1:1 mapping between ports and PLLs */
4265                 i = (enum intel_dpll_id)intel_dig_port->port;
4266                 pll = &dev_priv->shared_dplls[i];
4267                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4268                         crtc->base.base.id, pll->name);
4269                 WARN_ON(pll->new_config->crtc_mask);
4270
4271                 goto found;
4272         }
4273
4274         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4275                 pll = &dev_priv->shared_dplls[i];
4276
4277                 /* Only want to check enabled timings first */
4278                 if (pll->new_config->crtc_mask == 0)
4279                         continue;
4280
4281                 if (memcmp(&crtc_state->dpll_hw_state,
4282                            &pll->new_config->hw_state,
4283                            sizeof(pll->new_config->hw_state)) == 0) {
4284                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4285                                       crtc->base.base.id, pll->name,
4286                                       pll->new_config->crtc_mask,
4287                                       pll->active);
4288                         goto found;
4289                 }
4290         }
4291
4292         /* Ok no matching timings, maybe there's a free one? */
4293         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4294                 pll = &dev_priv->shared_dplls[i];
4295                 if (pll->new_config->crtc_mask == 0) {
4296                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4297                                       crtc->base.base.id, pll->name);
4298                         goto found;
4299                 }
4300         }
4301
4302         return NULL;
4303
4304 found:
4305         if (pll->new_config->crtc_mask == 0)
4306                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4307
4308         crtc_state->shared_dpll = i;
4309         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4310                          pipe_name(crtc->pipe));
4311
4312         pll->new_config->crtc_mask |= 1 << crtc->pipe;
4313
4314         return pll;
4315 }
4316
4317 /**
4318  * intel_shared_dpll_start_config - start a new PLL staged config
4319  * @dev_priv: DRM device
4320  * @clear_pipes: mask of pipes that will have their PLLs freed
4321  *
4322  * Starts a new PLL staged config, copying the current config but
4323  * releasing the references of pipes specified in clear_pipes.
4324  */
4325 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4326                                           unsigned clear_pipes)
4327 {
4328         struct intel_shared_dpll *pll;
4329         enum intel_dpll_id i;
4330
4331         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4332                 pll = &dev_priv->shared_dplls[i];
4333
4334                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4335                                           GFP_KERNEL);
4336                 if (!pll->new_config)
4337                         goto cleanup;
4338
4339                 pll->new_config->crtc_mask &= ~clear_pipes;
4340         }
4341
4342         return 0;
4343
4344 cleanup:
4345         while (--i >= 0) {
4346                 pll = &dev_priv->shared_dplls[i];
4347                 kfree(pll->new_config);
4348                 pll->new_config = NULL;
4349         }
4350
4351         return -ENOMEM;
4352 }
4353
4354 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4355 {
4356         struct intel_shared_dpll *pll;
4357         enum intel_dpll_id i;
4358
4359         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4360                 pll = &dev_priv->shared_dplls[i];
4361
4362                 WARN_ON(pll->new_config == &pll->config);
4363
4364                 pll->config = *pll->new_config;
4365                 kfree(pll->new_config);
4366                 pll->new_config = NULL;
4367         }
4368 }
4369
4370 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4371 {
4372         struct intel_shared_dpll *pll;
4373         enum intel_dpll_id i;
4374
4375         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4376                 pll = &dev_priv->shared_dplls[i];
4377
4378                 WARN_ON(pll->new_config == &pll->config);
4379
4380                 kfree(pll->new_config);
4381                 pll->new_config = NULL;
4382         }
4383 }
4384
4385 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4386 {
4387         struct drm_i915_private *dev_priv = dev->dev_private;
4388         int dslreg = PIPEDSL(pipe);
4389         u32 temp;
4390
4391         temp = I915_READ(dslreg);
4392         udelay(500);
4393         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4394                 if (wait_for(I915_READ(dslreg) != temp, 5))
4395                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4396         }
4397 }
4398
4399 /**
4400  * skl_update_scaler_users - Stages update to crtc's scaler state
4401  * @intel_crtc: crtc
4402  * @crtc_state: crtc_state
4403  * @plane: plane (NULL indicates crtc is requesting update)
4404  * @plane_state: plane's state
4405  * @force_detach: request unconditional detachment of scaler
4406  *
4407  * This function updates scaler state for requested plane or crtc.
4408  * To request scaler usage update for a plane, caller shall pass plane pointer.
4409  * To request scaler usage update for crtc, caller shall pass plane pointer
4410  * as NULL.
4411  *
4412  * Return
4413  *     0 - scaler_usage updated successfully
4414  *    error - requested scaling cannot be supported or other error condition
4415  */
4416 int
4417 skl_update_scaler_users(
4418         struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4419         struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4420         int force_detach)
4421 {
4422         int need_scaling;
4423         int idx;
4424         int src_w, src_h, dst_w, dst_h;
4425         int *scaler_id;
4426         struct drm_framebuffer *fb;
4427         struct intel_crtc_scaler_state *scaler_state;
4428         unsigned int rotation;
4429
4430         if (!intel_crtc || !crtc_state)
4431                 return 0;
4432
4433         scaler_state = &crtc_state->scaler_state;
4434
4435         idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4436         fb = intel_plane ? plane_state->base.fb : NULL;
4437
4438         if (intel_plane) {
4439                 src_w = drm_rect_width(&plane_state->src) >> 16;
4440                 src_h = drm_rect_height(&plane_state->src) >> 16;
4441                 dst_w = drm_rect_width(&plane_state->dst);
4442                 dst_h = drm_rect_height(&plane_state->dst);
4443                 scaler_id = &plane_state->scaler_id;
4444                 rotation = plane_state->base.rotation;
4445         } else {
4446                 struct drm_display_mode *adjusted_mode =
4447                         &crtc_state->base.adjusted_mode;
4448                 src_w = crtc_state->pipe_src_w;
4449                 src_h = crtc_state->pipe_src_h;
4450                 dst_w = adjusted_mode->hdisplay;
4451                 dst_h = adjusted_mode->vdisplay;
4452                 scaler_id = &scaler_state->scaler_id;
4453                 rotation = DRM_ROTATE_0;
4454         }
4455
4456         need_scaling = intel_rotation_90_or_270(rotation) ?
4457                 (src_h != dst_w || src_w != dst_h):
4458                 (src_w != dst_w || src_h != dst_h);
4459
4460         /*
4461          * if plane is being disabled or scaler is no more required or force detach
4462          *  - free scaler binded to this plane/crtc
4463          *  - in order to do this, update crtc->scaler_usage
4464          *
4465          * Here scaler state in crtc_state is set free so that
4466          * scaler can be assigned to other user. Actual register
4467          * update to free the scaler is done in plane/panel-fit programming.
4468          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4469          */
4470         if (force_detach || !need_scaling || (intel_plane &&
4471                 (!fb || !plane_state->visible))) {
4472                 if (*scaler_id >= 0) {
4473                         scaler_state->scaler_users &= ~(1 << idx);
4474                         scaler_state->scalers[*scaler_id].in_use = 0;
4475
4476                         DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4477                                 "crtc_state = %p scaler_users = 0x%x\n",
4478                                 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4479                                 intel_plane ? intel_plane->base.base.id :
4480                                 intel_crtc->base.base.id, crtc_state,
4481                                 scaler_state->scaler_users);
4482                         *scaler_id = -1;
4483                 }
4484                 return 0;
4485         }
4486
4487         /* range checks */
4488         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4489                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4490
4491                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4492                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4493                 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4494                         "size is out of scaler range\n",
4495                         intel_plane ? "PLANE" : "CRTC",
4496                         intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4497                         intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4498                 return -EINVAL;
4499         }
4500
4501         /* check colorkey */
4502         if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4503                 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4504                         intel_plane->base.base.id);
4505                 return -EINVAL;
4506         }
4507
4508         /* Check src format */
4509         if (intel_plane) {
4510                 switch (fb->pixel_format) {
4511                 case DRM_FORMAT_RGB565:
4512                 case DRM_FORMAT_XBGR8888:
4513                 case DRM_FORMAT_XRGB8888:
4514                 case DRM_FORMAT_ABGR8888:
4515                 case DRM_FORMAT_ARGB8888:
4516                 case DRM_FORMAT_XRGB2101010:
4517                 case DRM_FORMAT_XBGR2101010:
4518                 case DRM_FORMAT_YUYV:
4519                 case DRM_FORMAT_YVYU:
4520                 case DRM_FORMAT_UYVY:
4521                 case DRM_FORMAT_VYUY:
4522                         break;
4523                 default:
4524                         DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4525                                 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4526                         return -EINVAL;
4527                 }
4528         }
4529
4530         /* mark this plane as a scaler user in crtc_state */
4531         scaler_state->scaler_users |= (1 << idx);
4532         DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4533                 "crtc_state = %p scaler_users = 0x%x\n",
4534                 intel_plane ? "PLANE" : "CRTC",
4535                 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4536                 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4537         return 0;
4538 }
4539
4540 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4541 {
4542         struct drm_device *dev = crtc->base.dev;
4543         struct drm_i915_private *dev_priv = dev->dev_private;
4544         int pipe = crtc->pipe;
4545         struct intel_crtc_scaler_state *scaler_state =
4546                 &crtc->config->scaler_state;
4547
4548         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4549
4550         /* To update pfit, first update scaler state */
4551         skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4552         intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4553         skl_detach_scalers(crtc);
4554         if (!enable)
4555                 return;
4556
4557         if (crtc->config->pch_pfit.enabled) {
4558                 int id;
4559
4560                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4561                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4562                         return;
4563                 }
4564
4565                 id = scaler_state->scaler_id;
4566                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4567                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4568                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4569                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4570
4571                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4572         }
4573 }
4574
4575 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4576 {
4577         struct drm_device *dev = crtc->base.dev;
4578         struct drm_i915_private *dev_priv = dev->dev_private;
4579         int pipe = crtc->pipe;
4580
4581         if (crtc->config->pch_pfit.enabled) {
4582                 /* Force use of hard-coded filter coefficients
4583                  * as some pre-programmed values are broken,
4584                  * e.g. x201.
4585                  */
4586                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4587                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4588                                                  PF_PIPE_SEL_IVB(pipe));
4589                 else
4590                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4591                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4592                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4593         }
4594 }
4595
4596 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4597 {
4598         struct drm_device *dev = crtc->dev;
4599         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4600         struct drm_plane *plane;
4601         struct intel_plane *intel_plane;
4602
4603         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4604                 intel_plane = to_intel_plane(plane);
4605                 if (intel_plane->pipe == pipe)
4606                         intel_plane_restore(&intel_plane->base);
4607         }
4608 }
4609
4610 void hsw_enable_ips(struct intel_crtc *crtc)
4611 {
4612         struct drm_device *dev = crtc->base.dev;
4613         struct drm_i915_private *dev_priv = dev->dev_private;
4614
4615         if (!crtc->config->ips_enabled)
4616                 return;
4617
4618         /* We can only enable IPS after we enable a plane and wait for a vblank */
4619         intel_wait_for_vblank(dev, crtc->pipe);
4620
4621         assert_plane_enabled(dev_priv, crtc->plane);
4622         if (IS_BROADWELL(dev)) {
4623                 mutex_lock(&dev_priv->rps.hw_lock);
4624                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4625                 mutex_unlock(&dev_priv->rps.hw_lock);
4626                 /* Quoting Art Runyan: "its not safe to expect any particular
4627                  * value in IPS_CTL bit 31 after enabling IPS through the
4628                  * mailbox." Moreover, the mailbox may return a bogus state,
4629                  * so we need to just enable it and continue on.
4630                  */
4631         } else {
4632                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4633                 /* The bit only becomes 1 in the next vblank, so this wait here
4634                  * is essentially intel_wait_for_vblank. If we don't have this
4635                  * and don't wait for vblanks until the end of crtc_enable, then
4636                  * the HW state readout code will complain that the expected
4637                  * IPS_CTL value is not the one we read. */
4638                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4639                         DRM_ERROR("Timed out waiting for IPS enable\n");
4640         }
4641 }
4642
4643 void hsw_disable_ips(struct intel_crtc *crtc)
4644 {
4645         struct drm_device *dev = crtc->base.dev;
4646         struct drm_i915_private *dev_priv = dev->dev_private;
4647
4648         if (!crtc->config->ips_enabled)
4649                 return;
4650
4651         assert_plane_enabled(dev_priv, crtc->plane);
4652         if (IS_BROADWELL(dev)) {
4653                 mutex_lock(&dev_priv->rps.hw_lock);
4654                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4655                 mutex_unlock(&dev_priv->rps.hw_lock);
4656                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4657                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4658                         DRM_ERROR("Timed out waiting for IPS disable\n");
4659         } else {
4660                 I915_WRITE(IPS_CTL, 0);
4661                 POSTING_READ(IPS_CTL);
4662         }
4663
4664         /* We need to wait for a vblank before we can disable the plane. */
4665         intel_wait_for_vblank(dev, crtc->pipe);
4666 }
4667
4668 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4669 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4670 {
4671         struct drm_device *dev = crtc->dev;
4672         struct drm_i915_private *dev_priv = dev->dev_private;
4673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4674         enum pipe pipe = intel_crtc->pipe;
4675         int palreg = PALETTE(pipe);
4676         int i;
4677         bool reenable_ips = false;
4678
4679         /* The clocks have to be on to load the palette. */
4680         if (!crtc->state->enable || !intel_crtc->active)
4681                 return;
4682
4683         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4684                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4685                         assert_dsi_pll_enabled(dev_priv);
4686                 else
4687                         assert_pll_enabled(dev_priv, pipe);
4688         }
4689
4690         /* use legacy palette for Ironlake */
4691         if (!HAS_GMCH_DISPLAY(dev))
4692                 palreg = LGC_PALETTE(pipe);
4693
4694         /* Workaround : Do not read or write the pipe palette/gamma data while
4695          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4696          */
4697         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4698             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4699              GAMMA_MODE_MODE_SPLIT)) {
4700                 hsw_disable_ips(intel_crtc);
4701                 reenable_ips = true;
4702         }
4703
4704         for (i = 0; i < 256; i++) {
4705                 I915_WRITE(palreg + 4 * i,
4706                            (intel_crtc->lut_r[i] << 16) |
4707                            (intel_crtc->lut_g[i] << 8) |
4708                            intel_crtc->lut_b[i]);
4709         }
4710
4711         if (reenable_ips)
4712                 hsw_enable_ips(intel_crtc);
4713 }
4714
4715 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4716 {
4717         if (intel_crtc->overlay) {
4718                 struct drm_device *dev = intel_crtc->base.dev;
4719                 struct drm_i915_private *dev_priv = dev->dev_private;
4720
4721                 mutex_lock(&dev->struct_mutex);
4722                 dev_priv->mm.interruptible = false;
4723                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4724                 dev_priv->mm.interruptible = true;
4725                 mutex_unlock(&dev->struct_mutex);
4726         }
4727
4728         /* Let userspace switch the overlay on again. In most cases userspace
4729          * has to recompute where to put it anyway.
4730          */
4731 }
4732
4733 /**
4734  * intel_post_enable_primary - Perform operations after enabling primary plane
4735  * @crtc: the CRTC whose primary plane was just enabled
4736  *
4737  * Performs potentially sleeping operations that must be done after the primary
4738  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4739  * called due to an explicit primary plane update, or due to an implicit
4740  * re-enable that is caused when a sprite plane is updated to no longer
4741  * completely hide the primary plane.
4742  */
4743 static void
4744 intel_post_enable_primary(struct drm_crtc *crtc)
4745 {
4746         struct drm_device *dev = crtc->dev;
4747         struct drm_i915_private *dev_priv = dev->dev_private;
4748         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4749         int pipe = intel_crtc->pipe;
4750
4751         /*
4752          * BDW signals flip done immediately if the plane
4753          * is disabled, even if the plane enable is already
4754          * armed to occur at the next vblank :(
4755          */
4756         if (IS_BROADWELL(dev))
4757                 intel_wait_for_vblank(dev, pipe);
4758
4759         /*
4760          * FIXME IPS should be fine as long as one plane is
4761          * enabled, but in practice it seems to have problems
4762          * when going from primary only to sprite only and vice
4763          * versa.
4764          */
4765         hsw_enable_ips(intel_crtc);
4766
4767         mutex_lock(&dev->struct_mutex);
4768         intel_fbc_update(dev);
4769         mutex_unlock(&dev->struct_mutex);
4770
4771         /*
4772          * Gen2 reports pipe underruns whenever all planes are disabled.
4773          * So don't enable underrun reporting before at least some planes
4774          * are enabled.
4775          * FIXME: Need to fix the logic to work when we turn off all planes
4776          * but leave the pipe running.
4777          */
4778         if (IS_GEN2(dev))
4779                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4780
4781         /* Underruns don't raise interrupts, so check manually. */
4782         if (HAS_GMCH_DISPLAY(dev))
4783                 i9xx_check_fifo_underruns(dev_priv);
4784 }
4785
4786 /**
4787  * intel_pre_disable_primary - Perform operations before disabling primary plane
4788  * @crtc: the CRTC whose primary plane is to be disabled
4789  *
4790  * Performs potentially sleeping operations that must be done before the
4791  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4792  * be called due to an explicit primary plane update, or due to an implicit
4793  * disable that is caused when a sprite plane completely hides the primary
4794  * plane.
4795  */
4796 static void
4797 intel_pre_disable_primary(struct drm_crtc *crtc)
4798 {
4799         struct drm_device *dev = crtc->dev;
4800         struct drm_i915_private *dev_priv = dev->dev_private;
4801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4802         int pipe = intel_crtc->pipe;
4803
4804         /*
4805          * Gen2 reports pipe underruns whenever all planes are disabled.
4806          * So diasble underrun reporting before all the planes get disabled.
4807          * FIXME: Need to fix the logic to work when we turn off all planes
4808          * but leave the pipe running.
4809          */
4810         if (IS_GEN2(dev))
4811                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4812
4813         /*
4814          * Vblank time updates from the shadow to live plane control register
4815          * are blocked if the memory self-refresh mode is active at that
4816          * moment. So to make sure the plane gets truly disabled, disable
4817          * first the self-refresh mode. The self-refresh enable bit in turn
4818          * will be checked/applied by the HW only at the next frame start
4819          * event which is after the vblank start event, so we need to have a
4820          * wait-for-vblank between disabling the plane and the pipe.
4821          */
4822         if (HAS_GMCH_DISPLAY(dev))
4823                 intel_set_memory_cxsr(dev_priv, false);
4824
4825         mutex_lock(&dev->struct_mutex);
4826         if (dev_priv->fbc.crtc == intel_crtc)
4827                 intel_fbc_disable(dev);
4828         mutex_unlock(&dev->struct_mutex);
4829
4830         /*
4831          * FIXME IPS should be fine as long as one plane is
4832          * enabled, but in practice it seems to have problems
4833          * when going from primary only to sprite only and vice
4834          * versa.
4835          */
4836         hsw_disable_ips(intel_crtc);
4837 }
4838
4839 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4840 {
4841         intel_enable_primary_hw_plane(crtc->primary, crtc);
4842         intel_enable_sprite_planes(crtc);
4843         intel_crtc_update_cursor(crtc, true);
4844
4845         intel_post_enable_primary(crtc);
4846 }
4847
4848 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4849 {
4850         struct drm_device *dev = crtc->dev;
4851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4852         struct intel_plane *intel_plane;
4853         int pipe = intel_crtc->pipe;
4854
4855         intel_crtc_wait_for_pending_flips(crtc);
4856
4857         intel_pre_disable_primary(crtc);
4858
4859         intel_crtc_dpms_overlay_disable(intel_crtc);
4860         for_each_intel_plane(dev, intel_plane) {
4861                 if (intel_plane->pipe == pipe) {
4862                         struct drm_crtc *from = intel_plane->base.crtc;
4863
4864                         intel_plane->disable_plane(&intel_plane->base,
4865                                                    from ?: crtc, true);
4866                 }
4867         }
4868
4869         /*
4870          * FIXME: Once we grow proper nuclear flip support out of this we need
4871          * to compute the mask of flip planes precisely. For the time being
4872          * consider this a flip to a NULL plane.
4873          */
4874         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4875 }
4876
4877 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4878 {
4879         struct drm_device *dev = crtc->dev;
4880         struct drm_i915_private *dev_priv = dev->dev_private;
4881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4882         struct intel_encoder *encoder;
4883         int pipe = intel_crtc->pipe;
4884
4885         WARN_ON(!crtc->state->enable);
4886
4887         if (intel_crtc->active)
4888                 return;
4889
4890         if (intel_crtc->config->has_pch_encoder)
4891                 intel_prepare_shared_dpll(intel_crtc);
4892
4893         if (intel_crtc->config->has_dp_encoder)
4894                 intel_dp_set_m_n(intel_crtc, M1_N1);
4895
4896         intel_set_pipe_timings(intel_crtc);
4897
4898         if (intel_crtc->config->has_pch_encoder) {
4899                 intel_cpu_transcoder_set_m_n(intel_crtc,
4900                                      &intel_crtc->config->fdi_m_n, NULL);
4901         }
4902
4903         ironlake_set_pipeconf(crtc);
4904
4905         intel_crtc->active = true;
4906
4907         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4908         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4909
4910         for_each_encoder_on_crtc(dev, crtc, encoder)
4911                 if (encoder->pre_enable)
4912                         encoder->pre_enable(encoder);
4913
4914         if (intel_crtc->config->has_pch_encoder) {
4915                 /* Note: FDI PLL enabling _must_ be done before we enable the
4916                  * cpu pipes, hence this is separate from all the other fdi/pch
4917                  * enabling. */
4918                 ironlake_fdi_pll_enable(intel_crtc);
4919         } else {
4920                 assert_fdi_tx_disabled(dev_priv, pipe);
4921                 assert_fdi_rx_disabled(dev_priv, pipe);
4922         }
4923
4924         ironlake_pfit_enable(intel_crtc);
4925
4926         /*
4927          * On ILK+ LUT must be loaded before the pipe is running but with
4928          * clocks enabled
4929          */
4930         intel_crtc_load_lut(crtc);
4931
4932         intel_update_watermarks(crtc);
4933         intel_enable_pipe(intel_crtc);
4934
4935         if (intel_crtc->config->has_pch_encoder)
4936                 ironlake_pch_enable(crtc);
4937
4938         assert_vblank_disabled(crtc);
4939         drm_crtc_vblank_on(crtc);
4940
4941         for_each_encoder_on_crtc(dev, crtc, encoder)
4942                 encoder->enable(encoder);
4943
4944         if (HAS_PCH_CPT(dev))
4945                 cpt_verify_modeset(dev, intel_crtc->pipe);
4946 }
4947
4948 /* IPS only exists on ULT machines and is tied to pipe A. */
4949 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4950 {
4951         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4952 }
4953
4954 /*
4955  * This implements the workaround described in the "notes" section of the mode
4956  * set sequence documentation. When going from no pipes or single pipe to
4957  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4958  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4959  */
4960 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4961 {
4962         struct drm_device *dev = crtc->base.dev;
4963         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4964
4965         /* We want to get the other_active_crtc only if there's only 1 other
4966          * active crtc. */
4967         for_each_intel_crtc(dev, crtc_it) {
4968                 if (!crtc_it->active || crtc_it == crtc)
4969                         continue;
4970
4971                 if (other_active_crtc)
4972                         return;
4973
4974                 other_active_crtc = crtc_it;
4975         }
4976         if (!other_active_crtc)
4977                 return;
4978
4979         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4980         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4981 }
4982
4983 static void haswell_crtc_enable(struct drm_crtc *crtc)
4984 {
4985         struct drm_device *dev = crtc->dev;
4986         struct drm_i915_private *dev_priv = dev->dev_private;
4987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4988         struct intel_encoder *encoder;
4989         int pipe = intel_crtc->pipe;
4990
4991         WARN_ON(!crtc->state->enable);
4992
4993         if (intel_crtc->active)
4994                 return;
4995
4996         if (intel_crtc_to_shared_dpll(intel_crtc))
4997                 intel_enable_shared_dpll(intel_crtc);
4998
4999         if (intel_crtc->config->has_dp_encoder)
5000                 intel_dp_set_m_n(intel_crtc, M1_N1);
5001
5002         intel_set_pipe_timings(intel_crtc);
5003
5004         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5005                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5006                            intel_crtc->config->pixel_multiplier - 1);
5007         }
5008
5009         if (intel_crtc->config->has_pch_encoder) {
5010                 intel_cpu_transcoder_set_m_n(intel_crtc,
5011                                      &intel_crtc->config->fdi_m_n, NULL);
5012         }
5013
5014         haswell_set_pipeconf(crtc);
5015
5016         intel_set_pipe_csc(crtc);
5017
5018         intel_crtc->active = true;
5019
5020         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5021         for_each_encoder_on_crtc(dev, crtc, encoder)
5022                 if (encoder->pre_enable)
5023                         encoder->pre_enable(encoder);
5024
5025         if (intel_crtc->config->has_pch_encoder) {
5026                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5027                                                       true);
5028                 dev_priv->display.fdi_link_train(crtc);
5029         }
5030
5031         intel_ddi_enable_pipe_clock(intel_crtc);
5032
5033         if (INTEL_INFO(dev)->gen == 9)
5034                 skylake_pfit_update(intel_crtc, 1);
5035         else if (INTEL_INFO(dev)->gen < 9)
5036                 ironlake_pfit_enable(intel_crtc);
5037         else
5038                 MISSING_CASE(INTEL_INFO(dev)->gen);
5039
5040         /*
5041          * On ILK+ LUT must be loaded before the pipe is running but with
5042          * clocks enabled
5043          */
5044         intel_crtc_load_lut(crtc);
5045
5046         intel_ddi_set_pipe_settings(crtc);
5047         intel_ddi_enable_transcoder_func(crtc);
5048
5049         intel_update_watermarks(crtc);
5050         intel_enable_pipe(intel_crtc);
5051
5052         if (intel_crtc->config->has_pch_encoder)
5053                 lpt_pch_enable(crtc);
5054
5055         if (intel_crtc->config->dp_encoder_is_mst)
5056                 intel_ddi_set_vc_payload_alloc(crtc, true);
5057
5058         assert_vblank_disabled(crtc);
5059         drm_crtc_vblank_on(crtc);
5060
5061         for_each_encoder_on_crtc(dev, crtc, encoder) {
5062                 encoder->enable(encoder);
5063                 intel_opregion_notify_encoder(encoder, true);
5064         }
5065
5066         /* If we change the relative order between pipe/planes enabling, we need
5067          * to change the workaround. */
5068         haswell_mode_set_planes_workaround(intel_crtc);
5069 }
5070
5071 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5072 {
5073         struct drm_device *dev = crtc->base.dev;
5074         struct drm_i915_private *dev_priv = dev->dev_private;
5075         int pipe = crtc->pipe;
5076
5077         /* To avoid upsetting the power well on haswell only disable the pfit if
5078          * it's in use. The hw state code will make sure we get this right. */
5079         if (crtc->config->pch_pfit.enabled) {
5080                 I915_WRITE(PF_CTL(pipe), 0);
5081                 I915_WRITE(PF_WIN_POS(pipe), 0);
5082                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5083         }
5084 }
5085
5086 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5087 {
5088         struct drm_device *dev = crtc->dev;
5089         struct drm_i915_private *dev_priv = dev->dev_private;
5090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5091         struct intel_encoder *encoder;
5092         int pipe = intel_crtc->pipe;
5093         u32 reg, temp;
5094
5095         if (!intel_crtc->active)
5096                 return;
5097
5098         for_each_encoder_on_crtc(dev, crtc, encoder)
5099                 encoder->disable(encoder);
5100
5101         drm_crtc_vblank_off(crtc);
5102         assert_vblank_disabled(crtc);
5103
5104         if (intel_crtc->config->has_pch_encoder)
5105                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5106
5107         intel_disable_pipe(intel_crtc);
5108
5109         ironlake_pfit_disable(intel_crtc);
5110
5111         for_each_encoder_on_crtc(dev, crtc, encoder)
5112                 if (encoder->post_disable)
5113                         encoder->post_disable(encoder);
5114
5115         if (intel_crtc->config->has_pch_encoder) {
5116                 ironlake_fdi_disable(crtc);
5117
5118                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5119
5120                 if (HAS_PCH_CPT(dev)) {
5121                         /* disable TRANS_DP_CTL */
5122                         reg = TRANS_DP_CTL(pipe);
5123                         temp = I915_READ(reg);
5124                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5125                                   TRANS_DP_PORT_SEL_MASK);
5126                         temp |= TRANS_DP_PORT_SEL_NONE;
5127                         I915_WRITE(reg, temp);
5128
5129                         /* disable DPLL_SEL */
5130                         temp = I915_READ(PCH_DPLL_SEL);
5131                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5132                         I915_WRITE(PCH_DPLL_SEL, temp);
5133                 }
5134
5135                 /* disable PCH DPLL */
5136                 intel_disable_shared_dpll(intel_crtc);
5137
5138                 ironlake_fdi_pll_disable(intel_crtc);
5139         }
5140
5141         intel_crtc->active = false;
5142         intel_update_watermarks(crtc);
5143
5144         mutex_lock(&dev->struct_mutex);
5145         intel_fbc_update(dev);
5146         mutex_unlock(&dev->struct_mutex);
5147 }
5148
5149 static void haswell_crtc_disable(struct drm_crtc *crtc)
5150 {
5151         struct drm_device *dev = crtc->dev;
5152         struct drm_i915_private *dev_priv = dev->dev_private;
5153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5154         struct intel_encoder *encoder;
5155         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5156
5157         if (!intel_crtc->active)
5158                 return;
5159
5160         for_each_encoder_on_crtc(dev, crtc, encoder) {
5161                 intel_opregion_notify_encoder(encoder, false);
5162                 encoder->disable(encoder);
5163         }
5164
5165         drm_crtc_vblank_off(crtc);
5166         assert_vblank_disabled(crtc);
5167
5168         if (intel_crtc->config->has_pch_encoder)
5169                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5170                                                       false);
5171         intel_disable_pipe(intel_crtc);
5172
5173         if (intel_crtc->config->dp_encoder_is_mst)
5174                 intel_ddi_set_vc_payload_alloc(crtc, false);
5175
5176         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5177
5178         if (INTEL_INFO(dev)->gen == 9)
5179                 skylake_pfit_update(intel_crtc, 0);
5180         else if (INTEL_INFO(dev)->gen < 9)
5181                 ironlake_pfit_disable(intel_crtc);
5182         else
5183                 MISSING_CASE(INTEL_INFO(dev)->gen);
5184
5185         intel_ddi_disable_pipe_clock(intel_crtc);
5186
5187         if (intel_crtc->config->has_pch_encoder) {
5188                 lpt_disable_pch_transcoder(dev_priv);
5189                 intel_ddi_fdi_disable(crtc);
5190         }
5191
5192         for_each_encoder_on_crtc(dev, crtc, encoder)
5193                 if (encoder->post_disable)
5194                         encoder->post_disable(encoder);
5195
5196         intel_crtc->active = false;
5197         intel_update_watermarks(crtc);
5198
5199         mutex_lock(&dev->struct_mutex);
5200         intel_fbc_update(dev);
5201         mutex_unlock(&dev->struct_mutex);
5202
5203         if (intel_crtc_to_shared_dpll(intel_crtc))
5204                 intel_disable_shared_dpll(intel_crtc);
5205 }
5206
5207 static void ironlake_crtc_off(struct drm_crtc *crtc)
5208 {
5209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5210         intel_put_shared_dpll(intel_crtc);
5211 }
5212
5213
5214 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5215 {
5216         struct drm_device *dev = crtc->base.dev;
5217         struct drm_i915_private *dev_priv = dev->dev_private;
5218         struct intel_crtc_state *pipe_config = crtc->config;
5219
5220         if (!pipe_config->gmch_pfit.control)
5221                 return;
5222
5223         /*
5224          * The panel fitter should only be adjusted whilst the pipe is disabled,
5225          * according to register description and PRM.
5226          */
5227         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5228         assert_pipe_disabled(dev_priv, crtc->pipe);
5229
5230         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5231         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5232
5233         /* Border color in case we don't scale up to the full screen. Black by
5234          * default, change to something else for debugging. */
5235         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5236 }
5237
5238 static enum intel_display_power_domain port_to_power_domain(enum port port)
5239 {
5240         switch (port) {
5241         case PORT_A:
5242                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5243         case PORT_B:
5244                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5245         case PORT_C:
5246                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5247         case PORT_D:
5248                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5249         default:
5250                 WARN_ON_ONCE(1);
5251                 return POWER_DOMAIN_PORT_OTHER;
5252         }
5253 }
5254
5255 #define for_each_power_domain(domain, mask)                             \
5256         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5257                 if ((1 << (domain)) & (mask))
5258
5259 enum intel_display_power_domain
5260 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5261 {
5262         struct drm_device *dev = intel_encoder->base.dev;
5263         struct intel_digital_port *intel_dig_port;
5264
5265         switch (intel_encoder->type) {
5266         case INTEL_OUTPUT_UNKNOWN:
5267                 /* Only DDI platforms should ever use this output type */
5268                 WARN_ON_ONCE(!HAS_DDI(dev));
5269         case INTEL_OUTPUT_DISPLAYPORT:
5270         case INTEL_OUTPUT_HDMI:
5271         case INTEL_OUTPUT_EDP:
5272                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5273                 return port_to_power_domain(intel_dig_port->port);
5274         case INTEL_OUTPUT_DP_MST:
5275                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5276                 return port_to_power_domain(intel_dig_port->port);
5277         case INTEL_OUTPUT_ANALOG:
5278                 return POWER_DOMAIN_PORT_CRT;
5279         case INTEL_OUTPUT_DSI:
5280                 return POWER_DOMAIN_PORT_DSI;
5281         default:
5282                 return POWER_DOMAIN_PORT_OTHER;
5283         }
5284 }
5285
5286 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5287 {
5288         struct drm_device *dev = crtc->dev;
5289         struct intel_encoder *intel_encoder;
5290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5291         enum pipe pipe = intel_crtc->pipe;
5292         unsigned long mask;
5293         enum transcoder transcoder;
5294
5295         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5296
5297         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5298         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5299         if (intel_crtc->config->pch_pfit.enabled ||
5300             intel_crtc->config->pch_pfit.force_thru)
5301                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5302
5303         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5304                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5305
5306         return mask;
5307 }
5308
5309 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5310 {
5311         struct drm_device *dev = state->dev;
5312         struct drm_i915_private *dev_priv = dev->dev_private;
5313         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5314         struct intel_crtc *crtc;
5315
5316         /*
5317          * First get all needed power domains, then put all unneeded, to avoid
5318          * any unnecessary toggling of the power wells.
5319          */
5320         for_each_intel_crtc(dev, crtc) {
5321                 enum intel_display_power_domain domain;
5322
5323                 if (!crtc->base.state->enable)
5324                         continue;
5325
5326                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5327
5328                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5329                         intel_display_power_get(dev_priv, domain);
5330         }
5331
5332         if (dev_priv->display.modeset_global_resources)
5333                 dev_priv->display.modeset_global_resources(state);
5334
5335         for_each_intel_crtc(dev, crtc) {
5336                 enum intel_display_power_domain domain;
5337
5338                 for_each_power_domain(domain, crtc->enabled_power_domains)
5339                         intel_display_power_put(dev_priv, domain);
5340
5341                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5342         }
5343
5344         intel_display_set_init_power(dev_priv, false);
5345 }
5346
5347 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5348 {
5349         struct drm_i915_private *dev_priv = dev->dev_private;
5350         uint32_t divider;
5351         uint32_t ratio;
5352         uint32_t current_freq;
5353         int ret;
5354
5355         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5356         switch (frequency) {
5357         case 144000:
5358                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5359                 ratio = BXT_DE_PLL_RATIO(60);
5360                 break;
5361         case 288000:
5362                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5363                 ratio = BXT_DE_PLL_RATIO(60);
5364                 break;
5365         case 384000:
5366                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5367                 ratio = BXT_DE_PLL_RATIO(60);
5368                 break;
5369         case 576000:
5370                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5371                 ratio = BXT_DE_PLL_RATIO(60);
5372                 break;
5373         case 624000:
5374                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5375                 ratio = BXT_DE_PLL_RATIO(65);
5376                 break;
5377         case 19200:
5378                 /*
5379                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5380                  * to suppress GCC warning.
5381                  */
5382                 ratio = 0;
5383                 divider = 0;
5384                 break;
5385         default:
5386                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5387
5388                 return;
5389         }
5390
5391         mutex_lock(&dev_priv->rps.hw_lock);
5392         /* Inform power controller of upcoming frequency change */
5393         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5394                                       0x80000000);
5395         mutex_unlock(&dev_priv->rps.hw_lock);
5396
5397         if (ret) {
5398                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5399                           ret, frequency);
5400                 return;
5401         }
5402
5403         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5404         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5405         current_freq = current_freq * 500 + 1000;
5406
5407         /*
5408          * DE PLL has to be disabled when
5409          * - setting to 19.2MHz (bypass, PLL isn't used)
5410          * - before setting to 624MHz (PLL needs toggling)
5411          * - before setting to any frequency from 624MHz (PLL needs toggling)
5412          */
5413         if (frequency == 19200 || frequency == 624000 ||
5414             current_freq == 624000) {
5415                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5416                 /* Timeout 200us */
5417                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5418                              1))
5419                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5420         }
5421
5422         if (frequency != 19200) {
5423                 uint32_t val;
5424
5425                 val = I915_READ(BXT_DE_PLL_CTL);
5426                 val &= ~BXT_DE_PLL_RATIO_MASK;
5427                 val |= ratio;
5428                 I915_WRITE(BXT_DE_PLL_CTL, val);
5429
5430                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5431                 /* Timeout 200us */
5432                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5433                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5434
5435                 val = I915_READ(CDCLK_CTL);
5436                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5437                 val |= divider;
5438                 /*
5439                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5440                  * enable otherwise.
5441                  */
5442                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5443                 if (frequency >= 500000)
5444                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5445
5446                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5447                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5448                 val |= (frequency - 1000) / 500;
5449                 I915_WRITE(CDCLK_CTL, val);
5450         }
5451
5452         mutex_lock(&dev_priv->rps.hw_lock);
5453         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5454                                       DIV_ROUND_UP(frequency, 25000));
5455         mutex_unlock(&dev_priv->rps.hw_lock);
5456
5457         if (ret) {
5458                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5459                           ret, frequency);
5460                 return;
5461         }
5462
5463         dev_priv->cdclk_freq = frequency;
5464 }
5465
5466 void broxton_init_cdclk(struct drm_device *dev)
5467 {
5468         struct drm_i915_private *dev_priv = dev->dev_private;
5469         uint32_t val;
5470
5471         /*
5472          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5473          * or else the reset will hang because there is no PCH to respond.
5474          * Move the handshake programming to initialization sequence.
5475          * Previously was left up to BIOS.
5476          */
5477         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5478         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5479         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5480
5481         /* Enable PG1 for cdclk */
5482         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5483
5484         /* check if cd clock is enabled */
5485         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5486                 DRM_DEBUG_KMS("Display already initialized\n");
5487                 return;
5488         }
5489
5490         /*
5491          * FIXME:
5492          * - The initial CDCLK needs to be read from VBT.
5493          *   Need to make this change after VBT has changes for BXT.
5494          * - check if setting the max (or any) cdclk freq is really necessary
5495          *   here, it belongs to modeset time
5496          */
5497         broxton_set_cdclk(dev, 624000);
5498
5499         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5500         POSTING_READ(DBUF_CTL);
5501
5502         udelay(10);
5503
5504         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5505                 DRM_ERROR("DBuf power enable timeout!\n");
5506 }
5507
5508 void broxton_uninit_cdclk(struct drm_device *dev)
5509 {
5510         struct drm_i915_private *dev_priv = dev->dev_private;
5511
5512         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5513         POSTING_READ(DBUF_CTL);
5514
5515         udelay(10);
5516
5517         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5518                 DRM_ERROR("DBuf power disable timeout!\n");
5519
5520         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5521         broxton_set_cdclk(dev, 19200);
5522
5523         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5524 }
5525
5526 /* returns HPLL frequency in kHz */
5527 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5528 {
5529         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5530
5531         /* Obtain SKU information */
5532         mutex_lock(&dev_priv->dpio_lock);
5533         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5534                 CCK_FUSE_HPLL_FREQ_MASK;
5535         mutex_unlock(&dev_priv->dpio_lock);
5536
5537         return vco_freq[hpll_freq] * 1000;
5538 }
5539
5540 static void vlv_update_cdclk(struct drm_device *dev)
5541 {
5542         struct drm_i915_private *dev_priv = dev->dev_private;
5543
5544         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5545         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5546                          dev_priv->cdclk_freq);
5547
5548         /*
5549          * Program the gmbus_freq based on the cdclk frequency.
5550          * BSpec erroneously claims we should aim for 4MHz, but
5551          * in fact 1MHz is the correct frequency.
5552          */
5553         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5554 }
5555
5556 /* Adjust CDclk dividers to allow high res or save power if possible */
5557 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5558 {
5559         struct drm_i915_private *dev_priv = dev->dev_private;
5560         u32 val, cmd;
5561
5562         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5563                                         != dev_priv->cdclk_freq);
5564
5565         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5566                 cmd = 2;
5567         else if (cdclk == 266667)
5568                 cmd = 1;
5569         else
5570                 cmd = 0;
5571
5572         mutex_lock(&dev_priv->rps.hw_lock);
5573         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5574         val &= ~DSPFREQGUAR_MASK;
5575         val |= (cmd << DSPFREQGUAR_SHIFT);
5576         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5577         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5578                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5579                      50)) {
5580                 DRM_ERROR("timed out waiting for CDclk change\n");
5581         }
5582         mutex_unlock(&dev_priv->rps.hw_lock);
5583
5584         if (cdclk == 400000) {
5585                 u32 divider;
5586
5587                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5588
5589                 mutex_lock(&dev_priv->dpio_lock);
5590                 /* adjust cdclk divider */
5591                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5592                 val &= ~DISPLAY_FREQUENCY_VALUES;
5593                 val |= divider;
5594                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5595
5596                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5597                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5598                              50))
5599                         DRM_ERROR("timed out waiting for CDclk change\n");
5600                 mutex_unlock(&dev_priv->dpio_lock);
5601         }
5602
5603         mutex_lock(&dev_priv->dpio_lock);
5604         /* adjust self-refresh exit latency value */
5605         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5606         val &= ~0x7f;
5607
5608         /*
5609          * For high bandwidth configs, we set a higher latency in the bunit
5610          * so that the core display fetch happens in time to avoid underruns.
5611          */
5612         if (cdclk == 400000)
5613                 val |= 4500 / 250; /* 4.5 usec */
5614         else
5615                 val |= 3000 / 250; /* 3.0 usec */
5616         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5617         mutex_unlock(&dev_priv->dpio_lock);
5618
5619         vlv_update_cdclk(dev);
5620 }
5621
5622 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5623 {
5624         struct drm_i915_private *dev_priv = dev->dev_private;
5625         u32 val, cmd;
5626
5627         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5628                                                 != dev_priv->cdclk_freq);
5629
5630         switch (cdclk) {
5631         case 333333:
5632         case 320000:
5633         case 266667:
5634         case 200000:
5635                 break;
5636         default:
5637                 MISSING_CASE(cdclk);
5638                 return;
5639         }
5640
5641         /*
5642          * Specs are full of misinformation, but testing on actual
5643          * hardware has shown that we just need to write the desired
5644          * CCK divider into the Punit register.
5645          */
5646         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5647
5648         mutex_lock(&dev_priv->rps.hw_lock);
5649         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5650         val &= ~DSPFREQGUAR_MASK_CHV;
5651         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5652         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5653         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5654                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5655                      50)) {
5656                 DRM_ERROR("timed out waiting for CDclk change\n");
5657         }
5658         mutex_unlock(&dev_priv->rps.hw_lock);
5659
5660         vlv_update_cdclk(dev);
5661 }
5662
5663 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5664                                  int max_pixclk)
5665 {
5666         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5667         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5668
5669         /*
5670          * Really only a few cases to deal with, as only 4 CDclks are supported:
5671          *   200MHz
5672          *   267MHz
5673          *   320/333MHz (depends on HPLL freq)
5674          *   400MHz (VLV only)
5675          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5676          * of the lower bin and adjust if needed.
5677          *
5678          * We seem to get an unstable or solid color picture at 200MHz.
5679          * Not sure what's wrong. For now use 200MHz only when all pipes
5680          * are off.
5681          */
5682         if (!IS_CHERRYVIEW(dev_priv) &&
5683             max_pixclk > freq_320*limit/100)
5684                 return 400000;
5685         else if (max_pixclk > 266667*limit/100)
5686                 return freq_320;
5687         else if (max_pixclk > 0)
5688                 return 266667;
5689         else
5690                 return 200000;
5691 }
5692
5693 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5694                               int max_pixclk)
5695 {
5696         /*
5697          * FIXME:
5698          * - remove the guardband, it's not needed on BXT
5699          * - set 19.2MHz bypass frequency if there are no active pipes
5700          */
5701         if (max_pixclk > 576000*9/10)
5702                 return 624000;
5703         else if (max_pixclk > 384000*9/10)
5704                 return 576000;
5705         else if (max_pixclk > 288000*9/10)
5706                 return 384000;
5707         else if (max_pixclk > 144000*9/10)
5708                 return 288000;
5709         else
5710                 return 144000;
5711 }
5712
5713 /* Compute the max pixel clock for new configuration. Uses atomic state if
5714  * that's non-NULL, look at current state otherwise. */
5715 static int intel_mode_max_pixclk(struct drm_device *dev,
5716                                  struct drm_atomic_state *state)
5717 {
5718         struct intel_crtc *intel_crtc;
5719         struct intel_crtc_state *crtc_state;
5720         int max_pixclk = 0;
5721
5722         for_each_intel_crtc(dev, intel_crtc) {
5723                 if (state)
5724                         crtc_state =
5725                                 intel_atomic_get_crtc_state(state, intel_crtc);
5726                 else
5727                         crtc_state = intel_crtc->config;
5728                 if (IS_ERR(crtc_state))
5729                         return PTR_ERR(crtc_state);
5730
5731                 if (!crtc_state->base.enable)
5732                         continue;
5733
5734                 max_pixclk = max(max_pixclk,
5735                                  crtc_state->base.adjusted_mode.crtc_clock);
5736         }
5737
5738         return max_pixclk;
5739 }
5740
5741 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5742 {
5743         struct drm_i915_private *dev_priv = to_i915(state->dev);
5744         struct drm_crtc *crtc;
5745         struct drm_crtc_state *crtc_state;
5746         int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5747         int cdclk, i;
5748
5749         if (max_pixclk < 0)
5750                 return max_pixclk;
5751
5752         if (IS_VALLEYVIEW(dev_priv))
5753                 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5754         else
5755                 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5756
5757         if (cdclk == dev_priv->cdclk_freq)
5758                 return 0;
5759
5760         /* add all active pipes to the state */
5761         for_each_crtc(state->dev, crtc) {
5762                 if (!crtc->state->enable)
5763                         continue;
5764
5765                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5766                 if (IS_ERR(crtc_state))
5767                         return PTR_ERR(crtc_state);
5768         }
5769
5770         /* disable/enable all currently active pipes while we change cdclk */
5771         for_each_crtc_in_state(state, crtc, crtc_state, i)
5772                 if (crtc_state->enable)
5773                         crtc_state->mode_changed = true;
5774
5775         return 0;
5776 }
5777
5778 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5779 {
5780         unsigned int credits, default_credits;
5781
5782         if (IS_CHERRYVIEW(dev_priv))
5783                 default_credits = PFI_CREDIT(12);
5784         else
5785                 default_credits = PFI_CREDIT(8);
5786
5787         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5788                 /* CHV suggested value is 31 or 63 */
5789                 if (IS_CHERRYVIEW(dev_priv))
5790                         credits = PFI_CREDIT_31;
5791                 else
5792                         credits = PFI_CREDIT(15);
5793         } else {
5794                 credits = default_credits;
5795         }
5796
5797         /*
5798          * WA - write default credits before re-programming
5799          * FIXME: should we also set the resend bit here?
5800          */
5801         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5802                    default_credits);
5803
5804         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5805                    credits | PFI_CREDIT_RESEND);
5806
5807         /*
5808          * FIXME is this guaranteed to clear
5809          * immediately or should we poll for it?
5810          */
5811         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5812 }
5813
5814 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5815 {
5816         struct drm_device *dev = old_state->dev;
5817         struct drm_i915_private *dev_priv = dev->dev_private;
5818         int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5819         int req_cdclk;
5820
5821         /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5822          * never fail. */
5823         if (WARN_ON(max_pixclk < 0))
5824                 return;
5825
5826         req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5827
5828         if (req_cdclk != dev_priv->cdclk_freq) {
5829                 /*
5830                  * FIXME: We can end up here with all power domains off, yet
5831                  * with a CDCLK frequency other than the minimum. To account
5832                  * for this take the PIPE-A power domain, which covers the HW
5833                  * blocks needed for the following programming. This can be
5834                  * removed once it's guaranteed that we get here either with
5835                  * the minimum CDCLK set, or the required power domains
5836                  * enabled.
5837                  */
5838                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5839
5840                 if (IS_CHERRYVIEW(dev))
5841                         cherryview_set_cdclk(dev, req_cdclk);
5842                 else
5843                         valleyview_set_cdclk(dev, req_cdclk);
5844
5845                 vlv_program_pfi_credits(dev_priv);
5846
5847                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5848         }
5849 }
5850
5851 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5852 {
5853         struct drm_device *dev = crtc->dev;
5854         struct drm_i915_private *dev_priv = to_i915(dev);
5855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5856         struct intel_encoder *encoder;
5857         int pipe = intel_crtc->pipe;
5858         bool is_dsi;
5859
5860         WARN_ON(!crtc->state->enable);
5861
5862         if (intel_crtc->active)
5863                 return;
5864
5865         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5866
5867         if (!is_dsi) {
5868                 if (IS_CHERRYVIEW(dev))
5869                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5870                 else
5871                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5872         }
5873
5874         if (intel_crtc->config->has_dp_encoder)
5875                 intel_dp_set_m_n(intel_crtc, M1_N1);
5876
5877         intel_set_pipe_timings(intel_crtc);
5878
5879         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5880                 struct drm_i915_private *dev_priv = dev->dev_private;
5881
5882                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5883                 I915_WRITE(CHV_CANVAS(pipe), 0);
5884         }
5885
5886         i9xx_set_pipeconf(intel_crtc);
5887
5888         intel_crtc->active = true;
5889
5890         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5891
5892         for_each_encoder_on_crtc(dev, crtc, encoder)
5893                 if (encoder->pre_pll_enable)
5894                         encoder->pre_pll_enable(encoder);
5895
5896         if (!is_dsi) {
5897                 if (IS_CHERRYVIEW(dev))
5898                         chv_enable_pll(intel_crtc, intel_crtc->config);
5899                 else
5900                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5901         }
5902
5903         for_each_encoder_on_crtc(dev, crtc, encoder)
5904                 if (encoder->pre_enable)
5905                         encoder->pre_enable(encoder);
5906
5907         i9xx_pfit_enable(intel_crtc);
5908
5909         intel_crtc_load_lut(crtc);
5910
5911         intel_update_watermarks(crtc);
5912         intel_enable_pipe(intel_crtc);
5913
5914         assert_vblank_disabled(crtc);
5915         drm_crtc_vblank_on(crtc);
5916
5917         for_each_encoder_on_crtc(dev, crtc, encoder)
5918                 encoder->enable(encoder);
5919 }
5920
5921 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5922 {
5923         struct drm_device *dev = crtc->base.dev;
5924         struct drm_i915_private *dev_priv = dev->dev_private;
5925
5926         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5927         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5928 }
5929
5930 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5931 {
5932         struct drm_device *dev = crtc->dev;
5933         struct drm_i915_private *dev_priv = to_i915(dev);
5934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5935         struct intel_encoder *encoder;
5936         int pipe = intel_crtc->pipe;
5937
5938         WARN_ON(!crtc->state->enable);
5939
5940         if (intel_crtc->active)
5941                 return;
5942
5943         i9xx_set_pll_dividers(intel_crtc);
5944
5945         if (intel_crtc->config->has_dp_encoder)
5946                 intel_dp_set_m_n(intel_crtc, M1_N1);
5947
5948         intel_set_pipe_timings(intel_crtc);
5949
5950         i9xx_set_pipeconf(intel_crtc);
5951
5952         intel_crtc->active = true;
5953
5954         if (!IS_GEN2(dev))
5955                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5956
5957         for_each_encoder_on_crtc(dev, crtc, encoder)
5958                 if (encoder->pre_enable)
5959                         encoder->pre_enable(encoder);
5960
5961         i9xx_enable_pll(intel_crtc);
5962
5963         i9xx_pfit_enable(intel_crtc);
5964
5965         intel_crtc_load_lut(crtc);
5966
5967         intel_update_watermarks(crtc);
5968         intel_enable_pipe(intel_crtc);
5969
5970         assert_vblank_disabled(crtc);
5971         drm_crtc_vblank_on(crtc);
5972
5973         for_each_encoder_on_crtc(dev, crtc, encoder)
5974                 encoder->enable(encoder);
5975 }
5976
5977 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5978 {
5979         struct drm_device *dev = crtc->base.dev;
5980         struct drm_i915_private *dev_priv = dev->dev_private;
5981
5982         if (!crtc->config->gmch_pfit.control)
5983                 return;
5984
5985         assert_pipe_disabled(dev_priv, crtc->pipe);
5986
5987         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5988                          I915_READ(PFIT_CONTROL));
5989         I915_WRITE(PFIT_CONTROL, 0);
5990 }
5991
5992 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5993 {
5994         struct drm_device *dev = crtc->dev;
5995         struct drm_i915_private *dev_priv = dev->dev_private;
5996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5997         struct intel_encoder *encoder;
5998         int pipe = intel_crtc->pipe;
5999
6000         if (!intel_crtc->active)
6001                 return;
6002
6003         /*
6004          * On gen2 planes are double buffered but the pipe isn't, so we must
6005          * wait for planes to fully turn off before disabling the pipe.
6006          * We also need to wait on all gmch platforms because of the
6007          * self-refresh mode constraint explained above.
6008          */
6009         intel_wait_for_vblank(dev, pipe);
6010
6011         for_each_encoder_on_crtc(dev, crtc, encoder)
6012                 encoder->disable(encoder);
6013
6014         drm_crtc_vblank_off(crtc);
6015         assert_vblank_disabled(crtc);
6016
6017         intel_disable_pipe(intel_crtc);
6018
6019         i9xx_pfit_disable(intel_crtc);
6020
6021         for_each_encoder_on_crtc(dev, crtc, encoder)
6022                 if (encoder->post_disable)
6023                         encoder->post_disable(encoder);
6024
6025         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6026                 if (IS_CHERRYVIEW(dev))
6027                         chv_disable_pll(dev_priv, pipe);
6028                 else if (IS_VALLEYVIEW(dev))
6029                         vlv_disable_pll(dev_priv, pipe);
6030                 else
6031                         i9xx_disable_pll(intel_crtc);
6032         }
6033
6034         if (!IS_GEN2(dev))
6035                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6036
6037         intel_crtc->active = false;
6038         intel_update_watermarks(crtc);
6039
6040         mutex_lock(&dev->struct_mutex);
6041         intel_fbc_update(dev);
6042         mutex_unlock(&dev->struct_mutex);
6043 }
6044
6045 static void i9xx_crtc_off(struct drm_crtc *crtc)
6046 {
6047 }
6048
6049 /* Master function to enable/disable CRTC and corresponding power wells */
6050 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6051 {
6052         struct drm_device *dev = crtc->dev;
6053         struct drm_i915_private *dev_priv = dev->dev_private;
6054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6055         enum intel_display_power_domain domain;
6056         unsigned long domains;
6057
6058         if (enable) {
6059                 if (!intel_crtc->active) {
6060                         domains = get_crtc_power_domains(crtc);
6061                         for_each_power_domain(domain, domains)
6062                                 intel_display_power_get(dev_priv, domain);
6063                         intel_crtc->enabled_power_domains = domains;
6064
6065                         dev_priv->display.crtc_enable(crtc);
6066                         intel_crtc_enable_planes(crtc);
6067                 }
6068         } else {
6069                 if (intel_crtc->active) {
6070                         intel_crtc_disable_planes(crtc);
6071                         dev_priv->display.crtc_disable(crtc);
6072
6073                         domains = intel_crtc->enabled_power_domains;
6074                         for_each_power_domain(domain, domains)
6075                                 intel_display_power_put(dev_priv, domain);
6076                         intel_crtc->enabled_power_domains = 0;
6077                 }
6078         }
6079 }
6080
6081 /**
6082  * Sets the power management mode of the pipe and plane.
6083  */
6084 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6085 {
6086         struct drm_device *dev = crtc->dev;
6087         struct intel_encoder *intel_encoder;
6088         bool enable = false;
6089
6090         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6091                 enable |= intel_encoder->connectors_active;
6092
6093         intel_crtc_control(crtc, enable);
6094
6095         crtc->state->active = enable;
6096 }
6097
6098 static void intel_crtc_disable(struct drm_crtc *crtc)
6099 {
6100         struct drm_device *dev = crtc->dev;
6101         struct drm_connector *connector;
6102         struct drm_i915_private *dev_priv = dev->dev_private;
6103
6104         /* crtc should still be enabled when we disable it. */
6105         WARN_ON(!crtc->state->enable);
6106
6107         intel_crtc_disable_planes(crtc);
6108         dev_priv->display.crtc_disable(crtc);
6109         dev_priv->display.off(crtc);
6110
6111         drm_plane_helper_disable(crtc->primary);
6112
6113         /* Update computed state. */
6114         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6115                 if (!connector->encoder || !connector->encoder->crtc)
6116                         continue;
6117
6118                 if (connector->encoder->crtc != crtc)
6119                         continue;
6120
6121                 connector->dpms = DRM_MODE_DPMS_OFF;
6122                 to_intel_encoder(connector->encoder)->connectors_active = false;
6123         }
6124 }
6125
6126 void intel_encoder_destroy(struct drm_encoder *encoder)
6127 {
6128         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6129
6130         drm_encoder_cleanup(encoder);
6131         kfree(intel_encoder);
6132 }
6133
6134 /* Simple dpms helper for encoders with just one connector, no cloning and only
6135  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6136  * state of the entire output pipe. */
6137 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6138 {
6139         if (mode == DRM_MODE_DPMS_ON) {
6140                 encoder->connectors_active = true;
6141
6142                 intel_crtc_update_dpms(encoder->base.crtc);
6143         } else {
6144                 encoder->connectors_active = false;
6145
6146                 intel_crtc_update_dpms(encoder->base.crtc);
6147         }
6148 }
6149
6150 /* Cross check the actual hw state with our own modeset state tracking (and it's
6151  * internal consistency). */
6152 static void intel_connector_check_state(struct intel_connector *connector)
6153 {
6154         if (connector->get_hw_state(connector)) {
6155                 struct intel_encoder *encoder = connector->encoder;
6156                 struct drm_crtc *crtc;
6157                 bool encoder_enabled;
6158                 enum pipe pipe;
6159
6160                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6161                               connector->base.base.id,
6162                               connector->base.name);
6163
6164                 /* there is no real hw state for MST connectors */
6165                 if (connector->mst_port)
6166                         return;
6167
6168                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6169                      "wrong connector dpms state\n");
6170                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6171                      "active connector not linked to encoder\n");
6172
6173                 if (encoder) {
6174                         I915_STATE_WARN(!encoder->connectors_active,
6175                              "encoder->connectors_active not set\n");
6176
6177                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6178                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6179                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
6180                                 return;
6181
6182                         crtc = encoder->base.crtc;
6183
6184                         I915_STATE_WARN(!crtc->state->enable,
6185                                         "crtc not enabled\n");
6186                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6187                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6188                              "encoder active on the wrong pipe\n");
6189                 }
6190         }
6191 }
6192
6193 int intel_connector_init(struct intel_connector *connector)
6194 {
6195         struct drm_connector_state *connector_state;
6196
6197         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6198         if (!connector_state)
6199                 return -ENOMEM;
6200
6201         connector->base.state = connector_state;
6202         return 0;
6203 }
6204
6205 struct intel_connector *intel_connector_alloc(void)
6206 {
6207         struct intel_connector *connector;
6208
6209         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6210         if (!connector)
6211                 return NULL;
6212
6213         if (intel_connector_init(connector) < 0) {
6214                 kfree(connector);
6215                 return NULL;
6216         }
6217
6218         return connector;
6219 }
6220
6221 /* Even simpler default implementation, if there's really no special case to
6222  * consider. */
6223 void intel_connector_dpms(struct drm_connector *connector, int mode)
6224 {
6225         /* All the simple cases only support two dpms states. */
6226         if (mode != DRM_MODE_DPMS_ON)
6227                 mode = DRM_MODE_DPMS_OFF;
6228
6229         if (mode == connector->dpms)
6230                 return;
6231
6232         connector->dpms = mode;
6233
6234         /* Only need to change hw state when actually enabled */
6235         if (connector->encoder)
6236                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6237
6238         intel_modeset_check_state(connector->dev);
6239 }
6240
6241 /* Simple connector->get_hw_state implementation for encoders that support only
6242  * one connector and no cloning and hence the encoder state determines the state
6243  * of the connector. */
6244 bool intel_connector_get_hw_state(struct intel_connector *connector)
6245 {
6246         enum pipe pipe = 0;
6247         struct intel_encoder *encoder = connector->encoder;
6248
6249         return encoder->get_hw_state(encoder, &pipe);
6250 }
6251
6252 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6253 {
6254         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6255                 return crtc_state->fdi_lanes;
6256
6257         return 0;
6258 }
6259
6260 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6261                                      struct intel_crtc_state *pipe_config)
6262 {
6263         struct drm_atomic_state *state = pipe_config->base.state;
6264         struct intel_crtc *other_crtc;
6265         struct intel_crtc_state *other_crtc_state;
6266
6267         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6268                       pipe_name(pipe), pipe_config->fdi_lanes);
6269         if (pipe_config->fdi_lanes > 4) {
6270                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6271                               pipe_name(pipe), pipe_config->fdi_lanes);
6272                 return -EINVAL;
6273         }
6274
6275         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6276                 if (pipe_config->fdi_lanes > 2) {
6277                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6278                                       pipe_config->fdi_lanes);
6279                         return -EINVAL;
6280                 } else {
6281                         return 0;
6282                 }
6283         }
6284
6285         if (INTEL_INFO(dev)->num_pipes == 2)
6286                 return 0;
6287
6288         /* Ivybridge 3 pipe is really complicated */
6289         switch (pipe) {
6290         case PIPE_A:
6291                 return 0;
6292         case PIPE_B:
6293                 if (pipe_config->fdi_lanes <= 2)
6294                         return 0;
6295
6296                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6297                 other_crtc_state =
6298                         intel_atomic_get_crtc_state(state, other_crtc);
6299                 if (IS_ERR(other_crtc_state))
6300                         return PTR_ERR(other_crtc_state);
6301
6302                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6303                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6304                                       pipe_name(pipe), pipe_config->fdi_lanes);
6305                         return -EINVAL;
6306                 }
6307                 return 0;
6308         case PIPE_C:
6309                 if (pipe_config->fdi_lanes > 2) {
6310                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6311                                       pipe_name(pipe), pipe_config->fdi_lanes);
6312                         return -EINVAL;
6313                 }
6314
6315                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6316                 other_crtc_state =
6317                         intel_atomic_get_crtc_state(state, other_crtc);
6318                 if (IS_ERR(other_crtc_state))
6319                         return PTR_ERR(other_crtc_state);
6320
6321                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6322                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6323                         return -EINVAL;
6324                 }
6325                 return 0;
6326         default:
6327                 BUG();
6328         }
6329 }
6330
6331 #define RETRY 1
6332 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6333                                        struct intel_crtc_state *pipe_config)
6334 {
6335         struct drm_device *dev = intel_crtc->base.dev;
6336         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6337         int lane, link_bw, fdi_dotclock, ret;
6338         bool needs_recompute = false;
6339
6340 retry:
6341         /* FDI is a binary signal running at ~2.7GHz, encoding
6342          * each output octet as 10 bits. The actual frequency
6343          * is stored as a divider into a 100MHz clock, and the
6344          * mode pixel clock is stored in units of 1KHz.
6345          * Hence the bw of each lane in terms of the mode signal
6346          * is:
6347          */
6348         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6349
6350         fdi_dotclock = adjusted_mode->crtc_clock;
6351
6352         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6353                                            pipe_config->pipe_bpp);
6354
6355         pipe_config->fdi_lanes = lane;
6356
6357         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6358                                link_bw, &pipe_config->fdi_m_n);
6359
6360         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6361                                        intel_crtc->pipe, pipe_config);
6362         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6363                 pipe_config->pipe_bpp -= 2*3;
6364                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6365                               pipe_config->pipe_bpp);
6366                 needs_recompute = true;
6367                 pipe_config->bw_constrained = true;
6368
6369                 goto retry;
6370         }
6371
6372         if (needs_recompute)
6373                 return RETRY;
6374
6375         return ret;
6376 }
6377
6378 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6379                                    struct intel_crtc_state *pipe_config)
6380 {
6381         pipe_config->ips_enabled = i915.enable_ips &&
6382                                    hsw_crtc_supports_ips(crtc) &&
6383                                    pipe_config->pipe_bpp <= 24;
6384 }
6385
6386 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6387                                      struct intel_crtc_state *pipe_config)
6388 {
6389         struct drm_device *dev = crtc->base.dev;
6390         struct drm_i915_private *dev_priv = dev->dev_private;
6391         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6392         int ret;
6393
6394         /* FIXME should check pixel clock limits on all platforms */
6395         if (INTEL_INFO(dev)->gen < 4) {
6396                 int clock_limit =
6397                         dev_priv->display.get_display_clock_speed(dev);
6398
6399                 /*
6400                  * Enable pixel doubling when the dot clock
6401                  * is > 90% of the (display) core speed.
6402                  *
6403                  * GDG double wide on either pipe,
6404                  * otherwise pipe A only.
6405                  */
6406                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6407                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6408                         clock_limit *= 2;
6409                         pipe_config->double_wide = true;
6410                 }
6411
6412                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6413                         return -EINVAL;
6414         }
6415
6416         /*
6417          * Pipe horizontal size must be even in:
6418          * - DVO ganged mode
6419          * - LVDS dual channel mode
6420          * - Double wide pipe
6421          */
6422         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6423              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6424                 pipe_config->pipe_src_w &= ~1;
6425
6426         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6427          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6428          */
6429         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6430                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6431                 return -EINVAL;
6432
6433         if (HAS_IPS(dev))
6434                 hsw_compute_ips_config(crtc, pipe_config);
6435
6436         if (pipe_config->has_pch_encoder)
6437                 return ironlake_fdi_compute_config(crtc, pipe_config);
6438
6439         /* FIXME: remove below call once atomic mode set is place and all crtc
6440          * related checks called from atomic_crtc_check function */
6441         ret = 0;
6442         DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6443                 crtc, pipe_config->base.state);
6444         ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6445
6446         return ret;
6447 }
6448
6449 static int skylake_get_display_clock_speed(struct drm_device *dev)
6450 {
6451         struct drm_i915_private *dev_priv = to_i915(dev);
6452         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6453         uint32_t cdctl = I915_READ(CDCLK_CTL);
6454         uint32_t linkrate;
6455
6456         if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6457                 WARN(1, "LCPLL1 not enabled\n");
6458                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6459         }
6460
6461         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6462                 return 540000;
6463
6464         linkrate = (I915_READ(DPLL_CTRL1) &
6465                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6466
6467         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6468             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6469                 /* vco 8640 */
6470                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6471                 case CDCLK_FREQ_450_432:
6472                         return 432000;
6473                 case CDCLK_FREQ_337_308:
6474                         return 308570;
6475                 case CDCLK_FREQ_675_617:
6476                         return 617140;
6477                 default:
6478                         WARN(1, "Unknown cd freq selection\n");
6479                 }
6480         } else {
6481                 /* vco 8100 */
6482                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6483                 case CDCLK_FREQ_450_432:
6484                         return 450000;
6485                 case CDCLK_FREQ_337_308:
6486                         return 337500;
6487                 case CDCLK_FREQ_675_617:
6488                         return 675000;
6489                 default:
6490                         WARN(1, "Unknown cd freq selection\n");
6491                 }
6492         }
6493
6494         /* error case, do as if DPLL0 isn't enabled */
6495         return 24000;
6496 }
6497
6498 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6499 {
6500         struct drm_i915_private *dev_priv = dev->dev_private;
6501         uint32_t lcpll = I915_READ(LCPLL_CTL);
6502         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6503
6504         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6505                 return 800000;
6506         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6507                 return 450000;
6508         else if (freq == LCPLL_CLK_FREQ_450)
6509                 return 450000;
6510         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6511                 return 540000;
6512         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6513                 return 337500;
6514         else
6515                 return 675000;
6516 }
6517
6518 static int haswell_get_display_clock_speed(struct drm_device *dev)
6519 {
6520         struct drm_i915_private *dev_priv = dev->dev_private;
6521         uint32_t lcpll = I915_READ(LCPLL_CTL);
6522         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6523
6524         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6525                 return 800000;
6526         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6527                 return 450000;
6528         else if (freq == LCPLL_CLK_FREQ_450)
6529                 return 450000;
6530         else if (IS_HSW_ULT(dev))
6531                 return 337500;
6532         else
6533                 return 540000;
6534 }
6535
6536 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6537 {
6538         struct drm_i915_private *dev_priv = dev->dev_private;
6539         u32 val;
6540         int divider;
6541
6542         if (dev_priv->hpll_freq == 0)
6543                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6544
6545         mutex_lock(&dev_priv->dpio_lock);
6546         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6547         mutex_unlock(&dev_priv->dpio_lock);
6548
6549         divider = val & DISPLAY_FREQUENCY_VALUES;
6550
6551         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6552              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6553              "cdclk change in progress\n");
6554
6555         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6556 }
6557
6558 static int ilk_get_display_clock_speed(struct drm_device *dev)
6559 {
6560         return 450000;
6561 }
6562
6563 static int i945_get_display_clock_speed(struct drm_device *dev)
6564 {
6565         return 400000;
6566 }
6567
6568 static int i915_get_display_clock_speed(struct drm_device *dev)
6569 {
6570         return 333333;
6571 }
6572
6573 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6574 {
6575         return 200000;
6576 }
6577
6578 static int pnv_get_display_clock_speed(struct drm_device *dev)
6579 {
6580         u16 gcfgc = 0;
6581
6582         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6583
6584         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6585         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6586                 return 266667;
6587         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6588                 return 333333;
6589         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6590                 return 444444;
6591         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6592                 return 200000;
6593         default:
6594                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6595         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6596                 return 133333;
6597         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6598                 return 166667;
6599         }
6600 }
6601
6602 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6603 {
6604         u16 gcfgc = 0;
6605
6606         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6607
6608         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6609                 return 133333;
6610         else {
6611                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6612                 case GC_DISPLAY_CLOCK_333_MHZ:
6613                         return 333333;
6614                 default:
6615                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6616                         return 190000;
6617                 }
6618         }
6619 }
6620
6621 static int i865_get_display_clock_speed(struct drm_device *dev)
6622 {
6623         return 266667;
6624 }
6625
6626 static int i855_get_display_clock_speed(struct drm_device *dev)
6627 {
6628         u16 hpllcc = 0;
6629         /* Assume that the hardware is in the high speed state.  This
6630          * should be the default.
6631          */
6632         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6633         case GC_CLOCK_133_200:
6634         case GC_CLOCK_100_200:
6635                 return 200000;
6636         case GC_CLOCK_166_250:
6637                 return 250000;
6638         case GC_CLOCK_100_133:
6639                 return 133333;
6640         }
6641
6642         /* Shouldn't happen */
6643         return 0;
6644 }
6645
6646 static int i830_get_display_clock_speed(struct drm_device *dev)
6647 {
6648         return 133333;
6649 }
6650
6651 static void
6652 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6653 {
6654         while (*num > DATA_LINK_M_N_MASK ||
6655                *den > DATA_LINK_M_N_MASK) {
6656                 *num >>= 1;
6657                 *den >>= 1;
6658         }
6659 }
6660
6661 static void compute_m_n(unsigned int m, unsigned int n,
6662                         uint32_t *ret_m, uint32_t *ret_n)
6663 {
6664         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6665         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6666         intel_reduce_m_n_ratio(ret_m, ret_n);
6667 }
6668
6669 void
6670 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6671                        int pixel_clock, int link_clock,
6672                        struct intel_link_m_n *m_n)
6673 {
6674         m_n->tu = 64;
6675
6676         compute_m_n(bits_per_pixel * pixel_clock,
6677                     link_clock * nlanes * 8,
6678                     &m_n->gmch_m, &m_n->gmch_n);
6679
6680         compute_m_n(pixel_clock, link_clock,
6681                     &m_n->link_m, &m_n->link_n);
6682 }
6683
6684 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6685 {
6686         if (i915.panel_use_ssc >= 0)
6687                 return i915.panel_use_ssc != 0;
6688         return dev_priv->vbt.lvds_use_ssc
6689                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6690 }
6691
6692 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6693                            int num_connectors)
6694 {
6695         struct drm_device *dev = crtc_state->base.crtc->dev;
6696         struct drm_i915_private *dev_priv = dev->dev_private;
6697         int refclk;
6698
6699         WARN_ON(!crtc_state->base.state);
6700
6701         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6702                 refclk = 100000;
6703         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6704             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6705                 refclk = dev_priv->vbt.lvds_ssc_freq;
6706                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6707         } else if (!IS_GEN2(dev)) {
6708                 refclk = 96000;
6709         } else {
6710                 refclk = 48000;
6711         }
6712
6713         return refclk;
6714 }
6715
6716 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6717 {
6718         return (1 << dpll->n) << 16 | dpll->m2;
6719 }
6720
6721 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6722 {
6723         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6724 }
6725
6726 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6727                                      struct intel_crtc_state *crtc_state,
6728                                      intel_clock_t *reduced_clock)
6729 {
6730         struct drm_device *dev = crtc->base.dev;
6731         u32 fp, fp2 = 0;
6732
6733         if (IS_PINEVIEW(dev)) {
6734                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6735                 if (reduced_clock)
6736                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6737         } else {
6738                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6739                 if (reduced_clock)
6740                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6741         }
6742
6743         crtc_state->dpll_hw_state.fp0 = fp;
6744
6745         crtc->lowfreq_avail = false;
6746         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6747             reduced_clock) {
6748                 crtc_state->dpll_hw_state.fp1 = fp2;
6749                 crtc->lowfreq_avail = true;
6750         } else {
6751                 crtc_state->dpll_hw_state.fp1 = fp;
6752         }
6753 }
6754
6755 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6756                 pipe)
6757 {
6758         u32 reg_val;
6759
6760         /*
6761          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6762          * and set it to a reasonable value instead.
6763          */
6764         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6765         reg_val &= 0xffffff00;
6766         reg_val |= 0x00000030;
6767         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6768
6769         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6770         reg_val &= 0x8cffffff;
6771         reg_val = 0x8c000000;
6772         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6773
6774         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6775         reg_val &= 0xffffff00;
6776         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6777
6778         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6779         reg_val &= 0x00ffffff;
6780         reg_val |= 0xb0000000;
6781         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6782 }
6783
6784 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6785                                          struct intel_link_m_n *m_n)
6786 {
6787         struct drm_device *dev = crtc->base.dev;
6788         struct drm_i915_private *dev_priv = dev->dev_private;
6789         int pipe = crtc->pipe;
6790
6791         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6792         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6793         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6794         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6795 }
6796
6797 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6798                                          struct intel_link_m_n *m_n,
6799                                          struct intel_link_m_n *m2_n2)
6800 {
6801         struct drm_device *dev = crtc->base.dev;
6802         struct drm_i915_private *dev_priv = dev->dev_private;
6803         int pipe = crtc->pipe;
6804         enum transcoder transcoder = crtc->config->cpu_transcoder;
6805
6806         if (INTEL_INFO(dev)->gen >= 5) {
6807                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6808                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6809                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6810                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6811                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6812                  * for gen < 8) and if DRRS is supported (to make sure the
6813                  * registers are not unnecessarily accessed).
6814                  */
6815                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6816                         crtc->config->has_drrs) {
6817                         I915_WRITE(PIPE_DATA_M2(transcoder),
6818                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6819                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6820                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6821                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6822                 }
6823         } else {
6824                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6825                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6826                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6827                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6828         }
6829 }
6830
6831 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6832 {
6833         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6834
6835         if (m_n == M1_N1) {
6836                 dp_m_n = &crtc->config->dp_m_n;
6837                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6838         } else if (m_n == M2_N2) {
6839
6840                 /*
6841                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6842                  * needs to be programmed into M1_N1.
6843                  */
6844                 dp_m_n = &crtc->config->dp_m2_n2;
6845         } else {
6846                 DRM_ERROR("Unsupported divider value\n");
6847                 return;
6848         }
6849
6850         if (crtc->config->has_pch_encoder)
6851                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6852         else
6853                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6854 }
6855
6856 static void vlv_update_pll(struct intel_crtc *crtc,
6857                            struct intel_crtc_state *pipe_config)
6858 {
6859         u32 dpll, dpll_md;
6860
6861         /*
6862          * Enable DPIO clock input. We should never disable the reference
6863          * clock for pipe B, since VGA hotplug / manual detection depends
6864          * on it.
6865          */
6866         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6867                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6868         /* We should never disable this, set it here for state tracking */
6869         if (crtc->pipe == PIPE_B)
6870                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6871         dpll |= DPLL_VCO_ENABLE;
6872         pipe_config->dpll_hw_state.dpll = dpll;
6873
6874         dpll_md = (pipe_config->pixel_multiplier - 1)
6875                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6876         pipe_config->dpll_hw_state.dpll_md = dpll_md;
6877 }
6878
6879 static void vlv_prepare_pll(struct intel_crtc *crtc,
6880                             const struct intel_crtc_state *pipe_config)
6881 {
6882         struct drm_device *dev = crtc->base.dev;
6883         struct drm_i915_private *dev_priv = dev->dev_private;
6884         int pipe = crtc->pipe;
6885         u32 mdiv;
6886         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6887         u32 coreclk, reg_val;
6888
6889         mutex_lock(&dev_priv->dpio_lock);
6890
6891         bestn = pipe_config->dpll.n;
6892         bestm1 = pipe_config->dpll.m1;
6893         bestm2 = pipe_config->dpll.m2;
6894         bestp1 = pipe_config->dpll.p1;
6895         bestp2 = pipe_config->dpll.p2;
6896
6897         /* See eDP HDMI DPIO driver vbios notes doc */
6898
6899         /* PLL B needs special handling */
6900         if (pipe == PIPE_B)
6901                 vlv_pllb_recal_opamp(dev_priv, pipe);
6902
6903         /* Set up Tx target for periodic Rcomp update */
6904         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6905
6906         /* Disable target IRef on PLL */
6907         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6908         reg_val &= 0x00ffffff;
6909         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6910
6911         /* Disable fast lock */
6912         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6913
6914         /* Set idtafcrecal before PLL is enabled */
6915         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6916         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6917         mdiv |= ((bestn << DPIO_N_SHIFT));
6918         mdiv |= (1 << DPIO_K_SHIFT);
6919
6920         /*
6921          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6922          * but we don't support that).
6923          * Note: don't use the DAC post divider as it seems unstable.
6924          */
6925         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6926         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6927
6928         mdiv |= DPIO_ENABLE_CALIBRATION;
6929         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6930
6931         /* Set HBR and RBR LPF coefficients */
6932         if (pipe_config->port_clock == 162000 ||
6933             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6934             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6935                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6936                                  0x009f0003);
6937         else
6938                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6939                                  0x00d0000f);
6940
6941         if (pipe_config->has_dp_encoder) {
6942                 /* Use SSC source */
6943                 if (pipe == PIPE_A)
6944                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6945                                          0x0df40000);
6946                 else
6947                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6948                                          0x0df70000);
6949         } else { /* HDMI or VGA */
6950                 /* Use bend source */
6951                 if (pipe == PIPE_A)
6952                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6953                                          0x0df70000);
6954                 else
6955                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6956                                          0x0df40000);
6957         }
6958
6959         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6960         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6961         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6962             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6963                 coreclk |= 0x01000000;
6964         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6965
6966         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6967         mutex_unlock(&dev_priv->dpio_lock);
6968 }
6969
6970 static void chv_update_pll(struct intel_crtc *crtc,
6971                            struct intel_crtc_state *pipe_config)
6972 {
6973         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6974                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6975                 DPLL_VCO_ENABLE;
6976         if (crtc->pipe != PIPE_A)
6977                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6978
6979         pipe_config->dpll_hw_state.dpll_md =
6980                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6981 }
6982
6983 static void chv_prepare_pll(struct intel_crtc *crtc,
6984                             const struct intel_crtc_state *pipe_config)
6985 {
6986         struct drm_device *dev = crtc->base.dev;
6987         struct drm_i915_private *dev_priv = dev->dev_private;
6988         int pipe = crtc->pipe;
6989         int dpll_reg = DPLL(crtc->pipe);
6990         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6991         u32 loopfilter, tribuf_calcntr;
6992         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6993         u32 dpio_val;
6994         int vco;
6995
6996         bestn = pipe_config->dpll.n;
6997         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6998         bestm1 = pipe_config->dpll.m1;
6999         bestm2 = pipe_config->dpll.m2 >> 22;
7000         bestp1 = pipe_config->dpll.p1;
7001         bestp2 = pipe_config->dpll.p2;
7002         vco = pipe_config->dpll.vco;
7003         dpio_val = 0;
7004         loopfilter = 0;
7005
7006         /*
7007          * Enable Refclk and SSC
7008          */
7009         I915_WRITE(dpll_reg,
7010                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7011
7012         mutex_lock(&dev_priv->dpio_lock);
7013
7014         /* p1 and p2 divider */
7015         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7016                         5 << DPIO_CHV_S1_DIV_SHIFT |
7017                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7018                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7019                         1 << DPIO_CHV_K_DIV_SHIFT);
7020
7021         /* Feedback post-divider - m2 */
7022         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7023
7024         /* Feedback refclk divider - n and m1 */
7025         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7026                         DPIO_CHV_M1_DIV_BY_2 |
7027                         1 << DPIO_CHV_N_DIV_SHIFT);
7028
7029         /* M2 fraction division */
7030         if (bestm2_frac)
7031                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7032
7033         /* M2 fraction division enable */
7034         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7035         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7036         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7037         if (bestm2_frac)
7038                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7039         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7040
7041         /* Program digital lock detect threshold */
7042         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7043         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7044                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7045         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7046         if (!bestm2_frac)
7047                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7048         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7049
7050         /* Loop filter */
7051         if (vco == 5400000) {
7052                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7053                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7054                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7055                 tribuf_calcntr = 0x9;
7056         } else if (vco <= 6200000) {
7057                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7058                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7059                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7060                 tribuf_calcntr = 0x9;
7061         } else if (vco <= 6480000) {
7062                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7063                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7064                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7065                 tribuf_calcntr = 0x8;
7066         } else {
7067                 /* Not supported. Apply the same limits as in the max case */
7068                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7069                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7070                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7071                 tribuf_calcntr = 0;
7072         }
7073         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7074
7075         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7076         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7077         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7078         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7079
7080         /* AFC Recal */
7081         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7082                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7083                         DPIO_AFC_RECAL);
7084
7085         mutex_unlock(&dev_priv->dpio_lock);
7086 }
7087
7088 /**
7089  * vlv_force_pll_on - forcibly enable just the PLL
7090  * @dev_priv: i915 private structure
7091  * @pipe: pipe PLL to enable
7092  * @dpll: PLL configuration
7093  *
7094  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7095  * in cases where we need the PLL enabled even when @pipe is not going to
7096  * be enabled.
7097  */
7098 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7099                       const struct dpll *dpll)
7100 {
7101         struct intel_crtc *crtc =
7102                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7103         struct intel_crtc_state pipe_config = {
7104                 .base.crtc = &crtc->base,
7105                 .pixel_multiplier = 1,
7106                 .dpll = *dpll,
7107         };
7108
7109         if (IS_CHERRYVIEW(dev)) {
7110                 chv_update_pll(crtc, &pipe_config);
7111                 chv_prepare_pll(crtc, &pipe_config);
7112                 chv_enable_pll(crtc, &pipe_config);
7113         } else {
7114                 vlv_update_pll(crtc, &pipe_config);
7115                 vlv_prepare_pll(crtc, &pipe_config);
7116                 vlv_enable_pll(crtc, &pipe_config);
7117         }
7118 }
7119
7120 /**
7121  * vlv_force_pll_off - forcibly disable just the PLL
7122  * @dev_priv: i915 private structure
7123  * @pipe: pipe PLL to disable
7124  *
7125  * Disable the PLL for @pipe. To be used in cases where we need
7126  * the PLL enabled even when @pipe is not going to be enabled.
7127  */
7128 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7129 {
7130         if (IS_CHERRYVIEW(dev))
7131                 chv_disable_pll(to_i915(dev), pipe);
7132         else
7133                 vlv_disable_pll(to_i915(dev), pipe);
7134 }
7135
7136 static void i9xx_update_pll(struct intel_crtc *crtc,
7137                             struct intel_crtc_state *crtc_state,
7138                             intel_clock_t *reduced_clock,
7139                             int num_connectors)
7140 {
7141         struct drm_device *dev = crtc->base.dev;
7142         struct drm_i915_private *dev_priv = dev->dev_private;
7143         u32 dpll;
7144         bool is_sdvo;
7145         struct dpll *clock = &crtc_state->dpll;
7146
7147         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7148
7149         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7150                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7151
7152         dpll = DPLL_VGA_MODE_DIS;
7153
7154         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7155                 dpll |= DPLLB_MODE_LVDS;
7156         else
7157                 dpll |= DPLLB_MODE_DAC_SERIAL;
7158
7159         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7160                 dpll |= (crtc_state->pixel_multiplier - 1)
7161                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7162         }
7163
7164         if (is_sdvo)
7165                 dpll |= DPLL_SDVO_HIGH_SPEED;
7166
7167         if (crtc_state->has_dp_encoder)
7168                 dpll |= DPLL_SDVO_HIGH_SPEED;
7169
7170         /* compute bitmask from p1 value */
7171         if (IS_PINEVIEW(dev))
7172                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7173         else {
7174                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7175                 if (IS_G4X(dev) && reduced_clock)
7176                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7177         }
7178         switch (clock->p2) {
7179         case 5:
7180                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7181                 break;
7182         case 7:
7183                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7184                 break;
7185         case 10:
7186                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7187                 break;
7188         case 14:
7189                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7190                 break;
7191         }
7192         if (INTEL_INFO(dev)->gen >= 4)
7193                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7194
7195         if (crtc_state->sdvo_tv_clock)
7196                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7197         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7198                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7199                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7200         else
7201                 dpll |= PLL_REF_INPUT_DREFCLK;
7202
7203         dpll |= DPLL_VCO_ENABLE;
7204         crtc_state->dpll_hw_state.dpll = dpll;
7205
7206         if (INTEL_INFO(dev)->gen >= 4) {
7207                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7208                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7209                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7210         }
7211 }
7212
7213 static void i8xx_update_pll(struct intel_crtc *crtc,
7214                             struct intel_crtc_state *crtc_state,
7215                             intel_clock_t *reduced_clock,
7216                             int num_connectors)
7217 {
7218         struct drm_device *dev = crtc->base.dev;
7219         struct drm_i915_private *dev_priv = dev->dev_private;
7220         u32 dpll;
7221         struct dpll *clock = &crtc_state->dpll;
7222
7223         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7224
7225         dpll = DPLL_VGA_MODE_DIS;
7226
7227         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7228                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7229         } else {
7230                 if (clock->p1 == 2)
7231                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7232                 else
7233                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7234                 if (clock->p2 == 4)
7235                         dpll |= PLL_P2_DIVIDE_BY_4;
7236         }
7237
7238         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7239                 dpll |= DPLL_DVO_2X_MODE;
7240
7241         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7242                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7243                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7244         else
7245                 dpll |= PLL_REF_INPUT_DREFCLK;
7246
7247         dpll |= DPLL_VCO_ENABLE;
7248         crtc_state->dpll_hw_state.dpll = dpll;
7249 }
7250
7251 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7252 {
7253         struct drm_device *dev = intel_crtc->base.dev;
7254         struct drm_i915_private *dev_priv = dev->dev_private;
7255         enum pipe pipe = intel_crtc->pipe;
7256         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7257         struct drm_display_mode *adjusted_mode =
7258                 &intel_crtc->config->base.adjusted_mode;
7259         uint32_t crtc_vtotal, crtc_vblank_end;
7260         int vsyncshift = 0;
7261
7262         /* We need to be careful not to changed the adjusted mode, for otherwise
7263          * the hw state checker will get angry at the mismatch. */
7264         crtc_vtotal = adjusted_mode->crtc_vtotal;
7265         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7266
7267         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7268                 /* the chip adds 2 halflines automatically */
7269                 crtc_vtotal -= 1;
7270                 crtc_vblank_end -= 1;
7271
7272                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7273                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7274                 else
7275                         vsyncshift = adjusted_mode->crtc_hsync_start -
7276                                 adjusted_mode->crtc_htotal / 2;
7277                 if (vsyncshift < 0)
7278                         vsyncshift += adjusted_mode->crtc_htotal;
7279         }
7280
7281         if (INTEL_INFO(dev)->gen > 3)
7282                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7283
7284         I915_WRITE(HTOTAL(cpu_transcoder),
7285                    (adjusted_mode->crtc_hdisplay - 1) |
7286                    ((adjusted_mode->crtc_htotal - 1) << 16));
7287         I915_WRITE(HBLANK(cpu_transcoder),
7288                    (adjusted_mode->crtc_hblank_start - 1) |
7289                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7290         I915_WRITE(HSYNC(cpu_transcoder),
7291                    (adjusted_mode->crtc_hsync_start - 1) |
7292                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7293
7294         I915_WRITE(VTOTAL(cpu_transcoder),
7295                    (adjusted_mode->crtc_vdisplay - 1) |
7296                    ((crtc_vtotal - 1) << 16));
7297         I915_WRITE(VBLANK(cpu_transcoder),
7298                    (adjusted_mode->crtc_vblank_start - 1) |
7299                    ((crtc_vblank_end - 1) << 16));
7300         I915_WRITE(VSYNC(cpu_transcoder),
7301                    (adjusted_mode->crtc_vsync_start - 1) |
7302                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7303
7304         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7305          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7306          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7307          * bits. */
7308         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7309             (pipe == PIPE_B || pipe == PIPE_C))
7310                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7311
7312         /* pipesrc controls the size that is scaled from, which should
7313          * always be the user's requested size.
7314          */
7315         I915_WRITE(PIPESRC(pipe),
7316                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7317                    (intel_crtc->config->pipe_src_h - 1));
7318 }
7319
7320 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7321                                    struct intel_crtc_state *pipe_config)
7322 {
7323         struct drm_device *dev = crtc->base.dev;
7324         struct drm_i915_private *dev_priv = dev->dev_private;
7325         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7326         uint32_t tmp;
7327
7328         tmp = I915_READ(HTOTAL(cpu_transcoder));
7329         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7330         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7331         tmp = I915_READ(HBLANK(cpu_transcoder));
7332         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7333         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7334         tmp = I915_READ(HSYNC(cpu_transcoder));
7335         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7336         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7337
7338         tmp = I915_READ(VTOTAL(cpu_transcoder));
7339         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7340         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7341         tmp = I915_READ(VBLANK(cpu_transcoder));
7342         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7343         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7344         tmp = I915_READ(VSYNC(cpu_transcoder));
7345         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7346         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7347
7348         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7349                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7350                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7351                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7352         }
7353
7354         tmp = I915_READ(PIPESRC(crtc->pipe));
7355         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7356         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7357
7358         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7359         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7360 }
7361
7362 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7363                                  struct intel_crtc_state *pipe_config)
7364 {
7365         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7366         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7367         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7368         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7369
7370         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7371         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7372         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7373         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7374
7375         mode->flags = pipe_config->base.adjusted_mode.flags;
7376
7377         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7378         mode->flags |= pipe_config->base.adjusted_mode.flags;
7379 }
7380
7381 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7382 {
7383         struct drm_device *dev = intel_crtc->base.dev;
7384         struct drm_i915_private *dev_priv = dev->dev_private;
7385         uint32_t pipeconf;
7386
7387         pipeconf = 0;
7388
7389         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7390             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7391                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7392
7393         if (intel_crtc->config->double_wide)
7394                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7395
7396         /* only g4x and later have fancy bpc/dither controls */
7397         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7398                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7399                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7400                         pipeconf |= PIPECONF_DITHER_EN |
7401                                     PIPECONF_DITHER_TYPE_SP;
7402
7403                 switch (intel_crtc->config->pipe_bpp) {
7404                 case 18:
7405                         pipeconf |= PIPECONF_6BPC;
7406                         break;
7407                 case 24:
7408                         pipeconf |= PIPECONF_8BPC;
7409                         break;
7410                 case 30:
7411                         pipeconf |= PIPECONF_10BPC;
7412                         break;
7413                 default:
7414                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7415                         BUG();
7416                 }
7417         }
7418
7419         if (HAS_PIPE_CXSR(dev)) {
7420                 if (intel_crtc->lowfreq_avail) {
7421                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7422                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7423                 } else {
7424                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7425                 }
7426         }
7427
7428         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7429                 if (INTEL_INFO(dev)->gen < 4 ||
7430                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7431                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7432                 else
7433                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7434         } else
7435                 pipeconf |= PIPECONF_PROGRESSIVE;
7436
7437         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7438                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7439
7440         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7441         POSTING_READ(PIPECONF(intel_crtc->pipe));
7442 }
7443
7444 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7445                                    struct intel_crtc_state *crtc_state)
7446 {
7447         struct drm_device *dev = crtc->base.dev;
7448         struct drm_i915_private *dev_priv = dev->dev_private;
7449         int refclk, num_connectors = 0;
7450         intel_clock_t clock, reduced_clock;
7451         bool ok, has_reduced_clock = false;
7452         bool is_lvds = false, is_dsi = false;
7453         struct intel_encoder *encoder;
7454         const intel_limit_t *limit;
7455         struct drm_atomic_state *state = crtc_state->base.state;
7456         struct drm_connector *connector;
7457         struct drm_connector_state *connector_state;
7458         int i;
7459
7460         memset(&crtc_state->dpll_hw_state, 0,
7461                sizeof(crtc_state->dpll_hw_state));
7462
7463         for_each_connector_in_state(state, connector, connector_state, i) {
7464                 if (connector_state->crtc != &crtc->base)
7465                         continue;
7466
7467                 encoder = to_intel_encoder(connector_state->best_encoder);
7468
7469                 switch (encoder->type) {
7470                 case INTEL_OUTPUT_LVDS:
7471                         is_lvds = true;
7472                         break;
7473                 case INTEL_OUTPUT_DSI:
7474                         is_dsi = true;
7475                         break;
7476                 default:
7477                         break;
7478                 }
7479
7480                 num_connectors++;
7481         }
7482
7483         if (is_dsi)
7484                 return 0;
7485
7486         if (!crtc_state->clock_set) {
7487                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7488
7489                 /*
7490                  * Returns a set of divisors for the desired target clock with
7491                  * the given refclk, or FALSE.  The returned values represent
7492                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7493                  * 2) / p1 / p2.
7494                  */
7495                 limit = intel_limit(crtc_state, refclk);
7496                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7497                                                  crtc_state->port_clock,
7498                                                  refclk, NULL, &clock);
7499                 if (!ok) {
7500                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7501                         return -EINVAL;
7502                 }
7503
7504                 if (is_lvds && dev_priv->lvds_downclock_avail) {
7505                         /*
7506                          * Ensure we match the reduced clock's P to the target
7507                          * clock.  If the clocks don't match, we can't switch
7508                          * the display clock by using the FP0/FP1. In such case
7509                          * we will disable the LVDS downclock feature.
7510                          */
7511                         has_reduced_clock =
7512                                 dev_priv->display.find_dpll(limit, crtc_state,
7513                                                             dev_priv->lvds_downclock,
7514                                                             refclk, &clock,
7515                                                             &reduced_clock);
7516                 }
7517                 /* Compat-code for transition, will disappear. */
7518                 crtc_state->dpll.n = clock.n;
7519                 crtc_state->dpll.m1 = clock.m1;
7520                 crtc_state->dpll.m2 = clock.m2;
7521                 crtc_state->dpll.p1 = clock.p1;
7522                 crtc_state->dpll.p2 = clock.p2;
7523         }
7524
7525         if (IS_GEN2(dev)) {
7526                 i8xx_update_pll(crtc, crtc_state,
7527                                 has_reduced_clock ? &reduced_clock : NULL,
7528                                 num_connectors);
7529         } else if (IS_CHERRYVIEW(dev)) {
7530                 chv_update_pll(crtc, crtc_state);
7531         } else if (IS_VALLEYVIEW(dev)) {
7532                 vlv_update_pll(crtc, crtc_state);
7533         } else {
7534                 i9xx_update_pll(crtc, crtc_state,
7535                                 has_reduced_clock ? &reduced_clock : NULL,
7536                                 num_connectors);
7537         }
7538
7539         return 0;
7540 }
7541
7542 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7543                                  struct intel_crtc_state *pipe_config)
7544 {
7545         struct drm_device *dev = crtc->base.dev;
7546         struct drm_i915_private *dev_priv = dev->dev_private;
7547         uint32_t tmp;
7548
7549         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7550                 return;
7551
7552         tmp = I915_READ(PFIT_CONTROL);
7553         if (!(tmp & PFIT_ENABLE))
7554                 return;
7555
7556         /* Check whether the pfit is attached to our pipe. */
7557         if (INTEL_INFO(dev)->gen < 4) {
7558                 if (crtc->pipe != PIPE_B)
7559                         return;
7560         } else {
7561                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7562                         return;
7563         }
7564
7565         pipe_config->gmch_pfit.control = tmp;
7566         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7567         if (INTEL_INFO(dev)->gen < 5)
7568                 pipe_config->gmch_pfit.lvds_border_bits =
7569                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7570 }
7571
7572 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7573                                struct intel_crtc_state *pipe_config)
7574 {
7575         struct drm_device *dev = crtc->base.dev;
7576         struct drm_i915_private *dev_priv = dev->dev_private;
7577         int pipe = pipe_config->cpu_transcoder;
7578         intel_clock_t clock;
7579         u32 mdiv;
7580         int refclk = 100000;
7581
7582         /* In case of MIPI DPLL will not even be used */
7583         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7584                 return;
7585
7586         mutex_lock(&dev_priv->dpio_lock);
7587         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7588         mutex_unlock(&dev_priv->dpio_lock);
7589
7590         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7591         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7592         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7593         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7594         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7595
7596         vlv_clock(refclk, &clock);
7597
7598         /* clock.dot is the fast clock */
7599         pipe_config->port_clock = clock.dot / 5;
7600 }
7601
7602 static void
7603 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7604                               struct intel_initial_plane_config *plane_config)
7605 {
7606         struct drm_device *dev = crtc->base.dev;
7607         struct drm_i915_private *dev_priv = dev->dev_private;
7608         u32 val, base, offset;
7609         int pipe = crtc->pipe, plane = crtc->plane;
7610         int fourcc, pixel_format;
7611         unsigned int aligned_height;
7612         struct drm_framebuffer *fb;
7613         struct intel_framebuffer *intel_fb;
7614
7615         val = I915_READ(DSPCNTR(plane));
7616         if (!(val & DISPLAY_PLANE_ENABLE))
7617                 return;
7618
7619         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7620         if (!intel_fb) {
7621                 DRM_DEBUG_KMS("failed to alloc fb\n");
7622                 return;
7623         }
7624
7625         fb = &intel_fb->base;
7626
7627         if (INTEL_INFO(dev)->gen >= 4) {
7628                 if (val & DISPPLANE_TILED) {
7629                         plane_config->tiling = I915_TILING_X;
7630                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7631                 }
7632         }
7633
7634         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7635         fourcc = i9xx_format_to_fourcc(pixel_format);
7636         fb->pixel_format = fourcc;
7637         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7638
7639         if (INTEL_INFO(dev)->gen >= 4) {
7640                 if (plane_config->tiling)
7641                         offset = I915_READ(DSPTILEOFF(plane));
7642                 else
7643                         offset = I915_READ(DSPLINOFF(plane));
7644                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7645         } else {
7646                 base = I915_READ(DSPADDR(plane));
7647         }
7648         plane_config->base = base;
7649
7650         val = I915_READ(PIPESRC(pipe));
7651         fb->width = ((val >> 16) & 0xfff) + 1;
7652         fb->height = ((val >> 0) & 0xfff) + 1;
7653
7654         val = I915_READ(DSPSTRIDE(pipe));
7655         fb->pitches[0] = val & 0xffffffc0;
7656
7657         aligned_height = intel_fb_align_height(dev, fb->height,
7658                                                fb->pixel_format,
7659                                                fb->modifier[0]);
7660
7661         plane_config->size = fb->pitches[0] * aligned_height;
7662
7663         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7664                       pipe_name(pipe), plane, fb->width, fb->height,
7665                       fb->bits_per_pixel, base, fb->pitches[0],
7666                       plane_config->size);
7667
7668         plane_config->fb = intel_fb;
7669 }
7670
7671 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7672                                struct intel_crtc_state *pipe_config)
7673 {
7674         struct drm_device *dev = crtc->base.dev;
7675         struct drm_i915_private *dev_priv = dev->dev_private;
7676         int pipe = pipe_config->cpu_transcoder;
7677         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7678         intel_clock_t clock;
7679         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7680         int refclk = 100000;
7681
7682         mutex_lock(&dev_priv->dpio_lock);
7683         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7684         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7685         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7686         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7687         mutex_unlock(&dev_priv->dpio_lock);
7688
7689         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7690         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7691         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7692         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7693         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7694
7695         chv_clock(refclk, &clock);
7696
7697         /* clock.dot is the fast clock */
7698         pipe_config->port_clock = clock.dot / 5;
7699 }
7700
7701 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7702                                  struct intel_crtc_state *pipe_config)
7703 {
7704         struct drm_device *dev = crtc->base.dev;
7705         struct drm_i915_private *dev_priv = dev->dev_private;
7706         uint32_t tmp;
7707
7708         if (!intel_display_power_is_enabled(dev_priv,
7709                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7710                 return false;
7711
7712         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7713         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7714
7715         tmp = I915_READ(PIPECONF(crtc->pipe));
7716         if (!(tmp & PIPECONF_ENABLE))
7717                 return false;
7718
7719         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7720                 switch (tmp & PIPECONF_BPC_MASK) {
7721                 case PIPECONF_6BPC:
7722                         pipe_config->pipe_bpp = 18;
7723                         break;
7724                 case PIPECONF_8BPC:
7725                         pipe_config->pipe_bpp = 24;
7726                         break;
7727                 case PIPECONF_10BPC:
7728                         pipe_config->pipe_bpp = 30;
7729                         break;
7730                 default:
7731                         break;
7732                 }
7733         }
7734
7735         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7736                 pipe_config->limited_color_range = true;
7737
7738         if (INTEL_INFO(dev)->gen < 4)
7739                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7740
7741         intel_get_pipe_timings(crtc, pipe_config);
7742
7743         i9xx_get_pfit_config(crtc, pipe_config);
7744
7745         if (INTEL_INFO(dev)->gen >= 4) {
7746                 tmp = I915_READ(DPLL_MD(crtc->pipe));
7747                 pipe_config->pixel_multiplier =
7748                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7749                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7750                 pipe_config->dpll_hw_state.dpll_md = tmp;
7751         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7752                 tmp = I915_READ(DPLL(crtc->pipe));
7753                 pipe_config->pixel_multiplier =
7754                         ((tmp & SDVO_MULTIPLIER_MASK)
7755                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7756         } else {
7757                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7758                  * port and will be fixed up in the encoder->get_config
7759                  * function. */
7760                 pipe_config->pixel_multiplier = 1;
7761         }
7762         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7763         if (!IS_VALLEYVIEW(dev)) {
7764                 /*
7765                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7766                  * on 830. Filter it out here so that we don't
7767                  * report errors due to that.
7768                  */
7769                 if (IS_I830(dev))
7770                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7771
7772                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7773                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7774         } else {
7775                 /* Mask out read-only status bits. */
7776                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7777                                                      DPLL_PORTC_READY_MASK |
7778                                                      DPLL_PORTB_READY_MASK);
7779         }
7780
7781         if (IS_CHERRYVIEW(dev))
7782                 chv_crtc_clock_get(crtc, pipe_config);
7783         else if (IS_VALLEYVIEW(dev))
7784                 vlv_crtc_clock_get(crtc, pipe_config);
7785         else
7786                 i9xx_crtc_clock_get(crtc, pipe_config);
7787
7788         return true;
7789 }
7790
7791 static void ironlake_init_pch_refclk(struct drm_device *dev)
7792 {
7793         struct drm_i915_private *dev_priv = dev->dev_private;
7794         struct intel_encoder *encoder;
7795         u32 val, final;
7796         bool has_lvds = false;
7797         bool has_cpu_edp = false;
7798         bool has_panel = false;
7799         bool has_ck505 = false;
7800         bool can_ssc = false;
7801
7802         /* We need to take the global config into account */
7803         for_each_intel_encoder(dev, encoder) {
7804                 switch (encoder->type) {
7805                 case INTEL_OUTPUT_LVDS:
7806                         has_panel = true;
7807                         has_lvds = true;
7808                         break;
7809                 case INTEL_OUTPUT_EDP:
7810                         has_panel = true;
7811                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7812                                 has_cpu_edp = true;
7813                         break;
7814                 default:
7815                         break;
7816                 }
7817         }
7818
7819         if (HAS_PCH_IBX(dev)) {
7820                 has_ck505 = dev_priv->vbt.display_clock_mode;
7821                 can_ssc = has_ck505;
7822         } else {
7823                 has_ck505 = false;
7824                 can_ssc = true;
7825         }
7826
7827         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7828                       has_panel, has_lvds, has_ck505);
7829
7830         /* Ironlake: try to setup display ref clock before DPLL
7831          * enabling. This is only under driver's control after
7832          * PCH B stepping, previous chipset stepping should be
7833          * ignoring this setting.
7834          */
7835         val = I915_READ(PCH_DREF_CONTROL);
7836
7837         /* As we must carefully and slowly disable/enable each source in turn,
7838          * compute the final state we want first and check if we need to
7839          * make any changes at all.
7840          */
7841         final = val;
7842         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7843         if (has_ck505)
7844                 final |= DREF_NONSPREAD_CK505_ENABLE;
7845         else
7846                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7847
7848         final &= ~DREF_SSC_SOURCE_MASK;
7849         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7850         final &= ~DREF_SSC1_ENABLE;
7851
7852         if (has_panel) {
7853                 final |= DREF_SSC_SOURCE_ENABLE;
7854
7855                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7856                         final |= DREF_SSC1_ENABLE;
7857
7858                 if (has_cpu_edp) {
7859                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7860                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7861                         else
7862                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7863                 } else
7864                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7865         } else {
7866                 final |= DREF_SSC_SOURCE_DISABLE;
7867                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7868         }
7869
7870         if (final == val)
7871                 return;
7872
7873         /* Always enable nonspread source */
7874         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7875
7876         if (has_ck505)
7877                 val |= DREF_NONSPREAD_CK505_ENABLE;
7878         else
7879                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7880
7881         if (has_panel) {
7882                 val &= ~DREF_SSC_SOURCE_MASK;
7883                 val |= DREF_SSC_SOURCE_ENABLE;
7884
7885                 /* SSC must be turned on before enabling the CPU output  */
7886                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7887                         DRM_DEBUG_KMS("Using SSC on panel\n");
7888                         val |= DREF_SSC1_ENABLE;
7889                 } else
7890                         val &= ~DREF_SSC1_ENABLE;
7891
7892                 /* Get SSC going before enabling the outputs */
7893                 I915_WRITE(PCH_DREF_CONTROL, val);
7894                 POSTING_READ(PCH_DREF_CONTROL);
7895                 udelay(200);
7896
7897                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7898
7899                 /* Enable CPU source on CPU attached eDP */
7900                 if (has_cpu_edp) {
7901                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7902                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7903                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7904                         } else
7905                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7906                 } else
7907                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7908
7909                 I915_WRITE(PCH_DREF_CONTROL, val);
7910                 POSTING_READ(PCH_DREF_CONTROL);
7911                 udelay(200);
7912         } else {
7913                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7914
7915                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7916
7917                 /* Turn off CPU output */
7918                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7919
7920                 I915_WRITE(PCH_DREF_CONTROL, val);
7921                 POSTING_READ(PCH_DREF_CONTROL);
7922                 udelay(200);
7923
7924                 /* Turn off the SSC source */
7925                 val &= ~DREF_SSC_SOURCE_MASK;
7926                 val |= DREF_SSC_SOURCE_DISABLE;
7927
7928                 /* Turn off SSC1 */
7929                 val &= ~DREF_SSC1_ENABLE;
7930
7931                 I915_WRITE(PCH_DREF_CONTROL, val);
7932                 POSTING_READ(PCH_DREF_CONTROL);
7933                 udelay(200);
7934         }
7935
7936         BUG_ON(val != final);
7937 }
7938
7939 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7940 {
7941         uint32_t tmp;
7942
7943         tmp = I915_READ(SOUTH_CHICKEN2);
7944         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7945         I915_WRITE(SOUTH_CHICKEN2, tmp);
7946
7947         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7948                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7949                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7950
7951         tmp = I915_READ(SOUTH_CHICKEN2);
7952         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7953         I915_WRITE(SOUTH_CHICKEN2, tmp);
7954
7955         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7956                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7957                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7958 }
7959
7960 /* WaMPhyProgramming:hsw */
7961 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7962 {
7963         uint32_t tmp;
7964
7965         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7966         tmp &= ~(0xFF << 24);
7967         tmp |= (0x12 << 24);
7968         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7969
7970         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7971         tmp |= (1 << 11);
7972         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7973
7974         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7975         tmp |= (1 << 11);
7976         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7977
7978         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7979         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7980         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7981
7982         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7983         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7984         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7985
7986         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7987         tmp &= ~(7 << 13);
7988         tmp |= (5 << 13);
7989         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7990
7991         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7992         tmp &= ~(7 << 13);
7993         tmp |= (5 << 13);
7994         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7995
7996         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7997         tmp &= ~0xFF;
7998         tmp |= 0x1C;
7999         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8000
8001         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8002         tmp &= ~0xFF;
8003         tmp |= 0x1C;
8004         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8005
8006         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8007         tmp &= ~(0xFF << 16);
8008         tmp |= (0x1C << 16);
8009         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8010
8011         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8012         tmp &= ~(0xFF << 16);
8013         tmp |= (0x1C << 16);
8014         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8015
8016         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8017         tmp |= (1 << 27);
8018         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8019
8020         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8021         tmp |= (1 << 27);
8022         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8023
8024         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8025         tmp &= ~(0xF << 28);
8026         tmp |= (4 << 28);
8027         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8028
8029         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8030         tmp &= ~(0xF << 28);
8031         tmp |= (4 << 28);
8032         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8033 }
8034
8035 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8036  * Programming" based on the parameters passed:
8037  * - Sequence to enable CLKOUT_DP
8038  * - Sequence to enable CLKOUT_DP without spread
8039  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8040  */
8041 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8042                                  bool with_fdi)
8043 {
8044         struct drm_i915_private *dev_priv = dev->dev_private;
8045         uint32_t reg, tmp;
8046
8047         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8048                 with_spread = true;
8049         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8050                  with_fdi, "LP PCH doesn't have FDI\n"))
8051                 with_fdi = false;
8052
8053         mutex_lock(&dev_priv->dpio_lock);
8054
8055         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8056         tmp &= ~SBI_SSCCTL_DISABLE;
8057         tmp |= SBI_SSCCTL_PATHALT;
8058         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8059
8060         udelay(24);
8061
8062         if (with_spread) {
8063                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8064                 tmp &= ~SBI_SSCCTL_PATHALT;
8065                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8066
8067                 if (with_fdi) {
8068                         lpt_reset_fdi_mphy(dev_priv);
8069                         lpt_program_fdi_mphy(dev_priv);
8070                 }
8071         }
8072
8073         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8074                SBI_GEN0 : SBI_DBUFF0;
8075         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8076         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8077         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8078
8079         mutex_unlock(&dev_priv->dpio_lock);
8080 }
8081
8082 /* Sequence to disable CLKOUT_DP */
8083 static void lpt_disable_clkout_dp(struct drm_device *dev)
8084 {
8085         struct drm_i915_private *dev_priv = dev->dev_private;
8086         uint32_t reg, tmp;
8087
8088         mutex_lock(&dev_priv->dpio_lock);
8089
8090         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8091                SBI_GEN0 : SBI_DBUFF0;
8092         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8093         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8094         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8095
8096         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8097         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8098                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8099                         tmp |= SBI_SSCCTL_PATHALT;
8100                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8101                         udelay(32);
8102                 }
8103                 tmp |= SBI_SSCCTL_DISABLE;
8104                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8105         }
8106
8107         mutex_unlock(&dev_priv->dpio_lock);
8108 }
8109
8110 static void lpt_init_pch_refclk(struct drm_device *dev)
8111 {
8112         struct intel_encoder *encoder;
8113         bool has_vga = false;
8114
8115         for_each_intel_encoder(dev, encoder) {
8116                 switch (encoder->type) {
8117                 case INTEL_OUTPUT_ANALOG:
8118                         has_vga = true;
8119                         break;
8120                 default:
8121                         break;
8122                 }
8123         }
8124
8125         if (has_vga)
8126                 lpt_enable_clkout_dp(dev, true, true);
8127         else
8128                 lpt_disable_clkout_dp(dev);
8129 }
8130
8131 /*
8132  * Initialize reference clocks when the driver loads
8133  */
8134 void intel_init_pch_refclk(struct drm_device *dev)
8135 {
8136         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8137                 ironlake_init_pch_refclk(dev);
8138         else if (HAS_PCH_LPT(dev))
8139                 lpt_init_pch_refclk(dev);
8140 }
8141
8142 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8143 {
8144         struct drm_device *dev = crtc_state->base.crtc->dev;
8145         struct drm_i915_private *dev_priv = dev->dev_private;
8146         struct drm_atomic_state *state = crtc_state->base.state;
8147         struct drm_connector *connector;
8148         struct drm_connector_state *connector_state;
8149         struct intel_encoder *encoder;
8150         int num_connectors = 0, i;
8151         bool is_lvds = false;
8152
8153         for_each_connector_in_state(state, connector, connector_state, i) {
8154                 if (connector_state->crtc != crtc_state->base.crtc)
8155                         continue;
8156
8157                 encoder = to_intel_encoder(connector_state->best_encoder);
8158
8159                 switch (encoder->type) {
8160                 case INTEL_OUTPUT_LVDS:
8161                         is_lvds = true;
8162                         break;
8163                 default:
8164                         break;
8165                 }
8166                 num_connectors++;
8167         }
8168
8169         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8170                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8171                               dev_priv->vbt.lvds_ssc_freq);
8172                 return dev_priv->vbt.lvds_ssc_freq;
8173         }
8174
8175         return 120000;
8176 }
8177
8178 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8179 {
8180         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8182         int pipe = intel_crtc->pipe;
8183         uint32_t val;
8184
8185         val = 0;
8186
8187         switch (intel_crtc->config->pipe_bpp) {
8188         case 18:
8189                 val |= PIPECONF_6BPC;
8190                 break;
8191         case 24:
8192                 val |= PIPECONF_8BPC;
8193                 break;
8194         case 30:
8195                 val |= PIPECONF_10BPC;
8196                 break;
8197         case 36:
8198                 val |= PIPECONF_12BPC;
8199                 break;
8200         default:
8201                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8202                 BUG();
8203         }
8204
8205         if (intel_crtc->config->dither)
8206                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8207
8208         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8209                 val |= PIPECONF_INTERLACED_ILK;
8210         else
8211                 val |= PIPECONF_PROGRESSIVE;
8212
8213         if (intel_crtc->config->limited_color_range)
8214                 val |= PIPECONF_COLOR_RANGE_SELECT;
8215
8216         I915_WRITE(PIPECONF(pipe), val);
8217         POSTING_READ(PIPECONF(pipe));
8218 }
8219
8220 /*
8221  * Set up the pipe CSC unit.
8222  *
8223  * Currently only full range RGB to limited range RGB conversion
8224  * is supported, but eventually this should handle various
8225  * RGB<->YCbCr scenarios as well.
8226  */
8227 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8228 {
8229         struct drm_device *dev = crtc->dev;
8230         struct drm_i915_private *dev_priv = dev->dev_private;
8231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8232         int pipe = intel_crtc->pipe;
8233         uint16_t coeff = 0x7800; /* 1.0 */
8234
8235         /*
8236          * TODO: Check what kind of values actually come out of the pipe
8237          * with these coeff/postoff values and adjust to get the best
8238          * accuracy. Perhaps we even need to take the bpc value into
8239          * consideration.
8240          */
8241
8242         if (intel_crtc->config->limited_color_range)
8243                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8244
8245         /*
8246          * GY/GU and RY/RU should be the other way around according
8247          * to BSpec, but reality doesn't agree. Just set them up in
8248          * a way that results in the correct picture.
8249          */
8250         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8251         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8252
8253         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8254         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8255
8256         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8257         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8258
8259         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8260         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8261         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8262
8263         if (INTEL_INFO(dev)->gen > 6) {
8264                 uint16_t postoff = 0;
8265
8266                 if (intel_crtc->config->limited_color_range)
8267                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8268
8269                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8270                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8271                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8272
8273                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8274         } else {
8275                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8276
8277                 if (intel_crtc->config->limited_color_range)
8278                         mode |= CSC_BLACK_SCREEN_OFFSET;
8279
8280                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8281         }
8282 }
8283
8284 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8285 {
8286         struct drm_device *dev = crtc->dev;
8287         struct drm_i915_private *dev_priv = dev->dev_private;
8288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8289         enum pipe pipe = intel_crtc->pipe;
8290         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8291         uint32_t val;
8292
8293         val = 0;
8294
8295         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8296                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8297
8298         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8299                 val |= PIPECONF_INTERLACED_ILK;
8300         else
8301                 val |= PIPECONF_PROGRESSIVE;
8302
8303         I915_WRITE(PIPECONF(cpu_transcoder), val);
8304         POSTING_READ(PIPECONF(cpu_transcoder));
8305
8306         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8307         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8308
8309         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8310                 val = 0;
8311
8312                 switch (intel_crtc->config->pipe_bpp) {
8313                 case 18:
8314                         val |= PIPEMISC_DITHER_6_BPC;
8315                         break;
8316                 case 24:
8317                         val |= PIPEMISC_DITHER_8_BPC;
8318                         break;
8319                 case 30:
8320                         val |= PIPEMISC_DITHER_10_BPC;
8321                         break;
8322                 case 36:
8323                         val |= PIPEMISC_DITHER_12_BPC;
8324                         break;
8325                 default:
8326                         /* Case prevented by pipe_config_set_bpp. */
8327                         BUG();
8328                 }
8329
8330                 if (intel_crtc->config->dither)
8331                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8332
8333                 I915_WRITE(PIPEMISC(pipe), val);
8334         }
8335 }
8336
8337 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8338                                     struct intel_crtc_state *crtc_state,
8339                                     intel_clock_t *clock,
8340                                     bool *has_reduced_clock,
8341                                     intel_clock_t *reduced_clock)
8342 {
8343         struct drm_device *dev = crtc->dev;
8344         struct drm_i915_private *dev_priv = dev->dev_private;
8345         int refclk;
8346         const intel_limit_t *limit;
8347         bool ret, is_lvds = false;
8348
8349         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8350
8351         refclk = ironlake_get_refclk(crtc_state);
8352
8353         /*
8354          * Returns a set of divisors for the desired target clock with the given
8355          * refclk, or FALSE.  The returned values represent the clock equation:
8356          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8357          */
8358         limit = intel_limit(crtc_state, refclk);
8359         ret = dev_priv->display.find_dpll(limit, crtc_state,
8360                                           crtc_state->port_clock,
8361                                           refclk, NULL, clock);
8362         if (!ret)
8363                 return false;
8364
8365         if (is_lvds && dev_priv->lvds_downclock_avail) {
8366                 /*
8367                  * Ensure we match the reduced clock's P to the target clock.
8368                  * If the clocks don't match, we can't switch the display clock
8369                  * by using the FP0/FP1. In such case we will disable the LVDS
8370                  * downclock feature.
8371                 */
8372                 *has_reduced_clock =
8373                         dev_priv->display.find_dpll(limit, crtc_state,
8374                                                     dev_priv->lvds_downclock,
8375                                                     refclk, clock,
8376                                                     reduced_clock);
8377         }
8378
8379         return true;
8380 }
8381
8382 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8383 {
8384         /*
8385          * Account for spread spectrum to avoid
8386          * oversubscribing the link. Max center spread
8387          * is 2.5%; use 5% for safety's sake.
8388          */
8389         u32 bps = target_clock * bpp * 21 / 20;
8390         return DIV_ROUND_UP(bps, link_bw * 8);
8391 }
8392
8393 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8394 {
8395         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8396 }
8397
8398 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8399                                       struct intel_crtc_state *crtc_state,
8400                                       u32 *fp,
8401                                       intel_clock_t *reduced_clock, u32 *fp2)
8402 {
8403         struct drm_crtc *crtc = &intel_crtc->base;
8404         struct drm_device *dev = crtc->dev;
8405         struct drm_i915_private *dev_priv = dev->dev_private;
8406         struct drm_atomic_state *state = crtc_state->base.state;
8407         struct drm_connector *connector;
8408         struct drm_connector_state *connector_state;
8409         struct intel_encoder *encoder;
8410         uint32_t dpll;
8411         int factor, num_connectors = 0, i;
8412         bool is_lvds = false, is_sdvo = false;
8413
8414         for_each_connector_in_state(state, connector, connector_state, i) {
8415                 if (connector_state->crtc != crtc_state->base.crtc)
8416                         continue;
8417
8418                 encoder = to_intel_encoder(connector_state->best_encoder);
8419
8420                 switch (encoder->type) {
8421                 case INTEL_OUTPUT_LVDS:
8422                         is_lvds = true;
8423                         break;
8424                 case INTEL_OUTPUT_SDVO:
8425                 case INTEL_OUTPUT_HDMI:
8426                         is_sdvo = true;
8427                         break;
8428                 default:
8429                         break;
8430                 }
8431
8432                 num_connectors++;
8433         }
8434
8435         /* Enable autotuning of the PLL clock (if permissible) */
8436         factor = 21;
8437         if (is_lvds) {
8438                 if ((intel_panel_use_ssc(dev_priv) &&
8439                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8440                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8441                         factor = 25;
8442         } else if (crtc_state->sdvo_tv_clock)
8443                 factor = 20;
8444
8445         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8446                 *fp |= FP_CB_TUNE;
8447
8448         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8449                 *fp2 |= FP_CB_TUNE;
8450
8451         dpll = 0;
8452
8453         if (is_lvds)
8454                 dpll |= DPLLB_MODE_LVDS;
8455         else
8456                 dpll |= DPLLB_MODE_DAC_SERIAL;
8457
8458         dpll |= (crtc_state->pixel_multiplier - 1)
8459                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8460
8461         if (is_sdvo)
8462                 dpll |= DPLL_SDVO_HIGH_SPEED;
8463         if (crtc_state->has_dp_encoder)
8464                 dpll |= DPLL_SDVO_HIGH_SPEED;
8465
8466         /* compute bitmask from p1 value */
8467         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8468         /* also FPA1 */
8469         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8470
8471         switch (crtc_state->dpll.p2) {
8472         case 5:
8473                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8474                 break;
8475         case 7:
8476                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8477                 break;
8478         case 10:
8479                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8480                 break;
8481         case 14:
8482                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8483                 break;
8484         }
8485
8486         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8487                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8488         else
8489                 dpll |= PLL_REF_INPUT_DREFCLK;
8490
8491         return dpll | DPLL_VCO_ENABLE;
8492 }
8493
8494 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8495                                        struct intel_crtc_state *crtc_state)
8496 {
8497         struct drm_device *dev = crtc->base.dev;
8498         intel_clock_t clock, reduced_clock;
8499         u32 dpll = 0, fp = 0, fp2 = 0;
8500         bool ok, has_reduced_clock = false;
8501         bool is_lvds = false;
8502         struct intel_shared_dpll *pll;
8503
8504         memset(&crtc_state->dpll_hw_state, 0,
8505                sizeof(crtc_state->dpll_hw_state));
8506
8507         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8508
8509         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8510              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8511
8512         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8513                                      &has_reduced_clock, &reduced_clock);
8514         if (!ok && !crtc_state->clock_set) {
8515                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8516                 return -EINVAL;
8517         }
8518         /* Compat-code for transition, will disappear. */
8519         if (!crtc_state->clock_set) {
8520                 crtc_state->dpll.n = clock.n;
8521                 crtc_state->dpll.m1 = clock.m1;
8522                 crtc_state->dpll.m2 = clock.m2;
8523                 crtc_state->dpll.p1 = clock.p1;
8524                 crtc_state->dpll.p2 = clock.p2;
8525         }
8526
8527         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8528         if (crtc_state->has_pch_encoder) {
8529                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8530                 if (has_reduced_clock)
8531                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8532
8533                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8534                                              &fp, &reduced_clock,
8535                                              has_reduced_clock ? &fp2 : NULL);
8536
8537                 crtc_state->dpll_hw_state.dpll = dpll;
8538                 crtc_state->dpll_hw_state.fp0 = fp;
8539                 if (has_reduced_clock)
8540                         crtc_state->dpll_hw_state.fp1 = fp2;
8541                 else
8542                         crtc_state->dpll_hw_state.fp1 = fp;
8543
8544                 pll = intel_get_shared_dpll(crtc, crtc_state);
8545                 if (pll == NULL) {
8546                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8547                                          pipe_name(crtc->pipe));
8548                         return -EINVAL;
8549                 }
8550         }
8551
8552         if (is_lvds && has_reduced_clock)
8553                 crtc->lowfreq_avail = true;
8554         else
8555                 crtc->lowfreq_avail = false;
8556
8557         return 0;
8558 }
8559
8560 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8561                                          struct intel_link_m_n *m_n)
8562 {
8563         struct drm_device *dev = crtc->base.dev;
8564         struct drm_i915_private *dev_priv = dev->dev_private;
8565         enum pipe pipe = crtc->pipe;
8566
8567         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8568         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8569         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8570                 & ~TU_SIZE_MASK;
8571         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8572         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8573                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8574 }
8575
8576 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8577                                          enum transcoder transcoder,
8578                                          struct intel_link_m_n *m_n,
8579                                          struct intel_link_m_n *m2_n2)
8580 {
8581         struct drm_device *dev = crtc->base.dev;
8582         struct drm_i915_private *dev_priv = dev->dev_private;
8583         enum pipe pipe = crtc->pipe;
8584
8585         if (INTEL_INFO(dev)->gen >= 5) {
8586                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8587                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8588                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8589                         & ~TU_SIZE_MASK;
8590                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8591                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8592                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8593                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8594                  * gen < 8) and if DRRS is supported (to make sure the
8595                  * registers are not unnecessarily read).
8596                  */
8597                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8598                         crtc->config->has_drrs) {
8599                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8600                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8601                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8602                                         & ~TU_SIZE_MASK;
8603                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8604                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8605                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8606                 }
8607         } else {
8608                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8609                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8610                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8611                         & ~TU_SIZE_MASK;
8612                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8613                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8614                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8615         }
8616 }
8617
8618 void intel_dp_get_m_n(struct intel_crtc *crtc,
8619                       struct intel_crtc_state *pipe_config)
8620 {
8621         if (pipe_config->has_pch_encoder)
8622                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8623         else
8624                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8625                                              &pipe_config->dp_m_n,
8626                                              &pipe_config->dp_m2_n2);
8627 }
8628
8629 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8630                                         struct intel_crtc_state *pipe_config)
8631 {
8632         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8633                                      &pipe_config->fdi_m_n, NULL);
8634 }
8635
8636 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8637                                     struct intel_crtc_state *pipe_config)
8638 {
8639         struct drm_device *dev = crtc->base.dev;
8640         struct drm_i915_private *dev_priv = dev->dev_private;
8641         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8642         uint32_t ps_ctrl = 0;
8643         int id = -1;
8644         int i;
8645
8646         /* find scaler attached to this pipe */
8647         for (i = 0; i < crtc->num_scalers; i++) {
8648                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8649                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8650                         id = i;
8651                         pipe_config->pch_pfit.enabled = true;
8652                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8653                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8654                         break;
8655                 }
8656         }
8657
8658         scaler_state->scaler_id = id;
8659         if (id >= 0) {
8660                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8661         } else {
8662                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8663         }
8664 }
8665
8666 static void
8667 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8668                                  struct intel_initial_plane_config *plane_config)
8669 {
8670         struct drm_device *dev = crtc->base.dev;
8671         struct drm_i915_private *dev_priv = dev->dev_private;
8672         u32 val, base, offset, stride_mult, tiling;
8673         int pipe = crtc->pipe;
8674         int fourcc, pixel_format;
8675         unsigned int aligned_height;
8676         struct drm_framebuffer *fb;
8677         struct intel_framebuffer *intel_fb;
8678
8679         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8680         if (!intel_fb) {
8681                 DRM_DEBUG_KMS("failed to alloc fb\n");
8682                 return;
8683         }
8684
8685         fb = &intel_fb->base;
8686
8687         val = I915_READ(PLANE_CTL(pipe, 0));
8688         if (!(val & PLANE_CTL_ENABLE))
8689                 goto error;
8690
8691         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8692         fourcc = skl_format_to_fourcc(pixel_format,
8693                                       val & PLANE_CTL_ORDER_RGBX,
8694                                       val & PLANE_CTL_ALPHA_MASK);
8695         fb->pixel_format = fourcc;
8696         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8697
8698         tiling = val & PLANE_CTL_TILED_MASK;
8699         switch (tiling) {
8700         case PLANE_CTL_TILED_LINEAR:
8701                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8702                 break;
8703         case PLANE_CTL_TILED_X:
8704                 plane_config->tiling = I915_TILING_X;
8705                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8706                 break;
8707         case PLANE_CTL_TILED_Y:
8708                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8709                 break;
8710         case PLANE_CTL_TILED_YF:
8711                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8712                 break;
8713         default:
8714                 MISSING_CASE(tiling);
8715                 goto error;
8716         }
8717
8718         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8719         plane_config->base = base;
8720
8721         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8722
8723         val = I915_READ(PLANE_SIZE(pipe, 0));
8724         fb->height = ((val >> 16) & 0xfff) + 1;
8725         fb->width = ((val >> 0) & 0x1fff) + 1;
8726
8727         val = I915_READ(PLANE_STRIDE(pipe, 0));
8728         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8729                                                 fb->pixel_format);
8730         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8731
8732         aligned_height = intel_fb_align_height(dev, fb->height,
8733                                                fb->pixel_format,
8734                                                fb->modifier[0]);
8735
8736         plane_config->size = fb->pitches[0] * aligned_height;
8737
8738         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8739                       pipe_name(pipe), fb->width, fb->height,
8740                       fb->bits_per_pixel, base, fb->pitches[0],
8741                       plane_config->size);
8742
8743         plane_config->fb = intel_fb;
8744         return;
8745
8746 error:
8747         kfree(fb);
8748 }
8749
8750 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8751                                      struct intel_crtc_state *pipe_config)
8752 {
8753         struct drm_device *dev = crtc->base.dev;
8754         struct drm_i915_private *dev_priv = dev->dev_private;
8755         uint32_t tmp;
8756
8757         tmp = I915_READ(PF_CTL(crtc->pipe));
8758
8759         if (tmp & PF_ENABLE) {
8760                 pipe_config->pch_pfit.enabled = true;
8761                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8762                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8763
8764                 /* We currently do not free assignements of panel fitters on
8765                  * ivb/hsw (since we don't use the higher upscaling modes which
8766                  * differentiates them) so just WARN about this case for now. */
8767                 if (IS_GEN7(dev)) {
8768                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8769                                 PF_PIPE_SEL_IVB(crtc->pipe));
8770                 }
8771         }
8772 }
8773
8774 static void
8775 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8776                                   struct intel_initial_plane_config *plane_config)
8777 {
8778         struct drm_device *dev = crtc->base.dev;
8779         struct drm_i915_private *dev_priv = dev->dev_private;
8780         u32 val, base, offset;
8781         int pipe = crtc->pipe;
8782         int fourcc, pixel_format;
8783         unsigned int aligned_height;
8784         struct drm_framebuffer *fb;
8785         struct intel_framebuffer *intel_fb;
8786
8787         val = I915_READ(DSPCNTR(pipe));
8788         if (!(val & DISPLAY_PLANE_ENABLE))
8789                 return;
8790
8791         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8792         if (!intel_fb) {
8793                 DRM_DEBUG_KMS("failed to alloc fb\n");
8794                 return;
8795         }
8796
8797         fb = &intel_fb->base;
8798
8799         if (INTEL_INFO(dev)->gen >= 4) {
8800                 if (val & DISPPLANE_TILED) {
8801                         plane_config->tiling = I915_TILING_X;
8802                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8803                 }
8804         }
8805
8806         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8807         fourcc = i9xx_format_to_fourcc(pixel_format);
8808         fb->pixel_format = fourcc;
8809         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8810
8811         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8812         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8813                 offset = I915_READ(DSPOFFSET(pipe));
8814         } else {
8815                 if (plane_config->tiling)
8816                         offset = I915_READ(DSPTILEOFF(pipe));
8817                 else
8818                         offset = I915_READ(DSPLINOFF(pipe));
8819         }
8820         plane_config->base = base;
8821
8822         val = I915_READ(PIPESRC(pipe));
8823         fb->width = ((val >> 16) & 0xfff) + 1;
8824         fb->height = ((val >> 0) & 0xfff) + 1;
8825
8826         val = I915_READ(DSPSTRIDE(pipe));
8827         fb->pitches[0] = val & 0xffffffc0;
8828
8829         aligned_height = intel_fb_align_height(dev, fb->height,
8830                                                fb->pixel_format,
8831                                                fb->modifier[0]);
8832
8833         plane_config->size = fb->pitches[0] * aligned_height;
8834
8835         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8836                       pipe_name(pipe), fb->width, fb->height,
8837                       fb->bits_per_pixel, base, fb->pitches[0],
8838                       plane_config->size);
8839
8840         plane_config->fb = intel_fb;
8841 }
8842
8843 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8844                                      struct intel_crtc_state *pipe_config)
8845 {
8846         struct drm_device *dev = crtc->base.dev;
8847         struct drm_i915_private *dev_priv = dev->dev_private;
8848         uint32_t tmp;
8849
8850         if (!intel_display_power_is_enabled(dev_priv,
8851                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8852                 return false;
8853
8854         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8855         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8856
8857         tmp = I915_READ(PIPECONF(crtc->pipe));
8858         if (!(tmp & PIPECONF_ENABLE))
8859                 return false;
8860
8861         switch (tmp & PIPECONF_BPC_MASK) {
8862         case PIPECONF_6BPC:
8863                 pipe_config->pipe_bpp = 18;
8864                 break;
8865         case PIPECONF_8BPC:
8866                 pipe_config->pipe_bpp = 24;
8867                 break;
8868         case PIPECONF_10BPC:
8869                 pipe_config->pipe_bpp = 30;
8870                 break;
8871         case PIPECONF_12BPC:
8872                 pipe_config->pipe_bpp = 36;
8873                 break;
8874         default:
8875                 break;
8876         }
8877
8878         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8879                 pipe_config->limited_color_range = true;
8880
8881         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8882                 struct intel_shared_dpll *pll;
8883
8884                 pipe_config->has_pch_encoder = true;
8885
8886                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8887                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8888                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8889
8890                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8891
8892                 if (HAS_PCH_IBX(dev_priv->dev)) {
8893                         pipe_config->shared_dpll =
8894                                 (enum intel_dpll_id) crtc->pipe;
8895                 } else {
8896                         tmp = I915_READ(PCH_DPLL_SEL);
8897                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8898                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8899                         else
8900                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8901                 }
8902
8903                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8904
8905                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8906                                            &pipe_config->dpll_hw_state));
8907
8908                 tmp = pipe_config->dpll_hw_state.dpll;
8909                 pipe_config->pixel_multiplier =
8910                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8911                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8912
8913                 ironlake_pch_clock_get(crtc, pipe_config);
8914         } else {
8915                 pipe_config->pixel_multiplier = 1;
8916         }
8917
8918         intel_get_pipe_timings(crtc, pipe_config);
8919
8920         ironlake_get_pfit_config(crtc, pipe_config);
8921
8922         return true;
8923 }
8924
8925 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8926 {
8927         struct drm_device *dev = dev_priv->dev;
8928         struct intel_crtc *crtc;
8929
8930         for_each_intel_crtc(dev, crtc)
8931                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8932                      pipe_name(crtc->pipe));
8933
8934         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8935         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8936         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8937         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8938         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8939         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8940              "CPU PWM1 enabled\n");
8941         if (IS_HASWELL(dev))
8942                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8943                      "CPU PWM2 enabled\n");
8944         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8945              "PCH PWM1 enabled\n");
8946         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8947              "Utility pin enabled\n");
8948         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8949
8950         /*
8951          * In theory we can still leave IRQs enabled, as long as only the HPD
8952          * interrupts remain enabled. We used to check for that, but since it's
8953          * gen-specific and since we only disable LCPLL after we fully disable
8954          * the interrupts, the check below should be enough.
8955          */
8956         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8957 }
8958
8959 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8960 {
8961         struct drm_device *dev = dev_priv->dev;
8962
8963         if (IS_HASWELL(dev))
8964                 return I915_READ(D_COMP_HSW);
8965         else
8966                 return I915_READ(D_COMP_BDW);
8967 }
8968
8969 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8970 {
8971         struct drm_device *dev = dev_priv->dev;
8972
8973         if (IS_HASWELL(dev)) {
8974                 mutex_lock(&dev_priv->rps.hw_lock);
8975                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8976                                             val))
8977                         DRM_ERROR("Failed to write to D_COMP\n");
8978                 mutex_unlock(&dev_priv->rps.hw_lock);
8979         } else {
8980                 I915_WRITE(D_COMP_BDW, val);
8981                 POSTING_READ(D_COMP_BDW);
8982         }
8983 }
8984
8985 /*
8986  * This function implements pieces of two sequences from BSpec:
8987  * - Sequence for display software to disable LCPLL
8988  * - Sequence for display software to allow package C8+
8989  * The steps implemented here are just the steps that actually touch the LCPLL
8990  * register. Callers should take care of disabling all the display engine
8991  * functions, doing the mode unset, fixing interrupts, etc.
8992  */
8993 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8994                               bool switch_to_fclk, bool allow_power_down)
8995 {
8996         uint32_t val;
8997
8998         assert_can_disable_lcpll(dev_priv);
8999
9000         val = I915_READ(LCPLL_CTL);
9001
9002         if (switch_to_fclk) {
9003                 val |= LCPLL_CD_SOURCE_FCLK;
9004                 I915_WRITE(LCPLL_CTL, val);
9005
9006                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9007                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9008                         DRM_ERROR("Switching to FCLK failed\n");
9009
9010                 val = I915_READ(LCPLL_CTL);
9011         }
9012
9013         val |= LCPLL_PLL_DISABLE;
9014         I915_WRITE(LCPLL_CTL, val);
9015         POSTING_READ(LCPLL_CTL);
9016
9017         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9018                 DRM_ERROR("LCPLL still locked\n");
9019
9020         val = hsw_read_dcomp(dev_priv);
9021         val |= D_COMP_COMP_DISABLE;
9022         hsw_write_dcomp(dev_priv, val);
9023         ndelay(100);
9024
9025         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9026                      1))
9027                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9028
9029         if (allow_power_down) {
9030                 val = I915_READ(LCPLL_CTL);
9031                 val |= LCPLL_POWER_DOWN_ALLOW;
9032                 I915_WRITE(LCPLL_CTL, val);
9033                 POSTING_READ(LCPLL_CTL);
9034         }
9035 }
9036
9037 /*
9038  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9039  * source.
9040  */
9041 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9042 {
9043         uint32_t val;
9044
9045         val = I915_READ(LCPLL_CTL);
9046
9047         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9048                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9049                 return;
9050
9051         /*
9052          * Make sure we're not on PC8 state before disabling PC8, otherwise
9053          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9054          */
9055         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9056
9057         if (val & LCPLL_POWER_DOWN_ALLOW) {
9058                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9059                 I915_WRITE(LCPLL_CTL, val);
9060                 POSTING_READ(LCPLL_CTL);
9061         }
9062
9063         val = hsw_read_dcomp(dev_priv);
9064         val |= D_COMP_COMP_FORCE;
9065         val &= ~D_COMP_COMP_DISABLE;
9066         hsw_write_dcomp(dev_priv, val);
9067
9068         val = I915_READ(LCPLL_CTL);
9069         val &= ~LCPLL_PLL_DISABLE;
9070         I915_WRITE(LCPLL_CTL, val);
9071
9072         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9073                 DRM_ERROR("LCPLL not locked yet\n");
9074
9075         if (val & LCPLL_CD_SOURCE_FCLK) {
9076                 val = I915_READ(LCPLL_CTL);
9077                 val &= ~LCPLL_CD_SOURCE_FCLK;
9078                 I915_WRITE(LCPLL_CTL, val);
9079
9080                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9081                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9082                         DRM_ERROR("Switching back to LCPLL failed\n");
9083         }
9084
9085         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9086 }
9087
9088 /*
9089  * Package states C8 and deeper are really deep PC states that can only be
9090  * reached when all the devices on the system allow it, so even if the graphics
9091  * device allows PC8+, it doesn't mean the system will actually get to these
9092  * states. Our driver only allows PC8+ when going into runtime PM.
9093  *
9094  * The requirements for PC8+ are that all the outputs are disabled, the power
9095  * well is disabled and most interrupts are disabled, and these are also
9096  * requirements for runtime PM. When these conditions are met, we manually do
9097  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9098  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9099  * hang the machine.
9100  *
9101  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9102  * the state of some registers, so when we come back from PC8+ we need to
9103  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9104  * need to take care of the registers kept by RC6. Notice that this happens even
9105  * if we don't put the device in PCI D3 state (which is what currently happens
9106  * because of the runtime PM support).
9107  *
9108  * For more, read "Display Sequences for Package C8" on the hardware
9109  * documentation.
9110  */
9111 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9112 {
9113         struct drm_device *dev = dev_priv->dev;
9114         uint32_t val;
9115
9116         DRM_DEBUG_KMS("Enabling package C8+\n");
9117
9118         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9119                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9120                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9121                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9122         }
9123
9124         lpt_disable_clkout_dp(dev);
9125         hsw_disable_lcpll(dev_priv, true, true);
9126 }
9127
9128 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9129 {
9130         struct drm_device *dev = dev_priv->dev;
9131         uint32_t val;
9132
9133         DRM_DEBUG_KMS("Disabling package C8+\n");
9134
9135         hsw_restore_lcpll(dev_priv);
9136         lpt_init_pch_refclk(dev);
9137
9138         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9139                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9140                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9141                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9142         }
9143
9144         intel_prepare_ddi(dev);
9145 }
9146
9147 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9148 {
9149         struct drm_device *dev = old_state->dev;
9150         struct drm_i915_private *dev_priv = dev->dev_private;
9151         int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9152         int req_cdclk;
9153
9154         /* see the comment in valleyview_modeset_global_resources */
9155         if (WARN_ON(max_pixclk < 0))
9156                 return;
9157
9158         req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9159
9160         if (req_cdclk != dev_priv->cdclk_freq)
9161                 broxton_set_cdclk(dev, req_cdclk);
9162 }
9163
9164 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9165                                       struct intel_crtc_state *crtc_state)
9166 {
9167         if (!intel_ddi_pll_select(crtc, crtc_state))
9168                 return -EINVAL;
9169
9170         crtc->lowfreq_avail = false;
9171
9172         return 0;
9173 }
9174
9175 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9176                                 enum port port,
9177                                 struct intel_crtc_state *pipe_config)
9178 {
9179         switch (port) {
9180         case PORT_A:
9181                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9182                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9183                 break;
9184         case PORT_B:
9185                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9186                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9187                 break;
9188         case PORT_C:
9189                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9190                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9191                 break;
9192         default:
9193                 DRM_ERROR("Incorrect port type\n");
9194         }
9195 }
9196
9197 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9198                                 enum port port,
9199                                 struct intel_crtc_state *pipe_config)
9200 {
9201         u32 temp, dpll_ctl1;
9202
9203         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9204         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9205
9206         switch (pipe_config->ddi_pll_sel) {
9207         case SKL_DPLL0:
9208                 /*
9209                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9210                  * of the shared DPLL framework and thus needs to be read out
9211                  * separately
9212                  */
9213                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9214                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9215                 break;
9216         case SKL_DPLL1:
9217                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9218                 break;
9219         case SKL_DPLL2:
9220                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9221                 break;
9222         case SKL_DPLL3:
9223                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9224                 break;
9225         }
9226 }
9227
9228 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9229                                 enum port port,
9230                                 struct intel_crtc_state *pipe_config)
9231 {
9232         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9233
9234         switch (pipe_config->ddi_pll_sel) {
9235         case PORT_CLK_SEL_WRPLL1:
9236                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9237                 break;
9238         case PORT_CLK_SEL_WRPLL2:
9239                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9240                 break;
9241         }
9242 }
9243
9244 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9245                                        struct intel_crtc_state *pipe_config)
9246 {
9247         struct drm_device *dev = crtc->base.dev;
9248         struct drm_i915_private *dev_priv = dev->dev_private;
9249         struct intel_shared_dpll *pll;
9250         enum port port;
9251         uint32_t tmp;
9252
9253         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9254
9255         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9256
9257         if (IS_SKYLAKE(dev))
9258                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9259         else if (IS_BROXTON(dev))
9260                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9261         else
9262                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9263
9264         if (pipe_config->shared_dpll >= 0) {
9265                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9266
9267                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9268                                            &pipe_config->dpll_hw_state));
9269         }
9270
9271         /*
9272          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9273          * DDI E. So just check whether this pipe is wired to DDI E and whether
9274          * the PCH transcoder is on.
9275          */
9276         if (INTEL_INFO(dev)->gen < 9 &&
9277             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9278                 pipe_config->has_pch_encoder = true;
9279
9280                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9281                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9282                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9283
9284                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9285         }
9286 }
9287
9288 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9289                                     struct intel_crtc_state *pipe_config)
9290 {
9291         struct drm_device *dev = crtc->base.dev;
9292         struct drm_i915_private *dev_priv = dev->dev_private;
9293         enum intel_display_power_domain pfit_domain;
9294         uint32_t tmp;
9295
9296         if (!intel_display_power_is_enabled(dev_priv,
9297                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9298                 return false;
9299
9300         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9301         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9302
9303         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9304         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9305                 enum pipe trans_edp_pipe;
9306                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9307                 default:
9308                         WARN(1, "unknown pipe linked to edp transcoder\n");
9309                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9310                 case TRANS_DDI_EDP_INPUT_A_ON:
9311                         trans_edp_pipe = PIPE_A;
9312                         break;
9313                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9314                         trans_edp_pipe = PIPE_B;
9315                         break;
9316                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9317                         trans_edp_pipe = PIPE_C;
9318                         break;
9319                 }
9320
9321                 if (trans_edp_pipe == crtc->pipe)
9322                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9323         }
9324
9325         if (!intel_display_power_is_enabled(dev_priv,
9326                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9327                 return false;
9328
9329         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9330         if (!(tmp & PIPECONF_ENABLE))
9331                 return false;
9332
9333         haswell_get_ddi_port_state(crtc, pipe_config);
9334
9335         intel_get_pipe_timings(crtc, pipe_config);
9336
9337         if (INTEL_INFO(dev)->gen >= 9) {
9338                 skl_init_scalers(dev, crtc, pipe_config);
9339         }
9340
9341         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9342
9343         if (INTEL_INFO(dev)->gen >= 9) {
9344                 pipe_config->scaler_state.scaler_id = -1;
9345                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9346         }
9347
9348         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9349                 if (INTEL_INFO(dev)->gen == 9)
9350                         skylake_get_pfit_config(crtc, pipe_config);
9351                 else if (INTEL_INFO(dev)->gen < 9)
9352                         ironlake_get_pfit_config(crtc, pipe_config);
9353                 else
9354                         MISSING_CASE(INTEL_INFO(dev)->gen);
9355         }
9356
9357         if (IS_HASWELL(dev))
9358                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9359                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9360
9361         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9362                 pipe_config->pixel_multiplier =
9363                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9364         } else {
9365                 pipe_config->pixel_multiplier = 1;
9366         }
9367
9368         return true;
9369 }
9370
9371 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9372 {
9373         struct drm_device *dev = crtc->dev;
9374         struct drm_i915_private *dev_priv = dev->dev_private;
9375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9376         uint32_t cntl = 0, size = 0;
9377
9378         if (base) {
9379                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9380                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9381                 unsigned int stride = roundup_pow_of_two(width) * 4;
9382
9383                 switch (stride) {
9384                 default:
9385                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9386                                   width, stride);
9387                         stride = 256;
9388                         /* fallthrough */
9389                 case 256:
9390                 case 512:
9391                 case 1024:
9392                 case 2048:
9393                         break;
9394                 }
9395
9396                 cntl |= CURSOR_ENABLE |
9397                         CURSOR_GAMMA_ENABLE |
9398                         CURSOR_FORMAT_ARGB |
9399                         CURSOR_STRIDE(stride);
9400
9401                 size = (height << 12) | width;
9402         }
9403
9404         if (intel_crtc->cursor_cntl != 0 &&
9405             (intel_crtc->cursor_base != base ||
9406              intel_crtc->cursor_size != size ||
9407              intel_crtc->cursor_cntl != cntl)) {
9408                 /* On these chipsets we can only modify the base/size/stride
9409                  * whilst the cursor is disabled.
9410                  */
9411                 I915_WRITE(_CURACNTR, 0);
9412                 POSTING_READ(_CURACNTR);
9413                 intel_crtc->cursor_cntl = 0;
9414         }
9415
9416         if (intel_crtc->cursor_base != base) {
9417                 I915_WRITE(_CURABASE, base);
9418                 intel_crtc->cursor_base = base;
9419         }
9420
9421         if (intel_crtc->cursor_size != size) {
9422                 I915_WRITE(CURSIZE, size);
9423                 intel_crtc->cursor_size = size;
9424         }
9425
9426         if (intel_crtc->cursor_cntl != cntl) {
9427                 I915_WRITE(_CURACNTR, cntl);
9428                 POSTING_READ(_CURACNTR);
9429                 intel_crtc->cursor_cntl = cntl;
9430         }
9431 }
9432
9433 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9434 {
9435         struct drm_device *dev = crtc->dev;
9436         struct drm_i915_private *dev_priv = dev->dev_private;
9437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9438         int pipe = intel_crtc->pipe;
9439         uint32_t cntl;
9440
9441         cntl = 0;
9442         if (base) {
9443                 cntl = MCURSOR_GAMMA_ENABLE;
9444                 switch (intel_crtc->base.cursor->state->crtc_w) {
9445                         case 64:
9446                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9447                                 break;
9448                         case 128:
9449                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9450                                 break;
9451                         case 256:
9452                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9453                                 break;
9454                         default:
9455                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9456                                 return;
9457                 }
9458                 cntl |= pipe << 28; /* Connect to correct pipe */
9459
9460                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9461                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9462         }
9463
9464         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9465                 cntl |= CURSOR_ROTATE_180;
9466
9467         if (intel_crtc->cursor_cntl != cntl) {
9468                 I915_WRITE(CURCNTR(pipe), cntl);
9469                 POSTING_READ(CURCNTR(pipe));
9470                 intel_crtc->cursor_cntl = cntl;
9471         }
9472
9473         /* and commit changes on next vblank */
9474         I915_WRITE(CURBASE(pipe), base);
9475         POSTING_READ(CURBASE(pipe));
9476
9477         intel_crtc->cursor_base = base;
9478 }
9479
9480 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9481 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9482                                      bool on)
9483 {
9484         struct drm_device *dev = crtc->dev;
9485         struct drm_i915_private *dev_priv = dev->dev_private;
9486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9487         int pipe = intel_crtc->pipe;
9488         int x = crtc->cursor_x;
9489         int y = crtc->cursor_y;
9490         u32 base = 0, pos = 0;
9491
9492         if (on)
9493                 base = intel_crtc->cursor_addr;
9494
9495         if (x >= intel_crtc->config->pipe_src_w)
9496                 base = 0;
9497
9498         if (y >= intel_crtc->config->pipe_src_h)
9499                 base = 0;
9500
9501         if (x < 0) {
9502                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9503                         base = 0;
9504
9505                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9506                 x = -x;
9507         }
9508         pos |= x << CURSOR_X_SHIFT;
9509
9510         if (y < 0) {
9511                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9512                         base = 0;
9513
9514                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9515                 y = -y;
9516         }
9517         pos |= y << CURSOR_Y_SHIFT;
9518
9519         if (base == 0 && intel_crtc->cursor_base == 0)
9520                 return;
9521
9522         I915_WRITE(CURPOS(pipe), pos);
9523
9524         /* ILK+ do this automagically */
9525         if (HAS_GMCH_DISPLAY(dev) &&
9526             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9527                 base += (intel_crtc->base.cursor->state->crtc_h *
9528                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9529         }
9530
9531         if (IS_845G(dev) || IS_I865G(dev))
9532                 i845_update_cursor(crtc, base);
9533         else
9534                 i9xx_update_cursor(crtc, base);
9535 }
9536
9537 static bool cursor_size_ok(struct drm_device *dev,
9538                            uint32_t width, uint32_t height)
9539 {
9540         if (width == 0 || height == 0)
9541                 return false;
9542
9543         /*
9544          * 845g/865g are special in that they are only limited by
9545          * the width of their cursors, the height is arbitrary up to
9546          * the precision of the register. Everything else requires
9547          * square cursors, limited to a few power-of-two sizes.
9548          */
9549         if (IS_845G(dev) || IS_I865G(dev)) {
9550                 if ((width & 63) != 0)
9551                         return false;
9552
9553                 if (width > (IS_845G(dev) ? 64 : 512))
9554                         return false;
9555
9556                 if (height > 1023)
9557                         return false;
9558         } else {
9559                 switch (width | height) {
9560                 case 256:
9561                 case 128:
9562                         if (IS_GEN2(dev))
9563                                 return false;
9564                 case 64:
9565                         break;
9566                 default:
9567                         return false;
9568                 }
9569         }
9570
9571         return true;
9572 }
9573
9574 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9575                                  u16 *blue, uint32_t start, uint32_t size)
9576 {
9577         int end = (start + size > 256) ? 256 : start + size, i;
9578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9579
9580         for (i = start; i < end; i++) {
9581                 intel_crtc->lut_r[i] = red[i] >> 8;
9582                 intel_crtc->lut_g[i] = green[i] >> 8;
9583                 intel_crtc->lut_b[i] = blue[i] >> 8;
9584         }
9585
9586         intel_crtc_load_lut(crtc);
9587 }
9588
9589 /* VESA 640x480x72Hz mode to set on the pipe */
9590 static struct drm_display_mode load_detect_mode = {
9591         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9592                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9593 };
9594
9595 struct drm_framebuffer *
9596 __intel_framebuffer_create(struct drm_device *dev,
9597                            struct drm_mode_fb_cmd2 *mode_cmd,
9598                            struct drm_i915_gem_object *obj)
9599 {
9600         struct intel_framebuffer *intel_fb;
9601         int ret;
9602
9603         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9604         if (!intel_fb) {
9605                 drm_gem_object_unreference(&obj->base);
9606                 return ERR_PTR(-ENOMEM);
9607         }
9608
9609         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9610         if (ret)
9611                 goto err;
9612
9613         return &intel_fb->base;
9614 err:
9615         drm_gem_object_unreference(&obj->base);
9616         kfree(intel_fb);
9617
9618         return ERR_PTR(ret);
9619 }
9620
9621 static struct drm_framebuffer *
9622 intel_framebuffer_create(struct drm_device *dev,
9623                          struct drm_mode_fb_cmd2 *mode_cmd,
9624                          struct drm_i915_gem_object *obj)
9625 {
9626         struct drm_framebuffer *fb;
9627         int ret;
9628
9629         ret = i915_mutex_lock_interruptible(dev);
9630         if (ret)
9631                 return ERR_PTR(ret);
9632         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9633         mutex_unlock(&dev->struct_mutex);
9634
9635         return fb;
9636 }
9637
9638 static u32
9639 intel_framebuffer_pitch_for_width(int width, int bpp)
9640 {
9641         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9642         return ALIGN(pitch, 64);
9643 }
9644
9645 static u32
9646 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9647 {
9648         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9649         return PAGE_ALIGN(pitch * mode->vdisplay);
9650 }
9651
9652 static struct drm_framebuffer *
9653 intel_framebuffer_create_for_mode(struct drm_device *dev,
9654                                   struct drm_display_mode *mode,
9655                                   int depth, int bpp)
9656 {
9657         struct drm_i915_gem_object *obj;
9658         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9659
9660         obj = i915_gem_alloc_object(dev,
9661                                     intel_framebuffer_size_for_mode(mode, bpp));
9662         if (obj == NULL)
9663                 return ERR_PTR(-ENOMEM);
9664
9665         mode_cmd.width = mode->hdisplay;
9666         mode_cmd.height = mode->vdisplay;
9667         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9668                                                                 bpp);
9669         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9670
9671         return intel_framebuffer_create(dev, &mode_cmd, obj);
9672 }
9673
9674 static struct drm_framebuffer *
9675 mode_fits_in_fbdev(struct drm_device *dev,
9676                    struct drm_display_mode *mode)
9677 {
9678 #ifdef CONFIG_DRM_I915_FBDEV
9679         struct drm_i915_private *dev_priv = dev->dev_private;
9680         struct drm_i915_gem_object *obj;
9681         struct drm_framebuffer *fb;
9682
9683         if (!dev_priv->fbdev)
9684                 return NULL;
9685
9686         if (!dev_priv->fbdev->fb)
9687                 return NULL;
9688
9689         obj = dev_priv->fbdev->fb->obj;
9690         BUG_ON(!obj);
9691
9692         fb = &dev_priv->fbdev->fb->base;
9693         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9694                                                                fb->bits_per_pixel))
9695                 return NULL;
9696
9697         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9698                 return NULL;
9699
9700         return fb;
9701 #else
9702         return NULL;
9703 #endif
9704 }
9705
9706 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9707                                            struct drm_crtc *crtc,
9708                                            struct drm_display_mode *mode,
9709                                            struct drm_framebuffer *fb,
9710                                            int x, int y)
9711 {
9712         struct drm_plane_state *plane_state;
9713         int hdisplay, vdisplay;
9714         int ret;
9715
9716         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9717         if (IS_ERR(plane_state))
9718                 return PTR_ERR(plane_state);
9719
9720         if (mode)
9721                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9722         else
9723                 hdisplay = vdisplay = 0;
9724
9725         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9726         if (ret)
9727                 return ret;
9728         drm_atomic_set_fb_for_plane(plane_state, fb);
9729         plane_state->crtc_x = 0;
9730         plane_state->crtc_y = 0;
9731         plane_state->crtc_w = hdisplay;
9732         plane_state->crtc_h = vdisplay;
9733         plane_state->src_x = x << 16;
9734         plane_state->src_y = y << 16;
9735         plane_state->src_w = hdisplay << 16;
9736         plane_state->src_h = vdisplay << 16;
9737
9738         return 0;
9739 }
9740
9741 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9742                                 struct drm_display_mode *mode,
9743                                 struct intel_load_detect_pipe *old,
9744                                 struct drm_modeset_acquire_ctx *ctx)
9745 {
9746         struct intel_crtc *intel_crtc;
9747         struct intel_encoder *intel_encoder =
9748                 intel_attached_encoder(connector);
9749         struct drm_crtc *possible_crtc;
9750         struct drm_encoder *encoder = &intel_encoder->base;
9751         struct drm_crtc *crtc = NULL;
9752         struct drm_device *dev = encoder->dev;
9753         struct drm_framebuffer *fb;
9754         struct drm_mode_config *config = &dev->mode_config;
9755         struct drm_atomic_state *state = NULL;
9756         struct drm_connector_state *connector_state;
9757         struct intel_crtc_state *crtc_state;
9758         int ret, i = -1;
9759
9760         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9761                       connector->base.id, connector->name,
9762                       encoder->base.id, encoder->name);
9763
9764 retry:
9765         ret = drm_modeset_lock(&config->connection_mutex, ctx);
9766         if (ret)
9767                 goto fail_unlock;
9768
9769         /*
9770          * Algorithm gets a little messy:
9771          *
9772          *   - if the connector already has an assigned crtc, use it (but make
9773          *     sure it's on first)
9774          *
9775          *   - try to find the first unused crtc that can drive this connector,
9776          *     and use that if we find one
9777          */
9778
9779         /* See if we already have a CRTC for this connector */
9780         if (encoder->crtc) {
9781                 crtc = encoder->crtc;
9782
9783                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9784                 if (ret)
9785                         goto fail_unlock;
9786                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9787                 if (ret)
9788                         goto fail_unlock;
9789
9790                 old->dpms_mode = connector->dpms;
9791                 old->load_detect_temp = false;
9792
9793                 /* Make sure the crtc and connector are running */
9794                 if (connector->dpms != DRM_MODE_DPMS_ON)
9795                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9796
9797                 return true;
9798         }
9799
9800         /* Find an unused one (if possible) */
9801         for_each_crtc(dev, possible_crtc) {
9802                 i++;
9803                 if (!(encoder->possible_crtcs & (1 << i)))
9804                         continue;
9805                 if (possible_crtc->state->enable)
9806                         continue;
9807                 /* This can occur when applying the pipe A quirk on resume. */
9808                 if (to_intel_crtc(possible_crtc)->new_enabled)
9809                         continue;
9810
9811                 crtc = possible_crtc;
9812                 break;
9813         }
9814
9815         /*
9816          * If we didn't find an unused CRTC, don't use any.
9817          */
9818         if (!crtc) {
9819                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9820                 goto fail_unlock;
9821         }
9822
9823         ret = drm_modeset_lock(&crtc->mutex, ctx);
9824         if (ret)
9825                 goto fail_unlock;
9826         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9827         if (ret)
9828                 goto fail_unlock;
9829         intel_encoder->new_crtc = to_intel_crtc(crtc);
9830         to_intel_connector(connector)->new_encoder = intel_encoder;
9831
9832         intel_crtc = to_intel_crtc(crtc);
9833         intel_crtc->new_enabled = true;
9834         old->dpms_mode = connector->dpms;
9835         old->load_detect_temp = true;
9836         old->release_fb = NULL;
9837
9838         state = drm_atomic_state_alloc(dev);
9839         if (!state)
9840                 return false;
9841
9842         state->acquire_ctx = ctx;
9843
9844         connector_state = drm_atomic_get_connector_state(state, connector);
9845         if (IS_ERR(connector_state)) {
9846                 ret = PTR_ERR(connector_state);
9847                 goto fail;
9848         }
9849
9850         connector_state->crtc = crtc;
9851         connector_state->best_encoder = &intel_encoder->base;
9852
9853         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9854         if (IS_ERR(crtc_state)) {
9855                 ret = PTR_ERR(crtc_state);
9856                 goto fail;
9857         }
9858
9859         crtc_state->base.active = crtc_state->base.enable = true;
9860
9861         if (!mode)
9862                 mode = &load_detect_mode;
9863
9864         /* We need a framebuffer large enough to accommodate all accesses
9865          * that the plane may generate whilst we perform load detection.
9866          * We can not rely on the fbcon either being present (we get called
9867          * during its initialisation to detect all boot displays, or it may
9868          * not even exist) or that it is large enough to satisfy the
9869          * requested mode.
9870          */
9871         fb = mode_fits_in_fbdev(dev, mode);
9872         if (fb == NULL) {
9873                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9874                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9875                 old->release_fb = fb;
9876         } else
9877                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9878         if (IS_ERR(fb)) {
9879                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9880                 goto fail;
9881         }
9882
9883         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9884         if (ret)
9885                 goto fail;
9886
9887         drm_mode_copy(&crtc_state->base.mode, mode);
9888
9889         if (intel_set_mode(crtc, state)) {
9890                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9891                 if (old->release_fb)
9892                         old->release_fb->funcs->destroy(old->release_fb);
9893                 goto fail;
9894         }
9895         crtc->primary->crtc = crtc;
9896
9897         /* let the connector get through one full cycle before testing */
9898         intel_wait_for_vblank(dev, intel_crtc->pipe);
9899         return true;
9900
9901  fail:
9902         intel_crtc->new_enabled = crtc->state->enable;
9903 fail_unlock:
9904         drm_atomic_state_free(state);
9905         state = NULL;
9906
9907         if (ret == -EDEADLK) {
9908                 drm_modeset_backoff(ctx);
9909                 goto retry;
9910         }
9911
9912         return false;
9913 }
9914
9915 void intel_release_load_detect_pipe(struct drm_connector *connector,
9916                                     struct intel_load_detect_pipe *old,
9917                                     struct drm_modeset_acquire_ctx *ctx)
9918 {
9919         struct drm_device *dev = connector->dev;
9920         struct intel_encoder *intel_encoder =
9921                 intel_attached_encoder(connector);
9922         struct drm_encoder *encoder = &intel_encoder->base;
9923         struct drm_crtc *crtc = encoder->crtc;
9924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9925         struct drm_atomic_state *state;
9926         struct drm_connector_state *connector_state;
9927         struct intel_crtc_state *crtc_state;
9928         int ret;
9929
9930         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9931                       connector->base.id, connector->name,
9932                       encoder->base.id, encoder->name);
9933
9934         if (old->load_detect_temp) {
9935                 state = drm_atomic_state_alloc(dev);
9936                 if (!state)
9937                         goto fail;
9938
9939                 state->acquire_ctx = ctx;
9940
9941                 connector_state = drm_atomic_get_connector_state(state, connector);
9942                 if (IS_ERR(connector_state))
9943                         goto fail;
9944
9945                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9946                 if (IS_ERR(crtc_state))
9947                         goto fail;
9948
9949                 to_intel_connector(connector)->new_encoder = NULL;
9950                 intel_encoder->new_crtc = NULL;
9951                 intel_crtc->new_enabled = false;
9952
9953                 connector_state->best_encoder = NULL;
9954                 connector_state->crtc = NULL;
9955
9956                 crtc_state->base.enable = crtc_state->base.active = false;
9957
9958                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9959                                                       0, 0);
9960                 if (ret)
9961                         goto fail;
9962
9963                 ret = intel_set_mode(crtc, state);
9964                 if (ret)
9965                         goto fail;
9966
9967                 if (old->release_fb) {
9968                         drm_framebuffer_unregister_private(old->release_fb);
9969                         drm_framebuffer_unreference(old->release_fb);
9970                 }
9971
9972                 return;
9973         }
9974
9975         /* Switch crtc and encoder back off if necessary */
9976         if (old->dpms_mode != DRM_MODE_DPMS_ON)
9977                 connector->funcs->dpms(connector, old->dpms_mode);
9978
9979         return;
9980 fail:
9981         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9982         drm_atomic_state_free(state);
9983 }
9984
9985 static int i9xx_pll_refclk(struct drm_device *dev,
9986                            const struct intel_crtc_state *pipe_config)
9987 {
9988         struct drm_i915_private *dev_priv = dev->dev_private;
9989         u32 dpll = pipe_config->dpll_hw_state.dpll;
9990
9991         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9992                 return dev_priv->vbt.lvds_ssc_freq;
9993         else if (HAS_PCH_SPLIT(dev))
9994                 return 120000;
9995         else if (!IS_GEN2(dev))
9996                 return 96000;
9997         else
9998                 return 48000;
9999 }
10000
10001 /* Returns the clock of the currently programmed mode of the given pipe. */
10002 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10003                                 struct intel_crtc_state *pipe_config)
10004 {
10005         struct drm_device *dev = crtc->base.dev;
10006         struct drm_i915_private *dev_priv = dev->dev_private;
10007         int pipe = pipe_config->cpu_transcoder;
10008         u32 dpll = pipe_config->dpll_hw_state.dpll;
10009         u32 fp;
10010         intel_clock_t clock;
10011         int refclk = i9xx_pll_refclk(dev, pipe_config);
10012
10013         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10014                 fp = pipe_config->dpll_hw_state.fp0;
10015         else
10016                 fp = pipe_config->dpll_hw_state.fp1;
10017
10018         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10019         if (IS_PINEVIEW(dev)) {
10020                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10021                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10022         } else {
10023                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10024                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10025         }
10026
10027         if (!IS_GEN2(dev)) {
10028                 if (IS_PINEVIEW(dev))
10029                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10030                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10031                 else
10032                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10033                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10034
10035                 switch (dpll & DPLL_MODE_MASK) {
10036                 case DPLLB_MODE_DAC_SERIAL:
10037                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10038                                 5 : 10;
10039                         break;
10040                 case DPLLB_MODE_LVDS:
10041                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10042                                 7 : 14;
10043                         break;
10044                 default:
10045                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10046                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10047                         return;
10048                 }
10049
10050                 if (IS_PINEVIEW(dev))
10051                         pineview_clock(refclk, &clock);
10052                 else
10053                         i9xx_clock(refclk, &clock);
10054         } else {
10055                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10056                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10057
10058                 if (is_lvds) {
10059                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10060                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10061
10062                         if (lvds & LVDS_CLKB_POWER_UP)
10063                                 clock.p2 = 7;
10064                         else
10065                                 clock.p2 = 14;
10066                 } else {
10067                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10068                                 clock.p1 = 2;
10069                         else {
10070                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10071                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10072                         }
10073                         if (dpll & PLL_P2_DIVIDE_BY_4)
10074                                 clock.p2 = 4;
10075                         else
10076                                 clock.p2 = 2;
10077                 }
10078
10079                 i9xx_clock(refclk, &clock);
10080         }
10081
10082         /*
10083          * This value includes pixel_multiplier. We will use
10084          * port_clock to compute adjusted_mode.crtc_clock in the
10085          * encoder's get_config() function.
10086          */
10087         pipe_config->port_clock = clock.dot;
10088 }
10089
10090 int intel_dotclock_calculate(int link_freq,
10091                              const struct intel_link_m_n *m_n)
10092 {
10093         /*
10094          * The calculation for the data clock is:
10095          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10096          * But we want to avoid losing precison if possible, so:
10097          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10098          *
10099          * and the link clock is simpler:
10100          * link_clock = (m * link_clock) / n
10101          */
10102
10103         if (!m_n->link_n)
10104                 return 0;
10105
10106         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10107 }
10108
10109 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10110                                    struct intel_crtc_state *pipe_config)
10111 {
10112         struct drm_device *dev = crtc->base.dev;
10113
10114         /* read out port_clock from the DPLL */
10115         i9xx_crtc_clock_get(crtc, pipe_config);
10116
10117         /*
10118          * This value does not include pixel_multiplier.
10119          * We will check that port_clock and adjusted_mode.crtc_clock
10120          * agree once we know their relationship in the encoder's
10121          * get_config() function.
10122          */
10123         pipe_config->base.adjusted_mode.crtc_clock =
10124                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10125                                          &pipe_config->fdi_m_n);
10126 }
10127
10128 /** Returns the currently programmed mode of the given pipe. */
10129 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10130                                              struct drm_crtc *crtc)
10131 {
10132         struct drm_i915_private *dev_priv = dev->dev_private;
10133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10134         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10135         struct drm_display_mode *mode;
10136         struct intel_crtc_state pipe_config;
10137         int htot = I915_READ(HTOTAL(cpu_transcoder));
10138         int hsync = I915_READ(HSYNC(cpu_transcoder));
10139         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10140         int vsync = I915_READ(VSYNC(cpu_transcoder));
10141         enum pipe pipe = intel_crtc->pipe;
10142
10143         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10144         if (!mode)
10145                 return NULL;
10146
10147         /*
10148          * Construct a pipe_config sufficient for getting the clock info
10149          * back out of crtc_clock_get.
10150          *
10151          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10152          * to use a real value here instead.
10153          */
10154         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10155         pipe_config.pixel_multiplier = 1;
10156         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10157         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10158         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10159         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10160
10161         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10162         mode->hdisplay = (htot & 0xffff) + 1;
10163         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10164         mode->hsync_start = (hsync & 0xffff) + 1;
10165         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10166         mode->vdisplay = (vtot & 0xffff) + 1;
10167         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10168         mode->vsync_start = (vsync & 0xffff) + 1;
10169         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10170
10171         drm_mode_set_name(mode);
10172
10173         return mode;
10174 }
10175
10176 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10177 {
10178         struct drm_device *dev = crtc->dev;
10179         struct drm_i915_private *dev_priv = dev->dev_private;
10180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10181
10182         if (!HAS_GMCH_DISPLAY(dev))
10183                 return;
10184
10185         if (!dev_priv->lvds_downclock_avail)
10186                 return;
10187
10188         /*
10189          * Since this is called by a timer, we should never get here in
10190          * the manual case.
10191          */
10192         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10193                 int pipe = intel_crtc->pipe;
10194                 int dpll_reg = DPLL(pipe);
10195                 int dpll;
10196
10197                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10198
10199                 assert_panel_unlocked(dev_priv, pipe);
10200
10201                 dpll = I915_READ(dpll_reg);
10202                 dpll |= DISPLAY_RATE_SELECT_FPA1;
10203                 I915_WRITE(dpll_reg, dpll);
10204                 intel_wait_for_vblank(dev, pipe);
10205                 dpll = I915_READ(dpll_reg);
10206                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10207                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10208         }
10209
10210 }
10211
10212 void intel_mark_busy(struct drm_device *dev)
10213 {
10214         struct drm_i915_private *dev_priv = dev->dev_private;
10215
10216         if (dev_priv->mm.busy)
10217                 return;
10218
10219         intel_runtime_pm_get(dev_priv);
10220         i915_update_gfx_val(dev_priv);
10221         if (INTEL_INFO(dev)->gen >= 6)
10222                 gen6_rps_busy(dev_priv);
10223         dev_priv->mm.busy = true;
10224 }
10225
10226 void intel_mark_idle(struct drm_device *dev)
10227 {
10228         struct drm_i915_private *dev_priv = dev->dev_private;
10229         struct drm_crtc *crtc;
10230
10231         if (!dev_priv->mm.busy)
10232                 return;
10233
10234         dev_priv->mm.busy = false;
10235
10236         for_each_crtc(dev, crtc) {
10237                 if (!crtc->primary->fb)
10238                         continue;
10239
10240                 intel_decrease_pllclock(crtc);
10241         }
10242
10243         if (INTEL_INFO(dev)->gen >= 6)
10244                 gen6_rps_idle(dev->dev_private);
10245
10246         intel_runtime_pm_put(dev_priv);
10247 }
10248
10249 static void intel_crtc_destroy(struct drm_crtc *crtc)
10250 {
10251         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10252         struct drm_device *dev = crtc->dev;
10253         struct intel_unpin_work *work;
10254
10255         spin_lock_irq(&dev->event_lock);
10256         work = intel_crtc->unpin_work;
10257         intel_crtc->unpin_work = NULL;
10258         spin_unlock_irq(&dev->event_lock);
10259
10260         if (work) {
10261                 cancel_work_sync(&work->work);
10262                 kfree(work);
10263         }
10264
10265         drm_crtc_cleanup(crtc);
10266
10267         kfree(intel_crtc);
10268 }
10269
10270 static void intel_unpin_work_fn(struct work_struct *__work)
10271 {
10272         struct intel_unpin_work *work =
10273                 container_of(__work, struct intel_unpin_work, work);
10274         struct drm_device *dev = work->crtc->dev;
10275         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10276
10277         mutex_lock(&dev->struct_mutex);
10278         intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10279         drm_gem_object_unreference(&work->pending_flip_obj->base);
10280
10281         intel_fbc_update(dev);
10282
10283         if (work->flip_queued_req)
10284                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10285         mutex_unlock(&dev->struct_mutex);
10286
10287         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10288         drm_framebuffer_unreference(work->old_fb);
10289
10290         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10291         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10292
10293         kfree(work);
10294 }
10295
10296 static void do_intel_finish_page_flip(struct drm_device *dev,
10297                                       struct drm_crtc *crtc)
10298 {
10299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10300         struct intel_unpin_work *work;
10301         unsigned long flags;
10302
10303         /* Ignore early vblank irqs */
10304         if (intel_crtc == NULL)
10305                 return;
10306
10307         /*
10308          * This is called both by irq handlers and the reset code (to complete
10309          * lost pageflips) so needs the full irqsave spinlocks.
10310          */
10311         spin_lock_irqsave(&dev->event_lock, flags);
10312         work = intel_crtc->unpin_work;
10313
10314         /* Ensure we don't miss a work->pending update ... */
10315         smp_rmb();
10316
10317         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10318                 spin_unlock_irqrestore(&dev->event_lock, flags);
10319                 return;
10320         }
10321
10322         page_flip_completed(intel_crtc);
10323
10324         spin_unlock_irqrestore(&dev->event_lock, flags);
10325 }
10326
10327 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10328 {
10329         struct drm_i915_private *dev_priv = dev->dev_private;
10330         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10331
10332         do_intel_finish_page_flip(dev, crtc);
10333 }
10334
10335 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10336 {
10337         struct drm_i915_private *dev_priv = dev->dev_private;
10338         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10339
10340         do_intel_finish_page_flip(dev, crtc);
10341 }
10342
10343 /* Is 'a' after or equal to 'b'? */
10344 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10345 {
10346         return !((a - b) & 0x80000000);
10347 }
10348
10349 static bool page_flip_finished(struct intel_crtc *crtc)
10350 {
10351         struct drm_device *dev = crtc->base.dev;
10352         struct drm_i915_private *dev_priv = dev->dev_private;
10353
10354         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10355             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10356                 return true;
10357
10358         /*
10359          * The relevant registers doen't exist on pre-ctg.
10360          * As the flip done interrupt doesn't trigger for mmio
10361          * flips on gmch platforms, a flip count check isn't
10362          * really needed there. But since ctg has the registers,
10363          * include it in the check anyway.
10364          */
10365         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10366                 return true;
10367
10368         /*
10369          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10370          * used the same base address. In that case the mmio flip might
10371          * have completed, but the CS hasn't even executed the flip yet.
10372          *
10373          * A flip count check isn't enough as the CS might have updated
10374          * the base address just after start of vblank, but before we
10375          * managed to process the interrupt. This means we'd complete the
10376          * CS flip too soon.
10377          *
10378          * Combining both checks should get us a good enough result. It may
10379          * still happen that the CS flip has been executed, but has not
10380          * yet actually completed. But in case the base address is the same
10381          * anyway, we don't really care.
10382          */
10383         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10384                 crtc->unpin_work->gtt_offset &&
10385                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10386                                     crtc->unpin_work->flip_count);
10387 }
10388
10389 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10390 {
10391         struct drm_i915_private *dev_priv = dev->dev_private;
10392         struct intel_crtc *intel_crtc =
10393                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10394         unsigned long flags;
10395
10396
10397         /*
10398          * This is called both by irq handlers and the reset code (to complete
10399          * lost pageflips) so needs the full irqsave spinlocks.
10400          *
10401          * NB: An MMIO update of the plane base pointer will also
10402          * generate a page-flip completion irq, i.e. every modeset
10403          * is also accompanied by a spurious intel_prepare_page_flip().
10404          */
10405         spin_lock_irqsave(&dev->event_lock, flags);
10406         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10407                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10408         spin_unlock_irqrestore(&dev->event_lock, flags);
10409 }
10410
10411 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10412 {
10413         /* Ensure that the work item is consistent when activating it ... */
10414         smp_wmb();
10415         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10416         /* and that it is marked active as soon as the irq could fire. */
10417         smp_wmb();
10418 }
10419
10420 static int intel_gen2_queue_flip(struct drm_device *dev,
10421                                  struct drm_crtc *crtc,
10422                                  struct drm_framebuffer *fb,
10423                                  struct drm_i915_gem_object *obj,
10424                                  struct intel_engine_cs *ring,
10425                                  uint32_t flags)
10426 {
10427         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10428         u32 flip_mask;
10429         int ret;
10430
10431         ret = intel_ring_begin(ring, 6);
10432         if (ret)
10433                 return ret;
10434
10435         /* Can't queue multiple flips, so wait for the previous
10436          * one to finish before executing the next.
10437          */
10438         if (intel_crtc->plane)
10439                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10440         else
10441                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10442         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10443         intel_ring_emit(ring, MI_NOOP);
10444         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10445                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10446         intel_ring_emit(ring, fb->pitches[0]);
10447         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10448         intel_ring_emit(ring, 0); /* aux display base address, unused */
10449
10450         intel_mark_page_flip_active(intel_crtc);
10451         __intel_ring_advance(ring);
10452         return 0;
10453 }
10454
10455 static int intel_gen3_queue_flip(struct drm_device *dev,
10456                                  struct drm_crtc *crtc,
10457                                  struct drm_framebuffer *fb,
10458                                  struct drm_i915_gem_object *obj,
10459                                  struct intel_engine_cs *ring,
10460                                  uint32_t flags)
10461 {
10462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10463         u32 flip_mask;
10464         int ret;
10465
10466         ret = intel_ring_begin(ring, 6);
10467         if (ret)
10468                 return ret;
10469
10470         if (intel_crtc->plane)
10471                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10472         else
10473                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10474         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10475         intel_ring_emit(ring, MI_NOOP);
10476         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10477                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10478         intel_ring_emit(ring, fb->pitches[0]);
10479         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10480         intel_ring_emit(ring, MI_NOOP);
10481
10482         intel_mark_page_flip_active(intel_crtc);
10483         __intel_ring_advance(ring);
10484         return 0;
10485 }
10486
10487 static int intel_gen4_queue_flip(struct drm_device *dev,
10488                                  struct drm_crtc *crtc,
10489                                  struct drm_framebuffer *fb,
10490                                  struct drm_i915_gem_object *obj,
10491                                  struct intel_engine_cs *ring,
10492                                  uint32_t flags)
10493 {
10494         struct drm_i915_private *dev_priv = dev->dev_private;
10495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10496         uint32_t pf, pipesrc;
10497         int ret;
10498
10499         ret = intel_ring_begin(ring, 4);
10500         if (ret)
10501                 return ret;
10502
10503         /* i965+ uses the linear or tiled offsets from the
10504          * Display Registers (which do not change across a page-flip)
10505          * so we need only reprogram the base address.
10506          */
10507         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10508                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10509         intel_ring_emit(ring, fb->pitches[0]);
10510         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10511                         obj->tiling_mode);
10512
10513         /* XXX Enabling the panel-fitter across page-flip is so far
10514          * untested on non-native modes, so ignore it for now.
10515          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10516          */
10517         pf = 0;
10518         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10519         intel_ring_emit(ring, pf | pipesrc);
10520
10521         intel_mark_page_flip_active(intel_crtc);
10522         __intel_ring_advance(ring);
10523         return 0;
10524 }
10525
10526 static int intel_gen6_queue_flip(struct drm_device *dev,
10527                                  struct drm_crtc *crtc,
10528                                  struct drm_framebuffer *fb,
10529                                  struct drm_i915_gem_object *obj,
10530                                  struct intel_engine_cs *ring,
10531                                  uint32_t flags)
10532 {
10533         struct drm_i915_private *dev_priv = dev->dev_private;
10534         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10535         uint32_t pf, pipesrc;
10536         int ret;
10537
10538         ret = intel_ring_begin(ring, 4);
10539         if (ret)
10540                 return ret;
10541
10542         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10543                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10544         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10545         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10546
10547         /* Contrary to the suggestions in the documentation,
10548          * "Enable Panel Fitter" does not seem to be required when page
10549          * flipping with a non-native mode, and worse causes a normal
10550          * modeset to fail.
10551          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10552          */
10553         pf = 0;
10554         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10555         intel_ring_emit(ring, pf | pipesrc);
10556
10557         intel_mark_page_flip_active(intel_crtc);
10558         __intel_ring_advance(ring);
10559         return 0;
10560 }
10561
10562 static int intel_gen7_queue_flip(struct drm_device *dev,
10563                                  struct drm_crtc *crtc,
10564                                  struct drm_framebuffer *fb,
10565                                  struct drm_i915_gem_object *obj,
10566                                  struct intel_engine_cs *ring,
10567                                  uint32_t flags)
10568 {
10569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10570         uint32_t plane_bit = 0;
10571         int len, ret;
10572
10573         switch (intel_crtc->plane) {
10574         case PLANE_A:
10575                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10576                 break;
10577         case PLANE_B:
10578                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10579                 break;
10580         case PLANE_C:
10581                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10582                 break;
10583         default:
10584                 WARN_ONCE(1, "unknown plane in flip command\n");
10585                 return -ENODEV;
10586         }
10587
10588         len = 4;
10589         if (ring->id == RCS) {
10590                 len += 6;
10591                 /*
10592                  * On Gen 8, SRM is now taking an extra dword to accommodate
10593                  * 48bits addresses, and we need a NOOP for the batch size to
10594                  * stay even.
10595                  */
10596                 if (IS_GEN8(dev))
10597                         len += 2;
10598         }
10599
10600         /*
10601          * BSpec MI_DISPLAY_FLIP for IVB:
10602          * "The full packet must be contained within the same cache line."
10603          *
10604          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10605          * cacheline, if we ever start emitting more commands before
10606          * the MI_DISPLAY_FLIP we may need to first emit everything else,
10607          * then do the cacheline alignment, and finally emit the
10608          * MI_DISPLAY_FLIP.
10609          */
10610         ret = intel_ring_cacheline_align(ring);
10611         if (ret)
10612                 return ret;
10613
10614         ret = intel_ring_begin(ring, len);
10615         if (ret)
10616                 return ret;
10617
10618         /* Unmask the flip-done completion message. Note that the bspec says that
10619          * we should do this for both the BCS and RCS, and that we must not unmask
10620          * more than one flip event at any time (or ensure that one flip message
10621          * can be sent by waiting for flip-done prior to queueing new flips).
10622          * Experimentation says that BCS works despite DERRMR masking all
10623          * flip-done completion events and that unmasking all planes at once
10624          * for the RCS also doesn't appear to drop events. Setting the DERRMR
10625          * to zero does lead to lockups within MI_DISPLAY_FLIP.
10626          */
10627         if (ring->id == RCS) {
10628                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10629                 intel_ring_emit(ring, DERRMR);
10630                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10631                                         DERRMR_PIPEB_PRI_FLIP_DONE |
10632                                         DERRMR_PIPEC_PRI_FLIP_DONE));
10633                 if (IS_GEN8(dev))
10634                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10635                                               MI_SRM_LRM_GLOBAL_GTT);
10636                 else
10637                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10638                                               MI_SRM_LRM_GLOBAL_GTT);
10639                 intel_ring_emit(ring, DERRMR);
10640                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10641                 if (IS_GEN8(dev)) {
10642                         intel_ring_emit(ring, 0);
10643                         intel_ring_emit(ring, MI_NOOP);
10644                 }
10645         }
10646
10647         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10648         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10649         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10650         intel_ring_emit(ring, (MI_NOOP));
10651
10652         intel_mark_page_flip_active(intel_crtc);
10653         __intel_ring_advance(ring);
10654         return 0;
10655 }
10656
10657 static bool use_mmio_flip(struct intel_engine_cs *ring,
10658                           struct drm_i915_gem_object *obj)
10659 {
10660         /*
10661          * This is not being used for older platforms, because
10662          * non-availability of flip done interrupt forces us to use
10663          * CS flips. Older platforms derive flip done using some clever
10664          * tricks involving the flip_pending status bits and vblank irqs.
10665          * So using MMIO flips there would disrupt this mechanism.
10666          */
10667
10668         if (ring == NULL)
10669                 return true;
10670
10671         if (INTEL_INFO(ring->dev)->gen < 5)
10672                 return false;
10673
10674         if (i915.use_mmio_flip < 0)
10675                 return false;
10676         else if (i915.use_mmio_flip > 0)
10677                 return true;
10678         else if (i915.enable_execlists)
10679                 return true;
10680         else
10681                 return ring != i915_gem_request_get_ring(obj->last_read_req);
10682 }
10683
10684 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10685 {
10686         struct drm_device *dev = intel_crtc->base.dev;
10687         struct drm_i915_private *dev_priv = dev->dev_private;
10688         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10689         const enum pipe pipe = intel_crtc->pipe;
10690         u32 ctl, stride;
10691
10692         ctl = I915_READ(PLANE_CTL(pipe, 0));
10693         ctl &= ~PLANE_CTL_TILED_MASK;
10694         switch (fb->modifier[0]) {
10695         case DRM_FORMAT_MOD_NONE:
10696                 break;
10697         case I915_FORMAT_MOD_X_TILED:
10698                 ctl |= PLANE_CTL_TILED_X;
10699                 break;
10700         case I915_FORMAT_MOD_Y_TILED:
10701                 ctl |= PLANE_CTL_TILED_Y;
10702                 break;
10703         case I915_FORMAT_MOD_Yf_TILED:
10704                 ctl |= PLANE_CTL_TILED_YF;
10705                 break;
10706         default:
10707                 MISSING_CASE(fb->modifier[0]);
10708         }
10709
10710         /*
10711          * The stride is either expressed as a multiple of 64 bytes chunks for
10712          * linear buffers or in number of tiles for tiled buffers.
10713          */
10714         stride = fb->pitches[0] /
10715                  intel_fb_stride_alignment(dev, fb->modifier[0],
10716                                            fb->pixel_format);
10717
10718         /*
10719          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10720          * PLANE_SURF updates, the update is then guaranteed to be atomic.
10721          */
10722         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10723         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10724
10725         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10726         POSTING_READ(PLANE_SURF(pipe, 0));
10727 }
10728
10729 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10730 {
10731         struct drm_device *dev = intel_crtc->base.dev;
10732         struct drm_i915_private *dev_priv = dev->dev_private;
10733         struct intel_framebuffer *intel_fb =
10734                 to_intel_framebuffer(intel_crtc->base.primary->fb);
10735         struct drm_i915_gem_object *obj = intel_fb->obj;
10736         u32 dspcntr;
10737         u32 reg;
10738
10739         reg = DSPCNTR(intel_crtc->plane);
10740         dspcntr = I915_READ(reg);
10741
10742         if (obj->tiling_mode != I915_TILING_NONE)
10743                 dspcntr |= DISPPLANE_TILED;
10744         else
10745                 dspcntr &= ~DISPPLANE_TILED;
10746
10747         I915_WRITE(reg, dspcntr);
10748
10749         I915_WRITE(DSPSURF(intel_crtc->plane),
10750                    intel_crtc->unpin_work->gtt_offset);
10751         POSTING_READ(DSPSURF(intel_crtc->plane));
10752
10753 }
10754
10755 /*
10756  * XXX: This is the temporary way to update the plane registers until we get
10757  * around to using the usual plane update functions for MMIO flips
10758  */
10759 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10760 {
10761         struct drm_device *dev = intel_crtc->base.dev;
10762         bool atomic_update;
10763         u32 start_vbl_count;
10764
10765         intel_mark_page_flip_active(intel_crtc);
10766
10767         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10768
10769         if (INTEL_INFO(dev)->gen >= 9)
10770                 skl_do_mmio_flip(intel_crtc);
10771         else
10772                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10773                 ilk_do_mmio_flip(intel_crtc);
10774
10775         if (atomic_update)
10776                 intel_pipe_update_end(intel_crtc, start_vbl_count);
10777 }
10778
10779 static void intel_mmio_flip_work_func(struct work_struct *work)
10780 {
10781         struct intel_mmio_flip *mmio_flip =
10782                 container_of(work, struct intel_mmio_flip, work);
10783
10784         if (mmio_flip->rq)
10785                 WARN_ON(__i915_wait_request(mmio_flip->rq,
10786                                             mmio_flip->crtc->reset_counter,
10787                                             false, NULL, NULL));
10788
10789         intel_do_mmio_flip(mmio_flip->crtc);
10790
10791         i915_gem_request_unreference__unlocked(mmio_flip->rq);
10792         kfree(mmio_flip);
10793 }
10794
10795 static int intel_queue_mmio_flip(struct drm_device *dev,
10796                                  struct drm_crtc *crtc,
10797                                  struct drm_framebuffer *fb,
10798                                  struct drm_i915_gem_object *obj,
10799                                  struct intel_engine_cs *ring,
10800                                  uint32_t flags)
10801 {
10802         struct intel_mmio_flip *mmio_flip;
10803
10804         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
10805         if (mmio_flip == NULL)
10806                 return -ENOMEM;
10807
10808         mmio_flip->rq = i915_gem_request_reference(obj->last_write_req);
10809         mmio_flip->crtc = to_intel_crtc(crtc);
10810
10811         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
10812         schedule_work(&mmio_flip->work);
10813
10814         return 0;
10815 }
10816
10817 static int intel_default_queue_flip(struct drm_device *dev,
10818                                     struct drm_crtc *crtc,
10819                                     struct drm_framebuffer *fb,
10820                                     struct drm_i915_gem_object *obj,
10821                                     struct intel_engine_cs *ring,
10822                                     uint32_t flags)
10823 {
10824         return -ENODEV;
10825 }
10826
10827 static bool __intel_pageflip_stall_check(struct drm_device *dev,
10828                                          struct drm_crtc *crtc)
10829 {
10830         struct drm_i915_private *dev_priv = dev->dev_private;
10831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10832         struct intel_unpin_work *work = intel_crtc->unpin_work;
10833         u32 addr;
10834
10835         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10836                 return true;
10837
10838         if (!work->enable_stall_check)
10839                 return false;
10840
10841         if (work->flip_ready_vblank == 0) {
10842                 if (work->flip_queued_req &&
10843                     !i915_gem_request_completed(work->flip_queued_req, true))
10844                         return false;
10845
10846                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10847         }
10848
10849         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10850                 return false;
10851
10852         /* Potential stall - if we see that the flip has happened,
10853          * assume a missed interrupt. */
10854         if (INTEL_INFO(dev)->gen >= 4)
10855                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10856         else
10857                 addr = I915_READ(DSPADDR(intel_crtc->plane));
10858
10859         /* There is a potential issue here with a false positive after a flip
10860          * to the same address. We could address this by checking for a
10861          * non-incrementing frame counter.
10862          */
10863         return addr == work->gtt_offset;
10864 }
10865
10866 void intel_check_page_flip(struct drm_device *dev, int pipe)
10867 {
10868         struct drm_i915_private *dev_priv = dev->dev_private;
10869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10871         struct intel_unpin_work *work;
10872
10873         WARN_ON(!in_interrupt());
10874
10875         if (crtc == NULL)
10876                 return;
10877
10878         spin_lock(&dev->event_lock);
10879         work = intel_crtc->unpin_work;
10880         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
10881                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10882                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
10883                 page_flip_completed(intel_crtc);
10884                 work = NULL;
10885         }
10886         if (work != NULL &&
10887             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10888                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
10889         spin_unlock(&dev->event_lock);
10890 }
10891
10892 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10893                                 struct drm_framebuffer *fb,
10894                                 struct drm_pending_vblank_event *event,
10895                                 uint32_t page_flip_flags)
10896 {
10897         struct drm_device *dev = crtc->dev;
10898         struct drm_i915_private *dev_priv = dev->dev_private;
10899         struct drm_framebuffer *old_fb = crtc->primary->fb;
10900         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10901         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10902         struct drm_plane *primary = crtc->primary;
10903         enum pipe pipe = intel_crtc->pipe;
10904         struct intel_unpin_work *work;
10905         struct intel_engine_cs *ring;
10906         bool mmio_flip;
10907         int ret;
10908
10909         /*
10910          * drm_mode_page_flip_ioctl() should already catch this, but double
10911          * check to be safe.  In the future we may enable pageflipping from
10912          * a disabled primary plane.
10913          */
10914         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10915                 return -EBUSY;
10916
10917         /* Can't change pixel format via MI display flips. */
10918         if (fb->pixel_format != crtc->primary->fb->pixel_format)
10919                 return -EINVAL;
10920
10921         /*
10922          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10923          * Note that pitch changes could also affect these register.
10924          */
10925         if (INTEL_INFO(dev)->gen > 3 &&
10926             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10927              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10928                 return -EINVAL;
10929
10930         if (i915_terminally_wedged(&dev_priv->gpu_error))
10931                 goto out_hang;
10932
10933         work = kzalloc(sizeof(*work), GFP_KERNEL);
10934         if (work == NULL)
10935                 return -ENOMEM;
10936
10937         work->event = event;
10938         work->crtc = crtc;
10939         work->old_fb = old_fb;
10940         INIT_WORK(&work->work, intel_unpin_work_fn);
10941
10942         ret = drm_crtc_vblank_get(crtc);
10943         if (ret)
10944                 goto free_work;
10945
10946         /* We borrow the event spin lock for protecting unpin_work */
10947         spin_lock_irq(&dev->event_lock);
10948         if (intel_crtc->unpin_work) {
10949                 /* Before declaring the flip queue wedged, check if
10950                  * the hardware completed the operation behind our backs.
10951                  */
10952                 if (__intel_pageflip_stall_check(dev, crtc)) {
10953                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10954                         page_flip_completed(intel_crtc);
10955                 } else {
10956                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10957                         spin_unlock_irq(&dev->event_lock);
10958
10959                         drm_crtc_vblank_put(crtc);
10960                         kfree(work);
10961                         return -EBUSY;
10962                 }
10963         }
10964         intel_crtc->unpin_work = work;
10965         spin_unlock_irq(&dev->event_lock);
10966
10967         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10968                 flush_workqueue(dev_priv->wq);
10969
10970         /* Reference the objects for the scheduled work. */
10971         drm_framebuffer_reference(work->old_fb);
10972         drm_gem_object_reference(&obj->base);
10973
10974         crtc->primary->fb = fb;
10975         update_state_fb(crtc->primary);
10976
10977         work->pending_flip_obj = obj;
10978
10979         ret = i915_mutex_lock_interruptible(dev);
10980         if (ret)
10981                 goto cleanup;
10982
10983         atomic_inc(&intel_crtc->unpin_work_count);
10984         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10985
10986         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10987                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10988
10989         if (IS_VALLEYVIEW(dev)) {
10990                 ring = &dev_priv->ring[BCS];
10991                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10992                         /* vlv: DISPLAY_FLIP fails to change tiling */
10993                         ring = NULL;
10994         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10995                 ring = &dev_priv->ring[BCS];
10996         } else if (INTEL_INFO(dev)->gen >= 7) {
10997                 ring = i915_gem_request_get_ring(obj->last_read_req);
10998                 if (ring == NULL || ring->id != RCS)
10999                         ring = &dev_priv->ring[BCS];
11000         } else {
11001                 ring = &dev_priv->ring[RCS];
11002         }
11003
11004         mmio_flip = use_mmio_flip(ring, obj);
11005
11006         /* When using CS flips, we want to emit semaphores between rings.
11007          * However, when using mmio flips we will create a task to do the
11008          * synchronisation, so all we want here is to pin the framebuffer
11009          * into the display plane and skip any waits.
11010          */
11011         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11012                                          crtc->primary->state,
11013                                          mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
11014         if (ret)
11015                 goto cleanup_pending;
11016
11017         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11018                                                   + intel_crtc->dspaddr_offset;
11019
11020         if (mmio_flip) {
11021                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11022                                             page_flip_flags);
11023                 if (ret)
11024                         goto cleanup_unpin;
11025
11026                 i915_gem_request_assign(&work->flip_queued_req,
11027                                         obj->last_write_req);
11028         } else {
11029                 if (obj->last_write_req) {
11030                         ret = i915_gem_check_olr(obj->last_write_req);
11031                         if (ret)
11032                                 goto cleanup_unpin;
11033                 }
11034
11035                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11036                                                    page_flip_flags);
11037                 if (ret)
11038                         goto cleanup_unpin;
11039
11040                 i915_gem_request_assign(&work->flip_queued_req,
11041                                         intel_ring_get_request(ring));
11042         }
11043
11044         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11045         work->enable_stall_check = true;
11046
11047         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11048                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11049
11050         intel_fbc_disable(dev);
11051         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11052         mutex_unlock(&dev->struct_mutex);
11053
11054         trace_i915_flip_request(intel_crtc->plane, obj);
11055
11056         return 0;
11057
11058 cleanup_unpin:
11059         intel_unpin_fb_obj(fb, crtc->primary->state);
11060 cleanup_pending:
11061         atomic_dec(&intel_crtc->unpin_work_count);
11062         mutex_unlock(&dev->struct_mutex);
11063 cleanup:
11064         crtc->primary->fb = old_fb;
11065         update_state_fb(crtc->primary);
11066
11067         drm_gem_object_unreference_unlocked(&obj->base);
11068         drm_framebuffer_unreference(work->old_fb);
11069
11070         spin_lock_irq(&dev->event_lock);
11071         intel_crtc->unpin_work = NULL;
11072         spin_unlock_irq(&dev->event_lock);
11073
11074         drm_crtc_vblank_put(crtc);
11075 free_work:
11076         kfree(work);
11077
11078         if (ret == -EIO) {
11079 out_hang:
11080                 ret = intel_plane_restore(primary);
11081                 if (ret == 0 && event) {
11082                         spin_lock_irq(&dev->event_lock);
11083                         drm_send_vblank_event(dev, pipe, event);
11084                         spin_unlock_irq(&dev->event_lock);
11085                 }
11086         }
11087         return ret;
11088 }
11089
11090 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11091         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11092         .load_lut = intel_crtc_load_lut,
11093         .atomic_begin = intel_begin_crtc_commit,
11094         .atomic_flush = intel_finish_crtc_commit,
11095 };
11096
11097 /**
11098  * intel_modeset_update_staged_output_state
11099  *
11100  * Updates the staged output configuration state, e.g. after we've read out the
11101  * current hw state.
11102  */
11103 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11104 {
11105         struct intel_crtc *crtc;
11106         struct intel_encoder *encoder;
11107         struct intel_connector *connector;
11108
11109         for_each_intel_connector(dev, connector) {
11110                 connector->new_encoder =
11111                         to_intel_encoder(connector->base.encoder);
11112         }
11113
11114         for_each_intel_encoder(dev, encoder) {
11115                 encoder->new_crtc =
11116                         to_intel_crtc(encoder->base.crtc);
11117         }
11118
11119         for_each_intel_crtc(dev, crtc) {
11120                 crtc->new_enabled = crtc->base.state->enable;
11121         }
11122 }
11123
11124 /* Transitional helper to copy current connector/encoder state to
11125  * connector->state. This is needed so that code that is partially
11126  * converted to atomic does the right thing.
11127  */
11128 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11129 {
11130         struct intel_connector *connector;
11131
11132         for_each_intel_connector(dev, connector) {
11133                 if (connector->base.encoder) {
11134                         connector->base.state->best_encoder =
11135                                 connector->base.encoder;
11136                         connector->base.state->crtc =
11137                                 connector->base.encoder->crtc;
11138                 } else {
11139                         connector->base.state->best_encoder = NULL;
11140                         connector->base.state->crtc = NULL;
11141                 }
11142         }
11143 }
11144
11145 /* Fixup legacy state after an atomic state swap.
11146  */
11147 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11148 {
11149         struct intel_crtc *crtc;
11150         struct intel_encoder *encoder;
11151         struct intel_connector *connector;
11152
11153         for_each_intel_connector(state->dev, connector) {
11154                 connector->base.encoder = connector->base.state->best_encoder;
11155                 if (connector->base.encoder)
11156                         connector->base.encoder->crtc =
11157                                 connector->base.state->crtc;
11158         }
11159
11160         /* Update crtc of disabled encoders */
11161         for_each_intel_encoder(state->dev, encoder) {
11162                 int num_connectors = 0;
11163
11164                 for_each_intel_connector(state->dev, connector)
11165                         if (connector->base.encoder == &encoder->base)
11166                                 num_connectors++;
11167
11168                 if (num_connectors == 0)
11169                         encoder->base.crtc = NULL;
11170         }
11171
11172         for_each_intel_crtc(state->dev, crtc) {
11173                 crtc->base.enabled = crtc->base.state->enable;
11174                 crtc->config = to_intel_crtc_state(crtc->base.state);
11175         }
11176
11177         /* Copy the new configuration to the staged state, to keep the few
11178          * pieces of code that haven't been converted yet happy */
11179         intel_modeset_update_staged_output_state(state->dev);
11180 }
11181
11182 static void
11183 connected_sink_compute_bpp(struct intel_connector *connector,
11184                            struct intel_crtc_state *pipe_config)
11185 {
11186         int bpp = pipe_config->pipe_bpp;
11187
11188         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11189                 connector->base.base.id,
11190                 connector->base.name);
11191
11192         /* Don't use an invalid EDID bpc value */
11193         if (connector->base.display_info.bpc &&
11194             connector->base.display_info.bpc * 3 < bpp) {
11195                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11196                               bpp, connector->base.display_info.bpc*3);
11197                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11198         }
11199
11200         /* Clamp bpp to 8 on screens without EDID 1.4 */
11201         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11202                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11203                               bpp);
11204                 pipe_config->pipe_bpp = 24;
11205         }
11206 }
11207
11208 static int
11209 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11210                           struct intel_crtc_state *pipe_config)
11211 {
11212         struct drm_device *dev = crtc->base.dev;
11213         struct drm_atomic_state *state;
11214         struct drm_connector *connector;
11215         struct drm_connector_state *connector_state;
11216         int bpp, i;
11217
11218         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11219                 bpp = 10*3;
11220         else if (INTEL_INFO(dev)->gen >= 5)
11221                 bpp = 12*3;
11222         else
11223                 bpp = 8*3;
11224
11225
11226         pipe_config->pipe_bpp = bpp;
11227
11228         state = pipe_config->base.state;
11229
11230         /* Clamp display bpp to EDID value */
11231         for_each_connector_in_state(state, connector, connector_state, i) {
11232                 if (connector_state->crtc != &crtc->base)
11233                         continue;
11234
11235                 connected_sink_compute_bpp(to_intel_connector(connector),
11236                                            pipe_config);
11237         }
11238
11239         return bpp;
11240 }
11241
11242 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11243 {
11244         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11245                         "type: 0x%x flags: 0x%x\n",
11246                 mode->crtc_clock,
11247                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11248                 mode->crtc_hsync_end, mode->crtc_htotal,
11249                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11250                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11251 }
11252
11253 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11254                                    struct intel_crtc_state *pipe_config,
11255                                    const char *context)
11256 {
11257         struct drm_device *dev = crtc->base.dev;
11258         struct drm_plane *plane;
11259         struct intel_plane *intel_plane;
11260         struct intel_plane_state *state;
11261         struct drm_framebuffer *fb;
11262
11263         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11264                       context, pipe_config, pipe_name(crtc->pipe));
11265
11266         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11267         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11268                       pipe_config->pipe_bpp, pipe_config->dither);
11269         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11270                       pipe_config->has_pch_encoder,
11271                       pipe_config->fdi_lanes,
11272                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11273                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11274                       pipe_config->fdi_m_n.tu);
11275         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11276                       pipe_config->has_dp_encoder,
11277                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11278                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11279                       pipe_config->dp_m_n.tu);
11280
11281         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11282                       pipe_config->has_dp_encoder,
11283                       pipe_config->dp_m2_n2.gmch_m,
11284                       pipe_config->dp_m2_n2.gmch_n,
11285                       pipe_config->dp_m2_n2.link_m,
11286                       pipe_config->dp_m2_n2.link_n,
11287                       pipe_config->dp_m2_n2.tu);
11288
11289         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11290                       pipe_config->has_audio,
11291                       pipe_config->has_infoframe);
11292
11293         DRM_DEBUG_KMS("requested mode:\n");
11294         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11295         DRM_DEBUG_KMS("adjusted mode:\n");
11296         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11297         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11298         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11299         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11300                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11301         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11302                       crtc->num_scalers,
11303                       pipe_config->scaler_state.scaler_users,
11304                       pipe_config->scaler_state.scaler_id);
11305         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11306                       pipe_config->gmch_pfit.control,
11307                       pipe_config->gmch_pfit.pgm_ratios,
11308                       pipe_config->gmch_pfit.lvds_border_bits);
11309         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11310                       pipe_config->pch_pfit.pos,
11311                       pipe_config->pch_pfit.size,
11312                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11313         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11314         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11315
11316         if (IS_BROXTON(dev)) {
11317                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11318                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11319                               "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11320                               pipe_config->ddi_pll_sel,
11321                               pipe_config->dpll_hw_state.ebb0,
11322                               pipe_config->dpll_hw_state.pll0,
11323                               pipe_config->dpll_hw_state.pll1,
11324                               pipe_config->dpll_hw_state.pll2,
11325                               pipe_config->dpll_hw_state.pll3,
11326                               pipe_config->dpll_hw_state.pll6,
11327                               pipe_config->dpll_hw_state.pll8,
11328                               pipe_config->dpll_hw_state.pcsdw12);
11329         } else if (IS_SKYLAKE(dev)) {
11330                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11331                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11332                               pipe_config->ddi_pll_sel,
11333                               pipe_config->dpll_hw_state.ctrl1,
11334                               pipe_config->dpll_hw_state.cfgcr1,
11335                               pipe_config->dpll_hw_state.cfgcr2);
11336         } else if (HAS_DDI(dev)) {
11337                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11338                               pipe_config->ddi_pll_sel,
11339                               pipe_config->dpll_hw_state.wrpll);
11340         } else {
11341                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11342                               "fp0: 0x%x, fp1: 0x%x\n",
11343                               pipe_config->dpll_hw_state.dpll,
11344                               pipe_config->dpll_hw_state.dpll_md,
11345                               pipe_config->dpll_hw_state.fp0,
11346                               pipe_config->dpll_hw_state.fp1);
11347         }
11348
11349         DRM_DEBUG_KMS("planes on this crtc\n");
11350         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11351                 intel_plane = to_intel_plane(plane);
11352                 if (intel_plane->pipe != crtc->pipe)
11353                         continue;
11354
11355                 state = to_intel_plane_state(plane->state);
11356                 fb = state->base.fb;
11357                 if (!fb) {
11358                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11359                                 "disabled, scaler_id = %d\n",
11360                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11361                                 plane->base.id, intel_plane->pipe,
11362                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11363                                 drm_plane_index(plane), state->scaler_id);
11364                         continue;
11365                 }
11366
11367                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11368                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11369                         plane->base.id, intel_plane->pipe,
11370                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11371                         drm_plane_index(plane));
11372                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11373                         fb->base.id, fb->width, fb->height, fb->pixel_format);
11374                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11375                         state->scaler_id,
11376                         state->src.x1 >> 16, state->src.y1 >> 16,
11377                         drm_rect_width(&state->src) >> 16,
11378                         drm_rect_height(&state->src) >> 16,
11379                         state->dst.x1, state->dst.y1,
11380                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11381         }
11382 }
11383
11384 static bool encoders_cloneable(const struct intel_encoder *a,
11385                                const struct intel_encoder *b)
11386 {
11387         /* masks could be asymmetric, so check both ways */
11388         return a == b || (a->cloneable & (1 << b->type) &&
11389                           b->cloneable & (1 << a->type));
11390 }
11391
11392 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11393                                          struct intel_crtc *crtc,
11394                                          struct intel_encoder *encoder)
11395 {
11396         struct intel_encoder *source_encoder;
11397         struct drm_connector *connector;
11398         struct drm_connector_state *connector_state;
11399         int i;
11400
11401         for_each_connector_in_state(state, connector, connector_state, i) {
11402                 if (connector_state->crtc != &crtc->base)
11403                         continue;
11404
11405                 source_encoder =
11406                         to_intel_encoder(connector_state->best_encoder);
11407                 if (!encoders_cloneable(encoder, source_encoder))
11408                         return false;
11409         }
11410
11411         return true;
11412 }
11413
11414 static bool check_encoder_cloning(struct drm_atomic_state *state,
11415                                   struct intel_crtc *crtc)
11416 {
11417         struct intel_encoder *encoder;
11418         struct drm_connector *connector;
11419         struct drm_connector_state *connector_state;
11420         int i;
11421
11422         for_each_connector_in_state(state, connector, connector_state, i) {
11423                 if (connector_state->crtc != &crtc->base)
11424                         continue;
11425
11426                 encoder = to_intel_encoder(connector_state->best_encoder);
11427                 if (!check_single_encoder_cloning(state, crtc, encoder))
11428                         return false;
11429         }
11430
11431         return true;
11432 }
11433
11434 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11435 {
11436         struct drm_device *dev = state->dev;
11437         struct intel_encoder *encoder;
11438         struct drm_connector *connector;
11439         struct drm_connector_state *connector_state;
11440         unsigned int used_ports = 0;
11441         int i;
11442
11443         /*
11444          * Walk the connector list instead of the encoder
11445          * list to detect the problem on ddi platforms
11446          * where there's just one encoder per digital port.
11447          */
11448         for_each_connector_in_state(state, connector, connector_state, i) {
11449                 if (!connector_state->best_encoder)
11450                         continue;
11451
11452                 encoder = to_intel_encoder(connector_state->best_encoder);
11453
11454                 WARN_ON(!connector_state->crtc);
11455
11456                 switch (encoder->type) {
11457                         unsigned int port_mask;
11458                 case INTEL_OUTPUT_UNKNOWN:
11459                         if (WARN_ON(!HAS_DDI(dev)))
11460                                 break;
11461                 case INTEL_OUTPUT_DISPLAYPORT:
11462                 case INTEL_OUTPUT_HDMI:
11463                 case INTEL_OUTPUT_EDP:
11464                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11465
11466                         /* the same port mustn't appear more than once */
11467                         if (used_ports & port_mask)
11468                                 return false;
11469
11470                         used_ports |= port_mask;
11471                 default:
11472                         break;
11473                 }
11474         }
11475
11476         return true;
11477 }
11478
11479 static void
11480 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11481 {
11482         struct drm_crtc_state tmp_state;
11483         struct intel_crtc_scaler_state scaler_state;
11484         struct intel_dpll_hw_state dpll_hw_state;
11485         enum intel_dpll_id shared_dpll;
11486         uint32_t ddi_pll_sel;
11487
11488         /* FIXME: before the switch to atomic started, a new pipe_config was
11489          * kzalloc'd. Code that depends on any field being zero should be
11490          * fixed, so that the crtc_state can be safely duplicated. For now,
11491          * only fields that are know to not cause problems are preserved. */
11492
11493         tmp_state = crtc_state->base;
11494         scaler_state = crtc_state->scaler_state;
11495         shared_dpll = crtc_state->shared_dpll;
11496         dpll_hw_state = crtc_state->dpll_hw_state;
11497         ddi_pll_sel = crtc_state->ddi_pll_sel;
11498
11499         memset(crtc_state, 0, sizeof *crtc_state);
11500
11501         crtc_state->base = tmp_state;
11502         crtc_state->scaler_state = scaler_state;
11503         crtc_state->shared_dpll = shared_dpll;
11504         crtc_state->dpll_hw_state = dpll_hw_state;
11505         crtc_state->ddi_pll_sel = ddi_pll_sel;
11506 }
11507
11508 static int
11509 intel_modeset_pipe_config(struct drm_crtc *crtc,
11510                           struct drm_atomic_state *state,
11511                           struct intel_crtc_state *pipe_config)
11512 {
11513         struct intel_encoder *encoder;
11514         struct drm_connector *connector;
11515         struct drm_connector_state *connector_state;
11516         int base_bpp, ret = -EINVAL;
11517         int i;
11518         bool retry = true;
11519
11520         if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11521                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11522                 return -EINVAL;
11523         }
11524
11525         if (!check_digital_port_conflicts(state)) {
11526                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11527                 return -EINVAL;
11528         }
11529
11530         clear_intel_crtc_state(pipe_config);
11531
11532         pipe_config->cpu_transcoder =
11533                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11534
11535         /*
11536          * Sanitize sync polarity flags based on requested ones. If neither
11537          * positive or negative polarity is requested, treat this as meaning
11538          * negative polarity.
11539          */
11540         if (!(pipe_config->base.adjusted_mode.flags &
11541               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11542                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11543
11544         if (!(pipe_config->base.adjusted_mode.flags &
11545               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11546                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11547
11548         /* Compute a starting value for pipe_config->pipe_bpp taking the source
11549          * plane pixel format and any sink constraints into account. Returns the
11550          * source plane bpp so that dithering can be selected on mismatches
11551          * after encoders and crtc also have had their say. */
11552         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11553                                              pipe_config);
11554         if (base_bpp < 0)
11555                 goto fail;
11556
11557         /*
11558          * Determine the real pipe dimensions. Note that stereo modes can
11559          * increase the actual pipe size due to the frame doubling and
11560          * insertion of additional space for blanks between the frame. This
11561          * is stored in the crtc timings. We use the requested mode to do this
11562          * computation to clearly distinguish it from the adjusted mode, which
11563          * can be changed by the connectors in the below retry loop.
11564          */
11565         drm_crtc_get_hv_timing(&pipe_config->base.mode,
11566                                &pipe_config->pipe_src_w,
11567                                &pipe_config->pipe_src_h);
11568
11569 encoder_retry:
11570         /* Ensure the port clock defaults are reset when retrying. */
11571         pipe_config->port_clock = 0;
11572         pipe_config->pixel_multiplier = 1;
11573
11574         /* Fill in default crtc timings, allow encoders to overwrite them. */
11575         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11576                               CRTC_STEREO_DOUBLE);
11577
11578         /* Pass our mode to the connectors and the CRTC to give them a chance to
11579          * adjust it according to limitations or connector properties, and also
11580          * a chance to reject the mode entirely.
11581          */
11582         for_each_connector_in_state(state, connector, connector_state, i) {
11583                 if (connector_state->crtc != crtc)
11584                         continue;
11585
11586                 encoder = to_intel_encoder(connector_state->best_encoder);
11587
11588                 if (!(encoder->compute_config(encoder, pipe_config))) {
11589                         DRM_DEBUG_KMS("Encoder config failure\n");
11590                         goto fail;
11591                 }
11592         }
11593
11594         /* Set default port clock if not overwritten by the encoder. Needs to be
11595          * done afterwards in case the encoder adjusts the mode. */
11596         if (!pipe_config->port_clock)
11597                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11598                         * pipe_config->pixel_multiplier;
11599
11600         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11601         if (ret < 0) {
11602                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11603                 goto fail;
11604         }
11605
11606         if (ret == RETRY) {
11607                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11608                         ret = -EINVAL;
11609                         goto fail;
11610                 }
11611
11612                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11613                 retry = false;
11614                 goto encoder_retry;
11615         }
11616
11617         pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11618         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11619                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11620
11621         return 0;
11622 fail:
11623         return ret;
11624 }
11625
11626 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11627 {
11628         struct drm_encoder *encoder;
11629         struct drm_device *dev = crtc->dev;
11630
11631         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11632                 if (encoder->crtc == crtc)
11633                         return true;
11634
11635         return false;
11636 }
11637
11638 static bool
11639 needs_modeset(struct drm_crtc_state *state)
11640 {
11641         return state->mode_changed || state->active_changed;
11642 }
11643
11644 static void
11645 intel_modeset_update_state(struct drm_atomic_state *state)
11646 {
11647         struct drm_device *dev = state->dev;
11648         struct drm_i915_private *dev_priv = dev->dev_private;
11649         struct intel_encoder *intel_encoder;
11650         struct drm_crtc *crtc;
11651         struct drm_crtc_state *crtc_state;
11652         struct drm_connector *connector;
11653         int i;
11654
11655         intel_shared_dpll_commit(dev_priv);
11656
11657         for_each_intel_encoder(dev, intel_encoder) {
11658                 if (!intel_encoder->base.crtc)
11659                         continue;
11660
11661                 for_each_crtc_in_state(state, crtc, crtc_state, i)
11662                         if (crtc == intel_encoder->base.crtc)
11663                                 break;
11664
11665                 if (crtc != intel_encoder->base.crtc)
11666                         continue;
11667
11668                 if (crtc_state->enable && needs_modeset(crtc_state))
11669                         intel_encoder->connectors_active = false;
11670         }
11671
11672         drm_atomic_helper_swap_state(state->dev, state);
11673         intel_modeset_fixup_state(state);
11674
11675         /* Double check state. */
11676         for_each_crtc(dev, crtc) {
11677                 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11678         }
11679
11680         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11681                 if (!connector->encoder || !connector->encoder->crtc)
11682                         continue;
11683
11684                 for_each_crtc_in_state(state, crtc, crtc_state, i)
11685                         if (crtc == connector->encoder->crtc)
11686                                 break;
11687
11688                 if (crtc != connector->encoder->crtc)
11689                         continue;
11690
11691                 if (crtc->state->enable && needs_modeset(crtc->state)) {
11692                         struct drm_property *dpms_property =
11693                                 dev->mode_config.dpms_property;
11694
11695                         connector->dpms = DRM_MODE_DPMS_ON;
11696                         drm_object_property_set_value(&connector->base,
11697                                                          dpms_property,
11698                                                          DRM_MODE_DPMS_ON);
11699
11700                         intel_encoder = to_intel_encoder(connector->encoder);
11701                         intel_encoder->connectors_active = true;
11702                 }
11703         }
11704
11705 }
11706
11707 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11708 {
11709         int diff;
11710
11711         if (clock1 == clock2)
11712                 return true;
11713
11714         if (!clock1 || !clock2)
11715                 return false;
11716
11717         diff = abs(clock1 - clock2);
11718
11719         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11720                 return true;
11721
11722         return false;
11723 }
11724
11725 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11726         list_for_each_entry((intel_crtc), \
11727                             &(dev)->mode_config.crtc_list, \
11728                             base.head) \
11729                 if (mask & (1 <<(intel_crtc)->pipe))
11730
11731 static bool
11732 intel_pipe_config_compare(struct drm_device *dev,
11733                           struct intel_crtc_state *current_config,
11734                           struct intel_crtc_state *pipe_config)
11735 {
11736 #define PIPE_CONF_CHECK_X(name) \
11737         if (current_config->name != pipe_config->name) { \
11738                 DRM_ERROR("mismatch in " #name " " \
11739                           "(expected 0x%08x, found 0x%08x)\n", \
11740                           current_config->name, \
11741                           pipe_config->name); \
11742                 return false; \
11743         }
11744
11745 #define PIPE_CONF_CHECK_I(name) \
11746         if (current_config->name != pipe_config->name) { \
11747                 DRM_ERROR("mismatch in " #name " " \
11748                           "(expected %i, found %i)\n", \
11749                           current_config->name, \
11750                           pipe_config->name); \
11751                 return false; \
11752         }
11753
11754 /* This is required for BDW+ where there is only one set of registers for
11755  * switching between high and low RR.
11756  * This macro can be used whenever a comparison has to be made between one
11757  * hw state and multiple sw state variables.
11758  */
11759 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11760         if ((current_config->name != pipe_config->name) && \
11761                 (current_config->alt_name != pipe_config->name)) { \
11762                         DRM_ERROR("mismatch in " #name " " \
11763                                   "(expected %i or %i, found %i)\n", \
11764                                   current_config->name, \
11765                                   current_config->alt_name, \
11766                                   pipe_config->name); \
11767                         return false; \
11768         }
11769
11770 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11771         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11772                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
11773                           "(expected %i, found %i)\n", \
11774                           current_config->name & (mask), \
11775                           pipe_config->name & (mask)); \
11776                 return false; \
11777         }
11778
11779 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11780         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11781                 DRM_ERROR("mismatch in " #name " " \
11782                           "(expected %i, found %i)\n", \
11783                           current_config->name, \
11784                           pipe_config->name); \
11785                 return false; \
11786         }
11787
11788 #define PIPE_CONF_QUIRK(quirk)  \
11789         ((current_config->quirks | pipe_config->quirks) & (quirk))
11790
11791         PIPE_CONF_CHECK_I(cpu_transcoder);
11792
11793         PIPE_CONF_CHECK_I(has_pch_encoder);
11794         PIPE_CONF_CHECK_I(fdi_lanes);
11795         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11796         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11797         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11798         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11799         PIPE_CONF_CHECK_I(fdi_m_n.tu);
11800
11801         PIPE_CONF_CHECK_I(has_dp_encoder);
11802
11803         if (INTEL_INFO(dev)->gen < 8) {
11804                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11805                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11806                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11807                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11808                 PIPE_CONF_CHECK_I(dp_m_n.tu);
11809
11810                 if (current_config->has_drrs) {
11811                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11812                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11813                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11814                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11815                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11816                 }
11817         } else {
11818                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11819                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11820                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11821                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11822                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11823         }
11824
11825         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11826         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11827         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11828         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11829         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11830         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11831
11832         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11833         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11834         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11835         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11836         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11837         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11838
11839         PIPE_CONF_CHECK_I(pixel_multiplier);
11840         PIPE_CONF_CHECK_I(has_hdmi_sink);
11841         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11842             IS_VALLEYVIEW(dev))
11843                 PIPE_CONF_CHECK_I(limited_color_range);
11844         PIPE_CONF_CHECK_I(has_infoframe);
11845
11846         PIPE_CONF_CHECK_I(has_audio);
11847
11848         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11849                               DRM_MODE_FLAG_INTERLACE);
11850
11851         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11852                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11853                                       DRM_MODE_FLAG_PHSYNC);
11854                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11855                                       DRM_MODE_FLAG_NHSYNC);
11856                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11857                                       DRM_MODE_FLAG_PVSYNC);
11858                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11859                                       DRM_MODE_FLAG_NVSYNC);
11860         }
11861
11862         PIPE_CONF_CHECK_I(pipe_src_w);
11863         PIPE_CONF_CHECK_I(pipe_src_h);
11864
11865         /*
11866          * FIXME: BIOS likes to set up a cloned config with lvds+external
11867          * screen. Since we don't yet re-compute the pipe config when moving
11868          * just the lvds port away to another pipe the sw tracking won't match.
11869          *
11870          * Proper atomic modesets with recomputed global state will fix this.
11871          * Until then just don't check gmch state for inherited modes.
11872          */
11873         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11874                 PIPE_CONF_CHECK_I(gmch_pfit.control);
11875                 /* pfit ratios are autocomputed by the hw on gen4+ */
11876                 if (INTEL_INFO(dev)->gen < 4)
11877                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11878                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11879         }
11880
11881         PIPE_CONF_CHECK_I(pch_pfit.enabled);
11882         if (current_config->pch_pfit.enabled) {
11883                 PIPE_CONF_CHECK_I(pch_pfit.pos);
11884                 PIPE_CONF_CHECK_I(pch_pfit.size);
11885         }
11886
11887         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11888
11889         /* BDW+ don't expose a synchronous way to read the state */
11890         if (IS_HASWELL(dev))
11891                 PIPE_CONF_CHECK_I(ips_enabled);
11892
11893         PIPE_CONF_CHECK_I(double_wide);
11894
11895         PIPE_CONF_CHECK_X(ddi_pll_sel);
11896
11897         PIPE_CONF_CHECK_I(shared_dpll);
11898         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11899         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11900         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11901         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11902         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11903         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11904         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11905         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11906
11907         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11908                 PIPE_CONF_CHECK_I(pipe_bpp);
11909
11910         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11911         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11912
11913 #undef PIPE_CONF_CHECK_X
11914 #undef PIPE_CONF_CHECK_I
11915 #undef PIPE_CONF_CHECK_I_ALT
11916 #undef PIPE_CONF_CHECK_FLAGS
11917 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11918 #undef PIPE_CONF_QUIRK
11919
11920         return true;
11921 }
11922
11923 static void check_wm_state(struct drm_device *dev)
11924 {
11925         struct drm_i915_private *dev_priv = dev->dev_private;
11926         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11927         struct intel_crtc *intel_crtc;
11928         int plane;
11929
11930         if (INTEL_INFO(dev)->gen < 9)
11931                 return;
11932
11933         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11934         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11935
11936         for_each_intel_crtc(dev, intel_crtc) {
11937                 struct skl_ddb_entry *hw_entry, *sw_entry;
11938                 const enum pipe pipe = intel_crtc->pipe;
11939
11940                 if (!intel_crtc->active)
11941                         continue;
11942
11943                 /* planes */
11944                 for_each_plane(dev_priv, pipe, plane) {
11945                         hw_entry = &hw_ddb.plane[pipe][plane];
11946                         sw_entry = &sw_ddb->plane[pipe][plane];
11947
11948                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
11949                                 continue;
11950
11951                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11952                                   "(expected (%u,%u), found (%u,%u))\n",
11953                                   pipe_name(pipe), plane + 1,
11954                                   sw_entry->start, sw_entry->end,
11955                                   hw_entry->start, hw_entry->end);
11956                 }
11957
11958                 /* cursor */
11959                 hw_entry = &hw_ddb.cursor[pipe];
11960                 sw_entry = &sw_ddb->cursor[pipe];
11961
11962                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11963                         continue;
11964
11965                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11966                           "(expected (%u,%u), found (%u,%u))\n",
11967                           pipe_name(pipe),
11968                           sw_entry->start, sw_entry->end,
11969                           hw_entry->start, hw_entry->end);
11970         }
11971 }
11972
11973 static void
11974 check_connector_state(struct drm_device *dev)
11975 {
11976         struct intel_connector *connector;
11977
11978         for_each_intel_connector(dev, connector) {
11979                 /* This also checks the encoder/connector hw state with the
11980                  * ->get_hw_state callbacks. */
11981                 intel_connector_check_state(connector);
11982
11983                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11984                      "connector's staged encoder doesn't match current encoder\n");
11985         }
11986 }
11987
11988 static void
11989 check_encoder_state(struct drm_device *dev)
11990 {
11991         struct intel_encoder *encoder;
11992         struct intel_connector *connector;
11993
11994         for_each_intel_encoder(dev, encoder) {
11995                 bool enabled = false;
11996                 bool active = false;
11997                 enum pipe pipe, tracked_pipe;
11998
11999                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12000                               encoder->base.base.id,
12001                               encoder->base.name);
12002
12003                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12004                      "encoder's stage crtc doesn't match current crtc\n");
12005                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12006                      "encoder's active_connectors set, but no crtc\n");
12007
12008                 for_each_intel_connector(dev, connector) {
12009                         if (connector->base.encoder != &encoder->base)
12010                                 continue;
12011                         enabled = true;
12012                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12013                                 active = true;
12014                 }
12015                 /*
12016                  * for MST connectors if we unplug the connector is gone
12017                  * away but the encoder is still connected to a crtc
12018                  * until a modeset happens in response to the hotplug.
12019                  */
12020                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12021                         continue;
12022
12023                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12024                      "encoder's enabled state mismatch "
12025                      "(expected %i, found %i)\n",
12026                      !!encoder->base.crtc, enabled);
12027                 I915_STATE_WARN(active && !encoder->base.crtc,
12028                      "active encoder with no crtc\n");
12029
12030                 I915_STATE_WARN(encoder->connectors_active != active,
12031                      "encoder's computed active state doesn't match tracked active state "
12032                      "(expected %i, found %i)\n", active, encoder->connectors_active);
12033
12034                 active = encoder->get_hw_state(encoder, &pipe);
12035                 I915_STATE_WARN(active != encoder->connectors_active,
12036                      "encoder's hw state doesn't match sw tracking "
12037                      "(expected %i, found %i)\n",
12038                      encoder->connectors_active, active);
12039
12040                 if (!encoder->base.crtc)
12041                         continue;
12042
12043                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12044                 I915_STATE_WARN(active && pipe != tracked_pipe,
12045                      "active encoder's pipe doesn't match"
12046                      "(expected %i, found %i)\n",
12047                      tracked_pipe, pipe);
12048
12049         }
12050 }
12051
12052 static void
12053 check_crtc_state(struct drm_device *dev)
12054 {
12055         struct drm_i915_private *dev_priv = dev->dev_private;
12056         struct intel_crtc *crtc;
12057         struct intel_encoder *encoder;
12058         struct intel_crtc_state pipe_config;
12059
12060         for_each_intel_crtc(dev, crtc) {
12061                 bool enabled = false;
12062                 bool active = false;
12063
12064                 memset(&pipe_config, 0, sizeof(pipe_config));
12065
12066                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12067                               crtc->base.base.id);
12068
12069                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12070                      "active crtc, but not enabled in sw tracking\n");
12071
12072                 for_each_intel_encoder(dev, encoder) {
12073                         if (encoder->base.crtc != &crtc->base)
12074                                 continue;
12075                         enabled = true;
12076                         if (encoder->connectors_active)
12077                                 active = true;
12078                 }
12079
12080                 I915_STATE_WARN(active != crtc->active,
12081                      "crtc's computed active state doesn't match tracked active state "
12082                      "(expected %i, found %i)\n", active, crtc->active);
12083                 I915_STATE_WARN(enabled != crtc->base.state->enable,
12084                      "crtc's computed enabled state doesn't match tracked enabled state "
12085                      "(expected %i, found %i)\n", enabled,
12086                                 crtc->base.state->enable);
12087
12088                 active = dev_priv->display.get_pipe_config(crtc,
12089                                                            &pipe_config);
12090
12091                 /* hw state is inconsistent with the pipe quirk */
12092                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12093                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12094                         active = crtc->active;
12095
12096                 for_each_intel_encoder(dev, encoder) {
12097                         enum pipe pipe;
12098                         if (encoder->base.crtc != &crtc->base)
12099                                 continue;
12100                         if (encoder->get_hw_state(encoder, &pipe))
12101                                 encoder->get_config(encoder, &pipe_config);
12102                 }
12103
12104                 I915_STATE_WARN(crtc->active != active,
12105                      "crtc active state doesn't match with hw state "
12106                      "(expected %i, found %i)\n", crtc->active, active);
12107
12108                 if (active &&
12109                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12110                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12111                         intel_dump_pipe_config(crtc, &pipe_config,
12112                                                "[hw state]");
12113                         intel_dump_pipe_config(crtc, crtc->config,
12114                                                "[sw state]");
12115                 }
12116         }
12117 }
12118
12119 static void
12120 check_shared_dpll_state(struct drm_device *dev)
12121 {
12122         struct drm_i915_private *dev_priv = dev->dev_private;
12123         struct intel_crtc *crtc;
12124         struct intel_dpll_hw_state dpll_hw_state;
12125         int i;
12126
12127         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12128                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12129                 int enabled_crtcs = 0, active_crtcs = 0;
12130                 bool active;
12131
12132                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12133
12134                 DRM_DEBUG_KMS("%s\n", pll->name);
12135
12136                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12137
12138                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12139                      "more active pll users than references: %i vs %i\n",
12140                      pll->active, hweight32(pll->config.crtc_mask));
12141                 I915_STATE_WARN(pll->active && !pll->on,
12142                      "pll in active use but not on in sw tracking\n");
12143                 I915_STATE_WARN(pll->on && !pll->active,
12144                      "pll in on but not on in use in sw tracking\n");
12145                 I915_STATE_WARN(pll->on != active,
12146                      "pll on state mismatch (expected %i, found %i)\n",
12147                      pll->on, active);
12148
12149                 for_each_intel_crtc(dev, crtc) {
12150                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12151                                 enabled_crtcs++;
12152                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12153                                 active_crtcs++;
12154                 }
12155                 I915_STATE_WARN(pll->active != active_crtcs,
12156                      "pll active crtcs mismatch (expected %i, found %i)\n",
12157                      pll->active, active_crtcs);
12158                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12159                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12160                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12161
12162                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12163                                        sizeof(dpll_hw_state)),
12164                      "pll hw state mismatch\n");
12165         }
12166 }
12167
12168 void
12169 intel_modeset_check_state(struct drm_device *dev)
12170 {
12171         check_wm_state(dev);
12172         check_connector_state(dev);
12173         check_encoder_state(dev);
12174         check_crtc_state(dev);
12175         check_shared_dpll_state(dev);
12176 }
12177
12178 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12179                                      int dotclock)
12180 {
12181         /*
12182          * FDI already provided one idea for the dotclock.
12183          * Yell if the encoder disagrees.
12184          */
12185         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12186              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12187              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12188 }
12189
12190 static void update_scanline_offset(struct intel_crtc *crtc)
12191 {
12192         struct drm_device *dev = crtc->base.dev;
12193
12194         /*
12195          * The scanline counter increments at the leading edge of hsync.
12196          *
12197          * On most platforms it starts counting from vtotal-1 on the
12198          * first active line. That means the scanline counter value is
12199          * always one less than what we would expect. Ie. just after
12200          * start of vblank, which also occurs at start of hsync (on the
12201          * last active line), the scanline counter will read vblank_start-1.
12202          *
12203          * On gen2 the scanline counter starts counting from 1 instead
12204          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12205          * to keep the value positive), instead of adding one.
12206          *
12207          * On HSW+ the behaviour of the scanline counter depends on the output
12208          * type. For DP ports it behaves like most other platforms, but on HDMI
12209          * there's an extra 1 line difference. So we need to add two instead of
12210          * one to the value.
12211          */
12212         if (IS_GEN2(dev)) {
12213                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12214                 int vtotal;
12215
12216                 vtotal = mode->crtc_vtotal;
12217                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12218                         vtotal /= 2;
12219
12220                 crtc->scanline_offset = vtotal - 1;
12221         } else if (HAS_DDI(dev) &&
12222                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12223                 crtc->scanline_offset = 2;
12224         } else
12225                 crtc->scanline_offset = 1;
12226 }
12227
12228 static struct intel_crtc_state *
12229 intel_modeset_compute_config(struct drm_crtc *crtc,
12230                              struct drm_atomic_state *state)
12231 {
12232         struct intel_crtc_state *pipe_config;
12233         int ret = 0;
12234
12235         ret = drm_atomic_add_affected_connectors(state, crtc);
12236         if (ret)
12237                 return ERR_PTR(ret);
12238
12239         ret = drm_atomic_helper_check_modeset(state->dev, state);
12240         if (ret)
12241                 return ERR_PTR(ret);
12242
12243         /*
12244          * Note this needs changes when we start tracking multiple modes
12245          * and crtcs.  At that point we'll need to compute the whole config
12246          * (i.e. one pipe_config for each crtc) rather than just the one
12247          * for this crtc.
12248          */
12249         pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12250         if (IS_ERR(pipe_config))
12251                 return pipe_config;
12252
12253         if (!pipe_config->base.enable)
12254                 return pipe_config;
12255
12256         ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12257         if (ret)
12258                 return ERR_PTR(ret);
12259
12260         /* Check things that can only be changed through modeset */
12261         if (pipe_config->has_audio !=
12262             to_intel_crtc(crtc)->config->has_audio)
12263                 pipe_config->base.mode_changed = true;
12264
12265         /*
12266          * Note we have an issue here with infoframes: current code
12267          * only updates them on the full mode set path per hw
12268          * requirements.  So here we should be checking for any
12269          * required changes and forcing a mode set.
12270          */
12271
12272         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12273
12274         ret = drm_atomic_helper_check_planes(state->dev, state);
12275         if (ret)
12276                 return ERR_PTR(ret);
12277
12278         return pipe_config;
12279 }
12280
12281 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12282 {
12283         struct drm_device *dev = state->dev;
12284         struct drm_i915_private *dev_priv = to_i915(dev);
12285         unsigned clear_pipes = 0;
12286         struct intel_crtc *intel_crtc;
12287         struct intel_crtc_state *intel_crtc_state;
12288         struct drm_crtc *crtc;
12289         struct drm_crtc_state *crtc_state;
12290         int ret = 0;
12291         int i;
12292
12293         if (!dev_priv->display.crtc_compute_clock)
12294                 return 0;
12295
12296         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12297                 intel_crtc = to_intel_crtc(crtc);
12298                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12299
12300                 if (needs_modeset(crtc_state)) {
12301                         clear_pipes |= 1 << intel_crtc->pipe;
12302                         intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12303                 }
12304         }
12305
12306         ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12307         if (ret)
12308                 goto done;
12309
12310         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12311                 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12312                         continue;
12313
12314                 intel_crtc = to_intel_crtc(crtc);
12315                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12316
12317                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12318                                                            intel_crtc_state);
12319                 if (ret) {
12320                         intel_shared_dpll_abort_config(dev_priv);
12321                         goto done;
12322                 }
12323         }
12324
12325 done:
12326         return ret;
12327 }
12328
12329 /* Code that should eventually be part of atomic_check() */
12330 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12331 {
12332         struct drm_device *dev = state->dev;
12333         int ret;
12334
12335         /*
12336          * See if the config requires any additional preparation, e.g.
12337          * to adjust global state with pipes off.  We need to do this
12338          * here so we can get the modeset_pipe updated config for the new
12339          * mode set on this crtc.  For other crtcs we need to use the
12340          * adjusted_mode bits in the crtc directly.
12341          */
12342         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12343                 ret = valleyview_modeset_global_pipes(state);
12344                 if (ret)
12345                         return ret;
12346         }
12347
12348         ret = __intel_set_mode_setup_plls(state);
12349         if (ret)
12350                 return ret;
12351
12352         return 0;
12353 }
12354
12355 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12356                             struct intel_crtc_state *pipe_config)
12357 {
12358         struct drm_device *dev = modeset_crtc->dev;
12359         struct drm_i915_private *dev_priv = dev->dev_private;
12360         struct drm_atomic_state *state = pipe_config->base.state;
12361         struct drm_crtc *crtc;
12362         struct drm_crtc_state *crtc_state;
12363         int ret = 0;
12364         int i;
12365
12366         ret = __intel_set_mode_checks(state);
12367         if (ret < 0)
12368                 return ret;
12369
12370         ret = drm_atomic_helper_prepare_planes(dev, state);
12371         if (ret)
12372                 return ret;
12373
12374         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12375                 if (!needs_modeset(crtc_state))
12376                         continue;
12377
12378                 if (!crtc_state->enable) {
12379                         intel_crtc_disable(crtc);
12380                 } else if (crtc->state->enable) {
12381                         intel_crtc_disable_planes(crtc);
12382                         dev_priv->display.crtc_disable(crtc);
12383                 }
12384         }
12385
12386         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12387          * to set it here already despite that we pass it down the callchain.
12388          *
12389          * Note we'll need to fix this up when we start tracking multiple
12390          * pipes; here we assume a single modeset_pipe and only track the
12391          * single crtc and mode.
12392          */
12393         if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12394                 modeset_crtc->mode = pipe_config->base.mode;
12395
12396                 /*
12397                  * Calculate and store various constants which
12398                  * are later needed by vblank and swap-completion
12399                  * timestamping. They are derived from true hwmode.
12400                  */
12401                 drm_calc_timestamping_constants(modeset_crtc,
12402                                                 &pipe_config->base.adjusted_mode);
12403         }
12404
12405         /* Only after disabling all output pipelines that will be changed can we
12406          * update the the output configuration. */
12407         intel_modeset_update_state(state);
12408
12409         /* The state has been swaped above, so state actually contains the
12410          * old state now. */
12411
12412         modeset_update_crtc_power_domains(state);
12413
12414         drm_atomic_helper_commit_planes(dev, state);
12415
12416         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12417         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12418                 if (!needs_modeset(crtc->state) || !crtc->state->enable)
12419                         continue;
12420
12421                 update_scanline_offset(to_intel_crtc(crtc));
12422
12423                 dev_priv->display.crtc_enable(crtc);
12424                 intel_crtc_enable_planes(crtc);
12425         }
12426
12427         /* FIXME: add subpixel order */
12428
12429         drm_atomic_helper_cleanup_planes(dev, state);
12430
12431         drm_atomic_state_free(state);
12432
12433         return 0;
12434 }
12435
12436 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12437                                       struct intel_crtc_state *pipe_config)
12438 {
12439         int ret;
12440
12441         ret = __intel_set_mode(crtc, pipe_config);
12442
12443         if (ret == 0)
12444                 intel_modeset_check_state(crtc->dev);
12445
12446         return ret;
12447 }
12448
12449 static int intel_set_mode(struct drm_crtc *crtc,
12450                           struct drm_atomic_state *state)
12451 {
12452         struct intel_crtc_state *pipe_config;
12453         int ret = 0;
12454
12455         pipe_config = intel_modeset_compute_config(crtc, state);
12456         if (IS_ERR(pipe_config)) {
12457                 ret = PTR_ERR(pipe_config);
12458                 goto out;
12459         }
12460
12461         ret = intel_set_mode_with_config(crtc, pipe_config);
12462         if (ret)
12463                 goto out;
12464
12465 out:
12466         return ret;
12467 }
12468
12469 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12470 {
12471         struct drm_device *dev = crtc->dev;
12472         struct drm_atomic_state *state;
12473         struct intel_crtc *intel_crtc;
12474         struct intel_encoder *encoder;
12475         struct intel_connector *connector;
12476         struct drm_connector_state *connector_state;
12477         struct intel_crtc_state *crtc_state;
12478         int ret;
12479
12480         state = drm_atomic_state_alloc(dev);
12481         if (!state) {
12482                 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12483                               crtc->base.id);
12484                 return;
12485         }
12486
12487         state->acquire_ctx = dev->mode_config.acquire_ctx;
12488
12489         /* The force restore path in the HW readout code relies on the staged
12490          * config still keeping the user requested config while the actual
12491          * state has been overwritten by the configuration read from HW. We
12492          * need to copy the staged config to the atomic state, otherwise the
12493          * mode set will just reapply the state the HW is already in. */
12494         for_each_intel_encoder(dev, encoder) {
12495                 if (&encoder->new_crtc->base != crtc)
12496                         continue;
12497
12498                 for_each_intel_connector(dev, connector) {
12499                         if (connector->new_encoder != encoder)
12500                                 continue;
12501
12502                         connector_state = drm_atomic_get_connector_state(state, &connector->base);
12503                         if (IS_ERR(connector_state)) {
12504                                 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12505                                               connector->base.base.id,
12506                                               connector->base.name,
12507                                               PTR_ERR(connector_state));
12508                                 continue;
12509                         }
12510
12511                         connector_state->crtc = crtc;
12512                         connector_state->best_encoder = &encoder->base;
12513                 }
12514         }
12515
12516         for_each_intel_crtc(dev, intel_crtc) {
12517                 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12518                         continue;
12519
12520                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12521                 if (IS_ERR(crtc_state)) {
12522                         DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12523                                       intel_crtc->base.base.id,
12524                                       PTR_ERR(crtc_state));
12525                         continue;
12526                 }
12527
12528                 crtc_state->base.active = crtc_state->base.enable =
12529                         intel_crtc->new_enabled;
12530
12531                 if (&intel_crtc->base == crtc)
12532                         drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12533         }
12534
12535         intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12536                                         crtc->primary->fb, crtc->x, crtc->y);
12537
12538         ret = intel_set_mode(crtc, state);
12539         if (ret)
12540                 drm_atomic_state_free(state);
12541 }
12542
12543 #undef for_each_intel_crtc_masked
12544
12545 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12546                                         struct drm_mode_set *set)
12547 {
12548         int ro;
12549
12550         for (ro = 0; ro < set->num_connectors; ro++)
12551                 if (set->connectors[ro] == &connector->base)
12552                         return true;
12553
12554         return false;
12555 }
12556
12557 static int
12558 intel_modeset_stage_output_state(struct drm_device *dev,
12559                                  struct drm_mode_set *set,
12560                                  struct drm_atomic_state *state)
12561 {
12562         struct intel_connector *connector;
12563         struct drm_connector *drm_connector;
12564         struct drm_connector_state *connector_state;
12565         struct drm_crtc *crtc;
12566         struct drm_crtc_state *crtc_state;
12567         int i, ret;
12568
12569         /* The upper layers ensure that we either disable a crtc or have a list
12570          * of connectors. For paranoia, double-check this. */
12571         WARN_ON(!set->fb && (set->num_connectors != 0));
12572         WARN_ON(set->fb && (set->num_connectors == 0));
12573
12574         for_each_intel_connector(dev, connector) {
12575                 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12576
12577                 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12578                         continue;
12579
12580                 connector_state =
12581                         drm_atomic_get_connector_state(state, &connector->base);
12582                 if (IS_ERR(connector_state))
12583                         return PTR_ERR(connector_state);
12584
12585                 if (in_mode_set) {
12586                         int pipe = to_intel_crtc(set->crtc)->pipe;
12587                         connector_state->best_encoder =
12588                                 &intel_find_encoder(connector, pipe)->base;
12589                 }
12590
12591                 if (connector->base.state->crtc != set->crtc)
12592                         continue;
12593
12594                 /* If we disable the crtc, disable all its connectors. Also, if
12595                  * the connector is on the changing crtc but not on the new
12596                  * connector list, disable it. */
12597                 if (!set->fb || !in_mode_set) {
12598                         connector_state->best_encoder = NULL;
12599
12600                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12601                                 connector->base.base.id,
12602                                 connector->base.name);
12603                 }
12604         }
12605         /* connector->new_encoder is now updated for all connectors. */
12606
12607         for_each_connector_in_state(state, drm_connector, connector_state, i) {
12608                 connector = to_intel_connector(drm_connector);
12609
12610                 if (!connector_state->best_encoder) {
12611                         ret = drm_atomic_set_crtc_for_connector(connector_state,
12612                                                                 NULL);
12613                         if (ret)
12614                                 return ret;
12615
12616                         continue;
12617                 }
12618
12619                 if (intel_connector_in_mode_set(connector, set)) {
12620                         struct drm_crtc *crtc = connector->base.state->crtc;
12621
12622                         /* If this connector was in a previous crtc, add it
12623                          * to the state. We might need to disable it. */
12624                         if (crtc) {
12625                                 crtc_state =
12626                                         drm_atomic_get_crtc_state(state, crtc);
12627                                 if (IS_ERR(crtc_state))
12628                                         return PTR_ERR(crtc_state);
12629                         }
12630
12631                         ret = drm_atomic_set_crtc_for_connector(connector_state,
12632                                                                 set->crtc);
12633                         if (ret)
12634                                 return ret;
12635                 }
12636
12637                 /* Make sure the new CRTC will work with the encoder */
12638                 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12639                                          connector_state->crtc)) {
12640                         return -EINVAL;
12641                 }
12642
12643                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12644                         connector->base.base.id,
12645                         connector->base.name,
12646                         connector_state->crtc->base.id);
12647
12648                 if (connector_state->best_encoder != &connector->encoder->base)
12649                         connector->encoder =
12650                                 to_intel_encoder(connector_state->best_encoder);
12651         }
12652
12653         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12654                 bool has_connectors;
12655
12656                 ret = drm_atomic_add_affected_connectors(state, crtc);
12657                 if (ret)
12658                         return ret;
12659
12660                 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12661                 if (has_connectors != crtc_state->enable)
12662                         crtc_state->enable =
12663                         crtc_state->active = has_connectors;
12664         }
12665
12666         ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12667                                               set->fb, set->x, set->y);
12668         if (ret)
12669                 return ret;
12670
12671         crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12672         if (IS_ERR(crtc_state))
12673                 return PTR_ERR(crtc_state);
12674
12675         if (set->mode)
12676                 drm_mode_copy(&crtc_state->mode, set->mode);
12677
12678         if (set->num_connectors)
12679                 crtc_state->active = true;
12680
12681         return 0;
12682 }
12683
12684 static bool primary_plane_visible(struct drm_crtc *crtc)
12685 {
12686         struct intel_plane_state *plane_state =
12687                 to_intel_plane_state(crtc->primary->state);
12688
12689         return plane_state->visible;
12690 }
12691
12692 static int intel_crtc_set_config(struct drm_mode_set *set)
12693 {
12694         struct drm_device *dev;
12695         struct drm_atomic_state *state = NULL;
12696         struct intel_crtc_state *pipe_config;
12697         bool primary_plane_was_visible;
12698         int ret;
12699
12700         BUG_ON(!set);
12701         BUG_ON(!set->crtc);
12702         BUG_ON(!set->crtc->helper_private);
12703
12704         /* Enforce sane interface api - has been abused by the fb helper. */
12705         BUG_ON(!set->mode && set->fb);
12706         BUG_ON(set->fb && set->num_connectors == 0);
12707
12708         if (set->fb) {
12709                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12710                                 set->crtc->base.id, set->fb->base.id,
12711                                 (int)set->num_connectors, set->x, set->y);
12712         } else {
12713                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12714         }
12715
12716         dev = set->crtc->dev;
12717
12718         state = drm_atomic_state_alloc(dev);
12719         if (!state)
12720                 return -ENOMEM;
12721
12722         state->acquire_ctx = dev->mode_config.acquire_ctx;
12723
12724         ret = intel_modeset_stage_output_state(dev, set, state);
12725         if (ret)
12726                 goto out;
12727
12728         pipe_config = intel_modeset_compute_config(set->crtc, state);
12729         if (IS_ERR(pipe_config)) {
12730                 ret = PTR_ERR(pipe_config);
12731                 goto out;
12732         }
12733
12734         intel_update_pipe_size(to_intel_crtc(set->crtc));
12735
12736         primary_plane_was_visible = primary_plane_visible(set->crtc);
12737
12738         ret = intel_set_mode_with_config(set->crtc, pipe_config);
12739
12740         if (ret == 0 &&
12741             pipe_config->base.enable &&
12742             pipe_config->base.planes_changed &&
12743             !needs_modeset(&pipe_config->base)) {
12744                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12745
12746                 /*
12747                  * We need to make sure the primary plane is re-enabled if it
12748                  * has previously been turned off.
12749                  */
12750                 if (ret == 0 && !primary_plane_was_visible &&
12751                     primary_plane_visible(set->crtc)) {
12752                         WARN_ON(!intel_crtc->active);
12753                         intel_post_enable_primary(set->crtc);
12754                 }
12755
12756                 /*
12757                  * In the fastboot case this may be our only check of the
12758                  * state after boot.  It would be better to only do it on
12759                  * the first update, but we don't have a nice way of doing that
12760                  * (and really, set_config isn't used much for high freq page
12761                  * flipping, so increasing its cost here shouldn't be a big
12762                  * deal).
12763                  */
12764                 if (i915.fastboot && ret == 0)
12765                         intel_modeset_check_state(set->crtc->dev);
12766         }
12767
12768         if (ret) {
12769                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12770                               set->crtc->base.id, ret);
12771         }
12772
12773 out:
12774         if (ret)
12775                 drm_atomic_state_free(state);
12776         return ret;
12777 }
12778
12779 static const struct drm_crtc_funcs intel_crtc_funcs = {
12780         .gamma_set = intel_crtc_gamma_set,
12781         .set_config = intel_crtc_set_config,
12782         .destroy = intel_crtc_destroy,
12783         .page_flip = intel_crtc_page_flip,
12784         .atomic_duplicate_state = intel_crtc_duplicate_state,
12785         .atomic_destroy_state = intel_crtc_destroy_state,
12786 };
12787
12788 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12789                                       struct intel_shared_dpll *pll,
12790                                       struct intel_dpll_hw_state *hw_state)
12791 {
12792         uint32_t val;
12793
12794         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12795                 return false;
12796
12797         val = I915_READ(PCH_DPLL(pll->id));
12798         hw_state->dpll = val;
12799         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12800         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12801
12802         return val & DPLL_VCO_ENABLE;
12803 }
12804
12805 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12806                                   struct intel_shared_dpll *pll)
12807 {
12808         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12809         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12810 }
12811
12812 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12813                                 struct intel_shared_dpll *pll)
12814 {
12815         /* PCH refclock must be enabled first */
12816         ibx_assert_pch_refclk_enabled(dev_priv);
12817
12818         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12819
12820         /* Wait for the clocks to stabilize. */
12821         POSTING_READ(PCH_DPLL(pll->id));
12822         udelay(150);
12823
12824         /* The pixel multiplier can only be updated once the
12825          * DPLL is enabled and the clocks are stable.
12826          *
12827          * So write it again.
12828          */
12829         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12830         POSTING_READ(PCH_DPLL(pll->id));
12831         udelay(200);
12832 }
12833
12834 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12835                                  struct intel_shared_dpll *pll)
12836 {
12837         struct drm_device *dev = dev_priv->dev;
12838         struct intel_crtc *crtc;
12839
12840         /* Make sure no transcoder isn't still depending on us. */
12841         for_each_intel_crtc(dev, crtc) {
12842                 if (intel_crtc_to_shared_dpll(crtc) == pll)
12843                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12844         }
12845
12846         I915_WRITE(PCH_DPLL(pll->id), 0);
12847         POSTING_READ(PCH_DPLL(pll->id));
12848         udelay(200);
12849 }
12850
12851 static char *ibx_pch_dpll_names[] = {
12852         "PCH DPLL A",
12853         "PCH DPLL B",
12854 };
12855
12856 static void ibx_pch_dpll_init(struct drm_device *dev)
12857 {
12858         struct drm_i915_private *dev_priv = dev->dev_private;
12859         int i;
12860
12861         dev_priv->num_shared_dpll = 2;
12862
12863         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12864                 dev_priv->shared_dplls[i].id = i;
12865                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12866                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12867                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12868                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12869                 dev_priv->shared_dplls[i].get_hw_state =
12870                         ibx_pch_dpll_get_hw_state;
12871         }
12872 }
12873
12874 static void intel_shared_dpll_init(struct drm_device *dev)
12875 {
12876         struct drm_i915_private *dev_priv = dev->dev_private;
12877
12878         if (HAS_DDI(dev))
12879                 intel_ddi_pll_init(dev);
12880         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12881                 ibx_pch_dpll_init(dev);
12882         else
12883                 dev_priv->num_shared_dpll = 0;
12884
12885         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12886 }
12887
12888 /**
12889  * intel_wm_need_update - Check whether watermarks need updating
12890  * @plane: drm plane
12891  * @state: new plane state
12892  *
12893  * Check current plane state versus the new one to determine whether
12894  * watermarks need to be recalculated.
12895  *
12896  * Returns true or false.
12897  */
12898 bool intel_wm_need_update(struct drm_plane *plane,
12899                           struct drm_plane_state *state)
12900 {
12901         /* Update watermarks on tiling changes. */
12902         if (!plane->state->fb || !state->fb ||
12903             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12904             plane->state->rotation != state->rotation)
12905                 return true;
12906
12907         return false;
12908 }
12909
12910 /**
12911  * intel_prepare_plane_fb - Prepare fb for usage on plane
12912  * @plane: drm plane to prepare for
12913  * @fb: framebuffer to prepare for presentation
12914  *
12915  * Prepares a framebuffer for usage on a display plane.  Generally this
12916  * involves pinning the underlying object and updating the frontbuffer tracking
12917  * bits.  Some older platforms need special physical address handling for
12918  * cursor planes.
12919  *
12920  * Returns 0 on success, negative error code on failure.
12921  */
12922 int
12923 intel_prepare_plane_fb(struct drm_plane *plane,
12924                        struct drm_framebuffer *fb,
12925                        const struct drm_plane_state *new_state)
12926 {
12927         struct drm_device *dev = plane->dev;
12928         struct intel_plane *intel_plane = to_intel_plane(plane);
12929         enum pipe pipe = intel_plane->pipe;
12930         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12931         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12932         unsigned frontbuffer_bits = 0;
12933         int ret = 0;
12934
12935         if (!obj)
12936                 return 0;
12937
12938         switch (plane->type) {
12939         case DRM_PLANE_TYPE_PRIMARY:
12940                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12941                 break;
12942         case DRM_PLANE_TYPE_CURSOR:
12943                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12944                 break;
12945         case DRM_PLANE_TYPE_OVERLAY:
12946                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12947                 break;
12948         }
12949
12950         mutex_lock(&dev->struct_mutex);
12951
12952         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12953             INTEL_INFO(dev)->cursor_needs_physical) {
12954                 int align = IS_I830(dev) ? 16 * 1024 : 256;
12955                 ret = i915_gem_object_attach_phys(obj, align);
12956                 if (ret)
12957                         DRM_DEBUG_KMS("failed to attach phys object\n");
12958         } else {
12959                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12960         }
12961
12962         if (ret == 0)
12963                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12964
12965         mutex_unlock(&dev->struct_mutex);
12966
12967         return ret;
12968 }
12969
12970 /**
12971  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12972  * @plane: drm plane to clean up for
12973  * @fb: old framebuffer that was on plane
12974  *
12975  * Cleans up a framebuffer that has just been removed from a plane.
12976  */
12977 void
12978 intel_cleanup_plane_fb(struct drm_plane *plane,
12979                        struct drm_framebuffer *fb,
12980                        const struct drm_plane_state *old_state)
12981 {
12982         struct drm_device *dev = plane->dev;
12983         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12984
12985         if (WARN_ON(!obj))
12986                 return;
12987
12988         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12989             !INTEL_INFO(dev)->cursor_needs_physical) {
12990                 mutex_lock(&dev->struct_mutex);
12991                 intel_unpin_fb_obj(fb, old_state);
12992                 mutex_unlock(&dev->struct_mutex);
12993         }
12994 }
12995
12996 int
12997 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12998 {
12999         int max_scale;
13000         struct drm_device *dev;
13001         struct drm_i915_private *dev_priv;
13002         int crtc_clock, cdclk;
13003
13004         if (!intel_crtc || !crtc_state)
13005                 return DRM_PLANE_HELPER_NO_SCALING;
13006
13007         dev = intel_crtc->base.dev;
13008         dev_priv = dev->dev_private;
13009         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13010         cdclk = dev_priv->display.get_display_clock_speed(dev);
13011
13012         if (!crtc_clock || !cdclk)
13013                 return DRM_PLANE_HELPER_NO_SCALING;
13014
13015         /*
13016          * skl max scale is lower of:
13017          *    close to 3 but not 3, -1 is for that purpose
13018          *            or
13019          *    cdclk/crtc_clock
13020          */
13021         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13022
13023         return max_scale;
13024 }
13025
13026 static int
13027 intel_check_primary_plane(struct drm_plane *plane,
13028                           struct intel_plane_state *state)
13029 {
13030         struct drm_device *dev = plane->dev;
13031         struct drm_i915_private *dev_priv = dev->dev_private;
13032         struct drm_crtc *crtc = state->base.crtc;
13033         struct intel_crtc *intel_crtc;
13034         struct intel_crtc_state *crtc_state;
13035         struct drm_framebuffer *fb = state->base.fb;
13036         struct drm_rect *dest = &state->dst;
13037         struct drm_rect *src = &state->src;
13038         const struct drm_rect *clip = &state->clip;
13039         bool can_position = false;
13040         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13041         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13042         int ret;
13043
13044         crtc = crtc ? crtc : plane->crtc;
13045         intel_crtc = to_intel_crtc(crtc);
13046         crtc_state = state->base.state ?
13047                 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13048
13049         if (INTEL_INFO(dev)->gen >= 9) {
13050                 min_scale = 1;
13051                 max_scale = skl_max_scale(intel_crtc, crtc_state);
13052                 can_position = true;
13053         }
13054
13055         ret = drm_plane_helper_check_update(plane, crtc, fb,
13056                                             src, dest, clip,
13057                                             min_scale,
13058                                             max_scale,
13059                                             can_position, true,
13060                                             &state->visible);
13061         if (ret)
13062                 return ret;
13063
13064         if (intel_crtc->active) {
13065                 struct intel_plane_state *old_state =
13066                         to_intel_plane_state(plane->state);
13067
13068                 intel_crtc->atomic.wait_for_flips = true;
13069
13070                 /*
13071                  * FBC does not work on some platforms for rotated
13072                  * planes, so disable it when rotation is not 0 and
13073                  * update it when rotation is set back to 0.
13074                  *
13075                  * FIXME: This is redundant with the fbc update done in
13076                  * the primary plane enable function except that that
13077                  * one is done too late. We eventually need to unify
13078                  * this.
13079                  */
13080                 if (state->visible &&
13081                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13082                     dev_priv->fbc.crtc == intel_crtc &&
13083                     state->base.rotation != BIT(DRM_ROTATE_0)) {
13084                         intel_crtc->atomic.disable_fbc = true;
13085                 }
13086
13087                 if (state->visible && !old_state->visible) {
13088                         /*
13089                          * BDW signals flip done immediately if the plane
13090                          * is disabled, even if the plane enable is already
13091                          * armed to occur at the next vblank :(
13092                          */
13093                         if (IS_BROADWELL(dev))
13094                                 intel_crtc->atomic.wait_vblank = true;
13095                 }
13096
13097                 intel_crtc->atomic.fb_bits |=
13098                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13099
13100                 intel_crtc->atomic.update_fbc = true;
13101
13102                 if (intel_wm_need_update(plane, &state->base))
13103                         intel_crtc->atomic.update_wm = true;
13104         }
13105
13106         if (INTEL_INFO(dev)->gen >= 9) {
13107                 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13108                         to_intel_plane(plane), state, 0);
13109                 if (ret)
13110                         return ret;
13111         }
13112
13113         return 0;
13114 }
13115
13116 static void
13117 intel_commit_primary_plane(struct drm_plane *plane,
13118                            struct intel_plane_state *state)
13119 {
13120         struct drm_crtc *crtc = state->base.crtc;
13121         struct drm_framebuffer *fb = state->base.fb;
13122         struct drm_device *dev = plane->dev;
13123         struct drm_i915_private *dev_priv = dev->dev_private;
13124         struct intel_crtc *intel_crtc;
13125         struct drm_rect *src = &state->src;
13126
13127         crtc = crtc ? crtc : plane->crtc;
13128         intel_crtc = to_intel_crtc(crtc);
13129
13130         plane->fb = fb;
13131         crtc->x = src->x1 >> 16;
13132         crtc->y = src->y1 >> 16;
13133
13134         if (intel_crtc->active) {
13135                 if (state->visible)
13136                         /* FIXME: kill this fastboot hack */
13137                         intel_update_pipe_size(intel_crtc);
13138
13139                 dev_priv->display.update_primary_plane(crtc, plane->fb,
13140                                                        crtc->x, crtc->y);
13141         }
13142 }
13143
13144 static void
13145 intel_disable_primary_plane(struct drm_plane *plane,
13146                             struct drm_crtc *crtc,
13147                             bool force)
13148 {
13149         struct drm_device *dev = plane->dev;
13150         struct drm_i915_private *dev_priv = dev->dev_private;
13151
13152         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13153 }
13154
13155 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13156 {
13157         struct drm_device *dev = crtc->dev;
13158         struct drm_i915_private *dev_priv = dev->dev_private;
13159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13160         struct intel_plane *intel_plane;
13161         struct drm_plane *p;
13162         unsigned fb_bits = 0;
13163
13164         /* Track fb's for any planes being disabled */
13165         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13166                 intel_plane = to_intel_plane(p);
13167
13168                 if (intel_crtc->atomic.disabled_planes &
13169                     (1 << drm_plane_index(p))) {
13170                         switch (p->type) {
13171                         case DRM_PLANE_TYPE_PRIMARY:
13172                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13173                                 break;
13174                         case DRM_PLANE_TYPE_CURSOR:
13175                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13176                                 break;
13177                         case DRM_PLANE_TYPE_OVERLAY:
13178                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13179                                 break;
13180                         }
13181
13182                         mutex_lock(&dev->struct_mutex);
13183                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13184                         mutex_unlock(&dev->struct_mutex);
13185                 }
13186         }
13187
13188         if (intel_crtc->atomic.wait_for_flips)
13189                 intel_crtc_wait_for_pending_flips(crtc);
13190
13191         if (intel_crtc->atomic.disable_fbc)
13192                 intel_fbc_disable(dev);
13193
13194         if (intel_crtc->atomic.pre_disable_primary)
13195                 intel_pre_disable_primary(crtc);
13196
13197         if (intel_crtc->atomic.update_wm)
13198                 intel_update_watermarks(crtc);
13199
13200         intel_runtime_pm_get(dev_priv);
13201
13202         /* Perform vblank evasion around commit operation */
13203         if (intel_crtc->active)
13204                 intel_crtc->atomic.evade =
13205                         intel_pipe_update_start(intel_crtc,
13206                                                 &intel_crtc->atomic.start_vbl_count);
13207 }
13208
13209 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13210 {
13211         struct drm_device *dev = crtc->dev;
13212         struct drm_i915_private *dev_priv = dev->dev_private;
13213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13214         struct drm_plane *p;
13215
13216         if (intel_crtc->atomic.evade)
13217                 intel_pipe_update_end(intel_crtc,
13218                                       intel_crtc->atomic.start_vbl_count);
13219
13220         intel_runtime_pm_put(dev_priv);
13221
13222         if (intel_crtc->atomic.wait_vblank)
13223                 intel_wait_for_vblank(dev, intel_crtc->pipe);
13224
13225         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13226
13227         if (intel_crtc->atomic.update_fbc) {
13228                 mutex_lock(&dev->struct_mutex);
13229                 intel_fbc_update(dev);
13230                 mutex_unlock(&dev->struct_mutex);
13231         }
13232
13233         if (intel_crtc->atomic.post_enable_primary)
13234                 intel_post_enable_primary(crtc);
13235
13236         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13237                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13238                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13239                                                        false, false);
13240
13241         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13242 }
13243
13244 /**
13245  * intel_plane_destroy - destroy a plane
13246  * @plane: plane to destroy
13247  *
13248  * Common destruction function for all types of planes (primary, cursor,
13249  * sprite).
13250  */
13251 void intel_plane_destroy(struct drm_plane *plane)
13252 {
13253         struct intel_plane *intel_plane = to_intel_plane(plane);
13254         drm_plane_cleanup(plane);
13255         kfree(intel_plane);
13256 }
13257
13258 const struct drm_plane_funcs intel_plane_funcs = {
13259         .update_plane = drm_atomic_helper_update_plane,
13260         .disable_plane = drm_atomic_helper_disable_plane,
13261         .destroy = intel_plane_destroy,
13262         .set_property = drm_atomic_helper_plane_set_property,
13263         .atomic_get_property = intel_plane_atomic_get_property,
13264         .atomic_set_property = intel_plane_atomic_set_property,
13265         .atomic_duplicate_state = intel_plane_duplicate_state,
13266         .atomic_destroy_state = intel_plane_destroy_state,
13267
13268 };
13269
13270 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13271                                                     int pipe)
13272 {
13273         struct intel_plane *primary;
13274         struct intel_plane_state *state;
13275         const uint32_t *intel_primary_formats;
13276         int num_formats;
13277
13278         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13279         if (primary == NULL)
13280                 return NULL;
13281
13282         state = intel_create_plane_state(&primary->base);
13283         if (!state) {
13284                 kfree(primary);
13285                 return NULL;
13286         }
13287         primary->base.state = &state->base;
13288
13289         primary->can_scale = false;
13290         primary->max_downscale = 1;
13291         if (INTEL_INFO(dev)->gen >= 9) {
13292                 primary->can_scale = true;
13293                 state->scaler_id = -1;
13294         }
13295         primary->pipe = pipe;
13296         primary->plane = pipe;
13297         primary->check_plane = intel_check_primary_plane;
13298         primary->commit_plane = intel_commit_primary_plane;
13299         primary->disable_plane = intel_disable_primary_plane;
13300         primary->ckey.flags = I915_SET_COLORKEY_NONE;
13301         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13302                 primary->plane = !pipe;
13303
13304         if (INTEL_INFO(dev)->gen >= 9) {
13305                 intel_primary_formats = skl_primary_formats;
13306                 num_formats = ARRAY_SIZE(skl_primary_formats);
13307         } else if (INTEL_INFO(dev)->gen >= 4) {
13308                 intel_primary_formats = i965_primary_formats;
13309                 num_formats = ARRAY_SIZE(i965_primary_formats);
13310         } else {
13311                 intel_primary_formats = i8xx_primary_formats;
13312                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13313         }
13314
13315         drm_universal_plane_init(dev, &primary->base, 0,
13316                                  &intel_plane_funcs,
13317                                  intel_primary_formats, num_formats,
13318                                  DRM_PLANE_TYPE_PRIMARY);
13319
13320         if (INTEL_INFO(dev)->gen >= 4)
13321                 intel_create_rotation_property(dev, primary);
13322
13323         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13324
13325         return &primary->base;
13326 }
13327
13328 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13329 {
13330         if (!dev->mode_config.rotation_property) {
13331                 unsigned long flags = BIT(DRM_ROTATE_0) |
13332                         BIT(DRM_ROTATE_180);
13333
13334                 if (INTEL_INFO(dev)->gen >= 9)
13335                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13336
13337                 dev->mode_config.rotation_property =
13338                         drm_mode_create_rotation_property(dev, flags);
13339         }
13340         if (dev->mode_config.rotation_property)
13341                 drm_object_attach_property(&plane->base.base,
13342                                 dev->mode_config.rotation_property,
13343                                 plane->base.state->rotation);
13344 }
13345
13346 static int
13347 intel_check_cursor_plane(struct drm_plane *plane,
13348                          struct intel_plane_state *state)
13349 {
13350         struct drm_crtc *crtc = state->base.crtc;
13351         struct drm_device *dev = plane->dev;
13352         struct drm_framebuffer *fb = state->base.fb;
13353         struct drm_rect *dest = &state->dst;
13354         struct drm_rect *src = &state->src;
13355         const struct drm_rect *clip = &state->clip;
13356         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13357         struct intel_crtc *intel_crtc;
13358         unsigned stride;
13359         int ret;
13360
13361         crtc = crtc ? crtc : plane->crtc;
13362         intel_crtc = to_intel_crtc(crtc);
13363
13364         ret = drm_plane_helper_check_update(plane, crtc, fb,
13365                                             src, dest, clip,
13366                                             DRM_PLANE_HELPER_NO_SCALING,
13367                                             DRM_PLANE_HELPER_NO_SCALING,
13368                                             true, true, &state->visible);
13369         if (ret)
13370                 return ret;
13371
13372
13373         /* if we want to turn off the cursor ignore width and height */
13374         if (!obj)
13375                 goto finish;
13376
13377         /* Check for which cursor types we support */
13378         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13379                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13380                           state->base.crtc_w, state->base.crtc_h);
13381                 return -EINVAL;
13382         }
13383
13384         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13385         if (obj->base.size < stride * state->base.crtc_h) {
13386                 DRM_DEBUG_KMS("buffer is too small\n");
13387                 return -ENOMEM;
13388         }
13389
13390         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13391                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13392                 ret = -EINVAL;
13393         }
13394
13395 finish:
13396         if (intel_crtc->active) {
13397                 if (plane->state->crtc_w != state->base.crtc_w)
13398                         intel_crtc->atomic.update_wm = true;
13399
13400                 intel_crtc->atomic.fb_bits |=
13401                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13402         }
13403
13404         return ret;
13405 }
13406
13407 static void
13408 intel_disable_cursor_plane(struct drm_plane *plane,
13409                            struct drm_crtc *crtc,
13410                            bool force)
13411 {
13412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13413
13414         if (!force) {
13415                 plane->fb = NULL;
13416                 intel_crtc->cursor_bo = NULL;
13417                 intel_crtc->cursor_addr = 0;
13418         }
13419
13420         intel_crtc_update_cursor(crtc, false);
13421 }
13422
13423 static void
13424 intel_commit_cursor_plane(struct drm_plane *plane,
13425                           struct intel_plane_state *state)
13426 {
13427         struct drm_crtc *crtc = state->base.crtc;
13428         struct drm_device *dev = plane->dev;
13429         struct intel_crtc *intel_crtc;
13430         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13431         uint32_t addr;
13432
13433         crtc = crtc ? crtc : plane->crtc;
13434         intel_crtc = to_intel_crtc(crtc);
13435
13436         plane->fb = state->base.fb;
13437         crtc->cursor_x = state->base.crtc_x;
13438         crtc->cursor_y = state->base.crtc_y;
13439
13440         if (intel_crtc->cursor_bo == obj)
13441                 goto update;
13442
13443         if (!obj)
13444                 addr = 0;
13445         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13446                 addr = i915_gem_obj_ggtt_offset(obj);
13447         else
13448                 addr = obj->phys_handle->busaddr;
13449
13450         intel_crtc->cursor_addr = addr;
13451         intel_crtc->cursor_bo = obj;
13452 update:
13453
13454         if (intel_crtc->active)
13455                 intel_crtc_update_cursor(crtc, state->visible);
13456 }
13457
13458 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13459                                                    int pipe)
13460 {
13461         struct intel_plane *cursor;
13462         struct intel_plane_state *state;
13463
13464         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13465         if (cursor == NULL)
13466                 return NULL;
13467
13468         state = intel_create_plane_state(&cursor->base);
13469         if (!state) {
13470                 kfree(cursor);
13471                 return NULL;
13472         }
13473         cursor->base.state = &state->base;
13474
13475         cursor->can_scale = false;
13476         cursor->max_downscale = 1;
13477         cursor->pipe = pipe;
13478         cursor->plane = pipe;
13479         cursor->check_plane = intel_check_cursor_plane;
13480         cursor->commit_plane = intel_commit_cursor_plane;
13481         cursor->disable_plane = intel_disable_cursor_plane;
13482
13483         drm_universal_plane_init(dev, &cursor->base, 0,
13484                                  &intel_plane_funcs,
13485                                  intel_cursor_formats,
13486                                  ARRAY_SIZE(intel_cursor_formats),
13487                                  DRM_PLANE_TYPE_CURSOR);
13488
13489         if (INTEL_INFO(dev)->gen >= 4) {
13490                 if (!dev->mode_config.rotation_property)
13491                         dev->mode_config.rotation_property =
13492                                 drm_mode_create_rotation_property(dev,
13493                                                         BIT(DRM_ROTATE_0) |
13494                                                         BIT(DRM_ROTATE_180));
13495                 if (dev->mode_config.rotation_property)
13496                         drm_object_attach_property(&cursor->base.base,
13497                                 dev->mode_config.rotation_property,
13498                                 state->base.rotation);
13499         }
13500
13501         if (INTEL_INFO(dev)->gen >=9)
13502                 state->scaler_id = -1;
13503
13504         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13505
13506         return &cursor->base;
13507 }
13508
13509 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13510         struct intel_crtc_state *crtc_state)
13511 {
13512         int i;
13513         struct intel_scaler *intel_scaler;
13514         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13515
13516         for (i = 0; i < intel_crtc->num_scalers; i++) {
13517                 intel_scaler = &scaler_state->scalers[i];
13518                 intel_scaler->in_use = 0;
13519                 intel_scaler->id = i;
13520
13521                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13522         }
13523
13524         scaler_state->scaler_id = -1;
13525 }
13526
13527 static void intel_crtc_init(struct drm_device *dev, int pipe)
13528 {
13529         struct drm_i915_private *dev_priv = dev->dev_private;
13530         struct intel_crtc *intel_crtc;
13531         struct intel_crtc_state *crtc_state = NULL;
13532         struct drm_plane *primary = NULL;
13533         struct drm_plane *cursor = NULL;
13534         int i, ret;
13535
13536         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13537         if (intel_crtc == NULL)
13538                 return;
13539
13540         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13541         if (!crtc_state)
13542                 goto fail;
13543         intel_crtc->config = crtc_state;
13544         intel_crtc->base.state = &crtc_state->base;
13545         crtc_state->base.crtc = &intel_crtc->base;
13546
13547         /* initialize shared scalers */
13548         if (INTEL_INFO(dev)->gen >= 9) {
13549                 if (pipe == PIPE_C)
13550                         intel_crtc->num_scalers = 1;
13551                 else
13552                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13553
13554                 skl_init_scalers(dev, intel_crtc, crtc_state);
13555         }
13556
13557         primary = intel_primary_plane_create(dev, pipe);
13558         if (!primary)
13559                 goto fail;
13560
13561         cursor = intel_cursor_plane_create(dev, pipe);
13562         if (!cursor)
13563                 goto fail;
13564
13565         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13566                                         cursor, &intel_crtc_funcs);
13567         if (ret)
13568                 goto fail;
13569
13570         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13571         for (i = 0; i < 256; i++) {
13572                 intel_crtc->lut_r[i] = i;
13573                 intel_crtc->lut_g[i] = i;
13574                 intel_crtc->lut_b[i] = i;
13575         }
13576
13577         /*
13578          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13579          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13580          */
13581         intel_crtc->pipe = pipe;
13582         intel_crtc->plane = pipe;
13583         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13584                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13585                 intel_crtc->plane = !pipe;
13586         }
13587
13588         intel_crtc->cursor_base = ~0;
13589         intel_crtc->cursor_cntl = ~0;
13590         intel_crtc->cursor_size = ~0;
13591
13592         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13593                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13594         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13595         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13596
13597         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13598
13599         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13600         return;
13601
13602 fail:
13603         if (primary)
13604                 drm_plane_cleanup(primary);
13605         if (cursor)
13606                 drm_plane_cleanup(cursor);
13607         kfree(crtc_state);
13608         kfree(intel_crtc);
13609 }
13610
13611 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13612 {
13613         struct drm_encoder *encoder = connector->base.encoder;
13614         struct drm_device *dev = connector->base.dev;
13615
13616         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13617
13618         if (!encoder || WARN_ON(!encoder->crtc))
13619                 return INVALID_PIPE;
13620
13621         return to_intel_crtc(encoder->crtc)->pipe;
13622 }
13623
13624 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13625                                 struct drm_file *file)
13626 {
13627         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13628         struct drm_crtc *drmmode_crtc;
13629         struct intel_crtc *crtc;
13630
13631         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13632
13633         if (!drmmode_crtc) {
13634                 DRM_ERROR("no such CRTC id\n");
13635                 return -ENOENT;
13636         }
13637
13638         crtc = to_intel_crtc(drmmode_crtc);
13639         pipe_from_crtc_id->pipe = crtc->pipe;
13640
13641         return 0;
13642 }
13643
13644 static int intel_encoder_clones(struct intel_encoder *encoder)
13645 {
13646         struct drm_device *dev = encoder->base.dev;
13647         struct intel_encoder *source_encoder;
13648         int index_mask = 0;
13649         int entry = 0;
13650
13651         for_each_intel_encoder(dev, source_encoder) {
13652                 if (encoders_cloneable(encoder, source_encoder))
13653                         index_mask |= (1 << entry);
13654
13655                 entry++;
13656         }
13657
13658         return index_mask;
13659 }
13660
13661 static bool has_edp_a(struct drm_device *dev)
13662 {
13663         struct drm_i915_private *dev_priv = dev->dev_private;
13664
13665         if (!IS_MOBILE(dev))
13666                 return false;
13667
13668         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13669                 return false;
13670
13671         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13672                 return false;
13673
13674         return true;
13675 }
13676
13677 static bool intel_crt_present(struct drm_device *dev)
13678 {
13679         struct drm_i915_private *dev_priv = dev->dev_private;
13680
13681         if (INTEL_INFO(dev)->gen >= 9)
13682                 return false;
13683
13684         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13685                 return false;
13686
13687         if (IS_CHERRYVIEW(dev))
13688                 return false;
13689
13690         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13691                 return false;
13692
13693         return true;
13694 }
13695
13696 static void intel_setup_outputs(struct drm_device *dev)
13697 {
13698         struct drm_i915_private *dev_priv = dev->dev_private;
13699         struct intel_encoder *encoder;
13700         bool dpd_is_edp = false;
13701
13702         intel_lvds_init(dev);
13703
13704         if (intel_crt_present(dev))
13705                 intel_crt_init(dev);
13706
13707         if (IS_BROXTON(dev)) {
13708                 /*
13709                  * FIXME: Broxton doesn't support port detection via the
13710                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13711                  * detect the ports.
13712                  */
13713                 intel_ddi_init(dev, PORT_A);
13714                 intel_ddi_init(dev, PORT_B);
13715                 intel_ddi_init(dev, PORT_C);
13716         } else if (HAS_DDI(dev)) {
13717                 int found;
13718
13719                 /*
13720                  * Haswell uses DDI functions to detect digital outputs.
13721                  * On SKL pre-D0 the strap isn't connected, so we assume
13722                  * it's there.
13723                  */
13724                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13725                 /* WaIgnoreDDIAStrap: skl */
13726                 if (found ||
13727                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13728                         intel_ddi_init(dev, PORT_A);
13729
13730                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13731                  * register */
13732                 found = I915_READ(SFUSE_STRAP);
13733
13734                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13735                         intel_ddi_init(dev, PORT_B);
13736                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13737                         intel_ddi_init(dev, PORT_C);
13738                 if (found & SFUSE_STRAP_DDID_DETECTED)
13739                         intel_ddi_init(dev, PORT_D);
13740         } else if (HAS_PCH_SPLIT(dev)) {
13741                 int found;
13742                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13743
13744                 if (has_edp_a(dev))
13745                         intel_dp_init(dev, DP_A, PORT_A);
13746
13747                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13748                         /* PCH SDVOB multiplex with HDMIB */
13749                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
13750                         if (!found)
13751                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13752                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13753                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
13754                 }
13755
13756                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13757                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13758
13759                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13760                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13761
13762                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13763                         intel_dp_init(dev, PCH_DP_C, PORT_C);
13764
13765                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13766                         intel_dp_init(dev, PCH_DP_D, PORT_D);
13767         } else if (IS_VALLEYVIEW(dev)) {
13768                 /*
13769                  * The DP_DETECTED bit is the latched state of the DDC
13770                  * SDA pin at boot. However since eDP doesn't require DDC
13771                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
13772                  * eDP ports may have been muxed to an alternate function.
13773                  * Thus we can't rely on the DP_DETECTED bit alone to detect
13774                  * eDP ports. Consult the VBT as well as DP_DETECTED to
13775                  * detect eDP ports.
13776                  */
13777                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13778                     !intel_dp_is_edp(dev, PORT_B))
13779                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13780                                         PORT_B);
13781                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13782                     intel_dp_is_edp(dev, PORT_B))
13783                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13784
13785                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13786                     !intel_dp_is_edp(dev, PORT_C))
13787                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13788                                         PORT_C);
13789                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13790                     intel_dp_is_edp(dev, PORT_C))
13791                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13792
13793                 if (IS_CHERRYVIEW(dev)) {
13794                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13795                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13796                                                 PORT_D);
13797                         /* eDP not supported on port D, so don't check VBT */
13798                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13799                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13800                 }
13801
13802                 intel_dsi_init(dev);
13803         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13804                 bool found = false;
13805
13806                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13807                         DRM_DEBUG_KMS("probing SDVOB\n");
13808                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13809                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13810                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13811                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13812                         }
13813
13814                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
13815                                 intel_dp_init(dev, DP_B, PORT_B);
13816                 }
13817
13818                 /* Before G4X SDVOC doesn't have its own detect register */
13819
13820                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13821                         DRM_DEBUG_KMS("probing SDVOC\n");
13822                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13823                 }
13824
13825                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13826
13827                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13828                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13829                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13830                         }
13831                         if (SUPPORTS_INTEGRATED_DP(dev))
13832                                 intel_dp_init(dev, DP_C, PORT_C);
13833                 }
13834
13835                 if (SUPPORTS_INTEGRATED_DP(dev) &&
13836                     (I915_READ(DP_D) & DP_DETECTED))
13837                         intel_dp_init(dev, DP_D, PORT_D);
13838         } else if (IS_GEN2(dev))
13839                 intel_dvo_init(dev);
13840
13841         if (SUPPORTS_TV(dev))
13842                 intel_tv_init(dev);
13843
13844         intel_psr_init(dev);
13845
13846         for_each_intel_encoder(dev, encoder) {
13847                 encoder->base.possible_crtcs = encoder->crtc_mask;
13848                 encoder->base.possible_clones =
13849                         intel_encoder_clones(encoder);
13850         }
13851
13852         intel_init_pch_refclk(dev);
13853
13854         drm_helper_move_panel_connectors_to_head(dev);
13855 }
13856
13857 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13858 {
13859         struct drm_device *dev = fb->dev;
13860         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13861
13862         drm_framebuffer_cleanup(fb);
13863         mutex_lock(&dev->struct_mutex);
13864         WARN_ON(!intel_fb->obj->framebuffer_references--);
13865         drm_gem_object_unreference(&intel_fb->obj->base);
13866         mutex_unlock(&dev->struct_mutex);
13867         kfree(intel_fb);
13868 }
13869
13870 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13871                                                 struct drm_file *file,
13872                                                 unsigned int *handle)
13873 {
13874         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13875         struct drm_i915_gem_object *obj = intel_fb->obj;
13876
13877         return drm_gem_handle_create(file, &obj->base, handle);
13878 }
13879
13880 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13881         .destroy = intel_user_framebuffer_destroy,
13882         .create_handle = intel_user_framebuffer_create_handle,
13883 };
13884
13885 static
13886 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13887                          uint32_t pixel_format)
13888 {
13889         u32 gen = INTEL_INFO(dev)->gen;
13890
13891         if (gen >= 9) {
13892                 /* "The stride in bytes must not exceed the of the size of 8K
13893                  *  pixels and 32K bytes."
13894                  */
13895                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13896         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13897                 return 32*1024;
13898         } else if (gen >= 4) {
13899                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13900                         return 16*1024;
13901                 else
13902                         return 32*1024;
13903         } else if (gen >= 3) {
13904                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13905                         return 8*1024;
13906                 else
13907                         return 16*1024;
13908         } else {
13909                 /* XXX DSPC is limited to 4k tiled */
13910                 return 8*1024;
13911         }
13912 }
13913
13914 static int intel_framebuffer_init(struct drm_device *dev,
13915                                   struct intel_framebuffer *intel_fb,
13916                                   struct drm_mode_fb_cmd2 *mode_cmd,
13917                                   struct drm_i915_gem_object *obj)
13918 {
13919         unsigned int aligned_height;
13920         int ret;
13921         u32 pitch_limit, stride_alignment;
13922
13923         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13924
13925         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13926                 /* Enforce that fb modifier and tiling mode match, but only for
13927                  * X-tiled. This is needed for FBC. */
13928                 if (!!(obj->tiling_mode == I915_TILING_X) !=
13929                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13930                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13931                         return -EINVAL;
13932                 }
13933         } else {
13934                 if (obj->tiling_mode == I915_TILING_X)
13935                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13936                 else if (obj->tiling_mode == I915_TILING_Y) {
13937                         DRM_DEBUG("No Y tiling for legacy addfb\n");
13938                         return -EINVAL;
13939                 }
13940         }
13941
13942         /* Passed in modifier sanity checking. */
13943         switch (mode_cmd->modifier[0]) {
13944         case I915_FORMAT_MOD_Y_TILED:
13945         case I915_FORMAT_MOD_Yf_TILED:
13946                 if (INTEL_INFO(dev)->gen < 9) {
13947                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13948                                   mode_cmd->modifier[0]);
13949                         return -EINVAL;
13950                 }
13951         case DRM_FORMAT_MOD_NONE:
13952         case I915_FORMAT_MOD_X_TILED:
13953                 break;
13954         default:
13955                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13956                           mode_cmd->modifier[0]);
13957                 return -EINVAL;
13958         }
13959
13960         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13961                                                      mode_cmd->pixel_format);
13962         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13963                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13964                           mode_cmd->pitches[0], stride_alignment);
13965                 return -EINVAL;
13966         }
13967
13968         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13969                                            mode_cmd->pixel_format);
13970         if (mode_cmd->pitches[0] > pitch_limit) {
13971                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13972                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13973                           "tiled" : "linear",
13974                           mode_cmd->pitches[0], pitch_limit);
13975                 return -EINVAL;
13976         }
13977
13978         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13979             mode_cmd->pitches[0] != obj->stride) {
13980                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13981                           mode_cmd->pitches[0], obj->stride);
13982                 return -EINVAL;
13983         }
13984
13985         /* Reject formats not supported by any plane early. */
13986         switch (mode_cmd->pixel_format) {
13987         case DRM_FORMAT_C8:
13988         case DRM_FORMAT_RGB565:
13989         case DRM_FORMAT_XRGB8888:
13990         case DRM_FORMAT_ARGB8888:
13991                 break;
13992         case DRM_FORMAT_XRGB1555:
13993                 if (INTEL_INFO(dev)->gen > 3) {
13994                         DRM_DEBUG("unsupported pixel format: %s\n",
13995                                   drm_get_format_name(mode_cmd->pixel_format));
13996                         return -EINVAL;
13997                 }
13998                 break;
13999         case DRM_FORMAT_ABGR8888:
14000                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14001                         DRM_DEBUG("unsupported pixel format: %s\n",
14002                                   drm_get_format_name(mode_cmd->pixel_format));
14003                         return -EINVAL;
14004                 }
14005                 break;
14006         case DRM_FORMAT_XBGR8888:
14007         case DRM_FORMAT_XRGB2101010:
14008         case DRM_FORMAT_XBGR2101010:
14009                 if (INTEL_INFO(dev)->gen < 4) {
14010                         DRM_DEBUG("unsupported pixel format: %s\n",
14011                                   drm_get_format_name(mode_cmd->pixel_format));
14012                         return -EINVAL;
14013                 }
14014                 break;
14015         case DRM_FORMAT_ABGR2101010:
14016                 if (!IS_VALLEYVIEW(dev)) {
14017                         DRM_DEBUG("unsupported pixel format: %s\n",
14018                                   drm_get_format_name(mode_cmd->pixel_format));
14019                         return -EINVAL;
14020                 }
14021                 break;
14022         case DRM_FORMAT_YUYV:
14023         case DRM_FORMAT_UYVY:
14024         case DRM_FORMAT_YVYU:
14025         case DRM_FORMAT_VYUY:
14026                 if (INTEL_INFO(dev)->gen < 5) {
14027                         DRM_DEBUG("unsupported pixel format: %s\n",
14028                                   drm_get_format_name(mode_cmd->pixel_format));
14029                         return -EINVAL;
14030                 }
14031                 break;
14032         default:
14033                 DRM_DEBUG("unsupported pixel format: %s\n",
14034                           drm_get_format_name(mode_cmd->pixel_format));
14035                 return -EINVAL;
14036         }
14037
14038         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14039         if (mode_cmd->offsets[0] != 0)
14040                 return -EINVAL;
14041
14042         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14043                                                mode_cmd->pixel_format,
14044                                                mode_cmd->modifier[0]);
14045         /* FIXME drm helper for size checks (especially planar formats)? */
14046         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14047                 return -EINVAL;
14048
14049         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14050         intel_fb->obj = obj;
14051         intel_fb->obj->framebuffer_references++;
14052
14053         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14054         if (ret) {
14055                 DRM_ERROR("framebuffer init failed %d\n", ret);
14056                 return ret;
14057         }
14058
14059         return 0;
14060 }
14061
14062 static struct drm_framebuffer *
14063 intel_user_framebuffer_create(struct drm_device *dev,
14064                               struct drm_file *filp,
14065                               struct drm_mode_fb_cmd2 *mode_cmd)
14066 {
14067         struct drm_i915_gem_object *obj;
14068
14069         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14070                                                 mode_cmd->handles[0]));
14071         if (&obj->base == NULL)
14072                 return ERR_PTR(-ENOENT);
14073
14074         return intel_framebuffer_create(dev, mode_cmd, obj);
14075 }
14076
14077 #ifndef CONFIG_DRM_I915_FBDEV
14078 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14079 {
14080 }
14081 #endif
14082
14083 static const struct drm_mode_config_funcs intel_mode_funcs = {
14084         .fb_create = intel_user_framebuffer_create,
14085         .output_poll_changed = intel_fbdev_output_poll_changed,
14086         .atomic_check = intel_atomic_check,
14087         .atomic_commit = intel_atomic_commit,
14088 };
14089
14090 /* Set up chip specific display functions */
14091 static void intel_init_display(struct drm_device *dev)
14092 {
14093         struct drm_i915_private *dev_priv = dev->dev_private;
14094
14095         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14096                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14097         else if (IS_CHERRYVIEW(dev))
14098                 dev_priv->display.find_dpll = chv_find_best_dpll;
14099         else if (IS_VALLEYVIEW(dev))
14100                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14101         else if (IS_PINEVIEW(dev))
14102                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14103         else
14104                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14105
14106         if (INTEL_INFO(dev)->gen >= 9) {
14107                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14108                 dev_priv->display.get_initial_plane_config =
14109                         skylake_get_initial_plane_config;
14110                 dev_priv->display.crtc_compute_clock =
14111                         haswell_crtc_compute_clock;
14112                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14113                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14114                 dev_priv->display.off = ironlake_crtc_off;
14115                 dev_priv->display.update_primary_plane =
14116                         skylake_update_primary_plane;
14117         } else if (HAS_DDI(dev)) {
14118                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14119                 dev_priv->display.get_initial_plane_config =
14120                         ironlake_get_initial_plane_config;
14121                 dev_priv->display.crtc_compute_clock =
14122                         haswell_crtc_compute_clock;
14123                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14124                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14125                 dev_priv->display.off = ironlake_crtc_off;
14126                 dev_priv->display.update_primary_plane =
14127                         ironlake_update_primary_plane;
14128         } else if (HAS_PCH_SPLIT(dev)) {
14129                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14130                 dev_priv->display.get_initial_plane_config =
14131                         ironlake_get_initial_plane_config;
14132                 dev_priv->display.crtc_compute_clock =
14133                         ironlake_crtc_compute_clock;
14134                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14135                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14136                 dev_priv->display.off = ironlake_crtc_off;
14137                 dev_priv->display.update_primary_plane =
14138                         ironlake_update_primary_plane;
14139         } else if (IS_VALLEYVIEW(dev)) {
14140                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14141                 dev_priv->display.get_initial_plane_config =
14142                         i9xx_get_initial_plane_config;
14143                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14144                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14145                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14146                 dev_priv->display.off = i9xx_crtc_off;
14147                 dev_priv->display.update_primary_plane =
14148                         i9xx_update_primary_plane;
14149         } else {
14150                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14151                 dev_priv->display.get_initial_plane_config =
14152                         i9xx_get_initial_plane_config;
14153                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14154                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14155                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14156                 dev_priv->display.off = i9xx_crtc_off;
14157                 dev_priv->display.update_primary_plane =
14158                         i9xx_update_primary_plane;
14159         }
14160
14161         /* Returns the core display clock speed */
14162         if (IS_SKYLAKE(dev))
14163                 dev_priv->display.get_display_clock_speed =
14164                         skylake_get_display_clock_speed;
14165         else if (IS_BROADWELL(dev))
14166                 dev_priv->display.get_display_clock_speed =
14167                         broadwell_get_display_clock_speed;
14168         else if (IS_HASWELL(dev))
14169                 dev_priv->display.get_display_clock_speed =
14170                         haswell_get_display_clock_speed;
14171         else if (IS_VALLEYVIEW(dev))
14172                 dev_priv->display.get_display_clock_speed =
14173                         valleyview_get_display_clock_speed;
14174         else if (IS_GEN5(dev))
14175                 dev_priv->display.get_display_clock_speed =
14176                         ilk_get_display_clock_speed;
14177         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14178                  IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14179                 dev_priv->display.get_display_clock_speed =
14180                         i945_get_display_clock_speed;
14181         else if (IS_I915G(dev))
14182                 dev_priv->display.get_display_clock_speed =
14183                         i915_get_display_clock_speed;
14184         else if (IS_I945GM(dev) || IS_845G(dev))
14185                 dev_priv->display.get_display_clock_speed =
14186                         i9xx_misc_get_display_clock_speed;
14187         else if (IS_PINEVIEW(dev))
14188                 dev_priv->display.get_display_clock_speed =
14189                         pnv_get_display_clock_speed;
14190         else if (IS_I915GM(dev))
14191                 dev_priv->display.get_display_clock_speed =
14192                         i915gm_get_display_clock_speed;
14193         else if (IS_I865G(dev))
14194                 dev_priv->display.get_display_clock_speed =
14195                         i865_get_display_clock_speed;
14196         else if (IS_I85X(dev))
14197                 dev_priv->display.get_display_clock_speed =
14198                         i855_get_display_clock_speed;
14199         else /* 852, 830 */
14200                 dev_priv->display.get_display_clock_speed =
14201                         i830_get_display_clock_speed;
14202
14203         if (IS_GEN5(dev)) {
14204                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14205         } else if (IS_GEN6(dev)) {
14206                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14207         } else if (IS_IVYBRIDGE(dev)) {
14208                 /* FIXME: detect B0+ stepping and use auto training */
14209                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14210         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14211                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14212         } else if (IS_VALLEYVIEW(dev)) {
14213                 dev_priv->display.modeset_global_resources =
14214                         valleyview_modeset_global_resources;
14215         } else if (IS_BROXTON(dev)) {
14216                 dev_priv->display.modeset_global_resources =
14217                         broxton_modeset_global_resources;
14218         }
14219
14220         switch (INTEL_INFO(dev)->gen) {
14221         case 2:
14222                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14223                 break;
14224
14225         case 3:
14226                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14227                 break;
14228
14229         case 4:
14230         case 5:
14231                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14232                 break;
14233
14234         case 6:
14235                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14236                 break;
14237         case 7:
14238         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14239                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14240                 break;
14241         case 9:
14242                 /* Drop through - unsupported since execlist only. */
14243         default:
14244                 /* Default just returns -ENODEV to indicate unsupported */
14245                 dev_priv->display.queue_flip = intel_default_queue_flip;
14246         }
14247
14248         intel_panel_init_backlight_funcs(dev);
14249
14250         mutex_init(&dev_priv->pps_mutex);
14251 }
14252
14253 /*
14254  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14255  * resume, or other times.  This quirk makes sure that's the case for
14256  * affected systems.
14257  */
14258 static void quirk_pipea_force(struct drm_device *dev)
14259 {
14260         struct drm_i915_private *dev_priv = dev->dev_private;
14261
14262         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14263         DRM_INFO("applying pipe a force quirk\n");
14264 }
14265
14266 static void quirk_pipeb_force(struct drm_device *dev)
14267 {
14268         struct drm_i915_private *dev_priv = dev->dev_private;
14269
14270         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14271         DRM_INFO("applying pipe b force quirk\n");
14272 }
14273
14274 /*
14275  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14276  */
14277 static void quirk_ssc_force_disable(struct drm_device *dev)
14278 {
14279         struct drm_i915_private *dev_priv = dev->dev_private;
14280         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14281         DRM_INFO("applying lvds SSC disable quirk\n");
14282 }
14283
14284 /*
14285  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14286  * brightness value
14287  */
14288 static void quirk_invert_brightness(struct drm_device *dev)
14289 {
14290         struct drm_i915_private *dev_priv = dev->dev_private;
14291         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14292         DRM_INFO("applying inverted panel brightness quirk\n");
14293 }
14294
14295 /* Some VBT's incorrectly indicate no backlight is present */
14296 static void quirk_backlight_present(struct drm_device *dev)
14297 {
14298         struct drm_i915_private *dev_priv = dev->dev_private;
14299         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14300         DRM_INFO("applying backlight present quirk\n");
14301 }
14302
14303 struct intel_quirk {
14304         int device;
14305         int subsystem_vendor;
14306         int subsystem_device;
14307         void (*hook)(struct drm_device *dev);
14308 };
14309
14310 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14311 struct intel_dmi_quirk {
14312         void (*hook)(struct drm_device *dev);
14313         const struct dmi_system_id (*dmi_id_list)[];
14314 };
14315
14316 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14317 {
14318         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14319         return 1;
14320 }
14321
14322 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14323         {
14324                 .dmi_id_list = &(const struct dmi_system_id[]) {
14325                         {
14326                                 .callback = intel_dmi_reverse_brightness,
14327                                 .ident = "NCR Corporation",
14328                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14329                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14330                                 },
14331                         },
14332                         { }  /* terminating entry */
14333                 },
14334                 .hook = quirk_invert_brightness,
14335         },
14336 };
14337
14338 static struct intel_quirk intel_quirks[] = {
14339         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14340         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14341
14342         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14343         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14344
14345         /* 830 needs to leave pipe A & dpll A up */
14346         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14347
14348         /* 830 needs to leave pipe B & dpll B up */
14349         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14350
14351         /* Lenovo U160 cannot use SSC on LVDS */
14352         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14353
14354         /* Sony Vaio Y cannot use SSC on LVDS */
14355         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14356
14357         /* Acer Aspire 5734Z must invert backlight brightness */
14358         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14359
14360         /* Acer/eMachines G725 */
14361         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14362
14363         /* Acer/eMachines e725 */
14364         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14365
14366         /* Acer/Packard Bell NCL20 */
14367         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14368
14369         /* Acer Aspire 4736Z */
14370         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14371
14372         /* Acer Aspire 5336 */
14373         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14374
14375         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14376         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14377
14378         /* Acer C720 Chromebook (Core i3 4005U) */
14379         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14380
14381         /* Apple Macbook 2,1 (Core 2 T7400) */
14382         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14383
14384         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14385         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14386
14387         /* HP Chromebook 14 (Celeron 2955U) */
14388         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14389
14390         /* Dell Chromebook 11 */
14391         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14392 };
14393
14394 static void intel_init_quirks(struct drm_device *dev)
14395 {
14396         struct pci_dev *d = dev->pdev;
14397         int i;
14398
14399         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14400                 struct intel_quirk *q = &intel_quirks[i];
14401
14402                 if (d->device == q->device &&
14403                     (d->subsystem_vendor == q->subsystem_vendor ||
14404                      q->subsystem_vendor == PCI_ANY_ID) &&
14405                     (d->subsystem_device == q->subsystem_device ||
14406                      q->subsystem_device == PCI_ANY_ID))
14407                         q->hook(dev);
14408         }
14409         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14410                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14411                         intel_dmi_quirks[i].hook(dev);
14412         }
14413 }
14414
14415 /* Disable the VGA plane that we never use */
14416 static void i915_disable_vga(struct drm_device *dev)
14417 {
14418         struct drm_i915_private *dev_priv = dev->dev_private;
14419         u8 sr1;
14420         u32 vga_reg = i915_vgacntrl_reg(dev);
14421
14422         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14423         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14424         outb(SR01, VGA_SR_INDEX);
14425         sr1 = inb(VGA_SR_DATA);
14426         outb(sr1 | 1<<5, VGA_SR_DATA);
14427         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14428         udelay(300);
14429
14430         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14431         POSTING_READ(vga_reg);
14432 }
14433
14434 void intel_modeset_init_hw(struct drm_device *dev)
14435 {
14436         intel_prepare_ddi(dev);
14437
14438         if (IS_VALLEYVIEW(dev))
14439                 vlv_update_cdclk(dev);
14440
14441         intel_init_clock_gating(dev);
14442
14443         intel_enable_gt_powersave(dev);
14444 }
14445
14446 void intel_modeset_init(struct drm_device *dev)
14447 {
14448         struct drm_i915_private *dev_priv = dev->dev_private;
14449         int sprite, ret;
14450         enum pipe pipe;
14451         struct intel_crtc *crtc;
14452
14453         drm_mode_config_init(dev);
14454
14455         dev->mode_config.min_width = 0;
14456         dev->mode_config.min_height = 0;
14457
14458         dev->mode_config.preferred_depth = 24;
14459         dev->mode_config.prefer_shadow = 1;
14460
14461         dev->mode_config.allow_fb_modifiers = true;
14462
14463         dev->mode_config.funcs = &intel_mode_funcs;
14464
14465         intel_init_quirks(dev);
14466
14467         intel_init_pm(dev);
14468
14469         if (INTEL_INFO(dev)->num_pipes == 0)
14470                 return;
14471
14472         intel_init_display(dev);
14473         intel_init_audio(dev);
14474
14475         if (IS_GEN2(dev)) {
14476                 dev->mode_config.max_width = 2048;
14477                 dev->mode_config.max_height = 2048;
14478         } else if (IS_GEN3(dev)) {
14479                 dev->mode_config.max_width = 4096;
14480                 dev->mode_config.max_height = 4096;
14481         } else {
14482                 dev->mode_config.max_width = 8192;
14483                 dev->mode_config.max_height = 8192;
14484         }
14485
14486         if (IS_845G(dev) || IS_I865G(dev)) {
14487                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14488                 dev->mode_config.cursor_height = 1023;
14489         } else if (IS_GEN2(dev)) {
14490                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14491                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14492         } else {
14493                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14494                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14495         }
14496
14497         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14498
14499         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14500                       INTEL_INFO(dev)->num_pipes,
14501                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14502
14503         for_each_pipe(dev_priv, pipe) {
14504                 intel_crtc_init(dev, pipe);
14505                 for_each_sprite(dev_priv, pipe, sprite) {
14506                         ret = intel_plane_init(dev, pipe, sprite);
14507                         if (ret)
14508                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14509                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14510                 }
14511         }
14512
14513         intel_init_dpio(dev);
14514
14515         intel_shared_dpll_init(dev);
14516
14517         /* Just disable it once at startup */
14518         i915_disable_vga(dev);
14519         intel_setup_outputs(dev);
14520
14521         /* Just in case the BIOS is doing something questionable. */
14522         intel_fbc_disable(dev);
14523
14524         drm_modeset_lock_all(dev);
14525         intel_modeset_setup_hw_state(dev, false);
14526         drm_modeset_unlock_all(dev);
14527
14528         for_each_intel_crtc(dev, crtc) {
14529                 if (!crtc->active)
14530                         continue;
14531
14532                 /*
14533                  * Note that reserving the BIOS fb up front prevents us
14534                  * from stuffing other stolen allocations like the ring
14535                  * on top.  This prevents some ugliness at boot time, and
14536                  * can even allow for smooth boot transitions if the BIOS
14537                  * fb is large enough for the active pipe configuration.
14538                  */
14539                 if (dev_priv->display.get_initial_plane_config) {
14540                         dev_priv->display.get_initial_plane_config(crtc,
14541                                                            &crtc->plane_config);
14542                         /*
14543                          * If the fb is shared between multiple heads, we'll
14544                          * just get the first one.
14545                          */
14546                         intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14547                 }
14548         }
14549 }
14550
14551 static void intel_enable_pipe_a(struct drm_device *dev)
14552 {
14553         struct intel_connector *connector;
14554         struct drm_connector *crt = NULL;
14555         struct intel_load_detect_pipe load_detect_temp;
14556         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14557
14558         /* We can't just switch on the pipe A, we need to set things up with a
14559          * proper mode and output configuration. As a gross hack, enable pipe A
14560          * by enabling the load detect pipe once. */
14561         for_each_intel_connector(dev, connector) {
14562                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14563                         crt = &connector->base;
14564                         break;
14565                 }
14566         }
14567
14568         if (!crt)
14569                 return;
14570
14571         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14572                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14573 }
14574
14575 static bool
14576 intel_check_plane_mapping(struct intel_crtc *crtc)
14577 {
14578         struct drm_device *dev = crtc->base.dev;
14579         struct drm_i915_private *dev_priv = dev->dev_private;
14580         u32 reg, val;
14581
14582         if (INTEL_INFO(dev)->num_pipes == 1)
14583                 return true;
14584
14585         reg = DSPCNTR(!crtc->plane);
14586         val = I915_READ(reg);
14587
14588         if ((val & DISPLAY_PLANE_ENABLE) &&
14589             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14590                 return false;
14591
14592         return true;
14593 }
14594
14595 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14596 {
14597         struct drm_device *dev = crtc->base.dev;
14598         struct drm_i915_private *dev_priv = dev->dev_private;
14599         u32 reg;
14600
14601         /* Clear any frame start delays used for debugging left by the BIOS */
14602         reg = PIPECONF(crtc->config->cpu_transcoder);
14603         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14604
14605         /* restore vblank interrupts to correct state */
14606         drm_crtc_vblank_reset(&crtc->base);
14607         if (crtc->active) {
14608                 update_scanline_offset(crtc);
14609                 drm_crtc_vblank_on(&crtc->base);
14610         }
14611
14612         /* We need to sanitize the plane -> pipe mapping first because this will
14613          * disable the crtc (and hence change the state) if it is wrong. Note
14614          * that gen4+ has a fixed plane -> pipe mapping.  */
14615         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14616                 struct intel_connector *connector;
14617                 bool plane;
14618
14619                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14620                               crtc->base.base.id);
14621
14622                 /* Pipe has the wrong plane attached and the plane is active.
14623                  * Temporarily change the plane mapping and disable everything
14624                  * ...  */
14625                 plane = crtc->plane;
14626                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14627                 crtc->plane = !plane;
14628                 intel_crtc_disable_planes(&crtc->base);
14629                 dev_priv->display.crtc_disable(&crtc->base);
14630                 crtc->plane = plane;
14631
14632                 /* ... and break all links. */
14633                 for_each_intel_connector(dev, connector) {
14634                         if (connector->encoder->base.crtc != &crtc->base)
14635                                 continue;
14636
14637                         connector->base.dpms = DRM_MODE_DPMS_OFF;
14638                         connector->base.encoder = NULL;
14639                 }
14640                 /* multiple connectors may have the same encoder:
14641                  *  handle them and break crtc link separately */
14642                 for_each_intel_connector(dev, connector)
14643                         if (connector->encoder->base.crtc == &crtc->base) {
14644                                 connector->encoder->base.crtc = NULL;
14645                                 connector->encoder->connectors_active = false;
14646                         }
14647
14648                 WARN_ON(crtc->active);
14649                 crtc->base.state->enable = false;
14650                 crtc->base.state->active = false;
14651                 crtc->base.enabled = false;
14652         }
14653
14654         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14655             crtc->pipe == PIPE_A && !crtc->active) {
14656                 /* BIOS forgot to enable pipe A, this mostly happens after
14657                  * resume. Force-enable the pipe to fix this, the update_dpms
14658                  * call below we restore the pipe to the right state, but leave
14659                  * the required bits on. */
14660                 intel_enable_pipe_a(dev);
14661         }
14662
14663         /* Adjust the state of the output pipe according to whether we
14664          * have active connectors/encoders. */
14665         intel_crtc_update_dpms(&crtc->base);
14666
14667         if (crtc->active != crtc->base.state->enable) {
14668                 struct intel_encoder *encoder;
14669
14670                 /* This can happen either due to bugs in the get_hw_state
14671                  * functions or because the pipe is force-enabled due to the
14672                  * pipe A quirk. */
14673                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14674                               crtc->base.base.id,
14675                               crtc->base.state->enable ? "enabled" : "disabled",
14676                               crtc->active ? "enabled" : "disabled");
14677
14678                 crtc->base.state->enable = crtc->active;
14679                 crtc->base.state->active = crtc->active;
14680                 crtc->base.enabled = crtc->active;
14681
14682                 /* Because we only establish the connector -> encoder ->
14683                  * crtc links if something is active, this means the
14684                  * crtc is now deactivated. Break the links. connector
14685                  * -> encoder links are only establish when things are
14686                  *  actually up, hence no need to break them. */
14687                 WARN_ON(crtc->active);
14688
14689                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14690                         WARN_ON(encoder->connectors_active);
14691                         encoder->base.crtc = NULL;
14692                 }
14693         }
14694
14695         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14696                 /*
14697                  * We start out with underrun reporting disabled to avoid races.
14698                  * For correct bookkeeping mark this on active crtcs.
14699                  *
14700                  * Also on gmch platforms we dont have any hardware bits to
14701                  * disable the underrun reporting. Which means we need to start
14702                  * out with underrun reporting disabled also on inactive pipes,
14703                  * since otherwise we'll complain about the garbage we read when
14704                  * e.g. coming up after runtime pm.
14705                  *
14706                  * No protection against concurrent access is required - at
14707                  * worst a fifo underrun happens which also sets this to false.
14708                  */
14709                 crtc->cpu_fifo_underrun_disabled = true;
14710                 crtc->pch_fifo_underrun_disabled = true;
14711         }
14712 }
14713
14714 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14715 {
14716         struct intel_connector *connector;
14717         struct drm_device *dev = encoder->base.dev;
14718
14719         /* We need to check both for a crtc link (meaning that the
14720          * encoder is active and trying to read from a pipe) and the
14721          * pipe itself being active. */
14722         bool has_active_crtc = encoder->base.crtc &&
14723                 to_intel_crtc(encoder->base.crtc)->active;
14724
14725         if (encoder->connectors_active && !has_active_crtc) {
14726                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14727                               encoder->base.base.id,
14728                               encoder->base.name);
14729
14730                 /* Connector is active, but has no active pipe. This is
14731                  * fallout from our resume register restoring. Disable
14732                  * the encoder manually again. */
14733                 if (encoder->base.crtc) {
14734                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14735                                       encoder->base.base.id,
14736                                       encoder->base.name);
14737                         encoder->disable(encoder);
14738                         if (encoder->post_disable)
14739                                 encoder->post_disable(encoder);
14740                 }
14741                 encoder->base.crtc = NULL;
14742                 encoder->connectors_active = false;
14743
14744                 /* Inconsistent output/port/pipe state happens presumably due to
14745                  * a bug in one of the get_hw_state functions. Or someplace else
14746                  * in our code, like the register restore mess on resume. Clamp
14747                  * things to off as a safer default. */
14748                 for_each_intel_connector(dev, connector) {
14749                         if (connector->encoder != encoder)
14750                                 continue;
14751                         connector->base.dpms = DRM_MODE_DPMS_OFF;
14752                         connector->base.encoder = NULL;
14753                 }
14754         }
14755         /* Enabled encoders without active connectors will be fixed in
14756          * the crtc fixup. */
14757 }
14758
14759 void i915_redisable_vga_power_on(struct drm_device *dev)
14760 {
14761         struct drm_i915_private *dev_priv = dev->dev_private;
14762         u32 vga_reg = i915_vgacntrl_reg(dev);
14763
14764         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14765                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14766                 i915_disable_vga(dev);
14767         }
14768 }
14769
14770 void i915_redisable_vga(struct drm_device *dev)
14771 {
14772         struct drm_i915_private *dev_priv = dev->dev_private;
14773
14774         /* This function can be called both from intel_modeset_setup_hw_state or
14775          * at a very early point in our resume sequence, where the power well
14776          * structures are not yet restored. Since this function is at a very
14777          * paranoid "someone might have enabled VGA while we were not looking"
14778          * level, just check if the power well is enabled instead of trying to
14779          * follow the "don't touch the power well if we don't need it" policy
14780          * the rest of the driver uses. */
14781         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14782                 return;
14783
14784         i915_redisable_vga_power_on(dev);
14785 }
14786
14787 static bool primary_get_hw_state(struct intel_crtc *crtc)
14788 {
14789         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14790
14791         if (!crtc->active)
14792                 return false;
14793
14794         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14795 }
14796
14797 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14798 {
14799         struct drm_i915_private *dev_priv = dev->dev_private;
14800         enum pipe pipe;
14801         struct intel_crtc *crtc;
14802         struct intel_encoder *encoder;
14803         struct intel_connector *connector;
14804         int i;
14805
14806         for_each_intel_crtc(dev, crtc) {
14807                 struct drm_plane *primary = crtc->base.primary;
14808                 struct intel_plane_state *plane_state;
14809
14810                 memset(crtc->config, 0, sizeof(*crtc->config));
14811
14812                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14813
14814                 crtc->active = dev_priv->display.get_pipe_config(crtc,
14815                                                                  crtc->config);
14816
14817                 crtc->base.state->enable = crtc->active;
14818                 crtc->base.state->active = crtc->active;
14819                 crtc->base.enabled = crtc->active;
14820
14821                 plane_state = to_intel_plane_state(primary->state);
14822                 plane_state->visible = primary_get_hw_state(crtc);
14823
14824                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14825                               crtc->base.base.id,
14826                               crtc->active ? "enabled" : "disabled");
14827         }
14828
14829         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14830                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14831
14832                 pll->on = pll->get_hw_state(dev_priv, pll,
14833                                             &pll->config.hw_state);
14834                 pll->active = 0;
14835                 pll->config.crtc_mask = 0;
14836                 for_each_intel_crtc(dev, crtc) {
14837                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14838                                 pll->active++;
14839                                 pll->config.crtc_mask |= 1 << crtc->pipe;
14840                         }
14841                 }
14842
14843                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14844                               pll->name, pll->config.crtc_mask, pll->on);
14845
14846                 if (pll->config.crtc_mask)
14847                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14848         }
14849
14850         for_each_intel_encoder(dev, encoder) {
14851                 pipe = 0;
14852
14853                 if (encoder->get_hw_state(encoder, &pipe)) {
14854                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14855                         encoder->base.crtc = &crtc->base;
14856                         encoder->get_config(encoder, crtc->config);
14857                 } else {
14858                         encoder->base.crtc = NULL;
14859                 }
14860
14861                 encoder->connectors_active = false;
14862                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14863                               encoder->base.base.id,
14864                               encoder->base.name,
14865                               encoder->base.crtc ? "enabled" : "disabled",
14866                               pipe_name(pipe));
14867         }
14868
14869         for_each_intel_connector(dev, connector) {
14870                 if (connector->get_hw_state(connector)) {
14871                         connector->base.dpms = DRM_MODE_DPMS_ON;
14872                         connector->encoder->connectors_active = true;
14873                         connector->base.encoder = &connector->encoder->base;
14874                 } else {
14875                         connector->base.dpms = DRM_MODE_DPMS_OFF;
14876                         connector->base.encoder = NULL;
14877                 }
14878                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14879                               connector->base.base.id,
14880                               connector->base.name,
14881                               connector->base.encoder ? "enabled" : "disabled");
14882         }
14883 }
14884
14885 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14886  * and i915 state tracking structures. */
14887 void intel_modeset_setup_hw_state(struct drm_device *dev,
14888                                   bool force_restore)
14889 {
14890         struct drm_i915_private *dev_priv = dev->dev_private;
14891         enum pipe pipe;
14892         struct intel_crtc *crtc;
14893         struct intel_encoder *encoder;
14894         int i;
14895
14896         intel_modeset_readout_hw_state(dev);
14897
14898         /*
14899          * Now that we have the config, copy it to each CRTC struct
14900          * Note that this could go away if we move to using crtc_config
14901          * checking everywhere.
14902          */
14903         for_each_intel_crtc(dev, crtc) {
14904                 if (crtc->active && i915.fastboot) {
14905                         intel_mode_from_pipe_config(&crtc->base.mode,
14906                                                     crtc->config);
14907                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14908                                       crtc->base.base.id);
14909                         drm_mode_debug_printmodeline(&crtc->base.mode);
14910                 }
14911         }
14912
14913         /* HW state is read out, now we need to sanitize this mess. */
14914         for_each_intel_encoder(dev, encoder) {
14915                 intel_sanitize_encoder(encoder);
14916         }
14917
14918         for_each_pipe(dev_priv, pipe) {
14919                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14920                 intel_sanitize_crtc(crtc);
14921                 intel_dump_pipe_config(crtc, crtc->config,
14922                                        "[setup_hw_state]");
14923         }
14924
14925         intel_modeset_update_connector_atomic_state(dev);
14926
14927         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14928                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14929
14930                 if (!pll->on || pll->active)
14931                         continue;
14932
14933                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14934
14935                 pll->disable(dev_priv, pll);
14936                 pll->on = false;
14937         }
14938
14939         if (IS_GEN9(dev))
14940                 skl_wm_get_hw_state(dev);
14941         else if (HAS_PCH_SPLIT(dev))
14942                 ilk_wm_get_hw_state(dev);
14943
14944         if (force_restore) {
14945                 i915_redisable_vga(dev);
14946
14947                 /*
14948                  * We need to use raw interfaces for restoring state to avoid
14949                  * checking (bogus) intermediate states.
14950                  */
14951                 for_each_pipe(dev_priv, pipe) {
14952                         struct drm_crtc *crtc =
14953                                 dev_priv->pipe_to_crtc_mapping[pipe];
14954
14955                         intel_crtc_restore_mode(crtc);
14956                 }
14957         } else {
14958                 intel_modeset_update_staged_output_state(dev);
14959         }
14960
14961         intel_modeset_check_state(dev);
14962 }
14963
14964 void intel_modeset_gem_init(struct drm_device *dev)
14965 {
14966         struct drm_i915_private *dev_priv = dev->dev_private;
14967         struct drm_crtc *c;
14968         struct drm_i915_gem_object *obj;
14969         int ret;
14970
14971         mutex_lock(&dev->struct_mutex);
14972         intel_init_gt_powersave(dev);
14973         mutex_unlock(&dev->struct_mutex);
14974
14975         /*
14976          * There may be no VBT; and if the BIOS enabled SSC we can
14977          * just keep using it to avoid unnecessary flicker.  Whereas if the
14978          * BIOS isn't using it, don't assume it will work even if the VBT
14979          * indicates as much.
14980          */
14981         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14982                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14983                                                 DREF_SSC1_ENABLE);
14984
14985         intel_modeset_init_hw(dev);
14986
14987         intel_setup_overlay(dev);
14988
14989         /*
14990          * Make sure any fbs we allocated at startup are properly
14991          * pinned & fenced.  When we do the allocation it's too early
14992          * for this.
14993          */
14994         for_each_crtc(dev, c) {
14995                 obj = intel_fb_obj(c->primary->fb);
14996                 if (obj == NULL)
14997                         continue;
14998
14999                 mutex_lock(&dev->struct_mutex);
15000                 ret = intel_pin_and_fence_fb_obj(c->primary,
15001                                                  c->primary->fb,
15002                                                  c->primary->state,
15003                                                  NULL);
15004                 mutex_unlock(&dev->struct_mutex);
15005                 if (ret) {
15006                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15007                                   to_intel_crtc(c)->pipe);
15008                         drm_framebuffer_unreference(c->primary->fb);
15009                         c->primary->fb = NULL;
15010                         update_state_fb(c->primary);
15011                 }
15012         }
15013
15014         intel_backlight_register(dev);
15015 }
15016
15017 void intel_connector_unregister(struct intel_connector *intel_connector)
15018 {
15019         struct drm_connector *connector = &intel_connector->base;
15020
15021         intel_panel_destroy_backlight(connector);
15022         drm_connector_unregister(connector);
15023 }
15024
15025 void intel_modeset_cleanup(struct drm_device *dev)
15026 {
15027         struct drm_i915_private *dev_priv = dev->dev_private;
15028         struct drm_connector *connector;
15029
15030         intel_disable_gt_powersave(dev);
15031
15032         intel_backlight_unregister(dev);
15033
15034         /*
15035          * Interrupts and polling as the first thing to avoid creating havoc.
15036          * Too much stuff here (turning of connectors, ...) would
15037          * experience fancy races otherwise.
15038          */
15039         intel_irq_uninstall(dev_priv);
15040
15041         /*
15042          * Due to the hpd irq storm handling the hotplug work can re-arm the
15043          * poll handlers. Hence disable polling after hpd handling is shut down.
15044          */
15045         drm_kms_helper_poll_fini(dev);
15046
15047         mutex_lock(&dev->struct_mutex);
15048
15049         intel_unregister_dsm_handler();
15050
15051         intel_fbc_disable(dev);
15052
15053         mutex_unlock(&dev->struct_mutex);
15054
15055         /* flush any delayed tasks or pending work */
15056         flush_scheduled_work();
15057
15058         /* destroy the backlight and sysfs files before encoders/connectors */
15059         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15060                 struct intel_connector *intel_connector;
15061
15062                 intel_connector = to_intel_connector(connector);
15063                 intel_connector->unregister(intel_connector);
15064         }
15065
15066         drm_mode_config_cleanup(dev);
15067
15068         intel_cleanup_overlay(dev);
15069
15070         mutex_lock(&dev->struct_mutex);
15071         intel_cleanup_gt_powersave(dev);
15072         mutex_unlock(&dev->struct_mutex);
15073 }
15074
15075 /*
15076  * Return which encoder is currently attached for connector.
15077  */
15078 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15079 {
15080         return &intel_attached_encoder(connector)->base;
15081 }
15082
15083 void intel_connector_attach_encoder(struct intel_connector *connector,
15084                                     struct intel_encoder *encoder)
15085 {
15086         connector->encoder = encoder;
15087         drm_mode_connector_attach_encoder(&connector->base,
15088                                           &encoder->base);
15089 }
15090
15091 /*
15092  * set vga decode state - true == enable VGA decode
15093  */
15094 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15095 {
15096         struct drm_i915_private *dev_priv = dev->dev_private;
15097         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15098         u16 gmch_ctrl;
15099
15100         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15101                 DRM_ERROR("failed to read control word\n");
15102                 return -EIO;
15103         }
15104
15105         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15106                 return 0;
15107
15108         if (state)
15109                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15110         else
15111                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15112
15113         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15114                 DRM_ERROR("failed to write control word\n");
15115                 return -EIO;
15116         }
15117
15118         return 0;
15119 }
15120
15121 struct intel_display_error_state {
15122
15123         u32 power_well_driver;
15124
15125         int num_transcoders;
15126
15127         struct intel_cursor_error_state {
15128                 u32 control;
15129                 u32 position;
15130                 u32 base;
15131                 u32 size;
15132         } cursor[I915_MAX_PIPES];
15133
15134         struct intel_pipe_error_state {
15135                 bool power_domain_on;
15136                 u32 source;
15137                 u32 stat;
15138         } pipe[I915_MAX_PIPES];
15139
15140         struct intel_plane_error_state {
15141                 u32 control;
15142                 u32 stride;
15143                 u32 size;
15144                 u32 pos;
15145                 u32 addr;
15146                 u32 surface;
15147                 u32 tile_offset;
15148         } plane[I915_MAX_PIPES];
15149
15150         struct intel_transcoder_error_state {
15151                 bool power_domain_on;
15152                 enum transcoder cpu_transcoder;
15153
15154                 u32 conf;
15155
15156                 u32 htotal;
15157                 u32 hblank;
15158                 u32 hsync;
15159                 u32 vtotal;
15160                 u32 vblank;
15161                 u32 vsync;
15162         } transcoder[4];
15163 };
15164
15165 struct intel_display_error_state *
15166 intel_display_capture_error_state(struct drm_device *dev)
15167 {
15168         struct drm_i915_private *dev_priv = dev->dev_private;
15169         struct intel_display_error_state *error;
15170         int transcoders[] = {
15171                 TRANSCODER_A,
15172                 TRANSCODER_B,
15173                 TRANSCODER_C,
15174                 TRANSCODER_EDP,
15175         };
15176         int i;
15177
15178         if (INTEL_INFO(dev)->num_pipes == 0)
15179                 return NULL;
15180
15181         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15182         if (error == NULL)
15183                 return NULL;
15184
15185         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15186                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15187
15188         for_each_pipe(dev_priv, i) {
15189                 error->pipe[i].power_domain_on =
15190                         __intel_display_power_is_enabled(dev_priv,
15191                                                          POWER_DOMAIN_PIPE(i));
15192                 if (!error->pipe[i].power_domain_on)
15193                         continue;
15194
15195                 error->cursor[i].control = I915_READ(CURCNTR(i));
15196                 error->cursor[i].position = I915_READ(CURPOS(i));
15197                 error->cursor[i].base = I915_READ(CURBASE(i));
15198
15199                 error->plane[i].control = I915_READ(DSPCNTR(i));
15200                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15201                 if (INTEL_INFO(dev)->gen <= 3) {
15202                         error->plane[i].size = I915_READ(DSPSIZE(i));
15203                         error->plane[i].pos = I915_READ(DSPPOS(i));
15204                 }
15205                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15206                         error->plane[i].addr = I915_READ(DSPADDR(i));
15207                 if (INTEL_INFO(dev)->gen >= 4) {
15208                         error->plane[i].surface = I915_READ(DSPSURF(i));
15209                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15210                 }
15211
15212                 error->pipe[i].source = I915_READ(PIPESRC(i));
15213
15214                 if (HAS_GMCH_DISPLAY(dev))
15215                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15216         }
15217
15218         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15219         if (HAS_DDI(dev_priv->dev))
15220                 error->num_transcoders++; /* Account for eDP. */
15221
15222         for (i = 0; i < error->num_transcoders; i++) {
15223                 enum transcoder cpu_transcoder = transcoders[i];
15224
15225                 error->transcoder[i].power_domain_on =
15226                         __intel_display_power_is_enabled(dev_priv,
15227                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15228                 if (!error->transcoder[i].power_domain_on)
15229                         continue;
15230
15231                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15232
15233                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15234                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15235                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15236                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15237                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15238                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15239                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15240         }
15241
15242         return error;
15243 }
15244
15245 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15246
15247 void
15248 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15249                                 struct drm_device *dev,
15250                                 struct intel_display_error_state *error)
15251 {
15252         struct drm_i915_private *dev_priv = dev->dev_private;
15253         int i;
15254
15255         if (!error)
15256                 return;
15257
15258         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15259         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15260                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15261                            error->power_well_driver);
15262         for_each_pipe(dev_priv, i) {
15263                 err_printf(m, "Pipe [%d]:\n", i);
15264                 err_printf(m, "  Power: %s\n",
15265                            error->pipe[i].power_domain_on ? "on" : "off");
15266                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15267                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15268
15269                 err_printf(m, "Plane [%d]:\n", i);
15270                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15271                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15272                 if (INTEL_INFO(dev)->gen <= 3) {
15273                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15274                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15275                 }
15276                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15277                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15278                 if (INTEL_INFO(dev)->gen >= 4) {
15279                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15280                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15281                 }
15282
15283                 err_printf(m, "Cursor [%d]:\n", i);
15284                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15285                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15286                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15287         }
15288
15289         for (i = 0; i < error->num_transcoders; i++) {
15290                 err_printf(m, "CPU transcoder: %c\n",
15291                            transcoder_name(error->transcoder[i].cpu_transcoder));
15292                 err_printf(m, "  Power: %s\n",
15293                            error->transcoder[i].power_domain_on ? "on" : "off");
15294                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15295                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15296                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15297                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15298                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15299                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15300                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15301         }
15302 }
15303
15304 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15305 {
15306         struct intel_crtc *crtc;
15307
15308         for_each_intel_crtc(dev, crtc) {
15309                 struct intel_unpin_work *work;
15310
15311                 spin_lock_irq(&dev->event_lock);
15312
15313                 work = crtc->unpin_work;
15314
15315                 if (work && work->event &&
15316                     work->event->base.file_priv == file) {
15317                         kfree(work->event);
15318                         work->event = NULL;
15319                 }
15320
15321                 spin_unlock_irq(&dev->event_lock);
15322         }
15323 }