drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  78
  79 static void intel_increase_pllclock(struct drm_device *dev,
  80                                     enum pipe pipe);
  81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  82
  83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  84                                 struct intel_crtc_config *pipe_config);
  85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  86                                    struct intel_crtc_config *pipe_config);
  87
  88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  89                           int x, int y, struct drm_framebuffer *old_fb);
  90 static int intel_framebuffer_init(struct drm_device *dev,
  91                                   struct intel_framebuffer *ifb,
  92                                   struct drm_mode_fb_cmd2 *mode_cmd,
  93                                   struct drm_i915_gem_object *obj);
  94 static void intel_dp_set_m_n(struct intel_crtc *crtc);
  95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  98                                          struct intel_link_m_n *m_n);
  99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 102 static void vlv_prepare_pll(struct intel_crtc *crtc);
 103
 104 typedef struct {
 105         int     min, max;
 106 } intel_range_t;
 107
 108 typedef struct {
 109         int     dot_limit;
 110         int     p2_slow, p2_fast;
 111 } intel_p2_t;
 112
 113 typedef struct intel_limit intel_limit_t;
 114 struct intel_limit {
 115         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 116         intel_p2_t          p2;
 117 };
 118
 119 int
 120 intel_pch_rawclk(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123
 124         WARN_ON(!HAS_PCH_SPLIT(dev));
 125
 126         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 127 }
 128
 129 static inline u32 /* units of 100MHz */
 130 intel_fdi_link_freq(struct drm_device *dev)
 131 {
 132         if (IS_GEN5(dev)) {
 133                 struct drm_i915_private *dev_priv = dev->dev_private;
 134                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 135         } else
 136                 return 27;
 137 }
 138
 139 static const intel_limit_t intel_limits_i8xx_dac = {
 140         .dot = { .min = 25000, .max = 350000 },
 141         .vco = { .min = 908000, .max = 1512000 },
 142         .n = { .min = 2, .max = 16 },
 143         .m = { .min = 96, .max = 140 },
 144         .m1 = { .min = 18, .max = 26 },
 145         .m2 = { .min = 6, .max = 16 },
 146         .p = { .min = 4, .max = 128 },
 147         .p1 = { .min = 2, .max = 33 },
 148         .p2 = { .dot_limit = 165000,
 149                 .p2_slow = 4, .p2_fast = 2 },
 150 };
 151
 152 static const intel_limit_t intel_limits_i8xx_dvo = {
 153         .dot = { .min = 25000, .max = 350000 },
 154         .vco = { .min = 908000, .max = 1512000 },
 155         .n = { .min = 2, .max = 16 },
 156         .m = { .min = 96, .max = 140 },
 157         .m1 = { .min = 18, .max = 26 },
 158         .m2 = { .min = 6, .max = 16 },
 159         .p = { .min = 4, .max = 128 },
 160         .p1 = { .min = 2, .max = 33 },
 161         .p2 = { .dot_limit = 165000,
 162                 .p2_slow = 4, .p2_fast = 4 },
 163 };
 164
 165 static const intel_limit_t intel_limits_i8xx_lvds = {
 166         .dot = { .min = 25000, .max = 350000 },
 167         .vco = { .min = 908000, .max = 1512000 },
 168         .n = { .min = 2, .max = 16 },
 169         .m = { .min = 96, .max = 140 },
 170         .m1 = { .min = 18, .max = 26 },
 171         .m2 = { .min = 6, .max = 16 },
 172         .p = { .min = 4, .max = 128 },
 173         .p1 = { .min = 1, .max = 6 },
 174         .p2 = { .dot_limit = 165000,
 175                 .p2_slow = 14, .p2_fast = 7 },
 176 };
 177
 178 static const intel_limit_t intel_limits_i9xx_sdvo = {
 179         .dot = { .min = 20000, .max = 400000 },
 180         .vco = { .min = 1400000, .max = 2800000 },
 181         .n = { .min = 1, .max = 6 },
 182         .m = { .min = 70, .max = 120 },
 183         .m1 = { .min = 8, .max = 18 },
 184         .m2 = { .min = 3, .max = 7 },
 185         .p = { .min = 5, .max = 80 },
 186         .p1 = { .min = 1, .max = 8 },
 187         .p2 = { .dot_limit = 200000,
 188                 .p2_slow = 10, .p2_fast = 5 },
 189 };
 190
 191 static const intel_limit_t intel_limits_i9xx_lvds = {
 192         .dot = { .min = 20000, .max = 400000 },
 193         .vco = { .min = 1400000, .max = 2800000 },
 194         .n = { .min = 1, .max = 6 },
 195         .m = { .min = 70, .max = 120 },
 196         .m1 = { .min = 8, .max = 18 },
 197         .m2 = { .min = 3, .max = 7 },
 198         .p = { .min = 7, .max = 98 },
 199         .p1 = { .min = 1, .max = 8 },
 200         .p2 = { .dot_limit = 112000,
 201                 .p2_slow = 14, .p2_fast = 7 },
 202 };
 203
 204
 205 static const intel_limit_t intel_limits_g4x_sdvo = {
 206         .dot = { .min = 25000, .max = 270000 },
 207         .vco = { .min = 1750000, .max = 3500000},
 208         .n = { .min = 1, .max = 4 },
 209         .m = { .min = 104, .max = 138 },
 210         .m1 = { .min = 17, .max = 23 },
 211         .m2 = { .min = 5, .max = 11 },
 212         .p = { .min = 10, .max = 30 },
 213         .p1 = { .min = 1, .max = 3},
 214         .p2 = { .dot_limit = 270000,
 215                 .p2_slow = 10,
 216                 .p2_fast = 10
 217         },
 218 };
 219
 220 static const intel_limit_t intel_limits_g4x_hdmi = {
 221         .dot = { .min = 22000, .max = 400000 },
 222         .vco = { .min = 1750000, .max = 3500000},
 223         .n = { .min = 1, .max = 4 },
 224         .m = { .min = 104, .max = 138 },
 225         .m1 = { .min = 16, .max = 23 },
 226         .m2 = { .min = 5, .max = 11 },
 227         .p = { .min = 5, .max = 80 },
 228         .p1 = { .min = 1, .max = 8},
 229         .p2 = { .dot_limit = 165000,
 230                 .p2_slow = 10, .p2_fast = 5 },
 231 };
 232
 233 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 234         .dot = { .min = 20000, .max = 115000 },
 235         .vco = { .min = 1750000, .max = 3500000 },
 236         .n = { .min = 1, .max = 3 },
 237         .m = { .min = 104, .max = 138 },
 238         .m1 = { .min = 17, .max = 23 },
 239         .m2 = { .min = 5, .max = 11 },
 240         .p = { .min = 28, .max = 112 },
 241         .p1 = { .min = 2, .max = 8 },
 242         .p2 = { .dot_limit = 0,
 243                 .p2_slow = 14, .p2_fast = 14
 244         },
 245 };
 246
 247 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 248         .dot = { .min = 80000, .max = 224000 },
 249         .vco = { .min = 1750000, .max = 3500000 },
 250         .n = { .min = 1, .max = 3 },
 251         .m = { .min = 104, .max = 138 },
 252         .m1 = { .min = 17, .max = 23 },
 253         .m2 = { .min = 5, .max = 11 },
 254         .p = { .min = 14, .max = 42 },
 255         .p1 = { .min = 2, .max = 6 },
 256         .p2 = { .dot_limit = 0,
 257                 .p2_slow = 7, .p2_fast = 7
 258         },
 259 };
 260
 261 static const intel_limit_t intel_limits_pineview_sdvo = {
 262         .dot = { .min = 20000, .max = 400000},
 263         .vco = { .min = 1700000, .max = 3500000 },
 264         /* Pineview's Ncounter is a ring counter */
 265         .n = { .min = 3, .max = 6 },
 266         .m = { .min = 2, .max = 256 },
 267         /* Pineview only has one combined m divider, which we treat as m2. */
 268         .m1 = { .min = 0, .max = 0 },
 269         .m2 = { .min = 0, .max = 254 },
 270         .p = { .min = 5, .max = 80 },
 271         .p1 = { .min = 1, .max = 8 },
 272         .p2 = { .dot_limit = 200000,
 273                 .p2_slow = 10, .p2_fast = 5 },
 274 };
 275
 276 static const intel_limit_t intel_limits_pineview_lvds = {
 277         .dot = { .min = 20000, .max = 400000 },
 278         .vco = { .min = 1700000, .max = 3500000 },
 279         .n = { .min = 3, .max = 6 },
 280         .m = { .min = 2, .max = 256 },
 281         .m1 = { .min = 0, .max = 0 },
 282         .m2 = { .min = 0, .max = 254 },
 283         .p = { .min = 7, .max = 112 },
 284         .p1 = { .min = 1, .max = 8 },
 285         .p2 = { .dot_limit = 112000,
 286                 .p2_slow = 14, .p2_fast = 14 },
 287 };
 288
 289 /* Ironlake / Sandybridge
 290  *
 291  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 292  * the range value for them is (actual_value - 2).
 293  */
 294 static const intel_limit_t intel_limits_ironlake_dac = {
 295         .dot = { .min = 25000, .max = 350000 },
 296         .vco = { .min = 1760000, .max = 3510000 },
 297         .n = { .min = 1, .max = 5 },
 298         .m = { .min = 79, .max = 127 },
 299         .m1 = { .min = 12, .max = 22 },
 300         .m2 = { .min = 5, .max = 9 },
 301         .p = { .min = 5, .max = 80 },
 302         .p1 = { .min = 1, .max = 8 },
 303         .p2 = { .dot_limit = 225000,
 304                 .p2_slow = 10, .p2_fast = 5 },
 305 };
 306
 307 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 308         .dot = { .min = 25000, .max = 350000 },
 309         .vco = { .min = 1760000, .max = 3510000 },
 310         .n = { .min = 1, .max = 3 },
 311         .m = { .min = 79, .max = 118 },
 312         .m1 = { .min = 12, .max = 22 },
 313         .m2 = { .min = 5, .max = 9 },
 314         .p = { .min = 28, .max = 112 },
 315         .p1 = { .min = 2, .max = 8 },
 316         .p2 = { .dot_limit = 225000,
 317                 .p2_slow = 14, .p2_fast = 14 },
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331 };
 332
 333 /* LVDS 100mhz refclk limits. */
 334 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 335         .dot = { .min = 25000, .max = 350000 },
 336         .vco = { .min = 1760000, .max = 3510000 },
 337         .n = { .min = 1, .max = 2 },
 338         .m = { .min = 79, .max = 126 },
 339         .m1 = { .min = 12, .max = 22 },
 340         .m2 = { .min = 5, .max = 9 },
 341         .p = { .min = 28, .max = 112 },
 342         .p1 = { .min = 2, .max = 8 },
 343         .p2 = { .dot_limit = 225000,
 344                 .p2_slow = 14, .p2_fast = 14 },
 345 };
 346
 347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 348         .dot = { .min = 25000, .max = 350000 },
 349         .vco = { .min = 1760000, .max = 3510000 },
 350         .n = { .min = 1, .max = 3 },
 351         .m = { .min = 79, .max = 126 },
 352         .m1 = { .min = 12, .max = 22 },
 353         .m2 = { .min = 5, .max = 9 },
 354         .p = { .min = 14, .max = 42 },
 355         .p1 = { .min = 2, .max = 6 },
 356         .p2 = { .dot_limit = 225000,
 357                 .p2_slow = 7, .p2_fast = 7 },
 358 };
 359
 360 static const intel_limit_t intel_limits_vlv = {
 361          /*
 362           * These are the data rate limits (measured in fast clocks)
 363           * since those are the strictest limits we have. The fast
 364           * clock and actual rate limits are more relaxed, so checking
 365           * them would make no difference.
 366           */
 367         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 368         .vco = { .min = 4000000, .max = 6000000 },
 369         .n = { .min = 1, .max = 7 },
 370         .m1 = { .min = 2, .max = 3 },
 371         .m2 = { .min = 11, .max = 156 },
 372         .p1 = { .min = 2, .max = 3 },
 373         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 374 };
 375
 376 static const intel_limit_t intel_limits_chv = {
 377         /*
 378          * These are the data rate limits (measured in fast clocks)
 379          * since those are the strictest limits we have.  The fast
 380          * clock and actual rate limits are more relaxed, so checking
 381          * them would make no difference.
 382          */
 383         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 384         .vco = { .min = 4860000, .max = 6700000 },
 385         .n = { .min = 1, .max = 1 },
 386         .m1 = { .min = 2, .max = 2 },
 387         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 388         .p1 = { .min = 2, .max = 4 },
 389         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 390 };
 391
 392 static void vlv_clock(int refclk, intel_clock_t *clock)
 393 {
 394         clock->m = clock->m1 * clock->m2;
 395         clock->p = clock->p1 * clock->p2;
 396         if (WARN_ON(clock->n == 0 || clock->p == 0))
 397                 return;
 398         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 399         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 400 }
 401
 402 /**
 403  * Returns whether any output on the specified pipe is of the specified type
 404  */
 405 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 406 {
 407         struct drm_device *dev = crtc->dev;
 408         struct intel_encoder *encoder;
 409
 410         for_each_encoder_on_crtc(dev, crtc, encoder)
 411                 if (encoder->type == type)
 412                         return true;
 413
 414         return false;
 415 }
 416
 417 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 418                                                 int refclk)
 419 {
 420         struct drm_device *dev = crtc->dev;
 421         const intel_limit_t *limit;
 422
 423         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 424                 if (intel_is_dual_link_lvds(dev)) {
 425                         if (refclk == 100000)
 426                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 427                         else
 428                                 limit = &intel_limits_ironlake_dual_lvds;
 429                 } else {
 430                         if (refclk == 100000)
 431                                 limit = &intel_limits_ironlake_single_lvds_100m;
 432                         else
 433                                 limit = &intel_limits_ironlake_single_lvds;
 434                 }
 435         } else
 436                 limit = &intel_limits_ironlake_dac;
 437
 438         return limit;
 439 }
 440
 441 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 442 {
 443         struct drm_device *dev = crtc->dev;
 444         const intel_limit_t *limit;
 445
 446         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 447                 if (intel_is_dual_link_lvds(dev))
 448                         limit = &intel_limits_g4x_dual_channel_lvds;
 449                 else
 450                         limit = &intel_limits_g4x_single_channel_lvds;
 451         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 452                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 453                 limit = &intel_limits_g4x_hdmi;
 454         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 455                 limit = &intel_limits_g4x_sdvo;
 456         } else /* The option is for other outputs */
 457                 limit = &intel_limits_i9xx_sdvo;
 458
 459         return limit;
 460 }
 461
 462 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 463 {
 464         struct drm_device *dev = crtc->dev;
 465         const intel_limit_t *limit;
 466
 467         if (HAS_PCH_SPLIT(dev))
 468                 limit = intel_ironlake_limit(crtc, refclk);
 469         else if (IS_G4X(dev)) {
 470                 limit = intel_g4x_limit(crtc);
 471         } else if (IS_PINEVIEW(dev)) {
 472                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 473                         limit = &intel_limits_pineview_lvds;
 474                 else
 475                         limit = &intel_limits_pineview_sdvo;
 476         } else if (IS_CHERRYVIEW(dev)) {
 477                 limit = &intel_limits_chv;
 478         } else if (IS_VALLEYVIEW(dev)) {
 479                 limit = &intel_limits_vlv;
 480         } else if (!IS_GEN2(dev)) {
 481                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 482                         limit = &intel_limits_i9xx_lvds;
 483                 else
 484                         limit = &intel_limits_i9xx_sdvo;
 485         } else {
 486                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 487                         limit = &intel_limits_i8xx_lvds;
 488                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 489                         limit = &intel_limits_i8xx_dvo;
 490                 else
 491                         limit = &intel_limits_i8xx_dac;
 492         }
 493         return limit;
 494 }
 495
 496 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 497 static void pineview_clock(int refclk, intel_clock_t *clock)
 498 {
 499         clock->m = clock->m2 + 2;
 500         clock->p = clock->p1 * clock->p2;
 501         if (WARN_ON(clock->n == 0 || clock->p == 0))
 502                 return;
 503         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 504         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 505 }
 506
 507 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 508 {
 509         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 510 }
 511
 512 static void i9xx_clock(int refclk, intel_clock_t *clock)
 513 {
 514         clock->m = i9xx_dpll_compute_m(clock);
 515         clock->p = clock->p1 * clock->p2;
 516         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 517                 return;
 518         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 519         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 520 }
 521
 522 static void chv_clock(int refclk, intel_clock_t *clock)
 523 {
 524         clock->m = clock->m1 * clock->m2;
 525         clock->p = clock->p1 * clock->p2;
 526         if (WARN_ON(clock->n == 0 || clock->p == 0))
 527                 return;
 528         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 529                         clock->n << 22);
 530         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 531 }
 532
 533 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 534 /**
 535  * Returns whether the given set of divisors are valid for a given refclk with
 536  * the given connectors.
 537  */
 538
 539 static bool intel_PLL_is_valid(struct drm_device *dev,
 540                                const intel_limit_t *limit,
 541                                const intel_clock_t *clock)
 542 {
 543         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 544                 INTELPllInvalid("n out of range\n");
 545         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 546                 INTELPllInvalid("p1 out of range\n");
 547         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 548                 INTELPllInvalid("m2 out of range\n");
 549         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 550                 INTELPllInvalid("m1 out of range\n");
 551
 552         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 553                 if (clock->m1 <= clock->m2)
 554                         INTELPllInvalid("m1 <= m2\n");
 555
 556         if (!IS_VALLEYVIEW(dev)) {
 557                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 558                         INTELPllInvalid("p out of range\n");
 559                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 560                         INTELPllInvalid("m out of range\n");
 561         }
 562
 563         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 564                 INTELPllInvalid("vco out of range\n");
 565         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 566          * connector, etc., rather than just a single range.
 567          */
 568         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 569                 INTELPllInvalid("dot out of range\n");
 570
 571         return true;
 572 }
 573
 574 static bool
 575 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 576                     int target, int refclk, intel_clock_t *match_clock,
 577                     intel_clock_t *best_clock)
 578 {
 579         struct drm_device *dev = crtc->dev;
 580         intel_clock_t clock;
 581         int err = target;
 582
 583         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 584                 /*
 585                  * For LVDS just rely on its current settings for dual-channel.
 586                  * We haven't figured out how to reliably set up different
 587                  * single/dual channel state, if we even can.
 588                  */
 589                 if (intel_is_dual_link_lvds(dev))
 590                         clock.p2 = limit->p2.p2_fast;
 591                 else
 592                         clock.p2 = limit->p2.p2_slow;
 593         } else {
 594                 if (target < limit->p2.dot_limit)
 595                         clock.p2 = limit->p2.p2_slow;
 596                 else
 597                         clock.p2 = limit->p2.p2_fast;
 598         }
 599
 600         memset(best_clock, 0, sizeof(*best_clock));
 601
 602         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 603              clock.m1++) {
 604                 for (clock.m2 = limit->m2.min;
 605                      clock.m2 <= limit->m2.max; clock.m2++) {
 606                         if (clock.m2 >= clock.m1)
 607                                 break;
 608                         for (clock.n = limit->n.min;
 609                              clock.n <= limit->n.max; clock.n++) {
 610                                 for (clock.p1 = limit->p1.min;
 611                                         clock.p1 <= limit->p1.max; clock.p1++) {
 612                                         int this_err;
 613
 614                                         i9xx_clock(refclk, &clock);
 615                                         if (!intel_PLL_is_valid(dev, limit,
 616                                                                 &clock))
 617                                                 continue;
 618                                         if (match_clock &&
 619                                             clock.p != match_clock->p)
 620                                                 continue;
 621
 622                                         this_err = abs(clock.dot - target);
 623                                         if (this_err < err) {
 624                                                 *best_clock = clock;
 625                                                 err = this_err;
 626                                         }
 627                                 }
 628                         }
 629                 }
 630         }
 631
 632         return (err != target);
 633 }
 634
 635 static bool
 636 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 637                    int target, int refclk, intel_clock_t *match_clock,
 638                    intel_clock_t *best_clock)
 639 {
 640         struct drm_device *dev = crtc->dev;
 641         intel_clock_t clock;
 642         int err = target;
 643
 644         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 645                 /*
 646                  * For LVDS just rely on its current settings for dual-channel.
 647                  * We haven't figured out how to reliably set up different
 648                  * single/dual channel state, if we even can.
 649                  */
 650                 if (intel_is_dual_link_lvds(dev))
 651                         clock.p2 = limit->p2.p2_fast;
 652                 else
 653                         clock.p2 = limit->p2.p2_slow;
 654         } else {
 655                 if (target < limit->p2.dot_limit)
 656                         clock.p2 = limit->p2.p2_slow;
 657                 else
 658                         clock.p2 = limit->p2.p2_fast;
 659         }
 660
 661         memset(best_clock, 0, sizeof(*best_clock));
 662
 663         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 664              clock.m1++) {
 665                 for (clock.m2 = limit->m2.min;
 666                      clock.m2 <= limit->m2.max; clock.m2++) {
 667                         for (clock.n = limit->n.min;
 668                              clock.n <= limit->n.max; clock.n++) {
 669                                 for (clock.p1 = limit->p1.min;
 670                                         clock.p1 <= limit->p1.max; clock.p1++) {
 671                                         int this_err;
 672
 673                                         pineview_clock(refclk, &clock);
 674                                         if (!intel_PLL_is_valid(dev, limit,
 675                                                                 &clock))
 676                                                 continue;
 677                                         if (match_clock &&
 678                                             clock.p != match_clock->p)
 679                                                 continue;
 680
 681                                         this_err = abs(clock.dot - target);
 682                                         if (this_err < err) {
 683                                                 *best_clock = clock;
 684                                                 err = this_err;
 685                                         }
 686                                 }
 687                         }
 688                 }
 689         }
 690
 691         return (err != target);
 692 }
 693
 694 static bool
 695 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 696                    int target, int refclk, intel_clock_t *match_clock,
 697                    intel_clock_t *best_clock)
 698 {
 699         struct drm_device *dev = crtc->dev;
 700         intel_clock_t clock;
 701         int max_n;
 702         bool found;
 703         /* approximately equals target * 0.00585 */
 704         int err_most = (target >> 8) + (target >> 9);
 705         found = false;
 706
 707         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 708                 if (intel_is_dual_link_lvds(dev))
 709                         clock.p2 = limit->p2.p2_fast;
 710                 else
 711                         clock.p2 = limit->p2.p2_slow;
 712         } else {
 713                 if (target < limit->p2.dot_limit)
 714                         clock.p2 = limit->p2.p2_slow;
 715                 else
 716                         clock.p2 = limit->p2.p2_fast;
 717         }
 718
 719         memset(best_clock, 0, sizeof(*best_clock));
 720         max_n = limit->n.max;
 721         /* based on hardware requirement, prefer smaller n to precision */
 722         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 723                 /* based on hardware requirement, prefere larger m1,m2 */
 724                 for (clock.m1 = limit->m1.max;
 725                      clock.m1 >= limit->m1.min; clock.m1--) {
 726                         for (clock.m2 = limit->m2.max;
 727                              clock.m2 >= limit->m2.min; clock.m2--) {
 728                                 for (clock.p1 = limit->p1.max;
 729                                      clock.p1 >= limit->p1.min; clock.p1--) {
 730                                         int this_err;
 731
 732                                         i9xx_clock(refclk, &clock);
 733                                         if (!intel_PLL_is_valid(dev, limit,
 734                                                                 &clock))
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err_most) {
 739                                                 *best_clock = clock;
 740                                                 err_most = this_err;
 741                                                 max_n = clock.n;
 742                                                 found = true;
 743                                         }
 744                                 }
 745                         }
 746                 }
 747         }
 748         return found;
 749 }
 750
 751 static bool
 752 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 753                    int target, int refclk, intel_clock_t *match_clock,
 754                    intel_clock_t *best_clock)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         intel_clock_t clock;
 758         unsigned int bestppm = 1000000;
 759         /* min update 19.2 MHz */
 760         int max_n = min(limit->n.max, refclk / 19200);
 761         bool found = false;
 762
 763         target *= 5; /* fast clock */
 764
 765         memset(best_clock, 0, sizeof(*best_clock));
 766
 767         /* based on hardware requirement, prefer smaller n to precision */
 768         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 769                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 770                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 771                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 772                                 clock.p = clock.p1 * clock.p2;
 773                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 774                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 775                                         unsigned int ppm, diff;
 776
 777                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 778                                                                      refclk * clock.m1);
 779
 780                                         vlv_clock(refclk, &clock);
 781
 782                                         if (!intel_PLL_is_valid(dev, limit,
 783                                                                 &clock))
 784                                                 continue;
 785
 786                                         diff = abs(clock.dot - target);
 787                                         ppm = div_u64(1000000ULL * diff, target);
 788
 789                                         if (ppm < 100 && clock.p > best_clock->p) {
 790                                                 bestppm = 0;
 791                                                 *best_clock = clock;
 792                                                 found = true;
 793                                         }
 794
 795                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 796                                                 bestppm = ppm;
 797                                                 *best_clock = clock;
 798                                                 found = true;
 799                                         }
 800                                 }
 801                         }
 802                 }
 803         }
 804
 805         return found;
 806 }
 807
 808 static bool
 809 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 810                    int target, int refclk, intel_clock_t *match_clock,
 811                    intel_clock_t *best_clock)
 812 {
 813         struct drm_device *dev = crtc->dev;
 814         intel_clock_t clock;
 815         uint64_t m2;
 816         int found = false;
 817
 818         memset(best_clock, 0, sizeof(*best_clock));
 819
 820         /*
 821          * Based on hardware doc, the n always set to 1, and m1 always
 822          * set to 2.  If requires to support 200Mhz refclk, we need to
 823          * revisit this because n may not 1 anymore.
 824          */
 825         clock.n = 1, clock.m1 = 2;
 826         target *= 5;    /* fast clock */
 827
 828         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 829                 for (clock.p2 = limit->p2.p2_fast;
 830                                 clock.p2 >= limit->p2.p2_slow;
 831                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 832
 833                         clock.p = clock.p1 * clock.p2;
 834
 835                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 836                                         clock.n) << 22, refclk * clock.m1);
 837
 838                         if (m2 > INT_MAX/clock.m1)
 839                                 continue;
 840
 841                         clock.m2 = m2;
 842
 843                         chv_clock(refclk, &clock);
 844
 845                         if (!intel_PLL_is_valid(dev, limit, &clock))
 846                                 continue;
 847
 848                         /* based on hardware requirement, prefer bigger p
 849                          */
 850                         if (clock.p > best_clock->p) {
 851                                 *best_clock = clock;
 852                                 found = true;
 853                         }
 854                 }
 855         }
 856
 857         return found;
 858 }
 859
 860 bool intel_crtc_active(struct drm_crtc *crtc)
 861 {
 862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 863
 864         /* Be paranoid as we can arrive here with only partial
 865          * state retrieved from the hardware during setup.
 866          *
 867          * We can ditch the adjusted_mode.crtc_clock check as soon
 868          * as Haswell has gained clock readout/fastboot support.
 869          *
 870          * We can ditch the crtc->primary->fb check as soon as we can
 871          * properly reconstruct framebuffers.
 872          */
 873         return intel_crtc->active && crtc->primary->fb &&
 874                 intel_crtc->config.adjusted_mode.crtc_clock;
 875 }
 876
 877 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 878                                              enum pipe pipe)
 879 {
 880         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 882
 883         return intel_crtc->config.cpu_transcoder;
 884 }
 885
 886 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 887 {
 888         struct drm_i915_private *dev_priv = dev->dev_private;
 889         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 890
 891         frame = I915_READ(frame_reg);
 892
 893         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 894                 WARN(1, "vblank wait timed out\n");
 895 }
 896
 897 /**
 898  * intel_wait_for_vblank - wait for vblank on a given pipe
 899  * @dev: drm device
 900  * @pipe: pipe to wait for
 901  *
 902  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 903  * mode setting code.
 904  */
 905 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 906 {
 907         struct drm_i915_private *dev_priv = dev->dev_private;
 908         int pipestat_reg = PIPESTAT(pipe);
 909
 910         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 911                 g4x_wait_for_vblank(dev, pipe);
 912                 return;
 913         }
 914
 915         /* Clear existing vblank status. Note this will clear any other
 916          * sticky status fields as well.
 917          *
 918          * This races with i915_driver_irq_handler() with the result
 919          * that either function could miss a vblank event.  Here it is not
 920          * fatal, as we will either wait upon the next vblank interrupt or
 921          * timeout.  Generally speaking intel_wait_for_vblank() is only
 922          * called during modeset at which time the GPU should be idle and
 923          * should *not* be performing page flips and thus not waiting on
 924          * vblanks...
 925          * Currently, the result of us stealing a vblank from the irq
 926          * handler is that a single frame will be skipped during swapbuffers.
 927          */
 928         I915_WRITE(pipestat_reg,
 929                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 930
 931         /* Wait for vblank interrupt bit to set */
 932         if (wait_for(I915_READ(pipestat_reg) &
 933                      PIPE_VBLANK_INTERRUPT_STATUS,
 934                      50))
 935                 DRM_DEBUG_KMS("vblank wait timed out\n");
 936 }
 937
 938 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 939 {
 940         struct drm_i915_private *dev_priv = dev->dev_private;
 941         u32 reg = PIPEDSL(pipe);
 942         u32 line1, line2;
 943         u32 line_mask;
 944
 945         if (IS_GEN2(dev))
 946                 line_mask = DSL_LINEMASK_GEN2;
 947         else
 948                 line_mask = DSL_LINEMASK_GEN3;
 949
 950         line1 = I915_READ(reg) & line_mask;
 951         mdelay(5);
 952         line2 = I915_READ(reg) & line_mask;
 953
 954         return line1 == line2;
 955 }
 956
 957 /*
 958  * intel_wait_for_pipe_off - wait for pipe to turn off
 959  * @dev: drm device
 960  * @pipe: pipe to wait for
 961  *
 962  * After disabling a pipe, we can't wait for vblank in the usual way,
 963  * spinning on the vblank interrupt status bit, since we won't actually
 964  * see an interrupt when the pipe is disabled.
 965  *
 966  * On Gen4 and above:
 967  *   wait for the pipe register state bit to turn off
 968  *
 969  * Otherwise:
 970  *   wait for the display line value to settle (it usually
 971  *   ends up stopping at the start of the next frame).
 972  *
 973  */
 974 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 975 {
 976         struct drm_i915_private *dev_priv = dev->dev_private;
 977         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 978                                                                       pipe);
 979
 980         if (INTEL_INFO(dev)->gen >= 4) {
 981                 int reg = PIPECONF(cpu_transcoder);
 982
 983                 /* Wait for the Pipe State to go off */
 984                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 985                              100))
 986                         WARN(1, "pipe_off wait timed out\n");
 987         } else {
 988                 /* Wait for the display line to settle */
 989                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 990                         WARN(1, "pipe_off wait timed out\n");
 991         }
 992 }
 993
 994 /*
 995  * ibx_digital_port_connected - is the specified port connected?
 996  * @dev_priv: i915 private structure
 997  * @port: the port to test
 998  *
 999  * Returns true if @port is connected, false otherwise.
1000  */
1001 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1002                                 struct intel_digital_port *port)
1003 {
1004         u32 bit;
1005
1006         if (HAS_PCH_IBX(dev_priv->dev)) {
1007                 switch (port->port) {
1008                 case PORT_B:
1009                         bit = SDE_PORTB_HOTPLUG;
1010                         break;
1011                 case PORT_C:
1012                         bit = SDE_PORTC_HOTPLUG;
1013                         break;
1014                 case PORT_D:
1015                         bit = SDE_PORTD_HOTPLUG;
1016                         break;
1017                 default:
1018                         return true;
1019                 }
1020         } else {
1021                 switch (port->port) {
1022                 case PORT_B:
1023                         bit = SDE_PORTB_HOTPLUG_CPT;
1024                         break;
1025                 case PORT_C:
1026                         bit = SDE_PORTC_HOTPLUG_CPT;
1027                         break;
1028                 case PORT_D:
1029                         bit = SDE_PORTD_HOTPLUG_CPT;
1030                         break;
1031                 default:
1032                         return true;
1033                 }
1034         }
1035
1036         return I915_READ(SDEISR) & bit;
1037 }
1038
1039 static const char *state_string(bool enabled)
1040 {
1041         return enabled ? "on" : "off";
1042 }
1043
1044 /* Only for pre-ILK configs */
1045 void assert_pll(struct drm_i915_private *dev_priv,
1046                 enum pipe pipe, bool state)
1047 {
1048         int reg;
1049         u32 val;
1050         bool cur_state;
1051
1052         reg = DPLL(pipe);
1053         val = I915_READ(reg);
1054         cur_state = !!(val & DPLL_VCO_ENABLE);
1055         WARN(cur_state != state,
1056              "PLL state assertion failure (expected %s, current %s)\n",
1057              state_string(state), state_string(cur_state));
1058 }
1059
1060 /* XXX: the dsi pll is shared between MIPI DSI ports */
1061 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1062 {
1063         u32 val;
1064         bool cur_state;
1065
1066         mutex_lock(&dev_priv->dpio_lock);
1067         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1068         mutex_unlock(&dev_priv->dpio_lock);
1069
1070         cur_state = val & DSI_PLL_VCO_EN;
1071         WARN(cur_state != state,
1072              "DSI PLL state assertion failure (expected %s, current %s)\n",
1073              state_string(state), state_string(cur_state));
1074 }
1075 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1076 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1077
1078 struct intel_shared_dpll *
1079 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1080 {
1081         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1082
1083         if (crtc->config.shared_dpll < 0)
1084                 return NULL;
1085
1086         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1087 }
1088
1089 /* For ILK+ */
1090 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1091                         struct intel_shared_dpll *pll,
1092                         bool state)
1093 {
1094         bool cur_state;
1095         struct intel_dpll_hw_state hw_state;
1096
1097         if (HAS_PCH_LPT(dev_priv->dev)) {
1098                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1099                 return;
1100         }
1101
1102         if (WARN (!pll,
1103                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1104                 return;
1105
1106         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1107         WARN(cur_state != state,
1108              "%s assertion failure (expected %s, current %s)\n",
1109              pll->name, state_string(state), state_string(cur_state));
1110 }
1111
1112 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1113                           enum pipe pipe, bool state)
1114 {
1115         int reg;
1116         u32 val;
1117         bool cur_state;
1118         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119                                                                       pipe);
1120
1121         if (HAS_DDI(dev_priv->dev)) {
1122                 /* DDI does not have a specific FDI_TX register */
1123                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1124                 val = I915_READ(reg);
1125                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1126         } else {
1127                 reg = FDI_TX_CTL(pipe);
1128                 val = I915_READ(reg);
1129                 cur_state = !!(val & FDI_TX_ENABLE);
1130         }
1131         WARN(cur_state != state,
1132              "FDI TX state assertion failure (expected %s, current %s)\n",
1133              state_string(state), state_string(cur_state));
1134 }
1135 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1136 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1137
1138 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1139                           enum pipe pipe, bool state)
1140 {
1141         int reg;
1142         u32 val;
1143         bool cur_state;
1144
1145         reg = FDI_RX_CTL(pipe);
1146         val = I915_READ(reg);
1147         cur_state = !!(val & FDI_RX_ENABLE);
1148         WARN(cur_state != state,
1149              "FDI RX state assertion failure (expected %s, current %s)\n",
1150              state_string(state), state_string(cur_state));
1151 }
1152 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1153 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1154
1155 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1156                                       enum pipe pipe)
1157 {
1158         int reg;
1159         u32 val;
1160
1161         /* ILK FDI PLL is always enabled */
1162         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1163                 return;
1164
1165         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1166         if (HAS_DDI(dev_priv->dev))
1167                 return;
1168
1169         reg = FDI_TX_CTL(pipe);
1170         val = I915_READ(reg);
1171         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1172 }
1173
1174 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1175                        enum pipe pipe, bool state)
1176 {
1177         int reg;
1178         u32 val;
1179         bool cur_state;
1180
1181         reg = FDI_RX_CTL(pipe);
1182         val = I915_READ(reg);
1183         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1184         WARN(cur_state != state,
1185              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186              state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1190                                   enum pipe pipe)
1191 {
1192         int pp_reg, lvds_reg;
1193         u32 val;
1194         enum pipe panel_pipe = PIPE_A;
1195         bool locked = true;
1196
1197         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1198                 pp_reg = PCH_PP_CONTROL;
1199                 lvds_reg = PCH_LVDS;
1200         } else {
1201                 pp_reg = PP_CONTROL;
1202                 lvds_reg = LVDS;
1203         }
1204
1205         val = I915_READ(pp_reg);
1206         if (!(val & PANEL_POWER_ON) ||
1207             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1208                 locked = false;
1209
1210         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1211                 panel_pipe = PIPE_B;
1212
1213         WARN(panel_pipe == pipe && locked,
1214              "panel assertion failure, pipe %c regs locked\n",
1215              pipe_name(pipe));
1216 }
1217
1218 static void assert_cursor(struct drm_i915_private *dev_priv,
1219                           enum pipe pipe, bool state)
1220 {
1221         struct drm_device *dev = dev_priv->dev;
1222         bool cur_state;
1223
1224         if (IS_845G(dev) || IS_I865G(dev))
1225                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1226         else
1227                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1228
1229         WARN(cur_state != state,
1230              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1231              pipe_name(pipe), state_string(state), state_string(cur_state));
1232 }
1233 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1234 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1235
1236 void assert_pipe(struct drm_i915_private *dev_priv,
1237                  enum pipe pipe, bool state)
1238 {
1239         int reg;
1240         u32 val;
1241         bool cur_state;
1242         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1243                                                                       pipe);
1244
1245         /* if we need the pipe A quirk it must be always on */
1246         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1247                 state = true;
1248
1249         if (!intel_display_power_enabled(dev_priv,
1250                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1251                 cur_state = false;
1252         } else {
1253                 reg = PIPECONF(cpu_transcoder);
1254                 val = I915_READ(reg);
1255                 cur_state = !!(val & PIPECONF_ENABLE);
1256         }
1257
1258         WARN(cur_state != state,
1259              "pipe %c assertion failure (expected %s, current %s)\n",
1260              pipe_name(pipe), state_string(state), state_string(cur_state));
1261 }
1262
1263 static void assert_plane(struct drm_i915_private *dev_priv,
1264                          enum plane plane, bool state)
1265 {
1266         int reg;
1267         u32 val;
1268         bool cur_state;
1269
1270         reg = DSPCNTR(plane);
1271         val = I915_READ(reg);
1272         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1273         WARN(cur_state != state,
1274              "plane %c assertion failure (expected %s, current %s)\n",
1275              plane_name(plane), state_string(state), state_string(cur_state));
1276 }
1277
1278 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1279 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1280
1281 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1282                                    enum pipe pipe)
1283 {
1284         struct drm_device *dev = dev_priv->dev;
1285         int reg, i;
1286         u32 val;
1287         int cur_pipe;
1288
1289         /* Primary planes are fixed to pipes on gen4+ */
1290         if (INTEL_INFO(dev)->gen >= 4) {
1291                 reg = DSPCNTR(pipe);
1292                 val = I915_READ(reg);
1293                 WARN(val & DISPLAY_PLANE_ENABLE,
1294                      "plane %c assertion failure, should be disabled but not\n",
1295                      plane_name(pipe));
1296                 return;
1297         }
1298
1299         /* Need to check both planes against the pipe */
1300         for_each_pipe(i) {
1301                 reg = DSPCNTR(i);
1302                 val = I915_READ(reg);
1303                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1304                         DISPPLANE_SEL_PIPE_SHIFT;
1305                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1306                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1307                      plane_name(i), pipe_name(pipe));
1308         }
1309 }
1310
1311 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1312                                     enum pipe pipe)
1313 {
1314         struct drm_device *dev = dev_priv->dev;
1315         int reg, sprite;
1316         u32 val;
1317
1318         if (IS_VALLEYVIEW(dev)) {
1319                 for_each_sprite(pipe, sprite) {
1320                         reg = SPCNTR(pipe, sprite);
1321                         val = I915_READ(reg);
1322                         WARN(val & SP_ENABLE,
1323                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1324                              sprite_name(pipe, sprite), pipe_name(pipe));
1325                 }
1326         } else if (INTEL_INFO(dev)->gen >= 7) {
1327                 reg = SPRCTL(pipe);
1328                 val = I915_READ(reg);
1329                 WARN(val & SPRITE_ENABLE,
1330                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1331                      plane_name(pipe), pipe_name(pipe));
1332         } else if (INTEL_INFO(dev)->gen >= 5) {
1333                 reg = DVSCNTR(pipe);
1334                 val = I915_READ(reg);
1335                 WARN(val & DVS_ENABLE,
1336                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337                      plane_name(pipe), pipe_name(pipe));
1338         }
1339 }
1340
1341 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1342 {
1343         u32 val;
1344         bool enabled;
1345
1346         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1347
1348         val = I915_READ(PCH_DREF_CONTROL);
1349         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1350                             DREF_SUPERSPREAD_SOURCE_MASK));
1351         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1352 }
1353
1354 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355                                            enum pipe pipe)
1356 {
1357         int reg;
1358         u32 val;
1359         bool enabled;
1360
1361         reg = PCH_TRANSCONF(pipe);
1362         val = I915_READ(reg);
1363         enabled = !!(val & TRANS_ENABLE);
1364         WARN(enabled,
1365              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1366              pipe_name(pipe));
1367 }
1368
1369 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1370                             enum pipe pipe, u32 port_sel, u32 val)
1371 {
1372         if ((val & DP_PORT_EN) == 0)
1373                 return false;
1374
1375         if (HAS_PCH_CPT(dev_priv->dev)) {
1376                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1377                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1378                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1379                         return false;
1380         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1381                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1382                         return false;
1383         } else {
1384                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1385                         return false;
1386         }
1387         return true;
1388 }
1389
1390 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1391                               enum pipe pipe, u32 val)
1392 {
1393         if ((val & SDVO_ENABLE) == 0)
1394                 return false;
1395
1396         if (HAS_PCH_CPT(dev_priv->dev)) {
1397                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1398                         return false;
1399         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1400                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1401                         return false;
1402         } else {
1403                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1404                         return false;
1405         }
1406         return true;
1407 }
1408
1409 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1410                               enum pipe pipe, u32 val)
1411 {
1412         if ((val & LVDS_PORT_EN) == 0)
1413                 return false;
1414
1415         if (HAS_PCH_CPT(dev_priv->dev)) {
1416                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1417                         return false;
1418         } else {
1419                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1420                         return false;
1421         }
1422         return true;
1423 }
1424
1425 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1426                               enum pipe pipe, u32 val)
1427 {
1428         if ((val & ADPA_DAC_ENABLE) == 0)
1429                 return false;
1430         if (HAS_PCH_CPT(dev_priv->dev)) {
1431                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1432                         return false;
1433         } else {
1434                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1435                         return false;
1436         }
1437         return true;
1438 }
1439
1440 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1441                                    enum pipe pipe, int reg, u32 port_sel)
1442 {
1443         u32 val = I915_READ(reg);
1444         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1445              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1446              reg, pipe_name(pipe));
1447
1448         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1449              && (val & DP_PIPEB_SELECT),
1450              "IBX PCH dp port still using transcoder B\n");
1451 }
1452
1453 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1454                                      enum pipe pipe, int reg)
1455 {
1456         u32 val = I915_READ(reg);
1457         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1458              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1459              reg, pipe_name(pipe));
1460
1461         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1462              && (val & SDVO_PIPE_B_SELECT),
1463              "IBX PCH hdmi port still using transcoder B\n");
1464 }
1465
1466 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1467                                       enum pipe pipe)
1468 {
1469         int reg;
1470         u32 val;
1471
1472         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1473         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1475
1476         reg = PCH_ADPA;
1477         val = I915_READ(reg);
1478         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1479              "PCH VGA enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         reg = PCH_LVDS;
1483         val = I915_READ(reg);
1484         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486              pipe_name(pipe));
1487
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void intel_init_dpio(struct drm_device *dev)
1494 {
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496
1497         if (!IS_VALLEYVIEW(dev))
1498                 return;
1499
1500         /*
1501          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1502          * CHV x1 PHY (DP/HDMI D)
1503          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1504          */
1505         if (IS_CHERRYVIEW(dev)) {
1506                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1507                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1508         } else {
1509                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1510         }
1511 }
1512
1513 static void intel_reset_dpio(struct drm_device *dev)
1514 {
1515         struct drm_i915_private *dev_priv = dev->dev_private;
1516
1517         if (!IS_VALLEYVIEW(dev))
1518                 return;
1519
1520         if (IS_CHERRYVIEW(dev)) {
1521                 enum dpio_phy phy;
1522                 u32 val;
1523
1524                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1525                         /* Poll for phypwrgood signal */
1526                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1527                                                 PHY_POWERGOOD(phy), 1))
1528                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1529
1530                         /*
1531                          * Deassert common lane reset for PHY.
1532                          *
1533                          * This should only be done on init and resume from S3
1534                          * with both PLLs disabled, or we risk losing DPIO and
1535                          * PLL synchronization.
1536                          */
1537                         val = I915_READ(DISPLAY_PHY_CONTROL);
1538                         I915_WRITE(DISPLAY_PHY_CONTROL,
1539                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1540                 }
1541
1542         } else {
1543                 /*
1544                  * If DPIO has already been reset, e.g. by BIOS, just skip all
1545                  * this.
1546                  */
1547                 if (I915_READ(DPIO_CTL) & DPIO_CMNRST)
1548                         return;
1549
1550                 /*
1551                  * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1552                  * Need to assert and de-assert PHY SB reset by gating the
1553                  * common lane power, then un-gating it.
1554                  * Simply ungating isn't enough to reset the PHY enough to get
1555                  * ports and lanes running.
1556                  */
1557                 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1558                                      false);
1559                 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1560                                      true);
1561         }
1562 }
1563
1564 static void vlv_enable_pll(struct intel_crtc *crtc)
1565 {
1566         struct drm_device *dev = crtc->base.dev;
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         int reg = DPLL(crtc->pipe);
1569         u32 dpll = crtc->config.dpll_hw_state.dpll;
1570
1571         assert_pipe_disabled(dev_priv, crtc->pipe);
1572
1573         /* No really, not for ILK+ */
1574         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1575
1576         /* PLL is protected by panel, make sure we can write it */
1577         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1578                 assert_panel_unlocked(dev_priv, crtc->pipe);
1579
1580         I915_WRITE(reg, dpll);
1581         POSTING_READ(reg);
1582         udelay(150);
1583
1584         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1585                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1586
1587         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1588         POSTING_READ(DPLL_MD(crtc->pipe));
1589
1590         /* We do this three times for luck */
1591         I915_WRITE(reg, dpll);
1592         POSTING_READ(reg);
1593         udelay(150); /* wait for warmup */
1594         I915_WRITE(reg, dpll);
1595         POSTING_READ(reg);
1596         udelay(150); /* wait for warmup */
1597         I915_WRITE(reg, dpll);
1598         POSTING_READ(reg);
1599         udelay(150); /* wait for warmup */
1600 }
1601
1602 static void chv_enable_pll(struct intel_crtc *crtc)
1603 {
1604         struct drm_device *dev = crtc->base.dev;
1605         struct drm_i915_private *dev_priv = dev->dev_private;
1606         int pipe = crtc->pipe;
1607         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1608         u32 tmp;
1609
1610         assert_pipe_disabled(dev_priv, crtc->pipe);
1611
1612         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1613
1614         mutex_lock(&dev_priv->dpio_lock);
1615
1616         /* Enable back the 10bit clock to display controller */
1617         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1618         tmp |= DPIO_DCLKP_EN;
1619         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1620
1621         /*
1622          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1623          */
1624         udelay(1);
1625
1626         /* Enable PLL */
1627         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1628
1629         /* Check PLL is locked */
1630         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1631                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1632
1633         /* not sure when this should be written */
1634         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1635         POSTING_READ(DPLL_MD(pipe));
1636
1637         mutex_unlock(&dev_priv->dpio_lock);
1638 }
1639
1640 static void i9xx_enable_pll(struct intel_crtc *crtc)
1641 {
1642         struct drm_device *dev = crtc->base.dev;
1643         struct drm_i915_private *dev_priv = dev->dev_private;
1644         int reg = DPLL(crtc->pipe);
1645         u32 dpll = crtc->config.dpll_hw_state.dpll;
1646
1647         assert_pipe_disabled(dev_priv, crtc->pipe);
1648
1649         /* No really, not for ILK+ */
1650         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1651
1652         /* PLL is protected by panel, make sure we can write it */
1653         if (IS_MOBILE(dev) && !IS_I830(dev))
1654                 assert_panel_unlocked(dev_priv, crtc->pipe);
1655
1656         I915_WRITE(reg, dpll);
1657
1658         /* Wait for the clocks to stabilize. */
1659         POSTING_READ(reg);
1660         udelay(150);
1661
1662         if (INTEL_INFO(dev)->gen >= 4) {
1663                 I915_WRITE(DPLL_MD(crtc->pipe),
1664                            crtc->config.dpll_hw_state.dpll_md);
1665         } else {
1666                 /* The pixel multiplier can only be updated once the
1667                  * DPLL is enabled and the clocks are stable.
1668                  *
1669                  * So write it again.
1670                  */
1671                 I915_WRITE(reg, dpll);
1672         }
1673
1674         /* We do this three times for luck */
1675         I915_WRITE(reg, dpll);
1676         POSTING_READ(reg);
1677         udelay(150); /* wait for warmup */
1678         I915_WRITE(reg, dpll);
1679         POSTING_READ(reg);
1680         udelay(150); /* wait for warmup */
1681         I915_WRITE(reg, dpll);
1682         POSTING_READ(reg);
1683         udelay(150); /* wait for warmup */
1684 }
1685
1686 /**
1687  * i9xx_disable_pll - disable a PLL
1688  * @dev_priv: i915 private structure
1689  * @pipe: pipe PLL to disable
1690  *
1691  * Disable the PLL for @pipe, making sure the pipe is off first.
1692  *
1693  * Note!  This is for pre-ILK only.
1694  */
1695 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1696 {
1697         /* Don't disable pipe A or pipe A PLLs if needed */
1698         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1699                 return;
1700
1701         /* Make sure the pipe isn't still relying on us */
1702         assert_pipe_disabled(dev_priv, pipe);
1703
1704         I915_WRITE(DPLL(pipe), 0);
1705         POSTING_READ(DPLL(pipe));
1706 }
1707
1708 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1709 {
1710         u32 val = 0;
1711
1712         /* Make sure the pipe isn't still relying on us */
1713         assert_pipe_disabled(dev_priv, pipe);
1714
1715         /*
1716          * Leave integrated clock source and reference clock enabled for pipe B.
1717          * The latter is needed for VGA hotplug / manual detection.
1718          */
1719         if (pipe == PIPE_B)
1720                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723
1724 }
1725
1726 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1727 {
1728         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1729         u32 val;
1730
1731         /* Make sure the pipe isn't still relying on us */
1732         assert_pipe_disabled(dev_priv, pipe);
1733
1734         /* Set PLL en = 0 */
1735         val = DPLL_SSC_REF_CLOCK_CHV;
1736         if (pipe != PIPE_A)
1737                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1738         I915_WRITE(DPLL(pipe), val);
1739         POSTING_READ(DPLL(pipe));
1740
1741         mutex_lock(&dev_priv->dpio_lock);
1742
1743         /* Disable 10bit clock to display controller */
1744         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1745         val &= ~DPIO_DCLKP_EN;
1746         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1747
1748         /* disable left/right clock distribution */
1749         if (pipe != PIPE_B) {
1750                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1751                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1752                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1753         } else {
1754                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1755                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1756                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1757         }
1758
1759         mutex_unlock(&dev_priv->dpio_lock);
1760 }
1761
1762 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1763                 struct intel_digital_port *dport)
1764 {
1765         u32 port_mask;
1766         int dpll_reg;
1767
1768         switch (dport->port) {
1769         case PORT_B:
1770                 port_mask = DPLL_PORTB_READY_MASK;
1771                 dpll_reg = DPLL(0);
1772                 break;
1773         case PORT_C:
1774                 port_mask = DPLL_PORTC_READY_MASK;
1775                 dpll_reg = DPLL(0);
1776                 break;
1777         case PORT_D:
1778                 port_mask = DPLL_PORTD_READY_MASK;
1779                 dpll_reg = DPIO_PHY_STATUS;
1780                 break;
1781         default:
1782                 BUG();
1783         }
1784
1785         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1786                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1787                      port_name(dport->port), I915_READ(dpll_reg));
1788 }
1789
1790 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1791 {
1792         struct drm_device *dev = crtc->base.dev;
1793         struct drm_i915_private *dev_priv = dev->dev_private;
1794         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1795
1796         if (WARN_ON(pll == NULL))
1797                 return;
1798
1799         WARN_ON(!pll->refcount);
1800         if (pll->active == 0) {
1801                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1802                 WARN_ON(pll->on);
1803                 assert_shared_dpll_disabled(dev_priv, pll);
1804
1805                 pll->mode_set(dev_priv, pll);
1806         }
1807 }
1808
1809 /**
1810  * intel_enable_shared_dpll - enable PCH PLL
1811  * @dev_priv: i915 private structure
1812  * @pipe: pipe PLL to enable
1813  *
1814  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1815  * drives the transcoder clock.
1816  */
1817 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1818 {
1819         struct drm_device *dev = crtc->base.dev;
1820         struct drm_i915_private *dev_priv = dev->dev_private;
1821         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1822
1823         if (WARN_ON(pll == NULL))
1824                 return;
1825
1826         if (WARN_ON(pll->refcount == 0))
1827                 return;
1828
1829         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1830                       pll->name, pll->active, pll->on,
1831                       crtc->base.base.id);
1832
1833         if (pll->active++) {
1834                 WARN_ON(!pll->on);
1835                 assert_shared_dpll_enabled(dev_priv, pll);
1836                 return;
1837         }
1838         WARN_ON(pll->on);
1839
1840         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1841         pll->enable(dev_priv, pll);
1842         pll->on = true;
1843 }
1844
1845 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1846 {
1847         struct drm_device *dev = crtc->base.dev;
1848         struct drm_i915_private *dev_priv = dev->dev_private;
1849         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1850
1851         /* PCH only available on ILK+ */
1852         BUG_ON(INTEL_INFO(dev)->gen < 5);
1853         if (WARN_ON(pll == NULL))
1854                return;
1855
1856         if (WARN_ON(pll->refcount == 0))
1857                 return;
1858
1859         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1860                       pll->name, pll->active, pll->on,
1861                       crtc->base.base.id);
1862
1863         if (WARN_ON(pll->active == 0)) {
1864                 assert_shared_dpll_disabled(dev_priv, pll);
1865                 return;
1866         }
1867
1868         assert_shared_dpll_enabled(dev_priv, pll);
1869         WARN_ON(!pll->on);
1870         if (--pll->active)
1871                 return;
1872
1873         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1874         pll->disable(dev_priv, pll);
1875         pll->on = false;
1876 }
1877
1878 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1879                                            enum pipe pipe)
1880 {
1881         struct drm_device *dev = dev_priv->dev;
1882         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1884         uint32_t reg, val, pipeconf_val;
1885
1886         /* PCH only available on ILK+ */
1887         BUG_ON(INTEL_INFO(dev)->gen < 5);
1888
1889         /* Make sure PCH DPLL is enabled */
1890         assert_shared_dpll_enabled(dev_priv,
1891                                    intel_crtc_to_shared_dpll(intel_crtc));
1892
1893         /* FDI must be feeding us bits for PCH ports */
1894         assert_fdi_tx_enabled(dev_priv, pipe);
1895         assert_fdi_rx_enabled(dev_priv, pipe);
1896
1897         if (HAS_PCH_CPT(dev)) {
1898                 /* Workaround: Set the timing override bit before enabling the
1899                  * pch transcoder. */
1900                 reg = TRANS_CHICKEN2(pipe);
1901                 val = I915_READ(reg);
1902                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1903                 I915_WRITE(reg, val);
1904         }
1905
1906         reg = PCH_TRANSCONF(pipe);
1907         val = I915_READ(reg);
1908         pipeconf_val = I915_READ(PIPECONF(pipe));
1909
1910         if (HAS_PCH_IBX(dev_priv->dev)) {
1911                 /*
1912                  * make the BPC in transcoder be consistent with
1913                  * that in pipeconf reg.
1914                  */
1915                 val &= ~PIPECONF_BPC_MASK;
1916                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1917         }
1918
1919         val &= ~TRANS_INTERLACE_MASK;
1920         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1921                 if (HAS_PCH_IBX(dev_priv->dev) &&
1922                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1923                         val |= TRANS_LEGACY_INTERLACED_ILK;
1924                 else
1925                         val |= TRANS_INTERLACED;
1926         else
1927                 val |= TRANS_PROGRESSIVE;
1928
1929         I915_WRITE(reg, val | TRANS_ENABLE);
1930         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1931                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1932 }
1933
1934 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1935                                       enum transcoder cpu_transcoder)
1936 {
1937         u32 val, pipeconf_val;
1938
1939         /* PCH only available on ILK+ */
1940         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1941
1942         /* FDI must be feeding us bits for PCH ports */
1943         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1944         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1945
1946         /* Workaround: set timing override bit. */
1947         val = I915_READ(_TRANSA_CHICKEN2);
1948         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1949         I915_WRITE(_TRANSA_CHICKEN2, val);
1950
1951         val = TRANS_ENABLE;
1952         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1953
1954         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1955             PIPECONF_INTERLACED_ILK)
1956                 val |= TRANS_INTERLACED;
1957         else
1958                 val |= TRANS_PROGRESSIVE;
1959
1960         I915_WRITE(LPT_TRANSCONF, val);
1961         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1962                 DRM_ERROR("Failed to enable PCH transcoder\n");
1963 }
1964
1965 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1966                                             enum pipe pipe)
1967 {
1968         struct drm_device *dev = dev_priv->dev;
1969         uint32_t reg, val;
1970
1971         /* FDI relies on the transcoder */
1972         assert_fdi_tx_disabled(dev_priv, pipe);
1973         assert_fdi_rx_disabled(dev_priv, pipe);
1974
1975         /* Ports must be off as well */
1976         assert_pch_ports_disabled(dev_priv, pipe);
1977
1978         reg = PCH_TRANSCONF(pipe);
1979         val = I915_READ(reg);
1980         val &= ~TRANS_ENABLE;
1981         I915_WRITE(reg, val);
1982         /* wait for PCH transcoder off, transcoder state */
1983         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1984                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1985
1986         if (!HAS_PCH_IBX(dev)) {
1987                 /* Workaround: Clear the timing override chicken bit again. */
1988                 reg = TRANS_CHICKEN2(pipe);
1989                 val = I915_READ(reg);
1990                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1991                 I915_WRITE(reg, val);
1992         }
1993 }
1994
1995 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1996 {
1997         u32 val;
1998
1999         val = I915_READ(LPT_TRANSCONF);
2000         val &= ~TRANS_ENABLE;
2001         I915_WRITE(LPT_TRANSCONF, val);
2002         /* wait for PCH transcoder off, transcoder state */
2003         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2004                 DRM_ERROR("Failed to disable PCH transcoder\n");
2005
2006         /* Workaround: clear timing override bit. */
2007         val = I915_READ(_TRANSA_CHICKEN2);
2008         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2009         I915_WRITE(_TRANSA_CHICKEN2, val);
2010 }
2011
2012 /**
2013  * intel_enable_pipe - enable a pipe, asserting requirements
2014  * @crtc: crtc responsible for the pipe
2015  *
2016  * Enable @crtc's pipe, making sure that various hardware specific requirements
2017  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2018  */
2019 static void intel_enable_pipe(struct intel_crtc *crtc)
2020 {
2021         struct drm_device *dev = crtc->base.dev;
2022         struct drm_i915_private *dev_priv = dev->dev_private;
2023         enum pipe pipe = crtc->pipe;
2024         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2025                                                                       pipe);
2026         enum pipe pch_transcoder;
2027         int reg;
2028         u32 val;
2029
2030         assert_planes_disabled(dev_priv, pipe);
2031         assert_cursor_disabled(dev_priv, pipe);
2032         assert_sprites_disabled(dev_priv, pipe);
2033
2034         if (HAS_PCH_LPT(dev_priv->dev))
2035                 pch_transcoder = TRANSCODER_A;
2036         else
2037                 pch_transcoder = pipe;
2038
2039         /*
2040          * A pipe without a PLL won't actually be able to drive bits from
2041          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2042          * need the check.
2043          */
2044         if (!HAS_PCH_SPLIT(dev_priv->dev))
2045                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2046                         assert_dsi_pll_enabled(dev_priv);
2047                 else
2048                         assert_pll_enabled(dev_priv, pipe);
2049         else {
2050                 if (crtc->config.has_pch_encoder) {
2051                         /* if driving the PCH, we need FDI enabled */
2052                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2053                         assert_fdi_tx_pll_enabled(dev_priv,
2054                                                   (enum pipe) cpu_transcoder);
2055                 }
2056                 /* FIXME: assert CPU port conditions for SNB+ */
2057         }
2058
2059         reg = PIPECONF(cpu_transcoder);
2060         val = I915_READ(reg);
2061         if (val & PIPECONF_ENABLE) {
2062                 WARN_ON(!(pipe == PIPE_A &&
2063                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
2064                 return;
2065         }
2066
2067         I915_WRITE(reg, val | PIPECONF_ENABLE);
2068         POSTING_READ(reg);
2069 }
2070
2071 /**
2072  * intel_disable_pipe - disable a pipe, asserting requirements
2073  * @dev_priv: i915 private structure
2074  * @pipe: pipe to disable
2075  *
2076  * Disable @pipe, making sure that various hardware specific requirements
2077  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2078  *
2079  * @pipe should be %PIPE_A or %PIPE_B.
2080  *
2081  * Will wait until the pipe has shut down before returning.
2082  */
2083 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2084                                enum pipe pipe)
2085 {
2086         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2087                                                                       pipe);
2088         int reg;
2089         u32 val;
2090
2091         /*
2092          * Make sure planes won't keep trying to pump pixels to us,
2093          * or we might hang the display.
2094          */
2095         assert_planes_disabled(dev_priv, pipe);
2096         assert_cursor_disabled(dev_priv, pipe);
2097         assert_sprites_disabled(dev_priv, pipe);
2098
2099         /* Don't disable pipe A or pipe A PLLs if needed */
2100         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2101                 return;
2102
2103         reg = PIPECONF(cpu_transcoder);
2104         val = I915_READ(reg);
2105         if ((val & PIPECONF_ENABLE) == 0)
2106                 return;
2107
2108         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2109         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2110 }
2111
2112 /*
2113  * Plane regs are double buffered, going from enabled->disabled needs a
2114  * trigger in order to latch.  The display address reg provides this.
2115  */
2116 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2117                                enum plane plane)
2118 {
2119         struct drm_device *dev = dev_priv->dev;
2120         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2121
2122         I915_WRITE(reg, I915_READ(reg));
2123         POSTING_READ(reg);
2124 }
2125
2126 /**
2127  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2128  * @dev_priv: i915 private structure
2129  * @plane: plane to enable
2130  * @pipe: pipe being fed
2131  *
2132  * Enable @plane on @pipe, making sure that @pipe is running first.
2133  */
2134 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2135                                           enum plane plane, enum pipe pipe)
2136 {
2137         struct drm_device *dev = dev_priv->dev;
2138         struct intel_crtc *intel_crtc =
2139                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2140         int reg;
2141         u32 val;
2142
2143         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2144         assert_pipe_enabled(dev_priv, pipe);
2145
2146         if (intel_crtc->primary_enabled)
2147                 return;
2148
2149         intel_crtc->primary_enabled = true;
2150
2151         reg = DSPCNTR(plane);
2152         val = I915_READ(reg);
2153         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2154
2155         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2156         intel_flush_primary_plane(dev_priv, plane);
2157
2158         /*
2159          * BDW signals flip done immediately if the plane
2160          * is disabled, even if the plane enable is already
2161          * armed to occur at the next vblank :(
2162          */
2163         if (IS_BROADWELL(dev))
2164                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2165 }
2166
2167 /**
2168  * intel_disable_primary_hw_plane - disable the primary hardware plane
2169  * @dev_priv: i915 private structure
2170  * @plane: plane to disable
2171  * @pipe: pipe consuming the data
2172  *
2173  * Disable @plane; should be an independent operation.
2174  */
2175 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2176                                            enum plane plane, enum pipe pipe)
2177 {
2178         struct intel_crtc *intel_crtc =
2179                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2180         int reg;
2181         u32 val;
2182
2183         if (!intel_crtc->primary_enabled)
2184                 return;
2185
2186         intel_crtc->primary_enabled = false;
2187
2188         reg = DSPCNTR(plane);
2189         val = I915_READ(reg);
2190         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2191
2192         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2193         intel_flush_primary_plane(dev_priv, plane);
2194 }
2195
2196 static bool need_vtd_wa(struct drm_device *dev)
2197 {
2198 #ifdef CONFIG_INTEL_IOMMU
2199         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2200                 return true;
2201 #endif
2202         return false;
2203 }
2204
2205 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2206 {
2207         int tile_height;
2208
2209         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2210         return ALIGN(height, tile_height);
2211 }
2212
2213 int
2214 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2215                            struct drm_i915_gem_object *obj,
2216                            struct intel_engine_cs *pipelined)
2217 {
2218         struct drm_i915_private *dev_priv = dev->dev_private;
2219         u32 alignment;
2220         int ret;
2221
2222         switch (obj->tiling_mode) {
2223         case I915_TILING_NONE:
2224                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2225                         alignment = 128 * 1024;
2226                 else if (INTEL_INFO(dev)->gen >= 4)
2227                         alignment = 4 * 1024;
2228                 else
2229                         alignment = 64 * 1024;
2230                 break;
2231         case I915_TILING_X:
2232                 /* pin() will align the object as required by fence */
2233                 alignment = 0;
2234                 break;
2235         case I915_TILING_Y:
2236                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2237                 return -EINVAL;
2238         default:
2239                 BUG();
2240         }
2241
2242         /* Note that the w/a also requires 64 PTE of padding following the
2243          * bo. We currently fill all unused PTE with the shadow page and so
2244          * we should always have valid PTE following the scanout preventing
2245          * the VT-d warning.
2246          */
2247         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2248                 alignment = 256 * 1024;
2249
2250         dev_priv->mm.interruptible = false;
2251         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2252         if (ret)
2253                 goto err_interruptible;
2254
2255         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2256          * fence, whereas 965+ only requires a fence if using
2257          * framebuffer compression.  For simplicity, we always install
2258          * a fence as the cost is not that onerous.
2259          */
2260         ret = i915_gem_object_get_fence(obj);
2261         if (ret)
2262                 goto err_unpin;
2263
2264         i915_gem_object_pin_fence(obj);
2265
2266         dev_priv->mm.interruptible = true;
2267         return 0;
2268
2269 err_unpin:
2270         i915_gem_object_unpin_from_display_plane(obj);
2271 err_interruptible:
2272         dev_priv->mm.interruptible = true;
2273         return ret;
2274 }
2275
2276 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2277 {
2278         i915_gem_object_unpin_fence(obj);
2279         i915_gem_object_unpin_from_display_plane(obj);
2280 }
2281
2282 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2283  * is assumed to be a power-of-two. */
2284 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2285                                              unsigned int tiling_mode,
2286                                              unsigned int cpp,
2287                                              unsigned int pitch)
2288 {
2289         if (tiling_mode != I915_TILING_NONE) {
2290                 unsigned int tile_rows, tiles;
2291
2292                 tile_rows = *y / 8;
2293                 *y %= 8;
2294
2295                 tiles = *x / (512/cpp);
2296                 *x %= 512/cpp;
2297
2298                 return tile_rows * pitch * 8 + tiles * 4096;
2299         } else {
2300                 unsigned int offset;
2301
2302                 offset = *y * pitch + *x * cpp;
2303                 *y = 0;
2304                 *x = (offset & 4095) / cpp;
2305                 return offset & -4096;
2306         }
2307 }
2308
2309 int intel_format_to_fourcc(int format)
2310 {
2311         switch (format) {
2312         case DISPPLANE_8BPP:
2313                 return DRM_FORMAT_C8;
2314         case DISPPLANE_BGRX555:
2315                 return DRM_FORMAT_XRGB1555;
2316         case DISPPLANE_BGRX565:
2317                 return DRM_FORMAT_RGB565;
2318         default:
2319         case DISPPLANE_BGRX888:
2320                 return DRM_FORMAT_XRGB8888;
2321         case DISPPLANE_RGBX888:
2322                 return DRM_FORMAT_XBGR8888;
2323         case DISPPLANE_BGRX101010:
2324                 return DRM_FORMAT_XRGB2101010;
2325         case DISPPLANE_RGBX101010:
2326                 return DRM_FORMAT_XBGR2101010;
2327         }
2328 }
2329
2330 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2331                                   struct intel_plane_config *plane_config)
2332 {
2333         struct drm_device *dev = crtc->base.dev;
2334         struct drm_i915_gem_object *obj = NULL;
2335         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2336         u32 base = plane_config->base;
2337
2338         if (plane_config->size == 0)
2339                 return false;
2340
2341         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2342                                                              plane_config->size);
2343         if (!obj)
2344                 return false;
2345
2346         if (plane_config->tiled) {
2347                 obj->tiling_mode = I915_TILING_X;
2348                 obj->stride = crtc->base.primary->fb->pitches[0];
2349         }
2350
2351         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2352         mode_cmd.width = crtc->base.primary->fb->width;
2353         mode_cmd.height = crtc->base.primary->fb->height;
2354         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2355
2356         mutex_lock(&dev->struct_mutex);
2357
2358         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2359                                    &mode_cmd, obj)) {
2360                 DRM_DEBUG_KMS("intel fb init failed\n");
2361                 goto out_unref_obj;
2362         }
2363
2364         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2365         mutex_unlock(&dev->struct_mutex);
2366
2367         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2368         return true;
2369
2370 out_unref_obj:
2371         drm_gem_object_unreference(&obj->base);
2372         mutex_unlock(&dev->struct_mutex);
2373         return false;
2374 }
2375
2376 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2377                                  struct intel_plane_config *plane_config)
2378 {
2379         struct drm_device *dev = intel_crtc->base.dev;
2380         struct drm_crtc *c;
2381         struct intel_crtc *i;
2382         struct intel_framebuffer *fb;
2383
2384         if (!intel_crtc->base.primary->fb)
2385                 return;
2386
2387         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2388                 return;
2389
2390         kfree(intel_crtc->base.primary->fb);
2391         intel_crtc->base.primary->fb = NULL;
2392
2393         /*
2394          * Failed to alloc the obj, check to see if we should share
2395          * an fb with another CRTC instead
2396          */
2397         for_each_crtc(dev, c) {
2398                 i = to_intel_crtc(c);
2399
2400                 if (c == &intel_crtc->base)
2401                         continue;
2402
2403                 if (!i->active || !c->primary->fb)
2404                         continue;
2405
2406                 fb = to_intel_framebuffer(c->primary->fb);
2407                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2408                         drm_framebuffer_reference(c->primary->fb);
2409                         intel_crtc->base.primary->fb = c->primary->fb;
2410                         fb->obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2411                         break;
2412                 }
2413         }
2414 }
2415
2416 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2417                                       struct drm_framebuffer *fb,
2418                                       int x, int y)
2419 {
2420         struct drm_device *dev = crtc->dev;
2421         struct drm_i915_private *dev_priv = dev->dev_private;
2422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2423         struct intel_framebuffer *intel_fb;
2424         struct drm_i915_gem_object *obj;
2425         int plane = intel_crtc->plane;
2426         unsigned long linear_offset;
2427         u32 dspcntr;
2428         u32 reg;
2429
2430         intel_fb = to_intel_framebuffer(fb);
2431         obj = intel_fb->obj;
2432
2433         reg = DSPCNTR(plane);
2434         dspcntr = I915_READ(reg);
2435         /* Mask out pixel format bits in case we change it */
2436         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2437         switch (fb->pixel_format) {
2438         case DRM_FORMAT_C8:
2439                 dspcntr |= DISPPLANE_8BPP;
2440                 break;
2441         case DRM_FORMAT_XRGB1555:
2442         case DRM_FORMAT_ARGB1555:
2443                 dspcntr |= DISPPLANE_BGRX555;
2444                 break;
2445         case DRM_FORMAT_RGB565:
2446                 dspcntr |= DISPPLANE_BGRX565;
2447                 break;
2448         case DRM_FORMAT_XRGB8888:
2449         case DRM_FORMAT_ARGB8888:
2450                 dspcntr |= DISPPLANE_BGRX888;
2451                 break;
2452         case DRM_FORMAT_XBGR8888:
2453         case DRM_FORMAT_ABGR8888:
2454                 dspcntr |= DISPPLANE_RGBX888;
2455                 break;
2456         case DRM_FORMAT_XRGB2101010:
2457         case DRM_FORMAT_ARGB2101010:
2458                 dspcntr |= DISPPLANE_BGRX101010;
2459                 break;
2460         case DRM_FORMAT_XBGR2101010:
2461         case DRM_FORMAT_ABGR2101010:
2462                 dspcntr |= DISPPLANE_RGBX101010;
2463                 break;
2464         default:
2465                 BUG();
2466         }
2467
2468         if (INTEL_INFO(dev)->gen >= 4) {
2469                 if (obj->tiling_mode != I915_TILING_NONE)
2470                         dspcntr |= DISPPLANE_TILED;
2471                 else
2472                         dspcntr &= ~DISPPLANE_TILED;
2473         }
2474
2475         if (IS_G4X(dev))
2476                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2477
2478         I915_WRITE(reg, dspcntr);
2479
2480         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2481
2482         if (INTEL_INFO(dev)->gen >= 4) {
2483                 intel_crtc->dspaddr_offset =
2484                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2485                                                        fb->bits_per_pixel / 8,
2486                                                        fb->pitches[0]);
2487                 linear_offset -= intel_crtc->dspaddr_offset;
2488         } else {
2489                 intel_crtc->dspaddr_offset = linear_offset;
2490         }
2491
2492         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2493                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2494                       fb->pitches[0]);
2495         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2496         if (INTEL_INFO(dev)->gen >= 4) {
2497                 I915_WRITE(DSPSURF(plane),
2498                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2499                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2500                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2501         } else
2502                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2503         POSTING_READ(reg);
2504 }
2505
2506 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2507                                           struct drm_framebuffer *fb,
2508                                           int x, int y)
2509 {
2510         struct drm_device *dev = crtc->dev;
2511         struct drm_i915_private *dev_priv = dev->dev_private;
2512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2513         struct intel_framebuffer *intel_fb;
2514         struct drm_i915_gem_object *obj;
2515         int plane = intel_crtc->plane;
2516         unsigned long linear_offset;
2517         u32 dspcntr;
2518         u32 reg;
2519
2520         intel_fb = to_intel_framebuffer(fb);
2521         obj = intel_fb->obj;
2522
2523         reg = DSPCNTR(plane);
2524         dspcntr = I915_READ(reg);
2525         /* Mask out pixel format bits in case we change it */
2526         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2527         switch (fb->pixel_format) {
2528         case DRM_FORMAT_C8:
2529                 dspcntr |= DISPPLANE_8BPP;
2530                 break;
2531         case DRM_FORMAT_RGB565:
2532                 dspcntr |= DISPPLANE_BGRX565;
2533                 break;
2534         case DRM_FORMAT_XRGB8888:
2535         case DRM_FORMAT_ARGB8888:
2536                 dspcntr |= DISPPLANE_BGRX888;
2537                 break;
2538         case DRM_FORMAT_XBGR8888:
2539         case DRM_FORMAT_ABGR8888:
2540                 dspcntr |= DISPPLANE_RGBX888;
2541                 break;
2542         case DRM_FORMAT_XRGB2101010:
2543         case DRM_FORMAT_ARGB2101010:
2544                 dspcntr |= DISPPLANE_BGRX101010;
2545                 break;
2546         case DRM_FORMAT_XBGR2101010:
2547         case DRM_FORMAT_ABGR2101010:
2548                 dspcntr |= DISPPLANE_RGBX101010;
2549                 break;
2550         default:
2551                 BUG();
2552         }
2553
2554         if (obj->tiling_mode != I915_TILING_NONE)
2555                 dspcntr |= DISPPLANE_TILED;
2556         else
2557                 dspcntr &= ~DISPPLANE_TILED;
2558
2559         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2560                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2561         else
2562                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2563
2564         I915_WRITE(reg, dspcntr);
2565
2566         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2567         intel_crtc->dspaddr_offset =
2568                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2569                                                fb->bits_per_pixel / 8,
2570                                                fb->pitches[0]);
2571         linear_offset -= intel_crtc->dspaddr_offset;
2572
2573         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2574                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2575                       fb->pitches[0]);
2576         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2577         I915_WRITE(DSPSURF(plane),
2578                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2579         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2580                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2581         } else {
2582                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2583                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2584         }
2585         POSTING_READ(reg);
2586 }
2587
2588 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2589 static int
2590 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2591                            int x, int y, enum mode_set_atomic state)
2592 {
2593         struct drm_device *dev = crtc->dev;
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595
2596         if (dev_priv->display.disable_fbc)
2597                 dev_priv->display.disable_fbc(dev);
2598         intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2599
2600         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2601
2602         return 0;
2603 }
2604
2605 void intel_display_handle_reset(struct drm_device *dev)
2606 {
2607         struct drm_i915_private *dev_priv = dev->dev_private;
2608         struct drm_crtc *crtc;
2609
2610         /*
2611          * Flips in the rings have been nuked by the reset,
2612          * so complete all pending flips so that user space
2613          * will get its events and not get stuck.
2614          *
2615          * Also update the base address of all primary
2616          * planes to the the last fb to make sure we're
2617          * showing the correct fb after a reset.
2618          *
2619          * Need to make two loops over the crtcs so that we
2620          * don't try to grab a crtc mutex before the
2621          * pending_flip_queue really got woken up.
2622          */
2623
2624         for_each_crtc(dev, crtc) {
2625                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2626                 enum plane plane = intel_crtc->plane;
2627
2628                 intel_prepare_page_flip(dev, plane);
2629                 intel_finish_page_flip_plane(dev, plane);
2630         }
2631
2632         for_each_crtc(dev, crtc) {
2633                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2634
2635                 drm_modeset_lock(&crtc->mutex, NULL);
2636                 /*
2637                  * FIXME: Once we have proper support for primary planes (and
2638                  * disabling them without disabling the entire crtc) allow again
2639                  * a NULL crtc->primary->fb.
2640                  */
2641                 if (intel_crtc->active && crtc->primary->fb)
2642                         dev_priv->display.update_primary_plane(crtc,
2643                                                                crtc->primary->fb,
2644                                                                crtc->x,
2645                                                                crtc->y);
2646                 drm_modeset_unlock(&crtc->mutex);
2647         }
2648 }
2649
2650 static int
2651 intel_finish_fb(struct drm_framebuffer *old_fb)
2652 {
2653         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2654         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2655         bool was_interruptible = dev_priv->mm.interruptible;
2656         int ret;
2657
2658         /* Big Hammer, we also need to ensure that any pending
2659          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2660          * current scanout is retired before unpinning the old
2661          * framebuffer.
2662          *
2663          * This should only fail upon a hung GPU, in which case we
2664          * can safely continue.
2665          */
2666         dev_priv->mm.interruptible = false;
2667         ret = i915_gem_object_finish_gpu(obj);
2668         dev_priv->mm.interruptible = was_interruptible;
2669
2670         return ret;
2671 }
2672
2673 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2674 {
2675         struct drm_device *dev = crtc->dev;
2676         struct drm_i915_private *dev_priv = dev->dev_private;
2677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2678         unsigned long flags;
2679         bool pending;
2680
2681         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2682             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2683                 return false;
2684
2685         spin_lock_irqsave(&dev->event_lock, flags);
2686         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2687         spin_unlock_irqrestore(&dev->event_lock, flags);
2688
2689         return pending;
2690 }
2691
2692 static int
2693 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2694                     struct drm_framebuffer *fb)
2695 {
2696         struct drm_device *dev = crtc->dev;
2697         struct drm_i915_private *dev_priv = dev->dev_private;
2698         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2699         enum pipe pipe = intel_crtc->pipe;
2700         struct drm_framebuffer *old_fb;
2701         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
2702         struct drm_i915_gem_object *old_obj;
2703         int ret;
2704
2705         if (intel_crtc_has_pending_flip(crtc)) {
2706                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2707                 return -EBUSY;
2708         }
2709
2710         /* no fb bound */
2711         if (!fb) {
2712                 DRM_ERROR("No FB bound\n");
2713                 return 0;
2714         }
2715
2716         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2717                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2718                           plane_name(intel_crtc->plane),
2719                           INTEL_INFO(dev)->num_pipes);
2720                 return -EINVAL;
2721         }
2722
2723         old_fb = crtc->primary->fb;
2724         old_obj = old_fb ? to_intel_framebuffer(old_fb)->obj : NULL;
2725
2726         mutex_lock(&dev->struct_mutex);
2727         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2728         if (ret == 0)
2729                 i915_gem_track_fb(old_obj, obj,
2730                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2731         mutex_unlock(&dev->struct_mutex);
2732         if (ret != 0) {
2733                 DRM_ERROR("pin & fence failed\n");
2734                 return ret;
2735         }
2736
2737         /*
2738          * Update pipe size and adjust fitter if needed: the reason for this is
2739          * that in compute_mode_changes we check the native mode (not the pfit
2740          * mode) to see if we can flip rather than do a full mode set. In the
2741          * fastboot case, we'll flip, but if we don't update the pipesrc and
2742          * pfit state, we'll end up with a big fb scanned out into the wrong
2743          * sized surface.
2744          *
2745          * To fix this properly, we need to hoist the checks up into
2746          * compute_mode_changes (or above), check the actual pfit state and
2747          * whether the platform allows pfit disable with pipe active, and only
2748          * then update the pipesrc and pfit state, even on the flip path.
2749          */
2750         if (i915.fastboot) {
2751                 const struct drm_display_mode *adjusted_mode =
2752                         &intel_crtc->config.adjusted_mode;
2753
2754                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2755                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2756                            (adjusted_mode->crtc_vdisplay - 1));
2757                 if (!intel_crtc->config.pch_pfit.enabled &&
2758                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2759                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2760                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2761                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2762                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2763                 }
2764                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2765                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2766         }
2767
2768         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2769
2770         if (intel_crtc->active)
2771                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2772
2773         crtc->primary->fb = fb;
2774         crtc->x = x;
2775         crtc->y = y;
2776
2777         if (old_fb) {
2778                 if (intel_crtc->active && old_fb != fb)
2779                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2780                 mutex_lock(&dev->struct_mutex);
2781                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2782                 mutex_unlock(&dev->struct_mutex);
2783         }
2784
2785         mutex_lock(&dev->struct_mutex);
2786         intel_update_fbc(dev);
2787         mutex_unlock(&dev->struct_mutex);
2788
2789         return 0;
2790 }
2791
2792 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2793 {
2794         struct drm_device *dev = crtc->dev;
2795         struct drm_i915_private *dev_priv = dev->dev_private;
2796         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797         int pipe = intel_crtc->pipe;
2798         u32 reg, temp;
2799
2800         /* enable normal train */
2801         reg = FDI_TX_CTL(pipe);
2802         temp = I915_READ(reg);
2803         if (IS_IVYBRIDGE(dev)) {
2804                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2805                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2806         } else {
2807                 temp &= ~FDI_LINK_TRAIN_NONE;
2808                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2809         }
2810         I915_WRITE(reg, temp);
2811
2812         reg = FDI_RX_CTL(pipe);
2813         temp = I915_READ(reg);
2814         if (HAS_PCH_CPT(dev)) {
2815                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2816                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2817         } else {
2818                 temp &= ~FDI_LINK_TRAIN_NONE;
2819                 temp |= FDI_LINK_TRAIN_NONE;
2820         }
2821         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2822
2823         /* wait one idle pattern time */
2824         POSTING_READ(reg);
2825         udelay(1000);
2826
2827         /* IVB wants error correction enabled */
2828         if (IS_IVYBRIDGE(dev))
2829                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2830                            FDI_FE_ERRC_ENABLE);
2831 }
2832
2833 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2834 {
2835         return crtc->base.enabled && crtc->active &&
2836                 crtc->config.has_pch_encoder;
2837 }
2838
2839 static void ivb_modeset_global_resources(struct drm_device *dev)
2840 {
2841         struct drm_i915_private *dev_priv = dev->dev_private;
2842         struct intel_crtc *pipe_B_crtc =
2843                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2844         struct intel_crtc *pipe_C_crtc =
2845                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2846         uint32_t temp;
2847
2848         /*
2849          * When everything is off disable fdi C so that we could enable fdi B
2850          * with all lanes. Note that we don't care about enabled pipes without
2851          * an enabled pch encoder.
2852          */
2853         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2854             !pipe_has_enabled_pch(pipe_C_crtc)) {
2855                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2856                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2857
2858                 temp = I915_READ(SOUTH_CHICKEN1);
2859                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2860                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2861                 I915_WRITE(SOUTH_CHICKEN1, temp);
2862         }
2863 }
2864
2865 /* The FDI link training functions for ILK/Ibexpeak. */
2866 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2867 {
2868         struct drm_device *dev = crtc->dev;
2869         struct drm_i915_private *dev_priv = dev->dev_private;
2870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2871         int pipe = intel_crtc->pipe;
2872         u32 reg, temp, tries;
2873
2874         /* FDI needs bits from pipe first */
2875         assert_pipe_enabled(dev_priv, pipe);
2876
2877         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2878            for train result */
2879         reg = FDI_RX_IMR(pipe);
2880         temp = I915_READ(reg);
2881         temp &= ~FDI_RX_SYMBOL_LOCK;
2882         temp &= ~FDI_RX_BIT_LOCK;
2883         I915_WRITE(reg, temp);
2884         I915_READ(reg);
2885         udelay(150);
2886
2887         /* enable CPU FDI TX and PCH FDI RX */
2888         reg = FDI_TX_CTL(pipe);
2889         temp = I915_READ(reg);
2890         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2891         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2892         temp &= ~FDI_LINK_TRAIN_NONE;
2893         temp |= FDI_LINK_TRAIN_PATTERN_1;
2894         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2895
2896         reg = FDI_RX_CTL(pipe);
2897         temp = I915_READ(reg);
2898         temp &= ~FDI_LINK_TRAIN_NONE;
2899         temp |= FDI_LINK_TRAIN_PATTERN_1;
2900         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2901
2902         POSTING_READ(reg);
2903         udelay(150);
2904
2905         /* Ironlake workaround, enable clock pointer after FDI enable*/
2906         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2907         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2908                    FDI_RX_PHASE_SYNC_POINTER_EN);
2909
2910         reg = FDI_RX_IIR(pipe);
2911         for (tries = 0; tries < 5; tries++) {
2912                 temp = I915_READ(reg);
2913                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2914
2915                 if ((temp & FDI_RX_BIT_LOCK)) {
2916                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2917                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2918                         break;
2919                 }
2920         }
2921         if (tries == 5)
2922                 DRM_ERROR("FDI train 1 fail!\n");
2923
2924         /* Train 2 */
2925         reg = FDI_TX_CTL(pipe);
2926         temp = I915_READ(reg);
2927         temp &= ~FDI_LINK_TRAIN_NONE;
2928         temp |= FDI_LINK_TRAIN_PATTERN_2;
2929         I915_WRITE(reg, temp);
2930
2931         reg = FDI_RX_CTL(pipe);
2932         temp = I915_READ(reg);
2933         temp &= ~FDI_LINK_TRAIN_NONE;
2934         temp |= FDI_LINK_TRAIN_PATTERN_2;
2935         I915_WRITE(reg, temp);
2936
2937         POSTING_READ(reg);
2938         udelay(150);
2939
2940         reg = FDI_RX_IIR(pipe);
2941         for (tries = 0; tries < 5; tries++) {
2942                 temp = I915_READ(reg);
2943                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2944
2945                 if (temp & FDI_RX_SYMBOL_LOCK) {
2946                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2947                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2948                         break;
2949                 }
2950         }
2951         if (tries == 5)
2952                 DRM_ERROR("FDI train 2 fail!\n");
2953
2954         DRM_DEBUG_KMS("FDI train done\n");
2955
2956 }
2957
2958 static const int snb_b_fdi_train_param[] = {
2959         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2960         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2961         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2962         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2963 };
2964
2965 /* The FDI link training functions for SNB/Cougarpoint. */
2966 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2967 {
2968         struct drm_device *dev = crtc->dev;
2969         struct drm_i915_private *dev_priv = dev->dev_private;
2970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971         int pipe = intel_crtc->pipe;
2972         u32 reg, temp, i, retry;
2973
2974         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2975            for train result */
2976         reg = FDI_RX_IMR(pipe);
2977         temp = I915_READ(reg);
2978         temp &= ~FDI_RX_SYMBOL_LOCK;
2979         temp &= ~FDI_RX_BIT_LOCK;
2980         I915_WRITE(reg, temp);
2981
2982         POSTING_READ(reg);
2983         udelay(150);
2984
2985         /* enable CPU FDI TX and PCH FDI RX */
2986         reg = FDI_TX_CTL(pipe);
2987         temp = I915_READ(reg);
2988         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2989         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2990         temp &= ~FDI_LINK_TRAIN_NONE;
2991         temp |= FDI_LINK_TRAIN_PATTERN_1;
2992         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2993         /* SNB-B */
2994         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2995         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2996
2997         I915_WRITE(FDI_RX_MISC(pipe),
2998                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2999
3000         reg = FDI_RX_CTL(pipe);
3001         temp = I915_READ(reg);
3002         if (HAS_PCH_CPT(dev)) {
3003                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3004                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3005         } else {
3006                 temp &= ~FDI_LINK_TRAIN_NONE;
3007                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3008         }
3009         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3010
3011         POSTING_READ(reg);
3012         udelay(150);
3013
3014         for (i = 0; i < 4; i++) {
3015                 reg = FDI_TX_CTL(pipe);
3016                 temp = I915_READ(reg);
3017                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3018                 temp |= snb_b_fdi_train_param[i];
3019                 I915_WRITE(reg, temp);
3020
3021                 POSTING_READ(reg);
3022                 udelay(500);
3023
3024                 for (retry = 0; retry < 5; retry++) {
3025                         reg = FDI_RX_IIR(pipe);
3026                         temp = I915_READ(reg);
3027                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3028                         if (temp & FDI_RX_BIT_LOCK) {
3029                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3030                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3031                                 break;
3032                         }
3033                         udelay(50);
3034                 }
3035                 if (retry < 5)
3036                         break;
3037         }
3038         if (i == 4)
3039                 DRM_ERROR("FDI train 1 fail!\n");
3040
3041         /* Train 2 */
3042         reg = FDI_TX_CTL(pipe);
3043         temp = I915_READ(reg);
3044         temp &= ~FDI_LINK_TRAIN_NONE;
3045         temp |= FDI_LINK_TRAIN_PATTERN_2;
3046         if (IS_GEN6(dev)) {
3047                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3048                 /* SNB-B */
3049                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3050         }
3051         I915_WRITE(reg, temp);
3052
3053         reg = FDI_RX_CTL(pipe);
3054         temp = I915_READ(reg);
3055         if (HAS_PCH_CPT(dev)) {
3056                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3057                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3058         } else {
3059                 temp &= ~FDI_LINK_TRAIN_NONE;
3060                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3061         }
3062         I915_WRITE(reg, temp);
3063
3064         POSTING_READ(reg);
3065         udelay(150);
3066
3067         for (i = 0; i < 4; i++) {
3068                 reg = FDI_TX_CTL(pipe);
3069                 temp = I915_READ(reg);
3070                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3071                 temp |= snb_b_fdi_train_param[i];
3072                 I915_WRITE(reg, temp);
3073
3074                 POSTING_READ(reg);
3075                 udelay(500);
3076
3077                 for (retry = 0; retry < 5; retry++) {
3078                         reg = FDI_RX_IIR(pipe);
3079                         temp = I915_READ(reg);
3080                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3081                         if (temp & FDI_RX_SYMBOL_LOCK) {
3082                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3083                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3084                                 break;
3085                         }
3086                         udelay(50);
3087                 }
3088                 if (retry < 5)
3089                         break;
3090         }
3091         if (i == 4)
3092                 DRM_ERROR("FDI train 2 fail!\n");
3093
3094         DRM_DEBUG_KMS("FDI train done.\n");
3095 }
3096
3097 /* Manual link training for Ivy Bridge A0 parts */
3098 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3099 {
3100         struct drm_device *dev = crtc->dev;
3101         struct drm_i915_private *dev_priv = dev->dev_private;
3102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3103         int pipe = intel_crtc->pipe;
3104         u32 reg, temp, i, j;
3105
3106         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3107            for train result */
3108         reg = FDI_RX_IMR(pipe);
3109         temp = I915_READ(reg);
3110         temp &= ~FDI_RX_SYMBOL_LOCK;
3111         temp &= ~FDI_RX_BIT_LOCK;
3112         I915_WRITE(reg, temp);
3113
3114         POSTING_READ(reg);
3115         udelay(150);
3116
3117         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3118                       I915_READ(FDI_RX_IIR(pipe)));
3119
3120         /* Try each vswing and preemphasis setting twice before moving on */
3121         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3122                 /* disable first in case we need to retry */
3123                 reg = FDI_TX_CTL(pipe);
3124                 temp = I915_READ(reg);
3125                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3126                 temp &= ~FDI_TX_ENABLE;
3127                 I915_WRITE(reg, temp);
3128
3129                 reg = FDI_RX_CTL(pipe);
3130                 temp = I915_READ(reg);
3131                 temp &= ~FDI_LINK_TRAIN_AUTO;
3132                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3133                 temp &= ~FDI_RX_ENABLE;
3134                 I915_WRITE(reg, temp);
3135
3136                 /* enable CPU FDI TX and PCH FDI RX */
3137                 reg = FDI_TX_CTL(pipe);
3138                 temp = I915_READ(reg);
3139                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3140                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3141                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3142                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3143                 temp |= snb_b_fdi_train_param[j/2];
3144                 temp |= FDI_COMPOSITE_SYNC;
3145                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3146
3147                 I915_WRITE(FDI_RX_MISC(pipe),
3148                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3149
3150                 reg = FDI_RX_CTL(pipe);
3151                 temp = I915_READ(reg);
3152                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3153                 temp |= FDI_COMPOSITE_SYNC;
3154                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3155
3156                 POSTING_READ(reg);
3157                 udelay(1); /* should be 0.5us */
3158
3159                 for (i = 0; i < 4; i++) {
3160                         reg = FDI_RX_IIR(pipe);
3161                         temp = I915_READ(reg);
3162                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3163
3164                         if (temp & FDI_RX_BIT_LOCK ||
3165                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3166                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3167                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3168                                               i);
3169                                 break;
3170                         }
3171                         udelay(1); /* should be 0.5us */
3172                 }
3173                 if (i == 4) {
3174                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3175                         continue;
3176                 }
3177
3178                 /* Train 2 */
3179                 reg = FDI_TX_CTL(pipe);
3180                 temp = I915_READ(reg);
3181                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3182                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3183                 I915_WRITE(reg, temp);
3184
3185                 reg = FDI_RX_CTL(pipe);
3186                 temp = I915_READ(reg);
3187                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3188                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3189                 I915_WRITE(reg, temp);
3190
3191                 POSTING_READ(reg);
3192                 udelay(2); /* should be 1.5us */
3193
3194                 for (i = 0; i < 4; i++) {
3195                         reg = FDI_RX_IIR(pipe);
3196                         temp = I915_READ(reg);
3197                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3198
3199                         if (temp & FDI_RX_SYMBOL_LOCK ||
3200                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3201                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3202                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3203                                               i);
3204                                 goto train_done;
3205                         }
3206                         udelay(2); /* should be 1.5us */
3207                 }
3208                 if (i == 4)
3209                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3210         }
3211
3212 train_done:
3213         DRM_DEBUG_KMS("FDI train done.\n");
3214 }
3215
3216 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3217 {
3218         struct drm_device *dev = intel_crtc->base.dev;
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         int pipe = intel_crtc->pipe;
3221         u32 reg, temp;
3222
3223
3224         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3225         reg = FDI_RX_CTL(pipe);
3226         temp = I915_READ(reg);
3227         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3228         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3229         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3230         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3231
3232         POSTING_READ(reg);
3233         udelay(200);
3234
3235         /* Switch from Rawclk to PCDclk */
3236         temp = I915_READ(reg);
3237         I915_WRITE(reg, temp | FDI_PCDCLK);
3238
3239         POSTING_READ(reg);
3240         udelay(200);
3241
3242         /* Enable CPU FDI TX PLL, always on for Ironlake */
3243         reg = FDI_TX_CTL(pipe);
3244         temp = I915_READ(reg);
3245         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3246                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3247
3248                 POSTING_READ(reg);
3249                 udelay(100);
3250         }
3251 }
3252
3253 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3254 {
3255         struct drm_device *dev = intel_crtc->base.dev;
3256         struct drm_i915_private *dev_priv = dev->dev_private;
3257         int pipe = intel_crtc->pipe;
3258         u32 reg, temp;
3259
3260         /* Switch from PCDclk to Rawclk */
3261         reg = FDI_RX_CTL(pipe);
3262         temp = I915_READ(reg);
3263         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3264
3265         /* Disable CPU FDI TX PLL */
3266         reg = FDI_TX_CTL(pipe);
3267         temp = I915_READ(reg);
3268         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3269
3270         POSTING_READ(reg);
3271         udelay(100);
3272
3273         reg = FDI_RX_CTL(pipe);
3274         temp = I915_READ(reg);
3275         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3276
3277         /* Wait for the clocks to turn off. */
3278         POSTING_READ(reg);
3279         udelay(100);
3280 }
3281
3282 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3283 {
3284         struct drm_device *dev = crtc->dev;
3285         struct drm_i915_private *dev_priv = dev->dev_private;
3286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3287         int pipe = intel_crtc->pipe;
3288         u32 reg, temp;
3289
3290         /* disable CPU FDI tx and PCH FDI rx */
3291         reg = FDI_TX_CTL(pipe);
3292         temp = I915_READ(reg);
3293         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3294         POSTING_READ(reg);
3295
3296         reg = FDI_RX_CTL(pipe);
3297         temp = I915_READ(reg);
3298         temp &= ~(0x7 << 16);
3299         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3300         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3301
3302         POSTING_READ(reg);
3303         udelay(100);
3304
3305         /* Ironlake workaround, disable clock pointer after downing FDI */
3306         if (HAS_PCH_IBX(dev))
3307                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3308
3309         /* still set train pattern 1 */
3310         reg = FDI_TX_CTL(pipe);
3311         temp = I915_READ(reg);
3312         temp &= ~FDI_LINK_TRAIN_NONE;
3313         temp |= FDI_LINK_TRAIN_PATTERN_1;
3314         I915_WRITE(reg, temp);
3315
3316         reg = FDI_RX_CTL(pipe);
3317         temp = I915_READ(reg);
3318         if (HAS_PCH_CPT(dev)) {
3319                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3320                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3321         } else {
3322                 temp &= ~FDI_LINK_TRAIN_NONE;
3323                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3324         }
3325         /* BPC in FDI rx is consistent with that in PIPECONF */
3326         temp &= ~(0x07 << 16);
3327         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3328         I915_WRITE(reg, temp);
3329
3330         POSTING_READ(reg);
3331         udelay(100);
3332 }
3333
3334 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3335 {
3336         struct intel_crtc *crtc;
3337
3338         /* Note that we don't need to be called with mode_config.lock here
3339          * as our list of CRTC objects is static for the lifetime of the
3340          * device and so cannot disappear as we iterate. Similarly, we can
3341          * happily treat the predicates as racy, atomic checks as userspace
3342          * cannot claim and pin a new fb without at least acquring the
3343          * struct_mutex and so serialising with us.
3344          */
3345         for_each_intel_crtc(dev, crtc) {
3346                 if (atomic_read(&crtc->unpin_work_count) == 0)
3347                         continue;
3348
3349                 if (crtc->unpin_work)
3350                         intel_wait_for_vblank(dev, crtc->pipe);
3351
3352                 return true;
3353         }
3354
3355         return false;
3356 }
3357
3358 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3359 {
3360         struct drm_device *dev = crtc->dev;
3361         struct drm_i915_private *dev_priv = dev->dev_private;
3362
3363         if (crtc->primary->fb == NULL)
3364                 return;
3365
3366         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3367
3368         WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3369                                    !intel_crtc_has_pending_flip(crtc),
3370                                    60*HZ) == 0);
3371
3372         mutex_lock(&dev->struct_mutex);
3373         intel_finish_fb(crtc->primary->fb);
3374         mutex_unlock(&dev->struct_mutex);
3375 }
3376
3377 /* Program iCLKIP clock to the desired frequency */
3378 static void lpt_program_iclkip(struct drm_crtc *crtc)
3379 {
3380         struct drm_device *dev = crtc->dev;
3381         struct drm_i915_private *dev_priv = dev->dev_private;
3382         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3383         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3384         u32 temp;
3385
3386         mutex_lock(&dev_priv->dpio_lock);
3387
3388         /* It is necessary to ungate the pixclk gate prior to programming
3389          * the divisors, and gate it back when it is done.
3390          */
3391         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3392
3393         /* Disable SSCCTL */
3394         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3395                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3396                                 SBI_SSCCTL_DISABLE,
3397                         SBI_ICLK);
3398
3399         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3400         if (clock == 20000) {
3401                 auxdiv = 1;
3402                 divsel = 0x41;
3403                 phaseinc = 0x20;
3404         } else {
3405                 /* The iCLK virtual clock root frequency is in MHz,
3406                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3407                  * divisors, it is necessary to divide one by another, so we
3408                  * convert the virtual clock precision to KHz here for higher
3409                  * precision.
3410                  */
3411                 u32 iclk_virtual_root_freq = 172800 * 1000;
3412                 u32 iclk_pi_range = 64;
3413                 u32 desired_divisor, msb_divisor_value, pi_value;
3414
3415                 desired_divisor = (iclk_virtual_root_freq / clock);
3416                 msb_divisor_value = desired_divisor / iclk_pi_range;
3417                 pi_value = desired_divisor % iclk_pi_range;
3418
3419                 auxdiv = 0;
3420                 divsel = msb_divisor_value - 2;
3421                 phaseinc = pi_value;
3422         }
3423
3424         /* This should not happen with any sane values */
3425         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3426                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3427         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3428                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3429
3430         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3431                         clock,
3432                         auxdiv,
3433                         divsel,
3434                         phasedir,
3435                         phaseinc);
3436
3437         /* Program SSCDIVINTPHASE6 */
3438         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3439         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3440         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3441         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3442         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3443         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3444         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3445         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3446
3447         /* Program SSCAUXDIV */
3448         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3449         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3450         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3451         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3452
3453         /* Enable modulator and associated divider */
3454         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3455         temp &= ~SBI_SSCCTL_DISABLE;
3456         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3457
3458         /* Wait for initialization time */
3459         udelay(24);
3460
3461         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3462
3463         mutex_unlock(&dev_priv->dpio_lock);
3464 }
3465
3466 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3467                                                 enum pipe pch_transcoder)
3468 {
3469         struct drm_device *dev = crtc->base.dev;
3470         struct drm_i915_private *dev_priv = dev->dev_private;
3471         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3472
3473         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3474                    I915_READ(HTOTAL(cpu_transcoder)));
3475         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3476                    I915_READ(HBLANK(cpu_transcoder)));
3477         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3478                    I915_READ(HSYNC(cpu_transcoder)));
3479
3480         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3481                    I915_READ(VTOTAL(cpu_transcoder)));
3482         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3483                    I915_READ(VBLANK(cpu_transcoder)));
3484         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3485                    I915_READ(VSYNC(cpu_transcoder)));
3486         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3487                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3488 }
3489
3490 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3491 {
3492         struct drm_i915_private *dev_priv = dev->dev_private;
3493         uint32_t temp;
3494
3495         temp = I915_READ(SOUTH_CHICKEN1);
3496         if (temp & FDI_BC_BIFURCATION_SELECT)
3497                 return;
3498
3499         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3500         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3501
3502         temp |= FDI_BC_BIFURCATION_SELECT;
3503         DRM_DEBUG_KMS("enabling fdi C rx\n");
3504         I915_WRITE(SOUTH_CHICKEN1, temp);
3505         POSTING_READ(SOUTH_CHICKEN1);
3506 }
3507
3508 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3509 {
3510         struct drm_device *dev = intel_crtc->base.dev;
3511         struct drm_i915_private *dev_priv = dev->dev_private;
3512
3513         switch (intel_crtc->pipe) {
3514         case PIPE_A:
3515                 break;
3516         case PIPE_B:
3517                 if (intel_crtc->config.fdi_lanes > 2)
3518                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3519                 else
3520                         cpt_enable_fdi_bc_bifurcation(dev);
3521
3522                 break;
3523         case PIPE_C:
3524                 cpt_enable_fdi_bc_bifurcation(dev);
3525
3526                 break;
3527         default:
3528                 BUG();
3529         }
3530 }
3531
3532 /*
3533  * Enable PCH resources required for PCH ports:
3534  *   - PCH PLLs
3535  *   - FDI training & RX/TX
3536  *   - update transcoder timings
3537  *   - DP transcoding bits
3538  *   - transcoder
3539  */
3540 static void ironlake_pch_enable(struct drm_crtc *crtc)
3541 {
3542         struct drm_device *dev = crtc->dev;
3543         struct drm_i915_private *dev_priv = dev->dev_private;
3544         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3545         int pipe = intel_crtc->pipe;
3546         u32 reg, temp;
3547
3548         assert_pch_transcoder_disabled(dev_priv, pipe);
3549
3550         if (IS_IVYBRIDGE(dev))
3551                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3552
3553         /* Write the TU size bits before fdi link training, so that error
3554          * detection works. */
3555         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3556                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3557
3558         /* For PCH output, training FDI link */
3559         dev_priv->display.fdi_link_train(crtc);
3560
3561         /* We need to program the right clock selection before writing the pixel
3562          * mutliplier into the DPLL. */
3563         if (HAS_PCH_CPT(dev)) {
3564                 u32 sel;
3565
3566                 temp = I915_READ(PCH_DPLL_SEL);
3567                 temp |= TRANS_DPLL_ENABLE(pipe);
3568                 sel = TRANS_DPLLB_SEL(pipe);
3569                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3570                         temp |= sel;
3571                 else
3572                         temp &= ~sel;
3573                 I915_WRITE(PCH_DPLL_SEL, temp);
3574         }
3575
3576         /* XXX: pch pll's can be enabled any time before we enable the PCH
3577          * transcoder, and we actually should do this to not upset any PCH
3578          * transcoder that already use the clock when we share it.
3579          *
3580          * Note that enable_shared_dpll tries to do the right thing, but
3581          * get_shared_dpll unconditionally resets the pll - we need that to have
3582          * the right LVDS enable sequence. */
3583         intel_enable_shared_dpll(intel_crtc);
3584
3585         /* set transcoder timing, panel must allow it */
3586         assert_panel_unlocked(dev_priv, pipe);
3587         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3588
3589         intel_fdi_normal_train(crtc);
3590
3591         /* For PCH DP, enable TRANS_DP_CTL */
3592         if (HAS_PCH_CPT(dev) &&
3593             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3594              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3595                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3596                 reg = TRANS_DP_CTL(pipe);
3597                 temp = I915_READ(reg);
3598                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3599                           TRANS_DP_SYNC_MASK |
3600                           TRANS_DP_BPC_MASK);
3601                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3602                          TRANS_DP_ENH_FRAMING);
3603                 temp |= bpc << 9; /* same format but at 11:9 */
3604
3605                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3606                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3607                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3608                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3609
3610                 switch (intel_trans_dp_port_sel(crtc)) {
3611                 case PCH_DP_B:
3612                         temp |= TRANS_DP_PORT_SEL_B;
3613                         break;
3614                 case PCH_DP_C:
3615                         temp |= TRANS_DP_PORT_SEL_C;
3616                         break;
3617                 case PCH_DP_D:
3618                         temp |= TRANS_DP_PORT_SEL_D;
3619                         break;
3620                 default:
3621                         BUG();
3622                 }
3623
3624                 I915_WRITE(reg, temp);
3625         }
3626
3627         ironlake_enable_pch_transcoder(dev_priv, pipe);
3628 }
3629
3630 static void lpt_pch_enable(struct drm_crtc *crtc)
3631 {
3632         struct drm_device *dev = crtc->dev;
3633         struct drm_i915_private *dev_priv = dev->dev_private;
3634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3635         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3636
3637         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3638
3639         lpt_program_iclkip(crtc);
3640
3641         /* Set transcoder timing. */
3642         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3643
3644         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3645 }
3646
3647 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3648 {
3649         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3650
3651         if (pll == NULL)
3652                 return;
3653
3654         if (pll->refcount == 0) {
3655                 WARN(1, "bad %s refcount\n", pll->name);
3656                 return;
3657         }
3658
3659         if (--pll->refcount == 0) {
3660                 WARN_ON(pll->on);
3661                 WARN_ON(pll->active);
3662         }
3663
3664         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3665 }
3666
3667 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3668 {
3669         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3670         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3671         enum intel_dpll_id i;
3672
3673         if (pll) {
3674                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3675                               crtc->base.base.id, pll->name);
3676                 intel_put_shared_dpll(crtc);
3677         }
3678
3679         if (HAS_PCH_IBX(dev_priv->dev)) {
3680                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3681                 i = (enum intel_dpll_id) crtc->pipe;
3682                 pll = &dev_priv->shared_dplls[i];
3683
3684                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3685                               crtc->base.base.id, pll->name);
3686
3687                 WARN_ON(pll->refcount);
3688
3689                 goto found;
3690         }
3691
3692         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3693                 pll = &dev_priv->shared_dplls[i];
3694
3695                 /* Only want to check enabled timings first */
3696                 if (pll->refcount == 0)
3697                         continue;
3698
3699                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3700                            sizeof(pll->hw_state)) == 0) {
3701                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3702                                       crtc->base.base.id,
3703                                       pll->name, pll->refcount, pll->active);
3704
3705                         goto found;
3706                 }
3707         }
3708
3709         /* Ok no matching timings, maybe there's a free one? */
3710         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3711                 pll = &dev_priv->shared_dplls[i];
3712                 if (pll->refcount == 0) {
3713                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3714                                       crtc->base.base.id, pll->name);
3715                         goto found;
3716                 }
3717         }
3718
3719         return NULL;
3720
3721 found:
3722         if (pll->refcount == 0)
3723                 pll->hw_state = crtc->config.dpll_hw_state;
3724
3725         crtc->config.shared_dpll = i;
3726         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3727                          pipe_name(crtc->pipe));
3728
3729         pll->refcount++;
3730
3731         return pll;
3732 }
3733
3734 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3735 {
3736         struct drm_i915_private *dev_priv = dev->dev_private;
3737         int dslreg = PIPEDSL(pipe);
3738         u32 temp;
3739
3740         temp = I915_READ(dslreg);
3741         udelay(500);
3742         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3743                 if (wait_for(I915_READ(dslreg) != temp, 5))
3744                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3745         }
3746 }
3747
3748 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3749 {
3750         struct drm_device *dev = crtc->base.dev;
3751         struct drm_i915_private *dev_priv = dev->dev_private;
3752         int pipe = crtc->pipe;
3753
3754         if (crtc->config.pch_pfit.enabled) {
3755                 /* Force use of hard-coded filter coefficients
3756                  * as some pre-programmed values are broken,
3757                  * e.g. x201.
3758                  */
3759                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3760                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3761                                                  PF_PIPE_SEL_IVB(pipe));
3762                 else
3763                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3764                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3765                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3766         }
3767 }
3768
3769 static void intel_enable_planes(struct drm_crtc *crtc)
3770 {
3771         struct drm_device *dev = crtc->dev;
3772         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3773         struct drm_plane *plane;
3774         struct intel_plane *intel_plane;
3775
3776         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3777                 intel_plane = to_intel_plane(plane);
3778                 if (intel_plane->pipe == pipe)
3779                         intel_plane_restore(&intel_plane->base);
3780         }
3781 }
3782
3783 static void intel_disable_planes(struct drm_crtc *crtc)
3784 {
3785         struct drm_device *dev = crtc->dev;
3786         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3787         struct drm_plane *plane;
3788         struct intel_plane *intel_plane;
3789
3790         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3791                 intel_plane = to_intel_plane(plane);
3792                 if (intel_plane->pipe == pipe)
3793                         intel_plane_disable(&intel_plane->base);
3794         }
3795 }
3796
3797 void hsw_enable_ips(struct intel_crtc *crtc)
3798 {
3799         struct drm_device *dev = crtc->base.dev;
3800         struct drm_i915_private *dev_priv = dev->dev_private;
3801
3802         if (!crtc->config.ips_enabled)
3803                 return;
3804
3805         /* We can only enable IPS after we enable a plane and wait for a vblank */
3806         intel_wait_for_vblank(dev, crtc->pipe);
3807
3808         assert_plane_enabled(dev_priv, crtc->plane);
3809         if (IS_BROADWELL(dev)) {
3810                 mutex_lock(&dev_priv->rps.hw_lock);
3811                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3812                 mutex_unlock(&dev_priv->rps.hw_lock);
3813                 /* Quoting Art Runyan: "its not safe to expect any particular
3814                  * value in IPS_CTL bit 31 after enabling IPS through the
3815                  * mailbox." Moreover, the mailbox may return a bogus state,
3816                  * so we need to just enable it and continue on.
3817                  */
3818         } else {
3819                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3820                 /* The bit only becomes 1 in the next vblank, so this wait here
3821                  * is essentially intel_wait_for_vblank. If we don't have this
3822                  * and don't wait for vblanks until the end of crtc_enable, then
3823                  * the HW state readout code will complain that the expected
3824                  * IPS_CTL value is not the one we read. */
3825                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3826                         DRM_ERROR("Timed out waiting for IPS enable\n");
3827         }
3828 }
3829
3830 void hsw_disable_ips(struct intel_crtc *crtc)
3831 {
3832         struct drm_device *dev = crtc->base.dev;
3833         struct drm_i915_private *dev_priv = dev->dev_private;
3834
3835         if (!crtc->config.ips_enabled)
3836                 return;
3837
3838         assert_plane_enabled(dev_priv, crtc->plane);
3839         if (IS_BROADWELL(dev)) {
3840                 mutex_lock(&dev_priv->rps.hw_lock);
3841                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3842                 mutex_unlock(&dev_priv->rps.hw_lock);
3843                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3844                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3845                         DRM_ERROR("Timed out waiting for IPS disable\n");
3846         } else {
3847                 I915_WRITE(IPS_CTL, 0);
3848                 POSTING_READ(IPS_CTL);
3849         }
3850
3851         /* We need to wait for a vblank before we can disable the plane. */
3852         intel_wait_for_vblank(dev, crtc->pipe);
3853 }
3854
3855 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3856 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3857 {
3858         struct drm_device *dev = crtc->dev;
3859         struct drm_i915_private *dev_priv = dev->dev_private;
3860         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3861         enum pipe pipe = intel_crtc->pipe;
3862         int palreg = PALETTE(pipe);
3863         int i;
3864         bool reenable_ips = false;
3865
3866         /* The clocks have to be on to load the palette. */
3867         if (!crtc->enabled || !intel_crtc->active)
3868                 return;
3869
3870         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3871                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3872                         assert_dsi_pll_enabled(dev_priv);
3873                 else
3874                         assert_pll_enabled(dev_priv, pipe);
3875         }
3876
3877         /* use legacy palette for Ironlake */
3878         if (HAS_PCH_SPLIT(dev))
3879                 palreg = LGC_PALETTE(pipe);
3880
3881         /* Workaround : Do not read or write the pipe palette/gamma data while
3882          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3883          */
3884         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3885             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3886              GAMMA_MODE_MODE_SPLIT)) {
3887                 hsw_disable_ips(intel_crtc);
3888                 reenable_ips = true;
3889         }
3890
3891         for (i = 0; i < 256; i++) {
3892                 I915_WRITE(palreg + 4 * i,
3893                            (intel_crtc->lut_r[i] << 16) |
3894                            (intel_crtc->lut_g[i] << 8) |
3895                            intel_crtc->lut_b[i]);
3896         }
3897
3898         if (reenable_ips)
3899                 hsw_enable_ips(intel_crtc);
3900 }
3901
3902 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3903 {
3904         if (!enable && intel_crtc->overlay) {
3905                 struct drm_device *dev = intel_crtc->base.dev;
3906                 struct drm_i915_private *dev_priv = dev->dev_private;
3907
3908                 mutex_lock(&dev->struct_mutex);
3909                 dev_priv->mm.interruptible = false;
3910                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3911                 dev_priv->mm.interruptible = true;
3912                 mutex_unlock(&dev->struct_mutex);
3913         }
3914
3915         /* Let userspace switch the overlay on again. In most cases userspace
3916          * has to recompute where to put it anyway.
3917          */
3918 }
3919
3920 /**
3921  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3922  * cursor plane briefly if not already running after enabling the display
3923  * plane.
3924  * This workaround avoids occasional blank screens when self refresh is
3925  * enabled.
3926  */
3927 static void
3928 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3929 {
3930         u32 cntl = I915_READ(CURCNTR(pipe));
3931
3932         if ((cntl & CURSOR_MODE) == 0) {
3933                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3934
3935                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3936                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3937                 intel_wait_for_vblank(dev_priv->dev, pipe);
3938                 I915_WRITE(CURCNTR(pipe), cntl);
3939                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3940                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3941         }
3942 }
3943
3944 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3945 {
3946         struct drm_device *dev = crtc->dev;
3947         struct drm_i915_private *dev_priv = dev->dev_private;
3948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3949         int pipe = intel_crtc->pipe;
3950         int plane = intel_crtc->plane;
3951
3952         drm_vblank_on(dev, pipe);
3953
3954         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3955         intel_enable_planes(crtc);
3956         /* The fixup needs to happen before cursor is enabled */
3957         if (IS_G4X(dev))
3958                 g4x_fixup_plane(dev_priv, pipe);
3959         intel_crtc_update_cursor(crtc, true);
3960         intel_crtc_dpms_overlay(intel_crtc, true);
3961
3962         hsw_enable_ips(intel_crtc);
3963
3964         mutex_lock(&dev->struct_mutex);
3965         intel_update_fbc(dev);
3966         mutex_unlock(&dev->struct_mutex);
3967
3968         /*
3969          * FIXME: Once we grow proper nuclear flip support out of this we need
3970          * to compute the mask of flip planes precisely. For the time being
3971          * consider this a flip from a NULL plane.
3972          */
3973         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3974 }
3975
3976 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3977 {
3978         struct drm_device *dev = crtc->dev;
3979         struct drm_i915_private *dev_priv = dev->dev_private;
3980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3981         int pipe = intel_crtc->pipe;
3982         int plane = intel_crtc->plane;
3983
3984         intel_crtc_wait_for_pending_flips(crtc);
3985
3986         if (dev_priv->fbc.plane == plane)
3987                 intel_disable_fbc(dev);
3988
3989         hsw_disable_ips(intel_crtc);
3990
3991         intel_crtc_dpms_overlay(intel_crtc, false);
3992         intel_crtc_update_cursor(crtc, false);
3993         intel_disable_planes(crtc);
3994         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3995
3996         /*
3997          * FIXME: Once we grow proper nuclear flip support out of this we need
3998          * to compute the mask of flip planes precisely. For the time being
3999          * consider this a flip to a NULL plane.
4000          */
4001         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4002
4003         drm_vblank_off(dev, pipe);
4004 }
4005
4006 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4007 {
4008         struct drm_device *dev = crtc->dev;
4009         struct drm_i915_private *dev_priv = dev->dev_private;
4010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4011         struct intel_encoder *encoder;
4012         int pipe = intel_crtc->pipe;
4013         enum plane plane = intel_crtc->plane;
4014
4015         WARN_ON(!crtc->enabled);
4016
4017         if (intel_crtc->active)
4018                 return;
4019
4020         if (intel_crtc->config.has_pch_encoder)
4021                 intel_prepare_shared_dpll(intel_crtc);
4022
4023         if (intel_crtc->config.has_dp_encoder)
4024                 intel_dp_set_m_n(intel_crtc);
4025
4026         intel_set_pipe_timings(intel_crtc);
4027
4028         if (intel_crtc->config.has_pch_encoder) {
4029                 intel_cpu_transcoder_set_m_n(intel_crtc,
4030                                              &intel_crtc->config.fdi_m_n);
4031         }
4032
4033         ironlake_set_pipeconf(crtc);
4034
4035         /* Set up the display plane register */
4036         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
4037         POSTING_READ(DSPCNTR(plane));
4038
4039         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4040                                                crtc->x, crtc->y);
4041
4042         intel_crtc->active = true;
4043
4044         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4045         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4046
4047         for_each_encoder_on_crtc(dev, crtc, encoder)
4048                 if (encoder->pre_enable)
4049                         encoder->pre_enable(encoder);
4050
4051         if (intel_crtc->config.has_pch_encoder) {
4052                 /* Note: FDI PLL enabling _must_ be done before we enable the
4053                  * cpu pipes, hence this is separate from all the other fdi/pch
4054                  * enabling. */
4055                 ironlake_fdi_pll_enable(intel_crtc);
4056         } else {
4057                 assert_fdi_tx_disabled(dev_priv, pipe);
4058                 assert_fdi_rx_disabled(dev_priv, pipe);
4059         }
4060
4061         ironlake_pfit_enable(intel_crtc);
4062
4063         /*
4064          * On ILK+ LUT must be loaded before the pipe is running but with
4065          * clocks enabled
4066          */
4067         intel_crtc_load_lut(crtc);
4068
4069         intel_update_watermarks(crtc);
4070         intel_enable_pipe(intel_crtc);
4071
4072         if (intel_crtc->config.has_pch_encoder)
4073                 ironlake_pch_enable(crtc);
4074
4075         for_each_encoder_on_crtc(dev, crtc, encoder)
4076                 encoder->enable(encoder);
4077
4078         if (HAS_PCH_CPT(dev))
4079                 cpt_verify_modeset(dev, intel_crtc->pipe);
4080
4081         intel_crtc_enable_planes(crtc);
4082 }
4083
4084 /* IPS only exists on ULT machines and is tied to pipe A. */
4085 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4086 {
4087         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4088 }
4089
4090 /*
4091  * This implements the workaround described in the "notes" section of the mode
4092  * set sequence documentation. When going from no pipes or single pipe to
4093  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4094  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4095  */
4096 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4097 {
4098         struct drm_device *dev = crtc->base.dev;
4099         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4100
4101         /* We want to get the other_active_crtc only if there's only 1 other
4102          * active crtc. */
4103         for_each_intel_crtc(dev, crtc_it) {
4104                 if (!crtc_it->active || crtc_it == crtc)
4105                         continue;
4106
4107                 if (other_active_crtc)
4108                         return;
4109
4110                 other_active_crtc = crtc_it;
4111         }
4112         if (!other_active_crtc)
4113                 return;
4114
4115         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4116         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4117 }
4118
4119 static void haswell_crtc_enable(struct drm_crtc *crtc)
4120 {
4121         struct drm_device *dev = crtc->dev;
4122         struct drm_i915_private *dev_priv = dev->dev_private;
4123         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4124         struct intel_encoder *encoder;
4125         int pipe = intel_crtc->pipe;
4126         enum plane plane = intel_crtc->plane;
4127
4128         WARN_ON(!crtc->enabled);
4129
4130         if (intel_crtc->active)
4131                 return;
4132
4133         if (intel_crtc->config.has_dp_encoder)
4134                 intel_dp_set_m_n(intel_crtc);
4135
4136         intel_set_pipe_timings(intel_crtc);
4137
4138         if (intel_crtc->config.has_pch_encoder) {
4139                 intel_cpu_transcoder_set_m_n(intel_crtc,
4140                                              &intel_crtc->config.fdi_m_n);
4141         }
4142
4143         haswell_set_pipeconf(crtc);
4144
4145         intel_set_pipe_csc(crtc);
4146
4147         /* Set up the display plane register */
4148         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4149         POSTING_READ(DSPCNTR(plane));
4150
4151         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4152                                                crtc->x, crtc->y);
4153
4154         intel_crtc->active = true;
4155
4156         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4157         if (intel_crtc->config.has_pch_encoder)
4158                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4159
4160         if (intel_crtc->config.has_pch_encoder)
4161                 dev_priv->display.fdi_link_train(crtc);
4162
4163         for_each_encoder_on_crtc(dev, crtc, encoder)
4164                 if (encoder->pre_enable)
4165                         encoder->pre_enable(encoder);
4166
4167         intel_ddi_enable_pipe_clock(intel_crtc);
4168
4169         ironlake_pfit_enable(intel_crtc);
4170
4171         /*
4172          * On ILK+ LUT must be loaded before the pipe is running but with
4173          * clocks enabled
4174          */
4175         intel_crtc_load_lut(crtc);
4176
4177         intel_ddi_set_pipe_settings(crtc);
4178         intel_ddi_enable_transcoder_func(crtc);
4179
4180         intel_update_watermarks(crtc);
4181         intel_enable_pipe(intel_crtc);
4182
4183         if (intel_crtc->config.has_pch_encoder)
4184                 lpt_pch_enable(crtc);
4185
4186         for_each_encoder_on_crtc(dev, crtc, encoder) {
4187                 encoder->enable(encoder);
4188                 intel_opregion_notify_encoder(encoder, true);
4189         }
4190
4191         /* If we change the relative order between pipe/planes enabling, we need
4192          * to change the workaround. */
4193         haswell_mode_set_planes_workaround(intel_crtc);
4194         intel_crtc_enable_planes(crtc);
4195 }
4196
4197 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4198 {
4199         struct drm_device *dev = crtc->base.dev;
4200         struct drm_i915_private *dev_priv = dev->dev_private;
4201         int pipe = crtc->pipe;
4202
4203         /* To avoid upsetting the power well on haswell only disable the pfit if
4204          * it's in use. The hw state code will make sure we get this right. */
4205         if (crtc->config.pch_pfit.enabled) {
4206                 I915_WRITE(PF_CTL(pipe), 0);
4207                 I915_WRITE(PF_WIN_POS(pipe), 0);
4208                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4209         }
4210 }
4211
4212 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4213 {
4214         struct drm_device *dev = crtc->dev;
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217         struct intel_encoder *encoder;
4218         int pipe = intel_crtc->pipe;
4219         u32 reg, temp;
4220
4221         if (!intel_crtc->active)
4222                 return;
4223
4224         intel_crtc_disable_planes(crtc);
4225
4226         for_each_encoder_on_crtc(dev, crtc, encoder)
4227                 encoder->disable(encoder);
4228
4229         if (intel_crtc->config.has_pch_encoder)
4230                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4231
4232         intel_disable_pipe(dev_priv, pipe);
4233
4234         ironlake_pfit_disable(intel_crtc);
4235
4236         for_each_encoder_on_crtc(dev, crtc, encoder)
4237                 if (encoder->post_disable)
4238                         encoder->post_disable(encoder);
4239
4240         if (intel_crtc->config.has_pch_encoder) {
4241                 ironlake_fdi_disable(crtc);
4242
4243                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4244                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4245
4246                 if (HAS_PCH_CPT(dev)) {
4247                         /* disable TRANS_DP_CTL */
4248                         reg = TRANS_DP_CTL(pipe);
4249                         temp = I915_READ(reg);
4250                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4251                                   TRANS_DP_PORT_SEL_MASK);
4252                         temp |= TRANS_DP_PORT_SEL_NONE;
4253                         I915_WRITE(reg, temp);
4254
4255                         /* disable DPLL_SEL */
4256                         temp = I915_READ(PCH_DPLL_SEL);
4257                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4258                         I915_WRITE(PCH_DPLL_SEL, temp);
4259                 }
4260
4261                 /* disable PCH DPLL */
4262                 intel_disable_shared_dpll(intel_crtc);
4263
4264                 ironlake_fdi_pll_disable(intel_crtc);
4265         }
4266
4267         intel_crtc->active = false;
4268         intel_update_watermarks(crtc);
4269
4270         mutex_lock(&dev->struct_mutex);
4271         intel_update_fbc(dev);
4272         mutex_unlock(&dev->struct_mutex);
4273 }
4274
4275 static void haswell_crtc_disable(struct drm_crtc *crtc)
4276 {
4277         struct drm_device *dev = crtc->dev;
4278         struct drm_i915_private *dev_priv = dev->dev_private;
4279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4280         struct intel_encoder *encoder;
4281         int pipe = intel_crtc->pipe;
4282         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4283
4284         if (!intel_crtc->active)
4285                 return;
4286
4287         intel_crtc_disable_planes(crtc);
4288
4289         for_each_encoder_on_crtc(dev, crtc, encoder) {
4290                 intel_opregion_notify_encoder(encoder, false);
4291                 encoder->disable(encoder);
4292         }
4293
4294         if (intel_crtc->config.has_pch_encoder)
4295                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4296         intel_disable_pipe(dev_priv, pipe);
4297
4298         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4299
4300         ironlake_pfit_disable(intel_crtc);
4301
4302         intel_ddi_disable_pipe_clock(intel_crtc);
4303
4304         for_each_encoder_on_crtc(dev, crtc, encoder)
4305                 if (encoder->post_disable)
4306                         encoder->post_disable(encoder);
4307
4308         if (intel_crtc->config.has_pch_encoder) {
4309                 lpt_disable_pch_transcoder(dev_priv);
4310                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4311                 intel_ddi_fdi_disable(crtc);
4312         }
4313
4314         intel_crtc->active = false;
4315         intel_update_watermarks(crtc);
4316
4317         mutex_lock(&dev->struct_mutex);
4318         intel_update_fbc(dev);
4319         mutex_unlock(&dev->struct_mutex);
4320 }
4321
4322 static void ironlake_crtc_off(struct drm_crtc *crtc)
4323 {
4324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4325         intel_put_shared_dpll(intel_crtc);
4326 }
4327
4328 static void haswell_crtc_off(struct drm_crtc *crtc)
4329 {
4330         intel_ddi_put_crtc_pll(crtc);
4331 }
4332
4333 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4334 {
4335         struct drm_device *dev = crtc->base.dev;
4336         struct drm_i915_private *dev_priv = dev->dev_private;
4337         struct intel_crtc_config *pipe_config = &crtc->config;
4338
4339         if (!crtc->config.gmch_pfit.control)
4340                 return;
4341
4342         /*
4343          * The panel fitter should only be adjusted whilst the pipe is disabled,
4344          * according to register description and PRM.
4345          */
4346         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4347         assert_pipe_disabled(dev_priv, crtc->pipe);
4348
4349         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4350         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4351
4352         /* Border color in case we don't scale up to the full screen. Black by
4353          * default, change to something else for debugging. */
4354         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4355 }
4356
4357 #define for_each_power_domain(domain, mask)                             \
4358         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4359                 if ((1 << (domain)) & (mask))
4360
4361 enum intel_display_power_domain
4362 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4363 {
4364         struct drm_device *dev = intel_encoder->base.dev;
4365         struct intel_digital_port *intel_dig_port;
4366
4367         switch (intel_encoder->type) {
4368         case INTEL_OUTPUT_UNKNOWN:
4369                 /* Only DDI platforms should ever use this output type */
4370                 WARN_ON_ONCE(!HAS_DDI(dev));
4371         case INTEL_OUTPUT_DISPLAYPORT:
4372         case INTEL_OUTPUT_HDMI:
4373         case INTEL_OUTPUT_EDP:
4374                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4375                 switch (intel_dig_port->port) {
4376                 case PORT_A:
4377                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4378                 case PORT_B:
4379                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4380                 case PORT_C:
4381                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4382                 case PORT_D:
4383                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4384                 default:
4385                         WARN_ON_ONCE(1);
4386                         return POWER_DOMAIN_PORT_OTHER;
4387                 }
4388         case INTEL_OUTPUT_ANALOG:
4389                 return POWER_DOMAIN_PORT_CRT;
4390         case INTEL_OUTPUT_DSI:
4391                 return POWER_DOMAIN_PORT_DSI;
4392         default:
4393                 return POWER_DOMAIN_PORT_OTHER;
4394         }
4395 }
4396
4397 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4398 {
4399         struct drm_device *dev = crtc->dev;
4400         struct intel_encoder *intel_encoder;
4401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4402         enum pipe pipe = intel_crtc->pipe;
4403         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4404         unsigned long mask;
4405         enum transcoder transcoder;
4406
4407         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4408
4409         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4410         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4411         if (pfit_enabled)
4412                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4413
4414         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4415                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4416
4417         return mask;
4418 }
4419
4420 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4421                                   bool enable)
4422 {
4423         if (dev_priv->power_domains.init_power_on == enable)
4424                 return;
4425
4426         if (enable)
4427                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4428         else
4429                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4430
4431         dev_priv->power_domains.init_power_on = enable;
4432 }
4433
4434 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4435 {
4436         struct drm_i915_private *dev_priv = dev->dev_private;
4437         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4438         struct intel_crtc *crtc;
4439
4440         /*
4441          * First get all needed power domains, then put all unneeded, to avoid
4442          * any unnecessary toggling of the power wells.
4443          */
4444         for_each_intel_crtc(dev, crtc) {
4445                 enum intel_display_power_domain domain;
4446
4447                 if (!crtc->base.enabled)
4448                         continue;
4449
4450                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4451
4452                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4453                         intel_display_power_get(dev_priv, domain);
4454         }
4455
4456         for_each_intel_crtc(dev, crtc) {
4457                 enum intel_display_power_domain domain;
4458
4459                 for_each_power_domain(domain, crtc->enabled_power_domains)
4460                         intel_display_power_put(dev_priv, domain);
4461
4462                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4463         }
4464
4465         intel_display_set_init_power(dev_priv, false);
4466 }
4467
4468 /* returns HPLL frequency in kHz */
4469 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4470 {
4471         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4472
4473         /* Obtain SKU information */
4474         mutex_lock(&dev_priv->dpio_lock);
4475         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4476                 CCK_FUSE_HPLL_FREQ_MASK;
4477         mutex_unlock(&dev_priv->dpio_lock);
4478
4479         return vco_freq[hpll_freq] * 1000;
4480 }
4481
4482 /* Adjust CDclk dividers to allow high res or save power if possible */
4483 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4484 {
4485         struct drm_i915_private *dev_priv = dev->dev_private;
4486         u32 val, cmd;
4487
4488         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4489         dev_priv->vlv_cdclk_freq = cdclk;
4490
4491         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4492                 cmd = 2;
4493         else if (cdclk == 266667)
4494                 cmd = 1;
4495         else
4496                 cmd = 0;
4497
4498         mutex_lock(&dev_priv->rps.hw_lock);
4499         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4500         val &= ~DSPFREQGUAR_MASK;
4501         val |= (cmd << DSPFREQGUAR_SHIFT);
4502         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4503         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4504                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4505                      50)) {
4506                 DRM_ERROR("timed out waiting for CDclk change\n");
4507         }
4508         mutex_unlock(&dev_priv->rps.hw_lock);
4509
4510         if (cdclk == 400000) {
4511                 u32 divider, vco;
4512
4513                 vco = valleyview_get_vco(dev_priv);
4514                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4515
4516                 mutex_lock(&dev_priv->dpio_lock);
4517                 /* adjust cdclk divider */
4518                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4519                 val &= ~DISPLAY_FREQUENCY_VALUES;
4520                 val |= divider;
4521                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4522                 mutex_unlock(&dev_priv->dpio_lock);
4523         }
4524
4525         mutex_lock(&dev_priv->dpio_lock);
4526         /* adjust self-refresh exit latency value */
4527         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4528         val &= ~0x7f;
4529
4530         /*
4531          * For high bandwidth configs, we set a higher latency in the bunit
4532          * so that the core display fetch happens in time to avoid underruns.
4533          */
4534         if (cdclk == 400000)
4535                 val |= 4500 / 250; /* 4.5 usec */
4536         else
4537                 val |= 3000 / 250; /* 3.0 usec */
4538         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4539         mutex_unlock(&dev_priv->dpio_lock);
4540
4541         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4542         intel_i2c_reset(dev);
4543 }
4544
4545 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4546                                  int max_pixclk)
4547 {
4548         int vco = valleyview_get_vco(dev_priv);
4549         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4550
4551         /*
4552          * Really only a few cases to deal with, as only 4 CDclks are supported:
4553          *   200MHz
4554          *   267MHz
4555          *   320/333MHz (depends on HPLL freq)
4556          *   400MHz
4557          * So we check to see whether we're above 90% of the lower bin and
4558          * adjust if needed.
4559          */
4560         if (max_pixclk > freq_320*9/10)
4561                 return 400000;
4562         else if (max_pixclk > 266667*9/10)
4563                 return freq_320;
4564         else
4565                 return 266667;
4566         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4567 }
4568
4569 /* compute the max pixel clock for new configuration */
4570 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4571 {
4572         struct drm_device *dev = dev_priv->dev;
4573         struct intel_crtc *intel_crtc;
4574         int max_pixclk = 0;
4575
4576         for_each_intel_crtc(dev, intel_crtc) {
4577                 if (intel_crtc->new_enabled)
4578                         max_pixclk = max(max_pixclk,
4579                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4580         }
4581
4582         return max_pixclk;
4583 }
4584
4585 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4586                                             unsigned *prepare_pipes)
4587 {
4588         struct drm_i915_private *dev_priv = dev->dev_private;
4589         struct intel_crtc *intel_crtc;
4590         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4591
4592         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4593             dev_priv->vlv_cdclk_freq)
4594                 return;
4595
4596         /* disable/enable all currently active pipes while we change cdclk */
4597         for_each_intel_crtc(dev, intel_crtc)
4598                 if (intel_crtc->base.enabled)
4599                         *prepare_pipes |= (1 << intel_crtc->pipe);
4600 }
4601
4602 static void valleyview_modeset_global_resources(struct drm_device *dev)
4603 {
4604         struct drm_i915_private *dev_priv = dev->dev_private;
4605         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4606         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4607
4608         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4609                 valleyview_set_cdclk(dev, req_cdclk);
4610         modeset_update_crtc_power_domains(dev);
4611 }
4612
4613 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4614 {
4615         struct drm_device *dev = crtc->dev;
4616         struct drm_i915_private *dev_priv = dev->dev_private;
4617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4618         struct intel_encoder *encoder;
4619         int pipe = intel_crtc->pipe;
4620         int plane = intel_crtc->plane;
4621         bool is_dsi;
4622         u32 dspcntr;
4623
4624         WARN_ON(!crtc->enabled);
4625
4626         if (intel_crtc->active)
4627                 return;
4628
4629         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4630
4631         if (!is_dsi && !IS_CHERRYVIEW(dev))
4632                 vlv_prepare_pll(intel_crtc);
4633
4634         /* Set up the display plane register */
4635         dspcntr = DISPPLANE_GAMMA_ENABLE;
4636
4637         if (intel_crtc->config.has_dp_encoder)
4638                 intel_dp_set_m_n(intel_crtc);
4639
4640         intel_set_pipe_timings(intel_crtc);
4641
4642         /* pipesrc and dspsize control the size that is scaled from,
4643          * which should always be the user's requested size.
4644          */
4645         I915_WRITE(DSPSIZE(plane),
4646                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4647                    (intel_crtc->config.pipe_src_w - 1));
4648         I915_WRITE(DSPPOS(plane), 0);
4649
4650         i9xx_set_pipeconf(intel_crtc);
4651
4652         I915_WRITE(DSPCNTR(plane), dspcntr);
4653         POSTING_READ(DSPCNTR(plane));
4654
4655         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4656                                                crtc->x, crtc->y);
4657
4658         intel_crtc->active = true;
4659
4660         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4661
4662         for_each_encoder_on_crtc(dev, crtc, encoder)
4663                 if (encoder->pre_pll_enable)
4664                         encoder->pre_pll_enable(encoder);
4665
4666         if (!is_dsi) {
4667                 if (IS_CHERRYVIEW(dev))
4668                         chv_enable_pll(intel_crtc);
4669                 else
4670                         vlv_enable_pll(intel_crtc);
4671         }
4672
4673         for_each_encoder_on_crtc(dev, crtc, encoder)
4674                 if (encoder->pre_enable)
4675                         encoder->pre_enable(encoder);
4676
4677         i9xx_pfit_enable(intel_crtc);
4678
4679         intel_crtc_load_lut(crtc);
4680
4681         intel_update_watermarks(crtc);
4682         intel_enable_pipe(intel_crtc);
4683
4684         for_each_encoder_on_crtc(dev, crtc, encoder)
4685                 encoder->enable(encoder);
4686
4687         intel_crtc_enable_planes(crtc);
4688
4689         /* Underruns don't raise interrupts, so check manually. */
4690         i9xx_check_fifo_underruns(dev);
4691 }
4692
4693 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4694 {
4695         struct drm_device *dev = crtc->base.dev;
4696         struct drm_i915_private *dev_priv = dev->dev_private;
4697
4698         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4699         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4700 }
4701
4702 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4703 {
4704         struct drm_device *dev = crtc->dev;
4705         struct drm_i915_private *dev_priv = dev->dev_private;
4706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4707         struct intel_encoder *encoder;
4708         int pipe = intel_crtc->pipe;
4709         int plane = intel_crtc->plane;
4710         u32 dspcntr;
4711
4712         WARN_ON(!crtc->enabled);
4713
4714         if (intel_crtc->active)
4715                 return;
4716
4717         i9xx_set_pll_dividers(intel_crtc);
4718
4719         /* Set up the display plane register */
4720         dspcntr = DISPPLANE_GAMMA_ENABLE;
4721
4722         if (pipe == 0)
4723                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4724         else
4725                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4726
4727         if (intel_crtc->config.has_dp_encoder)
4728                 intel_dp_set_m_n(intel_crtc);
4729
4730         intel_set_pipe_timings(intel_crtc);
4731
4732         /* pipesrc and dspsize control the size that is scaled from,
4733          * which should always be the user's requested size.
4734          */
4735         I915_WRITE(DSPSIZE(plane),
4736                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4737                    (intel_crtc->config.pipe_src_w - 1));
4738         I915_WRITE(DSPPOS(plane), 0);
4739
4740         i9xx_set_pipeconf(intel_crtc);
4741
4742         I915_WRITE(DSPCNTR(plane), dspcntr);
4743         POSTING_READ(DSPCNTR(plane));
4744
4745         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4746                                                crtc->x, crtc->y);
4747
4748         intel_crtc->active = true;
4749
4750         if (!IS_GEN2(dev))
4751                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4752
4753         for_each_encoder_on_crtc(dev, crtc, encoder)
4754                 if (encoder->pre_enable)
4755                         encoder->pre_enable(encoder);
4756
4757         i9xx_enable_pll(intel_crtc);
4758
4759         i9xx_pfit_enable(intel_crtc);
4760
4761         intel_crtc_load_lut(crtc);
4762
4763         intel_update_watermarks(crtc);
4764         intel_enable_pipe(intel_crtc);
4765
4766         for_each_encoder_on_crtc(dev, crtc, encoder)
4767                 encoder->enable(encoder);
4768
4769         intel_crtc_enable_planes(crtc);
4770
4771         /*
4772          * Gen2 reports pipe underruns whenever all planes are disabled.
4773          * So don't enable underrun reporting before at least some planes
4774          * are enabled.
4775          * FIXME: Need to fix the logic to work when we turn off all planes
4776          * but leave the pipe running.
4777          */
4778         if (IS_GEN2(dev))
4779                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4780
4781         /* Underruns don't raise interrupts, so check manually. */
4782         i9xx_check_fifo_underruns(dev);
4783 }
4784
4785 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4786 {
4787         struct drm_device *dev = crtc->base.dev;
4788         struct drm_i915_private *dev_priv = dev->dev_private;
4789
4790         if (!crtc->config.gmch_pfit.control)
4791                 return;
4792
4793         assert_pipe_disabled(dev_priv, crtc->pipe);
4794
4795         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4796                          I915_READ(PFIT_CONTROL));
4797         I915_WRITE(PFIT_CONTROL, 0);
4798 }
4799
4800 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4801 {
4802         struct drm_device *dev = crtc->dev;
4803         struct drm_i915_private *dev_priv = dev->dev_private;
4804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4805         struct intel_encoder *encoder;
4806         int pipe = intel_crtc->pipe;
4807
4808         if (!intel_crtc->active)
4809                 return;
4810
4811         /*
4812          * Gen2 reports pipe underruns whenever all planes are disabled.
4813          * So diasble underrun reporting before all the planes get disabled.
4814          * FIXME: Need to fix the logic to work when we turn off all planes
4815          * but leave the pipe running.
4816          */
4817         if (IS_GEN2(dev))
4818                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4819
4820         intel_crtc_disable_planes(crtc);
4821
4822         for_each_encoder_on_crtc(dev, crtc, encoder)
4823                 encoder->disable(encoder);
4824
4825         /*
4826          * On gen2 planes are double buffered but the pipe isn't, so we must
4827          * wait for planes to fully turn off before disabling the pipe.
4828          */
4829         if (IS_GEN2(dev))
4830                 intel_wait_for_vblank(dev, pipe);
4831
4832         intel_disable_pipe(dev_priv, pipe);
4833
4834         i9xx_pfit_disable(intel_crtc);
4835
4836         for_each_encoder_on_crtc(dev, crtc, encoder)
4837                 if (encoder->post_disable)
4838                         encoder->post_disable(encoder);
4839
4840         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4841                 if (IS_CHERRYVIEW(dev))
4842                         chv_disable_pll(dev_priv, pipe);
4843                 else if (IS_VALLEYVIEW(dev))
4844                         vlv_disable_pll(dev_priv, pipe);
4845                 else
4846                         i9xx_disable_pll(dev_priv, pipe);
4847         }
4848
4849         if (!IS_GEN2(dev))
4850                 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4851
4852         intel_crtc->active = false;
4853         intel_update_watermarks(crtc);
4854
4855         mutex_lock(&dev->struct_mutex);
4856         intel_update_fbc(dev);
4857         mutex_unlock(&dev->struct_mutex);
4858 }
4859
4860 static void i9xx_crtc_off(struct drm_crtc *crtc)
4861 {
4862 }
4863
4864 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4865                                     bool enabled)
4866 {
4867         struct drm_device *dev = crtc->dev;
4868         struct drm_i915_master_private *master_priv;
4869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4870         int pipe = intel_crtc->pipe;
4871
4872         if (!dev->primary->master)
4873                 return;
4874
4875         master_priv = dev->primary->master->driver_priv;
4876         if (!master_priv->sarea_priv)
4877                 return;
4878
4879         switch (pipe) {
4880         case 0:
4881                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4882                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4883                 break;
4884         case 1:
4885                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4886                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4887                 break;
4888         default:
4889                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4890                 break;
4891         }
4892 }
4893
4894 /**
4895  * Sets the power management mode of the pipe and plane.
4896  */
4897 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4898 {
4899         struct drm_device *dev = crtc->dev;
4900         struct drm_i915_private *dev_priv = dev->dev_private;
4901         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4902         struct intel_encoder *intel_encoder;
4903         enum intel_display_power_domain domain;
4904         unsigned long domains;
4905         bool enable = false;
4906
4907         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4908                 enable |= intel_encoder->connectors_active;
4909
4910         if (enable) {
4911                 if (!intel_crtc->active) {
4912                         /*
4913                          * FIXME: DDI plls and relevant code isn't converted
4914                          * yet, so do runtime PM for DPMS only for all other
4915                          * platforms for now.
4916                          */
4917                         if (!HAS_DDI(dev)) {
4918                                 domains = get_crtc_power_domains(crtc);
4919                                 for_each_power_domain(domain, domains)
4920                                         intel_display_power_get(dev_priv, domain);
4921                                 intel_crtc->enabled_power_domains = domains;
4922                         }
4923
4924                         dev_priv->display.crtc_enable(crtc);
4925                 }
4926         } else {
4927                 if (intel_crtc->active) {
4928                         dev_priv->display.crtc_disable(crtc);
4929
4930                         if (!HAS_DDI(dev)) {
4931                                 domains = intel_crtc->enabled_power_domains;
4932                                 for_each_power_domain(domain, domains)
4933                                         intel_display_power_put(dev_priv, domain);
4934                                 intel_crtc->enabled_power_domains = 0;
4935                         }
4936                 }
4937         }
4938
4939         intel_crtc_update_sarea(crtc, enable);
4940 }
4941
4942 static void intel_crtc_disable(struct drm_crtc *crtc)
4943 {
4944         struct drm_device *dev = crtc->dev;
4945         struct drm_connector *connector;
4946         struct drm_i915_private *dev_priv = dev->dev_private;
4947         struct drm_i915_gem_object *old_obj;
4948         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4949
4950         /* crtc should still be enabled when we disable it. */
4951         WARN_ON(!crtc->enabled);
4952
4953         dev_priv->display.crtc_disable(crtc);
4954         intel_crtc_update_sarea(crtc, false);
4955         dev_priv->display.off(crtc);
4956
4957         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4958         assert_cursor_disabled(dev_priv, pipe);
4959         assert_pipe_disabled(dev->dev_private, pipe);
4960
4961         if (crtc->primary->fb) {
4962                 old_obj = to_intel_framebuffer(crtc->primary->fb)->obj;
4963                 mutex_lock(&dev->struct_mutex);
4964                 intel_unpin_fb_obj(old_obj);
4965                 i915_gem_track_fb(old_obj, NULL,
4966                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
4967                 mutex_unlock(&dev->struct_mutex);
4968                 crtc->primary->fb = NULL;
4969         }
4970
4971         /* Update computed state. */
4972         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4973                 if (!connector->encoder || !connector->encoder->crtc)
4974                         continue;
4975
4976                 if (connector->encoder->crtc != crtc)
4977                         continue;
4978
4979                 connector->dpms = DRM_MODE_DPMS_OFF;
4980                 to_intel_encoder(connector->encoder)->connectors_active = false;
4981         }
4982 }
4983
4984 void intel_encoder_destroy(struct drm_encoder *encoder)
4985 {
4986         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4987
4988         drm_encoder_cleanup(encoder);
4989         kfree(intel_encoder);
4990 }
4991
4992 /* Simple dpms helper for encoders with just one connector, no cloning and only
4993  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4994  * state of the entire output pipe. */
4995 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4996 {
4997         if (mode == DRM_MODE_DPMS_ON) {
4998                 encoder->connectors_active = true;
4999
5000                 intel_crtc_update_dpms(encoder->base.crtc);
5001         } else {
5002                 encoder->connectors_active = false;
5003
5004                 intel_crtc_update_dpms(encoder->base.crtc);
5005         }
5006 }
5007
5008 /* Cross check the actual hw state with our own modeset state tracking (and it's
5009  * internal consistency). */
5010 static void intel_connector_check_state(struct intel_connector *connector)
5011 {
5012         if (connector->get_hw_state(connector)) {
5013                 struct intel_encoder *encoder = connector->encoder;
5014                 struct drm_crtc *crtc;
5015                 bool encoder_enabled;
5016                 enum pipe pipe;
5017
5018                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5019                               connector->base.base.id,
5020                               connector->base.name);
5021
5022                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5023                      "wrong connector dpms state\n");
5024                 WARN(connector->base.encoder != &encoder->base,
5025                      "active connector not linked to encoder\n");
5026                 WARN(!encoder->connectors_active,
5027                      "encoder->connectors_active not set\n");
5028
5029                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5030                 WARN(!encoder_enabled, "encoder not enabled\n");
5031                 if (WARN_ON(!encoder->base.crtc))
5032                         return;
5033
5034                 crtc = encoder->base.crtc;
5035
5036                 WARN(!crtc->enabled, "crtc not enabled\n");
5037                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5038                 WARN(pipe != to_intel_crtc(crtc)->pipe,
5039                      "encoder active on the wrong pipe\n");
5040         }
5041 }
5042
5043 /* Even simpler default implementation, if there's really no special case to
5044  * consider. */
5045 void intel_connector_dpms(struct drm_connector *connector, int mode)
5046 {
5047         /* All the simple cases only support two dpms states. */
5048         if (mode != DRM_MODE_DPMS_ON)
5049                 mode = DRM_MODE_DPMS_OFF;
5050
5051         if (mode == connector->dpms)
5052                 return;
5053
5054         connector->dpms = mode;
5055
5056         /* Only need to change hw state when actually enabled */
5057         if (connector->encoder)
5058                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5059
5060         intel_modeset_check_state(connector->dev);
5061 }
5062
5063 /* Simple connector->get_hw_state implementation for encoders that support only
5064  * one connector and no cloning and hence the encoder state determines the state
5065  * of the connector. */
5066 bool intel_connector_get_hw_state(struct intel_connector *connector)
5067 {
5068         enum pipe pipe = 0;
5069         struct intel_encoder *encoder = connector->encoder;
5070
5071         return encoder->get_hw_state(encoder, &pipe);
5072 }
5073
5074 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5075                                      struct intel_crtc_config *pipe_config)
5076 {
5077         struct drm_i915_private *dev_priv = dev->dev_private;
5078         struct intel_crtc *pipe_B_crtc =
5079                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5080
5081         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5082                       pipe_name(pipe), pipe_config->fdi_lanes);
5083         if (pipe_config->fdi_lanes > 4) {
5084                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5085                               pipe_name(pipe), pipe_config->fdi_lanes);
5086                 return false;
5087         }
5088
5089         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5090                 if (pipe_config->fdi_lanes > 2) {
5091                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5092                                       pipe_config->fdi_lanes);
5093                         return false;
5094                 } else {
5095                         return true;
5096                 }
5097         }
5098
5099         if (INTEL_INFO(dev)->num_pipes == 2)
5100                 return true;
5101
5102         /* Ivybridge 3 pipe is really complicated */
5103         switch (pipe) {
5104         case PIPE_A:
5105                 return true;
5106         case PIPE_B:
5107                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5108                     pipe_config->fdi_lanes > 2) {
5109                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5110                                       pipe_name(pipe), pipe_config->fdi_lanes);
5111                         return false;
5112                 }
5113                 return true;
5114         case PIPE_C:
5115                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5116                     pipe_B_crtc->config.fdi_lanes <= 2) {
5117                         if (pipe_config->fdi_lanes > 2) {
5118                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5119                                               pipe_name(pipe), pipe_config->fdi_lanes);
5120                                 return false;
5121                         }
5122                 } else {
5123                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5124                         return false;
5125                 }
5126                 return true;
5127         default:
5128                 BUG();
5129         }
5130 }
5131
5132 #define RETRY 1
5133 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5134                                        struct intel_crtc_config *pipe_config)
5135 {
5136         struct drm_device *dev = intel_crtc->base.dev;
5137         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5138         int lane, link_bw, fdi_dotclock;
5139         bool setup_ok, needs_recompute = false;
5140
5141 retry:
5142         /* FDI is a binary signal running at ~2.7GHz, encoding
5143          * each output octet as 10 bits. The actual frequency
5144          * is stored as a divider into a 100MHz clock, and the
5145          * mode pixel clock is stored in units of 1KHz.
5146          * Hence the bw of each lane in terms of the mode signal
5147          * is:
5148          */
5149         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5150
5151         fdi_dotclock = adjusted_mode->crtc_clock;
5152
5153         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5154                                            pipe_config->pipe_bpp);
5155
5156         pipe_config->fdi_lanes = lane;
5157
5158         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5159                                link_bw, &pipe_config->fdi_m_n);
5160
5161         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5162                                             intel_crtc->pipe, pipe_config);
5163         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5164                 pipe_config->pipe_bpp -= 2*3;
5165                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5166                               pipe_config->pipe_bpp);
5167                 needs_recompute = true;
5168                 pipe_config->bw_constrained = true;
5169
5170                 goto retry;
5171         }
5172
5173         if (needs_recompute)
5174                 return RETRY;
5175
5176         return setup_ok ? 0 : -EINVAL;
5177 }
5178
5179 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5180                                    struct intel_crtc_config *pipe_config)
5181 {
5182         pipe_config->ips_enabled = i915.enable_ips &&
5183                                    hsw_crtc_supports_ips(crtc) &&
5184                                    pipe_config->pipe_bpp <= 24;
5185 }
5186
5187 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5188                                      struct intel_crtc_config *pipe_config)
5189 {
5190         struct drm_device *dev = crtc->base.dev;
5191         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5192
5193         /* FIXME should check pixel clock limits on all platforms */
5194         if (INTEL_INFO(dev)->gen < 4) {
5195                 struct drm_i915_private *dev_priv = dev->dev_private;
5196                 int clock_limit =
5197                         dev_priv->display.get_display_clock_speed(dev);
5198
5199                 /*
5200                  * Enable pixel doubling when the dot clock
5201                  * is > 90% of the (display) core speed.
5202                  *
5203                  * GDG double wide on either pipe,
5204                  * otherwise pipe A only.
5205                  */
5206                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5207                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5208                         clock_limit *= 2;
5209                         pipe_config->double_wide = true;
5210                 }
5211
5212                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5213                         return -EINVAL;
5214         }
5215
5216         /*
5217          * Pipe horizontal size must be even in:
5218          * - DVO ganged mode
5219          * - LVDS dual channel mode
5220          * - Double wide pipe
5221          */
5222         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5223              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5224                 pipe_config->pipe_src_w &= ~1;
5225
5226         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5227          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5228          */
5229         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5230                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5231                 return -EINVAL;
5232
5233         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5234                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5235         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5236                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5237                  * for lvds. */
5238                 pipe_config->pipe_bpp = 8*3;
5239         }
5240
5241         if (HAS_IPS(dev))
5242                 hsw_compute_ips_config(crtc, pipe_config);
5243
5244         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5245          * clock survives for now. */
5246         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5247                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5248
5249         if (pipe_config->has_pch_encoder)
5250                 return ironlake_fdi_compute_config(crtc, pipe_config);
5251
5252         return 0;
5253 }
5254
5255 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5256 {
5257         struct drm_i915_private *dev_priv = dev->dev_private;
5258         int vco = valleyview_get_vco(dev_priv);
5259         u32 val;
5260         int divider;
5261
5262         mutex_lock(&dev_priv->dpio_lock);
5263         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5264         mutex_unlock(&dev_priv->dpio_lock);
5265
5266         divider = val & DISPLAY_FREQUENCY_VALUES;
5267
5268         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5269 }
5270
5271 static int i945_get_display_clock_speed(struct drm_device *dev)
5272 {
5273         return 400000;
5274 }
5275
5276 static int i915_get_display_clock_speed(struct drm_device *dev)
5277 {
5278         return 333000;
5279 }
5280
5281 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5282 {
5283         return 200000;
5284 }
5285
5286 static int pnv_get_display_clock_speed(struct drm_device *dev)
5287 {
5288         u16 gcfgc = 0;
5289
5290         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5291
5292         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5293         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5294                 return 267000;
5295         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5296                 return 333000;
5297         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5298                 return 444000;
5299         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5300                 return 200000;
5301         default:
5302                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5303         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5304                 return 133000;
5305         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5306                 return 167000;
5307         }
5308 }
5309
5310 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5311 {
5312         u16 gcfgc = 0;
5313
5314         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5315
5316         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5317                 return 133000;
5318         else {
5319                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5320                 case GC_DISPLAY_CLOCK_333_MHZ:
5321                         return 333000;
5322                 default:
5323                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5324                         return 190000;
5325                 }
5326         }
5327 }
5328
5329 static int i865_get_display_clock_speed(struct drm_device *dev)
5330 {
5331         return 266000;
5332 }
5333
5334 static int i855_get_display_clock_speed(struct drm_device *dev)
5335 {
5336         u16 hpllcc = 0;
5337         /* Assume that the hardware is in the high speed state.  This
5338          * should be the default.
5339          */
5340         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5341         case GC_CLOCK_133_200:
5342         case GC_CLOCK_100_200:
5343                 return 200000;
5344         case GC_CLOCK_166_250:
5345                 return 250000;
5346         case GC_CLOCK_100_133:
5347                 return 133000;
5348         }
5349
5350         /* Shouldn't happen */
5351         return 0;
5352 }
5353
5354 static int i830_get_display_clock_speed(struct drm_device *dev)
5355 {
5356         return 133000;
5357 }
5358
5359 static void
5360 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5361 {
5362         while (*num > DATA_LINK_M_N_MASK ||
5363                *den > DATA_LINK_M_N_MASK) {
5364                 *num >>= 1;
5365                 *den >>= 1;
5366         }
5367 }
5368
5369 static void compute_m_n(unsigned int m, unsigned int n,
5370                         uint32_t *ret_m, uint32_t *ret_n)
5371 {
5372         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5373         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5374         intel_reduce_m_n_ratio(ret_m, ret_n);
5375 }
5376
5377 void
5378 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5379                        int pixel_clock, int link_clock,
5380                        struct intel_link_m_n *m_n)
5381 {
5382         m_n->tu = 64;
5383
5384         compute_m_n(bits_per_pixel * pixel_clock,
5385                     link_clock * nlanes * 8,
5386                     &m_n->gmch_m, &m_n->gmch_n);
5387
5388         compute_m_n(pixel_clock, link_clock,
5389                     &m_n->link_m, &m_n->link_n);
5390 }
5391
5392 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5393 {
5394         if (i915.panel_use_ssc >= 0)
5395                 return i915.panel_use_ssc != 0;
5396         return dev_priv->vbt.lvds_use_ssc
5397                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5398 }
5399
5400 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5401 {
5402         struct drm_device *dev = crtc->dev;
5403         struct drm_i915_private *dev_priv = dev->dev_private;
5404         int refclk;
5405
5406         if (IS_VALLEYVIEW(dev)) {
5407                 refclk = 100000;
5408         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5409             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5410                 refclk = dev_priv->vbt.lvds_ssc_freq;
5411                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5412         } else if (!IS_GEN2(dev)) {
5413                 refclk = 96000;
5414         } else {
5415                 refclk = 48000;
5416         }
5417
5418         return refclk;
5419 }
5420
5421 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5422 {
5423         return (1 << dpll->n) << 16 | dpll->m2;
5424 }
5425
5426 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5427 {
5428         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5429 }
5430
5431 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5432                                      intel_clock_t *reduced_clock)
5433 {
5434         struct drm_device *dev = crtc->base.dev;
5435         u32 fp, fp2 = 0;
5436
5437         if (IS_PINEVIEW(dev)) {
5438                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5439                 if (reduced_clock)
5440                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5441         } else {
5442                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5443                 if (reduced_clock)
5444                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5445         }
5446
5447         crtc->config.dpll_hw_state.fp0 = fp;
5448
5449         crtc->lowfreq_avail = false;
5450         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5451             reduced_clock && i915.powersave) {
5452                 crtc->config.dpll_hw_state.fp1 = fp2;
5453                 crtc->lowfreq_avail = true;
5454         } else {
5455                 crtc->config.dpll_hw_state.fp1 = fp;
5456         }
5457 }
5458
5459 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5460                 pipe)
5461 {
5462         u32 reg_val;
5463
5464         /*
5465          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5466          * and set it to a reasonable value instead.
5467          */
5468         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5469         reg_val &= 0xffffff00;
5470         reg_val |= 0x00000030;
5471         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5472
5473         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5474         reg_val &= 0x8cffffff;
5475         reg_val = 0x8c000000;
5476         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5477
5478         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5479         reg_val &= 0xffffff00;
5480         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5481
5482         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5483         reg_val &= 0x00ffffff;
5484         reg_val |= 0xb0000000;
5485         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5486 }
5487
5488 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5489                                          struct intel_link_m_n *m_n)
5490 {
5491         struct drm_device *dev = crtc->base.dev;
5492         struct drm_i915_private *dev_priv = dev->dev_private;
5493         int pipe = crtc->pipe;
5494
5495         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5496         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5497         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5498         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5499 }
5500
5501 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5502                                          struct intel_link_m_n *m_n)
5503 {
5504         struct drm_device *dev = crtc->base.dev;
5505         struct drm_i915_private *dev_priv = dev->dev_private;
5506         int pipe = crtc->pipe;
5507         enum transcoder transcoder = crtc->config.cpu_transcoder;
5508
5509         if (INTEL_INFO(dev)->gen >= 5) {
5510                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5511                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5512                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5513                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5514         } else {
5515                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5516                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5517                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5518                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5519         }
5520 }
5521
5522 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5523 {
5524         if (crtc->config.has_pch_encoder)
5525                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5526         else
5527                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5528 }
5529
5530 static void vlv_update_pll(struct intel_crtc *crtc)
5531 {
5532         u32 dpll, dpll_md;
5533
5534         /*
5535          * Enable DPIO clock input. We should never disable the reference
5536          * clock for pipe B, since VGA hotplug / manual detection depends
5537          * on it.
5538          */
5539         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5540                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5541         /* We should never disable this, set it here for state tracking */
5542         if (crtc->pipe == PIPE_B)
5543                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5544         dpll |= DPLL_VCO_ENABLE;
5545         crtc->config.dpll_hw_state.dpll = dpll;
5546
5547         dpll_md = (crtc->config.pixel_multiplier - 1)
5548                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5549         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5550 }
5551
5552 static void vlv_prepare_pll(struct intel_crtc *crtc)
5553 {
5554         struct drm_device *dev = crtc->base.dev;
5555         struct drm_i915_private *dev_priv = dev->dev_private;
5556         int pipe = crtc->pipe;
5557         u32 mdiv;
5558         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5559         u32 coreclk, reg_val;
5560
5561         mutex_lock(&dev_priv->dpio_lock);
5562
5563         bestn = crtc->config.dpll.n;
5564         bestm1 = crtc->config.dpll.m1;
5565         bestm2 = crtc->config.dpll.m2;
5566         bestp1 = crtc->config.dpll.p1;
5567         bestp2 = crtc->config.dpll.p2;
5568
5569         /* See eDP HDMI DPIO driver vbios notes doc */
5570
5571         /* PLL B needs special handling */
5572         if (pipe == PIPE_B)
5573                 vlv_pllb_recal_opamp(dev_priv, pipe);
5574
5575         /* Set up Tx target for periodic Rcomp update */
5576         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5577
5578         /* Disable target IRef on PLL */
5579         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5580         reg_val &= 0x00ffffff;
5581         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5582
5583         /* Disable fast lock */
5584         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5585
5586         /* Set idtafcrecal before PLL is enabled */
5587         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5588         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5589         mdiv |= ((bestn << DPIO_N_SHIFT));
5590         mdiv |= (1 << DPIO_K_SHIFT);
5591
5592         /*
5593          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5594          * but we don't support that).
5595          * Note: don't use the DAC post divider as it seems unstable.
5596          */
5597         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5598         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5599
5600         mdiv |= DPIO_ENABLE_CALIBRATION;
5601         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5602
5603         /* Set HBR and RBR LPF coefficients */
5604         if (crtc->config.port_clock == 162000 ||
5605             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5606             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5607                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5608                                  0x009f0003);
5609         else
5610                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5611                                  0x00d0000f);
5612
5613         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5614             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5615                 /* Use SSC source */
5616                 if (pipe == PIPE_A)
5617                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5618                                          0x0df40000);
5619                 else
5620                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5621                                          0x0df70000);
5622         } else { /* HDMI or VGA */
5623                 /* Use bend source */
5624                 if (pipe == PIPE_A)
5625                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5626                                          0x0df70000);
5627                 else
5628                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5629                                          0x0df40000);
5630         }
5631
5632         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5633         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5634         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5635             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5636                 coreclk |= 0x01000000;
5637         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5638
5639         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5640         mutex_unlock(&dev_priv->dpio_lock);
5641 }
5642
5643 static void chv_update_pll(struct intel_crtc *crtc)
5644 {
5645         struct drm_device *dev = crtc->base.dev;
5646         struct drm_i915_private *dev_priv = dev->dev_private;
5647         int pipe = crtc->pipe;
5648         int dpll_reg = DPLL(crtc->pipe);
5649         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5650         u32 loopfilter, intcoeff;
5651         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5652         int refclk;
5653
5654         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5655                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5656                 DPLL_VCO_ENABLE;
5657         if (pipe != PIPE_A)
5658                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5659
5660         crtc->config.dpll_hw_state.dpll_md =
5661                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5662
5663         bestn = crtc->config.dpll.n;
5664         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5665         bestm1 = crtc->config.dpll.m1;
5666         bestm2 = crtc->config.dpll.m2 >> 22;
5667         bestp1 = crtc->config.dpll.p1;
5668         bestp2 = crtc->config.dpll.p2;
5669
5670         /*
5671          * Enable Refclk and SSC
5672          */
5673         I915_WRITE(dpll_reg,
5674                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5675
5676         mutex_lock(&dev_priv->dpio_lock);
5677
5678         /* p1 and p2 divider */
5679         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5680                         5 << DPIO_CHV_S1_DIV_SHIFT |
5681                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5682                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5683                         1 << DPIO_CHV_K_DIV_SHIFT);
5684
5685         /* Feedback post-divider - m2 */
5686         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5687
5688         /* Feedback refclk divider - n and m1 */
5689         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5690                         DPIO_CHV_M1_DIV_BY_2 |
5691                         1 << DPIO_CHV_N_DIV_SHIFT);
5692
5693         /* M2 fraction division */
5694         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5695
5696         /* M2 fraction division enable */
5697         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5698                        DPIO_CHV_FRAC_DIV_EN |
5699                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5700
5701         /* Loop filter */
5702         refclk = i9xx_get_refclk(&crtc->base, 0);
5703         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5704                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5705         if (refclk == 100000)
5706                 intcoeff = 11;
5707         else if (refclk == 38400)
5708                 intcoeff = 10;
5709         else
5710                 intcoeff = 9;
5711         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5712         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5713
5714         /* AFC Recal */
5715         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5716                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5717                         DPIO_AFC_RECAL);
5718
5719         mutex_unlock(&dev_priv->dpio_lock);
5720 }
5721
5722 static void i9xx_update_pll(struct intel_crtc *crtc,
5723                             intel_clock_t *reduced_clock,
5724                             int num_connectors)
5725 {
5726         struct drm_device *dev = crtc->base.dev;
5727         struct drm_i915_private *dev_priv = dev->dev_private;
5728         u32 dpll;
5729         bool is_sdvo;
5730         struct dpll *clock = &crtc->config.dpll;
5731
5732         i9xx_update_pll_dividers(crtc, reduced_clock);
5733
5734         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5735                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5736
5737         dpll = DPLL_VGA_MODE_DIS;
5738
5739         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5740                 dpll |= DPLLB_MODE_LVDS;
5741         else
5742                 dpll |= DPLLB_MODE_DAC_SERIAL;
5743
5744         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5745                 dpll |= (crtc->config.pixel_multiplier - 1)
5746                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5747         }
5748
5749         if (is_sdvo)
5750                 dpll |= DPLL_SDVO_HIGH_SPEED;
5751
5752         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5753                 dpll |= DPLL_SDVO_HIGH_SPEED;
5754
5755         /* compute bitmask from p1 value */
5756         if (IS_PINEVIEW(dev))
5757                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5758         else {
5759                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5760                 if (IS_G4X(dev) && reduced_clock)
5761                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5762         }
5763         switch (clock->p2) {
5764         case 5:
5765                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5766                 break;
5767         case 7:
5768                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5769                 break;
5770         case 10:
5771                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5772                 break;
5773         case 14:
5774                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5775                 break;
5776         }
5777         if (INTEL_INFO(dev)->gen >= 4)
5778                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5779
5780         if (crtc->config.sdvo_tv_clock)
5781                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5782         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5783                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5784                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5785         else
5786                 dpll |= PLL_REF_INPUT_DREFCLK;
5787
5788         dpll |= DPLL_VCO_ENABLE;
5789         crtc->config.dpll_hw_state.dpll = dpll;
5790
5791         if (INTEL_INFO(dev)->gen >= 4) {
5792                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5793                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5794                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5795         }
5796 }
5797
5798 static void i8xx_update_pll(struct intel_crtc *crtc,
5799                             intel_clock_t *reduced_clock,
5800                             int num_connectors)
5801 {
5802         struct drm_device *dev = crtc->base.dev;
5803         struct drm_i915_private *dev_priv = dev->dev_private;
5804         u32 dpll;
5805         struct dpll *clock = &crtc->config.dpll;
5806
5807         i9xx_update_pll_dividers(crtc, reduced_clock);
5808
5809         dpll = DPLL_VGA_MODE_DIS;
5810
5811         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5812                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5813         } else {
5814                 if (clock->p1 == 2)
5815                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5816                 else
5817                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5818                 if (clock->p2 == 4)
5819                         dpll |= PLL_P2_DIVIDE_BY_4;
5820         }
5821
5822         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5823                 dpll |= DPLL_DVO_2X_MODE;
5824
5825         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5826                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5827                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5828         else
5829                 dpll |= PLL_REF_INPUT_DREFCLK;
5830
5831         dpll |= DPLL_VCO_ENABLE;
5832         crtc->config.dpll_hw_state.dpll = dpll;
5833 }
5834
5835 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5836 {
5837         struct drm_device *dev = intel_crtc->base.dev;
5838         struct drm_i915_private *dev_priv = dev->dev_private;
5839         enum pipe pipe = intel_crtc->pipe;
5840         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5841         struct drm_display_mode *adjusted_mode =
5842                 &intel_crtc->config.adjusted_mode;
5843         uint32_t crtc_vtotal, crtc_vblank_end;
5844         int vsyncshift = 0;
5845
5846         /* We need to be careful not to changed the adjusted mode, for otherwise
5847          * the hw state checker will get angry at the mismatch. */
5848         crtc_vtotal = adjusted_mode->crtc_vtotal;
5849         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5850
5851         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5852                 /* the chip adds 2 halflines automatically */
5853                 crtc_vtotal -= 1;
5854                 crtc_vblank_end -= 1;
5855
5856                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5857                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5858                 else
5859                         vsyncshift = adjusted_mode->crtc_hsync_start -
5860                                 adjusted_mode->crtc_htotal / 2;
5861                 if (vsyncshift < 0)
5862                         vsyncshift += adjusted_mode->crtc_htotal;
5863         }
5864
5865         if (INTEL_INFO(dev)->gen > 3)
5866                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5867
5868         I915_WRITE(HTOTAL(cpu_transcoder),
5869                    (adjusted_mode->crtc_hdisplay - 1) |
5870                    ((adjusted_mode->crtc_htotal - 1) << 16));
5871         I915_WRITE(HBLANK(cpu_transcoder),
5872                    (adjusted_mode->crtc_hblank_start - 1) |
5873                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5874         I915_WRITE(HSYNC(cpu_transcoder),
5875                    (adjusted_mode->crtc_hsync_start - 1) |
5876                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5877
5878         I915_WRITE(VTOTAL(cpu_transcoder),
5879                    (adjusted_mode->crtc_vdisplay - 1) |
5880                    ((crtc_vtotal - 1) << 16));
5881         I915_WRITE(VBLANK(cpu_transcoder),
5882                    (adjusted_mode->crtc_vblank_start - 1) |
5883                    ((crtc_vblank_end - 1) << 16));
5884         I915_WRITE(VSYNC(cpu_transcoder),
5885                    (adjusted_mode->crtc_vsync_start - 1) |
5886                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5887
5888         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5889          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5890          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5891          * bits. */
5892         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5893             (pipe == PIPE_B || pipe == PIPE_C))
5894                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5895
5896         /* pipesrc controls the size that is scaled from, which should
5897          * always be the user's requested size.
5898          */
5899         I915_WRITE(PIPESRC(pipe),
5900                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5901                    (intel_crtc->config.pipe_src_h - 1));
5902 }
5903
5904 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5905                                    struct intel_crtc_config *pipe_config)
5906 {
5907         struct drm_device *dev = crtc->base.dev;
5908         struct drm_i915_private *dev_priv = dev->dev_private;
5909         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5910         uint32_t tmp;
5911
5912         tmp = I915_READ(HTOTAL(cpu_transcoder));
5913         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5914         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5915         tmp = I915_READ(HBLANK(cpu_transcoder));
5916         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5917         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5918         tmp = I915_READ(HSYNC(cpu_transcoder));
5919         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5920         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5921
5922         tmp = I915_READ(VTOTAL(cpu_transcoder));
5923         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5924         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5925         tmp = I915_READ(VBLANK(cpu_transcoder));
5926         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5927         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5928         tmp = I915_READ(VSYNC(cpu_transcoder));
5929         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5930         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5931
5932         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5933                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5934                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5935                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5936         }
5937
5938         tmp = I915_READ(PIPESRC(crtc->pipe));
5939         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5940         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5941
5942         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5943         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5944 }
5945
5946 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5947                                  struct intel_crtc_config *pipe_config)
5948 {
5949         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5950         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5951         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5952         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5953
5954         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5955         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5956         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5957         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5958
5959         mode->flags = pipe_config->adjusted_mode.flags;
5960
5961         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5962         mode->flags |= pipe_config->adjusted_mode.flags;
5963 }
5964
5965 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5966 {
5967         struct drm_device *dev = intel_crtc->base.dev;
5968         struct drm_i915_private *dev_priv = dev->dev_private;
5969         uint32_t pipeconf;
5970
5971         pipeconf = 0;
5972
5973         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5974             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5975                 pipeconf |= PIPECONF_ENABLE;
5976
5977         if (intel_crtc->config.double_wide)
5978                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5979
5980         /* only g4x and later have fancy bpc/dither controls */
5981         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5982                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5983                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5984                         pipeconf |= PIPECONF_DITHER_EN |
5985                                     PIPECONF_DITHER_TYPE_SP;
5986
5987                 switch (intel_crtc->config.pipe_bpp) {
5988                 case 18:
5989                         pipeconf |= PIPECONF_6BPC;
5990                         break;
5991                 case 24:
5992                         pipeconf |= PIPECONF_8BPC;
5993                         break;
5994                 case 30:
5995                         pipeconf |= PIPECONF_10BPC;
5996                         break;
5997                 default:
5998                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5999                         BUG();
6000                 }
6001         }
6002
6003         if (HAS_PIPE_CXSR(dev)) {
6004                 if (intel_crtc->lowfreq_avail) {
6005                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6006                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6007                 } else {
6008                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6009                 }
6010         }
6011
6012         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6013                 if (INTEL_INFO(dev)->gen < 4 ||
6014                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6015                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6016                 else
6017                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6018         } else
6019                 pipeconf |= PIPECONF_PROGRESSIVE;
6020
6021         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6022                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6023
6024         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6025         POSTING_READ(PIPECONF(intel_crtc->pipe));
6026 }
6027
6028 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6029                               int x, int y,
6030                               struct drm_framebuffer *fb)
6031 {
6032         struct drm_device *dev = crtc->dev;
6033         struct drm_i915_private *dev_priv = dev->dev_private;
6034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6035         int refclk, num_connectors = 0;
6036         intel_clock_t clock, reduced_clock;
6037         bool ok, has_reduced_clock = false;
6038         bool is_lvds = false, is_dsi = false;
6039         struct intel_encoder *encoder;
6040         const intel_limit_t *limit;
6041
6042         for_each_encoder_on_crtc(dev, crtc, encoder) {
6043                 switch (encoder->type) {
6044                 case INTEL_OUTPUT_LVDS:
6045                         is_lvds = true;
6046                         break;
6047                 case INTEL_OUTPUT_DSI:
6048                         is_dsi = true;
6049                         break;
6050                 }
6051
6052                 num_connectors++;
6053         }
6054
6055         if (is_dsi)
6056                 return 0;
6057
6058         if (!intel_crtc->config.clock_set) {
6059                 refclk = i9xx_get_refclk(crtc, num_connectors);
6060
6061                 /*
6062                  * Returns a set of divisors for the desired target clock with
6063                  * the given refclk, or FALSE.  The returned values represent
6064                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6065                  * 2) / p1 / p2.
6066                  */
6067                 limit = intel_limit(crtc, refclk);
6068                 ok = dev_priv->display.find_dpll(limit, crtc,
6069                                                  intel_crtc->config.port_clock,
6070                                                  refclk, NULL, &clock);
6071                 if (!ok) {
6072                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6073                         return -EINVAL;
6074                 }
6075
6076                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6077                         /*
6078                          * Ensure we match the reduced clock's P to the target
6079                          * clock.  If the clocks don't match, we can't switch
6080                          * the display clock by using the FP0/FP1. In such case
6081                          * we will disable the LVDS downclock feature.
6082                          */
6083                         has_reduced_clock =
6084                                 dev_priv->display.find_dpll(limit, crtc,
6085                                                             dev_priv->lvds_downclock,
6086                                                             refclk, &clock,
6087                                                             &reduced_clock);
6088                 }
6089                 /* Compat-code for transition, will disappear. */
6090                 intel_crtc->config.dpll.n = clock.n;
6091                 intel_crtc->config.dpll.m1 = clock.m1;
6092                 intel_crtc->config.dpll.m2 = clock.m2;
6093                 intel_crtc->config.dpll.p1 = clock.p1;
6094                 intel_crtc->config.dpll.p2 = clock.p2;
6095         }
6096
6097         if (IS_GEN2(dev)) {
6098                 i8xx_update_pll(intel_crtc,
6099                                 has_reduced_clock ? &reduced_clock : NULL,
6100                                 num_connectors);
6101         } else if (IS_CHERRYVIEW(dev)) {
6102                 chv_update_pll(intel_crtc);
6103         } else if (IS_VALLEYVIEW(dev)) {
6104                 vlv_update_pll(intel_crtc);
6105         } else {
6106                 i9xx_update_pll(intel_crtc,
6107                                 has_reduced_clock ? &reduced_clock : NULL,
6108                                 num_connectors);
6109         }
6110
6111         return 0;
6112 }
6113
6114 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6115                                  struct intel_crtc_config *pipe_config)
6116 {
6117         struct drm_device *dev = crtc->base.dev;
6118         struct drm_i915_private *dev_priv = dev->dev_private;
6119         uint32_t tmp;
6120
6121         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6122                 return;
6123
6124         tmp = I915_READ(PFIT_CONTROL);
6125         if (!(tmp & PFIT_ENABLE))
6126                 return;
6127
6128         /* Check whether the pfit is attached to our pipe. */
6129         if (INTEL_INFO(dev)->gen < 4) {
6130                 if (crtc->pipe != PIPE_B)
6131                         return;
6132         } else {
6133                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6134                         return;
6135         }
6136
6137         pipe_config->gmch_pfit.control = tmp;
6138         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6139         if (INTEL_INFO(dev)->gen < 5)
6140                 pipe_config->gmch_pfit.lvds_border_bits =
6141                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6142 }
6143
6144 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6145                                struct intel_crtc_config *pipe_config)
6146 {
6147         struct drm_device *dev = crtc->base.dev;
6148         struct drm_i915_private *dev_priv = dev->dev_private;
6149         int pipe = pipe_config->cpu_transcoder;
6150         intel_clock_t clock;
6151         u32 mdiv;
6152         int refclk = 100000;
6153
6154         mutex_lock(&dev_priv->dpio_lock);
6155         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6156         mutex_unlock(&dev_priv->dpio_lock);
6157
6158         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6159         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6160         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6161         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6162         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6163
6164         vlv_clock(refclk, &clock);
6165
6166         /* clock.dot is the fast clock */
6167         pipe_config->port_clock = clock.dot / 5;
6168 }
6169
6170 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6171                                   struct intel_plane_config *plane_config)
6172 {
6173         struct drm_device *dev = crtc->base.dev;
6174         struct drm_i915_private *dev_priv = dev->dev_private;
6175         u32 val, base, offset;
6176         int pipe = crtc->pipe, plane = crtc->plane;
6177         int fourcc, pixel_format;
6178         int aligned_height;
6179
6180         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6181         if (!crtc->base.primary->fb) {
6182                 DRM_DEBUG_KMS("failed to alloc fb\n");
6183                 return;
6184         }
6185
6186         val = I915_READ(DSPCNTR(plane));
6187
6188         if (INTEL_INFO(dev)->gen >= 4)
6189                 if (val & DISPPLANE_TILED)
6190                         plane_config->tiled = true;
6191
6192         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6193         fourcc = intel_format_to_fourcc(pixel_format);
6194         crtc->base.primary->fb->pixel_format = fourcc;
6195         crtc->base.primary->fb->bits_per_pixel =
6196                 drm_format_plane_cpp(fourcc, 0) * 8;
6197
6198         if (INTEL_INFO(dev)->gen >= 4) {
6199                 if (plane_config->tiled)
6200                         offset = I915_READ(DSPTILEOFF(plane));
6201                 else
6202                         offset = I915_READ(DSPLINOFF(plane));
6203                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6204         } else {
6205                 base = I915_READ(DSPADDR(plane));
6206         }
6207         plane_config->base = base;
6208
6209         val = I915_READ(PIPESRC(pipe));
6210         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6211         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6212
6213         val = I915_READ(DSPSTRIDE(pipe));
6214         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6215
6216         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6217                                             plane_config->tiled);
6218
6219         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6220                                         aligned_height);
6221
6222         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6223                       pipe, plane, crtc->base.primary->fb->width,
6224                       crtc->base.primary->fb->height,
6225                       crtc->base.primary->fb->bits_per_pixel, base,
6226                       crtc->base.primary->fb->pitches[0],
6227                       plane_config->size);
6228
6229 }
6230
6231 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6232                                struct intel_crtc_config *pipe_config)
6233 {
6234         struct drm_device *dev = crtc->base.dev;
6235         struct drm_i915_private *dev_priv = dev->dev_private;
6236         int pipe = pipe_config->cpu_transcoder;
6237         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6238         intel_clock_t clock;
6239         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6240         int refclk = 100000;
6241
6242         mutex_lock(&dev_priv->dpio_lock);
6243         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6244         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6245         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6246         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6247         mutex_unlock(&dev_priv->dpio_lock);
6248
6249         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6250         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6251         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6252         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6253         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6254
6255         chv_clock(refclk, &clock);
6256
6257         /* clock.dot is the fast clock */
6258         pipe_config->port_clock = clock.dot / 5;
6259 }
6260
6261 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6262                                  struct intel_crtc_config *pipe_config)
6263 {
6264         struct drm_device *dev = crtc->base.dev;
6265         struct drm_i915_private *dev_priv = dev->dev_private;
6266         uint32_t tmp;
6267
6268         if (!intel_display_power_enabled(dev_priv,
6269                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6270                 return false;
6271
6272         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6273         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6274
6275         tmp = I915_READ(PIPECONF(crtc->pipe));
6276         if (!(tmp & PIPECONF_ENABLE))
6277                 return false;
6278
6279         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6280                 switch (tmp & PIPECONF_BPC_MASK) {
6281                 case PIPECONF_6BPC:
6282                         pipe_config->pipe_bpp = 18;
6283                         break;
6284                 case PIPECONF_8BPC:
6285                         pipe_config->pipe_bpp = 24;
6286                         break;
6287                 case PIPECONF_10BPC:
6288                         pipe_config->pipe_bpp = 30;
6289                         break;
6290                 default:
6291                         break;
6292                 }
6293         }
6294
6295         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6296                 pipe_config->limited_color_range = true;
6297
6298         if (INTEL_INFO(dev)->gen < 4)
6299                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6300
6301         intel_get_pipe_timings(crtc, pipe_config);
6302
6303         i9xx_get_pfit_config(crtc, pipe_config);
6304
6305         if (INTEL_INFO(dev)->gen >= 4) {
6306                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6307                 pipe_config->pixel_multiplier =
6308                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6309                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6310                 pipe_config->dpll_hw_state.dpll_md = tmp;
6311         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6312                 tmp = I915_READ(DPLL(crtc->pipe));
6313                 pipe_config->pixel_multiplier =
6314                         ((tmp & SDVO_MULTIPLIER_MASK)
6315                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6316         } else {
6317                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6318                  * port and will be fixed up in the encoder->get_config
6319                  * function. */
6320                 pipe_config->pixel_multiplier = 1;
6321         }
6322         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6323         if (!IS_VALLEYVIEW(dev)) {
6324                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6325                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6326         } else {
6327                 /* Mask out read-only status bits. */
6328                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6329                                                      DPLL_PORTC_READY_MASK |
6330                                                      DPLL_PORTB_READY_MASK);
6331         }
6332
6333         if (IS_CHERRYVIEW(dev))
6334                 chv_crtc_clock_get(crtc, pipe_config);
6335         else if (IS_VALLEYVIEW(dev))
6336                 vlv_crtc_clock_get(crtc, pipe_config);
6337         else
6338                 i9xx_crtc_clock_get(crtc, pipe_config);
6339
6340         return true;
6341 }
6342
6343 static void ironlake_init_pch_refclk(struct drm_device *dev)
6344 {
6345         struct drm_i915_private *dev_priv = dev->dev_private;
6346         struct drm_mode_config *mode_config = &dev->mode_config;
6347         struct intel_encoder *encoder;
6348         u32 val, final;
6349         bool has_lvds = false;
6350         bool has_cpu_edp = false;
6351         bool has_panel = false;
6352         bool has_ck505 = false;
6353         bool can_ssc = false;
6354
6355         /* We need to take the global config into account */
6356         list_for_each_entry(encoder, &mode_config->encoder_list,
6357                             base.head) {
6358                 switch (encoder->type) {
6359                 case INTEL_OUTPUT_LVDS:
6360                         has_panel = true;
6361                         has_lvds = true;
6362                         break;
6363                 case INTEL_OUTPUT_EDP:
6364                         has_panel = true;
6365                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6366                                 has_cpu_edp = true;
6367                         break;
6368                 }
6369         }
6370
6371         if (HAS_PCH_IBX(dev)) {
6372                 has_ck505 = dev_priv->vbt.display_clock_mode;
6373                 can_ssc = has_ck505;
6374         } else {
6375                 has_ck505 = false;
6376                 can_ssc = true;
6377         }
6378
6379         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6380                       has_panel, has_lvds, has_ck505);
6381
6382         /* Ironlake: try to setup display ref clock before DPLL
6383          * enabling. This is only under driver's control after
6384          * PCH B stepping, previous chipset stepping should be
6385          * ignoring this setting.
6386          */
6387         val = I915_READ(PCH_DREF_CONTROL);
6388
6389         /* As we must carefully and slowly disable/enable each source in turn,
6390          * compute the final state we want first and check if we need to
6391          * make any changes at all.
6392          */
6393         final = val;
6394         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6395         if (has_ck505)
6396                 final |= DREF_NONSPREAD_CK505_ENABLE;
6397         else
6398                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6399
6400         final &= ~DREF_SSC_SOURCE_MASK;
6401         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6402         final &= ~DREF_SSC1_ENABLE;
6403
6404         if (has_panel) {
6405                 final |= DREF_SSC_SOURCE_ENABLE;
6406
6407                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6408                         final |= DREF_SSC1_ENABLE;
6409
6410                 if (has_cpu_edp) {
6411                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6412                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6413                         else
6414                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6415                 } else
6416                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6417         } else {
6418                 final |= DREF_SSC_SOURCE_DISABLE;
6419                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6420         }
6421
6422         if (final == val)
6423                 return;
6424
6425         /* Always enable nonspread source */
6426         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6427
6428         if (has_ck505)
6429                 val |= DREF_NONSPREAD_CK505_ENABLE;
6430         else
6431                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6432
6433         if (has_panel) {
6434                 val &= ~DREF_SSC_SOURCE_MASK;
6435                 val |= DREF_SSC_SOURCE_ENABLE;
6436
6437                 /* SSC must be turned on before enabling the CPU output  */
6438                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6439                         DRM_DEBUG_KMS("Using SSC on panel\n");
6440                         val |= DREF_SSC1_ENABLE;
6441                 } else
6442                         val &= ~DREF_SSC1_ENABLE;
6443
6444                 /* Get SSC going before enabling the outputs */
6445                 I915_WRITE(PCH_DREF_CONTROL, val);
6446                 POSTING_READ(PCH_DREF_CONTROL);
6447                 udelay(200);
6448
6449                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6450
6451                 /* Enable CPU source on CPU attached eDP */
6452                 if (has_cpu_edp) {
6453                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6454                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6455                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6456                         } else
6457                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6458                 } else
6459                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6460
6461                 I915_WRITE(PCH_DREF_CONTROL, val);
6462                 POSTING_READ(PCH_DREF_CONTROL);
6463                 udelay(200);
6464         } else {
6465                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6466
6467                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6468
6469                 /* Turn off CPU output */
6470                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6471
6472                 I915_WRITE(PCH_DREF_CONTROL, val);
6473                 POSTING_READ(PCH_DREF_CONTROL);
6474                 udelay(200);
6475
6476                 /* Turn off the SSC source */
6477                 val &= ~DREF_SSC_SOURCE_MASK;
6478                 val |= DREF_SSC_SOURCE_DISABLE;
6479
6480                 /* Turn off SSC1 */
6481                 val &= ~DREF_SSC1_ENABLE;
6482
6483                 I915_WRITE(PCH_DREF_CONTROL, val);
6484                 POSTING_READ(PCH_DREF_CONTROL);
6485                 udelay(200);
6486         }
6487
6488         BUG_ON(val != final);
6489 }
6490
6491 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6492 {
6493         uint32_t tmp;
6494
6495         tmp = I915_READ(SOUTH_CHICKEN2);
6496         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6497         I915_WRITE(SOUTH_CHICKEN2, tmp);
6498
6499         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6500                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6501                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6502
6503         tmp = I915_READ(SOUTH_CHICKEN2);
6504         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6505         I915_WRITE(SOUTH_CHICKEN2, tmp);
6506
6507         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6508                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6509                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6510 }
6511
6512 /* WaMPhyProgramming:hsw */
6513 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6514 {
6515         uint32_t tmp;
6516
6517         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6518         tmp &= ~(0xFF << 24);
6519         tmp |= (0x12 << 24);
6520         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6521
6522         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6523         tmp |= (1 << 11);
6524         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6525
6526         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6527         tmp |= (1 << 11);
6528         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6529
6530         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6531         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6532         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6533
6534         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6535         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6536         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6537
6538         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6539         tmp &= ~(7 << 13);
6540         tmp |= (5 << 13);
6541         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6542
6543         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6544         tmp &= ~(7 << 13);
6545         tmp |= (5 << 13);
6546         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6547
6548         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6549         tmp &= ~0xFF;
6550         tmp |= 0x1C;
6551         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6552
6553         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6554         tmp &= ~0xFF;
6555         tmp |= 0x1C;
6556         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6557
6558         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6559         tmp &= ~(0xFF << 16);
6560         tmp |= (0x1C << 16);
6561         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6562
6563         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6564         tmp &= ~(0xFF << 16);
6565         tmp |= (0x1C << 16);
6566         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6567
6568         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6569         tmp |= (1 << 27);
6570         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6571
6572         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6573         tmp |= (1 << 27);
6574         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6575
6576         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6577         tmp &= ~(0xF << 28);
6578         tmp |= (4 << 28);
6579         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6580
6581         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6582         tmp &= ~(0xF << 28);
6583         tmp |= (4 << 28);
6584         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6585 }
6586
6587 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6588  * Programming" based on the parameters passed:
6589  * - Sequence to enable CLKOUT_DP
6590  * - Sequence to enable CLKOUT_DP without spread
6591  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6592  */
6593 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6594                                  bool with_fdi)
6595 {
6596         struct drm_i915_private *dev_priv = dev->dev_private;
6597         uint32_t reg, tmp;
6598
6599         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6600                 with_spread = true;
6601         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6602                  with_fdi, "LP PCH doesn't have FDI\n"))
6603                 with_fdi = false;
6604
6605         mutex_lock(&dev_priv->dpio_lock);
6606
6607         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6608         tmp &= ~SBI_SSCCTL_DISABLE;
6609         tmp |= SBI_SSCCTL_PATHALT;
6610         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6611
6612         udelay(24);
6613
6614         if (with_spread) {
6615                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6616                 tmp &= ~SBI_SSCCTL_PATHALT;
6617                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6618
6619                 if (with_fdi) {
6620                         lpt_reset_fdi_mphy(dev_priv);
6621                         lpt_program_fdi_mphy(dev_priv);
6622                 }
6623         }
6624
6625         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6626                SBI_GEN0 : SBI_DBUFF0;
6627         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6628         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6629         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6630
6631         mutex_unlock(&dev_priv->dpio_lock);
6632 }
6633
6634 /* Sequence to disable CLKOUT_DP */
6635 static void lpt_disable_clkout_dp(struct drm_device *dev)
6636 {
6637         struct drm_i915_private *dev_priv = dev->dev_private;
6638         uint32_t reg, tmp;
6639
6640         mutex_lock(&dev_priv->dpio_lock);
6641
6642         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6643                SBI_GEN0 : SBI_DBUFF0;
6644         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6645         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6646         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6647
6648         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6649         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6650                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6651                         tmp |= SBI_SSCCTL_PATHALT;
6652                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6653                         udelay(32);
6654                 }
6655                 tmp |= SBI_SSCCTL_DISABLE;
6656                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6657         }
6658
6659         mutex_unlock(&dev_priv->dpio_lock);
6660 }
6661
6662 static void lpt_init_pch_refclk(struct drm_device *dev)
6663 {
6664         struct drm_mode_config *mode_config = &dev->mode_config;
6665         struct intel_encoder *encoder;
6666         bool has_vga = false;
6667
6668         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6669                 switch (encoder->type) {
6670                 case INTEL_OUTPUT_ANALOG:
6671                         has_vga = true;
6672                         break;
6673                 }
6674         }
6675
6676         if (has_vga)
6677                 lpt_enable_clkout_dp(dev, true, true);
6678         else
6679                 lpt_disable_clkout_dp(dev);
6680 }
6681
6682 /*
6683  * Initialize reference clocks when the driver loads
6684  */
6685 void intel_init_pch_refclk(struct drm_device *dev)
6686 {
6687         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6688                 ironlake_init_pch_refclk(dev);
6689         else if (HAS_PCH_LPT(dev))
6690                 lpt_init_pch_refclk(dev);
6691 }
6692
6693 static int ironlake_get_refclk(struct drm_crtc *crtc)
6694 {
6695         struct drm_device *dev = crtc->dev;
6696         struct drm_i915_private *dev_priv = dev->dev_private;
6697         struct intel_encoder *encoder;
6698         int num_connectors = 0;
6699         bool is_lvds = false;
6700
6701         for_each_encoder_on_crtc(dev, crtc, encoder) {
6702                 switch (encoder->type) {
6703                 case INTEL_OUTPUT_LVDS:
6704                         is_lvds = true;
6705                         break;
6706                 }
6707                 num_connectors++;
6708         }
6709
6710         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6711                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6712                               dev_priv->vbt.lvds_ssc_freq);
6713                 return dev_priv->vbt.lvds_ssc_freq;
6714         }
6715
6716         return 120000;
6717 }
6718
6719 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6720 {
6721         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6722         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6723         int pipe = intel_crtc->pipe;
6724         uint32_t val;
6725
6726         val = 0;
6727
6728         switch (intel_crtc->config.pipe_bpp) {
6729         case 18:
6730                 val |= PIPECONF_6BPC;
6731                 break;
6732         case 24:
6733                 val |= PIPECONF_8BPC;
6734                 break;
6735         case 30:
6736                 val |= PIPECONF_10BPC;
6737                 break;
6738         case 36:
6739                 val |= PIPECONF_12BPC;
6740                 break;
6741         default:
6742                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6743                 BUG();
6744         }
6745
6746         if (intel_crtc->config.dither)
6747                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6748
6749         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6750                 val |= PIPECONF_INTERLACED_ILK;
6751         else
6752                 val |= PIPECONF_PROGRESSIVE;
6753
6754         if (intel_crtc->config.limited_color_range)
6755                 val |= PIPECONF_COLOR_RANGE_SELECT;
6756
6757         I915_WRITE(PIPECONF(pipe), val);
6758         POSTING_READ(PIPECONF(pipe));
6759 }
6760
6761 /*
6762  * Set up the pipe CSC unit.
6763  *
6764  * Currently only full range RGB to limited range RGB conversion
6765  * is supported, but eventually this should handle various
6766  * RGB<->YCbCr scenarios as well.
6767  */
6768 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6769 {
6770         struct drm_device *dev = crtc->dev;
6771         struct drm_i915_private *dev_priv = dev->dev_private;
6772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6773         int pipe = intel_crtc->pipe;
6774         uint16_t coeff = 0x7800; /* 1.0 */
6775
6776         /*
6777          * TODO: Check what kind of values actually come out of the pipe
6778          * with these coeff/postoff values and adjust to get the best
6779          * accuracy. Perhaps we even need to take the bpc value into
6780          * consideration.
6781          */
6782
6783         if (intel_crtc->config.limited_color_range)
6784                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6785
6786         /*
6787          * GY/GU and RY/RU should be the other way around according
6788          * to BSpec, but reality doesn't agree. Just set them up in
6789          * a way that results in the correct picture.
6790          */
6791         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6792         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6793
6794         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6795         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6796
6797         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6798         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6799
6800         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6801         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6802         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6803
6804         if (INTEL_INFO(dev)->gen > 6) {
6805                 uint16_t postoff = 0;
6806
6807                 if (intel_crtc->config.limited_color_range)
6808                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6809
6810                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6811                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6812                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6813
6814                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6815         } else {
6816                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6817
6818                 if (intel_crtc->config.limited_color_range)
6819                         mode |= CSC_BLACK_SCREEN_OFFSET;
6820
6821                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6822         }
6823 }
6824
6825 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6826 {
6827         struct drm_device *dev = crtc->dev;
6828         struct drm_i915_private *dev_priv = dev->dev_private;
6829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6830         enum pipe pipe = intel_crtc->pipe;
6831         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6832         uint32_t val;
6833
6834         val = 0;
6835
6836         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6837                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6838
6839         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6840                 val |= PIPECONF_INTERLACED_ILK;
6841         else
6842                 val |= PIPECONF_PROGRESSIVE;
6843
6844         I915_WRITE(PIPECONF(cpu_transcoder), val);
6845         POSTING_READ(PIPECONF(cpu_transcoder));
6846
6847         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6848         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6849
6850         if (IS_BROADWELL(dev)) {
6851                 val = 0;
6852
6853                 switch (intel_crtc->config.pipe_bpp) {
6854                 case 18:
6855                         val |= PIPEMISC_DITHER_6_BPC;
6856                         break;
6857                 case 24:
6858                         val |= PIPEMISC_DITHER_8_BPC;
6859                         break;
6860                 case 30:
6861                         val |= PIPEMISC_DITHER_10_BPC;
6862                         break;
6863                 case 36:
6864                         val |= PIPEMISC_DITHER_12_BPC;
6865                         break;
6866                 default:
6867                         /* Case prevented by pipe_config_set_bpp. */
6868                         BUG();
6869                 }
6870
6871                 if (intel_crtc->config.dither)
6872                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6873
6874                 I915_WRITE(PIPEMISC(pipe), val);
6875         }
6876 }
6877
6878 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6879                                     intel_clock_t *clock,
6880                                     bool *has_reduced_clock,
6881                                     intel_clock_t *reduced_clock)
6882 {
6883         struct drm_device *dev = crtc->dev;
6884         struct drm_i915_private *dev_priv = dev->dev_private;
6885         struct intel_encoder *intel_encoder;
6886         int refclk;
6887         const intel_limit_t *limit;
6888         bool ret, is_lvds = false;
6889
6890         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6891                 switch (intel_encoder->type) {
6892                 case INTEL_OUTPUT_LVDS:
6893                         is_lvds = true;
6894                         break;
6895                 }
6896         }
6897
6898         refclk = ironlake_get_refclk(crtc);
6899
6900         /*
6901          * Returns a set of divisors for the desired target clock with the given
6902          * refclk, or FALSE.  The returned values represent the clock equation:
6903          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6904          */
6905         limit = intel_limit(crtc, refclk);
6906         ret = dev_priv->display.find_dpll(limit, crtc,
6907                                           to_intel_crtc(crtc)->config.port_clock,
6908                                           refclk, NULL, clock);
6909         if (!ret)
6910                 return false;
6911
6912         if (is_lvds && dev_priv->lvds_downclock_avail) {
6913                 /*
6914                  * Ensure we match the reduced clock's P to the target clock.
6915                  * If the clocks don't match, we can't switch the display clock
6916                  * by using the FP0/FP1. In such case we will disable the LVDS
6917                  * downclock feature.
6918                 */
6919                 *has_reduced_clock =
6920                         dev_priv->display.find_dpll(limit, crtc,
6921                                                     dev_priv->lvds_downclock,
6922                                                     refclk, clock,
6923                                                     reduced_clock);
6924         }
6925
6926         return true;
6927 }
6928
6929 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6930 {
6931         /*
6932          * Account for spread spectrum to avoid
6933          * oversubscribing the link. Max center spread
6934          * is 2.5%; use 5% for safety's sake.
6935          */
6936         u32 bps = target_clock * bpp * 21 / 20;
6937         return DIV_ROUND_UP(bps, link_bw * 8);
6938 }
6939
6940 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6941 {
6942         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6943 }
6944
6945 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6946                                       u32 *fp,
6947                                       intel_clock_t *reduced_clock, u32 *fp2)
6948 {
6949         struct drm_crtc *crtc = &intel_crtc->base;
6950         struct drm_device *dev = crtc->dev;
6951         struct drm_i915_private *dev_priv = dev->dev_private;
6952         struct intel_encoder *intel_encoder;
6953         uint32_t dpll;
6954         int factor, num_connectors = 0;
6955         bool is_lvds = false, is_sdvo = false;
6956
6957         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6958                 switch (intel_encoder->type) {
6959                 case INTEL_OUTPUT_LVDS:
6960                         is_lvds = true;
6961                         break;
6962                 case INTEL_OUTPUT_SDVO:
6963                 case INTEL_OUTPUT_HDMI:
6964                         is_sdvo = true;
6965                         break;
6966                 }
6967
6968                 num_connectors++;
6969         }
6970
6971         /* Enable autotuning of the PLL clock (if permissible) */
6972         factor = 21;
6973         if (is_lvds) {
6974                 if ((intel_panel_use_ssc(dev_priv) &&
6975                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6976                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6977                         factor = 25;
6978         } else if (intel_crtc->config.sdvo_tv_clock)
6979                 factor = 20;
6980
6981         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6982                 *fp |= FP_CB_TUNE;
6983
6984         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6985                 *fp2 |= FP_CB_TUNE;
6986
6987         dpll = 0;
6988
6989         if (is_lvds)
6990                 dpll |= DPLLB_MODE_LVDS;
6991         else
6992                 dpll |= DPLLB_MODE_DAC_SERIAL;
6993
6994         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6995                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6996
6997         if (is_sdvo)
6998                 dpll |= DPLL_SDVO_HIGH_SPEED;
6999         if (intel_crtc->config.has_dp_encoder)
7000                 dpll |= DPLL_SDVO_HIGH_SPEED;
7001
7002         /* compute bitmask from p1 value */
7003         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7004         /* also FPA1 */
7005         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7006
7007         switch (intel_crtc->config.dpll.p2) {
7008         case 5:
7009                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7010                 break;
7011         case 7:
7012                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7013                 break;
7014         case 10:
7015                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7016                 break;
7017         case 14:
7018                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7019                 break;
7020         }
7021
7022         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7023                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7024         else
7025                 dpll |= PLL_REF_INPUT_DREFCLK;
7026
7027         return dpll | DPLL_VCO_ENABLE;
7028 }
7029
7030 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7031                                   int x, int y,
7032                                   struct drm_framebuffer *fb)
7033 {
7034         struct drm_device *dev = crtc->dev;
7035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7036         int num_connectors = 0;
7037         intel_clock_t clock, reduced_clock;
7038         u32 dpll = 0, fp = 0, fp2 = 0;
7039         bool ok, has_reduced_clock = false;
7040         bool is_lvds = false;
7041         struct intel_encoder *encoder;
7042         struct intel_shared_dpll *pll;
7043
7044         for_each_encoder_on_crtc(dev, crtc, encoder) {
7045                 switch (encoder->type) {
7046                 case INTEL_OUTPUT_LVDS:
7047                         is_lvds = true;
7048                         break;
7049                 }
7050
7051                 num_connectors++;
7052         }
7053
7054         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7055              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7056
7057         ok = ironlake_compute_clocks(crtc, &clock,
7058                                      &has_reduced_clock, &reduced_clock);
7059         if (!ok && !intel_crtc->config.clock_set) {
7060                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7061                 return -EINVAL;
7062         }
7063         /* Compat-code for transition, will disappear. */
7064         if (!intel_crtc->config.clock_set) {
7065                 intel_crtc->config.dpll.n = clock.n;
7066                 intel_crtc->config.dpll.m1 = clock.m1;
7067                 intel_crtc->config.dpll.m2 = clock.m2;
7068                 intel_crtc->config.dpll.p1 = clock.p1;
7069                 intel_crtc->config.dpll.p2 = clock.p2;
7070         }
7071
7072         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7073         if (intel_crtc->config.has_pch_encoder) {
7074                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7075                 if (has_reduced_clock)
7076                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7077
7078                 dpll = ironlake_compute_dpll(intel_crtc,
7079                                              &fp, &reduced_clock,
7080                                              has_reduced_clock ? &fp2 : NULL);
7081
7082                 intel_crtc->config.dpll_hw_state.dpll = dpll;
7083                 intel_crtc->config.dpll_hw_state.fp0 = fp;
7084                 if (has_reduced_clock)
7085                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
7086                 else
7087                         intel_crtc->config.dpll_hw_state.fp1 = fp;
7088
7089                 pll = intel_get_shared_dpll(intel_crtc);
7090                 if (pll == NULL) {
7091                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7092                                          pipe_name(intel_crtc->pipe));
7093                         return -EINVAL;
7094                 }
7095         } else
7096                 intel_put_shared_dpll(intel_crtc);
7097
7098         if (is_lvds && has_reduced_clock && i915.powersave)
7099                 intel_crtc->lowfreq_avail = true;
7100         else
7101                 intel_crtc->lowfreq_avail = false;
7102
7103         return 0;
7104 }
7105
7106 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7107                                          struct intel_link_m_n *m_n)
7108 {
7109         struct drm_device *dev = crtc->base.dev;
7110         struct drm_i915_private *dev_priv = dev->dev_private;
7111         enum pipe pipe = crtc->pipe;
7112
7113         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7114         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7115         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7116                 & ~TU_SIZE_MASK;
7117         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7118         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7119                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7120 }
7121
7122 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7123                                          enum transcoder transcoder,
7124                                          struct intel_link_m_n *m_n)
7125 {
7126         struct drm_device *dev = crtc->base.dev;
7127         struct drm_i915_private *dev_priv = dev->dev_private;
7128         enum pipe pipe = crtc->pipe;
7129
7130         if (INTEL_INFO(dev)->gen >= 5) {
7131                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7132                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7133                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7134                         & ~TU_SIZE_MASK;
7135                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7136                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7137                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7138         } else {
7139                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7140                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7141                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7142                         & ~TU_SIZE_MASK;
7143                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7144                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7145                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7146         }
7147 }
7148
7149 void intel_dp_get_m_n(struct intel_crtc *crtc,
7150                       struct intel_crtc_config *pipe_config)
7151 {
7152         if (crtc->config.has_pch_encoder)
7153                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7154         else
7155                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7156                                              &pipe_config->dp_m_n);
7157 }
7158
7159 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7160                                         struct intel_crtc_config *pipe_config)
7161 {
7162         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7163                                      &pipe_config->fdi_m_n);
7164 }
7165
7166 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7167                                      struct intel_crtc_config *pipe_config)
7168 {
7169         struct drm_device *dev = crtc->base.dev;
7170         struct drm_i915_private *dev_priv = dev->dev_private;
7171         uint32_t tmp;
7172
7173         tmp = I915_READ(PF_CTL(crtc->pipe));
7174
7175         if (tmp & PF_ENABLE) {
7176                 pipe_config->pch_pfit.enabled = true;
7177                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7178                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7179
7180                 /* We currently do not free assignements of panel fitters on
7181                  * ivb/hsw (since we don't use the higher upscaling modes which
7182                  * differentiates them) so just WARN about this case for now. */
7183                 if (IS_GEN7(dev)) {
7184                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7185                                 PF_PIPE_SEL_IVB(crtc->pipe));
7186                 }
7187         }
7188 }
7189
7190 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7191                                       struct intel_plane_config *plane_config)
7192 {
7193         struct drm_device *dev = crtc->base.dev;
7194         struct drm_i915_private *dev_priv = dev->dev_private;
7195         u32 val, base, offset;
7196         int pipe = crtc->pipe, plane = crtc->plane;
7197         int fourcc, pixel_format;
7198         int aligned_height;
7199
7200         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7201         if (!crtc->base.primary->fb) {
7202                 DRM_DEBUG_KMS("failed to alloc fb\n");
7203                 return;
7204         }
7205
7206         val = I915_READ(DSPCNTR(plane));
7207
7208         if (INTEL_INFO(dev)->gen >= 4)
7209                 if (val & DISPPLANE_TILED)
7210                         plane_config->tiled = true;
7211
7212         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7213         fourcc = intel_format_to_fourcc(pixel_format);
7214         crtc->base.primary->fb->pixel_format = fourcc;
7215         crtc->base.primary->fb->bits_per_pixel =
7216                 drm_format_plane_cpp(fourcc, 0) * 8;
7217
7218         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7219         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7220                 offset = I915_READ(DSPOFFSET(plane));
7221         } else {
7222                 if (plane_config->tiled)
7223                         offset = I915_READ(DSPTILEOFF(plane));
7224                 else
7225                         offset = I915_READ(DSPLINOFF(plane));
7226         }
7227         plane_config->base = base;
7228
7229         val = I915_READ(PIPESRC(pipe));
7230         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7231         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7232
7233         val = I915_READ(DSPSTRIDE(pipe));
7234         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7235
7236         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7237                                             plane_config->tiled);
7238
7239         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7240                                         aligned_height);
7241
7242         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7243                       pipe, plane, crtc->base.primary->fb->width,
7244                       crtc->base.primary->fb->height,
7245                       crtc->base.primary->fb->bits_per_pixel, base,
7246                       crtc->base.primary->fb->pitches[0],
7247                       plane_config->size);
7248 }
7249
7250 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7251                                      struct intel_crtc_config *pipe_config)
7252 {
7253         struct drm_device *dev = crtc->base.dev;
7254         struct drm_i915_private *dev_priv = dev->dev_private;
7255         uint32_t tmp;
7256
7257         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7258         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7259
7260         tmp = I915_READ(PIPECONF(crtc->pipe));
7261         if (!(tmp & PIPECONF_ENABLE))
7262                 return false;
7263
7264         switch (tmp & PIPECONF_BPC_MASK) {
7265         case PIPECONF_6BPC:
7266                 pipe_config->pipe_bpp = 18;
7267                 break;
7268         case PIPECONF_8BPC:
7269                 pipe_config->pipe_bpp = 24;
7270                 break;
7271         case PIPECONF_10BPC:
7272                 pipe_config->pipe_bpp = 30;
7273                 break;
7274         case PIPECONF_12BPC:
7275                 pipe_config->pipe_bpp = 36;
7276                 break;
7277         default:
7278                 break;
7279         }
7280
7281         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7282                 pipe_config->limited_color_range = true;
7283
7284         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7285                 struct intel_shared_dpll *pll;
7286
7287                 pipe_config->has_pch_encoder = true;
7288
7289                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7290                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7291                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7292
7293                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7294
7295                 if (HAS_PCH_IBX(dev_priv->dev)) {
7296                         pipe_config->shared_dpll =
7297                                 (enum intel_dpll_id) crtc->pipe;
7298                 } else {
7299                         tmp = I915_READ(PCH_DPLL_SEL);
7300                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7301                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7302                         else
7303                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7304                 }
7305
7306                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7307
7308                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7309                                            &pipe_config->dpll_hw_state));
7310
7311                 tmp = pipe_config->dpll_hw_state.dpll;
7312                 pipe_config->pixel_multiplier =
7313                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7314                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7315
7316                 ironlake_pch_clock_get(crtc, pipe_config);
7317         } else {
7318                 pipe_config->pixel_multiplier = 1;
7319         }
7320
7321         intel_get_pipe_timings(crtc, pipe_config);
7322
7323         ironlake_get_pfit_config(crtc, pipe_config);
7324
7325         return true;
7326 }
7327
7328 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7329 {
7330         struct drm_device *dev = dev_priv->dev;
7331         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7332         struct intel_crtc *crtc;
7333
7334         for_each_intel_crtc(dev, crtc)
7335                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7336                      pipe_name(crtc->pipe));
7337
7338         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7339         WARN(plls->spll_refcount, "SPLL enabled\n");
7340         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7341         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7342         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7343         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7344              "CPU PWM1 enabled\n");
7345         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7346              "CPU PWM2 enabled\n");
7347         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7348              "PCH PWM1 enabled\n");
7349         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7350              "Utility pin enabled\n");
7351         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7352
7353         /*
7354          * In theory we can still leave IRQs enabled, as long as only the HPD
7355          * interrupts remain enabled. We used to check for that, but since it's
7356          * gen-specific and since we only disable LCPLL after we fully disable
7357          * the interrupts, the check below should be enough.
7358          */
7359         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7360 }
7361
7362 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7363 {
7364         struct drm_device *dev = dev_priv->dev;
7365
7366         if (IS_HASWELL(dev)) {
7367                 mutex_lock(&dev_priv->rps.hw_lock);
7368                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7369                                             val))
7370                         DRM_ERROR("Failed to disable D_COMP\n");
7371                 mutex_unlock(&dev_priv->rps.hw_lock);
7372         } else {
7373                 I915_WRITE(D_COMP, val);
7374         }
7375         POSTING_READ(D_COMP);
7376 }
7377
7378 /*
7379  * This function implements pieces of two sequences from BSpec:
7380  * - Sequence for display software to disable LCPLL
7381  * - Sequence for display software to allow package C8+
7382  * The steps implemented here are just the steps that actually touch the LCPLL
7383  * register. Callers should take care of disabling all the display engine
7384  * functions, doing the mode unset, fixing interrupts, etc.
7385  */
7386 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7387                               bool switch_to_fclk, bool allow_power_down)
7388 {
7389         uint32_t val;
7390
7391         assert_can_disable_lcpll(dev_priv);
7392
7393         val = I915_READ(LCPLL_CTL);
7394
7395         if (switch_to_fclk) {
7396                 val |= LCPLL_CD_SOURCE_FCLK;
7397                 I915_WRITE(LCPLL_CTL, val);
7398
7399                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7400                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7401                         DRM_ERROR("Switching to FCLK failed\n");
7402
7403                 val = I915_READ(LCPLL_CTL);
7404         }
7405
7406         val |= LCPLL_PLL_DISABLE;
7407         I915_WRITE(LCPLL_CTL, val);
7408         POSTING_READ(LCPLL_CTL);
7409
7410         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7411                 DRM_ERROR("LCPLL still locked\n");
7412
7413         val = I915_READ(D_COMP);
7414         val |= D_COMP_COMP_DISABLE;
7415         hsw_write_dcomp(dev_priv, val);
7416         ndelay(100);
7417
7418         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7419                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7420
7421         if (allow_power_down) {
7422                 val = I915_READ(LCPLL_CTL);
7423                 val |= LCPLL_POWER_DOWN_ALLOW;
7424                 I915_WRITE(LCPLL_CTL, val);
7425                 POSTING_READ(LCPLL_CTL);
7426         }
7427 }
7428
7429 /*
7430  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7431  * source.
7432  */
7433 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7434 {
7435         uint32_t val;
7436         unsigned long irqflags;
7437
7438         val = I915_READ(LCPLL_CTL);
7439
7440         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7441                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7442                 return;
7443
7444         /*
7445          * Make sure we're not on PC8 state before disabling PC8, otherwise
7446          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7447          *
7448          * The other problem is that hsw_restore_lcpll() is called as part of
7449          * the runtime PM resume sequence, so we can't just call
7450          * gen6_gt_force_wake_get() because that function calls
7451          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7452          * while we are on the resume sequence. So to solve this problem we have
7453          * to call special forcewake code that doesn't touch runtime PM and
7454          * doesn't enable the forcewake delayed work.
7455          */
7456         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7457         if (dev_priv->uncore.forcewake_count++ == 0)
7458                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7459         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7460
7461         if (val & LCPLL_POWER_DOWN_ALLOW) {
7462                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7463                 I915_WRITE(LCPLL_CTL, val);
7464                 POSTING_READ(LCPLL_CTL);
7465         }
7466
7467         val = I915_READ(D_COMP);
7468         val |= D_COMP_COMP_FORCE;
7469         val &= ~D_COMP_COMP_DISABLE;
7470         hsw_write_dcomp(dev_priv, val);
7471
7472         val = I915_READ(LCPLL_CTL);
7473         val &= ~LCPLL_PLL_DISABLE;
7474         I915_WRITE(LCPLL_CTL, val);
7475
7476         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7477                 DRM_ERROR("LCPLL not locked yet\n");
7478
7479         if (val & LCPLL_CD_SOURCE_FCLK) {
7480                 val = I915_READ(LCPLL_CTL);
7481                 val &= ~LCPLL_CD_SOURCE_FCLK;
7482                 I915_WRITE(LCPLL_CTL, val);
7483
7484                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7485                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7486                         DRM_ERROR("Switching back to LCPLL failed\n");
7487         }
7488
7489         /* See the big comment above. */
7490         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7491         if (--dev_priv->uncore.forcewake_count == 0)
7492                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7493         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7494 }
7495
7496 /*
7497  * Package states C8 and deeper are really deep PC states that can only be
7498  * reached when all the devices on the system allow it, so even if the graphics
7499  * device allows PC8+, it doesn't mean the system will actually get to these
7500  * states. Our driver only allows PC8+ when going into runtime PM.
7501  *
7502  * The requirements for PC8+ are that all the outputs are disabled, the power
7503  * well is disabled and most interrupts are disabled, and these are also
7504  * requirements for runtime PM. When these conditions are met, we manually do
7505  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7506  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7507  * hang the machine.
7508  *
7509  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7510  * the state of some registers, so when we come back from PC8+ we need to
7511  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7512  * need to take care of the registers kept by RC6. Notice that this happens even
7513  * if we don't put the device in PCI D3 state (which is what currently happens
7514  * because of the runtime PM support).
7515  *
7516  * For more, read "Display Sequences for Package C8" on the hardware
7517  * documentation.
7518  */
7519 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7520 {
7521         struct drm_device *dev = dev_priv->dev;
7522         uint32_t val;
7523
7524         DRM_DEBUG_KMS("Enabling package C8+\n");
7525
7526         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7527                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7528                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7529                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7530         }
7531
7532         lpt_disable_clkout_dp(dev);
7533         hsw_disable_lcpll(dev_priv, true, true);
7534 }
7535
7536 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7537 {
7538         struct drm_device *dev = dev_priv->dev;
7539         uint32_t val;
7540
7541         DRM_DEBUG_KMS("Disabling package C8+\n");
7542
7543         hsw_restore_lcpll(dev_priv);
7544         lpt_init_pch_refclk(dev);
7545
7546         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7547                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7548                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7549                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7550         }
7551
7552         intel_prepare_ddi(dev);
7553 }
7554
7555 static void snb_modeset_global_resources(struct drm_device *dev)
7556 {
7557         modeset_update_crtc_power_domains(dev);
7558 }
7559
7560 static void haswell_modeset_global_resources(struct drm_device *dev)
7561 {
7562         modeset_update_crtc_power_domains(dev);
7563 }
7564
7565 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7566                                  int x, int y,
7567                                  struct drm_framebuffer *fb)
7568 {
7569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7570
7571         if (!intel_ddi_pll_select(intel_crtc))
7572                 return -EINVAL;
7573         intel_ddi_pll_enable(intel_crtc);
7574
7575         intel_crtc->lowfreq_avail = false;
7576
7577         return 0;
7578 }
7579
7580 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7581                                     struct intel_crtc_config *pipe_config)
7582 {
7583         struct drm_device *dev = crtc->base.dev;
7584         struct drm_i915_private *dev_priv = dev->dev_private;
7585         enum intel_display_power_domain pfit_domain;
7586         uint32_t tmp;
7587
7588         if (!intel_display_power_enabled(dev_priv,
7589                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7590                 return false;
7591
7592         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7593         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7594
7595         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7596         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7597                 enum pipe trans_edp_pipe;
7598                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7599                 default:
7600                         WARN(1, "unknown pipe linked to edp transcoder\n");
7601                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7602                 case TRANS_DDI_EDP_INPUT_A_ON:
7603                         trans_edp_pipe = PIPE_A;
7604                         break;
7605                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7606                         trans_edp_pipe = PIPE_B;
7607                         break;
7608                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7609                         trans_edp_pipe = PIPE_C;
7610                         break;
7611                 }
7612
7613                 if (trans_edp_pipe == crtc->pipe)
7614                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7615         }
7616
7617         if (!intel_display_power_enabled(dev_priv,
7618                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7619                 return false;
7620
7621         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7622         if (!(tmp & PIPECONF_ENABLE))
7623                 return false;
7624
7625         /*
7626          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7627          * DDI E. So just check whether this pipe is wired to DDI E and whether
7628          * the PCH transcoder is on.
7629          */
7630         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7631         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7632             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7633                 pipe_config->has_pch_encoder = true;
7634
7635                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7636                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7637                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7638
7639                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7640         }
7641
7642         intel_get_pipe_timings(crtc, pipe_config);
7643
7644         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7645         if (intel_display_power_enabled(dev_priv, pfit_domain))
7646                 ironlake_get_pfit_config(crtc, pipe_config);
7647
7648         if (IS_HASWELL(dev))
7649                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7650                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7651
7652         pipe_config->pixel_multiplier = 1;
7653
7654         return true;
7655 }
7656
7657 static struct {
7658         int clock;
7659         u32 config;
7660 } hdmi_audio_clock[] = {
7661         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7662         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7663         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7664         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7665         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7666         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7667         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7668         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7669         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7670         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7671 };
7672
7673 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7674 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7675 {
7676         int i;
7677
7678         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7679                 if (mode->clock == hdmi_audio_clock[i].clock)
7680                         break;
7681         }
7682
7683         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7684                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7685                 i = 1;
7686         }
7687
7688         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7689                       hdmi_audio_clock[i].clock,
7690                       hdmi_audio_clock[i].config);
7691
7692         return hdmi_audio_clock[i].config;
7693 }
7694
7695 static bool intel_eld_uptodate(struct drm_connector *connector,
7696                                int reg_eldv, uint32_t bits_eldv,
7697                                int reg_elda, uint32_t bits_elda,
7698                                int reg_edid)
7699 {
7700         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7701         uint8_t *eld = connector->eld;
7702         uint32_t i;
7703
7704         i = I915_READ(reg_eldv);
7705         i &= bits_eldv;
7706
7707         if (!eld[0])
7708                 return !i;
7709
7710         if (!i)
7711                 return false;
7712
7713         i = I915_READ(reg_elda);
7714         i &= ~bits_elda;
7715         I915_WRITE(reg_elda, i);
7716
7717         for (i = 0; i < eld[2]; i++)
7718                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7719                         return false;
7720
7721         return true;
7722 }
7723
7724 static void g4x_write_eld(struct drm_connector *connector,
7725                           struct drm_crtc *crtc,
7726                           struct drm_display_mode *mode)
7727 {
7728         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7729         uint8_t *eld = connector->eld;
7730         uint32_t eldv;
7731         uint32_t len;
7732         uint32_t i;
7733
7734         i = I915_READ(G4X_AUD_VID_DID);
7735
7736         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7737                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7738         else
7739                 eldv = G4X_ELDV_DEVCTG;
7740
7741         if (intel_eld_uptodate(connector,
7742                                G4X_AUD_CNTL_ST, eldv,
7743                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7744                                G4X_HDMIW_HDMIEDID))
7745                 return;
7746
7747         i = I915_READ(G4X_AUD_CNTL_ST);
7748         i &= ~(eldv | G4X_ELD_ADDR);
7749         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7750         I915_WRITE(G4X_AUD_CNTL_ST, i);
7751
7752         if (!eld[0])
7753                 return;
7754
7755         len = min_t(uint8_t, eld[2], len);
7756         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7757         for (i = 0; i < len; i++)
7758                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7759
7760         i = I915_READ(G4X_AUD_CNTL_ST);
7761         i |= eldv;
7762         I915_WRITE(G4X_AUD_CNTL_ST, i);
7763 }
7764
7765 static void haswell_write_eld(struct drm_connector *connector,
7766                               struct drm_crtc *crtc,
7767                               struct drm_display_mode *mode)
7768 {
7769         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7770         uint8_t *eld = connector->eld;
7771         uint32_t eldv;
7772         uint32_t i;
7773         int len;
7774         int pipe = to_intel_crtc(crtc)->pipe;
7775         int tmp;
7776
7777         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7778         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7779         int aud_config = HSW_AUD_CFG(pipe);
7780         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7781
7782         /* Audio output enable */
7783         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7784         tmp = I915_READ(aud_cntrl_st2);
7785         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7786         I915_WRITE(aud_cntrl_st2, tmp);
7787         POSTING_READ(aud_cntrl_st2);
7788
7789         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7790
7791         /* Set ELD valid state */
7792         tmp = I915_READ(aud_cntrl_st2);
7793         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7794         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7795         I915_WRITE(aud_cntrl_st2, tmp);
7796         tmp = I915_READ(aud_cntrl_st2);
7797         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7798
7799         /* Enable HDMI mode */
7800         tmp = I915_READ(aud_config);
7801         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7802         /* clear N_programing_enable and N_value_index */
7803         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7804         I915_WRITE(aud_config, tmp);
7805
7806         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7807
7808         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7809
7810         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7811                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7812                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7813                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7814         } else {
7815                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7816         }
7817
7818         if (intel_eld_uptodate(connector,
7819                                aud_cntrl_st2, eldv,
7820                                aud_cntl_st, IBX_ELD_ADDRESS,
7821                                hdmiw_hdmiedid))
7822                 return;
7823
7824         i = I915_READ(aud_cntrl_st2);
7825         i &= ~eldv;
7826         I915_WRITE(aud_cntrl_st2, i);
7827
7828         if (!eld[0])
7829                 return;
7830
7831         i = I915_READ(aud_cntl_st);
7832         i &= ~IBX_ELD_ADDRESS;
7833         I915_WRITE(aud_cntl_st, i);
7834         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7835         DRM_DEBUG_DRIVER("port num:%d\n", i);
7836
7837         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7838         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7839         for (i = 0; i < len; i++)
7840                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7841
7842         i = I915_READ(aud_cntrl_st2);
7843         i |= eldv;
7844         I915_WRITE(aud_cntrl_st2, i);
7845
7846 }
7847
7848 static void ironlake_write_eld(struct drm_connector *connector,
7849                                struct drm_crtc *crtc,
7850                                struct drm_display_mode *mode)
7851 {
7852         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7853         uint8_t *eld = connector->eld;
7854         uint32_t eldv;
7855         uint32_t i;
7856         int len;
7857         int hdmiw_hdmiedid;
7858         int aud_config;
7859         int aud_cntl_st;
7860         int aud_cntrl_st2;
7861         int pipe = to_intel_crtc(crtc)->pipe;
7862
7863         if (HAS_PCH_IBX(connector->dev)) {
7864                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7865                 aud_config = IBX_AUD_CFG(pipe);
7866                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7867                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7868         } else if (IS_VALLEYVIEW(connector->dev)) {
7869                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7870                 aud_config = VLV_AUD_CFG(pipe);
7871                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7872                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7873         } else {
7874                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7875                 aud_config = CPT_AUD_CFG(pipe);
7876                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7877                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7878         }
7879
7880         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7881
7882         if (IS_VALLEYVIEW(connector->dev))  {
7883                 struct intel_encoder *intel_encoder;
7884                 struct intel_digital_port *intel_dig_port;
7885
7886                 intel_encoder = intel_attached_encoder(connector);
7887                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7888                 i = intel_dig_port->port;
7889         } else {
7890                 i = I915_READ(aud_cntl_st);
7891                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7892                 /* DIP_Port_Select, 0x1 = PortB */
7893         }
7894
7895         if (!i) {
7896                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7897                 /* operate blindly on all ports */
7898                 eldv = IBX_ELD_VALIDB;
7899                 eldv |= IBX_ELD_VALIDB << 4;
7900                 eldv |= IBX_ELD_VALIDB << 8;
7901         } else {
7902                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7903                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7904         }
7905
7906         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7907                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7908                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7909                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7910         } else {
7911                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7912         }
7913
7914         if (intel_eld_uptodate(connector,
7915                                aud_cntrl_st2, eldv,
7916                                aud_cntl_st, IBX_ELD_ADDRESS,
7917                                hdmiw_hdmiedid))
7918                 return;
7919
7920         i = I915_READ(aud_cntrl_st2);
7921         i &= ~eldv;
7922         I915_WRITE(aud_cntrl_st2, i);
7923
7924         if (!eld[0])
7925                 return;
7926
7927         i = I915_READ(aud_cntl_st);
7928         i &= ~IBX_ELD_ADDRESS;
7929         I915_WRITE(aud_cntl_st, i);
7930
7931         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7932         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7933         for (i = 0; i < len; i++)
7934                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7935
7936         i = I915_READ(aud_cntrl_st2);
7937         i |= eldv;
7938         I915_WRITE(aud_cntrl_st2, i);
7939 }
7940
7941 void intel_write_eld(struct drm_encoder *encoder,
7942                      struct drm_display_mode *mode)
7943 {
7944         struct drm_crtc *crtc = encoder->crtc;
7945         struct drm_connector *connector;
7946         struct drm_device *dev = encoder->dev;
7947         struct drm_i915_private *dev_priv = dev->dev_private;
7948
7949         connector = drm_select_eld(encoder, mode);
7950         if (!connector)
7951                 return;
7952
7953         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7954                          connector->base.id,
7955                          connector->name,
7956                          connector->encoder->base.id,
7957                          connector->encoder->name);
7958
7959         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7960
7961         if (dev_priv->display.write_eld)
7962                 dev_priv->display.write_eld(connector, crtc, mode);
7963 }
7964
7965 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7966 {
7967         struct drm_device *dev = crtc->dev;
7968         struct drm_i915_private *dev_priv = dev->dev_private;
7969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7970         uint32_t cntl;
7971
7972         if (base != intel_crtc->cursor_base) {
7973                 /* On these chipsets we can only modify the base whilst
7974                  * the cursor is disabled.
7975                  */
7976                 if (intel_crtc->cursor_cntl) {
7977                         I915_WRITE(_CURACNTR, 0);
7978                         POSTING_READ(_CURACNTR);
7979                         intel_crtc->cursor_cntl = 0;
7980                 }
7981
7982                 I915_WRITE(_CURABASE, base);
7983                 POSTING_READ(_CURABASE);
7984         }
7985
7986         /* XXX width must be 64, stride 256 => 0x00 << 28 */
7987         cntl = 0;
7988         if (base)
7989                 cntl = (CURSOR_ENABLE |
7990                         CURSOR_GAMMA_ENABLE |
7991                         CURSOR_FORMAT_ARGB);
7992         if (intel_crtc->cursor_cntl != cntl) {
7993                 I915_WRITE(_CURACNTR, cntl);
7994                 POSTING_READ(_CURACNTR);
7995                 intel_crtc->cursor_cntl = cntl;
7996         }
7997 }
7998
7999 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8000 {
8001         struct drm_device *dev = crtc->dev;
8002         struct drm_i915_private *dev_priv = dev->dev_private;
8003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8004         int pipe = intel_crtc->pipe;
8005         uint32_t cntl;
8006
8007         cntl = 0;
8008         if (base) {
8009                 cntl = MCURSOR_GAMMA_ENABLE;
8010                 switch (intel_crtc->cursor_width) {
8011                         case 64:
8012                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8013                                 break;
8014                         case 128:
8015                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8016                                 break;
8017                         case 256:
8018                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8019                                 break;
8020                         default:
8021                                 WARN_ON(1);
8022                                 return;
8023                 }
8024                 cntl |= pipe << 28; /* Connect to correct pipe */
8025         }
8026         if (intel_crtc->cursor_cntl != cntl) {
8027                 I915_WRITE(CURCNTR(pipe), cntl);
8028                 POSTING_READ(CURCNTR(pipe));
8029                 intel_crtc->cursor_cntl = cntl;
8030         }
8031
8032         /* and commit changes on next vblank */
8033         I915_WRITE(CURBASE(pipe), base);
8034         POSTING_READ(CURBASE(pipe));
8035 }
8036
8037 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8038 {
8039         struct drm_device *dev = crtc->dev;
8040         struct drm_i915_private *dev_priv = dev->dev_private;
8041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8042         int pipe = intel_crtc->pipe;
8043         uint32_t cntl;
8044
8045         cntl = 0;
8046         if (base) {
8047                 cntl = MCURSOR_GAMMA_ENABLE;
8048                 switch (intel_crtc->cursor_width) {
8049                         case 64:
8050                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8051                                 break;
8052                         case 128:
8053                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8054                                 break;
8055                         case 256:
8056                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8057                                 break;
8058                         default:
8059                                 WARN_ON(1);
8060                                 return;
8061                 }
8062         }
8063         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8064                 cntl |= CURSOR_PIPE_CSC_ENABLE;
8065
8066         if (intel_crtc->cursor_cntl != cntl) {
8067                 I915_WRITE(CURCNTR(pipe), cntl);
8068                 POSTING_READ(CURCNTR(pipe));
8069                 intel_crtc->cursor_cntl = cntl;
8070         }
8071
8072         /* and commit changes on next vblank */
8073         I915_WRITE(CURBASE(pipe), base);
8074         POSTING_READ(CURBASE(pipe));
8075 }
8076
8077 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8078 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8079                                      bool on)
8080 {
8081         struct drm_device *dev = crtc->dev;
8082         struct drm_i915_private *dev_priv = dev->dev_private;
8083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8084         int pipe = intel_crtc->pipe;
8085         int x = crtc->cursor_x;
8086         int y = crtc->cursor_y;
8087         u32 base = 0, pos = 0;
8088
8089         if (on)
8090                 base = intel_crtc->cursor_addr;
8091
8092         if (x >= intel_crtc->config.pipe_src_w)
8093                 base = 0;
8094
8095         if (y >= intel_crtc->config.pipe_src_h)
8096                 base = 0;
8097
8098         if (x < 0) {
8099                 if (x + intel_crtc->cursor_width <= 0)
8100                         base = 0;
8101
8102                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8103                 x = -x;
8104         }
8105         pos |= x << CURSOR_X_SHIFT;
8106
8107         if (y < 0) {
8108                 if (y + intel_crtc->cursor_height <= 0)
8109                         base = 0;
8110
8111                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8112                 y = -y;
8113         }
8114         pos |= y << CURSOR_Y_SHIFT;
8115
8116         if (base == 0 && intel_crtc->cursor_base == 0)
8117                 return;
8118
8119         I915_WRITE(CURPOS(pipe), pos);
8120
8121         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8122                 ivb_update_cursor(crtc, base);
8123         else if (IS_845G(dev) || IS_I865G(dev))
8124                 i845_update_cursor(crtc, base);
8125         else
8126                 i9xx_update_cursor(crtc, base);
8127         intel_crtc->cursor_base = base;
8128 }
8129
8130 /*
8131  * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8132  *
8133  * Note that the object's reference will be consumed if the update fails.  If
8134  * the update succeeds, the reference of the old object (if any) will be
8135  * consumed.
8136  */
8137 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8138                                      struct drm_i915_gem_object *obj,
8139                                      uint32_t width, uint32_t height)
8140 {
8141         struct drm_device *dev = crtc->dev;
8142         struct drm_i915_private *dev_priv = dev->dev_private;
8143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8144         enum pipe pipe = intel_crtc->pipe;
8145         unsigned old_width;
8146         uint32_t addr;
8147         int ret;
8148
8149         /* if we want to turn off the cursor ignore width and height */
8150         if (!obj) {
8151                 DRM_DEBUG_KMS("cursor off\n");
8152                 addr = 0;
8153                 obj = NULL;
8154                 mutex_lock(&dev->struct_mutex);
8155                 goto finish;
8156         }
8157
8158         /* Check for which cursor types we support */
8159         if (!((width == 64 && height == 64) ||
8160                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8161                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8162                 DRM_DEBUG("Cursor dimension not supported\n");
8163                 return -EINVAL;
8164         }
8165
8166         if (obj->base.size < width * height * 4) {
8167                 DRM_DEBUG_KMS("buffer is too small\n");
8168                 ret = -ENOMEM;
8169                 goto fail;
8170         }
8171
8172         /* we only need to pin inside GTT if cursor is non-phy */
8173         mutex_lock(&dev->struct_mutex);
8174         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8175                 unsigned alignment;
8176
8177                 if (obj->tiling_mode) {
8178                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8179                         ret = -EINVAL;
8180                         goto fail_locked;
8181                 }
8182
8183                 /* Note that the w/a also requires 2 PTE of padding following
8184                  * the bo. We currently fill all unused PTE with the shadow
8185                  * page and so we should always have valid PTE following the
8186                  * cursor preventing the VT-d warning.
8187                  */
8188                 alignment = 0;
8189                 if (need_vtd_wa(dev))
8190                         alignment = 64*1024;
8191
8192                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8193                 if (ret) {
8194                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8195                         goto fail_locked;
8196                 }
8197
8198                 ret = i915_gem_object_put_fence(obj);
8199                 if (ret) {
8200                         DRM_DEBUG_KMS("failed to release fence for cursor");
8201                         goto fail_unpin;
8202                 }
8203
8204                 addr = i915_gem_obj_ggtt_offset(obj);
8205         } else {
8206                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8207                 ret = i915_gem_object_attach_phys(obj, align);
8208                 if (ret) {
8209                         DRM_DEBUG_KMS("failed to attach phys object\n");
8210                         goto fail_locked;
8211                 }
8212                 addr = obj->phys_handle->busaddr;
8213         }
8214
8215         if (IS_GEN2(dev))
8216                 I915_WRITE(CURSIZE, (height << 12) | width);
8217
8218  finish:
8219         if (intel_crtc->cursor_bo) {
8220                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8221                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8222         }
8223
8224         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8225                           INTEL_FRONTBUFFER_CURSOR(pipe));
8226         mutex_unlock(&dev->struct_mutex);
8227
8228         old_width = intel_crtc->cursor_width;
8229
8230         intel_crtc->cursor_addr = addr;
8231         intel_crtc->cursor_bo = obj;
8232         intel_crtc->cursor_width = width;
8233         intel_crtc->cursor_height = height;
8234
8235         if (intel_crtc->active) {
8236                 if (old_width != width)
8237                         intel_update_watermarks(crtc);
8238                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8239         }
8240
8241         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8242
8243         return 0;
8244 fail_unpin:
8245         i915_gem_object_unpin_from_display_plane(obj);
8246 fail_locked:
8247         mutex_unlock(&dev->struct_mutex);
8248 fail:
8249         drm_gem_object_unreference_unlocked(&obj->base);
8250         return ret;
8251 }
8252
8253 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8254                                  u16 *blue, uint32_t start, uint32_t size)
8255 {
8256         int end = (start + size > 256) ? 256 : start + size, i;
8257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8258
8259         for (i = start; i < end; i++) {
8260                 intel_crtc->lut_r[i] = red[i] >> 8;
8261                 intel_crtc->lut_g[i] = green[i] >> 8;
8262                 intel_crtc->lut_b[i] = blue[i] >> 8;
8263         }
8264
8265         intel_crtc_load_lut(crtc);
8266 }
8267
8268 /* VESA 640x480x72Hz mode to set on the pipe */
8269 static struct drm_display_mode load_detect_mode = {
8270         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8271                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8272 };
8273
8274 struct drm_framebuffer *
8275 __intel_framebuffer_create(struct drm_device *dev,
8276                            struct drm_mode_fb_cmd2 *mode_cmd,
8277                            struct drm_i915_gem_object *obj)
8278 {
8279         struct intel_framebuffer *intel_fb;
8280         int ret;
8281
8282         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8283         if (!intel_fb) {
8284                 drm_gem_object_unreference_unlocked(&obj->base);
8285                 return ERR_PTR(-ENOMEM);
8286         }
8287
8288         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8289         if (ret)
8290                 goto err;
8291
8292         return &intel_fb->base;
8293 err:
8294         drm_gem_object_unreference_unlocked(&obj->base);
8295         kfree(intel_fb);
8296
8297         return ERR_PTR(ret);
8298 }
8299
8300 static struct drm_framebuffer *
8301 intel_framebuffer_create(struct drm_device *dev,
8302                          struct drm_mode_fb_cmd2 *mode_cmd,
8303                          struct drm_i915_gem_object *obj)
8304 {
8305         struct drm_framebuffer *fb;
8306         int ret;
8307
8308         ret = i915_mutex_lock_interruptible(dev);
8309         if (ret)
8310                 return ERR_PTR(ret);
8311         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8312         mutex_unlock(&dev->struct_mutex);
8313
8314         return fb;
8315 }
8316
8317 static u32
8318 intel_framebuffer_pitch_for_width(int width, int bpp)
8319 {
8320         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8321         return ALIGN(pitch, 64);
8322 }
8323
8324 static u32
8325 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8326 {
8327         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8328         return PAGE_ALIGN(pitch * mode->vdisplay);
8329 }
8330
8331 static struct drm_framebuffer *
8332 intel_framebuffer_create_for_mode(struct drm_device *dev,
8333                                   struct drm_display_mode *mode,
8334                                   int depth, int bpp)
8335 {
8336         struct drm_i915_gem_object *obj;
8337         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8338
8339         obj = i915_gem_alloc_object(dev,
8340                                     intel_framebuffer_size_for_mode(mode, bpp));
8341         if (obj == NULL)
8342                 return ERR_PTR(-ENOMEM);
8343
8344         mode_cmd.width = mode->hdisplay;
8345         mode_cmd.height = mode->vdisplay;
8346         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8347                                                                 bpp);
8348         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8349
8350         return intel_framebuffer_create(dev, &mode_cmd, obj);
8351 }
8352
8353 static struct drm_framebuffer *
8354 mode_fits_in_fbdev(struct drm_device *dev,
8355                    struct drm_display_mode *mode)
8356 {
8357 #ifdef CONFIG_DRM_I915_FBDEV
8358         struct drm_i915_private *dev_priv = dev->dev_private;
8359         struct drm_i915_gem_object *obj;
8360         struct drm_framebuffer *fb;
8361
8362         if (!dev_priv->fbdev)
8363                 return NULL;
8364
8365         if (!dev_priv->fbdev->fb)
8366                 return NULL;
8367
8368         obj = dev_priv->fbdev->fb->obj;
8369         BUG_ON(!obj);
8370
8371         fb = &dev_priv->fbdev->fb->base;
8372         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8373                                                                fb->bits_per_pixel))
8374                 return NULL;
8375
8376         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8377                 return NULL;
8378
8379         return fb;
8380 #else
8381         return NULL;
8382 #endif
8383 }
8384
8385 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8386                                 struct drm_display_mode *mode,
8387                                 struct intel_load_detect_pipe *old,
8388                                 struct drm_modeset_acquire_ctx *ctx)
8389 {
8390         struct intel_crtc *intel_crtc;
8391         struct intel_encoder *intel_encoder =
8392                 intel_attached_encoder(connector);
8393         struct drm_crtc *possible_crtc;
8394         struct drm_encoder *encoder = &intel_encoder->base;
8395         struct drm_crtc *crtc = NULL;
8396         struct drm_device *dev = encoder->dev;
8397         struct drm_framebuffer *fb;
8398         struct drm_mode_config *config = &dev->mode_config;
8399         int ret, i = -1;
8400
8401         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8402                       connector->base.id, connector->name,
8403                       encoder->base.id, encoder->name);
8404
8405         drm_modeset_acquire_init(ctx, 0);
8406
8407 retry:
8408         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8409         if (ret)
8410                 goto fail_unlock;
8411
8412         /*
8413          * Algorithm gets a little messy:
8414          *
8415          *   - if the connector already has an assigned crtc, use it (but make
8416          *     sure it's on first)
8417          *
8418          *   - try to find the first unused crtc that can drive this connector,
8419          *     and use that if we find one
8420          */
8421
8422         /* See if we already have a CRTC for this connector */
8423         if (encoder->crtc) {
8424                 crtc = encoder->crtc;
8425
8426                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8427                 if (ret)
8428                         goto fail_unlock;
8429
8430                 old->dpms_mode = connector->dpms;
8431                 old->load_detect_temp = false;
8432
8433                 /* Make sure the crtc and connector are running */
8434                 if (connector->dpms != DRM_MODE_DPMS_ON)
8435                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8436
8437                 return true;
8438         }
8439
8440         /* Find an unused one (if possible) */
8441         for_each_crtc(dev, possible_crtc) {
8442                 i++;
8443                 if (!(encoder->possible_crtcs & (1 << i)))
8444                         continue;
8445                 if (!possible_crtc->enabled) {
8446                         crtc = possible_crtc;
8447                         break;
8448                 }
8449         }
8450
8451         /*
8452          * If we didn't find an unused CRTC, don't use any.
8453          */
8454         if (!crtc) {
8455                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8456                 goto fail_unlock;
8457         }
8458
8459         ret = drm_modeset_lock(&crtc->mutex, ctx);
8460         if (ret)
8461                 goto fail_unlock;
8462         intel_encoder->new_crtc = to_intel_crtc(crtc);
8463         to_intel_connector(connector)->new_encoder = intel_encoder;
8464
8465         intel_crtc = to_intel_crtc(crtc);
8466         intel_crtc->new_enabled = true;
8467         intel_crtc->new_config = &intel_crtc->config;
8468         old->dpms_mode = connector->dpms;
8469         old->load_detect_temp = true;
8470         old->release_fb = NULL;
8471
8472         if (!mode)
8473                 mode = &load_detect_mode;
8474
8475         /* We need a framebuffer large enough to accommodate all accesses
8476          * that the plane may generate whilst we perform load detection.
8477          * We can not rely on the fbcon either being present (we get called
8478          * during its initialisation to detect all boot displays, or it may
8479          * not even exist) or that it is large enough to satisfy the
8480          * requested mode.
8481          */
8482         fb = mode_fits_in_fbdev(dev, mode);
8483         if (fb == NULL) {
8484                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8485                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8486                 old->release_fb = fb;
8487         } else
8488                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8489         if (IS_ERR(fb)) {
8490                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8491                 goto fail;
8492         }
8493
8494         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8495                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8496                 if (old->release_fb)
8497                         old->release_fb->funcs->destroy(old->release_fb);
8498                 goto fail;
8499         }
8500
8501         /* let the connector get through one full cycle before testing */
8502         intel_wait_for_vblank(dev, intel_crtc->pipe);
8503         return true;
8504
8505  fail:
8506         intel_crtc->new_enabled = crtc->enabled;
8507         if (intel_crtc->new_enabled)
8508                 intel_crtc->new_config = &intel_crtc->config;
8509         else
8510                 intel_crtc->new_config = NULL;
8511 fail_unlock:
8512         if (ret == -EDEADLK) {
8513                 drm_modeset_backoff(ctx);
8514                 goto retry;
8515         }
8516
8517         drm_modeset_drop_locks(ctx);
8518         drm_modeset_acquire_fini(ctx);
8519
8520         return false;
8521 }
8522
8523 void intel_release_load_detect_pipe(struct drm_connector *connector,
8524                                     struct intel_load_detect_pipe *old,
8525                                     struct drm_modeset_acquire_ctx *ctx)
8526 {
8527         struct intel_encoder *intel_encoder =
8528                 intel_attached_encoder(connector);
8529         struct drm_encoder *encoder = &intel_encoder->base;
8530         struct drm_crtc *crtc = encoder->crtc;
8531         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8532
8533         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8534                       connector->base.id, connector->name,
8535                       encoder->base.id, encoder->name);
8536
8537         if (old->load_detect_temp) {
8538                 to_intel_connector(connector)->new_encoder = NULL;
8539                 intel_encoder->new_crtc = NULL;
8540                 intel_crtc->new_enabled = false;
8541                 intel_crtc->new_config = NULL;
8542                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8543
8544                 if (old->release_fb) {
8545                         drm_framebuffer_unregister_private(old->release_fb);
8546                         drm_framebuffer_unreference(old->release_fb);
8547                 }
8548
8549                 goto unlock;
8550                 return;
8551         }
8552
8553         /* Switch crtc and encoder back off if necessary */
8554         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8555                 connector->funcs->dpms(connector, old->dpms_mode);
8556
8557 unlock:
8558         drm_modeset_drop_locks(ctx);
8559         drm_modeset_acquire_fini(ctx);
8560 }
8561
8562 static int i9xx_pll_refclk(struct drm_device *dev,
8563                            const struct intel_crtc_config *pipe_config)
8564 {
8565         struct drm_i915_private *dev_priv = dev->dev_private;
8566         u32 dpll = pipe_config->dpll_hw_state.dpll;
8567
8568         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8569                 return dev_priv->vbt.lvds_ssc_freq;
8570         else if (HAS_PCH_SPLIT(dev))
8571                 return 120000;
8572         else if (!IS_GEN2(dev))
8573                 return 96000;
8574         else
8575                 return 48000;
8576 }
8577
8578 /* Returns the clock of the currently programmed mode of the given pipe. */
8579 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8580                                 struct intel_crtc_config *pipe_config)
8581 {
8582         struct drm_device *dev = crtc->base.dev;
8583         struct drm_i915_private *dev_priv = dev->dev_private;
8584         int pipe = pipe_config->cpu_transcoder;
8585         u32 dpll = pipe_config->dpll_hw_state.dpll;
8586         u32 fp;
8587         intel_clock_t clock;
8588         int refclk = i9xx_pll_refclk(dev, pipe_config);
8589
8590         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8591                 fp = pipe_config->dpll_hw_state.fp0;
8592         else
8593                 fp = pipe_config->dpll_hw_state.fp1;
8594
8595         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8596         if (IS_PINEVIEW(dev)) {
8597                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8598                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8599         } else {
8600                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8601                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8602         }
8603
8604         if (!IS_GEN2(dev)) {
8605                 if (IS_PINEVIEW(dev))
8606                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8607                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8608                 else
8609                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8610                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8611
8612                 switch (dpll & DPLL_MODE_MASK) {
8613                 case DPLLB_MODE_DAC_SERIAL:
8614                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8615                                 5 : 10;
8616                         break;
8617                 case DPLLB_MODE_LVDS:
8618                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8619                                 7 : 14;
8620                         break;
8621                 default:
8622                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8623                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8624                         return;
8625                 }
8626
8627                 if (IS_PINEVIEW(dev))
8628                         pineview_clock(refclk, &clock);
8629                 else
8630                         i9xx_clock(refclk, &clock);
8631         } else {
8632                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8633                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8634
8635                 if (is_lvds) {
8636                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8637                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8638
8639                         if (lvds & LVDS_CLKB_POWER_UP)
8640                                 clock.p2 = 7;
8641                         else
8642                                 clock.p2 = 14;
8643                 } else {
8644                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8645                                 clock.p1 = 2;
8646                         else {
8647                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8648                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8649                         }
8650                         if (dpll & PLL_P2_DIVIDE_BY_4)
8651                                 clock.p2 = 4;
8652                         else
8653                                 clock.p2 = 2;
8654                 }
8655
8656                 i9xx_clock(refclk, &clock);
8657         }
8658
8659         /*
8660          * This value includes pixel_multiplier. We will use
8661          * port_clock to compute adjusted_mode.crtc_clock in the
8662          * encoder's get_config() function.
8663          */
8664         pipe_config->port_clock = clock.dot;
8665 }
8666
8667 int intel_dotclock_calculate(int link_freq,
8668                              const struct intel_link_m_n *m_n)
8669 {
8670         /*
8671          * The calculation for the data clock is:
8672          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8673          * But we want to avoid losing precison if possible, so:
8674          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8675          *
8676          * and the link clock is simpler:
8677          * link_clock = (m * link_clock) / n
8678          */
8679
8680         if (!m_n->link_n)
8681                 return 0;
8682
8683         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8684 }
8685
8686 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8687                                    struct intel_crtc_config *pipe_config)
8688 {
8689         struct drm_device *dev = crtc->base.dev;
8690
8691         /* read out port_clock from the DPLL */
8692         i9xx_crtc_clock_get(crtc, pipe_config);
8693
8694         /*
8695          * This value does not include pixel_multiplier.
8696          * We will check that port_clock and adjusted_mode.crtc_clock
8697          * agree once we know their relationship in the encoder's
8698          * get_config() function.
8699          */
8700         pipe_config->adjusted_mode.crtc_clock =
8701                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8702                                          &pipe_config->fdi_m_n);
8703 }
8704
8705 /** Returns the currently programmed mode of the given pipe. */
8706 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8707                                              struct drm_crtc *crtc)
8708 {
8709         struct drm_i915_private *dev_priv = dev->dev_private;
8710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8711         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8712         struct drm_display_mode *mode;
8713         struct intel_crtc_config pipe_config;
8714         int htot = I915_READ(HTOTAL(cpu_transcoder));
8715         int hsync = I915_READ(HSYNC(cpu_transcoder));
8716         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8717         int vsync = I915_READ(VSYNC(cpu_transcoder));
8718         enum pipe pipe = intel_crtc->pipe;
8719
8720         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8721         if (!mode)
8722                 return NULL;
8723
8724         /*
8725          * Construct a pipe_config sufficient for getting the clock info
8726          * back out of crtc_clock_get.
8727          *
8728          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8729          * to use a real value here instead.
8730          */
8731         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8732         pipe_config.pixel_multiplier = 1;
8733         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8734         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8735         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8736         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8737
8738         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8739         mode->hdisplay = (htot & 0xffff) + 1;
8740         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8741         mode->hsync_start = (hsync & 0xffff) + 1;
8742         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8743         mode->vdisplay = (vtot & 0xffff) + 1;
8744         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8745         mode->vsync_start = (vsync & 0xffff) + 1;
8746         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8747
8748         drm_mode_set_name(mode);
8749
8750         return mode;
8751 }
8752
8753 static void intel_increase_pllclock(struct drm_device *dev,
8754                                     enum pipe pipe)
8755 {
8756         struct drm_i915_private *dev_priv = dev->dev_private;
8757         int dpll_reg = DPLL(pipe);
8758         int dpll;
8759
8760         if (HAS_PCH_SPLIT(dev))
8761                 return;
8762
8763         if (!dev_priv->lvds_downclock_avail)
8764                 return;
8765
8766         dpll = I915_READ(dpll_reg);
8767         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8768                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8769
8770                 assert_panel_unlocked(dev_priv, pipe);
8771
8772                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8773                 I915_WRITE(dpll_reg, dpll);
8774                 intel_wait_for_vblank(dev, pipe);
8775
8776                 dpll = I915_READ(dpll_reg);
8777                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8778                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8779         }
8780 }
8781
8782 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8783 {
8784         struct drm_device *dev = crtc->dev;
8785         struct drm_i915_private *dev_priv = dev->dev_private;
8786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8787
8788         if (HAS_PCH_SPLIT(dev))
8789                 return;
8790
8791         if (!dev_priv->lvds_downclock_avail)
8792                 return;
8793
8794         /*
8795          * Since this is called by a timer, we should never get here in
8796          * the manual case.
8797          */
8798         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8799                 int pipe = intel_crtc->pipe;
8800                 int dpll_reg = DPLL(pipe);
8801                 int dpll;
8802
8803                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8804
8805                 assert_panel_unlocked(dev_priv, pipe);
8806
8807                 dpll = I915_READ(dpll_reg);
8808                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8809                 I915_WRITE(dpll_reg, dpll);
8810                 intel_wait_for_vblank(dev, pipe);
8811                 dpll = I915_READ(dpll_reg);
8812                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8813                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8814         }
8815
8816 }
8817
8818 void intel_mark_busy(struct drm_device *dev)
8819 {
8820         struct drm_i915_private *dev_priv = dev->dev_private;
8821
8822         if (dev_priv->mm.busy)
8823                 return;
8824
8825         intel_runtime_pm_get(dev_priv);
8826         i915_update_gfx_val(dev_priv);
8827         dev_priv->mm.busy = true;
8828 }
8829
8830 void intel_mark_idle(struct drm_device *dev)
8831 {
8832         struct drm_i915_private *dev_priv = dev->dev_private;
8833         struct drm_crtc *crtc;
8834
8835         if (!dev_priv->mm.busy)
8836                 return;
8837
8838         dev_priv->mm.busy = false;
8839
8840         if (!i915.powersave)
8841                 goto out;
8842
8843         for_each_crtc(dev, crtc) {
8844                 if (!crtc->primary->fb)
8845                         continue;
8846
8847                 intel_decrease_pllclock(crtc);
8848         }
8849
8850         if (INTEL_INFO(dev)->gen >= 6)
8851                 gen6_rps_idle(dev->dev_private);
8852
8853 out:
8854         intel_runtime_pm_put(dev_priv);
8855 }
8856
8857
8858 /**
8859  * intel_mark_fb_busy - mark given planes as busy
8860  * @dev: DRM device
8861  * @frontbuffer_bits: bits for the affected planes
8862  * @ring: optional ring for asynchronous commands
8863  *
8864  * This function gets called every time the screen contents change. It can be
8865  * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8866  */
8867 static void intel_mark_fb_busy(struct drm_device *dev,
8868                                unsigned frontbuffer_bits,
8869                                struct intel_engine_cs *ring)
8870 {
8871         enum pipe pipe;
8872
8873         if (!i915.powersave)
8874                 return;
8875
8876         for_each_pipe(pipe) {
8877                 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8878                         continue;
8879
8880                 intel_increase_pllclock(dev, pipe);
8881                 if (ring && intel_fbc_enabled(dev))
8882                         ring->fbc_dirty = true;
8883         }
8884 }
8885
8886 /**
8887  * intel_fb_obj_invalidate - invalidate frontbuffer object
8888  * @obj: GEM object to invalidate
8889  * @ring: set for asynchronous rendering
8890  *
8891  * This function gets called every time rendering on the given object starts and
8892  * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8893  * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8894  * until the rendering completes or a flip on this frontbuffer plane is
8895  * scheduled.
8896  */
8897 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8898                              struct intel_engine_cs *ring)
8899 {
8900         struct drm_device *dev = obj->base.dev;
8901         struct drm_i915_private *dev_priv = dev->dev_private;
8902
8903         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8904
8905         if (!obj->frontbuffer_bits)
8906                 return;
8907
8908         if (ring) {
8909                 mutex_lock(&dev_priv->fb_tracking.lock);
8910                 dev_priv->fb_tracking.busy_bits
8911                         |= obj->frontbuffer_bits;
8912                 dev_priv->fb_tracking.flip_bits
8913                         &= ~obj->frontbuffer_bits;
8914                 mutex_unlock(&dev_priv->fb_tracking.lock);
8915         }
8916
8917         intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8918
8919         intel_edp_psr_exit(dev);
8920 }
8921
8922 /**
8923  * intel_frontbuffer_flush - flush frontbuffer
8924  * @dev: DRM device
8925  * @frontbuffer_bits: frontbuffer plane tracking bits
8926  *
8927  * This function gets called every time rendering on the given planes has
8928  * completed and frontbuffer caching can be started again. Flushes will get
8929  * delayed if they're blocked by some oustanding asynchronous rendering.
8930  *
8931  * Can be called without any locks held.
8932  */
8933 void intel_frontbuffer_flush(struct drm_device *dev,
8934                              unsigned frontbuffer_bits)
8935 {
8936         struct drm_i915_private *dev_priv = dev->dev_private;
8937
8938         /* Delay flushing when rings are still busy.*/
8939         mutex_lock(&dev_priv->fb_tracking.lock);
8940         frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
8941         mutex_unlock(&dev_priv->fb_tracking.lock);
8942
8943         intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
8944
8945         intel_edp_psr_exit(dev);
8946 }
8947
8948 /**
8949  * intel_fb_obj_flush - flush frontbuffer object
8950  * @obj: GEM object to flush
8951  * @retire: set when retiring asynchronous rendering
8952  *
8953  * This function gets called every time rendering on the given object has
8954  * completed and frontbuffer caching can be started again. If @retire is true
8955  * then any delayed flushes will be unblocked.
8956  */
8957 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
8958                         bool retire)
8959 {
8960         struct drm_device *dev = obj->base.dev;
8961         struct drm_i915_private *dev_priv = dev->dev_private;
8962         unsigned frontbuffer_bits;
8963
8964         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8965
8966         if (!obj->frontbuffer_bits)
8967                 return;
8968
8969         frontbuffer_bits = obj->frontbuffer_bits;
8970
8971         if (retire) {
8972                 mutex_lock(&dev_priv->fb_tracking.lock);
8973                 /* Filter out new bits since rendering started. */
8974                 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
8975
8976                 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
8977                 mutex_unlock(&dev_priv->fb_tracking.lock);
8978         }
8979
8980         intel_frontbuffer_flush(dev, frontbuffer_bits);
8981 }
8982
8983 /**
8984  * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
8985  * @dev: DRM device
8986  * @frontbuffer_bits: frontbuffer plane tracking bits
8987  *
8988  * This function gets called after scheduling a flip on @obj. The actual
8989  * frontbuffer flushing will be delayed until completion is signalled with
8990  * intel_frontbuffer_flip_complete. If an invalidate happens in between this
8991  * flush will be cancelled.
8992  *
8993  * Can be called without any locks held.
8994  */
8995 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
8996                                     unsigned frontbuffer_bits)
8997 {
8998         struct drm_i915_private *dev_priv = dev->dev_private;
8999
9000         mutex_lock(&dev_priv->fb_tracking.lock);
9001         dev_priv->fb_tracking.flip_bits
9002                 |= frontbuffer_bits;
9003         mutex_unlock(&dev_priv->fb_tracking.lock);
9004 }
9005
9006 /**
9007  * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9008  * @dev: DRM device
9009  * @frontbuffer_bits: frontbuffer plane tracking bits
9010  *
9011  * This function gets called after the flip has been latched and will complete
9012  * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9013  *
9014  * Can be called without any locks held.
9015  */
9016 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9017                                      unsigned frontbuffer_bits)
9018 {
9019         struct drm_i915_private *dev_priv = dev->dev_private;
9020
9021         mutex_lock(&dev_priv->fb_tracking.lock);
9022         /* Mask any cancelled flips. */
9023         frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9024         dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9025         mutex_unlock(&dev_priv->fb_tracking.lock);
9026
9027         intel_frontbuffer_flush(dev, frontbuffer_bits);
9028 }
9029
9030 static void intel_crtc_destroy(struct drm_crtc *crtc)
9031 {
9032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9033         struct drm_device *dev = crtc->dev;
9034         struct intel_unpin_work *work;
9035         unsigned long flags;
9036
9037         spin_lock_irqsave(&dev->event_lock, flags);
9038         work = intel_crtc->unpin_work;
9039         intel_crtc->unpin_work = NULL;
9040         spin_unlock_irqrestore(&dev->event_lock, flags);
9041
9042         if (work) {
9043                 cancel_work_sync(&work->work);
9044                 kfree(work);
9045         }
9046
9047         drm_crtc_cleanup(crtc);
9048
9049         kfree(intel_crtc);
9050 }
9051
9052 static void intel_unpin_work_fn(struct work_struct *__work)
9053 {
9054         struct intel_unpin_work *work =
9055                 container_of(__work, struct intel_unpin_work, work);
9056         struct drm_device *dev = work->crtc->dev;
9057         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9058
9059         mutex_lock(&dev->struct_mutex);
9060         intel_unpin_fb_obj(work->old_fb_obj);
9061         drm_gem_object_unreference(&work->pending_flip_obj->base);
9062         drm_gem_object_unreference(&work->old_fb_obj->base);
9063
9064         intel_update_fbc(dev);
9065         mutex_unlock(&dev->struct_mutex);
9066
9067         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9068
9069         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9070         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9071
9072         kfree(work);
9073 }
9074
9075 static void do_intel_finish_page_flip(struct drm_device *dev,
9076                                       struct drm_crtc *crtc)
9077 {
9078         struct drm_i915_private *dev_priv = dev->dev_private;
9079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9080         struct intel_unpin_work *work;
9081         unsigned long flags;
9082
9083         /* Ignore early vblank irqs */
9084         if (intel_crtc == NULL)
9085                 return;
9086
9087         spin_lock_irqsave(&dev->event_lock, flags);
9088         work = intel_crtc->unpin_work;
9089
9090         /* Ensure we don't miss a work->pending update ... */
9091         smp_rmb();
9092
9093         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9094                 spin_unlock_irqrestore(&dev->event_lock, flags);
9095                 return;
9096         }
9097
9098         /* and that the unpin work is consistent wrt ->pending. */
9099         smp_rmb();
9100
9101         intel_crtc->unpin_work = NULL;
9102
9103         if (work->event)
9104                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9105
9106         drm_crtc_vblank_put(crtc);
9107
9108         spin_unlock_irqrestore(&dev->event_lock, flags);
9109
9110         wake_up_all(&dev_priv->pending_flip_queue);
9111
9112         queue_work(dev_priv->wq, &work->work);
9113
9114         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9115 }
9116
9117 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9118 {
9119         struct drm_i915_private *dev_priv = dev->dev_private;
9120         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9121
9122         do_intel_finish_page_flip(dev, crtc);
9123 }
9124
9125 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9126 {
9127         struct drm_i915_private *dev_priv = dev->dev_private;
9128         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9129
9130         do_intel_finish_page_flip(dev, crtc);
9131 }
9132
9133 /* Is 'a' after or equal to 'b'? */
9134 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9135 {
9136         return !((a - b) & 0x80000000);
9137 }
9138
9139 static bool page_flip_finished(struct intel_crtc *crtc)
9140 {
9141         struct drm_device *dev = crtc->base.dev;
9142         struct drm_i915_private *dev_priv = dev->dev_private;
9143
9144         /*
9145          * The relevant registers doen't exist on pre-ctg.
9146          * As the flip done interrupt doesn't trigger for mmio
9147          * flips on gmch platforms, a flip count check isn't
9148          * really needed there. But since ctg has the registers,
9149          * include it in the check anyway.
9150          */
9151         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9152                 return true;
9153
9154         /*
9155          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9156          * used the same base address. In that case the mmio flip might
9157          * have completed, but the CS hasn't even executed the flip yet.
9158          *
9159          * A flip count check isn't enough as the CS might have updated
9160          * the base address just after start of vblank, but before we
9161          * managed to process the interrupt. This means we'd complete the
9162          * CS flip too soon.
9163          *
9164          * Combining both checks should get us a good enough result. It may
9165          * still happen that the CS flip has been executed, but has not
9166          * yet actually completed. But in case the base address is the same
9167          * anyway, we don't really care.
9168          */
9169         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9170                 crtc->unpin_work->gtt_offset &&
9171                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9172                                     crtc->unpin_work->flip_count);
9173 }
9174
9175 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9176 {
9177         struct drm_i915_private *dev_priv = dev->dev_private;
9178         struct intel_crtc *intel_crtc =
9179                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9180         unsigned long flags;
9181
9182         /* NB: An MMIO update of the plane base pointer will also
9183          * generate a page-flip completion irq, i.e. every modeset
9184          * is also accompanied by a spurious intel_prepare_page_flip().
9185          */
9186         spin_lock_irqsave(&dev->event_lock, flags);
9187         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9188                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9189         spin_unlock_irqrestore(&dev->event_lock, flags);
9190 }
9191
9192 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9193 {
9194         /* Ensure that the work item is consistent when activating it ... */
9195         smp_wmb();
9196         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9197         /* and that it is marked active as soon as the irq could fire. */
9198         smp_wmb();
9199 }
9200
9201 static int intel_gen2_queue_flip(struct drm_device *dev,
9202                                  struct drm_crtc *crtc,
9203                                  struct drm_framebuffer *fb,
9204                                  struct drm_i915_gem_object *obj,
9205                                  struct intel_engine_cs *ring,
9206                                  uint32_t flags)
9207 {
9208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9209         u32 flip_mask;
9210         int ret;
9211
9212         ret = intel_ring_begin(ring, 6);
9213         if (ret)
9214                 return ret;
9215
9216         /* Can't queue multiple flips, so wait for the previous
9217          * one to finish before executing the next.
9218          */
9219         if (intel_crtc->plane)
9220                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9221         else
9222                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9223         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9224         intel_ring_emit(ring, MI_NOOP);
9225         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9226                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9227         intel_ring_emit(ring, fb->pitches[0]);
9228         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9229         intel_ring_emit(ring, 0); /* aux display base address, unused */
9230
9231         intel_mark_page_flip_active(intel_crtc);
9232         __intel_ring_advance(ring);
9233         return 0;
9234 }
9235
9236 static int intel_gen3_queue_flip(struct drm_device *dev,
9237                                  struct drm_crtc *crtc,
9238                                  struct drm_framebuffer *fb,
9239                                  struct drm_i915_gem_object *obj,
9240                                  struct intel_engine_cs *ring,
9241                                  uint32_t flags)
9242 {
9243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9244         u32 flip_mask;
9245         int ret;
9246
9247         ret = intel_ring_begin(ring, 6);
9248         if (ret)
9249                 return ret;
9250
9251         if (intel_crtc->plane)
9252                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9253         else
9254                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9255         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9256         intel_ring_emit(ring, MI_NOOP);
9257         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9258                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9259         intel_ring_emit(ring, fb->pitches[0]);
9260         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9261         intel_ring_emit(ring, MI_NOOP);
9262
9263         intel_mark_page_flip_active(intel_crtc);
9264         __intel_ring_advance(ring);
9265         return 0;
9266 }
9267
9268 static int intel_gen4_queue_flip(struct drm_device *dev,
9269                                  struct drm_crtc *crtc,
9270                                  struct drm_framebuffer *fb,
9271                                  struct drm_i915_gem_object *obj,
9272                                  struct intel_engine_cs *ring,
9273                                  uint32_t flags)
9274 {
9275         struct drm_i915_private *dev_priv = dev->dev_private;
9276         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9277         uint32_t pf, pipesrc;
9278         int ret;
9279
9280         ret = intel_ring_begin(ring, 4);
9281         if (ret)
9282                 return ret;
9283
9284         /* i965+ uses the linear or tiled offsets from the
9285          * Display Registers (which do not change across a page-flip)
9286          * so we need only reprogram the base address.
9287          */
9288         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9289                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9290         intel_ring_emit(ring, fb->pitches[0]);
9291         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9292                         obj->tiling_mode);
9293
9294         /* XXX Enabling the panel-fitter across page-flip is so far
9295          * untested on non-native modes, so ignore it for now.
9296          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9297          */
9298         pf = 0;
9299         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9300         intel_ring_emit(ring, pf | pipesrc);
9301
9302         intel_mark_page_flip_active(intel_crtc);
9303         __intel_ring_advance(ring);
9304         return 0;
9305 }
9306
9307 static int intel_gen6_queue_flip(struct drm_device *dev,
9308                                  struct drm_crtc *crtc,
9309                                  struct drm_framebuffer *fb,
9310                                  struct drm_i915_gem_object *obj,
9311                                  struct intel_engine_cs *ring,
9312                                  uint32_t flags)
9313 {
9314         struct drm_i915_private *dev_priv = dev->dev_private;
9315         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9316         uint32_t pf, pipesrc;
9317         int ret;
9318
9319         ret = intel_ring_begin(ring, 4);
9320         if (ret)
9321                 return ret;
9322
9323         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9324                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9325         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9326         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9327
9328         /* Contrary to the suggestions in the documentation,
9329          * "Enable Panel Fitter" does not seem to be required when page
9330          * flipping with a non-native mode, and worse causes a normal
9331          * modeset to fail.
9332          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9333          */
9334         pf = 0;
9335         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9336         intel_ring_emit(ring, pf | pipesrc);
9337
9338         intel_mark_page_flip_active(intel_crtc);
9339         __intel_ring_advance(ring);
9340         return 0;
9341 }
9342
9343 static int intel_gen7_queue_flip(struct drm_device *dev,
9344                                  struct drm_crtc *crtc,
9345                                  struct drm_framebuffer *fb,
9346                                  struct drm_i915_gem_object *obj,
9347                                  struct intel_engine_cs *ring,
9348                                  uint32_t flags)
9349 {
9350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9351         uint32_t plane_bit = 0;
9352         int len, ret;
9353
9354         switch (intel_crtc->plane) {
9355         case PLANE_A:
9356                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9357                 break;
9358         case PLANE_B:
9359                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9360                 break;
9361         case PLANE_C:
9362                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9363                 break;
9364         default:
9365                 WARN_ONCE(1, "unknown plane in flip command\n");
9366                 return -ENODEV;
9367         }
9368
9369         len = 4;
9370         if (ring->id == RCS) {
9371                 len += 6;
9372                 /*
9373                  * On Gen 8, SRM is now taking an extra dword to accommodate
9374                  * 48bits addresses, and we need a NOOP for the batch size to
9375                  * stay even.
9376                  */
9377                 if (IS_GEN8(dev))
9378                         len += 2;
9379         }
9380
9381         /*
9382          * BSpec MI_DISPLAY_FLIP for IVB:
9383          * "The full packet must be contained within the same cache line."
9384          *
9385          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9386          * cacheline, if we ever start emitting more commands before
9387          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9388          * then do the cacheline alignment, and finally emit the
9389          * MI_DISPLAY_FLIP.
9390          */
9391         ret = intel_ring_cacheline_align(ring);
9392         if (ret)
9393                 return ret;
9394
9395         ret = intel_ring_begin(ring, len);
9396         if (ret)
9397                 return ret;
9398
9399         /* Unmask the flip-done completion message. Note that the bspec says that
9400          * we should do this for both the BCS and RCS, and that we must not unmask
9401          * more than one flip event at any time (or ensure that one flip message
9402          * can be sent by waiting for flip-done prior to queueing new flips).
9403          * Experimentation says that BCS works despite DERRMR masking all
9404          * flip-done completion events and that unmasking all planes at once
9405          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9406          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9407          */
9408         if (ring->id == RCS) {
9409                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9410                 intel_ring_emit(ring, DERRMR);
9411                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9412                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9413                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9414                 if (IS_GEN8(dev))
9415                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9416                                               MI_SRM_LRM_GLOBAL_GTT);
9417                 else
9418                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9419                                               MI_SRM_LRM_GLOBAL_GTT);
9420                 intel_ring_emit(ring, DERRMR);
9421                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9422                 if (IS_GEN8(dev)) {
9423                         intel_ring_emit(ring, 0);
9424                         intel_ring_emit(ring, MI_NOOP);
9425                 }
9426         }
9427
9428         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9429         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9430         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9431         intel_ring_emit(ring, (MI_NOOP));
9432
9433         intel_mark_page_flip_active(intel_crtc);
9434         __intel_ring_advance(ring);
9435         return 0;
9436 }
9437
9438 static bool use_mmio_flip(struct intel_engine_cs *ring,
9439                           struct drm_i915_gem_object *obj)
9440 {
9441         /*
9442          * This is not being used for older platforms, because
9443          * non-availability of flip done interrupt forces us to use
9444          * CS flips. Older platforms derive flip done using some clever
9445          * tricks involving the flip_pending status bits and vblank irqs.
9446          * So using MMIO flips there would disrupt this mechanism.
9447          */
9448
9449         if (INTEL_INFO(ring->dev)->gen < 5)
9450                 return false;
9451
9452         if (i915.use_mmio_flip < 0)
9453                 return false;
9454         else if (i915.use_mmio_flip > 0)
9455                 return true;
9456         else
9457                 return ring != obj->ring;
9458 }
9459
9460 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9461 {
9462         struct drm_device *dev = intel_crtc->base.dev;
9463         struct drm_i915_private *dev_priv = dev->dev_private;
9464         struct intel_framebuffer *intel_fb =
9465                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9466         struct drm_i915_gem_object *obj = intel_fb->obj;
9467         u32 dspcntr;
9468         u32 reg;
9469
9470         intel_mark_page_flip_active(intel_crtc);
9471
9472         reg = DSPCNTR(intel_crtc->plane);
9473         dspcntr = I915_READ(reg);
9474
9475         if (INTEL_INFO(dev)->gen >= 4) {
9476                 if (obj->tiling_mode != I915_TILING_NONE)
9477                         dspcntr |= DISPPLANE_TILED;
9478                 else
9479                         dspcntr &= ~DISPPLANE_TILED;
9480         }
9481         I915_WRITE(reg, dspcntr);
9482
9483         I915_WRITE(DSPSURF(intel_crtc->plane),
9484                    intel_crtc->unpin_work->gtt_offset);
9485         POSTING_READ(DSPSURF(intel_crtc->plane));
9486 }
9487
9488 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9489 {
9490         struct intel_engine_cs *ring;
9491         int ret;
9492
9493         lockdep_assert_held(&obj->base.dev->struct_mutex);
9494
9495         if (!obj->last_write_seqno)
9496                 return 0;
9497
9498         ring = obj->ring;
9499
9500         if (i915_seqno_passed(ring->get_seqno(ring, true),
9501                               obj->last_write_seqno))
9502                 return 0;
9503
9504         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9505         if (ret)
9506                 return ret;
9507
9508         if (WARN_ON(!ring->irq_get(ring)))
9509                 return 0;
9510
9511         return 1;
9512 }
9513
9514 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9515 {
9516         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9517         struct intel_crtc *intel_crtc;
9518         unsigned long irq_flags;
9519         u32 seqno;
9520
9521         seqno = ring->get_seqno(ring, false);
9522
9523         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9524         for_each_intel_crtc(ring->dev, intel_crtc) {
9525                 struct intel_mmio_flip *mmio_flip;
9526
9527                 mmio_flip = &intel_crtc->mmio_flip;
9528                 if (mmio_flip->seqno == 0)
9529                         continue;
9530
9531                 if (ring->id != mmio_flip->ring_id)
9532                         continue;
9533
9534                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9535                         intel_do_mmio_flip(intel_crtc);
9536                         mmio_flip->seqno = 0;
9537                         ring->irq_put(ring);
9538                 }
9539         }
9540         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9541 }
9542
9543 static int intel_queue_mmio_flip(struct drm_device *dev,
9544                                  struct drm_crtc *crtc,
9545                                  struct drm_framebuffer *fb,
9546                                  struct drm_i915_gem_object *obj,
9547                                  struct intel_engine_cs *ring,
9548                                  uint32_t flags)
9549 {
9550         struct drm_i915_private *dev_priv = dev->dev_private;
9551         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9552         unsigned long irq_flags;
9553         int ret;
9554
9555         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9556                 return -EBUSY;
9557
9558         ret = intel_postpone_flip(obj);
9559         if (ret < 0)
9560                 return ret;
9561         if (ret == 0) {
9562                 intel_do_mmio_flip(intel_crtc);
9563                 return 0;
9564         }
9565
9566         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9567         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9568         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9569         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9570
9571         /*
9572          * Double check to catch cases where irq fired before
9573          * mmio flip data was ready
9574          */
9575         intel_notify_mmio_flip(obj->ring);
9576         return 0;
9577 }
9578
9579 static int intel_default_queue_flip(struct drm_device *dev,
9580                                     struct drm_crtc *crtc,
9581                                     struct drm_framebuffer *fb,
9582                                     struct drm_i915_gem_object *obj,
9583                                     struct intel_engine_cs *ring,
9584                                     uint32_t flags)
9585 {
9586         return -ENODEV;
9587 }
9588
9589 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9590                                 struct drm_framebuffer *fb,
9591                                 struct drm_pending_vblank_event *event,
9592                                 uint32_t page_flip_flags)
9593 {
9594         struct drm_device *dev = crtc->dev;
9595         struct drm_i915_private *dev_priv = dev->dev_private;
9596         struct drm_framebuffer *old_fb = crtc->primary->fb;
9597         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9598         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9599         enum pipe pipe = intel_crtc->pipe;
9600         struct intel_unpin_work *work;
9601         struct intel_engine_cs *ring;
9602         unsigned long flags;
9603         int ret;
9604
9605         /* Can't change pixel format via MI display flips. */
9606         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9607                 return -EINVAL;
9608
9609         /*
9610          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9611          * Note that pitch changes could also affect these register.
9612          */
9613         if (INTEL_INFO(dev)->gen > 3 &&
9614             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9615              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9616                 return -EINVAL;
9617
9618         if (i915_terminally_wedged(&dev_priv->gpu_error))
9619                 goto out_hang;
9620
9621         work = kzalloc(sizeof(*work), GFP_KERNEL);
9622         if (work == NULL)
9623                 return -ENOMEM;
9624
9625         work->event = event;
9626         work->crtc = crtc;
9627         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9628         INIT_WORK(&work->work, intel_unpin_work_fn);
9629
9630         ret = drm_crtc_vblank_get(crtc);
9631         if (ret)
9632                 goto free_work;
9633
9634         /* We borrow the event spin lock for protecting unpin_work */
9635         spin_lock_irqsave(&dev->event_lock, flags);
9636         if (intel_crtc->unpin_work) {
9637                 spin_unlock_irqrestore(&dev->event_lock, flags);
9638                 kfree(work);
9639                 drm_crtc_vblank_put(crtc);
9640
9641                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9642                 return -EBUSY;
9643         }
9644         intel_crtc->unpin_work = work;
9645         spin_unlock_irqrestore(&dev->event_lock, flags);
9646
9647         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9648                 flush_workqueue(dev_priv->wq);
9649
9650         ret = i915_mutex_lock_interruptible(dev);
9651         if (ret)
9652                 goto cleanup;
9653
9654         /* Reference the objects for the scheduled work. */
9655         drm_gem_object_reference(&work->old_fb_obj->base);
9656         drm_gem_object_reference(&obj->base);
9657
9658         crtc->primary->fb = fb;
9659
9660         work->pending_flip_obj = obj;
9661
9662         work->enable_stall_check = true;
9663
9664         atomic_inc(&intel_crtc->unpin_work_count);
9665         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9666
9667         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9668                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9669
9670         if (IS_VALLEYVIEW(dev)) {
9671                 ring = &dev_priv->ring[BCS];
9672         } else if (INTEL_INFO(dev)->gen >= 7) {
9673                 ring = obj->ring;
9674                 if (ring == NULL || ring->id != RCS)
9675                         ring = &dev_priv->ring[BCS];
9676         } else {
9677                 ring = &dev_priv->ring[RCS];
9678         }
9679
9680         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9681         if (ret)
9682                 goto cleanup_pending;
9683
9684         work->gtt_offset =
9685                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9686
9687         if (use_mmio_flip(ring, obj))
9688                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9689                                             page_flip_flags);
9690         else
9691                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9692                                 page_flip_flags);
9693         if (ret)
9694                 goto cleanup_unpin;
9695
9696         i915_gem_track_fb(work->old_fb_obj, obj,
9697                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9698
9699         intel_disable_fbc(dev);
9700         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9701         mutex_unlock(&dev->struct_mutex);
9702
9703         trace_i915_flip_request(intel_crtc->plane, obj);
9704
9705         return 0;
9706
9707 cleanup_unpin:
9708         intel_unpin_fb_obj(obj);
9709 cleanup_pending:
9710         atomic_dec(&intel_crtc->unpin_work_count);
9711         crtc->primary->fb = old_fb;
9712         drm_gem_object_unreference(&work->old_fb_obj->base);
9713         drm_gem_object_unreference(&obj->base);
9714         mutex_unlock(&dev->struct_mutex);
9715
9716 cleanup:
9717         spin_lock_irqsave(&dev->event_lock, flags);
9718         intel_crtc->unpin_work = NULL;
9719         spin_unlock_irqrestore(&dev->event_lock, flags);
9720
9721         drm_crtc_vblank_put(crtc);
9722 free_work:
9723         kfree(work);
9724
9725         if (ret == -EIO) {
9726 out_hang:
9727                 intel_crtc_wait_for_pending_flips(crtc);
9728                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9729                 if (ret == 0 && event)
9730                         drm_send_vblank_event(dev, pipe, event);
9731         }
9732         return ret;
9733 }
9734
9735 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9736         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9737         .load_lut = intel_crtc_load_lut,
9738 };
9739
9740 /**
9741  * intel_modeset_update_staged_output_state
9742  *
9743  * Updates the staged output configuration state, e.g. after we've read out the
9744  * current hw state.
9745  */
9746 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9747 {
9748         struct intel_crtc *crtc;
9749         struct intel_encoder *encoder;
9750         struct intel_connector *connector;
9751
9752         list_for_each_entry(connector, &dev->mode_config.connector_list,
9753                             base.head) {
9754                 connector->new_encoder =
9755                         to_intel_encoder(connector->base.encoder);
9756         }
9757
9758         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9759                             base.head) {
9760                 encoder->new_crtc =
9761                         to_intel_crtc(encoder->base.crtc);
9762         }
9763
9764         for_each_intel_crtc(dev, crtc) {
9765                 crtc->new_enabled = crtc->base.enabled;
9766
9767                 if (crtc->new_enabled)
9768                         crtc->new_config = &crtc->config;
9769                 else
9770                         crtc->new_config = NULL;
9771         }
9772 }
9773
9774 /**
9775  * intel_modeset_commit_output_state
9776  *
9777  * This function copies the stage display pipe configuration to the real one.
9778  */
9779 static void intel_modeset_commit_output_state(struct drm_device *dev)
9780 {
9781         struct intel_crtc *crtc;
9782         struct intel_encoder *encoder;
9783         struct intel_connector *connector;
9784
9785         list_for_each_entry(connector, &dev->mode_config.connector_list,
9786                             base.head) {
9787                 connector->base.encoder = &connector->new_encoder->base;
9788         }
9789
9790         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9791                             base.head) {
9792                 encoder->base.crtc = &encoder->new_crtc->base;
9793         }
9794
9795         for_each_intel_crtc(dev, crtc) {
9796                 crtc->base.enabled = crtc->new_enabled;
9797         }
9798 }
9799
9800 static void
9801 connected_sink_compute_bpp(struct intel_connector *connector,
9802                            struct intel_crtc_config *pipe_config)
9803 {
9804         int bpp = pipe_config->pipe_bpp;
9805
9806         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9807                 connector->base.base.id,
9808                 connector->base.name);
9809
9810         /* Don't use an invalid EDID bpc value */
9811         if (connector->base.display_info.bpc &&
9812             connector->base.display_info.bpc * 3 < bpp) {
9813                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9814                               bpp, connector->base.display_info.bpc*3);
9815                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9816         }
9817
9818         /* Clamp bpp to 8 on screens without EDID 1.4 */
9819         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9820                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9821                               bpp);
9822                 pipe_config->pipe_bpp = 24;
9823         }
9824 }
9825
9826 static int
9827 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9828                           struct drm_framebuffer *fb,
9829                           struct intel_crtc_config *pipe_config)
9830 {
9831         struct drm_device *dev = crtc->base.dev;
9832         struct intel_connector *connector;
9833         int bpp;
9834
9835         switch (fb->pixel_format) {
9836         case DRM_FORMAT_C8:
9837                 bpp = 8*3; /* since we go through a colormap */
9838                 break;
9839         case DRM_FORMAT_XRGB1555:
9840         case DRM_FORMAT_ARGB1555:
9841                 /* checked in intel_framebuffer_init already */
9842                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9843                         return -EINVAL;
9844         case DRM_FORMAT_RGB565:
9845                 bpp = 6*3; /* min is 18bpp */
9846                 break;
9847         case DRM_FORMAT_XBGR8888:
9848         case DRM_FORMAT_ABGR8888:
9849                 /* checked in intel_framebuffer_init already */
9850                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9851                         return -EINVAL;
9852         case DRM_FORMAT_XRGB8888:
9853         case DRM_FORMAT_ARGB8888:
9854                 bpp = 8*3;
9855                 break;
9856         case DRM_FORMAT_XRGB2101010:
9857         case DRM_FORMAT_ARGB2101010:
9858         case DRM_FORMAT_XBGR2101010:
9859         case DRM_FORMAT_ABGR2101010:
9860                 /* checked in intel_framebuffer_init already */
9861                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9862                         return -EINVAL;
9863                 bpp = 10*3;
9864                 break;
9865         /* TODO: gen4+ supports 16 bpc floating point, too. */
9866         default:
9867                 DRM_DEBUG_KMS("unsupported depth\n");
9868                 return -EINVAL;
9869         }
9870
9871         pipe_config->pipe_bpp = bpp;
9872
9873         /* Clamp display bpp to EDID value */
9874         list_for_each_entry(connector, &dev->mode_config.connector_list,
9875                             base.head) {
9876                 if (!connector->new_encoder ||
9877                     connector->new_encoder->new_crtc != crtc)
9878                         continue;
9879
9880                 connected_sink_compute_bpp(connector, pipe_config);
9881         }
9882
9883         return bpp;
9884 }
9885
9886 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9887 {
9888         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9889                         "type: 0x%x flags: 0x%x\n",
9890                 mode->crtc_clock,
9891                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9892                 mode->crtc_hsync_end, mode->crtc_htotal,
9893                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9894                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9895 }
9896
9897 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9898                                    struct intel_crtc_config *pipe_config,
9899                                    const char *context)
9900 {
9901         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9902                       context, pipe_name(crtc->pipe));
9903
9904         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9905         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9906                       pipe_config->pipe_bpp, pipe_config->dither);
9907         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9908                       pipe_config->has_pch_encoder,
9909                       pipe_config->fdi_lanes,
9910                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9911                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9912                       pipe_config->fdi_m_n.tu);
9913         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9914                       pipe_config->has_dp_encoder,
9915                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9916                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9917                       pipe_config->dp_m_n.tu);
9918         DRM_DEBUG_KMS("requested mode:\n");
9919         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9920         DRM_DEBUG_KMS("adjusted mode:\n");
9921         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9922         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9923         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9924         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9925                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9926         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9927                       pipe_config->gmch_pfit.control,
9928                       pipe_config->gmch_pfit.pgm_ratios,
9929                       pipe_config->gmch_pfit.lvds_border_bits);
9930         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9931                       pipe_config->pch_pfit.pos,
9932                       pipe_config->pch_pfit.size,
9933                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9934         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9935         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9936 }
9937
9938 static bool encoders_cloneable(const struct intel_encoder *a,
9939                                const struct intel_encoder *b)
9940 {
9941         /* masks could be asymmetric, so check both ways */
9942         return a == b || (a->cloneable & (1 << b->type) &&
9943                           b->cloneable & (1 << a->type));
9944 }
9945
9946 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9947                                          struct intel_encoder *encoder)
9948 {
9949         struct drm_device *dev = crtc->base.dev;
9950         struct intel_encoder *source_encoder;
9951
9952         list_for_each_entry(source_encoder,
9953                             &dev->mode_config.encoder_list, base.head) {
9954                 if (source_encoder->new_crtc != crtc)
9955                         continue;
9956
9957                 if (!encoders_cloneable(encoder, source_encoder))
9958                         return false;
9959         }
9960
9961         return true;
9962 }
9963
9964 static bool check_encoder_cloning(struct intel_crtc *crtc)
9965 {
9966         struct drm_device *dev = crtc->base.dev;
9967         struct intel_encoder *encoder;
9968
9969         list_for_each_entry(encoder,
9970                             &dev->mode_config.encoder_list, base.head) {
9971                 if (encoder->new_crtc != crtc)
9972                         continue;
9973
9974                 if (!check_single_encoder_cloning(crtc, encoder))
9975                         return false;
9976         }
9977
9978         return true;
9979 }
9980
9981 static struct intel_crtc_config *
9982 intel_modeset_pipe_config(struct drm_crtc *crtc,
9983                           struct drm_framebuffer *fb,
9984                           struct drm_display_mode *mode)
9985 {
9986         struct drm_device *dev = crtc->dev;
9987         struct intel_encoder *encoder;
9988         struct intel_crtc_config *pipe_config;
9989         int plane_bpp, ret = -EINVAL;
9990         bool retry = true;
9991
9992         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9993                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9994                 return ERR_PTR(-EINVAL);
9995         }
9996
9997         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9998         if (!pipe_config)
9999                 return ERR_PTR(-ENOMEM);
10000
10001         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10002         drm_mode_copy(&pipe_config->requested_mode, mode);
10003
10004         pipe_config->cpu_transcoder =
10005                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10006         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10007
10008         /*
10009          * Sanitize sync polarity flags based on requested ones. If neither
10010          * positive or negative polarity is requested, treat this as meaning
10011          * negative polarity.
10012          */
10013         if (!(pipe_config->adjusted_mode.flags &
10014               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10015                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10016
10017         if (!(pipe_config->adjusted_mode.flags &
10018               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10019                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10020
10021         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10022          * plane pixel format and any sink constraints into account. Returns the
10023          * source plane bpp so that dithering can be selected on mismatches
10024          * after encoders and crtc also have had their say. */
10025         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10026                                               fb, pipe_config);
10027         if (plane_bpp < 0)
10028                 goto fail;
10029
10030         /*
10031          * Determine the real pipe dimensions. Note that stereo modes can
10032          * increase the actual pipe size due to the frame doubling and
10033          * insertion of additional space for blanks between the frame. This
10034          * is stored in the crtc timings. We use the requested mode to do this
10035          * computation to clearly distinguish it from the adjusted mode, which
10036          * can be changed by the connectors in the below retry loop.
10037          */
10038         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10039         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10040         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10041
10042 encoder_retry:
10043         /* Ensure the port clock defaults are reset when retrying. */
10044         pipe_config->port_clock = 0;
10045         pipe_config->pixel_multiplier = 1;
10046
10047         /* Fill in default crtc timings, allow encoders to overwrite them. */
10048         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10049
10050         /* Pass our mode to the connectors and the CRTC to give them a chance to
10051          * adjust it according to limitations or connector properties, and also
10052          * a chance to reject the mode entirely.
10053          */
10054         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10055                             base.head) {
10056
10057                 if (&encoder->new_crtc->base != crtc)
10058                         continue;
10059
10060                 if (!(encoder->compute_config(encoder, pipe_config))) {
10061                         DRM_DEBUG_KMS("Encoder config failure\n");
10062                         goto fail;
10063                 }
10064         }
10065
10066         /* Set default port clock if not overwritten by the encoder. Needs to be
10067          * done afterwards in case the encoder adjusts the mode. */
10068         if (!pipe_config->port_clock)
10069                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10070                         * pipe_config->pixel_multiplier;
10071
10072         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10073         if (ret < 0) {
10074                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10075                 goto fail;
10076         }
10077
10078         if (ret == RETRY) {
10079                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10080                         ret = -EINVAL;
10081                         goto fail;
10082                 }
10083
10084                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10085                 retry = false;
10086                 goto encoder_retry;
10087         }
10088
10089         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10090         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10091                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10092
10093         return pipe_config;
10094 fail:
10095         kfree(pipe_config);
10096         return ERR_PTR(ret);
10097 }
10098
10099 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10100  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10101 static void
10102 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10103                              unsigned *prepare_pipes, unsigned *disable_pipes)
10104 {
10105         struct intel_crtc *intel_crtc;
10106         struct drm_device *dev = crtc->dev;
10107         struct intel_encoder *encoder;
10108         struct intel_connector *connector;
10109         struct drm_crtc *tmp_crtc;
10110
10111         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10112
10113         /* Check which crtcs have changed outputs connected to them, these need
10114          * to be part of the prepare_pipes mask. We don't (yet) support global
10115          * modeset across multiple crtcs, so modeset_pipes will only have one
10116          * bit set at most. */
10117         list_for_each_entry(connector, &dev->mode_config.connector_list,
10118                             base.head) {
10119                 if (connector->base.encoder == &connector->new_encoder->base)
10120                         continue;
10121
10122                 if (connector->base.encoder) {
10123                         tmp_crtc = connector->base.encoder->crtc;
10124
10125                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10126                 }
10127
10128                 if (connector->new_encoder)
10129                         *prepare_pipes |=
10130                                 1 << connector->new_encoder->new_crtc->pipe;
10131         }
10132
10133         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10134                             base.head) {
10135                 if (encoder->base.crtc == &encoder->new_crtc->base)
10136                         continue;
10137
10138                 if (encoder->base.crtc) {
10139                         tmp_crtc = encoder->base.crtc;
10140
10141                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10142                 }
10143
10144                 if (encoder->new_crtc)
10145                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10146         }
10147
10148         /* Check for pipes that will be enabled/disabled ... */
10149         for_each_intel_crtc(dev, intel_crtc) {
10150                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10151                         continue;
10152
10153                 if (!intel_crtc->new_enabled)
10154                         *disable_pipes |= 1 << intel_crtc->pipe;
10155                 else
10156                         *prepare_pipes |= 1 << intel_crtc->pipe;
10157         }
10158
10159
10160         /* set_mode is also used to update properties on life display pipes. */
10161         intel_crtc = to_intel_crtc(crtc);
10162         if (intel_crtc->new_enabled)
10163                 *prepare_pipes |= 1 << intel_crtc->pipe;
10164
10165         /*
10166          * For simplicity do a full modeset on any pipe where the output routing
10167          * changed. We could be more clever, but that would require us to be
10168          * more careful with calling the relevant encoder->mode_set functions.
10169          */
10170         if (*prepare_pipes)
10171                 *modeset_pipes = *prepare_pipes;
10172
10173         /* ... and mask these out. */
10174         *modeset_pipes &= ~(*disable_pipes);
10175         *prepare_pipes &= ~(*disable_pipes);
10176
10177         /*
10178          * HACK: We don't (yet) fully support global modesets. intel_set_config
10179          * obies this rule, but the modeset restore mode of
10180          * intel_modeset_setup_hw_state does not.
10181          */
10182         *modeset_pipes &= 1 << intel_crtc->pipe;
10183         *prepare_pipes &= 1 << intel_crtc->pipe;
10184
10185         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10186                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10187 }
10188
10189 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10190 {
10191         struct drm_encoder *encoder;
10192         struct drm_device *dev = crtc->dev;
10193
10194         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10195                 if (encoder->crtc == crtc)
10196                         return true;
10197
10198         return false;
10199 }
10200
10201 static void
10202 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10203 {
10204         struct intel_encoder *intel_encoder;
10205         struct intel_crtc *intel_crtc;
10206         struct drm_connector *connector;
10207
10208         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10209                             base.head) {
10210                 if (!intel_encoder->base.crtc)
10211                         continue;
10212
10213                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10214
10215                 if (prepare_pipes & (1 << intel_crtc->pipe))
10216                         intel_encoder->connectors_active = false;
10217         }
10218
10219         intel_modeset_commit_output_state(dev);
10220
10221         /* Double check state. */
10222         for_each_intel_crtc(dev, intel_crtc) {
10223                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10224                 WARN_ON(intel_crtc->new_config &&
10225                         intel_crtc->new_config != &intel_crtc->config);
10226                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10227         }
10228
10229         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10230                 if (!connector->encoder || !connector->encoder->crtc)
10231                         continue;
10232
10233                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10234
10235                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10236                         struct drm_property *dpms_property =
10237                                 dev->mode_config.dpms_property;
10238
10239                         connector->dpms = DRM_MODE_DPMS_ON;
10240                         drm_object_property_set_value(&connector->base,
10241                                                          dpms_property,
10242                                                          DRM_MODE_DPMS_ON);
10243
10244                         intel_encoder = to_intel_encoder(connector->encoder);
10245                         intel_encoder->connectors_active = true;
10246                 }
10247         }
10248
10249 }
10250
10251 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10252 {
10253         int diff;
10254
10255         if (clock1 == clock2)
10256                 return true;
10257
10258         if (!clock1 || !clock2)
10259                 return false;
10260
10261         diff = abs(clock1 - clock2);
10262
10263         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10264                 return true;
10265
10266         return false;
10267 }
10268
10269 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10270         list_for_each_entry((intel_crtc), \
10271                             &(dev)->mode_config.crtc_list, \
10272                             base.head) \
10273                 if (mask & (1 <<(intel_crtc)->pipe))
10274
10275 static bool
10276 intel_pipe_config_compare(struct drm_device *dev,
10277                           struct intel_crtc_config *current_config,
10278                           struct intel_crtc_config *pipe_config)
10279 {
10280 #define PIPE_CONF_CHECK_X(name) \
10281         if (current_config->name != pipe_config->name) { \
10282                 DRM_ERROR("mismatch in " #name " " \
10283                           "(expected 0x%08x, found 0x%08x)\n", \
10284                           current_config->name, \
10285                           pipe_config->name); \
10286                 return false; \
10287         }
10288
10289 #define PIPE_CONF_CHECK_I(name) \
10290         if (current_config->name != pipe_config->name) { \
10291                 DRM_ERROR("mismatch in " #name " " \
10292                           "(expected %i, found %i)\n", \
10293                           current_config->name, \
10294                           pipe_config->name); \
10295                 return false; \
10296         }
10297
10298 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10299         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10300                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10301                           "(expected %i, found %i)\n", \
10302                           current_config->name & (mask), \
10303                           pipe_config->name & (mask)); \
10304                 return false; \
10305         }
10306
10307 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10308         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10309                 DRM_ERROR("mismatch in " #name " " \
10310                           "(expected %i, found %i)\n", \
10311                           current_config->name, \
10312                           pipe_config->name); \
10313                 return false; \
10314         }
10315
10316 #define PIPE_CONF_QUIRK(quirk)  \
10317         ((current_config->quirks | pipe_config->quirks) & (quirk))
10318
10319         PIPE_CONF_CHECK_I(cpu_transcoder);
10320
10321         PIPE_CONF_CHECK_I(has_pch_encoder);
10322         PIPE_CONF_CHECK_I(fdi_lanes);
10323         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10324         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10325         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10326         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10327         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10328
10329         PIPE_CONF_CHECK_I(has_dp_encoder);
10330         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10331         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10332         PIPE_CONF_CHECK_I(dp_m_n.link_m);
10333         PIPE_CONF_CHECK_I(dp_m_n.link_n);
10334         PIPE_CONF_CHECK_I(dp_m_n.tu);
10335
10336         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10337         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10338         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10339         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10340         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10341         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10342
10343         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10344         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10345         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10346         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10347         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10348         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10349
10350         PIPE_CONF_CHECK_I(pixel_multiplier);
10351         PIPE_CONF_CHECK_I(has_hdmi_sink);
10352         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10353             IS_VALLEYVIEW(dev))
10354                 PIPE_CONF_CHECK_I(limited_color_range);
10355
10356         PIPE_CONF_CHECK_I(has_audio);
10357
10358         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10359                               DRM_MODE_FLAG_INTERLACE);
10360
10361         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10362                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10363                                       DRM_MODE_FLAG_PHSYNC);
10364                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10365                                       DRM_MODE_FLAG_NHSYNC);
10366                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10367                                       DRM_MODE_FLAG_PVSYNC);
10368                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10369                                       DRM_MODE_FLAG_NVSYNC);
10370         }
10371
10372         PIPE_CONF_CHECK_I(pipe_src_w);
10373         PIPE_CONF_CHECK_I(pipe_src_h);
10374
10375         /*
10376          * FIXME: BIOS likes to set up a cloned config with lvds+external
10377          * screen. Since we don't yet re-compute the pipe config when moving
10378          * just the lvds port away to another pipe the sw tracking won't match.
10379          *
10380          * Proper atomic modesets with recomputed global state will fix this.
10381          * Until then just don't check gmch state for inherited modes.
10382          */
10383         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10384                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10385                 /* pfit ratios are autocomputed by the hw on gen4+ */
10386                 if (INTEL_INFO(dev)->gen < 4)
10387                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10388                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10389         }
10390
10391         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10392         if (current_config->pch_pfit.enabled) {
10393                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10394                 PIPE_CONF_CHECK_I(pch_pfit.size);
10395         }
10396
10397         /* BDW+ don't expose a synchronous way to read the state */
10398         if (IS_HASWELL(dev))
10399                 PIPE_CONF_CHECK_I(ips_enabled);
10400
10401         PIPE_CONF_CHECK_I(double_wide);
10402
10403         PIPE_CONF_CHECK_I(shared_dpll);
10404         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10405         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10406         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10407         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10408
10409         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10410                 PIPE_CONF_CHECK_I(pipe_bpp);
10411
10412         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10413         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10414
10415 #undef PIPE_CONF_CHECK_X
10416 #undef PIPE_CONF_CHECK_I
10417 #undef PIPE_CONF_CHECK_FLAGS
10418 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10419 #undef PIPE_CONF_QUIRK
10420
10421         return true;
10422 }
10423
10424 static void
10425 check_connector_state(struct drm_device *dev)
10426 {
10427         struct intel_connector *connector;
10428
10429         list_for_each_entry(connector, &dev->mode_config.connector_list,
10430                             base.head) {
10431                 /* This also checks the encoder/connector hw state with the
10432                  * ->get_hw_state callbacks. */
10433                 intel_connector_check_state(connector);
10434
10435                 WARN(&connector->new_encoder->base != connector->base.encoder,
10436                      "connector's staged encoder doesn't match current encoder\n");
10437         }
10438 }
10439
10440 static void
10441 check_encoder_state(struct drm_device *dev)
10442 {
10443         struct intel_encoder *encoder;
10444         struct intel_connector *connector;
10445
10446         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10447                             base.head) {
10448                 bool enabled = false;
10449                 bool active = false;
10450                 enum pipe pipe, tracked_pipe;
10451
10452                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10453                               encoder->base.base.id,
10454                               encoder->base.name);
10455
10456                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10457                      "encoder's stage crtc doesn't match current crtc\n");
10458                 WARN(encoder->connectors_active && !encoder->base.crtc,
10459                      "encoder's active_connectors set, but no crtc\n");
10460
10461                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10462                                     base.head) {
10463                         if (connector->base.encoder != &encoder->base)
10464                                 continue;
10465                         enabled = true;
10466                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10467                                 active = true;
10468                 }
10469                 WARN(!!encoder->base.crtc != enabled,
10470                      "encoder's enabled state mismatch "
10471                      "(expected %i, found %i)\n",
10472                      !!encoder->base.crtc, enabled);
10473                 WARN(active && !encoder->base.crtc,
10474                      "active encoder with no crtc\n");
10475
10476                 WARN(encoder->connectors_active != active,
10477                      "encoder's computed active state doesn't match tracked active state "
10478                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10479
10480                 active = encoder->get_hw_state(encoder, &pipe);
10481                 WARN(active != encoder->connectors_active,
10482                      "encoder's hw state doesn't match sw tracking "
10483                      "(expected %i, found %i)\n",
10484                      encoder->connectors_active, active);
10485
10486                 if (!encoder->base.crtc)
10487                         continue;
10488
10489                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10490                 WARN(active && pipe != tracked_pipe,
10491                      "active encoder's pipe doesn't match"
10492                      "(expected %i, found %i)\n",
10493                      tracked_pipe, pipe);
10494
10495         }
10496 }
10497
10498 static void
10499 check_crtc_state(struct drm_device *dev)
10500 {
10501         struct drm_i915_private *dev_priv = dev->dev_private;
10502         struct intel_crtc *crtc;
10503         struct intel_encoder *encoder;
10504         struct intel_crtc_config pipe_config;
10505
10506         for_each_intel_crtc(dev, crtc) {
10507                 bool enabled = false;
10508                 bool active = false;
10509
10510                 memset(&pipe_config, 0, sizeof(pipe_config));
10511
10512                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10513                               crtc->base.base.id);
10514
10515                 WARN(crtc->active && !crtc->base.enabled,
10516                      "active crtc, but not enabled in sw tracking\n");
10517
10518                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10519                                     base.head) {
10520                         if (encoder->base.crtc != &crtc->base)
10521                                 continue;
10522                         enabled = true;
10523                         if (encoder->connectors_active)
10524                                 active = true;
10525                 }
10526
10527                 WARN(active != crtc->active,
10528                      "crtc's computed active state doesn't match tracked active state "
10529                      "(expected %i, found %i)\n", active, crtc->active);
10530                 WARN(enabled != crtc->base.enabled,
10531                      "crtc's computed enabled state doesn't match tracked enabled state "
10532                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10533
10534                 active = dev_priv->display.get_pipe_config(crtc,
10535                                                            &pipe_config);
10536
10537                 /* hw state is inconsistent with the pipe A quirk */
10538                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10539                         active = crtc->active;
10540
10541                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10542                                     base.head) {
10543                         enum pipe pipe;
10544                         if (encoder->base.crtc != &crtc->base)
10545                                 continue;
10546                         if (encoder->get_hw_state(encoder, &pipe))
10547                                 encoder->get_config(encoder, &pipe_config);
10548                 }
10549
10550                 WARN(crtc->active != active,
10551                      "crtc active state doesn't match with hw state "
10552                      "(expected %i, found %i)\n", crtc->active, active);
10553
10554                 if (active &&
10555                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10556                         WARN(1, "pipe state doesn't match!\n");
10557                         intel_dump_pipe_config(crtc, &pipe_config,
10558                                                "[hw state]");
10559                         intel_dump_pipe_config(crtc, &crtc->config,
10560                                                "[sw state]");
10561                 }
10562         }
10563 }
10564
10565 static void
10566 check_shared_dpll_state(struct drm_device *dev)
10567 {
10568         struct drm_i915_private *dev_priv = dev->dev_private;
10569         struct intel_crtc *crtc;
10570         struct intel_dpll_hw_state dpll_hw_state;
10571         int i;
10572
10573         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10574                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10575                 int enabled_crtcs = 0, active_crtcs = 0;
10576                 bool active;
10577
10578                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10579
10580                 DRM_DEBUG_KMS("%s\n", pll->name);
10581
10582                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10583
10584                 WARN(pll->active > pll->refcount,
10585                      "more active pll users than references: %i vs %i\n",
10586                      pll->active, pll->refcount);
10587                 WARN(pll->active && !pll->on,
10588                      "pll in active use but not on in sw tracking\n");
10589                 WARN(pll->on && !pll->active,
10590                      "pll in on but not on in use in sw tracking\n");
10591                 WARN(pll->on != active,
10592                      "pll on state mismatch (expected %i, found %i)\n",
10593                      pll->on, active);
10594
10595                 for_each_intel_crtc(dev, crtc) {
10596                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10597                                 enabled_crtcs++;
10598                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10599                                 active_crtcs++;
10600                 }
10601                 WARN(pll->active != active_crtcs,
10602                      "pll active crtcs mismatch (expected %i, found %i)\n",
10603                      pll->active, active_crtcs);
10604                 WARN(pll->refcount != enabled_crtcs,
10605                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10606                      pll->refcount, enabled_crtcs);
10607
10608                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10609                                        sizeof(dpll_hw_state)),
10610                      "pll hw state mismatch\n");
10611         }
10612 }
10613
10614 void
10615 intel_modeset_check_state(struct drm_device *dev)
10616 {
10617         check_connector_state(dev);
10618         check_encoder_state(dev);
10619         check_crtc_state(dev);
10620         check_shared_dpll_state(dev);
10621 }
10622
10623 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10624                                      int dotclock)
10625 {
10626         /*
10627          * FDI already provided one idea for the dotclock.
10628          * Yell if the encoder disagrees.
10629          */
10630         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10631              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10632              pipe_config->adjusted_mode.crtc_clock, dotclock);
10633 }
10634
10635 static void update_scanline_offset(struct intel_crtc *crtc)
10636 {
10637         struct drm_device *dev = crtc->base.dev;
10638
10639         /*
10640          * The scanline counter increments at the leading edge of hsync.
10641          *
10642          * On most platforms it starts counting from vtotal-1 on the
10643          * first active line. That means the scanline counter value is
10644          * always one less than what we would expect. Ie. just after
10645          * start of vblank, which also occurs at start of hsync (on the
10646          * last active line), the scanline counter will read vblank_start-1.
10647          *
10648          * On gen2 the scanline counter starts counting from 1 instead
10649          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10650          * to keep the value positive), instead of adding one.
10651          *
10652          * On HSW+ the behaviour of the scanline counter depends on the output
10653          * type. For DP ports it behaves like most other platforms, but on HDMI
10654          * there's an extra 1 line difference. So we need to add two instead of
10655          * one to the value.
10656          */
10657         if (IS_GEN2(dev)) {
10658                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10659                 int vtotal;
10660
10661                 vtotal = mode->crtc_vtotal;
10662                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10663                         vtotal /= 2;
10664
10665                 crtc->scanline_offset = vtotal - 1;
10666         } else if (HAS_DDI(dev) &&
10667                    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10668                 crtc->scanline_offset = 2;
10669         } else
10670                 crtc->scanline_offset = 1;
10671 }
10672
10673 static int __intel_set_mode(struct drm_crtc *crtc,
10674                             struct drm_display_mode *mode,
10675                             int x, int y, struct drm_framebuffer *fb)
10676 {
10677         struct drm_device *dev = crtc->dev;
10678         struct drm_i915_private *dev_priv = dev->dev_private;
10679         struct drm_display_mode *saved_mode;
10680         struct intel_crtc_config *pipe_config = NULL;
10681         struct intel_crtc *intel_crtc;
10682         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10683         int ret = 0;
10684
10685         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10686         if (!saved_mode)
10687                 return -ENOMEM;
10688
10689         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10690                                      &prepare_pipes, &disable_pipes);
10691
10692         *saved_mode = crtc->mode;
10693
10694         /* Hack: Because we don't (yet) support global modeset on multiple
10695          * crtcs, we don't keep track of the new mode for more than one crtc.
10696          * Hence simply check whether any bit is set in modeset_pipes in all the
10697          * pieces of code that are not yet converted to deal with mutliple crtcs
10698          * changing their mode at the same time. */
10699         if (modeset_pipes) {
10700                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10701                 if (IS_ERR(pipe_config)) {
10702                         ret = PTR_ERR(pipe_config);
10703                         pipe_config = NULL;
10704
10705                         goto out;
10706                 }
10707                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10708                                        "[modeset]");
10709                 to_intel_crtc(crtc)->new_config = pipe_config;
10710         }
10711
10712         /*
10713          * See if the config requires any additional preparation, e.g.
10714          * to adjust global state with pipes off.  We need to do this
10715          * here so we can get the modeset_pipe updated config for the new
10716          * mode set on this crtc.  For other crtcs we need to use the
10717          * adjusted_mode bits in the crtc directly.
10718          */
10719         if (IS_VALLEYVIEW(dev)) {
10720                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10721
10722                 /* may have added more to prepare_pipes than we should */
10723                 prepare_pipes &= ~disable_pipes;
10724         }
10725
10726         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10727                 intel_crtc_disable(&intel_crtc->base);
10728
10729         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10730                 if (intel_crtc->base.enabled)
10731                         dev_priv->display.crtc_disable(&intel_crtc->base);
10732         }
10733
10734         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10735          * to set it here already despite that we pass it down the callchain.
10736          */
10737         if (modeset_pipes) {
10738                 crtc->mode = *mode;
10739                 /* mode_set/enable/disable functions rely on a correct pipe
10740                  * config. */
10741                 to_intel_crtc(crtc)->config = *pipe_config;
10742                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10743
10744                 /*
10745                  * Calculate and store various constants which
10746                  * are later needed by vblank and swap-completion
10747                  * timestamping. They are derived from true hwmode.
10748                  */
10749                 drm_calc_timestamping_constants(crtc,
10750                                                 &pipe_config->adjusted_mode);
10751         }
10752
10753         /* Only after disabling all output pipelines that will be changed can we
10754          * update the the output configuration. */
10755         intel_modeset_update_state(dev, prepare_pipes);
10756
10757         if (dev_priv->display.modeset_global_resources)
10758                 dev_priv->display.modeset_global_resources(dev);
10759
10760         /* Set up the DPLL and any encoders state that needs to adjust or depend
10761          * on the DPLL.
10762          */
10763         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10764                 struct drm_framebuffer *old_fb;
10765                 struct drm_i915_gem_object *old_obj = NULL;
10766                 struct drm_i915_gem_object *obj =
10767                         to_intel_framebuffer(fb)->obj;
10768
10769                 mutex_lock(&dev->struct_mutex);
10770                 ret = intel_pin_and_fence_fb_obj(dev,
10771                                                  obj,
10772                                                  NULL);
10773                 if (ret != 0) {
10774                         DRM_ERROR("pin & fence failed\n");
10775                         mutex_unlock(&dev->struct_mutex);
10776                         goto done;
10777                 }
10778                 old_fb = crtc->primary->fb;
10779                 if (old_fb) {
10780                         old_obj = to_intel_framebuffer(old_fb)->obj;
10781                         intel_unpin_fb_obj(old_obj);
10782                 }
10783                 i915_gem_track_fb(old_obj, obj,
10784                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10785                 mutex_unlock(&dev->struct_mutex);
10786
10787                 crtc->primary->fb = fb;
10788                 crtc->x = x;
10789                 crtc->y = y;
10790
10791                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10792                                                       x, y, fb);
10793                 if (ret)
10794                         goto done;
10795         }
10796
10797         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10798         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10799                 update_scanline_offset(intel_crtc);
10800
10801                 dev_priv->display.crtc_enable(&intel_crtc->base);
10802         }
10803
10804         /* FIXME: add subpixel order */
10805 done:
10806         if (ret && crtc->enabled)
10807                 crtc->mode = *saved_mode;
10808
10809 out:
10810         kfree(pipe_config);
10811         kfree(saved_mode);
10812         return ret;
10813 }
10814
10815 static int intel_set_mode(struct drm_crtc *crtc,
10816                           struct drm_display_mode *mode,
10817                           int x, int y, struct drm_framebuffer *fb)
10818 {
10819         int ret;
10820
10821         ret = __intel_set_mode(crtc, mode, x, y, fb);
10822
10823         if (ret == 0)
10824                 intel_modeset_check_state(crtc->dev);
10825
10826         return ret;
10827 }
10828
10829 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10830 {
10831         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10832 }
10833
10834 #undef for_each_intel_crtc_masked
10835
10836 static void intel_set_config_free(struct intel_set_config *config)
10837 {
10838         if (!config)
10839                 return;
10840
10841         kfree(config->save_connector_encoders);
10842         kfree(config->save_encoder_crtcs);
10843         kfree(config->save_crtc_enabled);
10844         kfree(config);
10845 }
10846
10847 static int intel_set_config_save_state(struct drm_device *dev,
10848                                        struct intel_set_config *config)
10849 {
10850         struct drm_crtc *crtc;
10851         struct drm_encoder *encoder;
10852         struct drm_connector *connector;
10853         int count;
10854
10855         config->save_crtc_enabled =
10856                 kcalloc(dev->mode_config.num_crtc,
10857                         sizeof(bool), GFP_KERNEL);
10858         if (!config->save_crtc_enabled)
10859                 return -ENOMEM;
10860
10861         config->save_encoder_crtcs =
10862                 kcalloc(dev->mode_config.num_encoder,
10863                         sizeof(struct drm_crtc *), GFP_KERNEL);
10864         if (!config->save_encoder_crtcs)
10865                 return -ENOMEM;
10866
10867         config->save_connector_encoders =
10868                 kcalloc(dev->mode_config.num_connector,
10869                         sizeof(struct drm_encoder *), GFP_KERNEL);
10870         if (!config->save_connector_encoders)
10871                 return -ENOMEM;
10872
10873         /* Copy data. Note that driver private data is not affected.
10874          * Should anything bad happen only the expected state is
10875          * restored, not the drivers personal bookkeeping.
10876          */
10877         count = 0;
10878         for_each_crtc(dev, crtc) {
10879                 config->save_crtc_enabled[count++] = crtc->enabled;
10880         }
10881
10882         count = 0;
10883         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10884                 config->save_encoder_crtcs[count++] = encoder->crtc;
10885         }
10886
10887         count = 0;
10888         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10889                 config->save_connector_encoders[count++] = connector->encoder;
10890         }
10891
10892         return 0;
10893 }
10894
10895 static void intel_set_config_restore_state(struct drm_device *dev,
10896                                            struct intel_set_config *config)
10897 {
10898         struct intel_crtc *crtc;
10899         struct intel_encoder *encoder;
10900         struct intel_connector *connector;
10901         int count;
10902
10903         count = 0;
10904         for_each_intel_crtc(dev, crtc) {
10905                 crtc->new_enabled = config->save_crtc_enabled[count++];
10906
10907                 if (crtc->new_enabled)
10908                         crtc->new_config = &crtc->config;
10909                 else
10910                         crtc->new_config = NULL;
10911         }
10912
10913         count = 0;
10914         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10915                 encoder->new_crtc =
10916                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10917         }
10918
10919         count = 0;
10920         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10921                 connector->new_encoder =
10922                         to_intel_encoder(config->save_connector_encoders[count++]);
10923         }
10924 }
10925
10926 static bool
10927 is_crtc_connector_off(struct drm_mode_set *set)
10928 {
10929         int i;
10930
10931         if (set->num_connectors == 0)
10932                 return false;
10933
10934         if (WARN_ON(set->connectors == NULL))
10935                 return false;
10936
10937         for (i = 0; i < set->num_connectors; i++)
10938                 if (set->connectors[i]->encoder &&
10939                     set->connectors[i]->encoder->crtc == set->crtc &&
10940                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10941                         return true;
10942
10943         return false;
10944 }
10945
10946 static void
10947 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10948                                       struct intel_set_config *config)
10949 {
10950
10951         /* We should be able to check here if the fb has the same properties
10952          * and then just flip_or_move it */
10953         if (is_crtc_connector_off(set)) {
10954                 config->mode_changed = true;
10955         } else if (set->crtc->primary->fb != set->fb) {
10956                 /*
10957                  * If we have no fb, we can only flip as long as the crtc is
10958                  * active, otherwise we need a full mode set.  The crtc may
10959                  * be active if we've only disabled the primary plane, or
10960                  * in fastboot situations.
10961                  */
10962                 if (set->crtc->primary->fb == NULL) {
10963                         struct intel_crtc *intel_crtc =
10964                                 to_intel_crtc(set->crtc);
10965
10966                         if (intel_crtc->active) {
10967                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10968                                 config->fb_changed = true;
10969                         } else {
10970                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10971                                 config->mode_changed = true;
10972                         }
10973                 } else if (set->fb == NULL) {
10974                         config->mode_changed = true;
10975                 } else if (set->fb->pixel_format !=
10976                            set->crtc->primary->fb->pixel_format) {
10977                         config->mode_changed = true;
10978                 } else {
10979                         config->fb_changed = true;
10980                 }
10981         }
10982
10983         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10984                 config->fb_changed = true;
10985
10986         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10987                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10988                 drm_mode_debug_printmodeline(&set->crtc->mode);
10989                 drm_mode_debug_printmodeline(set->mode);
10990                 config->mode_changed = true;
10991         }
10992
10993         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10994                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10995 }
10996
10997 static int
10998 intel_modeset_stage_output_state(struct drm_device *dev,
10999                                  struct drm_mode_set *set,
11000                                  struct intel_set_config *config)
11001 {
11002         struct intel_connector *connector;
11003         struct intel_encoder *encoder;
11004         struct intel_crtc *crtc;
11005         int ro;
11006
11007         /* The upper layers ensure that we either disable a crtc or have a list
11008          * of connectors. For paranoia, double-check this. */
11009         WARN_ON(!set->fb && (set->num_connectors != 0));
11010         WARN_ON(set->fb && (set->num_connectors == 0));
11011
11012         list_for_each_entry(connector, &dev->mode_config.connector_list,
11013                             base.head) {
11014                 /* Otherwise traverse passed in connector list and get encoders
11015                  * for them. */
11016                 for (ro = 0; ro < set->num_connectors; ro++) {
11017                         if (set->connectors[ro] == &connector->base) {
11018                                 connector->new_encoder = connector->encoder;
11019                                 break;
11020                         }
11021                 }
11022
11023                 /* If we disable the crtc, disable all its connectors. Also, if
11024                  * the connector is on the changing crtc but not on the new
11025                  * connector list, disable it. */
11026                 if ((!set->fb || ro == set->num_connectors) &&
11027                     connector->base.encoder &&
11028                     connector->base.encoder->crtc == set->crtc) {
11029                         connector->new_encoder = NULL;
11030
11031                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11032                                 connector->base.base.id,
11033                                 connector->base.name);
11034                 }
11035
11036
11037                 if (&connector->new_encoder->base != connector->base.encoder) {
11038                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11039                         config->mode_changed = true;
11040                 }
11041         }
11042         /* connector->new_encoder is now updated for all connectors. */
11043
11044         /* Update crtc of enabled connectors. */
11045         list_for_each_entry(connector, &dev->mode_config.connector_list,
11046                             base.head) {
11047                 struct drm_crtc *new_crtc;
11048
11049                 if (!connector->new_encoder)
11050                         continue;
11051
11052                 new_crtc = connector->new_encoder->base.crtc;
11053
11054                 for (ro = 0; ro < set->num_connectors; ro++) {
11055                         if (set->connectors[ro] == &connector->base)
11056                                 new_crtc = set->crtc;
11057                 }
11058
11059                 /* Make sure the new CRTC will work with the encoder */
11060                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11061                                          new_crtc)) {
11062                         return -EINVAL;
11063                 }
11064                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
11065
11066                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11067                         connector->base.base.id,
11068                         connector->base.name,
11069                         new_crtc->base.id);
11070         }
11071
11072         /* Check for any encoders that needs to be disabled. */
11073         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11074                             base.head) {
11075                 int num_connectors = 0;
11076                 list_for_each_entry(connector,
11077                                     &dev->mode_config.connector_list,
11078                                     base.head) {
11079                         if (connector->new_encoder == encoder) {
11080                                 WARN_ON(!connector->new_encoder->new_crtc);
11081                                 num_connectors++;
11082                         }
11083                 }
11084
11085                 if (num_connectors == 0)
11086                         encoder->new_crtc = NULL;
11087                 else if (num_connectors > 1)
11088                         return -EINVAL;
11089
11090                 /* Only now check for crtc changes so we don't miss encoders
11091                  * that will be disabled. */
11092                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11093                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11094                         config->mode_changed = true;
11095                 }
11096         }
11097         /* Now we've also updated encoder->new_crtc for all encoders. */
11098
11099         for_each_intel_crtc(dev, crtc) {
11100                 crtc->new_enabled = false;
11101
11102                 list_for_each_entry(encoder,
11103                                     &dev->mode_config.encoder_list,
11104                                     base.head) {
11105                         if (encoder->new_crtc == crtc) {
11106                                 crtc->new_enabled = true;
11107                                 break;
11108                         }
11109                 }
11110
11111                 if (crtc->new_enabled != crtc->base.enabled) {
11112                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11113                                       crtc->new_enabled ? "en" : "dis");
11114                         config->mode_changed = true;
11115                 }
11116
11117                 if (crtc->new_enabled)
11118                         crtc->new_config = &crtc->config;
11119                 else
11120                         crtc->new_config = NULL;
11121         }
11122
11123         return 0;
11124 }
11125
11126 static void disable_crtc_nofb(struct intel_crtc *crtc)
11127 {
11128         struct drm_device *dev = crtc->base.dev;
11129         struct intel_encoder *encoder;
11130         struct intel_connector *connector;
11131
11132         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11133                       pipe_name(crtc->pipe));
11134
11135         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11136                 if (connector->new_encoder &&
11137                     connector->new_encoder->new_crtc == crtc)
11138                         connector->new_encoder = NULL;
11139         }
11140
11141         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11142                 if (encoder->new_crtc == crtc)
11143                         encoder->new_crtc = NULL;
11144         }
11145
11146         crtc->new_enabled = false;
11147         crtc->new_config = NULL;
11148 }
11149
11150 static int intel_crtc_set_config(struct drm_mode_set *set)
11151 {
11152         struct drm_device *dev;
11153         struct drm_mode_set save_set;
11154         struct intel_set_config *config;
11155         int ret;
11156
11157         BUG_ON(!set);
11158         BUG_ON(!set->crtc);
11159         BUG_ON(!set->crtc->helper_private);
11160
11161         /* Enforce sane interface api - has been abused by the fb helper. */
11162         BUG_ON(!set->mode && set->fb);
11163         BUG_ON(set->fb && set->num_connectors == 0);
11164
11165         if (set->fb) {
11166                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11167                                 set->crtc->base.id, set->fb->base.id,
11168                                 (int)set->num_connectors, set->x, set->y);
11169         } else {
11170                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11171         }
11172
11173         dev = set->crtc->dev;
11174
11175         ret = -ENOMEM;
11176         config = kzalloc(sizeof(*config), GFP_KERNEL);
11177         if (!config)
11178                 goto out_config;
11179
11180         ret = intel_set_config_save_state(dev, config);
11181         if (ret)
11182                 goto out_config;
11183
11184         save_set.crtc = set->crtc;
11185         save_set.mode = &set->crtc->mode;
11186         save_set.x = set->crtc->x;
11187         save_set.y = set->crtc->y;
11188         save_set.fb = set->crtc->primary->fb;
11189
11190         /* Compute whether we need a full modeset, only an fb base update or no
11191          * change at all. In the future we might also check whether only the
11192          * mode changed, e.g. for LVDS where we only change the panel fitter in
11193          * such cases. */
11194         intel_set_config_compute_mode_changes(set, config);
11195
11196         ret = intel_modeset_stage_output_state(dev, set, config);
11197         if (ret)
11198                 goto fail;
11199
11200         if (config->mode_changed) {
11201                 ret = intel_set_mode(set->crtc, set->mode,
11202                                      set->x, set->y, set->fb);
11203         } else if (config->fb_changed) {
11204                 struct drm_i915_private *dev_priv = dev->dev_private;
11205                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11206
11207                 intel_crtc_wait_for_pending_flips(set->crtc);
11208
11209                 ret = intel_pipe_set_base(set->crtc,
11210                                           set->x, set->y, set->fb);
11211
11212                 /*
11213                  * We need to make sure the primary plane is re-enabled if it
11214                  * has previously been turned off.
11215                  */
11216                 if (!intel_crtc->primary_enabled && ret == 0) {
11217                         WARN_ON(!intel_crtc->active);
11218                         intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11219                                                       intel_crtc->pipe);
11220                 }
11221
11222                 /*
11223                  * In the fastboot case this may be our only check of the
11224                  * state after boot.  It would be better to only do it on
11225                  * the first update, but we don't have a nice way of doing that
11226                  * (and really, set_config isn't used much for high freq page
11227                  * flipping, so increasing its cost here shouldn't be a big
11228                  * deal).
11229                  */
11230                 if (i915.fastboot && ret == 0)
11231                         intel_modeset_check_state(set->crtc->dev);
11232         }
11233
11234         if (ret) {
11235                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11236                               set->crtc->base.id, ret);
11237 fail:
11238                 intel_set_config_restore_state(dev, config);
11239
11240                 /*
11241                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11242                  * force the pipe off to avoid oopsing in the modeset code
11243                  * due to fb==NULL. This should only happen during boot since
11244                  * we don't yet reconstruct the FB from the hardware state.
11245                  */
11246                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11247                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11248
11249                 /* Try to restore the config */
11250                 if (config->mode_changed &&
11251                     intel_set_mode(save_set.crtc, save_set.mode,
11252                                    save_set.x, save_set.y, save_set.fb))
11253                         DRM_ERROR("failed to restore config after modeset failure\n");
11254         }
11255
11256 out_config:
11257         intel_set_config_free(config);
11258         return ret;
11259 }
11260
11261 static const struct drm_crtc_funcs intel_crtc_funcs = {
11262         .gamma_set = intel_crtc_gamma_set,
11263         .set_config = intel_crtc_set_config,
11264         .destroy = intel_crtc_destroy,
11265         .page_flip = intel_crtc_page_flip,
11266 };
11267
11268 static void intel_cpu_pll_init(struct drm_device *dev)
11269 {
11270         if (HAS_DDI(dev))
11271                 intel_ddi_pll_init(dev);
11272 }
11273
11274 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11275                                       struct intel_shared_dpll *pll,
11276                                       struct intel_dpll_hw_state *hw_state)
11277 {
11278         uint32_t val;
11279
11280         val = I915_READ(PCH_DPLL(pll->id));
11281         hw_state->dpll = val;
11282         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11283         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11284
11285         return val & DPLL_VCO_ENABLE;
11286 }
11287
11288 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11289                                   struct intel_shared_dpll *pll)
11290 {
11291         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11292         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11293 }
11294
11295 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11296                                 struct intel_shared_dpll *pll)
11297 {
11298         /* PCH refclock must be enabled first */
11299         ibx_assert_pch_refclk_enabled(dev_priv);
11300
11301         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11302
11303         /* Wait for the clocks to stabilize. */
11304         POSTING_READ(PCH_DPLL(pll->id));
11305         udelay(150);
11306
11307         /* The pixel multiplier can only be updated once the
11308          * DPLL is enabled and the clocks are stable.
11309          *
11310          * So write it again.
11311          */
11312         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11313         POSTING_READ(PCH_DPLL(pll->id));
11314         udelay(200);
11315 }
11316
11317 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11318                                  struct intel_shared_dpll *pll)
11319 {
11320         struct drm_device *dev = dev_priv->dev;
11321         struct intel_crtc *crtc;
11322
11323         /* Make sure no transcoder isn't still depending on us. */
11324         for_each_intel_crtc(dev, crtc) {
11325                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11326                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11327         }
11328
11329         I915_WRITE(PCH_DPLL(pll->id), 0);
11330         POSTING_READ(PCH_DPLL(pll->id));
11331         udelay(200);
11332 }
11333
11334 static char *ibx_pch_dpll_names[] = {
11335         "PCH DPLL A",
11336         "PCH DPLL B",
11337 };
11338
11339 static void ibx_pch_dpll_init(struct drm_device *dev)
11340 {
11341         struct drm_i915_private *dev_priv = dev->dev_private;
11342         int i;
11343
11344         dev_priv->num_shared_dpll = 2;
11345
11346         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11347                 dev_priv->shared_dplls[i].id = i;
11348                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11349                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11350                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11351                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11352                 dev_priv->shared_dplls[i].get_hw_state =
11353                         ibx_pch_dpll_get_hw_state;
11354         }
11355 }
11356
11357 static void intel_shared_dpll_init(struct drm_device *dev)
11358 {
11359         struct drm_i915_private *dev_priv = dev->dev_private;
11360
11361         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11362                 ibx_pch_dpll_init(dev);
11363         else
11364                 dev_priv->num_shared_dpll = 0;
11365
11366         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11367 }
11368
11369 static int
11370 intel_primary_plane_disable(struct drm_plane *plane)
11371 {
11372         struct drm_device *dev = plane->dev;
11373         struct drm_i915_private *dev_priv = dev->dev_private;
11374         struct intel_plane *intel_plane = to_intel_plane(plane);
11375         struct intel_crtc *intel_crtc;
11376
11377         if (!plane->fb)
11378                 return 0;
11379
11380         BUG_ON(!plane->crtc);
11381
11382         intel_crtc = to_intel_crtc(plane->crtc);
11383
11384         /*
11385          * Even though we checked plane->fb above, it's still possible that
11386          * the primary plane has been implicitly disabled because the crtc
11387          * coordinates given weren't visible, or because we detected
11388          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11389          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11390          * In either case, we need to unpin the FB and let the fb pointer get
11391          * updated, but otherwise we don't need to touch the hardware.
11392          */
11393         if (!intel_crtc->primary_enabled)
11394                 goto disable_unpin;
11395
11396         intel_crtc_wait_for_pending_flips(plane->crtc);
11397         intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11398                                        intel_plane->pipe);
11399 disable_unpin:
11400         i915_gem_track_fb(to_intel_framebuffer(plane->fb)->obj, NULL,
11401                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11402         intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
11403         plane->fb = NULL;
11404
11405         return 0;
11406 }
11407
11408 static int
11409 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11410                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11411                              unsigned int crtc_w, unsigned int crtc_h,
11412                              uint32_t src_x, uint32_t src_y,
11413                              uint32_t src_w, uint32_t src_h)
11414 {
11415         struct drm_device *dev = crtc->dev;
11416         struct drm_i915_private *dev_priv = dev->dev_private;
11417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11418         struct intel_plane *intel_plane = to_intel_plane(plane);
11419         struct drm_i915_gem_object *obj, *old_obj = NULL;
11420         struct drm_rect dest = {
11421                 /* integer pixels */
11422                 .x1 = crtc_x,
11423                 .y1 = crtc_y,
11424                 .x2 = crtc_x + crtc_w,
11425                 .y2 = crtc_y + crtc_h,
11426         };
11427         struct drm_rect src = {
11428                 /* 16.16 fixed point */
11429                 .x1 = src_x,
11430                 .y1 = src_y,
11431                 .x2 = src_x + src_w,
11432                 .y2 = src_y + src_h,
11433         };
11434         const struct drm_rect clip = {
11435                 /* integer pixels */
11436                 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11437                 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11438         };
11439         bool visible;
11440         int ret;
11441
11442         ret = drm_plane_helper_check_update(plane, crtc, fb,
11443                                             &src, &dest, &clip,
11444                                             DRM_PLANE_HELPER_NO_SCALING,
11445                                             DRM_PLANE_HELPER_NO_SCALING,
11446                                             false, true, &visible);
11447
11448         if (ret)
11449                 return ret;
11450
11451         if (plane->fb)
11452                 old_obj = to_intel_framebuffer(plane->fb)->obj;
11453         obj = to_intel_framebuffer(fb)->obj;
11454
11455         /*
11456          * If the CRTC isn't enabled, we're just pinning the framebuffer,
11457          * updating the fb pointer, and returning without touching the
11458          * hardware.  This allows us to later do a drmModeSetCrtc with fb=-1 to
11459          * turn on the display with all planes setup as desired.
11460          */
11461         if (!crtc->enabled) {
11462                 /*
11463                  * If we already called setplane while the crtc was disabled,
11464                  * we may have an fb pinned; unpin it.
11465                  */
11466                 if (plane->fb)
11467                         intel_unpin_fb_obj(old_obj);
11468
11469                 i915_gem_track_fb(old_obj, obj,
11470                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11471
11472                 /* Pin and return without programming hardware */
11473                 return intel_pin_and_fence_fb_obj(dev, obj, NULL);
11474         }
11475
11476         intel_crtc_wait_for_pending_flips(crtc);
11477
11478         /*
11479          * If clipping results in a non-visible primary plane, we'll disable
11480          * the primary plane.  Note that this is a bit different than what
11481          * happens if userspace explicitly disables the plane by passing fb=0
11482          * because plane->fb still gets set and pinned.
11483          */
11484         if (!visible) {
11485                 /*
11486                  * Try to pin the new fb first so that we can bail out if we
11487                  * fail.
11488                  */
11489                 if (plane->fb != fb) {
11490                         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11491                         if (ret)
11492                                 return ret;
11493                 }
11494
11495                 i915_gem_track_fb(old_obj, obj,
11496                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11497
11498                 if (intel_crtc->primary_enabled)
11499                         intel_disable_primary_hw_plane(dev_priv,
11500                                                        intel_plane->plane,
11501                                                        intel_plane->pipe);
11502
11503
11504                 if (plane->fb != fb)
11505                         if (plane->fb)
11506                                 intel_unpin_fb_obj(old_obj);
11507
11508                 return 0;
11509         }
11510
11511         ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11512         if (ret)
11513                 return ret;
11514
11515         if (!intel_crtc->primary_enabled)
11516                 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11517                                               intel_crtc->pipe);
11518
11519         return 0;
11520 }
11521
11522 /* Common destruction function for both primary and cursor planes */
11523 static void intel_plane_destroy(struct drm_plane *plane)
11524 {
11525         struct intel_plane *intel_plane = to_intel_plane(plane);
11526         drm_plane_cleanup(plane);
11527         kfree(intel_plane);
11528 }
11529
11530 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11531         .update_plane = intel_primary_plane_setplane,
11532         .disable_plane = intel_primary_plane_disable,
11533         .destroy = intel_plane_destroy,
11534 };
11535
11536 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11537                                                     int pipe)
11538 {
11539         struct intel_plane *primary;
11540         const uint32_t *intel_primary_formats;
11541         int num_formats;
11542
11543         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11544         if (primary == NULL)
11545                 return NULL;
11546
11547         primary->can_scale = false;
11548         primary->max_downscale = 1;
11549         primary->pipe = pipe;
11550         primary->plane = pipe;
11551         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11552                 primary->plane = !pipe;
11553
11554         if (INTEL_INFO(dev)->gen <= 3) {
11555                 intel_primary_formats = intel_primary_formats_gen2;
11556                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11557         } else {
11558                 intel_primary_formats = intel_primary_formats_gen4;
11559                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11560         }
11561
11562         drm_universal_plane_init(dev, &primary->base, 0,
11563                                  &intel_primary_plane_funcs,
11564                                  intel_primary_formats, num_formats,
11565                                  DRM_PLANE_TYPE_PRIMARY);
11566         return &primary->base;
11567 }
11568
11569 static int
11570 intel_cursor_plane_disable(struct drm_plane *plane)
11571 {
11572         if (!plane->fb)
11573                 return 0;
11574
11575         BUG_ON(!plane->crtc);
11576
11577         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11578 }
11579
11580 static int
11581 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11582                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11583                           unsigned int crtc_w, unsigned int crtc_h,
11584                           uint32_t src_x, uint32_t src_y,
11585                           uint32_t src_w, uint32_t src_h)
11586 {
11587         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11588         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11589         struct drm_i915_gem_object *obj = intel_fb->obj;
11590         struct drm_rect dest = {
11591                 /* integer pixels */
11592                 .x1 = crtc_x,
11593                 .y1 = crtc_y,
11594                 .x2 = crtc_x + crtc_w,
11595                 .y2 = crtc_y + crtc_h,
11596         };
11597         struct drm_rect src = {
11598                 /* 16.16 fixed point */
11599                 .x1 = src_x,
11600                 .y1 = src_y,
11601                 .x2 = src_x + src_w,
11602                 .y2 = src_y + src_h,
11603         };
11604         const struct drm_rect clip = {
11605                 /* integer pixels */
11606                 .x2 = intel_crtc->config.pipe_src_w,
11607                 .y2 = intel_crtc->config.pipe_src_h,
11608         };
11609         bool visible;
11610         int ret;
11611
11612         ret = drm_plane_helper_check_update(plane, crtc, fb,
11613                                             &src, &dest, &clip,
11614                                             DRM_PLANE_HELPER_NO_SCALING,
11615                                             DRM_PLANE_HELPER_NO_SCALING,
11616                                             true, true, &visible);
11617         if (ret)
11618                 return ret;
11619
11620         crtc->cursor_x = crtc_x;
11621         crtc->cursor_y = crtc_y;
11622         if (fb != crtc->cursor->fb) {
11623                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11624         } else {
11625                 intel_crtc_update_cursor(crtc, visible);
11626                 return 0;
11627         }
11628 }
11629 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11630         .update_plane = intel_cursor_plane_update,
11631         .disable_plane = intel_cursor_plane_disable,
11632         .destroy = intel_plane_destroy,
11633 };
11634
11635 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11636                                                    int pipe)
11637 {
11638         struct intel_plane *cursor;
11639
11640         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11641         if (cursor == NULL)
11642                 return NULL;
11643
11644         cursor->can_scale = false;
11645         cursor->max_downscale = 1;
11646         cursor->pipe = pipe;
11647         cursor->plane = pipe;
11648
11649         drm_universal_plane_init(dev, &cursor->base, 0,
11650                                  &intel_cursor_plane_funcs,
11651                                  intel_cursor_formats,
11652                                  ARRAY_SIZE(intel_cursor_formats),
11653                                  DRM_PLANE_TYPE_CURSOR);
11654         return &cursor->base;
11655 }
11656
11657 static void intel_crtc_init(struct drm_device *dev, int pipe)
11658 {
11659         struct drm_i915_private *dev_priv = dev->dev_private;
11660         struct intel_crtc *intel_crtc;
11661         struct drm_plane *primary = NULL;
11662         struct drm_plane *cursor = NULL;
11663         int i, ret;
11664
11665         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11666         if (intel_crtc == NULL)
11667                 return;
11668
11669         primary = intel_primary_plane_create(dev, pipe);
11670         if (!primary)
11671                 goto fail;
11672
11673         cursor = intel_cursor_plane_create(dev, pipe);
11674         if (!cursor)
11675                 goto fail;
11676
11677         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11678                                         cursor, &intel_crtc_funcs);
11679         if (ret)
11680                 goto fail;
11681
11682         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11683         for (i = 0; i < 256; i++) {
11684                 intel_crtc->lut_r[i] = i;
11685                 intel_crtc->lut_g[i] = i;
11686                 intel_crtc->lut_b[i] = i;
11687         }
11688
11689         /*
11690          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11691          * is hooked to pipe B. Hence we want plane A feeding pipe B.
11692          */
11693         intel_crtc->pipe = pipe;
11694         intel_crtc->plane = pipe;
11695         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11696                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11697                 intel_crtc->plane = !pipe;
11698         }
11699
11700         intel_crtc->cursor_base = ~0;
11701         intel_crtc->cursor_cntl = ~0;
11702
11703         init_waitqueue_head(&intel_crtc->vbl_wait);
11704
11705         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11706                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11707         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11708         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11709
11710         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11711
11712         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11713         return;
11714
11715 fail:
11716         if (primary)
11717                 drm_plane_cleanup(primary);
11718         if (cursor)
11719                 drm_plane_cleanup(cursor);
11720         kfree(intel_crtc);
11721 }
11722
11723 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11724 {
11725         struct drm_encoder *encoder = connector->base.encoder;
11726         struct drm_device *dev = connector->base.dev;
11727
11728         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11729
11730         if (!encoder)
11731                 return INVALID_PIPE;
11732
11733         return to_intel_crtc(encoder->crtc)->pipe;
11734 }
11735
11736 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11737                                 struct drm_file *file)
11738 {
11739         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11740         struct drm_mode_object *drmmode_obj;
11741         struct intel_crtc *crtc;
11742
11743         if (!drm_core_check_feature(dev, DRIVER_MODESET))
11744                 return -ENODEV;
11745
11746         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11747                         DRM_MODE_OBJECT_CRTC);
11748
11749         if (!drmmode_obj) {
11750                 DRM_ERROR("no such CRTC id\n");
11751                 return -ENOENT;
11752         }
11753
11754         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11755         pipe_from_crtc_id->pipe = crtc->pipe;
11756
11757         return 0;
11758 }
11759
11760 static int intel_encoder_clones(struct intel_encoder *encoder)
11761 {
11762         struct drm_device *dev = encoder->base.dev;
11763         struct intel_encoder *source_encoder;
11764         int index_mask = 0;
11765         int entry = 0;
11766
11767         list_for_each_entry(source_encoder,
11768                             &dev->mode_config.encoder_list, base.head) {
11769                 if (encoders_cloneable(encoder, source_encoder))
11770                         index_mask |= (1 << entry);
11771
11772                 entry++;
11773         }
11774
11775         return index_mask;
11776 }
11777
11778 static bool has_edp_a(struct drm_device *dev)
11779 {
11780         struct drm_i915_private *dev_priv = dev->dev_private;
11781
11782         if (!IS_MOBILE(dev))
11783                 return false;
11784
11785         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11786                 return false;
11787
11788         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11789                 return false;
11790
11791         return true;
11792 }
11793
11794 const char *intel_output_name(int output)
11795 {
11796         static const char *names[] = {
11797                 [INTEL_OUTPUT_UNUSED] = "Unused",
11798                 [INTEL_OUTPUT_ANALOG] = "Analog",
11799                 [INTEL_OUTPUT_DVO] = "DVO",
11800                 [INTEL_OUTPUT_SDVO] = "SDVO",
11801                 [INTEL_OUTPUT_LVDS] = "LVDS",
11802                 [INTEL_OUTPUT_TVOUT] = "TV",
11803                 [INTEL_OUTPUT_HDMI] = "HDMI",
11804                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11805                 [INTEL_OUTPUT_EDP] = "eDP",
11806                 [INTEL_OUTPUT_DSI] = "DSI",
11807                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11808         };
11809
11810         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11811                 return "Invalid";
11812
11813         return names[output];
11814 }
11815
11816 static bool intel_crt_present(struct drm_device *dev)
11817 {
11818         struct drm_i915_private *dev_priv = dev->dev_private;
11819
11820         if (IS_ULT(dev))
11821                 return false;
11822
11823         if (IS_CHERRYVIEW(dev))
11824                 return false;
11825
11826         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11827                 return false;
11828
11829         return true;
11830 }
11831
11832 static void intel_setup_outputs(struct drm_device *dev)
11833 {
11834         struct drm_i915_private *dev_priv = dev->dev_private;
11835         struct intel_encoder *encoder;
11836         bool dpd_is_edp = false;
11837
11838         intel_lvds_init(dev);
11839
11840         if (intel_crt_present(dev))
11841                 intel_crt_init(dev);
11842
11843         if (HAS_DDI(dev)) {
11844                 int found;
11845
11846                 /* Haswell uses DDI functions to detect digital outputs */
11847                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11848                 /* DDI A only supports eDP */
11849                 if (found)
11850                         intel_ddi_init(dev, PORT_A);
11851
11852                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11853                  * register */
11854                 found = I915_READ(SFUSE_STRAP);
11855
11856                 if (found & SFUSE_STRAP_DDIB_DETECTED)
11857                         intel_ddi_init(dev, PORT_B);
11858                 if (found & SFUSE_STRAP_DDIC_DETECTED)
11859                         intel_ddi_init(dev, PORT_C);
11860                 if (found & SFUSE_STRAP_DDID_DETECTED)
11861                         intel_ddi_init(dev, PORT_D);
11862         } else if (HAS_PCH_SPLIT(dev)) {
11863                 int found;
11864                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11865
11866                 if (has_edp_a(dev))
11867                         intel_dp_init(dev, DP_A, PORT_A);
11868
11869                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11870                         /* PCH SDVOB multiplex with HDMIB */
11871                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
11872                         if (!found)
11873                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11874                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11875                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
11876                 }
11877
11878                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11879                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11880
11881                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11882                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11883
11884                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11885                         intel_dp_init(dev, PCH_DP_C, PORT_C);
11886
11887                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11888                         intel_dp_init(dev, PCH_DP_D, PORT_D);
11889         } else if (IS_VALLEYVIEW(dev)) {
11890                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11891                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11892                                         PORT_B);
11893                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11894                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11895                 }
11896
11897                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11898                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11899                                         PORT_C);
11900                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11901                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11902                 }
11903
11904                 if (IS_CHERRYVIEW(dev)) {
11905                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11906                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11907                                                 PORT_D);
11908                                 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11909                                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11910                         }
11911                 }
11912
11913                 intel_dsi_init(dev);
11914         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11915                 bool found = false;
11916
11917                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11918                         DRM_DEBUG_KMS("probing SDVOB\n");
11919                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11920                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11921                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11922                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11923                         }
11924
11925                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
11926                                 intel_dp_init(dev, DP_B, PORT_B);
11927                 }
11928
11929                 /* Before G4X SDVOC doesn't have its own detect register */
11930
11931                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11932                         DRM_DEBUG_KMS("probing SDVOC\n");
11933                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11934                 }
11935
11936                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11937
11938                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11939                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11940                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11941                         }
11942                         if (SUPPORTS_INTEGRATED_DP(dev))
11943                                 intel_dp_init(dev, DP_C, PORT_C);
11944                 }
11945
11946                 if (SUPPORTS_INTEGRATED_DP(dev) &&
11947                     (I915_READ(DP_D) & DP_DETECTED))
11948                         intel_dp_init(dev, DP_D, PORT_D);
11949         } else if (IS_GEN2(dev))
11950                 intel_dvo_init(dev);
11951
11952         if (SUPPORTS_TV(dev))
11953                 intel_tv_init(dev);
11954
11955         intel_edp_psr_init(dev);
11956
11957         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11958                 encoder->base.possible_crtcs = encoder->crtc_mask;
11959                 encoder->base.possible_clones =
11960                         intel_encoder_clones(encoder);
11961         }
11962
11963         intel_init_pch_refclk(dev);
11964
11965         drm_helper_move_panel_connectors_to_head(dev);
11966 }
11967
11968 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11969 {
11970         struct drm_device *dev = fb->dev;
11971         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11972
11973         drm_framebuffer_cleanup(fb);
11974         mutex_lock(&dev->struct_mutex);
11975         WARN_ON(!intel_fb->obj->framebuffer_references--);
11976         drm_gem_object_unreference(&intel_fb->obj->base);
11977         mutex_unlock(&dev->struct_mutex);
11978         kfree(intel_fb);
11979 }
11980
11981 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11982                                                 struct drm_file *file,
11983                                                 unsigned int *handle)
11984 {
11985         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11986         struct drm_i915_gem_object *obj = intel_fb->obj;
11987
11988         return drm_gem_handle_create(file, &obj->base, handle);
11989 }
11990
11991 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11992         .destroy = intel_user_framebuffer_destroy,
11993         .create_handle = intel_user_framebuffer_create_handle,
11994 };
11995
11996 static int intel_framebuffer_init(struct drm_device *dev,
11997                                   struct intel_framebuffer *intel_fb,
11998                                   struct drm_mode_fb_cmd2 *mode_cmd,
11999                                   struct drm_i915_gem_object *obj)
12000 {
12001         int aligned_height;
12002         int pitch_limit;
12003         int ret;
12004
12005         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12006
12007         if (obj->tiling_mode == I915_TILING_Y) {
12008                 DRM_DEBUG("hardware does not support tiling Y\n");
12009                 return -EINVAL;
12010         }
12011
12012         if (mode_cmd->pitches[0] & 63) {
12013                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12014                           mode_cmd->pitches[0]);
12015                 return -EINVAL;
12016         }
12017
12018         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12019                 pitch_limit = 32*1024;
12020         } else if (INTEL_INFO(dev)->gen >= 4) {
12021                 if (obj->tiling_mode)
12022                         pitch_limit = 16*1024;
12023                 else
12024                         pitch_limit = 32*1024;
12025         } else if (INTEL_INFO(dev)->gen >= 3) {
12026                 if (obj->tiling_mode)
12027                         pitch_limit = 8*1024;
12028                 else
12029                         pitch_limit = 16*1024;
12030         } else
12031                 /* XXX DSPC is limited to 4k tiled */
12032                 pitch_limit = 8*1024;
12033
12034         if (mode_cmd->pitches[0] > pitch_limit) {
12035                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12036                           obj->tiling_mode ? "tiled" : "linear",
12037                           mode_cmd->pitches[0], pitch_limit);
12038                 return -EINVAL;
12039         }
12040
12041         if (obj->tiling_mode != I915_TILING_NONE &&
12042             mode_cmd->pitches[0] != obj->stride) {
12043                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12044                           mode_cmd->pitches[0], obj->stride);
12045                 return -EINVAL;
12046         }
12047
12048         /* Reject formats not supported by any plane early. */
12049         switch (mode_cmd->pixel_format) {
12050         case DRM_FORMAT_C8:
12051         case DRM_FORMAT_RGB565:
12052         case DRM_FORMAT_XRGB8888:
12053         case DRM_FORMAT_ARGB8888:
12054                 break;
12055         case DRM_FORMAT_XRGB1555:
12056         case DRM_FORMAT_ARGB1555:
12057                 if (INTEL_INFO(dev)->gen > 3) {
12058                         DRM_DEBUG("unsupported pixel format: %s\n",
12059                                   drm_get_format_name(mode_cmd->pixel_format));
12060                         return -EINVAL;
12061                 }
12062                 break;
12063         case DRM_FORMAT_XBGR8888:
12064         case DRM_FORMAT_ABGR8888:
12065         case DRM_FORMAT_XRGB2101010:
12066         case DRM_FORMAT_ARGB2101010:
12067         case DRM_FORMAT_XBGR2101010:
12068         case DRM_FORMAT_ABGR2101010:
12069                 if (INTEL_INFO(dev)->gen < 4) {
12070                         DRM_DEBUG("unsupported pixel format: %s\n",
12071                                   drm_get_format_name(mode_cmd->pixel_format));
12072                         return -EINVAL;
12073                 }
12074                 break;
12075         case DRM_FORMAT_YUYV:
12076         case DRM_FORMAT_UYVY:
12077         case DRM_FORMAT_YVYU:
12078         case DRM_FORMAT_VYUY:
12079                 if (INTEL_INFO(dev)->gen < 5) {
12080                         DRM_DEBUG("unsupported pixel format: %s\n",
12081                                   drm_get_format_name(mode_cmd->pixel_format));
12082                         return -EINVAL;
12083                 }
12084                 break;
12085         default:
12086                 DRM_DEBUG("unsupported pixel format: %s\n",
12087                           drm_get_format_name(mode_cmd->pixel_format));
12088                 return -EINVAL;
12089         }
12090
12091         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12092         if (mode_cmd->offsets[0] != 0)
12093                 return -EINVAL;
12094
12095         aligned_height = intel_align_height(dev, mode_cmd->height,
12096                                             obj->tiling_mode);
12097         /* FIXME drm helper for size checks (especially planar formats)? */
12098         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12099                 return -EINVAL;
12100
12101         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12102         intel_fb->obj = obj;
12103         intel_fb->obj->framebuffer_references++;
12104
12105         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12106         if (ret) {
12107                 DRM_ERROR("framebuffer init failed %d\n", ret);
12108                 return ret;
12109         }
12110
12111         return 0;
12112 }
12113
12114 static struct drm_framebuffer *
12115 intel_user_framebuffer_create(struct drm_device *dev,
12116                               struct drm_file *filp,
12117                               struct drm_mode_fb_cmd2 *mode_cmd)
12118 {
12119         struct drm_i915_gem_object *obj;
12120
12121         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12122                                                 mode_cmd->handles[0]));
12123         if (&obj->base == NULL)
12124                 return ERR_PTR(-ENOENT);
12125
12126         return intel_framebuffer_create(dev, mode_cmd, obj);
12127 }
12128
12129 #ifndef CONFIG_DRM_I915_FBDEV
12130 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12131 {
12132 }
12133 #endif
12134
12135 static const struct drm_mode_config_funcs intel_mode_funcs = {
12136         .fb_create = intel_user_framebuffer_create,
12137         .output_poll_changed = intel_fbdev_output_poll_changed,
12138 };
12139
12140 /* Set up chip specific display functions */
12141 static void intel_init_display(struct drm_device *dev)
12142 {
12143         struct drm_i915_private *dev_priv = dev->dev_private;
12144
12145         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12146                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12147         else if (IS_CHERRYVIEW(dev))
12148                 dev_priv->display.find_dpll = chv_find_best_dpll;
12149         else if (IS_VALLEYVIEW(dev))
12150                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12151         else if (IS_PINEVIEW(dev))
12152                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12153         else
12154                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12155
12156         if (HAS_DDI(dev)) {
12157                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12158                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12159                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12160                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12161                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12162                 dev_priv->display.off = haswell_crtc_off;
12163                 dev_priv->display.update_primary_plane =
12164                         ironlake_update_primary_plane;
12165         } else if (HAS_PCH_SPLIT(dev)) {
12166                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12167                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12168                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12169                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12170                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12171                 dev_priv->display.off = ironlake_crtc_off;
12172                 dev_priv->display.update_primary_plane =
12173                         ironlake_update_primary_plane;
12174         } else if (IS_VALLEYVIEW(dev)) {
12175                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12176                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12177                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12178                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12179                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12180                 dev_priv->display.off = i9xx_crtc_off;
12181                 dev_priv->display.update_primary_plane =
12182                         i9xx_update_primary_plane;
12183         } else {
12184                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12185                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12186                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12187                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12188                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12189                 dev_priv->display.off = i9xx_crtc_off;
12190                 dev_priv->display.update_primary_plane =
12191                         i9xx_update_primary_plane;
12192         }
12193
12194         /* Returns the core display clock speed */
12195         if (IS_VALLEYVIEW(dev))
12196                 dev_priv->display.get_display_clock_speed =
12197                         valleyview_get_display_clock_speed;
12198         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12199                 dev_priv->display.get_display_clock_speed =
12200                         i945_get_display_clock_speed;
12201         else if (IS_I915G(dev))
12202                 dev_priv->display.get_display_clock_speed =
12203                         i915_get_display_clock_speed;
12204         else if (IS_I945GM(dev) || IS_845G(dev))
12205                 dev_priv->display.get_display_clock_speed =
12206                         i9xx_misc_get_display_clock_speed;
12207         else if (IS_PINEVIEW(dev))
12208                 dev_priv->display.get_display_clock_speed =
12209                         pnv_get_display_clock_speed;
12210         else if (IS_I915GM(dev))
12211                 dev_priv->display.get_display_clock_speed =
12212                         i915gm_get_display_clock_speed;
12213         else if (IS_I865G(dev))
12214                 dev_priv->display.get_display_clock_speed =
12215                         i865_get_display_clock_speed;
12216         else if (IS_I85X(dev))
12217                 dev_priv->display.get_display_clock_speed =
12218                         i855_get_display_clock_speed;
12219         else /* 852, 830 */
12220                 dev_priv->display.get_display_clock_speed =
12221                         i830_get_display_clock_speed;
12222
12223         if (HAS_PCH_SPLIT(dev)) {
12224                 if (IS_GEN5(dev)) {
12225                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12226                         dev_priv->display.write_eld = ironlake_write_eld;
12227                 } else if (IS_GEN6(dev)) {
12228                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12229                         dev_priv->display.write_eld = ironlake_write_eld;
12230                         dev_priv->display.modeset_global_resources =
12231                                 snb_modeset_global_resources;
12232                 } else if (IS_IVYBRIDGE(dev)) {
12233                         /* FIXME: detect B0+ stepping and use auto training */
12234                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12235                         dev_priv->display.write_eld = ironlake_write_eld;
12236                         dev_priv->display.modeset_global_resources =
12237                                 ivb_modeset_global_resources;
12238                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12239                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12240                         dev_priv->display.write_eld = haswell_write_eld;
12241                         dev_priv->display.modeset_global_resources =
12242                                 haswell_modeset_global_resources;
12243                 }
12244         } else if (IS_G4X(dev)) {
12245                 dev_priv->display.write_eld = g4x_write_eld;
12246         } else if (IS_VALLEYVIEW(dev)) {
12247                 dev_priv->display.modeset_global_resources =
12248                         valleyview_modeset_global_resources;
12249                 dev_priv->display.write_eld = ironlake_write_eld;
12250         }
12251
12252         /* Default just returns -ENODEV to indicate unsupported */
12253         dev_priv->display.queue_flip = intel_default_queue_flip;
12254
12255         switch (INTEL_INFO(dev)->gen) {
12256         case 2:
12257                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12258                 break;
12259
12260         case 3:
12261                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12262                 break;
12263
12264         case 4:
12265         case 5:
12266                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12267                 break;
12268
12269         case 6:
12270                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12271                 break;
12272         case 7:
12273         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12274                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12275                 break;
12276         }
12277
12278         intel_panel_init_backlight_funcs(dev);
12279 }
12280
12281 /*
12282  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12283  * resume, or other times.  This quirk makes sure that's the case for
12284  * affected systems.
12285  */
12286 static void quirk_pipea_force(struct drm_device *dev)
12287 {
12288         struct drm_i915_private *dev_priv = dev->dev_private;
12289
12290         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12291         DRM_INFO("applying pipe a force quirk\n");
12292 }
12293
12294 /*
12295  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12296  */
12297 static void quirk_ssc_force_disable(struct drm_device *dev)
12298 {
12299         struct drm_i915_private *dev_priv = dev->dev_private;
12300         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12301         DRM_INFO("applying lvds SSC disable quirk\n");
12302 }
12303
12304 /*
12305  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12306  * brightness value
12307  */
12308 static void quirk_invert_brightness(struct drm_device *dev)
12309 {
12310         struct drm_i915_private *dev_priv = dev->dev_private;
12311         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12312         DRM_INFO("applying inverted panel brightness quirk\n");
12313 }
12314
12315 struct intel_quirk {
12316         int device;
12317         int subsystem_vendor;
12318         int subsystem_device;
12319         void (*hook)(struct drm_device *dev);
12320 };
12321
12322 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12323 struct intel_dmi_quirk {
12324         void (*hook)(struct drm_device *dev);
12325         const struct dmi_system_id (*dmi_id_list)[];
12326 };
12327
12328 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12329 {
12330         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12331         return 1;
12332 }
12333
12334 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12335         {
12336                 .dmi_id_list = &(const struct dmi_system_id[]) {
12337                         {
12338                                 .callback = intel_dmi_reverse_brightness,
12339                                 .ident = "NCR Corporation",
12340                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12341                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12342                                 },
12343                         },
12344                         { }  /* terminating entry */
12345                 },
12346                 .hook = quirk_invert_brightness,
12347         },
12348 };
12349
12350 static struct intel_quirk intel_quirks[] = {
12351         /* HP Mini needs pipe A force quirk (LP: #322104) */
12352         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12353
12354         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12355         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12356
12357         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12358         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12359
12360         /* Lenovo U160 cannot use SSC on LVDS */
12361         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12362
12363         /* Sony Vaio Y cannot use SSC on LVDS */
12364         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12365
12366         /* Acer Aspire 5734Z must invert backlight brightness */
12367         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12368
12369         /* Acer/eMachines G725 */
12370         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12371
12372         /* Acer/eMachines e725 */
12373         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12374
12375         /* Acer/Packard Bell NCL20 */
12376         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12377
12378         /* Acer Aspire 4736Z */
12379         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12380
12381         /* Acer Aspire 5336 */
12382         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12383 };
12384
12385 static void intel_init_quirks(struct drm_device *dev)
12386 {
12387         struct pci_dev *d = dev->pdev;
12388         int i;
12389
12390         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12391                 struct intel_quirk *q = &intel_quirks[i];
12392
12393                 if (d->device == q->device &&
12394                     (d->subsystem_vendor == q->subsystem_vendor ||
12395                      q->subsystem_vendor == PCI_ANY_ID) &&
12396                     (d->subsystem_device == q->subsystem_device ||
12397                      q->subsystem_device == PCI_ANY_ID))
12398                         q->hook(dev);
12399         }
12400         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12401                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12402                         intel_dmi_quirks[i].hook(dev);
12403         }
12404 }
12405
12406 /* Disable the VGA plane that we never use */
12407 static void i915_disable_vga(struct drm_device *dev)
12408 {
12409         struct drm_i915_private *dev_priv = dev->dev_private;
12410         u8 sr1;
12411         u32 vga_reg = i915_vgacntrl_reg(dev);
12412
12413         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12414         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12415         outb(SR01, VGA_SR_INDEX);
12416         sr1 = inb(VGA_SR_DATA);
12417         outb(sr1 | 1<<5, VGA_SR_DATA);
12418         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12419         udelay(300);
12420
12421         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12422         POSTING_READ(vga_reg);
12423 }
12424
12425 void intel_modeset_init_hw(struct drm_device *dev)
12426 {
12427         intel_prepare_ddi(dev);
12428
12429         intel_init_clock_gating(dev);
12430
12431         intel_reset_dpio(dev);
12432
12433         intel_enable_gt_powersave(dev);
12434 }
12435
12436 void intel_modeset_suspend_hw(struct drm_device *dev)
12437 {
12438         intel_suspend_hw(dev);
12439 }
12440
12441 void intel_modeset_init(struct drm_device *dev)
12442 {
12443         struct drm_i915_private *dev_priv = dev->dev_private;
12444         int sprite, ret;
12445         enum pipe pipe;
12446         struct intel_crtc *crtc;
12447
12448         drm_mode_config_init(dev);
12449
12450         dev->mode_config.min_width = 0;
12451         dev->mode_config.min_height = 0;
12452
12453         dev->mode_config.preferred_depth = 24;
12454         dev->mode_config.prefer_shadow = 1;
12455
12456         dev->mode_config.funcs = &intel_mode_funcs;
12457
12458         intel_init_quirks(dev);
12459
12460         intel_init_pm(dev);
12461
12462         if (INTEL_INFO(dev)->num_pipes == 0)
12463                 return;
12464
12465         intel_init_display(dev);
12466
12467         if (IS_GEN2(dev)) {
12468                 dev->mode_config.max_width = 2048;
12469                 dev->mode_config.max_height = 2048;
12470         } else if (IS_GEN3(dev)) {
12471                 dev->mode_config.max_width = 4096;
12472                 dev->mode_config.max_height = 4096;
12473         } else {
12474                 dev->mode_config.max_width = 8192;
12475                 dev->mode_config.max_height = 8192;
12476         }
12477
12478         if (IS_GEN2(dev)) {
12479                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12480                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12481         } else {
12482                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12483                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12484         }
12485
12486         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12487
12488         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12489                       INTEL_INFO(dev)->num_pipes,
12490                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12491
12492         for_each_pipe(pipe) {
12493                 intel_crtc_init(dev, pipe);
12494                 for_each_sprite(pipe, sprite) {
12495                         ret = intel_plane_init(dev, pipe, sprite);
12496                         if (ret)
12497                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12498                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12499                 }
12500         }
12501
12502         intel_init_dpio(dev);
12503         intel_reset_dpio(dev);
12504
12505         intel_cpu_pll_init(dev);
12506         intel_shared_dpll_init(dev);
12507
12508         /* Just disable it once at startup */
12509         i915_disable_vga(dev);
12510         intel_setup_outputs(dev);
12511
12512         /* Just in case the BIOS is doing something questionable. */
12513         intel_disable_fbc(dev);
12514
12515         drm_modeset_lock_all(dev);
12516         intel_modeset_setup_hw_state(dev, false);
12517         drm_modeset_unlock_all(dev);
12518
12519         for_each_intel_crtc(dev, crtc) {
12520                 if (!crtc->active)
12521                         continue;
12522
12523                 /*
12524                  * Note that reserving the BIOS fb up front prevents us
12525                  * from stuffing other stolen allocations like the ring
12526                  * on top.  This prevents some ugliness at boot time, and
12527                  * can even allow for smooth boot transitions if the BIOS
12528                  * fb is large enough for the active pipe configuration.
12529                  */
12530                 if (dev_priv->display.get_plane_config) {
12531                         dev_priv->display.get_plane_config(crtc,
12532                                                            &crtc->plane_config);
12533                         /*
12534                          * If the fb is shared between multiple heads, we'll
12535                          * just get the first one.
12536                          */
12537                         intel_find_plane_obj(crtc, &crtc->plane_config);
12538                 }
12539         }
12540 }
12541
12542 static void intel_enable_pipe_a(struct drm_device *dev)
12543 {
12544         struct intel_connector *connector;
12545         struct drm_connector *crt = NULL;
12546         struct intel_load_detect_pipe load_detect_temp;
12547         struct drm_modeset_acquire_ctx ctx;
12548
12549         /* We can't just switch on the pipe A, we need to set things up with a
12550          * proper mode and output configuration. As a gross hack, enable pipe A
12551          * by enabling the load detect pipe once. */
12552         list_for_each_entry(connector,
12553                             &dev->mode_config.connector_list,
12554                             base.head) {
12555                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12556                         crt = &connector->base;
12557                         break;
12558                 }
12559         }
12560
12561         if (!crt)
12562                 return;
12563
12564         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12565                 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12566
12567
12568 }
12569
12570 static bool
12571 intel_check_plane_mapping(struct intel_crtc *crtc)
12572 {
12573         struct drm_device *dev = crtc->base.dev;
12574         struct drm_i915_private *dev_priv = dev->dev_private;
12575         u32 reg, val;
12576
12577         if (INTEL_INFO(dev)->num_pipes == 1)
12578                 return true;
12579
12580         reg = DSPCNTR(!crtc->plane);
12581         val = I915_READ(reg);
12582
12583         if ((val & DISPLAY_PLANE_ENABLE) &&
12584             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12585                 return false;
12586
12587         return true;
12588 }
12589
12590 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12591 {
12592         struct drm_device *dev = crtc->base.dev;
12593         struct drm_i915_private *dev_priv = dev->dev_private;
12594         u32 reg;
12595
12596         /* Clear any frame start delays used for debugging left by the BIOS */
12597         reg = PIPECONF(crtc->config.cpu_transcoder);
12598         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12599
12600         /* restore vblank interrupts to correct state */
12601         if (crtc->active)
12602                 drm_vblank_on(dev, crtc->pipe);
12603         else
12604                 drm_vblank_off(dev, crtc->pipe);
12605
12606         /* We need to sanitize the plane -> pipe mapping first because this will
12607          * disable the crtc (and hence change the state) if it is wrong. Note
12608          * that gen4+ has a fixed plane -> pipe mapping.  */
12609         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12610                 struct intel_connector *connector;
12611                 bool plane;
12612
12613                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12614                               crtc->base.base.id);
12615
12616                 /* Pipe has the wrong plane attached and the plane is active.
12617                  * Temporarily change the plane mapping and disable everything
12618                  * ...  */
12619                 plane = crtc->plane;
12620                 crtc->plane = !plane;
12621                 dev_priv->display.crtc_disable(&crtc->base);
12622                 crtc->plane = plane;
12623
12624                 /* ... and break all links. */
12625                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12626                                     base.head) {
12627                         if (connector->encoder->base.crtc != &crtc->base)
12628                                 continue;
12629
12630                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12631                         connector->base.encoder = NULL;
12632                 }
12633                 /* multiple connectors may have the same encoder:
12634                  *  handle them and break crtc link separately */
12635                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12636                                     base.head)
12637                         if (connector->encoder->base.crtc == &crtc->base) {
12638                                 connector->encoder->base.crtc = NULL;
12639                                 connector->encoder->connectors_active = false;
12640                         }
12641
12642                 WARN_ON(crtc->active);
12643                 crtc->base.enabled = false;
12644         }
12645
12646         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12647             crtc->pipe == PIPE_A && !crtc->active) {
12648                 /* BIOS forgot to enable pipe A, this mostly happens after
12649                  * resume. Force-enable the pipe to fix this, the update_dpms
12650                  * call below we restore the pipe to the right state, but leave
12651                  * the required bits on. */
12652                 intel_enable_pipe_a(dev);
12653         }
12654
12655         /* Adjust the state of the output pipe according to whether we
12656          * have active connectors/encoders. */
12657         intel_crtc_update_dpms(&crtc->base);
12658
12659         if (crtc->active != crtc->base.enabled) {
12660                 struct intel_encoder *encoder;
12661
12662                 /* This can happen either due to bugs in the get_hw_state
12663                  * functions or because the pipe is force-enabled due to the
12664                  * pipe A quirk. */
12665                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12666                               crtc->base.base.id,
12667                               crtc->base.enabled ? "enabled" : "disabled",
12668                               crtc->active ? "enabled" : "disabled");
12669
12670                 crtc->base.enabled = crtc->active;
12671
12672                 /* Because we only establish the connector -> encoder ->
12673                  * crtc links if something is active, this means the
12674                  * crtc is now deactivated. Break the links. connector
12675                  * -> encoder links are only establish when things are
12676                  *  actually up, hence no need to break them. */
12677                 WARN_ON(crtc->active);
12678
12679                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12680                         WARN_ON(encoder->connectors_active);
12681                         encoder->base.crtc = NULL;
12682                 }
12683         }
12684
12685         if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12686                 /*
12687                  * We start out with underrun reporting disabled to avoid races.
12688                  * For correct bookkeeping mark this on active crtcs.
12689                  *
12690                  * Also on gmch platforms we dont have any hardware bits to
12691                  * disable the underrun reporting. Which means we need to start
12692                  * out with underrun reporting disabled also on inactive pipes,
12693                  * since otherwise we'll complain about the garbage we read when
12694                  * e.g. coming up after runtime pm.
12695                  *
12696                  * No protection against concurrent access is required - at
12697                  * worst a fifo underrun happens which also sets this to false.
12698                  */
12699                 crtc->cpu_fifo_underrun_disabled = true;
12700                 crtc->pch_fifo_underrun_disabled = true;
12701
12702                 update_scanline_offset(crtc);
12703         }
12704 }
12705
12706 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12707 {
12708         struct intel_connector *connector;
12709         struct drm_device *dev = encoder->base.dev;
12710
12711         /* We need to check both for a crtc link (meaning that the
12712          * encoder is active and trying to read from a pipe) and the
12713          * pipe itself being active. */
12714         bool has_active_crtc = encoder->base.crtc &&
12715                 to_intel_crtc(encoder->base.crtc)->active;
12716
12717         if (encoder->connectors_active && !has_active_crtc) {
12718                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12719                               encoder->base.base.id,
12720                               encoder->base.name);
12721
12722                 /* Connector is active, but has no active pipe. This is
12723                  * fallout from our resume register restoring. Disable
12724                  * the encoder manually again. */
12725                 if (encoder->base.crtc) {
12726                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12727                                       encoder->base.base.id,
12728                                       encoder->base.name);
12729                         encoder->disable(encoder);
12730                 }
12731                 encoder->base.crtc = NULL;
12732                 encoder->connectors_active = false;
12733
12734                 /* Inconsistent output/port/pipe state happens presumably due to
12735                  * a bug in one of the get_hw_state functions. Or someplace else
12736                  * in our code, like the register restore mess on resume. Clamp
12737                  * things to off as a safer default. */
12738                 list_for_each_entry(connector,
12739                                     &dev->mode_config.connector_list,
12740                                     base.head) {
12741                         if (connector->encoder != encoder)
12742                                 continue;
12743                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12744                         connector->base.encoder = NULL;
12745                 }
12746         }
12747         /* Enabled encoders without active connectors will be fixed in
12748          * the crtc fixup. */
12749 }
12750
12751 void i915_redisable_vga_power_on(struct drm_device *dev)
12752 {
12753         struct drm_i915_private *dev_priv = dev->dev_private;
12754         u32 vga_reg = i915_vgacntrl_reg(dev);
12755
12756         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12757                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12758                 i915_disable_vga(dev);
12759         }
12760 }
12761
12762 void i915_redisable_vga(struct drm_device *dev)
12763 {
12764         struct drm_i915_private *dev_priv = dev->dev_private;
12765
12766         /* This function can be called both from intel_modeset_setup_hw_state or
12767          * at a very early point in our resume sequence, where the power well
12768          * structures are not yet restored. Since this function is at a very
12769          * paranoid "someone might have enabled VGA while we were not looking"
12770          * level, just check if the power well is enabled instead of trying to
12771          * follow the "don't touch the power well if we don't need it" policy
12772          * the rest of the driver uses. */
12773         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12774                 return;
12775
12776         i915_redisable_vga_power_on(dev);
12777 }
12778
12779 static bool primary_get_hw_state(struct intel_crtc *crtc)
12780 {
12781         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12782
12783         if (!crtc->active)
12784                 return false;
12785
12786         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12787 }
12788
12789 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12790 {
12791         struct drm_i915_private *dev_priv = dev->dev_private;
12792         enum pipe pipe;
12793         struct intel_crtc *crtc;
12794         struct intel_encoder *encoder;
12795         struct intel_connector *connector;
12796         int i;
12797
12798         for_each_intel_crtc(dev, crtc) {
12799                 memset(&crtc->config, 0, sizeof(crtc->config));
12800
12801                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12802
12803                 crtc->active = dev_priv->display.get_pipe_config(crtc,
12804                                                                  &crtc->config);
12805
12806                 crtc->base.enabled = crtc->active;
12807                 crtc->primary_enabled = primary_get_hw_state(crtc);
12808
12809                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12810                               crtc->base.base.id,
12811                               crtc->active ? "enabled" : "disabled");
12812         }
12813
12814         /* FIXME: Smash this into the new shared dpll infrastructure. */
12815         if (HAS_DDI(dev))
12816                 intel_ddi_setup_hw_pll_state(dev);
12817
12818         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12819                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12820
12821                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12822                 pll->active = 0;
12823                 for_each_intel_crtc(dev, crtc) {
12824                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12825                                 pll->active++;
12826                 }
12827                 pll->refcount = pll->active;
12828
12829                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12830                               pll->name, pll->refcount, pll->on);
12831         }
12832
12833         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12834                             base.head) {
12835                 pipe = 0;
12836
12837                 if (encoder->get_hw_state(encoder, &pipe)) {
12838                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12839                         encoder->base.crtc = &crtc->base;
12840                         encoder->get_config(encoder, &crtc->config);
12841                 } else {
12842                         encoder->base.crtc = NULL;
12843                 }
12844
12845                 encoder->connectors_active = false;
12846                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12847                               encoder->base.base.id,
12848                               encoder->base.name,
12849                               encoder->base.crtc ? "enabled" : "disabled",
12850                               pipe_name(pipe));
12851         }
12852
12853         list_for_each_entry(connector, &dev->mode_config.connector_list,
12854                             base.head) {
12855                 if (connector->get_hw_state(connector)) {
12856                         connector->base.dpms = DRM_MODE_DPMS_ON;
12857                         connector->encoder->connectors_active = true;
12858                         connector->base.encoder = &connector->encoder->base;
12859                 } else {
12860                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12861                         connector->base.encoder = NULL;
12862                 }
12863                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12864                               connector->base.base.id,
12865                               connector->base.name,
12866                               connector->base.encoder ? "enabled" : "disabled");
12867         }
12868 }
12869
12870 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12871  * and i915 state tracking structures. */
12872 void intel_modeset_setup_hw_state(struct drm_device *dev,
12873                                   bool force_restore)
12874 {
12875         struct drm_i915_private *dev_priv = dev->dev_private;
12876         enum pipe pipe;
12877         struct intel_crtc *crtc;
12878         struct intel_encoder *encoder;
12879         int i;
12880
12881         intel_modeset_readout_hw_state(dev);
12882
12883         /*
12884          * Now that we have the config, copy it to each CRTC struct
12885          * Note that this could go away if we move to using crtc_config
12886          * checking everywhere.
12887          */
12888         for_each_intel_crtc(dev, crtc) {
12889                 if (crtc->active && i915.fastboot) {
12890                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12891                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12892                                       crtc->base.base.id);
12893                         drm_mode_debug_printmodeline(&crtc->base.mode);
12894                 }
12895         }
12896
12897         /* HW state is read out, now we need to sanitize this mess. */
12898         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12899                             base.head) {
12900                 intel_sanitize_encoder(encoder);
12901         }
12902
12903         for_each_pipe(pipe) {
12904                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12905                 intel_sanitize_crtc(crtc);
12906                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12907         }
12908
12909         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12910                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12911
12912                 if (!pll->on || pll->active)
12913                         continue;
12914
12915                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12916
12917                 pll->disable(dev_priv, pll);
12918                 pll->on = false;
12919         }
12920
12921         if (HAS_PCH_SPLIT(dev))
12922                 ilk_wm_get_hw_state(dev);
12923
12924         if (force_restore) {
12925                 i915_redisable_vga(dev);
12926
12927                 /*
12928                  * We need to use raw interfaces for restoring state to avoid
12929                  * checking (bogus) intermediate states.
12930                  */
12931                 for_each_pipe(pipe) {
12932                         struct drm_crtc *crtc =
12933                                 dev_priv->pipe_to_crtc_mapping[pipe];
12934
12935                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12936                                          crtc->primary->fb);
12937                 }
12938         } else {
12939                 intel_modeset_update_staged_output_state(dev);
12940         }
12941
12942         intel_modeset_check_state(dev);
12943 }
12944
12945 void intel_modeset_gem_init(struct drm_device *dev)
12946 {
12947         struct drm_crtc *c;
12948         struct intel_framebuffer *fb;
12949
12950         mutex_lock(&dev->struct_mutex);
12951         intel_init_gt_powersave(dev);
12952         mutex_unlock(&dev->struct_mutex);
12953
12954         intel_modeset_init_hw(dev);
12955
12956         intel_setup_overlay(dev);
12957
12958         /*
12959          * Make sure any fbs we allocated at startup are properly
12960          * pinned & fenced.  When we do the allocation it's too early
12961          * for this.
12962          */
12963         mutex_lock(&dev->struct_mutex);
12964         for_each_crtc(dev, c) {
12965                 if (!c->primary->fb)
12966                         continue;
12967
12968                 fb = to_intel_framebuffer(c->primary->fb);
12969                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12970                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
12971                                   to_intel_crtc(c)->pipe);
12972                         drm_framebuffer_unreference(c->primary->fb);
12973                         c->primary->fb = NULL;
12974                 }
12975         }
12976         mutex_unlock(&dev->struct_mutex);
12977 }
12978
12979 void intel_connector_unregister(struct intel_connector *intel_connector)
12980 {
12981         struct drm_connector *connector = &intel_connector->base;
12982
12983         intel_panel_destroy_backlight(connector);
12984         drm_sysfs_connector_remove(connector);
12985 }
12986
12987 void intel_modeset_cleanup(struct drm_device *dev)
12988 {
12989         struct drm_i915_private *dev_priv = dev->dev_private;
12990         struct drm_connector *connector;
12991
12992         /*
12993          * Interrupts and polling as the first thing to avoid creating havoc.
12994          * Too much stuff here (turning of rps, connectors, ...) would
12995          * experience fancy races otherwise.
12996          */
12997         drm_irq_uninstall(dev);
12998         cancel_work_sync(&dev_priv->hotplug_work);
12999         /*
13000          * Due to the hpd irq storm handling the hotplug work can re-arm the
13001          * poll handlers. Hence disable polling after hpd handling is shut down.
13002          */
13003         drm_kms_helper_poll_fini(dev);
13004
13005         mutex_lock(&dev->struct_mutex);
13006
13007         intel_unregister_dsm_handler();
13008
13009         intel_disable_fbc(dev);
13010
13011         intel_disable_gt_powersave(dev);
13012
13013         ironlake_teardown_rc6(dev);
13014
13015         mutex_unlock(&dev->struct_mutex);
13016
13017         /* flush any delayed tasks or pending work */
13018         flush_scheduled_work();
13019
13020         /* destroy the backlight and sysfs files before encoders/connectors */
13021         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13022                 struct intel_connector *intel_connector;
13023
13024                 intel_connector = to_intel_connector(connector);
13025                 intel_connector->unregister(intel_connector);
13026         }
13027
13028         drm_mode_config_cleanup(dev);
13029
13030         intel_cleanup_overlay(dev);
13031
13032         mutex_lock(&dev->struct_mutex);
13033         intel_cleanup_gt_powersave(dev);
13034         mutex_unlock(&dev->struct_mutex);
13035 }
13036
13037 /*
13038  * Return which encoder is currently attached for connector.
13039  */
13040 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13041 {
13042         return &intel_attached_encoder(connector)->base;
13043 }
13044
13045 void intel_connector_attach_encoder(struct intel_connector *connector,
13046                                     struct intel_encoder *encoder)
13047 {
13048         connector->encoder = encoder;
13049         drm_mode_connector_attach_encoder(&connector->base,
13050                                           &encoder->base);
13051 }
13052
13053 /*
13054  * set vga decode state - true == enable VGA decode
13055  */
13056 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13057 {
13058         struct drm_i915_private *dev_priv = dev->dev_private;
13059         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13060         u16 gmch_ctrl;
13061
13062         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13063                 DRM_ERROR("failed to read control word\n");
13064                 return -EIO;
13065         }
13066
13067         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13068                 return 0;
13069
13070         if (state)
13071                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13072         else
13073                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13074
13075         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13076                 DRM_ERROR("failed to write control word\n");
13077                 return -EIO;
13078         }
13079
13080         return 0;
13081 }
13082
13083 struct intel_display_error_state {
13084
13085         u32 power_well_driver;
13086
13087         int num_transcoders;
13088
13089         struct intel_cursor_error_state {
13090                 u32 control;
13091                 u32 position;
13092                 u32 base;
13093                 u32 size;
13094         } cursor[I915_MAX_PIPES];
13095
13096         struct intel_pipe_error_state {
13097                 bool power_domain_on;
13098                 u32 source;
13099                 u32 stat;
13100         } pipe[I915_MAX_PIPES];
13101
13102         struct intel_plane_error_state {
13103                 u32 control;
13104                 u32 stride;
13105                 u32 size;
13106                 u32 pos;
13107                 u32 addr;
13108                 u32 surface;
13109                 u32 tile_offset;
13110         } plane[I915_MAX_PIPES];
13111
13112         struct intel_transcoder_error_state {
13113                 bool power_domain_on;
13114                 enum transcoder cpu_transcoder;
13115
13116                 u32 conf;
13117
13118                 u32 htotal;
13119                 u32 hblank;
13120                 u32 hsync;
13121                 u32 vtotal;
13122                 u32 vblank;
13123                 u32 vsync;
13124         } transcoder[4];
13125 };
13126
13127 struct intel_display_error_state *
13128 intel_display_capture_error_state(struct drm_device *dev)
13129 {
13130         struct drm_i915_private *dev_priv = dev->dev_private;
13131         struct intel_display_error_state *error;
13132         int transcoders[] = {
13133                 TRANSCODER_A,
13134                 TRANSCODER_B,
13135                 TRANSCODER_C,
13136                 TRANSCODER_EDP,
13137         };
13138         int i;
13139
13140         if (INTEL_INFO(dev)->num_pipes == 0)
13141                 return NULL;
13142
13143         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13144         if (error == NULL)
13145                 return NULL;
13146
13147         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13148                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13149
13150         for_each_pipe(i) {
13151                 error->pipe[i].power_domain_on =
13152                         intel_display_power_enabled_unlocked(dev_priv,
13153                                                            POWER_DOMAIN_PIPE(i));
13154                 if (!error->pipe[i].power_domain_on)
13155                         continue;
13156
13157                 error->cursor[i].control = I915_READ(CURCNTR(i));
13158                 error->cursor[i].position = I915_READ(CURPOS(i));
13159                 error->cursor[i].base = I915_READ(CURBASE(i));
13160
13161                 error->plane[i].control = I915_READ(DSPCNTR(i));
13162                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13163                 if (INTEL_INFO(dev)->gen <= 3) {
13164                         error->plane[i].size = I915_READ(DSPSIZE(i));
13165                         error->plane[i].pos = I915_READ(DSPPOS(i));
13166                 }
13167                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13168                         error->plane[i].addr = I915_READ(DSPADDR(i));
13169                 if (INTEL_INFO(dev)->gen >= 4) {
13170                         error->plane[i].surface = I915_READ(DSPSURF(i));
13171                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13172                 }
13173
13174                 error->pipe[i].source = I915_READ(PIPESRC(i));
13175
13176                 if (!HAS_PCH_SPLIT(dev))
13177                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13178         }
13179
13180         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13181         if (HAS_DDI(dev_priv->dev))
13182                 error->num_transcoders++; /* Account for eDP. */
13183
13184         for (i = 0; i < error->num_transcoders; i++) {
13185                 enum transcoder cpu_transcoder = transcoders[i];
13186
13187                 error->transcoder[i].power_domain_on =
13188                         intel_display_power_enabled_unlocked(dev_priv,
13189                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13190                 if (!error->transcoder[i].power_domain_on)
13191                         continue;
13192
13193                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13194
13195                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13196                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13197                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13198                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13199                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13200                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13201                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13202         }
13203
13204         return error;
13205 }
13206
13207 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13208
13209 void
13210 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13211                                 struct drm_device *dev,
13212                                 struct intel_display_error_state *error)
13213 {
13214         int i;
13215
13216         if (!error)
13217                 return;
13218
13219         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13220         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13221                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13222                            error->power_well_driver);
13223         for_each_pipe(i) {
13224                 err_printf(m, "Pipe [%d]:\n", i);
13225                 err_printf(m, "  Power: %s\n",
13226                            error->pipe[i].power_domain_on ? "on" : "off");
13227                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13228                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13229
13230                 err_printf(m, "Plane [%d]:\n", i);
13231                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13232                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13233                 if (INTEL_INFO(dev)->gen <= 3) {
13234                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13235                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13236                 }
13237                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13238                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13239                 if (INTEL_INFO(dev)->gen >= 4) {
13240                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13241                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13242                 }
13243
13244                 err_printf(m, "Cursor [%d]:\n", i);
13245                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13246                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13247                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13248         }
13249
13250         for (i = 0; i < error->num_transcoders; i++) {
13251                 err_printf(m, "CPU transcoder: %c\n",
13252                            transcoder_name(error->transcoder[i].cpu_transcoder));
13253                 err_printf(m, "  Power: %s\n",
13254                            error->transcoder[i].power_domain_on ? "on" : "off");
13255                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13256                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13257                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13258                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13259                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13260                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13261                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13262         }
13263 }