drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 /* FDI */
  80 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  81
  82 static bool
  83 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  84                     int target, int refclk, intel_clock_t *best_clock);
  85 static bool
  86 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  87                         int target, int refclk, intel_clock_t *best_clock);
  88
  89 static bool
  90 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  91                       int target, int refclk, intel_clock_t *best_clock);
  92 static bool
  93 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                            int target, int refclk, intel_clock_t *best_clock);
  95
  96 static inline u32 /* units of 100MHz */
  97 intel_fdi_link_freq(struct drm_device *dev)
  98 {
  99         if (IS_GEN5(dev)) {
 100                 struct drm_i915_private *dev_priv = dev->dev_private;
 101                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 102         } else
 103                 return 27;
 104 }
 105
 106 static const intel_limit_t intel_limits_i8xx_dvo = {
 107         .dot = { .min = 25000, .max = 350000 },
 108         .vco = { .min = 930000, .max = 1400000 },
 109         .n = { .min = 3, .max = 16 },
 110         .m = { .min = 96, .max = 140 },
 111         .m1 = { .min = 18, .max = 26 },
 112         .m2 = { .min = 6, .max = 16 },
 113         .p = { .min = 4, .max = 128 },
 114         .p1 = { .min = 2, .max = 33 },
 115         .p2 = { .dot_limit = 165000,
 116                 .p2_slow = 4, .p2_fast = 2 },
 117         .find_pll = intel_find_best_PLL,
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 930000, .max = 1400000 },
 123         .n = { .min = 3, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131         .find_pll = intel_find_best_PLL,
 132 };
 133
 134 static const intel_limit_t intel_limits_i9xx_sdvo = {
 135         .dot = { .min = 20000, .max = 400000 },
 136         .vco = { .min = 1400000, .max = 2800000 },
 137         .n = { .min = 1, .max = 6 },
 138         .m = { .min = 70, .max = 120 },
 139         .m1 = { .min = 10, .max = 22 },
 140         .m2 = { .min = 5, .max = 9 },
 141         .p = { .min = 5, .max = 80 },
 142         .p1 = { .min = 1, .max = 8 },
 143         .p2 = { .dot_limit = 200000,
 144                 .p2_slow = 10, .p2_fast = 5 },
 145         .find_pll = intel_find_best_PLL,
 146 };
 147
 148 static const intel_limit_t intel_limits_i9xx_lvds = {
 149         .dot = { .min = 20000, .max = 400000 },
 150         .vco = { .min = 1400000, .max = 2800000 },
 151         .n = { .min = 1, .max = 6 },
 152         .m = { .min = 70, .max = 120 },
 153         .m1 = { .min = 10, .max = 22 },
 154         .m2 = { .min = 5, .max = 9 },
 155         .p = { .min = 7, .max = 98 },
 156         .p1 = { .min = 1, .max = 8 },
 157         .p2 = { .dot_limit = 112000,
 158                 .p2_slow = 14, .p2_fast = 7 },
 159         .find_pll = intel_find_best_PLL,
 160 };
 161
 162
 163 static const intel_limit_t intel_limits_g4x_sdvo = {
 164         .dot = { .min = 25000, .max = 270000 },
 165         .vco = { .min = 1750000, .max = 3500000},
 166         .n = { .min = 1, .max = 4 },
 167         .m = { .min = 104, .max = 138 },
 168         .m1 = { .min = 17, .max = 23 },
 169         .m2 = { .min = 5, .max = 11 },
 170         .p = { .min = 10, .max = 30 },
 171         .p1 = { .min = 1, .max = 3},
 172         .p2 = { .dot_limit = 270000,
 173                 .p2_slow = 10,
 174                 .p2_fast = 10
 175         },
 176         .find_pll = intel_g4x_find_best_PLL,
 177 };
 178
 179 static const intel_limit_t intel_limits_g4x_hdmi = {
 180         .dot = { .min = 22000, .max = 400000 },
 181         .vco = { .min = 1750000, .max = 3500000},
 182         .n = { .min = 1, .max = 4 },
 183         .m = { .min = 104, .max = 138 },
 184         .m1 = { .min = 16, .max = 23 },
 185         .m2 = { .min = 5, .max = 11 },
 186         .p = { .min = 5, .max = 80 },
 187         .p1 = { .min = 1, .max = 8},
 188         .p2 = { .dot_limit = 165000,
 189                 .p2_slow = 10, .p2_fast = 5 },
 190         .find_pll = intel_g4x_find_best_PLL,
 191 };
 192
 193 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 194         .dot = { .min = 20000, .max = 115000 },
 195         .vco = { .min = 1750000, .max = 3500000 },
 196         .n = { .min = 1, .max = 3 },
 197         .m = { .min = 104, .max = 138 },
 198         .m1 = { .min = 17, .max = 23 },
 199         .m2 = { .min = 5, .max = 11 },
 200         .p = { .min = 28, .max = 112 },
 201         .p1 = { .min = 2, .max = 8 },
 202         .p2 = { .dot_limit = 0,
 203                 .p2_slow = 14, .p2_fast = 14
 204         },
 205         .find_pll = intel_g4x_find_best_PLL,
 206 };
 207
 208 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 209         .dot = { .min = 80000, .max = 224000 },
 210         .vco = { .min = 1750000, .max = 3500000 },
 211         .n = { .min = 1, .max = 3 },
 212         .m = { .min = 104, .max = 138 },
 213         .m1 = { .min = 17, .max = 23 },
 214         .m2 = { .min = 5, .max = 11 },
 215         .p = { .min = 14, .max = 42 },
 216         .p1 = { .min = 2, .max = 6 },
 217         .p2 = { .dot_limit = 0,
 218                 .p2_slow = 7, .p2_fast = 7
 219         },
 220         .find_pll = intel_g4x_find_best_PLL,
 221 };
 222
 223 static const intel_limit_t intel_limits_g4x_display_port = {
 224         .dot = { .min = 161670, .max = 227000 },
 225         .vco = { .min = 1750000, .max = 3500000},
 226         .n = { .min = 1, .max = 2 },
 227         .m = { .min = 97, .max = 108 },
 228         .m1 = { .min = 0x10, .max = 0x12 },
 229         .m2 = { .min = 0x05, .max = 0x06 },
 230         .p = { .min = 10, .max = 20 },
 231         .p1 = { .min = 1, .max = 2},
 232         .p2 = { .dot_limit = 0,
 233                 .p2_slow = 10, .p2_fast = 10 },
 234         .find_pll = intel_find_pll_g4x_dp,
 235 };
 236
 237 static const intel_limit_t intel_limits_pineview_sdvo = {
 238         .dot = { .min = 20000, .max = 400000},
 239         .vco = { .min = 1700000, .max = 3500000 },
 240         /* Pineview's Ncounter is a ring counter */
 241         .n = { .min = 3, .max = 6 },
 242         .m = { .min = 2, .max = 256 },
 243         /* Pineview only has one combined m divider, which we treat as m2. */
 244         .m1 = { .min = 0, .max = 0 },
 245         .m2 = { .min = 0, .max = 254 },
 246         .p = { .min = 5, .max = 80 },
 247         .p1 = { .min = 1, .max = 8 },
 248         .p2 = { .dot_limit = 200000,
 249                 .p2_slow = 10, .p2_fast = 5 },
 250         .find_pll = intel_find_best_PLL,
 251 };
 252
 253 static const intel_limit_t intel_limits_pineview_lvds = {
 254         .dot = { .min = 20000, .max = 400000 },
 255         .vco = { .min = 1700000, .max = 3500000 },
 256         .n = { .min = 3, .max = 6 },
 257         .m = { .min = 2, .max = 256 },
 258         .m1 = { .min = 0, .max = 0 },
 259         .m2 = { .min = 0, .max = 254 },
 260         .p = { .min = 7, .max = 112 },
 261         .p1 = { .min = 1, .max = 8 },
 262         .p2 = { .dot_limit = 112000,
 263                 .p2_slow = 14, .p2_fast = 14 },
 264         .find_pll = intel_find_best_PLL,
 265 };
 266
 267 /* Ironlake / Sandybridge
 268  *
 269  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 270  * the range value for them is (actual_value - 2).
 271  */
 272 static const intel_limit_t intel_limits_ironlake_dac = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 5 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283         .find_pll = intel_g4x_find_best_PLL,
 284 };
 285
 286 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 3 },
 290         .m = { .min = 79, .max = 118 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297         .find_pll = intel_g4x_find_best_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 3 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 14, .max = 56 },
 308         .p1 = { .min = 2, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 7, .p2_fast = 7 },
 311         .find_pll = intel_g4x_find_best_PLL,
 312 };
 313
 314 /* LVDS 100mhz refclk limits. */
 315 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 316         .dot = { .min = 25000, .max = 350000 },
 317         .vco = { .min = 1760000, .max = 3510000 },
 318         .n = { .min = 1, .max = 2 },
 319         .m = { .min = 79, .max = 126 },
 320         .m1 = { .min = 12, .max = 22 },
 321         .m2 = { .min = 5, .max = 9 },
 322         .p = { .min = 28, .max = 112 },
 323         .p1 = { .min = 2,.max = 8 },
 324         .p2 = { .dot_limit = 225000,
 325                 .p2_slow = 14, .p2_fast = 14 },
 326         .find_pll = intel_g4x_find_best_PLL,
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 126 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 42 },
 337         .p1 = { .min = 2,.max = 6 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340         .find_pll = intel_g4x_find_best_PLL,
 341 };
 342
 343 static const intel_limit_t intel_limits_ironlake_display_port = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000},
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 81, .max = 90 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 10, .max = 20 },
 351         .p1 = { .min = 1, .max = 2},
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 10, .p2_fast = 10 },
 354         .find_pll = intel_find_pll_ironlake_dp,
 355 };
 356
 357 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 358                                                 int refclk)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         struct drm_i915_private *dev_priv = dev->dev_private;
 362         const intel_limit_t *limit;
 363
 364         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 365                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 366                     LVDS_CLKB_POWER_UP) {
 367                         /* LVDS dual channel */
 368                         if (refclk == 100000)
 369                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 370                         else
 371                                 limit = &intel_limits_ironlake_dual_lvds;
 372                 } else {
 373                         if (refclk == 100000)
 374                                 limit = &intel_limits_ironlake_single_lvds_100m;
 375                         else
 376                                 limit = &intel_limits_ironlake_single_lvds;
 377                 }
 378         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 379                         HAS_eDP)
 380                 limit = &intel_limits_ironlake_display_port;
 381         else
 382                 limit = &intel_limits_ironlake_dac;
 383
 384         return limit;
 385 }
 386
 387 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 388 {
 389         struct drm_device *dev = crtc->dev;
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         const intel_limit_t *limit;
 392
 393         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 394                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 395                     LVDS_CLKB_POWER_UP)
 396                         /* LVDS with dual channel */
 397                         limit = &intel_limits_g4x_dual_channel_lvds;
 398                 else
 399                         /* LVDS with dual channel */
 400                         limit = &intel_limits_g4x_single_channel_lvds;
 401         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 402                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 403                 limit = &intel_limits_g4x_hdmi;
 404         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 405                 limit = &intel_limits_g4x_sdvo;
 406         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 407                 limit = &intel_limits_g4x_display_port;
 408         } else /* The option is for other outputs */
 409                 limit = &intel_limits_i9xx_sdvo;
 410
 411         return limit;
 412 }
 413
 414 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 415 {
 416         struct drm_device *dev = crtc->dev;
 417         const intel_limit_t *limit;
 418
 419         if (HAS_PCH_SPLIT(dev))
 420                 limit = intel_ironlake_limit(crtc, refclk);
 421         else if (IS_G4X(dev)) {
 422                 limit = intel_g4x_limit(crtc);
 423         } else if (IS_PINEVIEW(dev)) {
 424                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 425                         limit = &intel_limits_pineview_lvds;
 426                 else
 427                         limit = &intel_limits_pineview_sdvo;
 428         } else if (!IS_GEN2(dev)) {
 429                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 430                         limit = &intel_limits_i9xx_lvds;
 431                 else
 432                         limit = &intel_limits_i9xx_sdvo;
 433         } else {
 434                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 435                         limit = &intel_limits_i8xx_lvds;
 436                 else
 437                         limit = &intel_limits_i8xx_dvo;
 438         }
 439         return limit;
 440 }
 441
 442 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 443 static void pineview_clock(int refclk, intel_clock_t *clock)
 444 {
 445         clock->m = clock->m2 + 2;
 446         clock->p = clock->p1 * clock->p2;
 447         clock->vco = refclk * clock->m / clock->n;
 448         clock->dot = clock->vco / clock->p;
 449 }
 450
 451 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 452 {
 453         if (IS_PINEVIEW(dev)) {
 454                 pineview_clock(refclk, clock);
 455                 return;
 456         }
 457         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 458         clock->p = clock->p1 * clock->p2;
 459         clock->vco = refclk * clock->m / (clock->n + 2);
 460         clock->dot = clock->vco / clock->p;
 461 }
 462
 463 /**
 464  * Returns whether any output on the specified pipe is of the specified type
 465  */
 466 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 467 {
 468         struct drm_device *dev = crtc->dev;
 469         struct drm_mode_config *mode_config = &dev->mode_config;
 470         struct intel_encoder *encoder;
 471
 472         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 473                 if (encoder->base.crtc == crtc && encoder->type == type)
 474                         return true;
 475
 476         return false;
 477 }
 478
 479 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 480 /**
 481  * Returns whether the given set of divisors are valid for a given refclk with
 482  * the given connectors.
 483  */
 484
 485 static bool intel_PLL_is_valid(struct drm_device *dev,
 486                                const intel_limit_t *limit,
 487                                const intel_clock_t *clock)
 488 {
 489         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 490                 INTELPllInvalid ("p1 out of range\n");
 491         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 492                 INTELPllInvalid ("p out of range\n");
 493         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 494                 INTELPllInvalid ("m2 out of range\n");
 495         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 496                 INTELPllInvalid ("m1 out of range\n");
 497         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 498                 INTELPllInvalid ("m1 <= m2\n");
 499         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 500                 INTELPllInvalid ("m out of range\n");
 501         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 502                 INTELPllInvalid ("n out of range\n");
 503         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 504                 INTELPllInvalid ("vco out of range\n");
 505         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 506          * connector, etc., rather than just a single range.
 507          */
 508         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 509                 INTELPllInvalid ("dot out of range\n");
 510
 511         return true;
 512 }
 513
 514 static bool
 515 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 516                     int target, int refclk, intel_clock_t *best_clock)
 517
 518 {
 519         struct drm_device *dev = crtc->dev;
 520         struct drm_i915_private *dev_priv = dev->dev_private;
 521         intel_clock_t clock;
 522         int err = target;
 523
 524         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 525             (I915_READ(LVDS)) != 0) {
 526                 /*
 527                  * For LVDS, if the panel is on, just rely on its current
 528                  * settings for dual-channel.  We haven't figured out how to
 529                  * reliably set up different single/dual channel state, if we
 530                  * even can.
 531                  */
 532                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 533                     LVDS_CLKB_POWER_UP)
 534                         clock.p2 = limit->p2.p2_fast;
 535                 else
 536                         clock.p2 = limit->p2.p2_slow;
 537         } else {
 538                 if (target < limit->p2.dot_limit)
 539                         clock.p2 = limit->p2.p2_slow;
 540                 else
 541                         clock.p2 = limit->p2.p2_fast;
 542         }
 543
 544         memset (best_clock, 0, sizeof (*best_clock));
 545
 546         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 547              clock.m1++) {
 548                 for (clock.m2 = limit->m2.min;
 549                      clock.m2 <= limit->m2.max; clock.m2++) {
 550                         /* m1 is always 0 in Pineview */
 551                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 552                                 break;
 553                         for (clock.n = limit->n.min;
 554                              clock.n <= limit->n.max; clock.n++) {
 555                                 for (clock.p1 = limit->p1.min;
 556                                         clock.p1 <= limit->p1.max; clock.p1++) {
 557                                         int this_err;
 558
 559                                         intel_clock(dev, refclk, &clock);
 560                                         if (!intel_PLL_is_valid(dev, limit,
 561                                                                 &clock))
 562                                                 continue;
 563
 564                                         this_err = abs(clock.dot - target);
 565                                         if (this_err < err) {
 566                                                 *best_clock = clock;
 567                                                 err = this_err;
 568                                         }
 569                                 }
 570                         }
 571                 }
 572         }
 573
 574         return (err != target);
 575 }
 576
 577 static bool
 578 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 579                         int target, int refclk, intel_clock_t *best_clock)
 580 {
 581         struct drm_device *dev = crtc->dev;
 582         struct drm_i915_private *dev_priv = dev->dev_private;
 583         intel_clock_t clock;
 584         int max_n;
 585         bool found;
 586         /* approximately equals target * 0.00585 */
 587         int err_most = (target >> 8) + (target >> 9);
 588         found = false;
 589
 590         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 591                 int lvds_reg;
 592
 593                 if (HAS_PCH_SPLIT(dev))
 594                         lvds_reg = PCH_LVDS;
 595                 else
 596                         lvds_reg = LVDS;
 597                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 598                     LVDS_CLKB_POWER_UP)
 599                         clock.p2 = limit->p2.p2_fast;
 600                 else
 601                         clock.p2 = limit->p2.p2_slow;
 602         } else {
 603                 if (target < limit->p2.dot_limit)
 604                         clock.p2 = limit->p2.p2_slow;
 605                 else
 606                         clock.p2 = limit->p2.p2_fast;
 607         }
 608
 609         memset(best_clock, 0, sizeof(*best_clock));
 610         max_n = limit->n.max;
 611         /* based on hardware requirement, prefer smaller n to precision */
 612         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 613                 /* based on hardware requirement, prefere larger m1,m2 */
 614                 for (clock.m1 = limit->m1.max;
 615                      clock.m1 >= limit->m1.min; clock.m1--) {
 616                         for (clock.m2 = limit->m2.max;
 617                              clock.m2 >= limit->m2.min; clock.m2--) {
 618                                 for (clock.p1 = limit->p1.max;
 619                                      clock.p1 >= limit->p1.min; clock.p1--) {
 620                                         int this_err;
 621
 622                                         intel_clock(dev, refclk, &clock);
 623                                         if (!intel_PLL_is_valid(dev, limit,
 624                                                                 &clock))
 625                                                 continue;
 626
 627                                         this_err = abs(clock.dot - target);
 628                                         if (this_err < err_most) {
 629                                                 *best_clock = clock;
 630                                                 err_most = this_err;
 631                                                 max_n = clock.n;
 632                                                 found = true;
 633                                         }
 634                                 }
 635                         }
 636                 }
 637         }
 638         return found;
 639 }
 640
 641 static bool
 642 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 643                            int target, int refclk, intel_clock_t *best_clock)
 644 {
 645         struct drm_device *dev = crtc->dev;
 646         intel_clock_t clock;
 647
 648         if (target < 200000) {
 649                 clock.n = 1;
 650                 clock.p1 = 2;
 651                 clock.p2 = 10;
 652                 clock.m1 = 12;
 653                 clock.m2 = 9;
 654         } else {
 655                 clock.n = 2;
 656                 clock.p1 = 1;
 657                 clock.p2 = 10;
 658                 clock.m1 = 14;
 659                 clock.m2 = 8;
 660         }
 661         intel_clock(dev, refclk, &clock);
 662         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 663         return true;
 664 }
 665
 666 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 667 static bool
 668 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 669                       int target, int refclk, intel_clock_t *best_clock)
 670 {
 671         intel_clock_t clock;
 672         if (target < 200000) {
 673                 clock.p1 = 2;
 674                 clock.p2 = 10;
 675                 clock.n = 2;
 676                 clock.m1 = 23;
 677                 clock.m2 = 8;
 678         } else {
 679                 clock.p1 = 1;
 680                 clock.p2 = 10;
 681                 clock.n = 1;
 682                 clock.m1 = 14;
 683                 clock.m2 = 2;
 684         }
 685         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 686         clock.p = (clock.p1 * clock.p2);
 687         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 688         clock.vco = 0;
 689         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 690         return true;
 691 }
 692
 693 /**
 694  * intel_wait_for_vblank - wait for vblank on a given pipe
 695  * @dev: drm device
 696  * @pipe: pipe to wait for
 697  *
 698  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 699  * mode setting code.
 700  */
 701 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 702 {
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704         int pipestat_reg = PIPESTAT(pipe);
 705
 706         /* Clear existing vblank status. Note this will clear any other
 707          * sticky status fields as well.
 708          *
 709          * This races with i915_driver_irq_handler() with the result
 710          * that either function could miss a vblank event.  Here it is not
 711          * fatal, as we will either wait upon the next vblank interrupt or
 712          * timeout.  Generally speaking intel_wait_for_vblank() is only
 713          * called during modeset at which time the GPU should be idle and
 714          * should *not* be performing page flips and thus not waiting on
 715          * vblanks...
 716          * Currently, the result of us stealing a vblank from the irq
 717          * handler is that a single frame will be skipped during swapbuffers.
 718          */
 719         I915_WRITE(pipestat_reg,
 720                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 721
 722         /* Wait for vblank interrupt bit to set */
 723         if (wait_for(I915_READ(pipestat_reg) &
 724                      PIPE_VBLANK_INTERRUPT_STATUS,
 725                      50))
 726                 DRM_DEBUG_KMS("vblank wait timed out\n");
 727 }
 728
 729 /*
 730  * intel_wait_for_pipe_off - wait for pipe to turn off
 731  * @dev: drm device
 732  * @pipe: pipe to wait for
 733  *
 734  * After disabling a pipe, we can't wait for vblank in the usual way,
 735  * spinning on the vblank interrupt status bit, since we won't actually
 736  * see an interrupt when the pipe is disabled.
 737  *
 738  * On Gen4 and above:
 739  *   wait for the pipe register state bit to turn off
 740  *
 741  * Otherwise:
 742  *   wait for the display line value to settle (it usually
 743  *   ends up stopping at the start of the next frame).
 744  *
 745  */
 746 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 747 {
 748         struct drm_i915_private *dev_priv = dev->dev_private;
 749
 750         if (INTEL_INFO(dev)->gen >= 4) {
 751                 int reg = PIPECONF(pipe);
 752
 753                 /* Wait for the Pipe State to go off */
 754                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 755                              100))
 756                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 757         } else {
 758                 u32 last_line;
 759                 int reg = PIPEDSL(pipe);
 760                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 761
 762                 /* Wait for the display line to settle */
 763                 do {
 764                         last_line = I915_READ(reg) & DSL_LINEMASK;
 765                         mdelay(5);
 766                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 767                          time_after(timeout, jiffies));
 768                 if (time_after(jiffies, timeout))
 769                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 770         }
 771 }
 772
 773 static const char *state_string(bool enabled)
 774 {
 775         return enabled ? "on" : "off";
 776 }
 777
 778 /* Only for pre-ILK configs */
 779 static void assert_pll(struct drm_i915_private *dev_priv,
 780                        enum pipe pipe, bool state)
 781 {
 782         int reg;
 783         u32 val;
 784         bool cur_state;
 785
 786         reg = DPLL(pipe);
 787         val = I915_READ(reg);
 788         cur_state = !!(val & DPLL_VCO_ENABLE);
 789         WARN(cur_state != state,
 790              "PLL state assertion failure (expected %s, current %s)\n",
 791              state_string(state), state_string(cur_state));
 792 }
 793 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 794 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 795
 796 /* For ILK+ */
 797 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 798                            enum pipe pipe, bool state)
 799 {
 800         int reg;
 801         u32 val;
 802         bool cur_state;
 803
 804         reg = PCH_DPLL(pipe);
 805         val = I915_READ(reg);
 806         cur_state = !!(val & DPLL_VCO_ENABLE);
 807         WARN(cur_state != state,
 808              "PCH PLL state assertion failure (expected %s, current %s)\n",
 809              state_string(state), state_string(cur_state));
 810 }
 811 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 812 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 813
 814 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 815                           enum pipe pipe, bool state)
 816 {
 817         int reg;
 818         u32 val;
 819         bool cur_state;
 820
 821         reg = FDI_TX_CTL(pipe);
 822         val = I915_READ(reg);
 823         cur_state = !!(val & FDI_TX_ENABLE);
 824         WARN(cur_state != state,
 825              "FDI TX state assertion failure (expected %s, current %s)\n",
 826              state_string(state), state_string(cur_state));
 827 }
 828 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 829 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 830
 831 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 832                           enum pipe pipe, bool state)
 833 {
 834         int reg;
 835         u32 val;
 836         bool cur_state;
 837
 838         reg = FDI_RX_CTL(pipe);
 839         val = I915_READ(reg);
 840         cur_state = !!(val & FDI_RX_ENABLE);
 841         WARN(cur_state != state,
 842              "FDI RX state assertion failure (expected %s, current %s)\n",
 843              state_string(state), state_string(cur_state));
 844 }
 845 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 846 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 847
 848 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 849                                       enum pipe pipe)
 850 {
 851         int reg;
 852         u32 val;
 853
 854         /* ILK FDI PLL is always enabled */
 855         if (dev_priv->info->gen == 5)
 856                 return;
 857
 858         reg = FDI_TX_CTL(pipe);
 859         val = I915_READ(reg);
 860         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 861 }
 862
 863 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 864                                       enum pipe pipe)
 865 {
 866         int reg;
 867         u32 val;
 868
 869         reg = FDI_RX_CTL(pipe);
 870         val = I915_READ(reg);
 871         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 872 }
 873
 874 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 875                                   enum pipe pipe)
 876 {
 877         int pp_reg, lvds_reg;
 878         u32 val;
 879         enum pipe panel_pipe = PIPE_A;
 880         bool locked = locked;
 881
 882         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 883                 pp_reg = PCH_PP_CONTROL;
 884                 lvds_reg = PCH_LVDS;
 885         } else {
 886                 pp_reg = PP_CONTROL;
 887                 lvds_reg = LVDS;
 888         }
 889
 890         val = I915_READ(pp_reg);
 891         if (!(val & PANEL_POWER_ON) ||
 892             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 893                 locked = false;
 894
 895         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 896                 panel_pipe = PIPE_B;
 897
 898         WARN(panel_pipe == pipe && locked,
 899              "panel assertion failure, pipe %c regs locked\n",
 900              pipe_name(pipe));
 901 }
 902
 903 static void assert_pipe(struct drm_i915_private *dev_priv,
 904                         enum pipe pipe, bool state)
 905 {
 906         int reg;
 907         u32 val;
 908         bool cur_state;
 909
 910         reg = PIPECONF(pipe);
 911         val = I915_READ(reg);
 912         cur_state = !!(val & PIPECONF_ENABLE);
 913         WARN(cur_state != state,
 914              "pipe %c assertion failure (expected %s, current %s)\n",
 915              pipe_name(pipe), state_string(state), state_string(cur_state));
 916 }
 917 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 918 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 919
 920 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 921                                  enum plane plane)
 922 {
 923         int reg;
 924         u32 val;
 925
 926         reg = DSPCNTR(plane);
 927         val = I915_READ(reg);
 928         WARN(!(val & DISPLAY_PLANE_ENABLE),
 929              "plane %c assertion failure, should be active but is disabled\n",
 930              plane_name(plane));
 931 }
 932
 933 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 934                                    enum pipe pipe)
 935 {
 936         int reg, i;
 937         u32 val;
 938         int cur_pipe;
 939
 940         /* Planes are fixed to pipes on ILK+ */
 941         if (HAS_PCH_SPLIT(dev_priv->dev))
 942                 return;
 943
 944         /* Need to check both planes against the pipe */
 945         for (i = 0; i < 2; i++) {
 946                 reg = DSPCNTR(i);
 947                 val = I915_READ(reg);
 948                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 949                         DISPPLANE_SEL_PIPE_SHIFT;
 950                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 951                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 952                      plane_name(i), pipe_name(pipe));
 953         }
 954 }
 955
 956 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 957 {
 958         u32 val;
 959         bool enabled;
 960
 961         val = I915_READ(PCH_DREF_CONTROL);
 962         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 963                             DREF_SUPERSPREAD_SOURCE_MASK));
 964         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 965 }
 966
 967 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 968                                        enum pipe pipe)
 969 {
 970         int reg;
 971         u32 val;
 972         bool enabled;
 973
 974         reg = TRANSCONF(pipe);
 975         val = I915_READ(reg);
 976         enabled = !!(val & TRANS_ENABLE);
 977         WARN(enabled,
 978              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 979              pipe_name(pipe));
 980 }
 981
 982 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
 983                                    enum pipe pipe, int reg)
 984 {
 985         u32 val = I915_READ(reg);
 986         WARN(DP_PIPE_ENABLED(val, pipe),
 987              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 988              reg, pipe_name(pipe));
 989 }
 990
 991 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 992                                      enum pipe pipe, int reg)
 993 {
 994         u32 val = I915_READ(reg);
 995         WARN(HDMI_PIPE_ENABLED(val, pipe),
 996              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 997              reg, pipe_name(pipe));
 998 }
 999
1000 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1001                                       enum pipe pipe)
1002 {
1003         int reg;
1004         u32 val;
1005
1006         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1007         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1008         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1009
1010         reg = PCH_ADPA;
1011         val = I915_READ(reg);
1012         WARN(ADPA_PIPE_ENABLED(val, pipe),
1013              "PCH VGA enabled on transcoder %c, should be disabled\n",
1014              pipe_name(pipe));
1015
1016         reg = PCH_LVDS;
1017         val = I915_READ(reg);
1018         WARN(LVDS_PIPE_ENABLED(val, pipe),
1019              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1020              pipe_name(pipe));
1021
1022         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1023         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1024         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1025 }
1026
1027 /**
1028  * intel_enable_pll - enable a PLL
1029  * @dev_priv: i915 private structure
1030  * @pipe: pipe PLL to enable
1031  *
1032  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1033  * make sure the PLL reg is writable first though, since the panel write
1034  * protect mechanism may be enabled.
1035  *
1036  * Note!  This is for pre-ILK only.
1037  */
1038 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1039 {
1040         int reg;
1041         u32 val;
1042
1043         /* No really, not for ILK+ */
1044         BUG_ON(dev_priv->info->gen >= 5);
1045
1046         /* PLL is protected by panel, make sure we can write it */
1047         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1048                 assert_panel_unlocked(dev_priv, pipe);
1049
1050         reg = DPLL(pipe);
1051         val = I915_READ(reg);
1052         val |= DPLL_VCO_ENABLE;
1053
1054         /* We do this three times for luck */
1055         I915_WRITE(reg, val);
1056         POSTING_READ(reg);
1057         udelay(150); /* wait for warmup */
1058         I915_WRITE(reg, val);
1059         POSTING_READ(reg);
1060         udelay(150); /* wait for warmup */
1061         I915_WRITE(reg, val);
1062         POSTING_READ(reg);
1063         udelay(150); /* wait for warmup */
1064 }
1065
1066 /**
1067  * intel_disable_pll - disable a PLL
1068  * @dev_priv: i915 private structure
1069  * @pipe: pipe PLL to disable
1070  *
1071  * Disable the PLL for @pipe, making sure the pipe is off first.
1072  *
1073  * Note!  This is for pre-ILK only.
1074  */
1075 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1076 {
1077         int reg;
1078         u32 val;
1079
1080         /* Don't disable pipe A or pipe A PLLs if needed */
1081         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1082                 return;
1083
1084         /* Make sure the pipe isn't still relying on us */
1085         assert_pipe_disabled(dev_priv, pipe);
1086
1087         reg = DPLL(pipe);
1088         val = I915_READ(reg);
1089         val &= ~DPLL_VCO_ENABLE;
1090         I915_WRITE(reg, val);
1091         POSTING_READ(reg);
1092 }
1093
1094 /**
1095  * intel_enable_pch_pll - enable PCH PLL
1096  * @dev_priv: i915 private structure
1097  * @pipe: pipe PLL to enable
1098  *
1099  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1100  * drives the transcoder clock.
1101  */
1102 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1103                                  enum pipe pipe)
1104 {
1105         int reg;
1106         u32 val;
1107
1108         /* PCH only available on ILK+ */
1109         BUG_ON(dev_priv->info->gen < 5);
1110
1111         /* PCH refclock must be enabled first */
1112         assert_pch_refclk_enabled(dev_priv);
1113
1114         reg = PCH_DPLL(pipe);
1115         val = I915_READ(reg);
1116         val |= DPLL_VCO_ENABLE;
1117         I915_WRITE(reg, val);
1118         POSTING_READ(reg);
1119         udelay(200);
1120 }
1121
1122 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1123                                   enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* PCH only available on ILK+ */
1129         BUG_ON(dev_priv->info->gen < 5);
1130
1131         /* Make sure transcoder isn't still depending on us */
1132         assert_transcoder_disabled(dev_priv, pipe);
1133
1134         reg = PCH_DPLL(pipe);
1135         val = I915_READ(reg);
1136         val &= ~DPLL_VCO_ENABLE;
1137         I915_WRITE(reg, val);
1138         POSTING_READ(reg);
1139         udelay(200);
1140 }
1141
1142 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1143                                     enum pipe pipe)
1144 {
1145         int reg;
1146         u32 val;
1147
1148         /* PCH only available on ILK+ */
1149         BUG_ON(dev_priv->info->gen < 5);
1150
1151         /* Make sure PCH DPLL is enabled */
1152         assert_pch_pll_enabled(dev_priv, pipe);
1153
1154         /* FDI must be feeding us bits for PCH ports */
1155         assert_fdi_tx_enabled(dev_priv, pipe);
1156         assert_fdi_rx_enabled(dev_priv, pipe);
1157
1158         reg = TRANSCONF(pipe);
1159         val = I915_READ(reg);
1160         /*
1161          * make the BPC in transcoder be consistent with
1162          * that in pipeconf reg.
1163          */
1164         val &= ~PIPE_BPC_MASK;
1165         val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1166         I915_WRITE(reg, val | TRANS_ENABLE);
1167         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1168                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1169 }
1170
1171 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1172                                      enum pipe pipe)
1173 {
1174         int reg;
1175         u32 val;
1176
1177         /* FDI relies on the transcoder */
1178         assert_fdi_tx_disabled(dev_priv, pipe);
1179         assert_fdi_rx_disabled(dev_priv, pipe);
1180
1181         /* Ports must be off as well */
1182         assert_pch_ports_disabled(dev_priv, pipe);
1183
1184         reg = TRANSCONF(pipe);
1185         val = I915_READ(reg);
1186         val &= ~TRANS_ENABLE;
1187         I915_WRITE(reg, val);
1188         /* wait for PCH transcoder off, transcoder state */
1189         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1190                 DRM_ERROR("failed to disable transcoder\n");
1191 }
1192
1193 /**
1194  * intel_enable_pipe - enable a pipe, asserting requirements
1195  * @dev_priv: i915 private structure
1196  * @pipe: pipe to enable
1197  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1198  *
1199  * Enable @pipe, making sure that various hardware specific requirements
1200  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1201  *
1202  * @pipe should be %PIPE_A or %PIPE_B.
1203  *
1204  * Will wait until the pipe is actually running (i.e. first vblank) before
1205  * returning.
1206  */
1207 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1208                               bool pch_port)
1209 {
1210         int reg;
1211         u32 val;
1212
1213         /*
1214          * A pipe without a PLL won't actually be able to drive bits from
1215          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1216          * need the check.
1217          */
1218         if (!HAS_PCH_SPLIT(dev_priv->dev))
1219                 assert_pll_enabled(dev_priv, pipe);
1220         else {
1221                 if (pch_port) {
1222                         /* if driving the PCH, we need FDI enabled */
1223                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1224                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1225                 }
1226                 /* FIXME: assert CPU port conditions for SNB+ */
1227         }
1228
1229         reg = PIPECONF(pipe);
1230         val = I915_READ(reg);
1231         if (val & PIPECONF_ENABLE)
1232                 return;
1233
1234         I915_WRITE(reg, val | PIPECONF_ENABLE);
1235         intel_wait_for_vblank(dev_priv->dev, pipe);
1236 }
1237
1238 /**
1239  * intel_disable_pipe - disable a pipe, asserting requirements
1240  * @dev_priv: i915 private structure
1241  * @pipe: pipe to disable
1242  *
1243  * Disable @pipe, making sure that various hardware specific requirements
1244  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1245  *
1246  * @pipe should be %PIPE_A or %PIPE_B.
1247  *
1248  * Will wait until the pipe has shut down before returning.
1249  */
1250 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1251                                enum pipe pipe)
1252 {
1253         int reg;
1254         u32 val;
1255
1256         /*
1257          * Make sure planes won't keep trying to pump pixels to us,
1258          * or we might hang the display.
1259          */
1260         assert_planes_disabled(dev_priv, pipe);
1261
1262         /* Don't disable pipe A or pipe A PLLs if needed */
1263         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1264                 return;
1265
1266         reg = PIPECONF(pipe);
1267         val = I915_READ(reg);
1268         if ((val & PIPECONF_ENABLE) == 0)
1269                 return;
1270
1271         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1272         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1273 }
1274
1275 /**
1276  * intel_enable_plane - enable a display plane on a given pipe
1277  * @dev_priv: i915 private structure
1278  * @plane: plane to enable
1279  * @pipe: pipe being fed
1280  *
1281  * Enable @plane on @pipe, making sure that @pipe is running first.
1282  */
1283 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1284                                enum plane plane, enum pipe pipe)
1285 {
1286         int reg;
1287         u32 val;
1288
1289         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1290         assert_pipe_enabled(dev_priv, pipe);
1291
1292         reg = DSPCNTR(plane);
1293         val = I915_READ(reg);
1294         if (val & DISPLAY_PLANE_ENABLE)
1295                 return;
1296
1297         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1298         intel_wait_for_vblank(dev_priv->dev, pipe);
1299 }
1300
1301 /*
1302  * Plane regs are double buffered, going from enabled->disabled needs a
1303  * trigger in order to latch.  The display address reg provides this.
1304  */
1305 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1306                                       enum plane plane)
1307 {
1308         u32 reg = DSPADDR(plane);
1309         I915_WRITE(reg, I915_READ(reg));
1310 }
1311
1312 /**
1313  * intel_disable_plane - disable a display plane
1314  * @dev_priv: i915 private structure
1315  * @plane: plane to disable
1316  * @pipe: pipe consuming the data
1317  *
1318  * Disable @plane; should be an independent operation.
1319  */
1320 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1321                                 enum plane plane, enum pipe pipe)
1322 {
1323         int reg;
1324         u32 val;
1325
1326         reg = DSPCNTR(plane);
1327         val = I915_READ(reg);
1328         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1329                 return;
1330
1331         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1332         intel_flush_display_plane(dev_priv, plane);
1333         intel_wait_for_vblank(dev_priv->dev, pipe);
1334 }
1335
1336 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1337                            enum pipe pipe, int reg)
1338 {
1339         u32 val = I915_READ(reg);
1340         if (DP_PIPE_ENABLED(val, pipe))
1341                 I915_WRITE(reg, val & ~DP_PORT_EN);
1342 }
1343
1344 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1345                              enum pipe pipe, int reg)
1346 {
1347         u32 val = I915_READ(reg);
1348         if (HDMI_PIPE_ENABLED(val, pipe))
1349                 I915_WRITE(reg, val & ~PORT_ENABLE);
1350 }
1351
1352 /* Disable any ports connected to this transcoder */
1353 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1354                                     enum pipe pipe)
1355 {
1356         u32 reg, val;
1357
1358         val = I915_READ(PCH_PP_CONTROL);
1359         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1360
1361         disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1362         disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1363         disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1364
1365         reg = PCH_ADPA;
1366         val = I915_READ(reg);
1367         if (ADPA_PIPE_ENABLED(val, pipe))
1368                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1369
1370         reg = PCH_LVDS;
1371         val = I915_READ(reg);
1372         if (LVDS_PIPE_ENABLED(val, pipe)) {
1373                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1374                 POSTING_READ(reg);
1375                 udelay(100);
1376         }
1377
1378         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1379         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1380         disable_pch_hdmi(dev_priv, pipe, HDMID);
1381 }
1382
1383 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1384 {
1385         struct drm_device *dev = crtc->dev;
1386         struct drm_i915_private *dev_priv = dev->dev_private;
1387         struct drm_framebuffer *fb = crtc->fb;
1388         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1389         struct drm_i915_gem_object *obj = intel_fb->obj;
1390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1391         int plane, i;
1392         u32 fbc_ctl, fbc_ctl2;
1393
1394         if (fb->pitch == dev_priv->cfb_pitch &&
1395             obj->fence_reg == dev_priv->cfb_fence &&
1396             intel_crtc->plane == dev_priv->cfb_plane &&
1397             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1398                 return;
1399
1400         i8xx_disable_fbc(dev);
1401
1402         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1403
1404         if (fb->pitch < dev_priv->cfb_pitch)
1405                 dev_priv->cfb_pitch = fb->pitch;
1406
1407         /* FBC_CTL wants 64B units */
1408         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1409         dev_priv->cfb_fence = obj->fence_reg;
1410         dev_priv->cfb_plane = intel_crtc->plane;
1411         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1412
1413         /* Clear old tags */
1414         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1415                 I915_WRITE(FBC_TAG + (i * 4), 0);
1416
1417         /* Set it up... */
1418         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1419         if (obj->tiling_mode != I915_TILING_NONE)
1420                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1421         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1422         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1423
1424         /* enable it... */
1425         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1426         if (IS_I945GM(dev))
1427                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1428         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1429         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1430         if (obj->tiling_mode != I915_TILING_NONE)
1431                 fbc_ctl |= dev_priv->cfb_fence;
1432         I915_WRITE(FBC_CONTROL, fbc_ctl);
1433
1434         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1435                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1436 }
1437
1438 void i8xx_disable_fbc(struct drm_device *dev)
1439 {
1440         struct drm_i915_private *dev_priv = dev->dev_private;
1441         u32 fbc_ctl;
1442
1443         /* Disable compression */
1444         fbc_ctl = I915_READ(FBC_CONTROL);
1445         if ((fbc_ctl & FBC_CTL_EN) == 0)
1446                 return;
1447
1448         fbc_ctl &= ~FBC_CTL_EN;
1449         I915_WRITE(FBC_CONTROL, fbc_ctl);
1450
1451         /* Wait for compressing bit to clear */
1452         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1453                 DRM_DEBUG_KMS("FBC idle timed out\n");
1454                 return;
1455         }
1456
1457         DRM_DEBUG_KMS("disabled FBC\n");
1458 }
1459
1460 static bool i8xx_fbc_enabled(struct drm_device *dev)
1461 {
1462         struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1465 }
1466
1467 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1468 {
1469         struct drm_device *dev = crtc->dev;
1470         struct drm_i915_private *dev_priv = dev->dev_private;
1471         struct drm_framebuffer *fb = crtc->fb;
1472         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1473         struct drm_i915_gem_object *obj = intel_fb->obj;
1474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1475         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1476         unsigned long stall_watermark = 200;
1477         u32 dpfc_ctl;
1478
1479         dpfc_ctl = I915_READ(DPFC_CONTROL);
1480         if (dpfc_ctl & DPFC_CTL_EN) {
1481                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1482                     dev_priv->cfb_fence == obj->fence_reg &&
1483                     dev_priv->cfb_plane == intel_crtc->plane &&
1484                     dev_priv->cfb_y == crtc->y)
1485                         return;
1486
1487                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1488                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1489         }
1490
1491         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1492         dev_priv->cfb_fence = obj->fence_reg;
1493         dev_priv->cfb_plane = intel_crtc->plane;
1494         dev_priv->cfb_y = crtc->y;
1495
1496         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1497         if (obj->tiling_mode != I915_TILING_NONE) {
1498                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1499                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1500         } else {
1501                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1502         }
1503
1504         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1505                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1506                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1507         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1508
1509         /* enable it... */
1510         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1511
1512         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1513 }
1514
1515 void g4x_disable_fbc(struct drm_device *dev)
1516 {
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518         u32 dpfc_ctl;
1519
1520         /* Disable compression */
1521         dpfc_ctl = I915_READ(DPFC_CONTROL);
1522         if (dpfc_ctl & DPFC_CTL_EN) {
1523                 dpfc_ctl &= ~DPFC_CTL_EN;
1524                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1525
1526                 DRM_DEBUG_KMS("disabled FBC\n");
1527         }
1528 }
1529
1530 static bool g4x_fbc_enabled(struct drm_device *dev)
1531 {
1532         struct drm_i915_private *dev_priv = dev->dev_private;
1533
1534         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1535 }
1536
1537 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1538 {
1539         struct drm_i915_private *dev_priv = dev->dev_private;
1540         u32 blt_ecoskpd;
1541
1542         /* Make sure blitter notifies FBC of writes */
1543         gen6_gt_force_wake_get(dev_priv);
1544         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1545         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1546                 GEN6_BLITTER_LOCK_SHIFT;
1547         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1548         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1549         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1550         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1551                          GEN6_BLITTER_LOCK_SHIFT);
1552         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1553         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1554         gen6_gt_force_wake_put(dev_priv);
1555 }
1556
1557 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1558 {
1559         struct drm_device *dev = crtc->dev;
1560         struct drm_i915_private *dev_priv = dev->dev_private;
1561         struct drm_framebuffer *fb = crtc->fb;
1562         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1563         struct drm_i915_gem_object *obj = intel_fb->obj;
1564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1565         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1566         unsigned long stall_watermark = 200;
1567         u32 dpfc_ctl;
1568
1569         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1570         if (dpfc_ctl & DPFC_CTL_EN) {
1571                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1572                     dev_priv->cfb_fence == obj->fence_reg &&
1573                     dev_priv->cfb_plane == intel_crtc->plane &&
1574                     dev_priv->cfb_offset == obj->gtt_offset &&
1575                     dev_priv->cfb_y == crtc->y)
1576                         return;
1577
1578                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1579                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1580         }
1581
1582         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1583         dev_priv->cfb_fence = obj->fence_reg;
1584         dev_priv->cfb_plane = intel_crtc->plane;
1585         dev_priv->cfb_offset = obj->gtt_offset;
1586         dev_priv->cfb_y = crtc->y;
1587
1588         dpfc_ctl &= DPFC_RESERVED;
1589         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1590         if (obj->tiling_mode != I915_TILING_NONE) {
1591                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1592                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1593         } else {
1594                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1595         }
1596
1597         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1598                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1599                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1600         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1601         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1602         /* enable it... */
1603         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1604
1605         if (IS_GEN6(dev)) {
1606                 I915_WRITE(SNB_DPFC_CTL_SA,
1607                            SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1608                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1609                 sandybridge_blit_fbc_update(dev);
1610         }
1611
1612         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1613 }
1614
1615 void ironlake_disable_fbc(struct drm_device *dev)
1616 {
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618         u32 dpfc_ctl;
1619
1620         /* Disable compression */
1621         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1622         if (dpfc_ctl & DPFC_CTL_EN) {
1623                 dpfc_ctl &= ~DPFC_CTL_EN;
1624                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1625
1626                 DRM_DEBUG_KMS("disabled FBC\n");
1627         }
1628 }
1629
1630 static bool ironlake_fbc_enabled(struct drm_device *dev)
1631 {
1632         struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1635 }
1636
1637 bool intel_fbc_enabled(struct drm_device *dev)
1638 {
1639         struct drm_i915_private *dev_priv = dev->dev_private;
1640
1641         if (!dev_priv->display.fbc_enabled)
1642                 return false;
1643
1644         return dev_priv->display.fbc_enabled(dev);
1645 }
1646
1647 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1648 {
1649         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1650
1651         if (!dev_priv->display.enable_fbc)
1652                 return;
1653
1654         dev_priv->display.enable_fbc(crtc, interval);
1655 }
1656
1657 void intel_disable_fbc(struct drm_device *dev)
1658 {
1659         struct drm_i915_private *dev_priv = dev->dev_private;
1660
1661         if (!dev_priv->display.disable_fbc)
1662                 return;
1663
1664         dev_priv->display.disable_fbc(dev);
1665 }
1666
1667 /**
1668  * intel_update_fbc - enable/disable FBC as needed
1669  * @dev: the drm_device
1670  *
1671  * Set up the framebuffer compression hardware at mode set time.  We
1672  * enable it if possible:
1673  *   - plane A only (on pre-965)
1674  *   - no pixel mulitply/line duplication
1675  *   - no alpha buffer discard
1676  *   - no dual wide
1677  *   - framebuffer <= 2048 in width, 1536 in height
1678  *
1679  * We can't assume that any compression will take place (worst case),
1680  * so the compressed buffer has to be the same size as the uncompressed
1681  * one.  It also must reside (along with the line length buffer) in
1682  * stolen memory.
1683  *
1684  * We need to enable/disable FBC on a global basis.
1685  */
1686 static void intel_update_fbc(struct drm_device *dev)
1687 {
1688         struct drm_i915_private *dev_priv = dev->dev_private;
1689         struct drm_crtc *crtc = NULL, *tmp_crtc;
1690         struct intel_crtc *intel_crtc;
1691         struct drm_framebuffer *fb;
1692         struct intel_framebuffer *intel_fb;
1693         struct drm_i915_gem_object *obj;
1694
1695         DRM_DEBUG_KMS("\n");
1696
1697         if (!i915_powersave)
1698                 return;
1699
1700         if (!I915_HAS_FBC(dev))
1701                 return;
1702
1703         /*
1704          * If FBC is already on, we just have to verify that we can
1705          * keep it that way...
1706          * Need to disable if:
1707          *   - more than one pipe is active
1708          *   - changing FBC params (stride, fence, mode)
1709          *   - new fb is too large to fit in compressed buffer
1710          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1711          */
1712         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1713                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1714                         if (crtc) {
1715                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1716                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1717                                 goto out_disable;
1718                         }
1719                         crtc = tmp_crtc;
1720                 }
1721         }
1722
1723         if (!crtc || crtc->fb == NULL) {
1724                 DRM_DEBUG_KMS("no output, disabling\n");
1725                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1726                 goto out_disable;
1727         }
1728
1729         intel_crtc = to_intel_crtc(crtc);
1730         fb = crtc->fb;
1731         intel_fb = to_intel_framebuffer(fb);
1732         obj = intel_fb->obj;
1733
1734         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1735                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1736                               "compression\n");
1737                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1738                 goto out_disable;
1739         }
1740         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1741             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1742                 DRM_DEBUG_KMS("mode incompatible with compression, "
1743                               "disabling\n");
1744                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1745                 goto out_disable;
1746         }
1747         if ((crtc->mode.hdisplay > 2048) ||
1748             (crtc->mode.vdisplay > 1536)) {
1749                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1750                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1751                 goto out_disable;
1752         }
1753         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1754                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1755                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1756                 goto out_disable;
1757         }
1758         if (obj->tiling_mode != I915_TILING_X) {
1759                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1760                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1761                 goto out_disable;
1762         }
1763
1764         /* If the kernel debugger is active, always disable compression */
1765         if (in_dbg_master())
1766                 goto out_disable;
1767
1768         intel_enable_fbc(crtc, 500);
1769         return;
1770
1771 out_disable:
1772         /* Multiple disables should be harmless */
1773         if (intel_fbc_enabled(dev)) {
1774                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1775                 intel_disable_fbc(dev);
1776         }
1777 }
1778
1779 int
1780 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1781                            struct drm_i915_gem_object *obj,
1782                            struct intel_ring_buffer *pipelined)
1783 {
1784         struct drm_i915_private *dev_priv = dev->dev_private;
1785         u32 alignment;
1786         int ret;
1787
1788         switch (obj->tiling_mode) {
1789         case I915_TILING_NONE:
1790                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1791                         alignment = 128 * 1024;
1792                 else if (INTEL_INFO(dev)->gen >= 4)
1793                         alignment = 4 * 1024;
1794                 else
1795                         alignment = 64 * 1024;
1796                 break;
1797         case I915_TILING_X:
1798                 /* pin() will align the object as required by fence */
1799                 alignment = 0;
1800                 break;
1801         case I915_TILING_Y:
1802                 /* FIXME: Is this true? */
1803                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1804                 return -EINVAL;
1805         default:
1806                 BUG();
1807         }
1808
1809         dev_priv->mm.interruptible = false;
1810         ret = i915_gem_object_pin(obj, alignment, true);
1811         if (ret)
1812                 goto err_interruptible;
1813
1814         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1815         if (ret)
1816                 goto err_unpin;
1817
1818         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1819          * fence, whereas 965+ only requires a fence if using
1820          * framebuffer compression.  For simplicity, we always install
1821          * a fence as the cost is not that onerous.
1822          */
1823         if (obj->tiling_mode != I915_TILING_NONE) {
1824                 ret = i915_gem_object_get_fence(obj, pipelined);
1825                 if (ret)
1826                         goto err_unpin;
1827         }
1828
1829         dev_priv->mm.interruptible = true;
1830         return 0;
1831
1832 err_unpin:
1833         i915_gem_object_unpin(obj);
1834 err_interruptible:
1835         dev_priv->mm.interruptible = true;
1836         return ret;
1837 }
1838
1839 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1840 static int
1841 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1842                            int x, int y, enum mode_set_atomic state)
1843 {
1844         struct drm_device *dev = crtc->dev;
1845         struct drm_i915_private *dev_priv = dev->dev_private;
1846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1847         struct intel_framebuffer *intel_fb;
1848         struct drm_i915_gem_object *obj;
1849         int plane = intel_crtc->plane;
1850         unsigned long Start, Offset;
1851         u32 dspcntr;
1852         u32 reg;
1853
1854         switch (plane) {
1855         case 0:
1856         case 1:
1857                 break;
1858         default:
1859                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1860                 return -EINVAL;
1861         }
1862
1863         intel_fb = to_intel_framebuffer(fb);
1864         obj = intel_fb->obj;
1865
1866         reg = DSPCNTR(plane);
1867         dspcntr = I915_READ(reg);
1868         /* Mask out pixel format bits in case we change it */
1869         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1870         switch (fb->bits_per_pixel) {
1871         case 8:
1872                 dspcntr |= DISPPLANE_8BPP;
1873                 break;
1874         case 16:
1875                 if (fb->depth == 15)
1876                         dspcntr |= DISPPLANE_15_16BPP;
1877                 else
1878                         dspcntr |= DISPPLANE_16BPP;
1879                 break;
1880         case 24:
1881         case 32:
1882                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1883                 break;
1884         default:
1885                 DRM_ERROR("Unknown color depth\n");
1886                 return -EINVAL;
1887         }
1888         if (INTEL_INFO(dev)->gen >= 4) {
1889                 if (obj->tiling_mode != I915_TILING_NONE)
1890                         dspcntr |= DISPPLANE_TILED;
1891                 else
1892                         dspcntr &= ~DISPPLANE_TILED;
1893         }
1894
1895         if (HAS_PCH_SPLIT(dev))
1896                 /* must disable */
1897                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1898
1899         I915_WRITE(reg, dspcntr);
1900
1901         Start = obj->gtt_offset;
1902         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1903
1904         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1905                       Start, Offset, x, y, fb->pitch);
1906         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1907         if (INTEL_INFO(dev)->gen >= 4) {
1908                 I915_WRITE(DSPSURF(plane), Start);
1909                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1910                 I915_WRITE(DSPADDR(plane), Offset);
1911         } else
1912                 I915_WRITE(DSPADDR(plane), Start + Offset);
1913         POSTING_READ(reg);
1914
1915         intel_update_fbc(dev);
1916         intel_increase_pllclock(crtc);
1917
1918         return 0;
1919 }
1920
1921 static int
1922 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1923                     struct drm_framebuffer *old_fb)
1924 {
1925         struct drm_device *dev = crtc->dev;
1926         struct drm_i915_master_private *master_priv;
1927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1928         int ret;
1929
1930         /* no fb bound */
1931         if (!crtc->fb) {
1932                 DRM_DEBUG_KMS("No FB bound\n");
1933                 return 0;
1934         }
1935
1936         switch (intel_crtc->plane) {
1937         case 0:
1938         case 1:
1939                 break;
1940         default:
1941                 return -EINVAL;
1942         }
1943
1944         mutex_lock(&dev->struct_mutex);
1945         ret = intel_pin_and_fence_fb_obj(dev,
1946                                          to_intel_framebuffer(crtc->fb)->obj,
1947                                          NULL);
1948         if (ret != 0) {
1949                 mutex_unlock(&dev->struct_mutex);
1950                 return ret;
1951         }
1952
1953         if (old_fb) {
1954                 struct drm_i915_private *dev_priv = dev->dev_private;
1955                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1956
1957                 wait_event(dev_priv->pending_flip_queue,
1958                            atomic_read(&dev_priv->mm.wedged) ||
1959                            atomic_read(&obj->pending_flip) == 0);
1960
1961                 /* Big Hammer, we also need to ensure that any pending
1962                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1963                  * current scanout is retired before unpinning the old
1964                  * framebuffer.
1965                  *
1966                  * This should only fail upon a hung GPU, in which case we
1967                  * can safely continue.
1968                  */
1969                 ret = i915_gem_object_flush_gpu(obj);
1970                 (void) ret;
1971         }
1972
1973         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1974                                          LEAVE_ATOMIC_MODE_SET);
1975         if (ret) {
1976                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1977                 mutex_unlock(&dev->struct_mutex);
1978                 return ret;
1979         }
1980
1981         if (old_fb) {
1982                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1983                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1984         }
1985
1986         mutex_unlock(&dev->struct_mutex);
1987
1988         if (!dev->primary->master)
1989                 return 0;
1990
1991         master_priv = dev->primary->master->driver_priv;
1992         if (!master_priv->sarea_priv)
1993                 return 0;
1994
1995         if (intel_crtc->pipe) {
1996                 master_priv->sarea_priv->pipeB_x = x;
1997                 master_priv->sarea_priv->pipeB_y = y;
1998         } else {
1999                 master_priv->sarea_priv->pipeA_x = x;
2000                 master_priv->sarea_priv->pipeA_y = y;
2001         }
2002
2003         return 0;
2004 }
2005
2006 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2007 {
2008         struct drm_device *dev = crtc->dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         u32 dpa_ctl;
2011
2012         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2013         dpa_ctl = I915_READ(DP_A);
2014         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2015
2016         if (clock < 200000) {
2017                 u32 temp;
2018                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2019                 /* workaround for 160Mhz:
2020                    1) program 0x4600c bits 15:0 = 0x8124
2021                    2) program 0x46010 bit 0 = 1
2022                    3) program 0x46034 bit 24 = 1
2023                    4) program 0x64000 bit 14 = 1
2024                    */
2025                 temp = I915_READ(0x4600c);
2026                 temp &= 0xffff0000;
2027                 I915_WRITE(0x4600c, temp | 0x8124);
2028
2029                 temp = I915_READ(0x46010);
2030                 I915_WRITE(0x46010, temp | 1);
2031
2032                 temp = I915_READ(0x46034);
2033                 I915_WRITE(0x46034, temp | (1 << 24));
2034         } else {
2035                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2036         }
2037         I915_WRITE(DP_A, dpa_ctl);
2038
2039         POSTING_READ(DP_A);
2040         udelay(500);
2041 }
2042
2043 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2044 {
2045         struct drm_device *dev = crtc->dev;
2046         struct drm_i915_private *dev_priv = dev->dev_private;
2047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2048         int pipe = intel_crtc->pipe;
2049         u32 reg, temp;
2050
2051         /* enable normal train */
2052         reg = FDI_TX_CTL(pipe);
2053         temp = I915_READ(reg);
2054         if (IS_GEN6(dev)) {
2055                 temp &= ~FDI_LINK_TRAIN_NONE;
2056                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2057         } else if (IS_IVYBRIDGE(dev)) {
2058                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2059                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2060         }
2061         I915_WRITE(reg, temp);
2062
2063         reg = FDI_RX_CTL(pipe);
2064         temp = I915_READ(reg);
2065         if (HAS_PCH_CPT(dev)) {
2066                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2067                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2068         } else {
2069                 temp &= ~FDI_LINK_TRAIN_NONE;
2070                 temp |= FDI_LINK_TRAIN_NONE;
2071         }
2072         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2073
2074         /* wait one idle pattern time */
2075         POSTING_READ(reg);
2076         udelay(1000);
2077
2078         /* IVB wants error correction enabled */
2079         if (IS_IVYBRIDGE(dev))
2080                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2081                            FDI_FE_ERRC_ENABLE);
2082 }
2083
2084 /* The FDI link training functions for ILK/Ibexpeak. */
2085 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2086 {
2087         struct drm_device *dev = crtc->dev;
2088         struct drm_i915_private *dev_priv = dev->dev_private;
2089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2090         int pipe = intel_crtc->pipe;
2091         int plane = intel_crtc->plane;
2092         u32 reg, temp, tries;
2093
2094         /* FDI needs bits from pipe & plane first */
2095         assert_pipe_enabled(dev_priv, pipe);
2096         assert_plane_enabled(dev_priv, plane);
2097
2098         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2099            for train result */
2100         reg = FDI_RX_IMR(pipe);
2101         temp = I915_READ(reg);
2102         temp &= ~FDI_RX_SYMBOL_LOCK;
2103         temp &= ~FDI_RX_BIT_LOCK;
2104         I915_WRITE(reg, temp);
2105         I915_READ(reg);
2106         udelay(150);
2107
2108         /* enable CPU FDI TX and PCH FDI RX */
2109         reg = FDI_TX_CTL(pipe);
2110         temp = I915_READ(reg);
2111         temp &= ~(7 << 19);
2112         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2113         temp &= ~FDI_LINK_TRAIN_NONE;
2114         temp |= FDI_LINK_TRAIN_PATTERN_1;
2115         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2116
2117         reg = FDI_RX_CTL(pipe);
2118         temp = I915_READ(reg);
2119         temp &= ~FDI_LINK_TRAIN_NONE;
2120         temp |= FDI_LINK_TRAIN_PATTERN_1;
2121         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2122
2123         POSTING_READ(reg);
2124         udelay(150);
2125
2126         /* Ironlake workaround, enable clock pointer after FDI enable*/
2127         if (HAS_PCH_IBX(dev)) {
2128                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2129                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2130                            FDI_RX_PHASE_SYNC_POINTER_EN);
2131         }
2132
2133         reg = FDI_RX_IIR(pipe);
2134         for (tries = 0; tries < 5; tries++) {
2135                 temp = I915_READ(reg);
2136                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2137
2138                 if ((temp & FDI_RX_BIT_LOCK)) {
2139                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2140                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2141                         break;
2142                 }
2143         }
2144         if (tries == 5)
2145                 DRM_ERROR("FDI train 1 fail!\n");
2146
2147         /* Train 2 */
2148         reg = FDI_TX_CTL(pipe);
2149         temp = I915_READ(reg);
2150         temp &= ~FDI_LINK_TRAIN_NONE;
2151         temp |= FDI_LINK_TRAIN_PATTERN_2;
2152         I915_WRITE(reg, temp);
2153
2154         reg = FDI_RX_CTL(pipe);
2155         temp = I915_READ(reg);
2156         temp &= ~FDI_LINK_TRAIN_NONE;
2157         temp |= FDI_LINK_TRAIN_PATTERN_2;
2158         I915_WRITE(reg, temp);
2159
2160         POSTING_READ(reg);
2161         udelay(150);
2162
2163         reg = FDI_RX_IIR(pipe);
2164         for (tries = 0; tries < 5; tries++) {
2165                 temp = I915_READ(reg);
2166                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2167
2168                 if (temp & FDI_RX_SYMBOL_LOCK) {
2169                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2170                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2171                         break;
2172                 }
2173         }
2174         if (tries == 5)
2175                 DRM_ERROR("FDI train 2 fail!\n");
2176
2177         DRM_DEBUG_KMS("FDI train done\n");
2178
2179 }
2180
2181 static const int snb_b_fdi_train_param [] = {
2182         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2183         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2184         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2185         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2186 };
2187
2188 /* The FDI link training functions for SNB/Cougarpoint. */
2189 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2190 {
2191         struct drm_device *dev = crtc->dev;
2192         struct drm_i915_private *dev_priv = dev->dev_private;
2193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2194         int pipe = intel_crtc->pipe;
2195         u32 reg, temp, i;
2196
2197         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2198            for train result */
2199         reg = FDI_RX_IMR(pipe);
2200         temp = I915_READ(reg);
2201         temp &= ~FDI_RX_SYMBOL_LOCK;
2202         temp &= ~FDI_RX_BIT_LOCK;
2203         I915_WRITE(reg, temp);
2204
2205         POSTING_READ(reg);
2206         udelay(150);
2207
2208         /* enable CPU FDI TX and PCH FDI RX */
2209         reg = FDI_TX_CTL(pipe);
2210         temp = I915_READ(reg);
2211         temp &= ~(7 << 19);
2212         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2213         temp &= ~FDI_LINK_TRAIN_NONE;
2214         temp |= FDI_LINK_TRAIN_PATTERN_1;
2215         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2216         /* SNB-B */
2217         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2218         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2219
2220         reg = FDI_RX_CTL(pipe);
2221         temp = I915_READ(reg);
2222         if (HAS_PCH_CPT(dev)) {
2223                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2224                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2225         } else {
2226                 temp &= ~FDI_LINK_TRAIN_NONE;
2227                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2228         }
2229         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2230
2231         POSTING_READ(reg);
2232         udelay(150);
2233
2234         for (i = 0; i < 4; i++ ) {
2235                 reg = FDI_TX_CTL(pipe);
2236                 temp = I915_READ(reg);
2237                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2238                 temp |= snb_b_fdi_train_param[i];
2239                 I915_WRITE(reg, temp);
2240
2241                 POSTING_READ(reg);
2242                 udelay(500);
2243
2244                 reg = FDI_RX_IIR(pipe);
2245                 temp = I915_READ(reg);
2246                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2247
2248                 if (temp & FDI_RX_BIT_LOCK) {
2249                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2250                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2251                         break;
2252                 }
2253         }
2254         if (i == 4)
2255                 DRM_ERROR("FDI train 1 fail!\n");
2256
2257         /* Train 2 */
2258         reg = FDI_TX_CTL(pipe);
2259         temp = I915_READ(reg);
2260         temp &= ~FDI_LINK_TRAIN_NONE;
2261         temp |= FDI_LINK_TRAIN_PATTERN_2;
2262         if (IS_GEN6(dev)) {
2263                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2264                 /* SNB-B */
2265                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2266         }
2267         I915_WRITE(reg, temp);
2268
2269         reg = FDI_RX_CTL(pipe);
2270         temp = I915_READ(reg);
2271         if (HAS_PCH_CPT(dev)) {
2272                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2273                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2274         } else {
2275                 temp &= ~FDI_LINK_TRAIN_NONE;
2276                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2277         }
2278         I915_WRITE(reg, temp);
2279
2280         POSTING_READ(reg);
2281         udelay(150);
2282
2283         for (i = 0; i < 4; i++ ) {
2284                 reg = FDI_TX_CTL(pipe);
2285                 temp = I915_READ(reg);
2286                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2287                 temp |= snb_b_fdi_train_param[i];
2288                 I915_WRITE(reg, temp);
2289
2290                 POSTING_READ(reg);
2291                 udelay(500);
2292
2293                 reg = FDI_RX_IIR(pipe);
2294                 temp = I915_READ(reg);
2295                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2296
2297                 if (temp & FDI_RX_SYMBOL_LOCK) {
2298                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2299                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2300                         break;
2301                 }
2302         }
2303         if (i == 4)
2304                 DRM_ERROR("FDI train 2 fail!\n");
2305
2306         DRM_DEBUG_KMS("FDI train done.\n");
2307 }
2308
2309 /* Manual link training for Ivy Bridge A0 parts */
2310 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2311 {
2312         struct drm_device *dev = crtc->dev;
2313         struct drm_i915_private *dev_priv = dev->dev_private;
2314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2315         int pipe = intel_crtc->pipe;
2316         u32 reg, temp, i;
2317
2318         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2319            for train result */
2320         reg = FDI_RX_IMR(pipe);
2321         temp = I915_READ(reg);
2322         temp &= ~FDI_RX_SYMBOL_LOCK;
2323         temp &= ~FDI_RX_BIT_LOCK;
2324         I915_WRITE(reg, temp);
2325
2326         POSTING_READ(reg);
2327         udelay(150);
2328
2329         /* enable CPU FDI TX and PCH FDI RX */
2330         reg = FDI_TX_CTL(pipe);
2331         temp = I915_READ(reg);
2332         temp &= ~(7 << 19);
2333         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2334         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2335         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2336         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2337         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2338         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2339
2340         reg = FDI_RX_CTL(pipe);
2341         temp = I915_READ(reg);
2342         temp &= ~FDI_LINK_TRAIN_AUTO;
2343         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2344         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2345         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2346
2347         POSTING_READ(reg);
2348         udelay(150);
2349
2350         for (i = 0; i < 4; i++ ) {
2351                 reg = FDI_TX_CTL(pipe);
2352                 temp = I915_READ(reg);
2353                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2354                 temp |= snb_b_fdi_train_param[i];
2355                 I915_WRITE(reg, temp);
2356
2357                 POSTING_READ(reg);
2358                 udelay(500);
2359
2360                 reg = FDI_RX_IIR(pipe);
2361                 temp = I915_READ(reg);
2362                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2363
2364                 if (temp & FDI_RX_BIT_LOCK ||
2365                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2366                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2367                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2368                         break;
2369                 }
2370         }
2371         if (i == 4)
2372                 DRM_ERROR("FDI train 1 fail!\n");
2373
2374         /* Train 2 */
2375         reg = FDI_TX_CTL(pipe);
2376         temp = I915_READ(reg);
2377         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2378         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2379         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2380         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2381         I915_WRITE(reg, temp);
2382
2383         reg = FDI_RX_CTL(pipe);
2384         temp = I915_READ(reg);
2385         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2386         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2387         I915_WRITE(reg, temp);
2388
2389         POSTING_READ(reg);
2390         udelay(150);
2391
2392         for (i = 0; i < 4; i++ ) {
2393                 reg = FDI_TX_CTL(pipe);
2394                 temp = I915_READ(reg);
2395                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2396                 temp |= snb_b_fdi_train_param[i];
2397                 I915_WRITE(reg, temp);
2398
2399                 POSTING_READ(reg);
2400                 udelay(500);
2401
2402                 reg = FDI_RX_IIR(pipe);
2403                 temp = I915_READ(reg);
2404                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2405
2406                 if (temp & FDI_RX_SYMBOL_LOCK) {
2407                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2408                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2409                         break;
2410                 }
2411         }
2412         if (i == 4)
2413                 DRM_ERROR("FDI train 2 fail!\n");
2414
2415         DRM_DEBUG_KMS("FDI train done.\n");
2416 }
2417
2418 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2419 {
2420         struct drm_device *dev = crtc->dev;
2421         struct drm_i915_private *dev_priv = dev->dev_private;
2422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2423         int pipe = intel_crtc->pipe;
2424         u32 reg, temp;
2425
2426         /* Write the TU size bits so error detection works */
2427         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2428                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2429
2430         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2431         reg = FDI_RX_CTL(pipe);
2432         temp = I915_READ(reg);
2433         temp &= ~((0x7 << 19) | (0x7 << 16));
2434         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2435         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2436         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2437
2438         POSTING_READ(reg);
2439         udelay(200);
2440
2441         /* Switch from Rawclk to PCDclk */
2442         temp = I915_READ(reg);
2443         I915_WRITE(reg, temp | FDI_PCDCLK);
2444
2445         POSTING_READ(reg);
2446         udelay(200);
2447
2448         /* Enable CPU FDI TX PLL, always on for Ironlake */
2449         reg = FDI_TX_CTL(pipe);
2450         temp = I915_READ(reg);
2451         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2452                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2453
2454                 POSTING_READ(reg);
2455                 udelay(100);
2456         }
2457 }
2458
2459 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2460 {
2461         struct drm_device *dev = crtc->dev;
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2464         int pipe = intel_crtc->pipe;
2465         u32 reg, temp;
2466
2467         /* disable CPU FDI tx and PCH FDI rx */
2468         reg = FDI_TX_CTL(pipe);
2469         temp = I915_READ(reg);
2470         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2471         POSTING_READ(reg);
2472
2473         reg = FDI_RX_CTL(pipe);
2474         temp = I915_READ(reg);
2475         temp &= ~(0x7 << 16);
2476         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2477         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2478
2479         POSTING_READ(reg);
2480         udelay(100);
2481
2482         /* Ironlake workaround, disable clock pointer after downing FDI */
2483         if (HAS_PCH_IBX(dev)) {
2484                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2485                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2486                            I915_READ(FDI_RX_CHICKEN(pipe) &
2487                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2488         }
2489
2490         /* still set train pattern 1 */
2491         reg = FDI_TX_CTL(pipe);
2492         temp = I915_READ(reg);
2493         temp &= ~FDI_LINK_TRAIN_NONE;
2494         temp |= FDI_LINK_TRAIN_PATTERN_1;
2495         I915_WRITE(reg, temp);
2496
2497         reg = FDI_RX_CTL(pipe);
2498         temp = I915_READ(reg);
2499         if (HAS_PCH_CPT(dev)) {
2500                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2501                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2502         } else {
2503                 temp &= ~FDI_LINK_TRAIN_NONE;
2504                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2505         }
2506         /* BPC in FDI rx is consistent with that in PIPECONF */
2507         temp &= ~(0x07 << 16);
2508         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2509         I915_WRITE(reg, temp);
2510
2511         POSTING_READ(reg);
2512         udelay(100);
2513 }
2514
2515 /*
2516  * When we disable a pipe, we need to clear any pending scanline wait events
2517  * to avoid hanging the ring, which we assume we are waiting on.
2518  */
2519 static void intel_clear_scanline_wait(struct drm_device *dev)
2520 {
2521         struct drm_i915_private *dev_priv = dev->dev_private;
2522         struct intel_ring_buffer *ring;
2523         u32 tmp;
2524
2525         if (IS_GEN2(dev))
2526                 /* Can't break the hang on i8xx */
2527                 return;
2528
2529         ring = LP_RING(dev_priv);
2530         tmp = I915_READ_CTL(ring);
2531         if (tmp & RING_WAIT)
2532                 I915_WRITE_CTL(ring, tmp);
2533 }
2534
2535 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2536 {
2537         struct drm_i915_gem_object *obj;
2538         struct drm_i915_private *dev_priv;
2539
2540         if (crtc->fb == NULL)
2541                 return;
2542
2543         obj = to_intel_framebuffer(crtc->fb)->obj;
2544         dev_priv = crtc->dev->dev_private;
2545         wait_event(dev_priv->pending_flip_queue,
2546                    atomic_read(&obj->pending_flip) == 0);
2547 }
2548
2549 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2550 {
2551         struct drm_device *dev = crtc->dev;
2552         struct drm_mode_config *mode_config = &dev->mode_config;
2553         struct intel_encoder *encoder;
2554
2555         /*
2556          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2557          * must be driven by its own crtc; no sharing is possible.
2558          */
2559         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2560                 if (encoder->base.crtc != crtc)
2561                         continue;
2562
2563                 switch (encoder->type) {
2564                 case INTEL_OUTPUT_EDP:
2565                         if (!intel_encoder_is_pch_edp(&encoder->base))
2566                                 return false;
2567                         continue;
2568                 }
2569         }
2570
2571         return true;
2572 }
2573
2574 /*
2575  * Enable PCH resources required for PCH ports:
2576  *   - PCH PLLs
2577  *   - FDI training & RX/TX
2578  *   - update transcoder timings
2579  *   - DP transcoding bits
2580  *   - transcoder
2581  */
2582 static void ironlake_pch_enable(struct drm_crtc *crtc)
2583 {
2584         struct drm_device *dev = crtc->dev;
2585         struct drm_i915_private *dev_priv = dev->dev_private;
2586         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2587         int pipe = intel_crtc->pipe;
2588         u32 reg, temp;
2589
2590         /* For PCH output, training FDI link */
2591         dev_priv->display.fdi_link_train(crtc);
2592
2593         intel_enable_pch_pll(dev_priv, pipe);
2594
2595         if (HAS_PCH_CPT(dev)) {
2596                 /* Be sure PCH DPLL SEL is set */
2597                 temp = I915_READ(PCH_DPLL_SEL);
2598                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2599                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2600                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2601                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2602                 I915_WRITE(PCH_DPLL_SEL, temp);
2603         }
2604
2605         /* set transcoder timing, panel must allow it */
2606         assert_panel_unlocked(dev_priv, pipe);
2607         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2608         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2609         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2610
2611         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2612         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2613         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2614
2615         intel_fdi_normal_train(crtc);
2616
2617         /* For PCH DP, enable TRANS_DP_CTL */
2618         if (HAS_PCH_CPT(dev) &&
2619             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2620                 reg = TRANS_DP_CTL(pipe);
2621                 temp = I915_READ(reg);
2622                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2623                           TRANS_DP_SYNC_MASK |
2624                           TRANS_DP_BPC_MASK);
2625                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2626                          TRANS_DP_ENH_FRAMING);
2627                 temp |= TRANS_DP_8BPC;
2628
2629                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2630                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2631                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2632                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2633
2634                 switch (intel_trans_dp_port_sel(crtc)) {
2635                 case PCH_DP_B:
2636                         temp |= TRANS_DP_PORT_SEL_B;
2637                         break;
2638                 case PCH_DP_C:
2639                         temp |= TRANS_DP_PORT_SEL_C;
2640                         break;
2641                 case PCH_DP_D:
2642                         temp |= TRANS_DP_PORT_SEL_D;
2643                         break;
2644                 default:
2645                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2646                         temp |= TRANS_DP_PORT_SEL_B;
2647                         break;
2648                 }
2649
2650                 I915_WRITE(reg, temp);
2651         }
2652
2653         intel_enable_transcoder(dev_priv, pipe);
2654 }
2655
2656 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2657 {
2658         struct drm_device *dev = crtc->dev;
2659         struct drm_i915_private *dev_priv = dev->dev_private;
2660         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2661         int pipe = intel_crtc->pipe;
2662         int plane = intel_crtc->plane;
2663         u32 temp;
2664         bool is_pch_port;
2665
2666         if (intel_crtc->active)
2667                 return;
2668
2669         intel_crtc->active = true;
2670         intel_update_watermarks(dev);
2671
2672         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2673                 temp = I915_READ(PCH_LVDS);
2674                 if ((temp & LVDS_PORT_EN) == 0)
2675                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2676         }
2677
2678         is_pch_port = intel_crtc_driving_pch(crtc);
2679
2680         if (is_pch_port)
2681                 ironlake_fdi_pll_enable(crtc);
2682         else
2683                 ironlake_fdi_disable(crtc);
2684
2685         /* Enable panel fitting for LVDS */
2686         if (dev_priv->pch_pf_size &&
2687             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2688                 /* Force use of hard-coded filter coefficients
2689                  * as some pre-programmed values are broken,
2690                  * e.g. x201.
2691                  */
2692                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2693                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2694                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2695         }
2696
2697         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2698         intel_enable_plane(dev_priv, plane, pipe);
2699
2700         if (is_pch_port)
2701                 ironlake_pch_enable(crtc);
2702
2703         intel_crtc_load_lut(crtc);
2704
2705         mutex_lock(&dev->struct_mutex);
2706         intel_update_fbc(dev);
2707         mutex_unlock(&dev->struct_mutex);
2708
2709         intel_crtc_update_cursor(crtc, true);
2710 }
2711
2712 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2713 {
2714         struct drm_device *dev = crtc->dev;
2715         struct drm_i915_private *dev_priv = dev->dev_private;
2716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2717         int pipe = intel_crtc->pipe;
2718         int plane = intel_crtc->plane;
2719         u32 reg, temp;
2720
2721         if (!intel_crtc->active)
2722                 return;
2723
2724         intel_crtc_wait_for_pending_flips(crtc);
2725         drm_vblank_off(dev, pipe);
2726         intel_crtc_update_cursor(crtc, false);
2727
2728         intel_disable_plane(dev_priv, plane, pipe);
2729
2730         if (dev_priv->cfb_plane == plane &&
2731             dev_priv->display.disable_fbc)
2732                 dev_priv->display.disable_fbc(dev);
2733
2734         intel_disable_pipe(dev_priv, pipe);
2735
2736         /* Disable PF */
2737         I915_WRITE(PF_CTL(pipe), 0);
2738         I915_WRITE(PF_WIN_SZ(pipe), 0);
2739
2740         ironlake_fdi_disable(crtc);
2741
2742         /* This is a horrible layering violation; we should be doing this in
2743          * the connector/encoder ->prepare instead, but we don't always have
2744          * enough information there about the config to know whether it will
2745          * actually be necessary or just cause undesired flicker.
2746          */
2747         intel_disable_pch_ports(dev_priv, pipe);
2748
2749         intel_disable_transcoder(dev_priv, pipe);
2750
2751         if (HAS_PCH_CPT(dev)) {
2752                 /* disable TRANS_DP_CTL */
2753                 reg = TRANS_DP_CTL(pipe);
2754                 temp = I915_READ(reg);
2755                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2756                 temp |= TRANS_DP_PORT_SEL_NONE;
2757                 I915_WRITE(reg, temp);
2758
2759                 /* disable DPLL_SEL */
2760                 temp = I915_READ(PCH_DPLL_SEL);
2761                 switch (pipe) {
2762                 case 0:
2763                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2764                         break;
2765                 case 1:
2766                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2767                         break;
2768                 case 2:
2769                         /* FIXME: manage transcoder PLLs? */
2770                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2771                         break;
2772                 default:
2773                         BUG(); /* wtf */
2774                 }
2775                 I915_WRITE(PCH_DPLL_SEL, temp);
2776         }
2777
2778         /* disable PCH DPLL */
2779         intel_disable_pch_pll(dev_priv, pipe);
2780
2781         /* Switch from PCDclk to Rawclk */
2782         reg = FDI_RX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2785
2786         /* Disable CPU FDI TX PLL */
2787         reg = FDI_TX_CTL(pipe);
2788         temp = I915_READ(reg);
2789         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2790
2791         POSTING_READ(reg);
2792         udelay(100);
2793
2794         reg = FDI_RX_CTL(pipe);
2795         temp = I915_READ(reg);
2796         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2797
2798         /* Wait for the clocks to turn off. */
2799         POSTING_READ(reg);
2800         udelay(100);
2801
2802         intel_crtc->active = false;
2803         intel_update_watermarks(dev);
2804
2805         mutex_lock(&dev->struct_mutex);
2806         intel_update_fbc(dev);
2807         intel_clear_scanline_wait(dev);
2808         mutex_unlock(&dev->struct_mutex);
2809 }
2810
2811 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2812 {
2813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2814         int pipe = intel_crtc->pipe;
2815         int plane = intel_crtc->plane;
2816
2817         /* XXX: When our outputs are all unaware of DPMS modes other than off
2818          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2819          */
2820         switch (mode) {
2821         case DRM_MODE_DPMS_ON:
2822         case DRM_MODE_DPMS_STANDBY:
2823         case DRM_MODE_DPMS_SUSPEND:
2824                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2825                 ironlake_crtc_enable(crtc);
2826                 break;
2827
2828         case DRM_MODE_DPMS_OFF:
2829                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2830                 ironlake_crtc_disable(crtc);
2831                 break;
2832         }
2833 }
2834
2835 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2836 {
2837         if (!enable && intel_crtc->overlay) {
2838                 struct drm_device *dev = intel_crtc->base.dev;
2839                 struct drm_i915_private *dev_priv = dev->dev_private;
2840
2841                 mutex_lock(&dev->struct_mutex);
2842                 dev_priv->mm.interruptible = false;
2843                 (void) intel_overlay_switch_off(intel_crtc->overlay);
2844                 dev_priv->mm.interruptible = true;
2845                 mutex_unlock(&dev->struct_mutex);
2846         }
2847
2848         /* Let userspace switch the overlay on again. In most cases userspace
2849          * has to recompute where to put it anyway.
2850          */
2851 }
2852
2853 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2854 {
2855         struct drm_device *dev = crtc->dev;
2856         struct drm_i915_private *dev_priv = dev->dev_private;
2857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2858         int pipe = intel_crtc->pipe;
2859         int plane = intel_crtc->plane;
2860
2861         if (intel_crtc->active)
2862                 return;
2863
2864         intel_crtc->active = true;
2865         intel_update_watermarks(dev);
2866
2867         intel_enable_pll(dev_priv, pipe);
2868         intel_enable_pipe(dev_priv, pipe, false);
2869         intel_enable_plane(dev_priv, plane, pipe);
2870
2871         intel_crtc_load_lut(crtc);
2872         intel_update_fbc(dev);
2873
2874         /* Give the overlay scaler a chance to enable if it's on this pipe */
2875         intel_crtc_dpms_overlay(intel_crtc, true);
2876         intel_crtc_update_cursor(crtc, true);
2877 }
2878
2879 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2880 {
2881         struct drm_device *dev = crtc->dev;
2882         struct drm_i915_private *dev_priv = dev->dev_private;
2883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2884         int pipe = intel_crtc->pipe;
2885         int plane = intel_crtc->plane;
2886
2887         if (!intel_crtc->active)
2888                 return;
2889
2890         /* Give the overlay scaler a chance to disable if it's on this pipe */
2891         intel_crtc_wait_for_pending_flips(crtc);
2892         drm_vblank_off(dev, pipe);
2893         intel_crtc_dpms_overlay(intel_crtc, false);
2894         intel_crtc_update_cursor(crtc, false);
2895
2896         if (dev_priv->cfb_plane == plane &&
2897             dev_priv->display.disable_fbc)
2898                 dev_priv->display.disable_fbc(dev);
2899
2900         intel_disable_plane(dev_priv, plane, pipe);
2901         intel_disable_pipe(dev_priv, pipe);
2902         intel_disable_pll(dev_priv, pipe);
2903
2904         intel_crtc->active = false;
2905         intel_update_fbc(dev);
2906         intel_update_watermarks(dev);
2907         intel_clear_scanline_wait(dev);
2908 }
2909
2910 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2911 {
2912         /* XXX: When our outputs are all unaware of DPMS modes other than off
2913          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2914          */
2915         switch (mode) {
2916         case DRM_MODE_DPMS_ON:
2917         case DRM_MODE_DPMS_STANDBY:
2918         case DRM_MODE_DPMS_SUSPEND:
2919                 i9xx_crtc_enable(crtc);
2920                 break;
2921         case DRM_MODE_DPMS_OFF:
2922                 i9xx_crtc_disable(crtc);
2923                 break;
2924         }
2925 }
2926
2927 /**
2928  * Sets the power management mode of the pipe and plane.
2929  */
2930 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2931 {
2932         struct drm_device *dev = crtc->dev;
2933         struct drm_i915_private *dev_priv = dev->dev_private;
2934         struct drm_i915_master_private *master_priv;
2935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2936         int pipe = intel_crtc->pipe;
2937         bool enabled;
2938
2939         if (intel_crtc->dpms_mode == mode)
2940                 return;
2941
2942         intel_crtc->dpms_mode = mode;
2943
2944         dev_priv->display.dpms(crtc, mode);
2945
2946         if (!dev->primary->master)
2947                 return;
2948
2949         master_priv = dev->primary->master->driver_priv;
2950         if (!master_priv->sarea_priv)
2951                 return;
2952
2953         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2954
2955         switch (pipe) {
2956         case 0:
2957                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2958                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2959                 break;
2960         case 1:
2961                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2962                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2963                 break;
2964         default:
2965                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
2966                 break;
2967         }
2968 }
2969
2970 static void intel_crtc_disable(struct drm_crtc *crtc)
2971 {
2972         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2973         struct drm_device *dev = crtc->dev;
2974
2975         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2976
2977         if (crtc->fb) {
2978                 mutex_lock(&dev->struct_mutex);
2979                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2980                 mutex_unlock(&dev->struct_mutex);
2981         }
2982 }
2983
2984 /* Prepare for a mode set.
2985  *
2986  * Note we could be a lot smarter here.  We need to figure out which outputs
2987  * will be enabled, which disabled (in short, how the config will changes)
2988  * and perform the minimum necessary steps to accomplish that, e.g. updating
2989  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2990  * panel fitting is in the proper state, etc.
2991  */
2992 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2993 {
2994         i9xx_crtc_disable(crtc);
2995 }
2996
2997 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2998 {
2999         i9xx_crtc_enable(crtc);
3000 }
3001
3002 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3003 {
3004         ironlake_crtc_disable(crtc);
3005 }
3006
3007 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3008 {
3009         ironlake_crtc_enable(crtc);
3010 }
3011
3012 void intel_encoder_prepare (struct drm_encoder *encoder)
3013 {
3014         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3015         /* lvds has its own version of prepare see intel_lvds_prepare */
3016         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3017 }
3018
3019 void intel_encoder_commit (struct drm_encoder *encoder)
3020 {
3021         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3022         /* lvds has its own version of commit see intel_lvds_commit */
3023         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3024 }
3025
3026 void intel_encoder_destroy(struct drm_encoder *encoder)
3027 {
3028         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3029
3030         drm_encoder_cleanup(encoder);
3031         kfree(intel_encoder);
3032 }
3033
3034 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3035                                   struct drm_display_mode *mode,
3036                                   struct drm_display_mode *adjusted_mode)
3037 {
3038         struct drm_device *dev = crtc->dev;
3039
3040         if (HAS_PCH_SPLIT(dev)) {
3041                 /* FDI link clock is fixed at 2.7G */
3042                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3043                         return false;
3044         }
3045
3046         /* XXX some encoders set the crtcinfo, others don't.
3047          * Obviously we need some form of conflict resolution here...
3048          */
3049         if (adjusted_mode->crtc_htotal == 0)
3050                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3051
3052         return true;
3053 }
3054
3055 static int i945_get_display_clock_speed(struct drm_device *dev)
3056 {
3057         return 400000;
3058 }
3059
3060 static int i915_get_display_clock_speed(struct drm_device *dev)
3061 {
3062         return 333000;
3063 }
3064
3065 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3066 {
3067         return 200000;
3068 }
3069
3070 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3071 {
3072         u16 gcfgc = 0;
3073
3074         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3075
3076         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3077                 return 133000;
3078         else {
3079                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3080                 case GC_DISPLAY_CLOCK_333_MHZ:
3081                         return 333000;
3082                 default:
3083                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3084                         return 190000;
3085                 }
3086         }
3087 }
3088
3089 static int i865_get_display_clock_speed(struct drm_device *dev)
3090 {
3091         return 266000;
3092 }
3093
3094 static int i855_get_display_clock_speed(struct drm_device *dev)
3095 {
3096         u16 hpllcc = 0;
3097         /* Assume that the hardware is in the high speed state.  This
3098          * should be the default.
3099          */
3100         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3101         case GC_CLOCK_133_200:
3102         case GC_CLOCK_100_200:
3103                 return 200000;
3104         case GC_CLOCK_166_250:
3105                 return 250000;
3106         case GC_CLOCK_100_133:
3107                 return 133000;
3108         }
3109
3110         /* Shouldn't happen */
3111         return 0;
3112 }
3113
3114 static int i830_get_display_clock_speed(struct drm_device *dev)
3115 {
3116         return 133000;
3117 }
3118
3119 struct fdi_m_n {
3120         u32        tu;
3121         u32        gmch_m;
3122         u32        gmch_n;
3123         u32        link_m;
3124         u32        link_n;
3125 };
3126
3127 static void
3128 fdi_reduce_ratio(u32 *num, u32 *den)
3129 {
3130         while (*num > 0xffffff || *den > 0xffffff) {
3131                 *num >>= 1;
3132                 *den >>= 1;
3133         }
3134 }
3135
3136 static void
3137 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3138                      int link_clock, struct fdi_m_n *m_n)
3139 {
3140         m_n->tu = 64; /* default size */
3141
3142         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3143         m_n->gmch_m = bits_per_pixel * pixel_clock;
3144         m_n->gmch_n = link_clock * nlanes * 8;
3145         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3146
3147         m_n->link_m = pixel_clock;
3148         m_n->link_n = link_clock;
3149         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3150 }
3151
3152
3153 struct intel_watermark_params {
3154         unsigned long fifo_size;
3155         unsigned long max_wm;
3156         unsigned long default_wm;
3157         unsigned long guard_size;
3158         unsigned long cacheline_size;
3159 };
3160
3161 /* Pineview has different values for various configs */
3162 static const struct intel_watermark_params pineview_display_wm = {
3163         PINEVIEW_DISPLAY_FIFO,
3164         PINEVIEW_MAX_WM,
3165         PINEVIEW_DFT_WM,
3166         PINEVIEW_GUARD_WM,
3167         PINEVIEW_FIFO_LINE_SIZE
3168 };
3169 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3170         PINEVIEW_DISPLAY_FIFO,
3171         PINEVIEW_MAX_WM,
3172         PINEVIEW_DFT_HPLLOFF_WM,
3173         PINEVIEW_GUARD_WM,
3174         PINEVIEW_FIFO_LINE_SIZE
3175 };
3176 static const struct intel_watermark_params pineview_cursor_wm = {
3177         PINEVIEW_CURSOR_FIFO,
3178         PINEVIEW_CURSOR_MAX_WM,
3179         PINEVIEW_CURSOR_DFT_WM,
3180         PINEVIEW_CURSOR_GUARD_WM,
3181         PINEVIEW_FIFO_LINE_SIZE,
3182 };
3183 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3184         PINEVIEW_CURSOR_FIFO,
3185         PINEVIEW_CURSOR_MAX_WM,
3186         PINEVIEW_CURSOR_DFT_WM,
3187         PINEVIEW_CURSOR_GUARD_WM,
3188         PINEVIEW_FIFO_LINE_SIZE
3189 };
3190 static const struct intel_watermark_params g4x_wm_info = {
3191         G4X_FIFO_SIZE,
3192         G4X_MAX_WM,
3193         G4X_MAX_WM,
3194         2,
3195         G4X_FIFO_LINE_SIZE,
3196 };
3197 static const struct intel_watermark_params g4x_cursor_wm_info = {
3198         I965_CURSOR_FIFO,
3199         I965_CURSOR_MAX_WM,
3200         I965_CURSOR_DFT_WM,
3201         2,
3202         G4X_FIFO_LINE_SIZE,
3203 };
3204 static const struct intel_watermark_params i965_cursor_wm_info = {
3205         I965_CURSOR_FIFO,
3206         I965_CURSOR_MAX_WM,
3207         I965_CURSOR_DFT_WM,
3208         2,
3209         I915_FIFO_LINE_SIZE,
3210 };
3211 static const struct intel_watermark_params i945_wm_info = {
3212         I945_FIFO_SIZE,
3213         I915_MAX_WM,
3214         1,
3215         2,
3216         I915_FIFO_LINE_SIZE
3217 };
3218 static const struct intel_watermark_params i915_wm_info = {
3219         I915_FIFO_SIZE,
3220         I915_MAX_WM,
3221         1,
3222         2,
3223         I915_FIFO_LINE_SIZE
3224 };
3225 static const struct intel_watermark_params i855_wm_info = {
3226         I855GM_FIFO_SIZE,
3227         I915_MAX_WM,
3228         1,
3229         2,
3230         I830_FIFO_LINE_SIZE
3231 };
3232 static const struct intel_watermark_params i830_wm_info = {
3233         I830_FIFO_SIZE,
3234         I915_MAX_WM,
3235         1,
3236         2,
3237         I830_FIFO_LINE_SIZE
3238 };
3239
3240 static const struct intel_watermark_params ironlake_display_wm_info = {
3241         ILK_DISPLAY_FIFO,
3242         ILK_DISPLAY_MAXWM,
3243         ILK_DISPLAY_DFTWM,
3244         2,
3245         ILK_FIFO_LINE_SIZE
3246 };
3247 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3248         ILK_CURSOR_FIFO,
3249         ILK_CURSOR_MAXWM,
3250         ILK_CURSOR_DFTWM,
3251         2,
3252         ILK_FIFO_LINE_SIZE
3253 };
3254 static const struct intel_watermark_params ironlake_display_srwm_info = {
3255         ILK_DISPLAY_SR_FIFO,
3256         ILK_DISPLAY_MAX_SRWM,
3257         ILK_DISPLAY_DFT_SRWM,
3258         2,
3259         ILK_FIFO_LINE_SIZE
3260 };
3261 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3262         ILK_CURSOR_SR_FIFO,
3263         ILK_CURSOR_MAX_SRWM,
3264         ILK_CURSOR_DFT_SRWM,
3265         2,
3266         ILK_FIFO_LINE_SIZE
3267 };
3268
3269 static const struct intel_watermark_params sandybridge_display_wm_info = {
3270         SNB_DISPLAY_FIFO,
3271         SNB_DISPLAY_MAXWM,
3272         SNB_DISPLAY_DFTWM,
3273         2,
3274         SNB_FIFO_LINE_SIZE
3275 };
3276 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3277         SNB_CURSOR_FIFO,
3278         SNB_CURSOR_MAXWM,
3279         SNB_CURSOR_DFTWM,
3280         2,
3281         SNB_FIFO_LINE_SIZE
3282 };
3283 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3284         SNB_DISPLAY_SR_FIFO,
3285         SNB_DISPLAY_MAX_SRWM,
3286         SNB_DISPLAY_DFT_SRWM,
3287         2,
3288         SNB_FIFO_LINE_SIZE
3289 };
3290 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3291         SNB_CURSOR_SR_FIFO,
3292         SNB_CURSOR_MAX_SRWM,
3293         SNB_CURSOR_DFT_SRWM,
3294         2,
3295         SNB_FIFO_LINE_SIZE
3296 };
3297
3298
3299 /**
3300  * intel_calculate_wm - calculate watermark level
3301  * @clock_in_khz: pixel clock
3302  * @wm: chip FIFO params
3303  * @pixel_size: display pixel size
3304  * @latency_ns: memory latency for the platform
3305  *
3306  * Calculate the watermark level (the level at which the display plane will
3307  * start fetching from memory again).  Each chip has a different display
3308  * FIFO size and allocation, so the caller needs to figure that out and pass
3309  * in the correct intel_watermark_params structure.
3310  *
3311  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3312  * on the pixel size.  When it reaches the watermark level, it'll start
3313  * fetching FIFO line sized based chunks from memory until the FIFO fills
3314  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3315  * will occur, and a display engine hang could result.
3316  */
3317 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3318                                         const struct intel_watermark_params *wm,
3319                                         int fifo_size,
3320                                         int pixel_size,
3321                                         unsigned long latency_ns)
3322 {
3323         long entries_required, wm_size;
3324
3325         /*
3326          * Note: we need to make sure we don't overflow for various clock &
3327          * latency values.
3328          * clocks go from a few thousand to several hundred thousand.
3329          * latency is usually a few thousand
3330          */
3331         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3332                 1000;
3333         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3334
3335         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
3336
3337         wm_size = fifo_size - (entries_required + wm->guard_size);
3338
3339         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
3340
3341         /* Don't promote wm_size to unsigned... */
3342         if (wm_size > (long)wm->max_wm)
3343                 wm_size = wm->max_wm;
3344         if (wm_size <= 0)
3345                 wm_size = wm->default_wm;
3346         return wm_size;
3347 }
3348
3349 struct cxsr_latency {
3350         int is_desktop;
3351         int is_ddr3;
3352         unsigned long fsb_freq;
3353         unsigned long mem_freq;
3354         unsigned long display_sr;
3355         unsigned long display_hpll_disable;
3356         unsigned long cursor_sr;
3357         unsigned long cursor_hpll_disable;
3358 };
3359
3360 static const struct cxsr_latency cxsr_latency_table[] = {
3361         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3362         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3363         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3364         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3365         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3366
3367         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3368         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3369         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3370         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3371         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3372
3373         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3374         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3375         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3376         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3377         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3378
3379         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3380         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3381         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3382         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3383         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3384
3385         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3386         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3387         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3388         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3389         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3390
3391         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3392         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3393         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3394         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3395         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3396 };
3397
3398 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3399                                                          int is_ddr3,
3400                                                          int fsb,
3401                                                          int mem)
3402 {
3403         const struct cxsr_latency *latency;
3404         int i;
3405
3406         if (fsb == 0 || mem == 0)
3407                 return NULL;
3408
3409         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3410                 latency = &cxsr_latency_table[i];
3411                 if (is_desktop == latency->is_desktop &&
3412                     is_ddr3 == latency->is_ddr3 &&
3413                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3414                         return latency;
3415         }
3416
3417         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3418
3419         return NULL;
3420 }
3421
3422 static void pineview_disable_cxsr(struct drm_device *dev)
3423 {
3424         struct drm_i915_private *dev_priv = dev->dev_private;
3425
3426         /* deactivate cxsr */
3427         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3428 }
3429
3430 /*
3431  * Latency for FIFO fetches is dependent on several factors:
3432  *   - memory configuration (speed, channels)
3433  *   - chipset
3434  *   - current MCH state
3435  * It can be fairly high in some situations, so here we assume a fairly
3436  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3437  * set this value too high, the FIFO will fetch frequently to stay full)
3438  * and power consumption (set it too low to save power and we might see
3439  * FIFO underruns and display "flicker").
3440  *
3441  * A value of 5us seems to be a good balance; safe for very low end
3442  * platforms but not overly aggressive on lower latency configs.
3443  */
3444 static const int latency_ns = 5000;
3445
3446 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3447 {
3448         struct drm_i915_private *dev_priv = dev->dev_private;
3449         uint32_t dsparb = I915_READ(DSPARB);
3450         int size;
3451
3452         size = dsparb & 0x7f;
3453         if (plane)
3454                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3455
3456         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3457                       plane ? "B" : "A", size);
3458
3459         return size;
3460 }
3461
3462 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3463 {
3464         struct drm_i915_private *dev_priv = dev->dev_private;
3465         uint32_t dsparb = I915_READ(DSPARB);
3466         int size;
3467
3468         size = dsparb & 0x1ff;
3469         if (plane)
3470                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3471         size >>= 1; /* Convert to cachelines */
3472
3473         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3474                       plane ? "B" : "A", size);
3475
3476         return size;
3477 }
3478
3479 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3480 {
3481         struct drm_i915_private *dev_priv = dev->dev_private;
3482         uint32_t dsparb = I915_READ(DSPARB);
3483         int size;
3484
3485         size = dsparb & 0x7f;
3486         size >>= 2; /* Convert to cachelines */
3487
3488         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3489                       plane ? "B" : "A",
3490                       size);
3491
3492         return size;
3493 }
3494
3495 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3496 {
3497         struct drm_i915_private *dev_priv = dev->dev_private;
3498         uint32_t dsparb = I915_READ(DSPARB);
3499         int size;
3500
3501         size = dsparb & 0x7f;
3502         size >>= 1; /* Convert to cachelines */
3503
3504         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3505                       plane ? "B" : "A", size);
3506
3507         return size;
3508 }
3509
3510 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3511 {
3512         struct drm_crtc *crtc, *enabled = NULL;
3513
3514         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3515                 if (crtc->enabled && crtc->fb) {
3516                         if (enabled)
3517                                 return NULL;
3518                         enabled = crtc;
3519                 }
3520         }
3521
3522         return enabled;
3523 }
3524
3525 static void pineview_update_wm(struct drm_device *dev)
3526 {
3527         struct drm_i915_private *dev_priv = dev->dev_private;
3528         struct drm_crtc *crtc;
3529         const struct cxsr_latency *latency;
3530         u32 reg;
3531         unsigned long wm;
3532
3533         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3534                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3535         if (!latency) {
3536                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3537                 pineview_disable_cxsr(dev);
3538                 return;
3539         }
3540
3541         crtc = single_enabled_crtc(dev);
3542         if (crtc) {
3543                 int clock = crtc->mode.clock;
3544                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3545
3546                 /* Display SR */
3547                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3548                                         pineview_display_wm.fifo_size,
3549                                         pixel_size, latency->display_sr);
3550                 reg = I915_READ(DSPFW1);
3551                 reg &= ~DSPFW_SR_MASK;
3552                 reg |= wm << DSPFW_SR_SHIFT;
3553                 I915_WRITE(DSPFW1, reg);
3554                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3555
3556                 /* cursor SR */
3557                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3558                                         pineview_display_wm.fifo_size,
3559                                         pixel_size, latency->cursor_sr);
3560                 reg = I915_READ(DSPFW3);
3561                 reg &= ~DSPFW_CURSOR_SR_MASK;
3562                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3563                 I915_WRITE(DSPFW3, reg);
3564
3565                 /* Display HPLL off SR */
3566                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3567                                         pineview_display_hplloff_wm.fifo_size,
3568                                         pixel_size, latency->display_hpll_disable);
3569                 reg = I915_READ(DSPFW3);
3570                 reg &= ~DSPFW_HPLL_SR_MASK;
3571                 reg |= wm & DSPFW_HPLL_SR_MASK;
3572                 I915_WRITE(DSPFW3, reg);
3573
3574                 /* cursor HPLL off SR */
3575                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3576                                         pineview_display_hplloff_wm.fifo_size,
3577                                         pixel_size, latency->cursor_hpll_disable);
3578                 reg = I915_READ(DSPFW3);
3579                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3580                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3581                 I915_WRITE(DSPFW3, reg);
3582                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3583
3584                 /* activate cxsr */
3585                 I915_WRITE(DSPFW3,
3586                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3587                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3588         } else {
3589                 pineview_disable_cxsr(dev);
3590                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3591         }
3592 }
3593
3594 static bool g4x_compute_wm0(struct drm_device *dev,
3595                             int plane,
3596                             const struct intel_watermark_params *display,
3597                             int display_latency_ns,
3598                             const struct intel_watermark_params *cursor,
3599                             int cursor_latency_ns,
3600                             int *plane_wm,
3601                             int *cursor_wm)
3602 {
3603         struct drm_crtc *crtc;
3604         int htotal, hdisplay, clock, pixel_size;
3605         int line_time_us, line_count;
3606         int entries, tlb_miss;
3607
3608         crtc = intel_get_crtc_for_plane(dev, plane);
3609         if (crtc->fb == NULL || !crtc->enabled) {
3610                 *cursor_wm = cursor->guard_size;
3611                 *plane_wm = display->guard_size;
3612                 return false;
3613         }
3614
3615         htotal = crtc->mode.htotal;
3616         hdisplay = crtc->mode.hdisplay;
3617         clock = crtc->mode.clock;
3618         pixel_size = crtc->fb->bits_per_pixel / 8;
3619
3620         /* Use the small buffer method to calculate plane watermark */
3621         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3622         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3623         if (tlb_miss > 0)
3624                 entries += tlb_miss;
3625         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3626         *plane_wm = entries + display->guard_size;
3627         if (*plane_wm > (int)display->max_wm)
3628                 *plane_wm = display->max_wm;
3629
3630         /* Use the large buffer method to calculate cursor watermark */
3631         line_time_us = ((htotal * 1000) / clock);
3632         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3633         entries = line_count * 64 * pixel_size;
3634         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3635         if (tlb_miss > 0)
3636                 entries += tlb_miss;
3637         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3638         *cursor_wm = entries + cursor->guard_size;
3639         if (*cursor_wm > (int)cursor->max_wm)
3640                 *cursor_wm = (int)cursor->max_wm;
3641
3642         return true;
3643 }
3644
3645 /*
3646  * Check the wm result.
3647  *
3648  * If any calculated watermark values is larger than the maximum value that
3649  * can be programmed into the associated watermark register, that watermark
3650  * must be disabled.
3651  */
3652 static bool g4x_check_srwm(struct drm_device *dev,
3653                            int display_wm, int cursor_wm,
3654                            const struct intel_watermark_params *display,
3655                            const struct intel_watermark_params *cursor)
3656 {
3657         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3658                       display_wm, cursor_wm);
3659
3660         if (display_wm > display->max_wm) {
3661                 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
3662                               display_wm, display->max_wm);
3663                 return false;
3664         }
3665
3666         if (cursor_wm > cursor->max_wm) {
3667                 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
3668                               cursor_wm, cursor->max_wm);
3669                 return false;
3670         }
3671
3672         if (!(display_wm || cursor_wm)) {
3673                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3674                 return false;
3675         }
3676
3677         return true;
3678 }
3679
3680 static bool g4x_compute_srwm(struct drm_device *dev,
3681                              int plane,
3682                              int latency_ns,
3683                              const struct intel_watermark_params *display,
3684                              const struct intel_watermark_params *cursor,
3685                              int *display_wm, int *cursor_wm)
3686 {
3687         struct drm_crtc *crtc;
3688         int hdisplay, htotal, pixel_size, clock;
3689         unsigned long line_time_us;
3690         int line_count, line_size;
3691         int small, large;
3692         int entries;
3693
3694         if (!latency_ns) {
3695                 *display_wm = *cursor_wm = 0;
3696                 return false;
3697         }
3698
3699         crtc = intel_get_crtc_for_plane(dev, plane);
3700         hdisplay = crtc->mode.hdisplay;
3701         htotal = crtc->mode.htotal;
3702         clock = crtc->mode.clock;
3703         pixel_size = crtc->fb->bits_per_pixel / 8;
3704
3705         line_time_us = (htotal * 1000) / clock;
3706         line_count = (latency_ns / line_time_us + 1000) / 1000;
3707         line_size = hdisplay * pixel_size;
3708
3709         /* Use the minimum of the small and large buffer method for primary */
3710         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3711         large = line_count * line_size;
3712
3713         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3714         *display_wm = entries + display->guard_size;
3715
3716         /* calculate the self-refresh watermark for display cursor */
3717         entries = line_count * pixel_size * 64;
3718         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3719         *cursor_wm = entries + cursor->guard_size;
3720
3721         return g4x_check_srwm(dev,
3722                               *display_wm, *cursor_wm,
3723                               display, cursor);
3724 }
3725
3726 #define single_plane_enabled(mask) is_power_of_2(mask)
3727
3728 static void g4x_update_wm(struct drm_device *dev)
3729 {
3730         static const int sr_latency_ns = 12000;
3731         struct drm_i915_private *dev_priv = dev->dev_private;
3732         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3733         int plane_sr, cursor_sr;
3734         unsigned int enabled = 0;
3735
3736         if (g4x_compute_wm0(dev, 0,
3737                             &g4x_wm_info, latency_ns,
3738                             &g4x_cursor_wm_info, latency_ns,
3739                             &planea_wm, &cursora_wm))
3740                 enabled |= 1;
3741
3742         if (g4x_compute_wm0(dev, 1,
3743                             &g4x_wm_info, latency_ns,
3744                             &g4x_cursor_wm_info, latency_ns,
3745                             &planeb_wm, &cursorb_wm))
3746                 enabled |= 2;
3747
3748         plane_sr = cursor_sr = 0;
3749         if (single_plane_enabled(enabled) &&
3750             g4x_compute_srwm(dev, ffs(enabled) - 1,
3751                              sr_latency_ns,
3752                              &g4x_wm_info,
3753                              &g4x_cursor_wm_info,
3754                              &plane_sr, &cursor_sr))
3755                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3756         else
3757                 I915_WRITE(FW_BLC_SELF,
3758                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3759
3760         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3761                       planea_wm, cursora_wm,
3762                       planeb_wm, cursorb_wm,
3763                       plane_sr, cursor_sr);
3764
3765         I915_WRITE(DSPFW1,
3766                    (plane_sr << DSPFW_SR_SHIFT) |
3767                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3768                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
3769                    planea_wm);
3770         I915_WRITE(DSPFW2,
3771                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3772                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3773         /* HPLL off in SR has some issues on G4x... disable it */
3774         I915_WRITE(DSPFW3,
3775                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3776                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3777 }
3778
3779 static void i965_update_wm(struct drm_device *dev)
3780 {
3781         struct drm_i915_private *dev_priv = dev->dev_private;
3782         struct drm_crtc *crtc;
3783         int srwm = 1;
3784         int cursor_sr = 16;
3785
3786         /* Calc sr entries for one plane configs */
3787         crtc = single_enabled_crtc(dev);
3788         if (crtc) {
3789                 /* self-refresh has much higher latency */
3790                 static const int sr_latency_ns = 12000;
3791                 int clock = crtc->mode.clock;
3792                 int htotal = crtc->mode.htotal;
3793                 int hdisplay = crtc->mode.hdisplay;
3794                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3795                 unsigned long line_time_us;
3796                 int entries;
3797
3798                 line_time_us = ((htotal * 1000) / clock);
3799
3800                 /* Use ns/us then divide to preserve precision */
3801                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3802                         pixel_size * hdisplay;
3803                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3804                 srwm = I965_FIFO_SIZE - entries;
3805                 if (srwm < 0)
3806                         srwm = 1;
3807                 srwm &= 0x1ff;
3808                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3809                               entries, srwm);
3810
3811                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3812                         pixel_size * 64;
3813                 entries = DIV_ROUND_UP(entries,
3814                                           i965_cursor_wm_info.cacheline_size);
3815                 cursor_sr = i965_cursor_wm_info.fifo_size -
3816                         (entries + i965_cursor_wm_info.guard_size);
3817
3818                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3819                         cursor_sr = i965_cursor_wm_info.max_wm;
3820
3821                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3822                               "cursor %d\n", srwm, cursor_sr);
3823
3824                 if (IS_CRESTLINE(dev))
3825                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3826         } else {
3827                 /* Turn off self refresh if both pipes are enabled */
3828                 if (IS_CRESTLINE(dev))
3829                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3830                                    & ~FW_BLC_SELF_EN);
3831         }
3832
3833         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3834                       srwm);
3835
3836         /* 965 has limitations... */
3837         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3838                    (8 << 16) | (8 << 8) | (8 << 0));
3839         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3840         /* update cursor SR watermark */
3841         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3842 }
3843
3844 static void i9xx_update_wm(struct drm_device *dev)
3845 {
3846         struct drm_i915_private *dev_priv = dev->dev_private;
3847         const struct intel_watermark_params *wm_info;
3848         uint32_t fwater_lo;
3849         uint32_t fwater_hi;
3850         int cwm, srwm = 1;
3851         int fifo_size;
3852         int planea_wm, planeb_wm;
3853         struct drm_crtc *crtc, *enabled = NULL;
3854
3855         if (IS_I945GM(dev))
3856                 wm_info = &i945_wm_info;
3857         else if (!IS_GEN2(dev))
3858                 wm_info = &i915_wm_info;
3859         else
3860                 wm_info = &i855_wm_info;
3861
3862         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3863         crtc = intel_get_crtc_for_plane(dev, 0);
3864         if (crtc->enabled && crtc->fb) {
3865                 planea_wm = intel_calculate_wm(crtc->mode.clock,
3866                                                wm_info, fifo_size,
3867                                                crtc->fb->bits_per_pixel / 8,
3868                                                latency_ns);
3869                 enabled = crtc;
3870         } else
3871                 planea_wm = fifo_size - wm_info->guard_size;
3872
3873         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3874         crtc = intel_get_crtc_for_plane(dev, 1);
3875         if (crtc->enabled && crtc->fb) {
3876                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3877                                                wm_info, fifo_size,
3878                                                crtc->fb->bits_per_pixel / 8,
3879                                                latency_ns);
3880                 if (enabled == NULL)
3881                         enabled = crtc;
3882                 else
3883                         enabled = NULL;
3884         } else
3885                 planeb_wm = fifo_size - wm_info->guard_size;
3886
3887         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3888
3889         /*
3890          * Overlay gets an aggressive default since video jitter is bad.
3891          */
3892         cwm = 2;
3893
3894         /* Play safe and disable self-refresh before adjusting watermarks. */
3895         if (IS_I945G(dev) || IS_I945GM(dev))
3896                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3897         else if (IS_I915GM(dev))
3898                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3899
3900         /* Calc sr entries for one plane configs */
3901         if (HAS_FW_BLC(dev) && enabled) {
3902                 /* self-refresh has much higher latency */
3903                 static const int sr_latency_ns = 6000;
3904                 int clock = enabled->mode.clock;
3905                 int htotal = enabled->mode.htotal;
3906                 int hdisplay = enabled->mode.hdisplay;
3907                 int pixel_size = enabled->fb->bits_per_pixel / 8;
3908                 unsigned long line_time_us;
3909                 int entries;
3910
3911                 line_time_us = (htotal * 1000) / clock;
3912
3913                 /* Use ns/us then divide to preserve precision */
3914                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3915                         pixel_size * hdisplay;
3916                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3917                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3918                 srwm = wm_info->fifo_size - entries;
3919                 if (srwm < 0)
3920                         srwm = 1;
3921
3922                 if (IS_I945G(dev) || IS_I945GM(dev))
3923                         I915_WRITE(FW_BLC_SELF,
3924                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3925                 else if (IS_I915GM(dev))
3926                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3927         }
3928
3929         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3930                       planea_wm, planeb_wm, cwm, srwm);
3931
3932         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3933         fwater_hi = (cwm & 0x1f);
3934
3935         /* Set request length to 8 cachelines per fetch */
3936         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3937         fwater_hi = fwater_hi | (1 << 8);
3938
3939         I915_WRITE(FW_BLC, fwater_lo);
3940         I915_WRITE(FW_BLC2, fwater_hi);
3941
3942         if (HAS_FW_BLC(dev)) {
3943                 if (enabled) {
3944                         if (IS_I945G(dev) || IS_I945GM(dev))
3945                                 I915_WRITE(FW_BLC_SELF,
3946                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3947                         else if (IS_I915GM(dev))
3948                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3949                         DRM_DEBUG_KMS("memory self refresh enabled\n");
3950                 } else
3951                         DRM_DEBUG_KMS("memory self refresh disabled\n");
3952         }
3953 }
3954
3955 static void i830_update_wm(struct drm_device *dev)
3956 {
3957         struct drm_i915_private *dev_priv = dev->dev_private;
3958         struct drm_crtc *crtc;
3959         uint32_t fwater_lo;
3960         int planea_wm;
3961
3962         crtc = single_enabled_crtc(dev);
3963         if (crtc == NULL)
3964                 return;
3965
3966         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3967                                        dev_priv->display.get_fifo_size(dev, 0),
3968                                        crtc->fb->bits_per_pixel / 8,
3969                                        latency_ns);
3970         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3971         fwater_lo |= (3<<8) | planea_wm;
3972
3973         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3974
3975         I915_WRITE(FW_BLC, fwater_lo);
3976 }
3977
3978 #define ILK_LP0_PLANE_LATENCY           700
3979 #define ILK_LP0_CURSOR_LATENCY          1300
3980
3981 static bool ironlake_compute_wm0(struct drm_device *dev,
3982                                  int pipe,
3983                                  const struct intel_watermark_params *display,
3984                                  int display_latency_ns,
3985                                  const struct intel_watermark_params *cursor,
3986                                  int cursor_latency_ns,
3987                                  int *plane_wm,
3988                                  int *cursor_wm)
3989 {
3990         struct drm_crtc *crtc;
3991         int htotal, hdisplay, clock, pixel_size;
3992         int line_time_us, line_count;
3993         int entries, tlb_miss;
3994
3995         crtc = intel_get_crtc_for_pipe(dev, pipe);
3996         if (crtc->fb == NULL || !crtc->enabled)
3997                 return false;
3998
3999         htotal = crtc->mode.htotal;
4000         hdisplay = crtc->mode.hdisplay;
4001         clock = crtc->mode.clock;
4002         pixel_size = crtc->fb->bits_per_pixel / 8;
4003
4004         /* Use the small buffer method to calculate plane watermark */
4005         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4006         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4007         if (tlb_miss > 0)
4008                 entries += tlb_miss;
4009         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4010         *plane_wm = entries + display->guard_size;
4011         if (*plane_wm > (int)display->max_wm)
4012                 *plane_wm = display->max_wm;
4013
4014         /* Use the large buffer method to calculate cursor watermark */
4015         line_time_us = ((htotal * 1000) / clock);
4016         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4017         entries = line_count * 64 * pixel_size;
4018         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4019         if (tlb_miss > 0)
4020                 entries += tlb_miss;
4021         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4022         *cursor_wm = entries + cursor->guard_size;
4023         if (*cursor_wm > (int)cursor->max_wm)
4024                 *cursor_wm = (int)cursor->max_wm;
4025
4026         return true;
4027 }
4028
4029 /*
4030  * Check the wm result.
4031  *
4032  * If any calculated watermark values is larger than the maximum value that
4033  * can be programmed into the associated watermark register, that watermark
4034  * must be disabled.
4035  */
4036 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4037                                 int fbc_wm, int display_wm, int cursor_wm,
4038                                 const struct intel_watermark_params *display,
4039                                 const struct intel_watermark_params *cursor)
4040 {
4041         struct drm_i915_private *dev_priv = dev->dev_private;
4042
4043         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4044                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4045
4046         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4047                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4048                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4049
4050                 /* fbc has it's own way to disable FBC WM */
4051                 I915_WRITE(DISP_ARB_CTL,
4052                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4053                 return false;
4054         }
4055
4056         if (display_wm > display->max_wm) {
4057                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4058                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4059                 return false;
4060         }
4061
4062         if (cursor_wm > cursor->max_wm) {
4063                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4064                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4065                 return false;
4066         }
4067
4068         if (!(fbc_wm || display_wm || cursor_wm)) {
4069                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4070                 return false;
4071         }
4072
4073         return true;
4074 }
4075
4076 /*
4077  * Compute watermark values of WM[1-3],
4078  */
4079 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4080                                   int latency_ns,
4081                                   const struct intel_watermark_params *display,
4082                                   const struct intel_watermark_params *cursor,
4083                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4084 {
4085         struct drm_crtc *crtc;
4086         unsigned long line_time_us;
4087         int hdisplay, htotal, pixel_size, clock;
4088         int line_count, line_size;
4089         int small, large;
4090         int entries;
4091
4092         if (!latency_ns) {
4093                 *fbc_wm = *display_wm = *cursor_wm = 0;
4094                 return false;
4095         }
4096
4097         crtc = intel_get_crtc_for_plane(dev, plane);
4098         hdisplay = crtc->mode.hdisplay;
4099         htotal = crtc->mode.htotal;
4100         clock = crtc->mode.clock;
4101         pixel_size = crtc->fb->bits_per_pixel / 8;
4102
4103         line_time_us = (htotal * 1000) / clock;
4104         line_count = (latency_ns / line_time_us + 1000) / 1000;
4105         line_size = hdisplay * pixel_size;
4106
4107         /* Use the minimum of the small and large buffer method for primary */
4108         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4109         large = line_count * line_size;
4110
4111         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4112         *display_wm = entries + display->guard_size;
4113
4114         /*
4115          * Spec says:
4116          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4117          */
4118         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4119
4120         /* calculate the self-refresh watermark for display cursor */
4121         entries = line_count * pixel_size * 64;
4122         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4123         *cursor_wm = entries + cursor->guard_size;
4124
4125         return ironlake_check_srwm(dev, level,
4126                                    *fbc_wm, *display_wm, *cursor_wm,
4127                                    display, cursor);
4128 }
4129
4130 static void ironlake_update_wm(struct drm_device *dev)
4131 {
4132         struct drm_i915_private *dev_priv = dev->dev_private;
4133         int fbc_wm, plane_wm, cursor_wm;
4134         unsigned int enabled;
4135
4136         enabled = 0;
4137         if (ironlake_compute_wm0(dev, 0,
4138                                  &ironlake_display_wm_info,
4139                                  ILK_LP0_PLANE_LATENCY,
4140                                  &ironlake_cursor_wm_info,
4141                                  ILK_LP0_CURSOR_LATENCY,
4142                                  &plane_wm, &cursor_wm)) {
4143                 I915_WRITE(WM0_PIPEA_ILK,
4144                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4145                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4146                               " plane %d, " "cursor: %d\n",
4147                               plane_wm, cursor_wm);
4148                 enabled |= 1;
4149         }
4150
4151         if (ironlake_compute_wm0(dev, 1,
4152                                  &ironlake_display_wm_info,
4153                                  ILK_LP0_PLANE_LATENCY,
4154                                  &ironlake_cursor_wm_info,
4155                                  ILK_LP0_CURSOR_LATENCY,
4156                                  &plane_wm, &cursor_wm)) {
4157                 I915_WRITE(WM0_PIPEB_ILK,
4158                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4159                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4160                               " plane %d, cursor: %d\n",
4161                               plane_wm, cursor_wm);
4162                 enabled |= 2;
4163         }
4164
4165         /*
4166          * Calculate and update the self-refresh watermark only when one
4167          * display plane is used.
4168          */
4169         I915_WRITE(WM3_LP_ILK, 0);
4170         I915_WRITE(WM2_LP_ILK, 0);
4171         I915_WRITE(WM1_LP_ILK, 0);
4172
4173         if (!single_plane_enabled(enabled))
4174                 return;
4175         enabled = ffs(enabled) - 1;
4176
4177         /* WM1 */
4178         if (!ironlake_compute_srwm(dev, 1, enabled,
4179                                    ILK_READ_WM1_LATENCY() * 500,
4180                                    &ironlake_display_srwm_info,
4181                                    &ironlake_cursor_srwm_info,
4182                                    &fbc_wm, &plane_wm, &cursor_wm))
4183                 return;
4184
4185         I915_WRITE(WM1_LP_ILK,
4186                    WM1_LP_SR_EN |
4187                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4188                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4189                    (plane_wm << WM1_LP_SR_SHIFT) |
4190                    cursor_wm);
4191
4192         /* WM2 */
4193         if (!ironlake_compute_srwm(dev, 2, enabled,
4194                                    ILK_READ_WM2_LATENCY() * 500,
4195                                    &ironlake_display_srwm_info,
4196                                    &ironlake_cursor_srwm_info,
4197                                    &fbc_wm, &plane_wm, &cursor_wm))
4198                 return;
4199
4200         I915_WRITE(WM2_LP_ILK,
4201                    WM2_LP_EN |
4202                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4203                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4204                    (plane_wm << WM1_LP_SR_SHIFT) |
4205                    cursor_wm);
4206
4207         /*
4208          * WM3 is unsupported on ILK, probably because we don't have latency
4209          * data for that power state
4210          */
4211 }
4212
4213 static void sandybridge_update_wm(struct drm_device *dev)
4214 {
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4217         int fbc_wm, plane_wm, cursor_wm;
4218         unsigned int enabled;
4219
4220         enabled = 0;
4221         if (ironlake_compute_wm0(dev, 0,
4222                                  &sandybridge_display_wm_info, latency,
4223                                  &sandybridge_cursor_wm_info, latency,
4224                                  &plane_wm, &cursor_wm)) {
4225                 I915_WRITE(WM0_PIPEA_ILK,
4226                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4227                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4228                               " plane %d, " "cursor: %d\n",
4229                               plane_wm, cursor_wm);
4230                 enabled |= 1;
4231         }
4232
4233         if (ironlake_compute_wm0(dev, 1,
4234                                  &sandybridge_display_wm_info, latency,
4235                                  &sandybridge_cursor_wm_info, latency,
4236                                  &plane_wm, &cursor_wm)) {
4237                 I915_WRITE(WM0_PIPEB_ILK,
4238                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4239                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4240                               " plane %d, cursor: %d\n",
4241                               plane_wm, cursor_wm);
4242                 enabled |= 2;
4243         }
4244
4245         /*
4246          * Calculate and update the self-refresh watermark only when one
4247          * display plane is used.
4248          *
4249          * SNB support 3 levels of watermark.
4250          *
4251          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4252          * and disabled in the descending order
4253          *
4254          */
4255         I915_WRITE(WM3_LP_ILK, 0);
4256         I915_WRITE(WM2_LP_ILK, 0);
4257         I915_WRITE(WM1_LP_ILK, 0);
4258
4259         if (!single_plane_enabled(enabled))
4260                 return;
4261         enabled = ffs(enabled) - 1;
4262
4263         /* WM1 */
4264         if (!ironlake_compute_srwm(dev, 1, enabled,
4265                                    SNB_READ_WM1_LATENCY() * 500,
4266                                    &sandybridge_display_srwm_info,
4267                                    &sandybridge_cursor_srwm_info,
4268                                    &fbc_wm, &plane_wm, &cursor_wm))
4269                 return;
4270
4271         I915_WRITE(WM1_LP_ILK,
4272                    WM1_LP_SR_EN |
4273                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4274                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4275                    (plane_wm << WM1_LP_SR_SHIFT) |
4276                    cursor_wm);
4277
4278         /* WM2 */
4279         if (!ironlake_compute_srwm(dev, 2, enabled,
4280                                    SNB_READ_WM2_LATENCY() * 500,
4281                                    &sandybridge_display_srwm_info,
4282                                    &sandybridge_cursor_srwm_info,
4283                                    &fbc_wm, &plane_wm, &cursor_wm))
4284                 return;
4285
4286         I915_WRITE(WM2_LP_ILK,
4287                    WM2_LP_EN |
4288                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4289                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4290                    (plane_wm << WM1_LP_SR_SHIFT) |
4291                    cursor_wm);
4292
4293         /* WM3 */
4294         if (!ironlake_compute_srwm(dev, 3, enabled,
4295                                    SNB_READ_WM3_LATENCY() * 500,
4296                                    &sandybridge_display_srwm_info,
4297                                    &sandybridge_cursor_srwm_info,
4298                                    &fbc_wm, &plane_wm, &cursor_wm))
4299                 return;
4300
4301         I915_WRITE(WM3_LP_ILK,
4302                    WM3_LP_EN |
4303                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4304                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4305                    (plane_wm << WM1_LP_SR_SHIFT) |
4306                    cursor_wm);
4307 }
4308
4309 /**
4310  * intel_update_watermarks - update FIFO watermark values based on current modes
4311  *
4312  * Calculate watermark values for the various WM regs based on current mode
4313  * and plane configuration.
4314  *
4315  * There are several cases to deal with here:
4316  *   - normal (i.e. non-self-refresh)
4317  *   - self-refresh (SR) mode
4318  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4319  *   - lines are small relative to FIFO size (buffer can hold more than 2
4320  *     lines), so need to account for TLB latency
4321  *
4322  *   The normal calculation is:
4323  *     watermark = dotclock * bytes per pixel * latency
4324  *   where latency is platform & configuration dependent (we assume pessimal
4325  *   values here).
4326  *
4327  *   The SR calculation is:
4328  *     watermark = (trunc(latency/line time)+1) * surface width *
4329  *       bytes per pixel
4330  *   where
4331  *     line time = htotal / dotclock
4332  *     surface width = hdisplay for normal plane and 64 for cursor
4333  *   and latency is assumed to be high, as above.
4334  *
4335  * The final value programmed to the register should always be rounded up,
4336  * and include an extra 2 entries to account for clock crossings.
4337  *
4338  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4339  * to set the non-SR watermarks to 8.
4340  */
4341 static void intel_update_watermarks(struct drm_device *dev)
4342 {
4343         struct drm_i915_private *dev_priv = dev->dev_private;
4344
4345         if (dev_priv->display.update_wm)
4346                 dev_priv->display.update_wm(dev);
4347 }
4348
4349 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4350 {
4351         return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4352 }
4353
4354 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4355                               struct drm_display_mode *mode,
4356                               struct drm_display_mode *adjusted_mode,
4357                               int x, int y,
4358                               struct drm_framebuffer *old_fb)
4359 {
4360         struct drm_device *dev = crtc->dev;
4361         struct drm_i915_private *dev_priv = dev->dev_private;
4362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4363         int pipe = intel_crtc->pipe;
4364         int plane = intel_crtc->plane;
4365         int refclk, num_connectors = 0;
4366         intel_clock_t clock, reduced_clock;
4367         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4368         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4369         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4370         struct drm_mode_config *mode_config = &dev->mode_config;
4371         struct intel_encoder *encoder;
4372         const intel_limit_t *limit;
4373         int ret;
4374         u32 temp;
4375         u32 lvds_sync = 0;
4376
4377         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4378                 if (encoder->base.crtc != crtc)
4379                         continue;
4380
4381                 switch (encoder->type) {
4382                 case INTEL_OUTPUT_LVDS:
4383                         is_lvds = true;
4384                         break;
4385                 case INTEL_OUTPUT_SDVO:
4386                 case INTEL_OUTPUT_HDMI:
4387                         is_sdvo = true;
4388                         if (encoder->needs_tv_clock)
4389                                 is_tv = true;
4390                         break;
4391                 case INTEL_OUTPUT_DVO:
4392                         is_dvo = true;
4393                         break;
4394                 case INTEL_OUTPUT_TVOUT:
4395                         is_tv = true;
4396                         break;
4397                 case INTEL_OUTPUT_ANALOG:
4398                         is_crt = true;
4399                         break;
4400                 case INTEL_OUTPUT_DISPLAYPORT:
4401                         is_dp = true;
4402                         break;
4403                 }
4404
4405                 num_connectors++;
4406         }
4407
4408         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4409                 refclk = dev_priv->lvds_ssc_freq * 1000;
4410                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4411                               refclk / 1000);
4412         } else if (!IS_GEN2(dev)) {
4413                 refclk = 96000;
4414         } else {
4415                 refclk = 48000;
4416         }
4417
4418         /*
4419          * Returns a set of divisors for the desired target clock with the given
4420          * refclk, or FALSE.  The returned values represent the clock equation:
4421          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4422          */
4423         limit = intel_limit(crtc, refclk);
4424         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4425         if (!ok) {
4426                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4427                 return -EINVAL;
4428         }
4429
4430         /* Ensure that the cursor is valid for the new mode before changing... */
4431         intel_crtc_update_cursor(crtc, true);
4432
4433         if (is_lvds && dev_priv->lvds_downclock_avail) {
4434                 has_reduced_clock = limit->find_pll(limit, crtc,
4435                                                     dev_priv->lvds_downclock,
4436                                                     refclk,
4437                                                     &reduced_clock);
4438                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4439                         /*
4440                          * If the different P is found, it means that we can't
4441                          * switch the display clock by using the FP0/FP1.
4442                          * In such case we will disable the LVDS downclock
4443                          * feature.
4444                          */
4445                         DRM_DEBUG_KMS("Different P is found for "
4446                                       "LVDS clock/downclock\n");
4447                         has_reduced_clock = 0;
4448                 }
4449         }
4450         /* SDVO TV has fixed PLL values depend on its clock range,
4451            this mirrors vbios setting. */
4452         if (is_sdvo && is_tv) {
4453                 if (adjusted_mode->clock >= 100000
4454                     && adjusted_mode->clock < 140500) {
4455                         clock.p1 = 2;
4456                         clock.p2 = 10;
4457                         clock.n = 3;
4458                         clock.m1 = 16;
4459                         clock.m2 = 8;
4460                 } else if (adjusted_mode->clock >= 140500
4461                            && adjusted_mode->clock <= 200000) {
4462                         clock.p1 = 1;
4463                         clock.p2 = 10;
4464                         clock.n = 6;
4465                         clock.m1 = 12;
4466                         clock.m2 = 8;
4467                 }
4468         }
4469
4470         if (IS_PINEVIEW(dev)) {
4471                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4472                 if (has_reduced_clock)
4473                         fp2 = (1 << reduced_clock.n) << 16 |
4474                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4475         } else {
4476                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4477                 if (has_reduced_clock)
4478                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4479                                 reduced_clock.m2;
4480         }
4481
4482         dpll = DPLL_VGA_MODE_DIS;
4483
4484         if (!IS_GEN2(dev)) {
4485                 if (is_lvds)
4486                         dpll |= DPLLB_MODE_LVDS;
4487                 else
4488                         dpll |= DPLLB_MODE_DAC_SERIAL;
4489                 if (is_sdvo) {
4490                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4491                         if (pixel_multiplier > 1) {
4492                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4493                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4494                         }
4495                         dpll |= DPLL_DVO_HIGH_SPEED;
4496                 }
4497                 if (is_dp)
4498                         dpll |= DPLL_DVO_HIGH_SPEED;
4499
4500                 /* compute bitmask from p1 value */
4501                 if (IS_PINEVIEW(dev))
4502                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4503                 else {
4504                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4505                         if (IS_G4X(dev) && has_reduced_clock)
4506                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4507                 }
4508                 switch (clock.p2) {
4509                 case 5:
4510                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4511                         break;
4512                 case 7:
4513                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4514                         break;
4515                 case 10:
4516                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4517                         break;
4518                 case 14:
4519                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4520                         break;
4521                 }
4522                 if (INTEL_INFO(dev)->gen >= 4)
4523                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4524         } else {
4525                 if (is_lvds) {
4526                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4527                 } else {
4528                         if (clock.p1 == 2)
4529                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4530                         else
4531                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4532                         if (clock.p2 == 4)
4533                                 dpll |= PLL_P2_DIVIDE_BY_4;
4534                 }
4535         }
4536
4537         if (is_sdvo && is_tv)
4538                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4539         else if (is_tv)
4540                 /* XXX: just matching BIOS for now */
4541                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4542                 dpll |= 3;
4543         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4544                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4545         else
4546                 dpll |= PLL_REF_INPUT_DREFCLK;
4547
4548         /* setup pipeconf */
4549         pipeconf = I915_READ(PIPECONF(pipe));
4550
4551         /* Set up the display plane register */
4552         dspcntr = DISPPLANE_GAMMA_ENABLE;
4553
4554         /* Ironlake's plane is forced to pipe, bit 24 is to
4555            enable color space conversion */
4556         if (pipe == 0)
4557                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4558         else
4559                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4560
4561         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4562                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4563                  * core speed.
4564                  *
4565                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4566                  * pipe == 0 check?
4567                  */
4568                 if (mode->clock >
4569                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4570                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4571                 else
4572                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4573         }
4574
4575         dpll |= DPLL_VCO_ENABLE;
4576
4577         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4578         drm_mode_debug_printmodeline(mode);
4579
4580         I915_WRITE(FP0(pipe), fp);
4581         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4582
4583         POSTING_READ(DPLL(pipe));
4584         udelay(150);
4585
4586         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4587          * This is an exception to the general rule that mode_set doesn't turn
4588          * things on.
4589          */
4590         if (is_lvds) {
4591                 temp = I915_READ(LVDS);
4592                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4593                 if (pipe == 1) {
4594                         temp |= LVDS_PIPEB_SELECT;
4595                 } else {
4596                         temp &= ~LVDS_PIPEB_SELECT;
4597                 }
4598                 /* set the corresponsding LVDS_BORDER bit */
4599                 temp |= dev_priv->lvds_border_bits;
4600                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4601                  * set the DPLLs for dual-channel mode or not.
4602                  */
4603                 if (clock.p2 == 7)
4604                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4605                 else
4606                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4607
4608                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4609                  * appropriately here, but we need to look more thoroughly into how
4610                  * panels behave in the two modes.
4611                  */
4612                 /* set the dithering flag on LVDS as needed */
4613                 if (INTEL_INFO(dev)->gen >= 4) {
4614                         if (dev_priv->lvds_dither)
4615                                 temp |= LVDS_ENABLE_DITHER;
4616                         else
4617                                 temp &= ~LVDS_ENABLE_DITHER;
4618                 }
4619                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4620                         lvds_sync |= LVDS_HSYNC_POLARITY;
4621                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4622                         lvds_sync |= LVDS_VSYNC_POLARITY;
4623                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4624                     != lvds_sync) {
4625                         char flags[2] = "-+";
4626                         DRM_INFO("Changing LVDS panel from "
4627                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4628                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
4629                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
4630                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4631                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4632                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4633                         temp |= lvds_sync;
4634                 }
4635                 I915_WRITE(LVDS, temp);
4636         }
4637
4638         if (is_dp) {
4639                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4640         }
4641
4642         I915_WRITE(DPLL(pipe), dpll);
4643
4644         /* Wait for the clocks to stabilize. */
4645         POSTING_READ(DPLL(pipe));
4646         udelay(150);
4647
4648         if (INTEL_INFO(dev)->gen >= 4) {
4649                 temp = 0;
4650                 if (is_sdvo) {
4651                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4652                         if (temp > 1)
4653                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4654                         else
4655                                 temp = 0;
4656                 }
4657                 I915_WRITE(DPLL_MD(pipe), temp);
4658         } else {
4659                 /* The pixel multiplier can only be updated once the
4660                  * DPLL is enabled and the clocks are stable.
4661                  *
4662                  * So write it again.
4663                  */
4664                 I915_WRITE(DPLL(pipe), dpll);
4665         }
4666
4667         intel_crtc->lowfreq_avail = false;
4668         if (is_lvds && has_reduced_clock && i915_powersave) {
4669                 I915_WRITE(FP1(pipe), fp2);
4670                 intel_crtc->lowfreq_avail = true;
4671                 if (HAS_PIPE_CXSR(dev)) {
4672                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4673                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4674                 }
4675         } else {
4676                 I915_WRITE(FP1(pipe), fp);
4677                 if (HAS_PIPE_CXSR(dev)) {
4678                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4679                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4680                 }
4681         }
4682
4683         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4684                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4685                 /* the chip adds 2 halflines automatically */
4686                 adjusted_mode->crtc_vdisplay -= 1;
4687                 adjusted_mode->crtc_vtotal -= 1;
4688                 adjusted_mode->crtc_vblank_start -= 1;
4689                 adjusted_mode->crtc_vblank_end -= 1;
4690                 adjusted_mode->crtc_vsync_end -= 1;
4691                 adjusted_mode->crtc_vsync_start -= 1;
4692         } else
4693                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4694
4695         I915_WRITE(HTOTAL(pipe),
4696                    (adjusted_mode->crtc_hdisplay - 1) |
4697                    ((adjusted_mode->crtc_htotal - 1) << 16));
4698         I915_WRITE(HBLANK(pipe),
4699                    (adjusted_mode->crtc_hblank_start - 1) |
4700                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4701         I915_WRITE(HSYNC(pipe),
4702                    (adjusted_mode->crtc_hsync_start - 1) |
4703                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4704
4705         I915_WRITE(VTOTAL(pipe),
4706                    (adjusted_mode->crtc_vdisplay - 1) |
4707                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4708         I915_WRITE(VBLANK(pipe),
4709                    (adjusted_mode->crtc_vblank_start - 1) |
4710                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4711         I915_WRITE(VSYNC(pipe),
4712                    (adjusted_mode->crtc_vsync_start - 1) |
4713                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4714
4715         /* pipesrc and dspsize control the size that is scaled from,
4716          * which should always be the user's requested size.
4717          */
4718         I915_WRITE(DSPSIZE(plane),
4719                    ((mode->vdisplay - 1) << 16) |
4720                    (mode->hdisplay - 1));
4721         I915_WRITE(DSPPOS(plane), 0);
4722         I915_WRITE(PIPESRC(pipe),
4723                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4724
4725         I915_WRITE(PIPECONF(pipe), pipeconf);
4726         POSTING_READ(PIPECONF(pipe));
4727         intel_enable_pipe(dev_priv, pipe, false);
4728
4729         intel_wait_for_vblank(dev, pipe);
4730
4731         I915_WRITE(DSPCNTR(plane), dspcntr);
4732         POSTING_READ(DSPCNTR(plane));
4733
4734         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4735
4736         intel_update_watermarks(dev);
4737
4738         return ret;
4739 }
4740
4741 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4742                                   struct drm_display_mode *mode,
4743                                   struct drm_display_mode *adjusted_mode,
4744                                   int x, int y,
4745                                   struct drm_framebuffer *old_fb)
4746 {
4747         struct drm_device *dev = crtc->dev;
4748         struct drm_i915_private *dev_priv = dev->dev_private;
4749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4750         int pipe = intel_crtc->pipe;
4751         int plane = intel_crtc->plane;
4752         int refclk, num_connectors = 0;
4753         intel_clock_t clock, reduced_clock;
4754         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4755         bool ok, has_reduced_clock = false, is_sdvo = false;
4756         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4757         struct intel_encoder *has_edp_encoder = NULL;
4758         struct drm_mode_config *mode_config = &dev->mode_config;
4759         struct intel_encoder *encoder;
4760         const intel_limit_t *limit;
4761         int ret;
4762         struct fdi_m_n m_n = {0};
4763         u32 temp;
4764         u32 lvds_sync = 0;
4765         int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
4766
4767         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4768                 if (encoder->base.crtc != crtc)
4769                         continue;
4770
4771                 switch (encoder->type) {
4772                 case INTEL_OUTPUT_LVDS:
4773                         is_lvds = true;
4774                         break;
4775                 case INTEL_OUTPUT_SDVO:
4776                 case INTEL_OUTPUT_HDMI:
4777                         is_sdvo = true;
4778                         if (encoder->needs_tv_clock)
4779                                 is_tv = true;
4780                         break;
4781                 case INTEL_OUTPUT_TVOUT:
4782                         is_tv = true;
4783                         break;
4784                 case INTEL_OUTPUT_ANALOG:
4785                         is_crt = true;
4786                         break;
4787                 case INTEL_OUTPUT_DISPLAYPORT:
4788                         is_dp = true;
4789                         break;
4790                 case INTEL_OUTPUT_EDP:
4791                         has_edp_encoder = encoder;
4792                         break;
4793                 }
4794
4795                 num_connectors++;
4796         }
4797
4798         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4799                 refclk = dev_priv->lvds_ssc_freq * 1000;
4800                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4801                               refclk / 1000);
4802         } else {
4803                 refclk = 96000;
4804                 if (!has_edp_encoder ||
4805                     intel_encoder_is_pch_edp(&has_edp_encoder->base))
4806                         refclk = 120000; /* 120Mhz refclk */
4807         }
4808
4809         /*
4810          * Returns a set of divisors for the desired target clock with the given
4811          * refclk, or FALSE.  The returned values represent the clock equation:
4812          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4813          */
4814         limit = intel_limit(crtc, refclk);
4815         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4816         if (!ok) {
4817                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4818                 return -EINVAL;
4819         }
4820
4821         /* Ensure that the cursor is valid for the new mode before changing... */
4822         intel_crtc_update_cursor(crtc, true);
4823
4824         if (is_lvds && dev_priv->lvds_downclock_avail) {
4825                 has_reduced_clock = limit->find_pll(limit, crtc,
4826                                                     dev_priv->lvds_downclock,
4827                                                     refclk,
4828                                                     &reduced_clock);
4829                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4830                         /*
4831                          * If the different P is found, it means that we can't
4832                          * switch the display clock by using the FP0/FP1.
4833                          * In such case we will disable the LVDS downclock
4834                          * feature.
4835                          */
4836                         DRM_DEBUG_KMS("Different P is found for "
4837                                       "LVDS clock/downclock\n");
4838                         has_reduced_clock = 0;
4839                 }
4840         }
4841         /* SDVO TV has fixed PLL values depend on its clock range,
4842            this mirrors vbios setting. */
4843         if (is_sdvo && is_tv) {
4844                 if (adjusted_mode->clock >= 100000
4845                     && adjusted_mode->clock < 140500) {
4846                         clock.p1 = 2;
4847                         clock.p2 = 10;
4848                         clock.n = 3;
4849                         clock.m1 = 16;
4850                         clock.m2 = 8;
4851                 } else if (adjusted_mode->clock >= 140500
4852                            && adjusted_mode->clock <= 200000) {
4853                         clock.p1 = 1;
4854                         clock.p2 = 10;
4855                         clock.n = 6;
4856                         clock.m1 = 12;
4857                         clock.m2 = 8;
4858                 }
4859         }
4860
4861         /* FDI link */
4862         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4863         lane = 0;
4864         /* CPU eDP doesn't require FDI link, so just set DP M/N
4865            according to current link config */
4866         if (has_edp_encoder &&
4867             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4868                 target_clock = mode->clock;
4869                 intel_edp_link_config(has_edp_encoder,
4870                                       &lane, &link_bw);
4871         } else {
4872                 /* [e]DP over FDI requires target mode clock
4873                    instead of link clock */
4874                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4875                         target_clock = mode->clock;
4876                 else
4877                         target_clock = adjusted_mode->clock;
4878
4879                 /* FDI is a binary signal running at ~2.7GHz, encoding
4880                  * each output octet as 10 bits. The actual frequency
4881                  * is stored as a divider into a 100MHz clock, and the
4882                  * mode pixel clock is stored in units of 1KHz.
4883                  * Hence the bw of each lane in terms of the mode signal
4884                  * is:
4885                  */
4886                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4887         }
4888
4889         /* determine panel color depth */
4890         temp = I915_READ(PIPECONF(pipe));
4891         temp &= ~PIPE_BPC_MASK;
4892         if (is_lvds) {
4893                 /* the BPC will be 6 if it is 18-bit LVDS panel */
4894                 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4895                         temp |= PIPE_8BPC;
4896                 else
4897                         temp |= PIPE_6BPC;
4898         } else if (has_edp_encoder) {
4899                 switch (dev_priv->edp.bpp/3) {
4900                 case 8:
4901                         temp |= PIPE_8BPC;
4902                         break;
4903                 case 10:
4904                         temp |= PIPE_10BPC;
4905                         break;
4906                 case 6:
4907                         temp |= PIPE_6BPC;
4908                         break;
4909                 case 12:
4910                         temp |= PIPE_12BPC;
4911                         break;
4912                 }
4913         } else
4914                 temp |= PIPE_8BPC;
4915         I915_WRITE(PIPECONF(pipe), temp);
4916
4917         switch (temp & PIPE_BPC_MASK) {
4918         case PIPE_8BPC:
4919                 bpp = 24;
4920                 break;
4921         case PIPE_10BPC:
4922                 bpp = 30;
4923                 break;
4924         case PIPE_6BPC:
4925                 bpp = 18;
4926                 break;
4927         case PIPE_12BPC:
4928                 bpp = 36;
4929                 break;
4930         default:
4931                 DRM_ERROR("unknown pipe bpc value\n");
4932                 bpp = 24;
4933         }
4934
4935         if (!lane) {
4936                 /*
4937                  * Account for spread spectrum to avoid
4938                  * oversubscribing the link. Max center spread
4939                  * is 2.5%; use 5% for safety's sake.
4940                  */
4941                 u32 bps = target_clock * bpp * 21 / 20;
4942                 lane = bps / (link_bw * 8) + 1;
4943         }
4944
4945         intel_crtc->fdi_lanes = lane;
4946
4947         if (pixel_multiplier > 1)
4948                 link_bw *= pixel_multiplier;
4949         ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4950
4951         /* Ironlake: try to setup display ref clock before DPLL
4952          * enabling. This is only under driver's control after
4953          * PCH B stepping, previous chipset stepping should be
4954          * ignoring this setting.
4955          */
4956         temp = I915_READ(PCH_DREF_CONTROL);
4957         /* Always enable nonspread source */
4958         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4959         temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4960         temp &= ~DREF_SSC_SOURCE_MASK;
4961         temp |= DREF_SSC_SOURCE_ENABLE;
4962         I915_WRITE(PCH_DREF_CONTROL, temp);
4963
4964         POSTING_READ(PCH_DREF_CONTROL);
4965         udelay(200);
4966
4967         if (has_edp_encoder) {
4968                 if (intel_panel_use_ssc(dev_priv)) {
4969                         temp |= DREF_SSC1_ENABLE;
4970                         I915_WRITE(PCH_DREF_CONTROL, temp);
4971
4972                         POSTING_READ(PCH_DREF_CONTROL);
4973                         udelay(200);
4974                 }
4975                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4976
4977                 /* Enable CPU source on CPU attached eDP */
4978                 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4979                         if (intel_panel_use_ssc(dev_priv))
4980                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4981                         else
4982                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4983                 } else {
4984                         /* Enable SSC on PCH eDP if needed */
4985                         if (intel_panel_use_ssc(dev_priv)) {
4986                                 DRM_ERROR("enabling SSC on PCH\n");
4987                                 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4988                         }
4989                 }
4990                 I915_WRITE(PCH_DREF_CONTROL, temp);
4991                 POSTING_READ(PCH_DREF_CONTROL);
4992                 udelay(200);
4993         }
4994
4995         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4996         if (has_reduced_clock)
4997                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4998                         reduced_clock.m2;
4999
5000         /* Enable autotuning of the PLL clock (if permissible) */
5001         factor = 21;
5002         if (is_lvds) {
5003                 if ((intel_panel_use_ssc(dev_priv) &&
5004                      dev_priv->lvds_ssc_freq == 100) ||
5005                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5006                         factor = 25;
5007         } else if (is_sdvo && is_tv)
5008                 factor = 20;
5009
5010         if (clock.m1 < factor * clock.n)
5011                 fp |= FP_CB_TUNE;
5012
5013         dpll = 0;
5014
5015         if (is_lvds)
5016                 dpll |= DPLLB_MODE_LVDS;
5017         else
5018                 dpll |= DPLLB_MODE_DAC_SERIAL;
5019         if (is_sdvo) {
5020                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5021                 if (pixel_multiplier > 1) {
5022                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5023                 }
5024                 dpll |= DPLL_DVO_HIGH_SPEED;
5025         }
5026         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5027                 dpll |= DPLL_DVO_HIGH_SPEED;
5028
5029         /* compute bitmask from p1 value */
5030         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5031         /* also FPA1 */
5032         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5033
5034         switch (clock.p2) {
5035         case 5:
5036                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5037                 break;
5038         case 7:
5039                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5040                 break;
5041         case 10:
5042                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5043                 break;
5044         case 14:
5045                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5046                 break;
5047         }
5048
5049         if (is_sdvo && is_tv)
5050                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5051         else if (is_tv)
5052                 /* XXX: just matching BIOS for now */
5053                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5054                 dpll |= 3;
5055         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5056                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5057         else
5058                 dpll |= PLL_REF_INPUT_DREFCLK;
5059
5060         /* setup pipeconf */
5061         pipeconf = I915_READ(PIPECONF(pipe));
5062
5063         /* Set up the display plane register */
5064         dspcntr = DISPPLANE_GAMMA_ENABLE;
5065
5066         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5067         drm_mode_debug_printmodeline(mode);
5068
5069         /* PCH eDP needs FDI, but CPU eDP does not */
5070         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5071                 I915_WRITE(PCH_FP0(pipe), fp);
5072                 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5073
5074                 POSTING_READ(PCH_DPLL(pipe));
5075                 udelay(150);
5076         }
5077
5078         /* enable transcoder DPLL */
5079         if (HAS_PCH_CPT(dev)) {
5080                 temp = I915_READ(PCH_DPLL_SEL);
5081                 switch (pipe) {
5082                 case 0:
5083                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5084                         break;
5085                 case 1:
5086                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5087                         break;
5088                 case 2:
5089                         /* FIXME: manage transcoder PLLs? */
5090                         temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5091                         break;
5092                 default:
5093                         BUG();
5094                 }
5095                 I915_WRITE(PCH_DPLL_SEL, temp);
5096
5097                 POSTING_READ(PCH_DPLL_SEL);
5098                 udelay(150);
5099         }
5100
5101         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5102          * This is an exception to the general rule that mode_set doesn't turn
5103          * things on.
5104          */
5105         if (is_lvds) {
5106                 temp = I915_READ(PCH_LVDS);
5107                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5108                 if (pipe == 1) {
5109                         if (HAS_PCH_CPT(dev))
5110                                 temp |= PORT_TRANS_B_SEL_CPT;
5111                         else
5112                                 temp |= LVDS_PIPEB_SELECT;
5113                 } else {
5114                         if (HAS_PCH_CPT(dev))
5115                                 temp &= ~PORT_TRANS_SEL_MASK;
5116                         else
5117                                 temp &= ~LVDS_PIPEB_SELECT;
5118                 }
5119                 /* set the corresponsding LVDS_BORDER bit */
5120                 temp |= dev_priv->lvds_border_bits;
5121                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5122                  * set the DPLLs for dual-channel mode or not.
5123                  */
5124                 if (clock.p2 == 7)
5125                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5126                 else
5127                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5128
5129                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5130                  * appropriately here, but we need to look more thoroughly into how
5131                  * panels behave in the two modes.
5132                  */
5133                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5134                         lvds_sync |= LVDS_HSYNC_POLARITY;
5135                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5136                         lvds_sync |= LVDS_VSYNC_POLARITY;
5137                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5138                     != lvds_sync) {
5139                         char flags[2] = "-+";
5140                         DRM_INFO("Changing LVDS panel from "
5141                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5142                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5143                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5144                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5145                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5146                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5147                         temp |= lvds_sync;
5148                 }
5149                 I915_WRITE(PCH_LVDS, temp);
5150         }
5151
5152         /* set the dithering flag and clear for anything other than a panel. */
5153         pipeconf &= ~PIPECONF_DITHER_EN;
5154         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5155         if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5156                 pipeconf |= PIPECONF_DITHER_EN;
5157                 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5158         }
5159
5160         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5161                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5162         } else {
5163                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5164                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5165                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5166                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5167                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5168         }
5169
5170         if (!has_edp_encoder ||
5171             intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5172                 I915_WRITE(PCH_DPLL(pipe), dpll);
5173
5174                 /* Wait for the clocks to stabilize. */
5175                 POSTING_READ(PCH_DPLL(pipe));
5176                 udelay(150);
5177
5178                 /* The pixel multiplier can only be updated once the
5179                  * DPLL is enabled and the clocks are stable.
5180                  *
5181                  * So write it again.
5182                  */
5183                 I915_WRITE(PCH_DPLL(pipe), dpll);
5184         }
5185
5186         intel_crtc->lowfreq_avail = false;
5187         if (is_lvds && has_reduced_clock && i915_powersave) {
5188                 I915_WRITE(PCH_FP1(pipe), fp2);
5189                 intel_crtc->lowfreq_avail = true;
5190                 if (HAS_PIPE_CXSR(dev)) {
5191                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5192                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5193                 }
5194         } else {
5195                 I915_WRITE(PCH_FP1(pipe), fp);
5196                 if (HAS_PIPE_CXSR(dev)) {
5197                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5198                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5199                 }
5200         }
5201
5202         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5203                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5204                 /* the chip adds 2 halflines automatically */
5205                 adjusted_mode->crtc_vdisplay -= 1;
5206                 adjusted_mode->crtc_vtotal -= 1;
5207                 adjusted_mode->crtc_vblank_start -= 1;
5208                 adjusted_mode->crtc_vblank_end -= 1;
5209                 adjusted_mode->crtc_vsync_end -= 1;
5210                 adjusted_mode->crtc_vsync_start -= 1;
5211         } else
5212                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5213
5214         I915_WRITE(HTOTAL(pipe),
5215                    (adjusted_mode->crtc_hdisplay - 1) |
5216                    ((adjusted_mode->crtc_htotal - 1) << 16));
5217         I915_WRITE(HBLANK(pipe),
5218                    (adjusted_mode->crtc_hblank_start - 1) |
5219                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5220         I915_WRITE(HSYNC(pipe),
5221                    (adjusted_mode->crtc_hsync_start - 1) |
5222                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5223
5224         I915_WRITE(VTOTAL(pipe),
5225                    (adjusted_mode->crtc_vdisplay - 1) |
5226                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5227         I915_WRITE(VBLANK(pipe),
5228                    (adjusted_mode->crtc_vblank_start - 1) |
5229                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5230         I915_WRITE(VSYNC(pipe),
5231                    (adjusted_mode->crtc_vsync_start - 1) |
5232                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5233
5234         /* pipesrc controls the size that is scaled from, which should
5235          * always be the user's requested size.
5236          */
5237         I915_WRITE(PIPESRC(pipe),
5238                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5239
5240         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5241         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5242         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5243         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5244
5245         if (has_edp_encoder &&
5246             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5247                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5248         }
5249
5250         I915_WRITE(PIPECONF(pipe), pipeconf);
5251         POSTING_READ(PIPECONF(pipe));
5252
5253         intel_wait_for_vblank(dev, pipe);
5254
5255         if (IS_GEN5(dev)) {
5256                 /* enable address swizzle for tiling buffer */
5257                 temp = I915_READ(DISP_ARB_CTL);
5258                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5259         }
5260
5261         I915_WRITE(DSPCNTR(plane), dspcntr);
5262         POSTING_READ(DSPCNTR(plane));
5263
5264         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5265
5266         intel_update_watermarks(dev);
5267
5268         return ret;
5269 }
5270
5271 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5272                                struct drm_display_mode *mode,
5273                                struct drm_display_mode *adjusted_mode,
5274                                int x, int y,
5275                                struct drm_framebuffer *old_fb)
5276 {
5277         struct drm_device *dev = crtc->dev;
5278         struct drm_i915_private *dev_priv = dev->dev_private;
5279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5280         int pipe = intel_crtc->pipe;
5281         int ret;
5282
5283         drm_vblank_pre_modeset(dev, pipe);
5284
5285         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5286                                               x, y, old_fb);
5287
5288         drm_vblank_post_modeset(dev, pipe);
5289
5290         return ret;
5291 }
5292
5293 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5294 void intel_crtc_load_lut(struct drm_crtc *crtc)
5295 {
5296         struct drm_device *dev = crtc->dev;
5297         struct drm_i915_private *dev_priv = dev->dev_private;
5298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5299         int palreg = PALETTE(intel_crtc->pipe);
5300         int i;
5301
5302         /* The clocks have to be on to load the palette. */
5303         if (!crtc->enabled)
5304                 return;
5305
5306         /* use legacy palette for Ironlake */
5307         if (HAS_PCH_SPLIT(dev))
5308                 palreg = LGC_PALETTE(intel_crtc->pipe);
5309
5310         for (i = 0; i < 256; i++) {
5311                 I915_WRITE(palreg + 4 * i,
5312                            (intel_crtc->lut_r[i] << 16) |
5313                            (intel_crtc->lut_g[i] << 8) |
5314                            intel_crtc->lut_b[i]);
5315         }
5316 }
5317
5318 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5319 {
5320         struct drm_device *dev = crtc->dev;
5321         struct drm_i915_private *dev_priv = dev->dev_private;
5322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5323         bool visible = base != 0;
5324         u32 cntl;
5325
5326         if (intel_crtc->cursor_visible == visible)
5327                 return;
5328
5329         cntl = I915_READ(_CURACNTR);
5330         if (visible) {
5331                 /* On these chipsets we can only modify the base whilst
5332                  * the cursor is disabled.
5333                  */
5334                 I915_WRITE(_CURABASE, base);
5335
5336                 cntl &= ~(CURSOR_FORMAT_MASK);
5337                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5338                 cntl |= CURSOR_ENABLE |
5339                         CURSOR_GAMMA_ENABLE |
5340                         CURSOR_FORMAT_ARGB;
5341         } else
5342                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5343         I915_WRITE(_CURACNTR, cntl);
5344
5345         intel_crtc->cursor_visible = visible;
5346 }
5347
5348 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5349 {
5350         struct drm_device *dev = crtc->dev;
5351         struct drm_i915_private *dev_priv = dev->dev_private;
5352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5353         int pipe = intel_crtc->pipe;
5354         bool visible = base != 0;
5355
5356         if (intel_crtc->cursor_visible != visible) {
5357                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5358                 if (base) {
5359                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5360                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5361                         cntl |= pipe << 28; /* Connect to correct pipe */
5362                 } else {
5363                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5364                         cntl |= CURSOR_MODE_DISABLE;
5365                 }
5366                 I915_WRITE(CURCNTR(pipe), cntl);
5367
5368                 intel_crtc->cursor_visible = visible;
5369         }
5370         /* and commit changes on next vblank */
5371         I915_WRITE(CURBASE(pipe), base);
5372 }
5373
5374 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5375 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5376                                      bool on)
5377 {
5378         struct drm_device *dev = crtc->dev;
5379         struct drm_i915_private *dev_priv = dev->dev_private;
5380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5381         int pipe = intel_crtc->pipe;
5382         int x = intel_crtc->cursor_x;
5383         int y = intel_crtc->cursor_y;
5384         u32 base, pos;
5385         bool visible;
5386
5387         pos = 0;
5388
5389         if (on && crtc->enabled && crtc->fb) {
5390                 base = intel_crtc->cursor_addr;
5391                 if (x > (int) crtc->fb->width)
5392                         base = 0;
5393
5394                 if (y > (int) crtc->fb->height)
5395                         base = 0;
5396         } else
5397                 base = 0;
5398
5399         if (x < 0) {
5400                 if (x + intel_crtc->cursor_width < 0)
5401                         base = 0;
5402
5403                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5404                 x = -x;
5405         }
5406         pos |= x << CURSOR_X_SHIFT;
5407
5408         if (y < 0) {
5409                 if (y + intel_crtc->cursor_height < 0)
5410                         base = 0;
5411
5412                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5413                 y = -y;
5414         }
5415         pos |= y << CURSOR_Y_SHIFT;
5416
5417         visible = base != 0;
5418         if (!visible && !intel_crtc->cursor_visible)
5419                 return;
5420
5421         I915_WRITE(CURPOS(pipe), pos);
5422         if (IS_845G(dev) || IS_I865G(dev))
5423                 i845_update_cursor(crtc, base);
5424         else
5425                 i9xx_update_cursor(crtc, base);
5426
5427         if (visible)
5428                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5429 }
5430
5431 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5432                                  struct drm_file *file,
5433                                  uint32_t handle,
5434                                  uint32_t width, uint32_t height)
5435 {
5436         struct drm_device *dev = crtc->dev;
5437         struct drm_i915_private *dev_priv = dev->dev_private;
5438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5439         struct drm_i915_gem_object *obj;
5440         uint32_t addr;
5441         int ret;
5442
5443         DRM_DEBUG_KMS("\n");
5444
5445         /* if we want to turn off the cursor ignore width and height */
5446         if (!handle) {
5447                 DRM_DEBUG_KMS("cursor off\n");
5448                 addr = 0;
5449                 obj = NULL;
5450                 mutex_lock(&dev->struct_mutex);
5451                 goto finish;
5452         }
5453
5454         /* Currently we only support 64x64 cursors */
5455         if (width != 64 || height != 64) {
5456                 DRM_ERROR("we currently only support 64x64 cursors\n");
5457                 return -EINVAL;
5458         }
5459
5460         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5461         if (&obj->base == NULL)
5462                 return -ENOENT;
5463
5464         if (obj->base.size < width * height * 4) {
5465                 DRM_ERROR("buffer is to small\n");
5466                 ret = -ENOMEM;
5467                 goto fail;
5468         }
5469
5470         /* we only need to pin inside GTT if cursor is non-phy */
5471         mutex_lock(&dev->struct_mutex);
5472         if (!dev_priv->info->cursor_needs_physical) {
5473                 if (obj->tiling_mode) {
5474                         DRM_ERROR("cursor cannot be tiled\n");
5475                         ret = -EINVAL;
5476                         goto fail_locked;
5477                 }
5478
5479                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
5480                 if (ret) {
5481                         DRM_ERROR("failed to pin cursor bo\n");
5482                         goto fail_locked;
5483                 }
5484
5485                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
5486                 if (ret) {
5487                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5488                         goto fail_unpin;
5489                 }
5490
5491                 ret = i915_gem_object_put_fence(obj);
5492                 if (ret) {
5493                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5494                         goto fail_unpin;
5495                 }
5496
5497                 addr = obj->gtt_offset;
5498         } else {
5499                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5500                 ret = i915_gem_attach_phys_object(dev, obj,
5501                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5502                                                   align);
5503                 if (ret) {
5504                         DRM_ERROR("failed to attach phys object\n");
5505                         goto fail_locked;
5506                 }
5507                 addr = obj->phys_obj->handle->busaddr;
5508         }
5509
5510         if (IS_GEN2(dev))
5511                 I915_WRITE(CURSIZE, (height << 12) | width);
5512
5513  finish:
5514         if (intel_crtc->cursor_bo) {
5515                 if (dev_priv->info->cursor_needs_physical) {
5516                         if (intel_crtc->cursor_bo != obj)
5517                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5518                 } else
5519                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5520                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5521         }
5522
5523         mutex_unlock(&dev->struct_mutex);
5524
5525         intel_crtc->cursor_addr = addr;
5526         intel_crtc->cursor_bo = obj;
5527         intel_crtc->cursor_width = width;
5528         intel_crtc->cursor_height = height;
5529
5530         intel_crtc_update_cursor(crtc, true);
5531
5532         return 0;
5533 fail_unpin:
5534         i915_gem_object_unpin(obj);
5535 fail_locked:
5536         mutex_unlock(&dev->struct_mutex);
5537 fail:
5538         drm_gem_object_unreference_unlocked(&obj->base);
5539         return ret;
5540 }
5541
5542 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5543 {
5544         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5545
5546         intel_crtc->cursor_x = x;
5547         intel_crtc->cursor_y = y;
5548
5549         intel_crtc_update_cursor(crtc, true);
5550
5551         return 0;
5552 }
5553
5554 /** Sets the color ramps on behalf of RandR */
5555 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5556                                  u16 blue, int regno)
5557 {
5558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5559
5560         intel_crtc->lut_r[regno] = red >> 8;
5561         intel_crtc->lut_g[regno] = green >> 8;
5562         intel_crtc->lut_b[regno] = blue >> 8;
5563 }
5564
5565 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5566                              u16 *blue, int regno)
5567 {
5568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5569
5570         *red = intel_crtc->lut_r[regno] << 8;
5571         *green = intel_crtc->lut_g[regno] << 8;
5572         *blue = intel_crtc->lut_b[regno] << 8;
5573 }
5574
5575 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5576                                  u16 *blue, uint32_t start, uint32_t size)
5577 {
5578         int end = (start + size > 256) ? 256 : start + size, i;
5579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5580
5581         for (i = start; i < end; i++) {
5582                 intel_crtc->lut_r[i] = red[i] >> 8;
5583                 intel_crtc->lut_g[i] = green[i] >> 8;
5584                 intel_crtc->lut_b[i] = blue[i] >> 8;
5585         }
5586
5587         intel_crtc_load_lut(crtc);
5588 }
5589
5590 /**
5591  * Get a pipe with a simple mode set on it for doing load-based monitor
5592  * detection.
5593  *
5594  * It will be up to the load-detect code to adjust the pipe as appropriate for
5595  * its requirements.  The pipe will be connected to no other encoders.
5596  *
5597  * Currently this code will only succeed if there is a pipe with no encoders
5598  * configured for it.  In the future, it could choose to temporarily disable
5599  * some outputs to free up a pipe for its use.
5600  *
5601  * \return crtc, or NULL if no pipes are available.
5602  */
5603
5604 /* VESA 640x480x72Hz mode to set on the pipe */
5605 static struct drm_display_mode load_detect_mode = {
5606         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5607                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5608 };
5609
5610 static struct drm_framebuffer *
5611 intel_framebuffer_create(struct drm_device *dev,
5612                          struct drm_mode_fb_cmd *mode_cmd,
5613                          struct drm_i915_gem_object *obj)
5614 {
5615         struct intel_framebuffer *intel_fb;
5616         int ret;
5617
5618         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5619         if (!intel_fb) {
5620                 drm_gem_object_unreference_unlocked(&obj->base);
5621                 return ERR_PTR(-ENOMEM);
5622         }
5623
5624         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5625         if (ret) {
5626                 drm_gem_object_unreference_unlocked(&obj->base);
5627                 kfree(intel_fb);
5628                 return ERR_PTR(ret);
5629         }
5630
5631         return &intel_fb->base;
5632 }
5633
5634 static u32
5635 intel_framebuffer_pitch_for_width(int width, int bpp)
5636 {
5637         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5638         return ALIGN(pitch, 64);
5639 }
5640
5641 static u32
5642 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5643 {
5644         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5645         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5646 }
5647
5648 static struct drm_framebuffer *
5649 intel_framebuffer_create_for_mode(struct drm_device *dev,
5650                                   struct drm_display_mode *mode,
5651                                   int depth, int bpp)
5652 {
5653         struct drm_i915_gem_object *obj;
5654         struct drm_mode_fb_cmd mode_cmd;
5655
5656         obj = i915_gem_alloc_object(dev,
5657                                     intel_framebuffer_size_for_mode(mode, bpp));
5658         if (obj == NULL)
5659                 return ERR_PTR(-ENOMEM);
5660
5661         mode_cmd.width = mode->hdisplay;
5662         mode_cmd.height = mode->vdisplay;
5663         mode_cmd.depth = depth;
5664         mode_cmd.bpp = bpp;
5665         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5666
5667         return intel_framebuffer_create(dev, &mode_cmd, obj);
5668 }
5669
5670 static struct drm_framebuffer *
5671 mode_fits_in_fbdev(struct drm_device *dev,
5672                    struct drm_display_mode *mode)
5673 {
5674         struct drm_i915_private *dev_priv = dev->dev_private;
5675         struct drm_i915_gem_object *obj;
5676         struct drm_framebuffer *fb;
5677
5678         if (dev_priv->fbdev == NULL)
5679                 return NULL;
5680
5681         obj = dev_priv->fbdev->ifb.obj;
5682         if (obj == NULL)
5683                 return NULL;
5684
5685         fb = &dev_priv->fbdev->ifb.base;
5686         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5687                                                           fb->bits_per_pixel))
5688                 return NULL;
5689
5690         if (obj->base.size < mode->vdisplay * fb->pitch)
5691                 return NULL;
5692
5693         return fb;
5694 }
5695
5696 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5697                                 struct drm_connector *connector,
5698                                 struct drm_display_mode *mode,
5699                                 struct intel_load_detect_pipe *old)
5700 {
5701         struct intel_crtc *intel_crtc;
5702         struct drm_crtc *possible_crtc;
5703         struct drm_encoder *encoder = &intel_encoder->base;
5704         struct drm_crtc *crtc = NULL;
5705         struct drm_device *dev = encoder->dev;
5706         struct drm_framebuffer *old_fb;
5707         int i = -1;
5708
5709         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5710                       connector->base.id, drm_get_connector_name(connector),
5711                       encoder->base.id, drm_get_encoder_name(encoder));
5712
5713         /*
5714          * Algorithm gets a little messy:
5715          *
5716          *   - if the connector already has an assigned crtc, use it (but make
5717          *     sure it's on first)
5718          *
5719          *   - try to find the first unused crtc that can drive this connector,
5720          *     and use that if we find one
5721          */
5722
5723         /* See if we already have a CRTC for this connector */
5724         if (encoder->crtc) {
5725                 crtc = encoder->crtc;
5726
5727                 intel_crtc = to_intel_crtc(crtc);
5728                 old->dpms_mode = intel_crtc->dpms_mode;
5729                 old->load_detect_temp = false;
5730
5731                 /* Make sure the crtc and connector are running */
5732                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5733                         struct drm_encoder_helper_funcs *encoder_funcs;
5734                         struct drm_crtc_helper_funcs *crtc_funcs;
5735
5736                         crtc_funcs = crtc->helper_private;
5737                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5738
5739                         encoder_funcs = encoder->helper_private;
5740                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5741                 }
5742
5743                 return true;
5744         }
5745
5746         /* Find an unused one (if possible) */
5747         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5748                 i++;
5749                 if (!(encoder->possible_crtcs & (1 << i)))
5750                         continue;
5751                 if (!possible_crtc->enabled) {
5752                         crtc = possible_crtc;
5753                         break;
5754                 }
5755         }
5756
5757         /*
5758          * If we didn't find an unused CRTC, don't use any.
5759          */
5760         if (!crtc) {
5761                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5762                 return false;
5763         }
5764
5765         encoder->crtc = crtc;
5766         connector->encoder = encoder;
5767
5768         intel_crtc = to_intel_crtc(crtc);
5769         old->dpms_mode = intel_crtc->dpms_mode;
5770         old->load_detect_temp = true;
5771         old->release_fb = NULL;
5772
5773         if (!mode)
5774                 mode = &load_detect_mode;
5775
5776         old_fb = crtc->fb;
5777
5778         /* We need a framebuffer large enough to accommodate all accesses
5779          * that the plane may generate whilst we perform load detection.
5780          * We can not rely on the fbcon either being present (we get called
5781          * during its initialisation to detect all boot displays, or it may
5782          * not even exist) or that it is large enough to satisfy the
5783          * requested mode.
5784          */
5785         crtc->fb = mode_fits_in_fbdev(dev, mode);
5786         if (crtc->fb == NULL) {
5787                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5788                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5789                 old->release_fb = crtc->fb;
5790         } else
5791                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5792         if (IS_ERR(crtc->fb)) {
5793                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5794                 crtc->fb = old_fb;
5795                 return false;
5796         }
5797
5798         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5799                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5800                 if (old->release_fb)
5801                         old->release_fb->funcs->destroy(old->release_fb);
5802                 crtc->fb = old_fb;
5803                 return false;
5804         }
5805
5806         /* let the connector get through one full cycle before testing */
5807         intel_wait_for_vblank(dev, intel_crtc->pipe);
5808
5809         return true;
5810 }
5811
5812 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5813                                     struct drm_connector *connector,
5814                                     struct intel_load_detect_pipe *old)
5815 {
5816         struct drm_encoder *encoder = &intel_encoder->base;
5817         struct drm_device *dev = encoder->dev;
5818         struct drm_crtc *crtc = encoder->crtc;
5819         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5820         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5821
5822         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5823                       connector->base.id, drm_get_connector_name(connector),
5824                       encoder->base.id, drm_get_encoder_name(encoder));
5825
5826         if (old->load_detect_temp) {
5827                 connector->encoder = NULL;
5828                 drm_helper_disable_unused_functions(dev);
5829
5830                 if (old->release_fb)
5831                         old->release_fb->funcs->destroy(old->release_fb);
5832
5833                 return;
5834         }
5835
5836         /* Switch crtc and encoder back off if necessary */
5837         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5838                 encoder_funcs->dpms(encoder, old->dpms_mode);
5839                 crtc_funcs->dpms(crtc, old->dpms_mode);
5840         }
5841 }
5842
5843 /* Returns the clock of the currently programmed mode of the given pipe. */
5844 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5845 {
5846         struct drm_i915_private *dev_priv = dev->dev_private;
5847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5848         int pipe = intel_crtc->pipe;
5849         u32 dpll = I915_READ(DPLL(pipe));
5850         u32 fp;
5851         intel_clock_t clock;
5852
5853         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5854                 fp = I915_READ(FP0(pipe));
5855         else
5856                 fp = I915_READ(FP1(pipe));
5857
5858         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5859         if (IS_PINEVIEW(dev)) {
5860                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5861                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5862         } else {
5863                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5864                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5865         }
5866
5867         if (!IS_GEN2(dev)) {
5868                 if (IS_PINEVIEW(dev))
5869                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5870                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5871                 else
5872                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5873                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5874
5875                 switch (dpll & DPLL_MODE_MASK) {
5876                 case DPLLB_MODE_DAC_SERIAL:
5877                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5878                                 5 : 10;
5879                         break;
5880                 case DPLLB_MODE_LVDS:
5881                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5882                                 7 : 14;
5883                         break;
5884                 default:
5885                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5886                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5887                         return 0;
5888                 }
5889
5890                 /* XXX: Handle the 100Mhz refclk */
5891                 intel_clock(dev, 96000, &clock);
5892         } else {
5893                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5894
5895                 if (is_lvds) {
5896                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5897                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5898                         clock.p2 = 14;
5899
5900                         if ((dpll & PLL_REF_INPUT_MASK) ==
5901                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5902                                 /* XXX: might not be 66MHz */
5903                                 intel_clock(dev, 66000, &clock);
5904                         } else
5905                                 intel_clock(dev, 48000, &clock);
5906                 } else {
5907                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5908                                 clock.p1 = 2;
5909                         else {
5910                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5911                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5912                         }
5913                         if (dpll & PLL_P2_DIVIDE_BY_4)
5914                                 clock.p2 = 4;
5915                         else
5916                                 clock.p2 = 2;
5917
5918                         intel_clock(dev, 48000, &clock);
5919                 }
5920         }
5921
5922         /* XXX: It would be nice to validate the clocks, but we can't reuse
5923          * i830PllIsValid() because it relies on the xf86_config connector
5924          * configuration being accurate, which it isn't necessarily.
5925          */
5926
5927         return clock.dot;
5928 }
5929
5930 /** Returns the currently programmed mode of the given pipe. */
5931 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5932                                              struct drm_crtc *crtc)
5933 {
5934         struct drm_i915_private *dev_priv = dev->dev_private;
5935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5936         int pipe = intel_crtc->pipe;
5937         struct drm_display_mode *mode;
5938         int htot = I915_READ(HTOTAL(pipe));
5939         int hsync = I915_READ(HSYNC(pipe));
5940         int vtot = I915_READ(VTOTAL(pipe));
5941         int vsync = I915_READ(VSYNC(pipe));
5942
5943         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5944         if (!mode)
5945                 return NULL;
5946
5947         mode->clock = intel_crtc_clock_get(dev, crtc);
5948         mode->hdisplay = (htot & 0xffff) + 1;
5949         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5950         mode->hsync_start = (hsync & 0xffff) + 1;
5951         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5952         mode->vdisplay = (vtot & 0xffff) + 1;
5953         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5954         mode->vsync_start = (vsync & 0xffff) + 1;
5955         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5956
5957         drm_mode_set_name(mode);
5958         drm_mode_set_crtcinfo(mode, 0);
5959
5960         return mode;
5961 }
5962
5963 #define GPU_IDLE_TIMEOUT 500 /* ms */
5964
5965 /* When this timer fires, we've been idle for awhile */
5966 static void intel_gpu_idle_timer(unsigned long arg)
5967 {
5968         struct drm_device *dev = (struct drm_device *)arg;
5969         drm_i915_private_t *dev_priv = dev->dev_private;
5970
5971         if (!list_empty(&dev_priv->mm.active_list)) {
5972                 /* Still processing requests, so just re-arm the timer. */
5973                 mod_timer(&dev_priv->idle_timer, jiffies +
5974                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5975                 return;
5976         }
5977
5978         dev_priv->busy = false;
5979         queue_work(dev_priv->wq, &dev_priv->idle_work);
5980 }
5981
5982 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5983
5984 static void intel_crtc_idle_timer(unsigned long arg)
5985 {
5986         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5987         struct drm_crtc *crtc = &intel_crtc->base;
5988         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5989         struct intel_framebuffer *intel_fb;
5990
5991         intel_fb = to_intel_framebuffer(crtc->fb);
5992         if (intel_fb && intel_fb->obj->active) {
5993                 /* The framebuffer is still being accessed by the GPU. */
5994                 mod_timer(&intel_crtc->idle_timer, jiffies +
5995                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5996                 return;
5997         }
5998
5999         intel_crtc->busy = false;
6000         queue_work(dev_priv->wq, &dev_priv->idle_work);
6001 }
6002
6003 static void intel_increase_pllclock(struct drm_crtc *crtc)
6004 {
6005         struct drm_device *dev = crtc->dev;
6006         drm_i915_private_t *dev_priv = dev->dev_private;
6007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6008         int pipe = intel_crtc->pipe;
6009         int dpll_reg = DPLL(pipe);
6010         int dpll;
6011
6012         if (HAS_PCH_SPLIT(dev))
6013                 return;
6014
6015         if (!dev_priv->lvds_downclock_avail)
6016                 return;
6017
6018         dpll = I915_READ(dpll_reg);
6019         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6020                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6021
6022                 /* Unlock panel regs */
6023                 I915_WRITE(PP_CONTROL,
6024                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6025
6026                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6027                 I915_WRITE(dpll_reg, dpll);
6028                 intel_wait_for_vblank(dev, pipe);
6029
6030                 dpll = I915_READ(dpll_reg);
6031                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6032                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6033
6034                 /* ...and lock them again */
6035                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6036         }
6037
6038         /* Schedule downclock */
6039         mod_timer(&intel_crtc->idle_timer, jiffies +
6040                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6041 }
6042
6043 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6044 {
6045         struct drm_device *dev = crtc->dev;
6046         drm_i915_private_t *dev_priv = dev->dev_private;
6047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6048         int pipe = intel_crtc->pipe;
6049         int dpll_reg = DPLL(pipe);
6050         int dpll = I915_READ(dpll_reg);
6051
6052         if (HAS_PCH_SPLIT(dev))
6053                 return;
6054
6055         if (!dev_priv->lvds_downclock_avail)
6056                 return;
6057
6058         /*
6059          * Since this is called by a timer, we should never get here in
6060          * the manual case.
6061          */
6062         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6063                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6064
6065                 /* Unlock panel regs */
6066                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6067                            PANEL_UNLOCK_REGS);
6068
6069                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6070                 I915_WRITE(dpll_reg, dpll);
6071                 intel_wait_for_vblank(dev, pipe);
6072                 dpll = I915_READ(dpll_reg);
6073                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6074                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6075
6076                 /* ...and lock them again */
6077                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6078         }
6079
6080 }
6081
6082 /**
6083  * intel_idle_update - adjust clocks for idleness
6084  * @work: work struct
6085  *
6086  * Either the GPU or display (or both) went idle.  Check the busy status
6087  * here and adjust the CRTC and GPU clocks as necessary.
6088  */
6089 static void intel_idle_update(struct work_struct *work)
6090 {
6091         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6092                                                     idle_work);
6093         struct drm_device *dev = dev_priv->dev;
6094         struct drm_crtc *crtc;
6095         struct intel_crtc *intel_crtc;
6096
6097         if (!i915_powersave)
6098                 return;
6099
6100         mutex_lock(&dev->struct_mutex);
6101
6102         i915_update_gfx_val(dev_priv);
6103
6104         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6105                 /* Skip inactive CRTCs */
6106                 if (!crtc->fb)
6107                         continue;
6108
6109                 intel_crtc = to_intel_crtc(crtc);
6110                 if (!intel_crtc->busy)
6111                         intel_decrease_pllclock(crtc);
6112         }
6113
6114
6115         mutex_unlock(&dev->struct_mutex);
6116 }
6117
6118 /**
6119  * intel_mark_busy - mark the GPU and possibly the display busy
6120  * @dev: drm device
6121  * @obj: object we're operating on
6122  *
6123  * Callers can use this function to indicate that the GPU is busy processing
6124  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6125  * buffer), we'll also mark the display as busy, so we know to increase its
6126  * clock frequency.
6127  */
6128 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6129 {
6130         drm_i915_private_t *dev_priv = dev->dev_private;
6131         struct drm_crtc *crtc = NULL;
6132         struct intel_framebuffer *intel_fb;
6133         struct intel_crtc *intel_crtc;
6134
6135         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6136                 return;
6137
6138         if (!dev_priv->busy)
6139                 dev_priv->busy = true;
6140         else
6141                 mod_timer(&dev_priv->idle_timer, jiffies +
6142                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6143
6144         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6145                 if (!crtc->fb)
6146                         continue;
6147
6148                 intel_crtc = to_intel_crtc(crtc);
6149                 intel_fb = to_intel_framebuffer(crtc->fb);
6150                 if (intel_fb->obj == obj) {
6151                         if (!intel_crtc->busy) {
6152                                 /* Non-busy -> busy, upclock */
6153                                 intel_increase_pllclock(crtc);
6154                                 intel_crtc->busy = true;
6155                         } else {
6156                                 /* Busy -> busy, put off timer */
6157                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6158                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6159                         }
6160                 }
6161         }
6162 }
6163
6164 static void intel_crtc_destroy(struct drm_crtc *crtc)
6165 {
6166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6167         struct drm_device *dev = crtc->dev;
6168         struct intel_unpin_work *work;
6169         unsigned long flags;
6170
6171         spin_lock_irqsave(&dev->event_lock, flags);
6172         work = intel_crtc->unpin_work;
6173         intel_crtc->unpin_work = NULL;
6174         spin_unlock_irqrestore(&dev->event_lock, flags);
6175
6176         if (work) {
6177                 cancel_work_sync(&work->work);
6178                 kfree(work);
6179         }
6180
6181         drm_crtc_cleanup(crtc);
6182
6183         kfree(intel_crtc);
6184 }
6185
6186 static void intel_unpin_work_fn(struct work_struct *__work)
6187 {
6188         struct intel_unpin_work *work =
6189                 container_of(__work, struct intel_unpin_work, work);
6190
6191         mutex_lock(&work->dev->struct_mutex);
6192         i915_gem_object_unpin(work->old_fb_obj);
6193         drm_gem_object_unreference(&work->pending_flip_obj->base);
6194         drm_gem_object_unreference(&work->old_fb_obj->base);
6195
6196         mutex_unlock(&work->dev->struct_mutex);
6197         kfree(work);
6198 }
6199
6200 static void do_intel_finish_page_flip(struct drm_device *dev,
6201                                       struct drm_crtc *crtc)
6202 {
6203         drm_i915_private_t *dev_priv = dev->dev_private;
6204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6205         struct intel_unpin_work *work;
6206         struct drm_i915_gem_object *obj;
6207         struct drm_pending_vblank_event *e;
6208         struct timeval tnow, tvbl;
6209         unsigned long flags;
6210
6211         /* Ignore early vblank irqs */
6212         if (intel_crtc == NULL)
6213                 return;
6214
6215         do_gettimeofday(&tnow);
6216
6217         spin_lock_irqsave(&dev->event_lock, flags);
6218         work = intel_crtc->unpin_work;
6219         if (work == NULL || !work->pending) {
6220                 spin_unlock_irqrestore(&dev->event_lock, flags);
6221                 return;
6222         }
6223
6224         intel_crtc->unpin_work = NULL;
6225
6226         if (work->event) {
6227                 e = work->event;
6228                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6229
6230                 /* Called before vblank count and timestamps have
6231                  * been updated for the vblank interval of flip
6232                  * completion? Need to increment vblank count and
6233                  * add one videorefresh duration to returned timestamp
6234                  * to account for this. We assume this happened if we
6235                  * get called over 0.9 frame durations after the last
6236                  * timestamped vblank.
6237                  *
6238                  * This calculation can not be used with vrefresh rates
6239                  * below 5Hz (10Hz to be on the safe side) without
6240                  * promoting to 64 integers.
6241                  */
6242                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6243                     9 * crtc->framedur_ns) {
6244                         e->event.sequence++;
6245                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6246                                              crtc->framedur_ns);
6247                 }
6248
6249                 e->event.tv_sec = tvbl.tv_sec;
6250                 e->event.tv_usec = tvbl.tv_usec;
6251
6252                 list_add_tail(&e->base.link,
6253                               &e->base.file_priv->event_list);
6254                 wake_up_interruptible(&e->base.file_priv->event_wait);
6255         }
6256
6257         drm_vblank_put(dev, intel_crtc->pipe);
6258
6259         spin_unlock_irqrestore(&dev->event_lock, flags);
6260
6261         obj = work->old_fb_obj;
6262
6263         atomic_clear_mask(1 << intel_crtc->plane,
6264                           &obj->pending_flip.counter);
6265         if (atomic_read(&obj->pending_flip) == 0)
6266                 wake_up(&dev_priv->pending_flip_queue);
6267
6268         schedule_work(&work->work);
6269
6270         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6271 }
6272
6273 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6274 {
6275         drm_i915_private_t *dev_priv = dev->dev_private;
6276         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6277
6278         do_intel_finish_page_flip(dev, crtc);
6279 }
6280
6281 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6282 {
6283         drm_i915_private_t *dev_priv = dev->dev_private;
6284         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6285
6286         do_intel_finish_page_flip(dev, crtc);
6287 }
6288
6289 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6290 {
6291         drm_i915_private_t *dev_priv = dev->dev_private;
6292         struct intel_crtc *intel_crtc =
6293                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6294         unsigned long flags;
6295
6296         spin_lock_irqsave(&dev->event_lock, flags);
6297         if (intel_crtc->unpin_work) {
6298                 if ((++intel_crtc->unpin_work->pending) > 1)
6299                         DRM_ERROR("Prepared flip multiple times\n");
6300         } else {
6301                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6302         }
6303         spin_unlock_irqrestore(&dev->event_lock, flags);
6304 }
6305
6306 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6307                                 struct drm_framebuffer *fb,
6308                                 struct drm_pending_vblank_event *event)
6309 {
6310         struct drm_device *dev = crtc->dev;
6311         struct drm_i915_private *dev_priv = dev->dev_private;
6312         struct intel_framebuffer *intel_fb;
6313         struct drm_i915_gem_object *obj;
6314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6315         struct intel_unpin_work *work;
6316         unsigned long flags, offset;
6317         int pipe = intel_crtc->pipe;
6318         u32 pf, pipesrc;
6319         int ret;
6320
6321         work = kzalloc(sizeof *work, GFP_KERNEL);
6322         if (work == NULL)
6323                 return -ENOMEM;
6324
6325         work->event = event;
6326         work->dev = crtc->dev;
6327         intel_fb = to_intel_framebuffer(crtc->fb);
6328         work->old_fb_obj = intel_fb->obj;
6329         INIT_WORK(&work->work, intel_unpin_work_fn);
6330
6331         /* We borrow the event spin lock for protecting unpin_work */
6332         spin_lock_irqsave(&dev->event_lock, flags);
6333         if (intel_crtc->unpin_work) {
6334                 spin_unlock_irqrestore(&dev->event_lock, flags);
6335                 kfree(work);
6336
6337                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6338                 return -EBUSY;
6339         }
6340         intel_crtc->unpin_work = work;
6341         spin_unlock_irqrestore(&dev->event_lock, flags);
6342
6343         intel_fb = to_intel_framebuffer(fb);
6344         obj = intel_fb->obj;
6345
6346         mutex_lock(&dev->struct_mutex);
6347         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6348         if (ret)
6349                 goto cleanup_work;
6350
6351         /* Reference the objects for the scheduled work. */
6352         drm_gem_object_reference(&work->old_fb_obj->base);
6353         drm_gem_object_reference(&obj->base);
6354
6355         crtc->fb = fb;
6356
6357         ret = drm_vblank_get(dev, intel_crtc->pipe);
6358         if (ret)
6359                 goto cleanup_objs;
6360
6361         if (IS_GEN3(dev) || IS_GEN2(dev)) {
6362                 u32 flip_mask;
6363
6364                 /* Can't queue multiple flips, so wait for the previous
6365                  * one to finish before executing the next.
6366                  */
6367                 ret = BEGIN_LP_RING(2);
6368                 if (ret)
6369                         goto cleanup_objs;
6370
6371                 if (intel_crtc->plane)
6372                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6373                 else
6374                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6375                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6376                 OUT_RING(MI_NOOP);
6377                 ADVANCE_LP_RING();
6378         }
6379
6380         work->pending_flip_obj = obj;
6381
6382         work->enable_stall_check = true;
6383
6384         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6385         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6386
6387         ret = BEGIN_LP_RING(4);
6388         if (ret)
6389                 goto cleanup_objs;
6390
6391         /* Block clients from rendering to the new back buffer until
6392          * the flip occurs and the object is no longer visible.
6393          */
6394         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6395
6396         switch (INTEL_INFO(dev)->gen) {
6397         case 2:
6398                 OUT_RING(MI_DISPLAY_FLIP |
6399                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6400                 OUT_RING(fb->pitch);
6401                 OUT_RING(obj->gtt_offset + offset);
6402                 OUT_RING(MI_NOOP);
6403                 break;
6404
6405         case 3:
6406                 OUT_RING(MI_DISPLAY_FLIP_I915 |
6407                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6408                 OUT_RING(fb->pitch);
6409                 OUT_RING(obj->gtt_offset + offset);
6410                 OUT_RING(MI_NOOP);
6411                 break;
6412
6413         case 4:
6414         case 5:
6415                 /* i965+ uses the linear or tiled offsets from the
6416                  * Display Registers (which do not change across a page-flip)
6417                  * so we need only reprogram the base address.
6418                  */
6419                 OUT_RING(MI_DISPLAY_FLIP |
6420                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6421                 OUT_RING(fb->pitch);
6422                 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6423
6424                 /* XXX Enabling the panel-fitter across page-flip is so far
6425                  * untested on non-native modes, so ignore it for now.
6426                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6427                  */
6428                 pf = 0;
6429                 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6430                 OUT_RING(pf | pipesrc);
6431                 break;
6432
6433         case 6:
6434         case 7:
6435                 OUT_RING(MI_DISPLAY_FLIP |
6436                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6437                 OUT_RING(fb->pitch | obj->tiling_mode);
6438                 OUT_RING(obj->gtt_offset);
6439
6440                 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6441                 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6442                 OUT_RING(pf | pipesrc);
6443                 break;
6444         }
6445         ADVANCE_LP_RING();
6446
6447         mutex_unlock(&dev->struct_mutex);
6448
6449         trace_i915_flip_request(intel_crtc->plane, obj);
6450
6451         return 0;
6452
6453 cleanup_objs:
6454         drm_gem_object_unreference(&work->old_fb_obj->base);
6455         drm_gem_object_unreference(&obj->base);
6456 cleanup_work:
6457         mutex_unlock(&dev->struct_mutex);
6458
6459         spin_lock_irqsave(&dev->event_lock, flags);
6460         intel_crtc->unpin_work = NULL;
6461         spin_unlock_irqrestore(&dev->event_lock, flags);
6462
6463         kfree(work);
6464
6465         return ret;
6466 }
6467
6468 static void intel_sanitize_modesetting(struct drm_device *dev,
6469                                        int pipe, int plane)
6470 {
6471         struct drm_i915_private *dev_priv = dev->dev_private;
6472         u32 reg, val;
6473
6474         if (HAS_PCH_SPLIT(dev))
6475                 return;
6476
6477         /* Who knows what state these registers were left in by the BIOS or
6478          * grub?
6479          *
6480          * If we leave the registers in a conflicting state (e.g. with the
6481          * display plane reading from the other pipe than the one we intend
6482          * to use) then when we attempt to teardown the active mode, we will
6483          * not disable the pipes and planes in the correct order -- leaving
6484          * a plane reading from a disabled pipe and possibly leading to
6485          * undefined behaviour.
6486          */
6487
6488         reg = DSPCNTR(plane);
6489         val = I915_READ(reg);
6490
6491         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6492                 return;
6493         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6494                 return;
6495
6496         /* This display plane is active and attached to the other CPU pipe. */
6497         pipe = !pipe;
6498
6499         /* Disable the plane and wait for it to stop reading from the pipe. */
6500         intel_disable_plane(dev_priv, plane, pipe);
6501         intel_disable_pipe(dev_priv, pipe);
6502 }
6503
6504 static void intel_crtc_reset(struct drm_crtc *crtc)
6505 {
6506         struct drm_device *dev = crtc->dev;
6507         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6508
6509         /* Reset flags back to the 'unknown' status so that they
6510          * will be correctly set on the initial modeset.
6511          */
6512         intel_crtc->dpms_mode = -1;
6513
6514         /* We need to fix up any BIOS configuration that conflicts with
6515          * our expectations.
6516          */
6517         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6518 }
6519
6520 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6521         .dpms = intel_crtc_dpms,
6522         .mode_fixup = intel_crtc_mode_fixup,
6523         .mode_set = intel_crtc_mode_set,
6524         .mode_set_base = intel_pipe_set_base,
6525         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6526         .load_lut = intel_crtc_load_lut,
6527         .disable = intel_crtc_disable,
6528 };
6529
6530 static const struct drm_crtc_funcs intel_crtc_funcs = {
6531         .reset = intel_crtc_reset,
6532         .cursor_set = intel_crtc_cursor_set,
6533         .cursor_move = intel_crtc_cursor_move,
6534         .gamma_set = intel_crtc_gamma_set,
6535         .set_config = drm_crtc_helper_set_config,
6536         .destroy = intel_crtc_destroy,
6537         .page_flip = intel_crtc_page_flip,
6538 };
6539
6540 static void intel_crtc_init(struct drm_device *dev, int pipe)
6541 {
6542         drm_i915_private_t *dev_priv = dev->dev_private;
6543         struct intel_crtc *intel_crtc;
6544         int i;
6545
6546         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6547         if (intel_crtc == NULL)
6548                 return;
6549
6550         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6551
6552         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6553         for (i = 0; i < 256; i++) {
6554                 intel_crtc->lut_r[i] = i;
6555                 intel_crtc->lut_g[i] = i;
6556                 intel_crtc->lut_b[i] = i;
6557         }
6558
6559         /* Swap pipes & planes for FBC on pre-965 */
6560         intel_crtc->pipe = pipe;
6561         intel_crtc->plane = pipe;
6562         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6563                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6564                 intel_crtc->plane = !pipe;
6565         }
6566
6567         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6568                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6569         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6570         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6571
6572         intel_crtc_reset(&intel_crtc->base);
6573         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6574
6575         if (HAS_PCH_SPLIT(dev)) {
6576                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6577                 intel_helper_funcs.commit = ironlake_crtc_commit;
6578         } else {
6579                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6580                 intel_helper_funcs.commit = i9xx_crtc_commit;
6581         }
6582
6583         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6584
6585         intel_crtc->busy = false;
6586
6587         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6588                     (unsigned long)intel_crtc);
6589 }
6590
6591 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6592                                 struct drm_file *file)
6593 {
6594         drm_i915_private_t *dev_priv = dev->dev_private;
6595         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6596         struct drm_mode_object *drmmode_obj;
6597         struct intel_crtc *crtc;
6598
6599         if (!dev_priv) {
6600                 DRM_ERROR("called with no initialization\n");
6601                 return -EINVAL;
6602         }
6603
6604         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6605                         DRM_MODE_OBJECT_CRTC);
6606
6607         if (!drmmode_obj) {
6608                 DRM_ERROR("no such CRTC id\n");
6609                 return -EINVAL;
6610         }
6611
6612         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6613         pipe_from_crtc_id->pipe = crtc->pipe;
6614
6615         return 0;
6616 }
6617
6618 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6619 {
6620         struct intel_encoder *encoder;
6621         int index_mask = 0;
6622         int entry = 0;
6623
6624         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6625                 if (type_mask & encoder->clone_mask)
6626                         index_mask |= (1 << entry);
6627                 entry++;
6628         }
6629
6630         return index_mask;
6631 }
6632
6633 static bool has_edp_a(struct drm_device *dev)
6634 {
6635         struct drm_i915_private *dev_priv = dev->dev_private;
6636
6637         if (!IS_MOBILE(dev))
6638                 return false;
6639
6640         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6641                 return false;
6642
6643         if (IS_GEN5(dev) &&
6644             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6645                 return false;
6646
6647         return true;
6648 }
6649
6650 static void intel_setup_outputs(struct drm_device *dev)
6651 {
6652         struct drm_i915_private *dev_priv = dev->dev_private;
6653         struct intel_encoder *encoder;
6654         bool dpd_is_edp = false;
6655         bool has_lvds = false;
6656
6657         if (IS_MOBILE(dev) && !IS_I830(dev))
6658                 has_lvds = intel_lvds_init(dev);
6659         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6660                 /* disable the panel fitter on everything but LVDS */
6661                 I915_WRITE(PFIT_CONTROL, 0);
6662         }
6663
6664         if (HAS_PCH_SPLIT(dev)) {
6665                 dpd_is_edp = intel_dpd_is_edp(dev);
6666
6667                 if (has_edp_a(dev))
6668                         intel_dp_init(dev, DP_A);
6669
6670                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6671                         intel_dp_init(dev, PCH_DP_D);
6672         }
6673
6674         intel_crt_init(dev);
6675
6676         if (HAS_PCH_SPLIT(dev)) {
6677                 int found;
6678
6679                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6680                         /* PCH SDVOB multiplex with HDMIB */
6681                         found = intel_sdvo_init(dev, PCH_SDVOB);
6682                         if (!found)
6683                                 intel_hdmi_init(dev, HDMIB);
6684                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6685                                 intel_dp_init(dev, PCH_DP_B);
6686                 }
6687
6688                 if (I915_READ(HDMIC) & PORT_DETECTED)
6689                         intel_hdmi_init(dev, HDMIC);
6690
6691                 if (I915_READ(HDMID) & PORT_DETECTED)
6692                         intel_hdmi_init(dev, HDMID);
6693
6694                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6695                         intel_dp_init(dev, PCH_DP_C);
6696
6697                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6698                         intel_dp_init(dev, PCH_DP_D);
6699
6700         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6701                 bool found = false;
6702
6703                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6704                         DRM_DEBUG_KMS("probing SDVOB\n");
6705                         found = intel_sdvo_init(dev, SDVOB);
6706                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6707                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6708                                 intel_hdmi_init(dev, SDVOB);
6709                         }
6710
6711                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6712                                 DRM_DEBUG_KMS("probing DP_B\n");
6713                                 intel_dp_init(dev, DP_B);
6714                         }
6715                 }
6716
6717                 /* Before G4X SDVOC doesn't have its own detect register */
6718
6719                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6720                         DRM_DEBUG_KMS("probing SDVOC\n");
6721                         found = intel_sdvo_init(dev, SDVOC);
6722                 }
6723
6724                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6725
6726                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6727                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6728                                 intel_hdmi_init(dev, SDVOC);
6729                         }
6730                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6731                                 DRM_DEBUG_KMS("probing DP_C\n");
6732                                 intel_dp_init(dev, DP_C);
6733                         }
6734                 }
6735
6736                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6737                     (I915_READ(DP_D) & DP_DETECTED)) {
6738                         DRM_DEBUG_KMS("probing DP_D\n");
6739                         intel_dp_init(dev, DP_D);
6740                 }
6741         } else if (IS_GEN2(dev))
6742                 intel_dvo_init(dev);
6743
6744         if (SUPPORTS_TV(dev))
6745                 intel_tv_init(dev);
6746
6747         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6748                 encoder->base.possible_crtcs = encoder->crtc_mask;
6749                 encoder->base.possible_clones =
6750                         intel_encoder_clones(dev, encoder->clone_mask);
6751         }
6752
6753         intel_panel_setup_backlight(dev);
6754
6755         /* disable all the possible outputs/crtcs before entering KMS mode */
6756         drm_helper_disable_unused_functions(dev);
6757 }
6758
6759 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6760 {
6761         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6762
6763         drm_framebuffer_cleanup(fb);
6764         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6765
6766         kfree(intel_fb);
6767 }
6768
6769 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6770                                                 struct drm_file *file,
6771                                                 unsigned int *handle)
6772 {
6773         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6774         struct drm_i915_gem_object *obj = intel_fb->obj;
6775
6776         return drm_gem_handle_create(file, &obj->base, handle);
6777 }
6778
6779 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6780         .destroy = intel_user_framebuffer_destroy,
6781         .create_handle = intel_user_framebuffer_create_handle,
6782 };
6783
6784 int intel_framebuffer_init(struct drm_device *dev,
6785                            struct intel_framebuffer *intel_fb,
6786                            struct drm_mode_fb_cmd *mode_cmd,
6787                            struct drm_i915_gem_object *obj)
6788 {
6789         int ret;
6790
6791         if (obj->tiling_mode == I915_TILING_Y)
6792                 return -EINVAL;
6793
6794         if (mode_cmd->pitch & 63)
6795                 return -EINVAL;
6796
6797         switch (mode_cmd->bpp) {
6798         case 8:
6799         case 16:
6800         case 24:
6801         case 32:
6802                 break;
6803         default:
6804                 return -EINVAL;
6805         }
6806
6807         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6808         if (ret) {
6809                 DRM_ERROR("framebuffer init failed %d\n", ret);
6810                 return ret;
6811         }
6812
6813         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6814         intel_fb->obj = obj;
6815         return 0;
6816 }
6817
6818 static struct drm_framebuffer *
6819 intel_user_framebuffer_create(struct drm_device *dev,
6820                               struct drm_file *filp,
6821                               struct drm_mode_fb_cmd *mode_cmd)
6822 {
6823         struct drm_i915_gem_object *obj;
6824
6825         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6826         if (&obj->base == NULL)
6827                 return ERR_PTR(-ENOENT);
6828
6829         return intel_framebuffer_create(dev, mode_cmd, obj);
6830 }
6831
6832 static const struct drm_mode_config_funcs intel_mode_funcs = {
6833         .fb_create = intel_user_framebuffer_create,
6834         .output_poll_changed = intel_fb_output_poll_changed,
6835 };
6836
6837 static struct drm_i915_gem_object *
6838 intel_alloc_context_page(struct drm_device *dev)
6839 {
6840         struct drm_i915_gem_object *ctx;
6841         int ret;
6842
6843         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6844
6845         ctx = i915_gem_alloc_object(dev, 4096);
6846         if (!ctx) {
6847                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6848                 return NULL;
6849         }
6850
6851         ret = i915_gem_object_pin(ctx, 4096, true);
6852         if (ret) {
6853                 DRM_ERROR("failed to pin power context: %d\n", ret);
6854                 goto err_unref;
6855         }
6856
6857         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6858         if (ret) {
6859                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6860                 goto err_unpin;
6861         }
6862
6863         return ctx;
6864
6865 err_unpin:
6866         i915_gem_object_unpin(ctx);
6867 err_unref:
6868         drm_gem_object_unreference(&ctx->base);
6869         mutex_unlock(&dev->struct_mutex);
6870         return NULL;
6871 }
6872
6873 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6874 {
6875         struct drm_i915_private *dev_priv = dev->dev_private;
6876         u16 rgvswctl;
6877
6878         rgvswctl = I915_READ16(MEMSWCTL);
6879         if (rgvswctl & MEMCTL_CMD_STS) {
6880                 DRM_DEBUG("gpu busy, RCS change rejected\n");
6881                 return false; /* still busy with another command */
6882         }
6883
6884         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6885                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6886         I915_WRITE16(MEMSWCTL, rgvswctl);
6887         POSTING_READ16(MEMSWCTL);
6888
6889         rgvswctl |= MEMCTL_CMD_STS;
6890         I915_WRITE16(MEMSWCTL, rgvswctl);
6891
6892         return true;
6893 }
6894
6895 void ironlake_enable_drps(struct drm_device *dev)
6896 {
6897         struct drm_i915_private *dev_priv = dev->dev_private;
6898         u32 rgvmodectl = I915_READ(MEMMODECTL);
6899         u8 fmax, fmin, fstart, vstart;
6900
6901         /* Enable temp reporting */
6902         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6903         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6904
6905         /* 100ms RC evaluation intervals */
6906         I915_WRITE(RCUPEI, 100000);
6907         I915_WRITE(RCDNEI, 100000);
6908
6909         /* Set max/min thresholds to 90ms and 80ms respectively */
6910         I915_WRITE(RCBMAXAVG, 90000);
6911         I915_WRITE(RCBMINAVG, 80000);
6912
6913         I915_WRITE(MEMIHYST, 1);
6914
6915         /* Set up min, max, and cur for interrupt handling */
6916         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6917         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6918         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6919                 MEMMODE_FSTART_SHIFT;
6920
6921         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6922                 PXVFREQ_PX_SHIFT;
6923
6924         dev_priv->fmax = fmax; /* IPS callback will increase this */
6925         dev_priv->fstart = fstart;
6926
6927         dev_priv->max_delay = fstart;
6928         dev_priv->min_delay = fmin;
6929         dev_priv->cur_delay = fstart;
6930
6931         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6932                          fmax, fmin, fstart);
6933
6934         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6935
6936         /*
6937          * Interrupts will be enabled in ironlake_irq_postinstall
6938          */
6939
6940         I915_WRITE(VIDSTART, vstart);
6941         POSTING_READ(VIDSTART);
6942
6943         rgvmodectl |= MEMMODE_SWMODE_EN;
6944         I915_WRITE(MEMMODECTL, rgvmodectl);
6945
6946         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6947                 DRM_ERROR("stuck trying to change perf mode\n");
6948         msleep(1);
6949
6950         ironlake_set_drps(dev, fstart);
6951
6952         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6953                 I915_READ(0x112e0);
6954         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6955         dev_priv->last_count2 = I915_READ(0x112f4);
6956         getrawmonotonic(&dev_priv->last_time2);
6957 }
6958
6959 void ironlake_disable_drps(struct drm_device *dev)
6960 {
6961         struct drm_i915_private *dev_priv = dev->dev_private;
6962         u16 rgvswctl = I915_READ16(MEMSWCTL);
6963
6964         /* Ack interrupts, disable EFC interrupt */
6965         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6966         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6967         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6968         I915_WRITE(DEIIR, DE_PCU_EVENT);
6969         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6970
6971         /* Go back to the starting frequency */
6972         ironlake_set_drps(dev, dev_priv->fstart);
6973         msleep(1);
6974         rgvswctl |= MEMCTL_CMD_STS;
6975         I915_WRITE(MEMSWCTL, rgvswctl);
6976         msleep(1);
6977
6978 }
6979
6980 void gen6_set_rps(struct drm_device *dev, u8 val)
6981 {
6982         struct drm_i915_private *dev_priv = dev->dev_private;
6983         u32 swreq;
6984
6985         swreq = (val & 0x3ff) << 25;
6986         I915_WRITE(GEN6_RPNSWREQ, swreq);
6987 }
6988
6989 void gen6_disable_rps(struct drm_device *dev)
6990 {
6991         struct drm_i915_private *dev_priv = dev->dev_private;
6992
6993         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6994         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6995         I915_WRITE(GEN6_PMIER, 0);
6996
6997         spin_lock_irq(&dev_priv->rps_lock);
6998         dev_priv->pm_iir = 0;
6999         spin_unlock_irq(&dev_priv->rps_lock);
7000
7001         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7002 }
7003
7004 static unsigned long intel_pxfreq(u32 vidfreq)
7005 {
7006         unsigned long freq;
7007         int div = (vidfreq & 0x3f0000) >> 16;
7008         int post = (vidfreq & 0x3000) >> 12;
7009         int pre = (vidfreq & 0x7);
7010
7011         if (!pre)
7012                 return 0;
7013
7014         freq = ((div * 133333) / ((1<<post) * pre));
7015
7016         return freq;
7017 }
7018
7019 void intel_init_emon(struct drm_device *dev)
7020 {
7021         struct drm_i915_private *dev_priv = dev->dev_private;
7022         u32 lcfuse;
7023         u8 pxw[16];
7024         int i;
7025
7026         /* Disable to program */
7027         I915_WRITE(ECR, 0);
7028         POSTING_READ(ECR);
7029
7030         /* Program energy weights for various events */
7031         I915_WRITE(SDEW, 0x15040d00);
7032         I915_WRITE(CSIEW0, 0x007f0000);
7033         I915_WRITE(CSIEW1, 0x1e220004);
7034         I915_WRITE(CSIEW2, 0x04000004);
7035
7036         for (i = 0; i < 5; i++)
7037                 I915_WRITE(PEW + (i * 4), 0);
7038         for (i = 0; i < 3; i++)
7039                 I915_WRITE(DEW + (i * 4), 0);
7040
7041         /* Program P-state weights to account for frequency power adjustment */
7042         for (i = 0; i < 16; i++) {
7043                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7044                 unsigned long freq = intel_pxfreq(pxvidfreq);
7045                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7046                         PXVFREQ_PX_SHIFT;
7047                 unsigned long val;
7048
7049                 val = vid * vid;
7050                 val *= (freq / 1000);
7051                 val *= 255;
7052                 val /= (127*127*900);
7053                 if (val > 0xff)
7054                         DRM_ERROR("bad pxval: %ld\n", val);
7055                 pxw[i] = val;
7056         }
7057         /* Render standby states get 0 weight */
7058         pxw[14] = 0;
7059         pxw[15] = 0;
7060
7061         for (i = 0; i < 4; i++) {
7062                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7063                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7064                 I915_WRITE(PXW + (i * 4), val);
7065         }
7066
7067         /* Adjust magic regs to magic values (more experimental results) */
7068         I915_WRITE(OGW0, 0);
7069         I915_WRITE(OGW1, 0);
7070         I915_WRITE(EG0, 0x00007f00);
7071         I915_WRITE(EG1, 0x0000000e);
7072         I915_WRITE(EG2, 0x000e0000);
7073         I915_WRITE(EG3, 0x68000300);
7074         I915_WRITE(EG4, 0x42000000);
7075         I915_WRITE(EG5, 0x00140031);
7076         I915_WRITE(EG6, 0);
7077         I915_WRITE(EG7, 0);
7078
7079         for (i = 0; i < 8; i++)
7080                 I915_WRITE(PXWL + (i * 4), 0);
7081
7082         /* Enable PMON + select events */
7083         I915_WRITE(ECR, 0x80000019);
7084
7085         lcfuse = I915_READ(LCFUSE02);
7086
7087         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7088 }
7089
7090 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7091 {
7092         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7093         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7094         u32 pcu_mbox, rc6_mask = 0;
7095         int cur_freq, min_freq, max_freq;
7096         int i;
7097
7098         /* Here begins a magic sequence of register writes to enable
7099          * auto-downclocking.
7100          *
7101          * Perhaps there might be some value in exposing these to
7102          * userspace...
7103          */
7104         I915_WRITE(GEN6_RC_STATE, 0);
7105         mutex_lock(&dev_priv->dev->struct_mutex);
7106         gen6_gt_force_wake_get(dev_priv);
7107
7108         /* disable the counters and set deterministic thresholds */
7109         I915_WRITE(GEN6_RC_CONTROL, 0);
7110
7111         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7112         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7113         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7114         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7115         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7116
7117         for (i = 0; i < I915_NUM_RINGS; i++)
7118                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7119
7120         I915_WRITE(GEN6_RC_SLEEP, 0);
7121         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7122         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7123         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7124         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7125
7126         if (i915_enable_rc6)
7127                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7128                         GEN6_RC_CTL_RC6_ENABLE;
7129
7130         I915_WRITE(GEN6_RC_CONTROL,
7131                    rc6_mask |
7132                    GEN6_RC_CTL_EI_MODE(1) |
7133                    GEN6_RC_CTL_HW_ENABLE);
7134
7135         I915_WRITE(GEN6_RPNSWREQ,
7136                    GEN6_FREQUENCY(10) |
7137                    GEN6_OFFSET(0) |
7138                    GEN6_AGGRESSIVE_TURBO);
7139         I915_WRITE(GEN6_RC_VIDEO_FREQ,
7140                    GEN6_FREQUENCY(12));
7141
7142         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7143         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7144                    18 << 24 |
7145                    6 << 16);
7146         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7147         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7148         I915_WRITE(GEN6_RP_UP_EI, 100000);
7149         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7150         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7151         I915_WRITE(GEN6_RP_CONTROL,
7152                    GEN6_RP_MEDIA_TURBO |
7153                    GEN6_RP_USE_NORMAL_FREQ |
7154                    GEN6_RP_MEDIA_IS_GFX |
7155                    GEN6_RP_ENABLE |
7156                    GEN6_RP_UP_BUSY_AVG |
7157                    GEN6_RP_DOWN_IDLE_CONT);
7158
7159         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7160                      500))
7161                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7162
7163         I915_WRITE(GEN6_PCODE_DATA, 0);
7164         I915_WRITE(GEN6_PCODE_MAILBOX,
7165                    GEN6_PCODE_READY |
7166                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7167         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7168                      500))
7169                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7170
7171         min_freq = (rp_state_cap & 0xff0000) >> 16;
7172         max_freq = rp_state_cap & 0xff;
7173         cur_freq = (gt_perf_status & 0xff00) >> 8;
7174
7175         /* Check for overclock support */
7176         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7177                      500))
7178                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7179         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7180         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7181         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7182                      500))
7183                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7184         if (pcu_mbox & (1<<31)) { /* OC supported */
7185                 max_freq = pcu_mbox & 0xff;
7186                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7187         }
7188
7189         /* In units of 100MHz */
7190         dev_priv->max_delay = max_freq;
7191         dev_priv->min_delay = min_freq;
7192         dev_priv->cur_delay = cur_freq;
7193
7194         /* requires MSI enabled */
7195         I915_WRITE(GEN6_PMIER,
7196                    GEN6_PM_MBOX_EVENT |
7197                    GEN6_PM_THERMAL_EVENT |
7198                    GEN6_PM_RP_DOWN_TIMEOUT |
7199                    GEN6_PM_RP_UP_THRESHOLD |
7200                    GEN6_PM_RP_DOWN_THRESHOLD |
7201                    GEN6_PM_RP_UP_EI_EXPIRED |
7202                    GEN6_PM_RP_DOWN_EI_EXPIRED);
7203         spin_lock_irq(&dev_priv->rps_lock);
7204         WARN_ON(dev_priv->pm_iir != 0);
7205         I915_WRITE(GEN6_PMIMR, 0);
7206         spin_unlock_irq(&dev_priv->rps_lock);
7207         /* enable all PM interrupts */
7208         I915_WRITE(GEN6_PMINTRMSK, 0);
7209
7210         gen6_gt_force_wake_put(dev_priv);
7211         mutex_unlock(&dev_priv->dev->struct_mutex);
7212 }
7213
7214 static void ironlake_init_clock_gating(struct drm_device *dev)
7215 {
7216         struct drm_i915_private *dev_priv = dev->dev_private;
7217         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7218
7219         /* Required for FBC */
7220         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7221                 DPFCRUNIT_CLOCK_GATE_DISABLE |
7222                 DPFDUNIT_CLOCK_GATE_DISABLE;
7223         /* Required for CxSR */
7224         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7225
7226         I915_WRITE(PCH_3DCGDIS0,
7227                    MARIUNIT_CLOCK_GATE_DISABLE |
7228                    SVSMUNIT_CLOCK_GATE_DISABLE);
7229         I915_WRITE(PCH_3DCGDIS1,
7230                    VFMUNIT_CLOCK_GATE_DISABLE);
7231
7232         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7233
7234         /*
7235          * According to the spec the following bits should be set in
7236          * order to enable memory self-refresh
7237          * The bit 22/21 of 0x42004
7238          * The bit 5 of 0x42020
7239          * The bit 15 of 0x45000
7240          */
7241         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7242                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
7243                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7244         I915_WRITE(ILK_DSPCLK_GATE,
7245                    (I915_READ(ILK_DSPCLK_GATE) |
7246                     ILK_DPARB_CLK_GATE));
7247         I915_WRITE(DISP_ARB_CTL,
7248                    (I915_READ(DISP_ARB_CTL) |
7249                     DISP_FBC_WM_DIS));
7250         I915_WRITE(WM3_LP_ILK, 0);
7251         I915_WRITE(WM2_LP_ILK, 0);
7252         I915_WRITE(WM1_LP_ILK, 0);
7253
7254         /*
7255          * Based on the document from hardware guys the following bits
7256          * should be set unconditionally in order to enable FBC.
7257          * The bit 22 of 0x42000
7258          * The bit 22 of 0x42004
7259          * The bit 7,8,9 of 0x42020.
7260          */
7261         if (IS_IRONLAKE_M(dev)) {
7262                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7263                            I915_READ(ILK_DISPLAY_CHICKEN1) |
7264                            ILK_FBCQ_DIS);
7265                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7266                            I915_READ(ILK_DISPLAY_CHICKEN2) |
7267                            ILK_DPARB_GATE);
7268                 I915_WRITE(ILK_DSPCLK_GATE,
7269                            I915_READ(ILK_DSPCLK_GATE) |
7270                            ILK_DPFC_DIS1 |
7271                            ILK_DPFC_DIS2 |
7272                            ILK_CLK_FBC);
7273         }
7274
7275         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7276                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7277                    ILK_ELPIN_409_SELECT);
7278         I915_WRITE(_3D_CHICKEN2,
7279                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7280                    _3D_CHICKEN2_WM_READ_PIPELINED);
7281 }
7282
7283 static void gen6_init_clock_gating(struct drm_device *dev)
7284 {
7285         struct drm_i915_private *dev_priv = dev->dev_private;
7286         int pipe;
7287         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7288
7289         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7290
7291         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7292                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7293                    ILK_ELPIN_409_SELECT);
7294
7295         I915_WRITE(WM3_LP_ILK, 0);
7296         I915_WRITE(WM2_LP_ILK, 0);
7297         I915_WRITE(WM1_LP_ILK, 0);
7298
7299         /*
7300          * According to the spec the following bits should be
7301          * set in order to enable memory self-refresh and fbc:
7302          * The bit21 and bit22 of 0x42000
7303          * The bit21 and bit22 of 0x42004
7304          * The bit5 and bit7 of 0x42020
7305          * The bit14 of 0x70180
7306          * The bit14 of 0x71180
7307          */
7308         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7309                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7310                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7311         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7312                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7313                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7314         I915_WRITE(ILK_DSPCLK_GATE,
7315                    I915_READ(ILK_DSPCLK_GATE) |
7316                    ILK_DPARB_CLK_GATE  |
7317                    ILK_DPFD_CLK_GATE);
7318
7319         for_each_pipe(pipe)
7320                 I915_WRITE(DSPCNTR(pipe),
7321                            I915_READ(DSPCNTR(pipe)) |
7322                            DISPPLANE_TRICKLE_FEED_DISABLE);
7323 }
7324
7325 static void ivybridge_init_clock_gating(struct drm_device *dev)
7326 {
7327         struct drm_i915_private *dev_priv = dev->dev_private;
7328         int pipe;
7329         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7330
7331         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7332
7333         I915_WRITE(WM3_LP_ILK, 0);
7334         I915_WRITE(WM2_LP_ILK, 0);
7335         I915_WRITE(WM1_LP_ILK, 0);
7336
7337         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7338
7339         for_each_pipe(pipe)
7340                 I915_WRITE(DSPCNTR(pipe),
7341                            I915_READ(DSPCNTR(pipe)) |
7342                            DISPPLANE_TRICKLE_FEED_DISABLE);
7343 }
7344
7345 static void g4x_init_clock_gating(struct drm_device *dev)
7346 {
7347         struct drm_i915_private *dev_priv = dev->dev_private;
7348         uint32_t dspclk_gate;
7349
7350         I915_WRITE(RENCLK_GATE_D1, 0);
7351         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7352                    GS_UNIT_CLOCK_GATE_DISABLE |
7353                    CL_UNIT_CLOCK_GATE_DISABLE);
7354         I915_WRITE(RAMCLK_GATE_D, 0);
7355         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7356                 OVRUNIT_CLOCK_GATE_DISABLE |
7357                 OVCUNIT_CLOCK_GATE_DISABLE;
7358         if (IS_GM45(dev))
7359                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7360         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7361 }
7362
7363 static void crestline_init_clock_gating(struct drm_device *dev)
7364 {
7365         struct drm_i915_private *dev_priv = dev->dev_private;
7366
7367         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7368         I915_WRITE(RENCLK_GATE_D2, 0);
7369         I915_WRITE(DSPCLK_GATE_D, 0);
7370         I915_WRITE(RAMCLK_GATE_D, 0);
7371         I915_WRITE16(DEUC, 0);
7372 }
7373
7374 static void broadwater_init_clock_gating(struct drm_device *dev)
7375 {
7376         struct drm_i915_private *dev_priv = dev->dev_private;
7377
7378         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7379                    I965_RCC_CLOCK_GATE_DISABLE |
7380                    I965_RCPB_CLOCK_GATE_DISABLE |
7381                    I965_ISC_CLOCK_GATE_DISABLE |
7382                    I965_FBC_CLOCK_GATE_DISABLE);
7383         I915_WRITE(RENCLK_GATE_D2, 0);
7384 }
7385
7386 static void gen3_init_clock_gating(struct drm_device *dev)
7387 {
7388         struct drm_i915_private *dev_priv = dev->dev_private;
7389         u32 dstate = I915_READ(D_STATE);
7390
7391         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7392                 DSTATE_DOT_CLOCK_GATING;
7393         I915_WRITE(D_STATE, dstate);
7394 }
7395
7396 static void i85x_init_clock_gating(struct drm_device *dev)
7397 {
7398         struct drm_i915_private *dev_priv = dev->dev_private;
7399
7400         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7401 }
7402
7403 static void i830_init_clock_gating(struct drm_device *dev)
7404 {
7405         struct drm_i915_private *dev_priv = dev->dev_private;
7406
7407         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7408 }
7409
7410 static void ibx_init_clock_gating(struct drm_device *dev)
7411 {
7412         struct drm_i915_private *dev_priv = dev->dev_private;
7413
7414         /*
7415          * On Ibex Peak and Cougar Point, we need to disable clock
7416          * gating for the panel power sequencer or it will fail to
7417          * start up when no ports are active.
7418          */
7419         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7420 }
7421
7422 static void cpt_init_clock_gating(struct drm_device *dev)
7423 {
7424         struct drm_i915_private *dev_priv = dev->dev_private;
7425
7426         /*
7427          * On Ibex Peak and Cougar Point, we need to disable clock
7428          * gating for the panel power sequencer or it will fail to
7429          * start up when no ports are active.
7430          */
7431         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7432         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7433                    DPLS_EDP_PPS_FIX_DIS);
7434 }
7435
7436 static void ironlake_teardown_rc6(struct drm_device *dev)
7437 {
7438         struct drm_i915_private *dev_priv = dev->dev_private;
7439
7440         if (dev_priv->renderctx) {
7441                 i915_gem_object_unpin(dev_priv->renderctx);
7442                 drm_gem_object_unreference(&dev_priv->renderctx->base);
7443                 dev_priv->renderctx = NULL;
7444         }
7445
7446         if (dev_priv->pwrctx) {
7447                 i915_gem_object_unpin(dev_priv->pwrctx);
7448                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7449                 dev_priv->pwrctx = NULL;
7450         }
7451 }
7452
7453 static void ironlake_disable_rc6(struct drm_device *dev)
7454 {
7455         struct drm_i915_private *dev_priv = dev->dev_private;
7456
7457         if (I915_READ(PWRCTXA)) {
7458                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7459                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7460                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7461                          50);
7462
7463                 I915_WRITE(PWRCTXA, 0);
7464                 POSTING_READ(PWRCTXA);
7465
7466                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7467                 POSTING_READ(RSTDBYCTL);
7468         }
7469
7470         ironlake_teardown_rc6(dev);
7471 }
7472
7473 static int ironlake_setup_rc6(struct drm_device *dev)
7474 {
7475         struct drm_i915_private *dev_priv = dev->dev_private;
7476
7477         if (dev_priv->renderctx == NULL)
7478                 dev_priv->renderctx = intel_alloc_context_page(dev);
7479         if (!dev_priv->renderctx)
7480                 return -ENOMEM;
7481
7482         if (dev_priv->pwrctx == NULL)
7483                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7484         if (!dev_priv->pwrctx) {
7485                 ironlake_teardown_rc6(dev);
7486                 return -ENOMEM;
7487         }
7488
7489         return 0;
7490 }
7491
7492 void ironlake_enable_rc6(struct drm_device *dev)
7493 {
7494         struct drm_i915_private *dev_priv = dev->dev_private;
7495         int ret;
7496
7497         /* rc6 disabled by default due to repeated reports of hanging during
7498          * boot and resume.
7499          */
7500         if (!i915_enable_rc6)
7501                 return;
7502
7503         mutex_lock(&dev->struct_mutex);
7504         ret = ironlake_setup_rc6(dev);
7505         if (ret) {
7506                 mutex_unlock(&dev->struct_mutex);
7507                 return;
7508         }
7509
7510         /*
7511          * GPU can automatically power down the render unit if given a page
7512          * to save state.
7513          */
7514         ret = BEGIN_LP_RING(6);
7515         if (ret) {
7516                 ironlake_teardown_rc6(dev);
7517                 mutex_unlock(&dev->struct_mutex);
7518                 return;
7519         }
7520
7521         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7522         OUT_RING(MI_SET_CONTEXT);
7523         OUT_RING(dev_priv->renderctx->gtt_offset |
7524                  MI_MM_SPACE_GTT |
7525                  MI_SAVE_EXT_STATE_EN |
7526                  MI_RESTORE_EXT_STATE_EN |
7527                  MI_RESTORE_INHIBIT);
7528         OUT_RING(MI_SUSPEND_FLUSH);
7529         OUT_RING(MI_NOOP);
7530         OUT_RING(MI_FLUSH);
7531         ADVANCE_LP_RING();
7532
7533         /*
7534          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7535          * does an implicit flush, combined with MI_FLUSH above, it should be
7536          * safe to assume that renderctx is valid
7537          */
7538         ret = intel_wait_ring_idle(LP_RING(dev_priv));
7539         if (ret) {
7540                 DRM_ERROR("failed to enable ironlake power power savings\n");
7541                 ironlake_teardown_rc6(dev);
7542                 mutex_unlock(&dev->struct_mutex);
7543                 return;
7544         }
7545
7546         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7547         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7548         mutex_unlock(&dev->struct_mutex);
7549 }
7550
7551 void intel_init_clock_gating(struct drm_device *dev)
7552 {
7553         struct drm_i915_private *dev_priv = dev->dev_private;
7554
7555         dev_priv->display.init_clock_gating(dev);
7556
7557         if (dev_priv->display.init_pch_clock_gating)
7558                 dev_priv->display.init_pch_clock_gating(dev);
7559 }
7560
7561 /* Set up chip specific display functions */
7562 static void intel_init_display(struct drm_device *dev)
7563 {
7564         struct drm_i915_private *dev_priv = dev->dev_private;
7565
7566         /* We always want a DPMS function */
7567         if (HAS_PCH_SPLIT(dev)) {
7568                 dev_priv->display.dpms = ironlake_crtc_dpms;
7569                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7570         } else {
7571                 dev_priv->display.dpms = i9xx_crtc_dpms;
7572                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7573         }
7574
7575         if (I915_HAS_FBC(dev)) {
7576                 if (HAS_PCH_SPLIT(dev)) {
7577                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7578                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
7579                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
7580                 } else if (IS_GM45(dev)) {
7581                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7582                         dev_priv->display.enable_fbc = g4x_enable_fbc;
7583                         dev_priv->display.disable_fbc = g4x_disable_fbc;
7584                 } else if (IS_CRESTLINE(dev)) {
7585                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7586                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
7587                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
7588                 }
7589                 /* 855GM needs testing */
7590         }
7591
7592         /* Returns the core display clock speed */
7593         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7594                 dev_priv->display.get_display_clock_speed =
7595                         i945_get_display_clock_speed;
7596         else if (IS_I915G(dev))
7597                 dev_priv->display.get_display_clock_speed =
7598                         i915_get_display_clock_speed;
7599         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7600                 dev_priv->display.get_display_clock_speed =
7601                         i9xx_misc_get_display_clock_speed;
7602         else if (IS_I915GM(dev))
7603                 dev_priv->display.get_display_clock_speed =
7604                         i915gm_get_display_clock_speed;
7605         else if (IS_I865G(dev))
7606                 dev_priv->display.get_display_clock_speed =
7607                         i865_get_display_clock_speed;
7608         else if (IS_I85X(dev))
7609                 dev_priv->display.get_display_clock_speed =
7610                         i855_get_display_clock_speed;
7611         else /* 852, 830 */
7612                 dev_priv->display.get_display_clock_speed =
7613                         i830_get_display_clock_speed;
7614
7615         /* For FIFO watermark updates */
7616         if (HAS_PCH_SPLIT(dev)) {
7617                 if (HAS_PCH_IBX(dev))
7618                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7619                 else if (HAS_PCH_CPT(dev))
7620                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7621
7622                 if (IS_GEN5(dev)) {
7623                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7624                                 dev_priv->display.update_wm = ironlake_update_wm;
7625                         else {
7626                                 DRM_DEBUG_KMS("Failed to get proper latency. "
7627                                               "Disable CxSR\n");
7628                                 dev_priv->display.update_wm = NULL;
7629                         }
7630                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7631                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7632                 } else if (IS_GEN6(dev)) {
7633                         if (SNB_READ_WM0_LATENCY()) {
7634                                 dev_priv->display.update_wm = sandybridge_update_wm;
7635                         } else {
7636                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7637                                               "Disable CxSR\n");
7638                                 dev_priv->display.update_wm = NULL;
7639                         }
7640                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7641                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7642                 } else if (IS_IVYBRIDGE(dev)) {
7643                         /* FIXME: detect B0+ stepping and use auto training */
7644                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7645                         if (SNB_READ_WM0_LATENCY()) {
7646                                 dev_priv->display.update_wm = sandybridge_update_wm;
7647                         } else {
7648                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7649                                               "Disable CxSR\n");
7650                                 dev_priv->display.update_wm = NULL;
7651                         }
7652                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7653
7654                 } else
7655                         dev_priv->display.update_wm = NULL;
7656         } else if (IS_PINEVIEW(dev)) {
7657                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7658                                             dev_priv->is_ddr3,
7659                                             dev_priv->fsb_freq,
7660                                             dev_priv->mem_freq)) {
7661                         DRM_INFO("failed to find known CxSR latency "
7662                                  "(found ddr%s fsb freq %d, mem freq %d), "
7663                                  "disabling CxSR\n",
7664                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
7665                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7666                         /* Disable CxSR and never update its watermark again */
7667                         pineview_disable_cxsr(dev);
7668                         dev_priv->display.update_wm = NULL;
7669                 } else
7670                         dev_priv->display.update_wm = pineview_update_wm;
7671         } else if (IS_G4X(dev)) {
7672                 dev_priv->display.update_wm = g4x_update_wm;
7673                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7674         } else if (IS_GEN4(dev)) {
7675                 dev_priv->display.update_wm = i965_update_wm;
7676                 if (IS_CRESTLINE(dev))
7677                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7678                 else if (IS_BROADWATER(dev))
7679                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7680         } else if (IS_GEN3(dev)) {
7681                 dev_priv->display.update_wm = i9xx_update_wm;
7682                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7683                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7684         } else if (IS_I865G(dev)) {
7685                 dev_priv->display.update_wm = i830_update_wm;
7686                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7687                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7688         } else if (IS_I85X(dev)) {
7689                 dev_priv->display.update_wm = i9xx_update_wm;
7690                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7691                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7692         } else {
7693                 dev_priv->display.update_wm = i830_update_wm;
7694                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7695                 if (IS_845G(dev))
7696                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7697                 else
7698                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7699         }
7700 }
7701
7702 /*
7703  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7704  * resume, or other times.  This quirk makes sure that's the case for
7705  * affected systems.
7706  */
7707 static void quirk_pipea_force (struct drm_device *dev)
7708 {
7709         struct drm_i915_private *dev_priv = dev->dev_private;
7710
7711         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7712         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7713 }
7714
7715 struct intel_quirk {
7716         int device;
7717         int subsystem_vendor;
7718         int subsystem_device;
7719         void (*hook)(struct drm_device *dev);
7720 };
7721
7722 struct intel_quirk intel_quirks[] = {
7723         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7724         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7725         /* HP Mini needs pipe A force quirk (LP: #322104) */
7726         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7727
7728         /* Thinkpad R31 needs pipe A force quirk */
7729         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7730         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7731         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7732
7733         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7734         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
7735         /* ThinkPad X40 needs pipe A force quirk */
7736
7737         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7738         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7739
7740         /* 855 & before need to leave pipe A & dpll A up */
7741         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7742         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7743 };
7744
7745 static void intel_init_quirks(struct drm_device *dev)
7746 {
7747         struct pci_dev *d = dev->pdev;
7748         int i;
7749
7750         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7751                 struct intel_quirk *q = &intel_quirks[i];
7752
7753                 if (d->device == q->device &&
7754                     (d->subsystem_vendor == q->subsystem_vendor ||
7755                      q->subsystem_vendor == PCI_ANY_ID) &&
7756                     (d->subsystem_device == q->subsystem_device ||
7757                      q->subsystem_device == PCI_ANY_ID))
7758                         q->hook(dev);
7759         }
7760 }
7761
7762 /* Disable the VGA plane that we never use */
7763 static void i915_disable_vga(struct drm_device *dev)
7764 {
7765         struct drm_i915_private *dev_priv = dev->dev_private;
7766         u8 sr1;
7767         u32 vga_reg;
7768
7769         if (HAS_PCH_SPLIT(dev))
7770                 vga_reg = CPU_VGACNTRL;
7771         else
7772                 vga_reg = VGACNTRL;
7773
7774         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7775         outb(1, VGA_SR_INDEX);
7776         sr1 = inb(VGA_SR_DATA);
7777         outb(sr1 | 1<<5, VGA_SR_DATA);
7778         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7779         udelay(300);
7780
7781         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7782         POSTING_READ(vga_reg);
7783 }
7784
7785 void intel_modeset_init(struct drm_device *dev)
7786 {
7787         struct drm_i915_private *dev_priv = dev->dev_private;
7788         int i;
7789
7790         drm_mode_config_init(dev);
7791
7792         dev->mode_config.min_width = 0;
7793         dev->mode_config.min_height = 0;
7794
7795         dev->mode_config.funcs = (void *)&intel_mode_funcs;
7796
7797         intel_init_quirks(dev);
7798
7799         intel_init_display(dev);
7800
7801         if (IS_GEN2(dev)) {
7802                 dev->mode_config.max_width = 2048;
7803                 dev->mode_config.max_height = 2048;
7804         } else if (IS_GEN3(dev)) {
7805                 dev->mode_config.max_width = 4096;
7806                 dev->mode_config.max_height = 4096;
7807         } else {
7808                 dev->mode_config.max_width = 8192;
7809                 dev->mode_config.max_height = 8192;
7810         }
7811         dev->mode_config.fb_base = dev->agp->base;
7812
7813         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7814                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7815
7816         for (i = 0; i < dev_priv->num_pipe; i++) {
7817                 intel_crtc_init(dev, i);
7818         }
7819
7820         /* Just disable it once at startup */
7821         i915_disable_vga(dev);
7822         intel_setup_outputs(dev);
7823
7824         intel_init_clock_gating(dev);
7825
7826         if (IS_IRONLAKE_M(dev)) {
7827                 ironlake_enable_drps(dev);
7828                 intel_init_emon(dev);
7829         }
7830
7831         if (IS_GEN6(dev))
7832                 gen6_enable_rps(dev_priv);
7833
7834         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7835         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7836                     (unsigned long)dev);
7837 }
7838
7839 void intel_modeset_gem_init(struct drm_device *dev)
7840 {
7841         if (IS_IRONLAKE_M(dev))
7842                 ironlake_enable_rc6(dev);
7843
7844         intel_setup_overlay(dev);
7845 }
7846
7847 void intel_modeset_cleanup(struct drm_device *dev)
7848 {
7849         struct drm_i915_private *dev_priv = dev->dev_private;
7850         struct drm_crtc *crtc;
7851         struct intel_crtc *intel_crtc;
7852
7853         drm_kms_helper_poll_fini(dev);
7854         mutex_lock(&dev->struct_mutex);
7855
7856         intel_unregister_dsm_handler();
7857
7858
7859         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7860                 /* Skip inactive CRTCs */
7861                 if (!crtc->fb)
7862                         continue;
7863
7864                 intel_crtc = to_intel_crtc(crtc);
7865                 intel_increase_pllclock(crtc);
7866         }
7867
7868         if (dev_priv->display.disable_fbc)
7869                 dev_priv->display.disable_fbc(dev);
7870
7871         if (IS_IRONLAKE_M(dev))
7872                 ironlake_disable_drps(dev);
7873         if (IS_GEN6(dev))
7874                 gen6_disable_rps(dev);
7875
7876         if (IS_IRONLAKE_M(dev))
7877                 ironlake_disable_rc6(dev);
7878
7879         mutex_unlock(&dev->struct_mutex);
7880
7881         /* Disable the irq before mode object teardown, for the irq might
7882          * enqueue unpin/hotplug work. */
7883         drm_irq_uninstall(dev);
7884         cancel_work_sync(&dev_priv->hotplug_work);
7885
7886         /* Shut off idle work before the crtcs get freed. */
7887         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7888                 intel_crtc = to_intel_crtc(crtc);
7889                 del_timer_sync(&intel_crtc->idle_timer);
7890         }
7891         del_timer_sync(&dev_priv->idle_timer);
7892         cancel_work_sync(&dev_priv->idle_work);
7893
7894         drm_mode_config_cleanup(dev);
7895 }
7896
7897 /*
7898  * Return which encoder is currently attached for connector.
7899  */
7900 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7901 {
7902         return &intel_attached_encoder(connector)->base;
7903 }
7904
7905 void intel_connector_attach_encoder(struct intel_connector *connector,
7906                                     struct intel_encoder *encoder)
7907 {
7908         connector->encoder = encoder;
7909         drm_mode_connector_attach_encoder(&connector->base,
7910                                           &encoder->base);
7911 }
7912
7913 /*
7914  * set vga decode state - true == enable VGA decode
7915  */
7916 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7917 {
7918         struct drm_i915_private *dev_priv = dev->dev_private;
7919         u16 gmch_ctrl;
7920
7921         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7922         if (state)
7923                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7924         else
7925                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7926         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7927         return 0;
7928 }
7929
7930 #ifdef CONFIG_DEBUG_FS
7931 #include <linux/seq_file.h>
7932
7933 struct intel_display_error_state {
7934         struct intel_cursor_error_state {
7935                 u32 control;
7936                 u32 position;
7937                 u32 base;
7938                 u32 size;
7939         } cursor[2];
7940
7941         struct intel_pipe_error_state {
7942                 u32 conf;
7943                 u32 source;
7944
7945                 u32 htotal;
7946                 u32 hblank;
7947                 u32 hsync;
7948                 u32 vtotal;
7949                 u32 vblank;
7950                 u32 vsync;
7951         } pipe[2];
7952
7953         struct intel_plane_error_state {
7954                 u32 control;
7955                 u32 stride;
7956                 u32 size;
7957                 u32 pos;
7958                 u32 addr;
7959                 u32 surface;
7960                 u32 tile_offset;
7961         } plane[2];
7962 };
7963
7964 struct intel_display_error_state *
7965 intel_display_capture_error_state(struct drm_device *dev)
7966 {
7967         drm_i915_private_t *dev_priv = dev->dev_private;
7968         struct intel_display_error_state *error;
7969         int i;
7970
7971         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7972         if (error == NULL)
7973                 return NULL;
7974
7975         for (i = 0; i < 2; i++) {
7976                 error->cursor[i].control = I915_READ(CURCNTR(i));
7977                 error->cursor[i].position = I915_READ(CURPOS(i));
7978                 error->cursor[i].base = I915_READ(CURBASE(i));
7979
7980                 error->plane[i].control = I915_READ(DSPCNTR(i));
7981                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7982                 error->plane[i].size = I915_READ(DSPSIZE(i));
7983                 error->plane[i].pos= I915_READ(DSPPOS(i));
7984                 error->plane[i].addr = I915_READ(DSPADDR(i));
7985                 if (INTEL_INFO(dev)->gen >= 4) {
7986                         error->plane[i].surface = I915_READ(DSPSURF(i));
7987                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7988                 }
7989
7990                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7991                 error->pipe[i].source = I915_READ(PIPESRC(i));
7992                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7993                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7994                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7995                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7996                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7997                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7998         }
7999
8000         return error;
8001 }
8002
8003 void
8004 intel_display_print_error_state(struct seq_file *m,
8005                                 struct drm_device *dev,
8006                                 struct intel_display_error_state *error)
8007 {
8008         int i;
8009
8010         for (i = 0; i < 2; i++) {
8011                 seq_printf(m, "Pipe [%d]:\n", i);
8012                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8013                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8014                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8015                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8016                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8017                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8018                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8019                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8020
8021                 seq_printf(m, "Plane [%d]:\n", i);
8022                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8023                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8024                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8025                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8026                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8027                 if (INTEL_INFO(dev)->gen >= 4) {
8028                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8029                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8030                 }
8031
8032                 seq_printf(m, "Cursor [%d]:\n", i);
8033                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8034                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8035                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8036         }
8037 }
8038 #endif