drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static inline u32 /* units of 100MHz */
 102 intel_fdi_link_freq(struct drm_device *dev)
 103 {
 104         if (IS_GEN5(dev)) {
 105                 struct drm_i915_private *dev_priv = dev->dev_private;
 106                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 107         } else
 108                 return 27;
 109 }
 110
 111 static const intel_limit_t intel_limits_i8xx_dvo = {
 112         .dot = { .min = 25000, .max = 350000 },
 113         .vco = { .min = 930000, .max = 1400000 },
 114         .n = { .min = 3, .max = 16 },
 115         .m = { .min = 96, .max = 140 },
 116         .m1 = { .min = 18, .max = 26 },
 117         .m2 = { .min = 6, .max = 16 },
 118         .p = { .min = 4, .max = 128 },
 119         .p1 = { .min = 2, .max = 33 },
 120         .p2 = { .dot_limit = 165000,
 121                 .p2_slow = 4, .p2_fast = 2 },
 122         .find_pll = intel_find_best_PLL,
 123 };
 124
 125 static const intel_limit_t intel_limits_i8xx_lvds = {
 126         .dot = { .min = 25000, .max = 350000 },
 127         .vco = { .min = 930000, .max = 1400000 },
 128         .n = { .min = 3, .max = 16 },
 129         .m = { .min = 96, .max = 140 },
 130         .m1 = { .min = 18, .max = 26 },
 131         .m2 = { .min = 6, .max = 16 },
 132         .p = { .min = 4, .max = 128 },
 133         .p1 = { .min = 1, .max = 6 },
 134         .p2 = { .dot_limit = 165000,
 135                 .p2_slow = 14, .p2_fast = 7 },
 136         .find_pll = intel_find_best_PLL,
 137 };
 138
 139 static const intel_limit_t intel_limits_i9xx_sdvo = {
 140         .dot = { .min = 20000, .max = 400000 },
 141         .vco = { .min = 1400000, .max = 2800000 },
 142         .n = { .min = 1, .max = 6 },
 143         .m = { .min = 70, .max = 120 },
 144         .m1 = { .min = 10, .max = 22 },
 145         .m2 = { .min = 5, .max = 9 },
 146         .p = { .min = 5, .max = 80 },
 147         .p1 = { .min = 1, .max = 8 },
 148         .p2 = { .dot_limit = 200000,
 149                 .p2_slow = 10, .p2_fast = 5 },
 150         .find_pll = intel_find_best_PLL,
 151 };
 152
 153 static const intel_limit_t intel_limits_i9xx_lvds = {
 154         .dot = { .min = 20000, .max = 400000 },
 155         .vco = { .min = 1400000, .max = 2800000 },
 156         .n = { .min = 1, .max = 6 },
 157         .m = { .min = 70, .max = 120 },
 158         .m1 = { .min = 10, .max = 22 },
 159         .m2 = { .min = 5, .max = 9 },
 160         .p = { .min = 7, .max = 98 },
 161         .p1 = { .min = 1, .max = 8 },
 162         .p2 = { .dot_limit = 112000,
 163                 .p2_slow = 14, .p2_fast = 7 },
 164         .find_pll = intel_find_best_PLL,
 165 };
 166
 167
 168 static const intel_limit_t intel_limits_g4x_sdvo = {
 169         .dot = { .min = 25000, .max = 270000 },
 170         .vco = { .min = 1750000, .max = 3500000},
 171         .n = { .min = 1, .max = 4 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 10, .max = 30 },
 176         .p1 = { .min = 1, .max = 3},
 177         .p2 = { .dot_limit = 270000,
 178                 .p2_slow = 10,
 179                 .p2_fast = 10
 180         },
 181         .find_pll = intel_g4x_find_best_PLL,
 182 };
 183
 184 static const intel_limit_t intel_limits_g4x_hdmi = {
 185         .dot = { .min = 22000, .max = 400000 },
 186         .vco = { .min = 1750000, .max = 3500000},
 187         .n = { .min = 1, .max = 4 },
 188         .m = { .min = 104, .max = 138 },
 189         .m1 = { .min = 16, .max = 23 },
 190         .m2 = { .min = 5, .max = 11 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8},
 193         .p2 = { .dot_limit = 165000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195         .find_pll = intel_g4x_find_best_PLL,
 196 };
 197
 198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 199         .dot = { .min = 20000, .max = 115000 },
 200         .vco = { .min = 1750000, .max = 3500000 },
 201         .n = { .min = 1, .max = 3 },
 202         .m = { .min = 104, .max = 138 },
 203         .m1 = { .min = 17, .max = 23 },
 204         .m2 = { .min = 5, .max = 11 },
 205         .p = { .min = 28, .max = 112 },
 206         .p1 = { .min = 2, .max = 8 },
 207         .p2 = { .dot_limit = 0,
 208                 .p2_slow = 14, .p2_fast = 14
 209         },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 214         .dot = { .min = 80000, .max = 224000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 14, .max = 42 },
 221         .p1 = { .min = 2, .max = 6 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 7, .p2_fast = 7
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_display_port = {
 229         .dot = { .min = 161670, .max = 227000 },
 230         .vco = { .min = 1750000, .max = 3500000},
 231         .n = { .min = 1, .max = 2 },
 232         .m = { .min = 97, .max = 108 },
 233         .m1 = { .min = 0x10, .max = 0x12 },
 234         .m2 = { .min = 0x05, .max = 0x06 },
 235         .p = { .min = 10, .max = 20 },
 236         .p1 = { .min = 1, .max = 2},
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 10, .p2_fast = 10 },
 239         .find_pll = intel_find_pll_g4x_dp,
 240 };
 241
 242 static const intel_limit_t intel_limits_pineview_sdvo = {
 243         .dot = { .min = 20000, .max = 400000},
 244         .vco = { .min = 1700000, .max = 3500000 },
 245         /* Pineview's Ncounter is a ring counter */
 246         .n = { .min = 3, .max = 6 },
 247         .m = { .min = 2, .max = 256 },
 248         /* Pineview only has one combined m divider, which we treat as m2. */
 249         .m1 = { .min = 0, .max = 0 },
 250         .m2 = { .min = 0, .max = 254 },
 251         .p = { .min = 5, .max = 80 },
 252         .p1 = { .min = 1, .max = 8 },
 253         .p2 = { .dot_limit = 200000,
 254                 .p2_slow = 10, .p2_fast = 5 },
 255         .find_pll = intel_find_best_PLL,
 256 };
 257
 258 static const intel_limit_t intel_limits_pineview_lvds = {
 259         .dot = { .min = 20000, .max = 400000 },
 260         .vco = { .min = 1700000, .max = 3500000 },
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         .m1 = { .min = 0, .max = 0 },
 264         .m2 = { .min = 0, .max = 254 },
 265         .p = { .min = 7, .max = 112 },
 266         .p1 = { .min = 1, .max = 8 },
 267         .p2 = { .dot_limit = 112000,
 268                 .p2_slow = 14, .p2_fast = 14 },
 269         .find_pll = intel_find_best_PLL,
 270 };
 271
 272 /* Ironlake / Sandybridge
 273  *
 274  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 275  * the range value for them is (actual_value - 2).
 276  */
 277 static const intel_limit_t intel_limits_ironlake_dac = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 1760000, .max = 3510000 },
 280         .n = { .min = 1, .max = 5 },
 281         .m = { .min = 79, .max = 127 },
 282         .m1 = { .min = 12, .max = 22 },
 283         .m2 = { .min = 5, .max = 9 },
 284         .p = { .min = 5, .max = 80 },
 285         .p1 = { .min = 1, .max = 8 },
 286         .p2 = { .dot_limit = 225000,
 287                 .p2_slow = 10, .p2_fast = 5 },
 288         .find_pll = intel_g4x_find_best_PLL,
 289 };
 290
 291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 292         .dot = { .min = 25000, .max = 350000 },
 293         .vco = { .min = 1760000, .max = 3510000 },
 294         .n = { .min = 1, .max = 3 },
 295         .m = { .min = 79, .max = 118 },
 296         .m1 = { .min = 12, .max = 22 },
 297         .m2 = { .min = 5, .max = 9 },
 298         .p = { .min = 28, .max = 112 },
 299         .p1 = { .min = 2, .max = 8 },
 300         .p2 = { .dot_limit = 225000,
 301                 .p2_slow = 14, .p2_fast = 14 },
 302         .find_pll = intel_g4x_find_best_PLL,
 303 };
 304
 305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 3 },
 309         .m = { .min = 79, .max = 127 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 14, .max = 56 },
 313         .p1 = { .min = 2, .max = 8 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 7, .p2_fast = 7 },
 316         .find_pll = intel_g4x_find_best_PLL,
 317 };
 318
 319 /* LVDS 100mhz refclk limits. */
 320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 2 },
 324         .m = { .min = 79, .max = 126 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 14, .p2_fast = 14 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 335         .dot = { .min = 25000, .max = 350000 },
 336         .vco = { .min = 1760000, .max = 3510000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 79, .max = 126 },
 339         .m1 = { .min = 12, .max = 22 },
 340         .m2 = { .min = 5, .max = 9 },
 341         .p = { .min = 14, .max = 42 },
 342         .p1 = { .min = 2, .max = 6 },
 343         .p2 = { .dot_limit = 225000,
 344                 .p2_slow = 7, .p2_fast = 7 },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 static const intel_limit_t intel_limits_ironlake_display_port = {
 349         .dot = { .min = 25000, .max = 350000 },
 350         .vco = { .min = 1760000, .max = 3510000},
 351         .n = { .min = 1, .max = 2 },
 352         .m = { .min = 81, .max = 90 },
 353         .m1 = { .min = 12, .max = 22 },
 354         .m2 = { .min = 5, .max = 9 },
 355         .p = { .min = 10, .max = 20 },
 356         .p1 = { .min = 1, .max = 2},
 357         .p2 = { .dot_limit = 0,
 358                 .p2_slow = 10, .p2_fast = 10 },
 359         .find_pll = intel_find_pll_ironlake_dp,
 360 };
 361
 362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 363 {
 364         unsigned long flags;
 365         u32 val = 0;
 366
 367         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 368         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 369                 DRM_ERROR("DPIO idle wait timed out\n");
 370                 goto out_unlock;
 371         }
 372
 373         I915_WRITE(DPIO_REG, reg);
 374         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 375                    DPIO_BYTE);
 376         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 377                 DRM_ERROR("DPIO read wait timed out\n");
 378                 goto out_unlock;
 379         }
 380         val = I915_READ(DPIO_DATA);
 381
 382 out_unlock:
 383         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 384         return val;
 385 }
 386
 387 static void vlv_init_dpio(struct drm_device *dev)
 388 {
 389         struct drm_i915_private *dev_priv = dev->dev_private;
 390
 391         /* Reset the DPIO config */
 392         I915_WRITE(DPIO_CTL, 0);
 393         POSTING_READ(DPIO_CTL);
 394         I915_WRITE(DPIO_CTL, 1);
 395         POSTING_READ(DPIO_CTL);
 396 }
 397
 398 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 399 {
 400         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 401         return 1;
 402 }
 403
 404 static const struct dmi_system_id intel_dual_link_lvds[] = {
 405         {
 406                 .callback = intel_dual_link_lvds_callback,
 407                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 408                 .matches = {
 409                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 410                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 411                 },
 412         },
 413         { }     /* terminating entry */
 414 };
 415
 416 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 417                               unsigned int reg)
 418 {
 419         unsigned int val;
 420
 421         /* use the module option value if specified */
 422         if (i915_lvds_channel_mode > 0)
 423                 return i915_lvds_channel_mode == 2;
 424
 425         if (dmi_check_system(intel_dual_link_lvds))
 426                 return true;
 427
 428         if (dev_priv->lvds_val)
 429                 val = dev_priv->lvds_val;
 430         else {
 431                 /* BIOS should set the proper LVDS register value at boot, but
 432                  * in reality, it doesn't set the value when the lid is closed;
 433                  * we need to check "the value to be set" in VBT when LVDS
 434                  * register is uninitialized.
 435                  */
 436                 val = I915_READ(reg);
 437                 if (!(val & ~LVDS_DETECTED))
 438                         val = dev_priv->bios_lvds_val;
 439                 dev_priv->lvds_val = val;
 440         }
 441         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 442 }
 443
 444 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 445                                                 int refclk)
 446 {
 447         struct drm_device *dev = crtc->dev;
 448         struct drm_i915_private *dev_priv = dev->dev_private;
 449         const intel_limit_t *limit;
 450
 451         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 452                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 453                         /* LVDS dual channel */
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_dual_lvds;
 458                 } else {
 459                         if (refclk == 100000)
 460                                 limit = &intel_limits_ironlake_single_lvds_100m;
 461                         else
 462                                 limit = &intel_limits_ironlake_single_lvds;
 463                 }
 464         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 465                         HAS_eDP)
 466                 limit = &intel_limits_ironlake_display_port;
 467         else
 468                 limit = &intel_limits_ironlake_dac;
 469
 470         return limit;
 471 }
 472
 473 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 474 {
 475         struct drm_device *dev = crtc->dev;
 476         struct drm_i915_private *dev_priv = dev->dev_private;
 477         const intel_limit_t *limit;
 478
 479         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 480                 if (is_dual_link_lvds(dev_priv, LVDS))
 481                         /* LVDS with dual channel */
 482                         limit = &intel_limits_g4x_dual_channel_lvds;
 483                 else
 484                         /* LVDS with dual channel */
 485                         limit = &intel_limits_g4x_single_channel_lvds;
 486         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 487                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 488                 limit = &intel_limits_g4x_hdmi;
 489         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 490                 limit = &intel_limits_g4x_sdvo;
 491         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 492                 limit = &intel_limits_g4x_display_port;
 493         } else /* The option is for other outputs */
 494                 limit = &intel_limits_i9xx_sdvo;
 495
 496         return limit;
 497 }
 498
 499 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 500 {
 501         struct drm_device *dev = crtc->dev;
 502         const intel_limit_t *limit;
 503
 504         if (HAS_PCH_SPLIT(dev))
 505                 limit = intel_ironlake_limit(crtc, refclk);
 506         else if (IS_G4X(dev)) {
 507                 limit = intel_g4x_limit(crtc);
 508         } else if (IS_PINEVIEW(dev)) {
 509                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 510                         limit = &intel_limits_pineview_lvds;
 511                 else
 512                         limit = &intel_limits_pineview_sdvo;
 513         } else if (!IS_GEN2(dev)) {
 514                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 515                         limit = &intel_limits_i9xx_lvds;
 516                 else
 517                         limit = &intel_limits_i9xx_sdvo;
 518         } else {
 519                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 520                         limit = &intel_limits_i8xx_lvds;
 521                 else
 522                         limit = &intel_limits_i8xx_dvo;
 523         }
 524         return limit;
 525 }
 526
 527 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 528 static void pineview_clock(int refclk, intel_clock_t *clock)
 529 {
 530         clock->m = clock->m2 + 2;
 531         clock->p = clock->p1 * clock->p2;
 532         clock->vco = refclk * clock->m / clock->n;
 533         clock->dot = clock->vco / clock->p;
 534 }
 535
 536 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 537 {
 538         if (IS_PINEVIEW(dev)) {
 539                 pineview_clock(refclk, clock);
 540                 return;
 541         }
 542         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 543         clock->p = clock->p1 * clock->p2;
 544         clock->vco = refclk * clock->m / (clock->n + 2);
 545         clock->dot = clock->vco / clock->p;
 546 }
 547
 548 /**
 549  * Returns whether any output on the specified pipe is of the specified type
 550  */
 551 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 552 {
 553         struct drm_device *dev = crtc->dev;
 554         struct drm_mode_config *mode_config = &dev->mode_config;
 555         struct intel_encoder *encoder;
 556
 557         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 558                 if (encoder->base.crtc == crtc && encoder->type == type)
 559                         return true;
 560
 561         return false;
 562 }
 563
 564 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 565 /**
 566  * Returns whether the given set of divisors are valid for a given refclk with
 567  * the given connectors.
 568  */
 569
 570 static bool intel_PLL_is_valid(struct drm_device *dev,
 571                                const intel_limit_t *limit,
 572                                const intel_clock_t *clock)
 573 {
 574         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 575                 INTELPllInvalid("p1 out of range\n");
 576         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 577                 INTELPllInvalid("p out of range\n");
 578         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 579                 INTELPllInvalid("m2 out of range\n");
 580         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 581                 INTELPllInvalid("m1 out of range\n");
 582         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 583                 INTELPllInvalid("m1 <= m2\n");
 584         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 585                 INTELPllInvalid("m out of range\n");
 586         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 587                 INTELPllInvalid("n out of range\n");
 588         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 589                 INTELPllInvalid("vco out of range\n");
 590         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 591          * connector, etc., rather than just a single range.
 592          */
 593         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 594                 INTELPllInvalid("dot out of range\n");
 595
 596         return true;
 597 }
 598
 599 static bool
 600 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 601                     int target, int refclk, intel_clock_t *match_clock,
 602                     intel_clock_t *best_clock)
 603
 604 {
 605         struct drm_device *dev = crtc->dev;
 606         struct drm_i915_private *dev_priv = dev->dev_private;
 607         intel_clock_t clock;
 608         int err = target;
 609
 610         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 611             (I915_READ(LVDS)) != 0) {
 612                 /*
 613                  * For LVDS, if the panel is on, just rely on its current
 614                  * settings for dual-channel.  We haven't figured out how to
 615                  * reliably set up different single/dual channel state, if we
 616                  * even can.
 617                  */
 618                 if (is_dual_link_lvds(dev_priv, LVDS))
 619                         clock.p2 = limit->p2.p2_fast;
 620                 else
 621                         clock.p2 = limit->p2.p2_slow;
 622         } else {
 623                 if (target < limit->p2.dot_limit)
 624                         clock.p2 = limit->p2.p2_slow;
 625                 else
 626                         clock.p2 = limit->p2.p2_fast;
 627         }
 628
 629         memset(best_clock, 0, sizeof(*best_clock));
 630
 631         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 632              clock.m1++) {
 633                 for (clock.m2 = limit->m2.min;
 634                      clock.m2 <= limit->m2.max; clock.m2++) {
 635                         /* m1 is always 0 in Pineview */
 636                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 637                                 break;
 638                         for (clock.n = limit->n.min;
 639                              clock.n <= limit->n.max; clock.n++) {
 640                                 for (clock.p1 = limit->p1.min;
 641                                         clock.p1 <= limit->p1.max; clock.p1++) {
 642                                         int this_err;
 643
 644                                         intel_clock(dev, refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648                                         if (match_clock &&
 649                                             clock.p != match_clock->p)
 650                                                 continue;
 651
 652                                         this_err = abs(clock.dot - target);
 653                                         if (this_err < err) {
 654                                                 *best_clock = clock;
 655                                                 err = this_err;
 656                                         }
 657                                 }
 658                         }
 659                 }
 660         }
 661
 662         return (err != target);
 663 }
 664
 665 static bool
 666 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 667                         int target, int refclk, intel_clock_t *match_clock,
 668                         intel_clock_t *best_clock)
 669 {
 670         struct drm_device *dev = crtc->dev;
 671         struct drm_i915_private *dev_priv = dev->dev_private;
 672         intel_clock_t clock;
 673         int max_n;
 674         bool found;
 675         /* approximately equals target * 0.00585 */
 676         int err_most = (target >> 8) + (target >> 9);
 677         found = false;
 678
 679         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 680                 int lvds_reg;
 681
 682                 if (HAS_PCH_SPLIT(dev))
 683                         lvds_reg = PCH_LVDS;
 684                 else
 685                         lvds_reg = LVDS;
 686                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 687                     LVDS_CLKB_POWER_UP)
 688                         clock.p2 = limit->p2.p2_fast;
 689                 else
 690                         clock.p2 = limit->p2.p2_slow;
 691         } else {
 692                 if (target < limit->p2.dot_limit)
 693                         clock.p2 = limit->p2.p2_slow;
 694                 else
 695                         clock.p2 = limit->p2.p2_fast;
 696         }
 697
 698         memset(best_clock, 0, sizeof(*best_clock));
 699         max_n = limit->n.max;
 700         /* based on hardware requirement, prefer smaller n to precision */
 701         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 702                 /* based on hardware requirement, prefere larger m1,m2 */
 703                 for (clock.m1 = limit->m1.max;
 704                      clock.m1 >= limit->m1.min; clock.m1--) {
 705                         for (clock.m2 = limit->m2.max;
 706                              clock.m2 >= limit->m2.min; clock.m2--) {
 707                                 for (clock.p1 = limit->p1.max;
 708                                      clock.p1 >= limit->p1.min; clock.p1--) {
 709                                         int this_err;
 710
 711                                         intel_clock(dev, refclk, &clock);
 712                                         if (!intel_PLL_is_valid(dev, limit,
 713                                                                 &clock))
 714                                                 continue;
 715                                         if (match_clock &&
 716                                             clock.p != match_clock->p)
 717                                                 continue;
 718
 719                                         this_err = abs(clock.dot - target);
 720                                         if (this_err < err_most) {
 721                                                 *best_clock = clock;
 722                                                 err_most = this_err;
 723                                                 max_n = clock.n;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730         return found;
 731 }
 732
 733 static bool
 734 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 735                            int target, int refclk, intel_clock_t *match_clock,
 736                            intel_clock_t *best_clock)
 737 {
 738         struct drm_device *dev = crtc->dev;
 739         intel_clock_t clock;
 740
 741         if (target < 200000) {
 742                 clock.n = 1;
 743                 clock.p1 = 2;
 744                 clock.p2 = 10;
 745                 clock.m1 = 12;
 746                 clock.m2 = 9;
 747         } else {
 748                 clock.n = 2;
 749                 clock.p1 = 1;
 750                 clock.p2 = 10;
 751                 clock.m1 = 14;
 752                 clock.m2 = 8;
 753         }
 754         intel_clock(dev, refclk, &clock);
 755         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 756         return true;
 757 }
 758
 759 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 760 static bool
 761 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 762                       int target, int refclk, intel_clock_t *match_clock,
 763                       intel_clock_t *best_clock)
 764 {
 765         intel_clock_t clock;
 766         if (target < 200000) {
 767                 clock.p1 = 2;
 768                 clock.p2 = 10;
 769                 clock.n = 2;
 770                 clock.m1 = 23;
 771                 clock.m2 = 8;
 772         } else {
 773                 clock.p1 = 1;
 774                 clock.p2 = 10;
 775                 clock.n = 1;
 776                 clock.m1 = 14;
 777                 clock.m2 = 2;
 778         }
 779         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 780         clock.p = (clock.p1 * clock.p2);
 781         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 782         clock.vco = 0;
 783         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 784         return true;
 785 }
 786
 787 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 788 {
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790         u32 frame, frame_reg = PIPEFRAME(pipe);
 791
 792         frame = I915_READ(frame_reg);
 793
 794         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 795                 DRM_DEBUG_KMS("vblank wait timed out\n");
 796 }
 797
 798 /**
 799  * intel_wait_for_vblank - wait for vblank on a given pipe
 800  * @dev: drm device
 801  * @pipe: pipe to wait for
 802  *
 803  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 804  * mode setting code.
 805  */
 806 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 807 {
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         int pipestat_reg = PIPESTAT(pipe);
 810
 811         if (INTEL_INFO(dev)->gen >= 5) {
 812                 ironlake_wait_for_vblank(dev, pipe);
 813                 return;
 814         }
 815
 816         /* Clear existing vblank status. Note this will clear any other
 817          * sticky status fields as well.
 818          *
 819          * This races with i915_driver_irq_handler() with the result
 820          * that either function could miss a vblank event.  Here it is not
 821          * fatal, as we will either wait upon the next vblank interrupt or
 822          * timeout.  Generally speaking intel_wait_for_vblank() is only
 823          * called during modeset at which time the GPU should be idle and
 824          * should *not* be performing page flips and thus not waiting on
 825          * vblanks...
 826          * Currently, the result of us stealing a vblank from the irq
 827          * handler is that a single frame will be skipped during swapbuffers.
 828          */
 829         I915_WRITE(pipestat_reg,
 830                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 831
 832         /* Wait for vblank interrupt bit to set */
 833         if (wait_for(I915_READ(pipestat_reg) &
 834                      PIPE_VBLANK_INTERRUPT_STATUS,
 835                      50))
 836                 DRM_DEBUG_KMS("vblank wait timed out\n");
 837 }
 838
 839 /*
 840  * intel_wait_for_pipe_off - wait for pipe to turn off
 841  * @dev: drm device
 842  * @pipe: pipe to wait for
 843  *
 844  * After disabling a pipe, we can't wait for vblank in the usual way,
 845  * spinning on the vblank interrupt status bit, since we won't actually
 846  * see an interrupt when the pipe is disabled.
 847  *
 848  * On Gen4 and above:
 849  *   wait for the pipe register state bit to turn off
 850  *
 851  * Otherwise:
 852  *   wait for the display line value to settle (it usually
 853  *   ends up stopping at the start of the next frame).
 854  *
 855  */
 856 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 857 {
 858         struct drm_i915_private *dev_priv = dev->dev_private;
 859
 860         if (INTEL_INFO(dev)->gen >= 4) {
 861                 int reg = PIPECONF(pipe);
 862
 863                 /* Wait for the Pipe State to go off */
 864                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 865                              100))
 866                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 867         } else {
 868                 u32 last_line, line_mask;
 869                 int reg = PIPEDSL(pipe);
 870                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 871
 872                 if (IS_GEN2(dev))
 873                         line_mask = DSL_LINEMASK_GEN2;
 874                 else
 875                         line_mask = DSL_LINEMASK_GEN3;
 876
 877                 /* Wait for the display line to settle */
 878                 do {
 879                         last_line = I915_READ(reg) & line_mask;
 880                         mdelay(5);
 881                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 882                          time_after(timeout, jiffies));
 883                 if (time_after(jiffies, timeout))
 884                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 885         }
 886 }
 887
 888 static const char *state_string(bool enabled)
 889 {
 890         return enabled ? "on" : "off";
 891 }
 892
 893 /* Only for pre-ILK configs */
 894 static void assert_pll(struct drm_i915_private *dev_priv,
 895                        enum pipe pipe, bool state)
 896 {
 897         int reg;
 898         u32 val;
 899         bool cur_state;
 900
 901         reg = DPLL(pipe);
 902         val = I915_READ(reg);
 903         cur_state = !!(val & DPLL_VCO_ENABLE);
 904         WARN(cur_state != state,
 905              "PLL state assertion failure (expected %s, current %s)\n",
 906              state_string(state), state_string(cur_state));
 907 }
 908 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 909 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 910
 911 /* For ILK+ */
 912 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 913                            struct intel_crtc *intel_crtc, bool state)
 914 {
 915         int reg;
 916         u32 val;
 917         bool cur_state;
 918
 919         if (!intel_crtc->pch_pll) {
 920                 WARN(1, "asserting PCH PLL enabled with no PLL\n");
 921                 return;
 922         }
 923
 924         if (HAS_PCH_CPT(dev_priv->dev)) {
 925                 u32 pch_dpll;
 926
 927                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 928
 929                 /* Make sure the selected PLL is enabled to the transcoder */
 930                 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
 931                      "transcoder %d PLL not enabled\n", intel_crtc->pipe);
 932         }
 933
 934         reg = intel_crtc->pch_pll->pll_reg;
 935         val = I915_READ(reg);
 936         cur_state = !!(val & DPLL_VCO_ENABLE);
 937         WARN(cur_state != state,
 938              "PCH PLL state assertion failure (expected %s, current %s)\n",
 939              state_string(state), state_string(cur_state));
 940 }
 941 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 942 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 943
 944 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 945                           enum pipe pipe, bool state)
 946 {
 947         int reg;
 948         u32 val;
 949         bool cur_state;
 950
 951         reg = FDI_TX_CTL(pipe);
 952         val = I915_READ(reg);
 953         cur_state = !!(val & FDI_TX_ENABLE);
 954         WARN(cur_state != state,
 955              "FDI TX state assertion failure (expected %s, current %s)\n",
 956              state_string(state), state_string(cur_state));
 957 }
 958 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 959 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 960
 961 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 962                           enum pipe pipe, bool state)
 963 {
 964         int reg;
 965         u32 val;
 966         bool cur_state;
 967
 968         reg = FDI_RX_CTL(pipe);
 969         val = I915_READ(reg);
 970         cur_state = !!(val & FDI_RX_ENABLE);
 971         WARN(cur_state != state,
 972              "FDI RX state assertion failure (expected %s, current %s)\n",
 973              state_string(state), state_string(cur_state));
 974 }
 975 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 976 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 977
 978 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 979                                       enum pipe pipe)
 980 {
 981         int reg;
 982         u32 val;
 983
 984         /* ILK FDI PLL is always enabled */
 985         if (dev_priv->info->gen == 5)
 986                 return;
 987
 988         reg = FDI_TX_CTL(pipe);
 989         val = I915_READ(reg);
 990         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 991 }
 992
 993 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 994                                       enum pipe pipe)
 995 {
 996         int reg;
 997         u32 val;
 998
 999         reg = FDI_RX_CTL(pipe);
1000         val = I915_READ(reg);
1001         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1002 }
1003
1004 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1005                                   enum pipe pipe)
1006 {
1007         int pp_reg, lvds_reg;
1008         u32 val;
1009         enum pipe panel_pipe = PIPE_A;
1010         bool locked = true;
1011
1012         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1013                 pp_reg = PCH_PP_CONTROL;
1014                 lvds_reg = PCH_LVDS;
1015         } else {
1016                 pp_reg = PP_CONTROL;
1017                 lvds_reg = LVDS;
1018         }
1019
1020         val = I915_READ(pp_reg);
1021         if (!(val & PANEL_POWER_ON) ||
1022             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1023                 locked = false;
1024
1025         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1026                 panel_pipe = PIPE_B;
1027
1028         WARN(panel_pipe == pipe && locked,
1029              "panel assertion failure, pipe %c regs locked\n",
1030              pipe_name(pipe));
1031 }
1032
1033 void assert_pipe(struct drm_i915_private *dev_priv,
1034                  enum pipe pipe, bool state)
1035 {
1036         int reg;
1037         u32 val;
1038         bool cur_state;
1039
1040         /* if we need the pipe A quirk it must be always on */
1041         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1042                 state = true;
1043
1044         reg = PIPECONF(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & PIPECONF_ENABLE);
1047         WARN(cur_state != state,
1048              "pipe %c assertion failure (expected %s, current %s)\n",
1049              pipe_name(pipe), state_string(state), state_string(cur_state));
1050 }
1051
1052 static void assert_plane(struct drm_i915_private *dev_priv,
1053                          enum plane plane, bool state)
1054 {
1055         int reg;
1056         u32 val;
1057         bool cur_state;
1058
1059         reg = DSPCNTR(plane);
1060         val = I915_READ(reg);
1061         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1062         WARN(cur_state != state,
1063              "plane %c assertion failure (expected %s, current %s)\n",
1064              plane_name(plane), state_string(state), state_string(cur_state));
1065 }
1066
1067 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1068 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1069
1070 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1071                                    enum pipe pipe)
1072 {
1073         int reg, i;
1074         u32 val;
1075         int cur_pipe;
1076
1077         /* Planes are fixed to pipes on ILK+ */
1078         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1079                 reg = DSPCNTR(pipe);
1080                 val = I915_READ(reg);
1081                 WARN((val & DISPLAY_PLANE_ENABLE),
1082                      "plane %c assertion failure, should be disabled but not\n",
1083                      plane_name(pipe));
1084                 return;
1085         }
1086
1087         /* Need to check both planes against the pipe */
1088         for (i = 0; i < 2; i++) {
1089                 reg = DSPCNTR(i);
1090                 val = I915_READ(reg);
1091                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1092                         DISPPLANE_SEL_PIPE_SHIFT;
1093                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1094                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1095                      plane_name(i), pipe_name(pipe));
1096         }
1097 }
1098
1099 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1100 {
1101         u32 val;
1102         bool enabled;
1103
1104         val = I915_READ(PCH_DREF_CONTROL);
1105         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1106                             DREF_SUPERSPREAD_SOURCE_MASK));
1107         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1108 }
1109
1110 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1111                                        enum pipe pipe)
1112 {
1113         int reg;
1114         u32 val;
1115         bool enabled;
1116
1117         reg = TRANSCONF(pipe);
1118         val = I915_READ(reg);
1119         enabled = !!(val & TRANS_ENABLE);
1120         WARN(enabled,
1121              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1122              pipe_name(pipe));
1123 }
1124
1125 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1126                             enum pipe pipe, u32 port_sel, u32 val)
1127 {
1128         if ((val & DP_PORT_EN) == 0)
1129                 return false;
1130
1131         if (HAS_PCH_CPT(dev_priv->dev)) {
1132                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1133                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1134                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1135                         return false;
1136         } else {
1137                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1138                         return false;
1139         }
1140         return true;
1141 }
1142
1143 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1144                               enum pipe pipe, u32 val)
1145 {
1146         if ((val & PORT_ENABLE) == 0)
1147                 return false;
1148
1149         if (HAS_PCH_CPT(dev_priv->dev)) {
1150                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1151                         return false;
1152         } else {
1153                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1154                         return false;
1155         }
1156         return true;
1157 }
1158
1159 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1160                               enum pipe pipe, u32 val)
1161 {
1162         if ((val & LVDS_PORT_EN) == 0)
1163                 return false;
1164
1165         if (HAS_PCH_CPT(dev_priv->dev)) {
1166                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1167                         return false;
1168         } else {
1169                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1170                         return false;
1171         }
1172         return true;
1173 }
1174
1175 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1176                               enum pipe pipe, u32 val)
1177 {
1178         if ((val & ADPA_DAC_ENABLE) == 0)
1179                 return false;
1180         if (HAS_PCH_CPT(dev_priv->dev)) {
1181                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1182                         return false;
1183         } else {
1184                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1185                         return false;
1186         }
1187         return true;
1188 }
1189
1190 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1191                                    enum pipe pipe, int reg, u32 port_sel)
1192 {
1193         u32 val = I915_READ(reg);
1194         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1195              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1196              reg, pipe_name(pipe));
1197 }
1198
1199 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1200                                      enum pipe pipe, int reg)
1201 {
1202         u32 val = I915_READ(reg);
1203         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1204              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1205              reg, pipe_name(pipe));
1206 }
1207
1208 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1209                                       enum pipe pipe)
1210 {
1211         int reg;
1212         u32 val;
1213
1214         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1215         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1216         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1217
1218         reg = PCH_ADPA;
1219         val = I915_READ(reg);
1220         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1221              "PCH VGA enabled on transcoder %c, should be disabled\n",
1222              pipe_name(pipe));
1223
1224         reg = PCH_LVDS;
1225         val = I915_READ(reg);
1226         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1227              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1228              pipe_name(pipe));
1229
1230         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1231         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1232         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1233 }
1234
1235 /**
1236  * intel_enable_pll - enable a PLL
1237  * @dev_priv: i915 private structure
1238  * @pipe: pipe PLL to enable
1239  *
1240  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1241  * make sure the PLL reg is writable first though, since the panel write
1242  * protect mechanism may be enabled.
1243  *
1244  * Note!  This is for pre-ILK only.
1245  */
1246 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1247 {
1248         int reg;
1249         u32 val;
1250
1251         /* No really, not for ILK+ */
1252         BUG_ON(dev_priv->info->gen >= 5);
1253
1254         /* PLL is protected by panel, make sure we can write it */
1255         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1256                 assert_panel_unlocked(dev_priv, pipe);
1257
1258         reg = DPLL(pipe);
1259         val = I915_READ(reg);
1260         val |= DPLL_VCO_ENABLE;
1261
1262         /* We do this three times for luck */
1263         I915_WRITE(reg, val);
1264         POSTING_READ(reg);
1265         udelay(150); /* wait for warmup */
1266         I915_WRITE(reg, val);
1267         POSTING_READ(reg);
1268         udelay(150); /* wait for warmup */
1269         I915_WRITE(reg, val);
1270         POSTING_READ(reg);
1271         udelay(150); /* wait for warmup */
1272 }
1273
1274 /**
1275  * intel_disable_pll - disable a PLL
1276  * @dev_priv: i915 private structure
1277  * @pipe: pipe PLL to disable
1278  *
1279  * Disable the PLL for @pipe, making sure the pipe is off first.
1280  *
1281  * Note!  This is for pre-ILK only.
1282  */
1283 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1284 {
1285         int reg;
1286         u32 val;
1287
1288         /* Don't disable pipe A or pipe A PLLs if needed */
1289         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1290                 return;
1291
1292         /* Make sure the pipe isn't still relying on us */
1293         assert_pipe_disabled(dev_priv, pipe);
1294
1295         reg = DPLL(pipe);
1296         val = I915_READ(reg);
1297         val &= ~DPLL_VCO_ENABLE;
1298         I915_WRITE(reg, val);
1299         POSTING_READ(reg);
1300 }
1301
1302 /* SBI access */
1303 static void
1304 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1305 {
1306         unsigned long flags;
1307
1308         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1309         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1310                                 100)) {
1311                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1312                 goto out_unlock;
1313         }
1314
1315         I915_WRITE(SBI_ADDR,
1316                         (reg << 16));
1317         I915_WRITE(SBI_DATA,
1318                         value);
1319         I915_WRITE(SBI_CTL_STAT,
1320                         SBI_BUSY |
1321                         SBI_CTL_OP_CRWR);
1322
1323         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1324                                 100)) {
1325                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1326                 goto out_unlock;
1327         }
1328
1329 out_unlock:
1330         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1331 }
1332
1333 static u32
1334 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1335 {
1336         unsigned long flags;
1337         u32 value;
1338
1339         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1340         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1341                                 100)) {
1342                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1343                 goto out_unlock;
1344         }
1345
1346         I915_WRITE(SBI_ADDR,
1347                         (reg << 16));
1348         I915_WRITE(SBI_CTL_STAT,
1349                         SBI_BUSY |
1350                         SBI_CTL_OP_CRRD);
1351
1352         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1353                                 100)) {
1354                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1355                 goto out_unlock;
1356         }
1357
1358         value = I915_READ(SBI_DATA);
1359
1360 out_unlock:
1361         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1362         return value;
1363 }
1364
1365 /**
1366  * intel_enable_pch_pll - enable PCH PLL
1367  * @dev_priv: i915 private structure
1368  * @pipe: pipe PLL to enable
1369  *
1370  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1371  * drives the transcoder clock.
1372  */
1373 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1374 {
1375         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1376         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1377         int reg;
1378         u32 val;
1379
1380         /* PCH only available on ILK+ */
1381         BUG_ON(dev_priv->info->gen < 5);
1382         BUG_ON(pll == NULL);
1383         BUG_ON(pll->refcount == 0);
1384
1385         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1386                       pll->pll_reg, pll->active, pll->on,
1387                       intel_crtc->base.base.id);
1388
1389         /* PCH refclock must be enabled first */
1390         assert_pch_refclk_enabled(dev_priv);
1391
1392         if (pll->active++ && pll->on) {
1393                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1394                 return;
1395         }
1396
1397         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1398
1399         reg = pll->pll_reg;
1400         val = I915_READ(reg);
1401         val |= DPLL_VCO_ENABLE;
1402         I915_WRITE(reg, val);
1403         POSTING_READ(reg);
1404         udelay(200);
1405
1406         pll->on = true;
1407 }
1408
1409 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1410 {
1411         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1412         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1413         int reg;
1414         u32 val;
1415
1416         /* PCH only available on ILK+ */
1417         BUG_ON(dev_priv->info->gen < 5);
1418         if (pll == NULL)
1419                return;
1420
1421         BUG_ON(pll->refcount == 0);
1422
1423         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1424                       pll->pll_reg, pll->active, pll->on,
1425                       intel_crtc->base.base.id);
1426
1427         BUG_ON(pll->active == 0);
1428         if (--pll->active) {
1429                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1430                 return;
1431         }
1432
1433         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1434
1435         /* Make sure transcoder isn't still depending on us */
1436         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1437
1438         reg = pll->pll_reg;
1439         val = I915_READ(reg);
1440         val &= ~DPLL_VCO_ENABLE;
1441         I915_WRITE(reg, val);
1442         POSTING_READ(reg);
1443         udelay(200);
1444
1445         pll->on = false;
1446 }
1447
1448 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1449                                     enum pipe pipe)
1450 {
1451         int reg;
1452         u32 val, pipeconf_val;
1453         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1454
1455         /* PCH only available on ILK+ */
1456         BUG_ON(dev_priv->info->gen < 5);
1457
1458         /* Make sure PCH DPLL is enabled */
1459         assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
1460
1461         /* FDI must be feeding us bits for PCH ports */
1462         assert_fdi_tx_enabled(dev_priv, pipe);
1463         assert_fdi_rx_enabled(dev_priv, pipe);
1464
1465         reg = TRANSCONF(pipe);
1466         val = I915_READ(reg);
1467         pipeconf_val = I915_READ(PIPECONF(pipe));
1468
1469         if (HAS_PCH_IBX(dev_priv->dev)) {
1470                 /*
1471                  * make the BPC in transcoder be consistent with
1472                  * that in pipeconf reg.
1473                  */
1474                 val &= ~PIPE_BPC_MASK;
1475                 val |= pipeconf_val & PIPE_BPC_MASK;
1476         }
1477
1478         val &= ~TRANS_INTERLACE_MASK;
1479         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1480                 if (HAS_PCH_IBX(dev_priv->dev) &&
1481                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1482                         val |= TRANS_LEGACY_INTERLACED_ILK;
1483                 else
1484                         val |= TRANS_INTERLACED;
1485         else
1486                 val |= TRANS_PROGRESSIVE;
1487
1488         I915_WRITE(reg, val | TRANS_ENABLE);
1489         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1490                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1491 }
1492
1493 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1494                                      enum pipe pipe)
1495 {
1496         int reg;
1497         u32 val;
1498
1499         /* FDI relies on the transcoder */
1500         assert_fdi_tx_disabled(dev_priv, pipe);
1501         assert_fdi_rx_disabled(dev_priv, pipe);
1502
1503         /* Ports must be off as well */
1504         assert_pch_ports_disabled(dev_priv, pipe);
1505
1506         reg = TRANSCONF(pipe);
1507         val = I915_READ(reg);
1508         val &= ~TRANS_ENABLE;
1509         I915_WRITE(reg, val);
1510         /* wait for PCH transcoder off, transcoder state */
1511         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1512                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1513 }
1514
1515 /**
1516  * intel_enable_pipe - enable a pipe, asserting requirements
1517  * @dev_priv: i915 private structure
1518  * @pipe: pipe to enable
1519  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1520  *
1521  * Enable @pipe, making sure that various hardware specific requirements
1522  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1523  *
1524  * @pipe should be %PIPE_A or %PIPE_B.
1525  *
1526  * Will wait until the pipe is actually running (i.e. first vblank) before
1527  * returning.
1528  */
1529 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1530                               bool pch_port)
1531 {
1532         int reg;
1533         u32 val;
1534
1535         /*
1536          * A pipe without a PLL won't actually be able to drive bits from
1537          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1538          * need the check.
1539          */
1540         if (!HAS_PCH_SPLIT(dev_priv->dev))
1541                 assert_pll_enabled(dev_priv, pipe);
1542         else {
1543                 if (pch_port) {
1544                         /* if driving the PCH, we need FDI enabled */
1545                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1546                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1547                 }
1548                 /* FIXME: assert CPU port conditions for SNB+ */
1549         }
1550
1551         reg = PIPECONF(pipe);
1552         val = I915_READ(reg);
1553         if (val & PIPECONF_ENABLE)
1554                 return;
1555
1556         I915_WRITE(reg, val | PIPECONF_ENABLE);
1557         intel_wait_for_vblank(dev_priv->dev, pipe);
1558 }
1559
1560 /**
1561  * intel_disable_pipe - disable a pipe, asserting requirements
1562  * @dev_priv: i915 private structure
1563  * @pipe: pipe to disable
1564  *
1565  * Disable @pipe, making sure that various hardware specific requirements
1566  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1567  *
1568  * @pipe should be %PIPE_A or %PIPE_B.
1569  *
1570  * Will wait until the pipe has shut down before returning.
1571  */
1572 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1573                                enum pipe pipe)
1574 {
1575         int reg;
1576         u32 val;
1577
1578         /*
1579          * Make sure planes won't keep trying to pump pixels to us,
1580          * or we might hang the display.
1581          */
1582         assert_planes_disabled(dev_priv, pipe);
1583
1584         /* Don't disable pipe A or pipe A PLLs if needed */
1585         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1586                 return;
1587
1588         reg = PIPECONF(pipe);
1589         val = I915_READ(reg);
1590         if ((val & PIPECONF_ENABLE) == 0)
1591                 return;
1592
1593         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1594         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1595 }
1596
1597 /*
1598  * Plane regs are double buffered, going from enabled->disabled needs a
1599  * trigger in order to latch.  The display address reg provides this.
1600  */
1601 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1602                                       enum plane plane)
1603 {
1604         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1605         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1606 }
1607
1608 /**
1609  * intel_enable_plane - enable a display plane on a given pipe
1610  * @dev_priv: i915 private structure
1611  * @plane: plane to enable
1612  * @pipe: pipe being fed
1613  *
1614  * Enable @plane on @pipe, making sure that @pipe is running first.
1615  */
1616 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1617                                enum plane plane, enum pipe pipe)
1618 {
1619         int reg;
1620         u32 val;
1621
1622         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1623         assert_pipe_enabled(dev_priv, pipe);
1624
1625         reg = DSPCNTR(plane);
1626         val = I915_READ(reg);
1627         if (val & DISPLAY_PLANE_ENABLE)
1628                 return;
1629
1630         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1631         intel_flush_display_plane(dev_priv, plane);
1632         intel_wait_for_vblank(dev_priv->dev, pipe);
1633 }
1634
1635 /**
1636  * intel_disable_plane - disable a display plane
1637  * @dev_priv: i915 private structure
1638  * @plane: plane to disable
1639  * @pipe: pipe consuming the data
1640  *
1641  * Disable @plane; should be an independent operation.
1642  */
1643 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1644                                 enum plane plane, enum pipe pipe)
1645 {
1646         int reg;
1647         u32 val;
1648
1649         reg = DSPCNTR(plane);
1650         val = I915_READ(reg);
1651         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1652                 return;
1653
1654         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1655         intel_flush_display_plane(dev_priv, plane);
1656         intel_wait_for_vblank(dev_priv->dev, pipe);
1657 }
1658
1659 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1660                            enum pipe pipe, int reg, u32 port_sel)
1661 {
1662         u32 val = I915_READ(reg);
1663         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1664                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1665                 I915_WRITE(reg, val & ~DP_PORT_EN);
1666         }
1667 }
1668
1669 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1670                              enum pipe pipe, int reg)
1671 {
1672         u32 val = I915_READ(reg);
1673         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1674                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1675                               reg, pipe);
1676                 I915_WRITE(reg, val & ~PORT_ENABLE);
1677         }
1678 }
1679
1680 /* Disable any ports connected to this transcoder */
1681 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1682                                     enum pipe pipe)
1683 {
1684         u32 reg, val;
1685
1686         val = I915_READ(PCH_PP_CONTROL);
1687         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1688
1689         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1690         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1691         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1692
1693         reg = PCH_ADPA;
1694         val = I915_READ(reg);
1695         if (adpa_pipe_enabled(dev_priv, val, pipe))
1696                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1697
1698         reg = PCH_LVDS;
1699         val = I915_READ(reg);
1700         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1701                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1702                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1703                 POSTING_READ(reg);
1704                 udelay(100);
1705         }
1706
1707         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1708         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1709         disable_pch_hdmi(dev_priv, pipe, HDMID);
1710 }
1711
1712 int
1713 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1714                            struct drm_i915_gem_object *obj,
1715                            struct intel_ring_buffer *pipelined)
1716 {
1717         struct drm_i915_private *dev_priv = dev->dev_private;
1718         u32 alignment;
1719         int ret;
1720
1721         switch (obj->tiling_mode) {
1722         case I915_TILING_NONE:
1723                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1724                         alignment = 128 * 1024;
1725                 else if (INTEL_INFO(dev)->gen >= 4)
1726                         alignment = 4 * 1024;
1727                 else
1728                         alignment = 64 * 1024;
1729                 break;
1730         case I915_TILING_X:
1731                 /* pin() will align the object as required by fence */
1732                 alignment = 0;
1733                 break;
1734         case I915_TILING_Y:
1735                 /* FIXME: Is this true? */
1736                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1737                 return -EINVAL;
1738         default:
1739                 BUG();
1740         }
1741
1742         dev_priv->mm.interruptible = false;
1743         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1744         if (ret)
1745                 goto err_interruptible;
1746
1747         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1748          * fence, whereas 965+ only requires a fence if using
1749          * framebuffer compression.  For simplicity, we always install
1750          * a fence as the cost is not that onerous.
1751          */
1752         ret = i915_gem_object_get_fence(obj);
1753         if (ret)
1754                 goto err_unpin;
1755
1756         i915_gem_object_pin_fence(obj);
1757
1758         dev_priv->mm.interruptible = true;
1759         return 0;
1760
1761 err_unpin:
1762         i915_gem_object_unpin(obj);
1763 err_interruptible:
1764         dev_priv->mm.interruptible = true;
1765         return ret;
1766 }
1767
1768 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1769 {
1770         i915_gem_object_unpin_fence(obj);
1771         i915_gem_object_unpin(obj);
1772 }
1773
1774 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1775                              int x, int y)
1776 {
1777         struct drm_device *dev = crtc->dev;
1778         struct drm_i915_private *dev_priv = dev->dev_private;
1779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1780         struct intel_framebuffer *intel_fb;
1781         struct drm_i915_gem_object *obj;
1782         int plane = intel_crtc->plane;
1783         unsigned long Start, Offset;
1784         u32 dspcntr;
1785         u32 reg;
1786
1787         switch (plane) {
1788         case 0:
1789         case 1:
1790                 break;
1791         default:
1792                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1793                 return -EINVAL;
1794         }
1795
1796         intel_fb = to_intel_framebuffer(fb);
1797         obj = intel_fb->obj;
1798
1799         reg = DSPCNTR(plane);
1800         dspcntr = I915_READ(reg);
1801         /* Mask out pixel format bits in case we change it */
1802         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1803         switch (fb->bits_per_pixel) {
1804         case 8:
1805                 dspcntr |= DISPPLANE_8BPP;
1806                 break;
1807         case 16:
1808                 if (fb->depth == 15)
1809                         dspcntr |= DISPPLANE_15_16BPP;
1810                 else
1811                         dspcntr |= DISPPLANE_16BPP;
1812                 break;
1813         case 24:
1814         case 32:
1815                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1816                 break;
1817         default:
1818                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1819                 return -EINVAL;
1820         }
1821         if (INTEL_INFO(dev)->gen >= 4) {
1822                 if (obj->tiling_mode != I915_TILING_NONE)
1823                         dspcntr |= DISPPLANE_TILED;
1824                 else
1825                         dspcntr &= ~DISPPLANE_TILED;
1826         }
1827
1828         I915_WRITE(reg, dspcntr);
1829
1830         Start = obj->gtt_offset;
1831         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1832
1833         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1834                       Start, Offset, x, y, fb->pitches[0]);
1835         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1836         if (INTEL_INFO(dev)->gen >= 4) {
1837                 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1838                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1839                 I915_WRITE(DSPADDR(plane), Offset);
1840         } else
1841                 I915_WRITE(DSPADDR(plane), Start + Offset);
1842         POSTING_READ(reg);
1843
1844         return 0;
1845 }
1846
1847 static int ironlake_update_plane(struct drm_crtc *crtc,
1848                                  struct drm_framebuffer *fb, int x, int y)
1849 {
1850         struct drm_device *dev = crtc->dev;
1851         struct drm_i915_private *dev_priv = dev->dev_private;
1852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1853         struct intel_framebuffer *intel_fb;
1854         struct drm_i915_gem_object *obj;
1855         int plane = intel_crtc->plane;
1856         unsigned long Start, Offset;
1857         u32 dspcntr;
1858         u32 reg;
1859
1860         switch (plane) {
1861         case 0:
1862         case 1:
1863         case 2:
1864                 break;
1865         default:
1866                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1867                 return -EINVAL;
1868         }
1869
1870         intel_fb = to_intel_framebuffer(fb);
1871         obj = intel_fb->obj;
1872
1873         reg = DSPCNTR(plane);
1874         dspcntr = I915_READ(reg);
1875         /* Mask out pixel format bits in case we change it */
1876         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1877         switch (fb->bits_per_pixel) {
1878         case 8:
1879                 dspcntr |= DISPPLANE_8BPP;
1880                 break;
1881         case 16:
1882                 if (fb->depth != 16)
1883                         return -EINVAL;
1884
1885                 dspcntr |= DISPPLANE_16BPP;
1886                 break;
1887         case 24:
1888         case 32:
1889                 if (fb->depth == 24)
1890                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1891                 else if (fb->depth == 30)
1892                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1893                 else
1894                         return -EINVAL;
1895                 break;
1896         default:
1897                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1898                 return -EINVAL;
1899         }
1900
1901         if (obj->tiling_mode != I915_TILING_NONE)
1902                 dspcntr |= DISPPLANE_TILED;
1903         else
1904                 dspcntr &= ~DISPPLANE_TILED;
1905
1906         /* must disable */
1907         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1908
1909         I915_WRITE(reg, dspcntr);
1910
1911         Start = obj->gtt_offset;
1912         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1913
1914         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1915                       Start, Offset, x, y, fb->pitches[0]);
1916         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1917         I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1918         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1919         I915_WRITE(DSPADDR(plane), Offset);
1920         POSTING_READ(reg);
1921
1922         return 0;
1923 }
1924
1925 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1926 static int
1927 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1928                            int x, int y, enum mode_set_atomic state)
1929 {
1930         struct drm_device *dev = crtc->dev;
1931         struct drm_i915_private *dev_priv = dev->dev_private;
1932
1933         if (dev_priv->display.disable_fbc)
1934                 dev_priv->display.disable_fbc(dev);
1935         intel_increase_pllclock(crtc);
1936
1937         return dev_priv->display.update_plane(crtc, fb, x, y);
1938 }
1939
1940 static int
1941 intel_finish_fb(struct drm_framebuffer *old_fb)
1942 {
1943         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1944         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1945         bool was_interruptible = dev_priv->mm.interruptible;
1946         int ret;
1947
1948         wait_event(dev_priv->pending_flip_queue,
1949                    atomic_read(&dev_priv->mm.wedged) ||
1950                    atomic_read(&obj->pending_flip) == 0);
1951
1952         /* Big Hammer, we also need to ensure that any pending
1953          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1954          * current scanout is retired before unpinning the old
1955          * framebuffer.
1956          *
1957          * This should only fail upon a hung GPU, in which case we
1958          * can safely continue.
1959          */
1960         dev_priv->mm.interruptible = false;
1961         ret = i915_gem_object_finish_gpu(obj);
1962         dev_priv->mm.interruptible = was_interruptible;
1963
1964         return ret;
1965 }
1966
1967 static int
1968 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1969                     struct drm_framebuffer *old_fb)
1970 {
1971         struct drm_device *dev = crtc->dev;
1972         struct drm_i915_private *dev_priv = dev->dev_private;
1973         struct drm_i915_master_private *master_priv;
1974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1975         int ret;
1976
1977         /* no fb bound */
1978         if (!crtc->fb) {
1979                 DRM_ERROR("No FB bound\n");
1980                 return 0;
1981         }
1982
1983         if(intel_crtc->plane > dev_priv->num_pipe) {
1984                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
1985                                 intel_crtc->plane,
1986                                 dev_priv->num_pipe);
1987                 return -EINVAL;
1988         }
1989
1990         mutex_lock(&dev->struct_mutex);
1991         ret = intel_pin_and_fence_fb_obj(dev,
1992                                          to_intel_framebuffer(crtc->fb)->obj,
1993                                          NULL);
1994         if (ret != 0) {
1995                 mutex_unlock(&dev->struct_mutex);
1996                 DRM_ERROR("pin & fence failed\n");
1997                 return ret;
1998         }
1999
2000         if (old_fb)
2001                 intel_finish_fb(old_fb);
2002
2003         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2004         if (ret) {
2005                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2006                 mutex_unlock(&dev->struct_mutex);
2007                 DRM_ERROR("failed to update base address\n");
2008                 return ret;
2009         }
2010
2011         if (old_fb) {
2012                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2013                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2014         }
2015
2016         intel_update_fbc(dev);
2017         mutex_unlock(&dev->struct_mutex);
2018
2019         if (!dev->primary->master)
2020                 return 0;
2021
2022         master_priv = dev->primary->master->driver_priv;
2023         if (!master_priv->sarea_priv)
2024                 return 0;
2025
2026         if (intel_crtc->pipe) {
2027                 master_priv->sarea_priv->pipeB_x = x;
2028                 master_priv->sarea_priv->pipeB_y = y;
2029         } else {
2030                 master_priv->sarea_priv->pipeA_x = x;
2031                 master_priv->sarea_priv->pipeA_y = y;
2032         }
2033
2034         return 0;
2035 }
2036
2037 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2038 {
2039         struct drm_device *dev = crtc->dev;
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041         u32 dpa_ctl;
2042
2043         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2044         dpa_ctl = I915_READ(DP_A);
2045         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2046
2047         if (clock < 200000) {
2048                 u32 temp;
2049                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2050                 /* workaround for 160Mhz:
2051                    1) program 0x4600c bits 15:0 = 0x8124
2052                    2) program 0x46010 bit 0 = 1
2053                    3) program 0x46034 bit 24 = 1
2054                    4) program 0x64000 bit 14 = 1
2055                    */
2056                 temp = I915_READ(0x4600c);
2057                 temp &= 0xffff0000;
2058                 I915_WRITE(0x4600c, temp | 0x8124);
2059
2060                 temp = I915_READ(0x46010);
2061                 I915_WRITE(0x46010, temp | 1);
2062
2063                 temp = I915_READ(0x46034);
2064                 I915_WRITE(0x46034, temp | (1 << 24));
2065         } else {
2066                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2067         }
2068         I915_WRITE(DP_A, dpa_ctl);
2069
2070         POSTING_READ(DP_A);
2071         udelay(500);
2072 }
2073
2074 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2075 {
2076         struct drm_device *dev = crtc->dev;
2077         struct drm_i915_private *dev_priv = dev->dev_private;
2078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079         int pipe = intel_crtc->pipe;
2080         u32 reg, temp;
2081
2082         /* enable normal train */
2083         reg = FDI_TX_CTL(pipe);
2084         temp = I915_READ(reg);
2085         if (IS_IVYBRIDGE(dev)) {
2086                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2087                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2088         } else {
2089                 temp &= ~FDI_LINK_TRAIN_NONE;
2090                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2091         }
2092         I915_WRITE(reg, temp);
2093
2094         reg = FDI_RX_CTL(pipe);
2095         temp = I915_READ(reg);
2096         if (HAS_PCH_CPT(dev)) {
2097                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2098                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2099         } else {
2100                 temp &= ~FDI_LINK_TRAIN_NONE;
2101                 temp |= FDI_LINK_TRAIN_NONE;
2102         }
2103         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2104
2105         /* wait one idle pattern time */
2106         POSTING_READ(reg);
2107         udelay(1000);
2108
2109         /* IVB wants error correction enabled */
2110         if (IS_IVYBRIDGE(dev))
2111                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2112                            FDI_FE_ERRC_ENABLE);
2113 }
2114
2115 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2116 {
2117         struct drm_i915_private *dev_priv = dev->dev_private;
2118         u32 flags = I915_READ(SOUTH_CHICKEN1);
2119
2120         flags |= FDI_PHASE_SYNC_OVR(pipe);
2121         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2122         flags |= FDI_PHASE_SYNC_EN(pipe);
2123         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2124         POSTING_READ(SOUTH_CHICKEN1);
2125 }
2126
2127 /* The FDI link training functions for ILK/Ibexpeak. */
2128 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = crtc->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133         int pipe = intel_crtc->pipe;
2134         int plane = intel_crtc->plane;
2135         u32 reg, temp, tries;
2136
2137         /* FDI needs bits from pipe & plane first */
2138         assert_pipe_enabled(dev_priv, pipe);
2139         assert_plane_enabled(dev_priv, plane);
2140
2141         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2142            for train result */
2143         reg = FDI_RX_IMR(pipe);
2144         temp = I915_READ(reg);
2145         temp &= ~FDI_RX_SYMBOL_LOCK;
2146         temp &= ~FDI_RX_BIT_LOCK;
2147         I915_WRITE(reg, temp);
2148         I915_READ(reg);
2149         udelay(150);
2150
2151         /* enable CPU FDI TX and PCH FDI RX */
2152         reg = FDI_TX_CTL(pipe);
2153         temp = I915_READ(reg);
2154         temp &= ~(7 << 19);
2155         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2156         temp &= ~FDI_LINK_TRAIN_NONE;
2157         temp |= FDI_LINK_TRAIN_PATTERN_1;
2158         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2159
2160         reg = FDI_RX_CTL(pipe);
2161         temp = I915_READ(reg);
2162         temp &= ~FDI_LINK_TRAIN_NONE;
2163         temp |= FDI_LINK_TRAIN_PATTERN_1;
2164         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2165
2166         POSTING_READ(reg);
2167         udelay(150);
2168
2169         /* Ironlake workaround, enable clock pointer after FDI enable*/
2170         if (HAS_PCH_IBX(dev)) {
2171                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2172                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2173                            FDI_RX_PHASE_SYNC_POINTER_EN);
2174         }
2175
2176         reg = FDI_RX_IIR(pipe);
2177         for (tries = 0; tries < 5; tries++) {
2178                 temp = I915_READ(reg);
2179                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2180
2181                 if ((temp & FDI_RX_BIT_LOCK)) {
2182                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2183                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2184                         break;
2185                 }
2186         }
2187         if (tries == 5)
2188                 DRM_ERROR("FDI train 1 fail!\n");
2189
2190         /* Train 2 */
2191         reg = FDI_TX_CTL(pipe);
2192         temp = I915_READ(reg);
2193         temp &= ~FDI_LINK_TRAIN_NONE;
2194         temp |= FDI_LINK_TRAIN_PATTERN_2;
2195         I915_WRITE(reg, temp);
2196
2197         reg = FDI_RX_CTL(pipe);
2198         temp = I915_READ(reg);
2199         temp &= ~FDI_LINK_TRAIN_NONE;
2200         temp |= FDI_LINK_TRAIN_PATTERN_2;
2201         I915_WRITE(reg, temp);
2202
2203         POSTING_READ(reg);
2204         udelay(150);
2205
2206         reg = FDI_RX_IIR(pipe);
2207         for (tries = 0; tries < 5; tries++) {
2208                 temp = I915_READ(reg);
2209                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2210
2211                 if (temp & FDI_RX_SYMBOL_LOCK) {
2212                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2213                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2214                         break;
2215                 }
2216         }
2217         if (tries == 5)
2218                 DRM_ERROR("FDI train 2 fail!\n");
2219
2220         DRM_DEBUG_KMS("FDI train done\n");
2221
2222 }
2223
2224 static const int snb_b_fdi_train_param[] = {
2225         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2226         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2227         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2228         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2229 };
2230
2231 /* The FDI link training functions for SNB/Cougarpoint. */
2232 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2233 {
2234         struct drm_device *dev = crtc->dev;
2235         struct drm_i915_private *dev_priv = dev->dev_private;
2236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2237         int pipe = intel_crtc->pipe;
2238         u32 reg, temp, i, retry;
2239
2240         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2241            for train result */
2242         reg = FDI_RX_IMR(pipe);
2243         temp = I915_READ(reg);
2244         temp &= ~FDI_RX_SYMBOL_LOCK;
2245         temp &= ~FDI_RX_BIT_LOCK;
2246         I915_WRITE(reg, temp);
2247
2248         POSTING_READ(reg);
2249         udelay(150);
2250
2251         /* enable CPU FDI TX and PCH FDI RX */
2252         reg = FDI_TX_CTL(pipe);
2253         temp = I915_READ(reg);
2254         temp &= ~(7 << 19);
2255         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2256         temp &= ~FDI_LINK_TRAIN_NONE;
2257         temp |= FDI_LINK_TRAIN_PATTERN_1;
2258         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2259         /* SNB-B */
2260         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2261         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2262
2263         reg = FDI_RX_CTL(pipe);
2264         temp = I915_READ(reg);
2265         if (HAS_PCH_CPT(dev)) {
2266                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2267                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2268         } else {
2269                 temp &= ~FDI_LINK_TRAIN_NONE;
2270                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2271         }
2272         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2273
2274         POSTING_READ(reg);
2275         udelay(150);
2276
2277         if (HAS_PCH_CPT(dev))
2278                 cpt_phase_pointer_enable(dev, pipe);
2279
2280         for (i = 0; i < 4; i++) {
2281                 reg = FDI_TX_CTL(pipe);
2282                 temp = I915_READ(reg);
2283                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2284                 temp |= snb_b_fdi_train_param[i];
2285                 I915_WRITE(reg, temp);
2286
2287                 POSTING_READ(reg);
2288                 udelay(500);
2289
2290                 for (retry = 0; retry < 5; retry++) {
2291                         reg = FDI_RX_IIR(pipe);
2292                         temp = I915_READ(reg);
2293                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2294                         if (temp & FDI_RX_BIT_LOCK) {
2295                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2296                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2297                                 break;
2298                         }
2299                         udelay(50);
2300                 }
2301                 if (retry < 5)
2302                         break;
2303         }
2304         if (i == 4)
2305                 DRM_ERROR("FDI train 1 fail!\n");
2306
2307         /* Train 2 */
2308         reg = FDI_TX_CTL(pipe);
2309         temp = I915_READ(reg);
2310         temp &= ~FDI_LINK_TRAIN_NONE;
2311         temp |= FDI_LINK_TRAIN_PATTERN_2;
2312         if (IS_GEN6(dev)) {
2313                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2314                 /* SNB-B */
2315                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2316         }
2317         I915_WRITE(reg, temp);
2318
2319         reg = FDI_RX_CTL(pipe);
2320         temp = I915_READ(reg);
2321         if (HAS_PCH_CPT(dev)) {
2322                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2323                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2324         } else {
2325                 temp &= ~FDI_LINK_TRAIN_NONE;
2326                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2327         }
2328         I915_WRITE(reg, temp);
2329
2330         POSTING_READ(reg);
2331         udelay(150);
2332
2333         for (i = 0; i < 4; i++) {
2334                 reg = FDI_TX_CTL(pipe);
2335                 temp = I915_READ(reg);
2336                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2337                 temp |= snb_b_fdi_train_param[i];
2338                 I915_WRITE(reg, temp);
2339
2340                 POSTING_READ(reg);
2341                 udelay(500);
2342
2343                 for (retry = 0; retry < 5; retry++) {
2344                         reg = FDI_RX_IIR(pipe);
2345                         temp = I915_READ(reg);
2346                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2347                         if (temp & FDI_RX_SYMBOL_LOCK) {
2348                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2349                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2350                                 break;
2351                         }
2352                         udelay(50);
2353                 }
2354                 if (retry < 5)
2355                         break;
2356         }
2357         if (i == 4)
2358                 DRM_ERROR("FDI train 2 fail!\n");
2359
2360         DRM_DEBUG_KMS("FDI train done.\n");
2361 }
2362
2363 /* Manual link training for Ivy Bridge A0 parts */
2364 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2365 {
2366         struct drm_device *dev = crtc->dev;
2367         struct drm_i915_private *dev_priv = dev->dev_private;
2368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2369         int pipe = intel_crtc->pipe;
2370         u32 reg, temp, i;
2371
2372         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2373            for train result */
2374         reg = FDI_RX_IMR(pipe);
2375         temp = I915_READ(reg);
2376         temp &= ~FDI_RX_SYMBOL_LOCK;
2377         temp &= ~FDI_RX_BIT_LOCK;
2378         I915_WRITE(reg, temp);
2379
2380         POSTING_READ(reg);
2381         udelay(150);
2382
2383         /* enable CPU FDI TX and PCH FDI RX */
2384         reg = FDI_TX_CTL(pipe);
2385         temp = I915_READ(reg);
2386         temp &= ~(7 << 19);
2387         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2388         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2389         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2390         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2391         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2392         temp |= FDI_COMPOSITE_SYNC;
2393         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2394
2395         reg = FDI_RX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         temp &= ~FDI_LINK_TRAIN_AUTO;
2398         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2399         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2400         temp |= FDI_COMPOSITE_SYNC;
2401         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2402
2403         POSTING_READ(reg);
2404         udelay(150);
2405
2406         if (HAS_PCH_CPT(dev))
2407                 cpt_phase_pointer_enable(dev, pipe);
2408
2409         for (i = 0; i < 4; i++) {
2410                 reg = FDI_TX_CTL(pipe);
2411                 temp = I915_READ(reg);
2412                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2413                 temp |= snb_b_fdi_train_param[i];
2414                 I915_WRITE(reg, temp);
2415
2416                 POSTING_READ(reg);
2417                 udelay(500);
2418
2419                 reg = FDI_RX_IIR(pipe);
2420                 temp = I915_READ(reg);
2421                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2422
2423                 if (temp & FDI_RX_BIT_LOCK ||
2424                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2425                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2426                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2427                         break;
2428                 }
2429         }
2430         if (i == 4)
2431                 DRM_ERROR("FDI train 1 fail!\n");
2432
2433         /* Train 2 */
2434         reg = FDI_TX_CTL(pipe);
2435         temp = I915_READ(reg);
2436         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2437         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2438         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2439         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2440         I915_WRITE(reg, temp);
2441
2442         reg = FDI_RX_CTL(pipe);
2443         temp = I915_READ(reg);
2444         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2445         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2446         I915_WRITE(reg, temp);
2447
2448         POSTING_READ(reg);
2449         udelay(150);
2450
2451         for (i = 0; i < 4; i++) {
2452                 reg = FDI_TX_CTL(pipe);
2453                 temp = I915_READ(reg);
2454                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2455                 temp |= snb_b_fdi_train_param[i];
2456                 I915_WRITE(reg, temp);
2457
2458                 POSTING_READ(reg);
2459                 udelay(500);
2460
2461                 reg = FDI_RX_IIR(pipe);
2462                 temp = I915_READ(reg);
2463                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2464
2465                 if (temp & FDI_RX_SYMBOL_LOCK) {
2466                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2467                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2468                         break;
2469                 }
2470         }
2471         if (i == 4)
2472                 DRM_ERROR("FDI train 2 fail!\n");
2473
2474         DRM_DEBUG_KMS("FDI train done.\n");
2475 }
2476
2477 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2478 {
2479         struct drm_device *dev = crtc->dev;
2480         struct drm_i915_private *dev_priv = dev->dev_private;
2481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2482         int pipe = intel_crtc->pipe;
2483         u32 reg, temp;
2484
2485         /* Write the TU size bits so error detection works */
2486         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2487                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2488
2489         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2490         reg = FDI_RX_CTL(pipe);
2491         temp = I915_READ(reg);
2492         temp &= ~((0x7 << 19) | (0x7 << 16));
2493         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2494         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2495         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2496
2497         POSTING_READ(reg);
2498         udelay(200);
2499
2500         /* Switch from Rawclk to PCDclk */
2501         temp = I915_READ(reg);
2502         I915_WRITE(reg, temp | FDI_PCDCLK);
2503
2504         POSTING_READ(reg);
2505         udelay(200);
2506
2507         /* Enable CPU FDI TX PLL, always on for Ironlake */
2508         reg = FDI_TX_CTL(pipe);
2509         temp = I915_READ(reg);
2510         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2511                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2512
2513                 POSTING_READ(reg);
2514                 udelay(100);
2515         }
2516 }
2517
2518 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2519 {
2520         struct drm_i915_private *dev_priv = dev->dev_private;
2521         u32 flags = I915_READ(SOUTH_CHICKEN1);
2522
2523         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2524         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2525         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2526         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2527         POSTING_READ(SOUTH_CHICKEN1);
2528 }
2529 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2530 {
2531         struct drm_device *dev = crtc->dev;
2532         struct drm_i915_private *dev_priv = dev->dev_private;
2533         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2534         int pipe = intel_crtc->pipe;
2535         u32 reg, temp;
2536
2537         /* disable CPU FDI tx and PCH FDI rx */
2538         reg = FDI_TX_CTL(pipe);
2539         temp = I915_READ(reg);
2540         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2541         POSTING_READ(reg);
2542
2543         reg = FDI_RX_CTL(pipe);
2544         temp = I915_READ(reg);
2545         temp &= ~(0x7 << 16);
2546         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2547         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2548
2549         POSTING_READ(reg);
2550         udelay(100);
2551
2552         /* Ironlake workaround, disable clock pointer after downing FDI */
2553         if (HAS_PCH_IBX(dev)) {
2554                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2555                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2556                            I915_READ(FDI_RX_CHICKEN(pipe) &
2557                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2558         } else if (HAS_PCH_CPT(dev)) {
2559                 cpt_phase_pointer_disable(dev, pipe);
2560         }
2561
2562         /* still set train pattern 1 */
2563         reg = FDI_TX_CTL(pipe);
2564         temp = I915_READ(reg);
2565         temp &= ~FDI_LINK_TRAIN_NONE;
2566         temp |= FDI_LINK_TRAIN_PATTERN_1;
2567         I915_WRITE(reg, temp);
2568
2569         reg = FDI_RX_CTL(pipe);
2570         temp = I915_READ(reg);
2571         if (HAS_PCH_CPT(dev)) {
2572                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2573                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2574         } else {
2575                 temp &= ~FDI_LINK_TRAIN_NONE;
2576                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2577         }
2578         /* BPC in FDI rx is consistent with that in PIPECONF */
2579         temp &= ~(0x07 << 16);
2580         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2581         I915_WRITE(reg, temp);
2582
2583         POSTING_READ(reg);
2584         udelay(100);
2585 }
2586
2587 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2588 {
2589         struct drm_device *dev = crtc->dev;
2590
2591         if (crtc->fb == NULL)
2592                 return;
2593
2594         mutex_lock(&dev->struct_mutex);
2595         intel_finish_fb(crtc->fb);
2596         mutex_unlock(&dev->struct_mutex);
2597 }
2598
2599 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2600 {
2601         struct drm_device *dev = crtc->dev;
2602         struct drm_mode_config *mode_config = &dev->mode_config;
2603         struct intel_encoder *encoder;
2604
2605         /*
2606          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2607          * must be driven by its own crtc; no sharing is possible.
2608          */
2609         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2610                 if (encoder->base.crtc != crtc)
2611                         continue;
2612
2613                 switch (encoder->type) {
2614                 case INTEL_OUTPUT_EDP:
2615                         if (!intel_encoder_is_pch_edp(&encoder->base))
2616                                 return false;
2617                         continue;
2618                 }
2619         }
2620
2621         return true;
2622 }
2623
2624 /*
2625  * Enable PCH resources required for PCH ports:
2626  *   - PCH PLLs
2627  *   - FDI training & RX/TX
2628  *   - update transcoder timings
2629  *   - DP transcoding bits
2630  *   - transcoder
2631  */
2632 static void ironlake_pch_enable(struct drm_crtc *crtc)
2633 {
2634         struct drm_device *dev = crtc->dev;
2635         struct drm_i915_private *dev_priv = dev->dev_private;
2636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637         int pipe = intel_crtc->pipe;
2638         u32 reg, temp;
2639
2640         /* For PCH output, training FDI link */
2641         dev_priv->display.fdi_link_train(crtc);
2642
2643         intel_enable_pch_pll(intel_crtc);
2644
2645         if (HAS_PCH_CPT(dev)) {
2646                 u32 sel;
2647
2648                 temp = I915_READ(PCH_DPLL_SEL);
2649                 switch (pipe) {
2650                 default:
2651                 case 0:
2652                         temp |= TRANSA_DPLL_ENABLE;
2653                         sel = TRANSA_DPLLB_SEL;
2654                         break;
2655                 case 1:
2656                         temp |= TRANSB_DPLL_ENABLE;
2657                         sel = TRANSB_DPLLB_SEL;
2658                         break;
2659                 case 2:
2660                         temp |= TRANSC_DPLL_ENABLE;
2661                         sel = TRANSC_DPLLB_SEL;
2662                         break;
2663                 }
2664                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2665                         temp |= sel;
2666                 else
2667                         temp &= ~sel;
2668                 I915_WRITE(PCH_DPLL_SEL, temp);
2669         }
2670
2671         /* set transcoder timing, panel must allow it */
2672         assert_panel_unlocked(dev_priv, pipe);
2673         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2674         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2675         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2676
2677         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2678         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2679         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2680         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
2681
2682         intel_fdi_normal_train(crtc);
2683
2684         /* For PCH DP, enable TRANS_DP_CTL */
2685         if (HAS_PCH_CPT(dev) &&
2686             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2687              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2688                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2689                 reg = TRANS_DP_CTL(pipe);
2690                 temp = I915_READ(reg);
2691                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2692                           TRANS_DP_SYNC_MASK |
2693                           TRANS_DP_BPC_MASK);
2694                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2695                          TRANS_DP_ENH_FRAMING);
2696                 temp |= bpc << 9; /* same format but at 11:9 */
2697
2698                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2699                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2700                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2701                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2702
2703                 switch (intel_trans_dp_port_sel(crtc)) {
2704                 case PCH_DP_B:
2705                         temp |= TRANS_DP_PORT_SEL_B;
2706                         break;
2707                 case PCH_DP_C:
2708                         temp |= TRANS_DP_PORT_SEL_C;
2709                         break;
2710                 case PCH_DP_D:
2711                         temp |= TRANS_DP_PORT_SEL_D;
2712                         break;
2713                 default:
2714                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2715                         temp |= TRANS_DP_PORT_SEL_B;
2716                         break;
2717                 }
2718
2719                 I915_WRITE(reg, temp);
2720         }
2721
2722         intel_enable_transcoder(dev_priv, pipe);
2723 }
2724
2725 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2726 {
2727         struct intel_pch_pll *pll = intel_crtc->pch_pll;
2728
2729         if (pll == NULL)
2730                 return;
2731
2732         if (pll->refcount == 0) {
2733                 WARN(1, "bad PCH PLL refcount\n");
2734                 return;
2735         }
2736
2737         --pll->refcount;
2738         intel_crtc->pch_pll = NULL;
2739 }
2740
2741 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2742 {
2743         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2744         struct intel_pch_pll *pll;
2745         int i;
2746
2747         pll = intel_crtc->pch_pll;
2748         if (pll) {
2749                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2750                               intel_crtc->base.base.id, pll->pll_reg);
2751                 goto prepare;
2752         }
2753
2754         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2755                 pll = &dev_priv->pch_plls[i];
2756
2757                 /* Only want to check enabled timings first */
2758                 if (pll->refcount == 0)
2759                         continue;
2760
2761                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2762                     fp == I915_READ(pll->fp0_reg)) {
2763                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2764                                       intel_crtc->base.base.id,
2765                                       pll->pll_reg, pll->refcount, pll->active);
2766
2767                         goto found;
2768                 }
2769         }
2770
2771         /* Ok no matching timings, maybe there's a free one? */
2772         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2773                 pll = &dev_priv->pch_plls[i];
2774                 if (pll->refcount == 0) {
2775                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2776                                       intel_crtc->base.base.id, pll->pll_reg);
2777                         goto found;
2778                 }
2779         }
2780
2781         return NULL;
2782
2783 found:
2784         intel_crtc->pch_pll = pll;
2785         pll->refcount++;
2786         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2787 prepare: /* separate function? */
2788         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2789
2790         /* Wait for the clocks to stabilize before rewriting the regs */
2791         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2792         POSTING_READ(pll->pll_reg);
2793         udelay(150);
2794
2795         I915_WRITE(pll->fp0_reg, fp);
2796         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2797         pll->on = false;
2798         return pll;
2799 }
2800
2801 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2802 {
2803         struct drm_i915_private *dev_priv = dev->dev_private;
2804         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2805         u32 temp;
2806
2807         temp = I915_READ(dslreg);
2808         udelay(500);
2809         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2810                 /* Without this, mode sets may fail silently on FDI */
2811                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2812                 udelay(250);
2813                 I915_WRITE(tc2reg, 0);
2814                 if (wait_for(I915_READ(dslreg) != temp, 5))
2815                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2816         }
2817 }
2818
2819 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2820 {
2821         struct drm_device *dev = crtc->dev;
2822         struct drm_i915_private *dev_priv = dev->dev_private;
2823         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2824         int pipe = intel_crtc->pipe;
2825         int plane = intel_crtc->plane;
2826         u32 temp;
2827         bool is_pch_port;
2828
2829         if (intel_crtc->active)
2830                 return;
2831
2832         intel_crtc->active = true;
2833         intel_update_watermarks(dev);
2834
2835         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2836                 temp = I915_READ(PCH_LVDS);
2837                 if ((temp & LVDS_PORT_EN) == 0)
2838                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2839         }
2840
2841         is_pch_port = intel_crtc_driving_pch(crtc);
2842
2843         if (is_pch_port)
2844                 ironlake_fdi_pll_enable(crtc);
2845         else
2846                 ironlake_fdi_disable(crtc);
2847
2848         /* Enable panel fitting for LVDS */
2849         if (dev_priv->pch_pf_size &&
2850             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2851                 /* Force use of hard-coded filter coefficients
2852                  * as some pre-programmed values are broken,
2853                  * e.g. x201.
2854                  */
2855                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2856                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2857                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2858         }
2859
2860         /*
2861          * On ILK+ LUT must be loaded before the pipe is running but with
2862          * clocks enabled
2863          */
2864         intel_crtc_load_lut(crtc);
2865
2866         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2867         intel_enable_plane(dev_priv, plane, pipe);
2868
2869         if (is_pch_port)
2870                 ironlake_pch_enable(crtc);
2871
2872         mutex_lock(&dev->struct_mutex);
2873         intel_update_fbc(dev);
2874         mutex_unlock(&dev->struct_mutex);
2875
2876         intel_crtc_update_cursor(crtc, true);
2877 }
2878
2879 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2880 {
2881         struct drm_device *dev = crtc->dev;
2882         struct drm_i915_private *dev_priv = dev->dev_private;
2883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2884         int pipe = intel_crtc->pipe;
2885         int plane = intel_crtc->plane;
2886         u32 reg, temp;
2887
2888         if (!intel_crtc->active)
2889                 return;
2890
2891         intel_crtc_wait_for_pending_flips(crtc);
2892         drm_vblank_off(dev, pipe);
2893         intel_crtc_update_cursor(crtc, false);
2894
2895         intel_disable_plane(dev_priv, plane, pipe);
2896
2897         if (dev_priv->cfb_plane == plane)
2898                 intel_disable_fbc(dev);
2899
2900         intel_disable_pipe(dev_priv, pipe);
2901
2902         /* Disable PF */
2903         I915_WRITE(PF_CTL(pipe), 0);
2904         I915_WRITE(PF_WIN_SZ(pipe), 0);
2905
2906         ironlake_fdi_disable(crtc);
2907
2908         /* This is a horrible layering violation; we should be doing this in
2909          * the connector/encoder ->prepare instead, but we don't always have
2910          * enough information there about the config to know whether it will
2911          * actually be necessary or just cause undesired flicker.
2912          */
2913         intel_disable_pch_ports(dev_priv, pipe);
2914
2915         intel_disable_transcoder(dev_priv, pipe);
2916
2917         if (HAS_PCH_CPT(dev)) {
2918                 /* disable TRANS_DP_CTL */
2919                 reg = TRANS_DP_CTL(pipe);
2920                 temp = I915_READ(reg);
2921                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2922                 temp |= TRANS_DP_PORT_SEL_NONE;
2923                 I915_WRITE(reg, temp);
2924
2925                 /* disable DPLL_SEL */
2926                 temp = I915_READ(PCH_DPLL_SEL);
2927                 switch (pipe) {
2928                 case 0:
2929                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2930                         break;
2931                 case 1:
2932                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2933                         break;
2934                 case 2:
2935                         /* C shares PLL A or B */
2936                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2937                         break;
2938                 default:
2939                         BUG(); /* wtf */
2940                 }
2941                 I915_WRITE(PCH_DPLL_SEL, temp);
2942         }
2943
2944         /* disable PCH DPLL */
2945         intel_disable_pch_pll(intel_crtc);
2946
2947         /* Switch from PCDclk to Rawclk */
2948         reg = FDI_RX_CTL(pipe);
2949         temp = I915_READ(reg);
2950         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2951
2952         /* Disable CPU FDI TX PLL */
2953         reg = FDI_TX_CTL(pipe);
2954         temp = I915_READ(reg);
2955         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2956
2957         POSTING_READ(reg);
2958         udelay(100);
2959
2960         reg = FDI_RX_CTL(pipe);
2961         temp = I915_READ(reg);
2962         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2963
2964         /* Wait for the clocks to turn off. */
2965         POSTING_READ(reg);
2966         udelay(100);
2967
2968         intel_crtc->active = false;
2969         intel_update_watermarks(dev);
2970
2971         mutex_lock(&dev->struct_mutex);
2972         intel_update_fbc(dev);
2973         mutex_unlock(&dev->struct_mutex);
2974 }
2975
2976 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2977 {
2978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2979         int pipe = intel_crtc->pipe;
2980         int plane = intel_crtc->plane;
2981
2982         /* XXX: When our outputs are all unaware of DPMS modes other than off
2983          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2984          */
2985         switch (mode) {
2986         case DRM_MODE_DPMS_ON:
2987         case DRM_MODE_DPMS_STANDBY:
2988         case DRM_MODE_DPMS_SUSPEND:
2989                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2990                 ironlake_crtc_enable(crtc);
2991                 break;
2992
2993         case DRM_MODE_DPMS_OFF:
2994                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2995                 ironlake_crtc_disable(crtc);
2996                 break;
2997         }
2998 }
2999
3000 static void ironlake_crtc_off(struct drm_crtc *crtc)
3001 {
3002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3003         intel_put_pch_pll(intel_crtc);
3004 }
3005
3006 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3007 {
3008         if (!enable && intel_crtc->overlay) {
3009                 struct drm_device *dev = intel_crtc->base.dev;
3010                 struct drm_i915_private *dev_priv = dev->dev_private;
3011
3012                 mutex_lock(&dev->struct_mutex);
3013                 dev_priv->mm.interruptible = false;
3014                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3015                 dev_priv->mm.interruptible = true;
3016                 mutex_unlock(&dev->struct_mutex);
3017         }
3018
3019         /* Let userspace switch the overlay on again. In most cases userspace
3020          * has to recompute where to put it anyway.
3021          */
3022 }
3023
3024 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3025 {
3026         struct drm_device *dev = crtc->dev;
3027         struct drm_i915_private *dev_priv = dev->dev_private;
3028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029         int pipe = intel_crtc->pipe;
3030         int plane = intel_crtc->plane;
3031
3032         if (intel_crtc->active)
3033                 return;
3034
3035         intel_crtc->active = true;
3036         intel_update_watermarks(dev);
3037
3038         intel_enable_pll(dev_priv, pipe);
3039         intel_enable_pipe(dev_priv, pipe, false);
3040         intel_enable_plane(dev_priv, plane, pipe);
3041
3042         intel_crtc_load_lut(crtc);
3043         intel_update_fbc(dev);
3044
3045         /* Give the overlay scaler a chance to enable if it's on this pipe */
3046         intel_crtc_dpms_overlay(intel_crtc, true);
3047         intel_crtc_update_cursor(crtc, true);
3048 }
3049
3050 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3051 {
3052         struct drm_device *dev = crtc->dev;
3053         struct drm_i915_private *dev_priv = dev->dev_private;
3054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3055         int pipe = intel_crtc->pipe;
3056         int plane = intel_crtc->plane;
3057
3058         if (!intel_crtc->active)
3059                 return;
3060
3061         /* Give the overlay scaler a chance to disable if it's on this pipe */
3062         intel_crtc_wait_for_pending_flips(crtc);
3063         drm_vblank_off(dev, pipe);
3064         intel_crtc_dpms_overlay(intel_crtc, false);
3065         intel_crtc_update_cursor(crtc, false);
3066
3067         if (dev_priv->cfb_plane == plane)
3068                 intel_disable_fbc(dev);
3069
3070         intel_disable_plane(dev_priv, plane, pipe);
3071         intel_disable_pipe(dev_priv, pipe);
3072         intel_disable_pll(dev_priv, pipe);
3073
3074         intel_crtc->active = false;
3075         intel_update_fbc(dev);
3076         intel_update_watermarks(dev);
3077 }
3078
3079 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3080 {
3081         /* XXX: When our outputs are all unaware of DPMS modes other than off
3082          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3083          */
3084         switch (mode) {
3085         case DRM_MODE_DPMS_ON:
3086         case DRM_MODE_DPMS_STANDBY:
3087         case DRM_MODE_DPMS_SUSPEND:
3088                 i9xx_crtc_enable(crtc);
3089                 break;
3090         case DRM_MODE_DPMS_OFF:
3091                 i9xx_crtc_disable(crtc);
3092                 break;
3093         }
3094 }
3095
3096 static void i9xx_crtc_off(struct drm_crtc *crtc)
3097 {
3098 }
3099
3100 /**
3101  * Sets the power management mode of the pipe and plane.
3102  */
3103 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3104 {
3105         struct drm_device *dev = crtc->dev;
3106         struct drm_i915_private *dev_priv = dev->dev_private;
3107         struct drm_i915_master_private *master_priv;
3108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3109         int pipe = intel_crtc->pipe;
3110         bool enabled;
3111
3112         if (intel_crtc->dpms_mode == mode)
3113                 return;
3114
3115         intel_crtc->dpms_mode = mode;
3116
3117         dev_priv->display.dpms(crtc, mode);
3118
3119         if (!dev->primary->master)
3120                 return;
3121
3122         master_priv = dev->primary->master->driver_priv;
3123         if (!master_priv->sarea_priv)
3124                 return;
3125
3126         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3127
3128         switch (pipe) {
3129         case 0:
3130                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3131                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3132                 break;
3133         case 1:
3134                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3135                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3136                 break;
3137         default:
3138                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3139                 break;
3140         }
3141 }
3142
3143 static void intel_crtc_disable(struct drm_crtc *crtc)
3144 {
3145         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3146         struct drm_device *dev = crtc->dev;
3147         struct drm_i915_private *dev_priv = dev->dev_private;
3148
3149         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3150         dev_priv->display.off(crtc);
3151
3152         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3153         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3154
3155         if (crtc->fb) {
3156                 mutex_lock(&dev->struct_mutex);
3157                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3158                 mutex_unlock(&dev->struct_mutex);
3159         }
3160 }
3161
3162 /* Prepare for a mode set.
3163  *
3164  * Note we could be a lot smarter here.  We need to figure out which outputs
3165  * will be enabled, which disabled (in short, how the config will changes)
3166  * and perform the minimum necessary steps to accomplish that, e.g. updating
3167  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3168  * panel fitting is in the proper state, etc.
3169  */
3170 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3171 {
3172         i9xx_crtc_disable(crtc);
3173 }
3174
3175 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3176 {
3177         i9xx_crtc_enable(crtc);
3178 }
3179
3180 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3181 {
3182         ironlake_crtc_disable(crtc);
3183 }
3184
3185 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3186 {
3187         ironlake_crtc_enable(crtc);
3188 }
3189
3190 void intel_encoder_prepare(struct drm_encoder *encoder)
3191 {
3192         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3193         /* lvds has its own version of prepare see intel_lvds_prepare */
3194         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3195 }
3196
3197 void intel_encoder_commit(struct drm_encoder *encoder)
3198 {
3199         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3200         struct drm_device *dev = encoder->dev;
3201         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3202
3203         /* lvds has its own version of commit see intel_lvds_commit */
3204         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3205
3206         if (HAS_PCH_CPT(dev))
3207                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3208 }
3209
3210 void intel_encoder_destroy(struct drm_encoder *encoder)
3211 {
3212         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3213
3214         drm_encoder_cleanup(encoder);
3215         kfree(intel_encoder);
3216 }
3217
3218 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3219                                   struct drm_display_mode *mode,
3220                                   struct drm_display_mode *adjusted_mode)
3221 {
3222         struct drm_device *dev = crtc->dev;
3223
3224         if (HAS_PCH_SPLIT(dev)) {
3225                 /* FDI link clock is fixed at 2.7G */
3226                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3227                         return false;
3228         }
3229
3230         /* All interlaced capable intel hw wants timings in frames. Note though
3231          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3232          * timings, so we need to be careful not to clobber these.*/
3233         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3234                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3235
3236         return true;
3237 }
3238
3239 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3240 {
3241         return 400000; /* FIXME */
3242 }
3243
3244 static int i945_get_display_clock_speed(struct drm_device *dev)
3245 {
3246         return 400000;
3247 }
3248
3249 static int i915_get_display_clock_speed(struct drm_device *dev)
3250 {
3251         return 333000;
3252 }
3253
3254 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3255 {
3256         return 200000;
3257 }
3258
3259 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3260 {
3261         u16 gcfgc = 0;
3262
3263         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3264
3265         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3266                 return 133000;
3267         else {
3268                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3269                 case GC_DISPLAY_CLOCK_333_MHZ:
3270                         return 333000;
3271                 default:
3272                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3273                         return 190000;
3274                 }
3275         }
3276 }
3277
3278 static int i865_get_display_clock_speed(struct drm_device *dev)
3279 {
3280         return 266000;
3281 }
3282
3283 static int i855_get_display_clock_speed(struct drm_device *dev)
3284 {
3285         u16 hpllcc = 0;
3286         /* Assume that the hardware is in the high speed state.  This
3287          * should be the default.
3288          */
3289         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3290         case GC_CLOCK_133_200:
3291         case GC_CLOCK_100_200:
3292                 return 200000;
3293         case GC_CLOCK_166_250:
3294                 return 250000;
3295         case GC_CLOCK_100_133:
3296                 return 133000;
3297         }
3298
3299         /* Shouldn't happen */
3300         return 0;
3301 }
3302
3303 static int i830_get_display_clock_speed(struct drm_device *dev)
3304 {
3305         return 133000;
3306 }
3307
3308 struct fdi_m_n {
3309         u32        tu;
3310         u32        gmch_m;
3311         u32        gmch_n;
3312         u32        link_m;
3313         u32        link_n;
3314 };
3315
3316 static void
3317 fdi_reduce_ratio(u32 *num, u32 *den)
3318 {
3319         while (*num > 0xffffff || *den > 0xffffff) {
3320                 *num >>= 1;
3321                 *den >>= 1;
3322         }
3323 }
3324
3325 static void
3326 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3327                      int link_clock, struct fdi_m_n *m_n)
3328 {
3329         m_n->tu = 64; /* default size */
3330
3331         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3332         m_n->gmch_m = bits_per_pixel * pixel_clock;
3333         m_n->gmch_n = link_clock * nlanes * 8;
3334         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3335
3336         m_n->link_m = pixel_clock;
3337         m_n->link_n = link_clock;
3338         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3339 }
3340
3341 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3342 {
3343         if (i915_panel_use_ssc >= 0)
3344                 return i915_panel_use_ssc != 0;
3345         return dev_priv->lvds_use_ssc
3346                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3347 }
3348
3349 /**
3350  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3351  * @crtc: CRTC structure
3352  * @mode: requested mode
3353  *
3354  * A pipe may be connected to one or more outputs.  Based on the depth of the
3355  * attached framebuffer, choose a good color depth to use on the pipe.
3356  *
3357  * If possible, match the pipe depth to the fb depth.  In some cases, this
3358  * isn't ideal, because the connected output supports a lesser or restricted
3359  * set of depths.  Resolve that here:
3360  *    LVDS typically supports only 6bpc, so clamp down in that case
3361  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3362  *    Displays may support a restricted set as well, check EDID and clamp as
3363  *      appropriate.
3364  *    DP may want to dither down to 6bpc to fit larger modes
3365  *
3366  * RETURNS:
3367  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3368  * true if they don't match).
3369  */
3370 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3371                                          unsigned int *pipe_bpp,
3372                                          struct drm_display_mode *mode)
3373 {
3374         struct drm_device *dev = crtc->dev;
3375         struct drm_i915_private *dev_priv = dev->dev_private;
3376         struct drm_encoder *encoder;
3377         struct drm_connector *connector;
3378         unsigned int display_bpc = UINT_MAX, bpc;
3379
3380         /* Walk the encoders & connectors on this crtc, get min bpc */
3381         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3382                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3383
3384                 if (encoder->crtc != crtc)
3385                         continue;
3386
3387                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3388                         unsigned int lvds_bpc;
3389
3390                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3391                             LVDS_A3_POWER_UP)
3392                                 lvds_bpc = 8;
3393                         else
3394                                 lvds_bpc = 6;
3395
3396                         if (lvds_bpc < display_bpc) {
3397                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3398                                 display_bpc = lvds_bpc;
3399                         }
3400                         continue;
3401                 }
3402
3403                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3404                         /* Use VBT settings if we have an eDP panel */
3405                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3406
3407                         if (edp_bpc < display_bpc) {
3408                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3409                                 display_bpc = edp_bpc;
3410                         }
3411                         continue;
3412                 }
3413
3414                 /* Not one of the known troublemakers, check the EDID */
3415                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3416                                     head) {
3417                         if (connector->encoder != encoder)
3418                                 continue;
3419
3420                         /* Don't use an invalid EDID bpc value */
3421                         if (connector->display_info.bpc &&
3422                             connector->display_info.bpc < display_bpc) {
3423                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3424                                 display_bpc = connector->display_info.bpc;
3425                         }
3426                 }
3427
3428                 /*
3429                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3430                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3431                  */
3432                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3433                         if (display_bpc > 8 && display_bpc < 12) {
3434                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3435                                 display_bpc = 12;
3436                         } else {
3437                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3438                                 display_bpc = 8;
3439                         }
3440                 }
3441         }
3442
3443         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3444                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3445                 display_bpc = 6;
3446         }
3447
3448         /*
3449          * We could just drive the pipe at the highest bpc all the time and
3450          * enable dithering as needed, but that costs bandwidth.  So choose
3451          * the minimum value that expresses the full color range of the fb but
3452          * also stays within the max display bpc discovered above.
3453          */
3454
3455         switch (crtc->fb->depth) {
3456         case 8:
3457                 bpc = 8; /* since we go through a colormap */
3458                 break;
3459         case 15:
3460         case 16:
3461                 bpc = 6; /* min is 18bpp */
3462                 break;
3463         case 24:
3464                 bpc = 8;
3465                 break;
3466         case 30:
3467                 bpc = 10;
3468                 break;
3469         case 48:
3470                 bpc = 12;
3471                 break;
3472         default:
3473                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3474                 bpc = min((unsigned int)8, display_bpc);
3475                 break;
3476         }
3477
3478         display_bpc = min(display_bpc, bpc);
3479
3480         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3481                       bpc, display_bpc);
3482
3483         *pipe_bpp = display_bpc * 3;
3484
3485         return display_bpc != bpc;
3486 }
3487
3488 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3489 {
3490         struct drm_device *dev = crtc->dev;
3491         struct drm_i915_private *dev_priv = dev->dev_private;
3492         int refclk;
3493
3494         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3495             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3496                 refclk = dev_priv->lvds_ssc_freq * 1000;
3497                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3498                               refclk / 1000);
3499         } else if (!IS_GEN2(dev)) {
3500                 refclk = 96000;
3501         } else {
3502                 refclk = 48000;
3503         }
3504
3505         return refclk;
3506 }
3507
3508 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3509                                       intel_clock_t *clock)
3510 {
3511         /* SDVO TV has fixed PLL values depend on its clock range,
3512            this mirrors vbios setting. */
3513         if (adjusted_mode->clock >= 100000
3514             && adjusted_mode->clock < 140500) {
3515                 clock->p1 = 2;
3516                 clock->p2 = 10;
3517                 clock->n = 3;
3518                 clock->m1 = 16;
3519                 clock->m2 = 8;
3520         } else if (adjusted_mode->clock >= 140500
3521                    && adjusted_mode->clock <= 200000) {
3522                 clock->p1 = 1;
3523                 clock->p2 = 10;
3524                 clock->n = 6;
3525                 clock->m1 = 12;
3526                 clock->m2 = 8;
3527         }
3528 }
3529
3530 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3531                                      intel_clock_t *clock,
3532                                      intel_clock_t *reduced_clock)
3533 {
3534         struct drm_device *dev = crtc->dev;
3535         struct drm_i915_private *dev_priv = dev->dev_private;
3536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3537         int pipe = intel_crtc->pipe;
3538         u32 fp, fp2 = 0;
3539
3540         if (IS_PINEVIEW(dev)) {
3541                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3542                 if (reduced_clock)
3543                         fp2 = (1 << reduced_clock->n) << 16 |
3544                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3545         } else {
3546                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3547                 if (reduced_clock)
3548                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3549                                 reduced_clock->m2;
3550         }
3551
3552         I915_WRITE(FP0(pipe), fp);
3553
3554         intel_crtc->lowfreq_avail = false;
3555         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3556             reduced_clock && i915_powersave) {
3557                 I915_WRITE(FP1(pipe), fp2);
3558                 intel_crtc->lowfreq_avail = true;
3559         } else {
3560                 I915_WRITE(FP1(pipe), fp);
3561         }
3562 }
3563
3564 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3565                               struct drm_display_mode *adjusted_mode)
3566 {
3567         struct drm_device *dev = crtc->dev;
3568         struct drm_i915_private *dev_priv = dev->dev_private;
3569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3570         int pipe = intel_crtc->pipe;
3571         u32 temp;
3572
3573         temp = I915_READ(LVDS);
3574         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3575         if (pipe == 1) {
3576                 temp |= LVDS_PIPEB_SELECT;
3577         } else {
3578                 temp &= ~LVDS_PIPEB_SELECT;
3579         }
3580         /* set the corresponsding LVDS_BORDER bit */
3581         temp |= dev_priv->lvds_border_bits;
3582         /* Set the B0-B3 data pairs corresponding to whether we're going to
3583          * set the DPLLs for dual-channel mode or not.
3584          */
3585         if (clock->p2 == 7)
3586                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3587         else
3588                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3589
3590         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3591          * appropriately here, but we need to look more thoroughly into how
3592          * panels behave in the two modes.
3593          */
3594         /* set the dithering flag on LVDS as needed */
3595         if (INTEL_INFO(dev)->gen >= 4) {
3596                 if (dev_priv->lvds_dither)
3597                         temp |= LVDS_ENABLE_DITHER;
3598                 else
3599                         temp &= ~LVDS_ENABLE_DITHER;
3600         }
3601         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3602         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3603                 temp |= LVDS_HSYNC_POLARITY;
3604         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3605                 temp |= LVDS_VSYNC_POLARITY;
3606         I915_WRITE(LVDS, temp);
3607 }
3608
3609 static void i9xx_update_pll(struct drm_crtc *crtc,
3610                             struct drm_display_mode *mode,
3611                             struct drm_display_mode *adjusted_mode,
3612                             intel_clock_t *clock, intel_clock_t *reduced_clock,
3613                             int num_connectors)
3614 {
3615         struct drm_device *dev = crtc->dev;
3616         struct drm_i915_private *dev_priv = dev->dev_private;
3617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3618         int pipe = intel_crtc->pipe;
3619         u32 dpll;
3620         bool is_sdvo;
3621
3622         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3623                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3624
3625         dpll = DPLL_VGA_MODE_DIS;
3626
3627         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3628                 dpll |= DPLLB_MODE_LVDS;
3629         else
3630                 dpll |= DPLLB_MODE_DAC_SERIAL;
3631         if (is_sdvo) {
3632                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3633                 if (pixel_multiplier > 1) {
3634                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3635                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3636                 }
3637                 dpll |= DPLL_DVO_HIGH_SPEED;
3638         }
3639         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3640                 dpll |= DPLL_DVO_HIGH_SPEED;
3641
3642         /* compute bitmask from p1 value */
3643         if (IS_PINEVIEW(dev))
3644                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3645         else {
3646                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3647                 if (IS_G4X(dev) && reduced_clock)
3648                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3649         }
3650         switch (clock->p2) {
3651         case 5:
3652                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3653                 break;
3654         case 7:
3655                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3656                 break;
3657         case 10:
3658                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3659                 break;
3660         case 14:
3661                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3662                 break;
3663         }
3664         if (INTEL_INFO(dev)->gen >= 4)
3665                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3666
3667         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3668                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3669         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3670                 /* XXX: just matching BIOS for now */
3671                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3672                 dpll |= 3;
3673         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3674                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3675                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3676         else
3677                 dpll |= PLL_REF_INPUT_DREFCLK;
3678
3679         dpll |= DPLL_VCO_ENABLE;
3680         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3681         POSTING_READ(DPLL(pipe));
3682         udelay(150);
3683
3684         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3685          * This is an exception to the general rule that mode_set doesn't turn
3686          * things on.
3687          */
3688         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3689                 intel_update_lvds(crtc, clock, adjusted_mode);
3690
3691         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3692                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3693
3694         I915_WRITE(DPLL(pipe), dpll);
3695
3696         /* Wait for the clocks to stabilize. */
3697         POSTING_READ(DPLL(pipe));
3698         udelay(150);
3699
3700         if (INTEL_INFO(dev)->gen >= 4) {
3701                 u32 temp = 0;
3702                 if (is_sdvo) {
3703                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3704                         if (temp > 1)
3705                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3706                         else
3707                                 temp = 0;
3708                 }
3709                 I915_WRITE(DPLL_MD(pipe), temp);
3710         } else {
3711                 /* The pixel multiplier can only be updated once the
3712                  * DPLL is enabled and the clocks are stable.
3713                  *
3714                  * So write it again.
3715                  */
3716                 I915_WRITE(DPLL(pipe), dpll);
3717         }
3718 }
3719
3720 static void i8xx_update_pll(struct drm_crtc *crtc,
3721                             struct drm_display_mode *adjusted_mode,
3722                             intel_clock_t *clock,
3723                             int num_connectors)
3724 {
3725         struct drm_device *dev = crtc->dev;
3726         struct drm_i915_private *dev_priv = dev->dev_private;
3727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3728         int pipe = intel_crtc->pipe;
3729         u32 dpll;
3730
3731         dpll = DPLL_VGA_MODE_DIS;
3732
3733         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3734                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3735         } else {
3736                 if (clock->p1 == 2)
3737                         dpll |= PLL_P1_DIVIDE_BY_TWO;
3738                 else
3739                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3740                 if (clock->p2 == 4)
3741                         dpll |= PLL_P2_DIVIDE_BY_4;
3742         }
3743
3744         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3745                 /* XXX: just matching BIOS for now */
3746                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3747                 dpll |= 3;
3748         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3749                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3750                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3751         else
3752                 dpll |= PLL_REF_INPUT_DREFCLK;
3753
3754         dpll |= DPLL_VCO_ENABLE;
3755         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3756         POSTING_READ(DPLL(pipe));
3757         udelay(150);
3758
3759         I915_WRITE(DPLL(pipe), dpll);
3760
3761         /* Wait for the clocks to stabilize. */
3762         POSTING_READ(DPLL(pipe));
3763         udelay(150);
3764
3765         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3766          * This is an exception to the general rule that mode_set doesn't turn
3767          * things on.
3768          */
3769         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3770                 intel_update_lvds(crtc, clock, adjusted_mode);
3771
3772         /* The pixel multiplier can only be updated once the
3773          * DPLL is enabled and the clocks are stable.
3774          *
3775          * So write it again.
3776          */
3777         I915_WRITE(DPLL(pipe), dpll);
3778 }
3779
3780 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3781                               struct drm_display_mode *mode,
3782                               struct drm_display_mode *adjusted_mode,
3783                               int x, int y,
3784                               struct drm_framebuffer *old_fb)
3785 {
3786         struct drm_device *dev = crtc->dev;
3787         struct drm_i915_private *dev_priv = dev->dev_private;
3788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3789         int pipe = intel_crtc->pipe;
3790         int plane = intel_crtc->plane;
3791         int refclk, num_connectors = 0;
3792         intel_clock_t clock, reduced_clock;
3793         u32 dspcntr, pipeconf, vsyncshift;
3794         bool ok, has_reduced_clock = false, is_sdvo = false;
3795         bool is_lvds = false, is_tv = false, is_dp = false;
3796         struct drm_mode_config *mode_config = &dev->mode_config;
3797         struct intel_encoder *encoder;
3798         const intel_limit_t *limit;
3799         int ret;
3800
3801         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3802                 if (encoder->base.crtc != crtc)
3803                         continue;
3804
3805                 switch (encoder->type) {
3806                 case INTEL_OUTPUT_LVDS:
3807                         is_lvds = true;
3808                         break;
3809                 case INTEL_OUTPUT_SDVO:
3810                 case INTEL_OUTPUT_HDMI:
3811                         is_sdvo = true;
3812                         if (encoder->needs_tv_clock)
3813                                 is_tv = true;
3814                         break;
3815                 case INTEL_OUTPUT_TVOUT:
3816                         is_tv = true;
3817                         break;
3818                 case INTEL_OUTPUT_DISPLAYPORT:
3819                         is_dp = true;
3820                         break;
3821                 }
3822
3823                 num_connectors++;
3824         }
3825
3826         refclk = i9xx_get_refclk(crtc, num_connectors);
3827
3828         /*
3829          * Returns a set of divisors for the desired target clock with the given
3830          * refclk, or FALSE.  The returned values represent the clock equation:
3831          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3832          */
3833         limit = intel_limit(crtc, refclk);
3834         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3835                              &clock);
3836         if (!ok) {
3837                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3838                 return -EINVAL;
3839         }
3840
3841         /* Ensure that the cursor is valid for the new mode before changing... */
3842         intel_crtc_update_cursor(crtc, true);
3843
3844         if (is_lvds && dev_priv->lvds_downclock_avail) {
3845                 /*
3846                  * Ensure we match the reduced clock's P to the target clock.
3847                  * If the clocks don't match, we can't switch the display clock
3848                  * by using the FP0/FP1. In such case we will disable the LVDS
3849                  * downclock feature.
3850                 */
3851                 has_reduced_clock = limit->find_pll(limit, crtc,
3852                                                     dev_priv->lvds_downclock,
3853                                                     refclk,
3854                                                     &clock,
3855                                                     &reduced_clock);
3856         }
3857
3858         if (is_sdvo && is_tv)
3859                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
3860
3861         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3862                                  &reduced_clock : NULL);
3863
3864         if (IS_GEN2(dev))
3865                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
3866         else
3867                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3868                                 has_reduced_clock ? &reduced_clock : NULL,
3869                                 num_connectors);
3870
3871         /* setup pipeconf */
3872         pipeconf = I915_READ(PIPECONF(pipe));
3873
3874         /* Set up the display plane register */
3875         dspcntr = DISPPLANE_GAMMA_ENABLE;
3876
3877         if (pipe == 0)
3878                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3879         else
3880                 dspcntr |= DISPPLANE_SEL_PIPE_B;
3881
3882         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3883                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3884                  * core speed.
3885                  *
3886                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3887                  * pipe == 0 check?
3888                  */
3889                 if (mode->clock >
3890                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3891                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3892                 else
3893                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3894         }
3895
3896         /* default to 8bpc */
3897         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3898         if (is_dp) {
3899                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3900                         pipeconf |= PIPECONF_BPP_6 |
3901                                     PIPECONF_DITHER_EN |
3902                                     PIPECONF_DITHER_TYPE_SP;
3903                 }
3904         }
3905
3906         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3907         drm_mode_debug_printmodeline(mode);
3908
3909         if (HAS_PIPE_CXSR(dev)) {
3910                 if (intel_crtc->lowfreq_avail) {
3911                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3912                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3913                 } else {
3914                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3915                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3916                 }
3917         }
3918
3919         pipeconf &= ~PIPECONF_INTERLACE_MASK;
3920         if (!IS_GEN2(dev) &&
3921             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3922                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3923                 /* the chip adds 2 halflines automatically */
3924                 adjusted_mode->crtc_vtotal -= 1;
3925                 adjusted_mode->crtc_vblank_end -= 1;
3926                 vsyncshift = adjusted_mode->crtc_hsync_start
3927                              - adjusted_mode->crtc_htotal/2;
3928         } else {
3929                 pipeconf |= PIPECONF_PROGRESSIVE;
3930                 vsyncshift = 0;
3931         }
3932
3933         if (!IS_GEN3(dev))
3934                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
3935
3936         I915_WRITE(HTOTAL(pipe),
3937                    (adjusted_mode->crtc_hdisplay - 1) |
3938                    ((adjusted_mode->crtc_htotal - 1) << 16));
3939         I915_WRITE(HBLANK(pipe),
3940                    (adjusted_mode->crtc_hblank_start - 1) |
3941                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3942         I915_WRITE(HSYNC(pipe),
3943                    (adjusted_mode->crtc_hsync_start - 1) |
3944                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3945
3946         I915_WRITE(VTOTAL(pipe),
3947                    (adjusted_mode->crtc_vdisplay - 1) |
3948                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3949         I915_WRITE(VBLANK(pipe),
3950                    (adjusted_mode->crtc_vblank_start - 1) |
3951                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3952         I915_WRITE(VSYNC(pipe),
3953                    (adjusted_mode->crtc_vsync_start - 1) |
3954                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3955
3956         /* pipesrc and dspsize control the size that is scaled from,
3957          * which should always be the user's requested size.
3958          */
3959         I915_WRITE(DSPSIZE(plane),
3960                    ((mode->vdisplay - 1) << 16) |
3961                    (mode->hdisplay - 1));
3962         I915_WRITE(DSPPOS(plane), 0);
3963         I915_WRITE(PIPESRC(pipe),
3964                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3965
3966         I915_WRITE(PIPECONF(pipe), pipeconf);
3967         POSTING_READ(PIPECONF(pipe));
3968         intel_enable_pipe(dev_priv, pipe, false);
3969
3970         intel_wait_for_vblank(dev, pipe);
3971
3972         I915_WRITE(DSPCNTR(plane), dspcntr);
3973         POSTING_READ(DSPCNTR(plane));
3974
3975         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3976
3977         intel_update_watermarks(dev);
3978
3979         return ret;
3980 }
3981
3982 /*
3983  * Initialize reference clocks when the driver loads
3984  */
3985 void ironlake_init_pch_refclk(struct drm_device *dev)
3986 {
3987         struct drm_i915_private *dev_priv = dev->dev_private;
3988         struct drm_mode_config *mode_config = &dev->mode_config;
3989         struct intel_encoder *encoder;
3990         u32 temp;
3991         bool has_lvds = false;
3992         bool has_cpu_edp = false;
3993         bool has_pch_edp = false;
3994         bool has_panel = false;
3995         bool has_ck505 = false;
3996         bool can_ssc = false;
3997
3998         /* We need to take the global config into account */
3999         list_for_each_entry(encoder, &mode_config->encoder_list,
4000                             base.head) {
4001                 switch (encoder->type) {
4002                 case INTEL_OUTPUT_LVDS:
4003                         has_panel = true;
4004                         has_lvds = true;
4005                         break;
4006                 case INTEL_OUTPUT_EDP:
4007                         has_panel = true;
4008                         if (intel_encoder_is_pch_edp(&encoder->base))
4009                                 has_pch_edp = true;
4010                         else
4011                                 has_cpu_edp = true;
4012                         break;
4013                 }
4014         }
4015
4016         if (HAS_PCH_IBX(dev)) {
4017                 has_ck505 = dev_priv->display_clock_mode;
4018                 can_ssc = has_ck505;
4019         } else {
4020                 has_ck505 = false;
4021                 can_ssc = true;
4022         }
4023
4024         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4025                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4026                       has_ck505);
4027
4028         /* Ironlake: try to setup display ref clock before DPLL
4029          * enabling. This is only under driver's control after
4030          * PCH B stepping, previous chipset stepping should be
4031          * ignoring this setting.
4032          */
4033         temp = I915_READ(PCH_DREF_CONTROL);
4034         /* Always enable nonspread source */
4035         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4036
4037         if (has_ck505)
4038                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4039         else
4040                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4041
4042         if (has_panel) {
4043                 temp &= ~DREF_SSC_SOURCE_MASK;
4044                 temp |= DREF_SSC_SOURCE_ENABLE;
4045
4046                 /* SSC must be turned on before enabling the CPU output  */
4047                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4048                         DRM_DEBUG_KMS("Using SSC on panel\n");
4049                         temp |= DREF_SSC1_ENABLE;
4050                 } else
4051                         temp &= ~DREF_SSC1_ENABLE;
4052
4053                 /* Get SSC going before enabling the outputs */
4054                 I915_WRITE(PCH_DREF_CONTROL, temp);
4055                 POSTING_READ(PCH_DREF_CONTROL);
4056                 udelay(200);
4057
4058                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4059
4060                 /* Enable CPU source on CPU attached eDP */
4061                 if (has_cpu_edp) {
4062                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4063                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4064                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4065                         }
4066                         else
4067                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4068                 } else
4069                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4070
4071                 I915_WRITE(PCH_DREF_CONTROL, temp);
4072                 POSTING_READ(PCH_DREF_CONTROL);
4073                 udelay(200);
4074         } else {
4075                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4076
4077                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4078
4079                 /* Turn off CPU output */
4080                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4081
4082                 I915_WRITE(PCH_DREF_CONTROL, temp);
4083                 POSTING_READ(PCH_DREF_CONTROL);
4084                 udelay(200);
4085
4086                 /* Turn off the SSC source */
4087                 temp &= ~DREF_SSC_SOURCE_MASK;
4088                 temp |= DREF_SSC_SOURCE_DISABLE;
4089
4090                 /* Turn off SSC1 */
4091                 temp &= ~ DREF_SSC1_ENABLE;
4092
4093                 I915_WRITE(PCH_DREF_CONTROL, temp);
4094                 POSTING_READ(PCH_DREF_CONTROL);
4095                 udelay(200);
4096         }
4097 }
4098
4099 static int ironlake_get_refclk(struct drm_crtc *crtc)
4100 {
4101         struct drm_device *dev = crtc->dev;
4102         struct drm_i915_private *dev_priv = dev->dev_private;
4103         struct intel_encoder *encoder;
4104         struct drm_mode_config *mode_config = &dev->mode_config;
4105         struct intel_encoder *edp_encoder = NULL;
4106         int num_connectors = 0;
4107         bool is_lvds = false;
4108
4109         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4110                 if (encoder->base.crtc != crtc)
4111                         continue;
4112
4113                 switch (encoder->type) {
4114                 case INTEL_OUTPUT_LVDS:
4115                         is_lvds = true;
4116                         break;
4117                 case INTEL_OUTPUT_EDP:
4118                         edp_encoder = encoder;
4119                         break;
4120                 }
4121                 num_connectors++;
4122         }
4123
4124         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4125                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4126                               dev_priv->lvds_ssc_freq);
4127                 return dev_priv->lvds_ssc_freq * 1000;
4128         }
4129
4130         return 120000;
4131 }
4132
4133 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4134                                   struct drm_display_mode *mode,
4135                                   struct drm_display_mode *adjusted_mode,
4136                                   int x, int y,
4137                                   struct drm_framebuffer *old_fb)
4138 {
4139         struct drm_device *dev = crtc->dev;
4140         struct drm_i915_private *dev_priv = dev->dev_private;
4141         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4142         int pipe = intel_crtc->pipe;
4143         int plane = intel_crtc->plane;
4144         int refclk, num_connectors = 0;
4145         intel_clock_t clock, reduced_clock;
4146         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4147         bool ok, has_reduced_clock = false, is_sdvo = false;
4148         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4149         struct drm_mode_config *mode_config = &dev->mode_config;
4150         struct intel_encoder *encoder, *edp_encoder = NULL;
4151         const intel_limit_t *limit;
4152         int ret;
4153         struct fdi_m_n m_n = {0};
4154         u32 temp;
4155         int target_clock, pixel_multiplier, lane, link_bw, factor;
4156         unsigned int pipe_bpp;
4157         bool dither;
4158         bool is_cpu_edp = false, is_pch_edp = false;
4159
4160         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4161                 if (encoder->base.crtc != crtc)
4162                         continue;
4163
4164                 switch (encoder->type) {
4165                 case INTEL_OUTPUT_LVDS:
4166                         is_lvds = true;
4167                         break;
4168                 case INTEL_OUTPUT_SDVO:
4169                 case INTEL_OUTPUT_HDMI:
4170                         is_sdvo = true;
4171                         if (encoder->needs_tv_clock)
4172                                 is_tv = true;
4173                         break;
4174                 case INTEL_OUTPUT_TVOUT:
4175                         is_tv = true;
4176                         break;
4177                 case INTEL_OUTPUT_ANALOG:
4178                         is_crt = true;
4179                         break;
4180                 case INTEL_OUTPUT_DISPLAYPORT:
4181                         is_dp = true;
4182                         break;
4183                 case INTEL_OUTPUT_EDP:
4184                         is_dp = true;
4185                         if (intel_encoder_is_pch_edp(&encoder->base))
4186                                 is_pch_edp = true;
4187                         else
4188                                 is_cpu_edp = true;
4189                         edp_encoder = encoder;
4190                         break;
4191                 }
4192
4193                 num_connectors++;
4194         }
4195
4196         refclk = ironlake_get_refclk(crtc);
4197
4198         /*
4199          * Returns a set of divisors for the desired target clock with the given
4200          * refclk, or FALSE.  The returned values represent the clock equation:
4201          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4202          */
4203         limit = intel_limit(crtc, refclk);
4204         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4205                              &clock);
4206         if (!ok) {
4207                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4208                 return -EINVAL;
4209         }
4210
4211         /* Ensure that the cursor is valid for the new mode before changing... */
4212         intel_crtc_update_cursor(crtc, true);
4213
4214         if (is_lvds && dev_priv->lvds_downclock_avail) {
4215                 /*
4216                  * Ensure we match the reduced clock's P to the target clock.
4217                  * If the clocks don't match, we can't switch the display clock
4218                  * by using the FP0/FP1. In such case we will disable the LVDS
4219                  * downclock feature.
4220                 */
4221                 has_reduced_clock = limit->find_pll(limit, crtc,
4222                                                     dev_priv->lvds_downclock,
4223                                                     refclk,
4224                                                     &clock,
4225                                                     &reduced_clock);
4226         }
4227         /* SDVO TV has fixed PLL values depend on its clock range,
4228            this mirrors vbios setting. */
4229         if (is_sdvo && is_tv) {
4230                 if (adjusted_mode->clock >= 100000
4231                     && adjusted_mode->clock < 140500) {
4232                         clock.p1 = 2;
4233                         clock.p2 = 10;
4234                         clock.n = 3;
4235                         clock.m1 = 16;
4236                         clock.m2 = 8;
4237                 } else if (adjusted_mode->clock >= 140500
4238                            && adjusted_mode->clock <= 200000) {
4239                         clock.p1 = 1;
4240                         clock.p2 = 10;
4241                         clock.n = 6;
4242                         clock.m1 = 12;
4243                         clock.m2 = 8;
4244                 }
4245         }
4246
4247         /* FDI link */
4248         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4249         lane = 0;
4250         /* CPU eDP doesn't require FDI link, so just set DP M/N
4251            according to current link config */
4252         if (is_cpu_edp) {
4253                 target_clock = mode->clock;
4254                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4255         } else {
4256                 /* [e]DP over FDI requires target mode clock
4257                    instead of link clock */
4258                 if (is_dp)
4259                         target_clock = mode->clock;
4260                 else
4261                         target_clock = adjusted_mode->clock;
4262
4263                 /* FDI is a binary signal running at ~2.7GHz, encoding
4264                  * each output octet as 10 bits. The actual frequency
4265                  * is stored as a divider into a 100MHz clock, and the
4266                  * mode pixel clock is stored in units of 1KHz.
4267                  * Hence the bw of each lane in terms of the mode signal
4268                  * is:
4269                  */
4270                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4271         }
4272
4273         /* determine panel color depth */
4274         temp = I915_READ(PIPECONF(pipe));
4275         temp &= ~PIPE_BPC_MASK;
4276         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4277         switch (pipe_bpp) {
4278         case 18:
4279                 temp |= PIPE_6BPC;
4280                 break;
4281         case 24:
4282                 temp |= PIPE_8BPC;
4283                 break;
4284         case 30:
4285                 temp |= PIPE_10BPC;
4286                 break;
4287         case 36:
4288                 temp |= PIPE_12BPC;
4289                 break;
4290         default:
4291                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4292                         pipe_bpp);
4293                 temp |= PIPE_8BPC;
4294                 pipe_bpp = 24;
4295                 break;
4296         }
4297
4298         intel_crtc->bpp = pipe_bpp;
4299         I915_WRITE(PIPECONF(pipe), temp);
4300
4301         if (!lane) {
4302                 /*
4303                  * Account for spread spectrum to avoid
4304                  * oversubscribing the link. Max center spread
4305                  * is 2.5%; use 5% for safety's sake.
4306                  */
4307                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4308                 lane = bps / (link_bw * 8) + 1;
4309         }
4310
4311         intel_crtc->fdi_lanes = lane;
4312
4313         if (pixel_multiplier > 1)
4314                 link_bw *= pixel_multiplier;
4315         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4316                              &m_n);
4317
4318         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4319         if (has_reduced_clock)
4320                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4321                         reduced_clock.m2;
4322
4323         /* Enable autotuning of the PLL clock (if permissible) */
4324         factor = 21;
4325         if (is_lvds) {
4326                 if ((intel_panel_use_ssc(dev_priv) &&
4327                      dev_priv->lvds_ssc_freq == 100) ||
4328                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4329                         factor = 25;
4330         } else if (is_sdvo && is_tv)
4331                 factor = 20;
4332
4333         if (clock.m < factor * clock.n)
4334                 fp |= FP_CB_TUNE;
4335
4336         dpll = 0;
4337
4338         if (is_lvds)
4339                 dpll |= DPLLB_MODE_LVDS;
4340         else
4341                 dpll |= DPLLB_MODE_DAC_SERIAL;
4342         if (is_sdvo) {
4343                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4344                 if (pixel_multiplier > 1) {
4345                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4346                 }
4347                 dpll |= DPLL_DVO_HIGH_SPEED;
4348         }
4349         if (is_dp && !is_cpu_edp)
4350                 dpll |= DPLL_DVO_HIGH_SPEED;
4351
4352         /* compute bitmask from p1 value */
4353         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4354         /* also FPA1 */
4355         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4356
4357         switch (clock.p2) {
4358         case 5:
4359                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4360                 break;
4361         case 7:
4362                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4363                 break;
4364         case 10:
4365                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4366                 break;
4367         case 14:
4368                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4369                 break;
4370         }
4371
4372         if (is_sdvo && is_tv)
4373                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4374         else if (is_tv)
4375                 /* XXX: just matching BIOS for now */
4376                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4377                 dpll |= 3;
4378         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4379                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4380         else
4381                 dpll |= PLL_REF_INPUT_DREFCLK;
4382
4383         /* setup pipeconf */
4384         pipeconf = I915_READ(PIPECONF(pipe));
4385
4386         /* Set up the display plane register */
4387         dspcntr = DISPPLANE_GAMMA_ENABLE;
4388
4389         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4390         drm_mode_debug_printmodeline(mode);
4391
4392         /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
4393         if (!is_cpu_edp) {
4394                 struct intel_pch_pll *pll;
4395
4396                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4397                 if (pll == NULL) {
4398                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4399                                          pipe);
4400                         return -EINVAL;
4401                 }
4402         } else
4403                 intel_put_pch_pll(intel_crtc);
4404
4405         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4406          * This is an exception to the general rule that mode_set doesn't turn
4407          * things on.
4408          */
4409         if (is_lvds) {
4410                 temp = I915_READ(PCH_LVDS);
4411                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4412                 if (HAS_PCH_CPT(dev)) {
4413                         temp &= ~PORT_TRANS_SEL_MASK;
4414                         temp |= PORT_TRANS_SEL_CPT(pipe);
4415                 } else {
4416                         if (pipe == 1)
4417                                 temp |= LVDS_PIPEB_SELECT;
4418                         else
4419                                 temp &= ~LVDS_PIPEB_SELECT;
4420                 }
4421
4422                 /* set the corresponsding LVDS_BORDER bit */
4423                 temp |= dev_priv->lvds_border_bits;
4424                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4425                  * set the DPLLs for dual-channel mode or not.
4426                  */
4427                 if (clock.p2 == 7)
4428                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4429                 else
4430                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4431
4432                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4433                  * appropriately here, but we need to look more thoroughly into how
4434                  * panels behave in the two modes.
4435                  */
4436                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4437                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4438                         temp |= LVDS_HSYNC_POLARITY;
4439                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4440                         temp |= LVDS_VSYNC_POLARITY;
4441                 I915_WRITE(PCH_LVDS, temp);
4442         }
4443
4444         pipeconf &= ~PIPECONF_DITHER_EN;
4445         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4446         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4447                 pipeconf |= PIPECONF_DITHER_EN;
4448                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4449         }
4450         if (is_dp && !is_cpu_edp) {
4451                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4452         } else {
4453                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4454                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4455                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4456                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4457                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4458         }
4459
4460         if (intel_crtc->pch_pll) {
4461                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4462
4463                 /* Wait for the clocks to stabilize. */
4464                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4465                 udelay(150);
4466
4467                 /* The pixel multiplier can only be updated once the
4468                  * DPLL is enabled and the clocks are stable.
4469                  *
4470                  * So write it again.
4471                  */
4472                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4473         }
4474
4475         intel_crtc->lowfreq_avail = false;
4476         if (intel_crtc->pch_pll) {
4477                 if (is_lvds && has_reduced_clock && i915_powersave) {
4478                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4479                         intel_crtc->lowfreq_avail = true;
4480                         if (HAS_PIPE_CXSR(dev)) {
4481                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4482                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4483                         }
4484                 } else {
4485                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4486                         if (HAS_PIPE_CXSR(dev)) {
4487                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4488                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4489                         }
4490                 }
4491         }
4492
4493         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4494         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4495                 pipeconf |= PIPECONF_INTERLACED_ILK;
4496                 /* the chip adds 2 halflines automatically */
4497                 adjusted_mode->crtc_vtotal -= 1;
4498                 adjusted_mode->crtc_vblank_end -= 1;
4499                 I915_WRITE(VSYNCSHIFT(pipe),
4500                            adjusted_mode->crtc_hsync_start
4501                            - adjusted_mode->crtc_htotal/2);
4502         } else {
4503                 pipeconf |= PIPECONF_PROGRESSIVE;
4504                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4505         }
4506
4507         I915_WRITE(HTOTAL(pipe),
4508                    (adjusted_mode->crtc_hdisplay - 1) |
4509                    ((adjusted_mode->crtc_htotal - 1) << 16));
4510         I915_WRITE(HBLANK(pipe),
4511                    (adjusted_mode->crtc_hblank_start - 1) |
4512                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4513         I915_WRITE(HSYNC(pipe),
4514                    (adjusted_mode->crtc_hsync_start - 1) |
4515                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4516
4517         I915_WRITE(VTOTAL(pipe),
4518                    (adjusted_mode->crtc_vdisplay - 1) |
4519                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4520         I915_WRITE(VBLANK(pipe),
4521                    (adjusted_mode->crtc_vblank_start - 1) |
4522                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4523         I915_WRITE(VSYNC(pipe),
4524                    (adjusted_mode->crtc_vsync_start - 1) |
4525                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4526
4527         /* pipesrc controls the size that is scaled from, which should
4528          * always be the user's requested size.
4529          */
4530         I915_WRITE(PIPESRC(pipe),
4531                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4532
4533         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4534         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4535         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4536         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4537
4538         if (is_cpu_edp)
4539                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4540
4541         I915_WRITE(PIPECONF(pipe), pipeconf);
4542         POSTING_READ(PIPECONF(pipe));
4543
4544         intel_wait_for_vblank(dev, pipe);
4545
4546         I915_WRITE(DSPCNTR(plane), dspcntr);
4547         POSTING_READ(DSPCNTR(plane));
4548
4549         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4550
4551         intel_update_watermarks(dev);
4552
4553         return ret;
4554 }
4555
4556 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4557                                struct drm_display_mode *mode,
4558                                struct drm_display_mode *adjusted_mode,
4559                                int x, int y,
4560                                struct drm_framebuffer *old_fb)
4561 {
4562         struct drm_device *dev = crtc->dev;
4563         struct drm_i915_private *dev_priv = dev->dev_private;
4564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4565         int pipe = intel_crtc->pipe;
4566         int ret;
4567
4568         drm_vblank_pre_modeset(dev, pipe);
4569
4570         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4571                                               x, y, old_fb);
4572         drm_vblank_post_modeset(dev, pipe);
4573
4574         if (ret)
4575                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4576         else
4577                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4578
4579         return ret;
4580 }
4581
4582 static bool intel_eld_uptodate(struct drm_connector *connector,
4583                                int reg_eldv, uint32_t bits_eldv,
4584                                int reg_elda, uint32_t bits_elda,
4585                                int reg_edid)
4586 {
4587         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4588         uint8_t *eld = connector->eld;
4589         uint32_t i;
4590
4591         i = I915_READ(reg_eldv);
4592         i &= bits_eldv;
4593
4594         if (!eld[0])
4595                 return !i;
4596
4597         if (!i)
4598                 return false;
4599
4600         i = I915_READ(reg_elda);
4601         i &= ~bits_elda;
4602         I915_WRITE(reg_elda, i);
4603
4604         for (i = 0; i < eld[2]; i++)
4605                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4606                         return false;
4607
4608         return true;
4609 }
4610
4611 static void g4x_write_eld(struct drm_connector *connector,
4612                           struct drm_crtc *crtc)
4613 {
4614         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4615         uint8_t *eld = connector->eld;
4616         uint32_t eldv;
4617         uint32_t len;
4618         uint32_t i;
4619
4620         i = I915_READ(G4X_AUD_VID_DID);
4621
4622         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4623                 eldv = G4X_ELDV_DEVCL_DEVBLC;
4624         else
4625                 eldv = G4X_ELDV_DEVCTG;
4626
4627         if (intel_eld_uptodate(connector,
4628                                G4X_AUD_CNTL_ST, eldv,
4629                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4630                                G4X_HDMIW_HDMIEDID))
4631                 return;
4632
4633         i = I915_READ(G4X_AUD_CNTL_ST);
4634         i &= ~(eldv | G4X_ELD_ADDR);
4635         len = (i >> 9) & 0x1f;          /* ELD buffer size */
4636         I915_WRITE(G4X_AUD_CNTL_ST, i);
4637
4638         if (!eld[0])
4639                 return;
4640
4641         len = min_t(uint8_t, eld[2], len);
4642         DRM_DEBUG_DRIVER("ELD size %d\n", len);
4643         for (i = 0; i < len; i++)
4644                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4645
4646         i = I915_READ(G4X_AUD_CNTL_ST);
4647         i |= eldv;
4648         I915_WRITE(G4X_AUD_CNTL_ST, i);
4649 }
4650
4651 static void ironlake_write_eld(struct drm_connector *connector,
4652                                      struct drm_crtc *crtc)
4653 {
4654         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4655         uint8_t *eld = connector->eld;
4656         uint32_t eldv;
4657         uint32_t i;
4658         int len;
4659         int hdmiw_hdmiedid;
4660         int aud_config;
4661         int aud_cntl_st;
4662         int aud_cntrl_st2;
4663
4664         if (HAS_PCH_IBX(connector->dev)) {
4665                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4666                 aud_config = IBX_AUD_CONFIG_A;
4667                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4668                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4669         } else {
4670                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4671                 aud_config = CPT_AUD_CONFIG_A;
4672                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4673                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4674         }
4675
4676         i = to_intel_crtc(crtc)->pipe;
4677         hdmiw_hdmiedid += i * 0x100;
4678         aud_cntl_st += i * 0x100;
4679         aud_config += i * 0x100;
4680
4681         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4682
4683         i = I915_READ(aud_cntl_st);
4684         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
4685         if (!i) {
4686                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4687                 /* operate blindly on all ports */
4688                 eldv = IBX_ELD_VALIDB;
4689                 eldv |= IBX_ELD_VALIDB << 4;
4690                 eldv |= IBX_ELD_VALIDB << 8;
4691         } else {
4692                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4693                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4694         }
4695
4696         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4697                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4698                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
4699                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4700         } else
4701                 I915_WRITE(aud_config, 0);
4702
4703         if (intel_eld_uptodate(connector,
4704                                aud_cntrl_st2, eldv,
4705                                aud_cntl_st, IBX_ELD_ADDRESS,
4706                                hdmiw_hdmiedid))
4707                 return;
4708
4709         i = I915_READ(aud_cntrl_st2);
4710         i &= ~eldv;
4711         I915_WRITE(aud_cntrl_st2, i);
4712
4713         if (!eld[0])
4714                 return;
4715
4716         i = I915_READ(aud_cntl_st);
4717         i &= ~IBX_ELD_ADDRESS;
4718         I915_WRITE(aud_cntl_st, i);
4719
4720         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
4721         DRM_DEBUG_DRIVER("ELD size %d\n", len);
4722         for (i = 0; i < len; i++)
4723                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4724
4725         i = I915_READ(aud_cntrl_st2);
4726         i |= eldv;
4727         I915_WRITE(aud_cntrl_st2, i);
4728 }
4729
4730 void intel_write_eld(struct drm_encoder *encoder,
4731                      struct drm_display_mode *mode)
4732 {
4733         struct drm_crtc *crtc = encoder->crtc;
4734         struct drm_connector *connector;
4735         struct drm_device *dev = encoder->dev;
4736         struct drm_i915_private *dev_priv = dev->dev_private;
4737
4738         connector = drm_select_eld(encoder, mode);
4739         if (!connector)
4740                 return;
4741
4742         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4743                          connector->base.id,
4744                          drm_get_connector_name(connector),
4745                          connector->encoder->base.id,
4746                          drm_get_encoder_name(connector->encoder));
4747
4748         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4749
4750         if (dev_priv->display.write_eld)
4751                 dev_priv->display.write_eld(connector, crtc);
4752 }
4753
4754 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4755 void intel_crtc_load_lut(struct drm_crtc *crtc)
4756 {
4757         struct drm_device *dev = crtc->dev;
4758         struct drm_i915_private *dev_priv = dev->dev_private;
4759         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4760         int palreg = PALETTE(intel_crtc->pipe);
4761         int i;
4762
4763         /* The clocks have to be on to load the palette. */
4764         if (!crtc->enabled || !intel_crtc->active)
4765                 return;
4766
4767         /* use legacy palette for Ironlake */
4768         if (HAS_PCH_SPLIT(dev))
4769                 palreg = LGC_PALETTE(intel_crtc->pipe);
4770
4771         for (i = 0; i < 256; i++) {
4772                 I915_WRITE(palreg + 4 * i,
4773                            (intel_crtc->lut_r[i] << 16) |
4774                            (intel_crtc->lut_g[i] << 8) |
4775                            intel_crtc->lut_b[i]);
4776         }
4777 }
4778
4779 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4780 {
4781         struct drm_device *dev = crtc->dev;
4782         struct drm_i915_private *dev_priv = dev->dev_private;
4783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4784         bool visible = base != 0;
4785         u32 cntl;
4786
4787         if (intel_crtc->cursor_visible == visible)
4788                 return;
4789
4790         cntl = I915_READ(_CURACNTR);
4791         if (visible) {
4792                 /* On these chipsets we can only modify the base whilst
4793                  * the cursor is disabled.
4794                  */
4795                 I915_WRITE(_CURABASE, base);
4796
4797                 cntl &= ~(CURSOR_FORMAT_MASK);
4798                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4799                 cntl |= CURSOR_ENABLE |
4800                         CURSOR_GAMMA_ENABLE |
4801                         CURSOR_FORMAT_ARGB;
4802         } else
4803                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4804         I915_WRITE(_CURACNTR, cntl);
4805
4806         intel_crtc->cursor_visible = visible;
4807 }
4808
4809 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4810 {
4811         struct drm_device *dev = crtc->dev;
4812         struct drm_i915_private *dev_priv = dev->dev_private;
4813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4814         int pipe = intel_crtc->pipe;
4815         bool visible = base != 0;
4816
4817         if (intel_crtc->cursor_visible != visible) {
4818                 uint32_t cntl = I915_READ(CURCNTR(pipe));
4819                 if (base) {
4820                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4821                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4822                         cntl |= pipe << 28; /* Connect to correct pipe */
4823                 } else {
4824                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4825                         cntl |= CURSOR_MODE_DISABLE;
4826                 }
4827                 I915_WRITE(CURCNTR(pipe), cntl);
4828
4829                 intel_crtc->cursor_visible = visible;
4830         }
4831         /* and commit changes on next vblank */
4832         I915_WRITE(CURBASE(pipe), base);
4833 }
4834
4835 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4836 {
4837         struct drm_device *dev = crtc->dev;
4838         struct drm_i915_private *dev_priv = dev->dev_private;
4839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4840         int pipe = intel_crtc->pipe;
4841         bool visible = base != 0;
4842
4843         if (intel_crtc->cursor_visible != visible) {
4844                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4845                 if (base) {
4846                         cntl &= ~CURSOR_MODE;
4847                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4848                 } else {
4849                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4850                         cntl |= CURSOR_MODE_DISABLE;
4851                 }
4852                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4853
4854                 intel_crtc->cursor_visible = visible;
4855         }
4856         /* and commit changes on next vblank */
4857         I915_WRITE(CURBASE_IVB(pipe), base);
4858 }
4859
4860 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4861 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4862                                      bool on)
4863 {
4864         struct drm_device *dev = crtc->dev;
4865         struct drm_i915_private *dev_priv = dev->dev_private;
4866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4867         int pipe = intel_crtc->pipe;
4868         int x = intel_crtc->cursor_x;
4869         int y = intel_crtc->cursor_y;
4870         u32 base, pos;
4871         bool visible;
4872
4873         pos = 0;
4874
4875         if (on && crtc->enabled && crtc->fb) {
4876                 base = intel_crtc->cursor_addr;
4877                 if (x > (int) crtc->fb->width)
4878                         base = 0;
4879
4880                 if (y > (int) crtc->fb->height)
4881                         base = 0;
4882         } else
4883                 base = 0;
4884
4885         if (x < 0) {
4886                 if (x + intel_crtc->cursor_width < 0)
4887                         base = 0;
4888
4889                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4890                 x = -x;
4891         }
4892         pos |= x << CURSOR_X_SHIFT;
4893
4894         if (y < 0) {
4895                 if (y + intel_crtc->cursor_height < 0)
4896                         base = 0;
4897
4898                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4899                 y = -y;
4900         }
4901         pos |= y << CURSOR_Y_SHIFT;
4902
4903         visible = base != 0;
4904         if (!visible && !intel_crtc->cursor_visible)
4905                 return;
4906
4907         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4908                 I915_WRITE(CURPOS_IVB(pipe), pos);
4909                 ivb_update_cursor(crtc, base);
4910         } else {
4911                 I915_WRITE(CURPOS(pipe), pos);
4912                 if (IS_845G(dev) || IS_I865G(dev))
4913                         i845_update_cursor(crtc, base);
4914                 else
4915                         i9xx_update_cursor(crtc, base);
4916         }
4917 }
4918
4919 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4920                                  struct drm_file *file,
4921                                  uint32_t handle,
4922                                  uint32_t width, uint32_t height)
4923 {
4924         struct drm_device *dev = crtc->dev;
4925         struct drm_i915_private *dev_priv = dev->dev_private;
4926         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4927         struct drm_i915_gem_object *obj;
4928         uint32_t addr;
4929         int ret;
4930
4931         DRM_DEBUG_KMS("\n");
4932
4933         /* if we want to turn off the cursor ignore width and height */
4934         if (!handle) {
4935                 DRM_DEBUG_KMS("cursor off\n");
4936                 addr = 0;
4937                 obj = NULL;
4938                 mutex_lock(&dev->struct_mutex);
4939                 goto finish;
4940         }
4941
4942         /* Currently we only support 64x64 cursors */
4943         if (width != 64 || height != 64) {
4944                 DRM_ERROR("we currently only support 64x64 cursors\n");
4945                 return -EINVAL;
4946         }
4947
4948         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4949         if (&obj->base == NULL)
4950                 return -ENOENT;
4951
4952         if (obj->base.size < width * height * 4) {
4953                 DRM_ERROR("buffer is to small\n");
4954                 ret = -ENOMEM;
4955                 goto fail;
4956         }
4957
4958         /* we only need to pin inside GTT if cursor is non-phy */
4959         mutex_lock(&dev->struct_mutex);
4960         if (!dev_priv->info->cursor_needs_physical) {
4961                 if (obj->tiling_mode) {
4962                         DRM_ERROR("cursor cannot be tiled\n");
4963                         ret = -EINVAL;
4964                         goto fail_locked;
4965                 }
4966
4967                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
4968                 if (ret) {
4969                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4970                         goto fail_locked;
4971                 }
4972
4973                 ret = i915_gem_object_put_fence(obj);
4974                 if (ret) {
4975                         DRM_ERROR("failed to release fence for cursor");
4976                         goto fail_unpin;
4977                 }
4978
4979                 addr = obj->gtt_offset;
4980         } else {
4981                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4982                 ret = i915_gem_attach_phys_object(dev, obj,
4983                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4984                                                   align);
4985                 if (ret) {
4986                         DRM_ERROR("failed to attach phys object\n");
4987                         goto fail_locked;
4988                 }
4989                 addr = obj->phys_obj->handle->busaddr;
4990         }
4991
4992         if (IS_GEN2(dev))
4993                 I915_WRITE(CURSIZE, (height << 12) | width);
4994
4995  finish:
4996         if (intel_crtc->cursor_bo) {
4997                 if (dev_priv->info->cursor_needs_physical) {
4998                         if (intel_crtc->cursor_bo != obj)
4999                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5000                 } else
5001                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5002                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5003         }
5004
5005         mutex_unlock(&dev->struct_mutex);
5006
5007         intel_crtc->cursor_addr = addr;
5008         intel_crtc->cursor_bo = obj;
5009         intel_crtc->cursor_width = width;
5010         intel_crtc->cursor_height = height;
5011
5012         intel_crtc_update_cursor(crtc, true);
5013
5014         return 0;
5015 fail_unpin:
5016         i915_gem_object_unpin(obj);
5017 fail_locked:
5018         mutex_unlock(&dev->struct_mutex);
5019 fail:
5020         drm_gem_object_unreference_unlocked(&obj->base);
5021         return ret;
5022 }
5023
5024 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5025 {
5026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5027
5028         intel_crtc->cursor_x = x;
5029         intel_crtc->cursor_y = y;
5030
5031         intel_crtc_update_cursor(crtc, true);
5032
5033         return 0;
5034 }
5035
5036 /** Sets the color ramps on behalf of RandR */
5037 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5038                                  u16 blue, int regno)
5039 {
5040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5041
5042         intel_crtc->lut_r[regno] = red >> 8;
5043         intel_crtc->lut_g[regno] = green >> 8;
5044         intel_crtc->lut_b[regno] = blue >> 8;
5045 }
5046
5047 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5048                              u16 *blue, int regno)
5049 {
5050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5051
5052         *red = intel_crtc->lut_r[regno] << 8;
5053         *green = intel_crtc->lut_g[regno] << 8;
5054         *blue = intel_crtc->lut_b[regno] << 8;
5055 }
5056
5057 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5058                                  u16 *blue, uint32_t start, uint32_t size)
5059 {
5060         int end = (start + size > 256) ? 256 : start + size, i;
5061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5062
5063         for (i = start; i < end; i++) {
5064                 intel_crtc->lut_r[i] = red[i] >> 8;
5065                 intel_crtc->lut_g[i] = green[i] >> 8;
5066                 intel_crtc->lut_b[i] = blue[i] >> 8;
5067         }
5068
5069         intel_crtc_load_lut(crtc);
5070 }
5071
5072 /**
5073  * Get a pipe with a simple mode set on it for doing load-based monitor
5074  * detection.
5075  *
5076  * It will be up to the load-detect code to adjust the pipe as appropriate for
5077  * its requirements.  The pipe will be connected to no other encoders.
5078  *
5079  * Currently this code will only succeed if there is a pipe with no encoders
5080  * configured for it.  In the future, it could choose to temporarily disable
5081  * some outputs to free up a pipe for its use.
5082  *
5083  * \return crtc, or NULL if no pipes are available.
5084  */
5085
5086 /* VESA 640x480x72Hz mode to set on the pipe */
5087 static struct drm_display_mode load_detect_mode = {
5088         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5089                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5090 };
5091
5092 static struct drm_framebuffer *
5093 intel_framebuffer_create(struct drm_device *dev,
5094                          struct drm_mode_fb_cmd2 *mode_cmd,
5095                          struct drm_i915_gem_object *obj)
5096 {
5097         struct intel_framebuffer *intel_fb;
5098         int ret;
5099
5100         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5101         if (!intel_fb) {
5102                 drm_gem_object_unreference_unlocked(&obj->base);
5103                 return ERR_PTR(-ENOMEM);
5104         }
5105
5106         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5107         if (ret) {
5108                 drm_gem_object_unreference_unlocked(&obj->base);
5109                 kfree(intel_fb);
5110                 return ERR_PTR(ret);
5111         }
5112
5113         return &intel_fb->base;
5114 }
5115
5116 static u32
5117 intel_framebuffer_pitch_for_width(int width, int bpp)
5118 {
5119         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5120         return ALIGN(pitch, 64);
5121 }
5122
5123 static u32
5124 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5125 {
5126         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5127         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5128 }
5129
5130 static struct drm_framebuffer *
5131 intel_framebuffer_create_for_mode(struct drm_device *dev,
5132                                   struct drm_display_mode *mode,
5133                                   int depth, int bpp)
5134 {
5135         struct drm_i915_gem_object *obj;
5136         struct drm_mode_fb_cmd2 mode_cmd;
5137
5138         obj = i915_gem_alloc_object(dev,
5139                                     intel_framebuffer_size_for_mode(mode, bpp));
5140         if (obj == NULL)
5141                 return ERR_PTR(-ENOMEM);
5142
5143         mode_cmd.width = mode->hdisplay;
5144         mode_cmd.height = mode->vdisplay;
5145         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5146                                                                 bpp);
5147         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5148
5149         return intel_framebuffer_create(dev, &mode_cmd, obj);
5150 }
5151
5152 static struct drm_framebuffer *
5153 mode_fits_in_fbdev(struct drm_device *dev,
5154                    struct drm_display_mode *mode)
5155 {
5156         struct drm_i915_private *dev_priv = dev->dev_private;
5157         struct drm_i915_gem_object *obj;
5158         struct drm_framebuffer *fb;
5159
5160         if (dev_priv->fbdev == NULL)
5161                 return NULL;
5162
5163         obj = dev_priv->fbdev->ifb.obj;
5164         if (obj == NULL)
5165                 return NULL;
5166
5167         fb = &dev_priv->fbdev->ifb.base;
5168         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5169                                                                fb->bits_per_pixel))
5170                 return NULL;
5171
5172         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5173                 return NULL;
5174
5175         return fb;
5176 }
5177
5178 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5179                                 struct drm_connector *connector,
5180                                 struct drm_display_mode *mode,
5181                                 struct intel_load_detect_pipe *old)
5182 {
5183         struct intel_crtc *intel_crtc;
5184         struct drm_crtc *possible_crtc;
5185         struct drm_encoder *encoder = &intel_encoder->base;
5186         struct drm_crtc *crtc = NULL;
5187         struct drm_device *dev = encoder->dev;
5188         struct drm_framebuffer *old_fb;
5189         int i = -1;
5190
5191         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5192                       connector->base.id, drm_get_connector_name(connector),
5193                       encoder->base.id, drm_get_encoder_name(encoder));
5194
5195         /*
5196          * Algorithm gets a little messy:
5197          *
5198          *   - if the connector already has an assigned crtc, use it (but make
5199          *     sure it's on first)
5200          *
5201          *   - try to find the first unused crtc that can drive this connector,
5202          *     and use that if we find one
5203          */
5204
5205         /* See if we already have a CRTC for this connector */
5206         if (encoder->crtc) {
5207                 crtc = encoder->crtc;
5208
5209                 intel_crtc = to_intel_crtc(crtc);
5210                 old->dpms_mode = intel_crtc->dpms_mode;
5211                 old->load_detect_temp = false;
5212
5213                 /* Make sure the crtc and connector are running */
5214                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5215                         struct drm_encoder_helper_funcs *encoder_funcs;
5216                         struct drm_crtc_helper_funcs *crtc_funcs;
5217
5218                         crtc_funcs = crtc->helper_private;
5219                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5220
5221                         encoder_funcs = encoder->helper_private;
5222                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5223                 }
5224
5225                 return true;
5226         }
5227
5228         /* Find an unused one (if possible) */
5229         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5230                 i++;
5231                 if (!(encoder->possible_crtcs & (1 << i)))
5232                         continue;
5233                 if (!possible_crtc->enabled) {
5234                         crtc = possible_crtc;
5235                         break;
5236                 }
5237         }
5238
5239         /*
5240          * If we didn't find an unused CRTC, don't use any.
5241          */
5242         if (!crtc) {
5243                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5244                 return false;
5245         }
5246
5247         encoder->crtc = crtc;
5248         connector->encoder = encoder;
5249
5250         intel_crtc = to_intel_crtc(crtc);
5251         old->dpms_mode = intel_crtc->dpms_mode;
5252         old->load_detect_temp = true;
5253         old->release_fb = NULL;
5254
5255         if (!mode)
5256                 mode = &load_detect_mode;
5257
5258         old_fb = crtc->fb;
5259
5260         /* We need a framebuffer large enough to accommodate all accesses
5261          * that the plane may generate whilst we perform load detection.
5262          * We can not rely on the fbcon either being present (we get called
5263          * during its initialisation to detect all boot displays, or it may
5264          * not even exist) or that it is large enough to satisfy the
5265          * requested mode.
5266          */
5267         crtc->fb = mode_fits_in_fbdev(dev, mode);
5268         if (crtc->fb == NULL) {
5269                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5270                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5271                 old->release_fb = crtc->fb;
5272         } else
5273                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5274         if (IS_ERR(crtc->fb)) {
5275                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5276                 crtc->fb = old_fb;
5277                 return false;
5278         }
5279
5280         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5281                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5282                 if (old->release_fb)
5283                         old->release_fb->funcs->destroy(old->release_fb);
5284                 crtc->fb = old_fb;
5285                 return false;
5286         }
5287
5288         /* let the connector get through one full cycle before testing */
5289         intel_wait_for_vblank(dev, intel_crtc->pipe);
5290
5291         return true;
5292 }
5293
5294 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5295                                     struct drm_connector *connector,
5296                                     struct intel_load_detect_pipe *old)
5297 {
5298         struct drm_encoder *encoder = &intel_encoder->base;
5299         struct drm_device *dev = encoder->dev;
5300         struct drm_crtc *crtc = encoder->crtc;
5301         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5302         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5303
5304         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5305                       connector->base.id, drm_get_connector_name(connector),
5306                       encoder->base.id, drm_get_encoder_name(encoder));
5307
5308         if (old->load_detect_temp) {
5309                 connector->encoder = NULL;
5310                 drm_helper_disable_unused_functions(dev);
5311
5312                 if (old->release_fb)
5313                         old->release_fb->funcs->destroy(old->release_fb);
5314
5315                 return;
5316         }
5317
5318         /* Switch crtc and encoder back off if necessary */
5319         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5320                 encoder_funcs->dpms(encoder, old->dpms_mode);
5321                 crtc_funcs->dpms(crtc, old->dpms_mode);
5322         }
5323 }
5324
5325 /* Returns the clock of the currently programmed mode of the given pipe. */
5326 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5327 {
5328         struct drm_i915_private *dev_priv = dev->dev_private;
5329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5330         int pipe = intel_crtc->pipe;
5331         u32 dpll = I915_READ(DPLL(pipe));
5332         u32 fp;
5333         intel_clock_t clock;
5334
5335         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5336                 fp = I915_READ(FP0(pipe));
5337         else
5338                 fp = I915_READ(FP1(pipe));
5339
5340         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5341         if (IS_PINEVIEW(dev)) {
5342                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5343                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5344         } else {
5345                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5346                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5347         }
5348
5349         if (!IS_GEN2(dev)) {
5350                 if (IS_PINEVIEW(dev))
5351                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5352                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5353                 else
5354                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5355                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5356
5357                 switch (dpll & DPLL_MODE_MASK) {
5358                 case DPLLB_MODE_DAC_SERIAL:
5359                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5360                                 5 : 10;
5361                         break;
5362                 case DPLLB_MODE_LVDS:
5363                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5364                                 7 : 14;
5365                         break;
5366                 default:
5367                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5368                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5369                         return 0;
5370                 }
5371
5372                 /* XXX: Handle the 100Mhz refclk */
5373                 intel_clock(dev, 96000, &clock);
5374         } else {
5375                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5376
5377                 if (is_lvds) {
5378                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5379                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5380                         clock.p2 = 14;
5381
5382                         if ((dpll & PLL_REF_INPUT_MASK) ==
5383                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5384                                 /* XXX: might not be 66MHz */
5385                                 intel_clock(dev, 66000, &clock);
5386                         } else
5387                                 intel_clock(dev, 48000, &clock);
5388                 } else {
5389                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5390                                 clock.p1 = 2;
5391                         else {
5392                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5393                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5394                         }
5395                         if (dpll & PLL_P2_DIVIDE_BY_4)
5396                                 clock.p2 = 4;
5397                         else
5398                                 clock.p2 = 2;
5399
5400                         intel_clock(dev, 48000, &clock);
5401                 }
5402         }
5403
5404         /* XXX: It would be nice to validate the clocks, but we can't reuse
5405          * i830PllIsValid() because it relies on the xf86_config connector
5406          * configuration being accurate, which it isn't necessarily.
5407          */
5408
5409         return clock.dot;
5410 }
5411
5412 /** Returns the currently programmed mode of the given pipe. */
5413 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5414                                              struct drm_crtc *crtc)
5415 {
5416         struct drm_i915_private *dev_priv = dev->dev_private;
5417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5418         int pipe = intel_crtc->pipe;
5419         struct drm_display_mode *mode;
5420         int htot = I915_READ(HTOTAL(pipe));
5421         int hsync = I915_READ(HSYNC(pipe));
5422         int vtot = I915_READ(VTOTAL(pipe));
5423         int vsync = I915_READ(VSYNC(pipe));
5424
5425         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5426         if (!mode)
5427                 return NULL;
5428
5429         mode->clock = intel_crtc_clock_get(dev, crtc);
5430         mode->hdisplay = (htot & 0xffff) + 1;
5431         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5432         mode->hsync_start = (hsync & 0xffff) + 1;
5433         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5434         mode->vdisplay = (vtot & 0xffff) + 1;
5435         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5436         mode->vsync_start = (vsync & 0xffff) + 1;
5437         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5438
5439         drm_mode_set_name(mode);
5440
5441         return mode;
5442 }
5443
5444 #define GPU_IDLE_TIMEOUT 500 /* ms */
5445
5446 /* When this timer fires, we've been idle for awhile */
5447 static void intel_gpu_idle_timer(unsigned long arg)
5448 {
5449         struct drm_device *dev = (struct drm_device *)arg;
5450         drm_i915_private_t *dev_priv = dev->dev_private;
5451
5452         if (!list_empty(&dev_priv->mm.active_list)) {
5453                 /* Still processing requests, so just re-arm the timer. */
5454                 mod_timer(&dev_priv->idle_timer, jiffies +
5455                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5456                 return;
5457         }
5458
5459         dev_priv->busy = false;
5460         queue_work(dev_priv->wq, &dev_priv->idle_work);
5461 }
5462
5463 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5464
5465 static void intel_crtc_idle_timer(unsigned long arg)
5466 {
5467         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5468         struct drm_crtc *crtc = &intel_crtc->base;
5469         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5470         struct intel_framebuffer *intel_fb;
5471
5472         intel_fb = to_intel_framebuffer(crtc->fb);
5473         if (intel_fb && intel_fb->obj->active) {
5474                 /* The framebuffer is still being accessed by the GPU. */
5475                 mod_timer(&intel_crtc->idle_timer, jiffies +
5476                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5477                 return;
5478         }
5479
5480         intel_crtc->busy = false;
5481         queue_work(dev_priv->wq, &dev_priv->idle_work);
5482 }
5483
5484 static void intel_increase_pllclock(struct drm_crtc *crtc)
5485 {
5486         struct drm_device *dev = crtc->dev;
5487         drm_i915_private_t *dev_priv = dev->dev_private;
5488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5489         int pipe = intel_crtc->pipe;
5490         int dpll_reg = DPLL(pipe);
5491         int dpll;
5492
5493         if (HAS_PCH_SPLIT(dev))
5494                 return;
5495
5496         if (!dev_priv->lvds_downclock_avail)
5497                 return;
5498
5499         dpll = I915_READ(dpll_reg);
5500         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5501                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5502
5503                 assert_panel_unlocked(dev_priv, pipe);
5504
5505                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5506                 I915_WRITE(dpll_reg, dpll);
5507                 intel_wait_for_vblank(dev, pipe);
5508
5509                 dpll = I915_READ(dpll_reg);
5510                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5511                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5512         }
5513
5514         /* Schedule downclock */
5515         mod_timer(&intel_crtc->idle_timer, jiffies +
5516                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5517 }
5518
5519 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5520 {
5521         struct drm_device *dev = crtc->dev;
5522         drm_i915_private_t *dev_priv = dev->dev_private;
5523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5524
5525         if (HAS_PCH_SPLIT(dev))
5526                 return;
5527
5528         if (!dev_priv->lvds_downclock_avail)
5529                 return;
5530
5531         /*
5532          * Since this is called by a timer, we should never get here in
5533          * the manual case.
5534          */
5535         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5536                 int pipe = intel_crtc->pipe;
5537                 int dpll_reg = DPLL(pipe);
5538                 int dpll;
5539
5540                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5541
5542                 assert_panel_unlocked(dev_priv, pipe);
5543
5544                 dpll = I915_READ(dpll_reg);
5545                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5546                 I915_WRITE(dpll_reg, dpll);
5547                 intel_wait_for_vblank(dev, pipe);
5548                 dpll = I915_READ(dpll_reg);
5549                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5550                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5551         }
5552
5553 }
5554
5555 /**
5556  * intel_idle_update - adjust clocks for idleness
5557  * @work: work struct
5558  *
5559  * Either the GPU or display (or both) went idle.  Check the busy status
5560  * here and adjust the CRTC and GPU clocks as necessary.
5561  */
5562 static void intel_idle_update(struct work_struct *work)
5563 {
5564         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5565                                                     idle_work);
5566         struct drm_device *dev = dev_priv->dev;
5567         struct drm_crtc *crtc;
5568         struct intel_crtc *intel_crtc;
5569
5570         if (!i915_powersave)
5571                 return;
5572
5573         mutex_lock(&dev->struct_mutex);
5574
5575         i915_update_gfx_val(dev_priv);
5576
5577         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5578                 /* Skip inactive CRTCs */
5579                 if (!crtc->fb)
5580                         continue;
5581
5582                 intel_crtc = to_intel_crtc(crtc);
5583                 if (!intel_crtc->busy)
5584                         intel_decrease_pllclock(crtc);
5585         }
5586
5587
5588         mutex_unlock(&dev->struct_mutex);
5589 }
5590
5591 /**
5592  * intel_mark_busy - mark the GPU and possibly the display busy
5593  * @dev: drm device
5594  * @obj: object we're operating on
5595  *
5596  * Callers can use this function to indicate that the GPU is busy processing
5597  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5598  * buffer), we'll also mark the display as busy, so we know to increase its
5599  * clock frequency.
5600  */
5601 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5602 {
5603         drm_i915_private_t *dev_priv = dev->dev_private;
5604         struct drm_crtc *crtc = NULL;
5605         struct intel_framebuffer *intel_fb;
5606         struct intel_crtc *intel_crtc;
5607
5608         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5609                 return;
5610
5611         if (!dev_priv->busy) {
5612                 intel_sanitize_pm(dev);
5613                 dev_priv->busy = true;
5614         } else
5615                 mod_timer(&dev_priv->idle_timer, jiffies +
5616                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5617
5618         if (obj == NULL)
5619                 return;
5620
5621         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5622                 if (!crtc->fb)
5623                         continue;
5624
5625                 intel_crtc = to_intel_crtc(crtc);
5626                 intel_fb = to_intel_framebuffer(crtc->fb);
5627                 if (intel_fb->obj == obj) {
5628                         if (!intel_crtc->busy) {
5629                                 /* Non-busy -> busy, upclock */
5630                                 intel_increase_pllclock(crtc);
5631                                 intel_crtc->busy = true;
5632                         } else {
5633                                 /* Busy -> busy, put off timer */
5634                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5635                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5636                         }
5637                 }
5638         }
5639 }
5640
5641 static void intel_crtc_destroy(struct drm_crtc *crtc)
5642 {
5643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5644         struct drm_device *dev = crtc->dev;
5645         struct intel_unpin_work *work;
5646         unsigned long flags;
5647
5648         spin_lock_irqsave(&dev->event_lock, flags);
5649         work = intel_crtc->unpin_work;
5650         intel_crtc->unpin_work = NULL;
5651         spin_unlock_irqrestore(&dev->event_lock, flags);
5652
5653         if (work) {
5654                 cancel_work_sync(&work->work);
5655                 kfree(work);
5656         }
5657
5658         drm_crtc_cleanup(crtc);
5659
5660         kfree(intel_crtc);
5661 }
5662
5663 static void intel_unpin_work_fn(struct work_struct *__work)
5664 {
5665         struct intel_unpin_work *work =
5666                 container_of(__work, struct intel_unpin_work, work);
5667
5668         mutex_lock(&work->dev->struct_mutex);
5669         intel_unpin_fb_obj(work->old_fb_obj);
5670         drm_gem_object_unreference(&work->pending_flip_obj->base);
5671         drm_gem_object_unreference(&work->old_fb_obj->base);
5672
5673         intel_update_fbc(work->dev);
5674         mutex_unlock(&work->dev->struct_mutex);
5675         kfree(work);
5676 }
5677
5678 static void do_intel_finish_page_flip(struct drm_device *dev,
5679                                       struct drm_crtc *crtc)
5680 {
5681         drm_i915_private_t *dev_priv = dev->dev_private;
5682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5683         struct intel_unpin_work *work;
5684         struct drm_i915_gem_object *obj;
5685         struct drm_pending_vblank_event *e;
5686         struct timeval tnow, tvbl;
5687         unsigned long flags;
5688
5689         /* Ignore early vblank irqs */
5690         if (intel_crtc == NULL)
5691                 return;
5692
5693         do_gettimeofday(&tnow);
5694
5695         spin_lock_irqsave(&dev->event_lock, flags);
5696         work = intel_crtc->unpin_work;
5697         if (work == NULL || !work->pending) {
5698                 spin_unlock_irqrestore(&dev->event_lock, flags);
5699                 return;
5700         }
5701
5702         intel_crtc->unpin_work = NULL;
5703
5704         if (work->event) {
5705                 e = work->event;
5706                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5707
5708                 /* Called before vblank count and timestamps have
5709                  * been updated for the vblank interval of flip
5710                  * completion? Need to increment vblank count and
5711                  * add one videorefresh duration to returned timestamp
5712                  * to account for this. We assume this happened if we
5713                  * get called over 0.9 frame durations after the last
5714                  * timestamped vblank.
5715                  *
5716                  * This calculation can not be used with vrefresh rates
5717                  * below 5Hz (10Hz to be on the safe side) without
5718                  * promoting to 64 integers.
5719                  */
5720                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5721                     9 * crtc->framedur_ns) {
5722                         e->event.sequence++;
5723                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5724                                              crtc->framedur_ns);
5725                 }
5726
5727                 e->event.tv_sec = tvbl.tv_sec;
5728                 e->event.tv_usec = tvbl.tv_usec;
5729
5730                 list_add_tail(&e->base.link,
5731                               &e->base.file_priv->event_list);
5732                 wake_up_interruptible(&e->base.file_priv->event_wait);
5733         }
5734
5735         drm_vblank_put(dev, intel_crtc->pipe);
5736
5737         spin_unlock_irqrestore(&dev->event_lock, flags);
5738
5739         obj = work->old_fb_obj;
5740
5741         atomic_clear_mask(1 << intel_crtc->plane,
5742                           &obj->pending_flip.counter);
5743         if (atomic_read(&obj->pending_flip) == 0)
5744                 wake_up(&dev_priv->pending_flip_queue);
5745
5746         schedule_work(&work->work);
5747
5748         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5749 }
5750
5751 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5752 {
5753         drm_i915_private_t *dev_priv = dev->dev_private;
5754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5755
5756         do_intel_finish_page_flip(dev, crtc);
5757 }
5758
5759 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5760 {
5761         drm_i915_private_t *dev_priv = dev->dev_private;
5762         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5763
5764         do_intel_finish_page_flip(dev, crtc);
5765 }
5766
5767 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5768 {
5769         drm_i915_private_t *dev_priv = dev->dev_private;
5770         struct intel_crtc *intel_crtc =
5771                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5772         unsigned long flags;
5773
5774         spin_lock_irqsave(&dev->event_lock, flags);
5775         if (intel_crtc->unpin_work) {
5776                 if ((++intel_crtc->unpin_work->pending) > 1)
5777                         DRM_ERROR("Prepared flip multiple times\n");
5778         } else {
5779                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5780         }
5781         spin_unlock_irqrestore(&dev->event_lock, flags);
5782 }
5783
5784 static int intel_gen2_queue_flip(struct drm_device *dev,
5785                                  struct drm_crtc *crtc,
5786                                  struct drm_framebuffer *fb,
5787                                  struct drm_i915_gem_object *obj)
5788 {
5789         struct drm_i915_private *dev_priv = dev->dev_private;
5790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5791         unsigned long offset;
5792         u32 flip_mask;
5793         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5794         int ret;
5795
5796         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5797         if (ret)
5798                 goto err;
5799
5800         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5801         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5802
5803         ret = intel_ring_begin(ring, 6);
5804         if (ret)
5805                 goto err_unpin;
5806
5807         /* Can't queue multiple flips, so wait for the previous
5808          * one to finish before executing the next.
5809          */
5810         if (intel_crtc->plane)
5811                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5812         else
5813                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5814         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5815         intel_ring_emit(ring, MI_NOOP);
5816         intel_ring_emit(ring, MI_DISPLAY_FLIP |
5817                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5818         intel_ring_emit(ring, fb->pitches[0]);
5819         intel_ring_emit(ring, obj->gtt_offset + offset);
5820         intel_ring_emit(ring, 0); /* aux display base address, unused */
5821         intel_ring_advance(ring);
5822         return 0;
5823
5824 err_unpin:
5825         intel_unpin_fb_obj(obj);
5826 err:
5827         return ret;
5828 }
5829
5830 static int intel_gen3_queue_flip(struct drm_device *dev,
5831                                  struct drm_crtc *crtc,
5832                                  struct drm_framebuffer *fb,
5833                                  struct drm_i915_gem_object *obj)
5834 {
5835         struct drm_i915_private *dev_priv = dev->dev_private;
5836         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5837         unsigned long offset;
5838         u32 flip_mask;
5839         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5840         int ret;
5841
5842         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5843         if (ret)
5844                 goto err;
5845
5846         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5847         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5848
5849         ret = intel_ring_begin(ring, 6);
5850         if (ret)
5851                 goto err_unpin;
5852
5853         if (intel_crtc->plane)
5854                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5855         else
5856                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5857         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5858         intel_ring_emit(ring, MI_NOOP);
5859         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
5860                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5861         intel_ring_emit(ring, fb->pitches[0]);
5862         intel_ring_emit(ring, obj->gtt_offset + offset);
5863         intel_ring_emit(ring, MI_NOOP);
5864
5865         intel_ring_advance(ring);
5866         return 0;
5867
5868 err_unpin:
5869         intel_unpin_fb_obj(obj);
5870 err:
5871         return ret;
5872 }
5873
5874 static int intel_gen4_queue_flip(struct drm_device *dev,
5875                                  struct drm_crtc *crtc,
5876                                  struct drm_framebuffer *fb,
5877                                  struct drm_i915_gem_object *obj)
5878 {
5879         struct drm_i915_private *dev_priv = dev->dev_private;
5880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5881         uint32_t pf, pipesrc;
5882         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5883         int ret;
5884
5885         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5886         if (ret)
5887                 goto err;
5888
5889         ret = intel_ring_begin(ring, 4);
5890         if (ret)
5891                 goto err_unpin;
5892
5893         /* i965+ uses the linear or tiled offsets from the
5894          * Display Registers (which do not change across a page-flip)
5895          * so we need only reprogram the base address.
5896          */
5897         intel_ring_emit(ring, MI_DISPLAY_FLIP |
5898                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5899         intel_ring_emit(ring, fb->pitches[0]);
5900         intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
5901
5902         /* XXX Enabling the panel-fitter across page-flip is so far
5903          * untested on non-native modes, so ignore it for now.
5904          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5905          */
5906         pf = 0;
5907         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5908         intel_ring_emit(ring, pf | pipesrc);
5909         intel_ring_advance(ring);
5910         return 0;
5911
5912 err_unpin:
5913         intel_unpin_fb_obj(obj);
5914 err:
5915         return ret;
5916 }
5917
5918 static int intel_gen6_queue_flip(struct drm_device *dev,
5919                                  struct drm_crtc *crtc,
5920                                  struct drm_framebuffer *fb,
5921                                  struct drm_i915_gem_object *obj)
5922 {
5923         struct drm_i915_private *dev_priv = dev->dev_private;
5924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5925         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5926         uint32_t pf, pipesrc;
5927         int ret;
5928
5929         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5930         if (ret)
5931                 goto err;
5932
5933         ret = intel_ring_begin(ring, 4);
5934         if (ret)
5935                 goto err_unpin;
5936
5937         intel_ring_emit(ring, MI_DISPLAY_FLIP |
5938                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5939         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
5940         intel_ring_emit(ring, obj->gtt_offset);
5941
5942         /* Contrary to the suggestions in the documentation,
5943          * "Enable Panel Fitter" does not seem to be required when page
5944          * flipping with a non-native mode, and worse causes a normal
5945          * modeset to fail.
5946          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5947          */
5948         pf = 0;
5949         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5950         intel_ring_emit(ring, pf | pipesrc);
5951         intel_ring_advance(ring);
5952         return 0;
5953
5954 err_unpin:
5955         intel_unpin_fb_obj(obj);
5956 err:
5957         return ret;
5958 }
5959
5960 /*
5961  * On gen7 we currently use the blit ring because (in early silicon at least)
5962  * the render ring doesn't give us interrpts for page flip completion, which
5963  * means clients will hang after the first flip is queued.  Fortunately the
5964  * blit ring generates interrupts properly, so use it instead.
5965  */
5966 static int intel_gen7_queue_flip(struct drm_device *dev,
5967                                  struct drm_crtc *crtc,
5968                                  struct drm_framebuffer *fb,
5969                                  struct drm_i915_gem_object *obj)
5970 {
5971         struct drm_i915_private *dev_priv = dev->dev_private;
5972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5973         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5974         int ret;
5975
5976         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5977         if (ret)
5978                 goto err;
5979
5980         ret = intel_ring_begin(ring, 4);
5981         if (ret)
5982                 goto err_unpin;
5983
5984         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
5985         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
5986         intel_ring_emit(ring, (obj->gtt_offset));
5987         intel_ring_emit(ring, (MI_NOOP));
5988         intel_ring_advance(ring);
5989         return 0;
5990
5991 err_unpin:
5992         intel_unpin_fb_obj(obj);
5993 err:
5994         return ret;
5995 }
5996
5997 static int intel_default_queue_flip(struct drm_device *dev,
5998                                     struct drm_crtc *crtc,
5999                                     struct drm_framebuffer *fb,
6000                                     struct drm_i915_gem_object *obj)
6001 {
6002         return -ENODEV;
6003 }
6004
6005 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6006                                 struct drm_framebuffer *fb,
6007                                 struct drm_pending_vblank_event *event)
6008 {
6009         struct drm_device *dev = crtc->dev;
6010         struct drm_i915_private *dev_priv = dev->dev_private;
6011         struct intel_framebuffer *intel_fb;
6012         struct drm_i915_gem_object *obj;
6013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6014         struct intel_unpin_work *work;
6015         unsigned long flags;
6016         int ret;
6017
6018         work = kzalloc(sizeof *work, GFP_KERNEL);
6019         if (work == NULL)
6020                 return -ENOMEM;
6021
6022         work->event = event;
6023         work->dev = crtc->dev;
6024         intel_fb = to_intel_framebuffer(crtc->fb);
6025         work->old_fb_obj = intel_fb->obj;
6026         INIT_WORK(&work->work, intel_unpin_work_fn);
6027
6028         ret = drm_vblank_get(dev, intel_crtc->pipe);
6029         if (ret)
6030                 goto free_work;
6031
6032         /* We borrow the event spin lock for protecting unpin_work */
6033         spin_lock_irqsave(&dev->event_lock, flags);
6034         if (intel_crtc->unpin_work) {
6035                 spin_unlock_irqrestore(&dev->event_lock, flags);
6036                 kfree(work);
6037                 drm_vblank_put(dev, intel_crtc->pipe);
6038
6039                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6040                 return -EBUSY;
6041         }
6042         intel_crtc->unpin_work = work;
6043         spin_unlock_irqrestore(&dev->event_lock, flags);
6044
6045         intel_fb = to_intel_framebuffer(fb);
6046         obj = intel_fb->obj;
6047
6048         mutex_lock(&dev->struct_mutex);
6049
6050         /* Reference the objects for the scheduled work. */
6051         drm_gem_object_reference(&work->old_fb_obj->base);
6052         drm_gem_object_reference(&obj->base);
6053
6054         crtc->fb = fb;
6055
6056         work->pending_flip_obj = obj;
6057
6058         work->enable_stall_check = true;
6059
6060         /* Block clients from rendering to the new back buffer until
6061          * the flip occurs and the object is no longer visible.
6062          */
6063         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6064
6065         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6066         if (ret)
6067                 goto cleanup_pending;
6068
6069         intel_disable_fbc(dev);
6070         intel_mark_busy(dev, obj);
6071         mutex_unlock(&dev->struct_mutex);
6072
6073         trace_i915_flip_request(intel_crtc->plane, obj);
6074
6075         return 0;
6076
6077 cleanup_pending:
6078         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6079         drm_gem_object_unreference(&work->old_fb_obj->base);
6080         drm_gem_object_unreference(&obj->base);
6081         mutex_unlock(&dev->struct_mutex);
6082
6083         spin_lock_irqsave(&dev->event_lock, flags);
6084         intel_crtc->unpin_work = NULL;
6085         spin_unlock_irqrestore(&dev->event_lock, flags);
6086
6087         drm_vblank_put(dev, intel_crtc->pipe);
6088 free_work:
6089         kfree(work);
6090
6091         return ret;
6092 }
6093
6094 static void intel_sanitize_modesetting(struct drm_device *dev,
6095                                        int pipe, int plane)
6096 {
6097         struct drm_i915_private *dev_priv = dev->dev_private;
6098         u32 reg, val;
6099
6100         /* Clear any frame start delays used for debugging left by the BIOS */
6101         for_each_pipe(pipe) {
6102                 reg = PIPECONF(pipe);
6103                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6104         }
6105
6106         if (HAS_PCH_SPLIT(dev))
6107                 return;
6108
6109         /* Who knows what state these registers were left in by the BIOS or
6110          * grub?
6111          *
6112          * If we leave the registers in a conflicting state (e.g. with the
6113          * display plane reading from the other pipe than the one we intend
6114          * to use) then when we attempt to teardown the active mode, we will
6115          * not disable the pipes and planes in the correct order -- leaving
6116          * a plane reading from a disabled pipe and possibly leading to
6117          * undefined behaviour.
6118          */
6119
6120         reg = DSPCNTR(plane);
6121         val = I915_READ(reg);
6122
6123         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6124                 return;
6125         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6126                 return;
6127
6128         /* This display plane is active and attached to the other CPU pipe. */
6129         pipe = !pipe;
6130
6131         /* Disable the plane and wait for it to stop reading from the pipe. */
6132         intel_disable_plane(dev_priv, plane, pipe);
6133         intel_disable_pipe(dev_priv, pipe);
6134 }
6135
6136 static void intel_crtc_reset(struct drm_crtc *crtc)
6137 {
6138         struct drm_device *dev = crtc->dev;
6139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6140
6141         /* Reset flags back to the 'unknown' status so that they
6142          * will be correctly set on the initial modeset.
6143          */
6144         intel_crtc->dpms_mode = -1;
6145
6146         /* We need to fix up any BIOS configuration that conflicts with
6147          * our expectations.
6148          */
6149         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6150 }
6151
6152 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6153         .dpms = intel_crtc_dpms,
6154         .mode_fixup = intel_crtc_mode_fixup,
6155         .mode_set = intel_crtc_mode_set,
6156         .mode_set_base = intel_pipe_set_base,
6157         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6158         .load_lut = intel_crtc_load_lut,
6159         .disable = intel_crtc_disable,
6160 };
6161
6162 static const struct drm_crtc_funcs intel_crtc_funcs = {
6163         .reset = intel_crtc_reset,
6164         .cursor_set = intel_crtc_cursor_set,
6165         .cursor_move = intel_crtc_cursor_move,
6166         .gamma_set = intel_crtc_gamma_set,
6167         .set_config = drm_crtc_helper_set_config,
6168         .destroy = intel_crtc_destroy,
6169         .page_flip = intel_crtc_page_flip,
6170 };
6171
6172 static void intel_pch_pll_init(struct drm_device *dev)
6173 {
6174         drm_i915_private_t *dev_priv = dev->dev_private;
6175         int i;
6176
6177         if (dev_priv->num_pch_pll == 0) {
6178                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6179                 return;
6180         }
6181
6182         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6183                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6184                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6185                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6186         }
6187 }
6188
6189 static void intel_crtc_init(struct drm_device *dev, int pipe)
6190 {
6191         drm_i915_private_t *dev_priv = dev->dev_private;
6192         struct intel_crtc *intel_crtc;
6193         int i;
6194
6195         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6196         if (intel_crtc == NULL)
6197                 return;
6198
6199         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6200
6201         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6202         for (i = 0; i < 256; i++) {
6203                 intel_crtc->lut_r[i] = i;
6204                 intel_crtc->lut_g[i] = i;
6205                 intel_crtc->lut_b[i] = i;
6206         }
6207
6208         /* Swap pipes & planes for FBC on pre-965 */
6209         intel_crtc->pipe = pipe;
6210         intel_crtc->plane = pipe;
6211         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6212                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6213                 intel_crtc->plane = !pipe;
6214         }
6215
6216         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6217                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6218         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6219         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6220
6221         intel_crtc_reset(&intel_crtc->base);
6222         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6223         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6224
6225         if (HAS_PCH_SPLIT(dev)) {
6226                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6227                 intel_helper_funcs.commit = ironlake_crtc_commit;
6228         } else {
6229                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6230                 intel_helper_funcs.commit = i9xx_crtc_commit;
6231         }
6232
6233         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6234
6235         intel_crtc->busy = false;
6236
6237         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6238                     (unsigned long)intel_crtc);
6239 }
6240
6241 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6242                                 struct drm_file *file)
6243 {
6244         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6245         struct drm_mode_object *drmmode_obj;
6246         struct intel_crtc *crtc;
6247
6248         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6249                 return -ENODEV;
6250
6251         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6252                         DRM_MODE_OBJECT_CRTC);
6253
6254         if (!drmmode_obj) {
6255                 DRM_ERROR("no such CRTC id\n");
6256                 return -EINVAL;
6257         }
6258
6259         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6260         pipe_from_crtc_id->pipe = crtc->pipe;
6261
6262         return 0;
6263 }
6264
6265 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6266 {
6267         struct intel_encoder *encoder;
6268         int index_mask = 0;
6269         int entry = 0;
6270
6271         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6272                 if (type_mask & encoder->clone_mask)
6273                         index_mask |= (1 << entry);
6274                 entry++;
6275         }
6276
6277         return index_mask;
6278 }
6279
6280 static bool has_edp_a(struct drm_device *dev)
6281 {
6282         struct drm_i915_private *dev_priv = dev->dev_private;
6283
6284         if (!IS_MOBILE(dev))
6285                 return false;
6286
6287         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6288                 return false;
6289
6290         if (IS_GEN5(dev) &&
6291             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6292                 return false;
6293
6294         return true;
6295 }
6296
6297 static void intel_setup_outputs(struct drm_device *dev)
6298 {
6299         struct drm_i915_private *dev_priv = dev->dev_private;
6300         struct intel_encoder *encoder;
6301         bool dpd_is_edp = false;
6302         bool has_lvds;
6303
6304         has_lvds = intel_lvds_init(dev);
6305         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6306                 /* disable the panel fitter on everything but LVDS */
6307                 I915_WRITE(PFIT_CONTROL, 0);
6308         }
6309
6310         if (HAS_PCH_SPLIT(dev)) {
6311                 dpd_is_edp = intel_dpd_is_edp(dev);
6312
6313                 if (has_edp_a(dev))
6314                         intel_dp_init(dev, DP_A);
6315
6316                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6317                         intel_dp_init(dev, PCH_DP_D);
6318         }
6319
6320         intel_crt_init(dev);
6321
6322         if (HAS_PCH_SPLIT(dev)) {
6323                 int found;
6324
6325                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6326                         /* PCH SDVOB multiplex with HDMIB */
6327                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
6328                         if (!found)
6329                                 intel_hdmi_init(dev, HDMIB);
6330                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6331                                 intel_dp_init(dev, PCH_DP_B);
6332                 }
6333
6334                 if (I915_READ(HDMIC) & PORT_DETECTED)
6335                         intel_hdmi_init(dev, HDMIC);
6336
6337                 if (I915_READ(HDMID) & PORT_DETECTED)
6338                         intel_hdmi_init(dev, HDMID);
6339
6340                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6341                         intel_dp_init(dev, PCH_DP_C);
6342
6343                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6344                         intel_dp_init(dev, PCH_DP_D);
6345
6346         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6347                 bool found = false;
6348
6349                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6350                         DRM_DEBUG_KMS("probing SDVOB\n");
6351                         found = intel_sdvo_init(dev, SDVOB, true);
6352                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6353                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6354                                 intel_hdmi_init(dev, SDVOB);
6355                         }
6356
6357                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6358                                 DRM_DEBUG_KMS("probing DP_B\n");
6359                                 intel_dp_init(dev, DP_B);
6360                         }
6361                 }
6362
6363                 /* Before G4X SDVOC doesn't have its own detect register */
6364
6365                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6366                         DRM_DEBUG_KMS("probing SDVOC\n");
6367                         found = intel_sdvo_init(dev, SDVOC, false);
6368                 }
6369
6370                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6371
6372                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6373                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6374                                 intel_hdmi_init(dev, SDVOC);
6375                         }
6376                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6377                                 DRM_DEBUG_KMS("probing DP_C\n");
6378                                 intel_dp_init(dev, DP_C);
6379                         }
6380                 }
6381
6382                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6383                     (I915_READ(DP_D) & DP_DETECTED)) {
6384                         DRM_DEBUG_KMS("probing DP_D\n");
6385                         intel_dp_init(dev, DP_D);
6386                 }
6387         } else if (IS_GEN2(dev))
6388                 intel_dvo_init(dev);
6389
6390         if (SUPPORTS_TV(dev))
6391                 intel_tv_init(dev);
6392
6393         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6394                 encoder->base.possible_crtcs = encoder->crtc_mask;
6395                 encoder->base.possible_clones =
6396                         intel_encoder_clones(dev, encoder->clone_mask);
6397         }
6398
6399         /* disable all the possible outputs/crtcs before entering KMS mode */
6400         drm_helper_disable_unused_functions(dev);
6401
6402         if (HAS_PCH_SPLIT(dev))
6403                 ironlake_init_pch_refclk(dev);
6404 }
6405
6406 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6407 {
6408         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6409
6410         drm_framebuffer_cleanup(fb);
6411         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6412
6413         kfree(intel_fb);
6414 }
6415
6416 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6417                                                 struct drm_file *file,
6418                                                 unsigned int *handle)
6419 {
6420         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6421         struct drm_i915_gem_object *obj = intel_fb->obj;
6422
6423         return drm_gem_handle_create(file, &obj->base, handle);
6424 }
6425
6426 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6427         .destroy = intel_user_framebuffer_destroy,
6428         .create_handle = intel_user_framebuffer_create_handle,
6429 };
6430
6431 int intel_framebuffer_init(struct drm_device *dev,
6432                            struct intel_framebuffer *intel_fb,
6433                            struct drm_mode_fb_cmd2 *mode_cmd,
6434                            struct drm_i915_gem_object *obj)
6435 {
6436         int ret;
6437
6438         if (obj->tiling_mode == I915_TILING_Y)
6439                 return -EINVAL;
6440
6441         if (mode_cmd->pitches[0] & 63)
6442                 return -EINVAL;
6443
6444         switch (mode_cmd->pixel_format) {
6445         case DRM_FORMAT_RGB332:
6446         case DRM_FORMAT_RGB565:
6447         case DRM_FORMAT_XRGB8888:
6448         case DRM_FORMAT_XBGR8888:
6449         case DRM_FORMAT_ARGB8888:
6450         case DRM_FORMAT_XRGB2101010:
6451         case DRM_FORMAT_ARGB2101010:
6452                 /* RGB formats are common across chipsets */
6453                 break;
6454         case DRM_FORMAT_YUYV:
6455         case DRM_FORMAT_UYVY:
6456         case DRM_FORMAT_YVYU:
6457         case DRM_FORMAT_VYUY:
6458                 break;
6459         default:
6460                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6461                                 mode_cmd->pixel_format);
6462                 return -EINVAL;
6463         }
6464
6465         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6466         if (ret) {
6467                 DRM_ERROR("framebuffer init failed %d\n", ret);
6468                 return ret;
6469         }
6470
6471         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6472         intel_fb->obj = obj;
6473         return 0;
6474 }
6475
6476 static struct drm_framebuffer *
6477 intel_user_framebuffer_create(struct drm_device *dev,
6478                               struct drm_file *filp,
6479                               struct drm_mode_fb_cmd2 *mode_cmd)
6480 {
6481         struct drm_i915_gem_object *obj;
6482
6483         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6484                                                 mode_cmd->handles[0]));
6485         if (&obj->base == NULL)
6486                 return ERR_PTR(-ENOENT);
6487
6488         return intel_framebuffer_create(dev, mode_cmd, obj);
6489 }
6490
6491 static const struct drm_mode_config_funcs intel_mode_funcs = {
6492         .fb_create = intel_user_framebuffer_create,
6493         .output_poll_changed = intel_fb_output_poll_changed,
6494 };
6495
6496 /* Set up chip specific display functions */
6497 static void intel_init_display(struct drm_device *dev)
6498 {
6499         struct drm_i915_private *dev_priv = dev->dev_private;
6500
6501         /* We always want a DPMS function */
6502         if (HAS_PCH_SPLIT(dev)) {
6503                 dev_priv->display.dpms = ironlake_crtc_dpms;
6504                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6505                 dev_priv->display.off = ironlake_crtc_off;
6506                 dev_priv->display.update_plane = ironlake_update_plane;
6507         } else {
6508                 dev_priv->display.dpms = i9xx_crtc_dpms;
6509                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6510                 dev_priv->display.off = i9xx_crtc_off;
6511                 dev_priv->display.update_plane = i9xx_update_plane;
6512         }
6513
6514         /* Returns the core display clock speed */
6515         if (IS_VALLEYVIEW(dev))
6516                 dev_priv->display.get_display_clock_speed =
6517                         valleyview_get_display_clock_speed;
6518         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6519                 dev_priv->display.get_display_clock_speed =
6520                         i945_get_display_clock_speed;
6521         else if (IS_I915G(dev))
6522                 dev_priv->display.get_display_clock_speed =
6523                         i915_get_display_clock_speed;
6524         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6525                 dev_priv->display.get_display_clock_speed =
6526                         i9xx_misc_get_display_clock_speed;
6527         else if (IS_I915GM(dev))
6528                 dev_priv->display.get_display_clock_speed =
6529                         i915gm_get_display_clock_speed;
6530         else if (IS_I865G(dev))
6531                 dev_priv->display.get_display_clock_speed =
6532                         i865_get_display_clock_speed;
6533         else if (IS_I85X(dev))
6534                 dev_priv->display.get_display_clock_speed =
6535                         i855_get_display_clock_speed;
6536         else /* 852, 830 */
6537                 dev_priv->display.get_display_clock_speed =
6538                         i830_get_display_clock_speed;
6539
6540         if (HAS_PCH_SPLIT(dev)) {
6541                 if (IS_GEN5(dev)) {
6542                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6543                         dev_priv->display.write_eld = ironlake_write_eld;
6544                 } else if (IS_GEN6(dev)) {
6545                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6546                         dev_priv->display.write_eld = ironlake_write_eld;
6547                 } else if (IS_IVYBRIDGE(dev)) {
6548                         /* FIXME: detect B0+ stepping and use auto training */
6549                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6550                         dev_priv->display.write_eld = ironlake_write_eld;
6551                 } else
6552                         dev_priv->display.update_wm = NULL;
6553         } else if (IS_VALLEYVIEW(dev)) {
6554                 dev_priv->display.force_wake_get = vlv_force_wake_get;
6555                 dev_priv->display.force_wake_put = vlv_force_wake_put;
6556         } else if (IS_G4X(dev)) {
6557                 dev_priv->display.write_eld = g4x_write_eld;
6558         }
6559
6560         /* Default just returns -ENODEV to indicate unsupported */
6561         dev_priv->display.queue_flip = intel_default_queue_flip;
6562
6563         switch (INTEL_INFO(dev)->gen) {
6564         case 2:
6565                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6566                 break;
6567
6568         case 3:
6569                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6570                 break;
6571
6572         case 4:
6573         case 5:
6574                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6575                 break;
6576
6577         case 6:
6578                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6579                 break;
6580         case 7:
6581                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6582                 break;
6583         }
6584 }
6585
6586 /*
6587  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6588  * resume, or other times.  This quirk makes sure that's the case for
6589  * affected systems.
6590  */
6591 static void quirk_pipea_force(struct drm_device *dev)
6592 {
6593         struct drm_i915_private *dev_priv = dev->dev_private;
6594
6595         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6596         DRM_INFO("applying pipe a force quirk\n");
6597 }
6598
6599 /*
6600  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6601  */
6602 static void quirk_ssc_force_disable(struct drm_device *dev)
6603 {
6604         struct drm_i915_private *dev_priv = dev->dev_private;
6605         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6606         DRM_INFO("applying lvds SSC disable quirk\n");
6607 }
6608
6609 /*
6610  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6611  * brightness value
6612  */
6613 static void quirk_invert_brightness(struct drm_device *dev)
6614 {
6615         struct drm_i915_private *dev_priv = dev->dev_private;
6616         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6617         DRM_INFO("applying inverted panel brightness quirk\n");
6618 }
6619
6620 struct intel_quirk {
6621         int device;
6622         int subsystem_vendor;
6623         int subsystem_device;
6624         void (*hook)(struct drm_device *dev);
6625 };
6626
6627 static struct intel_quirk intel_quirks[] = {
6628         /* HP Mini needs pipe A force quirk (LP: #322104) */
6629         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6630
6631         /* Thinkpad R31 needs pipe A force quirk */
6632         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6633         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6634         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6635
6636         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6637         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6638         /* ThinkPad X40 needs pipe A force quirk */
6639
6640         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6641         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6642
6643         /* 855 & before need to leave pipe A & dpll A up */
6644         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6645         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6646
6647         /* Lenovo U160 cannot use SSC on LVDS */
6648         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6649
6650         /* Sony Vaio Y cannot use SSC on LVDS */
6651         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6652
6653         /* Acer Aspire 5734Z must invert backlight brightness */
6654         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6655 };
6656
6657 static void intel_init_quirks(struct drm_device *dev)
6658 {
6659         struct pci_dev *d = dev->pdev;
6660         int i;
6661
6662         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6663                 struct intel_quirk *q = &intel_quirks[i];
6664
6665                 if (d->device == q->device &&
6666                     (d->subsystem_vendor == q->subsystem_vendor ||
6667                      q->subsystem_vendor == PCI_ANY_ID) &&
6668                     (d->subsystem_device == q->subsystem_device ||
6669                      q->subsystem_device == PCI_ANY_ID))
6670                         q->hook(dev);
6671         }
6672 }
6673
6674 /* Disable the VGA plane that we never use */
6675 static void i915_disable_vga(struct drm_device *dev)
6676 {
6677         struct drm_i915_private *dev_priv = dev->dev_private;
6678         u8 sr1;
6679         u32 vga_reg;
6680
6681         if (HAS_PCH_SPLIT(dev))
6682                 vga_reg = CPU_VGACNTRL;
6683         else
6684                 vga_reg = VGACNTRL;
6685
6686         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6687         outb(SR01, VGA_SR_INDEX);
6688         sr1 = inb(VGA_SR_DATA);
6689         outb(sr1 | 1<<5, VGA_SR_DATA);
6690         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6691         udelay(300);
6692
6693         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6694         POSTING_READ(vga_reg);
6695 }
6696
6697 static void ivb_pch_pwm_override(struct drm_device *dev)
6698 {
6699         struct drm_i915_private *dev_priv = dev->dev_private;
6700
6701         /*
6702          * IVB has CPU eDP backlight regs too, set things up to let the
6703          * PCH regs control the backlight
6704          */
6705         I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6706         I915_WRITE(BLC_PWM_CPU_CTL, 0);
6707         I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6708 }
6709
6710 void intel_modeset_init_hw(struct drm_device *dev)
6711 {
6712         struct drm_i915_private *dev_priv = dev->dev_private;
6713
6714         intel_init_clock_gating(dev);
6715
6716         if (IS_IRONLAKE_M(dev)) {
6717                 ironlake_enable_drps(dev);
6718                 ironlake_enable_rc6(dev);
6719                 intel_init_emon(dev);
6720         }
6721
6722         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6723                 gen6_enable_rps(dev_priv);
6724                 gen6_update_ring_freq(dev_priv);
6725         }
6726
6727         if (IS_IVYBRIDGE(dev))
6728                 ivb_pch_pwm_override(dev);
6729 }
6730
6731 void intel_modeset_init(struct drm_device *dev)
6732 {
6733         struct drm_i915_private *dev_priv = dev->dev_private;
6734         int i, ret;
6735
6736         drm_mode_config_init(dev);
6737
6738         dev->mode_config.min_width = 0;
6739         dev->mode_config.min_height = 0;
6740
6741         dev->mode_config.preferred_depth = 24;
6742         dev->mode_config.prefer_shadow = 1;
6743
6744         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6745
6746         intel_init_quirks(dev);
6747
6748         intel_init_pm(dev);
6749
6750         intel_init_display(dev);
6751
6752         if (IS_GEN2(dev)) {
6753                 dev->mode_config.max_width = 2048;
6754                 dev->mode_config.max_height = 2048;
6755         } else if (IS_GEN3(dev)) {
6756                 dev->mode_config.max_width = 4096;
6757                 dev->mode_config.max_height = 4096;
6758         } else {
6759                 dev->mode_config.max_width = 8192;
6760                 dev->mode_config.max_height = 8192;
6761         }
6762         dev->mode_config.fb_base = dev->agp->base;
6763
6764         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6765                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6766
6767         for (i = 0; i < dev_priv->num_pipe; i++) {
6768                 intel_crtc_init(dev, i);
6769                 ret = intel_plane_init(dev, i);
6770                 if (ret)
6771                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6772         }
6773
6774         intel_pch_pll_init(dev);
6775
6776         /* Just disable it once at startup */
6777         i915_disable_vga(dev);
6778         intel_setup_outputs(dev);
6779
6780         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6781         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6782                     (unsigned long)dev);
6783 }
6784
6785 void intel_modeset_gem_init(struct drm_device *dev)
6786 {
6787         intel_modeset_init_hw(dev);
6788
6789         intel_setup_overlay(dev);
6790 }
6791
6792 void intel_modeset_cleanup(struct drm_device *dev)
6793 {
6794         struct drm_i915_private *dev_priv = dev->dev_private;
6795         struct drm_crtc *crtc;
6796         struct intel_crtc *intel_crtc;
6797
6798         drm_kms_helper_poll_fini(dev);
6799         mutex_lock(&dev->struct_mutex);
6800
6801         intel_unregister_dsm_handler();
6802
6803
6804         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6805                 /* Skip inactive CRTCs */
6806                 if (!crtc->fb)
6807                         continue;
6808
6809                 intel_crtc = to_intel_crtc(crtc);
6810                 intel_increase_pllclock(crtc);
6811         }
6812
6813         intel_disable_fbc(dev);
6814
6815         if (IS_IRONLAKE_M(dev))
6816                 ironlake_disable_drps(dev);
6817         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
6818                 gen6_disable_rps(dev);
6819
6820         if (IS_IRONLAKE_M(dev))
6821                 ironlake_disable_rc6(dev);
6822
6823         if (IS_VALLEYVIEW(dev))
6824                 vlv_init_dpio(dev);
6825
6826         mutex_unlock(&dev->struct_mutex);
6827
6828         /* Disable the irq before mode object teardown, for the irq might
6829          * enqueue unpin/hotplug work. */
6830         drm_irq_uninstall(dev);
6831         cancel_work_sync(&dev_priv->hotplug_work);
6832         cancel_work_sync(&dev_priv->rps_work);
6833
6834         /* flush any delayed tasks or pending work */
6835         flush_scheduled_work();
6836
6837         /* Shut off idle work before the crtcs get freed. */
6838         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6839                 intel_crtc = to_intel_crtc(crtc);
6840                 del_timer_sync(&intel_crtc->idle_timer);
6841         }
6842         del_timer_sync(&dev_priv->idle_timer);
6843         cancel_work_sync(&dev_priv->idle_work);
6844
6845         drm_mode_config_cleanup(dev);
6846 }
6847
6848 /*
6849  * Return which encoder is currently attached for connector.
6850  */
6851 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6852 {
6853         return &intel_attached_encoder(connector)->base;
6854 }
6855
6856 void intel_connector_attach_encoder(struct intel_connector *connector,
6857                                     struct intel_encoder *encoder)
6858 {
6859         connector->encoder = encoder;
6860         drm_mode_connector_attach_encoder(&connector->base,
6861                                           &encoder->base);
6862 }
6863
6864 /*
6865  * set vga decode state - true == enable VGA decode
6866  */
6867 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6868 {
6869         struct drm_i915_private *dev_priv = dev->dev_private;
6870         u16 gmch_ctrl;
6871
6872         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6873         if (state)
6874                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6875         else
6876                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6877         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6878         return 0;
6879 }
6880
6881 #ifdef CONFIG_DEBUG_FS
6882 #include <linux/seq_file.h>
6883
6884 struct intel_display_error_state {
6885         struct intel_cursor_error_state {
6886                 u32 control;
6887                 u32 position;
6888                 u32 base;
6889                 u32 size;
6890         } cursor[2];
6891
6892         struct intel_pipe_error_state {
6893                 u32 conf;
6894                 u32 source;
6895
6896                 u32 htotal;
6897                 u32 hblank;
6898                 u32 hsync;
6899                 u32 vtotal;
6900                 u32 vblank;
6901                 u32 vsync;
6902         } pipe[2];
6903
6904         struct intel_plane_error_state {
6905                 u32 control;
6906                 u32 stride;
6907                 u32 size;
6908                 u32 pos;
6909                 u32 addr;
6910                 u32 surface;
6911                 u32 tile_offset;
6912         } plane[2];
6913 };
6914
6915 struct intel_display_error_state *
6916 intel_display_capture_error_state(struct drm_device *dev)
6917 {
6918         drm_i915_private_t *dev_priv = dev->dev_private;
6919         struct intel_display_error_state *error;
6920         int i;
6921
6922         error = kmalloc(sizeof(*error), GFP_ATOMIC);
6923         if (error == NULL)
6924                 return NULL;
6925
6926         for (i = 0; i < 2; i++) {
6927                 error->cursor[i].control = I915_READ(CURCNTR(i));
6928                 error->cursor[i].position = I915_READ(CURPOS(i));
6929                 error->cursor[i].base = I915_READ(CURBASE(i));
6930
6931                 error->plane[i].control = I915_READ(DSPCNTR(i));
6932                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6933                 error->plane[i].size = I915_READ(DSPSIZE(i));
6934                 error->plane[i].pos = I915_READ(DSPPOS(i));
6935                 error->plane[i].addr = I915_READ(DSPADDR(i));
6936                 if (INTEL_INFO(dev)->gen >= 4) {
6937                         error->plane[i].surface = I915_READ(DSPSURF(i));
6938                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6939                 }
6940
6941                 error->pipe[i].conf = I915_READ(PIPECONF(i));
6942                 error->pipe[i].source = I915_READ(PIPESRC(i));
6943                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6944                 error->pipe[i].hblank = I915_READ(HBLANK(i));
6945                 error->pipe[i].hsync = I915_READ(HSYNC(i));
6946                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6947                 error->pipe[i].vblank = I915_READ(VBLANK(i));
6948                 error->pipe[i].vsync = I915_READ(VSYNC(i));
6949         }
6950
6951         return error;
6952 }
6953
6954 void
6955 intel_display_print_error_state(struct seq_file *m,
6956                                 struct drm_device *dev,
6957                                 struct intel_display_error_state *error)
6958 {
6959         int i;
6960
6961         for (i = 0; i < 2; i++) {
6962                 seq_printf(m, "Pipe [%d]:\n", i);
6963                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
6964                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
6965                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
6966                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
6967                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
6968                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
6969                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
6970                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
6971
6972                 seq_printf(m, "Plane [%d]:\n", i);
6973                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
6974                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
6975                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
6976                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
6977                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
6978                 if (INTEL_INFO(dev)->gen >= 4) {
6979                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
6980                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
6981                 }
6982
6983                 seq_printf(m, "Cursor [%d]:\n", i);
6984                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
6985                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
6986                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
6987         }
6988 }
6989 #endif