drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_set_mode(struct drm_atomic_state *state);
  90 static int intel_framebuffer_init(struct drm_device *dev,
  91                                   struct intel_framebuffer *ifb,
  92                                   struct drm_mode_fb_cmd2 *mode_cmd,
  93                                   struct drm_i915_gem_object *obj);
  94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  97                                          struct intel_link_m_n *m_n,
  98                                          struct intel_link_m_n *m2_n2);
  99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 102 static void vlv_prepare_pll(struct intel_crtc *crtc,
 103                             const struct intel_crtc_state *pipe_config);
 104 static void chv_prepare_pll(struct intel_crtc *crtc,
 105                             const struct intel_crtc_state *pipe_config);
 106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 109         struct intel_crtc_state *crtc_state);
 110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 111                            int num_connectors);
 112
 113 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 114 {
 115         if (!connector->mst_port)
 116                 return connector->encoder;
 117         else
 118                 return &connector->mst_port->mst_encoders[pipe]->base;
 119 }
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 int
 137 intel_pch_rawclk(struct drm_device *dev)
 138 {
 139         struct drm_i915_private *dev_priv = dev->dev_private;
 140
 141         WARN_ON(!HAS_PCH_SPLIT(dev));
 142
 143         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 144 }
 145
 146 static inline u32 /* units of 100MHz */
 147 intel_fdi_link_freq(struct drm_device *dev)
 148 {
 149         if (IS_GEN5(dev)) {
 150                 struct drm_i915_private *dev_priv = dev->dev_private;
 151                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 152         } else
 153                 return 27;
 154 }
 155
 156 static const intel_limit_t intel_limits_i8xx_dac = {
 157         .dot = { .min = 25000, .max = 350000 },
 158         .vco = { .min = 908000, .max = 1512000 },
 159         .n = { .min = 2, .max = 16 },
 160         .m = { .min = 96, .max = 140 },
 161         .m1 = { .min = 18, .max = 26 },
 162         .m2 = { .min = 6, .max = 16 },
 163         .p = { .min = 4, .max = 128 },
 164         .p1 = { .min = 2, .max = 33 },
 165         .p2 = { .dot_limit = 165000,
 166                 .p2_slow = 4, .p2_fast = 2 },
 167 };
 168
 169 static const intel_limit_t intel_limits_i8xx_dvo = {
 170         .dot = { .min = 25000, .max = 350000 },
 171         .vco = { .min = 908000, .max = 1512000 },
 172         .n = { .min = 2, .max = 16 },
 173         .m = { .min = 96, .max = 140 },
 174         .m1 = { .min = 18, .max = 26 },
 175         .m2 = { .min = 6, .max = 16 },
 176         .p = { .min = 4, .max = 128 },
 177         .p1 = { .min = 2, .max = 33 },
 178         .p2 = { .dot_limit = 165000,
 179                 .p2_slow = 4, .p2_fast = 4 },
 180 };
 181
 182 static const intel_limit_t intel_limits_i8xx_lvds = {
 183         .dot = { .min = 25000, .max = 350000 },
 184         .vco = { .min = 908000, .max = 1512000 },
 185         .n = { .min = 2, .max = 16 },
 186         .m = { .min = 96, .max = 140 },
 187         .m1 = { .min = 18, .max = 26 },
 188         .m2 = { .min = 6, .max = 16 },
 189         .p = { .min = 4, .max = 128 },
 190         .p1 = { .min = 1, .max = 6 },
 191         .p2 = { .dot_limit = 165000,
 192                 .p2_slow = 14, .p2_fast = 7 },
 193 };
 194
 195 static const intel_limit_t intel_limits_i9xx_sdvo = {
 196         .dot = { .min = 20000, .max = 400000 },
 197         .vco = { .min = 1400000, .max = 2800000 },
 198         .n = { .min = 1, .max = 6 },
 199         .m = { .min = 70, .max = 120 },
 200         .m1 = { .min = 8, .max = 18 },
 201         .m2 = { .min = 3, .max = 7 },
 202         .p = { .min = 5, .max = 80 },
 203         .p1 = { .min = 1, .max = 8 },
 204         .p2 = { .dot_limit = 200000,
 205                 .p2_slow = 10, .p2_fast = 5 },
 206 };
 207
 208 static const intel_limit_t intel_limits_i9xx_lvds = {
 209         .dot = { .min = 20000, .max = 400000 },
 210         .vco = { .min = 1400000, .max = 2800000 },
 211         .n = { .min = 1, .max = 6 },
 212         .m = { .min = 70, .max = 120 },
 213         .m1 = { .min = 8, .max = 18 },
 214         .m2 = { .min = 3, .max = 7 },
 215         .p = { .min = 7, .max = 98 },
 216         .p1 = { .min = 1, .max = 8 },
 217         .p2 = { .dot_limit = 112000,
 218                 .p2_slow = 14, .p2_fast = 7 },
 219 };
 220
 221
 222 static const intel_limit_t intel_limits_g4x_sdvo = {
 223         .dot = { .min = 25000, .max = 270000 },
 224         .vco = { .min = 1750000, .max = 3500000},
 225         .n = { .min = 1, .max = 4 },
 226         .m = { .min = 104, .max = 138 },
 227         .m1 = { .min = 17, .max = 23 },
 228         .m2 = { .min = 5, .max = 11 },
 229         .p = { .min = 10, .max = 30 },
 230         .p1 = { .min = 1, .max = 3},
 231         .p2 = { .dot_limit = 270000,
 232                 .p2_slow = 10,
 233                 .p2_fast = 10
 234         },
 235 };
 236
 237 static const intel_limit_t intel_limits_g4x_hdmi = {
 238         .dot = { .min = 22000, .max = 400000 },
 239         .vco = { .min = 1750000, .max = 3500000},
 240         .n = { .min = 1, .max = 4 },
 241         .m = { .min = 104, .max = 138 },
 242         .m1 = { .min = 16, .max = 23 },
 243         .m2 = { .min = 5, .max = 11 },
 244         .p = { .min = 5, .max = 80 },
 245         .p1 = { .min = 1, .max = 8},
 246         .p2 = { .dot_limit = 165000,
 247                 .p2_slow = 10, .p2_fast = 5 },
 248 };
 249
 250 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 251         .dot = { .min = 20000, .max = 115000 },
 252         .vco = { .min = 1750000, .max = 3500000 },
 253         .n = { .min = 1, .max = 3 },
 254         .m = { .min = 104, .max = 138 },
 255         .m1 = { .min = 17, .max = 23 },
 256         .m2 = { .min = 5, .max = 11 },
 257         .p = { .min = 28, .max = 112 },
 258         .p1 = { .min = 2, .max = 8 },
 259         .p2 = { .dot_limit = 0,
 260                 .p2_slow = 14, .p2_fast = 14
 261         },
 262 };
 263
 264 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 265         .dot = { .min = 80000, .max = 224000 },
 266         .vco = { .min = 1750000, .max = 3500000 },
 267         .n = { .min = 1, .max = 3 },
 268         .m = { .min = 104, .max = 138 },
 269         .m1 = { .min = 17, .max = 23 },
 270         .m2 = { .min = 5, .max = 11 },
 271         .p = { .min = 14, .max = 42 },
 272         .p1 = { .min = 2, .max = 6 },
 273         .p2 = { .dot_limit = 0,
 274                 .p2_slow = 7, .p2_fast = 7
 275         },
 276 };
 277
 278 static const intel_limit_t intel_limits_pineview_sdvo = {
 279         .dot = { .min = 20000, .max = 400000},
 280         .vco = { .min = 1700000, .max = 3500000 },
 281         /* Pineview's Ncounter is a ring counter */
 282         .n = { .min = 3, .max = 6 },
 283         .m = { .min = 2, .max = 256 },
 284         /* Pineview only has one combined m divider, which we treat as m2. */
 285         .m1 = { .min = 0, .max = 0 },
 286         .m2 = { .min = 0, .max = 254 },
 287         .p = { .min = 5, .max = 80 },
 288         .p1 = { .min = 1, .max = 8 },
 289         .p2 = { .dot_limit = 200000,
 290                 .p2_slow = 10, .p2_fast = 5 },
 291 };
 292
 293 static const intel_limit_t intel_limits_pineview_lvds = {
 294         .dot = { .min = 20000, .max = 400000 },
 295         .vco = { .min = 1700000, .max = 3500000 },
 296         .n = { .min = 3, .max = 6 },
 297         .m = { .min = 2, .max = 256 },
 298         .m1 = { .min = 0, .max = 0 },
 299         .m2 = { .min = 0, .max = 254 },
 300         .p = { .min = 7, .max = 112 },
 301         .p1 = { .min = 1, .max = 8 },
 302         .p2 = { .dot_limit = 112000,
 303                 .p2_slow = 14, .p2_fast = 14 },
 304 };
 305
 306 /* Ironlake / Sandybridge
 307  *
 308  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 309  * the range value for them is (actual_value - 2).
 310  */
 311 static const intel_limit_t intel_limits_ironlake_dac = {
 312         .dot = { .min = 25000, .max = 350000 },
 313         .vco = { .min = 1760000, .max = 3510000 },
 314         .n = { .min = 1, .max = 5 },
 315         .m = { .min = 79, .max = 127 },
 316         .m1 = { .min = 12, .max = 22 },
 317         .m2 = { .min = 5, .max = 9 },
 318         .p = { .min = 5, .max = 80 },
 319         .p1 = { .min = 1, .max = 8 },
 320         .p2 = { .dot_limit = 225000,
 321                 .p2_slow = 10, .p2_fast = 5 },
 322 };
 323
 324 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 325         .dot = { .min = 25000, .max = 350000 },
 326         .vco = { .min = 1760000, .max = 3510000 },
 327         .n = { .min = 1, .max = 3 },
 328         .m = { .min = 79, .max = 118 },
 329         .m1 = { .min = 12, .max = 22 },
 330         .m2 = { .min = 5, .max = 9 },
 331         .p = { .min = 28, .max = 112 },
 332         .p1 = { .min = 2, .max = 8 },
 333         .p2 = { .dot_limit = 225000,
 334                 .p2_slow = 14, .p2_fast = 14 },
 335 };
 336
 337 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 338         .dot = { .min = 25000, .max = 350000 },
 339         .vco = { .min = 1760000, .max = 3510000 },
 340         .n = { .min = 1, .max = 3 },
 341         .m = { .min = 79, .max = 127 },
 342         .m1 = { .min = 12, .max = 22 },
 343         .m2 = { .min = 5, .max = 9 },
 344         .p = { .min = 14, .max = 56 },
 345         .p1 = { .min = 2, .max = 8 },
 346         .p2 = { .dot_limit = 225000,
 347                 .p2_slow = 7, .p2_fast = 7 },
 348 };
 349
 350 /* LVDS 100mhz refclk limits. */
 351 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 352         .dot = { .min = 25000, .max = 350000 },
 353         .vco = { .min = 1760000, .max = 3510000 },
 354         .n = { .min = 1, .max = 2 },
 355         .m = { .min = 79, .max = 126 },
 356         .m1 = { .min = 12, .max = 22 },
 357         .m2 = { .min = 5, .max = 9 },
 358         .p = { .min = 28, .max = 112 },
 359         .p1 = { .min = 2, .max = 8 },
 360         .p2 = { .dot_limit = 225000,
 361                 .p2_slow = 14, .p2_fast = 14 },
 362 };
 363
 364 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 365         .dot = { .min = 25000, .max = 350000 },
 366         .vco = { .min = 1760000, .max = 3510000 },
 367         .n = { .min = 1, .max = 3 },
 368         .m = { .min = 79, .max = 126 },
 369         .m1 = { .min = 12, .max = 22 },
 370         .m2 = { .min = 5, .max = 9 },
 371         .p = { .min = 14, .max = 42 },
 372         .p1 = { .min = 2, .max = 6 },
 373         .p2 = { .dot_limit = 225000,
 374                 .p2_slow = 7, .p2_fast = 7 },
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv = {
 378          /*
 379           * These are the data rate limits (measured in fast clocks)
 380           * since those are the strictest limits we have. The fast
 381           * clock and actual rate limits are more relaxed, so checking
 382           * them would make no difference.
 383           */
 384         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 385         .vco = { .min = 4000000, .max = 6000000 },
 386         .n = { .min = 1, .max = 7 },
 387         .m1 = { .min = 2, .max = 3 },
 388         .m2 = { .min = 11, .max = 156 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 391 };
 392
 393 static const intel_limit_t intel_limits_chv = {
 394         /*
 395          * These are the data rate limits (measured in fast clocks)
 396          * since those are the strictest limits we have.  The fast
 397          * clock and actual rate limits are more relaxed, so checking
 398          * them would make no difference.
 399          */
 400         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 401         .vco = { .min = 4800000, .max = 6480000 },
 402         .n = { .min = 1, .max = 1 },
 403         .m1 = { .min = 2, .max = 2 },
 404         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 405         .p1 = { .min = 2, .max = 4 },
 406         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 407 };
 408
 409 static const intel_limit_t intel_limits_bxt = {
 410         /* FIXME: find real dot limits */
 411         .dot = { .min = 0, .max = INT_MAX },
 412         .vco = { .min = 4800000, .max = 6480000 },
 413         .n = { .min = 1, .max = 1 },
 414         .m1 = { .min = 2, .max = 2 },
 415         /* FIXME: find real m2 limits */
 416         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 417         .p1 = { .min = 2, .max = 4 },
 418         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 419 };
 420
 421 static bool
 422 needs_modeset(struct drm_crtc_state *state)
 423 {
 424         return state->mode_changed || state->active_changed;
 425 }
 426
 427 /**
 428  * Returns whether any output on the specified pipe is of the specified type
 429  */
 430 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 431 {
 432         struct drm_device *dev = crtc->base.dev;
 433         struct intel_encoder *encoder;
 434
 435         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 436                 if (encoder->type == type)
 437                         return true;
 438
 439         return false;
 440 }
 441
 442 /**
 443  * Returns whether any output on the specified pipe will have the specified
 444  * type after a staged modeset is complete, i.e., the same as
 445  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 446  * encoder->crtc.
 447  */
 448 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 449                                       int type)
 450 {
 451         struct drm_atomic_state *state = crtc_state->base.state;
 452         struct drm_connector *connector;
 453         struct drm_connector_state *connector_state;
 454         struct intel_encoder *encoder;
 455         int i, num_connectors = 0;
 456
 457         for_each_connector_in_state(state, connector, connector_state, i) {
 458                 if (connector_state->crtc != crtc_state->base.crtc)
 459                         continue;
 460
 461                 num_connectors++;
 462
 463                 encoder = to_intel_encoder(connector_state->best_encoder);
 464                 if (encoder->type == type)
 465                         return true;
 466         }
 467
 468         WARN_ON(num_connectors == 0);
 469
 470         return false;
 471 }
 472
 473 static const intel_limit_t *
 474 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 475 {
 476         struct drm_device *dev = crtc_state->base.crtc->dev;
 477         const intel_limit_t *limit;
 478
 479         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 480                 if (intel_is_dual_link_lvds(dev)) {
 481                         if (refclk == 100000)
 482                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 483                         else
 484                                 limit = &intel_limits_ironlake_dual_lvds;
 485                 } else {
 486                         if (refclk == 100000)
 487                                 limit = &intel_limits_ironlake_single_lvds_100m;
 488                         else
 489                                 limit = &intel_limits_ironlake_single_lvds;
 490                 }
 491         } else
 492                 limit = &intel_limits_ironlake_dac;
 493
 494         return limit;
 495 }
 496
 497 static const intel_limit_t *
 498 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 499 {
 500         struct drm_device *dev = crtc_state->base.crtc->dev;
 501         const intel_limit_t *limit;
 502
 503         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 504                 if (intel_is_dual_link_lvds(dev))
 505                         limit = &intel_limits_g4x_dual_channel_lvds;
 506                 else
 507                         limit = &intel_limits_g4x_single_channel_lvds;
 508         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 509                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 510                 limit = &intel_limits_g4x_hdmi;
 511         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 512                 limit = &intel_limits_g4x_sdvo;
 513         } else /* The option is for other outputs */
 514                 limit = &intel_limits_i9xx_sdvo;
 515
 516         return limit;
 517 }
 518
 519 static const intel_limit_t *
 520 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 521 {
 522         struct drm_device *dev = crtc_state->base.crtc->dev;
 523         const intel_limit_t *limit;
 524
 525         if (IS_BROXTON(dev))
 526                 limit = &intel_limits_bxt;
 527         else if (HAS_PCH_SPLIT(dev))
 528                 limit = intel_ironlake_limit(crtc_state, refclk);
 529         else if (IS_G4X(dev)) {
 530                 limit = intel_g4x_limit(crtc_state);
 531         } else if (IS_PINEVIEW(dev)) {
 532                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 533                         limit = &intel_limits_pineview_lvds;
 534                 else
 535                         limit = &intel_limits_pineview_sdvo;
 536         } else if (IS_CHERRYVIEW(dev)) {
 537                 limit = &intel_limits_chv;
 538         } else if (IS_VALLEYVIEW(dev)) {
 539                 limit = &intel_limits_vlv;
 540         } else if (!IS_GEN2(dev)) {
 541                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 542                         limit = &intel_limits_i9xx_lvds;
 543                 else
 544                         limit = &intel_limits_i9xx_sdvo;
 545         } else {
 546                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 547                         limit = &intel_limits_i8xx_lvds;
 548                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 549                         limit = &intel_limits_i8xx_dvo;
 550                 else
 551                         limit = &intel_limits_i8xx_dac;
 552         }
 553         return limit;
 554 }
 555
 556 /*
 557  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 558  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 559  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 560  * The helpers' return value is the rate of the clock that is fed to the
 561  * display engine's pipe which can be the above fast dot clock rate or a
 562  * divided-down version of it.
 563  */
 564 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 565 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 566 {
 567         clock->m = clock->m2 + 2;
 568         clock->p = clock->p1 * clock->p2;
 569         if (WARN_ON(clock->n == 0 || clock->p == 0))
 570                 return 0;
 571         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 572         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 573
 574         return clock->dot;
 575 }
 576
 577 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 578 {
 579         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 580 }
 581
 582 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 583 {
 584         clock->m = i9xx_dpll_compute_m(clock);
 585         clock->p = clock->p1 * clock->p2;
 586         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 587                 return 0;
 588         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 589         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 590
 591         return clock->dot;
 592 }
 593
 594 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 595 {
 596         clock->m = clock->m1 * clock->m2;
 597         clock->p = clock->p1 * clock->p2;
 598         if (WARN_ON(clock->n == 0 || clock->p == 0))
 599                 return 0;
 600         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 601         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 602
 603         return clock->dot / 5;
 604 }
 605
 606 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 607 {
 608         clock->m = clock->m1 * clock->m2;
 609         clock->p = clock->p1 * clock->p2;
 610         if (WARN_ON(clock->n == 0 || clock->p == 0))
 611                 return 0;
 612         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 613                         clock->n << 22);
 614         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 615
 616         return clock->dot / 5;
 617 }
 618
 619 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 620 /**
 621  * Returns whether the given set of divisors are valid for a given refclk with
 622  * the given connectors.
 623  */
 624
 625 static bool intel_PLL_is_valid(struct drm_device *dev,
 626                                const intel_limit_t *limit,
 627                                const intel_clock_t *clock)
 628 {
 629         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 630                 INTELPllInvalid("n out of range\n");
 631         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 632                 INTELPllInvalid("p1 out of range\n");
 633         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 634                 INTELPllInvalid("m2 out of range\n");
 635         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 636                 INTELPllInvalid("m1 out of range\n");
 637
 638         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 639                 if (clock->m1 <= clock->m2)
 640                         INTELPllInvalid("m1 <= m2\n");
 641
 642         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 643                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 644                         INTELPllInvalid("p out of range\n");
 645                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 646                         INTELPllInvalid("m out of range\n");
 647         }
 648
 649         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 650                 INTELPllInvalid("vco out of range\n");
 651         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 652          * connector, etc., rather than just a single range.
 653          */
 654         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 655                 INTELPllInvalid("dot out of range\n");
 656
 657         return true;
 658 }
 659
 660 static int
 661 i9xx_select_p2_div(const intel_limit_t *limit,
 662                    const struct intel_crtc_state *crtc_state,
 663                    int target)
 664 {
 665         struct drm_device *dev = crtc_state->base.crtc->dev;
 666
 667         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 668                 /*
 669                  * For LVDS just rely on its current settings for dual-channel.
 670                  * We haven't figured out how to reliably set up different
 671                  * single/dual channel state, if we even can.
 672                  */
 673                 if (intel_is_dual_link_lvds(dev))
 674                         return limit->p2.p2_fast;
 675                 else
 676                         return limit->p2.p2_slow;
 677         } else {
 678                 if (target < limit->p2.dot_limit)
 679                         return limit->p2.p2_slow;
 680                 else
 681                         return limit->p2.p2_fast;
 682         }
 683 }
 684
 685 static bool
 686 i9xx_find_best_dpll(const intel_limit_t *limit,
 687                     struct intel_crtc_state *crtc_state,
 688                     int target, int refclk, intel_clock_t *match_clock,
 689                     intel_clock_t *best_clock)
 690 {
 691         struct drm_device *dev = crtc_state->base.crtc->dev;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         memset(best_clock, 0, sizeof(*best_clock));
 696
 697         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 698
 699         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 700              clock.m1++) {
 701                 for (clock.m2 = limit->m2.min;
 702                      clock.m2 <= limit->m2.max; clock.m2++) {
 703                         if (clock.m2 >= clock.m1)
 704                                 break;
 705                         for (clock.n = limit->n.min;
 706                              clock.n <= limit->n.max; clock.n++) {
 707                                 for (clock.p1 = limit->p1.min;
 708                                         clock.p1 <= limit->p1.max; clock.p1++) {
 709                                         int this_err;
 710
 711                                         i9xx_calc_dpll_params(refclk, &clock);
 712                                         if (!intel_PLL_is_valid(dev, limit,
 713                                                                 &clock))
 714                                                 continue;
 715                                         if (match_clock &&
 716                                             clock.p != match_clock->p)
 717                                                 continue;
 718
 719                                         this_err = abs(clock.dot - target);
 720                                         if (this_err < err) {
 721                                                 *best_clock = clock;
 722                                                 err = this_err;
 723                                         }
 724                                 }
 725                         }
 726                 }
 727         }
 728
 729         return (err != target);
 730 }
 731
 732 static bool
 733 pnv_find_best_dpll(const intel_limit_t *limit,
 734                    struct intel_crtc_state *crtc_state,
 735                    int target, int refclk, intel_clock_t *match_clock,
 736                    intel_clock_t *best_clock)
 737 {
 738         struct drm_device *dev = crtc_state->base.crtc->dev;
 739         intel_clock_t clock;
 740         int err = target;
 741
 742         memset(best_clock, 0, sizeof(*best_clock));
 743
 744         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 745
 746         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 747              clock.m1++) {
 748                 for (clock.m2 = limit->m2.min;
 749                      clock.m2 <= limit->m2.max; clock.m2++) {
 750                         for (clock.n = limit->n.min;
 751                              clock.n <= limit->n.max; clock.n++) {
 752                                 for (clock.p1 = limit->p1.min;
 753                                         clock.p1 <= limit->p1.max; clock.p1++) {
 754                                         int this_err;
 755
 756                                         pnv_calc_dpll_params(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760                                         if (match_clock &&
 761                                             clock.p != match_clock->p)
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err) {
 766                                                 *best_clock = clock;
 767                                                 err = this_err;
 768                                         }
 769                                 }
 770                         }
 771                 }
 772         }
 773
 774         return (err != target);
 775 }
 776
 777 static bool
 778 g4x_find_best_dpll(const intel_limit_t *limit,
 779                    struct intel_crtc_state *crtc_state,
 780                    int target, int refclk, intel_clock_t *match_clock,
 781                    intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc_state->base.crtc->dev;
 784         intel_clock_t clock;
 785         int max_n;
 786         bool found = false;
 787         /* approximately equals target * 0.00585 */
 788         int err_most = (target >> 8) + (target >> 9);
 789
 790         memset(best_clock, 0, sizeof(*best_clock));
 791
 792         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 793
 794         max_n = limit->n.max;
 795         /* based on hardware requirement, prefer smaller n to precision */
 796         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 797                 /* based on hardware requirement, prefere larger m1,m2 */
 798                 for (clock.m1 = limit->m1.max;
 799                      clock.m1 >= limit->m1.min; clock.m1--) {
 800                         for (clock.m2 = limit->m2.max;
 801                              clock.m2 >= limit->m2.min; clock.m2--) {
 802                                 for (clock.p1 = limit->p1.max;
 803                                      clock.p1 >= limit->p1.min; clock.p1--) {
 804                                         int this_err;
 805
 806                                         i9xx_calc_dpll_params(refclk, &clock);
 807                                         if (!intel_PLL_is_valid(dev, limit,
 808                                                                 &clock))
 809                                                 continue;
 810
 811                                         this_err = abs(clock.dot - target);
 812                                         if (this_err < err_most) {
 813                                                 *best_clock = clock;
 814                                                 err_most = this_err;
 815                                                 max_n = clock.n;
 816                                                 found = true;
 817                                         }
 818                                 }
 819                         }
 820                 }
 821         }
 822         return found;
 823 }
 824
 825 /*
 826  * Check if the calculated PLL configuration is more optimal compared to the
 827  * best configuration and error found so far. Return the calculated error.
 828  */
 829 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 830                                const intel_clock_t *calculated_clock,
 831                                const intel_clock_t *best_clock,
 832                                unsigned int best_error_ppm,
 833                                unsigned int *error_ppm)
 834 {
 835         /*
 836          * For CHV ignore the error and consider only the P value.
 837          * Prefer a bigger P value based on HW requirements.
 838          */
 839         if (IS_CHERRYVIEW(dev)) {
 840                 *error_ppm = 0;
 841
 842                 return calculated_clock->p > best_clock->p;
 843         }
 844
 845         if (WARN_ON_ONCE(!target_freq))
 846                 return false;
 847
 848         *error_ppm = div_u64(1000000ULL *
 849                                 abs(target_freq - calculated_clock->dot),
 850                              target_freq);
 851         /*
 852          * Prefer a better P value over a better (smaller) error if the error
 853          * is small. Ensure this preference for future configurations too by
 854          * setting the error to 0.
 855          */
 856         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 857                 *error_ppm = 0;
 858
 859                 return true;
 860         }
 861
 862         return *error_ppm + 10 < best_error_ppm;
 863 }
 864
 865 static bool
 866 vlv_find_best_dpll(const intel_limit_t *limit,
 867                    struct intel_crtc_state *crtc_state,
 868                    int target, int refclk, intel_clock_t *match_clock,
 869                    intel_clock_t *best_clock)
 870 {
 871         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 872         struct drm_device *dev = crtc->base.dev;
 873         intel_clock_t clock;
 874         unsigned int bestppm = 1000000;
 875         /* min update 19.2 MHz */
 876         int max_n = min(limit->n.max, refclk / 19200);
 877         bool found = false;
 878
 879         target *= 5; /* fast clock */
 880
 881         memset(best_clock, 0, sizeof(*best_clock));
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 885                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 886                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 887                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 888                                 clock.p = clock.p1 * clock.p2;
 889                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 890                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 891                                         unsigned int ppm;
 892
 893                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 894                                                                      refclk * clock.m1);
 895
 896                                         vlv_calc_dpll_params(refclk, &clock);
 897
 898                                         if (!intel_PLL_is_valid(dev, limit,
 899                                                                 &clock))
 900                                                 continue;
 901
 902                                         if (!vlv_PLL_is_optimal(dev, target,
 903                                                                 &clock,
 904                                                                 best_clock,
 905                                                                 bestppm, &ppm))
 906                                                 continue;
 907
 908                                         *best_clock = clock;
 909                                         bestppm = ppm;
 910                                         found = true;
 911                                 }
 912                         }
 913                 }
 914         }
 915
 916         return found;
 917 }
 918
 919 static bool
 920 chv_find_best_dpll(const intel_limit_t *limit,
 921                    struct intel_crtc_state *crtc_state,
 922                    int target, int refclk, intel_clock_t *match_clock,
 923                    intel_clock_t *best_clock)
 924 {
 925         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 926         struct drm_device *dev = crtc->base.dev;
 927         unsigned int best_error_ppm;
 928         intel_clock_t clock;
 929         uint64_t m2;
 930         int found = false;
 931
 932         memset(best_clock, 0, sizeof(*best_clock));
 933         best_error_ppm = 1000000;
 934
 935         /*
 936          * Based on hardware doc, the n always set to 1, and m1 always
 937          * set to 2.  If requires to support 200Mhz refclk, we need to
 938          * revisit this because n may not 1 anymore.
 939          */
 940         clock.n = 1, clock.m1 = 2;
 941         target *= 5;    /* fast clock */
 942
 943         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 944                 for (clock.p2 = limit->p2.p2_fast;
 945                                 clock.p2 >= limit->p2.p2_slow;
 946                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 947                         unsigned int error_ppm;
 948
 949                         clock.p = clock.p1 * clock.p2;
 950
 951                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 952                                         clock.n) << 22, refclk * clock.m1);
 953
 954                         if (m2 > INT_MAX/clock.m1)
 955                                 continue;
 956
 957                         clock.m2 = m2;
 958
 959                         chv_calc_dpll_params(refclk, &clock);
 960
 961                         if (!intel_PLL_is_valid(dev, limit, &clock))
 962                                 continue;
 963
 964                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 965                                                 best_error_ppm, &error_ppm))
 966                                 continue;
 967
 968                         *best_clock = clock;
 969                         best_error_ppm = error_ppm;
 970                         found = true;
 971                 }
 972         }
 973
 974         return found;
 975 }
 976
 977 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 978                         intel_clock_t *best_clock)
 979 {
 980         int refclk = i9xx_get_refclk(crtc_state, 0);
 981
 982         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 983                                   target_clock, refclk, NULL, best_clock);
 984 }
 985
 986 bool intel_crtc_active(struct drm_crtc *crtc)
 987 {
 988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 989
 990         /* Be paranoid as we can arrive here with only partial
 991          * state retrieved from the hardware during setup.
 992          *
 993          * We can ditch the adjusted_mode.crtc_clock check as soon
 994          * as Haswell has gained clock readout/fastboot support.
 995          *
 996          * We can ditch the crtc->primary->fb check as soon as we can
 997          * properly reconstruct framebuffers.
 998          *
 999          * FIXME: The intel_crtc->active here should be switched to
1000          * crtc->state->active once we have proper CRTC states wired up
1001          * for atomic.
1002          */
1003         return intel_crtc->active && crtc->primary->state->fb &&
1004                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1005 }
1006
1007 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1008                                              enum pipe pipe)
1009 {
1010         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1012
1013         return intel_crtc->config->cpu_transcoder;
1014 }
1015
1016 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1017 {
1018         struct drm_i915_private *dev_priv = dev->dev_private;
1019         u32 reg = PIPEDSL(pipe);
1020         u32 line1, line2;
1021         u32 line_mask;
1022
1023         if (IS_GEN2(dev))
1024                 line_mask = DSL_LINEMASK_GEN2;
1025         else
1026                 line_mask = DSL_LINEMASK_GEN3;
1027
1028         line1 = I915_READ(reg) & line_mask;
1029         mdelay(5);
1030         line2 = I915_READ(reg) & line_mask;
1031
1032         return line1 == line2;
1033 }
1034
1035 /*
1036  * intel_wait_for_pipe_off - wait for pipe to turn off
1037  * @crtc: crtc whose pipe to wait for
1038  *
1039  * After disabling a pipe, we can't wait for vblank in the usual way,
1040  * spinning on the vblank interrupt status bit, since we won't actually
1041  * see an interrupt when the pipe is disabled.
1042  *
1043  * On Gen4 and above:
1044  *   wait for the pipe register state bit to turn off
1045  *
1046  * Otherwise:
1047  *   wait for the display line value to settle (it usually
1048  *   ends up stopping at the start of the next frame).
1049  *
1050  */
1051 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1052 {
1053         struct drm_device *dev = crtc->base.dev;
1054         struct drm_i915_private *dev_priv = dev->dev_private;
1055         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1056         enum pipe pipe = crtc->pipe;
1057
1058         if (INTEL_INFO(dev)->gen >= 4) {
1059                 int reg = PIPECONF(cpu_transcoder);
1060
1061                 /* Wait for the Pipe State to go off */
1062                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1063                              100))
1064                         WARN(1, "pipe_off wait timed out\n");
1065         } else {
1066                 /* Wait for the display line to settle */
1067                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1068                         WARN(1, "pipe_off wait timed out\n");
1069         }
1070 }
1071
1072 /*
1073  * ibx_digital_port_connected - is the specified port connected?
1074  * @dev_priv: i915 private structure
1075  * @port: the port to test
1076  *
1077  * Returns true if @port is connected, false otherwise.
1078  */
1079 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1080                                 struct intel_digital_port *port)
1081 {
1082         u32 bit;
1083
1084         if (HAS_PCH_IBX(dev_priv->dev)) {
1085                 switch (port->port) {
1086                 case PORT_B:
1087                         bit = SDE_PORTB_HOTPLUG;
1088                         break;
1089                 case PORT_C:
1090                         bit = SDE_PORTC_HOTPLUG;
1091                         break;
1092                 case PORT_D:
1093                         bit = SDE_PORTD_HOTPLUG;
1094                         break;
1095                 default:
1096                         return true;
1097                 }
1098         } else {
1099                 switch (port->port) {
1100                 case PORT_B:
1101                         bit = SDE_PORTB_HOTPLUG_CPT;
1102                         break;
1103                 case PORT_C:
1104                         bit = SDE_PORTC_HOTPLUG_CPT;
1105                         break;
1106                 case PORT_D:
1107                         bit = SDE_PORTD_HOTPLUG_CPT;
1108                         break;
1109                 default:
1110                         return true;
1111                 }
1112         }
1113
1114         return I915_READ(SDEISR) & bit;
1115 }
1116
1117 static const char *state_string(bool enabled)
1118 {
1119         return enabled ? "on" : "off";
1120 }
1121
1122 /* Only for pre-ILK configs */
1123 void assert_pll(struct drm_i915_private *dev_priv,
1124                 enum pipe pipe, bool state)
1125 {
1126         int reg;
1127         u32 val;
1128         bool cur_state;
1129
1130         reg = DPLL(pipe);
1131         val = I915_READ(reg);
1132         cur_state = !!(val & DPLL_VCO_ENABLE);
1133         I915_STATE_WARN(cur_state != state,
1134              "PLL state assertion failure (expected %s, current %s)\n",
1135              state_string(state), state_string(cur_state));
1136 }
1137
1138 /* XXX: the dsi pll is shared between MIPI DSI ports */
1139 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1140 {
1141         u32 val;
1142         bool cur_state;
1143
1144         mutex_lock(&dev_priv->sb_lock);
1145         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1146         mutex_unlock(&dev_priv->sb_lock);
1147
1148         cur_state = val & DSI_PLL_VCO_EN;
1149         I915_STATE_WARN(cur_state != state,
1150              "DSI PLL state assertion failure (expected %s, current %s)\n",
1151              state_string(state), state_string(cur_state));
1152 }
1153 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1154 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1155
1156 struct intel_shared_dpll *
1157 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1158 {
1159         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1160
1161         if (crtc->config->shared_dpll < 0)
1162                 return NULL;
1163
1164         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1165 }
1166
1167 /* For ILK+ */
1168 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1169                         struct intel_shared_dpll *pll,
1170                         bool state)
1171 {
1172         bool cur_state;
1173         struct intel_dpll_hw_state hw_state;
1174
1175         if (WARN (!pll,
1176                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1177                 return;
1178
1179         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1180         I915_STATE_WARN(cur_state != state,
1181              "%s assertion failure (expected %s, current %s)\n",
1182              pll->name, state_string(state), state_string(cur_state));
1183 }
1184
1185 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1186                           enum pipe pipe, bool state)
1187 {
1188         int reg;
1189         u32 val;
1190         bool cur_state;
1191         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192                                                                       pipe);
1193
1194         if (HAS_DDI(dev_priv->dev)) {
1195                 /* DDI does not have a specific FDI_TX register */
1196                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1197                 val = I915_READ(reg);
1198                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1199         } else {
1200                 reg = FDI_TX_CTL(pipe);
1201                 val = I915_READ(reg);
1202                 cur_state = !!(val & FDI_TX_ENABLE);
1203         }
1204         I915_STATE_WARN(cur_state != state,
1205              "FDI TX state assertion failure (expected %s, current %s)\n",
1206              state_string(state), state_string(cur_state));
1207 }
1208 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1209 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1210
1211 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1212                           enum pipe pipe, bool state)
1213 {
1214         int reg;
1215         u32 val;
1216         bool cur_state;
1217
1218         reg = FDI_RX_CTL(pipe);
1219         val = I915_READ(reg);
1220         cur_state = !!(val & FDI_RX_ENABLE);
1221         I915_STATE_WARN(cur_state != state,
1222              "FDI RX state assertion failure (expected %s, current %s)\n",
1223              state_string(state), state_string(cur_state));
1224 }
1225 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1226 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1227
1228 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1229                                       enum pipe pipe)
1230 {
1231         int reg;
1232         u32 val;
1233
1234         /* ILK FDI PLL is always enabled */
1235         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1236                 return;
1237
1238         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1239         if (HAS_DDI(dev_priv->dev))
1240                 return;
1241
1242         reg = FDI_TX_CTL(pipe);
1243         val = I915_READ(reg);
1244         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1245 }
1246
1247 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1248                        enum pipe pipe, bool state)
1249 {
1250         int reg;
1251         u32 val;
1252         bool cur_state;
1253
1254         reg = FDI_RX_CTL(pipe);
1255         val = I915_READ(reg);
1256         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1257         I915_STATE_WARN(cur_state != state,
1258              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1259              state_string(state), state_string(cur_state));
1260 }
1261
1262 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1263                            enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int pp_reg;
1267         u32 val;
1268         enum pipe panel_pipe = PIPE_A;
1269         bool locked = true;
1270
1271         if (WARN_ON(HAS_DDI(dev)))
1272                 return;
1273
1274         if (HAS_PCH_SPLIT(dev)) {
1275                 u32 port_sel;
1276
1277                 pp_reg = PCH_PP_CONTROL;
1278                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1279
1280                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1281                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1282                         panel_pipe = PIPE_B;
1283                 /* XXX: else fix for eDP */
1284         } else if (IS_VALLEYVIEW(dev)) {
1285                 /* presumably write lock depends on pipe, not port select */
1286                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1287                 panel_pipe = pipe;
1288         } else {
1289                 pp_reg = PP_CONTROL;
1290                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1291                         panel_pipe = PIPE_B;
1292         }
1293
1294         val = I915_READ(pp_reg);
1295         if (!(val & PANEL_POWER_ON) ||
1296             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1297                 locked = false;
1298
1299         I915_STATE_WARN(panel_pipe == pipe && locked,
1300              "panel assertion failure, pipe %c regs locked\n",
1301              pipe_name(pipe));
1302 }
1303
1304 static void assert_cursor(struct drm_i915_private *dev_priv,
1305                           enum pipe pipe, bool state)
1306 {
1307         struct drm_device *dev = dev_priv->dev;
1308         bool cur_state;
1309
1310         if (IS_845G(dev) || IS_I865G(dev))
1311                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1312         else
1313                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1314
1315         I915_STATE_WARN(cur_state != state,
1316              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1317              pipe_name(pipe), state_string(state), state_string(cur_state));
1318 }
1319 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1320 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1321
1322 void assert_pipe(struct drm_i915_private *dev_priv,
1323                  enum pipe pipe, bool state)
1324 {
1325         int reg;
1326         u32 val;
1327         bool cur_state;
1328         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1329                                                                       pipe);
1330
1331         /* if we need the pipe quirk it must be always on */
1332         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1333             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1334                 state = true;
1335
1336         if (!intel_display_power_is_enabled(dev_priv,
1337                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1338                 cur_state = false;
1339         } else {
1340                 reg = PIPECONF(cpu_transcoder);
1341                 val = I915_READ(reg);
1342                 cur_state = !!(val & PIPECONF_ENABLE);
1343         }
1344
1345         I915_STATE_WARN(cur_state != state,
1346              "pipe %c assertion failure (expected %s, current %s)\n",
1347              pipe_name(pipe), state_string(state), state_string(cur_state));
1348 }
1349
1350 static void assert_plane(struct drm_i915_private *dev_priv,
1351                          enum plane plane, bool state)
1352 {
1353         int reg;
1354         u32 val;
1355         bool cur_state;
1356
1357         reg = DSPCNTR(plane);
1358         val = I915_READ(reg);
1359         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1360         I915_STATE_WARN(cur_state != state,
1361              "plane %c assertion failure (expected %s, current %s)\n",
1362              plane_name(plane), state_string(state), state_string(cur_state));
1363 }
1364
1365 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1366 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1367
1368 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1369                                    enum pipe pipe)
1370 {
1371         struct drm_device *dev = dev_priv->dev;
1372         int reg, i;
1373         u32 val;
1374         int cur_pipe;
1375
1376         /* Primary planes are fixed to pipes on gen4+ */
1377         if (INTEL_INFO(dev)->gen >= 4) {
1378                 reg = DSPCNTR(pipe);
1379                 val = I915_READ(reg);
1380                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1381                      "plane %c assertion failure, should be disabled but not\n",
1382                      plane_name(pipe));
1383                 return;
1384         }
1385
1386         /* Need to check both planes against the pipe */
1387         for_each_pipe(dev_priv, i) {
1388                 reg = DSPCNTR(i);
1389                 val = I915_READ(reg);
1390                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1391                         DISPPLANE_SEL_PIPE_SHIFT;
1392                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1393                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1394                      plane_name(i), pipe_name(pipe));
1395         }
1396 }
1397
1398 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1399                                     enum pipe pipe)
1400 {
1401         struct drm_device *dev = dev_priv->dev;
1402         int reg, sprite;
1403         u32 val;
1404
1405         if (INTEL_INFO(dev)->gen >= 9) {
1406                 for_each_sprite(dev_priv, pipe, sprite) {
1407                         val = I915_READ(PLANE_CTL(pipe, sprite));
1408                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1409                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1410                              sprite, pipe_name(pipe));
1411                 }
1412         } else if (IS_VALLEYVIEW(dev)) {
1413                 for_each_sprite(dev_priv, pipe, sprite) {
1414                         reg = SPCNTR(pipe, sprite);
1415                         val = I915_READ(reg);
1416                         I915_STATE_WARN(val & SP_ENABLE,
1417                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1418                              sprite_name(pipe, sprite), pipe_name(pipe));
1419                 }
1420         } else if (INTEL_INFO(dev)->gen >= 7) {
1421                 reg = SPRCTL(pipe);
1422                 val = I915_READ(reg);
1423                 I915_STATE_WARN(val & SPRITE_ENABLE,
1424                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425                      plane_name(pipe), pipe_name(pipe));
1426         } else if (INTEL_INFO(dev)->gen >= 5) {
1427                 reg = DVSCNTR(pipe);
1428                 val = I915_READ(reg);
1429                 I915_STATE_WARN(val & DVS_ENABLE,
1430                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431                      plane_name(pipe), pipe_name(pipe));
1432         }
1433 }
1434
1435 static void assert_vblank_disabled(struct drm_crtc *crtc)
1436 {
1437         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1438                 drm_crtc_vblank_put(crtc);
1439 }
1440
1441 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1442 {
1443         u32 val;
1444         bool enabled;
1445
1446         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1447
1448         val = I915_READ(PCH_DREF_CONTROL);
1449         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1450                             DREF_SUPERSPREAD_SOURCE_MASK));
1451         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1452 }
1453
1454 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1455                                            enum pipe pipe)
1456 {
1457         int reg;
1458         u32 val;
1459         bool enabled;
1460
1461         reg = PCH_TRANSCONF(pipe);
1462         val = I915_READ(reg);
1463         enabled = !!(val & TRANS_ENABLE);
1464         I915_STATE_WARN(enabled,
1465              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1466              pipe_name(pipe));
1467 }
1468
1469 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1470                             enum pipe pipe, u32 port_sel, u32 val)
1471 {
1472         if ((val & DP_PORT_EN) == 0)
1473                 return false;
1474
1475         if (HAS_PCH_CPT(dev_priv->dev)) {
1476                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1477                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1478                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1479                         return false;
1480         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1481                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1482                         return false;
1483         } else {
1484                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1485                         return false;
1486         }
1487         return true;
1488 }
1489
1490 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1491                               enum pipe pipe, u32 val)
1492 {
1493         if ((val & SDVO_ENABLE) == 0)
1494                 return false;
1495
1496         if (HAS_PCH_CPT(dev_priv->dev)) {
1497                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1498                         return false;
1499         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1500                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1501                         return false;
1502         } else {
1503                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1504                         return false;
1505         }
1506         return true;
1507 }
1508
1509 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1510                               enum pipe pipe, u32 val)
1511 {
1512         if ((val & LVDS_PORT_EN) == 0)
1513                 return false;
1514
1515         if (HAS_PCH_CPT(dev_priv->dev)) {
1516                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1517                         return false;
1518         } else {
1519                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1520                         return false;
1521         }
1522         return true;
1523 }
1524
1525 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1526                               enum pipe pipe, u32 val)
1527 {
1528         if ((val & ADPA_DAC_ENABLE) == 0)
1529                 return false;
1530         if (HAS_PCH_CPT(dev_priv->dev)) {
1531                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1532                         return false;
1533         } else {
1534                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1535                         return false;
1536         }
1537         return true;
1538 }
1539
1540 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1541                                    enum pipe pipe, int reg, u32 port_sel)
1542 {
1543         u32 val = I915_READ(reg);
1544         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1545              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1546              reg, pipe_name(pipe));
1547
1548         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1549              && (val & DP_PIPEB_SELECT),
1550              "IBX PCH dp port still using transcoder B\n");
1551 }
1552
1553 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1554                                      enum pipe pipe, int reg)
1555 {
1556         u32 val = I915_READ(reg);
1557         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1558              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1559              reg, pipe_name(pipe));
1560
1561         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1562              && (val & SDVO_PIPE_B_SELECT),
1563              "IBX PCH hdmi port still using transcoder B\n");
1564 }
1565
1566 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1567                                       enum pipe pipe)
1568 {
1569         int reg;
1570         u32 val;
1571
1572         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1573         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1574         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1575
1576         reg = PCH_ADPA;
1577         val = I915_READ(reg);
1578         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1579              "PCH VGA enabled on transcoder %c, should be disabled\n",
1580              pipe_name(pipe));
1581
1582         reg = PCH_LVDS;
1583         val = I915_READ(reg);
1584         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1585              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1586              pipe_name(pipe));
1587
1588         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1591 }
1592
1593 static void intel_init_dpio(struct drm_device *dev)
1594 {
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597         if (!IS_VALLEYVIEW(dev))
1598                 return;
1599
1600         /*
1601          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1602          * CHV x1 PHY (DP/HDMI D)
1603          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1604          */
1605         if (IS_CHERRYVIEW(dev)) {
1606                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1607                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1608         } else {
1609                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1610         }
1611 }
1612
1613 static void vlv_enable_pll(struct intel_crtc *crtc,
1614                            const struct intel_crtc_state *pipe_config)
1615 {
1616         struct drm_device *dev = crtc->base.dev;
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618         int reg = DPLL(crtc->pipe);
1619         u32 dpll = pipe_config->dpll_hw_state.dpll;
1620
1621         assert_pipe_disabled(dev_priv, crtc->pipe);
1622
1623         /* No really, not for ILK+ */
1624         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1625
1626         /* PLL is protected by panel, make sure we can write it */
1627         if (IS_MOBILE(dev_priv->dev))
1628                 assert_panel_unlocked(dev_priv, crtc->pipe);
1629
1630         I915_WRITE(reg, dpll);
1631         POSTING_READ(reg);
1632         udelay(150);
1633
1634         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1636
1637         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1638         POSTING_READ(DPLL_MD(crtc->pipe));
1639
1640         /* We do this three times for luck */
1641         I915_WRITE(reg, dpll);
1642         POSTING_READ(reg);
1643         udelay(150); /* wait for warmup */
1644         I915_WRITE(reg, dpll);
1645         POSTING_READ(reg);
1646         udelay(150); /* wait for warmup */
1647         I915_WRITE(reg, dpll);
1648         POSTING_READ(reg);
1649         udelay(150); /* wait for warmup */
1650 }
1651
1652 static void chv_enable_pll(struct intel_crtc *crtc,
1653                            const struct intel_crtc_state *pipe_config)
1654 {
1655         struct drm_device *dev = crtc->base.dev;
1656         struct drm_i915_private *dev_priv = dev->dev_private;
1657         int pipe = crtc->pipe;
1658         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1659         u32 tmp;
1660
1661         assert_pipe_disabled(dev_priv, crtc->pipe);
1662
1663         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1664
1665         mutex_lock(&dev_priv->sb_lock);
1666
1667         /* Enable back the 10bit clock to display controller */
1668         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1669         tmp |= DPIO_DCLKP_EN;
1670         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1671
1672         mutex_unlock(&dev_priv->sb_lock);
1673
1674         /*
1675          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1676          */
1677         udelay(1);
1678
1679         /* Enable PLL */
1680         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1681
1682         /* Check PLL is locked */
1683         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1684                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1685
1686         /* not sure when this should be written */
1687         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1688         POSTING_READ(DPLL_MD(pipe));
1689 }
1690
1691 static int intel_num_dvo_pipes(struct drm_device *dev)
1692 {
1693         struct intel_crtc *crtc;
1694         int count = 0;
1695
1696         for_each_intel_crtc(dev, crtc)
1697                 count += crtc->base.state->active &&
1698                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1699
1700         return count;
1701 }
1702
1703 static void i9xx_enable_pll(struct intel_crtc *crtc)
1704 {
1705         struct drm_device *dev = crtc->base.dev;
1706         struct drm_i915_private *dev_priv = dev->dev_private;
1707         int reg = DPLL(crtc->pipe);
1708         u32 dpll = crtc->config->dpll_hw_state.dpll;
1709
1710         assert_pipe_disabled(dev_priv, crtc->pipe);
1711
1712         /* No really, not for ILK+ */
1713         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1714
1715         /* PLL is protected by panel, make sure we can write it */
1716         if (IS_MOBILE(dev) && !IS_I830(dev))
1717                 assert_panel_unlocked(dev_priv, crtc->pipe);
1718
1719         /* Enable DVO 2x clock on both PLLs if necessary */
1720         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1721                 /*
1722                  * It appears to be important that we don't enable this
1723                  * for the current pipe before otherwise configuring the
1724                  * PLL. No idea how this should be handled if multiple
1725                  * DVO outputs are enabled simultaneosly.
1726                  */
1727                 dpll |= DPLL_DVO_2X_MODE;
1728                 I915_WRITE(DPLL(!crtc->pipe),
1729                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1730         }
1731
1732         /* Wait for the clocks to stabilize. */
1733         POSTING_READ(reg);
1734         udelay(150);
1735
1736         if (INTEL_INFO(dev)->gen >= 4) {
1737                 I915_WRITE(DPLL_MD(crtc->pipe),
1738                            crtc->config->dpll_hw_state.dpll_md);
1739         } else {
1740                 /* The pixel multiplier can only be updated once the
1741                  * DPLL is enabled and the clocks are stable.
1742                  *
1743                  * So write it again.
1744                  */
1745                 I915_WRITE(reg, dpll);
1746         }
1747
1748         /* We do this three times for luck */
1749         I915_WRITE(reg, dpll);
1750         POSTING_READ(reg);
1751         udelay(150); /* wait for warmup */
1752         I915_WRITE(reg, dpll);
1753         POSTING_READ(reg);
1754         udelay(150); /* wait for warmup */
1755         I915_WRITE(reg, dpll);
1756         POSTING_READ(reg);
1757         udelay(150); /* wait for warmup */
1758 }
1759
1760 /**
1761  * i9xx_disable_pll - disable a PLL
1762  * @dev_priv: i915 private structure
1763  * @pipe: pipe PLL to disable
1764  *
1765  * Disable the PLL for @pipe, making sure the pipe is off first.
1766  *
1767  * Note!  This is for pre-ILK only.
1768  */
1769 static void i9xx_disable_pll(struct intel_crtc *crtc)
1770 {
1771         struct drm_device *dev = crtc->base.dev;
1772         struct drm_i915_private *dev_priv = dev->dev_private;
1773         enum pipe pipe = crtc->pipe;
1774
1775         /* Disable DVO 2x clock on both PLLs if necessary */
1776         if (IS_I830(dev) &&
1777             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1778             !intel_num_dvo_pipes(dev)) {
1779                 I915_WRITE(DPLL(PIPE_B),
1780                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1781                 I915_WRITE(DPLL(PIPE_A),
1782                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1783         }
1784
1785         /* Don't disable pipe or pipe PLLs if needed */
1786         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1787             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1788                 return;
1789
1790         /* Make sure the pipe isn't still relying on us */
1791         assert_pipe_disabled(dev_priv, pipe);
1792
1793         I915_WRITE(DPLL(pipe), 0);
1794         POSTING_READ(DPLL(pipe));
1795 }
1796
1797 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1798 {
1799         u32 val = 0;
1800
1801         /* Make sure the pipe isn't still relying on us */
1802         assert_pipe_disabled(dev_priv, pipe);
1803
1804         /*
1805          * Leave integrated clock source and reference clock enabled for pipe B.
1806          * The latter is needed for VGA hotplug / manual detection.
1807          */
1808         if (pipe == PIPE_B)
1809                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1810         I915_WRITE(DPLL(pipe), val);
1811         POSTING_READ(DPLL(pipe));
1812
1813 }
1814
1815 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1816 {
1817         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1818         u32 val;
1819
1820         /* Make sure the pipe isn't still relying on us */
1821         assert_pipe_disabled(dev_priv, pipe);
1822
1823         /* Set PLL en = 0 */
1824         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1825         if (pipe != PIPE_A)
1826                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1827         I915_WRITE(DPLL(pipe), val);
1828         POSTING_READ(DPLL(pipe));
1829
1830         mutex_lock(&dev_priv->sb_lock);
1831
1832         /* Disable 10bit clock to display controller */
1833         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1834         val &= ~DPIO_DCLKP_EN;
1835         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1836
1837         /* disable left/right clock distribution */
1838         if (pipe != PIPE_B) {
1839                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1840                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1841                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1842         } else {
1843                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1844                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1845                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1846         }
1847
1848         mutex_unlock(&dev_priv->sb_lock);
1849 }
1850
1851 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1852                          struct intel_digital_port *dport,
1853                          unsigned int expected_mask)
1854 {
1855         u32 port_mask;
1856         int dpll_reg;
1857
1858         switch (dport->port) {
1859         case PORT_B:
1860                 port_mask = DPLL_PORTB_READY_MASK;
1861                 dpll_reg = DPLL(0);
1862                 break;
1863         case PORT_C:
1864                 port_mask = DPLL_PORTC_READY_MASK;
1865                 dpll_reg = DPLL(0);
1866                 expected_mask <<= 4;
1867                 break;
1868         case PORT_D:
1869                 port_mask = DPLL_PORTD_READY_MASK;
1870                 dpll_reg = DPIO_PHY_STATUS;
1871                 break;
1872         default:
1873                 BUG();
1874         }
1875
1876         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1877                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1878                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1879 }
1880
1881 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1882 {
1883         struct drm_device *dev = crtc->base.dev;
1884         struct drm_i915_private *dev_priv = dev->dev_private;
1885         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1886
1887         if (WARN_ON(pll == NULL))
1888                 return;
1889
1890         WARN_ON(!pll->config.crtc_mask);
1891         if (pll->active == 0) {
1892                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1893                 WARN_ON(pll->on);
1894                 assert_shared_dpll_disabled(dev_priv, pll);
1895
1896                 pll->mode_set(dev_priv, pll);
1897         }
1898 }
1899
1900 /**
1901  * intel_enable_shared_dpll - enable PCH PLL
1902  * @dev_priv: i915 private structure
1903  * @pipe: pipe PLL to enable
1904  *
1905  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1906  * drives the transcoder clock.
1907  */
1908 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1909 {
1910         struct drm_device *dev = crtc->base.dev;
1911         struct drm_i915_private *dev_priv = dev->dev_private;
1912         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1913
1914         if (WARN_ON(pll == NULL))
1915                 return;
1916
1917         if (WARN_ON(pll->config.crtc_mask == 0))
1918                 return;
1919
1920         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1921                       pll->name, pll->active, pll->on,
1922                       crtc->base.base.id);
1923
1924         if (pll->active++) {
1925                 WARN_ON(!pll->on);
1926                 assert_shared_dpll_enabled(dev_priv, pll);
1927                 return;
1928         }
1929         WARN_ON(pll->on);
1930
1931         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1932
1933         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1934         pll->enable(dev_priv, pll);
1935         pll->on = true;
1936 }
1937
1938 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1939 {
1940         struct drm_device *dev = crtc->base.dev;
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1943
1944         /* PCH only available on ILK+ */
1945         BUG_ON(INTEL_INFO(dev)->gen < 5);
1946         if (pll == NULL)
1947                 return;
1948
1949         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1950                 return;
1951
1952         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1953                       pll->name, pll->active, pll->on,
1954                       crtc->base.base.id);
1955
1956         if (WARN_ON(pll->active == 0)) {
1957                 assert_shared_dpll_disabled(dev_priv, pll);
1958                 return;
1959         }
1960
1961         assert_shared_dpll_enabled(dev_priv, pll);
1962         WARN_ON(!pll->on);
1963         if (--pll->active)
1964                 return;
1965
1966         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1967         pll->disable(dev_priv, pll);
1968         pll->on = false;
1969
1970         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1971 }
1972
1973 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1974                                            enum pipe pipe)
1975 {
1976         struct drm_device *dev = dev_priv->dev;
1977         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1979         uint32_t reg, val, pipeconf_val;
1980
1981         /* PCH only available on ILK+ */
1982         BUG_ON(!HAS_PCH_SPLIT(dev));
1983
1984         /* Make sure PCH DPLL is enabled */
1985         assert_shared_dpll_enabled(dev_priv,
1986                                    intel_crtc_to_shared_dpll(intel_crtc));
1987
1988         /* FDI must be feeding us bits for PCH ports */
1989         assert_fdi_tx_enabled(dev_priv, pipe);
1990         assert_fdi_rx_enabled(dev_priv, pipe);
1991
1992         if (HAS_PCH_CPT(dev)) {
1993                 /* Workaround: Set the timing override bit before enabling the
1994                  * pch transcoder. */
1995                 reg = TRANS_CHICKEN2(pipe);
1996                 val = I915_READ(reg);
1997                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1998                 I915_WRITE(reg, val);
1999         }
2000
2001         reg = PCH_TRANSCONF(pipe);
2002         val = I915_READ(reg);
2003         pipeconf_val = I915_READ(PIPECONF(pipe));
2004
2005         if (HAS_PCH_IBX(dev_priv->dev)) {
2006                 /*
2007                  * Make the BPC in transcoder be consistent with
2008                  * that in pipeconf reg. For HDMI we must use 8bpc
2009                  * here for both 8bpc and 12bpc.
2010                  */
2011                 val &= ~PIPECONF_BPC_MASK;
2012                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2013                         val |= PIPECONF_8BPC;
2014                 else
2015                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2016         }
2017
2018         val &= ~TRANS_INTERLACE_MASK;
2019         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2020                 if (HAS_PCH_IBX(dev_priv->dev) &&
2021                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2022                         val |= TRANS_LEGACY_INTERLACED_ILK;
2023                 else
2024                         val |= TRANS_INTERLACED;
2025         else
2026                 val |= TRANS_PROGRESSIVE;
2027
2028         I915_WRITE(reg, val | TRANS_ENABLE);
2029         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2030                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2031 }
2032
2033 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2034                                       enum transcoder cpu_transcoder)
2035 {
2036         u32 val, pipeconf_val;
2037
2038         /* PCH only available on ILK+ */
2039         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2040
2041         /* FDI must be feeding us bits for PCH ports */
2042         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2043         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2044
2045         /* Workaround: set timing override bit. */
2046         val = I915_READ(_TRANSA_CHICKEN2);
2047         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2048         I915_WRITE(_TRANSA_CHICKEN2, val);
2049
2050         val = TRANS_ENABLE;
2051         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2052
2053         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2054             PIPECONF_INTERLACED_ILK)
2055                 val |= TRANS_INTERLACED;
2056         else
2057                 val |= TRANS_PROGRESSIVE;
2058
2059         I915_WRITE(LPT_TRANSCONF, val);
2060         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2061                 DRM_ERROR("Failed to enable PCH transcoder\n");
2062 }
2063
2064 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2065                                             enum pipe pipe)
2066 {
2067         struct drm_device *dev = dev_priv->dev;
2068         uint32_t reg, val;
2069
2070         /* FDI relies on the transcoder */
2071         assert_fdi_tx_disabled(dev_priv, pipe);
2072         assert_fdi_rx_disabled(dev_priv, pipe);
2073
2074         /* Ports must be off as well */
2075         assert_pch_ports_disabled(dev_priv, pipe);
2076
2077         reg = PCH_TRANSCONF(pipe);
2078         val = I915_READ(reg);
2079         val &= ~TRANS_ENABLE;
2080         I915_WRITE(reg, val);
2081         /* wait for PCH transcoder off, transcoder state */
2082         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2083                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2084
2085         if (!HAS_PCH_IBX(dev)) {
2086                 /* Workaround: Clear the timing override chicken bit again. */
2087                 reg = TRANS_CHICKEN2(pipe);
2088                 val = I915_READ(reg);
2089                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2090                 I915_WRITE(reg, val);
2091         }
2092 }
2093
2094 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2095 {
2096         u32 val;
2097
2098         val = I915_READ(LPT_TRANSCONF);
2099         val &= ~TRANS_ENABLE;
2100         I915_WRITE(LPT_TRANSCONF, val);
2101         /* wait for PCH transcoder off, transcoder state */
2102         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2103                 DRM_ERROR("Failed to disable PCH transcoder\n");
2104
2105         /* Workaround: clear timing override bit. */
2106         val = I915_READ(_TRANSA_CHICKEN2);
2107         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2108         I915_WRITE(_TRANSA_CHICKEN2, val);
2109 }
2110
2111 /**
2112  * intel_enable_pipe - enable a pipe, asserting requirements
2113  * @crtc: crtc responsible for the pipe
2114  *
2115  * Enable @crtc's pipe, making sure that various hardware specific requirements
2116  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2117  */
2118 static void intel_enable_pipe(struct intel_crtc *crtc)
2119 {
2120         struct drm_device *dev = crtc->base.dev;
2121         struct drm_i915_private *dev_priv = dev->dev_private;
2122         enum pipe pipe = crtc->pipe;
2123         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2124                                                                       pipe);
2125         enum pipe pch_transcoder;
2126         int reg;
2127         u32 val;
2128
2129         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2130
2131         assert_planes_disabled(dev_priv, pipe);
2132         assert_cursor_disabled(dev_priv, pipe);
2133         assert_sprites_disabled(dev_priv, pipe);
2134
2135         if (HAS_PCH_LPT(dev_priv->dev))
2136                 pch_transcoder = TRANSCODER_A;
2137         else
2138                 pch_transcoder = pipe;
2139
2140         /*
2141          * A pipe without a PLL won't actually be able to drive bits from
2142          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2143          * need the check.
2144          */
2145         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2146                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2147                         assert_dsi_pll_enabled(dev_priv);
2148                 else
2149                         assert_pll_enabled(dev_priv, pipe);
2150         else {
2151                 if (crtc->config->has_pch_encoder) {
2152                         /* if driving the PCH, we need FDI enabled */
2153                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2154                         assert_fdi_tx_pll_enabled(dev_priv,
2155                                                   (enum pipe) cpu_transcoder);
2156                 }
2157                 /* FIXME: assert CPU port conditions for SNB+ */
2158         }
2159
2160         reg = PIPECONF(cpu_transcoder);
2161         val = I915_READ(reg);
2162         if (val & PIPECONF_ENABLE) {
2163                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2164                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2165                 return;
2166         }
2167
2168         I915_WRITE(reg, val | PIPECONF_ENABLE);
2169         POSTING_READ(reg);
2170 }
2171
2172 /**
2173  * intel_disable_pipe - disable a pipe, asserting requirements
2174  * @crtc: crtc whose pipes is to be disabled
2175  *
2176  * Disable the pipe of @crtc, making sure that various hardware
2177  * specific requirements are met, if applicable, e.g. plane
2178  * disabled, panel fitter off, etc.
2179  *
2180  * Will wait until the pipe has shut down before returning.
2181  */
2182 static void intel_disable_pipe(struct intel_crtc *crtc)
2183 {
2184         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2185         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2186         enum pipe pipe = crtc->pipe;
2187         int reg;
2188         u32 val;
2189
2190         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2191
2192         /*
2193          * Make sure planes won't keep trying to pump pixels to us,
2194          * or we might hang the display.
2195          */
2196         assert_planes_disabled(dev_priv, pipe);
2197         assert_cursor_disabled(dev_priv, pipe);
2198         assert_sprites_disabled(dev_priv, pipe);
2199
2200         reg = PIPECONF(cpu_transcoder);
2201         val = I915_READ(reg);
2202         if ((val & PIPECONF_ENABLE) == 0)
2203                 return;
2204
2205         /*
2206          * Double wide has implications for planes
2207          * so best keep it disabled when not needed.
2208          */
2209         if (crtc->config->double_wide)
2210                 val &= ~PIPECONF_DOUBLE_WIDE;
2211
2212         /* Don't disable pipe or pipe PLLs if needed */
2213         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2214             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2215                 val &= ~PIPECONF_ENABLE;
2216
2217         I915_WRITE(reg, val);
2218         if ((val & PIPECONF_ENABLE) == 0)
2219                 intel_wait_for_pipe_off(crtc);
2220 }
2221
2222 static bool need_vtd_wa(struct drm_device *dev)
2223 {
2224 #ifdef CONFIG_INTEL_IOMMU
2225         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2226                 return true;
2227 #endif
2228         return false;
2229 }
2230
2231 unsigned int
2232 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2233                   uint64_t fb_format_modifier)
2234 {
2235         unsigned int tile_height;
2236         uint32_t pixel_bytes;
2237
2238         switch (fb_format_modifier) {
2239         case DRM_FORMAT_MOD_NONE:
2240                 tile_height = 1;
2241                 break;
2242         case I915_FORMAT_MOD_X_TILED:
2243                 tile_height = IS_GEN2(dev) ? 16 : 8;
2244                 break;
2245         case I915_FORMAT_MOD_Y_TILED:
2246                 tile_height = 32;
2247                 break;
2248         case I915_FORMAT_MOD_Yf_TILED:
2249                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2250                 switch (pixel_bytes) {
2251                 default:
2252                 case 1:
2253                         tile_height = 64;
2254                         break;
2255                 case 2:
2256                 case 4:
2257                         tile_height = 32;
2258                         break;
2259                 case 8:
2260                         tile_height = 16;
2261                         break;
2262                 case 16:
2263                         WARN_ONCE(1,
2264                                   "128-bit pixels are not supported for display!");
2265                         tile_height = 16;
2266                         break;
2267                 }
2268                 break;
2269         default:
2270                 MISSING_CASE(fb_format_modifier);
2271                 tile_height = 1;
2272                 break;
2273         }
2274
2275         return tile_height;
2276 }
2277
2278 unsigned int
2279 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2280                       uint32_t pixel_format, uint64_t fb_format_modifier)
2281 {
2282         return ALIGN(height, intel_tile_height(dev, pixel_format,
2283                                                fb_format_modifier));
2284 }
2285
2286 static int
2287 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2288                         const struct drm_plane_state *plane_state)
2289 {
2290         struct intel_rotation_info *info = &view->rotation_info;
2291         unsigned int tile_height, tile_pitch;
2292
2293         *view = i915_ggtt_view_normal;
2294
2295         if (!plane_state)
2296                 return 0;
2297
2298         if (!intel_rotation_90_or_270(plane_state->rotation))
2299                 return 0;
2300
2301         *view = i915_ggtt_view_rotated;
2302
2303         info->height = fb->height;
2304         info->pixel_format = fb->pixel_format;
2305         info->pitch = fb->pitches[0];
2306         info->fb_modifier = fb->modifier[0];
2307
2308         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2309                                         fb->modifier[0]);
2310         tile_pitch = PAGE_SIZE / tile_height;
2311         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2312         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2313         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2314
2315         return 0;
2316 }
2317
2318 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2319 {
2320         if (INTEL_INFO(dev_priv)->gen >= 9)
2321                 return 256 * 1024;
2322         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2323                  IS_VALLEYVIEW(dev_priv))
2324                 return 128 * 1024;
2325         else if (INTEL_INFO(dev_priv)->gen >= 4)
2326                 return 4 * 1024;
2327         else
2328                 return 0;
2329 }
2330
2331 int
2332 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2333                            struct drm_framebuffer *fb,
2334                            const struct drm_plane_state *plane_state,
2335                            struct intel_engine_cs *pipelined,
2336                            struct drm_i915_gem_request **pipelined_request)
2337 {
2338         struct drm_device *dev = fb->dev;
2339         struct drm_i915_private *dev_priv = dev->dev_private;
2340         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2341         struct i915_ggtt_view view;
2342         u32 alignment;
2343         int ret;
2344
2345         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2346
2347         switch (fb->modifier[0]) {
2348         case DRM_FORMAT_MOD_NONE:
2349                 alignment = intel_linear_alignment(dev_priv);
2350                 break;
2351         case I915_FORMAT_MOD_X_TILED:
2352                 if (INTEL_INFO(dev)->gen >= 9)
2353                         alignment = 256 * 1024;
2354                 else {
2355                         /* pin() will align the object as required by fence */
2356                         alignment = 0;
2357                 }
2358                 break;
2359         case I915_FORMAT_MOD_Y_TILED:
2360         case I915_FORMAT_MOD_Yf_TILED:
2361                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2362                           "Y tiling bo slipped through, driver bug!\n"))
2363                         return -EINVAL;
2364                 alignment = 1 * 1024 * 1024;
2365                 break;
2366         default:
2367                 MISSING_CASE(fb->modifier[0]);
2368                 return -EINVAL;
2369         }
2370
2371         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2372         if (ret)
2373                 return ret;
2374
2375         /* Note that the w/a also requires 64 PTE of padding following the
2376          * bo. We currently fill all unused PTE with the shadow page and so
2377          * we should always have valid PTE following the scanout preventing
2378          * the VT-d warning.
2379          */
2380         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2381                 alignment = 256 * 1024;
2382
2383         /*
2384          * Global gtt pte registers are special registers which actually forward
2385          * writes to a chunk of system memory. Which means that there is no risk
2386          * that the register values disappear as soon as we call
2387          * intel_runtime_pm_put(), so it is correct to wrap only the
2388          * pin/unpin/fence and not more.
2389          */
2390         intel_runtime_pm_get(dev_priv);
2391
2392         dev_priv->mm.interruptible = false;
2393         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2394                                                    pipelined_request, &view);
2395         if (ret)
2396                 goto err_interruptible;
2397
2398         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2399          * fence, whereas 965+ only requires a fence if using
2400          * framebuffer compression.  For simplicity, we always install
2401          * a fence as the cost is not that onerous.
2402          */
2403         ret = i915_gem_object_get_fence(obj);
2404         if (ret)
2405                 goto err_unpin;
2406
2407         i915_gem_object_pin_fence(obj);
2408
2409         dev_priv->mm.interruptible = true;
2410         intel_runtime_pm_put(dev_priv);
2411         return 0;
2412
2413 err_unpin:
2414         i915_gem_object_unpin_from_display_plane(obj, &view);
2415 err_interruptible:
2416         dev_priv->mm.interruptible = true;
2417         intel_runtime_pm_put(dev_priv);
2418         return ret;
2419 }
2420
2421 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2422                                const struct drm_plane_state *plane_state)
2423 {
2424         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2425         struct i915_ggtt_view view;
2426         int ret;
2427
2428         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2429
2430         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2431         WARN_ONCE(ret, "Couldn't get view from plane state!");
2432
2433         i915_gem_object_unpin_fence(obj);
2434         i915_gem_object_unpin_from_display_plane(obj, &view);
2435 }
2436
2437 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2438  * is assumed to be a power-of-two. */
2439 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2440                                              int *x, int *y,
2441                                              unsigned int tiling_mode,
2442                                              unsigned int cpp,
2443                                              unsigned int pitch)
2444 {
2445         if (tiling_mode != I915_TILING_NONE) {
2446                 unsigned int tile_rows, tiles;
2447
2448                 tile_rows = *y / 8;
2449                 *y %= 8;
2450
2451                 tiles = *x / (512/cpp);
2452                 *x %= 512/cpp;
2453
2454                 return tile_rows * pitch * 8 + tiles * 4096;
2455         } else {
2456                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2457                 unsigned int offset;
2458
2459                 offset = *y * pitch + *x * cpp;
2460                 *y = (offset & alignment) / pitch;
2461                 *x = ((offset & alignment) - *y * pitch) / cpp;
2462                 return offset & ~alignment;
2463         }
2464 }
2465
2466 static int i9xx_format_to_fourcc(int format)
2467 {
2468         switch (format) {
2469         case DISPPLANE_8BPP:
2470                 return DRM_FORMAT_C8;
2471         case DISPPLANE_BGRX555:
2472                 return DRM_FORMAT_XRGB1555;
2473         case DISPPLANE_BGRX565:
2474                 return DRM_FORMAT_RGB565;
2475         default:
2476         case DISPPLANE_BGRX888:
2477                 return DRM_FORMAT_XRGB8888;
2478         case DISPPLANE_RGBX888:
2479                 return DRM_FORMAT_XBGR8888;
2480         case DISPPLANE_BGRX101010:
2481                 return DRM_FORMAT_XRGB2101010;
2482         case DISPPLANE_RGBX101010:
2483                 return DRM_FORMAT_XBGR2101010;
2484         }
2485 }
2486
2487 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2488 {
2489         switch (format) {
2490         case PLANE_CTL_FORMAT_RGB_565:
2491                 return DRM_FORMAT_RGB565;
2492         default:
2493         case PLANE_CTL_FORMAT_XRGB_8888:
2494                 if (rgb_order) {
2495                         if (alpha)
2496                                 return DRM_FORMAT_ABGR8888;
2497                         else
2498                                 return DRM_FORMAT_XBGR8888;
2499                 } else {
2500                         if (alpha)
2501                                 return DRM_FORMAT_ARGB8888;
2502                         else
2503                                 return DRM_FORMAT_XRGB8888;
2504                 }
2505         case PLANE_CTL_FORMAT_XRGB_2101010:
2506                 if (rgb_order)
2507                         return DRM_FORMAT_XBGR2101010;
2508                 else
2509                         return DRM_FORMAT_XRGB2101010;
2510         }
2511 }
2512
2513 static bool
2514 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2515                               struct intel_initial_plane_config *plane_config)
2516 {
2517         struct drm_device *dev = crtc->base.dev;
2518         struct drm_i915_gem_object *obj = NULL;
2519         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2520         struct drm_framebuffer *fb = &plane_config->fb->base;
2521         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2522         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2523                                     PAGE_SIZE);
2524
2525         size_aligned -= base_aligned;
2526
2527         if (plane_config->size == 0)
2528                 return false;
2529
2530         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2531                                                              base_aligned,
2532                                                              base_aligned,
2533                                                              size_aligned);
2534         if (!obj)
2535                 return false;
2536
2537         obj->tiling_mode = plane_config->tiling;
2538         if (obj->tiling_mode == I915_TILING_X)
2539                 obj->stride = fb->pitches[0];
2540
2541         mode_cmd.pixel_format = fb->pixel_format;
2542         mode_cmd.width = fb->width;
2543         mode_cmd.height = fb->height;
2544         mode_cmd.pitches[0] = fb->pitches[0];
2545         mode_cmd.modifier[0] = fb->modifier[0];
2546         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2547
2548         mutex_lock(&dev->struct_mutex);
2549         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2550                                    &mode_cmd, obj)) {
2551                 DRM_DEBUG_KMS("intel fb init failed\n");
2552                 goto out_unref_obj;
2553         }
2554         mutex_unlock(&dev->struct_mutex);
2555
2556         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2557         return true;
2558
2559 out_unref_obj:
2560         drm_gem_object_unreference(&obj->base);
2561         mutex_unlock(&dev->struct_mutex);
2562         return false;
2563 }
2564
2565 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2566 static void
2567 update_state_fb(struct drm_plane *plane)
2568 {
2569         if (plane->fb == plane->state->fb)
2570                 return;
2571
2572         if (plane->state->fb)
2573                 drm_framebuffer_unreference(plane->state->fb);
2574         plane->state->fb = plane->fb;
2575         if (plane->state->fb)
2576                 drm_framebuffer_reference(plane->state->fb);
2577 }
2578
2579 static void
2580 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2581                              struct intel_initial_plane_config *plane_config)
2582 {
2583         struct drm_device *dev = intel_crtc->base.dev;
2584         struct drm_i915_private *dev_priv = dev->dev_private;
2585         struct drm_crtc *c;
2586         struct intel_crtc *i;
2587         struct drm_i915_gem_object *obj;
2588         struct drm_plane *primary = intel_crtc->base.primary;
2589         struct drm_framebuffer *fb;
2590
2591         if (!plane_config->fb)
2592                 return;
2593
2594         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2595                 fb = &plane_config->fb->base;
2596                 goto valid_fb;
2597         }
2598
2599         kfree(plane_config->fb);
2600
2601         /*
2602          * Failed to alloc the obj, check to see if we should share
2603          * an fb with another CRTC instead
2604          */
2605         for_each_crtc(dev, c) {
2606                 i = to_intel_crtc(c);
2607
2608                 if (c == &intel_crtc->base)
2609                         continue;
2610
2611                 if (!i->active)
2612                         continue;
2613
2614                 fb = c->primary->fb;
2615                 if (!fb)
2616                         continue;
2617
2618                 obj = intel_fb_obj(fb);
2619                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2620                         drm_framebuffer_reference(fb);
2621                         goto valid_fb;
2622                 }
2623         }
2624
2625         return;
2626
2627 valid_fb:
2628         obj = intel_fb_obj(fb);
2629         if (obj->tiling_mode != I915_TILING_NONE)
2630                 dev_priv->preserve_bios_swizzle = true;
2631
2632         primary->fb = fb;
2633         primary->crtc = primary->state->crtc = &intel_crtc->base;
2634         update_state_fb(primary);
2635         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2636         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2637 }
2638
2639 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2640                                       struct drm_framebuffer *fb,
2641                                       int x, int y)
2642 {
2643         struct drm_device *dev = crtc->dev;
2644         struct drm_i915_private *dev_priv = dev->dev_private;
2645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2646         struct drm_plane *primary = crtc->primary;
2647         bool visible = to_intel_plane_state(primary->state)->visible;
2648         struct drm_i915_gem_object *obj;
2649         int plane = intel_crtc->plane;
2650         unsigned long linear_offset;
2651         u32 dspcntr;
2652         u32 reg = DSPCNTR(plane);
2653         int pixel_size;
2654
2655         if (!visible || !fb) {
2656                 I915_WRITE(reg, 0);
2657                 if (INTEL_INFO(dev)->gen >= 4)
2658                         I915_WRITE(DSPSURF(plane), 0);
2659                 else
2660                         I915_WRITE(DSPADDR(plane), 0);
2661                 POSTING_READ(reg);
2662                 return;
2663         }
2664
2665         obj = intel_fb_obj(fb);
2666         if (WARN_ON(obj == NULL))
2667                 return;
2668
2669         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2670
2671         dspcntr = DISPPLANE_GAMMA_ENABLE;
2672
2673         dspcntr |= DISPLAY_PLANE_ENABLE;
2674
2675         if (INTEL_INFO(dev)->gen < 4) {
2676                 if (intel_crtc->pipe == PIPE_B)
2677                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2678
2679                 /* pipesrc and dspsize control the size that is scaled from,
2680                  * which should always be the user's requested size.
2681                  */
2682                 I915_WRITE(DSPSIZE(plane),
2683                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2684                            (intel_crtc->config->pipe_src_w - 1));
2685                 I915_WRITE(DSPPOS(plane), 0);
2686         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2687                 I915_WRITE(PRIMSIZE(plane),
2688                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2689                            (intel_crtc->config->pipe_src_w - 1));
2690                 I915_WRITE(PRIMPOS(plane), 0);
2691                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2692         }
2693
2694         switch (fb->pixel_format) {
2695         case DRM_FORMAT_C8:
2696                 dspcntr |= DISPPLANE_8BPP;
2697                 break;
2698         case DRM_FORMAT_XRGB1555:
2699                 dspcntr |= DISPPLANE_BGRX555;
2700                 break;
2701         case DRM_FORMAT_RGB565:
2702                 dspcntr |= DISPPLANE_BGRX565;
2703                 break;
2704         case DRM_FORMAT_XRGB8888:
2705                 dspcntr |= DISPPLANE_BGRX888;
2706                 break;
2707         case DRM_FORMAT_XBGR8888:
2708                 dspcntr |= DISPPLANE_RGBX888;
2709                 break;
2710         case DRM_FORMAT_XRGB2101010:
2711                 dspcntr |= DISPPLANE_BGRX101010;
2712                 break;
2713         case DRM_FORMAT_XBGR2101010:
2714                 dspcntr |= DISPPLANE_RGBX101010;
2715                 break;
2716         default:
2717                 BUG();
2718         }
2719
2720         if (INTEL_INFO(dev)->gen >= 4 &&
2721             obj->tiling_mode != I915_TILING_NONE)
2722                 dspcntr |= DISPPLANE_TILED;
2723
2724         if (IS_G4X(dev))
2725                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2726
2727         linear_offset = y * fb->pitches[0] + x * pixel_size;
2728
2729         if (INTEL_INFO(dev)->gen >= 4) {
2730                 intel_crtc->dspaddr_offset =
2731                         intel_gen4_compute_page_offset(dev_priv,
2732                                                        &x, &y, obj->tiling_mode,
2733                                                        pixel_size,
2734                                                        fb->pitches[0]);
2735                 linear_offset -= intel_crtc->dspaddr_offset;
2736         } else {
2737                 intel_crtc->dspaddr_offset = linear_offset;
2738         }
2739
2740         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2741                 dspcntr |= DISPPLANE_ROTATE_180;
2742
2743                 x += (intel_crtc->config->pipe_src_w - 1);
2744                 y += (intel_crtc->config->pipe_src_h - 1);
2745
2746                 /* Finding the last pixel of the last line of the display
2747                 data and adding to linear_offset*/
2748                 linear_offset +=
2749                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2750                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2751         }
2752
2753         I915_WRITE(reg, dspcntr);
2754
2755         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2756         if (INTEL_INFO(dev)->gen >= 4) {
2757                 I915_WRITE(DSPSURF(plane),
2758                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2759                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2760                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2761         } else
2762                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2763         POSTING_READ(reg);
2764 }
2765
2766 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2767                                           struct drm_framebuffer *fb,
2768                                           int x, int y)
2769 {
2770         struct drm_device *dev = crtc->dev;
2771         struct drm_i915_private *dev_priv = dev->dev_private;
2772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773         struct drm_plane *primary = crtc->primary;
2774         bool visible = to_intel_plane_state(primary->state)->visible;
2775         struct drm_i915_gem_object *obj;
2776         int plane = intel_crtc->plane;
2777         unsigned long linear_offset;
2778         u32 dspcntr;
2779         u32 reg = DSPCNTR(plane);
2780         int pixel_size;
2781
2782         if (!visible || !fb) {
2783                 I915_WRITE(reg, 0);
2784                 I915_WRITE(DSPSURF(plane), 0);
2785                 POSTING_READ(reg);
2786                 return;
2787         }
2788
2789         obj = intel_fb_obj(fb);
2790         if (WARN_ON(obj == NULL))
2791                 return;
2792
2793         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2794
2795         dspcntr = DISPPLANE_GAMMA_ENABLE;
2796
2797         dspcntr |= DISPLAY_PLANE_ENABLE;
2798
2799         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2800                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2801
2802         switch (fb->pixel_format) {
2803         case DRM_FORMAT_C8:
2804                 dspcntr |= DISPPLANE_8BPP;
2805                 break;
2806         case DRM_FORMAT_RGB565:
2807                 dspcntr |= DISPPLANE_BGRX565;
2808                 break;
2809         case DRM_FORMAT_XRGB8888:
2810                 dspcntr |= DISPPLANE_BGRX888;
2811                 break;
2812         case DRM_FORMAT_XBGR8888:
2813                 dspcntr |= DISPPLANE_RGBX888;
2814                 break;
2815         case DRM_FORMAT_XRGB2101010:
2816                 dspcntr |= DISPPLANE_BGRX101010;
2817                 break;
2818         case DRM_FORMAT_XBGR2101010:
2819                 dspcntr |= DISPPLANE_RGBX101010;
2820                 break;
2821         default:
2822                 BUG();
2823         }
2824
2825         if (obj->tiling_mode != I915_TILING_NONE)
2826                 dspcntr |= DISPPLANE_TILED;
2827
2828         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2829                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2830
2831         linear_offset = y * fb->pitches[0] + x * pixel_size;
2832         intel_crtc->dspaddr_offset =
2833                 intel_gen4_compute_page_offset(dev_priv,
2834                                                &x, &y, obj->tiling_mode,
2835                                                pixel_size,
2836                                                fb->pitches[0]);
2837         linear_offset -= intel_crtc->dspaddr_offset;
2838         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2839                 dspcntr |= DISPPLANE_ROTATE_180;
2840
2841                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2842                         x += (intel_crtc->config->pipe_src_w - 1);
2843                         y += (intel_crtc->config->pipe_src_h - 1);
2844
2845                         /* Finding the last pixel of the last line of the display
2846                         data and adding to linear_offset*/
2847                         linear_offset +=
2848                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2849                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2850                 }
2851         }
2852
2853         I915_WRITE(reg, dspcntr);
2854
2855         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2856         I915_WRITE(DSPSURF(plane),
2857                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2858         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2859                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2860         } else {
2861                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2862                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2863         }
2864         POSTING_READ(reg);
2865 }
2866
2867 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2868                               uint32_t pixel_format)
2869 {
2870         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2871
2872         /*
2873          * The stride is either expressed as a multiple of 64 bytes
2874          * chunks for linear buffers or in number of tiles for tiled
2875          * buffers.
2876          */
2877         switch (fb_modifier) {
2878         case DRM_FORMAT_MOD_NONE:
2879                 return 64;
2880         case I915_FORMAT_MOD_X_TILED:
2881                 if (INTEL_INFO(dev)->gen == 2)
2882                         return 128;
2883                 return 512;
2884         case I915_FORMAT_MOD_Y_TILED:
2885                 /* No need to check for old gens and Y tiling since this is
2886                  * about the display engine and those will be blocked before
2887                  * we get here.
2888                  */
2889                 return 128;
2890         case I915_FORMAT_MOD_Yf_TILED:
2891                 if (bits_per_pixel == 8)
2892                         return 64;
2893                 else
2894                         return 128;
2895         default:
2896                 MISSING_CASE(fb_modifier);
2897                 return 64;
2898         }
2899 }
2900
2901 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2902                                      struct drm_i915_gem_object *obj)
2903 {
2904         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2905
2906         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2907                 view = &i915_ggtt_view_rotated;
2908
2909         return i915_gem_obj_ggtt_offset_view(obj, view);
2910 }
2911
2912 /*
2913  * This function detaches (aka. unbinds) unused scalers in hardware
2914  */
2915 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2916 {
2917         struct drm_device *dev;
2918         struct drm_i915_private *dev_priv;
2919         struct intel_crtc_scaler_state *scaler_state;
2920         int i;
2921
2922         dev = intel_crtc->base.dev;
2923         dev_priv = dev->dev_private;
2924         scaler_state = &intel_crtc->config->scaler_state;
2925
2926         /* loop through and disable scalers that aren't in use */
2927         for (i = 0; i < intel_crtc->num_scalers; i++) {
2928                 if (!scaler_state->scalers[i].in_use) {
2929                         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2930                         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2931                         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2932                         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2933                                 intel_crtc->base.base.id, intel_crtc->pipe, i);
2934                 }
2935         }
2936 }
2937
2938 u32 skl_plane_ctl_format(uint32_t pixel_format)
2939 {
2940         switch (pixel_format) {
2941         case DRM_FORMAT_C8:
2942                 return PLANE_CTL_FORMAT_INDEXED;
2943         case DRM_FORMAT_RGB565:
2944                 return PLANE_CTL_FORMAT_RGB_565;
2945         case DRM_FORMAT_XBGR8888:
2946                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2947         case DRM_FORMAT_XRGB8888:
2948                 return PLANE_CTL_FORMAT_XRGB_8888;
2949         /*
2950          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2951          * to be already pre-multiplied. We need to add a knob (or a different
2952          * DRM_FORMAT) for user-space to configure that.
2953          */
2954         case DRM_FORMAT_ABGR8888:
2955                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2956                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2957         case DRM_FORMAT_ARGB8888:
2958                 return PLANE_CTL_FORMAT_XRGB_8888 |
2959                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2960         case DRM_FORMAT_XRGB2101010:
2961                 return PLANE_CTL_FORMAT_XRGB_2101010;
2962         case DRM_FORMAT_XBGR2101010:
2963                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2964         case DRM_FORMAT_YUYV:
2965                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2966         case DRM_FORMAT_YVYU:
2967                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2968         case DRM_FORMAT_UYVY:
2969                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2970         case DRM_FORMAT_VYUY:
2971                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2972         default:
2973                 MISSING_CASE(pixel_format);
2974         }
2975
2976         return 0;
2977 }
2978
2979 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2980 {
2981         switch (fb_modifier) {
2982         case DRM_FORMAT_MOD_NONE:
2983                 break;
2984         case I915_FORMAT_MOD_X_TILED:
2985                 return PLANE_CTL_TILED_X;
2986         case I915_FORMAT_MOD_Y_TILED:
2987                 return PLANE_CTL_TILED_Y;
2988         case I915_FORMAT_MOD_Yf_TILED:
2989                 return PLANE_CTL_TILED_YF;
2990         default:
2991                 MISSING_CASE(fb_modifier);
2992         }
2993
2994         return 0;
2995 }
2996
2997 u32 skl_plane_ctl_rotation(unsigned int rotation)
2998 {
2999         switch (rotation) {
3000         case BIT(DRM_ROTATE_0):
3001                 break;
3002         /*
3003          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3004          * while i915 HW rotation is clockwise, thats why this swapping.
3005          */
3006         case BIT(DRM_ROTATE_90):
3007                 return PLANE_CTL_ROTATE_270;
3008         case BIT(DRM_ROTATE_180):
3009                 return PLANE_CTL_ROTATE_180;
3010         case BIT(DRM_ROTATE_270):
3011                 return PLANE_CTL_ROTATE_90;
3012         default:
3013                 MISSING_CASE(rotation);
3014         }
3015
3016         return 0;
3017 }
3018
3019 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3020                                          struct drm_framebuffer *fb,
3021                                          int x, int y)
3022 {
3023         struct drm_device *dev = crtc->dev;
3024         struct drm_i915_private *dev_priv = dev->dev_private;
3025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3026         struct drm_plane *plane = crtc->primary;
3027         bool visible = to_intel_plane_state(plane->state)->visible;
3028         struct drm_i915_gem_object *obj;
3029         int pipe = intel_crtc->pipe;
3030         u32 plane_ctl, stride_div, stride;
3031         u32 tile_height, plane_offset, plane_size;
3032         unsigned int rotation;
3033         int x_offset, y_offset;
3034         unsigned long surf_addr;
3035         struct intel_crtc_state *crtc_state = intel_crtc->config;
3036         struct intel_plane_state *plane_state;
3037         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3038         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3039         int scaler_id = -1;
3040
3041         plane_state = to_intel_plane_state(plane->state);
3042
3043         if (!visible || !fb) {
3044                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3045                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3046                 POSTING_READ(PLANE_CTL(pipe, 0));
3047                 return;
3048         }
3049
3050         plane_ctl = PLANE_CTL_ENABLE |
3051                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3052                     PLANE_CTL_PIPE_CSC_ENABLE;
3053
3054         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3055         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3056         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3057
3058         rotation = plane->state->rotation;
3059         plane_ctl |= skl_plane_ctl_rotation(rotation);
3060
3061         obj = intel_fb_obj(fb);
3062         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3063                                                fb->pixel_format);
3064         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3065
3066         /*
3067          * FIXME: intel_plane_state->src, dst aren't set when transitional
3068          * update_plane helpers are called from legacy paths.
3069          * Once full atomic crtc is available, below check can be avoided.
3070          */
3071         if (drm_rect_width(&plane_state->src)) {
3072                 scaler_id = plane_state->scaler_id;
3073                 src_x = plane_state->src.x1 >> 16;
3074                 src_y = plane_state->src.y1 >> 16;
3075                 src_w = drm_rect_width(&plane_state->src) >> 16;
3076                 src_h = drm_rect_height(&plane_state->src) >> 16;
3077                 dst_x = plane_state->dst.x1;
3078                 dst_y = plane_state->dst.y1;
3079                 dst_w = drm_rect_width(&plane_state->dst);
3080                 dst_h = drm_rect_height(&plane_state->dst);
3081
3082                 WARN_ON(x != src_x || y != src_y);
3083         } else {
3084                 src_w = intel_crtc->config->pipe_src_w;
3085                 src_h = intel_crtc->config->pipe_src_h;
3086         }
3087
3088         if (intel_rotation_90_or_270(rotation)) {
3089                 /* stride = Surface height in tiles */
3090                 tile_height = intel_tile_height(dev, fb->pixel_format,
3091                                                 fb->modifier[0]);
3092                 stride = DIV_ROUND_UP(fb->height, tile_height);
3093                 x_offset = stride * tile_height - y - src_h;
3094                 y_offset = x;
3095                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3096         } else {
3097                 stride = fb->pitches[0] / stride_div;
3098                 x_offset = x;
3099                 y_offset = y;
3100                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3101         }
3102         plane_offset = y_offset << 16 | x_offset;
3103
3104         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3105         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3106         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3107         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3108
3109         if (scaler_id >= 0) {
3110                 uint32_t ps_ctrl = 0;
3111
3112                 WARN_ON(!dst_w || !dst_h);
3113                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3114                         crtc_state->scaler_state.scalers[scaler_id].mode;
3115                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3116                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3117                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3118                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3119                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3120         } else {
3121                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3122         }
3123
3124         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3125
3126         POSTING_READ(PLANE_SURF(pipe, 0));
3127 }
3128
3129 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3130 static int
3131 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3132                            int x, int y, enum mode_set_atomic state)
3133 {
3134         struct drm_device *dev = crtc->dev;
3135         struct drm_i915_private *dev_priv = dev->dev_private;
3136
3137         if (dev_priv->display.disable_fbc)
3138                 dev_priv->display.disable_fbc(dev);
3139
3140         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3141
3142         return 0;
3143 }
3144
3145 static void intel_complete_page_flips(struct drm_device *dev)
3146 {
3147         struct drm_crtc *crtc;
3148
3149         for_each_crtc(dev, crtc) {
3150                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3151                 enum plane plane = intel_crtc->plane;
3152
3153                 intel_prepare_page_flip(dev, plane);
3154                 intel_finish_page_flip_plane(dev, plane);
3155         }
3156 }
3157
3158 static void intel_update_primary_planes(struct drm_device *dev)
3159 {
3160         struct drm_i915_private *dev_priv = dev->dev_private;
3161         struct drm_crtc *crtc;
3162
3163         for_each_crtc(dev, crtc) {
3164                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3165
3166                 drm_modeset_lock(&crtc->mutex, NULL);
3167                 /*
3168                  * FIXME: Once we have proper support for primary planes (and
3169                  * disabling them without disabling the entire crtc) allow again
3170                  * a NULL crtc->primary->fb.
3171                  */
3172                 if (intel_crtc->active && crtc->primary->fb)
3173                         dev_priv->display.update_primary_plane(crtc,
3174                                                                crtc->primary->fb,
3175                                                                crtc->x,
3176                                                                crtc->y);
3177                 drm_modeset_unlock(&crtc->mutex);
3178         }
3179 }
3180
3181 void intel_prepare_reset(struct drm_device *dev)
3182 {
3183         /* no reset support for gen2 */
3184         if (IS_GEN2(dev))
3185                 return;
3186
3187         /* reset doesn't touch the display */
3188         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3189                 return;
3190
3191         drm_modeset_lock_all(dev);
3192         /*
3193          * Disabling the crtcs gracefully seems nicer. Also the
3194          * g33 docs say we should at least disable all the planes.
3195          */
3196         intel_display_suspend(dev);
3197 }
3198
3199 void intel_finish_reset(struct drm_device *dev)
3200 {
3201         struct drm_i915_private *dev_priv = to_i915(dev);
3202
3203         /*
3204          * Flips in the rings will be nuked by the reset,
3205          * so complete all pending flips so that user space
3206          * will get its events and not get stuck.
3207          */
3208         intel_complete_page_flips(dev);
3209
3210         /* no reset support for gen2 */
3211         if (IS_GEN2(dev))
3212                 return;
3213
3214         /* reset doesn't touch the display */
3215         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3216                 /*
3217                  * Flips in the rings have been nuked by the reset,
3218                  * so update the base address of all primary
3219                  * planes to the the last fb to make sure we're
3220                  * showing the correct fb after a reset.
3221                  */
3222                 intel_update_primary_planes(dev);
3223                 return;
3224         }
3225
3226         /*
3227          * The display has been reset as well,
3228          * so need a full re-initialization.
3229          */
3230         intel_runtime_pm_disable_interrupts(dev_priv);
3231         intel_runtime_pm_enable_interrupts(dev_priv);
3232
3233         intel_modeset_init_hw(dev);
3234
3235         spin_lock_irq(&dev_priv->irq_lock);
3236         if (dev_priv->display.hpd_irq_setup)
3237                 dev_priv->display.hpd_irq_setup(dev);
3238         spin_unlock_irq(&dev_priv->irq_lock);
3239
3240         intel_modeset_setup_hw_state(dev, true);
3241
3242         intel_hpd_init(dev_priv);
3243
3244         drm_modeset_unlock_all(dev);
3245 }
3246
3247 static void
3248 intel_finish_fb(struct drm_framebuffer *old_fb)
3249 {
3250         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3251         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3252         bool was_interruptible = dev_priv->mm.interruptible;
3253         int ret;
3254
3255         /* Big Hammer, we also need to ensure that any pending
3256          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3257          * current scanout is retired before unpinning the old
3258          * framebuffer. Note that we rely on userspace rendering
3259          * into the buffer attached to the pipe they are waiting
3260          * on. If not, userspace generates a GPU hang with IPEHR
3261          * point to the MI_WAIT_FOR_EVENT.
3262          *
3263          * This should only fail upon a hung GPU, in which case we
3264          * can safely continue.
3265          */
3266         dev_priv->mm.interruptible = false;
3267         ret = i915_gem_object_wait_rendering(obj, true);
3268         dev_priv->mm.interruptible = was_interruptible;
3269
3270         WARN_ON(ret);
3271 }
3272
3273 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3274 {
3275         struct drm_device *dev = crtc->dev;
3276         struct drm_i915_private *dev_priv = dev->dev_private;
3277         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3278         bool pending;
3279
3280         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3281             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3282                 return false;
3283
3284         spin_lock_irq(&dev->event_lock);
3285         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3286         spin_unlock_irq(&dev->event_lock);
3287
3288         return pending;
3289 }
3290
3291 static void intel_update_pipe_size(struct intel_crtc *crtc)
3292 {
3293         struct drm_device *dev = crtc->base.dev;
3294         struct drm_i915_private *dev_priv = dev->dev_private;
3295         const struct drm_display_mode *adjusted_mode;
3296
3297         if (!i915.fastboot)
3298                 return;
3299
3300         /*
3301          * Update pipe size and adjust fitter if needed: the reason for this is
3302          * that in compute_mode_changes we check the native mode (not the pfit
3303          * mode) to see if we can flip rather than do a full mode set. In the
3304          * fastboot case, we'll flip, but if we don't update the pipesrc and
3305          * pfit state, we'll end up with a big fb scanned out into the wrong
3306          * sized surface.
3307          *
3308          * To fix this properly, we need to hoist the checks up into
3309          * compute_mode_changes (or above), check the actual pfit state and
3310          * whether the platform allows pfit disable with pipe active, and only
3311          * then update the pipesrc and pfit state, even on the flip path.
3312          */
3313
3314         adjusted_mode = &crtc->config->base.adjusted_mode;
3315
3316         I915_WRITE(PIPESRC(crtc->pipe),
3317                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3318                    (adjusted_mode->crtc_vdisplay - 1));
3319         if (!crtc->config->pch_pfit.enabled &&
3320             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3321              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3322                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3323                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3324                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3325         }
3326         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3327         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3328 }
3329
3330 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3331 {
3332         struct drm_device *dev = crtc->dev;
3333         struct drm_i915_private *dev_priv = dev->dev_private;
3334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3335         int pipe = intel_crtc->pipe;
3336         u32 reg, temp;
3337
3338         /* enable normal train */
3339         reg = FDI_TX_CTL(pipe);
3340         temp = I915_READ(reg);
3341         if (IS_IVYBRIDGE(dev)) {
3342                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3343                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3344         } else {
3345                 temp &= ~FDI_LINK_TRAIN_NONE;
3346                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3347         }
3348         I915_WRITE(reg, temp);
3349
3350         reg = FDI_RX_CTL(pipe);
3351         temp = I915_READ(reg);
3352         if (HAS_PCH_CPT(dev)) {
3353                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3354                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3355         } else {
3356                 temp &= ~FDI_LINK_TRAIN_NONE;
3357                 temp |= FDI_LINK_TRAIN_NONE;
3358         }
3359         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3360
3361         /* wait one idle pattern time */
3362         POSTING_READ(reg);
3363         udelay(1000);
3364
3365         /* IVB wants error correction enabled */
3366         if (IS_IVYBRIDGE(dev))
3367                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3368                            FDI_FE_ERRC_ENABLE);
3369 }
3370
3371 /* The FDI link training functions for ILK/Ibexpeak. */
3372 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3373 {
3374         struct drm_device *dev = crtc->dev;
3375         struct drm_i915_private *dev_priv = dev->dev_private;
3376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3377         int pipe = intel_crtc->pipe;
3378         u32 reg, temp, tries;
3379
3380         /* FDI needs bits from pipe first */
3381         assert_pipe_enabled(dev_priv, pipe);
3382
3383         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3384            for train result */
3385         reg = FDI_RX_IMR(pipe);
3386         temp = I915_READ(reg);
3387         temp &= ~FDI_RX_SYMBOL_LOCK;
3388         temp &= ~FDI_RX_BIT_LOCK;
3389         I915_WRITE(reg, temp);
3390         I915_READ(reg);
3391         udelay(150);
3392
3393         /* enable CPU FDI TX and PCH FDI RX */
3394         reg = FDI_TX_CTL(pipe);
3395         temp = I915_READ(reg);
3396         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3397         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3398         temp &= ~FDI_LINK_TRAIN_NONE;
3399         temp |= FDI_LINK_TRAIN_PATTERN_1;
3400         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3401
3402         reg = FDI_RX_CTL(pipe);
3403         temp = I915_READ(reg);
3404         temp &= ~FDI_LINK_TRAIN_NONE;
3405         temp |= FDI_LINK_TRAIN_PATTERN_1;
3406         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3407
3408         POSTING_READ(reg);
3409         udelay(150);
3410
3411         /* Ironlake workaround, enable clock pointer after FDI enable*/
3412         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3413         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3414                    FDI_RX_PHASE_SYNC_POINTER_EN);
3415
3416         reg = FDI_RX_IIR(pipe);
3417         for (tries = 0; tries < 5; tries++) {
3418                 temp = I915_READ(reg);
3419                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3420
3421                 if ((temp & FDI_RX_BIT_LOCK)) {
3422                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3423                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3424                         break;
3425                 }
3426         }
3427         if (tries == 5)
3428                 DRM_ERROR("FDI train 1 fail!\n");
3429
3430         /* Train 2 */
3431         reg = FDI_TX_CTL(pipe);
3432         temp = I915_READ(reg);
3433         temp &= ~FDI_LINK_TRAIN_NONE;
3434         temp |= FDI_LINK_TRAIN_PATTERN_2;
3435         I915_WRITE(reg, temp);
3436
3437         reg = FDI_RX_CTL(pipe);
3438         temp = I915_READ(reg);
3439         temp &= ~FDI_LINK_TRAIN_NONE;
3440         temp |= FDI_LINK_TRAIN_PATTERN_2;
3441         I915_WRITE(reg, temp);
3442
3443         POSTING_READ(reg);
3444         udelay(150);
3445
3446         reg = FDI_RX_IIR(pipe);
3447         for (tries = 0; tries < 5; tries++) {
3448                 temp = I915_READ(reg);
3449                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3450
3451                 if (temp & FDI_RX_SYMBOL_LOCK) {
3452                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3453                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3454                         break;
3455                 }
3456         }
3457         if (tries == 5)
3458                 DRM_ERROR("FDI train 2 fail!\n");
3459
3460         DRM_DEBUG_KMS("FDI train done\n");
3461
3462 }
3463
3464 static const int snb_b_fdi_train_param[] = {
3465         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3466         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3467         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3468         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3469 };
3470
3471 /* The FDI link training functions for SNB/Cougarpoint. */
3472 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3473 {
3474         struct drm_device *dev = crtc->dev;
3475         struct drm_i915_private *dev_priv = dev->dev_private;
3476         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3477         int pipe = intel_crtc->pipe;
3478         u32 reg, temp, i, retry;
3479
3480         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3481            for train result */
3482         reg = FDI_RX_IMR(pipe);
3483         temp = I915_READ(reg);
3484         temp &= ~FDI_RX_SYMBOL_LOCK;
3485         temp &= ~FDI_RX_BIT_LOCK;
3486         I915_WRITE(reg, temp);
3487
3488         POSTING_READ(reg);
3489         udelay(150);
3490
3491         /* enable CPU FDI TX and PCH FDI RX */
3492         reg = FDI_TX_CTL(pipe);
3493         temp = I915_READ(reg);
3494         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3495         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3496         temp &= ~FDI_LINK_TRAIN_NONE;
3497         temp |= FDI_LINK_TRAIN_PATTERN_1;
3498         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3499         /* SNB-B */
3500         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3501         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3502
3503         I915_WRITE(FDI_RX_MISC(pipe),
3504                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3505
3506         reg = FDI_RX_CTL(pipe);
3507         temp = I915_READ(reg);
3508         if (HAS_PCH_CPT(dev)) {
3509                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3510                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3511         } else {
3512                 temp &= ~FDI_LINK_TRAIN_NONE;
3513                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3514         }
3515         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3516
3517         POSTING_READ(reg);
3518         udelay(150);
3519
3520         for (i = 0; i < 4; i++) {
3521                 reg = FDI_TX_CTL(pipe);
3522                 temp = I915_READ(reg);
3523                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3524                 temp |= snb_b_fdi_train_param[i];
3525                 I915_WRITE(reg, temp);
3526
3527                 POSTING_READ(reg);
3528                 udelay(500);
3529
3530                 for (retry = 0; retry < 5; retry++) {
3531                         reg = FDI_RX_IIR(pipe);
3532                         temp = I915_READ(reg);
3533                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3534                         if (temp & FDI_RX_BIT_LOCK) {
3535                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3536                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3537                                 break;
3538                         }
3539                         udelay(50);
3540                 }
3541                 if (retry < 5)
3542                         break;
3543         }
3544         if (i == 4)
3545                 DRM_ERROR("FDI train 1 fail!\n");
3546
3547         /* Train 2 */
3548         reg = FDI_TX_CTL(pipe);
3549         temp = I915_READ(reg);
3550         temp &= ~FDI_LINK_TRAIN_NONE;
3551         temp |= FDI_LINK_TRAIN_PATTERN_2;
3552         if (IS_GEN6(dev)) {
3553                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3554                 /* SNB-B */
3555                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3556         }
3557         I915_WRITE(reg, temp);
3558
3559         reg = FDI_RX_CTL(pipe);
3560         temp = I915_READ(reg);
3561         if (HAS_PCH_CPT(dev)) {
3562                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3563                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3564         } else {
3565                 temp &= ~FDI_LINK_TRAIN_NONE;
3566                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3567         }
3568         I915_WRITE(reg, temp);
3569
3570         POSTING_READ(reg);
3571         udelay(150);
3572
3573         for (i = 0; i < 4; i++) {
3574                 reg = FDI_TX_CTL(pipe);
3575                 temp = I915_READ(reg);
3576                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3577                 temp |= snb_b_fdi_train_param[i];
3578                 I915_WRITE(reg, temp);
3579
3580                 POSTING_READ(reg);
3581                 udelay(500);
3582
3583                 for (retry = 0; retry < 5; retry++) {
3584                         reg = FDI_RX_IIR(pipe);
3585                         temp = I915_READ(reg);
3586                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3587                         if (temp & FDI_RX_SYMBOL_LOCK) {
3588                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3589                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3590                                 break;
3591                         }
3592                         udelay(50);
3593                 }
3594                 if (retry < 5)
3595                         break;
3596         }
3597         if (i == 4)
3598                 DRM_ERROR("FDI train 2 fail!\n");
3599
3600         DRM_DEBUG_KMS("FDI train done.\n");
3601 }
3602
3603 /* Manual link training for Ivy Bridge A0 parts */
3604 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3605 {
3606         struct drm_device *dev = crtc->dev;
3607         struct drm_i915_private *dev_priv = dev->dev_private;
3608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3609         int pipe = intel_crtc->pipe;
3610         u32 reg, temp, i, j;
3611
3612         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3613            for train result */
3614         reg = FDI_RX_IMR(pipe);
3615         temp = I915_READ(reg);
3616         temp &= ~FDI_RX_SYMBOL_LOCK;
3617         temp &= ~FDI_RX_BIT_LOCK;
3618         I915_WRITE(reg, temp);
3619
3620         POSTING_READ(reg);
3621         udelay(150);
3622
3623         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3624                       I915_READ(FDI_RX_IIR(pipe)));
3625
3626         /* Try each vswing and preemphasis setting twice before moving on */
3627         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3628                 /* disable first in case we need to retry */
3629                 reg = FDI_TX_CTL(pipe);
3630                 temp = I915_READ(reg);
3631                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3632                 temp &= ~FDI_TX_ENABLE;
3633                 I915_WRITE(reg, temp);
3634
3635                 reg = FDI_RX_CTL(pipe);
3636                 temp = I915_READ(reg);
3637                 temp &= ~FDI_LINK_TRAIN_AUTO;
3638                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3639                 temp &= ~FDI_RX_ENABLE;
3640                 I915_WRITE(reg, temp);
3641
3642                 /* enable CPU FDI TX and PCH FDI RX */
3643                 reg = FDI_TX_CTL(pipe);
3644                 temp = I915_READ(reg);
3645                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3646                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3647                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3648                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3649                 temp |= snb_b_fdi_train_param[j/2];
3650                 temp |= FDI_COMPOSITE_SYNC;
3651                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3652
3653                 I915_WRITE(FDI_RX_MISC(pipe),
3654                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3655
3656                 reg = FDI_RX_CTL(pipe);
3657                 temp = I915_READ(reg);
3658                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3659                 temp |= FDI_COMPOSITE_SYNC;
3660                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3661
3662                 POSTING_READ(reg);
3663                 udelay(1); /* should be 0.5us */
3664
3665                 for (i = 0; i < 4; i++) {
3666                         reg = FDI_RX_IIR(pipe);
3667                         temp = I915_READ(reg);
3668                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3669
3670                         if (temp & FDI_RX_BIT_LOCK ||
3671                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3672                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3673                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3674                                               i);
3675                                 break;
3676                         }
3677                         udelay(1); /* should be 0.5us */
3678                 }
3679                 if (i == 4) {
3680                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3681                         continue;
3682                 }
3683
3684                 /* Train 2 */
3685                 reg = FDI_TX_CTL(pipe);
3686                 temp = I915_READ(reg);
3687                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3688                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3689                 I915_WRITE(reg, temp);
3690
3691                 reg = FDI_RX_CTL(pipe);
3692                 temp = I915_READ(reg);
3693                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3694                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3695                 I915_WRITE(reg, temp);
3696
3697                 POSTING_READ(reg);
3698                 udelay(2); /* should be 1.5us */
3699
3700                 for (i = 0; i < 4; i++) {
3701                         reg = FDI_RX_IIR(pipe);
3702                         temp = I915_READ(reg);
3703                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3704
3705                         if (temp & FDI_RX_SYMBOL_LOCK ||
3706                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3707                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3708                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3709                                               i);
3710                                 goto train_done;
3711                         }
3712                         udelay(2); /* should be 1.5us */
3713                 }
3714                 if (i == 4)
3715                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3716         }
3717
3718 train_done:
3719         DRM_DEBUG_KMS("FDI train done.\n");
3720 }
3721
3722 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3723 {
3724         struct drm_device *dev = intel_crtc->base.dev;
3725         struct drm_i915_private *dev_priv = dev->dev_private;
3726         int pipe = intel_crtc->pipe;
3727         u32 reg, temp;
3728
3729
3730         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3731         reg = FDI_RX_CTL(pipe);
3732         temp = I915_READ(reg);
3733         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3734         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3735         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3736         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3737
3738         POSTING_READ(reg);
3739         udelay(200);
3740
3741         /* Switch from Rawclk to PCDclk */
3742         temp = I915_READ(reg);
3743         I915_WRITE(reg, temp | FDI_PCDCLK);
3744
3745         POSTING_READ(reg);
3746         udelay(200);
3747
3748         /* Enable CPU FDI TX PLL, always on for Ironlake */
3749         reg = FDI_TX_CTL(pipe);
3750         temp = I915_READ(reg);
3751         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3752                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3753
3754                 POSTING_READ(reg);
3755                 udelay(100);
3756         }
3757 }
3758
3759 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3760 {
3761         struct drm_device *dev = intel_crtc->base.dev;
3762         struct drm_i915_private *dev_priv = dev->dev_private;
3763         int pipe = intel_crtc->pipe;
3764         u32 reg, temp;
3765
3766         /* Switch from PCDclk to Rawclk */
3767         reg = FDI_RX_CTL(pipe);
3768         temp = I915_READ(reg);
3769         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3770
3771         /* Disable CPU FDI TX PLL */
3772         reg = FDI_TX_CTL(pipe);
3773         temp = I915_READ(reg);
3774         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3775
3776         POSTING_READ(reg);
3777         udelay(100);
3778
3779         reg = FDI_RX_CTL(pipe);
3780         temp = I915_READ(reg);
3781         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3782
3783         /* Wait for the clocks to turn off. */
3784         POSTING_READ(reg);
3785         udelay(100);
3786 }
3787
3788 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3789 {
3790         struct drm_device *dev = crtc->dev;
3791         struct drm_i915_private *dev_priv = dev->dev_private;
3792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3793         int pipe = intel_crtc->pipe;
3794         u32 reg, temp;
3795
3796         /* disable CPU FDI tx and PCH FDI rx */
3797         reg = FDI_TX_CTL(pipe);
3798         temp = I915_READ(reg);
3799         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3800         POSTING_READ(reg);
3801
3802         reg = FDI_RX_CTL(pipe);
3803         temp = I915_READ(reg);
3804         temp &= ~(0x7 << 16);
3805         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3806         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3807
3808         POSTING_READ(reg);
3809         udelay(100);
3810
3811         /* Ironlake workaround, disable clock pointer after downing FDI */
3812         if (HAS_PCH_IBX(dev))
3813                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3814
3815         /* still set train pattern 1 */
3816         reg = FDI_TX_CTL(pipe);
3817         temp = I915_READ(reg);
3818         temp &= ~FDI_LINK_TRAIN_NONE;
3819         temp |= FDI_LINK_TRAIN_PATTERN_1;
3820         I915_WRITE(reg, temp);
3821
3822         reg = FDI_RX_CTL(pipe);
3823         temp = I915_READ(reg);
3824         if (HAS_PCH_CPT(dev)) {
3825                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3826                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3827         } else {
3828                 temp &= ~FDI_LINK_TRAIN_NONE;
3829                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3830         }
3831         /* BPC in FDI rx is consistent with that in PIPECONF */
3832         temp &= ~(0x07 << 16);
3833         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3834         I915_WRITE(reg, temp);
3835
3836         POSTING_READ(reg);
3837         udelay(100);
3838 }
3839
3840 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3841 {
3842         struct intel_crtc *crtc;
3843
3844         /* Note that we don't need to be called with mode_config.lock here
3845          * as our list of CRTC objects is static for the lifetime of the
3846          * device and so cannot disappear as we iterate. Similarly, we can
3847          * happily treat the predicates as racy, atomic checks as userspace
3848          * cannot claim and pin a new fb without at least acquring the
3849          * struct_mutex and so serialising with us.
3850          */
3851         for_each_intel_crtc(dev, crtc) {
3852                 if (atomic_read(&crtc->unpin_work_count) == 0)
3853                         continue;
3854
3855                 if (crtc->unpin_work)
3856                         intel_wait_for_vblank(dev, crtc->pipe);
3857
3858                 return true;
3859         }
3860
3861         return false;
3862 }
3863
3864 static void page_flip_completed(struct intel_crtc *intel_crtc)
3865 {
3866         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3867         struct intel_unpin_work *work = intel_crtc->unpin_work;
3868
3869         /* ensure that the unpin work is consistent wrt ->pending. */
3870         smp_rmb();
3871         intel_crtc->unpin_work = NULL;
3872
3873         if (work->event)
3874                 drm_send_vblank_event(intel_crtc->base.dev,
3875                                       intel_crtc->pipe,
3876                                       work->event);
3877
3878         drm_crtc_vblank_put(&intel_crtc->base);
3879
3880         wake_up_all(&dev_priv->pending_flip_queue);
3881         queue_work(dev_priv->wq, &work->work);
3882
3883         trace_i915_flip_complete(intel_crtc->plane,
3884                                  work->pending_flip_obj);
3885 }
3886
3887 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3888 {
3889         struct drm_device *dev = crtc->dev;
3890         struct drm_i915_private *dev_priv = dev->dev_private;
3891
3892         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3893         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3894                                        !intel_crtc_has_pending_flip(crtc),
3895                                        60*HZ) == 0)) {
3896                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3897
3898                 spin_lock_irq(&dev->event_lock);
3899                 if (intel_crtc->unpin_work) {
3900                         WARN_ONCE(1, "Removing stuck page flip\n");
3901                         page_flip_completed(intel_crtc);
3902                 }
3903                 spin_unlock_irq(&dev->event_lock);
3904         }
3905
3906         if (crtc->primary->fb) {
3907                 mutex_lock(&dev->struct_mutex);
3908                 intel_finish_fb(crtc->primary->fb);
3909                 mutex_unlock(&dev->struct_mutex);
3910         }
3911 }
3912
3913 /* Program iCLKIP clock to the desired frequency */
3914 static void lpt_program_iclkip(struct drm_crtc *crtc)
3915 {
3916         struct drm_device *dev = crtc->dev;
3917         struct drm_i915_private *dev_priv = dev->dev_private;
3918         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3919         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3920         u32 temp;
3921
3922         mutex_lock(&dev_priv->sb_lock);
3923
3924         /* It is necessary to ungate the pixclk gate prior to programming
3925          * the divisors, and gate it back when it is done.
3926          */
3927         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3928
3929         /* Disable SSCCTL */
3930         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3931                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3932                                 SBI_SSCCTL_DISABLE,
3933                         SBI_ICLK);
3934
3935         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3936         if (clock == 20000) {
3937                 auxdiv = 1;
3938                 divsel = 0x41;
3939                 phaseinc = 0x20;
3940         } else {
3941                 /* The iCLK virtual clock root frequency is in MHz,
3942                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3943                  * divisors, it is necessary to divide one by another, so we
3944                  * convert the virtual clock precision to KHz here for higher
3945                  * precision.
3946                  */
3947                 u32 iclk_virtual_root_freq = 172800 * 1000;
3948                 u32 iclk_pi_range = 64;
3949                 u32 desired_divisor, msb_divisor_value, pi_value;
3950
3951                 desired_divisor = (iclk_virtual_root_freq / clock);
3952                 msb_divisor_value = desired_divisor / iclk_pi_range;
3953                 pi_value = desired_divisor % iclk_pi_range;
3954
3955                 auxdiv = 0;
3956                 divsel = msb_divisor_value - 2;
3957                 phaseinc = pi_value;
3958         }
3959
3960         /* This should not happen with any sane values */
3961         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3962                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3963         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3964                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3965
3966         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3967                         clock,
3968                         auxdiv,
3969                         divsel,
3970                         phasedir,
3971                         phaseinc);
3972
3973         /* Program SSCDIVINTPHASE6 */
3974         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3975         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3976         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3977         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3978         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3979         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3980         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3981         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3982
3983         /* Program SSCAUXDIV */
3984         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3985         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3986         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3987         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3988
3989         /* Enable modulator and associated divider */
3990         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3991         temp &= ~SBI_SSCCTL_DISABLE;
3992         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3993
3994         /* Wait for initialization time */
3995         udelay(24);
3996
3997         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3998
3999         mutex_unlock(&dev_priv->sb_lock);
4000 }
4001
4002 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4003                                                 enum pipe pch_transcoder)
4004 {
4005         struct drm_device *dev = crtc->base.dev;
4006         struct drm_i915_private *dev_priv = dev->dev_private;
4007         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4008
4009         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4010                    I915_READ(HTOTAL(cpu_transcoder)));
4011         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4012                    I915_READ(HBLANK(cpu_transcoder)));
4013         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4014                    I915_READ(HSYNC(cpu_transcoder)));
4015
4016         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4017                    I915_READ(VTOTAL(cpu_transcoder)));
4018         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4019                    I915_READ(VBLANK(cpu_transcoder)));
4020         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4021                    I915_READ(VSYNC(cpu_transcoder)));
4022         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4023                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4024 }
4025
4026 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4027 {
4028         struct drm_i915_private *dev_priv = dev->dev_private;
4029         uint32_t temp;
4030
4031         temp = I915_READ(SOUTH_CHICKEN1);
4032         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4033                 return;
4034
4035         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4036         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4037
4038         temp &= ~FDI_BC_BIFURCATION_SELECT;
4039         if (enable)
4040                 temp |= FDI_BC_BIFURCATION_SELECT;
4041
4042         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4043         I915_WRITE(SOUTH_CHICKEN1, temp);
4044         POSTING_READ(SOUTH_CHICKEN1);
4045 }
4046
4047 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4048 {
4049         struct drm_device *dev = intel_crtc->base.dev;
4050
4051         switch (intel_crtc->pipe) {
4052         case PIPE_A:
4053                 break;
4054         case PIPE_B:
4055                 if (intel_crtc->config->fdi_lanes > 2)
4056                         cpt_set_fdi_bc_bifurcation(dev, false);
4057                 else
4058                         cpt_set_fdi_bc_bifurcation(dev, true);
4059
4060                 break;
4061         case PIPE_C:
4062                 cpt_set_fdi_bc_bifurcation(dev, true);
4063
4064                 break;
4065         default:
4066                 BUG();
4067         }
4068 }
4069
4070 /*
4071  * Enable PCH resources required for PCH ports:
4072  *   - PCH PLLs
4073  *   - FDI training & RX/TX
4074  *   - update transcoder timings
4075  *   - DP transcoding bits
4076  *   - transcoder
4077  */
4078 static void ironlake_pch_enable(struct drm_crtc *crtc)
4079 {
4080         struct drm_device *dev = crtc->dev;
4081         struct drm_i915_private *dev_priv = dev->dev_private;
4082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4083         int pipe = intel_crtc->pipe;
4084         u32 reg, temp;
4085
4086         assert_pch_transcoder_disabled(dev_priv, pipe);
4087
4088         if (IS_IVYBRIDGE(dev))
4089                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4090
4091         /* Write the TU size bits before fdi link training, so that error
4092          * detection works. */
4093         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4094                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4095
4096         /* For PCH output, training FDI link */
4097         dev_priv->display.fdi_link_train(crtc);
4098
4099         /* We need to program the right clock selection before writing the pixel
4100          * mutliplier into the DPLL. */
4101         if (HAS_PCH_CPT(dev)) {
4102                 u32 sel;
4103
4104                 temp = I915_READ(PCH_DPLL_SEL);
4105                 temp |= TRANS_DPLL_ENABLE(pipe);
4106                 sel = TRANS_DPLLB_SEL(pipe);
4107                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4108                         temp |= sel;
4109                 else
4110                         temp &= ~sel;
4111                 I915_WRITE(PCH_DPLL_SEL, temp);
4112         }
4113
4114         /* XXX: pch pll's can be enabled any time before we enable the PCH
4115          * transcoder, and we actually should do this to not upset any PCH
4116          * transcoder that already use the clock when we share it.
4117          *
4118          * Note that enable_shared_dpll tries to do the right thing, but
4119          * get_shared_dpll unconditionally resets the pll - we need that to have
4120          * the right LVDS enable sequence. */
4121         intel_enable_shared_dpll(intel_crtc);
4122
4123         /* set transcoder timing, panel must allow it */
4124         assert_panel_unlocked(dev_priv, pipe);
4125         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4126
4127         intel_fdi_normal_train(crtc);
4128
4129         /* For PCH DP, enable TRANS_DP_CTL */
4130         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4131                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4132                 reg = TRANS_DP_CTL(pipe);
4133                 temp = I915_READ(reg);
4134                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4135                           TRANS_DP_SYNC_MASK |
4136                           TRANS_DP_BPC_MASK);
4137                 temp |= TRANS_DP_OUTPUT_ENABLE;
4138                 temp |= bpc << 9; /* same format but at 11:9 */
4139
4140                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4141                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4142                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4143                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4144
4145                 switch (intel_trans_dp_port_sel(crtc)) {
4146                 case PCH_DP_B:
4147                         temp |= TRANS_DP_PORT_SEL_B;
4148                         break;
4149                 case PCH_DP_C:
4150                         temp |= TRANS_DP_PORT_SEL_C;
4151                         break;
4152                 case PCH_DP_D:
4153                         temp |= TRANS_DP_PORT_SEL_D;
4154                         break;
4155                 default:
4156                         BUG();
4157                 }
4158
4159                 I915_WRITE(reg, temp);
4160         }
4161
4162         ironlake_enable_pch_transcoder(dev_priv, pipe);
4163 }
4164
4165 static void lpt_pch_enable(struct drm_crtc *crtc)
4166 {
4167         struct drm_device *dev = crtc->dev;
4168         struct drm_i915_private *dev_priv = dev->dev_private;
4169         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4170         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4171
4172         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4173
4174         lpt_program_iclkip(crtc);
4175
4176         /* Set transcoder timing. */
4177         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4178
4179         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4180 }
4181
4182 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4183                                                 struct intel_crtc_state *crtc_state)
4184 {
4185         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4186         struct intel_shared_dpll *pll;
4187         struct intel_shared_dpll_config *shared_dpll;
4188         enum intel_dpll_id i;
4189
4190         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4191
4192         if (HAS_PCH_IBX(dev_priv->dev)) {
4193                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4194                 i = (enum intel_dpll_id) crtc->pipe;
4195                 pll = &dev_priv->shared_dplls[i];
4196
4197                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4198                               crtc->base.base.id, pll->name);
4199
4200                 WARN_ON(shared_dpll[i].crtc_mask);
4201
4202                 goto found;
4203         }
4204
4205         if (IS_BROXTON(dev_priv->dev)) {
4206                 /* PLL is attached to port in bxt */
4207                 struct intel_encoder *encoder;
4208                 struct intel_digital_port *intel_dig_port;
4209
4210                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4211                 if (WARN_ON(!encoder))
4212                         return NULL;
4213
4214                 intel_dig_port = enc_to_dig_port(&encoder->base);
4215                 /* 1:1 mapping between ports and PLLs */
4216                 i = (enum intel_dpll_id)intel_dig_port->port;
4217                 pll = &dev_priv->shared_dplls[i];
4218                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4219                         crtc->base.base.id, pll->name);
4220                 WARN_ON(shared_dpll[i].crtc_mask);
4221
4222                 goto found;
4223         }
4224
4225         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4226                 pll = &dev_priv->shared_dplls[i];
4227
4228                 /* Only want to check enabled timings first */
4229                 if (shared_dpll[i].crtc_mask == 0)
4230                         continue;
4231
4232                 if (memcmp(&crtc_state->dpll_hw_state,
4233                            &shared_dpll[i].hw_state,
4234                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4235                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4236                                       crtc->base.base.id, pll->name,
4237                                       shared_dpll[i].crtc_mask,
4238                                       pll->active);
4239                         goto found;
4240                 }
4241         }
4242
4243         /* Ok no matching timings, maybe there's a free one? */
4244         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4245                 pll = &dev_priv->shared_dplls[i];
4246                 if (shared_dpll[i].crtc_mask == 0) {
4247                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4248                                       crtc->base.base.id, pll->name);
4249                         goto found;
4250                 }
4251         }
4252
4253         return NULL;
4254
4255 found:
4256         if (shared_dpll[i].crtc_mask == 0)
4257                 shared_dpll[i].hw_state =
4258                         crtc_state->dpll_hw_state;
4259
4260         crtc_state->shared_dpll = i;
4261         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4262                          pipe_name(crtc->pipe));
4263
4264         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4265
4266         return pll;
4267 }
4268
4269 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4270 {
4271         struct drm_i915_private *dev_priv = to_i915(state->dev);
4272         struct intel_shared_dpll_config *shared_dpll;
4273         struct intel_shared_dpll *pll;
4274         enum intel_dpll_id i;
4275
4276         if (!to_intel_atomic_state(state)->dpll_set)
4277                 return;
4278
4279         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4280         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4281                 pll = &dev_priv->shared_dplls[i];
4282                 pll->config = shared_dpll[i];
4283         }
4284 }
4285
4286 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4287 {
4288         struct drm_i915_private *dev_priv = dev->dev_private;
4289         int dslreg = PIPEDSL(pipe);
4290         u32 temp;
4291
4292         temp = I915_READ(dslreg);
4293         udelay(500);
4294         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4295                 if (wait_for(I915_READ(dslreg) != temp, 5))
4296                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4297         }
4298 }
4299
4300 static int
4301 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4302                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4303                   int src_w, int src_h, int dst_w, int dst_h)
4304 {
4305         struct intel_crtc_scaler_state *scaler_state =
4306                 &crtc_state->scaler_state;
4307         struct intel_crtc *intel_crtc =
4308                 to_intel_crtc(crtc_state->base.crtc);
4309         int need_scaling;
4310
4311         need_scaling = intel_rotation_90_or_270(rotation) ?
4312                 (src_h != dst_w || src_w != dst_h):
4313                 (src_w != dst_w || src_h != dst_h);
4314
4315         /*
4316          * if plane is being disabled or scaler is no more required or force detach
4317          *  - free scaler binded to this plane/crtc
4318          *  - in order to do this, update crtc->scaler_usage
4319          *
4320          * Here scaler state in crtc_state is set free so that
4321          * scaler can be assigned to other user. Actual register
4322          * update to free the scaler is done in plane/panel-fit programming.
4323          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4324          */
4325         if (force_detach || !need_scaling) {
4326                 if (*scaler_id >= 0) {
4327                         scaler_state->scaler_users &= ~(1 << scaler_user);
4328                         scaler_state->scalers[*scaler_id].in_use = 0;
4329
4330                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4331                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4332                                 intel_crtc->pipe, scaler_user, *scaler_id,
4333                                 scaler_state->scaler_users);
4334                         *scaler_id = -1;
4335                 }
4336                 return 0;
4337         }
4338
4339         /* range checks */
4340         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4341                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4342
4343                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4344                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4345                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4346                         "size is out of scaler range\n",
4347                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4348                 return -EINVAL;
4349         }
4350
4351         /* mark this plane as a scaler user in crtc_state */
4352         scaler_state->scaler_users |= (1 << scaler_user);
4353         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4354                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4355                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4356                 scaler_state->scaler_users);
4357
4358         return 0;
4359 }
4360
4361 /**
4362  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4363  *
4364  * @state: crtc's scaler state
4365  * @force_detach: whether to forcibly disable scaler
4366  *
4367  * Return
4368  *     0 - scaler_usage updated successfully
4369  *    error - requested scaling cannot be supported or other error condition
4370  */
4371 int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4372 {
4373         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4374         struct drm_display_mode *adjusted_mode =
4375                 &state->base.adjusted_mode;
4376
4377         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4378                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4379
4380         return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4381                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4382                 state->pipe_src_w, state->pipe_src_h,
4383                 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4384 }
4385
4386 /**
4387  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4388  *
4389  * @state: crtc's scaler state
4390  * @plane_state: atomic plane state to update
4391  *
4392  * Return
4393  *     0 - scaler_usage updated successfully
4394  *    error - requested scaling cannot be supported or other error condition
4395  */
4396 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4397                                    struct intel_plane_state *plane_state)
4398 {
4399
4400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4401         struct intel_plane *intel_plane =
4402                 to_intel_plane(plane_state->base.plane);
4403         struct drm_framebuffer *fb = plane_state->base.fb;
4404         int ret;
4405
4406         bool force_detach = !fb || !plane_state->visible;
4407
4408         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4409                       intel_plane->base.base.id, intel_crtc->pipe,
4410                       drm_plane_index(&intel_plane->base));
4411
4412         ret = skl_update_scaler(crtc_state, force_detach,
4413                                 drm_plane_index(&intel_plane->base),
4414                                 &plane_state->scaler_id,
4415                                 plane_state->base.rotation,
4416                                 drm_rect_width(&plane_state->src) >> 16,
4417                                 drm_rect_height(&plane_state->src) >> 16,
4418                                 drm_rect_width(&plane_state->dst),
4419                                 drm_rect_height(&plane_state->dst));
4420
4421         if (ret || plane_state->scaler_id < 0)
4422                 return ret;
4423
4424         /* check colorkey */
4425         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4426                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4427                               intel_plane->base.base.id);
4428                 return -EINVAL;
4429         }
4430
4431         /* Check src format */
4432         switch (fb->pixel_format) {
4433         case DRM_FORMAT_RGB565:
4434         case DRM_FORMAT_XBGR8888:
4435         case DRM_FORMAT_XRGB8888:
4436         case DRM_FORMAT_ABGR8888:
4437         case DRM_FORMAT_ARGB8888:
4438         case DRM_FORMAT_XRGB2101010:
4439         case DRM_FORMAT_XBGR2101010:
4440         case DRM_FORMAT_YUYV:
4441         case DRM_FORMAT_YVYU:
4442         case DRM_FORMAT_UYVY:
4443         case DRM_FORMAT_VYUY:
4444                 break;
4445         default:
4446                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4447                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4448                 return -EINVAL;
4449         }
4450
4451         return 0;
4452 }
4453
4454 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4455 {
4456         struct drm_device *dev = crtc->base.dev;
4457         struct drm_i915_private *dev_priv = dev->dev_private;
4458         int pipe = crtc->pipe;
4459         struct intel_crtc_scaler_state *scaler_state =
4460                 &crtc->config->scaler_state;
4461
4462         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4463
4464         /* To update pfit, first update scaler state */
4465         skl_update_scaler_crtc(crtc->config, !enable);
4466         intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4467         skl_detach_scalers(crtc);
4468         if (!enable)
4469                 return;
4470
4471         if (crtc->config->pch_pfit.enabled) {
4472                 int id;
4473
4474                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4475                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4476                         return;
4477                 }
4478
4479                 id = scaler_state->scaler_id;
4480                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4481                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4482                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4483                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4484
4485                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4486         }
4487 }
4488
4489 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4490 {
4491         struct drm_device *dev = crtc->base.dev;
4492         struct drm_i915_private *dev_priv = dev->dev_private;
4493         int pipe = crtc->pipe;
4494
4495         if (crtc->config->pch_pfit.enabled) {
4496                 /* Force use of hard-coded filter coefficients
4497                  * as some pre-programmed values are broken,
4498                  * e.g. x201.
4499                  */
4500                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4501                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4502                                                  PF_PIPE_SEL_IVB(pipe));
4503                 else
4504                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4505                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4506                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4507         }
4508 }
4509
4510 void hsw_enable_ips(struct intel_crtc *crtc)
4511 {
4512         struct drm_device *dev = crtc->base.dev;
4513         struct drm_i915_private *dev_priv = dev->dev_private;
4514
4515         if (!crtc->config->ips_enabled)
4516                 return;
4517
4518         /* We can only enable IPS after we enable a plane and wait for a vblank */
4519         intel_wait_for_vblank(dev, crtc->pipe);
4520
4521         assert_plane_enabled(dev_priv, crtc->plane);
4522         if (IS_BROADWELL(dev)) {
4523                 mutex_lock(&dev_priv->rps.hw_lock);
4524                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4525                 mutex_unlock(&dev_priv->rps.hw_lock);
4526                 /* Quoting Art Runyan: "its not safe to expect any particular
4527                  * value in IPS_CTL bit 31 after enabling IPS through the
4528                  * mailbox." Moreover, the mailbox may return a bogus state,
4529                  * so we need to just enable it and continue on.
4530                  */
4531         } else {
4532                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4533                 /* The bit only becomes 1 in the next vblank, so this wait here
4534                  * is essentially intel_wait_for_vblank. If we don't have this
4535                  * and don't wait for vblanks until the end of crtc_enable, then
4536                  * the HW state readout code will complain that the expected
4537                  * IPS_CTL value is not the one we read. */
4538                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4539                         DRM_ERROR("Timed out waiting for IPS enable\n");
4540         }
4541 }
4542
4543 void hsw_disable_ips(struct intel_crtc *crtc)
4544 {
4545         struct drm_device *dev = crtc->base.dev;
4546         struct drm_i915_private *dev_priv = dev->dev_private;
4547
4548         if (!crtc->config->ips_enabled)
4549                 return;
4550
4551         assert_plane_enabled(dev_priv, crtc->plane);
4552         if (IS_BROADWELL(dev)) {
4553                 mutex_lock(&dev_priv->rps.hw_lock);
4554                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4555                 mutex_unlock(&dev_priv->rps.hw_lock);
4556                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4557                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4558                         DRM_ERROR("Timed out waiting for IPS disable\n");
4559         } else {
4560                 I915_WRITE(IPS_CTL, 0);
4561                 POSTING_READ(IPS_CTL);
4562         }
4563
4564         /* We need to wait for a vblank before we can disable the plane. */
4565         intel_wait_for_vblank(dev, crtc->pipe);
4566 }
4567
4568 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4569 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4570 {
4571         struct drm_device *dev = crtc->dev;
4572         struct drm_i915_private *dev_priv = dev->dev_private;
4573         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4574         enum pipe pipe = intel_crtc->pipe;
4575         int palreg = PALETTE(pipe);
4576         int i;
4577         bool reenable_ips = false;
4578
4579         /* The clocks have to be on to load the palette. */
4580         if (!crtc->state->active)
4581                 return;
4582
4583         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4584                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4585                         assert_dsi_pll_enabled(dev_priv);
4586                 else
4587                         assert_pll_enabled(dev_priv, pipe);
4588         }
4589
4590         /* use legacy palette for Ironlake */
4591         if (!HAS_GMCH_DISPLAY(dev))
4592                 palreg = LGC_PALETTE(pipe);
4593
4594         /* Workaround : Do not read or write the pipe palette/gamma data while
4595          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4596          */
4597         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4598             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4599              GAMMA_MODE_MODE_SPLIT)) {
4600                 hsw_disable_ips(intel_crtc);
4601                 reenable_ips = true;
4602         }
4603
4604         for (i = 0; i < 256; i++) {
4605                 I915_WRITE(palreg + 4 * i,
4606                            (intel_crtc->lut_r[i] << 16) |
4607                            (intel_crtc->lut_g[i] << 8) |
4608                            intel_crtc->lut_b[i]);
4609         }
4610
4611         if (reenable_ips)
4612                 hsw_enable_ips(intel_crtc);
4613 }
4614
4615 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4616 {
4617         if (intel_crtc->overlay) {
4618                 struct drm_device *dev = intel_crtc->base.dev;
4619                 struct drm_i915_private *dev_priv = dev->dev_private;
4620
4621                 mutex_lock(&dev->struct_mutex);
4622                 dev_priv->mm.interruptible = false;
4623                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4624                 dev_priv->mm.interruptible = true;
4625                 mutex_unlock(&dev->struct_mutex);
4626         }
4627
4628         /* Let userspace switch the overlay on again. In most cases userspace
4629          * has to recompute where to put it anyway.
4630          */
4631 }
4632
4633 /**
4634  * intel_post_enable_primary - Perform operations after enabling primary plane
4635  * @crtc: the CRTC whose primary plane was just enabled
4636  *
4637  * Performs potentially sleeping operations that must be done after the primary
4638  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4639  * called due to an explicit primary plane update, or due to an implicit
4640  * re-enable that is caused when a sprite plane is updated to no longer
4641  * completely hide the primary plane.
4642  */
4643 static void
4644 intel_post_enable_primary(struct drm_crtc *crtc)
4645 {
4646         struct drm_device *dev = crtc->dev;
4647         struct drm_i915_private *dev_priv = dev->dev_private;
4648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4649         int pipe = intel_crtc->pipe;
4650
4651         /*
4652          * BDW signals flip done immediately if the plane
4653          * is disabled, even if the plane enable is already
4654          * armed to occur at the next vblank :(
4655          */
4656         if (IS_BROADWELL(dev))
4657                 intel_wait_for_vblank(dev, pipe);
4658
4659         /*
4660          * FIXME IPS should be fine as long as one plane is
4661          * enabled, but in practice it seems to have problems
4662          * when going from primary only to sprite only and vice
4663          * versa.
4664          */
4665         hsw_enable_ips(intel_crtc);
4666
4667         /*
4668          * Gen2 reports pipe underruns whenever all planes are disabled.
4669          * So don't enable underrun reporting before at least some planes
4670          * are enabled.
4671          * FIXME: Need to fix the logic to work when we turn off all planes
4672          * but leave the pipe running.
4673          */
4674         if (IS_GEN2(dev))
4675                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4676
4677         /* Underruns don't raise interrupts, so check manually. */
4678         if (HAS_GMCH_DISPLAY(dev))
4679                 i9xx_check_fifo_underruns(dev_priv);
4680 }
4681
4682 /**
4683  * intel_pre_disable_primary - Perform operations before disabling primary plane
4684  * @crtc: the CRTC whose primary plane is to be disabled
4685  *
4686  * Performs potentially sleeping operations that must be done before the
4687  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4688  * be called due to an explicit primary plane update, or due to an implicit
4689  * disable that is caused when a sprite plane completely hides the primary
4690  * plane.
4691  */
4692 static void
4693 intel_pre_disable_primary(struct drm_crtc *crtc)
4694 {
4695         struct drm_device *dev = crtc->dev;
4696         struct drm_i915_private *dev_priv = dev->dev_private;
4697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698         int pipe = intel_crtc->pipe;
4699
4700         /*
4701          * Gen2 reports pipe underruns whenever all planes are disabled.
4702          * So diasble underrun reporting before all the planes get disabled.
4703          * FIXME: Need to fix the logic to work when we turn off all planes
4704          * but leave the pipe running.
4705          */
4706         if (IS_GEN2(dev))
4707                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4708
4709         /*
4710          * Vblank time updates from the shadow to live plane control register
4711          * are blocked if the memory self-refresh mode is active at that
4712          * moment. So to make sure the plane gets truly disabled, disable
4713          * first the self-refresh mode. The self-refresh enable bit in turn
4714          * will be checked/applied by the HW only at the next frame start
4715          * event which is after the vblank start event, so we need to have a
4716          * wait-for-vblank between disabling the plane and the pipe.
4717          */
4718         if (HAS_GMCH_DISPLAY(dev)) {
4719                 intel_set_memory_cxsr(dev_priv, false);
4720                 dev_priv->wm.vlv.cxsr = false;
4721                 intel_wait_for_vblank(dev, pipe);
4722         }
4723
4724         /*
4725          * FIXME IPS should be fine as long as one plane is
4726          * enabled, but in practice it seems to have problems
4727          * when going from primary only to sprite only and vice
4728          * versa.
4729          */
4730         hsw_disable_ips(intel_crtc);
4731 }
4732
4733 static void intel_post_plane_update(struct intel_crtc *crtc)
4734 {
4735         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4736         struct drm_device *dev = crtc->base.dev;
4737         struct drm_plane *plane;
4738
4739         if (atomic->wait_vblank)
4740                 intel_wait_for_vblank(dev, crtc->pipe);
4741
4742         intel_frontbuffer_flip(dev, atomic->fb_bits);
4743
4744         if (atomic->disable_cxsr)
4745                 crtc->wm.cxsr_allowed = true;
4746
4747         if (crtc->atomic.update_wm_post)
4748                 intel_update_watermarks(&crtc->base);
4749
4750         if (atomic->update_fbc) {
4751                 mutex_lock(&dev->struct_mutex);
4752                 intel_fbc_update(dev);
4753                 mutex_unlock(&dev->struct_mutex);
4754         }
4755
4756         if (atomic->post_enable_primary)
4757                 intel_post_enable_primary(&crtc->base);
4758
4759         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4760                 intel_update_sprite_watermarks(plane, &crtc->base,
4761                                                0, 0, 0, false, false);
4762
4763         memset(atomic, 0, sizeof(*atomic));
4764 }
4765
4766 static void intel_pre_plane_update(struct intel_crtc *crtc)
4767 {
4768         struct drm_device *dev = crtc->base.dev;
4769         struct drm_i915_private *dev_priv = dev->dev_private;
4770         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4771         struct drm_plane *p;
4772
4773         /* Track fb's for any planes being disabled */
4774         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4775                 struct intel_plane *plane = to_intel_plane(p);
4776
4777                 mutex_lock(&dev->struct_mutex);
4778                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4779                                   plane->frontbuffer_bit);
4780                 mutex_unlock(&dev->struct_mutex);
4781         }
4782
4783         if (atomic->wait_for_flips)
4784                 intel_crtc_wait_for_pending_flips(&crtc->base);
4785
4786         if (atomic->disable_fbc &&
4787             dev_priv->fbc.crtc == crtc) {
4788                 mutex_lock(&dev->struct_mutex);
4789                 if (dev_priv->fbc.crtc == crtc)
4790                         intel_fbc_disable(dev);
4791                 mutex_unlock(&dev->struct_mutex);
4792         }
4793
4794         if (crtc->atomic.disable_ips)
4795                 hsw_disable_ips(crtc);
4796
4797         if (atomic->pre_disable_primary)
4798                 intel_pre_disable_primary(&crtc->base);
4799
4800         if (atomic->disable_cxsr) {
4801                 crtc->wm.cxsr_allowed = false;
4802                 intel_set_memory_cxsr(dev_priv, false);
4803         }
4804 }
4805
4806 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4807 {
4808         struct drm_device *dev = crtc->dev;
4809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4810         struct drm_plane *p;
4811         int pipe = intel_crtc->pipe;
4812
4813         intel_crtc_dpms_overlay_disable(intel_crtc);
4814
4815         drm_for_each_plane_mask(p, dev, plane_mask)
4816                 to_intel_plane(p)->disable_plane(p, crtc);
4817
4818         /*
4819          * FIXME: Once we grow proper nuclear flip support out of this we need
4820          * to compute the mask of flip planes precisely. For the time being
4821          * consider this a flip to a NULL plane.
4822          */
4823         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4824 }
4825
4826 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4827 {
4828         struct drm_device *dev = crtc->dev;
4829         struct drm_i915_private *dev_priv = dev->dev_private;
4830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4831         struct intel_encoder *encoder;
4832         int pipe = intel_crtc->pipe;
4833
4834         if (WARN_ON(intel_crtc->active))
4835                 return;
4836
4837         if (intel_crtc->config->has_pch_encoder)
4838                 intel_prepare_shared_dpll(intel_crtc);
4839
4840         if (intel_crtc->config->has_dp_encoder)
4841                 intel_dp_set_m_n(intel_crtc, M1_N1);
4842
4843         intel_set_pipe_timings(intel_crtc);
4844
4845         if (intel_crtc->config->has_pch_encoder) {
4846                 intel_cpu_transcoder_set_m_n(intel_crtc,
4847                                      &intel_crtc->config->fdi_m_n, NULL);
4848         }
4849
4850         ironlake_set_pipeconf(crtc);
4851
4852         intel_crtc->active = true;
4853
4854         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4855         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4856
4857         for_each_encoder_on_crtc(dev, crtc, encoder)
4858                 if (encoder->pre_enable)
4859                         encoder->pre_enable(encoder);
4860
4861         if (intel_crtc->config->has_pch_encoder) {
4862                 /* Note: FDI PLL enabling _must_ be done before we enable the
4863                  * cpu pipes, hence this is separate from all the other fdi/pch
4864                  * enabling. */
4865                 ironlake_fdi_pll_enable(intel_crtc);
4866         } else {
4867                 assert_fdi_tx_disabled(dev_priv, pipe);
4868                 assert_fdi_rx_disabled(dev_priv, pipe);
4869         }
4870
4871         ironlake_pfit_enable(intel_crtc);
4872
4873         /*
4874          * On ILK+ LUT must be loaded before the pipe is running but with
4875          * clocks enabled
4876          */
4877         intel_crtc_load_lut(crtc);
4878
4879         intel_update_watermarks(crtc);
4880         intel_enable_pipe(intel_crtc);
4881
4882         if (intel_crtc->config->has_pch_encoder)
4883                 ironlake_pch_enable(crtc);
4884
4885         assert_vblank_disabled(crtc);
4886         drm_crtc_vblank_on(crtc);
4887
4888         for_each_encoder_on_crtc(dev, crtc, encoder)
4889                 encoder->enable(encoder);
4890
4891         if (HAS_PCH_CPT(dev))
4892                 cpt_verify_modeset(dev, intel_crtc->pipe);
4893 }
4894
4895 /* IPS only exists on ULT machines and is tied to pipe A. */
4896 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4897 {
4898         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4899 }
4900
4901 static void haswell_crtc_enable(struct drm_crtc *crtc)
4902 {
4903         struct drm_device *dev = crtc->dev;
4904         struct drm_i915_private *dev_priv = dev->dev_private;
4905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4906         struct intel_encoder *encoder;
4907         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4908         struct intel_crtc_state *pipe_config =
4909                 to_intel_crtc_state(crtc->state);
4910
4911         if (WARN_ON(intel_crtc->active))
4912                 return;
4913
4914         if (intel_crtc_to_shared_dpll(intel_crtc))
4915                 intel_enable_shared_dpll(intel_crtc);
4916
4917         if (intel_crtc->config->has_dp_encoder)
4918                 intel_dp_set_m_n(intel_crtc, M1_N1);
4919
4920         intel_set_pipe_timings(intel_crtc);
4921
4922         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4923                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4924                            intel_crtc->config->pixel_multiplier - 1);
4925         }
4926
4927         if (intel_crtc->config->has_pch_encoder) {
4928                 intel_cpu_transcoder_set_m_n(intel_crtc,
4929                                      &intel_crtc->config->fdi_m_n, NULL);
4930         }
4931
4932         haswell_set_pipeconf(crtc);
4933
4934         intel_set_pipe_csc(crtc);
4935
4936         intel_crtc->active = true;
4937
4938         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4939         for_each_encoder_on_crtc(dev, crtc, encoder)
4940                 if (encoder->pre_enable)
4941                         encoder->pre_enable(encoder);
4942
4943         if (intel_crtc->config->has_pch_encoder) {
4944                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4945                                                       true);
4946                 dev_priv->display.fdi_link_train(crtc);
4947         }
4948
4949         intel_ddi_enable_pipe_clock(intel_crtc);
4950
4951         if (INTEL_INFO(dev)->gen == 9)
4952                 skylake_pfit_update(intel_crtc, 1);
4953         else if (INTEL_INFO(dev)->gen < 9)
4954                 ironlake_pfit_enable(intel_crtc);
4955         else
4956                 MISSING_CASE(INTEL_INFO(dev)->gen);
4957
4958         /*
4959          * On ILK+ LUT must be loaded before the pipe is running but with
4960          * clocks enabled
4961          */
4962         intel_crtc_load_lut(crtc);
4963
4964         intel_ddi_set_pipe_settings(crtc);
4965         intel_ddi_enable_transcoder_func(crtc);
4966
4967         intel_update_watermarks(crtc);
4968         intel_enable_pipe(intel_crtc);
4969
4970         if (intel_crtc->config->has_pch_encoder)
4971                 lpt_pch_enable(crtc);
4972
4973         if (intel_crtc->config->dp_encoder_is_mst)
4974                 intel_ddi_set_vc_payload_alloc(crtc, true);
4975
4976         assert_vblank_disabled(crtc);
4977         drm_crtc_vblank_on(crtc);
4978
4979         for_each_encoder_on_crtc(dev, crtc, encoder) {
4980                 encoder->enable(encoder);
4981                 intel_opregion_notify_encoder(encoder, true);
4982         }
4983
4984         /* If we change the relative order between pipe/planes enabling, we need
4985          * to change the workaround. */
4986         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4987         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4988                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4989                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4990         }
4991 }
4992
4993 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4994 {
4995         struct drm_device *dev = crtc->base.dev;
4996         struct drm_i915_private *dev_priv = dev->dev_private;
4997         int pipe = crtc->pipe;
4998
4999         /* To avoid upsetting the power well on haswell only disable the pfit if
5000          * it's in use. The hw state code will make sure we get this right. */
5001         if (crtc->config->pch_pfit.enabled) {
5002                 I915_WRITE(PF_CTL(pipe), 0);
5003                 I915_WRITE(PF_WIN_POS(pipe), 0);
5004                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5005         }
5006 }
5007
5008 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5009 {
5010         struct drm_device *dev = crtc->dev;
5011         struct drm_i915_private *dev_priv = dev->dev_private;
5012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5013         struct intel_encoder *encoder;
5014         int pipe = intel_crtc->pipe;
5015         u32 reg, temp;
5016
5017         for_each_encoder_on_crtc(dev, crtc, encoder)
5018                 encoder->disable(encoder);
5019
5020         drm_crtc_vblank_off(crtc);
5021         assert_vblank_disabled(crtc);
5022
5023         if (intel_crtc->config->has_pch_encoder)
5024                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5025
5026         intel_disable_pipe(intel_crtc);
5027
5028         ironlake_pfit_disable(intel_crtc);
5029
5030         if (intel_crtc->config->has_pch_encoder)
5031                 ironlake_fdi_disable(crtc);
5032
5033         for_each_encoder_on_crtc(dev, crtc, encoder)
5034                 if (encoder->post_disable)
5035                         encoder->post_disable(encoder);
5036
5037         if (intel_crtc->config->has_pch_encoder) {
5038                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5039
5040                 if (HAS_PCH_CPT(dev)) {
5041                         /* disable TRANS_DP_CTL */
5042                         reg = TRANS_DP_CTL(pipe);
5043                         temp = I915_READ(reg);
5044                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5045                                   TRANS_DP_PORT_SEL_MASK);
5046                         temp |= TRANS_DP_PORT_SEL_NONE;
5047                         I915_WRITE(reg, temp);
5048
5049                         /* disable DPLL_SEL */
5050                         temp = I915_READ(PCH_DPLL_SEL);
5051                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5052                         I915_WRITE(PCH_DPLL_SEL, temp);
5053                 }
5054
5055                 ironlake_fdi_pll_disable(intel_crtc);
5056         }
5057 }
5058
5059 static void haswell_crtc_disable(struct drm_crtc *crtc)
5060 {
5061         struct drm_device *dev = crtc->dev;
5062         struct drm_i915_private *dev_priv = dev->dev_private;
5063         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5064         struct intel_encoder *encoder;
5065         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5066
5067         for_each_encoder_on_crtc(dev, crtc, encoder) {
5068                 intel_opregion_notify_encoder(encoder, false);
5069                 encoder->disable(encoder);
5070         }
5071
5072         drm_crtc_vblank_off(crtc);
5073         assert_vblank_disabled(crtc);
5074
5075         if (intel_crtc->config->has_pch_encoder)
5076                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5077                                                       false);
5078         intel_disable_pipe(intel_crtc);
5079
5080         if (intel_crtc->config->dp_encoder_is_mst)
5081                 intel_ddi_set_vc_payload_alloc(crtc, false);
5082
5083         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5084
5085         if (INTEL_INFO(dev)->gen == 9)
5086                 skylake_pfit_update(intel_crtc, 0);
5087         else if (INTEL_INFO(dev)->gen < 9)
5088                 ironlake_pfit_disable(intel_crtc);
5089         else
5090                 MISSING_CASE(INTEL_INFO(dev)->gen);
5091
5092         intel_ddi_disable_pipe_clock(intel_crtc);
5093
5094         if (intel_crtc->config->has_pch_encoder) {
5095                 lpt_disable_pch_transcoder(dev_priv);
5096                 intel_ddi_fdi_disable(crtc);
5097         }
5098
5099         for_each_encoder_on_crtc(dev, crtc, encoder)
5100                 if (encoder->post_disable)
5101                         encoder->post_disable(encoder);
5102 }
5103
5104 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5105 {
5106         struct drm_device *dev = crtc->base.dev;
5107         struct drm_i915_private *dev_priv = dev->dev_private;
5108         struct intel_crtc_state *pipe_config = crtc->config;
5109
5110         if (!pipe_config->gmch_pfit.control)
5111                 return;
5112
5113         /*
5114          * The panel fitter should only be adjusted whilst the pipe is disabled,
5115          * according to register description and PRM.
5116          */
5117         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5118         assert_pipe_disabled(dev_priv, crtc->pipe);
5119
5120         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5121         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5122
5123         /* Border color in case we don't scale up to the full screen. Black by
5124          * default, change to something else for debugging. */
5125         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5126 }
5127
5128 static enum intel_display_power_domain port_to_power_domain(enum port port)
5129 {
5130         switch (port) {
5131         case PORT_A:
5132                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5133         case PORT_B:
5134                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5135         case PORT_C:
5136                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5137         case PORT_D:
5138                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5139         default:
5140                 WARN_ON_ONCE(1);
5141                 return POWER_DOMAIN_PORT_OTHER;
5142         }
5143 }
5144
5145 #define for_each_power_domain(domain, mask)                             \
5146         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5147                 if ((1 << (domain)) & (mask))
5148
5149 enum intel_display_power_domain
5150 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5151 {
5152         struct drm_device *dev = intel_encoder->base.dev;
5153         struct intel_digital_port *intel_dig_port;
5154
5155         switch (intel_encoder->type) {
5156         case INTEL_OUTPUT_UNKNOWN:
5157                 /* Only DDI platforms should ever use this output type */
5158                 WARN_ON_ONCE(!HAS_DDI(dev));
5159         case INTEL_OUTPUT_DISPLAYPORT:
5160         case INTEL_OUTPUT_HDMI:
5161         case INTEL_OUTPUT_EDP:
5162                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5163                 return port_to_power_domain(intel_dig_port->port);
5164         case INTEL_OUTPUT_DP_MST:
5165                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5166                 return port_to_power_domain(intel_dig_port->port);
5167         case INTEL_OUTPUT_ANALOG:
5168                 return POWER_DOMAIN_PORT_CRT;
5169         case INTEL_OUTPUT_DSI:
5170                 return POWER_DOMAIN_PORT_DSI;
5171         default:
5172                 return POWER_DOMAIN_PORT_OTHER;
5173         }
5174 }
5175
5176 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5177 {
5178         struct drm_device *dev = crtc->dev;
5179         struct intel_encoder *intel_encoder;
5180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5181         enum pipe pipe = intel_crtc->pipe;
5182         unsigned long mask;
5183         enum transcoder transcoder;
5184
5185         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5186
5187         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5188         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5189         if (intel_crtc->config->pch_pfit.enabled ||
5190             intel_crtc->config->pch_pfit.force_thru)
5191                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5192
5193         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5194                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5195
5196         return mask;
5197 }
5198
5199 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5200 {
5201         struct drm_device *dev = state->dev;
5202         struct drm_i915_private *dev_priv = dev->dev_private;
5203         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5204         struct intel_crtc *crtc;
5205
5206         /*
5207          * First get all needed power domains, then put all unneeded, to avoid
5208          * any unnecessary toggling of the power wells.
5209          */
5210         for_each_intel_crtc(dev, crtc) {
5211                 enum intel_display_power_domain domain;
5212
5213                 if (!crtc->base.state->enable)
5214                         continue;
5215
5216                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5217
5218                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5219                         intel_display_power_get(dev_priv, domain);
5220         }
5221
5222         if (dev_priv->display.modeset_commit_cdclk) {
5223                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5224
5225                 if (cdclk != dev_priv->cdclk_freq &&
5226                     !WARN_ON(!state->allow_modeset))
5227                         dev_priv->display.modeset_commit_cdclk(state);
5228         }
5229
5230         for_each_intel_crtc(dev, crtc) {
5231                 enum intel_display_power_domain domain;
5232
5233                 for_each_power_domain(domain, crtc->enabled_power_domains)
5234                         intel_display_power_put(dev_priv, domain);
5235
5236                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5237         }
5238
5239         intel_display_set_init_power(dev_priv, false);
5240 }
5241
5242 static void intel_update_max_cdclk(struct drm_device *dev)
5243 {
5244         struct drm_i915_private *dev_priv = dev->dev_private;
5245
5246         if (IS_SKYLAKE(dev)) {
5247                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5248
5249                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5250                         dev_priv->max_cdclk_freq = 675000;
5251                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5252                         dev_priv->max_cdclk_freq = 540000;
5253                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5254                         dev_priv->max_cdclk_freq = 450000;
5255                 else
5256                         dev_priv->max_cdclk_freq = 337500;
5257         } else if (IS_BROADWELL(dev))  {
5258                 /*
5259                  * FIXME with extra cooling we can allow
5260                  * 540 MHz for ULX and 675 Mhz for ULT.
5261                  * How can we know if extra cooling is
5262                  * available? PCI ID, VTB, something else?
5263                  */
5264                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5265                         dev_priv->max_cdclk_freq = 450000;
5266                 else if (IS_BDW_ULX(dev))
5267                         dev_priv->max_cdclk_freq = 450000;
5268                 else if (IS_BDW_ULT(dev))
5269                         dev_priv->max_cdclk_freq = 540000;
5270                 else
5271                         dev_priv->max_cdclk_freq = 675000;
5272         } else if (IS_CHERRYVIEW(dev)) {
5273                 dev_priv->max_cdclk_freq = 320000;
5274         } else if (IS_VALLEYVIEW(dev)) {
5275                 dev_priv->max_cdclk_freq = 400000;
5276         } else {
5277                 /* otherwise assume cdclk is fixed */
5278                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5279         }
5280
5281         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5282                          dev_priv->max_cdclk_freq);
5283 }
5284
5285 static void intel_update_cdclk(struct drm_device *dev)
5286 {
5287         struct drm_i915_private *dev_priv = dev->dev_private;
5288
5289         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5290         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5291                          dev_priv->cdclk_freq);
5292
5293         /*
5294          * Program the gmbus_freq based on the cdclk frequency.
5295          * BSpec erroneously claims we should aim for 4MHz, but
5296          * in fact 1MHz is the correct frequency.
5297          */
5298         if (IS_VALLEYVIEW(dev)) {
5299                 /*
5300                  * Program the gmbus_freq based on the cdclk frequency.
5301                  * BSpec erroneously claims we should aim for 4MHz, but
5302                  * in fact 1MHz is the correct frequency.
5303                  */
5304                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5305         }
5306
5307         if (dev_priv->max_cdclk_freq == 0)
5308                 intel_update_max_cdclk(dev);
5309 }
5310
5311 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5312 {
5313         struct drm_i915_private *dev_priv = dev->dev_private;
5314         uint32_t divider;
5315         uint32_t ratio;
5316         uint32_t current_freq;
5317         int ret;
5318
5319         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5320         switch (frequency) {
5321         case 144000:
5322                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5323                 ratio = BXT_DE_PLL_RATIO(60);
5324                 break;
5325         case 288000:
5326                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5327                 ratio = BXT_DE_PLL_RATIO(60);
5328                 break;
5329         case 384000:
5330                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5331                 ratio = BXT_DE_PLL_RATIO(60);
5332                 break;
5333         case 576000:
5334                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5335                 ratio = BXT_DE_PLL_RATIO(60);
5336                 break;
5337         case 624000:
5338                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5339                 ratio = BXT_DE_PLL_RATIO(65);
5340                 break;
5341         case 19200:
5342                 /*
5343                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5344                  * to suppress GCC warning.
5345                  */
5346                 ratio = 0;
5347                 divider = 0;
5348                 break;
5349         default:
5350                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5351
5352                 return;
5353         }
5354
5355         mutex_lock(&dev_priv->rps.hw_lock);
5356         /* Inform power controller of upcoming frequency change */
5357         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5358                                       0x80000000);
5359         mutex_unlock(&dev_priv->rps.hw_lock);
5360
5361         if (ret) {
5362                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5363                           ret, frequency);
5364                 return;
5365         }
5366
5367         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5368         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5369         current_freq = current_freq * 500 + 1000;
5370
5371         /*
5372          * DE PLL has to be disabled when
5373          * - setting to 19.2MHz (bypass, PLL isn't used)
5374          * - before setting to 624MHz (PLL needs toggling)
5375          * - before setting to any frequency from 624MHz (PLL needs toggling)
5376          */
5377         if (frequency == 19200 || frequency == 624000 ||
5378             current_freq == 624000) {
5379                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5380                 /* Timeout 200us */
5381                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5382                              1))
5383                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5384         }
5385
5386         if (frequency != 19200) {
5387                 uint32_t val;
5388
5389                 val = I915_READ(BXT_DE_PLL_CTL);
5390                 val &= ~BXT_DE_PLL_RATIO_MASK;
5391                 val |= ratio;
5392                 I915_WRITE(BXT_DE_PLL_CTL, val);
5393
5394                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5395                 /* Timeout 200us */
5396                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5397                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5398
5399                 val = I915_READ(CDCLK_CTL);
5400                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5401                 val |= divider;
5402                 /*
5403                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5404                  * enable otherwise.
5405                  */
5406                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5407                 if (frequency >= 500000)
5408                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5409
5410                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5411                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5412                 val |= (frequency - 1000) / 500;
5413                 I915_WRITE(CDCLK_CTL, val);
5414         }
5415
5416         mutex_lock(&dev_priv->rps.hw_lock);
5417         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5418                                       DIV_ROUND_UP(frequency, 25000));
5419         mutex_unlock(&dev_priv->rps.hw_lock);
5420
5421         if (ret) {
5422                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5423                           ret, frequency);
5424                 return;
5425         }
5426
5427         intel_update_cdclk(dev);
5428 }
5429
5430 void broxton_init_cdclk(struct drm_device *dev)
5431 {
5432         struct drm_i915_private *dev_priv = dev->dev_private;
5433         uint32_t val;
5434
5435         /*
5436          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5437          * or else the reset will hang because there is no PCH to respond.
5438          * Move the handshake programming to initialization sequence.
5439          * Previously was left up to BIOS.
5440          */
5441         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5442         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5443         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5444
5445         /* Enable PG1 for cdclk */
5446         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5447
5448         /* check if cd clock is enabled */
5449         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5450                 DRM_DEBUG_KMS("Display already initialized\n");
5451                 return;
5452         }
5453
5454         /*
5455          * FIXME:
5456          * - The initial CDCLK needs to be read from VBT.
5457          *   Need to make this change after VBT has changes for BXT.
5458          * - check if setting the max (or any) cdclk freq is really necessary
5459          *   here, it belongs to modeset time
5460          */
5461         broxton_set_cdclk(dev, 624000);
5462
5463         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5464         POSTING_READ(DBUF_CTL);
5465
5466         udelay(10);
5467
5468         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5469                 DRM_ERROR("DBuf power enable timeout!\n");
5470 }
5471
5472 void broxton_uninit_cdclk(struct drm_device *dev)
5473 {
5474         struct drm_i915_private *dev_priv = dev->dev_private;
5475
5476         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5477         POSTING_READ(DBUF_CTL);
5478
5479         udelay(10);
5480
5481         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5482                 DRM_ERROR("DBuf power disable timeout!\n");
5483
5484         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5485         broxton_set_cdclk(dev, 19200);
5486
5487         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5488 }
5489
5490 static const struct skl_cdclk_entry {
5491         unsigned int freq;
5492         unsigned int vco;
5493 } skl_cdclk_frequencies[] = {
5494         { .freq = 308570, .vco = 8640 },
5495         { .freq = 337500, .vco = 8100 },
5496         { .freq = 432000, .vco = 8640 },
5497         { .freq = 450000, .vco = 8100 },
5498         { .freq = 540000, .vco = 8100 },
5499         { .freq = 617140, .vco = 8640 },
5500         { .freq = 675000, .vco = 8100 },
5501 };
5502
5503 static unsigned int skl_cdclk_decimal(unsigned int freq)
5504 {
5505         return (freq - 1000) / 500;
5506 }
5507
5508 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5509 {
5510         unsigned int i;
5511
5512         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5513                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5514
5515                 if (e->freq == freq)
5516                         return e->vco;
5517         }
5518
5519         return 8100;
5520 }
5521
5522 static void
5523 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5524 {
5525         unsigned int min_freq;
5526         u32 val;
5527
5528         /* select the minimum CDCLK before enabling DPLL 0 */
5529         val = I915_READ(CDCLK_CTL);
5530         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5531         val |= CDCLK_FREQ_337_308;
5532
5533         if (required_vco == 8640)
5534                 min_freq = 308570;
5535         else
5536                 min_freq = 337500;
5537
5538         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5539
5540         I915_WRITE(CDCLK_CTL, val);
5541         POSTING_READ(CDCLK_CTL);
5542
5543         /*
5544          * We always enable DPLL0 with the lowest link rate possible, but still
5545          * taking into account the VCO required to operate the eDP panel at the
5546          * desired frequency. The usual DP link rates operate with a VCO of
5547          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5548          * The modeset code is responsible for the selection of the exact link
5549          * rate later on, with the constraint of choosing a frequency that
5550          * works with required_vco.
5551          */
5552         val = I915_READ(DPLL_CTRL1);
5553
5554         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5555                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5556         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5557         if (required_vco == 8640)
5558                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5559                                             SKL_DPLL0);
5560         else
5561                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5562                                             SKL_DPLL0);
5563
5564         I915_WRITE(DPLL_CTRL1, val);
5565         POSTING_READ(DPLL_CTRL1);
5566
5567         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5568
5569         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5570                 DRM_ERROR("DPLL0 not locked\n");
5571 }
5572
5573 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5574 {
5575         int ret;
5576         u32 val;
5577
5578         /* inform PCU we want to change CDCLK */
5579         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5580         mutex_lock(&dev_priv->rps.hw_lock);
5581         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5582         mutex_unlock(&dev_priv->rps.hw_lock);
5583
5584         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5585 }
5586
5587 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5588 {
5589         unsigned int i;
5590
5591         for (i = 0; i < 15; i++) {
5592                 if (skl_cdclk_pcu_ready(dev_priv))
5593                         return true;
5594                 udelay(10);
5595         }
5596
5597         return false;
5598 }
5599
5600 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5601 {
5602         struct drm_device *dev = dev_priv->dev;
5603         u32 freq_select, pcu_ack;
5604
5605         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5606
5607         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5608                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5609                 return;
5610         }
5611
5612         /* set CDCLK_CTL */
5613         switch(freq) {
5614         case 450000:
5615         case 432000:
5616                 freq_select = CDCLK_FREQ_450_432;
5617                 pcu_ack = 1;
5618                 break;
5619         case 540000:
5620                 freq_select = CDCLK_FREQ_540;
5621                 pcu_ack = 2;
5622                 break;
5623         case 308570:
5624         case 337500:
5625         default:
5626                 freq_select = CDCLK_FREQ_337_308;
5627                 pcu_ack = 0;
5628                 break;
5629         case 617140:
5630         case 675000:
5631                 freq_select = CDCLK_FREQ_675_617;
5632                 pcu_ack = 3;
5633                 break;
5634         }
5635
5636         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5637         POSTING_READ(CDCLK_CTL);
5638
5639         /* inform PCU of the change */
5640         mutex_lock(&dev_priv->rps.hw_lock);
5641         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5642         mutex_unlock(&dev_priv->rps.hw_lock);
5643
5644         intel_update_cdclk(dev);
5645 }
5646
5647 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5648 {
5649         /* disable DBUF power */
5650         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5651         POSTING_READ(DBUF_CTL);
5652
5653         udelay(10);
5654
5655         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5656                 DRM_ERROR("DBuf power disable timeout\n");
5657
5658         /* disable DPLL0 */
5659         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5660         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5661                 DRM_ERROR("Couldn't disable DPLL0\n");
5662
5663         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5664 }
5665
5666 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5667 {
5668         u32 val;
5669         unsigned int required_vco;
5670
5671         /* enable PCH reset handshake */
5672         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5673         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5674
5675         /* enable PG1 and Misc I/O */
5676         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5677
5678         /* DPLL0 already enabed !? */
5679         if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5680                 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5681                 return;
5682         }
5683
5684         /* enable DPLL0 */
5685         required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5686         skl_dpll0_enable(dev_priv, required_vco);
5687
5688         /* set CDCLK to the frequency the BIOS chose */
5689         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5690
5691         /* enable DBUF power */
5692         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5693         POSTING_READ(DBUF_CTL);
5694
5695         udelay(10);
5696
5697         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5698                 DRM_ERROR("DBuf power enable timeout\n");
5699 }
5700
5701 /* returns HPLL frequency in kHz */
5702 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5703 {
5704         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5705
5706         /* Obtain SKU information */
5707         mutex_lock(&dev_priv->sb_lock);
5708         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5709                 CCK_FUSE_HPLL_FREQ_MASK;
5710         mutex_unlock(&dev_priv->sb_lock);
5711
5712         return vco_freq[hpll_freq] * 1000;
5713 }
5714
5715 /* Adjust CDclk dividers to allow high res or save power if possible */
5716 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5717 {
5718         struct drm_i915_private *dev_priv = dev->dev_private;
5719         u32 val, cmd;
5720
5721         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5722                                         != dev_priv->cdclk_freq);
5723
5724         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5725                 cmd = 2;
5726         else if (cdclk == 266667)
5727                 cmd = 1;
5728         else
5729                 cmd = 0;
5730
5731         mutex_lock(&dev_priv->rps.hw_lock);
5732         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5733         val &= ~DSPFREQGUAR_MASK;
5734         val |= (cmd << DSPFREQGUAR_SHIFT);
5735         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5736         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5737                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5738                      50)) {
5739                 DRM_ERROR("timed out waiting for CDclk change\n");
5740         }
5741         mutex_unlock(&dev_priv->rps.hw_lock);
5742
5743         mutex_lock(&dev_priv->sb_lock);
5744
5745         if (cdclk == 400000) {
5746                 u32 divider;
5747
5748                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5749
5750                 /* adjust cdclk divider */
5751                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5752                 val &= ~DISPLAY_FREQUENCY_VALUES;
5753                 val |= divider;
5754                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5755
5756                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5757                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5758                              50))
5759                         DRM_ERROR("timed out waiting for CDclk change\n");
5760         }
5761
5762         /* adjust self-refresh exit latency value */
5763         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5764         val &= ~0x7f;
5765
5766         /*
5767          * For high bandwidth configs, we set a higher latency in the bunit
5768          * so that the core display fetch happens in time to avoid underruns.
5769          */
5770         if (cdclk == 400000)
5771                 val |= 4500 / 250; /* 4.5 usec */
5772         else
5773                 val |= 3000 / 250; /* 3.0 usec */
5774         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5775
5776         mutex_unlock(&dev_priv->sb_lock);
5777
5778         intel_update_cdclk(dev);
5779 }
5780
5781 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5782 {
5783         struct drm_i915_private *dev_priv = dev->dev_private;
5784         u32 val, cmd;
5785
5786         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5787                                                 != dev_priv->cdclk_freq);
5788
5789         switch (cdclk) {
5790         case 333333:
5791         case 320000:
5792         case 266667:
5793         case 200000:
5794                 break;
5795         default:
5796                 MISSING_CASE(cdclk);
5797                 return;
5798         }
5799
5800         /*
5801          * Specs are full of misinformation, but testing on actual
5802          * hardware has shown that we just need to write the desired
5803          * CCK divider into the Punit register.
5804          */
5805         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5806
5807         mutex_lock(&dev_priv->rps.hw_lock);
5808         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5809         val &= ~DSPFREQGUAR_MASK_CHV;
5810         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5811         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5812         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5813                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5814                      50)) {
5815                 DRM_ERROR("timed out waiting for CDclk change\n");
5816         }
5817         mutex_unlock(&dev_priv->rps.hw_lock);
5818
5819         intel_update_cdclk(dev);
5820 }
5821
5822 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5823                                  int max_pixclk)
5824 {
5825         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5826         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5827
5828         /*
5829          * Really only a few cases to deal with, as only 4 CDclks are supported:
5830          *   200MHz
5831          *   267MHz
5832          *   320/333MHz (depends on HPLL freq)
5833          *   400MHz (VLV only)
5834          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5835          * of the lower bin and adjust if needed.
5836          *
5837          * We seem to get an unstable or solid color picture at 200MHz.
5838          * Not sure what's wrong. For now use 200MHz only when all pipes
5839          * are off.
5840          */
5841         if (!IS_CHERRYVIEW(dev_priv) &&
5842             max_pixclk > freq_320*limit/100)
5843                 return 400000;
5844         else if (max_pixclk > 266667*limit/100)
5845                 return freq_320;
5846         else if (max_pixclk > 0)
5847                 return 266667;
5848         else
5849                 return 200000;
5850 }
5851
5852 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5853                               int max_pixclk)
5854 {
5855         /*
5856          * FIXME:
5857          * - remove the guardband, it's not needed on BXT
5858          * - set 19.2MHz bypass frequency if there are no active pipes
5859          */
5860         if (max_pixclk > 576000*9/10)
5861                 return 624000;
5862         else if (max_pixclk > 384000*9/10)
5863                 return 576000;
5864         else if (max_pixclk > 288000*9/10)
5865                 return 384000;
5866         else if (max_pixclk > 144000*9/10)
5867                 return 288000;
5868         else
5869                 return 144000;
5870 }
5871
5872 /* Compute the max pixel clock for new configuration. Uses atomic state if
5873  * that's non-NULL, look at current state otherwise. */
5874 static int intel_mode_max_pixclk(struct drm_device *dev,
5875                                  struct drm_atomic_state *state)
5876 {
5877         struct intel_crtc *intel_crtc;
5878         struct intel_crtc_state *crtc_state;
5879         int max_pixclk = 0;
5880
5881         for_each_intel_crtc(dev, intel_crtc) {
5882                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5883                 if (IS_ERR(crtc_state))
5884                         return PTR_ERR(crtc_state);
5885
5886                 if (!crtc_state->base.enable)
5887                         continue;
5888
5889                 max_pixclk = max(max_pixclk,
5890                                  crtc_state->base.adjusted_mode.crtc_clock);
5891         }
5892
5893         return max_pixclk;
5894 }
5895
5896 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5897 {
5898         struct drm_device *dev = state->dev;
5899         struct drm_i915_private *dev_priv = dev->dev_private;
5900         int max_pixclk = intel_mode_max_pixclk(dev, state);
5901
5902         if (max_pixclk < 0)
5903                 return max_pixclk;
5904
5905         to_intel_atomic_state(state)->cdclk =
5906                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5907
5908         return 0;
5909 }
5910
5911 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5912 {
5913         struct drm_device *dev = state->dev;
5914         struct drm_i915_private *dev_priv = dev->dev_private;
5915         int max_pixclk = intel_mode_max_pixclk(dev, state);
5916
5917         if (max_pixclk < 0)
5918                 return max_pixclk;
5919
5920         to_intel_atomic_state(state)->cdclk =
5921                 broxton_calc_cdclk(dev_priv, max_pixclk);
5922
5923         return 0;
5924 }
5925
5926 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5927 {
5928         unsigned int credits, default_credits;
5929
5930         if (IS_CHERRYVIEW(dev_priv))
5931                 default_credits = PFI_CREDIT(12);
5932         else
5933                 default_credits = PFI_CREDIT(8);
5934
5935         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5936                 /* CHV suggested value is 31 or 63 */
5937                 if (IS_CHERRYVIEW(dev_priv))
5938                         credits = PFI_CREDIT_63;
5939                 else
5940                         credits = PFI_CREDIT(15);
5941         } else {
5942                 credits = default_credits;
5943         }
5944
5945         /*
5946          * WA - write default credits before re-programming
5947          * FIXME: should we also set the resend bit here?
5948          */
5949         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5950                    default_credits);
5951
5952         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5953                    credits | PFI_CREDIT_RESEND);
5954
5955         /*
5956          * FIXME is this guaranteed to clear
5957          * immediately or should we poll for it?
5958          */
5959         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5960 }
5961
5962 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5963 {
5964         struct drm_device *dev = old_state->dev;
5965         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5966         struct drm_i915_private *dev_priv = dev->dev_private;
5967
5968         /*
5969          * FIXME: We can end up here with all power domains off, yet
5970          * with a CDCLK frequency other than the minimum. To account
5971          * for this take the PIPE-A power domain, which covers the HW
5972          * blocks needed for the following programming. This can be
5973          * removed once it's guaranteed that we get here either with
5974          * the minimum CDCLK set, or the required power domains
5975          * enabled.
5976          */
5977         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5978
5979         if (IS_CHERRYVIEW(dev))
5980                 cherryview_set_cdclk(dev, req_cdclk);
5981         else
5982                 valleyview_set_cdclk(dev, req_cdclk);
5983
5984         vlv_program_pfi_credits(dev_priv);
5985
5986         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5987 }
5988
5989 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5990 {
5991         struct drm_device *dev = crtc->dev;
5992         struct drm_i915_private *dev_priv = to_i915(dev);
5993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5994         struct intel_encoder *encoder;
5995         int pipe = intel_crtc->pipe;
5996         bool is_dsi;
5997
5998         if (WARN_ON(intel_crtc->active))
5999                 return;
6000
6001         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6002
6003         if (!is_dsi) {
6004                 if (IS_CHERRYVIEW(dev))
6005                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6006                 else
6007                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6008         }
6009
6010         if (intel_crtc->config->has_dp_encoder)
6011                 intel_dp_set_m_n(intel_crtc, M1_N1);
6012
6013         intel_set_pipe_timings(intel_crtc);
6014
6015         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6016                 struct drm_i915_private *dev_priv = dev->dev_private;
6017
6018                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6019                 I915_WRITE(CHV_CANVAS(pipe), 0);
6020         }
6021
6022         i9xx_set_pipeconf(intel_crtc);
6023
6024         intel_crtc->active = true;
6025
6026         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6027
6028         for_each_encoder_on_crtc(dev, crtc, encoder)
6029                 if (encoder->pre_pll_enable)
6030                         encoder->pre_pll_enable(encoder);
6031
6032         if (!is_dsi) {
6033                 if (IS_CHERRYVIEW(dev))
6034                         chv_enable_pll(intel_crtc, intel_crtc->config);
6035                 else
6036                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6037         }
6038
6039         for_each_encoder_on_crtc(dev, crtc, encoder)
6040                 if (encoder->pre_enable)
6041                         encoder->pre_enable(encoder);
6042
6043         i9xx_pfit_enable(intel_crtc);
6044
6045         intel_crtc_load_lut(crtc);
6046
6047         intel_enable_pipe(intel_crtc);
6048
6049         assert_vblank_disabled(crtc);
6050         drm_crtc_vblank_on(crtc);
6051
6052         for_each_encoder_on_crtc(dev, crtc, encoder)
6053                 encoder->enable(encoder);
6054 }
6055
6056 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6057 {
6058         struct drm_device *dev = crtc->base.dev;
6059         struct drm_i915_private *dev_priv = dev->dev_private;
6060
6061         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6062         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6063 }
6064
6065 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6066 {
6067         struct drm_device *dev = crtc->dev;
6068         struct drm_i915_private *dev_priv = to_i915(dev);
6069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6070         struct intel_encoder *encoder;
6071         int pipe = intel_crtc->pipe;
6072
6073         if (WARN_ON(intel_crtc->active))
6074                 return;
6075
6076         i9xx_set_pll_dividers(intel_crtc);
6077
6078         if (intel_crtc->config->has_dp_encoder)
6079                 intel_dp_set_m_n(intel_crtc, M1_N1);
6080
6081         intel_set_pipe_timings(intel_crtc);
6082
6083         i9xx_set_pipeconf(intel_crtc);
6084
6085         intel_crtc->active = true;
6086
6087         if (!IS_GEN2(dev))
6088                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6089
6090         for_each_encoder_on_crtc(dev, crtc, encoder)
6091                 if (encoder->pre_enable)
6092                         encoder->pre_enable(encoder);
6093
6094         i9xx_enable_pll(intel_crtc);
6095
6096         i9xx_pfit_enable(intel_crtc);
6097
6098         intel_crtc_load_lut(crtc);
6099
6100         intel_update_watermarks(crtc);
6101         intel_enable_pipe(intel_crtc);
6102
6103         assert_vblank_disabled(crtc);
6104         drm_crtc_vblank_on(crtc);
6105
6106         for_each_encoder_on_crtc(dev, crtc, encoder)
6107                 encoder->enable(encoder);
6108 }
6109
6110 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6111 {
6112         struct drm_device *dev = crtc->base.dev;
6113         struct drm_i915_private *dev_priv = dev->dev_private;
6114
6115         if (!crtc->config->gmch_pfit.control)
6116                 return;
6117
6118         assert_pipe_disabled(dev_priv, crtc->pipe);
6119
6120         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6121                          I915_READ(PFIT_CONTROL));
6122         I915_WRITE(PFIT_CONTROL, 0);
6123 }
6124
6125 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6126 {
6127         struct drm_device *dev = crtc->dev;
6128         struct drm_i915_private *dev_priv = dev->dev_private;
6129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6130         struct intel_encoder *encoder;
6131         int pipe = intel_crtc->pipe;
6132
6133         /*
6134          * On gen2 planes are double buffered but the pipe isn't, so we must
6135          * wait for planes to fully turn off before disabling the pipe.
6136          * We also need to wait on all gmch platforms because of the
6137          * self-refresh mode constraint explained above.
6138          */
6139         intel_wait_for_vblank(dev, pipe);
6140
6141         for_each_encoder_on_crtc(dev, crtc, encoder)
6142                 encoder->disable(encoder);
6143
6144         drm_crtc_vblank_off(crtc);
6145         assert_vblank_disabled(crtc);
6146
6147         intel_disable_pipe(intel_crtc);
6148
6149         i9xx_pfit_disable(intel_crtc);
6150
6151         for_each_encoder_on_crtc(dev, crtc, encoder)
6152                 if (encoder->post_disable)
6153                         encoder->post_disable(encoder);
6154
6155         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6156                 if (IS_CHERRYVIEW(dev))
6157                         chv_disable_pll(dev_priv, pipe);
6158                 else if (IS_VALLEYVIEW(dev))
6159                         vlv_disable_pll(dev_priv, pipe);
6160                 else
6161                         i9xx_disable_pll(intel_crtc);
6162         }
6163
6164         if (!IS_GEN2(dev))
6165                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6166 }
6167
6168 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6169 {
6170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6171         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6172         enum intel_display_power_domain domain;
6173         unsigned long domains;
6174
6175         if (!intel_crtc->active)
6176                 return;
6177
6178         if (to_intel_plane_state(crtc->primary->state)->visible) {
6179                 intel_crtc_wait_for_pending_flips(crtc);
6180                 intel_pre_disable_primary(crtc);
6181         }
6182
6183         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6184         dev_priv->display.crtc_disable(crtc);
6185
6186         domains = intel_crtc->enabled_power_domains;
6187         for_each_power_domain(domain, domains)
6188                 intel_display_power_put(dev_priv, domain);
6189         intel_crtc->enabled_power_domains = 0;
6190 }
6191
6192 /*
6193  * turn all crtc's off, but do not adjust state
6194  * This has to be paired with a call to intel_modeset_setup_hw_state.
6195  */
6196 void intel_display_suspend(struct drm_device *dev)
6197 {
6198         struct drm_crtc *crtc;
6199
6200         for_each_crtc(dev, crtc)
6201                 intel_crtc_disable_noatomic(crtc);
6202 }
6203
6204 /* Master function to enable/disable CRTC and corresponding power wells */
6205 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6206 {
6207         struct drm_device *dev = crtc->dev;
6208         struct drm_mode_config *config = &dev->mode_config;
6209         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6211         struct intel_crtc_state *pipe_config;
6212         struct drm_atomic_state *state;
6213         int ret;
6214
6215         if (enable == intel_crtc->active)
6216                 return 0;
6217
6218         if (enable && !crtc->state->enable)
6219                 return 0;
6220
6221         /* this function should be called with drm_modeset_lock_all for now */
6222         if (WARN_ON(!ctx))
6223                 return -EIO;
6224         lockdep_assert_held(&ctx->ww_ctx);
6225
6226         state = drm_atomic_state_alloc(dev);
6227         if (WARN_ON(!state))
6228                 return -ENOMEM;
6229
6230         state->acquire_ctx = ctx;
6231         state->allow_modeset = true;
6232
6233         pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6234         if (IS_ERR(pipe_config)) {
6235                 ret = PTR_ERR(pipe_config);
6236                 goto err;
6237         }
6238         pipe_config->base.active = enable;
6239
6240         ret = intel_set_mode(state);
6241         if (!ret)
6242                 return ret;
6243
6244 err:
6245         DRM_ERROR("Updating crtc active failed with %i\n", ret);
6246         drm_atomic_state_free(state);
6247         return ret;
6248 }
6249
6250 /**
6251  * Sets the power management mode of the pipe and plane.
6252  */
6253 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6254 {
6255         struct drm_device *dev = crtc->dev;
6256         struct intel_encoder *intel_encoder;
6257         bool enable = false;
6258
6259         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6260                 enable |= intel_encoder->connectors_active;
6261
6262         intel_crtc_control(crtc, enable);
6263 }
6264
6265 void intel_encoder_destroy(struct drm_encoder *encoder)
6266 {
6267         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6268
6269         drm_encoder_cleanup(encoder);
6270         kfree(intel_encoder);
6271 }
6272
6273 /* Simple dpms helper for encoders with just one connector, no cloning and only
6274  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6275  * state of the entire output pipe. */
6276 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6277 {
6278         if (mode == DRM_MODE_DPMS_ON) {
6279                 encoder->connectors_active = true;
6280
6281                 intel_crtc_update_dpms(encoder->base.crtc);
6282         } else {
6283                 encoder->connectors_active = false;
6284
6285                 intel_crtc_update_dpms(encoder->base.crtc);
6286         }
6287 }
6288
6289 /* Cross check the actual hw state with our own modeset state tracking (and it's
6290  * internal consistency). */
6291 static void intel_connector_check_state(struct intel_connector *connector)
6292 {
6293         if (connector->get_hw_state(connector)) {
6294                 struct intel_encoder *encoder = connector->encoder;
6295                 struct drm_crtc *crtc;
6296                 bool encoder_enabled;
6297                 enum pipe pipe;
6298
6299                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6300                               connector->base.base.id,
6301                               connector->base.name);
6302
6303                 /* there is no real hw state for MST connectors */
6304                 if (connector->mst_port)
6305                         return;
6306
6307                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6308                      "wrong connector dpms state\n");
6309                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6310                      "active connector not linked to encoder\n");
6311
6312                 if (encoder) {
6313                         I915_STATE_WARN(!encoder->connectors_active,
6314                              "encoder->connectors_active not set\n");
6315
6316                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6317                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6318                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
6319                                 return;
6320
6321                         crtc = encoder->base.crtc;
6322
6323                         I915_STATE_WARN(!crtc->state->enable,
6324                                         "crtc not enabled\n");
6325                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6326                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6327                              "encoder active on the wrong pipe\n");
6328                 }
6329         }
6330 }
6331
6332 int intel_connector_init(struct intel_connector *connector)
6333 {
6334         struct drm_connector_state *connector_state;
6335
6336         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6337         if (!connector_state)
6338                 return -ENOMEM;
6339
6340         connector->base.state = connector_state;
6341         return 0;
6342 }
6343
6344 struct intel_connector *intel_connector_alloc(void)
6345 {
6346         struct intel_connector *connector;
6347
6348         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6349         if (!connector)
6350                 return NULL;
6351
6352         if (intel_connector_init(connector) < 0) {
6353                 kfree(connector);
6354                 return NULL;
6355         }
6356
6357         return connector;
6358 }
6359
6360 /* Even simpler default implementation, if there's really no special case to
6361  * consider. */
6362 void intel_connector_dpms(struct drm_connector *connector, int mode)
6363 {
6364         /* All the simple cases only support two dpms states. */
6365         if (mode != DRM_MODE_DPMS_ON)
6366                 mode = DRM_MODE_DPMS_OFF;
6367
6368         if (mode == connector->dpms)
6369                 return;
6370
6371         connector->dpms = mode;
6372
6373         /* Only need to change hw state when actually enabled */
6374         if (connector->encoder)
6375                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6376
6377         intel_modeset_check_state(connector->dev);
6378 }
6379
6380 /* Simple connector->get_hw_state implementation for encoders that support only
6381  * one connector and no cloning and hence the encoder state determines the state
6382  * of the connector. */
6383 bool intel_connector_get_hw_state(struct intel_connector *connector)
6384 {
6385         enum pipe pipe = 0;
6386         struct intel_encoder *encoder = connector->encoder;
6387
6388         return encoder->get_hw_state(encoder, &pipe);
6389 }
6390
6391 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6392 {
6393         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6394                 return crtc_state->fdi_lanes;
6395
6396         return 0;
6397 }
6398
6399 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6400                                      struct intel_crtc_state *pipe_config)
6401 {
6402         struct drm_atomic_state *state = pipe_config->base.state;
6403         struct intel_crtc *other_crtc;
6404         struct intel_crtc_state *other_crtc_state;
6405
6406         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6407                       pipe_name(pipe), pipe_config->fdi_lanes);
6408         if (pipe_config->fdi_lanes > 4) {
6409                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6410                               pipe_name(pipe), pipe_config->fdi_lanes);
6411                 return -EINVAL;
6412         }
6413
6414         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6415                 if (pipe_config->fdi_lanes > 2) {
6416                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6417                                       pipe_config->fdi_lanes);
6418                         return -EINVAL;
6419                 } else {
6420                         return 0;
6421                 }
6422         }
6423
6424         if (INTEL_INFO(dev)->num_pipes == 2)
6425                 return 0;
6426
6427         /* Ivybridge 3 pipe is really complicated */
6428         switch (pipe) {
6429         case PIPE_A:
6430                 return 0;
6431         case PIPE_B:
6432                 if (pipe_config->fdi_lanes <= 2)
6433                         return 0;
6434
6435                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6436                 other_crtc_state =
6437                         intel_atomic_get_crtc_state(state, other_crtc);
6438                 if (IS_ERR(other_crtc_state))
6439                         return PTR_ERR(other_crtc_state);
6440
6441                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6442                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6443                                       pipe_name(pipe), pipe_config->fdi_lanes);
6444                         return -EINVAL;
6445                 }
6446                 return 0;
6447         case PIPE_C:
6448                 if (pipe_config->fdi_lanes > 2) {
6449                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6450                                       pipe_name(pipe), pipe_config->fdi_lanes);
6451                         return -EINVAL;
6452                 }
6453
6454                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6455                 other_crtc_state =
6456                         intel_atomic_get_crtc_state(state, other_crtc);
6457                 if (IS_ERR(other_crtc_state))
6458                         return PTR_ERR(other_crtc_state);
6459
6460                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6461                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6462                         return -EINVAL;
6463                 }
6464                 return 0;
6465         default:
6466                 BUG();
6467         }
6468 }
6469
6470 #define RETRY 1
6471 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6472                                        struct intel_crtc_state *pipe_config)
6473 {
6474         struct drm_device *dev = intel_crtc->base.dev;
6475         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6476         int lane, link_bw, fdi_dotclock, ret;
6477         bool needs_recompute = false;
6478
6479 retry:
6480         /* FDI is a binary signal running at ~2.7GHz, encoding
6481          * each output octet as 10 bits. The actual frequency
6482          * is stored as a divider into a 100MHz clock, and the
6483          * mode pixel clock is stored in units of 1KHz.
6484          * Hence the bw of each lane in terms of the mode signal
6485          * is:
6486          */
6487         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6488
6489         fdi_dotclock = adjusted_mode->crtc_clock;
6490
6491         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6492                                            pipe_config->pipe_bpp);
6493
6494         pipe_config->fdi_lanes = lane;
6495
6496         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6497                                link_bw, &pipe_config->fdi_m_n);
6498
6499         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6500                                        intel_crtc->pipe, pipe_config);
6501         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6502                 pipe_config->pipe_bpp -= 2*3;
6503                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6504                               pipe_config->pipe_bpp);
6505                 needs_recompute = true;
6506                 pipe_config->bw_constrained = true;
6507
6508                 goto retry;
6509         }
6510
6511         if (needs_recompute)
6512                 return RETRY;
6513
6514         return ret;
6515 }
6516
6517 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6518                                      struct intel_crtc_state *pipe_config)
6519 {
6520         if (pipe_config->pipe_bpp > 24)
6521                 return false;
6522
6523         /* HSW can handle pixel rate up to cdclk? */
6524         if (IS_HASWELL(dev_priv->dev))
6525                 return true;
6526
6527         /*
6528          * We compare against max which means we must take
6529          * the increased cdclk requirement into account when
6530          * calculating the new cdclk.
6531          *
6532          * Should measure whether using a lower cdclk w/o IPS
6533          */
6534         return ilk_pipe_pixel_rate(pipe_config) <=
6535                 dev_priv->max_cdclk_freq * 95 / 100;
6536 }
6537
6538 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6539                                    struct intel_crtc_state *pipe_config)
6540 {
6541         struct drm_device *dev = crtc->base.dev;
6542         struct drm_i915_private *dev_priv = dev->dev_private;
6543
6544         pipe_config->ips_enabled = i915.enable_ips &&
6545                 hsw_crtc_supports_ips(crtc) &&
6546                 pipe_config_supports_ips(dev_priv, pipe_config);
6547 }
6548
6549 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6550                                      struct intel_crtc_state *pipe_config)
6551 {
6552         struct drm_device *dev = crtc->base.dev;
6553         struct drm_i915_private *dev_priv = dev->dev_private;
6554         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6555
6556         /* FIXME should check pixel clock limits on all platforms */
6557         if (INTEL_INFO(dev)->gen < 4) {
6558                 int clock_limit = dev_priv->max_cdclk_freq;
6559
6560                 /*
6561                  * Enable pixel doubling when the dot clock
6562                  * is > 90% of the (display) core speed.
6563                  *
6564                  * GDG double wide on either pipe,
6565                  * otherwise pipe A only.
6566                  */
6567                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6568                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6569                         clock_limit *= 2;
6570                         pipe_config->double_wide = true;
6571                 }
6572
6573                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6574                         return -EINVAL;
6575         }
6576
6577         /*
6578          * Pipe horizontal size must be even in:
6579          * - DVO ganged mode
6580          * - LVDS dual channel mode
6581          * - Double wide pipe
6582          */
6583         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6584              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6585                 pipe_config->pipe_src_w &= ~1;
6586
6587         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6588          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6589          */
6590         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6591                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6592                 return -EINVAL;
6593
6594         if (HAS_IPS(dev))
6595                 hsw_compute_ips_config(crtc, pipe_config);
6596
6597         if (pipe_config->has_pch_encoder)
6598                 return ironlake_fdi_compute_config(crtc, pipe_config);
6599
6600         return 0;
6601 }
6602
6603 static int skylake_get_display_clock_speed(struct drm_device *dev)
6604 {
6605         struct drm_i915_private *dev_priv = to_i915(dev);
6606         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6607         uint32_t cdctl = I915_READ(CDCLK_CTL);
6608         uint32_t linkrate;
6609
6610         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6611                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6612
6613         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6614                 return 540000;
6615
6616         linkrate = (I915_READ(DPLL_CTRL1) &
6617                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6618
6619         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6620             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6621                 /* vco 8640 */
6622                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6623                 case CDCLK_FREQ_450_432:
6624                         return 432000;
6625                 case CDCLK_FREQ_337_308:
6626                         return 308570;
6627                 case CDCLK_FREQ_675_617:
6628                         return 617140;
6629                 default:
6630                         WARN(1, "Unknown cd freq selection\n");
6631                 }
6632         } else {
6633                 /* vco 8100 */
6634                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6635                 case CDCLK_FREQ_450_432:
6636                         return 450000;
6637                 case CDCLK_FREQ_337_308:
6638                         return 337500;
6639                 case CDCLK_FREQ_675_617:
6640                         return 675000;
6641                 default:
6642                         WARN(1, "Unknown cd freq selection\n");
6643                 }
6644         }
6645
6646         /* error case, do as if DPLL0 isn't enabled */
6647         return 24000;
6648 }
6649
6650 static int broxton_get_display_clock_speed(struct drm_device *dev)
6651 {
6652         struct drm_i915_private *dev_priv = to_i915(dev);
6653         uint32_t cdctl = I915_READ(CDCLK_CTL);
6654         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6655         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6656         int cdclk;
6657
6658         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6659                 return 19200;
6660
6661         cdclk = 19200 * pll_ratio / 2;
6662
6663         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6664         case BXT_CDCLK_CD2X_DIV_SEL_1:
6665                 return cdclk;  /* 576MHz or 624MHz */
6666         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6667                 return cdclk * 2 / 3; /* 384MHz */
6668         case BXT_CDCLK_CD2X_DIV_SEL_2:
6669                 return cdclk / 2; /* 288MHz */
6670         case BXT_CDCLK_CD2X_DIV_SEL_4:
6671                 return cdclk / 4; /* 144MHz */
6672         }
6673
6674         /* error case, do as if DE PLL isn't enabled */
6675         return 19200;
6676 }
6677
6678 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6679 {
6680         struct drm_i915_private *dev_priv = dev->dev_private;
6681         uint32_t lcpll = I915_READ(LCPLL_CTL);
6682         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6683
6684         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6685                 return 800000;
6686         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6687                 return 450000;
6688         else if (freq == LCPLL_CLK_FREQ_450)
6689                 return 450000;
6690         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6691                 return 540000;
6692         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6693                 return 337500;
6694         else
6695                 return 675000;
6696 }
6697
6698 static int haswell_get_display_clock_speed(struct drm_device *dev)
6699 {
6700         struct drm_i915_private *dev_priv = dev->dev_private;
6701         uint32_t lcpll = I915_READ(LCPLL_CTL);
6702         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6703
6704         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6705                 return 800000;
6706         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6707                 return 450000;
6708         else if (freq == LCPLL_CLK_FREQ_450)
6709                 return 450000;
6710         else if (IS_HSW_ULT(dev))
6711                 return 337500;
6712         else
6713                 return 540000;
6714 }
6715
6716 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6717 {
6718         struct drm_i915_private *dev_priv = dev->dev_private;
6719         u32 val;
6720         int divider;
6721
6722         if (dev_priv->hpll_freq == 0)
6723                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6724
6725         mutex_lock(&dev_priv->sb_lock);
6726         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6727         mutex_unlock(&dev_priv->sb_lock);
6728
6729         divider = val & DISPLAY_FREQUENCY_VALUES;
6730
6731         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6732              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6733              "cdclk change in progress\n");
6734
6735         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6736 }
6737
6738 static int ilk_get_display_clock_speed(struct drm_device *dev)
6739 {
6740         return 450000;
6741 }
6742
6743 static int i945_get_display_clock_speed(struct drm_device *dev)
6744 {
6745         return 400000;
6746 }
6747
6748 static int i915_get_display_clock_speed(struct drm_device *dev)
6749 {
6750         return 333333;
6751 }
6752
6753 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6754 {
6755         return 200000;
6756 }
6757
6758 static int pnv_get_display_clock_speed(struct drm_device *dev)
6759 {
6760         u16 gcfgc = 0;
6761
6762         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6763
6764         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6765         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6766                 return 266667;
6767         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6768                 return 333333;
6769         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6770                 return 444444;
6771         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6772                 return 200000;
6773         default:
6774                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6775         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6776                 return 133333;
6777         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6778                 return 166667;
6779         }
6780 }
6781
6782 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6783 {
6784         u16 gcfgc = 0;
6785
6786         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6787
6788         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6789                 return 133333;
6790         else {
6791                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6792                 case GC_DISPLAY_CLOCK_333_MHZ:
6793                         return 333333;
6794                 default:
6795                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6796                         return 190000;
6797                 }
6798         }
6799 }
6800
6801 static int i865_get_display_clock_speed(struct drm_device *dev)
6802 {
6803         return 266667;
6804 }
6805
6806 static int i85x_get_display_clock_speed(struct drm_device *dev)
6807 {
6808         u16 hpllcc = 0;
6809
6810         /*
6811          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6812          * encoding is different :(
6813          * FIXME is this the right way to detect 852GM/852GMV?
6814          */
6815         if (dev->pdev->revision == 0x1)
6816                 return 133333;
6817
6818         pci_bus_read_config_word(dev->pdev->bus,
6819                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6820
6821         /* Assume that the hardware is in the high speed state.  This
6822          * should be the default.
6823          */
6824         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6825         case GC_CLOCK_133_200:
6826         case GC_CLOCK_133_200_2:
6827         case GC_CLOCK_100_200:
6828                 return 200000;
6829         case GC_CLOCK_166_250:
6830                 return 250000;
6831         case GC_CLOCK_100_133:
6832                 return 133333;
6833         case GC_CLOCK_133_266:
6834         case GC_CLOCK_133_266_2:
6835         case GC_CLOCK_166_266:
6836                 return 266667;
6837         }
6838
6839         /* Shouldn't happen */
6840         return 0;
6841 }
6842
6843 static int i830_get_display_clock_speed(struct drm_device *dev)
6844 {
6845         return 133333;
6846 }
6847
6848 static unsigned int intel_hpll_vco(struct drm_device *dev)
6849 {
6850         struct drm_i915_private *dev_priv = dev->dev_private;
6851         static const unsigned int blb_vco[8] = {
6852                 [0] = 3200000,
6853                 [1] = 4000000,
6854                 [2] = 5333333,
6855                 [3] = 4800000,
6856                 [4] = 6400000,
6857         };
6858         static const unsigned int pnv_vco[8] = {
6859                 [0] = 3200000,
6860                 [1] = 4000000,
6861                 [2] = 5333333,
6862                 [3] = 4800000,
6863                 [4] = 2666667,
6864         };
6865         static const unsigned int cl_vco[8] = {
6866                 [0] = 3200000,
6867                 [1] = 4000000,
6868                 [2] = 5333333,
6869                 [3] = 6400000,
6870                 [4] = 3333333,
6871                 [5] = 3566667,
6872                 [6] = 4266667,
6873         };
6874         static const unsigned int elk_vco[8] = {
6875                 [0] = 3200000,
6876                 [1] = 4000000,
6877                 [2] = 5333333,
6878                 [3] = 4800000,
6879         };
6880         static const unsigned int ctg_vco[8] = {
6881                 [0] = 3200000,
6882                 [1] = 4000000,
6883                 [2] = 5333333,
6884                 [3] = 6400000,
6885                 [4] = 2666667,
6886                 [5] = 4266667,
6887         };
6888         const unsigned int *vco_table;
6889         unsigned int vco;
6890         uint8_t tmp = 0;
6891
6892         /* FIXME other chipsets? */
6893         if (IS_GM45(dev))
6894                 vco_table = ctg_vco;
6895         else if (IS_G4X(dev))
6896                 vco_table = elk_vco;
6897         else if (IS_CRESTLINE(dev))
6898                 vco_table = cl_vco;
6899         else if (IS_PINEVIEW(dev))
6900                 vco_table = pnv_vco;
6901         else if (IS_G33(dev))
6902                 vco_table = blb_vco;
6903         else
6904                 return 0;
6905
6906         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6907
6908         vco = vco_table[tmp & 0x7];
6909         if (vco == 0)
6910                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6911         else
6912                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6913
6914         return vco;
6915 }
6916
6917 static int gm45_get_display_clock_speed(struct drm_device *dev)
6918 {
6919         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6920         uint16_t tmp = 0;
6921
6922         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6923
6924         cdclk_sel = (tmp >> 12) & 0x1;
6925
6926         switch (vco) {
6927         case 2666667:
6928         case 4000000:
6929         case 5333333:
6930                 return cdclk_sel ? 333333 : 222222;
6931         case 3200000:
6932                 return cdclk_sel ? 320000 : 228571;
6933         default:
6934                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6935                 return 222222;
6936         }
6937 }
6938
6939 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6940 {
6941         static const uint8_t div_3200[] = { 16, 10,  8 };
6942         static const uint8_t div_4000[] = { 20, 12, 10 };
6943         static const uint8_t div_5333[] = { 24, 16, 14 };
6944         const uint8_t *div_table;
6945         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6946         uint16_t tmp = 0;
6947
6948         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6949
6950         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6951
6952         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6953                 goto fail;
6954
6955         switch (vco) {
6956         case 3200000:
6957                 div_table = div_3200;
6958                 break;
6959         case 4000000:
6960                 div_table = div_4000;
6961                 break;
6962         case 5333333:
6963                 div_table = div_5333;
6964                 break;
6965         default:
6966                 goto fail;
6967         }
6968
6969         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6970
6971 fail:
6972         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6973         return 200000;
6974 }
6975
6976 static int g33_get_display_clock_speed(struct drm_device *dev)
6977 {
6978         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6979         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6980         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6981         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6982         const uint8_t *div_table;
6983         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6984         uint16_t tmp = 0;
6985
6986         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6987
6988         cdclk_sel = (tmp >> 4) & 0x7;
6989
6990         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6991                 goto fail;
6992
6993         switch (vco) {
6994         case 3200000:
6995                 div_table = div_3200;
6996                 break;
6997         case 4000000:
6998                 div_table = div_4000;
6999                 break;
7000         case 4800000:
7001                 div_table = div_4800;
7002                 break;
7003         case 5333333:
7004                 div_table = div_5333;
7005                 break;
7006         default:
7007                 goto fail;
7008         }
7009
7010         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7011
7012 fail:
7013         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7014         return 190476;
7015 }
7016
7017 static void
7018 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7019 {
7020         while (*num > DATA_LINK_M_N_MASK ||
7021                *den > DATA_LINK_M_N_MASK) {
7022                 *num >>= 1;
7023                 *den >>= 1;
7024         }
7025 }
7026
7027 static void compute_m_n(unsigned int m, unsigned int n,
7028                         uint32_t *ret_m, uint32_t *ret_n)
7029 {
7030         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7031         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7032         intel_reduce_m_n_ratio(ret_m, ret_n);
7033 }
7034
7035 void
7036 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7037                        int pixel_clock, int link_clock,
7038                        struct intel_link_m_n *m_n)
7039 {
7040         m_n->tu = 64;
7041
7042         compute_m_n(bits_per_pixel * pixel_clock,
7043                     link_clock * nlanes * 8,
7044                     &m_n->gmch_m, &m_n->gmch_n);
7045
7046         compute_m_n(pixel_clock, link_clock,
7047                     &m_n->link_m, &m_n->link_n);
7048 }
7049
7050 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7051 {
7052         if (i915.panel_use_ssc >= 0)
7053                 return i915.panel_use_ssc != 0;
7054         return dev_priv->vbt.lvds_use_ssc
7055                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7056 }
7057
7058 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7059                            int num_connectors)
7060 {
7061         struct drm_device *dev = crtc_state->base.crtc->dev;
7062         struct drm_i915_private *dev_priv = dev->dev_private;
7063         int refclk;
7064
7065         WARN_ON(!crtc_state->base.state);
7066
7067         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7068                 refclk = 100000;
7069         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7070             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7071                 refclk = dev_priv->vbt.lvds_ssc_freq;
7072                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7073         } else if (!IS_GEN2(dev)) {
7074                 refclk = 96000;
7075         } else {
7076                 refclk = 48000;
7077         }
7078
7079         return refclk;
7080 }
7081
7082 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7083 {
7084         return (1 << dpll->n) << 16 | dpll->m2;
7085 }
7086
7087 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7088 {
7089         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7090 }
7091
7092 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7093                                      struct intel_crtc_state *crtc_state,
7094                                      intel_clock_t *reduced_clock)
7095 {
7096         struct drm_device *dev = crtc->base.dev;
7097         u32 fp, fp2 = 0;
7098
7099         if (IS_PINEVIEW(dev)) {
7100                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7101                 if (reduced_clock)
7102                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7103         } else {
7104                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7105                 if (reduced_clock)
7106                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7107         }
7108
7109         crtc_state->dpll_hw_state.fp0 = fp;
7110
7111         crtc->lowfreq_avail = false;
7112         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7113             reduced_clock) {
7114                 crtc_state->dpll_hw_state.fp1 = fp2;
7115                 crtc->lowfreq_avail = true;
7116         } else {
7117                 crtc_state->dpll_hw_state.fp1 = fp;
7118         }
7119 }
7120
7121 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7122                 pipe)
7123 {
7124         u32 reg_val;
7125
7126         /*
7127          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7128          * and set it to a reasonable value instead.
7129          */
7130         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7131         reg_val &= 0xffffff00;
7132         reg_val |= 0x00000030;
7133         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7134
7135         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7136         reg_val &= 0x8cffffff;
7137         reg_val = 0x8c000000;
7138         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7139
7140         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7141         reg_val &= 0xffffff00;
7142         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7143
7144         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7145         reg_val &= 0x00ffffff;
7146         reg_val |= 0xb0000000;
7147         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7148 }
7149
7150 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7151                                          struct intel_link_m_n *m_n)
7152 {
7153         struct drm_device *dev = crtc->base.dev;
7154         struct drm_i915_private *dev_priv = dev->dev_private;
7155         int pipe = crtc->pipe;
7156
7157         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7158         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7159         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7160         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7161 }
7162
7163 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7164                                          struct intel_link_m_n *m_n,
7165                                          struct intel_link_m_n *m2_n2)
7166 {
7167         struct drm_device *dev = crtc->base.dev;
7168         struct drm_i915_private *dev_priv = dev->dev_private;
7169         int pipe = crtc->pipe;
7170         enum transcoder transcoder = crtc->config->cpu_transcoder;
7171
7172         if (INTEL_INFO(dev)->gen >= 5) {
7173                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7174                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7175                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7176                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7177                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7178                  * for gen < 8) and if DRRS is supported (to make sure the
7179                  * registers are not unnecessarily accessed).
7180                  */
7181                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7182                         crtc->config->has_drrs) {
7183                         I915_WRITE(PIPE_DATA_M2(transcoder),
7184                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7185                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7186                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7187                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7188                 }
7189         } else {
7190                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7191                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7192                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7193                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7194         }
7195 }
7196
7197 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7198 {
7199         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7200
7201         if (m_n == M1_N1) {
7202                 dp_m_n = &crtc->config->dp_m_n;
7203                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7204         } else if (m_n == M2_N2) {
7205
7206                 /*
7207                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7208                  * needs to be programmed into M1_N1.
7209                  */
7210                 dp_m_n = &crtc->config->dp_m2_n2;
7211         } else {
7212                 DRM_ERROR("Unsupported divider value\n");
7213                 return;
7214         }
7215
7216         if (crtc->config->has_pch_encoder)
7217                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7218         else
7219                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7220 }
7221
7222 static void vlv_compute_dpll(struct intel_crtc *crtc,
7223                              struct intel_crtc_state *pipe_config)
7224 {
7225         u32 dpll, dpll_md;
7226
7227         /*
7228          * Enable DPIO clock input. We should never disable the reference
7229          * clock for pipe B, since VGA hotplug / manual detection depends
7230          * on it.
7231          */
7232         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7233                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7234         /* We should never disable this, set it here for state tracking */
7235         if (crtc->pipe == PIPE_B)
7236                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7237         dpll |= DPLL_VCO_ENABLE;
7238         pipe_config->dpll_hw_state.dpll = dpll;
7239
7240         dpll_md = (pipe_config->pixel_multiplier - 1)
7241                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7242         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7243 }
7244
7245 static void vlv_prepare_pll(struct intel_crtc *crtc,
7246                             const struct intel_crtc_state *pipe_config)
7247 {
7248         struct drm_device *dev = crtc->base.dev;
7249         struct drm_i915_private *dev_priv = dev->dev_private;
7250         int pipe = crtc->pipe;
7251         u32 mdiv;
7252         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7253         u32 coreclk, reg_val;
7254
7255         mutex_lock(&dev_priv->sb_lock);
7256
7257         bestn = pipe_config->dpll.n;
7258         bestm1 = pipe_config->dpll.m1;
7259         bestm2 = pipe_config->dpll.m2;
7260         bestp1 = pipe_config->dpll.p1;
7261         bestp2 = pipe_config->dpll.p2;
7262
7263         /* See eDP HDMI DPIO driver vbios notes doc */
7264
7265         /* PLL B needs special handling */
7266         if (pipe == PIPE_B)
7267                 vlv_pllb_recal_opamp(dev_priv, pipe);
7268
7269         /* Set up Tx target for periodic Rcomp update */
7270         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7271
7272         /* Disable target IRef on PLL */
7273         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7274         reg_val &= 0x00ffffff;
7275         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7276
7277         /* Disable fast lock */
7278         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7279
7280         /* Set idtafcrecal before PLL is enabled */
7281         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7282         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7283         mdiv |= ((bestn << DPIO_N_SHIFT));
7284         mdiv |= (1 << DPIO_K_SHIFT);
7285
7286         /*
7287          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7288          * but we don't support that).
7289          * Note: don't use the DAC post divider as it seems unstable.
7290          */
7291         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7292         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7293
7294         mdiv |= DPIO_ENABLE_CALIBRATION;
7295         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7296
7297         /* Set HBR and RBR LPF coefficients */
7298         if (pipe_config->port_clock == 162000 ||
7299             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7300             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7301                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7302                                  0x009f0003);
7303         else
7304                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7305                                  0x00d0000f);
7306
7307         if (pipe_config->has_dp_encoder) {
7308                 /* Use SSC source */
7309                 if (pipe == PIPE_A)
7310                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7311                                          0x0df40000);
7312                 else
7313                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7314                                          0x0df70000);
7315         } else { /* HDMI or VGA */
7316                 /* Use bend source */
7317                 if (pipe == PIPE_A)
7318                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7319                                          0x0df70000);
7320                 else
7321                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7322                                          0x0df40000);
7323         }
7324
7325         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7326         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7327         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7328             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7329                 coreclk |= 0x01000000;
7330         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7331
7332         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7333         mutex_unlock(&dev_priv->sb_lock);
7334 }
7335
7336 static void chv_compute_dpll(struct intel_crtc *crtc,
7337                              struct intel_crtc_state *pipe_config)
7338 {
7339         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7340                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7341                 DPLL_VCO_ENABLE;
7342         if (crtc->pipe != PIPE_A)
7343                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7344
7345         pipe_config->dpll_hw_state.dpll_md =
7346                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7347 }
7348
7349 static void chv_prepare_pll(struct intel_crtc *crtc,
7350                             const struct intel_crtc_state *pipe_config)
7351 {
7352         struct drm_device *dev = crtc->base.dev;
7353         struct drm_i915_private *dev_priv = dev->dev_private;
7354         int pipe = crtc->pipe;
7355         int dpll_reg = DPLL(crtc->pipe);
7356         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7357         u32 loopfilter, tribuf_calcntr;
7358         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7359         u32 dpio_val;
7360         int vco;
7361
7362         bestn = pipe_config->dpll.n;
7363         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7364         bestm1 = pipe_config->dpll.m1;
7365         bestm2 = pipe_config->dpll.m2 >> 22;
7366         bestp1 = pipe_config->dpll.p1;
7367         bestp2 = pipe_config->dpll.p2;
7368         vco = pipe_config->dpll.vco;
7369         dpio_val = 0;
7370         loopfilter = 0;
7371
7372         /*
7373          * Enable Refclk and SSC
7374          */
7375         I915_WRITE(dpll_reg,
7376                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7377
7378         mutex_lock(&dev_priv->sb_lock);
7379
7380         /* p1 and p2 divider */
7381         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7382                         5 << DPIO_CHV_S1_DIV_SHIFT |
7383                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7384                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7385                         1 << DPIO_CHV_K_DIV_SHIFT);
7386
7387         /* Feedback post-divider - m2 */
7388         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7389
7390         /* Feedback refclk divider - n and m1 */
7391         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7392                         DPIO_CHV_M1_DIV_BY_2 |
7393                         1 << DPIO_CHV_N_DIV_SHIFT);
7394
7395         /* M2 fraction division */
7396         if (bestm2_frac)
7397                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7398
7399         /* M2 fraction division enable */
7400         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7401         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7402         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7403         if (bestm2_frac)
7404                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7405         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7406
7407         /* Program digital lock detect threshold */
7408         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7409         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7410                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7411         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7412         if (!bestm2_frac)
7413                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7414         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7415
7416         /* Loop filter */
7417         if (vco == 5400000) {
7418                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7419                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7420                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7421                 tribuf_calcntr = 0x9;
7422         } else if (vco <= 6200000) {
7423                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7424                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7425                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7426                 tribuf_calcntr = 0x9;
7427         } else if (vco <= 6480000) {
7428                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7429                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7430                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7431                 tribuf_calcntr = 0x8;
7432         } else {
7433                 /* Not supported. Apply the same limits as in the max case */
7434                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7435                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7436                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7437                 tribuf_calcntr = 0;
7438         }
7439         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7440
7441         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7442         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7443         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7444         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7445
7446         /* AFC Recal */
7447         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7448                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7449                         DPIO_AFC_RECAL);
7450
7451         mutex_unlock(&dev_priv->sb_lock);
7452 }
7453
7454 /**
7455  * vlv_force_pll_on - forcibly enable just the PLL
7456  * @dev_priv: i915 private structure
7457  * @pipe: pipe PLL to enable
7458  * @dpll: PLL configuration
7459  *
7460  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7461  * in cases where we need the PLL enabled even when @pipe is not going to
7462  * be enabled.
7463  */
7464 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7465                       const struct dpll *dpll)
7466 {
7467         struct intel_crtc *crtc =
7468                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7469         struct intel_crtc_state pipe_config = {
7470                 .base.crtc = &crtc->base,
7471                 .pixel_multiplier = 1,
7472                 .dpll = *dpll,
7473         };
7474
7475         if (IS_CHERRYVIEW(dev)) {
7476                 chv_compute_dpll(crtc, &pipe_config);
7477                 chv_prepare_pll(crtc, &pipe_config);
7478                 chv_enable_pll(crtc, &pipe_config);
7479         } else {
7480                 vlv_compute_dpll(crtc, &pipe_config);
7481                 vlv_prepare_pll(crtc, &pipe_config);
7482                 vlv_enable_pll(crtc, &pipe_config);
7483         }
7484 }
7485
7486 /**
7487  * vlv_force_pll_off - forcibly disable just the PLL
7488  * @dev_priv: i915 private structure
7489  * @pipe: pipe PLL to disable
7490  *
7491  * Disable the PLL for @pipe. To be used in cases where we need
7492  * the PLL enabled even when @pipe is not going to be enabled.
7493  */
7494 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7495 {
7496         if (IS_CHERRYVIEW(dev))
7497                 chv_disable_pll(to_i915(dev), pipe);
7498         else
7499                 vlv_disable_pll(to_i915(dev), pipe);
7500 }
7501
7502 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7503                               struct intel_crtc_state *crtc_state,
7504                               intel_clock_t *reduced_clock,
7505                               int num_connectors)
7506 {
7507         struct drm_device *dev = crtc->base.dev;
7508         struct drm_i915_private *dev_priv = dev->dev_private;
7509         u32 dpll;
7510         bool is_sdvo;
7511         struct dpll *clock = &crtc_state->dpll;
7512
7513         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7514
7515         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7516                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7517
7518         dpll = DPLL_VGA_MODE_DIS;
7519
7520         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7521                 dpll |= DPLLB_MODE_LVDS;
7522         else
7523                 dpll |= DPLLB_MODE_DAC_SERIAL;
7524
7525         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7526                 dpll |= (crtc_state->pixel_multiplier - 1)
7527                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7528         }
7529
7530         if (is_sdvo)
7531                 dpll |= DPLL_SDVO_HIGH_SPEED;
7532
7533         if (crtc_state->has_dp_encoder)
7534                 dpll |= DPLL_SDVO_HIGH_SPEED;
7535
7536         /* compute bitmask from p1 value */
7537         if (IS_PINEVIEW(dev))
7538                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7539         else {
7540                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7541                 if (IS_G4X(dev) && reduced_clock)
7542                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7543         }
7544         switch (clock->p2) {
7545         case 5:
7546                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7547                 break;
7548         case 7:
7549                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7550                 break;
7551         case 10:
7552                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7553                 break;
7554         case 14:
7555                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7556                 break;
7557         }
7558         if (INTEL_INFO(dev)->gen >= 4)
7559                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7560
7561         if (crtc_state->sdvo_tv_clock)
7562                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7563         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7564                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7565                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7566         else
7567                 dpll |= PLL_REF_INPUT_DREFCLK;
7568
7569         dpll |= DPLL_VCO_ENABLE;
7570         crtc_state->dpll_hw_state.dpll = dpll;
7571
7572         if (INTEL_INFO(dev)->gen >= 4) {
7573                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7574                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7575                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7576         }
7577 }
7578
7579 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7580                               struct intel_crtc_state *crtc_state,
7581                               intel_clock_t *reduced_clock,
7582                               int num_connectors)
7583 {
7584         struct drm_device *dev = crtc->base.dev;
7585         struct drm_i915_private *dev_priv = dev->dev_private;
7586         u32 dpll;
7587         struct dpll *clock = &crtc_state->dpll;
7588
7589         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7590
7591         dpll = DPLL_VGA_MODE_DIS;
7592
7593         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7594                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7595         } else {
7596                 if (clock->p1 == 2)
7597                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7598                 else
7599                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7600                 if (clock->p2 == 4)
7601                         dpll |= PLL_P2_DIVIDE_BY_4;
7602         }
7603
7604         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7605                 dpll |= DPLL_DVO_2X_MODE;
7606
7607         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7608                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7609                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7610         else
7611                 dpll |= PLL_REF_INPUT_DREFCLK;
7612
7613         dpll |= DPLL_VCO_ENABLE;
7614         crtc_state->dpll_hw_state.dpll = dpll;
7615 }
7616
7617 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7618 {
7619         struct drm_device *dev = intel_crtc->base.dev;
7620         struct drm_i915_private *dev_priv = dev->dev_private;
7621         enum pipe pipe = intel_crtc->pipe;
7622         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7623         struct drm_display_mode *adjusted_mode =
7624                 &intel_crtc->config->base.adjusted_mode;
7625         uint32_t crtc_vtotal, crtc_vblank_end;
7626         int vsyncshift = 0;
7627
7628         /* We need to be careful not to changed the adjusted mode, for otherwise
7629          * the hw state checker will get angry at the mismatch. */
7630         crtc_vtotal = adjusted_mode->crtc_vtotal;
7631         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7632
7633         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7634                 /* the chip adds 2 halflines automatically */
7635                 crtc_vtotal -= 1;
7636                 crtc_vblank_end -= 1;
7637
7638                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7639                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7640                 else
7641                         vsyncshift = adjusted_mode->crtc_hsync_start -
7642                                 adjusted_mode->crtc_htotal / 2;
7643                 if (vsyncshift < 0)
7644                         vsyncshift += adjusted_mode->crtc_htotal;
7645         }
7646
7647         if (INTEL_INFO(dev)->gen > 3)
7648                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7649
7650         I915_WRITE(HTOTAL(cpu_transcoder),
7651                    (adjusted_mode->crtc_hdisplay - 1) |
7652                    ((adjusted_mode->crtc_htotal - 1) << 16));
7653         I915_WRITE(HBLANK(cpu_transcoder),
7654                    (adjusted_mode->crtc_hblank_start - 1) |
7655                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7656         I915_WRITE(HSYNC(cpu_transcoder),
7657                    (adjusted_mode->crtc_hsync_start - 1) |
7658                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7659
7660         I915_WRITE(VTOTAL(cpu_transcoder),
7661                    (adjusted_mode->crtc_vdisplay - 1) |
7662                    ((crtc_vtotal - 1) << 16));
7663         I915_WRITE(VBLANK(cpu_transcoder),
7664                    (adjusted_mode->crtc_vblank_start - 1) |
7665                    ((crtc_vblank_end - 1) << 16));
7666         I915_WRITE(VSYNC(cpu_transcoder),
7667                    (adjusted_mode->crtc_vsync_start - 1) |
7668                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7669
7670         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7671          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7672          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7673          * bits. */
7674         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7675             (pipe == PIPE_B || pipe == PIPE_C))
7676                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7677
7678         /* pipesrc controls the size that is scaled from, which should
7679          * always be the user's requested size.
7680          */
7681         I915_WRITE(PIPESRC(pipe),
7682                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7683                    (intel_crtc->config->pipe_src_h - 1));
7684 }
7685
7686 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7687                                    struct intel_crtc_state *pipe_config)
7688 {
7689         struct drm_device *dev = crtc->base.dev;
7690         struct drm_i915_private *dev_priv = dev->dev_private;
7691         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7692         uint32_t tmp;
7693
7694         tmp = I915_READ(HTOTAL(cpu_transcoder));
7695         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7696         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7697         tmp = I915_READ(HBLANK(cpu_transcoder));
7698         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7699         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7700         tmp = I915_READ(HSYNC(cpu_transcoder));
7701         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7702         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7703
7704         tmp = I915_READ(VTOTAL(cpu_transcoder));
7705         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7706         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7707         tmp = I915_READ(VBLANK(cpu_transcoder));
7708         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7709         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7710         tmp = I915_READ(VSYNC(cpu_transcoder));
7711         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7712         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7713
7714         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7715                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7716                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7717                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7718         }
7719
7720         tmp = I915_READ(PIPESRC(crtc->pipe));
7721         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7722         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7723
7724         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7725         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7726 }
7727
7728 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7729                                  struct intel_crtc_state *pipe_config)
7730 {
7731         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7732         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7733         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7734         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7735
7736         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7737         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7738         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7739         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7740
7741         mode->flags = pipe_config->base.adjusted_mode.flags;
7742
7743         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7744         mode->flags |= pipe_config->base.adjusted_mode.flags;
7745 }
7746
7747 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7748 {
7749         struct drm_device *dev = intel_crtc->base.dev;
7750         struct drm_i915_private *dev_priv = dev->dev_private;
7751         uint32_t pipeconf;
7752
7753         pipeconf = 0;
7754
7755         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7756             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7757                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7758
7759         if (intel_crtc->config->double_wide)
7760                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7761
7762         /* only g4x and later have fancy bpc/dither controls */
7763         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7764                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7765                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7766                         pipeconf |= PIPECONF_DITHER_EN |
7767                                     PIPECONF_DITHER_TYPE_SP;
7768
7769                 switch (intel_crtc->config->pipe_bpp) {
7770                 case 18:
7771                         pipeconf |= PIPECONF_6BPC;
7772                         break;
7773                 case 24:
7774                         pipeconf |= PIPECONF_8BPC;
7775                         break;
7776                 case 30:
7777                         pipeconf |= PIPECONF_10BPC;
7778                         break;
7779                 default:
7780                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7781                         BUG();
7782                 }
7783         }
7784
7785         if (HAS_PIPE_CXSR(dev)) {
7786                 if (intel_crtc->lowfreq_avail) {
7787                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7788                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7789                 } else {
7790                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7791                 }
7792         }
7793
7794         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7795                 if (INTEL_INFO(dev)->gen < 4 ||
7796                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7797                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7798                 else
7799                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7800         } else
7801                 pipeconf |= PIPECONF_PROGRESSIVE;
7802
7803         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7804                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7805
7806         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7807         POSTING_READ(PIPECONF(intel_crtc->pipe));
7808 }
7809
7810 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7811                                    struct intel_crtc_state *crtc_state)
7812 {
7813         struct drm_device *dev = crtc->base.dev;
7814         struct drm_i915_private *dev_priv = dev->dev_private;
7815         int refclk, num_connectors = 0;
7816         intel_clock_t clock;
7817         bool ok;
7818         bool is_dsi = false;
7819         struct intel_encoder *encoder;
7820         const intel_limit_t *limit;
7821         struct drm_atomic_state *state = crtc_state->base.state;
7822         struct drm_connector *connector;
7823         struct drm_connector_state *connector_state;
7824         int i;
7825
7826         memset(&crtc_state->dpll_hw_state, 0,
7827                sizeof(crtc_state->dpll_hw_state));
7828
7829         for_each_connector_in_state(state, connector, connector_state, i) {
7830                 if (connector_state->crtc != &crtc->base)
7831                         continue;
7832
7833                 encoder = to_intel_encoder(connector_state->best_encoder);
7834
7835                 switch (encoder->type) {
7836                 case INTEL_OUTPUT_DSI:
7837                         is_dsi = true;
7838                         break;
7839                 default:
7840                         break;
7841                 }
7842
7843                 num_connectors++;
7844         }
7845
7846         if (is_dsi)
7847                 return 0;
7848
7849         if (!crtc_state->clock_set) {
7850                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7851
7852                 /*
7853                  * Returns a set of divisors for the desired target clock with
7854                  * the given refclk, or FALSE.  The returned values represent
7855                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7856                  * 2) / p1 / p2.
7857                  */
7858                 limit = intel_limit(crtc_state, refclk);
7859                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7860                                                  crtc_state->port_clock,
7861                                                  refclk, NULL, &clock);
7862                 if (!ok) {
7863                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7864                         return -EINVAL;
7865                 }
7866
7867                 /* Compat-code for transition, will disappear. */
7868                 crtc_state->dpll.n = clock.n;
7869                 crtc_state->dpll.m1 = clock.m1;
7870                 crtc_state->dpll.m2 = clock.m2;
7871                 crtc_state->dpll.p1 = clock.p1;
7872                 crtc_state->dpll.p2 = clock.p2;
7873         }
7874
7875         if (IS_GEN2(dev)) {
7876                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7877                                   num_connectors);
7878         } else if (IS_CHERRYVIEW(dev)) {
7879                 chv_compute_dpll(crtc, crtc_state);
7880         } else if (IS_VALLEYVIEW(dev)) {
7881                 vlv_compute_dpll(crtc, crtc_state);
7882         } else {
7883                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7884                                   num_connectors);
7885         }
7886
7887         return 0;
7888 }
7889
7890 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7891                                  struct intel_crtc_state *pipe_config)
7892 {
7893         struct drm_device *dev = crtc->base.dev;
7894         struct drm_i915_private *dev_priv = dev->dev_private;
7895         uint32_t tmp;
7896
7897         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7898                 return;
7899
7900         tmp = I915_READ(PFIT_CONTROL);
7901         if (!(tmp & PFIT_ENABLE))
7902                 return;
7903
7904         /* Check whether the pfit is attached to our pipe. */
7905         if (INTEL_INFO(dev)->gen < 4) {
7906                 if (crtc->pipe != PIPE_B)
7907                         return;
7908         } else {
7909                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7910                         return;
7911         }
7912
7913         pipe_config->gmch_pfit.control = tmp;
7914         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7915         if (INTEL_INFO(dev)->gen < 5)
7916                 pipe_config->gmch_pfit.lvds_border_bits =
7917                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7918 }
7919
7920 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7921                                struct intel_crtc_state *pipe_config)
7922 {
7923         struct drm_device *dev = crtc->base.dev;
7924         struct drm_i915_private *dev_priv = dev->dev_private;
7925         int pipe = pipe_config->cpu_transcoder;
7926         intel_clock_t clock;
7927         u32 mdiv;
7928         int refclk = 100000;
7929
7930         /* In case of MIPI DPLL will not even be used */
7931         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7932                 return;
7933
7934         mutex_lock(&dev_priv->sb_lock);
7935         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7936         mutex_unlock(&dev_priv->sb_lock);
7937
7938         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7939         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7940         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7941         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7942         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7943
7944         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7945 }
7946
7947 static void
7948 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7949                               struct intel_initial_plane_config *plane_config)
7950 {
7951         struct drm_device *dev = crtc->base.dev;
7952         struct drm_i915_private *dev_priv = dev->dev_private;
7953         u32 val, base, offset;
7954         int pipe = crtc->pipe, plane = crtc->plane;
7955         int fourcc, pixel_format;
7956         unsigned int aligned_height;
7957         struct drm_framebuffer *fb;
7958         struct intel_framebuffer *intel_fb;
7959
7960         val = I915_READ(DSPCNTR(plane));
7961         if (!(val & DISPLAY_PLANE_ENABLE))
7962                 return;
7963
7964         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7965         if (!intel_fb) {
7966                 DRM_DEBUG_KMS("failed to alloc fb\n");
7967                 return;
7968         }
7969
7970         fb = &intel_fb->base;
7971
7972         if (INTEL_INFO(dev)->gen >= 4) {
7973                 if (val & DISPPLANE_TILED) {
7974                         plane_config->tiling = I915_TILING_X;
7975                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7976                 }
7977         }
7978
7979         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7980         fourcc = i9xx_format_to_fourcc(pixel_format);
7981         fb->pixel_format = fourcc;
7982         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7983
7984         if (INTEL_INFO(dev)->gen >= 4) {
7985                 if (plane_config->tiling)
7986                         offset = I915_READ(DSPTILEOFF(plane));
7987                 else
7988                         offset = I915_READ(DSPLINOFF(plane));
7989                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7990         } else {
7991                 base = I915_READ(DSPADDR(plane));
7992         }
7993         plane_config->base = base;
7994
7995         val = I915_READ(PIPESRC(pipe));
7996         fb->width = ((val >> 16) & 0xfff) + 1;
7997         fb->height = ((val >> 0) & 0xfff) + 1;
7998
7999         val = I915_READ(DSPSTRIDE(pipe));
8000         fb->pitches[0] = val & 0xffffffc0;
8001
8002         aligned_height = intel_fb_align_height(dev, fb->height,
8003                                                fb->pixel_format,
8004                                                fb->modifier[0]);
8005
8006         plane_config->size = fb->pitches[0] * aligned_height;
8007
8008         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8009                       pipe_name(pipe), plane, fb->width, fb->height,
8010                       fb->bits_per_pixel, base, fb->pitches[0],
8011                       plane_config->size);
8012
8013         plane_config->fb = intel_fb;
8014 }
8015
8016 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8017                                struct intel_crtc_state *pipe_config)
8018 {
8019         struct drm_device *dev = crtc->base.dev;
8020         struct drm_i915_private *dev_priv = dev->dev_private;
8021         int pipe = pipe_config->cpu_transcoder;
8022         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8023         intel_clock_t clock;
8024         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8025         int refclk = 100000;
8026
8027         mutex_lock(&dev_priv->sb_lock);
8028         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8029         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8030         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8031         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8032         mutex_unlock(&dev_priv->sb_lock);
8033
8034         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8035         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8036         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8037         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8038         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8039
8040         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8041 }
8042
8043 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8044                                  struct intel_crtc_state *pipe_config)
8045 {
8046         struct drm_device *dev = crtc->base.dev;
8047         struct drm_i915_private *dev_priv = dev->dev_private;
8048         uint32_t tmp;
8049
8050         if (!intel_display_power_is_enabled(dev_priv,
8051                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8052                 return false;
8053
8054         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8055         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8056
8057         tmp = I915_READ(PIPECONF(crtc->pipe));
8058         if (!(tmp & PIPECONF_ENABLE))
8059                 return false;
8060
8061         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8062                 switch (tmp & PIPECONF_BPC_MASK) {
8063                 case PIPECONF_6BPC:
8064                         pipe_config->pipe_bpp = 18;
8065                         break;
8066                 case PIPECONF_8BPC:
8067                         pipe_config->pipe_bpp = 24;
8068                         break;
8069                 case PIPECONF_10BPC:
8070                         pipe_config->pipe_bpp = 30;
8071                         break;
8072                 default:
8073                         break;
8074                 }
8075         }
8076
8077         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8078                 pipe_config->limited_color_range = true;
8079
8080         if (INTEL_INFO(dev)->gen < 4)
8081                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8082
8083         intel_get_pipe_timings(crtc, pipe_config);
8084
8085         i9xx_get_pfit_config(crtc, pipe_config);
8086
8087         if (INTEL_INFO(dev)->gen >= 4) {
8088                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8089                 pipe_config->pixel_multiplier =
8090                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8091                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8092                 pipe_config->dpll_hw_state.dpll_md = tmp;
8093         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8094                 tmp = I915_READ(DPLL(crtc->pipe));
8095                 pipe_config->pixel_multiplier =
8096                         ((tmp & SDVO_MULTIPLIER_MASK)
8097                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8098         } else {
8099                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8100                  * port and will be fixed up in the encoder->get_config
8101                  * function. */
8102                 pipe_config->pixel_multiplier = 1;
8103         }
8104         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8105         if (!IS_VALLEYVIEW(dev)) {
8106                 /*
8107                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8108                  * on 830. Filter it out here so that we don't
8109                  * report errors due to that.
8110                  */
8111                 if (IS_I830(dev))
8112                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8113
8114                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8115                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8116         } else {
8117                 /* Mask out read-only status bits. */
8118                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8119                                                      DPLL_PORTC_READY_MASK |
8120                                                      DPLL_PORTB_READY_MASK);
8121         }
8122
8123         if (IS_CHERRYVIEW(dev))
8124                 chv_crtc_clock_get(crtc, pipe_config);
8125         else if (IS_VALLEYVIEW(dev))
8126                 vlv_crtc_clock_get(crtc, pipe_config);
8127         else
8128                 i9xx_crtc_clock_get(crtc, pipe_config);
8129
8130         return true;
8131 }
8132
8133 static void ironlake_init_pch_refclk(struct drm_device *dev)
8134 {
8135         struct drm_i915_private *dev_priv = dev->dev_private;
8136         struct intel_encoder *encoder;
8137         u32 val, final;
8138         bool has_lvds = false;
8139         bool has_cpu_edp = false;
8140         bool has_panel = false;
8141         bool has_ck505 = false;
8142         bool can_ssc = false;
8143
8144         /* We need to take the global config into account */
8145         for_each_intel_encoder(dev, encoder) {
8146                 switch (encoder->type) {
8147                 case INTEL_OUTPUT_LVDS:
8148                         has_panel = true;
8149                         has_lvds = true;
8150                         break;
8151                 case INTEL_OUTPUT_EDP:
8152                         has_panel = true;
8153                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8154                                 has_cpu_edp = true;
8155                         break;
8156                 default:
8157                         break;
8158                 }
8159         }
8160
8161         if (HAS_PCH_IBX(dev)) {
8162                 has_ck505 = dev_priv->vbt.display_clock_mode;
8163                 can_ssc = has_ck505;
8164         } else {
8165                 has_ck505 = false;
8166                 can_ssc = true;
8167         }
8168
8169         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8170                       has_panel, has_lvds, has_ck505);
8171
8172         /* Ironlake: try to setup display ref clock before DPLL
8173          * enabling. This is only under driver's control after
8174          * PCH B stepping, previous chipset stepping should be
8175          * ignoring this setting.
8176          */
8177         val = I915_READ(PCH_DREF_CONTROL);
8178
8179         /* As we must carefully and slowly disable/enable each source in turn,
8180          * compute the final state we want first and check if we need to
8181          * make any changes at all.
8182          */
8183         final = val;
8184         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8185         if (has_ck505)
8186                 final |= DREF_NONSPREAD_CK505_ENABLE;
8187         else
8188                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8189
8190         final &= ~DREF_SSC_SOURCE_MASK;
8191         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8192         final &= ~DREF_SSC1_ENABLE;
8193
8194         if (has_panel) {
8195                 final |= DREF_SSC_SOURCE_ENABLE;
8196
8197                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8198                         final |= DREF_SSC1_ENABLE;
8199
8200                 if (has_cpu_edp) {
8201                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8202                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8203                         else
8204                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8205                 } else
8206                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8207         } else {
8208                 final |= DREF_SSC_SOURCE_DISABLE;
8209                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8210         }
8211
8212         if (final == val)
8213                 return;
8214
8215         /* Always enable nonspread source */
8216         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8217
8218         if (has_ck505)
8219                 val |= DREF_NONSPREAD_CK505_ENABLE;
8220         else
8221                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8222
8223         if (has_panel) {
8224                 val &= ~DREF_SSC_SOURCE_MASK;
8225                 val |= DREF_SSC_SOURCE_ENABLE;
8226
8227                 /* SSC must be turned on before enabling the CPU output  */
8228                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8229                         DRM_DEBUG_KMS("Using SSC on panel\n");
8230                         val |= DREF_SSC1_ENABLE;
8231                 } else
8232                         val &= ~DREF_SSC1_ENABLE;
8233
8234                 /* Get SSC going before enabling the outputs */
8235                 I915_WRITE(PCH_DREF_CONTROL, val);
8236                 POSTING_READ(PCH_DREF_CONTROL);
8237                 udelay(200);
8238
8239                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8240
8241                 /* Enable CPU source on CPU attached eDP */
8242                 if (has_cpu_edp) {
8243                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8244                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8245                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8246                         } else
8247                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8248                 } else
8249                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8250
8251                 I915_WRITE(PCH_DREF_CONTROL, val);
8252                 POSTING_READ(PCH_DREF_CONTROL);
8253                 udelay(200);
8254         } else {
8255                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8256
8257                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8258
8259                 /* Turn off CPU output */
8260                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8261
8262                 I915_WRITE(PCH_DREF_CONTROL, val);
8263                 POSTING_READ(PCH_DREF_CONTROL);
8264                 udelay(200);
8265
8266                 /* Turn off the SSC source */
8267                 val &= ~DREF_SSC_SOURCE_MASK;
8268                 val |= DREF_SSC_SOURCE_DISABLE;
8269
8270                 /* Turn off SSC1 */
8271                 val &= ~DREF_SSC1_ENABLE;
8272
8273                 I915_WRITE(PCH_DREF_CONTROL, val);
8274                 POSTING_READ(PCH_DREF_CONTROL);
8275                 udelay(200);
8276         }
8277
8278         BUG_ON(val != final);
8279 }
8280
8281 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8282 {
8283         uint32_t tmp;
8284
8285         tmp = I915_READ(SOUTH_CHICKEN2);
8286         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8287         I915_WRITE(SOUTH_CHICKEN2, tmp);
8288
8289         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8290                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8291                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8292
8293         tmp = I915_READ(SOUTH_CHICKEN2);
8294         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8295         I915_WRITE(SOUTH_CHICKEN2, tmp);
8296
8297         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8298                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8299                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8300 }
8301
8302 /* WaMPhyProgramming:hsw */
8303 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8304 {
8305         uint32_t tmp;
8306
8307         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8308         tmp &= ~(0xFF << 24);
8309         tmp |= (0x12 << 24);
8310         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8311
8312         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8313         tmp |= (1 << 11);
8314         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8315
8316         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8317         tmp |= (1 << 11);
8318         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8319
8320         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8321         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8322         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8323
8324         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8325         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8326         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8327
8328         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8329         tmp &= ~(7 << 13);
8330         tmp |= (5 << 13);
8331         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8332
8333         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8334         tmp &= ~(7 << 13);
8335         tmp |= (5 << 13);
8336         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8337
8338         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8339         tmp &= ~0xFF;
8340         tmp |= 0x1C;
8341         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8342
8343         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8344         tmp &= ~0xFF;
8345         tmp |= 0x1C;
8346         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8347
8348         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8349         tmp &= ~(0xFF << 16);
8350         tmp |= (0x1C << 16);
8351         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8352
8353         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8354         tmp &= ~(0xFF << 16);
8355         tmp |= (0x1C << 16);
8356         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8357
8358         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8359         tmp |= (1 << 27);
8360         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8361
8362         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8363         tmp |= (1 << 27);
8364         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8365
8366         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8367         tmp &= ~(0xF << 28);
8368         tmp |= (4 << 28);
8369         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8370
8371         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8372         tmp &= ~(0xF << 28);
8373         tmp |= (4 << 28);
8374         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8375 }
8376
8377 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8378  * Programming" based on the parameters passed:
8379  * - Sequence to enable CLKOUT_DP
8380  * - Sequence to enable CLKOUT_DP without spread
8381  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8382  */
8383 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8384                                  bool with_fdi)
8385 {
8386         struct drm_i915_private *dev_priv = dev->dev_private;
8387         uint32_t reg, tmp;
8388
8389         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8390                 with_spread = true;
8391         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8392                  with_fdi, "LP PCH doesn't have FDI\n"))
8393                 with_fdi = false;
8394
8395         mutex_lock(&dev_priv->sb_lock);
8396
8397         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8398         tmp &= ~SBI_SSCCTL_DISABLE;
8399         tmp |= SBI_SSCCTL_PATHALT;
8400         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8401
8402         udelay(24);
8403
8404         if (with_spread) {
8405                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8406                 tmp &= ~SBI_SSCCTL_PATHALT;
8407                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8408
8409                 if (with_fdi) {
8410                         lpt_reset_fdi_mphy(dev_priv);
8411                         lpt_program_fdi_mphy(dev_priv);
8412                 }
8413         }
8414
8415         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8416                SBI_GEN0 : SBI_DBUFF0;
8417         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8418         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8419         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8420
8421         mutex_unlock(&dev_priv->sb_lock);
8422 }
8423
8424 /* Sequence to disable CLKOUT_DP */
8425 static void lpt_disable_clkout_dp(struct drm_device *dev)
8426 {
8427         struct drm_i915_private *dev_priv = dev->dev_private;
8428         uint32_t reg, tmp;
8429
8430         mutex_lock(&dev_priv->sb_lock);
8431
8432         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8433                SBI_GEN0 : SBI_DBUFF0;
8434         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8435         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8436         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8437
8438         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8439         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8440                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8441                         tmp |= SBI_SSCCTL_PATHALT;
8442                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8443                         udelay(32);
8444                 }
8445                 tmp |= SBI_SSCCTL_DISABLE;
8446                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8447         }
8448
8449         mutex_unlock(&dev_priv->sb_lock);
8450 }
8451
8452 static void lpt_init_pch_refclk(struct drm_device *dev)
8453 {
8454         struct intel_encoder *encoder;
8455         bool has_vga = false;
8456
8457         for_each_intel_encoder(dev, encoder) {
8458                 switch (encoder->type) {
8459                 case INTEL_OUTPUT_ANALOG:
8460                         has_vga = true;
8461                         break;
8462                 default:
8463                         break;
8464                 }
8465         }
8466
8467         if (has_vga)
8468                 lpt_enable_clkout_dp(dev, true, true);
8469         else
8470                 lpt_disable_clkout_dp(dev);
8471 }
8472
8473 /*
8474  * Initialize reference clocks when the driver loads
8475  */
8476 void intel_init_pch_refclk(struct drm_device *dev)
8477 {
8478         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8479                 ironlake_init_pch_refclk(dev);
8480         else if (HAS_PCH_LPT(dev))
8481                 lpt_init_pch_refclk(dev);
8482 }
8483
8484 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8485 {
8486         struct drm_device *dev = crtc_state->base.crtc->dev;
8487         struct drm_i915_private *dev_priv = dev->dev_private;
8488         struct drm_atomic_state *state = crtc_state->base.state;
8489         struct drm_connector *connector;
8490         struct drm_connector_state *connector_state;
8491         struct intel_encoder *encoder;
8492         int num_connectors = 0, i;
8493         bool is_lvds = false;
8494
8495         for_each_connector_in_state(state, connector, connector_state, i) {
8496                 if (connector_state->crtc != crtc_state->base.crtc)
8497                         continue;
8498
8499                 encoder = to_intel_encoder(connector_state->best_encoder);
8500
8501                 switch (encoder->type) {
8502                 case INTEL_OUTPUT_LVDS:
8503                         is_lvds = true;
8504                         break;
8505                 default:
8506                         break;
8507                 }
8508                 num_connectors++;
8509         }
8510
8511         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8512                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8513                               dev_priv->vbt.lvds_ssc_freq);
8514                 return dev_priv->vbt.lvds_ssc_freq;
8515         }
8516
8517         return 120000;
8518 }
8519
8520 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8521 {
8522         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8524         int pipe = intel_crtc->pipe;
8525         uint32_t val;
8526
8527         val = 0;
8528
8529         switch (intel_crtc->config->pipe_bpp) {
8530         case 18:
8531                 val |= PIPECONF_6BPC;
8532                 break;
8533         case 24:
8534                 val |= PIPECONF_8BPC;
8535                 break;
8536         case 30:
8537                 val |= PIPECONF_10BPC;
8538                 break;
8539         case 36:
8540                 val |= PIPECONF_12BPC;
8541                 break;
8542         default:
8543                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8544                 BUG();
8545         }
8546
8547         if (intel_crtc->config->dither)
8548                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8549
8550         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8551                 val |= PIPECONF_INTERLACED_ILK;
8552         else
8553                 val |= PIPECONF_PROGRESSIVE;
8554
8555         if (intel_crtc->config->limited_color_range)
8556                 val |= PIPECONF_COLOR_RANGE_SELECT;
8557
8558         I915_WRITE(PIPECONF(pipe), val);
8559         POSTING_READ(PIPECONF(pipe));
8560 }
8561
8562 /*
8563  * Set up the pipe CSC unit.
8564  *
8565  * Currently only full range RGB to limited range RGB conversion
8566  * is supported, but eventually this should handle various
8567  * RGB<->YCbCr scenarios as well.
8568  */
8569 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8570 {
8571         struct drm_device *dev = crtc->dev;
8572         struct drm_i915_private *dev_priv = dev->dev_private;
8573         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8574         int pipe = intel_crtc->pipe;
8575         uint16_t coeff = 0x7800; /* 1.0 */
8576
8577         /*
8578          * TODO: Check what kind of values actually come out of the pipe
8579          * with these coeff/postoff values and adjust to get the best
8580          * accuracy. Perhaps we even need to take the bpc value into
8581          * consideration.
8582          */
8583
8584         if (intel_crtc->config->limited_color_range)
8585                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8586
8587         /*
8588          * GY/GU and RY/RU should be the other way around according
8589          * to BSpec, but reality doesn't agree. Just set them up in
8590          * a way that results in the correct picture.
8591          */
8592         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8593         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8594
8595         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8596         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8597
8598         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8599         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8600
8601         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8602         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8603         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8604
8605         if (INTEL_INFO(dev)->gen > 6) {
8606                 uint16_t postoff = 0;
8607
8608                 if (intel_crtc->config->limited_color_range)
8609                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8610
8611                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8612                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8613                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8614
8615                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8616         } else {
8617                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8618
8619                 if (intel_crtc->config->limited_color_range)
8620                         mode |= CSC_BLACK_SCREEN_OFFSET;
8621
8622                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8623         }
8624 }
8625
8626 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8627 {
8628         struct drm_device *dev = crtc->dev;
8629         struct drm_i915_private *dev_priv = dev->dev_private;
8630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8631         enum pipe pipe = intel_crtc->pipe;
8632         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8633         uint32_t val;
8634
8635         val = 0;
8636
8637         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8638                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8639
8640         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8641                 val |= PIPECONF_INTERLACED_ILK;
8642         else
8643                 val |= PIPECONF_PROGRESSIVE;
8644
8645         I915_WRITE(PIPECONF(cpu_transcoder), val);
8646         POSTING_READ(PIPECONF(cpu_transcoder));
8647
8648         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8649         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8650
8651         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8652                 val = 0;
8653
8654                 switch (intel_crtc->config->pipe_bpp) {
8655                 case 18:
8656                         val |= PIPEMISC_DITHER_6_BPC;
8657                         break;
8658                 case 24:
8659                         val |= PIPEMISC_DITHER_8_BPC;
8660                         break;
8661                 case 30:
8662                         val |= PIPEMISC_DITHER_10_BPC;
8663                         break;
8664                 case 36:
8665                         val |= PIPEMISC_DITHER_12_BPC;
8666                         break;
8667                 default:
8668                         /* Case prevented by pipe_config_set_bpp. */
8669                         BUG();
8670                 }
8671
8672                 if (intel_crtc->config->dither)
8673                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8674
8675                 I915_WRITE(PIPEMISC(pipe), val);
8676         }
8677 }
8678
8679 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8680                                     struct intel_crtc_state *crtc_state,
8681                                     intel_clock_t *clock,
8682                                     bool *has_reduced_clock,
8683                                     intel_clock_t *reduced_clock)
8684 {
8685         struct drm_device *dev = crtc->dev;
8686         struct drm_i915_private *dev_priv = dev->dev_private;
8687         int refclk;
8688         const intel_limit_t *limit;
8689         bool ret;
8690
8691         refclk = ironlake_get_refclk(crtc_state);
8692
8693         /*
8694          * Returns a set of divisors for the desired target clock with the given
8695          * refclk, or FALSE.  The returned values represent the clock equation:
8696          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8697          */
8698         limit = intel_limit(crtc_state, refclk);
8699         ret = dev_priv->display.find_dpll(limit, crtc_state,
8700                                           crtc_state->port_clock,
8701                                           refclk, NULL, clock);
8702         if (!ret)
8703                 return false;
8704
8705         return true;
8706 }
8707
8708 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8709 {
8710         /*
8711          * Account for spread spectrum to avoid
8712          * oversubscribing the link. Max center spread
8713          * is 2.5%; use 5% for safety's sake.
8714          */
8715         u32 bps = target_clock * bpp * 21 / 20;
8716         return DIV_ROUND_UP(bps, link_bw * 8);
8717 }
8718
8719 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8720 {
8721         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8722 }
8723
8724 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8725                                       struct intel_crtc_state *crtc_state,
8726                                       u32 *fp,
8727                                       intel_clock_t *reduced_clock, u32 *fp2)
8728 {
8729         struct drm_crtc *crtc = &intel_crtc->base;
8730         struct drm_device *dev = crtc->dev;
8731         struct drm_i915_private *dev_priv = dev->dev_private;
8732         struct drm_atomic_state *state = crtc_state->base.state;
8733         struct drm_connector *connector;
8734         struct drm_connector_state *connector_state;
8735         struct intel_encoder *encoder;
8736         uint32_t dpll;
8737         int factor, num_connectors = 0, i;
8738         bool is_lvds = false, is_sdvo = false;
8739
8740         for_each_connector_in_state(state, connector, connector_state, i) {
8741                 if (connector_state->crtc != crtc_state->base.crtc)
8742                         continue;
8743
8744                 encoder = to_intel_encoder(connector_state->best_encoder);
8745
8746                 switch (encoder->type) {
8747                 case INTEL_OUTPUT_LVDS:
8748                         is_lvds = true;
8749                         break;
8750                 case INTEL_OUTPUT_SDVO:
8751                 case INTEL_OUTPUT_HDMI:
8752                         is_sdvo = true;
8753                         break;
8754                 default:
8755                         break;
8756                 }
8757
8758                 num_connectors++;
8759         }
8760
8761         /* Enable autotuning of the PLL clock (if permissible) */
8762         factor = 21;
8763         if (is_lvds) {
8764                 if ((intel_panel_use_ssc(dev_priv) &&
8765                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8766                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8767                         factor = 25;
8768         } else if (crtc_state->sdvo_tv_clock)
8769                 factor = 20;
8770
8771         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8772                 *fp |= FP_CB_TUNE;
8773
8774         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8775                 *fp2 |= FP_CB_TUNE;
8776
8777         dpll = 0;
8778
8779         if (is_lvds)
8780                 dpll |= DPLLB_MODE_LVDS;
8781         else
8782                 dpll |= DPLLB_MODE_DAC_SERIAL;
8783
8784         dpll |= (crtc_state->pixel_multiplier - 1)
8785                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8786
8787         if (is_sdvo)
8788                 dpll |= DPLL_SDVO_HIGH_SPEED;
8789         if (crtc_state->has_dp_encoder)
8790                 dpll |= DPLL_SDVO_HIGH_SPEED;
8791
8792         /* compute bitmask from p1 value */
8793         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8794         /* also FPA1 */
8795         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8796
8797         switch (crtc_state->dpll.p2) {
8798         case 5:
8799                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8800                 break;
8801         case 7:
8802                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8803                 break;
8804         case 10:
8805                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8806                 break;
8807         case 14:
8808                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8809                 break;
8810         }
8811
8812         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8813                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8814         else
8815                 dpll |= PLL_REF_INPUT_DREFCLK;
8816
8817         return dpll | DPLL_VCO_ENABLE;
8818 }
8819
8820 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8821                                        struct intel_crtc_state *crtc_state)
8822 {
8823         struct drm_device *dev = crtc->base.dev;
8824         intel_clock_t clock, reduced_clock;
8825         u32 dpll = 0, fp = 0, fp2 = 0;
8826         bool ok, has_reduced_clock = false;
8827         bool is_lvds = false;
8828         struct intel_shared_dpll *pll;
8829
8830         memset(&crtc_state->dpll_hw_state, 0,
8831                sizeof(crtc_state->dpll_hw_state));
8832
8833         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8834
8835         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8836              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8837
8838         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8839                                      &has_reduced_clock, &reduced_clock);
8840         if (!ok && !crtc_state->clock_set) {
8841                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8842                 return -EINVAL;
8843         }
8844         /* Compat-code for transition, will disappear. */
8845         if (!crtc_state->clock_set) {
8846                 crtc_state->dpll.n = clock.n;
8847                 crtc_state->dpll.m1 = clock.m1;
8848                 crtc_state->dpll.m2 = clock.m2;
8849                 crtc_state->dpll.p1 = clock.p1;
8850                 crtc_state->dpll.p2 = clock.p2;
8851         }
8852
8853         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8854         if (crtc_state->has_pch_encoder) {
8855                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8856                 if (has_reduced_clock)
8857                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8858
8859                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8860                                              &fp, &reduced_clock,
8861                                              has_reduced_clock ? &fp2 : NULL);
8862
8863                 crtc_state->dpll_hw_state.dpll = dpll;
8864                 crtc_state->dpll_hw_state.fp0 = fp;
8865                 if (has_reduced_clock)
8866                         crtc_state->dpll_hw_state.fp1 = fp2;
8867                 else
8868                         crtc_state->dpll_hw_state.fp1 = fp;
8869
8870                 pll = intel_get_shared_dpll(crtc, crtc_state);
8871                 if (pll == NULL) {
8872                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8873                                          pipe_name(crtc->pipe));
8874                         return -EINVAL;
8875                 }
8876         }
8877
8878         if (is_lvds && has_reduced_clock)
8879                 crtc->lowfreq_avail = true;
8880         else
8881                 crtc->lowfreq_avail = false;
8882
8883         return 0;
8884 }
8885
8886 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8887                                          struct intel_link_m_n *m_n)
8888 {
8889         struct drm_device *dev = crtc->base.dev;
8890         struct drm_i915_private *dev_priv = dev->dev_private;
8891         enum pipe pipe = crtc->pipe;
8892
8893         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8894         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8895         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8896                 & ~TU_SIZE_MASK;
8897         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8898         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8899                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8900 }
8901
8902 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8903                                          enum transcoder transcoder,
8904                                          struct intel_link_m_n *m_n,
8905                                          struct intel_link_m_n *m2_n2)
8906 {
8907         struct drm_device *dev = crtc->base.dev;
8908         struct drm_i915_private *dev_priv = dev->dev_private;
8909         enum pipe pipe = crtc->pipe;
8910
8911         if (INTEL_INFO(dev)->gen >= 5) {
8912                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8913                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8914                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8915                         & ~TU_SIZE_MASK;
8916                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8917                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8918                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8919                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8920                  * gen < 8) and if DRRS is supported (to make sure the
8921                  * registers are not unnecessarily read).
8922                  */
8923                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8924                         crtc->config->has_drrs) {
8925                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8926                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8927                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8928                                         & ~TU_SIZE_MASK;
8929                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8930                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8931                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8932                 }
8933         } else {
8934                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8935                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8936                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8937                         & ~TU_SIZE_MASK;
8938                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8939                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8940                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8941         }
8942 }
8943
8944 void intel_dp_get_m_n(struct intel_crtc *crtc,
8945                       struct intel_crtc_state *pipe_config)
8946 {
8947         if (pipe_config->has_pch_encoder)
8948                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8949         else
8950                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8951                                              &pipe_config->dp_m_n,
8952                                              &pipe_config->dp_m2_n2);
8953 }
8954
8955 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8956                                         struct intel_crtc_state *pipe_config)
8957 {
8958         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8959                                      &pipe_config->fdi_m_n, NULL);
8960 }
8961
8962 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8963                                     struct intel_crtc_state *pipe_config)
8964 {
8965         struct drm_device *dev = crtc->base.dev;
8966         struct drm_i915_private *dev_priv = dev->dev_private;
8967         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8968         uint32_t ps_ctrl = 0;
8969         int id = -1;
8970         int i;
8971
8972         /* find scaler attached to this pipe */
8973         for (i = 0; i < crtc->num_scalers; i++) {
8974                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8975                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8976                         id = i;
8977                         pipe_config->pch_pfit.enabled = true;
8978                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8979                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8980                         break;
8981                 }
8982         }
8983
8984         scaler_state->scaler_id = id;
8985         if (id >= 0) {
8986                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8987         } else {
8988                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8989         }
8990 }
8991
8992 static void
8993 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8994                                  struct intel_initial_plane_config *plane_config)
8995 {
8996         struct drm_device *dev = crtc->base.dev;
8997         struct drm_i915_private *dev_priv = dev->dev_private;
8998         u32 val, base, offset, stride_mult, tiling;
8999         int pipe = crtc->pipe;
9000         int fourcc, pixel_format;
9001         unsigned int aligned_height;
9002         struct drm_framebuffer *fb;
9003         struct intel_framebuffer *intel_fb;
9004
9005         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9006         if (!intel_fb) {
9007                 DRM_DEBUG_KMS("failed to alloc fb\n");
9008                 return;
9009         }
9010
9011         fb = &intel_fb->base;
9012
9013         val = I915_READ(PLANE_CTL(pipe, 0));
9014         if (!(val & PLANE_CTL_ENABLE))
9015                 goto error;
9016
9017         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9018         fourcc = skl_format_to_fourcc(pixel_format,
9019                                       val & PLANE_CTL_ORDER_RGBX,
9020                                       val & PLANE_CTL_ALPHA_MASK);
9021         fb->pixel_format = fourcc;
9022         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9023
9024         tiling = val & PLANE_CTL_TILED_MASK;
9025         switch (tiling) {
9026         case PLANE_CTL_TILED_LINEAR:
9027                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9028                 break;
9029         case PLANE_CTL_TILED_X:
9030                 plane_config->tiling = I915_TILING_X;
9031                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9032                 break;
9033         case PLANE_CTL_TILED_Y:
9034                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9035                 break;
9036         case PLANE_CTL_TILED_YF:
9037                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9038                 break;
9039         default:
9040                 MISSING_CASE(tiling);
9041                 goto error;
9042         }
9043
9044         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9045         plane_config->base = base;
9046
9047         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9048
9049         val = I915_READ(PLANE_SIZE(pipe, 0));
9050         fb->height = ((val >> 16) & 0xfff) + 1;
9051         fb->width = ((val >> 0) & 0x1fff) + 1;
9052
9053         val = I915_READ(PLANE_STRIDE(pipe, 0));
9054         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9055                                                 fb->pixel_format);
9056         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9057
9058         aligned_height = intel_fb_align_height(dev, fb->height,
9059                                                fb->pixel_format,
9060                                                fb->modifier[0]);
9061
9062         plane_config->size = fb->pitches[0] * aligned_height;
9063
9064         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9065                       pipe_name(pipe), fb->width, fb->height,
9066                       fb->bits_per_pixel, base, fb->pitches[0],
9067                       plane_config->size);
9068
9069         plane_config->fb = intel_fb;
9070         return;
9071
9072 error:
9073         kfree(fb);
9074 }
9075
9076 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9077                                      struct intel_crtc_state *pipe_config)
9078 {
9079         struct drm_device *dev = crtc->base.dev;
9080         struct drm_i915_private *dev_priv = dev->dev_private;
9081         uint32_t tmp;
9082
9083         tmp = I915_READ(PF_CTL(crtc->pipe));
9084
9085         if (tmp & PF_ENABLE) {
9086                 pipe_config->pch_pfit.enabled = true;
9087                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9088                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9089
9090                 /* We currently do not free assignements of panel fitters on
9091                  * ivb/hsw (since we don't use the higher upscaling modes which
9092                  * differentiates them) so just WARN about this case for now. */
9093                 if (IS_GEN7(dev)) {
9094                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9095                                 PF_PIPE_SEL_IVB(crtc->pipe));
9096                 }
9097         }
9098 }
9099
9100 static void
9101 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9102                                   struct intel_initial_plane_config *plane_config)
9103 {
9104         struct drm_device *dev = crtc->base.dev;
9105         struct drm_i915_private *dev_priv = dev->dev_private;
9106         u32 val, base, offset;
9107         int pipe = crtc->pipe;
9108         int fourcc, pixel_format;
9109         unsigned int aligned_height;
9110         struct drm_framebuffer *fb;
9111         struct intel_framebuffer *intel_fb;
9112
9113         val = I915_READ(DSPCNTR(pipe));
9114         if (!(val & DISPLAY_PLANE_ENABLE))
9115                 return;
9116
9117         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9118         if (!intel_fb) {
9119                 DRM_DEBUG_KMS("failed to alloc fb\n");
9120                 return;
9121         }
9122
9123         fb = &intel_fb->base;
9124
9125         if (INTEL_INFO(dev)->gen >= 4) {
9126                 if (val & DISPPLANE_TILED) {
9127                         plane_config->tiling = I915_TILING_X;
9128                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9129                 }
9130         }
9131
9132         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9133         fourcc = i9xx_format_to_fourcc(pixel_format);
9134         fb->pixel_format = fourcc;
9135         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9136
9137         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9138         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9139                 offset = I915_READ(DSPOFFSET(pipe));
9140         } else {
9141                 if (plane_config->tiling)
9142                         offset = I915_READ(DSPTILEOFF(pipe));
9143                 else
9144                         offset = I915_READ(DSPLINOFF(pipe));
9145         }
9146         plane_config->base = base;
9147
9148         val = I915_READ(PIPESRC(pipe));
9149         fb->width = ((val >> 16) & 0xfff) + 1;
9150         fb->height = ((val >> 0) & 0xfff) + 1;
9151
9152         val = I915_READ(DSPSTRIDE(pipe));
9153         fb->pitches[0] = val & 0xffffffc0;
9154
9155         aligned_height = intel_fb_align_height(dev, fb->height,
9156                                                fb->pixel_format,
9157                                                fb->modifier[0]);
9158
9159         plane_config->size = fb->pitches[0] * aligned_height;
9160
9161         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9162                       pipe_name(pipe), fb->width, fb->height,
9163                       fb->bits_per_pixel, base, fb->pitches[0],
9164                       plane_config->size);
9165
9166         plane_config->fb = intel_fb;
9167 }
9168
9169 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9170                                      struct intel_crtc_state *pipe_config)
9171 {
9172         struct drm_device *dev = crtc->base.dev;
9173         struct drm_i915_private *dev_priv = dev->dev_private;
9174         uint32_t tmp;
9175
9176         if (!intel_display_power_is_enabled(dev_priv,
9177                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9178                 return false;
9179
9180         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9181         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9182
9183         tmp = I915_READ(PIPECONF(crtc->pipe));
9184         if (!(tmp & PIPECONF_ENABLE))
9185                 return false;
9186
9187         switch (tmp & PIPECONF_BPC_MASK) {
9188         case PIPECONF_6BPC:
9189                 pipe_config->pipe_bpp = 18;
9190                 break;
9191         case PIPECONF_8BPC:
9192                 pipe_config->pipe_bpp = 24;
9193                 break;
9194         case PIPECONF_10BPC:
9195                 pipe_config->pipe_bpp = 30;
9196                 break;
9197         case PIPECONF_12BPC:
9198                 pipe_config->pipe_bpp = 36;
9199                 break;
9200         default:
9201                 break;
9202         }
9203
9204         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9205                 pipe_config->limited_color_range = true;
9206
9207         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9208                 struct intel_shared_dpll *pll;
9209
9210                 pipe_config->has_pch_encoder = true;
9211
9212                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9213                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9214                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9215
9216                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9217
9218                 if (HAS_PCH_IBX(dev_priv->dev)) {
9219                         pipe_config->shared_dpll =
9220                                 (enum intel_dpll_id) crtc->pipe;
9221                 } else {
9222                         tmp = I915_READ(PCH_DPLL_SEL);
9223                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9224                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9225                         else
9226                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9227                 }
9228
9229                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9230
9231                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9232                                            &pipe_config->dpll_hw_state));
9233
9234                 tmp = pipe_config->dpll_hw_state.dpll;
9235                 pipe_config->pixel_multiplier =
9236                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9237                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9238
9239                 ironlake_pch_clock_get(crtc, pipe_config);
9240         } else {
9241                 pipe_config->pixel_multiplier = 1;
9242         }
9243
9244         intel_get_pipe_timings(crtc, pipe_config);
9245
9246         ironlake_get_pfit_config(crtc, pipe_config);
9247
9248         return true;
9249 }
9250
9251 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9252 {
9253         struct drm_device *dev = dev_priv->dev;
9254         struct intel_crtc *crtc;
9255
9256         for_each_intel_crtc(dev, crtc)
9257                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9258                      pipe_name(crtc->pipe));
9259
9260         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9261         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9262         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9263         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9264         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9265         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9266              "CPU PWM1 enabled\n");
9267         if (IS_HASWELL(dev))
9268                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9269                      "CPU PWM2 enabled\n");
9270         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9271              "PCH PWM1 enabled\n");
9272         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9273              "Utility pin enabled\n");
9274         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9275
9276         /*
9277          * In theory we can still leave IRQs enabled, as long as only the HPD
9278          * interrupts remain enabled. We used to check for that, but since it's
9279          * gen-specific and since we only disable LCPLL after we fully disable
9280          * the interrupts, the check below should be enough.
9281          */
9282         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9283 }
9284
9285 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9286 {
9287         struct drm_device *dev = dev_priv->dev;
9288
9289         if (IS_HASWELL(dev))
9290                 return I915_READ(D_COMP_HSW);
9291         else
9292                 return I915_READ(D_COMP_BDW);
9293 }
9294
9295 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9296 {
9297         struct drm_device *dev = dev_priv->dev;
9298
9299         if (IS_HASWELL(dev)) {
9300                 mutex_lock(&dev_priv->rps.hw_lock);
9301                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9302                                             val))
9303                         DRM_ERROR("Failed to write to D_COMP\n");
9304                 mutex_unlock(&dev_priv->rps.hw_lock);
9305         } else {
9306                 I915_WRITE(D_COMP_BDW, val);
9307                 POSTING_READ(D_COMP_BDW);
9308         }
9309 }
9310
9311 /*
9312  * This function implements pieces of two sequences from BSpec:
9313  * - Sequence for display software to disable LCPLL
9314  * - Sequence for display software to allow package C8+
9315  * The steps implemented here are just the steps that actually touch the LCPLL
9316  * register. Callers should take care of disabling all the display engine
9317  * functions, doing the mode unset, fixing interrupts, etc.
9318  */
9319 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9320                               bool switch_to_fclk, bool allow_power_down)
9321 {
9322         uint32_t val;
9323
9324         assert_can_disable_lcpll(dev_priv);
9325
9326         val = I915_READ(LCPLL_CTL);
9327
9328         if (switch_to_fclk) {
9329                 val |= LCPLL_CD_SOURCE_FCLK;
9330                 I915_WRITE(LCPLL_CTL, val);
9331
9332                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9333                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9334                         DRM_ERROR("Switching to FCLK failed\n");
9335
9336                 val = I915_READ(LCPLL_CTL);
9337         }
9338
9339         val |= LCPLL_PLL_DISABLE;
9340         I915_WRITE(LCPLL_CTL, val);
9341         POSTING_READ(LCPLL_CTL);
9342
9343         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9344                 DRM_ERROR("LCPLL still locked\n");
9345
9346         val = hsw_read_dcomp(dev_priv);
9347         val |= D_COMP_COMP_DISABLE;
9348         hsw_write_dcomp(dev_priv, val);
9349         ndelay(100);
9350
9351         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9352                      1))
9353                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9354
9355         if (allow_power_down) {
9356                 val = I915_READ(LCPLL_CTL);
9357                 val |= LCPLL_POWER_DOWN_ALLOW;
9358                 I915_WRITE(LCPLL_CTL, val);
9359                 POSTING_READ(LCPLL_CTL);
9360         }
9361 }
9362
9363 /*
9364  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9365  * source.
9366  */
9367 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9368 {
9369         uint32_t val;
9370
9371         val = I915_READ(LCPLL_CTL);
9372
9373         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9374                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9375                 return;
9376
9377         /*
9378          * Make sure we're not on PC8 state before disabling PC8, otherwise
9379          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9380          */
9381         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9382
9383         if (val & LCPLL_POWER_DOWN_ALLOW) {
9384                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9385                 I915_WRITE(LCPLL_CTL, val);
9386                 POSTING_READ(LCPLL_CTL);
9387         }
9388
9389         val = hsw_read_dcomp(dev_priv);
9390         val |= D_COMP_COMP_FORCE;
9391         val &= ~D_COMP_COMP_DISABLE;
9392         hsw_write_dcomp(dev_priv, val);
9393
9394         val = I915_READ(LCPLL_CTL);
9395         val &= ~LCPLL_PLL_DISABLE;
9396         I915_WRITE(LCPLL_CTL, val);
9397
9398         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9399                 DRM_ERROR("LCPLL not locked yet\n");
9400
9401         if (val & LCPLL_CD_SOURCE_FCLK) {
9402                 val = I915_READ(LCPLL_CTL);
9403                 val &= ~LCPLL_CD_SOURCE_FCLK;
9404                 I915_WRITE(LCPLL_CTL, val);
9405
9406                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9407                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9408                         DRM_ERROR("Switching back to LCPLL failed\n");
9409         }
9410
9411         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9412         intel_update_cdclk(dev_priv->dev);
9413 }
9414
9415 /*
9416  * Package states C8 and deeper are really deep PC states that can only be
9417  * reached when all the devices on the system allow it, so even if the graphics
9418  * device allows PC8+, it doesn't mean the system will actually get to these
9419  * states. Our driver only allows PC8+ when going into runtime PM.
9420  *
9421  * The requirements for PC8+ are that all the outputs are disabled, the power
9422  * well is disabled and most interrupts are disabled, and these are also
9423  * requirements for runtime PM. When these conditions are met, we manually do
9424  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9425  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9426  * hang the machine.
9427  *
9428  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9429  * the state of some registers, so when we come back from PC8+ we need to
9430  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9431  * need to take care of the registers kept by RC6. Notice that this happens even
9432  * if we don't put the device in PCI D3 state (which is what currently happens
9433  * because of the runtime PM support).
9434  *
9435  * For more, read "Display Sequences for Package C8" on the hardware
9436  * documentation.
9437  */
9438 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9439 {
9440         struct drm_device *dev = dev_priv->dev;
9441         uint32_t val;
9442
9443         DRM_DEBUG_KMS("Enabling package C8+\n");
9444
9445         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9446                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9447                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9448                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9449         }
9450
9451         lpt_disable_clkout_dp(dev);
9452         hsw_disable_lcpll(dev_priv, true, true);
9453 }
9454
9455 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9456 {
9457         struct drm_device *dev = dev_priv->dev;
9458         uint32_t val;
9459
9460         DRM_DEBUG_KMS("Disabling package C8+\n");
9461
9462         hsw_restore_lcpll(dev_priv);
9463         lpt_init_pch_refclk(dev);
9464
9465         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9466                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9467                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9468                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9469         }
9470
9471         intel_prepare_ddi(dev);
9472 }
9473
9474 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9475 {
9476         struct drm_device *dev = old_state->dev;
9477         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9478
9479         broxton_set_cdclk(dev, req_cdclk);
9480 }
9481
9482 /* compute the max rate for new configuration */
9483 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9484 {
9485         struct intel_crtc *intel_crtc;
9486         struct intel_crtc_state *crtc_state;
9487         int max_pixel_rate = 0;
9488
9489         for_each_intel_crtc(state->dev, intel_crtc) {
9490                 int pixel_rate;
9491
9492                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9493                 if (IS_ERR(crtc_state))
9494                         return PTR_ERR(crtc_state);
9495
9496                 if (!crtc_state->base.enable)
9497                         continue;
9498
9499                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9500
9501                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9502                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9503                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9504
9505                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9506         }
9507
9508         return max_pixel_rate;
9509 }
9510
9511 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9512 {
9513         struct drm_i915_private *dev_priv = dev->dev_private;
9514         uint32_t val, data;
9515         int ret;
9516
9517         if (WARN((I915_READ(LCPLL_CTL) &
9518                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9519                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9520                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9521                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9522                  "trying to change cdclk frequency with cdclk not enabled\n"))
9523                 return;
9524
9525         mutex_lock(&dev_priv->rps.hw_lock);
9526         ret = sandybridge_pcode_write(dev_priv,
9527                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9528         mutex_unlock(&dev_priv->rps.hw_lock);
9529         if (ret) {
9530                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9531                 return;
9532         }
9533
9534         val = I915_READ(LCPLL_CTL);
9535         val |= LCPLL_CD_SOURCE_FCLK;
9536         I915_WRITE(LCPLL_CTL, val);
9537
9538         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9539                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9540                 DRM_ERROR("Switching to FCLK failed\n");
9541
9542         val = I915_READ(LCPLL_CTL);
9543         val &= ~LCPLL_CLK_FREQ_MASK;
9544
9545         switch (cdclk) {
9546         case 450000:
9547                 val |= LCPLL_CLK_FREQ_450;
9548                 data = 0;
9549                 break;
9550         case 540000:
9551                 val |= LCPLL_CLK_FREQ_54O_BDW;
9552                 data = 1;
9553                 break;
9554         case 337500:
9555                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9556                 data = 2;
9557                 break;
9558         case 675000:
9559                 val |= LCPLL_CLK_FREQ_675_BDW;
9560                 data = 3;
9561                 break;
9562         default:
9563                 WARN(1, "invalid cdclk frequency\n");
9564                 return;
9565         }
9566
9567         I915_WRITE(LCPLL_CTL, val);
9568
9569         val = I915_READ(LCPLL_CTL);
9570         val &= ~LCPLL_CD_SOURCE_FCLK;
9571         I915_WRITE(LCPLL_CTL, val);
9572
9573         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9574                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9575                 DRM_ERROR("Switching back to LCPLL failed\n");
9576
9577         mutex_lock(&dev_priv->rps.hw_lock);
9578         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9579         mutex_unlock(&dev_priv->rps.hw_lock);
9580
9581         intel_update_cdclk(dev);
9582
9583         WARN(cdclk != dev_priv->cdclk_freq,
9584              "cdclk requested %d kHz but got %d kHz\n",
9585              cdclk, dev_priv->cdclk_freq);
9586 }
9587
9588 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9589 {
9590         struct drm_i915_private *dev_priv = to_i915(state->dev);
9591         int max_pixclk = ilk_max_pixel_rate(state);
9592         int cdclk;
9593
9594         /*
9595          * FIXME should also account for plane ratio
9596          * once 64bpp pixel formats are supported.
9597          */
9598         if (max_pixclk > 540000)
9599                 cdclk = 675000;
9600         else if (max_pixclk > 450000)
9601                 cdclk = 540000;
9602         else if (max_pixclk > 337500)
9603                 cdclk = 450000;
9604         else
9605                 cdclk = 337500;
9606
9607         /*
9608          * FIXME move the cdclk caclulation to
9609          * compute_config() so we can fail gracegully.
9610          */
9611         if (cdclk > dev_priv->max_cdclk_freq) {
9612                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9613                           cdclk, dev_priv->max_cdclk_freq);
9614                 cdclk = dev_priv->max_cdclk_freq;
9615         }
9616
9617         to_intel_atomic_state(state)->cdclk = cdclk;
9618
9619         return 0;
9620 }
9621
9622 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9623 {
9624         struct drm_device *dev = old_state->dev;
9625         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9626
9627         broadwell_set_cdclk(dev, req_cdclk);
9628 }
9629
9630 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9631                                       struct intel_crtc_state *crtc_state)
9632 {
9633         if (!intel_ddi_pll_select(crtc, crtc_state))
9634                 return -EINVAL;
9635
9636         crtc->lowfreq_avail = false;
9637
9638         return 0;
9639 }
9640
9641 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9642                                 enum port port,
9643                                 struct intel_crtc_state *pipe_config)
9644 {
9645         switch (port) {
9646         case PORT_A:
9647                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9648                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9649                 break;
9650         case PORT_B:
9651                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9652                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9653                 break;
9654         case PORT_C:
9655                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9656                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9657                 break;
9658         default:
9659                 DRM_ERROR("Incorrect port type\n");
9660         }
9661 }
9662
9663 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9664                                 enum port port,
9665                                 struct intel_crtc_state *pipe_config)
9666 {
9667         u32 temp, dpll_ctl1;
9668
9669         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9670         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9671
9672         switch (pipe_config->ddi_pll_sel) {
9673         case SKL_DPLL0:
9674                 /*
9675                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9676                  * of the shared DPLL framework and thus needs to be read out
9677                  * separately
9678                  */
9679                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9680                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9681                 break;
9682         case SKL_DPLL1:
9683                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9684                 break;
9685         case SKL_DPLL2:
9686                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9687                 break;
9688         case SKL_DPLL3:
9689                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9690                 break;
9691         }
9692 }
9693
9694 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9695                                 enum port port,
9696                                 struct intel_crtc_state *pipe_config)
9697 {
9698         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9699
9700         switch (pipe_config->ddi_pll_sel) {
9701         case PORT_CLK_SEL_WRPLL1:
9702                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9703                 break;
9704         case PORT_CLK_SEL_WRPLL2:
9705                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9706                 break;
9707         }
9708 }
9709
9710 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9711                                        struct intel_crtc_state *pipe_config)
9712 {
9713         struct drm_device *dev = crtc->base.dev;
9714         struct drm_i915_private *dev_priv = dev->dev_private;
9715         struct intel_shared_dpll *pll;
9716         enum port port;
9717         uint32_t tmp;
9718
9719         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9720
9721         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9722
9723         if (IS_SKYLAKE(dev))
9724                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9725         else if (IS_BROXTON(dev))
9726                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9727         else
9728                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9729
9730         if (pipe_config->shared_dpll >= 0) {
9731                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9732
9733                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9734                                            &pipe_config->dpll_hw_state));
9735         }
9736
9737         /*
9738          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9739          * DDI E. So just check whether this pipe is wired to DDI E and whether
9740          * the PCH transcoder is on.
9741          */
9742         if (INTEL_INFO(dev)->gen < 9 &&
9743             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9744                 pipe_config->has_pch_encoder = true;
9745
9746                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9747                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9748                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9749
9750                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9751         }
9752 }
9753
9754 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9755                                     struct intel_crtc_state *pipe_config)
9756 {
9757         struct drm_device *dev = crtc->base.dev;
9758         struct drm_i915_private *dev_priv = dev->dev_private;
9759         enum intel_display_power_domain pfit_domain;
9760         uint32_t tmp;
9761
9762         if (!intel_display_power_is_enabled(dev_priv,
9763                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9764                 return false;
9765
9766         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9767         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9768
9769         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9770         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9771                 enum pipe trans_edp_pipe;
9772                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9773                 default:
9774                         WARN(1, "unknown pipe linked to edp transcoder\n");
9775                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9776                 case TRANS_DDI_EDP_INPUT_A_ON:
9777                         trans_edp_pipe = PIPE_A;
9778                         break;
9779                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9780                         trans_edp_pipe = PIPE_B;
9781                         break;
9782                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9783                         trans_edp_pipe = PIPE_C;
9784                         break;
9785                 }
9786
9787                 if (trans_edp_pipe == crtc->pipe)
9788                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9789         }
9790
9791         if (!intel_display_power_is_enabled(dev_priv,
9792                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9793                 return false;
9794
9795         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9796         if (!(tmp & PIPECONF_ENABLE))
9797                 return false;
9798
9799         haswell_get_ddi_port_state(crtc, pipe_config);
9800
9801         intel_get_pipe_timings(crtc, pipe_config);
9802
9803         if (INTEL_INFO(dev)->gen >= 9) {
9804                 skl_init_scalers(dev, crtc, pipe_config);
9805         }
9806
9807         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9808
9809         if (INTEL_INFO(dev)->gen >= 9) {
9810                 pipe_config->scaler_state.scaler_id = -1;
9811                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9812         }
9813
9814         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9815                 if (INTEL_INFO(dev)->gen == 9)
9816                         skylake_get_pfit_config(crtc, pipe_config);
9817                 else if (INTEL_INFO(dev)->gen < 9)
9818                         ironlake_get_pfit_config(crtc, pipe_config);
9819                 else
9820                         MISSING_CASE(INTEL_INFO(dev)->gen);
9821         }
9822
9823         if (IS_HASWELL(dev))
9824                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9825                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9826
9827         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9828                 pipe_config->pixel_multiplier =
9829                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9830         } else {
9831                 pipe_config->pixel_multiplier = 1;
9832         }
9833
9834         return true;
9835 }
9836
9837 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9838 {
9839         struct drm_device *dev = crtc->dev;
9840         struct drm_i915_private *dev_priv = dev->dev_private;
9841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9842         uint32_t cntl = 0, size = 0;
9843
9844         if (base) {
9845                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9846                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9847                 unsigned int stride = roundup_pow_of_two(width) * 4;
9848
9849                 switch (stride) {
9850                 default:
9851                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9852                                   width, stride);
9853                         stride = 256;
9854                         /* fallthrough */
9855                 case 256:
9856                 case 512:
9857                 case 1024:
9858                 case 2048:
9859                         break;
9860                 }
9861
9862                 cntl |= CURSOR_ENABLE |
9863                         CURSOR_GAMMA_ENABLE |
9864                         CURSOR_FORMAT_ARGB |
9865                         CURSOR_STRIDE(stride);
9866
9867                 size = (height << 12) | width;
9868         }
9869
9870         if (intel_crtc->cursor_cntl != 0 &&
9871             (intel_crtc->cursor_base != base ||
9872              intel_crtc->cursor_size != size ||
9873              intel_crtc->cursor_cntl != cntl)) {
9874                 /* On these chipsets we can only modify the base/size/stride
9875                  * whilst the cursor is disabled.
9876                  */
9877                 I915_WRITE(_CURACNTR, 0);
9878                 POSTING_READ(_CURACNTR);
9879                 intel_crtc->cursor_cntl = 0;
9880         }
9881
9882         if (intel_crtc->cursor_base != base) {
9883                 I915_WRITE(_CURABASE, base);
9884                 intel_crtc->cursor_base = base;
9885         }
9886
9887         if (intel_crtc->cursor_size != size) {
9888                 I915_WRITE(CURSIZE, size);
9889                 intel_crtc->cursor_size = size;
9890         }
9891
9892         if (intel_crtc->cursor_cntl != cntl) {
9893                 I915_WRITE(_CURACNTR, cntl);
9894                 POSTING_READ(_CURACNTR);
9895                 intel_crtc->cursor_cntl = cntl;
9896         }
9897 }
9898
9899 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9900 {
9901         struct drm_device *dev = crtc->dev;
9902         struct drm_i915_private *dev_priv = dev->dev_private;
9903         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9904         int pipe = intel_crtc->pipe;
9905         uint32_t cntl;
9906
9907         cntl = 0;
9908         if (base) {
9909                 cntl = MCURSOR_GAMMA_ENABLE;
9910                 switch (intel_crtc->base.cursor->state->crtc_w) {
9911                         case 64:
9912                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9913                                 break;
9914                         case 128:
9915                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9916                                 break;
9917                         case 256:
9918                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9919                                 break;
9920                         default:
9921                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9922                                 return;
9923                 }
9924                 cntl |= pipe << 28; /* Connect to correct pipe */
9925
9926                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9927                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9928         }
9929
9930         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9931                 cntl |= CURSOR_ROTATE_180;
9932
9933         if (intel_crtc->cursor_cntl != cntl) {
9934                 I915_WRITE(CURCNTR(pipe), cntl);
9935                 POSTING_READ(CURCNTR(pipe));
9936                 intel_crtc->cursor_cntl = cntl;
9937         }
9938
9939         /* and commit changes on next vblank */
9940         I915_WRITE(CURBASE(pipe), base);
9941         POSTING_READ(CURBASE(pipe));
9942
9943         intel_crtc->cursor_base = base;
9944 }
9945
9946 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9947 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9948                                      bool on)
9949 {
9950         struct drm_device *dev = crtc->dev;
9951         struct drm_i915_private *dev_priv = dev->dev_private;
9952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9953         int pipe = intel_crtc->pipe;
9954         int x = crtc->cursor_x;
9955         int y = crtc->cursor_y;
9956         u32 base = 0, pos = 0;
9957
9958         if (on)
9959                 base = intel_crtc->cursor_addr;
9960
9961         if (x >= intel_crtc->config->pipe_src_w)
9962                 base = 0;
9963
9964         if (y >= intel_crtc->config->pipe_src_h)
9965                 base = 0;
9966
9967         if (x < 0) {
9968                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9969                         base = 0;
9970
9971                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9972                 x = -x;
9973         }
9974         pos |= x << CURSOR_X_SHIFT;
9975
9976         if (y < 0) {
9977                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9978                         base = 0;
9979
9980                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9981                 y = -y;
9982         }
9983         pos |= y << CURSOR_Y_SHIFT;
9984
9985         if (base == 0 && intel_crtc->cursor_base == 0)
9986                 return;
9987
9988         I915_WRITE(CURPOS(pipe), pos);
9989
9990         /* ILK+ do this automagically */
9991         if (HAS_GMCH_DISPLAY(dev) &&
9992             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9993                 base += (intel_crtc->base.cursor->state->crtc_h *
9994                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9995         }
9996
9997         if (IS_845G(dev) || IS_I865G(dev))
9998                 i845_update_cursor(crtc, base);
9999         else
10000                 i9xx_update_cursor(crtc, base);
10001 }
10002
10003 static bool cursor_size_ok(struct drm_device *dev,
10004                            uint32_t width, uint32_t height)
10005 {
10006         if (width == 0 || height == 0)
10007                 return false;
10008
10009         /*
10010          * 845g/865g are special in that they are only limited by
10011          * the width of their cursors, the height is arbitrary up to
10012          * the precision of the register. Everything else requires
10013          * square cursors, limited to a few power-of-two sizes.
10014          */
10015         if (IS_845G(dev) || IS_I865G(dev)) {
10016                 if ((width & 63) != 0)
10017                         return false;
10018
10019                 if (width > (IS_845G(dev) ? 64 : 512))
10020                         return false;
10021
10022                 if (height > 1023)
10023                         return false;
10024         } else {
10025                 switch (width | height) {
10026                 case 256:
10027                 case 128:
10028                         if (IS_GEN2(dev))
10029                                 return false;
10030                 case 64:
10031                         break;
10032                 default:
10033                         return false;
10034                 }
10035         }
10036
10037         return true;
10038 }
10039
10040 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10041                                  u16 *blue, uint32_t start, uint32_t size)
10042 {
10043         int end = (start + size > 256) ? 256 : start + size, i;
10044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10045
10046         for (i = start; i < end; i++) {
10047                 intel_crtc->lut_r[i] = red[i] >> 8;
10048                 intel_crtc->lut_g[i] = green[i] >> 8;
10049                 intel_crtc->lut_b[i] = blue[i] >> 8;
10050         }
10051
10052         intel_crtc_load_lut(crtc);
10053 }
10054
10055 /* VESA 640x480x72Hz mode to set on the pipe */
10056 static struct drm_display_mode load_detect_mode = {
10057         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10058                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10059 };
10060
10061 struct drm_framebuffer *
10062 __intel_framebuffer_create(struct drm_device *dev,
10063                            struct drm_mode_fb_cmd2 *mode_cmd,
10064                            struct drm_i915_gem_object *obj)
10065 {
10066         struct intel_framebuffer *intel_fb;
10067         int ret;
10068
10069         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10070         if (!intel_fb) {
10071                 drm_gem_object_unreference(&obj->base);
10072                 return ERR_PTR(-ENOMEM);
10073         }
10074
10075         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10076         if (ret)
10077                 goto err;
10078
10079         return &intel_fb->base;
10080 err:
10081         drm_gem_object_unreference(&obj->base);
10082         kfree(intel_fb);
10083
10084         return ERR_PTR(ret);
10085 }
10086
10087 static struct drm_framebuffer *
10088 intel_framebuffer_create(struct drm_device *dev,
10089                          struct drm_mode_fb_cmd2 *mode_cmd,
10090                          struct drm_i915_gem_object *obj)
10091 {
10092         struct drm_framebuffer *fb;
10093         int ret;
10094
10095         ret = i915_mutex_lock_interruptible(dev);
10096         if (ret)
10097                 return ERR_PTR(ret);
10098         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10099         mutex_unlock(&dev->struct_mutex);
10100
10101         return fb;
10102 }
10103
10104 static u32
10105 intel_framebuffer_pitch_for_width(int width, int bpp)
10106 {
10107         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10108         return ALIGN(pitch, 64);
10109 }
10110
10111 static u32
10112 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10113 {
10114         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10115         return PAGE_ALIGN(pitch * mode->vdisplay);
10116 }
10117
10118 static struct drm_framebuffer *
10119 intel_framebuffer_create_for_mode(struct drm_device *dev,
10120                                   struct drm_display_mode *mode,
10121                                   int depth, int bpp)
10122 {
10123         struct drm_i915_gem_object *obj;
10124         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10125
10126         obj = i915_gem_alloc_object(dev,
10127                                     intel_framebuffer_size_for_mode(mode, bpp));
10128         if (obj == NULL)
10129                 return ERR_PTR(-ENOMEM);
10130
10131         mode_cmd.width = mode->hdisplay;
10132         mode_cmd.height = mode->vdisplay;
10133         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10134                                                                 bpp);
10135         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10136
10137         return intel_framebuffer_create(dev, &mode_cmd, obj);
10138 }
10139
10140 static struct drm_framebuffer *
10141 mode_fits_in_fbdev(struct drm_device *dev,
10142                    struct drm_display_mode *mode)
10143 {
10144 #ifdef CONFIG_DRM_I915_FBDEV
10145         struct drm_i915_private *dev_priv = dev->dev_private;
10146         struct drm_i915_gem_object *obj;
10147         struct drm_framebuffer *fb;
10148
10149         if (!dev_priv->fbdev)
10150                 return NULL;
10151
10152         if (!dev_priv->fbdev->fb)
10153                 return NULL;
10154
10155         obj = dev_priv->fbdev->fb->obj;
10156         BUG_ON(!obj);
10157
10158         fb = &dev_priv->fbdev->fb->base;
10159         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10160                                                                fb->bits_per_pixel))
10161                 return NULL;
10162
10163         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10164                 return NULL;
10165
10166         return fb;
10167 #else
10168         return NULL;
10169 #endif
10170 }
10171
10172 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10173                                            struct drm_crtc *crtc,
10174                                            struct drm_display_mode *mode,
10175                                            struct drm_framebuffer *fb,
10176                                            int x, int y)
10177 {
10178         struct drm_plane_state *plane_state;
10179         int hdisplay, vdisplay;
10180         int ret;
10181
10182         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10183         if (IS_ERR(plane_state))
10184                 return PTR_ERR(plane_state);
10185
10186         if (mode)
10187                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10188         else
10189                 hdisplay = vdisplay = 0;
10190
10191         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10192         if (ret)
10193                 return ret;
10194         drm_atomic_set_fb_for_plane(plane_state, fb);
10195         plane_state->crtc_x = 0;
10196         plane_state->crtc_y = 0;
10197         plane_state->crtc_w = hdisplay;
10198         plane_state->crtc_h = vdisplay;
10199         plane_state->src_x = x << 16;
10200         plane_state->src_y = y << 16;
10201         plane_state->src_w = hdisplay << 16;
10202         plane_state->src_h = vdisplay << 16;
10203
10204         return 0;
10205 }
10206
10207 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10208                                 struct drm_display_mode *mode,
10209                                 struct intel_load_detect_pipe *old,
10210                                 struct drm_modeset_acquire_ctx *ctx)
10211 {
10212         struct intel_crtc *intel_crtc;
10213         struct intel_encoder *intel_encoder =
10214                 intel_attached_encoder(connector);
10215         struct drm_crtc *possible_crtc;
10216         struct drm_encoder *encoder = &intel_encoder->base;
10217         struct drm_crtc *crtc = NULL;
10218         struct drm_device *dev = encoder->dev;
10219         struct drm_framebuffer *fb;
10220         struct drm_mode_config *config = &dev->mode_config;
10221         struct drm_atomic_state *state = NULL;
10222         struct drm_connector_state *connector_state;
10223         struct intel_crtc_state *crtc_state;
10224         int ret, i = -1;
10225
10226         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10227                       connector->base.id, connector->name,
10228                       encoder->base.id, encoder->name);
10229
10230 retry:
10231         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10232         if (ret)
10233                 goto fail_unlock;
10234
10235         /*
10236          * Algorithm gets a little messy:
10237          *
10238          *   - if the connector already has an assigned crtc, use it (but make
10239          *     sure it's on first)
10240          *
10241          *   - try to find the first unused crtc that can drive this connector,
10242          *     and use that if we find one
10243          */
10244
10245         /* See if we already have a CRTC for this connector */
10246         if (encoder->crtc) {
10247                 crtc = encoder->crtc;
10248
10249                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10250                 if (ret)
10251                         goto fail_unlock;
10252                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10253                 if (ret)
10254                         goto fail_unlock;
10255
10256                 old->dpms_mode = connector->dpms;
10257                 old->load_detect_temp = false;
10258
10259                 /* Make sure the crtc and connector are running */
10260                 if (connector->dpms != DRM_MODE_DPMS_ON)
10261                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10262
10263                 return true;
10264         }
10265
10266         /* Find an unused one (if possible) */
10267         for_each_crtc(dev, possible_crtc) {
10268                 i++;
10269                 if (!(encoder->possible_crtcs & (1 << i)))
10270                         continue;
10271                 if (possible_crtc->state->enable)
10272                         continue;
10273                 /* This can occur when applying the pipe A quirk on resume. */
10274                 if (to_intel_crtc(possible_crtc)->new_enabled)
10275                         continue;
10276
10277                 crtc = possible_crtc;
10278                 break;
10279         }
10280
10281         /*
10282          * If we didn't find an unused CRTC, don't use any.
10283          */
10284         if (!crtc) {
10285                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10286                 goto fail_unlock;
10287         }
10288
10289         ret = drm_modeset_lock(&crtc->mutex, ctx);
10290         if (ret)
10291                 goto fail_unlock;
10292         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10293         if (ret)
10294                 goto fail_unlock;
10295         intel_encoder->new_crtc = to_intel_crtc(crtc);
10296         to_intel_connector(connector)->new_encoder = intel_encoder;
10297
10298         intel_crtc = to_intel_crtc(crtc);
10299         intel_crtc->new_enabled = true;
10300         old->dpms_mode = connector->dpms;
10301         old->load_detect_temp = true;
10302         old->release_fb = NULL;
10303
10304         state = drm_atomic_state_alloc(dev);
10305         if (!state)
10306                 return false;
10307
10308         state->acquire_ctx = ctx;
10309
10310         connector_state = drm_atomic_get_connector_state(state, connector);
10311         if (IS_ERR(connector_state)) {
10312                 ret = PTR_ERR(connector_state);
10313                 goto fail;
10314         }
10315
10316         connector_state->crtc = crtc;
10317         connector_state->best_encoder = &intel_encoder->base;
10318
10319         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10320         if (IS_ERR(crtc_state)) {
10321                 ret = PTR_ERR(crtc_state);
10322                 goto fail;
10323         }
10324
10325         crtc_state->base.active = crtc_state->base.enable = true;
10326
10327         if (!mode)
10328                 mode = &load_detect_mode;
10329
10330         /* We need a framebuffer large enough to accommodate all accesses
10331          * that the plane may generate whilst we perform load detection.
10332          * We can not rely on the fbcon either being present (we get called
10333          * during its initialisation to detect all boot displays, or it may
10334          * not even exist) or that it is large enough to satisfy the
10335          * requested mode.
10336          */
10337         fb = mode_fits_in_fbdev(dev, mode);
10338         if (fb == NULL) {
10339                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10340                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10341                 old->release_fb = fb;
10342         } else
10343                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10344         if (IS_ERR(fb)) {
10345                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10346                 goto fail;
10347         }
10348
10349         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10350         if (ret)
10351                 goto fail;
10352
10353         drm_mode_copy(&crtc_state->base.mode, mode);
10354
10355         if (intel_set_mode(state)) {
10356                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10357                 if (old->release_fb)
10358                         old->release_fb->funcs->destroy(old->release_fb);
10359                 goto fail;
10360         }
10361         crtc->primary->crtc = crtc;
10362
10363         /* let the connector get through one full cycle before testing */
10364         intel_wait_for_vblank(dev, intel_crtc->pipe);
10365         return true;
10366
10367  fail:
10368         intel_crtc->new_enabled = crtc->state->enable;
10369 fail_unlock:
10370         drm_atomic_state_free(state);
10371         state = NULL;
10372
10373         if (ret == -EDEADLK) {
10374                 drm_modeset_backoff(ctx);
10375                 goto retry;
10376         }
10377
10378         return false;
10379 }
10380
10381 void intel_release_load_detect_pipe(struct drm_connector *connector,
10382                                     struct intel_load_detect_pipe *old,
10383                                     struct drm_modeset_acquire_ctx *ctx)
10384 {
10385         struct drm_device *dev = connector->dev;
10386         struct intel_encoder *intel_encoder =
10387                 intel_attached_encoder(connector);
10388         struct drm_encoder *encoder = &intel_encoder->base;
10389         struct drm_crtc *crtc = encoder->crtc;
10390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10391         struct drm_atomic_state *state;
10392         struct drm_connector_state *connector_state;
10393         struct intel_crtc_state *crtc_state;
10394         int ret;
10395
10396         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10397                       connector->base.id, connector->name,
10398                       encoder->base.id, encoder->name);
10399
10400         if (old->load_detect_temp) {
10401                 state = drm_atomic_state_alloc(dev);
10402                 if (!state)
10403                         goto fail;
10404
10405                 state->acquire_ctx = ctx;
10406
10407                 connector_state = drm_atomic_get_connector_state(state, connector);
10408                 if (IS_ERR(connector_state))
10409                         goto fail;
10410
10411                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10412                 if (IS_ERR(crtc_state))
10413                         goto fail;
10414
10415                 to_intel_connector(connector)->new_encoder = NULL;
10416                 intel_encoder->new_crtc = NULL;
10417                 intel_crtc->new_enabled = false;
10418
10419                 connector_state->best_encoder = NULL;
10420                 connector_state->crtc = NULL;
10421
10422                 crtc_state->base.enable = crtc_state->base.active = false;
10423
10424                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10425                                                       0, 0);
10426                 if (ret)
10427                         goto fail;
10428
10429                 ret = intel_set_mode(state);
10430                 if (ret)
10431                         goto fail;
10432
10433                 if (old->release_fb) {
10434                         drm_framebuffer_unregister_private(old->release_fb);
10435                         drm_framebuffer_unreference(old->release_fb);
10436                 }
10437
10438                 return;
10439         }
10440
10441         /* Switch crtc and encoder back off if necessary */
10442         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10443                 connector->funcs->dpms(connector, old->dpms_mode);
10444
10445         return;
10446 fail:
10447         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10448         drm_atomic_state_free(state);
10449 }
10450
10451 static int i9xx_pll_refclk(struct drm_device *dev,
10452                            const struct intel_crtc_state *pipe_config)
10453 {
10454         struct drm_i915_private *dev_priv = dev->dev_private;
10455         u32 dpll = pipe_config->dpll_hw_state.dpll;
10456
10457         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10458                 return dev_priv->vbt.lvds_ssc_freq;
10459         else if (HAS_PCH_SPLIT(dev))
10460                 return 120000;
10461         else if (!IS_GEN2(dev))
10462                 return 96000;
10463         else
10464                 return 48000;
10465 }
10466
10467 /* Returns the clock of the currently programmed mode of the given pipe. */
10468 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10469                                 struct intel_crtc_state *pipe_config)
10470 {
10471         struct drm_device *dev = crtc->base.dev;
10472         struct drm_i915_private *dev_priv = dev->dev_private;
10473         int pipe = pipe_config->cpu_transcoder;
10474         u32 dpll = pipe_config->dpll_hw_state.dpll;
10475         u32 fp;
10476         intel_clock_t clock;
10477         int port_clock;
10478         int refclk = i9xx_pll_refclk(dev, pipe_config);
10479
10480         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10481                 fp = pipe_config->dpll_hw_state.fp0;
10482         else
10483                 fp = pipe_config->dpll_hw_state.fp1;
10484
10485         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10486         if (IS_PINEVIEW(dev)) {
10487                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10488                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10489         } else {
10490                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10491                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10492         }
10493
10494         if (!IS_GEN2(dev)) {
10495                 if (IS_PINEVIEW(dev))
10496                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10497                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10498                 else
10499                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10500                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10501
10502                 switch (dpll & DPLL_MODE_MASK) {
10503                 case DPLLB_MODE_DAC_SERIAL:
10504                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10505                                 5 : 10;
10506                         break;
10507                 case DPLLB_MODE_LVDS:
10508                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10509                                 7 : 14;
10510                         break;
10511                 default:
10512                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10513                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10514                         return;
10515                 }
10516
10517                 if (IS_PINEVIEW(dev))
10518                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10519                 else
10520                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10521         } else {
10522                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10523                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10524
10525                 if (is_lvds) {
10526                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10527                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10528
10529                         if (lvds & LVDS_CLKB_POWER_UP)
10530                                 clock.p2 = 7;
10531                         else
10532                                 clock.p2 = 14;
10533                 } else {
10534                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10535                                 clock.p1 = 2;
10536                         else {
10537                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10538                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10539                         }
10540                         if (dpll & PLL_P2_DIVIDE_BY_4)
10541                                 clock.p2 = 4;
10542                         else
10543                                 clock.p2 = 2;
10544                 }
10545
10546                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10547         }
10548
10549         /*
10550          * This value includes pixel_multiplier. We will use
10551          * port_clock to compute adjusted_mode.crtc_clock in the
10552          * encoder's get_config() function.
10553          */
10554         pipe_config->port_clock = port_clock;
10555 }
10556
10557 int intel_dotclock_calculate(int link_freq,
10558                              const struct intel_link_m_n *m_n)
10559 {
10560         /*
10561          * The calculation for the data clock is:
10562          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10563          * But we want to avoid losing precison if possible, so:
10564          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10565          *
10566          * and the link clock is simpler:
10567          * link_clock = (m * link_clock) / n
10568          */
10569
10570         if (!m_n->link_n)
10571                 return 0;
10572
10573         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10574 }
10575
10576 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10577                                    struct intel_crtc_state *pipe_config)
10578 {
10579         struct drm_device *dev = crtc->base.dev;
10580
10581         /* read out port_clock from the DPLL */
10582         i9xx_crtc_clock_get(crtc, pipe_config);
10583
10584         /*
10585          * This value does not include pixel_multiplier.
10586          * We will check that port_clock and adjusted_mode.crtc_clock
10587          * agree once we know their relationship in the encoder's
10588          * get_config() function.
10589          */
10590         pipe_config->base.adjusted_mode.crtc_clock =
10591                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10592                                          &pipe_config->fdi_m_n);
10593 }
10594
10595 /** Returns the currently programmed mode of the given pipe. */
10596 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10597                                              struct drm_crtc *crtc)
10598 {
10599         struct drm_i915_private *dev_priv = dev->dev_private;
10600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10601         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10602         struct drm_display_mode *mode;
10603         struct intel_crtc_state pipe_config;
10604         int htot = I915_READ(HTOTAL(cpu_transcoder));
10605         int hsync = I915_READ(HSYNC(cpu_transcoder));
10606         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10607         int vsync = I915_READ(VSYNC(cpu_transcoder));
10608         enum pipe pipe = intel_crtc->pipe;
10609
10610         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10611         if (!mode)
10612                 return NULL;
10613
10614         /*
10615          * Construct a pipe_config sufficient for getting the clock info
10616          * back out of crtc_clock_get.
10617          *
10618          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10619          * to use a real value here instead.
10620          */
10621         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10622         pipe_config.pixel_multiplier = 1;
10623         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10624         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10625         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10626         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10627
10628         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10629         mode->hdisplay = (htot & 0xffff) + 1;
10630         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10631         mode->hsync_start = (hsync & 0xffff) + 1;
10632         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10633         mode->vdisplay = (vtot & 0xffff) + 1;
10634         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10635         mode->vsync_start = (vsync & 0xffff) + 1;
10636         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10637
10638         drm_mode_set_name(mode);
10639
10640         return mode;
10641 }
10642
10643 void intel_mark_busy(struct drm_device *dev)
10644 {
10645         struct drm_i915_private *dev_priv = dev->dev_private;
10646
10647         if (dev_priv->mm.busy)
10648                 return;
10649
10650         intel_runtime_pm_get(dev_priv);
10651         i915_update_gfx_val(dev_priv);
10652         if (INTEL_INFO(dev)->gen >= 6)
10653                 gen6_rps_busy(dev_priv);
10654         dev_priv->mm.busy = true;
10655 }
10656
10657 void intel_mark_idle(struct drm_device *dev)
10658 {
10659         struct drm_i915_private *dev_priv = dev->dev_private;
10660
10661         if (!dev_priv->mm.busy)
10662                 return;
10663
10664         dev_priv->mm.busy = false;
10665
10666         if (INTEL_INFO(dev)->gen >= 6)
10667                 gen6_rps_idle(dev->dev_private);
10668
10669         intel_runtime_pm_put(dev_priv);
10670 }
10671
10672 static void intel_crtc_destroy(struct drm_crtc *crtc)
10673 {
10674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10675         struct drm_device *dev = crtc->dev;
10676         struct intel_unpin_work *work;
10677
10678         spin_lock_irq(&dev->event_lock);
10679         work = intel_crtc->unpin_work;
10680         intel_crtc->unpin_work = NULL;
10681         spin_unlock_irq(&dev->event_lock);
10682
10683         if (work) {
10684                 cancel_work_sync(&work->work);
10685                 kfree(work);
10686         }
10687
10688         drm_crtc_cleanup(crtc);
10689
10690         kfree(intel_crtc);
10691 }
10692
10693 static void intel_unpin_work_fn(struct work_struct *__work)
10694 {
10695         struct intel_unpin_work *work =
10696                 container_of(__work, struct intel_unpin_work, work);
10697         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10698         struct drm_device *dev = crtc->base.dev;
10699         struct drm_plane *primary = crtc->base.primary;
10700
10701         mutex_lock(&dev->struct_mutex);
10702         intel_unpin_fb_obj(work->old_fb, primary->state);
10703         drm_gem_object_unreference(&work->pending_flip_obj->base);
10704
10705         intel_fbc_update(dev);
10706
10707         if (work->flip_queued_req)
10708                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10709         mutex_unlock(&dev->struct_mutex);
10710
10711         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10712         drm_framebuffer_unreference(work->old_fb);
10713
10714         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10715         atomic_dec(&crtc->unpin_work_count);
10716
10717         kfree(work);
10718 }
10719
10720 static void do_intel_finish_page_flip(struct drm_device *dev,
10721                                       struct drm_crtc *crtc)
10722 {
10723         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10724         struct intel_unpin_work *work;
10725         unsigned long flags;
10726
10727         /* Ignore early vblank irqs */
10728         if (intel_crtc == NULL)
10729                 return;
10730
10731         /*
10732          * This is called both by irq handlers and the reset code (to complete
10733          * lost pageflips) so needs the full irqsave spinlocks.
10734          */
10735         spin_lock_irqsave(&dev->event_lock, flags);
10736         work = intel_crtc->unpin_work;
10737
10738         /* Ensure we don't miss a work->pending update ... */
10739         smp_rmb();
10740
10741         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10742                 spin_unlock_irqrestore(&dev->event_lock, flags);
10743                 return;
10744         }
10745
10746         page_flip_completed(intel_crtc);
10747
10748         spin_unlock_irqrestore(&dev->event_lock, flags);
10749 }
10750
10751 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10752 {
10753         struct drm_i915_private *dev_priv = dev->dev_private;
10754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10755
10756         do_intel_finish_page_flip(dev, crtc);
10757 }
10758
10759 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10760 {
10761         struct drm_i915_private *dev_priv = dev->dev_private;
10762         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10763
10764         do_intel_finish_page_flip(dev, crtc);
10765 }
10766
10767 /* Is 'a' after or equal to 'b'? */
10768 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10769 {
10770         return !((a - b) & 0x80000000);
10771 }
10772
10773 static bool page_flip_finished(struct intel_crtc *crtc)
10774 {
10775         struct drm_device *dev = crtc->base.dev;
10776         struct drm_i915_private *dev_priv = dev->dev_private;
10777
10778         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10779             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10780                 return true;
10781
10782         /*
10783          * The relevant registers doen't exist on pre-ctg.
10784          * As the flip done interrupt doesn't trigger for mmio
10785          * flips on gmch platforms, a flip count check isn't
10786          * really needed there. But since ctg has the registers,
10787          * include it in the check anyway.
10788          */
10789         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10790                 return true;
10791
10792         /*
10793          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10794          * used the same base address. In that case the mmio flip might
10795          * have completed, but the CS hasn't even executed the flip yet.
10796          *
10797          * A flip count check isn't enough as the CS might have updated
10798          * the base address just after start of vblank, but before we
10799          * managed to process the interrupt. This means we'd complete the
10800          * CS flip too soon.
10801          *
10802          * Combining both checks should get us a good enough result. It may
10803          * still happen that the CS flip has been executed, but has not
10804          * yet actually completed. But in case the base address is the same
10805          * anyway, we don't really care.
10806          */
10807         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10808                 crtc->unpin_work->gtt_offset &&
10809                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10810                                     crtc->unpin_work->flip_count);
10811 }
10812
10813 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10814 {
10815         struct drm_i915_private *dev_priv = dev->dev_private;
10816         struct intel_crtc *intel_crtc =
10817                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10818         unsigned long flags;
10819
10820
10821         /*
10822          * This is called both by irq handlers and the reset code (to complete
10823          * lost pageflips) so needs the full irqsave spinlocks.
10824          *
10825          * NB: An MMIO update of the plane base pointer will also
10826          * generate a page-flip completion irq, i.e. every modeset
10827          * is also accompanied by a spurious intel_prepare_page_flip().
10828          */
10829         spin_lock_irqsave(&dev->event_lock, flags);
10830         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10831                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10832         spin_unlock_irqrestore(&dev->event_lock, flags);
10833 }
10834
10835 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10836 {
10837         /* Ensure that the work item is consistent when activating it ... */
10838         smp_wmb();
10839         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10840         /* and that it is marked active as soon as the irq could fire. */
10841         smp_wmb();
10842 }
10843
10844 static int intel_gen2_queue_flip(struct drm_device *dev,
10845                                  struct drm_crtc *crtc,
10846                                  struct drm_framebuffer *fb,
10847                                  struct drm_i915_gem_object *obj,
10848                                  struct drm_i915_gem_request *req,
10849                                  uint32_t flags)
10850 {
10851         struct intel_engine_cs *ring = req->ring;
10852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10853         u32 flip_mask;
10854         int ret;
10855
10856         ret = intel_ring_begin(req, 6);
10857         if (ret)
10858                 return ret;
10859
10860         /* Can't queue multiple flips, so wait for the previous
10861          * one to finish before executing the next.
10862          */
10863         if (intel_crtc->plane)
10864                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10865         else
10866                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10867         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10868         intel_ring_emit(ring, MI_NOOP);
10869         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10870                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10871         intel_ring_emit(ring, fb->pitches[0]);
10872         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10873         intel_ring_emit(ring, 0); /* aux display base address, unused */
10874
10875         intel_mark_page_flip_active(intel_crtc);
10876         return 0;
10877 }
10878
10879 static int intel_gen3_queue_flip(struct drm_device *dev,
10880                                  struct drm_crtc *crtc,
10881                                  struct drm_framebuffer *fb,
10882                                  struct drm_i915_gem_object *obj,
10883                                  struct drm_i915_gem_request *req,
10884                                  uint32_t flags)
10885 {
10886         struct intel_engine_cs *ring = req->ring;
10887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10888         u32 flip_mask;
10889         int ret;
10890
10891         ret = intel_ring_begin(req, 6);
10892         if (ret)
10893                 return ret;
10894
10895         if (intel_crtc->plane)
10896                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10897         else
10898                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10899         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10900         intel_ring_emit(ring, MI_NOOP);
10901         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10902                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10903         intel_ring_emit(ring, fb->pitches[0]);
10904         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10905         intel_ring_emit(ring, MI_NOOP);
10906
10907         intel_mark_page_flip_active(intel_crtc);
10908         return 0;
10909 }
10910
10911 static int intel_gen4_queue_flip(struct drm_device *dev,
10912                                  struct drm_crtc *crtc,
10913                                  struct drm_framebuffer *fb,
10914                                  struct drm_i915_gem_object *obj,
10915                                  struct drm_i915_gem_request *req,
10916                                  uint32_t flags)
10917 {
10918         struct intel_engine_cs *ring = req->ring;
10919         struct drm_i915_private *dev_priv = dev->dev_private;
10920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10921         uint32_t pf, pipesrc;
10922         int ret;
10923
10924         ret = intel_ring_begin(req, 4);
10925         if (ret)
10926                 return ret;
10927
10928         /* i965+ uses the linear or tiled offsets from the
10929          * Display Registers (which do not change across a page-flip)
10930          * so we need only reprogram the base address.
10931          */
10932         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10933                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10934         intel_ring_emit(ring, fb->pitches[0]);
10935         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10936                         obj->tiling_mode);
10937
10938         /* XXX Enabling the panel-fitter across page-flip is so far
10939          * untested on non-native modes, so ignore it for now.
10940          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10941          */
10942         pf = 0;
10943         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10944         intel_ring_emit(ring, pf | pipesrc);
10945
10946         intel_mark_page_flip_active(intel_crtc);
10947         return 0;
10948 }
10949
10950 static int intel_gen6_queue_flip(struct drm_device *dev,
10951                                  struct drm_crtc *crtc,
10952                                  struct drm_framebuffer *fb,
10953                                  struct drm_i915_gem_object *obj,
10954                                  struct drm_i915_gem_request *req,
10955                                  uint32_t flags)
10956 {
10957         struct intel_engine_cs *ring = req->ring;
10958         struct drm_i915_private *dev_priv = dev->dev_private;
10959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10960         uint32_t pf, pipesrc;
10961         int ret;
10962
10963         ret = intel_ring_begin(req, 4);
10964         if (ret)
10965                 return ret;
10966
10967         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10968                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10969         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10970         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10971
10972         /* Contrary to the suggestions in the documentation,
10973          * "Enable Panel Fitter" does not seem to be required when page
10974          * flipping with a non-native mode, and worse causes a normal
10975          * modeset to fail.
10976          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10977          */
10978         pf = 0;
10979         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10980         intel_ring_emit(ring, pf | pipesrc);
10981
10982         intel_mark_page_flip_active(intel_crtc);
10983         return 0;
10984 }
10985
10986 static int intel_gen7_queue_flip(struct drm_device *dev,
10987                                  struct drm_crtc *crtc,
10988                                  struct drm_framebuffer *fb,
10989                                  struct drm_i915_gem_object *obj,
10990                                  struct drm_i915_gem_request *req,
10991                                  uint32_t flags)
10992 {
10993         struct intel_engine_cs *ring = req->ring;
10994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10995         uint32_t plane_bit = 0;
10996         int len, ret;
10997
10998         switch (intel_crtc->plane) {
10999         case PLANE_A:
11000                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11001                 break;
11002         case PLANE_B:
11003                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11004                 break;
11005         case PLANE_C:
11006                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11007                 break;
11008         default:
11009                 WARN_ONCE(1, "unknown plane in flip command\n");
11010                 return -ENODEV;
11011         }
11012
11013         len = 4;
11014         if (ring->id == RCS) {
11015                 len += 6;
11016                 /*
11017                  * On Gen 8, SRM is now taking an extra dword to accommodate
11018                  * 48bits addresses, and we need a NOOP for the batch size to
11019                  * stay even.
11020                  */
11021                 if (IS_GEN8(dev))
11022                         len += 2;
11023         }
11024
11025         /*
11026          * BSpec MI_DISPLAY_FLIP for IVB:
11027          * "The full packet must be contained within the same cache line."
11028          *
11029          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11030          * cacheline, if we ever start emitting more commands before
11031          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11032          * then do the cacheline alignment, and finally emit the
11033          * MI_DISPLAY_FLIP.
11034          */
11035         ret = intel_ring_cacheline_align(req);
11036         if (ret)
11037                 return ret;
11038
11039         ret = intel_ring_begin(req, len);
11040         if (ret)
11041                 return ret;
11042
11043         /* Unmask the flip-done completion message. Note that the bspec says that
11044          * we should do this for both the BCS and RCS, and that we must not unmask
11045          * more than one flip event at any time (or ensure that one flip message
11046          * can be sent by waiting for flip-done prior to queueing new flips).
11047          * Experimentation says that BCS works despite DERRMR masking all
11048          * flip-done completion events and that unmasking all planes at once
11049          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11050          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11051          */
11052         if (ring->id == RCS) {
11053                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11054                 intel_ring_emit(ring, DERRMR);
11055                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11056                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11057                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11058                 if (IS_GEN8(dev))
11059                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11060                                               MI_SRM_LRM_GLOBAL_GTT);
11061                 else
11062                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11063                                               MI_SRM_LRM_GLOBAL_GTT);
11064                 intel_ring_emit(ring, DERRMR);
11065                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11066                 if (IS_GEN8(dev)) {
11067                         intel_ring_emit(ring, 0);
11068                         intel_ring_emit(ring, MI_NOOP);
11069                 }
11070         }
11071
11072         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11073         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11074         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11075         intel_ring_emit(ring, (MI_NOOP));
11076
11077         intel_mark_page_flip_active(intel_crtc);
11078         return 0;
11079 }
11080
11081 static bool use_mmio_flip(struct intel_engine_cs *ring,
11082                           struct drm_i915_gem_object *obj)
11083 {
11084         /*
11085          * This is not being used for older platforms, because
11086          * non-availability of flip done interrupt forces us to use
11087          * CS flips. Older platforms derive flip done using some clever
11088          * tricks involving the flip_pending status bits and vblank irqs.
11089          * So using MMIO flips there would disrupt this mechanism.
11090          */
11091
11092         if (ring == NULL)
11093                 return true;
11094
11095         if (INTEL_INFO(ring->dev)->gen < 5)
11096                 return false;
11097
11098         if (i915.use_mmio_flip < 0)
11099                 return false;
11100         else if (i915.use_mmio_flip > 0)
11101                 return true;
11102         else if (i915.enable_execlists)
11103                 return true;
11104         else
11105                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11106 }
11107
11108 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11109 {
11110         struct drm_device *dev = intel_crtc->base.dev;
11111         struct drm_i915_private *dev_priv = dev->dev_private;
11112         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11113         const enum pipe pipe = intel_crtc->pipe;
11114         u32 ctl, stride;
11115
11116         ctl = I915_READ(PLANE_CTL(pipe, 0));
11117         ctl &= ~PLANE_CTL_TILED_MASK;
11118         switch (fb->modifier[0]) {
11119         case DRM_FORMAT_MOD_NONE:
11120                 break;
11121         case I915_FORMAT_MOD_X_TILED:
11122                 ctl |= PLANE_CTL_TILED_X;
11123                 break;
11124         case I915_FORMAT_MOD_Y_TILED:
11125                 ctl |= PLANE_CTL_TILED_Y;
11126                 break;
11127         case I915_FORMAT_MOD_Yf_TILED:
11128                 ctl |= PLANE_CTL_TILED_YF;
11129                 break;
11130         default:
11131                 MISSING_CASE(fb->modifier[0]);
11132         }
11133
11134         /*
11135          * The stride is either expressed as a multiple of 64 bytes chunks for
11136          * linear buffers or in number of tiles for tiled buffers.
11137          */
11138         stride = fb->pitches[0] /
11139                  intel_fb_stride_alignment(dev, fb->modifier[0],
11140                                            fb->pixel_format);
11141
11142         /*
11143          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11144          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11145          */
11146         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11147         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11148
11149         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11150         POSTING_READ(PLANE_SURF(pipe, 0));
11151 }
11152
11153 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11154 {
11155         struct drm_device *dev = intel_crtc->base.dev;
11156         struct drm_i915_private *dev_priv = dev->dev_private;
11157         struct intel_framebuffer *intel_fb =
11158                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11159         struct drm_i915_gem_object *obj = intel_fb->obj;
11160         u32 dspcntr;
11161         u32 reg;
11162
11163         reg = DSPCNTR(intel_crtc->plane);
11164         dspcntr = I915_READ(reg);
11165
11166         if (obj->tiling_mode != I915_TILING_NONE)
11167                 dspcntr |= DISPPLANE_TILED;
11168         else
11169                 dspcntr &= ~DISPPLANE_TILED;
11170
11171         I915_WRITE(reg, dspcntr);
11172
11173         I915_WRITE(DSPSURF(intel_crtc->plane),
11174                    intel_crtc->unpin_work->gtt_offset);
11175         POSTING_READ(DSPSURF(intel_crtc->plane));
11176
11177 }
11178
11179 /*
11180  * XXX: This is the temporary way to update the plane registers until we get
11181  * around to using the usual plane update functions for MMIO flips
11182  */
11183 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11184 {
11185         struct drm_device *dev = intel_crtc->base.dev;
11186         bool atomic_update;
11187         u32 start_vbl_count;
11188
11189         intel_mark_page_flip_active(intel_crtc);
11190
11191         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11192
11193         if (INTEL_INFO(dev)->gen >= 9)
11194                 skl_do_mmio_flip(intel_crtc);
11195         else
11196                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11197                 ilk_do_mmio_flip(intel_crtc);
11198
11199         if (atomic_update)
11200                 intel_pipe_update_end(intel_crtc, start_vbl_count);
11201 }
11202
11203 static void intel_mmio_flip_work_func(struct work_struct *work)
11204 {
11205         struct intel_mmio_flip *mmio_flip =
11206                 container_of(work, struct intel_mmio_flip, work);
11207
11208         if (mmio_flip->req)
11209                 WARN_ON(__i915_wait_request(mmio_flip->req,
11210                                             mmio_flip->crtc->reset_counter,
11211                                             false, NULL,
11212                                             &mmio_flip->i915->rps.mmioflips));
11213
11214         intel_do_mmio_flip(mmio_flip->crtc);
11215
11216         i915_gem_request_unreference__unlocked(mmio_flip->req);
11217         kfree(mmio_flip);
11218 }
11219
11220 static int intel_queue_mmio_flip(struct drm_device *dev,
11221                                  struct drm_crtc *crtc,
11222                                  struct drm_framebuffer *fb,
11223                                  struct drm_i915_gem_object *obj,
11224                                  struct intel_engine_cs *ring,
11225                                  uint32_t flags)
11226 {
11227         struct intel_mmio_flip *mmio_flip;
11228
11229         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11230         if (mmio_flip == NULL)
11231                 return -ENOMEM;
11232
11233         mmio_flip->i915 = to_i915(dev);
11234         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11235         mmio_flip->crtc = to_intel_crtc(crtc);
11236
11237         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11238         schedule_work(&mmio_flip->work);
11239
11240         return 0;
11241 }
11242
11243 static int intel_default_queue_flip(struct drm_device *dev,
11244                                     struct drm_crtc *crtc,
11245                                     struct drm_framebuffer *fb,
11246                                     struct drm_i915_gem_object *obj,
11247                                     struct drm_i915_gem_request *req,
11248                                     uint32_t flags)
11249 {
11250         return -ENODEV;
11251 }
11252
11253 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11254                                          struct drm_crtc *crtc)
11255 {
11256         struct drm_i915_private *dev_priv = dev->dev_private;
11257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11258         struct intel_unpin_work *work = intel_crtc->unpin_work;
11259         u32 addr;
11260
11261         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11262                 return true;
11263
11264         if (!work->enable_stall_check)
11265                 return false;
11266
11267         if (work->flip_ready_vblank == 0) {
11268                 if (work->flip_queued_req &&
11269                     !i915_gem_request_completed(work->flip_queued_req, true))
11270                         return false;
11271
11272                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11273         }
11274
11275         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11276                 return false;
11277
11278         /* Potential stall - if we see that the flip has happened,
11279          * assume a missed interrupt. */
11280         if (INTEL_INFO(dev)->gen >= 4)
11281                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11282         else
11283                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11284
11285         /* There is a potential issue here with a false positive after a flip
11286          * to the same address. We could address this by checking for a
11287          * non-incrementing frame counter.
11288          */
11289         return addr == work->gtt_offset;
11290 }
11291
11292 void intel_check_page_flip(struct drm_device *dev, int pipe)
11293 {
11294         struct drm_i915_private *dev_priv = dev->dev_private;
11295         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11296         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11297         struct intel_unpin_work *work;
11298
11299         WARN_ON(!in_interrupt());
11300
11301         if (crtc == NULL)
11302                 return;
11303
11304         spin_lock(&dev->event_lock);
11305         work = intel_crtc->unpin_work;
11306         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11307                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11308                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11309                 page_flip_completed(intel_crtc);
11310                 work = NULL;
11311         }
11312         if (work != NULL &&
11313             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11314                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11315         spin_unlock(&dev->event_lock);
11316 }
11317
11318 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11319                                 struct drm_framebuffer *fb,
11320                                 struct drm_pending_vblank_event *event,
11321                                 uint32_t page_flip_flags)
11322 {
11323         struct drm_device *dev = crtc->dev;
11324         struct drm_i915_private *dev_priv = dev->dev_private;
11325         struct drm_framebuffer *old_fb = crtc->primary->fb;
11326         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11327         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11328         struct drm_plane *primary = crtc->primary;
11329         enum pipe pipe = intel_crtc->pipe;
11330         struct intel_unpin_work *work;
11331         struct intel_engine_cs *ring;
11332         bool mmio_flip;
11333         struct drm_i915_gem_request *request = NULL;
11334         int ret;
11335
11336         /*
11337          * drm_mode_page_flip_ioctl() should already catch this, but double
11338          * check to be safe.  In the future we may enable pageflipping from
11339          * a disabled primary plane.
11340          */
11341         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11342                 return -EBUSY;
11343
11344         /* Can't change pixel format via MI display flips. */
11345         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11346                 return -EINVAL;
11347
11348         /*
11349          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11350          * Note that pitch changes could also affect these register.
11351          */
11352         if (INTEL_INFO(dev)->gen > 3 &&
11353             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11354              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11355                 return -EINVAL;
11356
11357         if (i915_terminally_wedged(&dev_priv->gpu_error))
11358                 goto out_hang;
11359
11360         work = kzalloc(sizeof(*work), GFP_KERNEL);
11361         if (work == NULL)
11362                 return -ENOMEM;
11363
11364         work->event = event;
11365         work->crtc = crtc;
11366         work->old_fb = old_fb;
11367         INIT_WORK(&work->work, intel_unpin_work_fn);
11368
11369         ret = drm_crtc_vblank_get(crtc);
11370         if (ret)
11371                 goto free_work;
11372
11373         /* We borrow the event spin lock for protecting unpin_work */
11374         spin_lock_irq(&dev->event_lock);
11375         if (intel_crtc->unpin_work) {
11376                 /* Before declaring the flip queue wedged, check if
11377                  * the hardware completed the operation behind our backs.
11378                  */
11379                 if (__intel_pageflip_stall_check(dev, crtc)) {
11380                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11381                         page_flip_completed(intel_crtc);
11382                 } else {
11383                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11384                         spin_unlock_irq(&dev->event_lock);
11385
11386                         drm_crtc_vblank_put(crtc);
11387                         kfree(work);
11388                         return -EBUSY;
11389                 }
11390         }
11391         intel_crtc->unpin_work = work;
11392         spin_unlock_irq(&dev->event_lock);
11393
11394         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11395                 flush_workqueue(dev_priv->wq);
11396
11397         /* Reference the objects for the scheduled work. */
11398         drm_framebuffer_reference(work->old_fb);
11399         drm_gem_object_reference(&obj->base);
11400
11401         crtc->primary->fb = fb;
11402         update_state_fb(crtc->primary);
11403
11404         work->pending_flip_obj = obj;
11405
11406         ret = i915_mutex_lock_interruptible(dev);
11407         if (ret)
11408                 goto cleanup;
11409
11410         atomic_inc(&intel_crtc->unpin_work_count);
11411         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11412
11413         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11414                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11415
11416         if (IS_VALLEYVIEW(dev)) {
11417                 ring = &dev_priv->ring[BCS];
11418                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11419                         /* vlv: DISPLAY_FLIP fails to change tiling */
11420                         ring = NULL;
11421         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11422                 ring = &dev_priv->ring[BCS];
11423         } else if (INTEL_INFO(dev)->gen >= 7) {
11424                 ring = i915_gem_request_get_ring(obj->last_write_req);
11425                 if (ring == NULL || ring->id != RCS)
11426                         ring = &dev_priv->ring[BCS];
11427         } else {
11428                 ring = &dev_priv->ring[RCS];
11429         }
11430
11431         mmio_flip = use_mmio_flip(ring, obj);
11432
11433         /* When using CS flips, we want to emit semaphores between rings.
11434          * However, when using mmio flips we will create a task to do the
11435          * synchronisation, so all we want here is to pin the framebuffer
11436          * into the display plane and skip any waits.
11437          */
11438         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11439                                          crtc->primary->state,
11440                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11441         if (ret)
11442                 goto cleanup_pending;
11443
11444         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11445                                                   + intel_crtc->dspaddr_offset;
11446
11447         if (mmio_flip) {
11448                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11449                                             page_flip_flags);
11450                 if (ret)
11451                         goto cleanup_unpin;
11452
11453                 i915_gem_request_assign(&work->flip_queued_req,
11454                                         obj->last_write_req);
11455         } else {
11456                 if (!request) {
11457                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11458                         if (ret)
11459                                 goto cleanup_unpin;
11460                 }
11461
11462                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11463                                                    page_flip_flags);
11464                 if (ret)
11465                         goto cleanup_unpin;
11466
11467                 i915_gem_request_assign(&work->flip_queued_req, request);
11468         }
11469
11470         if (request)
11471                 i915_add_request_no_flush(request);
11472
11473         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11474         work->enable_stall_check = true;
11475
11476         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11477                           to_intel_plane(primary)->frontbuffer_bit);
11478
11479         intel_fbc_disable(dev);
11480         intel_frontbuffer_flip_prepare(dev,
11481                                        to_intel_plane(primary)->frontbuffer_bit);
11482         mutex_unlock(&dev->struct_mutex);
11483
11484         trace_i915_flip_request(intel_crtc->plane, obj);
11485
11486         return 0;
11487
11488 cleanup_unpin:
11489         intel_unpin_fb_obj(fb, crtc->primary->state);
11490 cleanup_pending:
11491         if (request)
11492                 i915_gem_request_cancel(request);
11493         atomic_dec(&intel_crtc->unpin_work_count);
11494         mutex_unlock(&dev->struct_mutex);
11495 cleanup:
11496         crtc->primary->fb = old_fb;
11497         update_state_fb(crtc->primary);
11498
11499         drm_gem_object_unreference_unlocked(&obj->base);
11500         drm_framebuffer_unreference(work->old_fb);
11501
11502         spin_lock_irq(&dev->event_lock);
11503         intel_crtc->unpin_work = NULL;
11504         spin_unlock_irq(&dev->event_lock);
11505
11506         drm_crtc_vblank_put(crtc);
11507 free_work:
11508         kfree(work);
11509
11510         if (ret == -EIO) {
11511                 struct drm_atomic_state *state;
11512                 struct drm_plane_state *plane_state;
11513
11514 out_hang:
11515                 state = drm_atomic_state_alloc(dev);
11516                 if (!state)
11517                         return -ENOMEM;
11518                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11519
11520 retry:
11521                 plane_state = drm_atomic_get_plane_state(state, primary);
11522                 ret = PTR_ERR_OR_ZERO(plane_state);
11523                 if (!ret) {
11524                         drm_atomic_set_fb_for_plane(plane_state, fb);
11525
11526                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11527                         if (!ret)
11528                                 ret = drm_atomic_commit(state);
11529                 }
11530
11531                 if (ret == -EDEADLK) {
11532                         drm_modeset_backoff(state->acquire_ctx);
11533                         drm_atomic_state_clear(state);
11534                         goto retry;
11535                 }
11536
11537                 if (ret)
11538                         drm_atomic_state_free(state);
11539
11540                 if (ret == 0 && event) {
11541                         spin_lock_irq(&dev->event_lock);
11542                         drm_send_vblank_event(dev, pipe, event);
11543                         spin_unlock_irq(&dev->event_lock);
11544                 }
11545         }
11546         return ret;
11547 }
11548
11549
11550 /**
11551  * intel_wm_need_update - Check whether watermarks need updating
11552  * @plane: drm plane
11553  * @state: new plane state
11554  *
11555  * Check current plane state versus the new one to determine whether
11556  * watermarks need to be recalculated.
11557  *
11558  * Returns true or false.
11559  */
11560 static bool intel_wm_need_update(struct drm_plane *plane,
11561                                  struct drm_plane_state *state)
11562 {
11563         /* Update watermarks on tiling changes. */
11564         if (!plane->state->fb || !state->fb ||
11565             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11566             plane->state->rotation != state->rotation)
11567                 return true;
11568
11569         if (plane->state->crtc_w != state->crtc_w)
11570                 return true;
11571
11572         return false;
11573 }
11574
11575 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11576                                     struct drm_plane_state *plane_state)
11577 {
11578         struct drm_crtc *crtc = crtc_state->crtc;
11579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11580         struct drm_plane *plane = plane_state->plane;
11581         struct drm_device *dev = crtc->dev;
11582         struct drm_i915_private *dev_priv = dev->dev_private;
11583         struct intel_plane_state *old_plane_state =
11584                 to_intel_plane_state(plane->state);
11585         int idx = intel_crtc->base.base.id, ret;
11586         int i = drm_plane_index(plane);
11587         bool mode_changed = needs_modeset(crtc_state);
11588         bool was_crtc_enabled = crtc->state->active;
11589         bool is_crtc_enabled = crtc_state->active;
11590
11591         bool turn_off, turn_on, visible, was_visible;
11592         struct drm_framebuffer *fb = plane_state->fb;
11593
11594         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11595             plane->type != DRM_PLANE_TYPE_CURSOR) {
11596                 ret = skl_update_scaler_plane(
11597                         to_intel_crtc_state(crtc_state),
11598                         to_intel_plane_state(plane_state));
11599                 if (ret)
11600                         return ret;
11601         }
11602
11603         /*
11604          * Disabling a plane is always okay; we just need to update
11605          * fb tracking in a special way since cleanup_fb() won't
11606          * get called by the plane helpers.
11607          */
11608         if (old_plane_state->base.fb && !fb)
11609                 intel_crtc->atomic.disabled_planes |= 1 << i;
11610
11611         was_visible = old_plane_state->visible;
11612         visible = to_intel_plane_state(plane_state)->visible;
11613
11614         if (!was_crtc_enabled && WARN_ON(was_visible))
11615                 was_visible = false;
11616
11617         if (!is_crtc_enabled && WARN_ON(visible))
11618                 visible = false;
11619
11620         if (!was_visible && !visible)
11621                 return 0;
11622
11623         turn_off = was_visible && (!visible || mode_changed);
11624         turn_on = visible && (!was_visible || mode_changed);
11625
11626         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11627                          plane->base.id, fb ? fb->base.id : -1);
11628
11629         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11630                          plane->base.id, was_visible, visible,
11631                          turn_off, turn_on, mode_changed);
11632
11633         if (turn_on) {
11634                 intel_crtc->atomic.update_wm_pre = true;
11635                 /* must disable cxsr around plane enable/disable */
11636                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11637                         intel_crtc->atomic.disable_cxsr = true;
11638                         /* to potentially re-enable cxsr */
11639                         intel_crtc->atomic.wait_vblank = true;
11640                         intel_crtc->atomic.update_wm_post = true;
11641                 }
11642         } else if (turn_off) {
11643                 intel_crtc->atomic.update_wm_post = true;
11644                 /* must disable cxsr around plane enable/disable */
11645                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11646                         if (is_crtc_enabled)
11647                                 intel_crtc->atomic.wait_vblank = true;
11648                         intel_crtc->atomic.disable_cxsr = true;
11649                 }
11650         } else if (intel_wm_need_update(plane, plane_state)) {
11651                 intel_crtc->atomic.update_wm_pre = true;
11652         }
11653
11654         if (visible)
11655                 intel_crtc->atomic.fb_bits |=
11656                         to_intel_plane(plane)->frontbuffer_bit;
11657
11658         switch (plane->type) {
11659         case DRM_PLANE_TYPE_PRIMARY:
11660                 intel_crtc->atomic.wait_for_flips = true;
11661                 intel_crtc->atomic.pre_disable_primary = turn_off;
11662                 intel_crtc->atomic.post_enable_primary = turn_on;
11663
11664                 if (turn_off) {
11665                         /*
11666                          * FIXME: Actually if we will still have any other
11667                          * plane enabled on the pipe we could let IPS enabled
11668                          * still, but for now lets consider that when we make
11669                          * primary invisible by setting DSPCNTR to 0 on
11670                          * update_primary_plane function IPS needs to be
11671                          * disable.
11672                          */
11673                         intel_crtc->atomic.disable_ips = true;
11674
11675                         intel_crtc->atomic.disable_fbc = true;
11676                 }
11677
11678                 /*
11679                  * FBC does not work on some platforms for rotated
11680                  * planes, so disable it when rotation is not 0 and
11681                  * update it when rotation is set back to 0.
11682                  *
11683                  * FIXME: This is redundant with the fbc update done in
11684                  * the primary plane enable function except that that
11685                  * one is done too late. We eventually need to unify
11686                  * this.
11687                  */
11688
11689                 if (visible &&
11690                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11691                     dev_priv->fbc.crtc == intel_crtc &&
11692                     plane_state->rotation != BIT(DRM_ROTATE_0))
11693                         intel_crtc->atomic.disable_fbc = true;
11694
11695                 /*
11696                  * BDW signals flip done immediately if the plane
11697                  * is disabled, even if the plane enable is already
11698                  * armed to occur at the next vblank :(
11699                  */
11700                 if (turn_on && IS_BROADWELL(dev))
11701                         intel_crtc->atomic.wait_vblank = true;
11702
11703                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11704                 break;
11705         case DRM_PLANE_TYPE_CURSOR:
11706                 break;
11707         case DRM_PLANE_TYPE_OVERLAY:
11708                 if (turn_off && !mode_changed) {
11709                         intel_crtc->atomic.wait_vblank = true;
11710                         intel_crtc->atomic.update_sprite_watermarks |=
11711                                 1 << i;
11712                 }
11713         }
11714         return 0;
11715 }
11716
11717 static bool encoders_cloneable(const struct intel_encoder *a,
11718                                const struct intel_encoder *b)
11719 {
11720         /* masks could be asymmetric, so check both ways */
11721         return a == b || (a->cloneable & (1 << b->type) &&
11722                           b->cloneable & (1 << a->type));
11723 }
11724
11725 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11726                                          struct intel_crtc *crtc,
11727                                          struct intel_encoder *encoder)
11728 {
11729         struct intel_encoder *source_encoder;
11730         struct drm_connector *connector;
11731         struct drm_connector_state *connector_state;
11732         int i;
11733
11734         for_each_connector_in_state(state, connector, connector_state, i) {
11735                 if (connector_state->crtc != &crtc->base)
11736                         continue;
11737
11738                 source_encoder =
11739                         to_intel_encoder(connector_state->best_encoder);
11740                 if (!encoders_cloneable(encoder, source_encoder))
11741                         return false;
11742         }
11743
11744         return true;
11745 }
11746
11747 static bool check_encoder_cloning(struct drm_atomic_state *state,
11748                                   struct intel_crtc *crtc)
11749 {
11750         struct intel_encoder *encoder;
11751         struct drm_connector *connector;
11752         struct drm_connector_state *connector_state;
11753         int i;
11754
11755         for_each_connector_in_state(state, connector, connector_state, i) {
11756                 if (connector_state->crtc != &crtc->base)
11757                         continue;
11758
11759                 encoder = to_intel_encoder(connector_state->best_encoder);
11760                 if (!check_single_encoder_cloning(state, crtc, encoder))
11761                         return false;
11762         }
11763
11764         return true;
11765 }
11766
11767 static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11768                                             struct drm_crtc_state *crtc_state)
11769 {
11770         struct intel_crtc_state *pipe_config =
11771                 to_intel_crtc_state(crtc_state);
11772         struct drm_plane *p;
11773         unsigned visible_mask = 0;
11774
11775         drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11776                 struct drm_plane_state *plane_state =
11777                         drm_atomic_get_existing_plane_state(crtc_state->state, p);
11778
11779                 if (WARN_ON(!plane_state))
11780                         continue;
11781
11782                 if (!plane_state->fb)
11783                         crtc_state->plane_mask &=
11784                                 ~(1 << drm_plane_index(p));
11785                 else if (to_intel_plane_state(plane_state)->visible)
11786                         visible_mask |= 1 << drm_plane_index(p);
11787         }
11788
11789         if (!visible_mask)
11790                 return;
11791
11792         pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11793 }
11794
11795 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11796                                    struct drm_crtc_state *crtc_state)
11797 {
11798         struct drm_device *dev = crtc->dev;
11799         struct drm_i915_private *dev_priv = dev->dev_private;
11800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11801         struct intel_crtc_state *pipe_config =
11802                 to_intel_crtc_state(crtc_state);
11803         struct drm_atomic_state *state = crtc_state->state;
11804         int ret, idx = crtc->base.id;
11805         bool mode_changed = needs_modeset(crtc_state);
11806
11807         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11808                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11809                 return -EINVAL;
11810         }
11811
11812         I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11813                 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11814                 idx, crtc->state->active, intel_crtc->active);
11815
11816         /* plane mask is fixed up after all initial planes are calculated */
11817         if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11818                 intel_crtc_check_initial_planes(crtc, crtc_state);
11819
11820         if (mode_changed && !crtc_state->active)
11821                 intel_crtc->atomic.update_wm_post = true;
11822
11823         if (mode_changed && crtc_state->enable &&
11824             dev_priv->display.crtc_compute_clock &&
11825             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11826                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11827                                                            pipe_config);
11828                 if (ret)
11829                         return ret;
11830         }
11831
11832         return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
11833 }
11834
11835 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11836         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11837         .load_lut = intel_crtc_load_lut,
11838         .atomic_begin = intel_begin_crtc_commit,
11839         .atomic_flush = intel_finish_crtc_commit,
11840         .atomic_check = intel_crtc_atomic_check,
11841 };
11842
11843 /**
11844  * intel_modeset_update_staged_output_state
11845  *
11846  * Updates the staged output configuration state, e.g. after we've read out the
11847  * current hw state.
11848  */
11849 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11850 {
11851         struct intel_crtc *crtc;
11852         struct intel_encoder *encoder;
11853         struct intel_connector *connector;
11854
11855         for_each_intel_connector(dev, connector) {
11856                 connector->new_encoder =
11857                         to_intel_encoder(connector->base.encoder);
11858         }
11859
11860         for_each_intel_encoder(dev, encoder) {
11861                 encoder->new_crtc =
11862                         to_intel_crtc(encoder->base.crtc);
11863         }
11864
11865         for_each_intel_crtc(dev, crtc) {
11866                 crtc->new_enabled = crtc->base.state->enable;
11867         }
11868 }
11869
11870 /* Transitional helper to copy current connector/encoder state to
11871  * connector->state. This is needed so that code that is partially
11872  * converted to atomic does the right thing.
11873  */
11874 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11875 {
11876         struct intel_connector *connector;
11877
11878         for_each_intel_connector(dev, connector) {
11879                 if (connector->base.encoder) {
11880                         connector->base.state->best_encoder =
11881                                 connector->base.encoder;
11882                         connector->base.state->crtc =
11883                                 connector->base.encoder->crtc;
11884                 } else {
11885                         connector->base.state->best_encoder = NULL;
11886                         connector->base.state->crtc = NULL;
11887                 }
11888         }
11889 }
11890
11891 static void
11892 connected_sink_compute_bpp(struct intel_connector *connector,
11893                            struct intel_crtc_state *pipe_config)
11894 {
11895         int bpp = pipe_config->pipe_bpp;
11896
11897         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11898                 connector->base.base.id,
11899                 connector->base.name);
11900
11901         /* Don't use an invalid EDID bpc value */
11902         if (connector->base.display_info.bpc &&
11903             connector->base.display_info.bpc * 3 < bpp) {
11904                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11905                               bpp, connector->base.display_info.bpc*3);
11906                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11907         }
11908
11909         /* Clamp bpp to 8 on screens without EDID 1.4 */
11910         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11911                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11912                               bpp);
11913                 pipe_config->pipe_bpp = 24;
11914         }
11915 }
11916
11917 static int
11918 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11919                           struct intel_crtc_state *pipe_config)
11920 {
11921         struct drm_device *dev = crtc->base.dev;
11922         struct drm_atomic_state *state;
11923         struct drm_connector *connector;
11924         struct drm_connector_state *connector_state;
11925         int bpp, i;
11926
11927         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11928                 bpp = 10*3;
11929         else if (INTEL_INFO(dev)->gen >= 5)
11930                 bpp = 12*3;
11931         else
11932                 bpp = 8*3;
11933
11934
11935         pipe_config->pipe_bpp = bpp;
11936
11937         state = pipe_config->base.state;
11938
11939         /* Clamp display bpp to EDID value */
11940         for_each_connector_in_state(state, connector, connector_state, i) {
11941                 if (connector_state->crtc != &crtc->base)
11942                         continue;
11943
11944                 connected_sink_compute_bpp(to_intel_connector(connector),
11945                                            pipe_config);
11946         }
11947
11948         return bpp;
11949 }
11950
11951 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11952 {
11953         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11954                         "type: 0x%x flags: 0x%x\n",
11955                 mode->crtc_clock,
11956                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11957                 mode->crtc_hsync_end, mode->crtc_htotal,
11958                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11959                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11960 }
11961
11962 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11963                                    struct intel_crtc_state *pipe_config,
11964                                    const char *context)
11965 {
11966         struct drm_device *dev = crtc->base.dev;
11967         struct drm_plane *plane;
11968         struct intel_plane *intel_plane;
11969         struct intel_plane_state *state;
11970         struct drm_framebuffer *fb;
11971
11972         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11973                       context, pipe_config, pipe_name(crtc->pipe));
11974
11975         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11976         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11977                       pipe_config->pipe_bpp, pipe_config->dither);
11978         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11979                       pipe_config->has_pch_encoder,
11980                       pipe_config->fdi_lanes,
11981                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11982                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11983                       pipe_config->fdi_m_n.tu);
11984         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11985                       pipe_config->has_dp_encoder,
11986                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11987                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11988                       pipe_config->dp_m_n.tu);
11989
11990         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11991                       pipe_config->has_dp_encoder,
11992                       pipe_config->dp_m2_n2.gmch_m,
11993                       pipe_config->dp_m2_n2.gmch_n,
11994                       pipe_config->dp_m2_n2.link_m,
11995                       pipe_config->dp_m2_n2.link_n,
11996                       pipe_config->dp_m2_n2.tu);
11997
11998         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11999                       pipe_config->has_audio,
12000                       pipe_config->has_infoframe);
12001
12002         DRM_DEBUG_KMS("requested mode:\n");
12003         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12004         DRM_DEBUG_KMS("adjusted mode:\n");
12005         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12006         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12007         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12008         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12009                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12010         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12011                       crtc->num_scalers,
12012                       pipe_config->scaler_state.scaler_users,
12013                       pipe_config->scaler_state.scaler_id);
12014         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12015                       pipe_config->gmch_pfit.control,
12016                       pipe_config->gmch_pfit.pgm_ratios,
12017                       pipe_config->gmch_pfit.lvds_border_bits);
12018         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12019                       pipe_config->pch_pfit.pos,
12020                       pipe_config->pch_pfit.size,
12021                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12022         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12023         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12024
12025         if (IS_BROXTON(dev)) {
12026                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12027                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12028                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12029                               pipe_config->ddi_pll_sel,
12030                               pipe_config->dpll_hw_state.ebb0,
12031                               pipe_config->dpll_hw_state.ebb4,
12032                               pipe_config->dpll_hw_state.pll0,
12033                               pipe_config->dpll_hw_state.pll1,
12034                               pipe_config->dpll_hw_state.pll2,
12035                               pipe_config->dpll_hw_state.pll3,
12036                               pipe_config->dpll_hw_state.pll6,
12037                               pipe_config->dpll_hw_state.pll8,
12038                               pipe_config->dpll_hw_state.pll9,
12039                               pipe_config->dpll_hw_state.pll10,
12040                               pipe_config->dpll_hw_state.pcsdw12);
12041         } else if (IS_SKYLAKE(dev)) {
12042                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12043                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12044                               pipe_config->ddi_pll_sel,
12045                               pipe_config->dpll_hw_state.ctrl1,
12046                               pipe_config->dpll_hw_state.cfgcr1,
12047                               pipe_config->dpll_hw_state.cfgcr2);
12048         } else if (HAS_DDI(dev)) {
12049                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12050                               pipe_config->ddi_pll_sel,
12051                               pipe_config->dpll_hw_state.wrpll);
12052         } else {
12053                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12054                               "fp0: 0x%x, fp1: 0x%x\n",
12055                               pipe_config->dpll_hw_state.dpll,
12056                               pipe_config->dpll_hw_state.dpll_md,
12057                               pipe_config->dpll_hw_state.fp0,
12058                               pipe_config->dpll_hw_state.fp1);
12059         }
12060
12061         DRM_DEBUG_KMS("planes on this crtc\n");
12062         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12063                 intel_plane = to_intel_plane(plane);
12064                 if (intel_plane->pipe != crtc->pipe)
12065                         continue;
12066
12067                 state = to_intel_plane_state(plane->state);
12068                 fb = state->base.fb;
12069                 if (!fb) {
12070                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12071                                 "disabled, scaler_id = %d\n",
12072                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12073                                 plane->base.id, intel_plane->pipe,
12074                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12075                                 drm_plane_index(plane), state->scaler_id);
12076                         continue;
12077                 }
12078
12079                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12080                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12081                         plane->base.id, intel_plane->pipe,
12082                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12083                         drm_plane_index(plane));
12084                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12085                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12086                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12087                         state->scaler_id,
12088                         state->src.x1 >> 16, state->src.y1 >> 16,
12089                         drm_rect_width(&state->src) >> 16,
12090                         drm_rect_height(&state->src) >> 16,
12091                         state->dst.x1, state->dst.y1,
12092                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12093         }
12094 }
12095
12096 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12097 {
12098         struct drm_device *dev = state->dev;
12099         struct intel_encoder *encoder;
12100         struct drm_connector *connector;
12101         struct drm_connector_state *connector_state;
12102         unsigned int used_ports = 0;
12103         int i;
12104
12105         /*
12106          * Walk the connector list instead of the encoder
12107          * list to detect the problem on ddi platforms
12108          * where there's just one encoder per digital port.
12109          */
12110         for_each_connector_in_state(state, connector, connector_state, i) {
12111                 if (!connector_state->best_encoder)
12112                         continue;
12113
12114                 encoder = to_intel_encoder(connector_state->best_encoder);
12115
12116                 WARN_ON(!connector_state->crtc);
12117
12118                 switch (encoder->type) {
12119                         unsigned int port_mask;
12120                 case INTEL_OUTPUT_UNKNOWN:
12121                         if (WARN_ON(!HAS_DDI(dev)))
12122                                 break;
12123                 case INTEL_OUTPUT_DISPLAYPORT:
12124                 case INTEL_OUTPUT_HDMI:
12125                 case INTEL_OUTPUT_EDP:
12126                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12127
12128                         /* the same port mustn't appear more than once */
12129                         if (used_ports & port_mask)
12130                                 return false;
12131
12132                         used_ports |= port_mask;
12133                 default:
12134                         break;
12135                 }
12136         }
12137
12138         return true;
12139 }
12140
12141 static void
12142 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12143 {
12144         struct drm_crtc_state tmp_state;
12145         struct intel_crtc_scaler_state scaler_state;
12146         struct intel_dpll_hw_state dpll_hw_state;
12147         enum intel_dpll_id shared_dpll;
12148         uint32_t ddi_pll_sel;
12149
12150         /* FIXME: before the switch to atomic started, a new pipe_config was
12151          * kzalloc'd. Code that depends on any field being zero should be
12152          * fixed, so that the crtc_state can be safely duplicated. For now,
12153          * only fields that are know to not cause problems are preserved. */
12154
12155         tmp_state = crtc_state->base;
12156         scaler_state = crtc_state->scaler_state;
12157         shared_dpll = crtc_state->shared_dpll;
12158         dpll_hw_state = crtc_state->dpll_hw_state;
12159         ddi_pll_sel = crtc_state->ddi_pll_sel;
12160
12161         memset(crtc_state, 0, sizeof *crtc_state);
12162
12163         crtc_state->base = tmp_state;
12164         crtc_state->scaler_state = scaler_state;
12165         crtc_state->shared_dpll = shared_dpll;
12166         crtc_state->dpll_hw_state = dpll_hw_state;
12167         crtc_state->ddi_pll_sel = ddi_pll_sel;
12168 }
12169
12170 static int
12171 intel_modeset_pipe_config(struct drm_crtc *crtc,
12172                           struct intel_crtc_state *pipe_config)
12173 {
12174         struct drm_atomic_state *state = pipe_config->base.state;
12175         struct intel_encoder *encoder;
12176         struct drm_connector *connector;
12177         struct drm_connector_state *connector_state;
12178         int base_bpp, ret = -EINVAL;
12179         int i;
12180         bool retry = true;
12181
12182         clear_intel_crtc_state(pipe_config);
12183
12184         pipe_config->cpu_transcoder =
12185                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12186
12187         /*
12188          * Sanitize sync polarity flags based on requested ones. If neither
12189          * positive or negative polarity is requested, treat this as meaning
12190          * negative polarity.
12191          */
12192         if (!(pipe_config->base.adjusted_mode.flags &
12193               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12194                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12195
12196         if (!(pipe_config->base.adjusted_mode.flags &
12197               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12198                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12199
12200         /* Compute a starting value for pipe_config->pipe_bpp taking the source
12201          * plane pixel format and any sink constraints into account. Returns the
12202          * source plane bpp so that dithering can be selected on mismatches
12203          * after encoders and crtc also have had their say. */
12204         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12205                                              pipe_config);
12206         if (base_bpp < 0)
12207                 goto fail;
12208
12209         /*
12210          * Determine the real pipe dimensions. Note that stereo modes can
12211          * increase the actual pipe size due to the frame doubling and
12212          * insertion of additional space for blanks between the frame. This
12213          * is stored in the crtc timings. We use the requested mode to do this
12214          * computation to clearly distinguish it from the adjusted mode, which
12215          * can be changed by the connectors in the below retry loop.
12216          */
12217         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12218                                &pipe_config->pipe_src_w,
12219                                &pipe_config->pipe_src_h);
12220
12221 encoder_retry:
12222         /* Ensure the port clock defaults are reset when retrying. */
12223         pipe_config->port_clock = 0;
12224         pipe_config->pixel_multiplier = 1;
12225
12226         /* Fill in default crtc timings, allow encoders to overwrite them. */
12227         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12228                               CRTC_STEREO_DOUBLE);
12229
12230         /* Pass our mode to the connectors and the CRTC to give them a chance to
12231          * adjust it according to limitations or connector properties, and also
12232          * a chance to reject the mode entirely.
12233          */
12234         for_each_connector_in_state(state, connector, connector_state, i) {
12235                 if (connector_state->crtc != crtc)
12236                         continue;
12237
12238                 encoder = to_intel_encoder(connector_state->best_encoder);
12239
12240                 if (!(encoder->compute_config(encoder, pipe_config))) {
12241                         DRM_DEBUG_KMS("Encoder config failure\n");
12242                         goto fail;
12243                 }
12244         }
12245
12246         /* Set default port clock if not overwritten by the encoder. Needs to be
12247          * done afterwards in case the encoder adjusts the mode. */
12248         if (!pipe_config->port_clock)
12249                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12250                         * pipe_config->pixel_multiplier;
12251
12252         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12253         if (ret < 0) {
12254                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12255                 goto fail;
12256         }
12257
12258         if (ret == RETRY) {
12259                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12260                         ret = -EINVAL;
12261                         goto fail;
12262                 }
12263
12264                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12265                 retry = false;
12266                 goto encoder_retry;
12267         }
12268
12269         pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12270         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12271                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12272
12273         /* Check if we need to force a modeset */
12274         if (pipe_config->has_audio !=
12275             to_intel_crtc_state(crtc->state)->has_audio) {
12276                 pipe_config->base.mode_changed = true;
12277                 ret = drm_atomic_add_affected_planes(state, crtc);
12278         }
12279
12280         /*
12281          * Note we have an issue here with infoframes: current code
12282          * only updates them on the full mode set path per hw
12283          * requirements.  So here we should be checking for any
12284          * required changes and forcing a mode set.
12285          */
12286 fail:
12287         return ret;
12288 }
12289
12290 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12291 {
12292         struct drm_encoder *encoder;
12293         struct drm_device *dev = crtc->dev;
12294
12295         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12296                 if (encoder->crtc == crtc)
12297                         return true;
12298
12299         return false;
12300 }
12301
12302 static void
12303 intel_modeset_update_state(struct drm_atomic_state *state)
12304 {
12305         struct drm_device *dev = state->dev;
12306         struct intel_encoder *intel_encoder;
12307         struct drm_crtc *crtc;
12308         struct drm_crtc_state *crtc_state;
12309         struct drm_connector *connector;
12310
12311         intel_shared_dpll_commit(state);
12312
12313         for_each_intel_encoder(dev, intel_encoder) {
12314                 if (!intel_encoder->base.crtc)
12315                         continue;
12316
12317                 crtc = intel_encoder->base.crtc;
12318                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12319                 if (!crtc_state || !needs_modeset(crtc->state))
12320                         continue;
12321
12322                 intel_encoder->connectors_active = false;
12323         }
12324
12325         drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12326         intel_modeset_update_staged_output_state(state->dev);
12327
12328         /* Double check state. */
12329         for_each_crtc(dev, crtc) {
12330                 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12331
12332                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12333
12334                 /* Update hwmode for vblank functions */
12335                 if (crtc->state->active)
12336                         crtc->hwmode = crtc->state->adjusted_mode;
12337                 else
12338                         crtc->hwmode.crtc_clock = 0;
12339         }
12340
12341         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12342                 if (!connector->encoder || !connector->encoder->crtc)
12343                         continue;
12344
12345                 crtc = connector->encoder->crtc;
12346                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12347                 if (!crtc_state || !needs_modeset(crtc->state))
12348                         continue;
12349
12350                 if (crtc->state->active) {
12351                         struct drm_property *dpms_property =
12352                                 dev->mode_config.dpms_property;
12353
12354                         connector->dpms = DRM_MODE_DPMS_ON;
12355                         drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12356
12357                         intel_encoder = to_intel_encoder(connector->encoder);
12358                         intel_encoder->connectors_active = true;
12359                 } else
12360                         connector->dpms = DRM_MODE_DPMS_OFF;
12361         }
12362 }
12363
12364 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12365 {
12366         int diff;
12367
12368         if (clock1 == clock2)
12369                 return true;
12370
12371         if (!clock1 || !clock2)
12372                 return false;
12373
12374         diff = abs(clock1 - clock2);
12375
12376         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12377                 return true;
12378
12379         return false;
12380 }
12381
12382 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12383         list_for_each_entry((intel_crtc), \
12384                             &(dev)->mode_config.crtc_list, \
12385                             base.head) \
12386                 if (mask & (1 <<(intel_crtc)->pipe))
12387
12388 static bool
12389 intel_pipe_config_compare(struct drm_device *dev,
12390                           struct intel_crtc_state *current_config,
12391                           struct intel_crtc_state *pipe_config)
12392 {
12393 #define PIPE_CONF_CHECK_X(name) \
12394         if (current_config->name != pipe_config->name) { \
12395                 DRM_ERROR("mismatch in " #name " " \
12396                           "(expected 0x%08x, found 0x%08x)\n", \
12397                           current_config->name, \
12398                           pipe_config->name); \
12399                 return false; \
12400         }
12401
12402 #define PIPE_CONF_CHECK_I(name) \
12403         if (current_config->name != pipe_config->name) { \
12404                 DRM_ERROR("mismatch in " #name " " \
12405                           "(expected %i, found %i)\n", \
12406                           current_config->name, \
12407                           pipe_config->name); \
12408                 return false; \
12409         }
12410
12411 /* This is required for BDW+ where there is only one set of registers for
12412  * switching between high and low RR.
12413  * This macro can be used whenever a comparison has to be made between one
12414  * hw state and multiple sw state variables.
12415  */
12416 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12417         if ((current_config->name != pipe_config->name) && \
12418                 (current_config->alt_name != pipe_config->name)) { \
12419                         DRM_ERROR("mismatch in " #name " " \
12420                                   "(expected %i or %i, found %i)\n", \
12421                                   current_config->name, \
12422                                   current_config->alt_name, \
12423                                   pipe_config->name); \
12424                         return false; \
12425         }
12426
12427 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12428         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12429                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
12430                           "(expected %i, found %i)\n", \
12431                           current_config->name & (mask), \
12432                           pipe_config->name & (mask)); \
12433                 return false; \
12434         }
12435
12436 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12437         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12438                 DRM_ERROR("mismatch in " #name " " \
12439                           "(expected %i, found %i)\n", \
12440                           current_config->name, \
12441                           pipe_config->name); \
12442                 return false; \
12443         }
12444
12445 #define PIPE_CONF_QUIRK(quirk)  \
12446         ((current_config->quirks | pipe_config->quirks) & (quirk))
12447
12448         PIPE_CONF_CHECK_I(cpu_transcoder);
12449
12450         PIPE_CONF_CHECK_I(has_pch_encoder);
12451         PIPE_CONF_CHECK_I(fdi_lanes);
12452         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12453         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12454         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12455         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12456         PIPE_CONF_CHECK_I(fdi_m_n.tu);
12457
12458         PIPE_CONF_CHECK_I(has_dp_encoder);
12459
12460         if (INTEL_INFO(dev)->gen < 8) {
12461                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12462                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12463                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12464                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12465                 PIPE_CONF_CHECK_I(dp_m_n.tu);
12466
12467                 if (current_config->has_drrs) {
12468                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12469                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12470                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12471                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12472                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12473                 }
12474         } else {
12475                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12476                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12477                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12478                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12479                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12480         }
12481
12482         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12483         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12484         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12485         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12486         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12487         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12488
12489         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12490         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12491         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12492         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12493         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12494         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12495
12496         PIPE_CONF_CHECK_I(pixel_multiplier);
12497         PIPE_CONF_CHECK_I(has_hdmi_sink);
12498         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12499             IS_VALLEYVIEW(dev))
12500                 PIPE_CONF_CHECK_I(limited_color_range);
12501         PIPE_CONF_CHECK_I(has_infoframe);
12502
12503         PIPE_CONF_CHECK_I(has_audio);
12504
12505         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12506                               DRM_MODE_FLAG_INTERLACE);
12507
12508         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12509                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12510                                       DRM_MODE_FLAG_PHSYNC);
12511                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12512                                       DRM_MODE_FLAG_NHSYNC);
12513                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12514                                       DRM_MODE_FLAG_PVSYNC);
12515                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12516                                       DRM_MODE_FLAG_NVSYNC);
12517         }
12518
12519         PIPE_CONF_CHECK_I(pipe_src_w);
12520         PIPE_CONF_CHECK_I(pipe_src_h);
12521
12522         /*
12523          * FIXME: BIOS likes to set up a cloned config with lvds+external
12524          * screen. Since we don't yet re-compute the pipe config when moving
12525          * just the lvds port away to another pipe the sw tracking won't match.
12526          *
12527          * Proper atomic modesets with recomputed global state will fix this.
12528          * Until then just don't check gmch state for inherited modes.
12529          */
12530         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12531                 PIPE_CONF_CHECK_I(gmch_pfit.control);
12532                 /* pfit ratios are autocomputed by the hw on gen4+ */
12533                 if (INTEL_INFO(dev)->gen < 4)
12534                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12535                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12536         }
12537
12538         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12539         if (current_config->pch_pfit.enabled) {
12540                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12541                 PIPE_CONF_CHECK_I(pch_pfit.size);
12542         }
12543
12544         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12545
12546         /* BDW+ don't expose a synchronous way to read the state */
12547         if (IS_HASWELL(dev))
12548                 PIPE_CONF_CHECK_I(ips_enabled);
12549
12550         PIPE_CONF_CHECK_I(double_wide);
12551
12552         PIPE_CONF_CHECK_X(ddi_pll_sel);
12553
12554         PIPE_CONF_CHECK_I(shared_dpll);
12555         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12556         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12557         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12558         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12559         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12560         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12561         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12562         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12563
12564         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12565                 PIPE_CONF_CHECK_I(pipe_bpp);
12566
12567         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12568         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12569
12570 #undef PIPE_CONF_CHECK_X
12571 #undef PIPE_CONF_CHECK_I
12572 #undef PIPE_CONF_CHECK_I_ALT
12573 #undef PIPE_CONF_CHECK_FLAGS
12574 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12575 #undef PIPE_CONF_QUIRK
12576
12577         return true;
12578 }
12579
12580 static void check_wm_state(struct drm_device *dev)
12581 {
12582         struct drm_i915_private *dev_priv = dev->dev_private;
12583         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12584         struct intel_crtc *intel_crtc;
12585         int plane;
12586
12587         if (INTEL_INFO(dev)->gen < 9)
12588                 return;
12589
12590         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12591         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12592
12593         for_each_intel_crtc(dev, intel_crtc) {
12594                 struct skl_ddb_entry *hw_entry, *sw_entry;
12595                 const enum pipe pipe = intel_crtc->pipe;
12596
12597                 if (!intel_crtc->active)
12598                         continue;
12599
12600                 /* planes */
12601                 for_each_plane(dev_priv, pipe, plane) {
12602                         hw_entry = &hw_ddb.plane[pipe][plane];
12603                         sw_entry = &sw_ddb->plane[pipe][plane];
12604
12605                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12606                                 continue;
12607
12608                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12609                                   "(expected (%u,%u), found (%u,%u))\n",
12610                                   pipe_name(pipe), plane + 1,
12611                                   sw_entry->start, sw_entry->end,
12612                                   hw_entry->start, hw_entry->end);
12613                 }
12614
12615                 /* cursor */
12616                 hw_entry = &hw_ddb.cursor[pipe];
12617                 sw_entry = &sw_ddb->cursor[pipe];
12618
12619                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12620                         continue;
12621
12622                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12623                           "(expected (%u,%u), found (%u,%u))\n",
12624                           pipe_name(pipe),
12625                           sw_entry->start, sw_entry->end,
12626                           hw_entry->start, hw_entry->end);
12627         }
12628 }
12629
12630 static void
12631 check_connector_state(struct drm_device *dev)
12632 {
12633         struct intel_connector *connector;
12634
12635         for_each_intel_connector(dev, connector) {
12636                 /* This also checks the encoder/connector hw state with the
12637                  * ->get_hw_state callbacks. */
12638                 intel_connector_check_state(connector);
12639
12640                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12641                      "connector's staged encoder doesn't match current encoder\n");
12642         }
12643 }
12644
12645 static void
12646 check_encoder_state(struct drm_device *dev)
12647 {
12648         struct intel_encoder *encoder;
12649         struct intel_connector *connector;
12650
12651         for_each_intel_encoder(dev, encoder) {
12652                 bool enabled = false;
12653                 bool active = false;
12654                 enum pipe pipe, tracked_pipe;
12655
12656                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12657                               encoder->base.base.id,
12658                               encoder->base.name);
12659
12660                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12661                      "encoder's stage crtc doesn't match current crtc\n");
12662                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12663                      "encoder's active_connectors set, but no crtc\n");
12664
12665                 for_each_intel_connector(dev, connector) {
12666                         if (connector->base.encoder != &encoder->base)
12667                                 continue;
12668                         enabled = true;
12669                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12670                                 active = true;
12671                 }
12672                 /*
12673                  * for MST connectors if we unplug the connector is gone
12674                  * away but the encoder is still connected to a crtc
12675                  * until a modeset happens in response to the hotplug.
12676                  */
12677                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12678                         continue;
12679
12680                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12681                      "encoder's enabled state mismatch "
12682                      "(expected %i, found %i)\n",
12683                      !!encoder->base.crtc, enabled);
12684                 I915_STATE_WARN(active && !encoder->base.crtc,
12685                      "active encoder with no crtc\n");
12686
12687                 I915_STATE_WARN(encoder->connectors_active != active,
12688                      "encoder's computed active state doesn't match tracked active state "
12689                      "(expected %i, found %i)\n", active, encoder->connectors_active);
12690
12691                 active = encoder->get_hw_state(encoder, &pipe);
12692                 I915_STATE_WARN(active != encoder->connectors_active,
12693                      "encoder's hw state doesn't match sw tracking "
12694                      "(expected %i, found %i)\n",
12695                      encoder->connectors_active, active);
12696
12697                 if (!encoder->base.crtc)
12698                         continue;
12699
12700                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12701                 I915_STATE_WARN(active && pipe != tracked_pipe,
12702                      "active encoder's pipe doesn't match"
12703                      "(expected %i, found %i)\n",
12704                      tracked_pipe, pipe);
12705
12706         }
12707 }
12708
12709 static void
12710 check_crtc_state(struct drm_device *dev)
12711 {
12712         struct drm_i915_private *dev_priv = dev->dev_private;
12713         struct intel_crtc *crtc;
12714         struct intel_encoder *encoder;
12715         struct intel_crtc_state pipe_config;
12716
12717         for_each_intel_crtc(dev, crtc) {
12718                 bool enabled = false;
12719                 bool active = false;
12720
12721                 memset(&pipe_config, 0, sizeof(pipe_config));
12722
12723                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12724                               crtc->base.base.id);
12725
12726                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12727                      "active crtc, but not enabled in sw tracking\n");
12728
12729                 for_each_intel_encoder(dev, encoder) {
12730                         if (encoder->base.crtc != &crtc->base)
12731                                 continue;
12732                         enabled = true;
12733                         if (encoder->connectors_active)
12734                                 active = true;
12735                 }
12736
12737                 I915_STATE_WARN(active != crtc->active,
12738                      "crtc's computed active state doesn't match tracked active state "
12739                      "(expected %i, found %i)\n", active, crtc->active);
12740                 I915_STATE_WARN(enabled != crtc->base.state->enable,
12741                      "crtc's computed enabled state doesn't match tracked enabled state "
12742                      "(expected %i, found %i)\n", enabled,
12743                                 crtc->base.state->enable);
12744
12745                 active = dev_priv->display.get_pipe_config(crtc,
12746                                                            &pipe_config);
12747
12748                 /* hw state is inconsistent with the pipe quirk */
12749                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12750                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12751                         active = crtc->active;
12752
12753                 for_each_intel_encoder(dev, encoder) {
12754                         enum pipe pipe;
12755                         if (encoder->base.crtc != &crtc->base)
12756                                 continue;
12757                         if (encoder->get_hw_state(encoder, &pipe))
12758                                 encoder->get_config(encoder, &pipe_config);
12759                 }
12760
12761                 I915_STATE_WARN(crtc->active != active,
12762                      "crtc active state doesn't match with hw state "
12763                      "(expected %i, found %i)\n", crtc->active, active);
12764
12765                 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12766                      "transitional active state does not match atomic hw state "
12767                      "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12768
12769                 if (active &&
12770                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12771                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12772                         intel_dump_pipe_config(crtc, &pipe_config,
12773                                                "[hw state]");
12774                         intel_dump_pipe_config(crtc, crtc->config,
12775                                                "[sw state]");
12776                 }
12777         }
12778 }
12779
12780 static void
12781 check_shared_dpll_state(struct drm_device *dev)
12782 {
12783         struct drm_i915_private *dev_priv = dev->dev_private;
12784         struct intel_crtc *crtc;
12785         struct intel_dpll_hw_state dpll_hw_state;
12786         int i;
12787
12788         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12789                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12790                 int enabled_crtcs = 0, active_crtcs = 0;
12791                 bool active;
12792
12793                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12794
12795                 DRM_DEBUG_KMS("%s\n", pll->name);
12796
12797                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12798
12799                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12800                      "more active pll users than references: %i vs %i\n",
12801                      pll->active, hweight32(pll->config.crtc_mask));
12802                 I915_STATE_WARN(pll->active && !pll->on,
12803                      "pll in active use but not on in sw tracking\n");
12804                 I915_STATE_WARN(pll->on && !pll->active,
12805                      "pll in on but not on in use in sw tracking\n");
12806                 I915_STATE_WARN(pll->on != active,
12807                      "pll on state mismatch (expected %i, found %i)\n",
12808                      pll->on, active);
12809
12810                 for_each_intel_crtc(dev, crtc) {
12811                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12812                                 enabled_crtcs++;
12813                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12814                                 active_crtcs++;
12815                 }
12816                 I915_STATE_WARN(pll->active != active_crtcs,
12817                      "pll active crtcs mismatch (expected %i, found %i)\n",
12818                      pll->active, active_crtcs);
12819                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12820                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12821                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12822
12823                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12824                                        sizeof(dpll_hw_state)),
12825                      "pll hw state mismatch\n");
12826         }
12827 }
12828
12829 void
12830 intel_modeset_check_state(struct drm_device *dev)
12831 {
12832         check_wm_state(dev);
12833         check_connector_state(dev);
12834         check_encoder_state(dev);
12835         check_crtc_state(dev);
12836         check_shared_dpll_state(dev);
12837 }
12838
12839 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12840                                      int dotclock)
12841 {
12842         /*
12843          * FDI already provided one idea for the dotclock.
12844          * Yell if the encoder disagrees.
12845          */
12846         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12847              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12848              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12849 }
12850
12851 static void update_scanline_offset(struct intel_crtc *crtc)
12852 {
12853         struct drm_device *dev = crtc->base.dev;
12854
12855         /*
12856          * The scanline counter increments at the leading edge of hsync.
12857          *
12858          * On most platforms it starts counting from vtotal-1 on the
12859          * first active line. That means the scanline counter value is
12860          * always one less than what we would expect. Ie. just after
12861          * start of vblank, which also occurs at start of hsync (on the
12862          * last active line), the scanline counter will read vblank_start-1.
12863          *
12864          * On gen2 the scanline counter starts counting from 1 instead
12865          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12866          * to keep the value positive), instead of adding one.
12867          *
12868          * On HSW+ the behaviour of the scanline counter depends on the output
12869          * type. For DP ports it behaves like most other platforms, but on HDMI
12870          * there's an extra 1 line difference. So we need to add two instead of
12871          * one to the value.
12872          */
12873         if (IS_GEN2(dev)) {
12874                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12875                 int vtotal;
12876
12877                 vtotal = mode->crtc_vtotal;
12878                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12879                         vtotal /= 2;
12880
12881                 crtc->scanline_offset = vtotal - 1;
12882         } else if (HAS_DDI(dev) &&
12883                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12884                 crtc->scanline_offset = 2;
12885         } else
12886                 crtc->scanline_offset = 1;
12887 }
12888
12889 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12890 {
12891         struct drm_device *dev = state->dev;
12892         struct drm_i915_private *dev_priv = to_i915(dev);
12893         struct intel_shared_dpll_config *shared_dpll = NULL;
12894         struct intel_crtc *intel_crtc;
12895         struct intel_crtc_state *intel_crtc_state;
12896         struct drm_crtc *crtc;
12897         struct drm_crtc_state *crtc_state;
12898         int i;
12899
12900         if (!dev_priv->display.crtc_compute_clock)
12901                 return;
12902
12903         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12904                 int dpll;
12905
12906                 intel_crtc = to_intel_crtc(crtc);
12907                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12908                 dpll = intel_crtc_state->shared_dpll;
12909
12910                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12911                         continue;
12912
12913                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12914
12915                 if (!shared_dpll)
12916                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12917
12918                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12919         }
12920 }
12921
12922 /*
12923  * This implements the workaround described in the "notes" section of the mode
12924  * set sequence documentation. When going from no pipes or single pipe to
12925  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12926  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12927  */
12928 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12929 {
12930         struct drm_crtc_state *crtc_state;
12931         struct intel_crtc *intel_crtc;
12932         struct drm_crtc *crtc;
12933         struct intel_crtc_state *first_crtc_state = NULL;
12934         struct intel_crtc_state *other_crtc_state = NULL;
12935         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12936         int i;
12937
12938         /* look at all crtc's that are going to be enabled in during modeset */
12939         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12940                 intel_crtc = to_intel_crtc(crtc);
12941
12942                 if (!crtc_state->active || !needs_modeset(crtc_state))
12943                         continue;
12944
12945                 if (first_crtc_state) {
12946                         other_crtc_state = to_intel_crtc_state(crtc_state);
12947                         break;
12948                 } else {
12949                         first_crtc_state = to_intel_crtc_state(crtc_state);
12950                         first_pipe = intel_crtc->pipe;
12951                 }
12952         }
12953
12954         /* No workaround needed? */
12955         if (!first_crtc_state)
12956                 return 0;
12957
12958         /* w/a possibly needed, check how many crtc's are already enabled. */
12959         for_each_intel_crtc(state->dev, intel_crtc) {
12960                 struct intel_crtc_state *pipe_config;
12961
12962                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12963                 if (IS_ERR(pipe_config))
12964                         return PTR_ERR(pipe_config);
12965
12966                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12967
12968                 if (!pipe_config->base.active ||
12969                     needs_modeset(&pipe_config->base))
12970                         continue;
12971
12972                 /* 2 or more enabled crtcs means no need for w/a */
12973                 if (enabled_pipe != INVALID_PIPE)
12974                         return 0;
12975
12976                 enabled_pipe = intel_crtc->pipe;
12977         }
12978
12979         if (enabled_pipe != INVALID_PIPE)
12980                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12981         else if (other_crtc_state)
12982                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12983
12984         return 0;
12985 }
12986
12987 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12988 {
12989         struct drm_crtc *crtc;
12990         struct drm_crtc_state *crtc_state;
12991         int ret = 0;
12992
12993         /* add all active pipes to the state */
12994         for_each_crtc(state->dev, crtc) {
12995                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12996                 if (IS_ERR(crtc_state))
12997                         return PTR_ERR(crtc_state);
12998
12999                 if (!crtc_state->active || needs_modeset(crtc_state))
13000                         continue;
13001
13002                 crtc_state->mode_changed = true;
13003
13004                 ret = drm_atomic_add_affected_connectors(state, crtc);
13005                 if (ret)
13006                         break;
13007
13008                 ret = drm_atomic_add_affected_planes(state, crtc);
13009                 if (ret)
13010                         break;
13011         }
13012
13013         return ret;
13014 }
13015
13016
13017 /* Code that should eventually be part of atomic_check() */
13018 static int intel_modeset_checks(struct drm_atomic_state *state)
13019 {
13020         struct drm_device *dev = state->dev;
13021         struct drm_i915_private *dev_priv = dev->dev_private;
13022         int ret;
13023
13024         if (!check_digital_port_conflicts(state)) {
13025                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13026                 return -EINVAL;
13027         }
13028
13029         /*
13030          * See if the config requires any additional preparation, e.g.
13031          * to adjust global state with pipes off.  We need to do this
13032          * here so we can get the modeset_pipe updated config for the new
13033          * mode set on this crtc.  For other crtcs we need to use the
13034          * adjusted_mode bits in the crtc directly.
13035          */
13036         if (dev_priv->display.modeset_calc_cdclk) {
13037                 unsigned int cdclk;
13038
13039                 ret = dev_priv->display.modeset_calc_cdclk(state);
13040
13041                 cdclk = to_intel_atomic_state(state)->cdclk;
13042                 if (!ret && cdclk != dev_priv->cdclk_freq)
13043                         ret = intel_modeset_all_pipes(state);
13044
13045                 if (ret < 0)
13046                         return ret;
13047         } else
13048                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13049
13050         intel_modeset_clear_plls(state);
13051
13052         if (IS_HASWELL(dev))
13053                 return haswell_mode_set_planes_workaround(state);
13054
13055         return 0;
13056 }
13057
13058 static int
13059 intel_modeset_compute_config(struct drm_atomic_state *state)
13060 {
13061         struct drm_crtc *crtc;
13062         struct drm_crtc_state *crtc_state;
13063         int ret, i;
13064         bool any_ms = false;
13065
13066         ret = drm_atomic_helper_check_modeset(state->dev, state);
13067         if (ret)
13068                 return ret;
13069
13070         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13071                 if (!crtc_state->enable) {
13072                         if (needs_modeset(crtc_state))
13073                                 any_ms = true;
13074                         continue;
13075                 }
13076
13077                 if (to_intel_crtc_state(crtc_state)->quirks &
13078                     PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13079                         ret = drm_atomic_add_affected_planes(state, crtc);
13080                         if (ret)
13081                                 return ret;
13082
13083                         /*
13084                          * We ought to handle i915.fastboot here.
13085                          * If no modeset is required and the primary plane has
13086                          * a fb, update the members of crtc_state as needed,
13087                          * and run the necessary updates during vblank evasion.
13088                          */
13089                 }
13090
13091                 if (!needs_modeset(crtc_state)) {
13092                         ret = drm_atomic_add_affected_connectors(state, crtc);
13093                         if (ret)
13094                                 return ret;
13095                 }
13096
13097                 ret = intel_modeset_pipe_config(crtc,
13098                                         to_intel_crtc_state(crtc_state));
13099                 if (ret)
13100                         return ret;
13101
13102                 if (needs_modeset(crtc_state))
13103                         any_ms = true;
13104
13105                 intel_dump_pipe_config(to_intel_crtc(crtc),
13106                                        to_intel_crtc_state(crtc_state),
13107                                        "[modeset]");
13108         }
13109
13110         if (any_ms) {
13111                 ret = intel_modeset_checks(state);
13112
13113                 if (ret)
13114                         return ret;
13115         } else
13116                 to_intel_atomic_state(state)->cdclk =
13117                         to_i915(state->dev)->cdclk_freq;
13118
13119         return drm_atomic_helper_check_planes(state->dev, state);
13120 }
13121
13122 static int __intel_set_mode(struct drm_atomic_state *state)
13123 {
13124         struct drm_device *dev = state->dev;
13125         struct drm_i915_private *dev_priv = dev->dev_private;
13126         struct drm_crtc *crtc;
13127         struct drm_crtc_state *crtc_state;
13128         int ret = 0;
13129         int i;
13130         bool any_ms = false;
13131
13132         ret = drm_atomic_helper_prepare_planes(dev, state);
13133         if (ret)
13134                 return ret;
13135
13136         drm_atomic_helper_swap_state(dev, state);
13137
13138         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13139                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13140
13141                 if (!needs_modeset(crtc->state))
13142                         continue;
13143
13144                 intel_pre_plane_update(intel_crtc);
13145
13146                 any_ms = true;
13147                 intel_pre_plane_update(intel_crtc);
13148
13149                 if (crtc_state->active) {
13150                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13151                         dev_priv->display.crtc_disable(crtc);
13152                         intel_crtc->active = false;
13153                         intel_disable_shared_dpll(intel_crtc);
13154                 }
13155         }
13156
13157         /* Only after disabling all output pipelines that will be changed can we
13158          * update the the output configuration. */
13159         intel_modeset_update_state(state);
13160
13161         /* The state has been swaped above, so state actually contains the
13162          * old state now. */
13163         if (any_ms)
13164                 modeset_update_crtc_power_domains(state);
13165
13166         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13167         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13168                 if (needs_modeset(crtc->state) && crtc->state->active) {
13169                         update_scanline_offset(to_intel_crtc(crtc));
13170                         dev_priv->display.crtc_enable(crtc);
13171                 }
13172
13173                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13174         }
13175
13176         /* FIXME: add subpixel order */
13177
13178         drm_atomic_helper_cleanup_planes(dev, state);
13179
13180         drm_atomic_state_free(state);
13181
13182         return 0;
13183 }
13184
13185 static int intel_set_mode_checked(struct drm_atomic_state *state)
13186 {
13187         struct drm_device *dev = state->dev;
13188         int ret;
13189
13190         ret = __intel_set_mode(state);
13191         if (ret == 0)
13192                 intel_modeset_check_state(dev);
13193
13194         return ret;
13195 }
13196
13197 static int intel_set_mode(struct drm_atomic_state *state)
13198 {
13199         int ret;
13200
13201         ret = intel_modeset_compute_config(state);
13202         if (ret)
13203                 return ret;
13204
13205         return intel_set_mode_checked(state);
13206 }
13207
13208 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13209 {
13210         struct drm_device *dev = crtc->dev;
13211         struct drm_atomic_state *state;
13212         struct intel_encoder *encoder;
13213         struct intel_connector *connector;
13214         struct drm_connector_state *connector_state;
13215         struct intel_crtc_state *crtc_state;
13216         int ret;
13217
13218         state = drm_atomic_state_alloc(dev);
13219         if (!state) {
13220                 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13221                               crtc->base.id);
13222                 return;
13223         }
13224
13225         state->acquire_ctx = dev->mode_config.acquire_ctx;
13226
13227         /* The force restore path in the HW readout code relies on the staged
13228          * config still keeping the user requested config while the actual
13229          * state has been overwritten by the configuration read from HW. We
13230          * need to copy the staged config to the atomic state, otherwise the
13231          * mode set will just reapply the state the HW is already in. */
13232         for_each_intel_encoder(dev, encoder) {
13233                 if (&encoder->new_crtc->base != crtc)
13234                         continue;
13235
13236                 for_each_intel_connector(dev, connector) {
13237                         if (connector->new_encoder != encoder)
13238                                 continue;
13239
13240                         connector_state = drm_atomic_get_connector_state(state, &connector->base);
13241                         if (IS_ERR(connector_state)) {
13242                                 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13243                                               connector->base.base.id,
13244                                               connector->base.name,
13245                                               PTR_ERR(connector_state));
13246                                 continue;
13247                         }
13248
13249                         connector_state->crtc = crtc;
13250                         connector_state->best_encoder = &encoder->base;
13251                 }
13252         }
13253
13254         crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13255         if (IS_ERR(crtc_state)) {
13256                 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13257                               crtc->base.id, PTR_ERR(crtc_state));
13258                 drm_atomic_state_free(state);
13259                 return;
13260         }
13261
13262         crtc_state->base.active = crtc_state->base.enable =
13263                 to_intel_crtc(crtc)->new_enabled;
13264
13265         drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13266
13267         intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13268                                         crtc->primary->fb, crtc->x, crtc->y);
13269
13270         ret = intel_set_mode(state);
13271         if (ret)
13272                 drm_atomic_state_free(state);
13273 }
13274
13275 #undef for_each_intel_crtc_masked
13276
13277 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13278                                         struct drm_mode_set *set)
13279 {
13280         int ro;
13281
13282         for (ro = 0; ro < set->num_connectors; ro++)
13283                 if (set->connectors[ro] == &connector->base)
13284                         return true;
13285
13286         return false;
13287 }
13288
13289 static int
13290 intel_modeset_stage_output_state(struct drm_device *dev,
13291                                  struct drm_mode_set *set,
13292                                  struct drm_atomic_state *state)
13293 {
13294         struct intel_connector *connector;
13295         struct drm_connector *drm_connector;
13296         struct drm_connector_state *connector_state;
13297         struct drm_crtc *crtc;
13298         struct drm_crtc_state *crtc_state;
13299         int i, ret;
13300
13301         /* The upper layers ensure that we either disable a crtc or have a list
13302          * of connectors. For paranoia, double-check this. */
13303         WARN_ON(!set->fb && (set->num_connectors != 0));
13304         WARN_ON(set->fb && (set->num_connectors == 0));
13305
13306         for_each_intel_connector(dev, connector) {
13307                 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13308
13309                 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13310                         continue;
13311
13312                 connector_state =
13313                         drm_atomic_get_connector_state(state, &connector->base);
13314                 if (IS_ERR(connector_state))
13315                         return PTR_ERR(connector_state);
13316
13317                 if (in_mode_set) {
13318                         int pipe = to_intel_crtc(set->crtc)->pipe;
13319                         connector_state->best_encoder =
13320                                 &intel_find_encoder(connector, pipe)->base;
13321                 }
13322
13323                 if (connector->base.state->crtc != set->crtc)
13324                         continue;
13325
13326                 /* If we disable the crtc, disable all its connectors. Also, if
13327                  * the connector is on the changing crtc but not on the new
13328                  * connector list, disable it. */
13329                 if (!set->fb || !in_mode_set) {
13330                         connector_state->best_encoder = NULL;
13331
13332                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13333                                 connector->base.base.id,
13334                                 connector->base.name);
13335                 }
13336         }
13337         /* connector->new_encoder is now updated for all connectors. */
13338
13339         for_each_connector_in_state(state, drm_connector, connector_state, i) {
13340                 connector = to_intel_connector(drm_connector);
13341
13342                 if (!connector_state->best_encoder) {
13343                         ret = drm_atomic_set_crtc_for_connector(connector_state,
13344                                                                 NULL);
13345                         if (ret)
13346                                 return ret;
13347
13348                         continue;
13349                 }
13350
13351                 if (intel_connector_in_mode_set(connector, set)) {
13352                         struct drm_crtc *crtc = connector->base.state->crtc;
13353
13354                         /* If this connector was in a previous crtc, add it
13355                          * to the state. We might need to disable it. */
13356                         if (crtc) {
13357                                 crtc_state =
13358                                         drm_atomic_get_crtc_state(state, crtc);
13359                                 if (IS_ERR(crtc_state))
13360                                         return PTR_ERR(crtc_state);
13361                         }
13362
13363                         ret = drm_atomic_set_crtc_for_connector(connector_state,
13364                                                                 set->crtc);
13365                         if (ret)
13366                                 return ret;
13367                 }
13368
13369                 /* Make sure the new CRTC will work with the encoder */
13370                 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13371                                          connector_state->crtc)) {
13372                         return -EINVAL;
13373                 }
13374
13375                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13376                         connector->base.base.id,
13377                         connector->base.name,
13378                         connector_state->crtc->base.id);
13379
13380                 if (connector_state->best_encoder != &connector->encoder->base)
13381                         connector->encoder =
13382                                 to_intel_encoder(connector_state->best_encoder);
13383         }
13384
13385         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13386                 bool has_connectors;
13387
13388                 ret = drm_atomic_add_affected_connectors(state, crtc);
13389                 if (ret)
13390                         return ret;
13391
13392                 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13393                 if (has_connectors != crtc_state->enable)
13394                         crtc_state->enable =
13395                         crtc_state->active = has_connectors;
13396         }
13397
13398         ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13399                                               set->fb, set->x, set->y);
13400         if (ret)
13401                 return ret;
13402
13403         crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13404         if (IS_ERR(crtc_state))
13405                 return PTR_ERR(crtc_state);
13406
13407         ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13408         if (ret)
13409                 return ret;
13410
13411         if (set->num_connectors)
13412                 crtc_state->active = true;
13413
13414         return 0;
13415 }
13416
13417 static int intel_crtc_set_config(struct drm_mode_set *set)
13418 {
13419         struct drm_device *dev;
13420         struct drm_atomic_state *state = NULL;
13421         int ret;
13422
13423         BUG_ON(!set);
13424         BUG_ON(!set->crtc);
13425         BUG_ON(!set->crtc->helper_private);
13426
13427         /* Enforce sane interface api - has been abused by the fb helper. */
13428         BUG_ON(!set->mode && set->fb);
13429         BUG_ON(set->fb && set->num_connectors == 0);
13430
13431         if (set->fb) {
13432                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13433                                 set->crtc->base.id, set->fb->base.id,
13434                                 (int)set->num_connectors, set->x, set->y);
13435         } else {
13436                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13437         }
13438
13439         dev = set->crtc->dev;
13440
13441         state = drm_atomic_state_alloc(dev);
13442         if (!state)
13443                 return -ENOMEM;
13444
13445         state->acquire_ctx = dev->mode_config.acquire_ctx;
13446
13447         ret = intel_modeset_stage_output_state(dev, set, state);
13448         if (ret)
13449                 goto out;
13450
13451         ret = intel_modeset_compute_config(state);
13452         if (ret)
13453                 goto out;
13454
13455         intel_update_pipe_size(to_intel_crtc(set->crtc));
13456
13457         ret = intel_set_mode_checked(state);
13458         if (ret) {
13459                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13460                               set->crtc->base.id, ret);
13461         }
13462
13463 out:
13464         if (ret)
13465                 drm_atomic_state_free(state);
13466         return ret;
13467 }
13468
13469 static const struct drm_crtc_funcs intel_crtc_funcs = {
13470         .gamma_set = intel_crtc_gamma_set,
13471         .set_config = intel_crtc_set_config,
13472         .destroy = intel_crtc_destroy,
13473         .page_flip = intel_crtc_page_flip,
13474         .atomic_duplicate_state = intel_crtc_duplicate_state,
13475         .atomic_destroy_state = intel_crtc_destroy_state,
13476 };
13477
13478 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13479                                       struct intel_shared_dpll *pll,
13480                                       struct intel_dpll_hw_state *hw_state)
13481 {
13482         uint32_t val;
13483
13484         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13485                 return false;
13486
13487         val = I915_READ(PCH_DPLL(pll->id));
13488         hw_state->dpll = val;
13489         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13490         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13491
13492         return val & DPLL_VCO_ENABLE;
13493 }
13494
13495 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13496                                   struct intel_shared_dpll *pll)
13497 {
13498         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13499         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13500 }
13501
13502 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13503                                 struct intel_shared_dpll *pll)
13504 {
13505         /* PCH refclock must be enabled first */
13506         ibx_assert_pch_refclk_enabled(dev_priv);
13507
13508         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13509
13510         /* Wait for the clocks to stabilize. */
13511         POSTING_READ(PCH_DPLL(pll->id));
13512         udelay(150);
13513
13514         /* The pixel multiplier can only be updated once the
13515          * DPLL is enabled and the clocks are stable.
13516          *
13517          * So write it again.
13518          */
13519         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13520         POSTING_READ(PCH_DPLL(pll->id));
13521         udelay(200);
13522 }
13523
13524 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13525                                  struct intel_shared_dpll *pll)
13526 {
13527         struct drm_device *dev = dev_priv->dev;
13528         struct intel_crtc *crtc;
13529
13530         /* Make sure no transcoder isn't still depending on us. */
13531         for_each_intel_crtc(dev, crtc) {
13532                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13533                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13534         }
13535
13536         I915_WRITE(PCH_DPLL(pll->id), 0);
13537         POSTING_READ(PCH_DPLL(pll->id));
13538         udelay(200);
13539 }
13540
13541 static char *ibx_pch_dpll_names[] = {
13542         "PCH DPLL A",
13543         "PCH DPLL B",
13544 };
13545
13546 static void ibx_pch_dpll_init(struct drm_device *dev)
13547 {
13548         struct drm_i915_private *dev_priv = dev->dev_private;
13549         int i;
13550
13551         dev_priv->num_shared_dpll = 2;
13552
13553         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13554                 dev_priv->shared_dplls[i].id = i;
13555                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13556                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13557                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13558                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13559                 dev_priv->shared_dplls[i].get_hw_state =
13560                         ibx_pch_dpll_get_hw_state;
13561         }
13562 }
13563
13564 static void intel_shared_dpll_init(struct drm_device *dev)
13565 {
13566         struct drm_i915_private *dev_priv = dev->dev_private;
13567
13568         intel_update_cdclk(dev);
13569
13570         if (HAS_DDI(dev))
13571                 intel_ddi_pll_init(dev);
13572         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13573                 ibx_pch_dpll_init(dev);
13574         else
13575                 dev_priv->num_shared_dpll = 0;
13576
13577         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13578 }
13579
13580 /**
13581  * intel_prepare_plane_fb - Prepare fb for usage on plane
13582  * @plane: drm plane to prepare for
13583  * @fb: framebuffer to prepare for presentation
13584  *
13585  * Prepares a framebuffer for usage on a display plane.  Generally this
13586  * involves pinning the underlying object and updating the frontbuffer tracking
13587  * bits.  Some older platforms need special physical address handling for
13588  * cursor planes.
13589  *
13590  * Returns 0 on success, negative error code on failure.
13591  */
13592 int
13593 intel_prepare_plane_fb(struct drm_plane *plane,
13594                        struct drm_framebuffer *fb,
13595                        const struct drm_plane_state *new_state)
13596 {
13597         struct drm_device *dev = plane->dev;
13598         struct intel_plane *intel_plane = to_intel_plane(plane);
13599         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13600         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13601         int ret = 0;
13602
13603         if (!obj)
13604                 return 0;
13605
13606         mutex_lock(&dev->struct_mutex);
13607
13608         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13609             INTEL_INFO(dev)->cursor_needs_physical) {
13610                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13611                 ret = i915_gem_object_attach_phys(obj, align);
13612                 if (ret)
13613                         DRM_DEBUG_KMS("failed to attach phys object\n");
13614         } else {
13615                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13616         }
13617
13618         if (ret == 0)
13619                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13620
13621         mutex_unlock(&dev->struct_mutex);
13622
13623         return ret;
13624 }
13625
13626 /**
13627  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13628  * @plane: drm plane to clean up for
13629  * @fb: old framebuffer that was on plane
13630  *
13631  * Cleans up a framebuffer that has just been removed from a plane.
13632  */
13633 void
13634 intel_cleanup_plane_fb(struct drm_plane *plane,
13635                        struct drm_framebuffer *fb,
13636                        const struct drm_plane_state *old_state)
13637 {
13638         struct drm_device *dev = plane->dev;
13639         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13640
13641         if (WARN_ON(!obj))
13642                 return;
13643
13644         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13645             !INTEL_INFO(dev)->cursor_needs_physical) {
13646                 mutex_lock(&dev->struct_mutex);
13647                 intel_unpin_fb_obj(fb, old_state);
13648                 mutex_unlock(&dev->struct_mutex);
13649         }
13650 }
13651
13652 int
13653 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13654 {
13655         int max_scale;
13656         struct drm_device *dev;
13657         struct drm_i915_private *dev_priv;
13658         int crtc_clock, cdclk;
13659
13660         if (!intel_crtc || !crtc_state)
13661                 return DRM_PLANE_HELPER_NO_SCALING;
13662
13663         dev = intel_crtc->base.dev;
13664         dev_priv = dev->dev_private;
13665         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13666         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13667
13668         if (!crtc_clock || !cdclk)
13669                 return DRM_PLANE_HELPER_NO_SCALING;
13670
13671         /*
13672          * skl max scale is lower of:
13673          *    close to 3 but not 3, -1 is for that purpose
13674          *            or
13675          *    cdclk/crtc_clock
13676          */
13677         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13678
13679         return max_scale;
13680 }
13681
13682 static int
13683 intel_check_primary_plane(struct drm_plane *plane,
13684                           struct intel_crtc_state *crtc_state,
13685                           struct intel_plane_state *state)
13686 {
13687         struct drm_crtc *crtc = state->base.crtc;
13688         struct drm_framebuffer *fb = state->base.fb;
13689         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13690         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13691         bool can_position = false;
13692
13693         /* use scaler when colorkey is not required */
13694         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13695             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13696                 min_scale = 1;
13697                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13698                 can_position = true;
13699         }
13700
13701         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13702                                              &state->dst, &state->clip,
13703                                              min_scale, max_scale,
13704                                              can_position, true,
13705                                              &state->visible);
13706 }
13707
13708 static void
13709 intel_commit_primary_plane(struct drm_plane *plane,
13710                            struct intel_plane_state *state)
13711 {
13712         struct drm_crtc *crtc = state->base.crtc;
13713         struct drm_framebuffer *fb = state->base.fb;
13714         struct drm_device *dev = plane->dev;
13715         struct drm_i915_private *dev_priv = dev->dev_private;
13716         struct intel_crtc *intel_crtc;
13717         struct drm_rect *src = &state->src;
13718
13719         crtc = crtc ? crtc : plane->crtc;
13720         intel_crtc = to_intel_crtc(crtc);
13721
13722         plane->fb = fb;
13723         crtc->x = src->x1 >> 16;
13724         crtc->y = src->y1 >> 16;
13725
13726         if (!crtc->state->active)
13727                 return;
13728
13729         if (state->visible)
13730                 /* FIXME: kill this fastboot hack */
13731                 intel_update_pipe_size(intel_crtc);
13732
13733         dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13734 }
13735
13736 static void
13737 intel_disable_primary_plane(struct drm_plane *plane,
13738                             struct drm_crtc *crtc)
13739 {
13740         struct drm_device *dev = plane->dev;
13741         struct drm_i915_private *dev_priv = dev->dev_private;
13742
13743         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13744 }
13745
13746 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13747 {
13748         struct drm_device *dev = crtc->dev;
13749         struct drm_i915_private *dev_priv = dev->dev_private;
13750         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13751
13752         if (!needs_modeset(crtc->state))
13753                 intel_pre_plane_update(intel_crtc);
13754
13755         if (intel_crtc->atomic.update_wm_pre)
13756                 intel_update_watermarks(crtc);
13757
13758         intel_runtime_pm_get(dev_priv);
13759
13760         /* Perform vblank evasion around commit operation */
13761         if (crtc->state->active)
13762                 intel_crtc->atomic.evade =
13763                         intel_pipe_update_start(intel_crtc,
13764                                                 &intel_crtc->atomic.start_vbl_count);
13765
13766         if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13767                 skl_detach_scalers(intel_crtc);
13768 }
13769
13770 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13771 {
13772         struct drm_device *dev = crtc->dev;
13773         struct drm_i915_private *dev_priv = dev->dev_private;
13774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13775
13776         if (intel_crtc->atomic.evade)
13777                 intel_pipe_update_end(intel_crtc,
13778                                       intel_crtc->atomic.start_vbl_count);
13779
13780         intel_runtime_pm_put(dev_priv);
13781
13782         intel_post_plane_update(intel_crtc);
13783 }
13784
13785 /**
13786  * intel_plane_destroy - destroy a plane
13787  * @plane: plane to destroy
13788  *
13789  * Common destruction function for all types of planes (primary, cursor,
13790  * sprite).
13791  */
13792 void intel_plane_destroy(struct drm_plane *plane)
13793 {
13794         struct intel_plane *intel_plane = to_intel_plane(plane);
13795         drm_plane_cleanup(plane);
13796         kfree(intel_plane);
13797 }
13798
13799 const struct drm_plane_funcs intel_plane_funcs = {
13800         .update_plane = drm_atomic_helper_update_plane,
13801         .disable_plane = drm_atomic_helper_disable_plane,
13802         .destroy = intel_plane_destroy,
13803         .set_property = drm_atomic_helper_plane_set_property,
13804         .atomic_get_property = intel_plane_atomic_get_property,
13805         .atomic_set_property = intel_plane_atomic_set_property,
13806         .atomic_duplicate_state = intel_plane_duplicate_state,
13807         .atomic_destroy_state = intel_plane_destroy_state,
13808
13809 };
13810
13811 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13812                                                     int pipe)
13813 {
13814         struct intel_plane *primary;
13815         struct intel_plane_state *state;
13816         const uint32_t *intel_primary_formats;
13817         int num_formats;
13818
13819         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13820         if (primary == NULL)
13821                 return NULL;
13822
13823         state = intel_create_plane_state(&primary->base);
13824         if (!state) {
13825                 kfree(primary);
13826                 return NULL;
13827         }
13828         primary->base.state = &state->base;
13829
13830         primary->can_scale = false;
13831         primary->max_downscale = 1;
13832         if (INTEL_INFO(dev)->gen >= 9) {
13833                 primary->can_scale = true;
13834                 state->scaler_id = -1;
13835         }
13836         primary->pipe = pipe;
13837         primary->plane = pipe;
13838         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13839         primary->check_plane = intel_check_primary_plane;
13840         primary->commit_plane = intel_commit_primary_plane;
13841         primary->disable_plane = intel_disable_primary_plane;
13842         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13843                 primary->plane = !pipe;
13844
13845         if (INTEL_INFO(dev)->gen >= 9) {
13846                 intel_primary_formats = skl_primary_formats;
13847                 num_formats = ARRAY_SIZE(skl_primary_formats);
13848         } else if (INTEL_INFO(dev)->gen >= 4) {
13849                 intel_primary_formats = i965_primary_formats;
13850                 num_formats = ARRAY_SIZE(i965_primary_formats);
13851         } else {
13852                 intel_primary_formats = i8xx_primary_formats;
13853                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13854         }
13855
13856         drm_universal_plane_init(dev, &primary->base, 0,
13857                                  &intel_plane_funcs,
13858                                  intel_primary_formats, num_formats,
13859                                  DRM_PLANE_TYPE_PRIMARY);
13860
13861         if (INTEL_INFO(dev)->gen >= 4)
13862                 intel_create_rotation_property(dev, primary);
13863
13864         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13865
13866         return &primary->base;
13867 }
13868
13869 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13870 {
13871         if (!dev->mode_config.rotation_property) {
13872                 unsigned long flags = BIT(DRM_ROTATE_0) |
13873                         BIT(DRM_ROTATE_180);
13874
13875                 if (INTEL_INFO(dev)->gen >= 9)
13876                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13877
13878                 dev->mode_config.rotation_property =
13879                         drm_mode_create_rotation_property(dev, flags);
13880         }
13881         if (dev->mode_config.rotation_property)
13882                 drm_object_attach_property(&plane->base.base,
13883                                 dev->mode_config.rotation_property,
13884                                 plane->base.state->rotation);
13885 }
13886
13887 static int
13888 intel_check_cursor_plane(struct drm_plane *plane,
13889                          struct intel_crtc_state *crtc_state,
13890                          struct intel_plane_state *state)
13891 {
13892         struct drm_crtc *crtc = crtc_state->base.crtc;
13893         struct drm_framebuffer *fb = state->base.fb;
13894         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13895         unsigned stride;
13896         int ret;
13897
13898         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13899                                             &state->dst, &state->clip,
13900                                             DRM_PLANE_HELPER_NO_SCALING,
13901                                             DRM_PLANE_HELPER_NO_SCALING,
13902                                             true, true, &state->visible);
13903         if (ret)
13904                 return ret;
13905
13906         /* if we want to turn off the cursor ignore width and height */
13907         if (!obj)
13908                 return 0;
13909
13910         /* Check for which cursor types we support */
13911         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13912                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13913                           state->base.crtc_w, state->base.crtc_h);
13914                 return -EINVAL;
13915         }
13916
13917         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13918         if (obj->base.size < stride * state->base.crtc_h) {
13919                 DRM_DEBUG_KMS("buffer is too small\n");
13920                 return -ENOMEM;
13921         }
13922
13923         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13924                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13925                 return -EINVAL;
13926         }
13927
13928         return 0;
13929 }
13930
13931 static void
13932 intel_disable_cursor_plane(struct drm_plane *plane,
13933                            struct drm_crtc *crtc)
13934 {
13935         intel_crtc_update_cursor(crtc, false);
13936 }
13937
13938 static void
13939 intel_commit_cursor_plane(struct drm_plane *plane,
13940                           struct intel_plane_state *state)
13941 {
13942         struct drm_crtc *crtc = state->base.crtc;
13943         struct drm_device *dev = plane->dev;
13944         struct intel_crtc *intel_crtc;
13945         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13946         uint32_t addr;
13947
13948         crtc = crtc ? crtc : plane->crtc;
13949         intel_crtc = to_intel_crtc(crtc);
13950
13951         plane->fb = state->base.fb;
13952         crtc->cursor_x = state->base.crtc_x;
13953         crtc->cursor_y = state->base.crtc_y;
13954
13955         if (intel_crtc->cursor_bo == obj)
13956                 goto update;
13957
13958         if (!obj)
13959                 addr = 0;
13960         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13961                 addr = i915_gem_obj_ggtt_offset(obj);
13962         else
13963                 addr = obj->phys_handle->busaddr;
13964
13965         intel_crtc->cursor_addr = addr;
13966         intel_crtc->cursor_bo = obj;
13967
13968 update:
13969         if (crtc->state->active)
13970                 intel_crtc_update_cursor(crtc, state->visible);
13971 }
13972
13973 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13974                                                    int pipe)
13975 {
13976         struct intel_plane *cursor;
13977         struct intel_plane_state *state;
13978
13979         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13980         if (cursor == NULL)
13981                 return NULL;
13982
13983         state = intel_create_plane_state(&cursor->base);
13984         if (!state) {
13985                 kfree(cursor);
13986                 return NULL;
13987         }
13988         cursor->base.state = &state->base;
13989
13990         cursor->can_scale = false;
13991         cursor->max_downscale = 1;
13992         cursor->pipe = pipe;
13993         cursor->plane = pipe;
13994         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13995         cursor->check_plane = intel_check_cursor_plane;
13996         cursor->commit_plane = intel_commit_cursor_plane;
13997         cursor->disable_plane = intel_disable_cursor_plane;
13998
13999         drm_universal_plane_init(dev, &cursor->base, 0,
14000                                  &intel_plane_funcs,
14001                                  intel_cursor_formats,
14002                                  ARRAY_SIZE(intel_cursor_formats),
14003                                  DRM_PLANE_TYPE_CURSOR);
14004
14005         if (INTEL_INFO(dev)->gen >= 4) {
14006                 if (!dev->mode_config.rotation_property)
14007                         dev->mode_config.rotation_property =
14008                                 drm_mode_create_rotation_property(dev,
14009                                                         BIT(DRM_ROTATE_0) |
14010                                                         BIT(DRM_ROTATE_180));
14011                 if (dev->mode_config.rotation_property)
14012                         drm_object_attach_property(&cursor->base.base,
14013                                 dev->mode_config.rotation_property,
14014                                 state->base.rotation);
14015         }
14016
14017         if (INTEL_INFO(dev)->gen >=9)
14018                 state->scaler_id = -1;
14019
14020         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14021
14022         return &cursor->base;
14023 }
14024
14025 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14026         struct intel_crtc_state *crtc_state)
14027 {
14028         int i;
14029         struct intel_scaler *intel_scaler;
14030         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14031
14032         for (i = 0; i < intel_crtc->num_scalers; i++) {
14033                 intel_scaler = &scaler_state->scalers[i];
14034                 intel_scaler->in_use = 0;
14035                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14036         }
14037
14038         scaler_state->scaler_id = -1;
14039 }
14040
14041 static void intel_crtc_init(struct drm_device *dev, int pipe)
14042 {
14043         struct drm_i915_private *dev_priv = dev->dev_private;
14044         struct intel_crtc *intel_crtc;
14045         struct intel_crtc_state *crtc_state = NULL;
14046         struct drm_plane *primary = NULL;
14047         struct drm_plane *cursor = NULL;
14048         int i, ret;
14049
14050         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14051         if (intel_crtc == NULL)
14052                 return;
14053
14054         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14055         if (!crtc_state)
14056                 goto fail;
14057         intel_crtc->config = crtc_state;
14058         intel_crtc->base.state = &crtc_state->base;
14059         crtc_state->base.crtc = &intel_crtc->base;
14060
14061         /* initialize shared scalers */
14062         if (INTEL_INFO(dev)->gen >= 9) {
14063                 if (pipe == PIPE_C)
14064                         intel_crtc->num_scalers = 1;
14065                 else
14066                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14067
14068                 skl_init_scalers(dev, intel_crtc, crtc_state);
14069         }
14070
14071         primary = intel_primary_plane_create(dev, pipe);
14072         if (!primary)
14073                 goto fail;
14074
14075         cursor = intel_cursor_plane_create(dev, pipe);
14076         if (!cursor)
14077                 goto fail;
14078
14079         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14080                                         cursor, &intel_crtc_funcs);
14081         if (ret)
14082                 goto fail;
14083
14084         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14085         for (i = 0; i < 256; i++) {
14086                 intel_crtc->lut_r[i] = i;
14087                 intel_crtc->lut_g[i] = i;
14088                 intel_crtc->lut_b[i] = i;
14089         }
14090
14091         /*
14092          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14093          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14094          */
14095         intel_crtc->pipe = pipe;
14096         intel_crtc->plane = pipe;
14097         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14098                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14099                 intel_crtc->plane = !pipe;
14100         }
14101
14102         intel_crtc->cursor_base = ~0;
14103         intel_crtc->cursor_cntl = ~0;
14104         intel_crtc->cursor_size = ~0;
14105
14106         intel_crtc->wm.cxsr_allowed = true;
14107
14108         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14109                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14110         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14111         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14112
14113         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14114
14115         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14116         return;
14117
14118 fail:
14119         if (primary)
14120                 drm_plane_cleanup(primary);
14121         if (cursor)
14122                 drm_plane_cleanup(cursor);
14123         kfree(crtc_state);
14124         kfree(intel_crtc);
14125 }
14126
14127 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14128 {
14129         struct drm_encoder *encoder = connector->base.encoder;
14130         struct drm_device *dev = connector->base.dev;
14131
14132         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14133
14134         if (!encoder || WARN_ON(!encoder->crtc))
14135                 return INVALID_PIPE;
14136
14137         return to_intel_crtc(encoder->crtc)->pipe;
14138 }
14139
14140 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14141                                 struct drm_file *file)
14142 {
14143         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14144         struct drm_crtc *drmmode_crtc;
14145         struct intel_crtc *crtc;
14146
14147         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14148
14149         if (!drmmode_crtc) {
14150                 DRM_ERROR("no such CRTC id\n");
14151                 return -ENOENT;
14152         }
14153
14154         crtc = to_intel_crtc(drmmode_crtc);
14155         pipe_from_crtc_id->pipe = crtc->pipe;
14156
14157         return 0;
14158 }
14159
14160 static int intel_encoder_clones(struct intel_encoder *encoder)
14161 {
14162         struct drm_device *dev = encoder->base.dev;
14163         struct intel_encoder *source_encoder;
14164         int index_mask = 0;
14165         int entry = 0;
14166
14167         for_each_intel_encoder(dev, source_encoder) {
14168                 if (encoders_cloneable(encoder, source_encoder))
14169                         index_mask |= (1 << entry);
14170
14171                 entry++;
14172         }
14173
14174         return index_mask;
14175 }
14176
14177 static bool has_edp_a(struct drm_device *dev)
14178 {
14179         struct drm_i915_private *dev_priv = dev->dev_private;
14180
14181         if (!IS_MOBILE(dev))
14182                 return false;
14183
14184         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14185                 return false;
14186
14187         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14188                 return false;
14189
14190         return true;
14191 }
14192
14193 static bool intel_crt_present(struct drm_device *dev)
14194 {
14195         struct drm_i915_private *dev_priv = dev->dev_private;
14196
14197         if (INTEL_INFO(dev)->gen >= 9)
14198                 return false;
14199
14200         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14201                 return false;
14202
14203         if (IS_CHERRYVIEW(dev))
14204                 return false;
14205
14206         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14207                 return false;
14208
14209         return true;
14210 }
14211
14212 static void intel_setup_outputs(struct drm_device *dev)
14213 {
14214         struct drm_i915_private *dev_priv = dev->dev_private;
14215         struct intel_encoder *encoder;
14216         bool dpd_is_edp = false;
14217
14218         intel_lvds_init(dev);
14219
14220         if (intel_crt_present(dev))
14221                 intel_crt_init(dev);
14222
14223         if (IS_BROXTON(dev)) {
14224                 /*
14225                  * FIXME: Broxton doesn't support port detection via the
14226                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14227                  * detect the ports.
14228                  */
14229                 intel_ddi_init(dev, PORT_A);
14230                 intel_ddi_init(dev, PORT_B);
14231                 intel_ddi_init(dev, PORT_C);
14232         } else if (HAS_DDI(dev)) {
14233                 int found;
14234
14235                 /*
14236                  * Haswell uses DDI functions to detect digital outputs.
14237                  * On SKL pre-D0 the strap isn't connected, so we assume
14238                  * it's there.
14239                  */
14240                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14241                 /* WaIgnoreDDIAStrap: skl */
14242                 if (found ||
14243                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14244                         intel_ddi_init(dev, PORT_A);
14245
14246                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14247                  * register */
14248                 found = I915_READ(SFUSE_STRAP);
14249
14250                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14251                         intel_ddi_init(dev, PORT_B);
14252                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14253                         intel_ddi_init(dev, PORT_C);
14254                 if (found & SFUSE_STRAP_DDID_DETECTED)
14255                         intel_ddi_init(dev, PORT_D);
14256         } else if (HAS_PCH_SPLIT(dev)) {
14257                 int found;
14258                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14259
14260                 if (has_edp_a(dev))
14261                         intel_dp_init(dev, DP_A, PORT_A);
14262
14263                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14264                         /* PCH SDVOB multiplex with HDMIB */
14265                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14266                         if (!found)
14267                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14268                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14269                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14270                 }
14271
14272                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14273                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14274
14275                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14276                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14277
14278                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14279                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14280
14281                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14282                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14283         } else if (IS_VALLEYVIEW(dev)) {
14284                 /*
14285                  * The DP_DETECTED bit is the latched state of the DDC
14286                  * SDA pin at boot. However since eDP doesn't require DDC
14287                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14288                  * eDP ports may have been muxed to an alternate function.
14289                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14290                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14291                  * detect eDP ports.
14292                  */
14293                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14294                     !intel_dp_is_edp(dev, PORT_B))
14295                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14296                                         PORT_B);
14297                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14298                     intel_dp_is_edp(dev, PORT_B))
14299                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14300
14301                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14302                     !intel_dp_is_edp(dev, PORT_C))
14303                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14304                                         PORT_C);
14305                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14306                     intel_dp_is_edp(dev, PORT_C))
14307                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14308
14309                 if (IS_CHERRYVIEW(dev)) {
14310                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14311                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14312                                                 PORT_D);
14313                         /* eDP not supported on port D, so don't check VBT */
14314                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14315                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14316                 }
14317
14318                 intel_dsi_init(dev);
14319         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14320                 bool found = false;
14321
14322                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14323                         DRM_DEBUG_KMS("probing SDVOB\n");
14324                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14325                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14326                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14327                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14328                         }
14329
14330                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
14331                                 intel_dp_init(dev, DP_B, PORT_B);
14332                 }
14333
14334                 /* Before G4X SDVOC doesn't have its own detect register */
14335
14336                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14337                         DRM_DEBUG_KMS("probing SDVOC\n");
14338                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14339                 }
14340
14341                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14342
14343                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14344                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14345                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14346                         }
14347                         if (SUPPORTS_INTEGRATED_DP(dev))
14348                                 intel_dp_init(dev, DP_C, PORT_C);
14349                 }
14350
14351                 if (SUPPORTS_INTEGRATED_DP(dev) &&
14352                     (I915_READ(DP_D) & DP_DETECTED))
14353                         intel_dp_init(dev, DP_D, PORT_D);
14354         } else if (IS_GEN2(dev))
14355                 intel_dvo_init(dev);
14356
14357         if (SUPPORTS_TV(dev))
14358                 intel_tv_init(dev);
14359
14360         intel_psr_init(dev);
14361
14362         for_each_intel_encoder(dev, encoder) {
14363                 encoder->base.possible_crtcs = encoder->crtc_mask;
14364                 encoder->base.possible_clones =
14365                         intel_encoder_clones(encoder);
14366         }
14367
14368         intel_init_pch_refclk(dev);
14369
14370         drm_helper_move_panel_connectors_to_head(dev);
14371 }
14372
14373 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14374 {
14375         struct drm_device *dev = fb->dev;
14376         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14377
14378         drm_framebuffer_cleanup(fb);
14379         mutex_lock(&dev->struct_mutex);
14380         WARN_ON(!intel_fb->obj->framebuffer_references--);
14381         drm_gem_object_unreference(&intel_fb->obj->base);
14382         mutex_unlock(&dev->struct_mutex);
14383         kfree(intel_fb);
14384 }
14385
14386 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14387                                                 struct drm_file *file,
14388                                                 unsigned int *handle)
14389 {
14390         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14391         struct drm_i915_gem_object *obj = intel_fb->obj;
14392
14393         return drm_gem_handle_create(file, &obj->base, handle);
14394 }
14395
14396 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14397         .destroy = intel_user_framebuffer_destroy,
14398         .create_handle = intel_user_framebuffer_create_handle,
14399 };
14400
14401 static
14402 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14403                          uint32_t pixel_format)
14404 {
14405         u32 gen = INTEL_INFO(dev)->gen;
14406
14407         if (gen >= 9) {
14408                 /* "The stride in bytes must not exceed the of the size of 8K
14409                  *  pixels and 32K bytes."
14410                  */
14411                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14412         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14413                 return 32*1024;
14414         } else if (gen >= 4) {
14415                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14416                         return 16*1024;
14417                 else
14418                         return 32*1024;
14419         } else if (gen >= 3) {
14420                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14421                         return 8*1024;
14422                 else
14423                         return 16*1024;
14424         } else {
14425                 /* XXX DSPC is limited to 4k tiled */
14426                 return 8*1024;
14427         }
14428 }
14429
14430 static int intel_framebuffer_init(struct drm_device *dev,
14431                                   struct intel_framebuffer *intel_fb,
14432                                   struct drm_mode_fb_cmd2 *mode_cmd,
14433                                   struct drm_i915_gem_object *obj)
14434 {
14435         unsigned int aligned_height;
14436         int ret;
14437         u32 pitch_limit, stride_alignment;
14438
14439         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14440
14441         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14442                 /* Enforce that fb modifier and tiling mode match, but only for
14443                  * X-tiled. This is needed for FBC. */
14444                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14445                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14446                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14447                         return -EINVAL;
14448                 }
14449         } else {
14450                 if (obj->tiling_mode == I915_TILING_X)
14451                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14452                 else if (obj->tiling_mode == I915_TILING_Y) {
14453                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14454                         return -EINVAL;
14455                 }
14456         }
14457
14458         /* Passed in modifier sanity checking. */
14459         switch (mode_cmd->modifier[0]) {
14460         case I915_FORMAT_MOD_Y_TILED:
14461         case I915_FORMAT_MOD_Yf_TILED:
14462                 if (INTEL_INFO(dev)->gen < 9) {
14463                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14464                                   mode_cmd->modifier[0]);
14465                         return -EINVAL;
14466                 }
14467         case DRM_FORMAT_MOD_NONE:
14468         case I915_FORMAT_MOD_X_TILED:
14469                 break;
14470         default:
14471                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14472                           mode_cmd->modifier[0]);
14473                 return -EINVAL;
14474         }
14475
14476         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14477                                                      mode_cmd->pixel_format);
14478         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14479                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14480                           mode_cmd->pitches[0], stride_alignment);
14481                 return -EINVAL;
14482         }
14483
14484         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14485                                            mode_cmd->pixel_format);
14486         if (mode_cmd->pitches[0] > pitch_limit) {
14487                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14488                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14489                           "tiled" : "linear",
14490                           mode_cmd->pitches[0], pitch_limit);
14491                 return -EINVAL;
14492         }
14493
14494         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14495             mode_cmd->pitches[0] != obj->stride) {
14496                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14497                           mode_cmd->pitches[0], obj->stride);
14498                 return -EINVAL;
14499         }
14500
14501         /* Reject formats not supported by any plane early. */
14502         switch (mode_cmd->pixel_format) {
14503         case DRM_FORMAT_C8:
14504         case DRM_FORMAT_RGB565:
14505         case DRM_FORMAT_XRGB8888:
14506         case DRM_FORMAT_ARGB8888:
14507                 break;
14508         case DRM_FORMAT_XRGB1555:
14509                 if (INTEL_INFO(dev)->gen > 3) {
14510                         DRM_DEBUG("unsupported pixel format: %s\n",
14511                                   drm_get_format_name(mode_cmd->pixel_format));
14512                         return -EINVAL;
14513                 }
14514                 break;
14515         case DRM_FORMAT_ABGR8888:
14516                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14517                         DRM_DEBUG("unsupported pixel format: %s\n",
14518                                   drm_get_format_name(mode_cmd->pixel_format));
14519                         return -EINVAL;
14520                 }
14521                 break;
14522         case DRM_FORMAT_XBGR8888:
14523         case DRM_FORMAT_XRGB2101010:
14524         case DRM_FORMAT_XBGR2101010:
14525                 if (INTEL_INFO(dev)->gen < 4) {
14526                         DRM_DEBUG("unsupported pixel format: %s\n",
14527                                   drm_get_format_name(mode_cmd->pixel_format));
14528                         return -EINVAL;
14529                 }
14530                 break;
14531         case DRM_FORMAT_ABGR2101010:
14532                 if (!IS_VALLEYVIEW(dev)) {
14533                         DRM_DEBUG("unsupported pixel format: %s\n",
14534                                   drm_get_format_name(mode_cmd->pixel_format));
14535                         return -EINVAL;
14536                 }
14537                 break;
14538         case DRM_FORMAT_YUYV:
14539         case DRM_FORMAT_UYVY:
14540         case DRM_FORMAT_YVYU:
14541         case DRM_FORMAT_VYUY:
14542                 if (INTEL_INFO(dev)->gen < 5) {
14543                         DRM_DEBUG("unsupported pixel format: %s\n",
14544                                   drm_get_format_name(mode_cmd->pixel_format));
14545                         return -EINVAL;
14546                 }
14547                 break;
14548         default:
14549                 DRM_DEBUG("unsupported pixel format: %s\n",
14550                           drm_get_format_name(mode_cmd->pixel_format));
14551                 return -EINVAL;
14552         }
14553
14554         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14555         if (mode_cmd->offsets[0] != 0)
14556                 return -EINVAL;
14557
14558         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14559                                                mode_cmd->pixel_format,
14560                                                mode_cmd->modifier[0]);
14561         /* FIXME drm helper for size checks (especially planar formats)? */
14562         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14563                 return -EINVAL;
14564
14565         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14566         intel_fb->obj = obj;
14567         intel_fb->obj->framebuffer_references++;
14568
14569         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14570         if (ret) {
14571                 DRM_ERROR("framebuffer init failed %d\n", ret);
14572                 return ret;
14573         }
14574
14575         return 0;
14576 }
14577
14578 static struct drm_framebuffer *
14579 intel_user_framebuffer_create(struct drm_device *dev,
14580                               struct drm_file *filp,
14581                               struct drm_mode_fb_cmd2 *mode_cmd)
14582 {
14583         struct drm_i915_gem_object *obj;
14584
14585         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14586                                                 mode_cmd->handles[0]));
14587         if (&obj->base == NULL)
14588                 return ERR_PTR(-ENOENT);
14589
14590         return intel_framebuffer_create(dev, mode_cmd, obj);
14591 }
14592
14593 #ifndef CONFIG_DRM_I915_FBDEV
14594 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14595 {
14596 }
14597 #endif
14598
14599 static const struct drm_mode_config_funcs intel_mode_funcs = {
14600         .fb_create = intel_user_framebuffer_create,
14601         .output_poll_changed = intel_fbdev_output_poll_changed,
14602         .atomic_check = intel_atomic_check,
14603         .atomic_commit = intel_atomic_commit,
14604         .atomic_state_alloc = intel_atomic_state_alloc,
14605         .atomic_state_clear = intel_atomic_state_clear,
14606 };
14607
14608 /* Set up chip specific display functions */
14609 static void intel_init_display(struct drm_device *dev)
14610 {
14611         struct drm_i915_private *dev_priv = dev->dev_private;
14612
14613         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14614                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14615         else if (IS_CHERRYVIEW(dev))
14616                 dev_priv->display.find_dpll = chv_find_best_dpll;
14617         else if (IS_VALLEYVIEW(dev))
14618                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14619         else if (IS_PINEVIEW(dev))
14620                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14621         else
14622                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14623
14624         if (INTEL_INFO(dev)->gen >= 9) {
14625                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14626                 dev_priv->display.get_initial_plane_config =
14627                         skylake_get_initial_plane_config;
14628                 dev_priv->display.crtc_compute_clock =
14629                         haswell_crtc_compute_clock;
14630                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14631                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14632                 dev_priv->display.update_primary_plane =
14633                         skylake_update_primary_plane;
14634         } else if (HAS_DDI(dev)) {
14635                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14636                 dev_priv->display.get_initial_plane_config =
14637                         ironlake_get_initial_plane_config;
14638                 dev_priv->display.crtc_compute_clock =
14639                         haswell_crtc_compute_clock;
14640                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14641                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14642                 dev_priv->display.update_primary_plane =
14643                         ironlake_update_primary_plane;
14644         } else if (HAS_PCH_SPLIT(dev)) {
14645                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14646                 dev_priv->display.get_initial_plane_config =
14647                         ironlake_get_initial_plane_config;
14648                 dev_priv->display.crtc_compute_clock =
14649                         ironlake_crtc_compute_clock;
14650                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14651                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14652                 dev_priv->display.update_primary_plane =
14653                         ironlake_update_primary_plane;
14654         } else if (IS_VALLEYVIEW(dev)) {
14655                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14656                 dev_priv->display.get_initial_plane_config =
14657                         i9xx_get_initial_plane_config;
14658                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14659                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14660                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14661                 dev_priv->display.update_primary_plane =
14662                         i9xx_update_primary_plane;
14663         } else {
14664                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14665                 dev_priv->display.get_initial_plane_config =
14666                         i9xx_get_initial_plane_config;
14667                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14668                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14669                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14670                 dev_priv->display.update_primary_plane =
14671                         i9xx_update_primary_plane;
14672         }
14673
14674         /* Returns the core display clock speed */
14675         if (IS_SKYLAKE(dev))
14676                 dev_priv->display.get_display_clock_speed =
14677                         skylake_get_display_clock_speed;
14678         else if (IS_BROXTON(dev))
14679                 dev_priv->display.get_display_clock_speed =
14680                         broxton_get_display_clock_speed;
14681         else if (IS_BROADWELL(dev))
14682                 dev_priv->display.get_display_clock_speed =
14683                         broadwell_get_display_clock_speed;
14684         else if (IS_HASWELL(dev))
14685                 dev_priv->display.get_display_clock_speed =
14686                         haswell_get_display_clock_speed;
14687         else if (IS_VALLEYVIEW(dev))
14688                 dev_priv->display.get_display_clock_speed =
14689                         valleyview_get_display_clock_speed;
14690         else if (IS_GEN5(dev))
14691                 dev_priv->display.get_display_clock_speed =
14692                         ilk_get_display_clock_speed;
14693         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14694                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14695                 dev_priv->display.get_display_clock_speed =
14696                         i945_get_display_clock_speed;
14697         else if (IS_GM45(dev))
14698                 dev_priv->display.get_display_clock_speed =
14699                         gm45_get_display_clock_speed;
14700         else if (IS_CRESTLINE(dev))
14701                 dev_priv->display.get_display_clock_speed =
14702                         i965gm_get_display_clock_speed;
14703         else if (IS_PINEVIEW(dev))
14704                 dev_priv->display.get_display_clock_speed =
14705                         pnv_get_display_clock_speed;
14706         else if (IS_G33(dev) || IS_G4X(dev))
14707                 dev_priv->display.get_display_clock_speed =
14708                         g33_get_display_clock_speed;
14709         else if (IS_I915G(dev))
14710                 dev_priv->display.get_display_clock_speed =
14711                         i915_get_display_clock_speed;
14712         else if (IS_I945GM(dev) || IS_845G(dev))
14713                 dev_priv->display.get_display_clock_speed =
14714                         i9xx_misc_get_display_clock_speed;
14715         else if (IS_PINEVIEW(dev))
14716                 dev_priv->display.get_display_clock_speed =
14717                         pnv_get_display_clock_speed;
14718         else if (IS_I915GM(dev))
14719                 dev_priv->display.get_display_clock_speed =
14720                         i915gm_get_display_clock_speed;
14721         else if (IS_I865G(dev))
14722                 dev_priv->display.get_display_clock_speed =
14723                         i865_get_display_clock_speed;
14724         else if (IS_I85X(dev))
14725                 dev_priv->display.get_display_clock_speed =
14726                         i85x_get_display_clock_speed;
14727         else { /* 830 */
14728                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14729                 dev_priv->display.get_display_clock_speed =
14730                         i830_get_display_clock_speed;
14731         }
14732
14733         if (IS_GEN5(dev)) {
14734                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14735         } else if (IS_GEN6(dev)) {
14736                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14737         } else if (IS_IVYBRIDGE(dev)) {
14738                 /* FIXME: detect B0+ stepping and use auto training */
14739                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14740         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14741                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14742                 if (IS_BROADWELL(dev)) {
14743                         dev_priv->display.modeset_commit_cdclk =
14744                                 broadwell_modeset_commit_cdclk;
14745                         dev_priv->display.modeset_calc_cdclk =
14746                                 broadwell_modeset_calc_cdclk;
14747                 }
14748         } else if (IS_VALLEYVIEW(dev)) {
14749                 dev_priv->display.modeset_commit_cdclk =
14750                         valleyview_modeset_commit_cdclk;
14751                 dev_priv->display.modeset_calc_cdclk =
14752                         valleyview_modeset_calc_cdclk;
14753         } else if (IS_BROXTON(dev)) {
14754                 dev_priv->display.modeset_commit_cdclk =
14755                         broxton_modeset_commit_cdclk;
14756                 dev_priv->display.modeset_calc_cdclk =
14757                         broxton_modeset_calc_cdclk;
14758         }
14759
14760         switch (INTEL_INFO(dev)->gen) {
14761         case 2:
14762                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14763                 break;
14764
14765         case 3:
14766                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14767                 break;
14768
14769         case 4:
14770         case 5:
14771                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14772                 break;
14773
14774         case 6:
14775                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14776                 break;
14777         case 7:
14778         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14779                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14780                 break;
14781         case 9:
14782                 /* Drop through - unsupported since execlist only. */
14783         default:
14784                 /* Default just returns -ENODEV to indicate unsupported */
14785                 dev_priv->display.queue_flip = intel_default_queue_flip;
14786         }
14787
14788         intel_panel_init_backlight_funcs(dev);
14789
14790         mutex_init(&dev_priv->pps_mutex);
14791 }
14792
14793 /*
14794  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14795  * resume, or other times.  This quirk makes sure that's the case for
14796  * affected systems.
14797  */
14798 static void quirk_pipea_force(struct drm_device *dev)
14799 {
14800         struct drm_i915_private *dev_priv = dev->dev_private;
14801
14802         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14803         DRM_INFO("applying pipe a force quirk\n");
14804 }
14805
14806 static void quirk_pipeb_force(struct drm_device *dev)
14807 {
14808         struct drm_i915_private *dev_priv = dev->dev_private;
14809
14810         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14811         DRM_INFO("applying pipe b force quirk\n");
14812 }
14813
14814 /*
14815  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14816  */
14817 static void quirk_ssc_force_disable(struct drm_device *dev)
14818 {
14819         struct drm_i915_private *dev_priv = dev->dev_private;
14820         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14821         DRM_INFO("applying lvds SSC disable quirk\n");
14822 }
14823
14824 /*
14825  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14826  * brightness value
14827  */
14828 static void quirk_invert_brightness(struct drm_device *dev)
14829 {
14830         struct drm_i915_private *dev_priv = dev->dev_private;
14831         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14832         DRM_INFO("applying inverted panel brightness quirk\n");
14833 }
14834
14835 /* Some VBT's incorrectly indicate no backlight is present */
14836 static void quirk_backlight_present(struct drm_device *dev)
14837 {
14838         struct drm_i915_private *dev_priv = dev->dev_private;
14839         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14840         DRM_INFO("applying backlight present quirk\n");
14841 }
14842
14843 struct intel_quirk {
14844         int device;
14845         int subsystem_vendor;
14846         int subsystem_device;
14847         void (*hook)(struct drm_device *dev);
14848 };
14849
14850 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14851 struct intel_dmi_quirk {
14852         void (*hook)(struct drm_device *dev);
14853         const struct dmi_system_id (*dmi_id_list)[];
14854 };
14855
14856 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14857 {
14858         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14859         return 1;
14860 }
14861
14862 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14863         {
14864                 .dmi_id_list = &(const struct dmi_system_id[]) {
14865                         {
14866                                 .callback = intel_dmi_reverse_brightness,
14867                                 .ident = "NCR Corporation",
14868                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14869                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14870                                 },
14871                         },
14872                         { }  /* terminating entry */
14873                 },
14874                 .hook = quirk_invert_brightness,
14875         },
14876 };
14877
14878 static struct intel_quirk intel_quirks[] = {
14879         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14880         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14881
14882         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14883         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14884
14885         /* 830 needs to leave pipe A & dpll A up */
14886         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14887
14888         /* 830 needs to leave pipe B & dpll B up */
14889         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14890
14891         /* Lenovo U160 cannot use SSC on LVDS */
14892         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14893
14894         /* Sony Vaio Y cannot use SSC on LVDS */
14895         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14896
14897         /* Acer Aspire 5734Z must invert backlight brightness */
14898         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14899
14900         /* Acer/eMachines G725 */
14901         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14902
14903         /* Acer/eMachines e725 */
14904         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14905
14906         /* Acer/Packard Bell NCL20 */
14907         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14908
14909         /* Acer Aspire 4736Z */
14910         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14911
14912         /* Acer Aspire 5336 */
14913         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14914
14915         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14916         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14917
14918         /* Acer C720 Chromebook (Core i3 4005U) */
14919         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14920
14921         /* Apple Macbook 2,1 (Core 2 T7400) */
14922         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14923
14924         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14925         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14926
14927         /* HP Chromebook 14 (Celeron 2955U) */
14928         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14929
14930         /* Dell Chromebook 11 */
14931         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14932 };
14933
14934 static void intel_init_quirks(struct drm_device *dev)
14935 {
14936         struct pci_dev *d = dev->pdev;
14937         int i;
14938
14939         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14940                 struct intel_quirk *q = &intel_quirks[i];
14941
14942                 if (d->device == q->device &&
14943                     (d->subsystem_vendor == q->subsystem_vendor ||
14944                      q->subsystem_vendor == PCI_ANY_ID) &&
14945                     (d->subsystem_device == q->subsystem_device ||
14946                      q->subsystem_device == PCI_ANY_ID))
14947                         q->hook(dev);
14948         }
14949         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14950                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14951                         intel_dmi_quirks[i].hook(dev);
14952         }
14953 }
14954
14955 /* Disable the VGA plane that we never use */
14956 static void i915_disable_vga(struct drm_device *dev)
14957 {
14958         struct drm_i915_private *dev_priv = dev->dev_private;
14959         u8 sr1;
14960         u32 vga_reg = i915_vgacntrl_reg(dev);
14961
14962         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14963         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14964         outb(SR01, VGA_SR_INDEX);
14965         sr1 = inb(VGA_SR_DATA);
14966         outb(sr1 | 1<<5, VGA_SR_DATA);
14967         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14968         udelay(300);
14969
14970         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14971         POSTING_READ(vga_reg);
14972 }
14973
14974 void intel_modeset_init_hw(struct drm_device *dev)
14975 {
14976         intel_update_cdclk(dev);
14977         intel_prepare_ddi(dev);
14978         intel_init_clock_gating(dev);
14979         intel_enable_gt_powersave(dev);
14980 }
14981
14982 void intel_modeset_init(struct drm_device *dev)
14983 {
14984         struct drm_i915_private *dev_priv = dev->dev_private;
14985         int sprite, ret;
14986         enum pipe pipe;
14987         struct intel_crtc *crtc;
14988
14989         drm_mode_config_init(dev);
14990
14991         dev->mode_config.min_width = 0;
14992         dev->mode_config.min_height = 0;
14993
14994         dev->mode_config.preferred_depth = 24;
14995         dev->mode_config.prefer_shadow = 1;
14996
14997         dev->mode_config.allow_fb_modifiers = true;
14998
14999         dev->mode_config.funcs = &intel_mode_funcs;
15000
15001         intel_init_quirks(dev);
15002
15003         intel_init_pm(dev);
15004
15005         if (INTEL_INFO(dev)->num_pipes == 0)
15006                 return;
15007
15008         intel_init_display(dev);
15009         intel_init_audio(dev);
15010
15011         if (IS_GEN2(dev)) {
15012                 dev->mode_config.max_width = 2048;
15013                 dev->mode_config.max_height = 2048;
15014         } else if (IS_GEN3(dev)) {
15015                 dev->mode_config.max_width = 4096;
15016                 dev->mode_config.max_height = 4096;
15017         } else {
15018                 dev->mode_config.max_width = 8192;
15019                 dev->mode_config.max_height = 8192;
15020         }
15021
15022         if (IS_845G(dev) || IS_I865G(dev)) {
15023                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15024                 dev->mode_config.cursor_height = 1023;
15025         } else if (IS_GEN2(dev)) {
15026                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15027                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15028         } else {
15029                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15030                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15031         }
15032
15033         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15034
15035         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15036                       INTEL_INFO(dev)->num_pipes,
15037                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15038
15039         for_each_pipe(dev_priv, pipe) {
15040                 intel_crtc_init(dev, pipe);
15041                 for_each_sprite(dev_priv, pipe, sprite) {
15042                         ret = intel_plane_init(dev, pipe, sprite);
15043                         if (ret)
15044                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15045                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15046                 }
15047         }
15048
15049         intel_init_dpio(dev);
15050
15051         intel_shared_dpll_init(dev);
15052
15053         /* Just disable it once at startup */
15054         i915_disable_vga(dev);
15055         intel_setup_outputs(dev);
15056
15057         /* Just in case the BIOS is doing something questionable. */
15058         intel_fbc_disable(dev);
15059
15060         drm_modeset_lock_all(dev);
15061         intel_modeset_setup_hw_state(dev, false);
15062         drm_modeset_unlock_all(dev);
15063
15064         for_each_intel_crtc(dev, crtc) {
15065                 if (!crtc->active)
15066                         continue;
15067
15068                 /*
15069                  * Note that reserving the BIOS fb up front prevents us
15070                  * from stuffing other stolen allocations like the ring
15071                  * on top.  This prevents some ugliness at boot time, and
15072                  * can even allow for smooth boot transitions if the BIOS
15073                  * fb is large enough for the active pipe configuration.
15074                  */
15075                 if (dev_priv->display.get_initial_plane_config) {
15076                         dev_priv->display.get_initial_plane_config(crtc,
15077                                                            &crtc->plane_config);
15078                         /*
15079                          * If the fb is shared between multiple heads, we'll
15080                          * just get the first one.
15081                          */
15082                         intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15083                 }
15084         }
15085 }
15086
15087 static void intel_enable_pipe_a(struct drm_device *dev)
15088 {
15089         struct intel_connector *connector;
15090         struct drm_connector *crt = NULL;
15091         struct intel_load_detect_pipe load_detect_temp;
15092         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15093
15094         /* We can't just switch on the pipe A, we need to set things up with a
15095          * proper mode and output configuration. As a gross hack, enable pipe A
15096          * by enabling the load detect pipe once. */
15097         for_each_intel_connector(dev, connector) {
15098                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15099                         crt = &connector->base;
15100                         break;
15101                 }
15102         }
15103
15104         if (!crt)
15105                 return;
15106
15107         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15108                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15109 }
15110
15111 static bool
15112 intel_check_plane_mapping(struct intel_crtc *crtc)
15113 {
15114         struct drm_device *dev = crtc->base.dev;
15115         struct drm_i915_private *dev_priv = dev->dev_private;
15116         u32 reg, val;
15117
15118         if (INTEL_INFO(dev)->num_pipes == 1)
15119                 return true;
15120
15121         reg = DSPCNTR(!crtc->plane);
15122         val = I915_READ(reg);
15123
15124         if ((val & DISPLAY_PLANE_ENABLE) &&
15125             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15126                 return false;
15127
15128         return true;
15129 }
15130
15131 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15132 {
15133         struct drm_device *dev = crtc->base.dev;
15134         struct drm_i915_private *dev_priv = dev->dev_private;
15135         struct intel_encoder *encoder;
15136         u32 reg;
15137         bool enable;
15138
15139         /* Clear any frame start delays used for debugging left by the BIOS */
15140         reg = PIPECONF(crtc->config->cpu_transcoder);
15141         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15142
15143         /* restore vblank interrupts to correct state */
15144         drm_crtc_vblank_reset(&crtc->base);
15145         if (crtc->active) {
15146                 update_scanline_offset(crtc);
15147                 drm_crtc_vblank_on(&crtc->base);
15148         }
15149
15150         /* We need to sanitize the plane -> pipe mapping first because this will
15151          * disable the crtc (and hence change the state) if it is wrong. Note
15152          * that gen4+ has a fixed plane -> pipe mapping.  */
15153         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15154                 bool plane;
15155
15156                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15157                               crtc->base.base.id);
15158
15159                 /* Pipe has the wrong plane attached and the plane is active.
15160                  * Temporarily change the plane mapping and disable everything
15161                  * ...  */
15162                 plane = crtc->plane;
15163                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15164                 crtc->plane = !plane;
15165                 intel_crtc_disable_noatomic(&crtc->base);
15166                 crtc->plane = plane;
15167         }
15168
15169         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15170             crtc->pipe == PIPE_A && !crtc->active) {
15171                 /* BIOS forgot to enable pipe A, this mostly happens after
15172                  * resume. Force-enable the pipe to fix this, the update_dpms
15173                  * call below we restore the pipe to the right state, but leave
15174                  * the required bits on. */
15175                 intel_enable_pipe_a(dev);
15176         }
15177
15178         /* Adjust the state of the output pipe according to whether we
15179          * have active connectors/encoders. */
15180         enable = false;
15181         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15182                 enable |= encoder->connectors_active;
15183
15184         if (!enable)
15185                 intel_crtc_disable_noatomic(&crtc->base);
15186
15187         if (crtc->active != crtc->base.state->active) {
15188
15189                 /* This can happen either due to bugs in the get_hw_state
15190                  * functions or because of calls to intel_crtc_disable_noatomic,
15191                  * or because the pipe is force-enabled due to the
15192                  * pipe A quirk. */
15193                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15194                               crtc->base.base.id,
15195                               crtc->base.state->enable ? "enabled" : "disabled",
15196                               crtc->active ? "enabled" : "disabled");
15197
15198                 crtc->base.state->enable = crtc->active;
15199                 crtc->base.state->active = crtc->active;
15200                 crtc->base.enabled = crtc->active;
15201
15202                 /* Because we only establish the connector -> encoder ->
15203                  * crtc links if something is active, this means the
15204                  * crtc is now deactivated. Break the links. connector
15205                  * -> encoder links are only establish when things are
15206                  *  actually up, hence no need to break them. */
15207                 WARN_ON(crtc->active);
15208
15209                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15210                         WARN_ON(encoder->connectors_active);
15211                         encoder->base.crtc = NULL;
15212                 }
15213         }
15214
15215         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15216                 /*
15217                  * We start out with underrun reporting disabled to avoid races.
15218                  * For correct bookkeeping mark this on active crtcs.
15219                  *
15220                  * Also on gmch platforms we dont have any hardware bits to
15221                  * disable the underrun reporting. Which means we need to start
15222                  * out with underrun reporting disabled also on inactive pipes,
15223                  * since otherwise we'll complain about the garbage we read when
15224                  * e.g. coming up after runtime pm.
15225                  *
15226                  * No protection against concurrent access is required - at
15227                  * worst a fifo underrun happens which also sets this to false.
15228                  */
15229                 crtc->cpu_fifo_underrun_disabled = true;
15230                 crtc->pch_fifo_underrun_disabled = true;
15231         }
15232 }
15233
15234 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15235 {
15236         struct intel_connector *connector;
15237         struct drm_device *dev = encoder->base.dev;
15238
15239         /* We need to check both for a crtc link (meaning that the
15240          * encoder is active and trying to read from a pipe) and the
15241          * pipe itself being active. */
15242         bool has_active_crtc = encoder->base.crtc &&
15243                 to_intel_crtc(encoder->base.crtc)->active;
15244
15245         if (encoder->connectors_active && !has_active_crtc) {
15246                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15247                               encoder->base.base.id,
15248                               encoder->base.name);
15249
15250                 /* Connector is active, but has no active pipe. This is
15251                  * fallout from our resume register restoring. Disable
15252                  * the encoder manually again. */
15253                 if (encoder->base.crtc) {
15254                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15255                                       encoder->base.base.id,
15256                                       encoder->base.name);
15257                         encoder->disable(encoder);
15258                         if (encoder->post_disable)
15259                                 encoder->post_disable(encoder);
15260                 }
15261                 encoder->base.crtc = NULL;
15262                 encoder->connectors_active = false;
15263
15264                 /* Inconsistent output/port/pipe state happens presumably due to
15265                  * a bug in one of the get_hw_state functions. Or someplace else
15266                  * in our code, like the register restore mess on resume. Clamp
15267                  * things to off as a safer default. */
15268                 for_each_intel_connector(dev, connector) {
15269                         if (connector->encoder != encoder)
15270                                 continue;
15271                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15272                         connector->base.encoder = NULL;
15273                 }
15274         }
15275         /* Enabled encoders without active connectors will be fixed in
15276          * the crtc fixup. */
15277 }
15278
15279 void i915_redisable_vga_power_on(struct drm_device *dev)
15280 {
15281         struct drm_i915_private *dev_priv = dev->dev_private;
15282         u32 vga_reg = i915_vgacntrl_reg(dev);
15283
15284         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15285                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15286                 i915_disable_vga(dev);
15287         }
15288 }
15289
15290 void i915_redisable_vga(struct drm_device *dev)
15291 {
15292         struct drm_i915_private *dev_priv = dev->dev_private;
15293
15294         /* This function can be called both from intel_modeset_setup_hw_state or
15295          * at a very early point in our resume sequence, where the power well
15296          * structures are not yet restored. Since this function is at a very
15297          * paranoid "someone might have enabled VGA while we were not looking"
15298          * level, just check if the power well is enabled instead of trying to
15299          * follow the "don't touch the power well if we don't need it" policy
15300          * the rest of the driver uses. */
15301         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15302                 return;
15303
15304         i915_redisable_vga_power_on(dev);
15305 }
15306
15307 static bool primary_get_hw_state(struct intel_crtc *crtc)
15308 {
15309         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15310
15311         return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15312 }
15313
15314 static void readout_plane_state(struct intel_crtc *crtc,
15315                                 struct intel_crtc_state *crtc_state)
15316 {
15317         struct intel_plane *p;
15318         struct drm_plane_state *drm_plane_state;
15319         bool active = crtc_state->base.active;
15320
15321         if (active) {
15322                 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15323
15324                 /* apply to previous sw state too */
15325                 to_intel_crtc_state(crtc->base.state)->quirks |=
15326                         PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15327         }
15328
15329         for_each_intel_plane(crtc->base.dev, p) {
15330                 bool visible = active;
15331
15332                 if (crtc->pipe != p->pipe)
15333                         continue;
15334
15335                 drm_plane_state = p->base.state;
15336                 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15337                         visible = primary_get_hw_state(crtc);
15338                         to_intel_plane_state(drm_plane_state)->visible = visible;
15339                 } else {
15340                         /*
15341                          * unknown state, assume it's off to force a transition
15342                          * to on when calculating state changes.
15343                          */
15344                         to_intel_plane_state(drm_plane_state)->visible = false;
15345                 }
15346
15347                 if (visible) {
15348                         crtc_state->base.plane_mask |=
15349                                 1 << drm_plane_index(&p->base);
15350                 } else if (crtc_state->base.state) {
15351                         /* Make this unconditional for atomic hw readout. */
15352                         crtc_state->base.plane_mask &=
15353                                 ~(1 << drm_plane_index(&p->base));
15354                 }
15355         }
15356 }
15357
15358 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15359 {
15360         struct drm_i915_private *dev_priv = dev->dev_private;
15361         enum pipe pipe;
15362         struct intel_crtc *crtc;
15363         struct intel_encoder *encoder;
15364         struct intel_connector *connector;
15365         int i;
15366
15367         for_each_intel_crtc(dev, crtc) {
15368                 memset(crtc->config, 0, sizeof(*crtc->config));
15369                 crtc->config->base.crtc = &crtc->base;
15370
15371                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15372
15373                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15374                                                                  crtc->config);
15375
15376                 crtc->base.state->enable = crtc->active;
15377                 crtc->base.state->active = crtc->active;
15378                 crtc->base.enabled = crtc->active;
15379                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15380
15381                 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15382
15383                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15384                               crtc->base.base.id,
15385                               crtc->active ? "enabled" : "disabled");
15386         }
15387
15388         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15389                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15390
15391                 pll->on = pll->get_hw_state(dev_priv, pll,
15392                                             &pll->config.hw_state);
15393                 pll->active = 0;
15394                 pll->config.crtc_mask = 0;
15395                 for_each_intel_crtc(dev, crtc) {
15396                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15397                                 pll->active++;
15398                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15399                         }
15400                 }
15401
15402                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15403                               pll->name, pll->config.crtc_mask, pll->on);
15404
15405                 if (pll->config.crtc_mask)
15406                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15407         }
15408
15409         for_each_intel_encoder(dev, encoder) {
15410                 pipe = 0;
15411
15412                 if (encoder->get_hw_state(encoder, &pipe)) {
15413                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15414                         encoder->base.crtc = &crtc->base;
15415                         encoder->get_config(encoder, crtc->config);
15416                 } else {
15417                         encoder->base.crtc = NULL;
15418                 }
15419
15420                 encoder->connectors_active = false;
15421                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15422                               encoder->base.base.id,
15423                               encoder->base.name,
15424                               encoder->base.crtc ? "enabled" : "disabled",
15425                               pipe_name(pipe));
15426         }
15427
15428         for_each_intel_connector(dev, connector) {
15429                 if (connector->get_hw_state(connector)) {
15430                         connector->base.dpms = DRM_MODE_DPMS_ON;
15431                         connector->encoder->connectors_active = true;
15432                         connector->base.encoder = &connector->encoder->base;
15433                 } else {
15434                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15435                         connector->base.encoder = NULL;
15436                 }
15437                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15438                               connector->base.base.id,
15439                               connector->base.name,
15440                               connector->base.encoder ? "enabled" : "disabled");
15441         }
15442 }
15443
15444 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15445  * and i915 state tracking structures. */
15446 void intel_modeset_setup_hw_state(struct drm_device *dev,
15447                                   bool force_restore)
15448 {
15449         struct drm_i915_private *dev_priv = dev->dev_private;
15450         enum pipe pipe;
15451         struct intel_crtc *crtc;
15452         struct intel_encoder *encoder;
15453         int i;
15454
15455         intel_modeset_readout_hw_state(dev);
15456
15457         /*
15458          * Now that we have the config, copy it to each CRTC struct
15459          * Note that this could go away if we move to using crtc_config
15460          * checking everywhere.
15461          */
15462         for_each_intel_crtc(dev, crtc) {
15463                 if (crtc->active && i915.fastboot) {
15464                         intel_mode_from_pipe_config(&crtc->base.mode,
15465                                                     crtc->config);
15466                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15467                                       crtc->base.base.id);
15468                         drm_mode_debug_printmodeline(&crtc->base.mode);
15469                 }
15470         }
15471
15472         /* HW state is read out, now we need to sanitize this mess. */
15473         for_each_intel_encoder(dev, encoder) {
15474                 intel_sanitize_encoder(encoder);
15475         }
15476
15477         for_each_pipe(dev_priv, pipe) {
15478                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15479                 intel_sanitize_crtc(crtc);
15480                 intel_dump_pipe_config(crtc, crtc->config,
15481                                        "[setup_hw_state]");
15482         }
15483
15484         intel_modeset_update_connector_atomic_state(dev);
15485
15486         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15487                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15488
15489                 if (!pll->on || pll->active)
15490                         continue;
15491
15492                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15493
15494                 pll->disable(dev_priv, pll);
15495                 pll->on = false;
15496         }
15497
15498         if (IS_VALLEYVIEW(dev))
15499                 vlv_wm_get_hw_state(dev);
15500         else if (IS_GEN9(dev))
15501                 skl_wm_get_hw_state(dev);
15502         else if (HAS_PCH_SPLIT(dev))
15503                 ilk_wm_get_hw_state(dev);
15504
15505         if (force_restore) {
15506                 i915_redisable_vga(dev);
15507
15508                 /*
15509                  * We need to use raw interfaces for restoring state to avoid
15510                  * checking (bogus) intermediate states.
15511                  */
15512                 for_each_pipe(dev_priv, pipe) {
15513                         struct drm_crtc *crtc =
15514                                 dev_priv->pipe_to_crtc_mapping[pipe];
15515
15516                         intel_crtc_restore_mode(crtc);
15517                 }
15518         } else {
15519                 intel_modeset_update_staged_output_state(dev);
15520         }
15521
15522         intel_modeset_check_state(dev);
15523 }
15524
15525 void intel_modeset_gem_init(struct drm_device *dev)
15526 {
15527         struct drm_i915_private *dev_priv = dev->dev_private;
15528         struct drm_crtc *c;
15529         struct drm_i915_gem_object *obj;
15530         int ret;
15531
15532         mutex_lock(&dev->struct_mutex);
15533         intel_init_gt_powersave(dev);
15534         mutex_unlock(&dev->struct_mutex);
15535
15536         /*
15537          * There may be no VBT; and if the BIOS enabled SSC we can
15538          * just keep using it to avoid unnecessary flicker.  Whereas if the
15539          * BIOS isn't using it, don't assume it will work even if the VBT
15540          * indicates as much.
15541          */
15542         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15543                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15544                                                 DREF_SSC1_ENABLE);
15545
15546         intel_modeset_init_hw(dev);
15547
15548         intel_setup_overlay(dev);
15549
15550         /*
15551          * Make sure any fbs we allocated at startup are properly
15552          * pinned & fenced.  When we do the allocation it's too early
15553          * for this.
15554          */
15555         for_each_crtc(dev, c) {
15556                 obj = intel_fb_obj(c->primary->fb);
15557                 if (obj == NULL)
15558                         continue;
15559
15560                 mutex_lock(&dev->struct_mutex);
15561                 ret = intel_pin_and_fence_fb_obj(c->primary,
15562                                                  c->primary->fb,
15563                                                  c->primary->state,
15564                                                  NULL, NULL);
15565                 mutex_unlock(&dev->struct_mutex);
15566                 if (ret) {
15567                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15568                                   to_intel_crtc(c)->pipe);
15569                         drm_framebuffer_unreference(c->primary->fb);
15570                         c->primary->fb = NULL;
15571                         c->primary->crtc = c->primary->state->crtc = NULL;
15572                         update_state_fb(c->primary);
15573                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15574                 }
15575         }
15576
15577         intel_backlight_register(dev);
15578 }
15579
15580 void intel_connector_unregister(struct intel_connector *intel_connector)
15581 {
15582         struct drm_connector *connector = &intel_connector->base;
15583
15584         intel_panel_destroy_backlight(connector);
15585         drm_connector_unregister(connector);
15586 }
15587
15588 void intel_modeset_cleanup(struct drm_device *dev)
15589 {
15590         struct drm_i915_private *dev_priv = dev->dev_private;
15591         struct drm_connector *connector;
15592
15593         intel_disable_gt_powersave(dev);
15594
15595         intel_backlight_unregister(dev);
15596
15597         /*
15598          * Interrupts and polling as the first thing to avoid creating havoc.
15599          * Too much stuff here (turning of connectors, ...) would
15600          * experience fancy races otherwise.
15601          */
15602         intel_irq_uninstall(dev_priv);
15603
15604         /*
15605          * Due to the hpd irq storm handling the hotplug work can re-arm the
15606          * poll handlers. Hence disable polling after hpd handling is shut down.
15607          */
15608         drm_kms_helper_poll_fini(dev);
15609
15610         mutex_lock(&dev->struct_mutex);
15611
15612         intel_unregister_dsm_handler();
15613
15614         intel_fbc_disable(dev);
15615
15616         mutex_unlock(&dev->struct_mutex);
15617
15618         /* flush any delayed tasks or pending work */
15619         flush_scheduled_work();
15620
15621         /* destroy the backlight and sysfs files before encoders/connectors */
15622         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15623                 struct intel_connector *intel_connector;
15624
15625                 intel_connector = to_intel_connector(connector);
15626                 intel_connector->unregister(intel_connector);
15627         }
15628
15629         drm_mode_config_cleanup(dev);
15630
15631         intel_cleanup_overlay(dev);
15632
15633         mutex_lock(&dev->struct_mutex);
15634         intel_cleanup_gt_powersave(dev);
15635         mutex_unlock(&dev->struct_mutex);
15636 }
15637
15638 /*
15639  * Return which encoder is currently attached for connector.
15640  */
15641 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15642 {
15643         return &intel_attached_encoder(connector)->base;
15644 }
15645
15646 void intel_connector_attach_encoder(struct intel_connector *connector,
15647                                     struct intel_encoder *encoder)
15648 {
15649         connector->encoder = encoder;
15650         drm_mode_connector_attach_encoder(&connector->base,
15651                                           &encoder->base);
15652 }
15653
15654 /*
15655  * set vga decode state - true == enable VGA decode
15656  */
15657 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15658 {
15659         struct drm_i915_private *dev_priv = dev->dev_private;
15660         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15661         u16 gmch_ctrl;
15662
15663         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15664                 DRM_ERROR("failed to read control word\n");
15665                 return -EIO;
15666         }
15667
15668         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15669                 return 0;
15670
15671         if (state)
15672                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15673         else
15674                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15675
15676         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15677                 DRM_ERROR("failed to write control word\n");
15678                 return -EIO;
15679         }
15680
15681         return 0;
15682 }
15683
15684 struct intel_display_error_state {
15685
15686         u32 power_well_driver;
15687
15688         int num_transcoders;
15689
15690         struct intel_cursor_error_state {
15691                 u32 control;
15692                 u32 position;
15693                 u32 base;
15694                 u32 size;
15695         } cursor[I915_MAX_PIPES];
15696
15697         struct intel_pipe_error_state {
15698                 bool power_domain_on;
15699                 u32 source;
15700                 u32 stat;
15701         } pipe[I915_MAX_PIPES];
15702
15703         struct intel_plane_error_state {
15704                 u32 control;
15705                 u32 stride;
15706                 u32 size;
15707                 u32 pos;
15708                 u32 addr;
15709                 u32 surface;
15710                 u32 tile_offset;
15711         } plane[I915_MAX_PIPES];
15712
15713         struct intel_transcoder_error_state {
15714                 bool power_domain_on;
15715                 enum transcoder cpu_transcoder;
15716
15717                 u32 conf;
15718
15719                 u32 htotal;
15720                 u32 hblank;
15721                 u32 hsync;
15722                 u32 vtotal;
15723                 u32 vblank;
15724                 u32 vsync;
15725         } transcoder[4];
15726 };
15727
15728 struct intel_display_error_state *
15729 intel_display_capture_error_state(struct drm_device *dev)
15730 {
15731         struct drm_i915_private *dev_priv = dev->dev_private;
15732         struct intel_display_error_state *error;
15733         int transcoders[] = {
15734                 TRANSCODER_A,
15735                 TRANSCODER_B,
15736                 TRANSCODER_C,
15737                 TRANSCODER_EDP,
15738         };
15739         int i;
15740
15741         if (INTEL_INFO(dev)->num_pipes == 0)
15742                 return NULL;
15743
15744         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15745         if (error == NULL)
15746                 return NULL;
15747
15748         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15749                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15750
15751         for_each_pipe(dev_priv, i) {
15752                 error->pipe[i].power_domain_on =
15753                         __intel_display_power_is_enabled(dev_priv,
15754                                                          POWER_DOMAIN_PIPE(i));
15755                 if (!error->pipe[i].power_domain_on)
15756                         continue;
15757
15758                 error->cursor[i].control = I915_READ(CURCNTR(i));
15759                 error->cursor[i].position = I915_READ(CURPOS(i));
15760                 error->cursor[i].base = I915_READ(CURBASE(i));
15761
15762                 error->plane[i].control = I915_READ(DSPCNTR(i));
15763                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15764                 if (INTEL_INFO(dev)->gen <= 3) {
15765                         error->plane[i].size = I915_READ(DSPSIZE(i));
15766                         error->plane[i].pos = I915_READ(DSPPOS(i));
15767                 }
15768                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15769                         error->plane[i].addr = I915_READ(DSPADDR(i));
15770                 if (INTEL_INFO(dev)->gen >= 4) {
15771                         error->plane[i].surface = I915_READ(DSPSURF(i));
15772                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15773                 }
15774
15775                 error->pipe[i].source = I915_READ(PIPESRC(i));
15776
15777                 if (HAS_GMCH_DISPLAY(dev))
15778                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15779         }
15780
15781         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15782         if (HAS_DDI(dev_priv->dev))
15783                 error->num_transcoders++; /* Account for eDP. */
15784
15785         for (i = 0; i < error->num_transcoders; i++) {
15786                 enum transcoder cpu_transcoder = transcoders[i];
15787
15788                 error->transcoder[i].power_domain_on =
15789                         __intel_display_power_is_enabled(dev_priv,
15790                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15791                 if (!error->transcoder[i].power_domain_on)
15792                         continue;
15793
15794                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15795
15796                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15797                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15798                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15799                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15800                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15801                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15802                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15803         }
15804
15805         return error;
15806 }
15807
15808 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15809
15810 void
15811 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15812                                 struct drm_device *dev,
15813                                 struct intel_display_error_state *error)
15814 {
15815         struct drm_i915_private *dev_priv = dev->dev_private;
15816         int i;
15817
15818         if (!error)
15819                 return;
15820
15821         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15822         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15823                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15824                            error->power_well_driver);
15825         for_each_pipe(dev_priv, i) {
15826                 err_printf(m, "Pipe [%d]:\n", i);
15827                 err_printf(m, "  Power: %s\n",
15828                            error->pipe[i].power_domain_on ? "on" : "off");
15829                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15830                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15831
15832                 err_printf(m, "Plane [%d]:\n", i);
15833                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15834                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15835                 if (INTEL_INFO(dev)->gen <= 3) {
15836                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15837                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15838                 }
15839                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15840                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15841                 if (INTEL_INFO(dev)->gen >= 4) {
15842                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15843                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15844                 }
15845
15846                 err_printf(m, "Cursor [%d]:\n", i);
15847                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15848                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15849                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15850         }
15851
15852         for (i = 0; i < error->num_transcoders; i++) {
15853                 err_printf(m, "CPU transcoder: %c\n",
15854                            transcoder_name(error->transcoder[i].cpu_transcoder));
15855                 err_printf(m, "  Power: %s\n",
15856                            error->transcoder[i].power_domain_on ? "on" : "off");
15857                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15858                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15859                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15860                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15861                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15862                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15863                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15864         }
15865 }
15866
15867 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15868 {
15869         struct intel_crtc *crtc;
15870
15871         for_each_intel_crtc(dev, crtc) {
15872                 struct intel_unpin_work *work;
15873
15874                 spin_lock_irq(&dev->event_lock);
15875
15876                 work = crtc->unpin_work;
15877
15878                 if (work && work->event &&
15879                     work->event->base.file_priv == file) {
15880                         kfree(work->event);
15881                         work->event = NULL;
15882                 }
15883
15884                 spin_unlock_irq(&dev->event_lock);
15885         }
15886 }