drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc,
  98                             const struct intel_crtc_config *pipe_config);
  99 static void chv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_config *pipe_config);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 412 {
 413         struct drm_device *dev = crtc->base.dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 /**
 424  * Returns whether any output on the specified pipe will have the specified
 425  * type after a staged modeset is complete, i.e., the same as
 426  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 427  * encoder->crtc.
 428  */
 429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 430 {
 431         struct drm_device *dev = crtc->base.dev;
 432         struct intel_encoder *encoder;
 433
 434         for_each_intel_encoder(dev, encoder)
 435                 if (encoder->new_crtc == crtc && encoder->type == type)
 436                         return true;
 437
 438         return false;
 439 }
 440
 441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 442                                                 int refclk)
 443 {
 444         struct drm_device *dev = crtc->base.dev;
 445         const intel_limit_t *limit;
 446
 447         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 448                 if (intel_is_dual_link_lvds(dev)) {
 449                         if (refclk == 100000)
 450                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 451                         else
 452                                 limit = &intel_limits_ironlake_dual_lvds;
 453                 } else {
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_single_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_single_lvds;
 458                 }
 459         } else
 460                 limit = &intel_limits_ironlake_dac;
 461
 462         return limit;
 463 }
 464
 465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 466 {
 467         struct drm_device *dev = crtc->base.dev;
 468         const intel_limit_t *limit;
 469
 470         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 471                 if (intel_is_dual_link_lvds(dev))
 472                         limit = &intel_limits_g4x_dual_channel_lvds;
 473                 else
 474                         limit = &intel_limits_g4x_single_channel_lvds;
 475         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 476                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 477                 limit = &intel_limits_g4x_hdmi;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 479                 limit = &intel_limits_g4x_sdvo;
 480         } else /* The option is for other outputs */
 481                 limit = &intel_limits_i9xx_sdvo;
 482
 483         return limit;
 484 }
 485
 486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 487 {
 488         struct drm_device *dev = crtc->base.dev;
 489         const intel_limit_t *limit;
 490
 491         if (HAS_PCH_SPLIT(dev))
 492                 limit = intel_ironlake_limit(crtc, refclk);
 493         else if (IS_G4X(dev)) {
 494                 limit = intel_g4x_limit(crtc);
 495         } else if (IS_PINEVIEW(dev)) {
 496                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 497                         limit = &intel_limits_pineview_lvds;
 498                 else
 499                         limit = &intel_limits_pineview_sdvo;
 500         } else if (IS_CHERRYVIEW(dev)) {
 501                 limit = &intel_limits_chv;
 502         } else if (IS_VALLEYVIEW(dev)) {
 503                 limit = &intel_limits_vlv;
 504         } else if (!IS_GEN2(dev)) {
 505                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 506                         limit = &intel_limits_i9xx_lvds;
 507                 else
 508                         limit = &intel_limits_i9xx_sdvo;
 509         } else {
 510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 511                         limit = &intel_limits_i8xx_lvds;
 512                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 513                         limit = &intel_limits_i8xx_dvo;
 514                 else
 515                         limit = &intel_limits_i8xx_dac;
 516         }
 517         return limit;
 518 }
 519
 520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 521 static void pineview_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = clock->m2 + 2;
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 532 {
 533         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 534 }
 535
 536 static void i9xx_clock(int refclk, intel_clock_t *clock)
 537 {
 538         clock->m = i9xx_dpll_compute_m(clock);
 539         clock->p = clock->p1 * clock->p2;
 540         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 541                 return;
 542         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 543         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 544 }
 545
 546 static void chv_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m1 * clock->m2;
 549         clock->p = clock->p1 * clock->p2;
 550         if (WARN_ON(clock->n == 0 || clock->p == 0))
 551                 return;
 552         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 553                         clock->n << 22);
 554         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 555 }
 556
 557 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 558 /**
 559  * Returns whether the given set of divisors are valid for a given refclk with
 560  * the given connectors.
 561  */
 562
 563 static bool intel_PLL_is_valid(struct drm_device *dev,
 564                                const intel_limit_t *limit,
 565                                const intel_clock_t *clock)
 566 {
 567         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 568                 INTELPllInvalid("n out of range\n");
 569         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 570                 INTELPllInvalid("p1 out of range\n");
 571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 572                 INTELPllInvalid("m2 out of range\n");
 573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 574                 INTELPllInvalid("m1 out of range\n");
 575
 576         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 577                 if (clock->m1 <= clock->m2)
 578                         INTELPllInvalid("m1 <= m2\n");
 579
 580         if (!IS_VALLEYVIEW(dev)) {
 581                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 582                         INTELPllInvalid("p out of range\n");
 583                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 584                         INTELPllInvalid("m out of range\n");
 585         }
 586
 587         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 588                 INTELPllInvalid("vco out of range\n");
 589         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 590          * connector, etc., rather than just a single range.
 591          */
 592         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 593                 INTELPllInvalid("dot out of range\n");
 594
 595         return true;
 596 }
 597
 598 static bool
 599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 600                     int target, int refclk, intel_clock_t *match_clock,
 601                     intel_clock_t *best_clock)
 602 {
 603         struct drm_device *dev = crtc->base.dev;
 604         intel_clock_t clock;
 605         int err = target;
 606
 607         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 608                 /*
 609                  * For LVDS just rely on its current settings for dual-channel.
 610                  * We haven't figured out how to reliably set up different
 611                  * single/dual channel state, if we even can.
 612                  */
 613                 if (intel_is_dual_link_lvds(dev))
 614                         clock.p2 = limit->p2.p2_fast;
 615                 else
 616                         clock.p2 = limit->p2.p2_slow;
 617         } else {
 618                 if (target < limit->p2.dot_limit)
 619                         clock.p2 = limit->p2.p2_slow;
 620                 else
 621                         clock.p2 = limit->p2.p2_fast;
 622         }
 623
 624         memset(best_clock, 0, sizeof(*best_clock));
 625
 626         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 627              clock.m1++) {
 628                 for (clock.m2 = limit->m2.min;
 629                      clock.m2 <= limit->m2.max; clock.m2++) {
 630                         if (clock.m2 >= clock.m1)
 631                                 break;
 632                         for (clock.n = limit->n.min;
 633                              clock.n <= limit->n.max; clock.n++) {
 634                                 for (clock.p1 = limit->p1.min;
 635                                         clock.p1 <= limit->p1.max; clock.p1++) {
 636                                         int this_err;
 637
 638                                         i9xx_clock(refclk, &clock);
 639                                         if (!intel_PLL_is_valid(dev, limit,
 640                                                                 &clock))
 641                                                 continue;
 642                                         if (match_clock &&
 643                                             clock.p != match_clock->p)
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err) {
 648                                                 *best_clock = clock;
 649                                                 err = this_err;
 650                                         }
 651                                 }
 652                         }
 653                 }
 654         }
 655
 656         return (err != target);
 657 }
 658
 659 static bool
 660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 661                    int target, int refclk, intel_clock_t *match_clock,
 662                    intel_clock_t *best_clock)
 663 {
 664         struct drm_device *dev = crtc->base.dev;
 665         intel_clock_t clock;
 666         int err = target;
 667
 668         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 /*
 670                  * For LVDS just rely on its current settings for dual-channel.
 671                  * We haven't figured out how to reliably set up different
 672                  * single/dual channel state, if we even can.
 673                  */
 674                 if (intel_is_dual_link_lvds(dev))
 675                         clock.p2 = limit->p2.p2_fast;
 676                 else
 677                         clock.p2 = limit->p2.p2_slow;
 678         } else {
 679                 if (target < limit->p2.dot_limit)
 680                         clock.p2 = limit->p2.p2_slow;
 681                 else
 682                         clock.p2 = limit->p2.p2_fast;
 683         }
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pineview_clock(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(dev, limit,
 699                                                                 &clock))
 700                                                 continue;
 701                                         if (match_clock &&
 702                                             clock.p != match_clock->p)
 703                                                 continue;
 704
 705                                         this_err = abs(clock.dot - target);
 706                                         if (this_err < err) {
 707                                                 *best_clock = clock;
 708                                                 err = this_err;
 709                                         }
 710                                 }
 711                         }
 712                 }
 713         }
 714
 715         return (err != target);
 716 }
 717
 718 static bool
 719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->base.dev;
 724         intel_clock_t clock;
 725         int max_n;
 726         bool found;
 727         /* approximately equals target * 0.00585 */
 728         int err_most = (target >> 8) + (target >> 9);
 729         found = false;
 730
 731         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 732                 if (intel_is_dual_link_lvds(dev))
 733                         clock.p2 = limit->p2.p2_fast;
 734                 else
 735                         clock.p2 = limit->p2.p2_slow;
 736         } else {
 737                 if (target < limit->p2.dot_limit)
 738                         clock.p2 = limit->p2.p2_slow;
 739                 else
 740                         clock.p2 = limit->p2.p2_fast;
 741         }
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744         max_n = limit->n.max;
 745         /* based on hardware requirement, prefer smaller n to precision */
 746         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 747                 /* based on hardware requirement, prefere larger m1,m2 */
 748                 for (clock.m1 = limit->m1.max;
 749                      clock.m1 >= limit->m1.min; clock.m1--) {
 750                         for (clock.m2 = limit->m2.max;
 751                              clock.m2 >= limit->m2.min; clock.m2--) {
 752                                 for (clock.p1 = limit->p1.max;
 753                                      clock.p1 >= limit->p1.min; clock.p1--) {
 754                                         int this_err;
 755
 756                                         i9xx_clock(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760
 761                                         this_err = abs(clock.dot - target);
 762                                         if (this_err < err_most) {
 763                                                 *best_clock = clock;
 764                                                 err_most = this_err;
 765                                                 max_n = clock.n;
 766                                                 found = true;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772         return found;
 773 }
 774
 775 static bool
 776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         intel_clock_t clock;
 782         unsigned int bestppm = 1000000;
 783         /* min update 19.2 MHz */
 784         int max_n = min(limit->n.max, refclk / 19200);
 785         bool found = false;
 786
 787         target *= 5; /* fast clock */
 788
 789         memset(best_clock, 0, sizeof(*best_clock));
 790
 791         /* based on hardware requirement, prefer smaller n to precision */
 792         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 793                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 794                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 795                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 796                                 clock.p = clock.p1 * clock.p2;
 797                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 798                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 799                                         unsigned int ppm, diff;
 800
 801                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 802                                                                      refclk * clock.m1);
 803
 804                                         vlv_clock(refclk, &clock);
 805
 806                                         if (!intel_PLL_is_valid(dev, limit,
 807                                                                 &clock))
 808                                                 continue;
 809
 810                                         diff = abs(clock.dot - target);
 811                                         ppm = div_u64(1000000ULL * diff, target);
 812
 813                                         if (ppm < 100 && clock.p > best_clock->p) {
 814                                                 bestppm = 0;
 815                                                 *best_clock = clock;
 816                                                 found = true;
 817                                         }
 818
 819                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 820                                                 bestppm = ppm;
 821                                                 *best_clock = clock;
 822                                                 found = true;
 823                                         }
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         return found;
 830 }
 831
 832 static bool
 833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 834                    int target, int refclk, intel_clock_t *match_clock,
 835                    intel_clock_t *best_clock)
 836 {
 837         struct drm_device *dev = crtc->base.dev;
 838         intel_clock_t clock;
 839         uint64_t m2;
 840         int found = false;
 841
 842         memset(best_clock, 0, sizeof(*best_clock));
 843
 844         /*
 845          * Based on hardware doc, the n always set to 1, and m1 always
 846          * set to 2.  If requires to support 200Mhz refclk, we need to
 847          * revisit this because n may not 1 anymore.
 848          */
 849         clock.n = 1, clock.m1 = 2;
 850         target *= 5;    /* fast clock */
 851
 852         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 853                 for (clock.p2 = limit->p2.p2_fast;
 854                                 clock.p2 >= limit->p2.p2_slow;
 855                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 856
 857                         clock.p = clock.p1 * clock.p2;
 858
 859                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 860                                         clock.n) << 22, refclk * clock.m1);
 861
 862                         if (m2 > INT_MAX/clock.m1)
 863                                 continue;
 864
 865                         clock.m2 = m2;
 866
 867                         chv_clock(refclk, &clock);
 868
 869                         if (!intel_PLL_is_valid(dev, limit, &clock))
 870                                 continue;
 871
 872                         /* based on hardware requirement, prefer bigger p
 873                          */
 874                         if (clock.p > best_clock->p) {
 875                                 *best_clock = clock;
 876                                 found = true;
 877                         }
 878                 }
 879         }
 880
 881         return found;
 882 }
 883
 884 bool intel_crtc_active(struct drm_crtc *crtc)
 885 {
 886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 887
 888         /* Be paranoid as we can arrive here with only partial
 889          * state retrieved from the hardware during setup.
 890          *
 891          * We can ditch the adjusted_mode.crtc_clock check as soon
 892          * as Haswell has gained clock readout/fastboot support.
 893          *
 894          * We can ditch the crtc->primary->fb check as soon as we can
 895          * properly reconstruct framebuffers.
 896          */
 897         return intel_crtc->active && crtc->primary->fb &&
 898                 intel_crtc->config.adjusted_mode.crtc_clock;
 899 }
 900
 901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 902                                              enum pipe pipe)
 903 {
 904         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 906
 907         return intel_crtc->config.cpu_transcoder;
 908 }
 909
 910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         u32 reg = PIPEDSL(pipe);
 914         u32 line1, line2;
 915         u32 line_mask;
 916
 917         if (IS_GEN2(dev))
 918                 line_mask = DSL_LINEMASK_GEN2;
 919         else
 920                 line_mask = DSL_LINEMASK_GEN3;
 921
 922         line1 = I915_READ(reg) & line_mask;
 923         mdelay(5);
 924         line2 = I915_READ(reg) & line_mask;
 925
 926         return line1 == line2;
 927 }
 928
 929 /*
 930  * intel_wait_for_pipe_off - wait for pipe to turn off
 931  * @crtc: crtc whose pipe to wait for
 932  *
 933  * After disabling a pipe, we can't wait for vblank in the usual way,
 934  * spinning on the vblank interrupt status bit, since we won't actually
 935  * see an interrupt when the pipe is disabled.
 936  *
 937  * On Gen4 and above:
 938  *   wait for the pipe register state bit to turn off
 939  *
 940  * Otherwise:
 941  *   wait for the display line value to settle (it usually
 942  *   ends up stopping at the start of the next frame).
 943  *
 944  */
 945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 946 {
 947         struct drm_device *dev = crtc->base.dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 950         enum pipe pipe = crtc->pipe;
 951
 952         if (INTEL_INFO(dev)->gen >= 4) {
 953                 int reg = PIPECONF(cpu_transcoder);
 954
 955                 /* Wait for the Pipe State to go off */
 956                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 957                              100))
 958                         WARN(1, "pipe_off wait timed out\n");
 959         } else {
 960                 /* Wait for the display line to settle */
 961                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 962                         WARN(1, "pipe_off wait timed out\n");
 963         }
 964 }
 965
 966 /*
 967  * ibx_digital_port_connected - is the specified port connected?
 968  * @dev_priv: i915 private structure
 969  * @port: the port to test
 970  *
 971  * Returns true if @port is connected, false otherwise.
 972  */
 973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 974                                 struct intel_digital_port *port)
 975 {
 976         u32 bit;
 977
 978         if (HAS_PCH_IBX(dev_priv->dev)) {
 979                 switch (port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         } else {
 993                 switch (port->port) {
 994                 case PORT_B:
 995                         bit = SDE_PORTB_HOTPLUG_CPT;
 996                         break;
 997                 case PORT_C:
 998                         bit = SDE_PORTC_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_D:
1001                         bit = SDE_PORTD_HOTPLUG_CPT;
1002                         break;
1003                 default:
1004                         return true;
1005                 }
1006         }
1007
1008         return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013         return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018                 enum pipe pipe, bool state)
1019 {
1020         int reg;
1021         u32 val;
1022         bool cur_state;
1023
1024         reg = DPLL(pipe);
1025         val = I915_READ(reg);
1026         cur_state = !!(val & DPLL_VCO_ENABLE);
1027         WARN(cur_state != state,
1028              "PLL state assertion failure (expected %s, current %s)\n",
1029              state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035         u32 val;
1036         bool cur_state;
1037
1038         mutex_lock(&dev_priv->dpio_lock);
1039         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040         mutex_unlock(&dev_priv->dpio_lock);
1041
1042         cur_state = val & DSI_PLL_VCO_EN;
1043         WARN(cur_state != state,
1044              "DSI PLL state assertion failure (expected %s, current %s)\n",
1045              state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055         if (crtc->config.shared_dpll < 0)
1056                 return NULL;
1057
1058         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063                         struct intel_shared_dpll *pll,
1064                         bool state)
1065 {
1066         bool cur_state;
1067         struct intel_dpll_hw_state hw_state;
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                            enum pipe pipe)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160         int pp_reg;
1161         u32 val;
1162         enum pipe panel_pipe = PIPE_A;
1163         bool locked = true;
1164
1165         if (WARN_ON(HAS_DDI(dev)))
1166                 return;
1167
1168         if (HAS_PCH_SPLIT(dev)) {
1169                 u32 port_sel;
1170
1171                 pp_reg = PCH_PP_CONTROL;
1172                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176                         panel_pipe = PIPE_B;
1177                 /* XXX: else fix for eDP */
1178         } else if (IS_VALLEYVIEW(dev)) {
1179                 /* presumably write lock depends on pipe, not port select */
1180                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181                 panel_pipe = pipe;
1182         } else {
1183                 pp_reg = PP_CONTROL;
1184                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185                         panel_pipe = PIPE_B;
1186         }
1187
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192
1193         WARN(panel_pipe == pipe && locked,
1194              "panel assertion failure, pipe %c regs locked\n",
1195              pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         struct drm_device *dev = dev_priv->dev;
1202         bool cur_state;
1203
1204         if (IS_845G(dev) || IS_I865G(dev))
1205                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206         else
1207                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209         WARN(cur_state != state,
1210              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211              pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217                  enum pipe pipe, bool state)
1218 {
1219         int reg;
1220         u32 val;
1221         bool cur_state;
1222         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223                                                                       pipe);
1224
1225         /* if we need the pipe quirk it must be always on */
1226         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228                 state = true;
1229
1230         if (!intel_display_power_is_enabled(dev_priv,
1231                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int reg, i;
1267         u32 val;
1268         int cur_pipe;
1269
1270         /* Primary planes are fixed to pipes on gen4+ */
1271         if (INTEL_INFO(dev)->gen >= 4) {
1272                 reg = DSPCNTR(pipe);
1273                 val = I915_READ(reg);
1274                 WARN(val & DISPLAY_PLANE_ENABLE,
1275                      "plane %c assertion failure, should be disabled but not\n",
1276                      plane_name(pipe));
1277                 return;
1278         }
1279
1280         /* Need to check both planes against the pipe */
1281         for_each_pipe(dev_priv, i) {
1282                 reg = DSPCNTR(i);
1283                 val = I915_READ(reg);
1284                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285                         DISPPLANE_SEL_PIPE_SHIFT;
1286                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288                      plane_name(i), pipe_name(pipe));
1289         }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe)
1294 {
1295         struct drm_device *dev = dev_priv->dev;
1296         int reg, sprite;
1297         u32 val;
1298
1299         if (INTEL_INFO(dev)->gen >= 9) {
1300                 for_each_sprite(pipe, sprite) {
1301                         val = I915_READ(PLANE_CTL(pipe, sprite));
1302                         WARN(val & PLANE_CTL_ENABLE,
1303                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304                              sprite, pipe_name(pipe));
1305                 }
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 for_each_sprite(pipe, sprite) {
1308                         reg = SPCNTR(pipe, sprite);
1309                         val = I915_READ(reg);
1310                         WARN(val & SP_ENABLE,
1311                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312                              sprite_name(pipe, sprite), pipe_name(pipe));
1313                 }
1314         } else if (INTEL_INFO(dev)->gen >= 7) {
1315                 reg = SPRCTL(pipe);
1316                 val = I915_READ(reg);
1317                 WARN(val & SPRITE_ENABLE,
1318                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                      plane_name(pipe), pipe_name(pipe));
1320         } else if (INTEL_INFO(dev)->gen >= 5) {
1321                 reg = DVSCNTR(pipe);
1322                 val = I915_READ(reg);
1323                 WARN(val & DVS_ENABLE,
1324                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325                      plane_name(pipe), pipe_name(pipe));
1326         }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332                 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337         u32 val;
1338         bool enabled;
1339
1340         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342         val = I915_READ(PCH_DREF_CONTROL);
1343         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344                             DREF_SUPERSPREAD_SOURCE_MASK));
1345         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349                                            enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353         bool enabled;
1354
1355         reg = PCH_TRANSCONF(pipe);
1356         val = I915_READ(reg);
1357         enabled = !!(val & TRANS_ENABLE);
1358         WARN(enabled,
1359              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360              pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364                             enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366         if ((val & DP_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373                         return false;
1374         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & SDVO_ENABLE) == 0)
1388                 return false;
1389
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392                         return false;
1393         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404                               enum pipe pipe, u32 val)
1405 {
1406         if ((val & LVDS_PORT_EN) == 0)
1407                 return false;
1408
1409         if (HAS_PCH_CPT(dev_priv->dev)) {
1410                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411                         return false;
1412         } else {
1413                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414                         return false;
1415         }
1416         return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420                               enum pipe pipe, u32 val)
1421 {
1422         if ((val & ADPA_DAC_ENABLE) == 0)
1423                 return false;
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435                                    enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              reg, pipe_name(pipe));
1441
1442         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443              && (val & DP_PIPEB_SELECT),
1444              "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448                                      enum pipe pipe, int reg)
1449 {
1450         u32 val = I915_READ(reg);
1451         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453              reg, pipe_name(pipe));
1454
1455         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456              && (val & SDVO_PIPE_B_SELECT),
1457              "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461                                       enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470         reg = PCH_ADPA;
1471         val = I915_READ(reg);
1472         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473              "PCH VGA enabled on transcoder %c, should be disabled\n",
1474              pipe_name(pipe));
1475
1476         reg = PCH_LVDS;
1477         val = I915_READ(reg);
1478         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491         if (!IS_VALLEYVIEW(dev))
1492                 return;
1493
1494         /*
1495          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496          * CHV x1 PHY (DP/HDMI D)
1497          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498          */
1499         if (IS_CHERRYVIEW(dev)) {
1500                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502         } else {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504         }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_config *pipe_config)
1509 {
1510         struct drm_device *dev = crtc->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int reg = DPLL(crtc->pipe);
1513         u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515         assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517         /* No really, not for ILK+ */
1518         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520         /* PLL is protected by panel, make sure we can write it */
1521         if (IS_MOBILE(dev_priv->dev))
1522                 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524         I915_WRITE(reg, dpll);
1525         POSTING_READ(reg);
1526         udelay(150);
1527
1528         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532         POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534         /* We do this three times for luck */
1535         I915_WRITE(reg, dpll);
1536         POSTING_READ(reg);
1537         udelay(150); /* wait for warmup */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_config *pipe_config)
1548 {
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int pipe = crtc->pipe;
1552         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553         u32 tmp;
1554
1555         assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559         mutex_lock(&dev_priv->dpio_lock);
1560
1561         /* Enable back the 10bit clock to display controller */
1562         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563         tmp |= DPIO_DCLKP_EN;
1564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566         /*
1567          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568          */
1569         udelay(1);
1570
1571         /* Enable PLL */
1572         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574         /* Check PLL is locked */
1575         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578         /* not sure when this should be written */
1579         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(pipe));
1581
1582         mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587         struct intel_crtc *crtc;
1588         int count = 0;
1589
1590         for_each_intel_crtc(dev, crtc)
1591                 count += crtc->active &&
1592                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594         return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         int reg = DPLL(crtc->pipe);
1602         u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606         /* No really, not for ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev) && !IS_I830(dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         /* Enable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615                 /*
1616                  * It appears to be important that we don't enable this
1617                  * for the current pipe before otherwise configuring the
1618                  * PLL. No idea how this should be handled if multiple
1619                  * DVO outputs are enabled simultaneosly.
1620                  */
1621                 dpll |= DPLL_DVO_2X_MODE;
1622                 I915_WRITE(DPLL(!crtc->pipe),
1623                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624         }
1625
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629
1630         if (INTEL_INFO(dev)->gen >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc->config.dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641
1642         /* We do this three times for luck */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655  * i9xx_disable_pll - disable a PLL
1656  * @dev_priv: i915 private structure
1657  * @pipe: pipe PLL to disable
1658  *
1659  * Disable the PLL for @pipe, making sure the pipe is off first.
1660  *
1661  * Note!  This is for pre-ILK only.
1662  */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         enum pipe pipe = crtc->pipe;
1668
1669         /* Disable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) &&
1671             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672             intel_num_dvo_pipes(dev) == 1) {
1673                 I915_WRITE(DPLL(PIPE_B),
1674                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675                 I915_WRITE(DPLL(PIPE_A),
1676                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677         }
1678
1679         /* Don't disable pipe or pipe PLLs if needed */
1680         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682                 return;
1683
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686
1687         I915_WRITE(DPLL(pipe), 0);
1688         POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         u32 val = 0;
1694
1695         /* Make sure the pipe isn't still relying on us */
1696         assert_pipe_disabled(dev_priv, pipe);
1697
1698         /*
1699          * Leave integrated clock source and reference clock enabled for pipe B.
1700          * The latter is needed for VGA hotplug / manual detection.
1701          */
1702         if (pipe == PIPE_B)
1703                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704         I915_WRITE(DPLL(pipe), val);
1705         POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712         u32 val;
1713
1714         /* Make sure the pipe isn't still relying on us */
1715         assert_pipe_disabled(dev_priv, pipe);
1716
1717         /* Set PLL en = 0 */
1718         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719         if (pipe != PIPE_A)
1720                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723
1724         mutex_lock(&dev_priv->dpio_lock);
1725
1726         /* Disable 10bit clock to display controller */
1727         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728         val &= ~DPIO_DCLKP_EN;
1729         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731         /* disable left/right clock distribution */
1732         if (pipe != PIPE_B) {
1733                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736         } else {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740         }
1741
1742         mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746                 struct intel_digital_port *dport)
1747 {
1748         u32 port_mask;
1749         int dpll_reg;
1750
1751         switch (dport->port) {
1752         case PORT_B:
1753                 port_mask = DPLL_PORTB_READY_MASK;
1754                 dpll_reg = DPLL(0);
1755                 break;
1756         case PORT_C:
1757                 port_mask = DPLL_PORTC_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_D:
1761                 port_mask = DPLL_PORTD_READY_MASK;
1762                 dpll_reg = DPIO_PHY_STATUS;
1763                 break;
1764         default:
1765                 BUG();
1766         }
1767
1768         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770                      port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779         if (WARN_ON(pll == NULL))
1780                 return;
1781
1782         WARN_ON(!pll->config.crtc_mask);
1783         if (pll->active == 0) {
1784                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785                 WARN_ON(pll->on);
1786                 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788                 pll->mode_set(dev_priv, pll);
1789         }
1790 }
1791
1792 /**
1793  * intel_enable_shared_dpll - enable PCH PLL
1794  * @dev_priv: i915 private structure
1795  * @pipe: pipe PLL to enable
1796  *
1797  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798  * drives the transcoder clock.
1799  */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808
1809         if (WARN_ON(pll->config.crtc_mask == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (pll->active++) {
1817                 WARN_ON(!pll->on);
1818                 assert_shared_dpll_enabled(dev_priv, pll);
1819                 return;
1820         }
1821         WARN_ON(pll->on);
1822
1823         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826         pll->enable(dev_priv, pll);
1827         pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->base.dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838         if (WARN_ON(pll == NULL))
1839                return;
1840
1841         if (WARN_ON(pll->config.crtc_mask == 0))
1842                 return;
1843
1844         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845                       pll->name, pll->active, pll->on,
1846                       crtc->base.base.id);
1847
1848         if (WARN_ON(pll->active == 0)) {
1849                 assert_shared_dpll_disabled(dev_priv, pll);
1850                 return;
1851         }
1852
1853         assert_shared_dpll_enabled(dev_priv, pll);
1854         WARN_ON(!pll->on);
1855         if (--pll->active)
1856                 return;
1857
1858         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859         pll->disable(dev_priv, pll);
1860         pll->on = false;
1861
1862         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866                                            enum pipe pipe)
1867 {
1868         struct drm_device *dev = dev_priv->dev;
1869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871         uint32_t reg, val, pipeconf_val;
1872
1873         /* PCH only available on ILK+ */
1874         BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876         /* Make sure PCH DPLL is enabled */
1877         assert_shared_dpll_enabled(dev_priv,
1878                                    intel_crtc_to_shared_dpll(intel_crtc));
1879
1880         /* FDI must be feeding us bits for PCH ports */
1881         assert_fdi_tx_enabled(dev_priv, pipe);
1882         assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884         if (HAS_PCH_CPT(dev)) {
1885                 /* Workaround: Set the timing override bit before enabling the
1886                  * pch transcoder. */
1887                 reg = TRANS_CHICKEN2(pipe);
1888                 val = I915_READ(reg);
1889                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890                 I915_WRITE(reg, val);
1891         }
1892
1893         reg = PCH_TRANSCONF(pipe);
1894         val = I915_READ(reg);
1895         pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897         if (HAS_PCH_IBX(dev_priv->dev)) {
1898                 /*
1899                  * make the BPC in transcoder be consistent with
1900                  * that in pipeconf reg.
1901                  */
1902                 val &= ~PIPECONF_BPC_MASK;
1903                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904         }
1905
1906         val &= ~TRANS_INTERLACE_MASK;
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908                 if (HAS_PCH_IBX(dev_priv->dev) &&
1909                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910                         val |= TRANS_LEGACY_INTERLACED_ILK;
1911                 else
1912                         val |= TRANS_INTERLACED;
1913         else
1914                 val |= TRANS_PROGRESSIVE;
1915
1916         I915_WRITE(reg, val | TRANS_ENABLE);
1917         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                       enum transcoder cpu_transcoder)
1923 {
1924         u32 val, pipeconf_val;
1925
1926         /* PCH only available on ILK+ */
1927         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929         /* FDI must be feeding us bits for PCH ports */
1930         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933         /* Workaround: set timing override bit. */
1934         val = I915_READ(_TRANSA_CHICKEN2);
1935         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936         I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938         val = TRANS_ENABLE;
1939         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942             PIPECONF_INTERLACED_ILK)
1943                 val |= TRANS_INTERLACED;
1944         else
1945                 val |= TRANS_PROGRESSIVE;
1946
1947         I915_WRITE(LPT_TRANSCONF, val);
1948         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949                 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953                                             enum pipe pipe)
1954 {
1955         struct drm_device *dev = dev_priv->dev;
1956         uint32_t reg, val;
1957
1958         /* FDI relies on the transcoder */
1959         assert_fdi_tx_disabled(dev_priv, pipe);
1960         assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962         /* Ports must be off as well */
1963         assert_pch_ports_disabled(dev_priv, pipe);
1964
1965         reg = PCH_TRANSCONF(pipe);
1966         val = I915_READ(reg);
1967         val &= ~TRANS_ENABLE;
1968         I915_WRITE(reg, val);
1969         /* wait for PCH transcoder off, transcoder state */
1970         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973         if (!HAS_PCH_IBX(dev)) {
1974                 /* Workaround: Clear the timing override chicken bit again. */
1975                 reg = TRANS_CHICKEN2(pipe);
1976                 val = I915_READ(reg);
1977                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978                 I915_WRITE(reg, val);
1979         }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984         u32 val;
1985
1986         val = I915_READ(LPT_TRANSCONF);
1987         val &= ~TRANS_ENABLE;
1988         I915_WRITE(LPT_TRANSCONF, val);
1989         /* wait for PCH transcoder off, transcoder state */
1990         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991                 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993         /* Workaround: clear timing override bit. */
1994         val = I915_READ(_TRANSA_CHICKEN2);
1995         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996         I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000  * intel_enable_pipe - enable a pipe, asserting requirements
2001  * @crtc: crtc responsible for the pipe
2002  *
2003  * Enable @crtc's pipe, making sure that various hardware specific requirements
2004  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005  */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->base.dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         enum pipe pipe = crtc->pipe;
2011         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012                                                                       pipe);
2013         enum pipe pch_transcoder;
2014         int reg;
2015         u32 val;
2016
2017         assert_planes_disabled(dev_priv, pipe);
2018         assert_cursor_disabled(dev_priv, pipe);
2019         assert_sprites_disabled(dev_priv, pipe);
2020
2021         if (HAS_PCH_LPT(dev_priv->dev))
2022                 pch_transcoder = TRANSCODER_A;
2023         else
2024                 pch_transcoder = pipe;
2025
2026         /*
2027          * A pipe without a PLL won't actually be able to drive bits from
2028          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029          * need the check.
2030          */
2031         if (!HAS_PCH_SPLIT(dev_priv->dev))
2032                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033                         assert_dsi_pll_enabled(dev_priv);
2034                 else
2035                         assert_pll_enabled(dev_priv, pipe);
2036         else {
2037                 if (crtc->config.has_pch_encoder) {
2038                         /* if driving the PCH, we need FDI enabled */
2039                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040                         assert_fdi_tx_pll_enabled(dev_priv,
2041                                                   (enum pipe) cpu_transcoder);
2042                 }
2043                 /* FIXME: assert CPU port conditions for SNB+ */
2044         }
2045
2046         reg = PIPECONF(cpu_transcoder);
2047         val = I915_READ(reg);
2048         if (val & PIPECONF_ENABLE) {
2049                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051                 return;
2052         }
2053
2054         I915_WRITE(reg, val | PIPECONF_ENABLE);
2055         POSTING_READ(reg);
2056 }
2057
2058 /**
2059  * intel_disable_pipe - disable a pipe, asserting requirements
2060  * @crtc: crtc whose pipes is to be disabled
2061  *
2062  * Disable the pipe of @crtc, making sure that various hardware
2063  * specific requirements are met, if applicable, e.g. plane
2064  * disabled, panel fitter off, etc.
2065  *
2066  * Will wait until the pipe has shut down before returning.
2067  */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072         enum pipe pipe = crtc->pipe;
2073         int reg;
2074         u32 val;
2075
2076         /*
2077          * Make sure planes won't keep trying to pump pixels to us,
2078          * or we might hang the display.
2079          */
2080         assert_planes_disabled(dev_priv, pipe);
2081         assert_cursor_disabled(dev_priv, pipe);
2082         assert_sprites_disabled(dev_priv, pipe);
2083
2084         reg = PIPECONF(cpu_transcoder);
2085         val = I915_READ(reg);
2086         if ((val & PIPECONF_ENABLE) == 0)
2087                 return;
2088
2089         /*
2090          * Double wide has implications for planes
2091          * so best keep it disabled when not needed.
2092          */
2093         if (crtc->config.double_wide)
2094                 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096         /* Don't disable pipe or pipe PLLs if needed */
2097         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099                 val &= ~PIPECONF_ENABLE;
2100
2101         I915_WRITE(reg, val);
2102         if ((val & PIPECONF_ENABLE) == 0)
2103                 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107  * Plane regs are double buffered, going from enabled->disabled needs a
2108  * trigger in order to latch.  The display address reg provides this.
2109  */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111                                enum plane plane)
2112 {
2113         struct drm_device *dev = dev_priv->dev;
2114         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116         I915_WRITE(reg, I915_READ(reg));
2117         POSTING_READ(reg);
2118 }
2119
2120 /**
2121  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122  * @plane:  plane to be enabled
2123  * @crtc: crtc for the plane
2124  *
2125  * Enable @plane on @crtc, making sure that the pipe is running first.
2126  */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128                                           struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = plane->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137         if (intel_crtc->primary_enabled)
2138                 return;
2139
2140         intel_crtc->primary_enabled = true;
2141
2142         dev_priv->display.update_primary_plane(crtc, plane->fb,
2143                                                crtc->x, crtc->y);
2144
2145         /*
2146          * BDW signals flip done immediately if the plane
2147          * is disabled, even if the plane enable is already
2148          * armed to occur at the next vblank :(
2149          */
2150         if (IS_BROADWELL(dev))
2151                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155  * intel_disable_primary_hw_plane - disable the primary hardware plane
2156  * @plane: plane to be disabled
2157  * @crtc: crtc for the plane
2158  *
2159  * Disable @plane on @crtc, making sure that the pipe is running first.
2160  */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162                                            struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = plane->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170         if (!intel_crtc->primary_enabled)
2171                 return;
2172
2173         intel_crtc->primary_enabled = false;
2174
2175         dev_priv->display.update_primary_plane(crtc, plane->fb,
2176                                                crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183                 return true;
2184 #endif
2185         return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190         int tile_height;
2191
2192         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193         return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198                            struct drm_framebuffer *fb,
2199                            struct intel_engine_cs *pipelined)
2200 {
2201         struct drm_device *dev = fb->dev;
2202         struct drm_i915_private *dev_priv = dev->dev_private;
2203         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2204         u32 alignment;
2205         int ret;
2206
2207         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208
2209         switch (obj->tiling_mode) {
2210         case I915_TILING_NONE:
2211                 if (INTEL_INFO(dev)->gen >= 9)
2212                         alignment = 256 * 1024;
2213                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2214                         alignment = 128 * 1024;
2215                 else if (INTEL_INFO(dev)->gen >= 4)
2216                         alignment = 4 * 1024;
2217                 else
2218                         alignment = 64 * 1024;
2219                 break;
2220         case I915_TILING_X:
2221                 if (INTEL_INFO(dev)->gen >= 9)
2222                         alignment = 256 * 1024;
2223                 else {
2224                         /* pin() will align the object as required by fence */
2225                         alignment = 0;
2226                 }
2227                 break;
2228         case I915_TILING_Y:
2229                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2230                 return -EINVAL;
2231         default:
2232                 BUG();
2233         }
2234
2235         /* Note that the w/a also requires 64 PTE of padding following the
2236          * bo. We currently fill all unused PTE with the shadow page and so
2237          * we should always have valid PTE following the scanout preventing
2238          * the VT-d warning.
2239          */
2240         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241                 alignment = 256 * 1024;
2242
2243         /*
2244          * Global gtt pte registers are special registers which actually forward
2245          * writes to a chunk of system memory. Which means that there is no risk
2246          * that the register values disappear as soon as we call
2247          * intel_runtime_pm_put(), so it is correct to wrap only the
2248          * pin/unpin/fence and not more.
2249          */
2250         intel_runtime_pm_get(dev_priv);
2251
2252         dev_priv->mm.interruptible = false;
2253         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2254         if (ret)
2255                 goto err_interruptible;
2256
2257         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258          * fence, whereas 965+ only requires a fence if using
2259          * framebuffer compression.  For simplicity, we always install
2260          * a fence as the cost is not that onerous.
2261          */
2262         ret = i915_gem_object_get_fence(obj);
2263         if (ret)
2264                 goto err_unpin;
2265
2266         i915_gem_object_pin_fence(obj);
2267
2268         dev_priv->mm.interruptible = true;
2269         intel_runtime_pm_put(dev_priv);
2270         return 0;
2271
2272 err_unpin:
2273         i915_gem_object_unpin_from_display_plane(obj);
2274 err_interruptible:
2275         dev_priv->mm.interruptible = true;
2276         intel_runtime_pm_put(dev_priv);
2277         return ret;
2278 }
2279
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281 {
2282         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283
2284         i915_gem_object_unpin_fence(obj);
2285         i915_gem_object_unpin_from_display_plane(obj);
2286 }
2287
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289  * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291                                              unsigned int tiling_mode,
2292                                              unsigned int cpp,
2293                                              unsigned int pitch)
2294 {
2295         if (tiling_mode != I915_TILING_NONE) {
2296                 unsigned int tile_rows, tiles;
2297
2298                 tile_rows = *y / 8;
2299                 *y %= 8;
2300
2301                 tiles = *x / (512/cpp);
2302                 *x %= 512/cpp;
2303
2304                 return tile_rows * pitch * 8 + tiles * 4096;
2305         } else {
2306                 unsigned int offset;
2307
2308                 offset = *y * pitch + *x * cpp;
2309                 *y = 0;
2310                 *x = (offset & 4095) / cpp;
2311                 return offset & -4096;
2312         }
2313 }
2314
2315 int intel_format_to_fourcc(int format)
2316 {
2317         switch (format) {
2318         case DISPPLANE_8BPP:
2319                 return DRM_FORMAT_C8;
2320         case DISPPLANE_BGRX555:
2321                 return DRM_FORMAT_XRGB1555;
2322         case DISPPLANE_BGRX565:
2323                 return DRM_FORMAT_RGB565;
2324         default:
2325         case DISPPLANE_BGRX888:
2326                 return DRM_FORMAT_XRGB8888;
2327         case DISPPLANE_RGBX888:
2328                 return DRM_FORMAT_XBGR8888;
2329         case DISPPLANE_BGRX101010:
2330                 return DRM_FORMAT_XRGB2101010;
2331         case DISPPLANE_RGBX101010:
2332                 return DRM_FORMAT_XBGR2101010;
2333         }
2334 }
2335
2336 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2337                                   struct intel_plane_config *plane_config)
2338 {
2339         struct drm_device *dev = crtc->base.dev;
2340         struct drm_i915_gem_object *obj = NULL;
2341         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342         u32 base = plane_config->base;
2343
2344         if (plane_config->size == 0)
2345                 return false;
2346
2347         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348                                                              plane_config->size);
2349         if (!obj)
2350                 return false;
2351
2352         if (plane_config->tiled) {
2353                 obj->tiling_mode = I915_TILING_X;
2354                 obj->stride = crtc->base.primary->fb->pitches[0];
2355         }
2356
2357         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358         mode_cmd.width = crtc->base.primary->fb->width;
2359         mode_cmd.height = crtc->base.primary->fb->height;
2360         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2361
2362         mutex_lock(&dev->struct_mutex);
2363
2364         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2365                                    &mode_cmd, obj)) {
2366                 DRM_DEBUG_KMS("intel fb init failed\n");
2367                 goto out_unref_obj;
2368         }
2369
2370         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2371         mutex_unlock(&dev->struct_mutex);
2372
2373         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374         return true;
2375
2376 out_unref_obj:
2377         drm_gem_object_unreference(&obj->base);
2378         mutex_unlock(&dev->struct_mutex);
2379         return false;
2380 }
2381
2382 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383                                  struct intel_plane_config *plane_config)
2384 {
2385         struct drm_device *dev = intel_crtc->base.dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct drm_crtc *c;
2388         struct intel_crtc *i;
2389         struct drm_i915_gem_object *obj;
2390
2391         if (!intel_crtc->base.primary->fb)
2392                 return;
2393
2394         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395                 return;
2396
2397         kfree(intel_crtc->base.primary->fb);
2398         intel_crtc->base.primary->fb = NULL;
2399
2400         /*
2401          * Failed to alloc the obj, check to see if we should share
2402          * an fb with another CRTC instead
2403          */
2404         for_each_crtc(dev, c) {
2405                 i = to_intel_crtc(c);
2406
2407                 if (c == &intel_crtc->base)
2408                         continue;
2409
2410                 if (!i->active)
2411                         continue;
2412
2413                 obj = intel_fb_obj(c->primary->fb);
2414                 if (obj == NULL)
2415                         continue;
2416
2417                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2418                         if (obj->tiling_mode != I915_TILING_NONE)
2419                                 dev_priv->preserve_bios_swizzle = true;
2420
2421                         drm_framebuffer_reference(c->primary->fb);
2422                         intel_crtc->base.primary->fb = c->primary->fb;
2423                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2424                         break;
2425                 }
2426         }
2427 }
2428
2429 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430                                       struct drm_framebuffer *fb,
2431                                       int x, int y)
2432 {
2433         struct drm_device *dev = crtc->dev;
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2436         struct drm_i915_gem_object *obj;
2437         int plane = intel_crtc->plane;
2438         unsigned long linear_offset;
2439         u32 dspcntr;
2440         u32 reg = DSPCNTR(plane);
2441         int pixel_size;
2442
2443         if (!intel_crtc->primary_enabled) {
2444                 I915_WRITE(reg, 0);
2445                 if (INTEL_INFO(dev)->gen >= 4)
2446                         I915_WRITE(DSPSURF(plane), 0);
2447                 else
2448                         I915_WRITE(DSPADDR(plane), 0);
2449                 POSTING_READ(reg);
2450                 return;
2451         }
2452
2453         obj = intel_fb_obj(fb);
2454         if (WARN_ON(obj == NULL))
2455                 return;
2456
2457         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458
2459         dspcntr = DISPPLANE_GAMMA_ENABLE;
2460
2461         dspcntr |= DISPLAY_PLANE_ENABLE;
2462
2463         if (INTEL_INFO(dev)->gen < 4) {
2464                 if (intel_crtc->pipe == PIPE_B)
2465                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2466
2467                 /* pipesrc and dspsize control the size that is scaled from,
2468                  * which should always be the user's requested size.
2469                  */
2470                 I915_WRITE(DSPSIZE(plane),
2471                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472                            (intel_crtc->config.pipe_src_w - 1));
2473                 I915_WRITE(DSPPOS(plane), 0);
2474         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475                 I915_WRITE(PRIMSIZE(plane),
2476                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477                            (intel_crtc->config.pipe_src_w - 1));
2478                 I915_WRITE(PRIMPOS(plane), 0);
2479                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2480         }
2481
2482         switch (fb->pixel_format) {
2483         case DRM_FORMAT_C8:
2484                 dspcntr |= DISPPLANE_8BPP;
2485                 break;
2486         case DRM_FORMAT_XRGB1555:
2487         case DRM_FORMAT_ARGB1555:
2488                 dspcntr |= DISPPLANE_BGRX555;
2489                 break;
2490         case DRM_FORMAT_RGB565:
2491                 dspcntr |= DISPPLANE_BGRX565;
2492                 break;
2493         case DRM_FORMAT_XRGB8888:
2494         case DRM_FORMAT_ARGB8888:
2495                 dspcntr |= DISPPLANE_BGRX888;
2496                 break;
2497         case DRM_FORMAT_XBGR8888:
2498         case DRM_FORMAT_ABGR8888:
2499                 dspcntr |= DISPPLANE_RGBX888;
2500                 break;
2501         case DRM_FORMAT_XRGB2101010:
2502         case DRM_FORMAT_ARGB2101010:
2503                 dspcntr |= DISPPLANE_BGRX101010;
2504                 break;
2505         case DRM_FORMAT_XBGR2101010:
2506         case DRM_FORMAT_ABGR2101010:
2507                 dspcntr |= DISPPLANE_RGBX101010;
2508                 break;
2509         default:
2510                 BUG();
2511         }
2512
2513         if (INTEL_INFO(dev)->gen >= 4 &&
2514             obj->tiling_mode != I915_TILING_NONE)
2515                 dspcntr |= DISPPLANE_TILED;
2516
2517         if (IS_G4X(dev))
2518                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519
2520         linear_offset = y * fb->pitches[0] + x * pixel_size;
2521
2522         if (INTEL_INFO(dev)->gen >= 4) {
2523                 intel_crtc->dspaddr_offset =
2524                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525                                                        pixel_size,
2526                                                        fb->pitches[0]);
2527                 linear_offset -= intel_crtc->dspaddr_offset;
2528         } else {
2529                 intel_crtc->dspaddr_offset = linear_offset;
2530         }
2531
2532         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533                 dspcntr |= DISPPLANE_ROTATE_180;
2534
2535                 x += (intel_crtc->config.pipe_src_w - 1);
2536                 y += (intel_crtc->config.pipe_src_h - 1);
2537
2538                 /* Finding the last pixel of the last line of the display
2539                 data and adding to linear_offset*/
2540                 linear_offset +=
2541                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543         }
2544
2545         I915_WRITE(reg, dspcntr);
2546
2547         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549                       fb->pitches[0]);
2550         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2551         if (INTEL_INFO(dev)->gen >= 4) {
2552                 I915_WRITE(DSPSURF(plane),
2553                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2555                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2556         } else
2557                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2558         POSTING_READ(reg);
2559 }
2560
2561 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562                                           struct drm_framebuffer *fb,
2563                                           int x, int y)
2564 {
2565         struct drm_device *dev = crtc->dev;
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568         struct drm_i915_gem_object *obj;
2569         int plane = intel_crtc->plane;
2570         unsigned long linear_offset;
2571         u32 dspcntr;
2572         u32 reg = DSPCNTR(plane);
2573         int pixel_size;
2574
2575         if (!intel_crtc->primary_enabled) {
2576                 I915_WRITE(reg, 0);
2577                 I915_WRITE(DSPSURF(plane), 0);
2578                 POSTING_READ(reg);
2579                 return;
2580         }
2581
2582         obj = intel_fb_obj(fb);
2583         if (WARN_ON(obj == NULL))
2584                 return;
2585
2586         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587
2588         dspcntr = DISPPLANE_GAMMA_ENABLE;
2589
2590         dspcntr |= DISPLAY_PLANE_ENABLE;
2591
2592         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594
2595         switch (fb->pixel_format) {
2596         case DRM_FORMAT_C8:
2597                 dspcntr |= DISPPLANE_8BPP;
2598                 break;
2599         case DRM_FORMAT_RGB565:
2600                 dspcntr |= DISPPLANE_BGRX565;
2601                 break;
2602         case DRM_FORMAT_XRGB8888:
2603         case DRM_FORMAT_ARGB8888:
2604                 dspcntr |= DISPPLANE_BGRX888;
2605                 break;
2606         case DRM_FORMAT_XBGR8888:
2607         case DRM_FORMAT_ABGR8888:
2608                 dspcntr |= DISPPLANE_RGBX888;
2609                 break;
2610         case DRM_FORMAT_XRGB2101010:
2611         case DRM_FORMAT_ARGB2101010:
2612                 dspcntr |= DISPPLANE_BGRX101010;
2613                 break;
2614         case DRM_FORMAT_XBGR2101010:
2615         case DRM_FORMAT_ABGR2101010:
2616                 dspcntr |= DISPPLANE_RGBX101010;
2617                 break;
2618         default:
2619                 BUG();
2620         }
2621
2622         if (obj->tiling_mode != I915_TILING_NONE)
2623                 dspcntr |= DISPPLANE_TILED;
2624
2625         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2626                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2627
2628         linear_offset = y * fb->pitches[0] + x * pixel_size;
2629         intel_crtc->dspaddr_offset =
2630                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2631                                                pixel_size,
2632                                                fb->pitches[0]);
2633         linear_offset -= intel_crtc->dspaddr_offset;
2634         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635                 dspcntr |= DISPPLANE_ROTATE_180;
2636
2637                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638                         x += (intel_crtc->config.pipe_src_w - 1);
2639                         y += (intel_crtc->config.pipe_src_h - 1);
2640
2641                         /* Finding the last pixel of the last line of the display
2642                         data and adding to linear_offset*/
2643                         linear_offset +=
2644                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646                 }
2647         }
2648
2649         I915_WRITE(reg, dspcntr);
2650
2651         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653                       fb->pitches[0]);
2654         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655         I915_WRITE(DSPSURF(plane),
2656                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2657         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2658                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659         } else {
2660                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662         }
2663         POSTING_READ(reg);
2664 }
2665
2666 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667                                          struct drm_framebuffer *fb,
2668                                          int x, int y)
2669 {
2670         struct drm_device *dev = crtc->dev;
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673         struct intel_framebuffer *intel_fb;
2674         struct drm_i915_gem_object *obj;
2675         int pipe = intel_crtc->pipe;
2676         u32 plane_ctl, stride;
2677
2678         if (!intel_crtc->primary_enabled) {
2679                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681                 POSTING_READ(PLANE_CTL(pipe, 0));
2682                 return;
2683         }
2684
2685         plane_ctl = PLANE_CTL_ENABLE |
2686                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2687                     PLANE_CTL_PIPE_CSC_ENABLE;
2688
2689         switch (fb->pixel_format) {
2690         case DRM_FORMAT_RGB565:
2691                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692                 break;
2693         case DRM_FORMAT_XRGB8888:
2694                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695                 break;
2696         case DRM_FORMAT_XBGR8888:
2697                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699                 break;
2700         case DRM_FORMAT_XRGB2101010:
2701                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702                 break;
2703         case DRM_FORMAT_XBGR2101010:
2704                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706                 break;
2707         default:
2708                 BUG();
2709         }
2710
2711         intel_fb = to_intel_framebuffer(fb);
2712         obj = intel_fb->obj;
2713
2714         /*
2715          * The stride is either expressed as a multiple of 64 bytes chunks for
2716          * linear buffers or in number of tiles for tiled buffers.
2717          */
2718         switch (obj->tiling_mode) {
2719         case I915_TILING_NONE:
2720                 stride = fb->pitches[0] >> 6;
2721                 break;
2722         case I915_TILING_X:
2723                 plane_ctl |= PLANE_CTL_TILED_X;
2724                 stride = fb->pitches[0] >> 9;
2725                 break;
2726         default:
2727                 BUG();
2728         }
2729
2730         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2731         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732                 plane_ctl |= PLANE_CTL_ROTATE_180;
2733
2734         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735
2736         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737                       i915_gem_obj_ggtt_offset(obj),
2738                       x, y, fb->width, fb->height,
2739                       fb->pitches[0]);
2740
2741         I915_WRITE(PLANE_POS(pipe, 0), 0);
2742         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743         I915_WRITE(PLANE_SIZE(pipe, 0),
2744                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2745                    (intel_crtc->config.pipe_src_w - 1));
2746         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748
2749         POSTING_READ(PLANE_SURF(pipe, 0));
2750 }
2751
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2753 static int
2754 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755                            int x, int y, enum mode_set_atomic state)
2756 {
2757         struct drm_device *dev = crtc->dev;
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759
2760         if (dev_priv->display.disable_fbc)
2761                 dev_priv->display.disable_fbc(dev);
2762
2763         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764
2765         return 0;
2766 }
2767
2768 void intel_display_handle_reset(struct drm_device *dev)
2769 {
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771         struct drm_crtc *crtc;
2772
2773         /*
2774          * Flips in the rings have been nuked by the reset,
2775          * so complete all pending flips so that user space
2776          * will get its events and not get stuck.
2777          *
2778          * Also update the base address of all primary
2779          * planes to the the last fb to make sure we're
2780          * showing the correct fb after a reset.
2781          *
2782          * Need to make two loops over the crtcs so that we
2783          * don't try to grab a crtc mutex before the
2784          * pending_flip_queue really got woken up.
2785          */
2786
2787         for_each_crtc(dev, crtc) {
2788                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789                 enum plane plane = intel_crtc->plane;
2790
2791                 intel_prepare_page_flip(dev, plane);
2792                 intel_finish_page_flip_plane(dev, plane);
2793         }
2794
2795         for_each_crtc(dev, crtc) {
2796                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797
2798                 drm_modeset_lock(&crtc->mutex, NULL);
2799                 /*
2800                  * FIXME: Once we have proper support for primary planes (and
2801                  * disabling them without disabling the entire crtc) allow again
2802                  * a NULL crtc->primary->fb.
2803                  */
2804                 if (intel_crtc->active && crtc->primary->fb)
2805                         dev_priv->display.update_primary_plane(crtc,
2806                                                                crtc->primary->fb,
2807                                                                crtc->x,
2808                                                                crtc->y);
2809                 drm_modeset_unlock(&crtc->mutex);
2810         }
2811 }
2812
2813 static int
2814 intel_finish_fb(struct drm_framebuffer *old_fb)
2815 {
2816         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2817         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2818         bool was_interruptible = dev_priv->mm.interruptible;
2819         int ret;
2820
2821         /* Big Hammer, we also need to ensure that any pending
2822          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2823          * current scanout is retired before unpinning the old
2824          * framebuffer.
2825          *
2826          * This should only fail upon a hung GPU, in which case we
2827          * can safely continue.
2828          */
2829         dev_priv->mm.interruptible = false;
2830         ret = i915_gem_object_finish_gpu(obj);
2831         dev_priv->mm.interruptible = was_interruptible;
2832
2833         return ret;
2834 }
2835
2836 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2837 {
2838         struct drm_device *dev = crtc->dev;
2839         struct drm_i915_private *dev_priv = dev->dev_private;
2840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841         bool pending;
2842
2843         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2844             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2845                 return false;
2846
2847         spin_lock_irq(&dev->event_lock);
2848         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2849         spin_unlock_irq(&dev->event_lock);
2850
2851         return pending;
2852 }
2853
2854 static void intel_update_pipe_size(struct intel_crtc *crtc)
2855 {
2856         struct drm_device *dev = crtc->base.dev;
2857         struct drm_i915_private *dev_priv = dev->dev_private;
2858         const struct drm_display_mode *adjusted_mode;
2859
2860         if (!i915.fastboot)
2861                 return;
2862
2863         /*
2864          * Update pipe size and adjust fitter if needed: the reason for this is
2865          * that in compute_mode_changes we check the native mode (not the pfit
2866          * mode) to see if we can flip rather than do a full mode set. In the
2867          * fastboot case, we'll flip, but if we don't update the pipesrc and
2868          * pfit state, we'll end up with a big fb scanned out into the wrong
2869          * sized surface.
2870          *
2871          * To fix this properly, we need to hoist the checks up into
2872          * compute_mode_changes (or above), check the actual pfit state and
2873          * whether the platform allows pfit disable with pipe active, and only
2874          * then update the pipesrc and pfit state, even on the flip path.
2875          */
2876
2877         adjusted_mode = &crtc->config.adjusted_mode;
2878
2879         I915_WRITE(PIPESRC(crtc->pipe),
2880                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2881                    (adjusted_mode->crtc_vdisplay - 1));
2882         if (!crtc->config.pch_pfit.enabled &&
2883             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2884              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2885                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2886                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2887                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2888         }
2889         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2890         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2891 }
2892
2893 static int
2894 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2895                     struct drm_framebuffer *fb)
2896 {
2897         struct drm_device *dev = crtc->dev;
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2900         enum pipe pipe = intel_crtc->pipe;
2901         struct drm_framebuffer *old_fb = crtc->primary->fb;
2902         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2903         int ret;
2904
2905         if (intel_crtc_has_pending_flip(crtc)) {
2906                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2907                 return -EBUSY;
2908         }
2909
2910         /* no fb bound */
2911         if (!fb) {
2912                 DRM_ERROR("No FB bound\n");
2913                 return 0;
2914         }
2915
2916         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2917                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2918                           plane_name(intel_crtc->plane),
2919                           INTEL_INFO(dev)->num_pipes);
2920                 return -EINVAL;
2921         }
2922
2923         mutex_lock(&dev->struct_mutex);
2924         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
2925         if (ret == 0)
2926                 i915_gem_track_fb(old_obj, intel_fb_obj(fb),
2927                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2928         mutex_unlock(&dev->struct_mutex);
2929         if (ret != 0) {
2930                 DRM_ERROR("pin & fence failed\n");
2931                 return ret;
2932         }
2933
2934         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2935
2936         if (intel_crtc->active)
2937                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2938
2939         crtc->primary->fb = fb;
2940         crtc->x = x;
2941         crtc->y = y;
2942
2943         if (old_fb) {
2944                 if (intel_crtc->active && old_fb != fb)
2945                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2946                 mutex_lock(&dev->struct_mutex);
2947                 intel_unpin_fb_obj(old_obj);
2948                 mutex_unlock(&dev->struct_mutex);
2949         }
2950
2951         mutex_lock(&dev->struct_mutex);
2952         intel_update_fbc(dev);
2953         mutex_unlock(&dev->struct_mutex);
2954
2955         return 0;
2956 }
2957
2958 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2959 {
2960         struct drm_device *dev = crtc->dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963         int pipe = intel_crtc->pipe;
2964         u32 reg, temp;
2965
2966         /* enable normal train */
2967         reg = FDI_TX_CTL(pipe);
2968         temp = I915_READ(reg);
2969         if (IS_IVYBRIDGE(dev)) {
2970                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2971                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2972         } else {
2973                 temp &= ~FDI_LINK_TRAIN_NONE;
2974                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2975         }
2976         I915_WRITE(reg, temp);
2977
2978         reg = FDI_RX_CTL(pipe);
2979         temp = I915_READ(reg);
2980         if (HAS_PCH_CPT(dev)) {
2981                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2982                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2983         } else {
2984                 temp &= ~FDI_LINK_TRAIN_NONE;
2985                 temp |= FDI_LINK_TRAIN_NONE;
2986         }
2987         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2988
2989         /* wait one idle pattern time */
2990         POSTING_READ(reg);
2991         udelay(1000);
2992
2993         /* IVB wants error correction enabled */
2994         if (IS_IVYBRIDGE(dev))
2995                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2996                            FDI_FE_ERRC_ENABLE);
2997 }
2998
2999 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3000 {
3001         return crtc->base.enabled && crtc->active &&
3002                 crtc->config.has_pch_encoder;
3003 }
3004
3005 static void ivb_modeset_global_resources(struct drm_device *dev)
3006 {
3007         struct drm_i915_private *dev_priv = dev->dev_private;
3008         struct intel_crtc *pipe_B_crtc =
3009                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3010         struct intel_crtc *pipe_C_crtc =
3011                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3012         uint32_t temp;
3013
3014         /*
3015          * When everything is off disable fdi C so that we could enable fdi B
3016          * with all lanes. Note that we don't care about enabled pipes without
3017          * an enabled pch encoder.
3018          */
3019         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3020             !pipe_has_enabled_pch(pipe_C_crtc)) {
3021                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3022                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3023
3024                 temp = I915_READ(SOUTH_CHICKEN1);
3025                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3026                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3027                 I915_WRITE(SOUTH_CHICKEN1, temp);
3028         }
3029 }
3030
3031 /* The FDI link training functions for ILK/Ibexpeak. */
3032 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3033 {
3034         struct drm_device *dev = crtc->dev;
3035         struct drm_i915_private *dev_priv = dev->dev_private;
3036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037         int pipe = intel_crtc->pipe;
3038         u32 reg, temp, tries;
3039
3040         /* FDI needs bits from pipe first */
3041         assert_pipe_enabled(dev_priv, pipe);
3042
3043         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3044            for train result */
3045         reg = FDI_RX_IMR(pipe);
3046         temp = I915_READ(reg);
3047         temp &= ~FDI_RX_SYMBOL_LOCK;
3048         temp &= ~FDI_RX_BIT_LOCK;
3049         I915_WRITE(reg, temp);
3050         I915_READ(reg);
3051         udelay(150);
3052
3053         /* enable CPU FDI TX and PCH FDI RX */
3054         reg = FDI_TX_CTL(pipe);
3055         temp = I915_READ(reg);
3056         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3057         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3058         temp &= ~FDI_LINK_TRAIN_NONE;
3059         temp |= FDI_LINK_TRAIN_PATTERN_1;
3060         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3061
3062         reg = FDI_RX_CTL(pipe);
3063         temp = I915_READ(reg);
3064         temp &= ~FDI_LINK_TRAIN_NONE;
3065         temp |= FDI_LINK_TRAIN_PATTERN_1;
3066         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3067
3068         POSTING_READ(reg);
3069         udelay(150);
3070
3071         /* Ironlake workaround, enable clock pointer after FDI enable*/
3072         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3073         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3074                    FDI_RX_PHASE_SYNC_POINTER_EN);
3075
3076         reg = FDI_RX_IIR(pipe);
3077         for (tries = 0; tries < 5; tries++) {
3078                 temp = I915_READ(reg);
3079                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3080
3081                 if ((temp & FDI_RX_BIT_LOCK)) {
3082                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3083                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3084                         break;
3085                 }
3086         }
3087         if (tries == 5)
3088                 DRM_ERROR("FDI train 1 fail!\n");
3089
3090         /* Train 2 */
3091         reg = FDI_TX_CTL(pipe);
3092         temp = I915_READ(reg);
3093         temp &= ~FDI_LINK_TRAIN_NONE;
3094         temp |= FDI_LINK_TRAIN_PATTERN_2;
3095         I915_WRITE(reg, temp);
3096
3097         reg = FDI_RX_CTL(pipe);
3098         temp = I915_READ(reg);
3099         temp &= ~FDI_LINK_TRAIN_NONE;
3100         temp |= FDI_LINK_TRAIN_PATTERN_2;
3101         I915_WRITE(reg, temp);
3102
3103         POSTING_READ(reg);
3104         udelay(150);
3105
3106         reg = FDI_RX_IIR(pipe);
3107         for (tries = 0; tries < 5; tries++) {
3108                 temp = I915_READ(reg);
3109                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3110
3111                 if (temp & FDI_RX_SYMBOL_LOCK) {
3112                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3113                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3114                         break;
3115                 }
3116         }
3117         if (tries == 5)
3118                 DRM_ERROR("FDI train 2 fail!\n");
3119
3120         DRM_DEBUG_KMS("FDI train done\n");
3121
3122 }
3123
3124 static const int snb_b_fdi_train_param[] = {
3125         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3126         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3127         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3128         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3129 };
3130
3131 /* The FDI link training functions for SNB/Cougarpoint. */
3132 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3133 {
3134         struct drm_device *dev = crtc->dev;
3135         struct drm_i915_private *dev_priv = dev->dev_private;
3136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3137         int pipe = intel_crtc->pipe;
3138         u32 reg, temp, i, retry;
3139
3140         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3141            for train result */
3142         reg = FDI_RX_IMR(pipe);
3143         temp = I915_READ(reg);
3144         temp &= ~FDI_RX_SYMBOL_LOCK;
3145         temp &= ~FDI_RX_BIT_LOCK;
3146         I915_WRITE(reg, temp);
3147
3148         POSTING_READ(reg);
3149         udelay(150);
3150
3151         /* enable CPU FDI TX and PCH FDI RX */
3152         reg = FDI_TX_CTL(pipe);
3153         temp = I915_READ(reg);
3154         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3155         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3156         temp &= ~FDI_LINK_TRAIN_NONE;
3157         temp |= FDI_LINK_TRAIN_PATTERN_1;
3158         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3159         /* SNB-B */
3160         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3161         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3162
3163         I915_WRITE(FDI_RX_MISC(pipe),
3164                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3165
3166         reg = FDI_RX_CTL(pipe);
3167         temp = I915_READ(reg);
3168         if (HAS_PCH_CPT(dev)) {
3169                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3170                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3171         } else {
3172                 temp &= ~FDI_LINK_TRAIN_NONE;
3173                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3174         }
3175         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3176
3177         POSTING_READ(reg);
3178         udelay(150);
3179
3180         for (i = 0; i < 4; i++) {
3181                 reg = FDI_TX_CTL(pipe);
3182                 temp = I915_READ(reg);
3183                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3184                 temp |= snb_b_fdi_train_param[i];
3185                 I915_WRITE(reg, temp);
3186
3187                 POSTING_READ(reg);
3188                 udelay(500);
3189
3190                 for (retry = 0; retry < 5; retry++) {
3191                         reg = FDI_RX_IIR(pipe);
3192                         temp = I915_READ(reg);
3193                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3194                         if (temp & FDI_RX_BIT_LOCK) {
3195                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3196                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3197                                 break;
3198                         }
3199                         udelay(50);
3200                 }
3201                 if (retry < 5)
3202                         break;
3203         }
3204         if (i == 4)
3205                 DRM_ERROR("FDI train 1 fail!\n");
3206
3207         /* Train 2 */
3208         reg = FDI_TX_CTL(pipe);
3209         temp = I915_READ(reg);
3210         temp &= ~FDI_LINK_TRAIN_NONE;
3211         temp |= FDI_LINK_TRAIN_PATTERN_2;
3212         if (IS_GEN6(dev)) {
3213                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3214                 /* SNB-B */
3215                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3216         }
3217         I915_WRITE(reg, temp);
3218
3219         reg = FDI_RX_CTL(pipe);
3220         temp = I915_READ(reg);
3221         if (HAS_PCH_CPT(dev)) {
3222                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3223                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3224         } else {
3225                 temp &= ~FDI_LINK_TRAIN_NONE;
3226                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3227         }
3228         I915_WRITE(reg, temp);
3229
3230         POSTING_READ(reg);
3231         udelay(150);
3232
3233         for (i = 0; i < 4; i++) {
3234                 reg = FDI_TX_CTL(pipe);
3235                 temp = I915_READ(reg);
3236                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3237                 temp |= snb_b_fdi_train_param[i];
3238                 I915_WRITE(reg, temp);
3239
3240                 POSTING_READ(reg);
3241                 udelay(500);
3242
3243                 for (retry = 0; retry < 5; retry++) {
3244                         reg = FDI_RX_IIR(pipe);
3245                         temp = I915_READ(reg);
3246                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3247                         if (temp & FDI_RX_SYMBOL_LOCK) {
3248                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3249                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3250                                 break;
3251                         }
3252                         udelay(50);
3253                 }
3254                 if (retry < 5)
3255                         break;
3256         }
3257         if (i == 4)
3258                 DRM_ERROR("FDI train 2 fail!\n");
3259
3260         DRM_DEBUG_KMS("FDI train done.\n");
3261 }
3262
3263 /* Manual link training for Ivy Bridge A0 parts */
3264 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3265 {
3266         struct drm_device *dev = crtc->dev;
3267         struct drm_i915_private *dev_priv = dev->dev_private;
3268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3269         int pipe = intel_crtc->pipe;
3270         u32 reg, temp, i, j;
3271
3272         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3273            for train result */
3274         reg = FDI_RX_IMR(pipe);
3275         temp = I915_READ(reg);
3276         temp &= ~FDI_RX_SYMBOL_LOCK;
3277         temp &= ~FDI_RX_BIT_LOCK;
3278         I915_WRITE(reg, temp);
3279
3280         POSTING_READ(reg);
3281         udelay(150);
3282
3283         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3284                       I915_READ(FDI_RX_IIR(pipe)));
3285
3286         /* Try each vswing and preemphasis setting twice before moving on */
3287         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3288                 /* disable first in case we need to retry */
3289                 reg = FDI_TX_CTL(pipe);
3290                 temp = I915_READ(reg);
3291                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3292                 temp &= ~FDI_TX_ENABLE;
3293                 I915_WRITE(reg, temp);
3294
3295                 reg = FDI_RX_CTL(pipe);
3296                 temp = I915_READ(reg);
3297                 temp &= ~FDI_LINK_TRAIN_AUTO;
3298                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3299                 temp &= ~FDI_RX_ENABLE;
3300                 I915_WRITE(reg, temp);
3301
3302                 /* enable CPU FDI TX and PCH FDI RX */
3303                 reg = FDI_TX_CTL(pipe);
3304                 temp = I915_READ(reg);
3305                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3306                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3307                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3308                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3309                 temp |= snb_b_fdi_train_param[j/2];
3310                 temp |= FDI_COMPOSITE_SYNC;
3311                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3312
3313                 I915_WRITE(FDI_RX_MISC(pipe),
3314                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3315
3316                 reg = FDI_RX_CTL(pipe);
3317                 temp = I915_READ(reg);
3318                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3319                 temp |= FDI_COMPOSITE_SYNC;
3320                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3321
3322                 POSTING_READ(reg);
3323                 udelay(1); /* should be 0.5us */
3324
3325                 for (i = 0; i < 4; i++) {
3326                         reg = FDI_RX_IIR(pipe);
3327                         temp = I915_READ(reg);
3328                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3329
3330                         if (temp & FDI_RX_BIT_LOCK ||
3331                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3332                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3333                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3334                                               i);
3335                                 break;
3336                         }
3337                         udelay(1); /* should be 0.5us */
3338                 }
3339                 if (i == 4) {
3340                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3341                         continue;
3342                 }
3343
3344                 /* Train 2 */
3345                 reg = FDI_TX_CTL(pipe);
3346                 temp = I915_READ(reg);
3347                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3348                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3349                 I915_WRITE(reg, temp);
3350
3351                 reg = FDI_RX_CTL(pipe);
3352                 temp = I915_READ(reg);
3353                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3354                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3355                 I915_WRITE(reg, temp);
3356
3357                 POSTING_READ(reg);
3358                 udelay(2); /* should be 1.5us */
3359
3360                 for (i = 0; i < 4; i++) {
3361                         reg = FDI_RX_IIR(pipe);
3362                         temp = I915_READ(reg);
3363                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3364
3365                         if (temp & FDI_RX_SYMBOL_LOCK ||
3366                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3367                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3368                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3369                                               i);
3370                                 goto train_done;
3371                         }
3372                         udelay(2); /* should be 1.5us */
3373                 }
3374                 if (i == 4)
3375                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3376         }
3377
3378 train_done:
3379         DRM_DEBUG_KMS("FDI train done.\n");
3380 }
3381
3382 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3383 {
3384         struct drm_device *dev = intel_crtc->base.dev;
3385         struct drm_i915_private *dev_priv = dev->dev_private;
3386         int pipe = intel_crtc->pipe;
3387         u32 reg, temp;
3388
3389
3390         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3391         reg = FDI_RX_CTL(pipe);
3392         temp = I915_READ(reg);
3393         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3394         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3395         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3396         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3397
3398         POSTING_READ(reg);
3399         udelay(200);
3400
3401         /* Switch from Rawclk to PCDclk */
3402         temp = I915_READ(reg);
3403         I915_WRITE(reg, temp | FDI_PCDCLK);
3404
3405         POSTING_READ(reg);
3406         udelay(200);
3407
3408         /* Enable CPU FDI TX PLL, always on for Ironlake */
3409         reg = FDI_TX_CTL(pipe);
3410         temp = I915_READ(reg);
3411         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3412                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3413
3414                 POSTING_READ(reg);
3415                 udelay(100);
3416         }
3417 }
3418
3419 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3420 {
3421         struct drm_device *dev = intel_crtc->base.dev;
3422         struct drm_i915_private *dev_priv = dev->dev_private;
3423         int pipe = intel_crtc->pipe;
3424         u32 reg, temp;
3425
3426         /* Switch from PCDclk to Rawclk */
3427         reg = FDI_RX_CTL(pipe);
3428         temp = I915_READ(reg);
3429         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3430
3431         /* Disable CPU FDI TX PLL */
3432         reg = FDI_TX_CTL(pipe);
3433         temp = I915_READ(reg);
3434         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3435
3436         POSTING_READ(reg);
3437         udelay(100);
3438
3439         reg = FDI_RX_CTL(pipe);
3440         temp = I915_READ(reg);
3441         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3442
3443         /* Wait for the clocks to turn off. */
3444         POSTING_READ(reg);
3445         udelay(100);
3446 }
3447
3448 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3449 {
3450         struct drm_device *dev = crtc->dev;
3451         struct drm_i915_private *dev_priv = dev->dev_private;
3452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3453         int pipe = intel_crtc->pipe;
3454         u32 reg, temp;
3455
3456         /* disable CPU FDI tx and PCH FDI rx */
3457         reg = FDI_TX_CTL(pipe);
3458         temp = I915_READ(reg);
3459         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3460         POSTING_READ(reg);
3461
3462         reg = FDI_RX_CTL(pipe);
3463         temp = I915_READ(reg);
3464         temp &= ~(0x7 << 16);
3465         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3466         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3467
3468         POSTING_READ(reg);
3469         udelay(100);
3470
3471         /* Ironlake workaround, disable clock pointer after downing FDI */
3472         if (HAS_PCH_IBX(dev))
3473                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3474
3475         /* still set train pattern 1 */
3476         reg = FDI_TX_CTL(pipe);
3477         temp = I915_READ(reg);
3478         temp &= ~FDI_LINK_TRAIN_NONE;
3479         temp |= FDI_LINK_TRAIN_PATTERN_1;
3480         I915_WRITE(reg, temp);
3481
3482         reg = FDI_RX_CTL(pipe);
3483         temp = I915_READ(reg);
3484         if (HAS_PCH_CPT(dev)) {
3485                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3486                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3487         } else {
3488                 temp &= ~FDI_LINK_TRAIN_NONE;
3489                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3490         }
3491         /* BPC in FDI rx is consistent with that in PIPECONF */
3492         temp &= ~(0x07 << 16);
3493         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3494         I915_WRITE(reg, temp);
3495
3496         POSTING_READ(reg);
3497         udelay(100);
3498 }
3499
3500 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3501 {
3502         struct intel_crtc *crtc;
3503
3504         /* Note that we don't need to be called with mode_config.lock here
3505          * as our list of CRTC objects is static for the lifetime of the
3506          * device and so cannot disappear as we iterate. Similarly, we can
3507          * happily treat the predicates as racy, atomic checks as userspace
3508          * cannot claim and pin a new fb without at least acquring the
3509          * struct_mutex and so serialising with us.
3510          */
3511         for_each_intel_crtc(dev, crtc) {
3512                 if (atomic_read(&crtc->unpin_work_count) == 0)
3513                         continue;
3514
3515                 if (crtc->unpin_work)
3516                         intel_wait_for_vblank(dev, crtc->pipe);
3517
3518                 return true;
3519         }
3520
3521         return false;
3522 }
3523
3524 static void page_flip_completed(struct intel_crtc *intel_crtc)
3525 {
3526         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3527         struct intel_unpin_work *work = intel_crtc->unpin_work;
3528
3529         /* ensure that the unpin work is consistent wrt ->pending. */
3530         smp_rmb();
3531         intel_crtc->unpin_work = NULL;
3532
3533         if (work->event)
3534                 drm_send_vblank_event(intel_crtc->base.dev,
3535                                       intel_crtc->pipe,
3536                                       work->event);
3537
3538         drm_crtc_vblank_put(&intel_crtc->base);
3539
3540         wake_up_all(&dev_priv->pending_flip_queue);
3541         queue_work(dev_priv->wq, &work->work);
3542
3543         trace_i915_flip_complete(intel_crtc->plane,
3544                                  work->pending_flip_obj);
3545 }
3546
3547 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3548 {
3549         struct drm_device *dev = crtc->dev;
3550         struct drm_i915_private *dev_priv = dev->dev_private;
3551
3552         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3553         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3554                                        !intel_crtc_has_pending_flip(crtc),
3555                                        60*HZ) == 0)) {
3556                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3557
3558                 spin_lock_irq(&dev->event_lock);
3559                 if (intel_crtc->unpin_work) {
3560                         WARN_ONCE(1, "Removing stuck page flip\n");
3561                         page_flip_completed(intel_crtc);
3562                 }
3563                 spin_unlock_irq(&dev->event_lock);
3564         }
3565
3566         if (crtc->primary->fb) {
3567                 mutex_lock(&dev->struct_mutex);
3568                 intel_finish_fb(crtc->primary->fb);
3569                 mutex_unlock(&dev->struct_mutex);
3570         }
3571 }
3572
3573 /* Program iCLKIP clock to the desired frequency */
3574 static void lpt_program_iclkip(struct drm_crtc *crtc)
3575 {
3576         struct drm_device *dev = crtc->dev;
3577         struct drm_i915_private *dev_priv = dev->dev_private;
3578         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3579         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3580         u32 temp;
3581
3582         mutex_lock(&dev_priv->dpio_lock);
3583
3584         /* It is necessary to ungate the pixclk gate prior to programming
3585          * the divisors, and gate it back when it is done.
3586          */
3587         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3588
3589         /* Disable SSCCTL */
3590         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3591                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3592                                 SBI_SSCCTL_DISABLE,
3593                         SBI_ICLK);
3594
3595         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3596         if (clock == 20000) {
3597                 auxdiv = 1;
3598                 divsel = 0x41;
3599                 phaseinc = 0x20;
3600         } else {
3601                 /* The iCLK virtual clock root frequency is in MHz,
3602                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3603                  * divisors, it is necessary to divide one by another, so we
3604                  * convert the virtual clock precision to KHz here for higher
3605                  * precision.
3606                  */
3607                 u32 iclk_virtual_root_freq = 172800 * 1000;
3608                 u32 iclk_pi_range = 64;
3609                 u32 desired_divisor, msb_divisor_value, pi_value;
3610
3611                 desired_divisor = (iclk_virtual_root_freq / clock);
3612                 msb_divisor_value = desired_divisor / iclk_pi_range;
3613                 pi_value = desired_divisor % iclk_pi_range;
3614
3615                 auxdiv = 0;
3616                 divsel = msb_divisor_value - 2;
3617                 phaseinc = pi_value;
3618         }
3619
3620         /* This should not happen with any sane values */
3621         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3622                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3623         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3624                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3625
3626         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3627                         clock,
3628                         auxdiv,
3629                         divsel,
3630                         phasedir,
3631                         phaseinc);
3632
3633         /* Program SSCDIVINTPHASE6 */
3634         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3635         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3636         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3637         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3638         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3639         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3640         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3641         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3642
3643         /* Program SSCAUXDIV */
3644         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3645         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3646         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3647         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3648
3649         /* Enable modulator and associated divider */
3650         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3651         temp &= ~SBI_SSCCTL_DISABLE;
3652         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3653
3654         /* Wait for initialization time */
3655         udelay(24);
3656
3657         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3658
3659         mutex_unlock(&dev_priv->dpio_lock);
3660 }
3661
3662 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3663                                                 enum pipe pch_transcoder)
3664 {
3665         struct drm_device *dev = crtc->base.dev;
3666         struct drm_i915_private *dev_priv = dev->dev_private;
3667         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3668
3669         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3670                    I915_READ(HTOTAL(cpu_transcoder)));
3671         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3672                    I915_READ(HBLANK(cpu_transcoder)));
3673         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3674                    I915_READ(HSYNC(cpu_transcoder)));
3675
3676         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3677                    I915_READ(VTOTAL(cpu_transcoder)));
3678         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3679                    I915_READ(VBLANK(cpu_transcoder)));
3680         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3681                    I915_READ(VSYNC(cpu_transcoder)));
3682         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3683                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3684 }
3685
3686 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3687 {
3688         struct drm_i915_private *dev_priv = dev->dev_private;
3689         uint32_t temp;
3690
3691         temp = I915_READ(SOUTH_CHICKEN1);
3692         if (temp & FDI_BC_BIFURCATION_SELECT)
3693                 return;
3694
3695         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3696         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3697
3698         temp |= FDI_BC_BIFURCATION_SELECT;
3699         DRM_DEBUG_KMS("enabling fdi C rx\n");
3700         I915_WRITE(SOUTH_CHICKEN1, temp);
3701         POSTING_READ(SOUTH_CHICKEN1);
3702 }
3703
3704 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3705 {
3706         struct drm_device *dev = intel_crtc->base.dev;
3707         struct drm_i915_private *dev_priv = dev->dev_private;
3708
3709         switch (intel_crtc->pipe) {
3710         case PIPE_A:
3711                 break;
3712         case PIPE_B:
3713                 if (intel_crtc->config.fdi_lanes > 2)
3714                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3715                 else
3716                         cpt_enable_fdi_bc_bifurcation(dev);
3717
3718                 break;
3719         case PIPE_C:
3720                 cpt_enable_fdi_bc_bifurcation(dev);
3721
3722                 break;
3723         default:
3724                 BUG();
3725         }
3726 }
3727
3728 /*
3729  * Enable PCH resources required for PCH ports:
3730  *   - PCH PLLs
3731  *   - FDI training & RX/TX
3732  *   - update transcoder timings
3733  *   - DP transcoding bits
3734  *   - transcoder
3735  */
3736 static void ironlake_pch_enable(struct drm_crtc *crtc)
3737 {
3738         struct drm_device *dev = crtc->dev;
3739         struct drm_i915_private *dev_priv = dev->dev_private;
3740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741         int pipe = intel_crtc->pipe;
3742         u32 reg, temp;
3743
3744         assert_pch_transcoder_disabled(dev_priv, pipe);
3745
3746         if (IS_IVYBRIDGE(dev))
3747                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3748
3749         /* Write the TU size bits before fdi link training, so that error
3750          * detection works. */
3751         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3752                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3753
3754         /* For PCH output, training FDI link */
3755         dev_priv->display.fdi_link_train(crtc);
3756
3757         /* We need to program the right clock selection before writing the pixel
3758          * mutliplier into the DPLL. */
3759         if (HAS_PCH_CPT(dev)) {
3760                 u32 sel;
3761
3762                 temp = I915_READ(PCH_DPLL_SEL);
3763                 temp |= TRANS_DPLL_ENABLE(pipe);
3764                 sel = TRANS_DPLLB_SEL(pipe);
3765                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3766                         temp |= sel;
3767                 else
3768                         temp &= ~sel;
3769                 I915_WRITE(PCH_DPLL_SEL, temp);
3770         }
3771
3772         /* XXX: pch pll's can be enabled any time before we enable the PCH
3773          * transcoder, and we actually should do this to not upset any PCH
3774          * transcoder that already use the clock when we share it.
3775          *
3776          * Note that enable_shared_dpll tries to do the right thing, but
3777          * get_shared_dpll unconditionally resets the pll - we need that to have
3778          * the right LVDS enable sequence. */
3779         intel_enable_shared_dpll(intel_crtc);
3780
3781         /* set transcoder timing, panel must allow it */
3782         assert_panel_unlocked(dev_priv, pipe);
3783         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3784
3785         intel_fdi_normal_train(crtc);
3786
3787         /* For PCH DP, enable TRANS_DP_CTL */
3788         if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3789                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3790                 reg = TRANS_DP_CTL(pipe);
3791                 temp = I915_READ(reg);
3792                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3793                           TRANS_DP_SYNC_MASK |
3794                           TRANS_DP_BPC_MASK);
3795                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3796                          TRANS_DP_ENH_FRAMING);
3797                 temp |= bpc << 9; /* same format but at 11:9 */
3798
3799                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3800                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3801                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3802                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3803
3804                 switch (intel_trans_dp_port_sel(crtc)) {
3805                 case PCH_DP_B:
3806                         temp |= TRANS_DP_PORT_SEL_B;
3807                         break;
3808                 case PCH_DP_C:
3809                         temp |= TRANS_DP_PORT_SEL_C;
3810                         break;
3811                 case PCH_DP_D:
3812                         temp |= TRANS_DP_PORT_SEL_D;
3813                         break;
3814                 default:
3815                         BUG();
3816                 }
3817
3818                 I915_WRITE(reg, temp);
3819         }
3820
3821         ironlake_enable_pch_transcoder(dev_priv, pipe);
3822 }
3823
3824 static void lpt_pch_enable(struct drm_crtc *crtc)
3825 {
3826         struct drm_device *dev = crtc->dev;
3827         struct drm_i915_private *dev_priv = dev->dev_private;
3828         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3829         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3830
3831         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3832
3833         lpt_program_iclkip(crtc);
3834
3835         /* Set transcoder timing. */
3836         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3837
3838         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3839 }
3840
3841 void intel_put_shared_dpll(struct intel_crtc *crtc)
3842 {
3843         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3844
3845         if (pll == NULL)
3846                 return;
3847
3848         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3849                 WARN(1, "bad %s crtc mask\n", pll->name);
3850                 return;
3851         }
3852
3853         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3854         if (pll->config.crtc_mask == 0) {
3855                 WARN_ON(pll->on);
3856                 WARN_ON(pll->active);
3857         }
3858
3859         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3860 }
3861
3862 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3863 {
3864         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3865         struct intel_shared_dpll *pll;
3866         enum intel_dpll_id i;
3867
3868         if (HAS_PCH_IBX(dev_priv->dev)) {
3869                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3870                 i = (enum intel_dpll_id) crtc->pipe;
3871                 pll = &dev_priv->shared_dplls[i];
3872
3873                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3874                               crtc->base.base.id, pll->name);
3875
3876                 WARN_ON(pll->new_config->crtc_mask);
3877
3878                 goto found;
3879         }
3880
3881         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3882                 pll = &dev_priv->shared_dplls[i];
3883
3884                 /* Only want to check enabled timings first */
3885                 if (pll->new_config->crtc_mask == 0)
3886                         continue;
3887
3888                 if (memcmp(&crtc->new_config->dpll_hw_state,
3889                            &pll->new_config->hw_state,
3890                            sizeof(pll->new_config->hw_state)) == 0) {
3891                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3892                                       crtc->base.base.id, pll->name,
3893                                       pll->new_config->crtc_mask,
3894                                       pll->active);
3895                         goto found;
3896                 }
3897         }
3898
3899         /* Ok no matching timings, maybe there's a free one? */
3900         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3901                 pll = &dev_priv->shared_dplls[i];
3902                 if (pll->new_config->crtc_mask == 0) {
3903                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3904                                       crtc->base.base.id, pll->name);
3905                         goto found;
3906                 }
3907         }
3908
3909         return NULL;
3910
3911 found:
3912         if (pll->new_config->crtc_mask == 0)
3913                 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3914
3915         crtc->new_config->shared_dpll = i;
3916         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3917                          pipe_name(crtc->pipe));
3918
3919         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3920
3921         return pll;
3922 }
3923
3924 /**
3925  * intel_shared_dpll_start_config - start a new PLL staged config
3926  * @dev_priv: DRM device
3927  * @clear_pipes: mask of pipes that will have their PLLs freed
3928  *
3929  * Starts a new PLL staged config, copying the current config but
3930  * releasing the references of pipes specified in clear_pipes.
3931  */
3932 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3933                                           unsigned clear_pipes)
3934 {
3935         struct intel_shared_dpll *pll;
3936         enum intel_dpll_id i;
3937
3938         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3939                 pll = &dev_priv->shared_dplls[i];
3940
3941                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3942                                           GFP_KERNEL);
3943                 if (!pll->new_config)
3944                         goto cleanup;
3945
3946                 pll->new_config->crtc_mask &= ~clear_pipes;
3947         }
3948
3949         return 0;
3950
3951 cleanup:
3952         while (--i >= 0) {
3953                 pll = &dev_priv->shared_dplls[i];
3954                 kfree(pll->new_config);
3955                 pll->new_config = NULL;
3956         }
3957
3958         return -ENOMEM;
3959 }
3960
3961 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3962 {
3963         struct intel_shared_dpll *pll;
3964         enum intel_dpll_id i;
3965
3966         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3967                 pll = &dev_priv->shared_dplls[i];
3968
3969                 WARN_ON(pll->new_config == &pll->config);
3970
3971                 pll->config = *pll->new_config;
3972                 kfree(pll->new_config);
3973                 pll->new_config = NULL;
3974         }
3975 }
3976
3977 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3978 {
3979         struct intel_shared_dpll *pll;
3980         enum intel_dpll_id i;
3981
3982         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3983                 pll = &dev_priv->shared_dplls[i];
3984
3985                 WARN_ON(pll->new_config == &pll->config);
3986
3987                 kfree(pll->new_config);
3988                 pll->new_config = NULL;
3989         }
3990 }
3991
3992 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3993 {
3994         struct drm_i915_private *dev_priv = dev->dev_private;
3995         int dslreg = PIPEDSL(pipe);
3996         u32 temp;
3997
3998         temp = I915_READ(dslreg);
3999         udelay(500);
4000         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4001                 if (wait_for(I915_READ(dslreg) != temp, 5))
4002                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4003         }
4004 }
4005
4006 static void skylake_pfit_enable(struct intel_crtc *crtc)
4007 {
4008         struct drm_device *dev = crtc->base.dev;
4009         struct drm_i915_private *dev_priv = dev->dev_private;
4010         int pipe = crtc->pipe;
4011
4012         if (crtc->config.pch_pfit.enabled) {
4013                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4014                 I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4015                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4016         }
4017 }
4018
4019 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4020 {
4021         struct drm_device *dev = crtc->base.dev;
4022         struct drm_i915_private *dev_priv = dev->dev_private;
4023         int pipe = crtc->pipe;
4024
4025         if (crtc->config.pch_pfit.enabled) {
4026                 /* Force use of hard-coded filter coefficients
4027                  * as some pre-programmed values are broken,
4028                  * e.g. x201.
4029                  */
4030                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4031                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4032                                                  PF_PIPE_SEL_IVB(pipe));
4033                 else
4034                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4035                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4036                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4037         }
4038 }
4039
4040 static void intel_enable_planes(struct drm_crtc *crtc)
4041 {
4042         struct drm_device *dev = crtc->dev;
4043         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4044         struct drm_plane *plane;
4045         struct intel_plane *intel_plane;
4046
4047         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4048                 intel_plane = to_intel_plane(plane);
4049                 if (intel_plane->pipe == pipe)
4050                         intel_plane_restore(&intel_plane->base);
4051         }
4052 }
4053
4054 static void intel_disable_planes(struct drm_crtc *crtc)
4055 {
4056         struct drm_device *dev = crtc->dev;
4057         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4058         struct drm_plane *plane;
4059         struct intel_plane *intel_plane;
4060
4061         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4062                 intel_plane = to_intel_plane(plane);
4063                 if (intel_plane->pipe == pipe)
4064                         intel_plane_disable(&intel_plane->base);
4065         }
4066 }
4067
4068 void hsw_enable_ips(struct intel_crtc *crtc)
4069 {
4070         struct drm_device *dev = crtc->base.dev;
4071         struct drm_i915_private *dev_priv = dev->dev_private;
4072
4073         if (!crtc->config.ips_enabled)
4074                 return;
4075
4076         /* We can only enable IPS after we enable a plane and wait for a vblank */
4077         intel_wait_for_vblank(dev, crtc->pipe);
4078
4079         assert_plane_enabled(dev_priv, crtc->plane);
4080         if (IS_BROADWELL(dev)) {
4081                 mutex_lock(&dev_priv->rps.hw_lock);
4082                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4083                 mutex_unlock(&dev_priv->rps.hw_lock);
4084                 /* Quoting Art Runyan: "its not safe to expect any particular
4085                  * value in IPS_CTL bit 31 after enabling IPS through the
4086                  * mailbox." Moreover, the mailbox may return a bogus state,
4087                  * so we need to just enable it and continue on.
4088                  */
4089         } else {
4090                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4091                 /* The bit only becomes 1 in the next vblank, so this wait here
4092                  * is essentially intel_wait_for_vblank. If we don't have this
4093                  * and don't wait for vblanks until the end of crtc_enable, then
4094                  * the HW state readout code will complain that the expected
4095                  * IPS_CTL value is not the one we read. */
4096                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4097                         DRM_ERROR("Timed out waiting for IPS enable\n");
4098         }
4099 }
4100
4101 void hsw_disable_ips(struct intel_crtc *crtc)
4102 {
4103         struct drm_device *dev = crtc->base.dev;
4104         struct drm_i915_private *dev_priv = dev->dev_private;
4105
4106         if (!crtc->config.ips_enabled)
4107                 return;
4108
4109         assert_plane_enabled(dev_priv, crtc->plane);
4110         if (IS_BROADWELL(dev)) {
4111                 mutex_lock(&dev_priv->rps.hw_lock);
4112                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4113                 mutex_unlock(&dev_priv->rps.hw_lock);
4114                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4115                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4116                         DRM_ERROR("Timed out waiting for IPS disable\n");
4117         } else {
4118                 I915_WRITE(IPS_CTL, 0);
4119                 POSTING_READ(IPS_CTL);
4120         }
4121
4122         /* We need to wait for a vblank before we can disable the plane. */
4123         intel_wait_for_vblank(dev, crtc->pipe);
4124 }
4125
4126 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4127 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4128 {
4129         struct drm_device *dev = crtc->dev;
4130         struct drm_i915_private *dev_priv = dev->dev_private;
4131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4132         enum pipe pipe = intel_crtc->pipe;
4133         int palreg = PALETTE(pipe);
4134         int i;
4135         bool reenable_ips = false;
4136
4137         /* The clocks have to be on to load the palette. */
4138         if (!crtc->enabled || !intel_crtc->active)
4139                 return;
4140
4141         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4142                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4143                         assert_dsi_pll_enabled(dev_priv);
4144                 else
4145                         assert_pll_enabled(dev_priv, pipe);
4146         }
4147
4148         /* use legacy palette for Ironlake */
4149         if (!HAS_GMCH_DISPLAY(dev))
4150                 palreg = LGC_PALETTE(pipe);
4151
4152         /* Workaround : Do not read or write the pipe palette/gamma data while
4153          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4154          */
4155         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4156             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4157              GAMMA_MODE_MODE_SPLIT)) {
4158                 hsw_disable_ips(intel_crtc);
4159                 reenable_ips = true;
4160         }
4161
4162         for (i = 0; i < 256; i++) {
4163                 I915_WRITE(palreg + 4 * i,
4164                            (intel_crtc->lut_r[i] << 16) |
4165                            (intel_crtc->lut_g[i] << 8) |
4166                            intel_crtc->lut_b[i]);
4167         }
4168
4169         if (reenable_ips)
4170                 hsw_enable_ips(intel_crtc);
4171 }
4172
4173 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4174 {
4175         if (!enable && intel_crtc->overlay) {
4176                 struct drm_device *dev = intel_crtc->base.dev;
4177                 struct drm_i915_private *dev_priv = dev->dev_private;
4178
4179                 mutex_lock(&dev->struct_mutex);
4180                 dev_priv->mm.interruptible = false;
4181                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4182                 dev_priv->mm.interruptible = true;
4183                 mutex_unlock(&dev->struct_mutex);
4184         }
4185
4186         /* Let userspace switch the overlay on again. In most cases userspace
4187          * has to recompute where to put it anyway.
4188          */
4189 }
4190
4191 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4192 {
4193         struct drm_device *dev = crtc->dev;
4194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4195         int pipe = intel_crtc->pipe;
4196
4197         intel_enable_primary_hw_plane(crtc->primary, crtc);
4198         intel_enable_planes(crtc);
4199         intel_crtc_update_cursor(crtc, true);
4200         intel_crtc_dpms_overlay(intel_crtc, true);
4201
4202         hsw_enable_ips(intel_crtc);
4203
4204         mutex_lock(&dev->struct_mutex);
4205         intel_update_fbc(dev);
4206         mutex_unlock(&dev->struct_mutex);
4207
4208         /*
4209          * FIXME: Once we grow proper nuclear flip support out of this we need
4210          * to compute the mask of flip planes precisely. For the time being
4211          * consider this a flip from a NULL plane.
4212          */
4213         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4214 }
4215
4216 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4217 {
4218         struct drm_device *dev = crtc->dev;
4219         struct drm_i915_private *dev_priv = dev->dev_private;
4220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4221         int pipe = intel_crtc->pipe;
4222         int plane = intel_crtc->plane;
4223
4224         intel_crtc_wait_for_pending_flips(crtc);
4225
4226         if (dev_priv->fbc.plane == plane)
4227                 intel_disable_fbc(dev);
4228
4229         hsw_disable_ips(intel_crtc);
4230
4231         intel_crtc_dpms_overlay(intel_crtc, false);
4232         intel_crtc_update_cursor(crtc, false);
4233         intel_disable_planes(crtc);
4234         intel_disable_primary_hw_plane(crtc->primary, crtc);
4235
4236         /*
4237          * FIXME: Once we grow proper nuclear flip support out of this we need
4238          * to compute the mask of flip planes precisely. For the time being
4239          * consider this a flip to a NULL plane.
4240          */
4241         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4242 }
4243
4244 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4245 {
4246         struct drm_device *dev = crtc->dev;
4247         struct drm_i915_private *dev_priv = dev->dev_private;
4248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4249         struct intel_encoder *encoder;
4250         int pipe = intel_crtc->pipe;
4251
4252         WARN_ON(!crtc->enabled);
4253
4254         if (intel_crtc->active)
4255                 return;
4256
4257         if (intel_crtc->config.has_pch_encoder)
4258                 intel_prepare_shared_dpll(intel_crtc);
4259
4260         if (intel_crtc->config.has_dp_encoder)
4261                 intel_dp_set_m_n(intel_crtc);
4262
4263         intel_set_pipe_timings(intel_crtc);
4264
4265         if (intel_crtc->config.has_pch_encoder) {
4266                 intel_cpu_transcoder_set_m_n(intel_crtc,
4267                                      &intel_crtc->config.fdi_m_n, NULL);
4268         }
4269
4270         ironlake_set_pipeconf(crtc);
4271
4272         intel_crtc->active = true;
4273
4274         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4275         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4276
4277         for_each_encoder_on_crtc(dev, crtc, encoder)
4278                 if (encoder->pre_enable)
4279                         encoder->pre_enable(encoder);
4280
4281         if (intel_crtc->config.has_pch_encoder) {
4282                 /* Note: FDI PLL enabling _must_ be done before we enable the
4283                  * cpu pipes, hence this is separate from all the other fdi/pch
4284                  * enabling. */
4285                 ironlake_fdi_pll_enable(intel_crtc);
4286         } else {
4287                 assert_fdi_tx_disabled(dev_priv, pipe);
4288                 assert_fdi_rx_disabled(dev_priv, pipe);
4289         }
4290
4291         ironlake_pfit_enable(intel_crtc);
4292
4293         /*
4294          * On ILK+ LUT must be loaded before the pipe is running but with
4295          * clocks enabled
4296          */
4297         intel_crtc_load_lut(crtc);
4298
4299         intel_update_watermarks(crtc);
4300         intel_enable_pipe(intel_crtc);
4301
4302         if (intel_crtc->config.has_pch_encoder)
4303                 ironlake_pch_enable(crtc);
4304
4305         for_each_encoder_on_crtc(dev, crtc, encoder)
4306                 encoder->enable(encoder);
4307
4308         if (HAS_PCH_CPT(dev))
4309                 cpt_verify_modeset(dev, intel_crtc->pipe);
4310
4311         assert_vblank_disabled(crtc);
4312         drm_crtc_vblank_on(crtc);
4313
4314         intel_crtc_enable_planes(crtc);
4315 }
4316
4317 /* IPS only exists on ULT machines and is tied to pipe A. */
4318 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4319 {
4320         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4321 }
4322
4323 /*
4324  * This implements the workaround described in the "notes" section of the mode
4325  * set sequence documentation. When going from no pipes or single pipe to
4326  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4327  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4328  */
4329 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4330 {
4331         struct drm_device *dev = crtc->base.dev;
4332         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4333
4334         /* We want to get the other_active_crtc only if there's only 1 other
4335          * active crtc. */
4336         for_each_intel_crtc(dev, crtc_it) {
4337                 if (!crtc_it->active || crtc_it == crtc)
4338                         continue;
4339
4340                 if (other_active_crtc)
4341                         return;
4342
4343                 other_active_crtc = crtc_it;
4344         }
4345         if (!other_active_crtc)
4346                 return;
4347
4348         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4349         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4350 }
4351
4352 static void haswell_crtc_enable(struct drm_crtc *crtc)
4353 {
4354         struct drm_device *dev = crtc->dev;
4355         struct drm_i915_private *dev_priv = dev->dev_private;
4356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4357         struct intel_encoder *encoder;
4358         int pipe = intel_crtc->pipe;
4359
4360         WARN_ON(!crtc->enabled);
4361
4362         if (intel_crtc->active)
4363                 return;
4364
4365         if (intel_crtc_to_shared_dpll(intel_crtc))
4366                 intel_enable_shared_dpll(intel_crtc);
4367
4368         if (intel_crtc->config.has_dp_encoder)
4369                 intel_dp_set_m_n(intel_crtc);
4370
4371         intel_set_pipe_timings(intel_crtc);
4372
4373         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4374                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4375                            intel_crtc->config.pixel_multiplier - 1);
4376         }
4377
4378         if (intel_crtc->config.has_pch_encoder) {
4379                 intel_cpu_transcoder_set_m_n(intel_crtc,
4380                                      &intel_crtc->config.fdi_m_n, NULL);
4381         }
4382
4383         haswell_set_pipeconf(crtc);
4384
4385         intel_set_pipe_csc(crtc);
4386
4387         intel_crtc->active = true;
4388
4389         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4390         for_each_encoder_on_crtc(dev, crtc, encoder)
4391                 if (encoder->pre_enable)
4392                         encoder->pre_enable(encoder);
4393
4394         if (intel_crtc->config.has_pch_encoder) {
4395                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4396                                                       true);
4397                 dev_priv->display.fdi_link_train(crtc);
4398         }
4399
4400         intel_ddi_enable_pipe_clock(intel_crtc);
4401
4402         if (IS_SKYLAKE(dev))
4403                 skylake_pfit_enable(intel_crtc);
4404         else
4405                 ironlake_pfit_enable(intel_crtc);
4406
4407         /*
4408          * On ILK+ LUT must be loaded before the pipe is running but with
4409          * clocks enabled
4410          */
4411         intel_crtc_load_lut(crtc);
4412
4413         intel_ddi_set_pipe_settings(crtc);
4414         intel_ddi_enable_transcoder_func(crtc);
4415
4416         intel_update_watermarks(crtc);
4417         intel_enable_pipe(intel_crtc);
4418
4419         if (intel_crtc->config.has_pch_encoder)
4420                 lpt_pch_enable(crtc);
4421
4422         if (intel_crtc->config.dp_encoder_is_mst)
4423                 intel_ddi_set_vc_payload_alloc(crtc, true);
4424
4425         for_each_encoder_on_crtc(dev, crtc, encoder) {
4426                 encoder->enable(encoder);
4427                 intel_opregion_notify_encoder(encoder, true);
4428         }
4429
4430         assert_vblank_disabled(crtc);
4431         drm_crtc_vblank_on(crtc);
4432
4433         /* If we change the relative order between pipe/planes enabling, we need
4434          * to change the workaround. */
4435         haswell_mode_set_planes_workaround(intel_crtc);
4436         intel_crtc_enable_planes(crtc);
4437 }
4438
4439 static void skylake_pfit_disable(struct intel_crtc *crtc)
4440 {
4441         struct drm_device *dev = crtc->base.dev;
4442         struct drm_i915_private *dev_priv = dev->dev_private;
4443         int pipe = crtc->pipe;
4444
4445         /* To avoid upsetting the power well on haswell only disable the pfit if
4446          * it's in use. The hw state code will make sure we get this right. */
4447         if (crtc->config.pch_pfit.enabled) {
4448                 I915_WRITE(PS_CTL(pipe), 0);
4449                 I915_WRITE(PS_WIN_POS(pipe), 0);
4450                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4451         }
4452 }
4453
4454 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4455 {
4456         struct drm_device *dev = crtc->base.dev;
4457         struct drm_i915_private *dev_priv = dev->dev_private;
4458         int pipe = crtc->pipe;
4459
4460         /* To avoid upsetting the power well on haswell only disable the pfit if
4461          * it's in use. The hw state code will make sure we get this right. */
4462         if (crtc->config.pch_pfit.enabled) {
4463                 I915_WRITE(PF_CTL(pipe), 0);
4464                 I915_WRITE(PF_WIN_POS(pipe), 0);
4465                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4466         }
4467 }
4468
4469 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4470 {
4471         struct drm_device *dev = crtc->dev;
4472         struct drm_i915_private *dev_priv = dev->dev_private;
4473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4474         struct intel_encoder *encoder;
4475         int pipe = intel_crtc->pipe;
4476         u32 reg, temp;
4477
4478         if (!intel_crtc->active)
4479                 return;
4480
4481         intel_crtc_disable_planes(crtc);
4482
4483         drm_crtc_vblank_off(crtc);
4484         assert_vblank_disabled(crtc);
4485
4486         for_each_encoder_on_crtc(dev, crtc, encoder)
4487                 encoder->disable(encoder);
4488
4489         if (intel_crtc->config.has_pch_encoder)
4490                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4491
4492         intel_disable_pipe(intel_crtc);
4493
4494         ironlake_pfit_disable(intel_crtc);
4495
4496         for_each_encoder_on_crtc(dev, crtc, encoder)
4497                 if (encoder->post_disable)
4498                         encoder->post_disable(encoder);
4499
4500         if (intel_crtc->config.has_pch_encoder) {
4501                 ironlake_fdi_disable(crtc);
4502
4503                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4504                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4505
4506                 if (HAS_PCH_CPT(dev)) {
4507                         /* disable TRANS_DP_CTL */
4508                         reg = TRANS_DP_CTL(pipe);
4509                         temp = I915_READ(reg);
4510                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4511                                   TRANS_DP_PORT_SEL_MASK);
4512                         temp |= TRANS_DP_PORT_SEL_NONE;
4513                         I915_WRITE(reg, temp);
4514
4515                         /* disable DPLL_SEL */
4516                         temp = I915_READ(PCH_DPLL_SEL);
4517                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4518                         I915_WRITE(PCH_DPLL_SEL, temp);
4519                 }
4520
4521                 /* disable PCH DPLL */
4522                 intel_disable_shared_dpll(intel_crtc);
4523
4524                 ironlake_fdi_pll_disable(intel_crtc);
4525         }
4526
4527         intel_crtc->active = false;
4528         intel_update_watermarks(crtc);
4529
4530         mutex_lock(&dev->struct_mutex);
4531         intel_update_fbc(dev);
4532         mutex_unlock(&dev->struct_mutex);
4533 }
4534
4535 static void haswell_crtc_disable(struct drm_crtc *crtc)
4536 {
4537         struct drm_device *dev = crtc->dev;
4538         struct drm_i915_private *dev_priv = dev->dev_private;
4539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4540         struct intel_encoder *encoder;
4541         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4542
4543         if (!intel_crtc->active)
4544                 return;
4545
4546         intel_crtc_disable_planes(crtc);
4547
4548         drm_crtc_vblank_off(crtc);
4549         assert_vblank_disabled(crtc);
4550
4551         for_each_encoder_on_crtc(dev, crtc, encoder) {
4552                 intel_opregion_notify_encoder(encoder, false);
4553                 encoder->disable(encoder);
4554         }
4555
4556         if (intel_crtc->config.has_pch_encoder)
4557                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4558                                                       false);
4559         intel_disable_pipe(intel_crtc);
4560
4561         if (intel_crtc->config.dp_encoder_is_mst)
4562                 intel_ddi_set_vc_payload_alloc(crtc, false);
4563
4564         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4565
4566         if (IS_SKYLAKE(dev))
4567                 skylake_pfit_disable(intel_crtc);
4568         else
4569                 ironlake_pfit_disable(intel_crtc);
4570
4571         intel_ddi_disable_pipe_clock(intel_crtc);
4572
4573         if (intel_crtc->config.has_pch_encoder) {
4574                 lpt_disable_pch_transcoder(dev_priv);
4575                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4576                                                       true);
4577                 intel_ddi_fdi_disable(crtc);
4578         }
4579
4580         for_each_encoder_on_crtc(dev, crtc, encoder)
4581                 if (encoder->post_disable)
4582                         encoder->post_disable(encoder);
4583
4584         intel_crtc->active = false;
4585         intel_update_watermarks(crtc);
4586
4587         mutex_lock(&dev->struct_mutex);
4588         intel_update_fbc(dev);
4589         mutex_unlock(&dev->struct_mutex);
4590
4591         if (intel_crtc_to_shared_dpll(intel_crtc))
4592                 intel_disable_shared_dpll(intel_crtc);
4593 }
4594
4595 static void ironlake_crtc_off(struct drm_crtc *crtc)
4596 {
4597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598         intel_put_shared_dpll(intel_crtc);
4599 }
4600
4601
4602 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4603 {
4604         struct drm_device *dev = crtc->base.dev;
4605         struct drm_i915_private *dev_priv = dev->dev_private;
4606         struct intel_crtc_config *pipe_config = &crtc->config;
4607
4608         if (!crtc->config.gmch_pfit.control)
4609                 return;
4610
4611         /*
4612          * The panel fitter should only be adjusted whilst the pipe is disabled,
4613          * according to register description and PRM.
4614          */
4615         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4616         assert_pipe_disabled(dev_priv, crtc->pipe);
4617
4618         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4619         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4620
4621         /* Border color in case we don't scale up to the full screen. Black by
4622          * default, change to something else for debugging. */
4623         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4624 }
4625
4626 static enum intel_display_power_domain port_to_power_domain(enum port port)
4627 {
4628         switch (port) {
4629         case PORT_A:
4630                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4631         case PORT_B:
4632                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4633         case PORT_C:
4634                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4635         case PORT_D:
4636                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4637         default:
4638                 WARN_ON_ONCE(1);
4639                 return POWER_DOMAIN_PORT_OTHER;
4640         }
4641 }
4642
4643 #define for_each_power_domain(domain, mask)                             \
4644         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4645                 if ((1 << (domain)) & (mask))
4646
4647 enum intel_display_power_domain
4648 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4649 {
4650         struct drm_device *dev = intel_encoder->base.dev;
4651         struct intel_digital_port *intel_dig_port;
4652
4653         switch (intel_encoder->type) {
4654         case INTEL_OUTPUT_UNKNOWN:
4655                 /* Only DDI platforms should ever use this output type */
4656                 WARN_ON_ONCE(!HAS_DDI(dev));
4657         case INTEL_OUTPUT_DISPLAYPORT:
4658         case INTEL_OUTPUT_HDMI:
4659         case INTEL_OUTPUT_EDP:
4660                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4661                 return port_to_power_domain(intel_dig_port->port);
4662         case INTEL_OUTPUT_DP_MST:
4663                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4664                 return port_to_power_domain(intel_dig_port->port);
4665         case INTEL_OUTPUT_ANALOG:
4666                 return POWER_DOMAIN_PORT_CRT;
4667         case INTEL_OUTPUT_DSI:
4668                 return POWER_DOMAIN_PORT_DSI;
4669         default:
4670                 return POWER_DOMAIN_PORT_OTHER;
4671         }
4672 }
4673
4674 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4675 {
4676         struct drm_device *dev = crtc->dev;
4677         struct intel_encoder *intel_encoder;
4678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4679         enum pipe pipe = intel_crtc->pipe;
4680         unsigned long mask;
4681         enum transcoder transcoder;
4682
4683         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4684
4685         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4686         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4687         if (intel_crtc->config.pch_pfit.enabled ||
4688             intel_crtc->config.pch_pfit.force_thru)
4689                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4690
4691         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4692                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4693
4694         return mask;
4695 }
4696
4697 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4698 {
4699         struct drm_i915_private *dev_priv = dev->dev_private;
4700         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4701         struct intel_crtc *crtc;
4702
4703         /*
4704          * First get all needed power domains, then put all unneeded, to avoid
4705          * any unnecessary toggling of the power wells.
4706          */
4707         for_each_intel_crtc(dev, crtc) {
4708                 enum intel_display_power_domain domain;
4709
4710                 if (!crtc->base.enabled)
4711                         continue;
4712
4713                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4714
4715                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4716                         intel_display_power_get(dev_priv, domain);
4717         }
4718
4719         if (dev_priv->display.modeset_global_resources)
4720                 dev_priv->display.modeset_global_resources(dev);
4721
4722         for_each_intel_crtc(dev, crtc) {
4723                 enum intel_display_power_domain domain;
4724
4725                 for_each_power_domain(domain, crtc->enabled_power_domains)
4726                         intel_display_power_put(dev_priv, domain);
4727
4728                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4729         }
4730
4731         intel_display_set_init_power(dev_priv, false);
4732 }
4733
4734 /* returns HPLL frequency in kHz */
4735 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4736 {
4737         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4738
4739         /* Obtain SKU information */
4740         mutex_lock(&dev_priv->dpio_lock);
4741         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4742                 CCK_FUSE_HPLL_FREQ_MASK;
4743         mutex_unlock(&dev_priv->dpio_lock);
4744
4745         return vco_freq[hpll_freq] * 1000;
4746 }
4747
4748 static void vlv_update_cdclk(struct drm_device *dev)
4749 {
4750         struct drm_i915_private *dev_priv = dev->dev_private;
4751
4752         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4753         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4754                          dev_priv->vlv_cdclk_freq);
4755
4756         /*
4757          * Program the gmbus_freq based on the cdclk frequency.
4758          * BSpec erroneously claims we should aim for 4MHz, but
4759          * in fact 1MHz is the correct frequency.
4760          */
4761         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4762 }
4763
4764 /* Adjust CDclk dividers to allow high res or save power if possible */
4765 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4766 {
4767         struct drm_i915_private *dev_priv = dev->dev_private;
4768         u32 val, cmd;
4769
4770         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4771
4772         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4773                 cmd = 2;
4774         else if (cdclk == 266667)
4775                 cmd = 1;
4776         else
4777                 cmd = 0;
4778
4779         mutex_lock(&dev_priv->rps.hw_lock);
4780         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4781         val &= ~DSPFREQGUAR_MASK;
4782         val |= (cmd << DSPFREQGUAR_SHIFT);
4783         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4784         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4785                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4786                      50)) {
4787                 DRM_ERROR("timed out waiting for CDclk change\n");
4788         }
4789         mutex_unlock(&dev_priv->rps.hw_lock);
4790
4791         if (cdclk == 400000) {
4792                 u32 divider;
4793
4794                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4795
4796                 mutex_lock(&dev_priv->dpio_lock);
4797                 /* adjust cdclk divider */
4798                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4799                 val &= ~DISPLAY_FREQUENCY_VALUES;
4800                 val |= divider;
4801                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4802
4803                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4804                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4805                              50))
4806                         DRM_ERROR("timed out waiting for CDclk change\n");
4807                 mutex_unlock(&dev_priv->dpio_lock);
4808         }
4809
4810         mutex_lock(&dev_priv->dpio_lock);
4811         /* adjust self-refresh exit latency value */
4812         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4813         val &= ~0x7f;
4814
4815         /*
4816          * For high bandwidth configs, we set a higher latency in the bunit
4817          * so that the core display fetch happens in time to avoid underruns.
4818          */
4819         if (cdclk == 400000)
4820                 val |= 4500 / 250; /* 4.5 usec */
4821         else
4822                 val |= 3000 / 250; /* 3.0 usec */
4823         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4824         mutex_unlock(&dev_priv->dpio_lock);
4825
4826         vlv_update_cdclk(dev);
4827 }
4828
4829 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4830 {
4831         struct drm_i915_private *dev_priv = dev->dev_private;
4832         u32 val, cmd;
4833
4834         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4835
4836         switch (cdclk) {
4837         case 400000:
4838                 cmd = 3;
4839                 break;
4840         case 333333:
4841         case 320000:
4842                 cmd = 2;
4843                 break;
4844         case 266667:
4845                 cmd = 1;
4846                 break;
4847         case 200000:
4848                 cmd = 0;
4849                 break;
4850         default:
4851                 WARN_ON(1);
4852                 return;
4853         }
4854
4855         mutex_lock(&dev_priv->rps.hw_lock);
4856         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4857         val &= ~DSPFREQGUAR_MASK_CHV;
4858         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4859         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4860         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4861                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4862                      50)) {
4863                 DRM_ERROR("timed out waiting for CDclk change\n");
4864         }
4865         mutex_unlock(&dev_priv->rps.hw_lock);
4866
4867         vlv_update_cdclk(dev);
4868 }
4869
4870 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4871                                  int max_pixclk)
4872 {
4873         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4874
4875         /* FIXME: Punit isn't quite ready yet */
4876         if (IS_CHERRYVIEW(dev_priv->dev))
4877                 return 400000;
4878
4879         /*
4880          * Really only a few cases to deal with, as only 4 CDclks are supported:
4881          *   200MHz
4882          *   267MHz
4883          *   320/333MHz (depends on HPLL freq)
4884          *   400MHz
4885          * So we check to see whether we're above 90% of the lower bin and
4886          * adjust if needed.
4887          *
4888          * We seem to get an unstable or solid color picture at 200MHz.
4889          * Not sure what's wrong. For now use 200MHz only when all pipes
4890          * are off.
4891          */
4892         if (max_pixclk > freq_320*9/10)
4893                 return 400000;
4894         else if (max_pixclk > 266667*9/10)
4895                 return freq_320;
4896         else if (max_pixclk > 0)
4897                 return 266667;
4898         else
4899                 return 200000;
4900 }
4901
4902 /* compute the max pixel clock for new configuration */
4903 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4904 {
4905         struct drm_device *dev = dev_priv->dev;
4906         struct intel_crtc *intel_crtc;
4907         int max_pixclk = 0;
4908
4909         for_each_intel_crtc(dev, intel_crtc) {
4910                 if (intel_crtc->new_enabled)
4911                         max_pixclk = max(max_pixclk,
4912                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4913         }
4914
4915         return max_pixclk;
4916 }
4917
4918 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4919                                             unsigned *prepare_pipes)
4920 {
4921         struct drm_i915_private *dev_priv = dev->dev_private;
4922         struct intel_crtc *intel_crtc;
4923         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4924
4925         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4926             dev_priv->vlv_cdclk_freq)
4927                 return;
4928
4929         /* disable/enable all currently active pipes while we change cdclk */
4930         for_each_intel_crtc(dev, intel_crtc)
4931                 if (intel_crtc->base.enabled)
4932                         *prepare_pipes |= (1 << intel_crtc->pipe);
4933 }
4934
4935 static void valleyview_modeset_global_resources(struct drm_device *dev)
4936 {
4937         struct drm_i915_private *dev_priv = dev->dev_private;
4938         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4939         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4940
4941         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4942                 if (IS_CHERRYVIEW(dev))
4943                         cherryview_set_cdclk(dev, req_cdclk);
4944                 else
4945                         valleyview_set_cdclk(dev, req_cdclk);
4946         }
4947 }
4948
4949 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4950 {
4951         struct drm_device *dev = crtc->dev;
4952         struct drm_i915_private *dev_priv = to_i915(dev);
4953         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4954         struct intel_encoder *encoder;
4955         int pipe = intel_crtc->pipe;
4956         bool is_dsi;
4957
4958         WARN_ON(!crtc->enabled);
4959
4960         if (intel_crtc->active)
4961                 return;
4962
4963         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4964
4965         if (!is_dsi) {
4966                 if (IS_CHERRYVIEW(dev))
4967                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
4968                 else
4969                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4970         }
4971
4972         if (intel_crtc->config.has_dp_encoder)
4973                 intel_dp_set_m_n(intel_crtc);
4974
4975         intel_set_pipe_timings(intel_crtc);
4976
4977         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4978                 struct drm_i915_private *dev_priv = dev->dev_private;
4979
4980                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4981                 I915_WRITE(CHV_CANVAS(pipe), 0);
4982         }
4983
4984         i9xx_set_pipeconf(intel_crtc);
4985
4986         intel_crtc->active = true;
4987
4988         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4989
4990         for_each_encoder_on_crtc(dev, crtc, encoder)
4991                 if (encoder->pre_pll_enable)
4992                         encoder->pre_pll_enable(encoder);
4993
4994         if (!is_dsi) {
4995                 if (IS_CHERRYVIEW(dev))
4996                         chv_enable_pll(intel_crtc, &intel_crtc->config);
4997                 else
4998                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
4999         }
5000
5001         for_each_encoder_on_crtc(dev, crtc, encoder)
5002                 if (encoder->pre_enable)
5003                         encoder->pre_enable(encoder);
5004
5005         i9xx_pfit_enable(intel_crtc);
5006
5007         intel_crtc_load_lut(crtc);
5008
5009         intel_update_watermarks(crtc);
5010         intel_enable_pipe(intel_crtc);
5011
5012         for_each_encoder_on_crtc(dev, crtc, encoder)
5013                 encoder->enable(encoder);
5014
5015         assert_vblank_disabled(crtc);
5016         drm_crtc_vblank_on(crtc);
5017
5018         intel_crtc_enable_planes(crtc);
5019
5020         /* Underruns don't raise interrupts, so check manually. */
5021         i9xx_check_fifo_underruns(dev_priv);
5022 }
5023
5024 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5025 {
5026         struct drm_device *dev = crtc->base.dev;
5027         struct drm_i915_private *dev_priv = dev->dev_private;
5028
5029         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
5030         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
5031 }
5032
5033 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5034 {
5035         struct drm_device *dev = crtc->dev;
5036         struct drm_i915_private *dev_priv = to_i915(dev);
5037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5038         struct intel_encoder *encoder;
5039         int pipe = intel_crtc->pipe;
5040
5041         WARN_ON(!crtc->enabled);
5042
5043         if (intel_crtc->active)
5044                 return;
5045
5046         i9xx_set_pll_dividers(intel_crtc);
5047
5048         if (intel_crtc->config.has_dp_encoder)
5049                 intel_dp_set_m_n(intel_crtc);
5050
5051         intel_set_pipe_timings(intel_crtc);
5052
5053         i9xx_set_pipeconf(intel_crtc);
5054
5055         intel_crtc->active = true;
5056
5057         if (!IS_GEN2(dev))
5058                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5059
5060         for_each_encoder_on_crtc(dev, crtc, encoder)
5061                 if (encoder->pre_enable)
5062                         encoder->pre_enable(encoder);
5063
5064         i9xx_enable_pll(intel_crtc);
5065
5066         i9xx_pfit_enable(intel_crtc);
5067
5068         intel_crtc_load_lut(crtc);
5069
5070         intel_update_watermarks(crtc);
5071         intel_enable_pipe(intel_crtc);
5072
5073         for_each_encoder_on_crtc(dev, crtc, encoder)
5074                 encoder->enable(encoder);
5075
5076         assert_vblank_disabled(crtc);
5077         drm_crtc_vblank_on(crtc);
5078
5079         intel_crtc_enable_planes(crtc);
5080
5081         /*
5082          * Gen2 reports pipe underruns whenever all planes are disabled.
5083          * So don't enable underrun reporting before at least some planes
5084          * are enabled.
5085          * FIXME: Need to fix the logic to work when we turn off all planes
5086          * but leave the pipe running.
5087          */
5088         if (IS_GEN2(dev))
5089                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5090
5091         /* Underruns don't raise interrupts, so check manually. */
5092         i9xx_check_fifo_underruns(dev_priv);
5093 }
5094
5095 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5096 {
5097         struct drm_device *dev = crtc->base.dev;
5098         struct drm_i915_private *dev_priv = dev->dev_private;
5099
5100         if (!crtc->config.gmch_pfit.control)
5101                 return;
5102
5103         assert_pipe_disabled(dev_priv, crtc->pipe);
5104
5105         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5106                          I915_READ(PFIT_CONTROL));
5107         I915_WRITE(PFIT_CONTROL, 0);
5108 }
5109
5110 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5111 {
5112         struct drm_device *dev = crtc->dev;
5113         struct drm_i915_private *dev_priv = dev->dev_private;
5114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5115         struct intel_encoder *encoder;
5116         int pipe = intel_crtc->pipe;
5117
5118         if (!intel_crtc->active)
5119                 return;
5120
5121         /*
5122          * Gen2 reports pipe underruns whenever all planes are disabled.
5123          * So diasble underrun reporting before all the planes get disabled.
5124          * FIXME: Need to fix the logic to work when we turn off all planes
5125          * but leave the pipe running.
5126          */
5127         if (IS_GEN2(dev))
5128                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5129
5130         /*
5131          * Vblank time updates from the shadow to live plane control register
5132          * are blocked if the memory self-refresh mode is active at that
5133          * moment. So to make sure the plane gets truly disabled, disable
5134          * first the self-refresh mode. The self-refresh enable bit in turn
5135          * will be checked/applied by the HW only at the next frame start
5136          * event which is after the vblank start event, so we need to have a
5137          * wait-for-vblank between disabling the plane and the pipe.
5138          */
5139         intel_set_memory_cxsr(dev_priv, false);
5140         intel_crtc_disable_planes(crtc);
5141
5142         /*
5143          * On gen2 planes are double buffered but the pipe isn't, so we must
5144          * wait for planes to fully turn off before disabling the pipe.
5145          * We also need to wait on all gmch platforms because of the
5146          * self-refresh mode constraint explained above.
5147          */
5148         intel_wait_for_vblank(dev, pipe);
5149
5150         drm_crtc_vblank_off(crtc);
5151         assert_vblank_disabled(crtc);
5152
5153         for_each_encoder_on_crtc(dev, crtc, encoder)
5154                 encoder->disable(encoder);
5155
5156         intel_disable_pipe(intel_crtc);
5157
5158         i9xx_pfit_disable(intel_crtc);
5159
5160         for_each_encoder_on_crtc(dev, crtc, encoder)
5161                 if (encoder->post_disable)
5162                         encoder->post_disable(encoder);
5163
5164         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5165                 if (IS_CHERRYVIEW(dev))
5166                         chv_disable_pll(dev_priv, pipe);
5167                 else if (IS_VALLEYVIEW(dev))
5168                         vlv_disable_pll(dev_priv, pipe);
5169                 else
5170                         i9xx_disable_pll(intel_crtc);
5171         }
5172
5173         if (!IS_GEN2(dev))
5174                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5175
5176         intel_crtc->active = false;
5177         intel_update_watermarks(crtc);
5178
5179         mutex_lock(&dev->struct_mutex);
5180         intel_update_fbc(dev);
5181         mutex_unlock(&dev->struct_mutex);
5182 }
5183
5184 static void i9xx_crtc_off(struct drm_crtc *crtc)
5185 {
5186 }
5187
5188 /* Master function to enable/disable CRTC and corresponding power wells */
5189 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5190 {
5191         struct drm_device *dev = crtc->dev;
5192         struct drm_i915_private *dev_priv = dev->dev_private;
5193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5194         enum intel_display_power_domain domain;
5195         unsigned long domains;
5196
5197         if (enable) {
5198                 if (!intel_crtc->active) {
5199                         domains = get_crtc_power_domains(crtc);
5200                         for_each_power_domain(domain, domains)
5201                                 intel_display_power_get(dev_priv, domain);
5202                         intel_crtc->enabled_power_domains = domains;
5203
5204                         dev_priv->display.crtc_enable(crtc);
5205                 }
5206         } else {
5207                 if (intel_crtc->active) {
5208                         dev_priv->display.crtc_disable(crtc);
5209
5210                         domains = intel_crtc->enabled_power_domains;
5211                         for_each_power_domain(domain, domains)
5212                                 intel_display_power_put(dev_priv, domain);
5213                         intel_crtc->enabled_power_domains = 0;
5214                 }
5215         }
5216 }
5217
5218 /**
5219  * Sets the power management mode of the pipe and plane.
5220  */
5221 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5222 {
5223         struct drm_device *dev = crtc->dev;
5224         struct intel_encoder *intel_encoder;
5225         bool enable = false;
5226
5227         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5228                 enable |= intel_encoder->connectors_active;
5229
5230         intel_crtc_control(crtc, enable);
5231 }
5232
5233 static void intel_crtc_disable(struct drm_crtc *crtc)
5234 {
5235         struct drm_device *dev = crtc->dev;
5236         struct drm_connector *connector;
5237         struct drm_i915_private *dev_priv = dev->dev_private;
5238         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5239         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5240
5241         /* crtc should still be enabled when we disable it. */
5242         WARN_ON(!crtc->enabled);
5243
5244         dev_priv->display.crtc_disable(crtc);
5245         dev_priv->display.off(crtc);
5246
5247         if (crtc->primary->fb) {
5248                 mutex_lock(&dev->struct_mutex);
5249                 intel_unpin_fb_obj(old_obj);
5250                 i915_gem_track_fb(old_obj, NULL,
5251                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5252                 mutex_unlock(&dev->struct_mutex);
5253                 crtc->primary->fb = NULL;
5254         }
5255
5256         /* Update computed state. */
5257         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5258                 if (!connector->encoder || !connector->encoder->crtc)
5259                         continue;
5260
5261                 if (connector->encoder->crtc != crtc)
5262                         continue;
5263
5264                 connector->dpms = DRM_MODE_DPMS_OFF;
5265                 to_intel_encoder(connector->encoder)->connectors_active = false;
5266         }
5267 }
5268
5269 void intel_encoder_destroy(struct drm_encoder *encoder)
5270 {
5271         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5272
5273         drm_encoder_cleanup(encoder);
5274         kfree(intel_encoder);
5275 }
5276
5277 /* Simple dpms helper for encoders with just one connector, no cloning and only
5278  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5279  * state of the entire output pipe. */
5280 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5281 {
5282         if (mode == DRM_MODE_DPMS_ON) {
5283                 encoder->connectors_active = true;
5284
5285                 intel_crtc_update_dpms(encoder->base.crtc);
5286         } else {
5287                 encoder->connectors_active = false;
5288
5289                 intel_crtc_update_dpms(encoder->base.crtc);
5290         }
5291 }
5292
5293 /* Cross check the actual hw state with our own modeset state tracking (and it's
5294  * internal consistency). */
5295 static void intel_connector_check_state(struct intel_connector *connector)
5296 {
5297         if (connector->get_hw_state(connector)) {
5298                 struct intel_encoder *encoder = connector->encoder;
5299                 struct drm_crtc *crtc;
5300                 bool encoder_enabled;
5301                 enum pipe pipe;
5302
5303                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5304                               connector->base.base.id,
5305                               connector->base.name);
5306
5307                 /* there is no real hw state for MST connectors */
5308                 if (connector->mst_port)
5309                         return;
5310
5311                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5312                      "wrong connector dpms state\n");
5313                 WARN(connector->base.encoder != &encoder->base,
5314                      "active connector not linked to encoder\n");
5315
5316                 if (encoder) {
5317                         WARN(!encoder->connectors_active,
5318                              "encoder->connectors_active not set\n");
5319
5320                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5321                         WARN(!encoder_enabled, "encoder not enabled\n");
5322                         if (WARN_ON(!encoder->base.crtc))
5323                                 return;
5324
5325                         crtc = encoder->base.crtc;
5326
5327                         WARN(!crtc->enabled, "crtc not enabled\n");
5328                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5329                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5330                              "encoder active on the wrong pipe\n");
5331                 }
5332         }
5333 }
5334
5335 /* Even simpler default implementation, if there's really no special case to
5336  * consider. */
5337 void intel_connector_dpms(struct drm_connector *connector, int mode)
5338 {
5339         /* All the simple cases only support two dpms states. */
5340         if (mode != DRM_MODE_DPMS_ON)
5341                 mode = DRM_MODE_DPMS_OFF;
5342
5343         if (mode == connector->dpms)
5344                 return;
5345
5346         connector->dpms = mode;
5347
5348         /* Only need to change hw state when actually enabled */
5349         if (connector->encoder)
5350                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5351
5352         intel_modeset_check_state(connector->dev);
5353 }
5354
5355 /* Simple connector->get_hw_state implementation for encoders that support only
5356  * one connector and no cloning and hence the encoder state determines the state
5357  * of the connector. */
5358 bool intel_connector_get_hw_state(struct intel_connector *connector)
5359 {
5360         enum pipe pipe = 0;
5361         struct intel_encoder *encoder = connector->encoder;
5362
5363         return encoder->get_hw_state(encoder, &pipe);
5364 }
5365
5366 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5367                                      struct intel_crtc_config *pipe_config)
5368 {
5369         struct drm_i915_private *dev_priv = dev->dev_private;
5370         struct intel_crtc *pipe_B_crtc =
5371                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5372
5373         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5374                       pipe_name(pipe), pipe_config->fdi_lanes);
5375         if (pipe_config->fdi_lanes > 4) {
5376                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5377                               pipe_name(pipe), pipe_config->fdi_lanes);
5378                 return false;
5379         }
5380
5381         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5382                 if (pipe_config->fdi_lanes > 2) {
5383                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5384                                       pipe_config->fdi_lanes);
5385                         return false;
5386                 } else {
5387                         return true;
5388                 }
5389         }
5390
5391         if (INTEL_INFO(dev)->num_pipes == 2)
5392                 return true;
5393
5394         /* Ivybridge 3 pipe is really complicated */
5395         switch (pipe) {
5396         case PIPE_A:
5397                 return true;
5398         case PIPE_B:
5399                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5400                     pipe_config->fdi_lanes > 2) {
5401                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5402                                       pipe_name(pipe), pipe_config->fdi_lanes);
5403                         return false;
5404                 }
5405                 return true;
5406         case PIPE_C:
5407                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5408                     pipe_B_crtc->config.fdi_lanes <= 2) {
5409                         if (pipe_config->fdi_lanes > 2) {
5410                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5411                                               pipe_name(pipe), pipe_config->fdi_lanes);
5412                                 return false;
5413                         }
5414                 } else {
5415                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5416                         return false;
5417                 }
5418                 return true;
5419         default:
5420                 BUG();
5421         }
5422 }
5423
5424 #define RETRY 1
5425 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5426                                        struct intel_crtc_config *pipe_config)
5427 {
5428         struct drm_device *dev = intel_crtc->base.dev;
5429         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5430         int lane, link_bw, fdi_dotclock;
5431         bool setup_ok, needs_recompute = false;
5432
5433 retry:
5434         /* FDI is a binary signal running at ~2.7GHz, encoding
5435          * each output octet as 10 bits. The actual frequency
5436          * is stored as a divider into a 100MHz clock, and the
5437          * mode pixel clock is stored in units of 1KHz.
5438          * Hence the bw of each lane in terms of the mode signal
5439          * is:
5440          */
5441         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5442
5443         fdi_dotclock = adjusted_mode->crtc_clock;
5444
5445         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5446                                            pipe_config->pipe_bpp);
5447
5448         pipe_config->fdi_lanes = lane;
5449
5450         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5451                                link_bw, &pipe_config->fdi_m_n);
5452
5453         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5454                                             intel_crtc->pipe, pipe_config);
5455         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5456                 pipe_config->pipe_bpp -= 2*3;
5457                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5458                               pipe_config->pipe_bpp);
5459                 needs_recompute = true;
5460                 pipe_config->bw_constrained = true;
5461
5462                 goto retry;
5463         }
5464
5465         if (needs_recompute)
5466                 return RETRY;
5467
5468         return setup_ok ? 0 : -EINVAL;
5469 }
5470
5471 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5472                                    struct intel_crtc_config *pipe_config)
5473 {
5474         pipe_config->ips_enabled = i915.enable_ips &&
5475                                    hsw_crtc_supports_ips(crtc) &&
5476                                    pipe_config->pipe_bpp <= 24;
5477 }
5478
5479 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5480                                      struct intel_crtc_config *pipe_config)
5481 {
5482         struct drm_device *dev = crtc->base.dev;
5483         struct drm_i915_private *dev_priv = dev->dev_private;
5484         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5485
5486         /* FIXME should check pixel clock limits on all platforms */
5487         if (INTEL_INFO(dev)->gen < 4) {
5488                 int clock_limit =
5489                         dev_priv->display.get_display_clock_speed(dev);
5490
5491                 /*
5492                  * Enable pixel doubling when the dot clock
5493                  * is > 90% of the (display) core speed.
5494                  *
5495                  * GDG double wide on either pipe,
5496                  * otherwise pipe A only.
5497                  */
5498                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5499                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5500                         clock_limit *= 2;
5501                         pipe_config->double_wide = true;
5502                 }
5503
5504                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5505                         return -EINVAL;
5506         }
5507
5508         /*
5509          * Pipe horizontal size must be even in:
5510          * - DVO ganged mode
5511          * - LVDS dual channel mode
5512          * - Double wide pipe
5513          */
5514         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5515              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5516                 pipe_config->pipe_src_w &= ~1;
5517
5518         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5519          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5520          */
5521         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5522                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5523                 return -EINVAL;
5524
5525         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5526                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5527         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5528                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5529                  * for lvds. */
5530                 pipe_config->pipe_bpp = 8*3;
5531         }
5532
5533         if (HAS_IPS(dev))
5534                 hsw_compute_ips_config(crtc, pipe_config);
5535
5536         if (pipe_config->has_pch_encoder)
5537                 return ironlake_fdi_compute_config(crtc, pipe_config);
5538
5539         return 0;
5540 }
5541
5542 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5543 {
5544         struct drm_i915_private *dev_priv = dev->dev_private;
5545         u32 val;
5546         int divider;
5547
5548         /* FIXME: Punit isn't quite ready yet */
5549         if (IS_CHERRYVIEW(dev))
5550                 return 400000;
5551
5552         if (dev_priv->hpll_freq == 0)
5553                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5554
5555         mutex_lock(&dev_priv->dpio_lock);
5556         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5557         mutex_unlock(&dev_priv->dpio_lock);
5558
5559         divider = val & DISPLAY_FREQUENCY_VALUES;
5560
5561         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5562              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5563              "cdclk change in progress\n");
5564
5565         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5566 }
5567
5568 static int i945_get_display_clock_speed(struct drm_device *dev)
5569 {
5570         return 400000;
5571 }
5572
5573 static int i915_get_display_clock_speed(struct drm_device *dev)
5574 {
5575         return 333000;
5576 }
5577
5578 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5579 {
5580         return 200000;
5581 }
5582
5583 static int pnv_get_display_clock_speed(struct drm_device *dev)
5584 {
5585         u16 gcfgc = 0;
5586
5587         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5588
5589         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5590         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5591                 return 267000;
5592         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5593                 return 333000;
5594         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5595                 return 444000;
5596         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5597                 return 200000;
5598         default:
5599                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5600         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5601                 return 133000;
5602         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5603                 return 167000;
5604         }
5605 }
5606
5607 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5608 {
5609         u16 gcfgc = 0;
5610
5611         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5612
5613         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5614                 return 133000;
5615         else {
5616                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5617                 case GC_DISPLAY_CLOCK_333_MHZ:
5618                         return 333000;
5619                 default:
5620                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5621                         return 190000;
5622                 }
5623         }
5624 }
5625
5626 static int i865_get_display_clock_speed(struct drm_device *dev)
5627 {
5628         return 266000;
5629 }
5630
5631 static int i855_get_display_clock_speed(struct drm_device *dev)
5632 {
5633         u16 hpllcc = 0;
5634         /* Assume that the hardware is in the high speed state.  This
5635          * should be the default.
5636          */
5637         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5638         case GC_CLOCK_133_200:
5639         case GC_CLOCK_100_200:
5640                 return 200000;
5641         case GC_CLOCK_166_250:
5642                 return 250000;
5643         case GC_CLOCK_100_133:
5644                 return 133000;
5645         }
5646
5647         /* Shouldn't happen */
5648         return 0;
5649 }
5650
5651 static int i830_get_display_clock_speed(struct drm_device *dev)
5652 {
5653         return 133000;
5654 }
5655
5656 static void
5657 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5658 {
5659         while (*num > DATA_LINK_M_N_MASK ||
5660                *den > DATA_LINK_M_N_MASK) {
5661                 *num >>= 1;
5662                 *den >>= 1;
5663         }
5664 }
5665
5666 static void compute_m_n(unsigned int m, unsigned int n,
5667                         uint32_t *ret_m, uint32_t *ret_n)
5668 {
5669         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5670         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5671         intel_reduce_m_n_ratio(ret_m, ret_n);
5672 }
5673
5674 void
5675 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5676                        int pixel_clock, int link_clock,
5677                        struct intel_link_m_n *m_n)
5678 {
5679         m_n->tu = 64;
5680
5681         compute_m_n(bits_per_pixel * pixel_clock,
5682                     link_clock * nlanes * 8,
5683                     &m_n->gmch_m, &m_n->gmch_n);
5684
5685         compute_m_n(pixel_clock, link_clock,
5686                     &m_n->link_m, &m_n->link_n);
5687 }
5688
5689 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5690 {
5691         if (i915.panel_use_ssc >= 0)
5692                 return i915.panel_use_ssc != 0;
5693         return dev_priv->vbt.lvds_use_ssc
5694                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5695 }
5696
5697 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5698 {
5699         struct drm_device *dev = crtc->base.dev;
5700         struct drm_i915_private *dev_priv = dev->dev_private;
5701         int refclk;
5702
5703         if (IS_VALLEYVIEW(dev)) {
5704                 refclk = 100000;
5705         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5706             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5707                 refclk = dev_priv->vbt.lvds_ssc_freq;
5708                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5709         } else if (!IS_GEN2(dev)) {
5710                 refclk = 96000;
5711         } else {
5712                 refclk = 48000;
5713         }
5714
5715         return refclk;
5716 }
5717
5718 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5719 {
5720         return (1 << dpll->n) << 16 | dpll->m2;
5721 }
5722
5723 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5724 {
5725         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5726 }
5727
5728 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5729                                      intel_clock_t *reduced_clock)
5730 {
5731         struct drm_device *dev = crtc->base.dev;
5732         u32 fp, fp2 = 0;
5733
5734         if (IS_PINEVIEW(dev)) {
5735                 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
5736                 if (reduced_clock)
5737                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5738         } else {
5739                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
5740                 if (reduced_clock)
5741                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5742         }
5743
5744         crtc->new_config->dpll_hw_state.fp0 = fp;
5745
5746         crtc->lowfreq_avail = false;
5747         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5748             reduced_clock && i915.powersave) {
5749                 crtc->new_config->dpll_hw_state.fp1 = fp2;
5750                 crtc->lowfreq_avail = true;
5751         } else {
5752                 crtc->new_config->dpll_hw_state.fp1 = fp;
5753         }
5754 }
5755
5756 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5757                 pipe)
5758 {
5759         u32 reg_val;
5760
5761         /*
5762          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5763          * and set it to a reasonable value instead.
5764          */
5765         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5766         reg_val &= 0xffffff00;
5767         reg_val |= 0x00000030;
5768         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5769
5770         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5771         reg_val &= 0x8cffffff;
5772         reg_val = 0x8c000000;
5773         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5774
5775         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5776         reg_val &= 0xffffff00;
5777         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5778
5779         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5780         reg_val &= 0x00ffffff;
5781         reg_val |= 0xb0000000;
5782         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5783 }
5784
5785 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5786                                          struct intel_link_m_n *m_n)
5787 {
5788         struct drm_device *dev = crtc->base.dev;
5789         struct drm_i915_private *dev_priv = dev->dev_private;
5790         int pipe = crtc->pipe;
5791
5792         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5793         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5794         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5795         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5796 }
5797
5798 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5799                                          struct intel_link_m_n *m_n,
5800                                          struct intel_link_m_n *m2_n2)
5801 {
5802         struct drm_device *dev = crtc->base.dev;
5803         struct drm_i915_private *dev_priv = dev->dev_private;
5804         int pipe = crtc->pipe;
5805         enum transcoder transcoder = crtc->config.cpu_transcoder;
5806
5807         if (INTEL_INFO(dev)->gen >= 5) {
5808                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5809                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5810                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5811                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5812                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5813                  * for gen < 8) and if DRRS is supported (to make sure the
5814                  * registers are not unnecessarily accessed).
5815                  */
5816                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5817                         crtc->config.has_drrs) {
5818                         I915_WRITE(PIPE_DATA_M2(transcoder),
5819                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5820                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5821                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5822                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5823                 }
5824         } else {
5825                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5826                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5827                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5828                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5829         }
5830 }
5831
5832 void intel_dp_set_m_n(struct intel_crtc *crtc)
5833 {
5834         if (crtc->config.has_pch_encoder)
5835                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5836         else
5837                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5838                                                    &crtc->config.dp_m2_n2);
5839 }
5840
5841 static void vlv_update_pll(struct intel_crtc *crtc,
5842                            struct intel_crtc_config *pipe_config)
5843 {
5844         u32 dpll, dpll_md;
5845
5846         /*
5847          * Enable DPIO clock input. We should never disable the reference
5848          * clock for pipe B, since VGA hotplug / manual detection depends
5849          * on it.
5850          */
5851         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5852                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5853         /* We should never disable this, set it here for state tracking */
5854         if (crtc->pipe == PIPE_B)
5855                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5856         dpll |= DPLL_VCO_ENABLE;
5857         pipe_config->dpll_hw_state.dpll = dpll;
5858
5859         dpll_md = (pipe_config->pixel_multiplier - 1)
5860                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5861         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5862 }
5863
5864 static void vlv_prepare_pll(struct intel_crtc *crtc,
5865                             const struct intel_crtc_config *pipe_config)
5866 {
5867         struct drm_device *dev = crtc->base.dev;
5868         struct drm_i915_private *dev_priv = dev->dev_private;
5869         int pipe = crtc->pipe;
5870         u32 mdiv;
5871         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5872         u32 coreclk, reg_val;
5873
5874         mutex_lock(&dev_priv->dpio_lock);
5875
5876         bestn = pipe_config->dpll.n;
5877         bestm1 = pipe_config->dpll.m1;
5878         bestm2 = pipe_config->dpll.m2;
5879         bestp1 = pipe_config->dpll.p1;
5880         bestp2 = pipe_config->dpll.p2;
5881
5882         /* See eDP HDMI DPIO driver vbios notes doc */
5883
5884         /* PLL B needs special handling */
5885         if (pipe == PIPE_B)
5886                 vlv_pllb_recal_opamp(dev_priv, pipe);
5887
5888         /* Set up Tx target for periodic Rcomp update */
5889         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5890
5891         /* Disable target IRef on PLL */
5892         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5893         reg_val &= 0x00ffffff;
5894         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5895
5896         /* Disable fast lock */
5897         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5898
5899         /* Set idtafcrecal before PLL is enabled */
5900         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5901         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5902         mdiv |= ((bestn << DPIO_N_SHIFT));
5903         mdiv |= (1 << DPIO_K_SHIFT);
5904
5905         /*
5906          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5907          * but we don't support that).
5908          * Note: don't use the DAC post divider as it seems unstable.
5909          */
5910         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5911         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5912
5913         mdiv |= DPIO_ENABLE_CALIBRATION;
5914         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5915
5916         /* Set HBR and RBR LPF coefficients */
5917         if (pipe_config->port_clock == 162000 ||
5918             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5919             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5920                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5921                                  0x009f0003);
5922         else
5923                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5924                                  0x00d0000f);
5925
5926         if (crtc->config.has_dp_encoder) {
5927                 /* Use SSC source */
5928                 if (pipe == PIPE_A)
5929                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5930                                          0x0df40000);
5931                 else
5932                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5933                                          0x0df70000);
5934         } else { /* HDMI or VGA */
5935                 /* Use bend source */
5936                 if (pipe == PIPE_A)
5937                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5938                                          0x0df70000);
5939                 else
5940                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5941                                          0x0df40000);
5942         }
5943
5944         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5945         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5946         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5947             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5948                 coreclk |= 0x01000000;
5949         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5950
5951         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5952         mutex_unlock(&dev_priv->dpio_lock);
5953 }
5954
5955 static void chv_update_pll(struct intel_crtc *crtc,
5956                            struct intel_crtc_config *pipe_config)
5957 {
5958         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5959                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5960                 DPLL_VCO_ENABLE;
5961         if (crtc->pipe != PIPE_A)
5962                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5963
5964         pipe_config->dpll_hw_state.dpll_md =
5965                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5966 }
5967
5968 static void chv_prepare_pll(struct intel_crtc *crtc,
5969                             const struct intel_crtc_config *pipe_config)
5970 {
5971         struct drm_device *dev = crtc->base.dev;
5972         struct drm_i915_private *dev_priv = dev->dev_private;
5973         int pipe = crtc->pipe;
5974         int dpll_reg = DPLL(crtc->pipe);
5975         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5976         u32 loopfilter, intcoeff;
5977         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5978         int refclk;
5979
5980         bestn = pipe_config->dpll.n;
5981         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5982         bestm1 = pipe_config->dpll.m1;
5983         bestm2 = pipe_config->dpll.m2 >> 22;
5984         bestp1 = pipe_config->dpll.p1;
5985         bestp2 = pipe_config->dpll.p2;
5986
5987         /*
5988          * Enable Refclk and SSC
5989          */
5990         I915_WRITE(dpll_reg,
5991                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5992
5993         mutex_lock(&dev_priv->dpio_lock);
5994
5995         /* p1 and p2 divider */
5996         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5997                         5 << DPIO_CHV_S1_DIV_SHIFT |
5998                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5999                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6000                         1 << DPIO_CHV_K_DIV_SHIFT);
6001
6002         /* Feedback post-divider - m2 */
6003         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6004
6005         /* Feedback refclk divider - n and m1 */
6006         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6007                         DPIO_CHV_M1_DIV_BY_2 |
6008                         1 << DPIO_CHV_N_DIV_SHIFT);
6009
6010         /* M2 fraction division */
6011         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6012
6013         /* M2 fraction division enable */
6014         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6015                        DPIO_CHV_FRAC_DIV_EN |
6016                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6017
6018         /* Loop filter */
6019         refclk = i9xx_get_refclk(crtc, 0);
6020         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6021                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6022         if (refclk == 100000)
6023                 intcoeff = 11;
6024         else if (refclk == 38400)
6025                 intcoeff = 10;
6026         else
6027                 intcoeff = 9;
6028         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6029         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6030
6031         /* AFC Recal */
6032         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6033                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6034                         DPIO_AFC_RECAL);
6035
6036         mutex_unlock(&dev_priv->dpio_lock);
6037 }
6038
6039 /**
6040  * vlv_force_pll_on - forcibly enable just the PLL
6041  * @dev_priv: i915 private structure
6042  * @pipe: pipe PLL to enable
6043  * @dpll: PLL configuration
6044  *
6045  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6046  * in cases where we need the PLL enabled even when @pipe is not going to
6047  * be enabled.
6048  */
6049 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6050                       const struct dpll *dpll)
6051 {
6052         struct intel_crtc *crtc =
6053                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6054         struct intel_crtc_config pipe_config = {
6055                 .pixel_multiplier = 1,
6056                 .dpll = *dpll,
6057         };
6058
6059         if (IS_CHERRYVIEW(dev)) {
6060                 chv_update_pll(crtc, &pipe_config);
6061                 chv_prepare_pll(crtc, &pipe_config);
6062                 chv_enable_pll(crtc, &pipe_config);
6063         } else {
6064                 vlv_update_pll(crtc, &pipe_config);
6065                 vlv_prepare_pll(crtc, &pipe_config);
6066                 vlv_enable_pll(crtc, &pipe_config);
6067         }
6068 }
6069
6070 /**
6071  * vlv_force_pll_off - forcibly disable just the PLL
6072  * @dev_priv: i915 private structure
6073  * @pipe: pipe PLL to disable
6074  *
6075  * Disable the PLL for @pipe. To be used in cases where we need
6076  * the PLL enabled even when @pipe is not going to be enabled.
6077  */
6078 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6079 {
6080         if (IS_CHERRYVIEW(dev))
6081                 chv_disable_pll(to_i915(dev), pipe);
6082         else
6083                 vlv_disable_pll(to_i915(dev), pipe);
6084 }
6085
6086 static void i9xx_update_pll(struct intel_crtc *crtc,
6087                             intel_clock_t *reduced_clock,
6088                             int num_connectors)
6089 {
6090         struct drm_device *dev = crtc->base.dev;
6091         struct drm_i915_private *dev_priv = dev->dev_private;
6092         u32 dpll;
6093         bool is_sdvo;
6094         struct dpll *clock = &crtc->new_config->dpll;
6095
6096         i9xx_update_pll_dividers(crtc, reduced_clock);
6097
6098         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6099                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6100
6101         dpll = DPLL_VGA_MODE_DIS;
6102
6103         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6104                 dpll |= DPLLB_MODE_LVDS;
6105         else
6106                 dpll |= DPLLB_MODE_DAC_SERIAL;
6107
6108         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6109                 dpll |= (crtc->new_config->pixel_multiplier - 1)
6110                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6111         }
6112
6113         if (is_sdvo)
6114                 dpll |= DPLL_SDVO_HIGH_SPEED;
6115
6116         if (crtc->new_config->has_dp_encoder)
6117                 dpll |= DPLL_SDVO_HIGH_SPEED;
6118
6119         /* compute bitmask from p1 value */
6120         if (IS_PINEVIEW(dev))
6121                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6122         else {
6123                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6124                 if (IS_G4X(dev) && reduced_clock)
6125                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6126         }
6127         switch (clock->p2) {
6128         case 5:
6129                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6130                 break;
6131         case 7:
6132                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6133                 break;
6134         case 10:
6135                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6136                 break;
6137         case 14:
6138                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6139                 break;
6140         }
6141         if (INTEL_INFO(dev)->gen >= 4)
6142                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6143
6144         if (crtc->new_config->sdvo_tv_clock)
6145                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6146         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6147                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6148                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6149         else
6150                 dpll |= PLL_REF_INPUT_DREFCLK;
6151
6152         dpll |= DPLL_VCO_ENABLE;
6153         crtc->new_config->dpll_hw_state.dpll = dpll;
6154
6155         if (INTEL_INFO(dev)->gen >= 4) {
6156                 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6157                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6158                 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6159         }
6160 }
6161
6162 static void i8xx_update_pll(struct intel_crtc *crtc,
6163                             intel_clock_t *reduced_clock,
6164                             int num_connectors)
6165 {
6166         struct drm_device *dev = crtc->base.dev;
6167         struct drm_i915_private *dev_priv = dev->dev_private;
6168         u32 dpll;
6169         struct dpll *clock = &crtc->new_config->dpll;
6170
6171         i9xx_update_pll_dividers(crtc, reduced_clock);
6172
6173         dpll = DPLL_VGA_MODE_DIS;
6174
6175         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6176                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6177         } else {
6178                 if (clock->p1 == 2)
6179                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6180                 else
6181                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6182                 if (clock->p2 == 4)
6183                         dpll |= PLL_P2_DIVIDE_BY_4;
6184         }
6185
6186         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6187                 dpll |= DPLL_DVO_2X_MODE;
6188
6189         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6190                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6191                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6192         else
6193                 dpll |= PLL_REF_INPUT_DREFCLK;
6194
6195         dpll |= DPLL_VCO_ENABLE;
6196         crtc->new_config->dpll_hw_state.dpll = dpll;
6197 }
6198
6199 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6200 {
6201         struct drm_device *dev = intel_crtc->base.dev;
6202         struct drm_i915_private *dev_priv = dev->dev_private;
6203         enum pipe pipe = intel_crtc->pipe;
6204         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6205         struct drm_display_mode *adjusted_mode =
6206                 &intel_crtc->config.adjusted_mode;
6207         uint32_t crtc_vtotal, crtc_vblank_end;
6208         int vsyncshift = 0;
6209
6210         /* We need to be careful not to changed the adjusted mode, for otherwise
6211          * the hw state checker will get angry at the mismatch. */
6212         crtc_vtotal = adjusted_mode->crtc_vtotal;
6213         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6214
6215         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6216                 /* the chip adds 2 halflines automatically */
6217                 crtc_vtotal -= 1;
6218                 crtc_vblank_end -= 1;
6219
6220                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6221                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6222                 else
6223                         vsyncshift = adjusted_mode->crtc_hsync_start -
6224                                 adjusted_mode->crtc_htotal / 2;
6225                 if (vsyncshift < 0)
6226                         vsyncshift += adjusted_mode->crtc_htotal;
6227         }
6228
6229         if (INTEL_INFO(dev)->gen > 3)
6230                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6231
6232         I915_WRITE(HTOTAL(cpu_transcoder),
6233                    (adjusted_mode->crtc_hdisplay - 1) |
6234                    ((adjusted_mode->crtc_htotal - 1) << 16));
6235         I915_WRITE(HBLANK(cpu_transcoder),
6236                    (adjusted_mode->crtc_hblank_start - 1) |
6237                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6238         I915_WRITE(HSYNC(cpu_transcoder),
6239                    (adjusted_mode->crtc_hsync_start - 1) |
6240                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6241
6242         I915_WRITE(VTOTAL(cpu_transcoder),
6243                    (adjusted_mode->crtc_vdisplay - 1) |
6244                    ((crtc_vtotal - 1) << 16));
6245         I915_WRITE(VBLANK(cpu_transcoder),
6246                    (adjusted_mode->crtc_vblank_start - 1) |
6247                    ((crtc_vblank_end - 1) << 16));
6248         I915_WRITE(VSYNC(cpu_transcoder),
6249                    (adjusted_mode->crtc_vsync_start - 1) |
6250                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6251
6252         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6253          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6254          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6255          * bits. */
6256         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6257             (pipe == PIPE_B || pipe == PIPE_C))
6258                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6259
6260         /* pipesrc controls the size that is scaled from, which should
6261          * always be the user's requested size.
6262          */
6263         I915_WRITE(PIPESRC(pipe),
6264                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6265                    (intel_crtc->config.pipe_src_h - 1));
6266 }
6267
6268 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6269                                    struct intel_crtc_config *pipe_config)
6270 {
6271         struct drm_device *dev = crtc->base.dev;
6272         struct drm_i915_private *dev_priv = dev->dev_private;
6273         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6274         uint32_t tmp;
6275
6276         tmp = I915_READ(HTOTAL(cpu_transcoder));
6277         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6278         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6279         tmp = I915_READ(HBLANK(cpu_transcoder));
6280         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6281         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6282         tmp = I915_READ(HSYNC(cpu_transcoder));
6283         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6284         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6285
6286         tmp = I915_READ(VTOTAL(cpu_transcoder));
6287         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6288         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6289         tmp = I915_READ(VBLANK(cpu_transcoder));
6290         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6291         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6292         tmp = I915_READ(VSYNC(cpu_transcoder));
6293         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6294         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6295
6296         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6297                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6298                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6299                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6300         }
6301
6302         tmp = I915_READ(PIPESRC(crtc->pipe));
6303         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6304         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6305
6306         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6307         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6308 }
6309
6310 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6311                                  struct intel_crtc_config *pipe_config)
6312 {
6313         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6314         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6315         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6316         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6317
6318         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6319         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6320         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6321         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6322
6323         mode->flags = pipe_config->adjusted_mode.flags;
6324
6325         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6326         mode->flags |= pipe_config->adjusted_mode.flags;
6327 }
6328
6329 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6330 {
6331         struct drm_device *dev = intel_crtc->base.dev;
6332         struct drm_i915_private *dev_priv = dev->dev_private;
6333         uint32_t pipeconf;
6334
6335         pipeconf = 0;
6336
6337         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6338             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6339                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6340
6341         if (intel_crtc->config.double_wide)
6342                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6343
6344         /* only g4x and later have fancy bpc/dither controls */
6345         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6346                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6347                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6348                         pipeconf |= PIPECONF_DITHER_EN |
6349                                     PIPECONF_DITHER_TYPE_SP;
6350
6351                 switch (intel_crtc->config.pipe_bpp) {
6352                 case 18:
6353                         pipeconf |= PIPECONF_6BPC;
6354                         break;
6355                 case 24:
6356                         pipeconf |= PIPECONF_8BPC;
6357                         break;
6358                 case 30:
6359                         pipeconf |= PIPECONF_10BPC;
6360                         break;
6361                 default:
6362                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6363                         BUG();
6364                 }
6365         }
6366
6367         if (HAS_PIPE_CXSR(dev)) {
6368                 if (intel_crtc->lowfreq_avail) {
6369                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6370                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6371                 } else {
6372                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6373                 }
6374         }
6375
6376         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6377                 if (INTEL_INFO(dev)->gen < 4 ||
6378                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6379                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6380                 else
6381                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6382         } else
6383                 pipeconf |= PIPECONF_PROGRESSIVE;
6384
6385         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6386                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6387
6388         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6389         POSTING_READ(PIPECONF(intel_crtc->pipe));
6390 }
6391
6392 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6393 {
6394         struct drm_device *dev = crtc->base.dev;
6395         struct drm_i915_private *dev_priv = dev->dev_private;
6396         int refclk, num_connectors = 0;
6397         intel_clock_t clock, reduced_clock;
6398         bool ok, has_reduced_clock = false;
6399         bool is_lvds = false, is_dsi = false;
6400         struct intel_encoder *encoder;
6401         const intel_limit_t *limit;
6402
6403         for_each_intel_encoder(dev, encoder) {
6404                 if (encoder->new_crtc != crtc)
6405                         continue;
6406
6407                 switch (encoder->type) {
6408                 case INTEL_OUTPUT_LVDS:
6409                         is_lvds = true;
6410                         break;
6411                 case INTEL_OUTPUT_DSI:
6412                         is_dsi = true;
6413                         break;
6414                 default:
6415                         break;
6416                 }
6417
6418                 num_connectors++;
6419         }
6420
6421         if (is_dsi)
6422                 return 0;
6423
6424         if (!crtc->new_config->clock_set) {
6425                 refclk = i9xx_get_refclk(crtc, num_connectors);
6426
6427                 /*
6428                  * Returns a set of divisors for the desired target clock with
6429                  * the given refclk, or FALSE.  The returned values represent
6430                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6431                  * 2) / p1 / p2.
6432                  */
6433                 limit = intel_limit(crtc, refclk);
6434                 ok = dev_priv->display.find_dpll(limit, crtc,
6435                                                  crtc->new_config->port_clock,
6436                                                  refclk, NULL, &clock);
6437                 if (!ok) {
6438                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6439                         return -EINVAL;
6440                 }
6441
6442                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6443                         /*
6444                          * Ensure we match the reduced clock's P to the target
6445                          * clock.  If the clocks don't match, we can't switch
6446                          * the display clock by using the FP0/FP1. In such case
6447                          * we will disable the LVDS downclock feature.
6448                          */
6449                         has_reduced_clock =
6450                                 dev_priv->display.find_dpll(limit, crtc,
6451                                                             dev_priv->lvds_downclock,
6452                                                             refclk, &clock,
6453                                                             &reduced_clock);
6454                 }
6455                 /* Compat-code for transition, will disappear. */
6456                 crtc->new_config->dpll.n = clock.n;
6457                 crtc->new_config->dpll.m1 = clock.m1;
6458                 crtc->new_config->dpll.m2 = clock.m2;
6459                 crtc->new_config->dpll.p1 = clock.p1;
6460                 crtc->new_config->dpll.p2 = clock.p2;
6461         }
6462
6463         if (IS_GEN2(dev)) {
6464                 i8xx_update_pll(crtc,
6465                                 has_reduced_clock ? &reduced_clock : NULL,
6466                                 num_connectors);
6467         } else if (IS_CHERRYVIEW(dev)) {
6468                 chv_update_pll(crtc, crtc->new_config);
6469         } else if (IS_VALLEYVIEW(dev)) {
6470                 vlv_update_pll(crtc, crtc->new_config);
6471         } else {
6472                 i9xx_update_pll(crtc,
6473                                 has_reduced_clock ? &reduced_clock : NULL,
6474                                 num_connectors);
6475         }
6476
6477         return 0;
6478 }
6479
6480 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6481                                  struct intel_crtc_config *pipe_config)
6482 {
6483         struct drm_device *dev = crtc->base.dev;
6484         struct drm_i915_private *dev_priv = dev->dev_private;
6485         uint32_t tmp;
6486
6487         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6488                 return;
6489
6490         tmp = I915_READ(PFIT_CONTROL);
6491         if (!(tmp & PFIT_ENABLE))
6492                 return;
6493
6494         /* Check whether the pfit is attached to our pipe. */
6495         if (INTEL_INFO(dev)->gen < 4) {
6496                 if (crtc->pipe != PIPE_B)
6497                         return;
6498         } else {
6499                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6500                         return;
6501         }
6502
6503         pipe_config->gmch_pfit.control = tmp;
6504         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6505         if (INTEL_INFO(dev)->gen < 5)
6506                 pipe_config->gmch_pfit.lvds_border_bits =
6507                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6508 }
6509
6510 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6511                                struct intel_crtc_config *pipe_config)
6512 {
6513         struct drm_device *dev = crtc->base.dev;
6514         struct drm_i915_private *dev_priv = dev->dev_private;
6515         int pipe = pipe_config->cpu_transcoder;
6516         intel_clock_t clock;
6517         u32 mdiv;
6518         int refclk = 100000;
6519
6520         /* In case of MIPI DPLL will not even be used */
6521         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6522                 return;
6523
6524         mutex_lock(&dev_priv->dpio_lock);
6525         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6526         mutex_unlock(&dev_priv->dpio_lock);
6527
6528         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6529         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6530         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6531         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6532         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6533
6534         vlv_clock(refclk, &clock);
6535
6536         /* clock.dot is the fast clock */
6537         pipe_config->port_clock = clock.dot / 5;
6538 }
6539
6540 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6541                                   struct intel_plane_config *plane_config)
6542 {
6543         struct drm_device *dev = crtc->base.dev;
6544         struct drm_i915_private *dev_priv = dev->dev_private;
6545         u32 val, base, offset;
6546         int pipe = crtc->pipe, plane = crtc->plane;
6547         int fourcc, pixel_format;
6548         int aligned_height;
6549
6550         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6551         if (!crtc->base.primary->fb) {
6552                 DRM_DEBUG_KMS("failed to alloc fb\n");
6553                 return;
6554         }
6555
6556         val = I915_READ(DSPCNTR(plane));
6557
6558         if (INTEL_INFO(dev)->gen >= 4)
6559                 if (val & DISPPLANE_TILED)
6560                         plane_config->tiled = true;
6561
6562         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6563         fourcc = intel_format_to_fourcc(pixel_format);
6564         crtc->base.primary->fb->pixel_format = fourcc;
6565         crtc->base.primary->fb->bits_per_pixel =
6566                 drm_format_plane_cpp(fourcc, 0) * 8;
6567
6568         if (INTEL_INFO(dev)->gen >= 4) {
6569                 if (plane_config->tiled)
6570                         offset = I915_READ(DSPTILEOFF(plane));
6571                 else
6572                         offset = I915_READ(DSPLINOFF(plane));
6573                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6574         } else {
6575                 base = I915_READ(DSPADDR(plane));
6576         }
6577         plane_config->base = base;
6578
6579         val = I915_READ(PIPESRC(pipe));
6580         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6581         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6582
6583         val = I915_READ(DSPSTRIDE(pipe));
6584         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6585
6586         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6587                                             plane_config->tiled);
6588
6589         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6590                                         aligned_height);
6591
6592         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6593                       pipe, plane, crtc->base.primary->fb->width,
6594                       crtc->base.primary->fb->height,
6595                       crtc->base.primary->fb->bits_per_pixel, base,
6596                       crtc->base.primary->fb->pitches[0],
6597                       plane_config->size);
6598
6599 }
6600
6601 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6602                                struct intel_crtc_config *pipe_config)
6603 {
6604         struct drm_device *dev = crtc->base.dev;
6605         struct drm_i915_private *dev_priv = dev->dev_private;
6606         int pipe = pipe_config->cpu_transcoder;
6607         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6608         intel_clock_t clock;
6609         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6610         int refclk = 100000;
6611
6612         mutex_lock(&dev_priv->dpio_lock);
6613         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6614         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6615         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6616         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6617         mutex_unlock(&dev_priv->dpio_lock);
6618
6619         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6620         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6621         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6622         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6623         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6624
6625         chv_clock(refclk, &clock);
6626
6627         /* clock.dot is the fast clock */
6628         pipe_config->port_clock = clock.dot / 5;
6629 }
6630
6631 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6632                                  struct intel_crtc_config *pipe_config)
6633 {
6634         struct drm_device *dev = crtc->base.dev;
6635         struct drm_i915_private *dev_priv = dev->dev_private;
6636         uint32_t tmp;
6637
6638         if (!intel_display_power_is_enabled(dev_priv,
6639                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6640                 return false;
6641
6642         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6643         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6644
6645         tmp = I915_READ(PIPECONF(crtc->pipe));
6646         if (!(tmp & PIPECONF_ENABLE))
6647                 return false;
6648
6649         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6650                 switch (tmp & PIPECONF_BPC_MASK) {
6651                 case PIPECONF_6BPC:
6652                         pipe_config->pipe_bpp = 18;
6653                         break;
6654                 case PIPECONF_8BPC:
6655                         pipe_config->pipe_bpp = 24;
6656                         break;
6657                 case PIPECONF_10BPC:
6658                         pipe_config->pipe_bpp = 30;
6659                         break;
6660                 default:
6661                         break;
6662                 }
6663         }
6664
6665         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6666                 pipe_config->limited_color_range = true;
6667
6668         if (INTEL_INFO(dev)->gen < 4)
6669                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6670
6671         intel_get_pipe_timings(crtc, pipe_config);
6672
6673         i9xx_get_pfit_config(crtc, pipe_config);
6674
6675         if (INTEL_INFO(dev)->gen >= 4) {
6676                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6677                 pipe_config->pixel_multiplier =
6678                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6679                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6680                 pipe_config->dpll_hw_state.dpll_md = tmp;
6681         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6682                 tmp = I915_READ(DPLL(crtc->pipe));
6683                 pipe_config->pixel_multiplier =
6684                         ((tmp & SDVO_MULTIPLIER_MASK)
6685                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6686         } else {
6687                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6688                  * port and will be fixed up in the encoder->get_config
6689                  * function. */
6690                 pipe_config->pixel_multiplier = 1;
6691         }
6692         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6693         if (!IS_VALLEYVIEW(dev)) {
6694                 /*
6695                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6696                  * on 830. Filter it out here so that we don't
6697                  * report errors due to that.
6698                  */
6699                 if (IS_I830(dev))
6700                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6701
6702                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6703                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6704         } else {
6705                 /* Mask out read-only status bits. */
6706                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6707                                                      DPLL_PORTC_READY_MASK |
6708                                                      DPLL_PORTB_READY_MASK);
6709         }
6710
6711         if (IS_CHERRYVIEW(dev))
6712                 chv_crtc_clock_get(crtc, pipe_config);
6713         else if (IS_VALLEYVIEW(dev))
6714                 vlv_crtc_clock_get(crtc, pipe_config);
6715         else
6716                 i9xx_crtc_clock_get(crtc, pipe_config);
6717
6718         return true;
6719 }
6720
6721 static void ironlake_init_pch_refclk(struct drm_device *dev)
6722 {
6723         struct drm_i915_private *dev_priv = dev->dev_private;
6724         struct intel_encoder *encoder;
6725         u32 val, final;
6726         bool has_lvds = false;
6727         bool has_cpu_edp = false;
6728         bool has_panel = false;
6729         bool has_ck505 = false;
6730         bool can_ssc = false;
6731
6732         /* We need to take the global config into account */
6733         for_each_intel_encoder(dev, encoder) {
6734                 switch (encoder->type) {
6735                 case INTEL_OUTPUT_LVDS:
6736                         has_panel = true;
6737                         has_lvds = true;
6738                         break;
6739                 case INTEL_OUTPUT_EDP:
6740                         has_panel = true;
6741                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6742                                 has_cpu_edp = true;
6743                         break;
6744                 default:
6745                         break;
6746                 }
6747         }
6748
6749         if (HAS_PCH_IBX(dev)) {
6750                 has_ck505 = dev_priv->vbt.display_clock_mode;
6751                 can_ssc = has_ck505;
6752         } else {
6753                 has_ck505 = false;
6754                 can_ssc = true;
6755         }
6756
6757         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6758                       has_panel, has_lvds, has_ck505);
6759
6760         /* Ironlake: try to setup display ref clock before DPLL
6761          * enabling. This is only under driver's control after
6762          * PCH B stepping, previous chipset stepping should be
6763          * ignoring this setting.
6764          */
6765         val = I915_READ(PCH_DREF_CONTROL);
6766
6767         /* As we must carefully and slowly disable/enable each source in turn,
6768          * compute the final state we want first and check if we need to
6769          * make any changes at all.
6770          */
6771         final = val;
6772         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6773         if (has_ck505)
6774                 final |= DREF_NONSPREAD_CK505_ENABLE;
6775         else
6776                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6777
6778         final &= ~DREF_SSC_SOURCE_MASK;
6779         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6780         final &= ~DREF_SSC1_ENABLE;
6781
6782         if (has_panel) {
6783                 final |= DREF_SSC_SOURCE_ENABLE;
6784
6785                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6786                         final |= DREF_SSC1_ENABLE;
6787
6788                 if (has_cpu_edp) {
6789                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6790                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6791                         else
6792                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6793                 } else
6794                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6795         } else {
6796                 final |= DREF_SSC_SOURCE_DISABLE;
6797                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6798         }
6799
6800         if (final == val)
6801                 return;
6802
6803         /* Always enable nonspread source */
6804         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6805
6806         if (has_ck505)
6807                 val |= DREF_NONSPREAD_CK505_ENABLE;
6808         else
6809                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6810
6811         if (has_panel) {
6812                 val &= ~DREF_SSC_SOURCE_MASK;
6813                 val |= DREF_SSC_SOURCE_ENABLE;
6814
6815                 /* SSC must be turned on before enabling the CPU output  */
6816                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6817                         DRM_DEBUG_KMS("Using SSC on panel\n");
6818                         val |= DREF_SSC1_ENABLE;
6819                 } else
6820                         val &= ~DREF_SSC1_ENABLE;
6821
6822                 /* Get SSC going before enabling the outputs */
6823                 I915_WRITE(PCH_DREF_CONTROL, val);
6824                 POSTING_READ(PCH_DREF_CONTROL);
6825                 udelay(200);
6826
6827                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6828
6829                 /* Enable CPU source on CPU attached eDP */
6830                 if (has_cpu_edp) {
6831                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6832                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6833                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6834                         } else
6835                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6836                 } else
6837                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6838
6839                 I915_WRITE(PCH_DREF_CONTROL, val);
6840                 POSTING_READ(PCH_DREF_CONTROL);
6841                 udelay(200);
6842         } else {
6843                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6844
6845                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6846
6847                 /* Turn off CPU output */
6848                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6849
6850                 I915_WRITE(PCH_DREF_CONTROL, val);
6851                 POSTING_READ(PCH_DREF_CONTROL);
6852                 udelay(200);
6853
6854                 /* Turn off the SSC source */
6855                 val &= ~DREF_SSC_SOURCE_MASK;
6856                 val |= DREF_SSC_SOURCE_DISABLE;
6857
6858                 /* Turn off SSC1 */
6859                 val &= ~DREF_SSC1_ENABLE;
6860
6861                 I915_WRITE(PCH_DREF_CONTROL, val);
6862                 POSTING_READ(PCH_DREF_CONTROL);
6863                 udelay(200);
6864         }
6865
6866         BUG_ON(val != final);
6867 }
6868
6869 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6870 {
6871         uint32_t tmp;
6872
6873         tmp = I915_READ(SOUTH_CHICKEN2);
6874         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6875         I915_WRITE(SOUTH_CHICKEN2, tmp);
6876
6877         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6878                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6879                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6880
6881         tmp = I915_READ(SOUTH_CHICKEN2);
6882         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6883         I915_WRITE(SOUTH_CHICKEN2, tmp);
6884
6885         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6886                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6887                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6888 }
6889
6890 /* WaMPhyProgramming:hsw */
6891 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6892 {
6893         uint32_t tmp;
6894
6895         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6896         tmp &= ~(0xFF << 24);
6897         tmp |= (0x12 << 24);
6898         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6899
6900         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6901         tmp |= (1 << 11);
6902         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6903
6904         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6905         tmp |= (1 << 11);
6906         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6907
6908         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6909         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6910         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6911
6912         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6913         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6914         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6915
6916         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6917         tmp &= ~(7 << 13);
6918         tmp |= (5 << 13);
6919         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6920
6921         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6922         tmp &= ~(7 << 13);
6923         tmp |= (5 << 13);
6924         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6925
6926         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6927         tmp &= ~0xFF;
6928         tmp |= 0x1C;
6929         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6930
6931         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6932         tmp &= ~0xFF;
6933         tmp |= 0x1C;
6934         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6935
6936         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6937         tmp &= ~(0xFF << 16);
6938         tmp |= (0x1C << 16);
6939         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6940
6941         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6942         tmp &= ~(0xFF << 16);
6943         tmp |= (0x1C << 16);
6944         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6945
6946         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6947         tmp |= (1 << 27);
6948         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6949
6950         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6951         tmp |= (1 << 27);
6952         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6953
6954         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6955         tmp &= ~(0xF << 28);
6956         tmp |= (4 << 28);
6957         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6958
6959         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6960         tmp &= ~(0xF << 28);
6961         tmp |= (4 << 28);
6962         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6963 }
6964
6965 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6966  * Programming" based on the parameters passed:
6967  * - Sequence to enable CLKOUT_DP
6968  * - Sequence to enable CLKOUT_DP without spread
6969  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6970  */
6971 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6972                                  bool with_fdi)
6973 {
6974         struct drm_i915_private *dev_priv = dev->dev_private;
6975         uint32_t reg, tmp;
6976
6977         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6978                 with_spread = true;
6979         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6980                  with_fdi, "LP PCH doesn't have FDI\n"))
6981                 with_fdi = false;
6982
6983         mutex_lock(&dev_priv->dpio_lock);
6984
6985         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6986         tmp &= ~SBI_SSCCTL_DISABLE;
6987         tmp |= SBI_SSCCTL_PATHALT;
6988         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6989
6990         udelay(24);
6991
6992         if (with_spread) {
6993                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6994                 tmp &= ~SBI_SSCCTL_PATHALT;
6995                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6996
6997                 if (with_fdi) {
6998                         lpt_reset_fdi_mphy(dev_priv);
6999                         lpt_program_fdi_mphy(dev_priv);
7000                 }
7001         }
7002
7003         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7004                SBI_GEN0 : SBI_DBUFF0;
7005         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7006         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7007         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7008
7009         mutex_unlock(&dev_priv->dpio_lock);
7010 }
7011
7012 /* Sequence to disable CLKOUT_DP */
7013 static void lpt_disable_clkout_dp(struct drm_device *dev)
7014 {
7015         struct drm_i915_private *dev_priv = dev->dev_private;
7016         uint32_t reg, tmp;
7017
7018         mutex_lock(&dev_priv->dpio_lock);
7019
7020         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7021                SBI_GEN0 : SBI_DBUFF0;
7022         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7023         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7024         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7025
7026         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7027         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7028                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7029                         tmp |= SBI_SSCCTL_PATHALT;
7030                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7031                         udelay(32);
7032                 }
7033                 tmp |= SBI_SSCCTL_DISABLE;
7034                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7035         }
7036
7037         mutex_unlock(&dev_priv->dpio_lock);
7038 }
7039
7040 static void lpt_init_pch_refclk(struct drm_device *dev)
7041 {
7042         struct intel_encoder *encoder;
7043         bool has_vga = false;
7044
7045         for_each_intel_encoder(dev, encoder) {
7046                 switch (encoder->type) {
7047                 case INTEL_OUTPUT_ANALOG:
7048                         has_vga = true;
7049                         break;
7050                 default:
7051                         break;
7052                 }
7053         }
7054
7055         if (has_vga)
7056                 lpt_enable_clkout_dp(dev, true, true);
7057         else
7058                 lpt_disable_clkout_dp(dev);
7059 }
7060
7061 /*
7062  * Initialize reference clocks when the driver loads
7063  */
7064 void intel_init_pch_refclk(struct drm_device *dev)
7065 {
7066         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7067                 ironlake_init_pch_refclk(dev);
7068         else if (HAS_PCH_LPT(dev))
7069                 lpt_init_pch_refclk(dev);
7070 }
7071
7072 static int ironlake_get_refclk(struct drm_crtc *crtc)
7073 {
7074         struct drm_device *dev = crtc->dev;
7075         struct drm_i915_private *dev_priv = dev->dev_private;
7076         struct intel_encoder *encoder;
7077         int num_connectors = 0;
7078         bool is_lvds = false;
7079
7080         for_each_intel_encoder(dev, encoder) {
7081                 if (encoder->new_crtc != to_intel_crtc(crtc))
7082                         continue;
7083
7084                 switch (encoder->type) {
7085                 case INTEL_OUTPUT_LVDS:
7086                         is_lvds = true;
7087                         break;
7088                 default:
7089                         break;
7090                 }
7091                 num_connectors++;
7092         }
7093
7094         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7095                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7096                               dev_priv->vbt.lvds_ssc_freq);
7097                 return dev_priv->vbt.lvds_ssc_freq;
7098         }
7099
7100         return 120000;
7101 }
7102
7103 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7104 {
7105         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7107         int pipe = intel_crtc->pipe;
7108         uint32_t val;
7109
7110         val = 0;
7111
7112         switch (intel_crtc->config.pipe_bpp) {
7113         case 18:
7114                 val |= PIPECONF_6BPC;
7115                 break;
7116         case 24:
7117                 val |= PIPECONF_8BPC;
7118                 break;
7119         case 30:
7120                 val |= PIPECONF_10BPC;
7121                 break;
7122         case 36:
7123                 val |= PIPECONF_12BPC;
7124                 break;
7125         default:
7126                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7127                 BUG();
7128         }
7129
7130         if (intel_crtc->config.dither)
7131                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7132
7133         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7134                 val |= PIPECONF_INTERLACED_ILK;
7135         else
7136                 val |= PIPECONF_PROGRESSIVE;
7137
7138         if (intel_crtc->config.limited_color_range)
7139                 val |= PIPECONF_COLOR_RANGE_SELECT;
7140
7141         I915_WRITE(PIPECONF(pipe), val);
7142         POSTING_READ(PIPECONF(pipe));
7143 }
7144
7145 /*
7146  * Set up the pipe CSC unit.
7147  *
7148  * Currently only full range RGB to limited range RGB conversion
7149  * is supported, but eventually this should handle various
7150  * RGB<->YCbCr scenarios as well.
7151  */
7152 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7153 {
7154         struct drm_device *dev = crtc->dev;
7155         struct drm_i915_private *dev_priv = dev->dev_private;
7156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7157         int pipe = intel_crtc->pipe;
7158         uint16_t coeff = 0x7800; /* 1.0 */
7159
7160         /*
7161          * TODO: Check what kind of values actually come out of the pipe
7162          * with these coeff/postoff values and adjust to get the best
7163          * accuracy. Perhaps we even need to take the bpc value into
7164          * consideration.
7165          */
7166
7167         if (intel_crtc->config.limited_color_range)
7168                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7169
7170         /*
7171          * GY/GU and RY/RU should be the other way around according
7172          * to BSpec, but reality doesn't agree. Just set them up in
7173          * a way that results in the correct picture.
7174          */
7175         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7176         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7177
7178         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7179         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7180
7181         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7182         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7183
7184         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7185         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7186         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7187
7188         if (INTEL_INFO(dev)->gen > 6) {
7189                 uint16_t postoff = 0;
7190
7191                 if (intel_crtc->config.limited_color_range)
7192                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7193
7194                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7195                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7196                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7197
7198                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7199         } else {
7200                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7201
7202                 if (intel_crtc->config.limited_color_range)
7203                         mode |= CSC_BLACK_SCREEN_OFFSET;
7204
7205                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7206         }
7207 }
7208
7209 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7210 {
7211         struct drm_device *dev = crtc->dev;
7212         struct drm_i915_private *dev_priv = dev->dev_private;
7213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7214         enum pipe pipe = intel_crtc->pipe;
7215         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7216         uint32_t val;
7217
7218         val = 0;
7219
7220         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7221                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7222
7223         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7224                 val |= PIPECONF_INTERLACED_ILK;
7225         else
7226                 val |= PIPECONF_PROGRESSIVE;
7227
7228         I915_WRITE(PIPECONF(cpu_transcoder), val);
7229         POSTING_READ(PIPECONF(cpu_transcoder));
7230
7231         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7232         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7233
7234         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7235                 val = 0;
7236
7237                 switch (intel_crtc->config.pipe_bpp) {
7238                 case 18:
7239                         val |= PIPEMISC_DITHER_6_BPC;
7240                         break;
7241                 case 24:
7242                         val |= PIPEMISC_DITHER_8_BPC;
7243                         break;
7244                 case 30:
7245                         val |= PIPEMISC_DITHER_10_BPC;
7246                         break;
7247                 case 36:
7248                         val |= PIPEMISC_DITHER_12_BPC;
7249                         break;
7250                 default:
7251                         /* Case prevented by pipe_config_set_bpp. */
7252                         BUG();
7253                 }
7254
7255                 if (intel_crtc->config.dither)
7256                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7257
7258                 I915_WRITE(PIPEMISC(pipe), val);
7259         }
7260 }
7261
7262 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7263                                     intel_clock_t *clock,
7264                                     bool *has_reduced_clock,
7265                                     intel_clock_t *reduced_clock)
7266 {
7267         struct drm_device *dev = crtc->dev;
7268         struct drm_i915_private *dev_priv = dev->dev_private;
7269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7270         int refclk;
7271         const intel_limit_t *limit;
7272         bool ret, is_lvds = false;
7273
7274         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7275
7276         refclk = ironlake_get_refclk(crtc);
7277
7278         /*
7279          * Returns a set of divisors for the desired target clock with the given
7280          * refclk, or FALSE.  The returned values represent the clock equation:
7281          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7282          */
7283         limit = intel_limit(intel_crtc, refclk);
7284         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7285                                           intel_crtc->new_config->port_clock,
7286                                           refclk, NULL, clock);
7287         if (!ret)
7288                 return false;
7289
7290         if (is_lvds && dev_priv->lvds_downclock_avail) {
7291                 /*
7292                  * Ensure we match the reduced clock's P to the target clock.
7293                  * If the clocks don't match, we can't switch the display clock
7294                  * by using the FP0/FP1. In such case we will disable the LVDS
7295                  * downclock feature.
7296                 */
7297                 *has_reduced_clock =
7298                         dev_priv->display.find_dpll(limit, intel_crtc,
7299                                                     dev_priv->lvds_downclock,
7300                                                     refclk, clock,
7301                                                     reduced_clock);
7302         }
7303
7304         return true;
7305 }
7306
7307 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7308 {
7309         /*
7310          * Account for spread spectrum to avoid
7311          * oversubscribing the link. Max center spread
7312          * is 2.5%; use 5% for safety's sake.
7313          */
7314         u32 bps = target_clock * bpp * 21 / 20;
7315         return DIV_ROUND_UP(bps, link_bw * 8);
7316 }
7317
7318 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7319 {
7320         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7321 }
7322
7323 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7324                                       u32 *fp,
7325                                       intel_clock_t *reduced_clock, u32 *fp2)
7326 {
7327         struct drm_crtc *crtc = &intel_crtc->base;
7328         struct drm_device *dev = crtc->dev;
7329         struct drm_i915_private *dev_priv = dev->dev_private;
7330         struct intel_encoder *intel_encoder;
7331         uint32_t dpll;
7332         int factor, num_connectors = 0;
7333         bool is_lvds = false, is_sdvo = false;
7334
7335         for_each_intel_encoder(dev, intel_encoder) {
7336                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7337                         continue;
7338
7339                 switch (intel_encoder->type) {
7340                 case INTEL_OUTPUT_LVDS:
7341                         is_lvds = true;
7342                         break;
7343                 case INTEL_OUTPUT_SDVO:
7344                 case INTEL_OUTPUT_HDMI:
7345                         is_sdvo = true;
7346                         break;
7347                 default:
7348                         break;
7349                 }
7350
7351                 num_connectors++;
7352         }
7353
7354         /* Enable autotuning of the PLL clock (if permissible) */
7355         factor = 21;
7356         if (is_lvds) {
7357                 if ((intel_panel_use_ssc(dev_priv) &&
7358                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7359                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7360                         factor = 25;
7361         } else if (intel_crtc->new_config->sdvo_tv_clock)
7362                 factor = 20;
7363
7364         if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7365                 *fp |= FP_CB_TUNE;
7366
7367         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7368                 *fp2 |= FP_CB_TUNE;
7369
7370         dpll = 0;
7371
7372         if (is_lvds)
7373                 dpll |= DPLLB_MODE_LVDS;
7374         else
7375                 dpll |= DPLLB_MODE_DAC_SERIAL;
7376
7377         dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7378                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7379
7380         if (is_sdvo)
7381                 dpll |= DPLL_SDVO_HIGH_SPEED;
7382         if (intel_crtc->new_config->has_dp_encoder)
7383                 dpll |= DPLL_SDVO_HIGH_SPEED;
7384
7385         /* compute bitmask from p1 value */
7386         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7387         /* also FPA1 */
7388         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7389
7390         switch (intel_crtc->new_config->dpll.p2) {
7391         case 5:
7392                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7393                 break;
7394         case 7:
7395                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7396                 break;
7397         case 10:
7398                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7399                 break;
7400         case 14:
7401                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7402                 break;
7403         }
7404
7405         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7406                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7407         else
7408                 dpll |= PLL_REF_INPUT_DREFCLK;
7409
7410         return dpll | DPLL_VCO_ENABLE;
7411 }
7412
7413 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7414 {
7415         struct drm_device *dev = crtc->base.dev;
7416         intel_clock_t clock, reduced_clock;
7417         u32 dpll = 0, fp = 0, fp2 = 0;
7418         bool ok, has_reduced_clock = false;
7419         bool is_lvds = false;
7420         struct intel_shared_dpll *pll;
7421
7422         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7423
7424         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7425              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7426
7427         ok = ironlake_compute_clocks(&crtc->base, &clock,
7428                                      &has_reduced_clock, &reduced_clock);
7429         if (!ok && !crtc->new_config->clock_set) {
7430                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7431                 return -EINVAL;
7432         }
7433         /* Compat-code for transition, will disappear. */
7434         if (!crtc->new_config->clock_set) {
7435                 crtc->new_config->dpll.n = clock.n;
7436                 crtc->new_config->dpll.m1 = clock.m1;
7437                 crtc->new_config->dpll.m2 = clock.m2;
7438                 crtc->new_config->dpll.p1 = clock.p1;
7439                 crtc->new_config->dpll.p2 = clock.p2;
7440         }
7441
7442         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7443         if (crtc->new_config->has_pch_encoder) {
7444                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7445                 if (has_reduced_clock)
7446                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7447
7448                 dpll = ironlake_compute_dpll(crtc,
7449                                              &fp, &reduced_clock,
7450                                              has_reduced_clock ? &fp2 : NULL);
7451
7452                 crtc->new_config->dpll_hw_state.dpll = dpll;
7453                 crtc->new_config->dpll_hw_state.fp0 = fp;
7454                 if (has_reduced_clock)
7455                         crtc->new_config->dpll_hw_state.fp1 = fp2;
7456                 else
7457                         crtc->new_config->dpll_hw_state.fp1 = fp;
7458
7459                 pll = intel_get_shared_dpll(crtc);
7460                 if (pll == NULL) {
7461                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7462                                          pipe_name(crtc->pipe));
7463                         return -EINVAL;
7464                 }
7465         }
7466
7467         if (is_lvds && has_reduced_clock && i915.powersave)
7468                 crtc->lowfreq_avail = true;
7469         else
7470                 crtc->lowfreq_avail = false;
7471
7472         return 0;
7473 }
7474
7475 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7476                                          struct intel_link_m_n *m_n)
7477 {
7478         struct drm_device *dev = crtc->base.dev;
7479         struct drm_i915_private *dev_priv = dev->dev_private;
7480         enum pipe pipe = crtc->pipe;
7481
7482         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7483         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7484         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7485                 & ~TU_SIZE_MASK;
7486         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7487         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7488                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7489 }
7490
7491 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7492                                          enum transcoder transcoder,
7493                                          struct intel_link_m_n *m_n,
7494                                          struct intel_link_m_n *m2_n2)
7495 {
7496         struct drm_device *dev = crtc->base.dev;
7497         struct drm_i915_private *dev_priv = dev->dev_private;
7498         enum pipe pipe = crtc->pipe;
7499
7500         if (INTEL_INFO(dev)->gen >= 5) {
7501                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7502                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7503                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7504                         & ~TU_SIZE_MASK;
7505                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7506                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7507                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7508                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7509                  * gen < 8) and if DRRS is supported (to make sure the
7510                  * registers are not unnecessarily read).
7511                  */
7512                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7513                         crtc->config.has_drrs) {
7514                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7515                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7516                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7517                                         & ~TU_SIZE_MASK;
7518                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7519                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7520                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7521                 }
7522         } else {
7523                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7524                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7525                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7526                         & ~TU_SIZE_MASK;
7527                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7528                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7529                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7530         }
7531 }
7532
7533 void intel_dp_get_m_n(struct intel_crtc *crtc,
7534                       struct intel_crtc_config *pipe_config)
7535 {
7536         if (crtc->config.has_pch_encoder)
7537                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7538         else
7539                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7540                                              &pipe_config->dp_m_n,
7541                                              &pipe_config->dp_m2_n2);
7542 }
7543
7544 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7545                                         struct intel_crtc_config *pipe_config)
7546 {
7547         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7548                                      &pipe_config->fdi_m_n, NULL);
7549 }
7550
7551 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7552                                     struct intel_crtc_config *pipe_config)
7553 {
7554         struct drm_device *dev = crtc->base.dev;
7555         struct drm_i915_private *dev_priv = dev->dev_private;
7556         uint32_t tmp;
7557
7558         tmp = I915_READ(PS_CTL(crtc->pipe));
7559
7560         if (tmp & PS_ENABLE) {
7561                 pipe_config->pch_pfit.enabled = true;
7562                 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7563                 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7564         }
7565 }
7566
7567 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7568                                      struct intel_crtc_config *pipe_config)
7569 {
7570         struct drm_device *dev = crtc->base.dev;
7571         struct drm_i915_private *dev_priv = dev->dev_private;
7572         uint32_t tmp;
7573
7574         tmp = I915_READ(PF_CTL(crtc->pipe));
7575
7576         if (tmp & PF_ENABLE) {
7577                 pipe_config->pch_pfit.enabled = true;
7578                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7579                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7580
7581                 /* We currently do not free assignements of panel fitters on
7582                  * ivb/hsw (since we don't use the higher upscaling modes which
7583                  * differentiates them) so just WARN about this case for now. */
7584                 if (IS_GEN7(dev)) {
7585                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7586                                 PF_PIPE_SEL_IVB(crtc->pipe));
7587                 }
7588         }
7589 }
7590
7591 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7592                                       struct intel_plane_config *plane_config)
7593 {
7594         struct drm_device *dev = crtc->base.dev;
7595         struct drm_i915_private *dev_priv = dev->dev_private;
7596         u32 val, base, offset;
7597         int pipe = crtc->pipe, plane = crtc->plane;
7598         int fourcc, pixel_format;
7599         int aligned_height;
7600
7601         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7602         if (!crtc->base.primary->fb) {
7603                 DRM_DEBUG_KMS("failed to alloc fb\n");
7604                 return;
7605         }
7606
7607         val = I915_READ(DSPCNTR(plane));
7608
7609         if (INTEL_INFO(dev)->gen >= 4)
7610                 if (val & DISPPLANE_TILED)
7611                         plane_config->tiled = true;
7612
7613         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7614         fourcc = intel_format_to_fourcc(pixel_format);
7615         crtc->base.primary->fb->pixel_format = fourcc;
7616         crtc->base.primary->fb->bits_per_pixel =
7617                 drm_format_plane_cpp(fourcc, 0) * 8;
7618
7619         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7620         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7621                 offset = I915_READ(DSPOFFSET(plane));
7622         } else {
7623                 if (plane_config->tiled)
7624                         offset = I915_READ(DSPTILEOFF(plane));
7625                 else
7626                         offset = I915_READ(DSPLINOFF(plane));
7627         }
7628         plane_config->base = base;
7629
7630         val = I915_READ(PIPESRC(pipe));
7631         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7632         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7633
7634         val = I915_READ(DSPSTRIDE(pipe));
7635         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7636
7637         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7638                                             plane_config->tiled);
7639
7640         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7641                                         aligned_height);
7642
7643         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7644                       pipe, plane, crtc->base.primary->fb->width,
7645                       crtc->base.primary->fb->height,
7646                       crtc->base.primary->fb->bits_per_pixel, base,
7647                       crtc->base.primary->fb->pitches[0],
7648                       plane_config->size);
7649 }
7650
7651 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7652                                      struct intel_crtc_config *pipe_config)
7653 {
7654         struct drm_device *dev = crtc->base.dev;
7655         struct drm_i915_private *dev_priv = dev->dev_private;
7656         uint32_t tmp;
7657
7658         if (!intel_display_power_is_enabled(dev_priv,
7659                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7660                 return false;
7661
7662         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7663         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7664
7665         tmp = I915_READ(PIPECONF(crtc->pipe));
7666         if (!(tmp & PIPECONF_ENABLE))
7667                 return false;
7668
7669         switch (tmp & PIPECONF_BPC_MASK) {
7670         case PIPECONF_6BPC:
7671                 pipe_config->pipe_bpp = 18;
7672                 break;
7673         case PIPECONF_8BPC:
7674                 pipe_config->pipe_bpp = 24;
7675                 break;
7676         case PIPECONF_10BPC:
7677                 pipe_config->pipe_bpp = 30;
7678                 break;
7679         case PIPECONF_12BPC:
7680                 pipe_config->pipe_bpp = 36;
7681                 break;
7682         default:
7683                 break;
7684         }
7685
7686         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7687                 pipe_config->limited_color_range = true;
7688
7689         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7690                 struct intel_shared_dpll *pll;
7691
7692                 pipe_config->has_pch_encoder = true;
7693
7694                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7695                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7696                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7697
7698                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7699
7700                 if (HAS_PCH_IBX(dev_priv->dev)) {
7701                         pipe_config->shared_dpll =
7702                                 (enum intel_dpll_id) crtc->pipe;
7703                 } else {
7704                         tmp = I915_READ(PCH_DPLL_SEL);
7705                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7706                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7707                         else
7708                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7709                 }
7710
7711                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7712
7713                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7714                                            &pipe_config->dpll_hw_state));
7715
7716                 tmp = pipe_config->dpll_hw_state.dpll;
7717                 pipe_config->pixel_multiplier =
7718                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7719                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7720
7721                 ironlake_pch_clock_get(crtc, pipe_config);
7722         } else {
7723                 pipe_config->pixel_multiplier = 1;
7724         }
7725
7726         intel_get_pipe_timings(crtc, pipe_config);
7727
7728         ironlake_get_pfit_config(crtc, pipe_config);
7729
7730         return true;
7731 }
7732
7733 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7734 {
7735         struct drm_device *dev = dev_priv->dev;
7736         struct intel_crtc *crtc;
7737
7738         for_each_intel_crtc(dev, crtc)
7739                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7740                      pipe_name(crtc->pipe));
7741
7742         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7743         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7744         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7745         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7746         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7747         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7748              "CPU PWM1 enabled\n");
7749         if (IS_HASWELL(dev))
7750                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7751                      "CPU PWM2 enabled\n");
7752         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7753              "PCH PWM1 enabled\n");
7754         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7755              "Utility pin enabled\n");
7756         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7757
7758         /*
7759          * In theory we can still leave IRQs enabled, as long as only the HPD
7760          * interrupts remain enabled. We used to check for that, but since it's
7761          * gen-specific and since we only disable LCPLL after we fully disable
7762          * the interrupts, the check below should be enough.
7763          */
7764         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7765 }
7766
7767 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7768 {
7769         struct drm_device *dev = dev_priv->dev;
7770
7771         if (IS_HASWELL(dev))
7772                 return I915_READ(D_COMP_HSW);
7773         else
7774                 return I915_READ(D_COMP_BDW);
7775 }
7776
7777 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7778 {
7779         struct drm_device *dev = dev_priv->dev;
7780
7781         if (IS_HASWELL(dev)) {
7782                 mutex_lock(&dev_priv->rps.hw_lock);
7783                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7784                                             val))
7785                         DRM_ERROR("Failed to write to D_COMP\n");
7786                 mutex_unlock(&dev_priv->rps.hw_lock);
7787         } else {
7788                 I915_WRITE(D_COMP_BDW, val);
7789                 POSTING_READ(D_COMP_BDW);
7790         }
7791 }
7792
7793 /*
7794  * This function implements pieces of two sequences from BSpec:
7795  * - Sequence for display software to disable LCPLL
7796  * - Sequence for display software to allow package C8+
7797  * The steps implemented here are just the steps that actually touch the LCPLL
7798  * register. Callers should take care of disabling all the display engine
7799  * functions, doing the mode unset, fixing interrupts, etc.
7800  */
7801 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7802                               bool switch_to_fclk, bool allow_power_down)
7803 {
7804         uint32_t val;
7805
7806         assert_can_disable_lcpll(dev_priv);
7807
7808         val = I915_READ(LCPLL_CTL);
7809
7810         if (switch_to_fclk) {
7811                 val |= LCPLL_CD_SOURCE_FCLK;
7812                 I915_WRITE(LCPLL_CTL, val);
7813
7814                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7815                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7816                         DRM_ERROR("Switching to FCLK failed\n");
7817
7818                 val = I915_READ(LCPLL_CTL);
7819         }
7820
7821         val |= LCPLL_PLL_DISABLE;
7822         I915_WRITE(LCPLL_CTL, val);
7823         POSTING_READ(LCPLL_CTL);
7824
7825         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7826                 DRM_ERROR("LCPLL still locked\n");
7827
7828         val = hsw_read_dcomp(dev_priv);
7829         val |= D_COMP_COMP_DISABLE;
7830         hsw_write_dcomp(dev_priv, val);
7831         ndelay(100);
7832
7833         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7834                      1))
7835                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7836
7837         if (allow_power_down) {
7838                 val = I915_READ(LCPLL_CTL);
7839                 val |= LCPLL_POWER_DOWN_ALLOW;
7840                 I915_WRITE(LCPLL_CTL, val);
7841                 POSTING_READ(LCPLL_CTL);
7842         }
7843 }
7844
7845 /*
7846  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7847  * source.
7848  */
7849 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7850 {
7851         uint32_t val;
7852
7853         val = I915_READ(LCPLL_CTL);
7854
7855         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7856                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7857                 return;
7858
7859         /*
7860          * Make sure we're not on PC8 state before disabling PC8, otherwise
7861          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7862          *
7863          * The other problem is that hsw_restore_lcpll() is called as part of
7864          * the runtime PM resume sequence, so we can't just call
7865          * gen6_gt_force_wake_get() because that function calls
7866          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7867          * while we are on the resume sequence. So to solve this problem we have
7868          * to call special forcewake code that doesn't touch runtime PM and
7869          * doesn't enable the forcewake delayed work.
7870          */
7871         spin_lock_irq(&dev_priv->uncore.lock);
7872         if (dev_priv->uncore.forcewake_count++ == 0)
7873                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7874         spin_unlock_irq(&dev_priv->uncore.lock);
7875
7876         if (val & LCPLL_POWER_DOWN_ALLOW) {
7877                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7878                 I915_WRITE(LCPLL_CTL, val);
7879                 POSTING_READ(LCPLL_CTL);
7880         }
7881
7882         val = hsw_read_dcomp(dev_priv);
7883         val |= D_COMP_COMP_FORCE;
7884         val &= ~D_COMP_COMP_DISABLE;
7885         hsw_write_dcomp(dev_priv, val);
7886
7887         val = I915_READ(LCPLL_CTL);
7888         val &= ~LCPLL_PLL_DISABLE;
7889         I915_WRITE(LCPLL_CTL, val);
7890
7891         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7892                 DRM_ERROR("LCPLL not locked yet\n");
7893
7894         if (val & LCPLL_CD_SOURCE_FCLK) {
7895                 val = I915_READ(LCPLL_CTL);
7896                 val &= ~LCPLL_CD_SOURCE_FCLK;
7897                 I915_WRITE(LCPLL_CTL, val);
7898
7899                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7900                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7901                         DRM_ERROR("Switching back to LCPLL failed\n");
7902         }
7903
7904         /* See the big comment above. */
7905         spin_lock_irq(&dev_priv->uncore.lock);
7906         if (--dev_priv->uncore.forcewake_count == 0)
7907                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7908         spin_unlock_irq(&dev_priv->uncore.lock);
7909 }
7910
7911 /*
7912  * Package states C8 and deeper are really deep PC states that can only be
7913  * reached when all the devices on the system allow it, so even if the graphics
7914  * device allows PC8+, it doesn't mean the system will actually get to these
7915  * states. Our driver only allows PC8+ when going into runtime PM.
7916  *
7917  * The requirements for PC8+ are that all the outputs are disabled, the power
7918  * well is disabled and most interrupts are disabled, and these are also
7919  * requirements for runtime PM. When these conditions are met, we manually do
7920  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7921  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7922  * hang the machine.
7923  *
7924  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7925  * the state of some registers, so when we come back from PC8+ we need to
7926  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7927  * need to take care of the registers kept by RC6. Notice that this happens even
7928  * if we don't put the device in PCI D3 state (which is what currently happens
7929  * because of the runtime PM support).
7930  *
7931  * For more, read "Display Sequences for Package C8" on the hardware
7932  * documentation.
7933  */
7934 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7935 {
7936         struct drm_device *dev = dev_priv->dev;
7937         uint32_t val;
7938
7939         DRM_DEBUG_KMS("Enabling package C8+\n");
7940
7941         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7942                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7943                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7944                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7945         }
7946
7947         lpt_disable_clkout_dp(dev);
7948         hsw_disable_lcpll(dev_priv, true, true);
7949 }
7950
7951 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7952 {
7953         struct drm_device *dev = dev_priv->dev;
7954         uint32_t val;
7955
7956         DRM_DEBUG_KMS("Disabling package C8+\n");
7957
7958         hsw_restore_lcpll(dev_priv);
7959         lpt_init_pch_refclk(dev);
7960
7961         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7962                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7963                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7964                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7965         }
7966
7967         intel_prepare_ddi(dev);
7968 }
7969
7970 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
7971 {
7972         if (!intel_ddi_pll_select(crtc))
7973                 return -EINVAL;
7974
7975         crtc->lowfreq_avail = false;
7976
7977         return 0;
7978 }
7979
7980 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
7981                                 enum port port,
7982                                 struct intel_crtc_config *pipe_config)
7983 {
7984         u32 temp;
7985
7986         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
7987         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
7988
7989         switch (pipe_config->ddi_pll_sel) {
7990         case SKL_DPLL1:
7991                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
7992                 break;
7993         case SKL_DPLL2:
7994                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
7995                 break;
7996         case SKL_DPLL3:
7997                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
7998                 break;
7999         }
8000 }
8001
8002 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8003                                 enum port port,
8004                                 struct intel_crtc_config *pipe_config)
8005 {
8006         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8007
8008         switch (pipe_config->ddi_pll_sel) {
8009         case PORT_CLK_SEL_WRPLL1:
8010                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8011                 break;
8012         case PORT_CLK_SEL_WRPLL2:
8013                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8014                 break;
8015         }
8016 }
8017
8018 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8019                                        struct intel_crtc_config *pipe_config)
8020 {
8021         struct drm_device *dev = crtc->base.dev;
8022         struct drm_i915_private *dev_priv = dev->dev_private;
8023         struct intel_shared_dpll *pll;
8024         enum port port;
8025         uint32_t tmp;
8026
8027         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8028
8029         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8030
8031         if (IS_SKYLAKE(dev))
8032                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8033         else
8034                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8035
8036         if (pipe_config->shared_dpll >= 0) {
8037                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8038
8039                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8040                                            &pipe_config->dpll_hw_state));
8041         }
8042
8043         /*
8044          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8045          * DDI E. So just check whether this pipe is wired to DDI E and whether
8046          * the PCH transcoder is on.
8047          */
8048         if (INTEL_INFO(dev)->gen < 9 &&
8049             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8050                 pipe_config->has_pch_encoder = true;
8051
8052                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8053                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8054                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8055
8056                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8057         }
8058 }
8059
8060 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8061                                     struct intel_crtc_config *pipe_config)
8062 {
8063         struct drm_device *dev = crtc->base.dev;
8064         struct drm_i915_private *dev_priv = dev->dev_private;
8065         enum intel_display_power_domain pfit_domain;
8066         uint32_t tmp;
8067
8068         if (!intel_display_power_is_enabled(dev_priv,
8069                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8070                 return false;
8071
8072         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8073         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8074
8075         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8076         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8077                 enum pipe trans_edp_pipe;
8078                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8079                 default:
8080                         WARN(1, "unknown pipe linked to edp transcoder\n");
8081                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8082                 case TRANS_DDI_EDP_INPUT_A_ON:
8083                         trans_edp_pipe = PIPE_A;
8084                         break;
8085                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8086                         trans_edp_pipe = PIPE_B;
8087                         break;
8088                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8089                         trans_edp_pipe = PIPE_C;
8090                         break;
8091                 }
8092
8093                 if (trans_edp_pipe == crtc->pipe)
8094                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8095         }
8096
8097         if (!intel_display_power_is_enabled(dev_priv,
8098                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8099                 return false;
8100
8101         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8102         if (!(tmp & PIPECONF_ENABLE))
8103                 return false;
8104
8105         haswell_get_ddi_port_state(crtc, pipe_config);
8106
8107         intel_get_pipe_timings(crtc, pipe_config);
8108
8109         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8110         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8111                 if (IS_SKYLAKE(dev))
8112                         skylake_get_pfit_config(crtc, pipe_config);
8113                 else
8114                         ironlake_get_pfit_config(crtc, pipe_config);
8115         }
8116
8117         if (IS_HASWELL(dev))
8118                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8119                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8120
8121         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8122                 pipe_config->pixel_multiplier =
8123                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8124         } else {
8125                 pipe_config->pixel_multiplier = 1;
8126         }
8127
8128         return true;
8129 }
8130
8131 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8132 {
8133         struct drm_device *dev = crtc->dev;
8134         struct drm_i915_private *dev_priv = dev->dev_private;
8135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8136         uint32_t cntl = 0, size = 0;
8137
8138         if (base) {
8139                 unsigned int width = intel_crtc->cursor_width;
8140                 unsigned int height = intel_crtc->cursor_height;
8141                 unsigned int stride = roundup_pow_of_two(width) * 4;
8142
8143                 switch (stride) {
8144                 default:
8145                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8146                                   width, stride);
8147                         stride = 256;
8148                         /* fallthrough */
8149                 case 256:
8150                 case 512:
8151                 case 1024:
8152                 case 2048:
8153                         break;
8154                 }
8155
8156                 cntl |= CURSOR_ENABLE |
8157                         CURSOR_GAMMA_ENABLE |
8158                         CURSOR_FORMAT_ARGB |
8159                         CURSOR_STRIDE(stride);
8160
8161                 size = (height << 12) | width;
8162         }
8163
8164         if (intel_crtc->cursor_cntl != 0 &&
8165             (intel_crtc->cursor_base != base ||
8166              intel_crtc->cursor_size != size ||
8167              intel_crtc->cursor_cntl != cntl)) {
8168                 /* On these chipsets we can only modify the base/size/stride
8169                  * whilst the cursor is disabled.
8170                  */
8171                 I915_WRITE(_CURACNTR, 0);
8172                 POSTING_READ(_CURACNTR);
8173                 intel_crtc->cursor_cntl = 0;
8174         }
8175
8176         if (intel_crtc->cursor_base != base) {
8177                 I915_WRITE(_CURABASE, base);
8178                 intel_crtc->cursor_base = base;
8179         }
8180
8181         if (intel_crtc->cursor_size != size) {
8182                 I915_WRITE(CURSIZE, size);
8183                 intel_crtc->cursor_size = size;
8184         }
8185
8186         if (intel_crtc->cursor_cntl != cntl) {
8187                 I915_WRITE(_CURACNTR, cntl);
8188                 POSTING_READ(_CURACNTR);
8189                 intel_crtc->cursor_cntl = cntl;
8190         }
8191 }
8192
8193 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8194 {
8195         struct drm_device *dev = crtc->dev;
8196         struct drm_i915_private *dev_priv = dev->dev_private;
8197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8198         int pipe = intel_crtc->pipe;
8199         uint32_t cntl;
8200
8201         cntl = 0;
8202         if (base) {
8203                 cntl = MCURSOR_GAMMA_ENABLE;
8204                 switch (intel_crtc->cursor_width) {
8205                         case 64:
8206                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8207                                 break;
8208                         case 128:
8209                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8210                                 break;
8211                         case 256:
8212                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8213                                 break;
8214                         default:
8215                                 WARN_ON(1);
8216                                 return;
8217                 }
8218                 cntl |= pipe << 28; /* Connect to correct pipe */
8219
8220                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8221                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8222         }
8223
8224         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8225                 cntl |= CURSOR_ROTATE_180;
8226
8227         if (intel_crtc->cursor_cntl != cntl) {
8228                 I915_WRITE(CURCNTR(pipe), cntl);
8229                 POSTING_READ(CURCNTR(pipe));
8230                 intel_crtc->cursor_cntl = cntl;
8231         }
8232
8233         /* and commit changes on next vblank */
8234         I915_WRITE(CURBASE(pipe), base);
8235         POSTING_READ(CURBASE(pipe));
8236
8237         intel_crtc->cursor_base = base;
8238 }
8239
8240 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8241 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8242                                      bool on)
8243 {
8244         struct drm_device *dev = crtc->dev;
8245         struct drm_i915_private *dev_priv = dev->dev_private;
8246         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8247         int pipe = intel_crtc->pipe;
8248         int x = crtc->cursor_x;
8249         int y = crtc->cursor_y;
8250         u32 base = 0, pos = 0;
8251
8252         if (on)
8253                 base = intel_crtc->cursor_addr;
8254
8255         if (x >= intel_crtc->config.pipe_src_w)
8256                 base = 0;
8257
8258         if (y >= intel_crtc->config.pipe_src_h)
8259                 base = 0;
8260
8261         if (x < 0) {
8262                 if (x + intel_crtc->cursor_width <= 0)
8263                         base = 0;
8264
8265                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8266                 x = -x;
8267         }
8268         pos |= x << CURSOR_X_SHIFT;
8269
8270         if (y < 0) {
8271                 if (y + intel_crtc->cursor_height <= 0)
8272                         base = 0;
8273
8274                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8275                 y = -y;
8276         }
8277         pos |= y << CURSOR_Y_SHIFT;
8278
8279         if (base == 0 && intel_crtc->cursor_base == 0)
8280                 return;
8281
8282         I915_WRITE(CURPOS(pipe), pos);
8283
8284         /* ILK+ do this automagically */
8285         if (HAS_GMCH_DISPLAY(dev) &&
8286                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8287                 base += (intel_crtc->cursor_height *
8288                         intel_crtc->cursor_width - 1) * 4;
8289         }
8290
8291         if (IS_845G(dev) || IS_I865G(dev))
8292                 i845_update_cursor(crtc, base);
8293         else
8294                 i9xx_update_cursor(crtc, base);
8295 }
8296
8297 static bool cursor_size_ok(struct drm_device *dev,
8298                            uint32_t width, uint32_t height)
8299 {
8300         if (width == 0 || height == 0)
8301                 return false;
8302
8303         /*
8304          * 845g/865g are special in that they are only limited by
8305          * the width of their cursors, the height is arbitrary up to
8306          * the precision of the register. Everything else requires
8307          * square cursors, limited to a few power-of-two sizes.
8308          */
8309         if (IS_845G(dev) || IS_I865G(dev)) {
8310                 if ((width & 63) != 0)
8311                         return false;
8312
8313                 if (width > (IS_845G(dev) ? 64 : 512))
8314                         return false;
8315
8316                 if (height > 1023)
8317                         return false;
8318         } else {
8319                 switch (width | height) {
8320                 case 256:
8321                 case 128:
8322                         if (IS_GEN2(dev))
8323                                 return false;
8324                 case 64:
8325                         break;
8326                 default:
8327                         return false;
8328                 }
8329         }
8330
8331         return true;
8332 }
8333
8334 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8335                                      struct drm_i915_gem_object *obj,
8336                                      uint32_t width, uint32_t height)
8337 {
8338         struct drm_device *dev = crtc->dev;
8339         struct drm_i915_private *dev_priv = to_i915(dev);
8340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8341         enum pipe pipe = intel_crtc->pipe;
8342         unsigned old_width;
8343         uint32_t addr;
8344         int ret;
8345
8346         /* if we want to turn off the cursor ignore width and height */
8347         if (!obj) {
8348                 DRM_DEBUG_KMS("cursor off\n");
8349                 addr = 0;
8350                 mutex_lock(&dev->struct_mutex);
8351                 goto finish;
8352         }
8353
8354         /* we only need to pin inside GTT if cursor is non-phy */
8355         mutex_lock(&dev->struct_mutex);
8356         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8357                 unsigned alignment;
8358
8359                 /*
8360                  * Global gtt pte registers are special registers which actually
8361                  * forward writes to a chunk of system memory. Which means that
8362                  * there is no risk that the register values disappear as soon
8363                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8364                  * only the pin/unpin/fence and not more.
8365                  */
8366                 intel_runtime_pm_get(dev_priv);
8367
8368                 /* Note that the w/a also requires 2 PTE of padding following
8369                  * the bo. We currently fill all unused PTE with the shadow
8370                  * page and so we should always have valid PTE following the
8371                  * cursor preventing the VT-d warning.
8372                  */
8373                 alignment = 0;
8374                 if (need_vtd_wa(dev))
8375                         alignment = 64*1024;
8376
8377                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8378                 if (ret) {
8379                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8380                         intel_runtime_pm_put(dev_priv);
8381                         goto fail_locked;
8382                 }
8383
8384                 ret = i915_gem_object_put_fence(obj);
8385                 if (ret) {
8386                         DRM_DEBUG_KMS("failed to release fence for cursor");
8387                         intel_runtime_pm_put(dev_priv);
8388                         goto fail_unpin;
8389                 }
8390
8391                 addr = i915_gem_obj_ggtt_offset(obj);
8392
8393                 intel_runtime_pm_put(dev_priv);
8394         } else {
8395                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8396                 ret = i915_gem_object_attach_phys(obj, align);
8397                 if (ret) {
8398                         DRM_DEBUG_KMS("failed to attach phys object\n");
8399                         goto fail_locked;
8400                 }
8401                 addr = obj->phys_handle->busaddr;
8402         }
8403
8404  finish:
8405         if (intel_crtc->cursor_bo) {
8406                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8407                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8408         }
8409
8410         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8411                           INTEL_FRONTBUFFER_CURSOR(pipe));
8412         mutex_unlock(&dev->struct_mutex);
8413
8414         old_width = intel_crtc->cursor_width;
8415
8416         intel_crtc->cursor_addr = addr;
8417         intel_crtc->cursor_bo = obj;
8418         intel_crtc->cursor_width = width;
8419         intel_crtc->cursor_height = height;
8420
8421         if (intel_crtc->active) {
8422                 if (old_width != width)
8423                         intel_update_watermarks(crtc);
8424                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8425
8426                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8427         }
8428
8429         return 0;
8430 fail_unpin:
8431         i915_gem_object_unpin_from_display_plane(obj);
8432 fail_locked:
8433         mutex_unlock(&dev->struct_mutex);
8434         return ret;
8435 }
8436
8437 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8438                                  u16 *blue, uint32_t start, uint32_t size)
8439 {
8440         int end = (start + size > 256) ? 256 : start + size, i;
8441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8442
8443         for (i = start; i < end; i++) {
8444                 intel_crtc->lut_r[i] = red[i] >> 8;
8445                 intel_crtc->lut_g[i] = green[i] >> 8;
8446                 intel_crtc->lut_b[i] = blue[i] >> 8;
8447         }
8448
8449         intel_crtc_load_lut(crtc);
8450 }
8451
8452 /* VESA 640x480x72Hz mode to set on the pipe */
8453 static struct drm_display_mode load_detect_mode = {
8454         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8455                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8456 };
8457
8458 struct drm_framebuffer *
8459 __intel_framebuffer_create(struct drm_device *dev,
8460                            struct drm_mode_fb_cmd2 *mode_cmd,
8461                            struct drm_i915_gem_object *obj)
8462 {
8463         struct intel_framebuffer *intel_fb;
8464         int ret;
8465
8466         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8467         if (!intel_fb) {
8468                 drm_gem_object_unreference(&obj->base);
8469                 return ERR_PTR(-ENOMEM);
8470         }
8471
8472         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8473         if (ret)
8474                 goto err;
8475
8476         return &intel_fb->base;
8477 err:
8478         drm_gem_object_unreference(&obj->base);
8479         kfree(intel_fb);
8480
8481         return ERR_PTR(ret);
8482 }
8483
8484 static struct drm_framebuffer *
8485 intel_framebuffer_create(struct drm_device *dev,
8486                          struct drm_mode_fb_cmd2 *mode_cmd,
8487                          struct drm_i915_gem_object *obj)
8488 {
8489         struct drm_framebuffer *fb;
8490         int ret;
8491
8492         ret = i915_mutex_lock_interruptible(dev);
8493         if (ret)
8494                 return ERR_PTR(ret);
8495         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8496         mutex_unlock(&dev->struct_mutex);
8497
8498         return fb;
8499 }
8500
8501 static u32
8502 intel_framebuffer_pitch_for_width(int width, int bpp)
8503 {
8504         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8505         return ALIGN(pitch, 64);
8506 }
8507
8508 static u32
8509 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8510 {
8511         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8512         return PAGE_ALIGN(pitch * mode->vdisplay);
8513 }
8514
8515 static struct drm_framebuffer *
8516 intel_framebuffer_create_for_mode(struct drm_device *dev,
8517                                   struct drm_display_mode *mode,
8518                                   int depth, int bpp)
8519 {
8520         struct drm_i915_gem_object *obj;
8521         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8522
8523         obj = i915_gem_alloc_object(dev,
8524                                     intel_framebuffer_size_for_mode(mode, bpp));
8525         if (obj == NULL)
8526                 return ERR_PTR(-ENOMEM);
8527
8528         mode_cmd.width = mode->hdisplay;
8529         mode_cmd.height = mode->vdisplay;
8530         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8531                                                                 bpp);
8532         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8533
8534         return intel_framebuffer_create(dev, &mode_cmd, obj);
8535 }
8536
8537 static struct drm_framebuffer *
8538 mode_fits_in_fbdev(struct drm_device *dev,
8539                    struct drm_display_mode *mode)
8540 {
8541 #ifdef CONFIG_DRM_I915_FBDEV
8542         struct drm_i915_private *dev_priv = dev->dev_private;
8543         struct drm_i915_gem_object *obj;
8544         struct drm_framebuffer *fb;
8545
8546         if (!dev_priv->fbdev)
8547                 return NULL;
8548
8549         if (!dev_priv->fbdev->fb)
8550                 return NULL;
8551
8552         obj = dev_priv->fbdev->fb->obj;
8553         BUG_ON(!obj);
8554
8555         fb = &dev_priv->fbdev->fb->base;
8556         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8557                                                                fb->bits_per_pixel))
8558                 return NULL;
8559
8560         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8561                 return NULL;
8562
8563         return fb;
8564 #else
8565         return NULL;
8566 #endif
8567 }
8568
8569 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8570                                 struct drm_display_mode *mode,
8571                                 struct intel_load_detect_pipe *old,
8572                                 struct drm_modeset_acquire_ctx *ctx)
8573 {
8574         struct intel_crtc *intel_crtc;
8575         struct intel_encoder *intel_encoder =
8576                 intel_attached_encoder(connector);
8577         struct drm_crtc *possible_crtc;
8578         struct drm_encoder *encoder = &intel_encoder->base;
8579         struct drm_crtc *crtc = NULL;
8580         struct drm_device *dev = encoder->dev;
8581         struct drm_framebuffer *fb;
8582         struct drm_mode_config *config = &dev->mode_config;
8583         int ret, i = -1;
8584
8585         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8586                       connector->base.id, connector->name,
8587                       encoder->base.id, encoder->name);
8588
8589 retry:
8590         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8591         if (ret)
8592                 goto fail_unlock;
8593
8594         /*
8595          * Algorithm gets a little messy:
8596          *
8597          *   - if the connector already has an assigned crtc, use it (but make
8598          *     sure it's on first)
8599          *
8600          *   - try to find the first unused crtc that can drive this connector,
8601          *     and use that if we find one
8602          */
8603
8604         /* See if we already have a CRTC for this connector */
8605         if (encoder->crtc) {
8606                 crtc = encoder->crtc;
8607
8608                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8609                 if (ret)
8610                         goto fail_unlock;
8611
8612                 old->dpms_mode = connector->dpms;
8613                 old->load_detect_temp = false;
8614
8615                 /* Make sure the crtc and connector are running */
8616                 if (connector->dpms != DRM_MODE_DPMS_ON)
8617                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8618
8619                 return true;
8620         }
8621
8622         /* Find an unused one (if possible) */
8623         for_each_crtc(dev, possible_crtc) {
8624                 i++;
8625                 if (!(encoder->possible_crtcs & (1 << i)))
8626                         continue;
8627                 if (possible_crtc->enabled)
8628                         continue;
8629                 /* This can occur when applying the pipe A quirk on resume. */
8630                 if (to_intel_crtc(possible_crtc)->new_enabled)
8631                         continue;
8632
8633                 crtc = possible_crtc;
8634                 break;
8635         }
8636
8637         /*
8638          * If we didn't find an unused CRTC, don't use any.
8639          */
8640         if (!crtc) {
8641                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8642                 goto fail_unlock;
8643         }
8644
8645         ret = drm_modeset_lock(&crtc->mutex, ctx);
8646         if (ret)
8647                 goto fail_unlock;
8648         intel_encoder->new_crtc = to_intel_crtc(crtc);
8649         to_intel_connector(connector)->new_encoder = intel_encoder;
8650
8651         intel_crtc = to_intel_crtc(crtc);
8652         intel_crtc->new_enabled = true;
8653         intel_crtc->new_config = &intel_crtc->config;
8654         old->dpms_mode = connector->dpms;
8655         old->load_detect_temp = true;
8656         old->release_fb = NULL;
8657
8658         if (!mode)
8659                 mode = &load_detect_mode;
8660
8661         /* We need a framebuffer large enough to accommodate all accesses
8662          * that the plane may generate whilst we perform load detection.
8663          * We can not rely on the fbcon either being present (we get called
8664          * during its initialisation to detect all boot displays, or it may
8665          * not even exist) or that it is large enough to satisfy the
8666          * requested mode.
8667          */
8668         fb = mode_fits_in_fbdev(dev, mode);
8669         if (fb == NULL) {
8670                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8671                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8672                 old->release_fb = fb;
8673         } else
8674                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8675         if (IS_ERR(fb)) {
8676                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8677                 goto fail;
8678         }
8679
8680         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8681                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8682                 if (old->release_fb)
8683                         old->release_fb->funcs->destroy(old->release_fb);
8684                 goto fail;
8685         }
8686
8687         /* let the connector get through one full cycle before testing */
8688         intel_wait_for_vblank(dev, intel_crtc->pipe);
8689         return true;
8690
8691  fail:
8692         intel_crtc->new_enabled = crtc->enabled;
8693         if (intel_crtc->new_enabled)
8694                 intel_crtc->new_config = &intel_crtc->config;
8695         else
8696                 intel_crtc->new_config = NULL;
8697 fail_unlock:
8698         if (ret == -EDEADLK) {
8699                 drm_modeset_backoff(ctx);
8700                 goto retry;
8701         }
8702
8703         return false;
8704 }
8705
8706 void intel_release_load_detect_pipe(struct drm_connector *connector,
8707                                     struct intel_load_detect_pipe *old)
8708 {
8709         struct intel_encoder *intel_encoder =
8710                 intel_attached_encoder(connector);
8711         struct drm_encoder *encoder = &intel_encoder->base;
8712         struct drm_crtc *crtc = encoder->crtc;
8713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8714
8715         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8716                       connector->base.id, connector->name,
8717                       encoder->base.id, encoder->name);
8718
8719         if (old->load_detect_temp) {
8720                 to_intel_connector(connector)->new_encoder = NULL;
8721                 intel_encoder->new_crtc = NULL;
8722                 intel_crtc->new_enabled = false;
8723                 intel_crtc->new_config = NULL;
8724                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8725
8726                 if (old->release_fb) {
8727                         drm_framebuffer_unregister_private(old->release_fb);
8728                         drm_framebuffer_unreference(old->release_fb);
8729                 }
8730
8731                 return;
8732         }
8733
8734         /* Switch crtc and encoder back off if necessary */
8735         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8736                 connector->funcs->dpms(connector, old->dpms_mode);
8737 }
8738
8739 static int i9xx_pll_refclk(struct drm_device *dev,
8740                            const struct intel_crtc_config *pipe_config)
8741 {
8742         struct drm_i915_private *dev_priv = dev->dev_private;
8743         u32 dpll = pipe_config->dpll_hw_state.dpll;
8744
8745         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8746                 return dev_priv->vbt.lvds_ssc_freq;
8747         else if (HAS_PCH_SPLIT(dev))
8748                 return 120000;
8749         else if (!IS_GEN2(dev))
8750                 return 96000;
8751         else
8752                 return 48000;
8753 }
8754
8755 /* Returns the clock of the currently programmed mode of the given pipe. */
8756 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8757                                 struct intel_crtc_config *pipe_config)
8758 {
8759         struct drm_device *dev = crtc->base.dev;
8760         struct drm_i915_private *dev_priv = dev->dev_private;
8761         int pipe = pipe_config->cpu_transcoder;
8762         u32 dpll = pipe_config->dpll_hw_state.dpll;
8763         u32 fp;
8764         intel_clock_t clock;
8765         int refclk = i9xx_pll_refclk(dev, pipe_config);
8766
8767         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8768                 fp = pipe_config->dpll_hw_state.fp0;
8769         else
8770                 fp = pipe_config->dpll_hw_state.fp1;
8771
8772         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8773         if (IS_PINEVIEW(dev)) {
8774                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8775                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8776         } else {
8777                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8778                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8779         }
8780
8781         if (!IS_GEN2(dev)) {
8782                 if (IS_PINEVIEW(dev))
8783                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8784                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8785                 else
8786                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8787                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8788
8789                 switch (dpll & DPLL_MODE_MASK) {
8790                 case DPLLB_MODE_DAC_SERIAL:
8791                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8792                                 5 : 10;
8793                         break;
8794                 case DPLLB_MODE_LVDS:
8795                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8796                                 7 : 14;
8797                         break;
8798                 default:
8799                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8800                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8801                         return;
8802                 }
8803
8804                 if (IS_PINEVIEW(dev))
8805                         pineview_clock(refclk, &clock);
8806                 else
8807                         i9xx_clock(refclk, &clock);
8808         } else {
8809                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8810                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8811
8812                 if (is_lvds) {
8813                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8814                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8815
8816                         if (lvds & LVDS_CLKB_POWER_UP)
8817                                 clock.p2 = 7;
8818                         else
8819                                 clock.p2 = 14;
8820                 } else {
8821                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8822                                 clock.p1 = 2;
8823                         else {
8824                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8825                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8826                         }
8827                         if (dpll & PLL_P2_DIVIDE_BY_4)
8828                                 clock.p2 = 4;
8829                         else
8830                                 clock.p2 = 2;
8831                 }
8832
8833                 i9xx_clock(refclk, &clock);
8834         }
8835
8836         /*
8837          * This value includes pixel_multiplier. We will use
8838          * port_clock to compute adjusted_mode.crtc_clock in the
8839          * encoder's get_config() function.
8840          */
8841         pipe_config->port_clock = clock.dot;
8842 }
8843
8844 int intel_dotclock_calculate(int link_freq,
8845                              const struct intel_link_m_n *m_n)
8846 {
8847         /*
8848          * The calculation for the data clock is:
8849          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8850          * But we want to avoid losing precison if possible, so:
8851          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8852          *
8853          * and the link clock is simpler:
8854          * link_clock = (m * link_clock) / n
8855          */
8856
8857         if (!m_n->link_n)
8858                 return 0;
8859
8860         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8861 }
8862
8863 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8864                                    struct intel_crtc_config *pipe_config)
8865 {
8866         struct drm_device *dev = crtc->base.dev;
8867
8868         /* read out port_clock from the DPLL */
8869         i9xx_crtc_clock_get(crtc, pipe_config);
8870
8871         /*
8872          * This value does not include pixel_multiplier.
8873          * We will check that port_clock and adjusted_mode.crtc_clock
8874          * agree once we know their relationship in the encoder's
8875          * get_config() function.
8876          */
8877         pipe_config->adjusted_mode.crtc_clock =
8878                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8879                                          &pipe_config->fdi_m_n);
8880 }
8881
8882 /** Returns the currently programmed mode of the given pipe. */
8883 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8884                                              struct drm_crtc *crtc)
8885 {
8886         struct drm_i915_private *dev_priv = dev->dev_private;
8887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8888         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8889         struct drm_display_mode *mode;
8890         struct intel_crtc_config pipe_config;
8891         int htot = I915_READ(HTOTAL(cpu_transcoder));
8892         int hsync = I915_READ(HSYNC(cpu_transcoder));
8893         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8894         int vsync = I915_READ(VSYNC(cpu_transcoder));
8895         enum pipe pipe = intel_crtc->pipe;
8896
8897         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8898         if (!mode)
8899                 return NULL;
8900
8901         /*
8902          * Construct a pipe_config sufficient for getting the clock info
8903          * back out of crtc_clock_get.
8904          *
8905          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8906          * to use a real value here instead.
8907          */
8908         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8909         pipe_config.pixel_multiplier = 1;
8910         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8911         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8912         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8913         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8914
8915         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8916         mode->hdisplay = (htot & 0xffff) + 1;
8917         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8918         mode->hsync_start = (hsync & 0xffff) + 1;
8919         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8920         mode->vdisplay = (vtot & 0xffff) + 1;
8921         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8922         mode->vsync_start = (vsync & 0xffff) + 1;
8923         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8924
8925         drm_mode_set_name(mode);
8926
8927         return mode;
8928 }
8929
8930 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8931 {
8932         struct drm_device *dev = crtc->dev;
8933         struct drm_i915_private *dev_priv = dev->dev_private;
8934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8935
8936         if (!HAS_GMCH_DISPLAY(dev))
8937                 return;
8938
8939         if (!dev_priv->lvds_downclock_avail)
8940                 return;
8941
8942         /*
8943          * Since this is called by a timer, we should never get here in
8944          * the manual case.
8945          */
8946         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8947                 int pipe = intel_crtc->pipe;
8948                 int dpll_reg = DPLL(pipe);
8949                 int dpll;
8950
8951                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8952
8953                 assert_panel_unlocked(dev_priv, pipe);
8954
8955                 dpll = I915_READ(dpll_reg);
8956                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8957                 I915_WRITE(dpll_reg, dpll);
8958                 intel_wait_for_vblank(dev, pipe);
8959                 dpll = I915_READ(dpll_reg);
8960                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8961                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8962         }
8963
8964 }
8965
8966 void intel_mark_busy(struct drm_device *dev)
8967 {
8968         struct drm_i915_private *dev_priv = dev->dev_private;
8969
8970         if (dev_priv->mm.busy)
8971                 return;
8972
8973         intel_runtime_pm_get(dev_priv);
8974         i915_update_gfx_val(dev_priv);
8975         dev_priv->mm.busy = true;
8976 }
8977
8978 void intel_mark_idle(struct drm_device *dev)
8979 {
8980         struct drm_i915_private *dev_priv = dev->dev_private;
8981         struct drm_crtc *crtc;
8982
8983         if (!dev_priv->mm.busy)
8984                 return;
8985
8986         dev_priv->mm.busy = false;
8987
8988         if (!i915.powersave)
8989                 goto out;
8990
8991         for_each_crtc(dev, crtc) {
8992                 if (!crtc->primary->fb)
8993                         continue;
8994
8995                 intel_decrease_pllclock(crtc);
8996         }
8997
8998         if (INTEL_INFO(dev)->gen >= 6)
8999                 gen6_rps_idle(dev->dev_private);
9000
9001 out:
9002         intel_runtime_pm_put(dev_priv);
9003 }
9004
9005 static void intel_crtc_destroy(struct drm_crtc *crtc)
9006 {
9007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9008         struct drm_device *dev = crtc->dev;
9009         struct intel_unpin_work *work;
9010
9011         spin_lock_irq(&dev->event_lock);
9012         work = intel_crtc->unpin_work;
9013         intel_crtc->unpin_work = NULL;
9014         spin_unlock_irq(&dev->event_lock);
9015
9016         if (work) {
9017                 cancel_work_sync(&work->work);
9018                 kfree(work);
9019         }
9020
9021         drm_crtc_cleanup(crtc);
9022
9023         kfree(intel_crtc);
9024 }
9025
9026 static void intel_unpin_work_fn(struct work_struct *__work)
9027 {
9028         struct intel_unpin_work *work =
9029                 container_of(__work, struct intel_unpin_work, work);
9030         struct drm_device *dev = work->crtc->dev;
9031         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9032
9033         mutex_lock(&dev->struct_mutex);
9034         intel_unpin_fb_obj(work->old_fb_obj);
9035         drm_gem_object_unreference(&work->pending_flip_obj->base);
9036         drm_gem_object_unreference(&work->old_fb_obj->base);
9037
9038         intel_update_fbc(dev);
9039         mutex_unlock(&dev->struct_mutex);
9040
9041         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9042
9043         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9044         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9045
9046         kfree(work);
9047 }
9048
9049 static void do_intel_finish_page_flip(struct drm_device *dev,
9050                                       struct drm_crtc *crtc)
9051 {
9052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9053         struct intel_unpin_work *work;
9054         unsigned long flags;
9055
9056         /* Ignore early vblank irqs */
9057         if (intel_crtc == NULL)
9058                 return;
9059
9060         /*
9061          * This is called both by irq handlers and the reset code (to complete
9062          * lost pageflips) so needs the full irqsave spinlocks.
9063          */
9064         spin_lock_irqsave(&dev->event_lock, flags);
9065         work = intel_crtc->unpin_work;
9066
9067         /* Ensure we don't miss a work->pending update ... */
9068         smp_rmb();
9069
9070         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9071                 spin_unlock_irqrestore(&dev->event_lock, flags);
9072                 return;
9073         }
9074
9075         page_flip_completed(intel_crtc);
9076
9077         spin_unlock_irqrestore(&dev->event_lock, flags);
9078 }
9079
9080 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9081 {
9082         struct drm_i915_private *dev_priv = dev->dev_private;
9083         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9084
9085         do_intel_finish_page_flip(dev, crtc);
9086 }
9087
9088 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9089 {
9090         struct drm_i915_private *dev_priv = dev->dev_private;
9091         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9092
9093         do_intel_finish_page_flip(dev, crtc);
9094 }
9095
9096 /* Is 'a' after or equal to 'b'? */
9097 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9098 {
9099         return !((a - b) & 0x80000000);
9100 }
9101
9102 static bool page_flip_finished(struct intel_crtc *crtc)
9103 {
9104         struct drm_device *dev = crtc->base.dev;
9105         struct drm_i915_private *dev_priv = dev->dev_private;
9106
9107         /*
9108          * The relevant registers doen't exist on pre-ctg.
9109          * As the flip done interrupt doesn't trigger for mmio
9110          * flips on gmch platforms, a flip count check isn't
9111          * really needed there. But since ctg has the registers,
9112          * include it in the check anyway.
9113          */
9114         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9115                 return true;
9116
9117         /*
9118          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9119          * used the same base address. In that case the mmio flip might
9120          * have completed, but the CS hasn't even executed the flip yet.
9121          *
9122          * A flip count check isn't enough as the CS might have updated
9123          * the base address just after start of vblank, but before we
9124          * managed to process the interrupt. This means we'd complete the
9125          * CS flip too soon.
9126          *
9127          * Combining both checks should get us a good enough result. It may
9128          * still happen that the CS flip has been executed, but has not
9129          * yet actually completed. But in case the base address is the same
9130          * anyway, we don't really care.
9131          */
9132         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9133                 crtc->unpin_work->gtt_offset &&
9134                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9135                                     crtc->unpin_work->flip_count);
9136 }
9137
9138 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9139 {
9140         struct drm_i915_private *dev_priv = dev->dev_private;
9141         struct intel_crtc *intel_crtc =
9142                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9143         unsigned long flags;
9144
9145
9146         /*
9147          * This is called both by irq handlers and the reset code (to complete
9148          * lost pageflips) so needs the full irqsave spinlocks.
9149          *
9150          * NB: An MMIO update of the plane base pointer will also
9151          * generate a page-flip completion irq, i.e. every modeset
9152          * is also accompanied by a spurious intel_prepare_page_flip().
9153          */
9154         spin_lock_irqsave(&dev->event_lock, flags);
9155         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9156                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9157         spin_unlock_irqrestore(&dev->event_lock, flags);
9158 }
9159
9160 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9161 {
9162         /* Ensure that the work item is consistent when activating it ... */
9163         smp_wmb();
9164         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9165         /* and that it is marked active as soon as the irq could fire. */
9166         smp_wmb();
9167 }
9168
9169 static int intel_gen2_queue_flip(struct drm_device *dev,
9170                                  struct drm_crtc *crtc,
9171                                  struct drm_framebuffer *fb,
9172                                  struct drm_i915_gem_object *obj,
9173                                  struct intel_engine_cs *ring,
9174                                  uint32_t flags)
9175 {
9176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9177         u32 flip_mask;
9178         int ret;
9179
9180         ret = intel_ring_begin(ring, 6);
9181         if (ret)
9182                 return ret;
9183
9184         /* Can't queue multiple flips, so wait for the previous
9185          * one to finish before executing the next.
9186          */
9187         if (intel_crtc->plane)
9188                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9189         else
9190                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9191         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9192         intel_ring_emit(ring, MI_NOOP);
9193         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9194                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9195         intel_ring_emit(ring, fb->pitches[0]);
9196         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9197         intel_ring_emit(ring, 0); /* aux display base address, unused */
9198
9199         intel_mark_page_flip_active(intel_crtc);
9200         __intel_ring_advance(ring);
9201         return 0;
9202 }
9203
9204 static int intel_gen3_queue_flip(struct drm_device *dev,
9205                                  struct drm_crtc *crtc,
9206                                  struct drm_framebuffer *fb,
9207                                  struct drm_i915_gem_object *obj,
9208                                  struct intel_engine_cs *ring,
9209                                  uint32_t flags)
9210 {
9211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9212         u32 flip_mask;
9213         int ret;
9214
9215         ret = intel_ring_begin(ring, 6);
9216         if (ret)
9217                 return ret;
9218
9219         if (intel_crtc->plane)
9220                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9221         else
9222                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9223         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9224         intel_ring_emit(ring, MI_NOOP);
9225         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9226                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9227         intel_ring_emit(ring, fb->pitches[0]);
9228         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9229         intel_ring_emit(ring, MI_NOOP);
9230
9231         intel_mark_page_flip_active(intel_crtc);
9232         __intel_ring_advance(ring);
9233         return 0;
9234 }
9235
9236 static int intel_gen4_queue_flip(struct drm_device *dev,
9237                                  struct drm_crtc *crtc,
9238                                  struct drm_framebuffer *fb,
9239                                  struct drm_i915_gem_object *obj,
9240                                  struct intel_engine_cs *ring,
9241                                  uint32_t flags)
9242 {
9243         struct drm_i915_private *dev_priv = dev->dev_private;
9244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9245         uint32_t pf, pipesrc;
9246         int ret;
9247
9248         ret = intel_ring_begin(ring, 4);
9249         if (ret)
9250                 return ret;
9251
9252         /* i965+ uses the linear or tiled offsets from the
9253          * Display Registers (which do not change across a page-flip)
9254          * so we need only reprogram the base address.
9255          */
9256         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9257                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9258         intel_ring_emit(ring, fb->pitches[0]);
9259         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9260                         obj->tiling_mode);
9261
9262         /* XXX Enabling the panel-fitter across page-flip is so far
9263          * untested on non-native modes, so ignore it for now.
9264          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9265          */
9266         pf = 0;
9267         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9268         intel_ring_emit(ring, pf | pipesrc);
9269
9270         intel_mark_page_flip_active(intel_crtc);
9271         __intel_ring_advance(ring);
9272         return 0;
9273 }
9274
9275 static int intel_gen6_queue_flip(struct drm_device *dev,
9276                                  struct drm_crtc *crtc,
9277                                  struct drm_framebuffer *fb,
9278                                  struct drm_i915_gem_object *obj,
9279                                  struct intel_engine_cs *ring,
9280                                  uint32_t flags)
9281 {
9282         struct drm_i915_private *dev_priv = dev->dev_private;
9283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9284         uint32_t pf, pipesrc;
9285         int ret;
9286
9287         ret = intel_ring_begin(ring, 4);
9288         if (ret)
9289                 return ret;
9290
9291         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9292                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9293         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9294         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9295
9296         /* Contrary to the suggestions in the documentation,
9297          * "Enable Panel Fitter" does not seem to be required when page
9298          * flipping with a non-native mode, and worse causes a normal
9299          * modeset to fail.
9300          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9301          */
9302         pf = 0;
9303         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9304         intel_ring_emit(ring, pf | pipesrc);
9305
9306         intel_mark_page_flip_active(intel_crtc);
9307         __intel_ring_advance(ring);
9308         return 0;
9309 }
9310
9311 static int intel_gen7_queue_flip(struct drm_device *dev,
9312                                  struct drm_crtc *crtc,
9313                                  struct drm_framebuffer *fb,
9314                                  struct drm_i915_gem_object *obj,
9315                                  struct intel_engine_cs *ring,
9316                                  uint32_t flags)
9317 {
9318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9319         uint32_t plane_bit = 0;
9320         int len, ret;
9321
9322         switch (intel_crtc->plane) {
9323         case PLANE_A:
9324                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9325                 break;
9326         case PLANE_B:
9327                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9328                 break;
9329         case PLANE_C:
9330                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9331                 break;
9332         default:
9333                 WARN_ONCE(1, "unknown plane in flip command\n");
9334                 return -ENODEV;
9335         }
9336
9337         len = 4;
9338         if (ring->id == RCS) {
9339                 len += 6;
9340                 /*
9341                  * On Gen 8, SRM is now taking an extra dword to accommodate
9342                  * 48bits addresses, and we need a NOOP for the batch size to
9343                  * stay even.
9344                  */
9345                 if (IS_GEN8(dev))
9346                         len += 2;
9347         }
9348
9349         /*
9350          * BSpec MI_DISPLAY_FLIP for IVB:
9351          * "The full packet must be contained within the same cache line."
9352          *
9353          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9354          * cacheline, if we ever start emitting more commands before
9355          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9356          * then do the cacheline alignment, and finally emit the
9357          * MI_DISPLAY_FLIP.
9358          */
9359         ret = intel_ring_cacheline_align(ring);
9360         if (ret)
9361                 return ret;
9362
9363         ret = intel_ring_begin(ring, len);
9364         if (ret)
9365                 return ret;
9366
9367         /* Unmask the flip-done completion message. Note that the bspec says that
9368          * we should do this for both the BCS and RCS, and that we must not unmask
9369          * more than one flip event at any time (or ensure that one flip message
9370          * can be sent by waiting for flip-done prior to queueing new flips).
9371          * Experimentation says that BCS works despite DERRMR masking all
9372          * flip-done completion events and that unmasking all planes at once
9373          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9374          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9375          */
9376         if (ring->id == RCS) {
9377                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9378                 intel_ring_emit(ring, DERRMR);
9379                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9380                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9381                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9382                 if (IS_GEN8(dev))
9383                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9384                                               MI_SRM_LRM_GLOBAL_GTT);
9385                 else
9386                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9387                                               MI_SRM_LRM_GLOBAL_GTT);
9388                 intel_ring_emit(ring, DERRMR);
9389                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9390                 if (IS_GEN8(dev)) {
9391                         intel_ring_emit(ring, 0);
9392                         intel_ring_emit(ring, MI_NOOP);
9393                 }
9394         }
9395
9396         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9397         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9398         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9399         intel_ring_emit(ring, (MI_NOOP));
9400
9401         intel_mark_page_flip_active(intel_crtc);
9402         __intel_ring_advance(ring);
9403         return 0;
9404 }
9405
9406 static bool use_mmio_flip(struct intel_engine_cs *ring,
9407                           struct drm_i915_gem_object *obj)
9408 {
9409         /*
9410          * This is not being used for older platforms, because
9411          * non-availability of flip done interrupt forces us to use
9412          * CS flips. Older platforms derive flip done using some clever
9413          * tricks involving the flip_pending status bits and vblank irqs.
9414          * So using MMIO flips there would disrupt this mechanism.
9415          */
9416
9417         if (ring == NULL)
9418                 return true;
9419
9420         if (INTEL_INFO(ring->dev)->gen < 5)
9421                 return false;
9422
9423         if (i915.use_mmio_flip < 0)
9424                 return false;
9425         else if (i915.use_mmio_flip > 0)
9426                 return true;
9427         else if (i915.enable_execlists)
9428                 return true;
9429         else
9430                 return ring != obj->ring;
9431 }
9432
9433 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9434 {
9435         struct drm_device *dev = intel_crtc->base.dev;
9436         struct drm_i915_private *dev_priv = dev->dev_private;
9437         struct intel_framebuffer *intel_fb =
9438                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9439         struct drm_i915_gem_object *obj = intel_fb->obj;
9440         bool atomic_update;
9441         u32 start_vbl_count;
9442         u32 dspcntr;
9443         u32 reg;
9444
9445         intel_mark_page_flip_active(intel_crtc);
9446
9447         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9448
9449         reg = DSPCNTR(intel_crtc->plane);
9450         dspcntr = I915_READ(reg);
9451
9452         if (obj->tiling_mode != I915_TILING_NONE)
9453                 dspcntr |= DISPPLANE_TILED;
9454         else
9455                 dspcntr &= ~DISPPLANE_TILED;
9456
9457         I915_WRITE(reg, dspcntr);
9458
9459         I915_WRITE(DSPSURF(intel_crtc->plane),
9460                    intel_crtc->unpin_work->gtt_offset);
9461         POSTING_READ(DSPSURF(intel_crtc->plane));
9462
9463         if (atomic_update)
9464                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9465 }
9466
9467 static void intel_mmio_flip_work_func(struct work_struct *work)
9468 {
9469         struct intel_crtc *intel_crtc =
9470                 container_of(work, struct intel_crtc, mmio_flip.work);
9471         struct intel_engine_cs *ring;
9472         uint32_t seqno;
9473
9474         seqno = intel_crtc->mmio_flip.seqno;
9475         ring = intel_crtc->mmio_flip.ring;
9476
9477         if (seqno)
9478                 WARN_ON(__i915_wait_seqno(ring, seqno,
9479                                           intel_crtc->reset_counter,
9480                                           false, NULL, NULL) != 0);
9481
9482         intel_do_mmio_flip(intel_crtc);
9483 }
9484
9485 static int intel_queue_mmio_flip(struct drm_device *dev,
9486                                  struct drm_crtc *crtc,
9487                                  struct drm_framebuffer *fb,
9488                                  struct drm_i915_gem_object *obj,
9489                                  struct intel_engine_cs *ring,
9490                                  uint32_t flags)
9491 {
9492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9493
9494         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9495         intel_crtc->mmio_flip.ring = obj->ring;
9496
9497         schedule_work(&intel_crtc->mmio_flip.work);
9498
9499         return 0;
9500 }
9501
9502 static int intel_gen9_queue_flip(struct drm_device *dev,
9503                                  struct drm_crtc *crtc,
9504                                  struct drm_framebuffer *fb,
9505                                  struct drm_i915_gem_object *obj,
9506                                  struct intel_engine_cs *ring,
9507                                  uint32_t flags)
9508 {
9509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9510         uint32_t plane = 0, stride;
9511         int ret;
9512
9513         switch(intel_crtc->pipe) {
9514         case PIPE_A:
9515                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9516                 break;
9517         case PIPE_B:
9518                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9519                 break;
9520         case PIPE_C:
9521                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9522                 break;
9523         default:
9524                 WARN_ONCE(1, "unknown plane in flip command\n");
9525                 return -ENODEV;
9526         }
9527
9528         switch (obj->tiling_mode) {
9529         case I915_TILING_NONE:
9530                 stride = fb->pitches[0] >> 6;
9531                 break;
9532         case I915_TILING_X:
9533                 stride = fb->pitches[0] >> 9;
9534                 break;
9535         default:
9536                 WARN_ONCE(1, "unknown tiling in flip command\n");
9537                 return -ENODEV;
9538         }
9539
9540         ret = intel_ring_begin(ring, 10);
9541         if (ret)
9542                 return ret;
9543
9544         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9545         intel_ring_emit(ring, DERRMR);
9546         intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9547                                 DERRMR_PIPEB_PRI_FLIP_DONE |
9548                                 DERRMR_PIPEC_PRI_FLIP_DONE));
9549         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9550                               MI_SRM_LRM_GLOBAL_GTT);
9551         intel_ring_emit(ring, DERRMR);
9552         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9553         intel_ring_emit(ring, 0);
9554
9555         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9556         intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9557         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9558
9559         intel_mark_page_flip_active(intel_crtc);
9560         __intel_ring_advance(ring);
9561
9562         return 0;
9563 }
9564
9565 static int intel_default_queue_flip(struct drm_device *dev,
9566                                     struct drm_crtc *crtc,
9567                                     struct drm_framebuffer *fb,
9568                                     struct drm_i915_gem_object *obj,
9569                                     struct intel_engine_cs *ring,
9570                                     uint32_t flags)
9571 {
9572         return -ENODEV;
9573 }
9574
9575 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9576                                          struct drm_crtc *crtc)
9577 {
9578         struct drm_i915_private *dev_priv = dev->dev_private;
9579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9580         struct intel_unpin_work *work = intel_crtc->unpin_work;
9581         u32 addr;
9582
9583         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9584                 return true;
9585
9586         if (!work->enable_stall_check)
9587                 return false;
9588
9589         if (work->flip_ready_vblank == 0) {
9590                 if (work->flip_queued_ring &&
9591                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9592                                        work->flip_queued_seqno))
9593                         return false;
9594
9595                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9596         }
9597
9598         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9599                 return false;
9600
9601         /* Potential stall - if we see that the flip has happened,
9602          * assume a missed interrupt. */
9603         if (INTEL_INFO(dev)->gen >= 4)
9604                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9605         else
9606                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9607
9608         /* There is a potential issue here with a false positive after a flip
9609          * to the same address. We could address this by checking for a
9610          * non-incrementing frame counter.
9611          */
9612         return addr == work->gtt_offset;
9613 }
9614
9615 void intel_check_page_flip(struct drm_device *dev, int pipe)
9616 {
9617         struct drm_i915_private *dev_priv = dev->dev_private;
9618         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9620
9621         WARN_ON(!in_irq());
9622
9623         if (crtc == NULL)
9624                 return;
9625
9626         spin_lock(&dev->event_lock);
9627         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9628                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9629                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9630                 page_flip_completed(intel_crtc);
9631         }
9632         spin_unlock(&dev->event_lock);
9633 }
9634
9635 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9636                                 struct drm_framebuffer *fb,
9637                                 struct drm_pending_vblank_event *event,
9638                                 uint32_t page_flip_flags)
9639 {
9640         struct drm_device *dev = crtc->dev;
9641         struct drm_i915_private *dev_priv = dev->dev_private;
9642         struct drm_framebuffer *old_fb = crtc->primary->fb;
9643         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9645         enum pipe pipe = intel_crtc->pipe;
9646         struct intel_unpin_work *work;
9647         struct intel_engine_cs *ring;
9648         int ret;
9649
9650         /*
9651          * drm_mode_page_flip_ioctl() should already catch this, but double
9652          * check to be safe.  In the future we may enable pageflipping from
9653          * a disabled primary plane.
9654          */
9655         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9656                 return -EBUSY;
9657
9658         /* Can't change pixel format via MI display flips. */
9659         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9660                 return -EINVAL;
9661
9662         /*
9663          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9664          * Note that pitch changes could also affect these register.
9665          */
9666         if (INTEL_INFO(dev)->gen > 3 &&
9667             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9668              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9669                 return -EINVAL;
9670
9671         if (i915_terminally_wedged(&dev_priv->gpu_error))
9672                 goto out_hang;
9673
9674         work = kzalloc(sizeof(*work), GFP_KERNEL);
9675         if (work == NULL)
9676                 return -ENOMEM;
9677
9678         work->event = event;
9679         work->crtc = crtc;
9680         work->old_fb_obj = intel_fb_obj(old_fb);
9681         INIT_WORK(&work->work, intel_unpin_work_fn);
9682
9683         ret = drm_crtc_vblank_get(crtc);
9684         if (ret)
9685                 goto free_work;
9686
9687         /* We borrow the event spin lock for protecting unpin_work */
9688         spin_lock_irq(&dev->event_lock);
9689         if (intel_crtc->unpin_work) {
9690                 /* Before declaring the flip queue wedged, check if
9691                  * the hardware completed the operation behind our backs.
9692                  */
9693                 if (__intel_pageflip_stall_check(dev, crtc)) {
9694                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9695                         page_flip_completed(intel_crtc);
9696                 } else {
9697                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9698                         spin_unlock_irq(&dev->event_lock);
9699
9700                         drm_crtc_vblank_put(crtc);
9701                         kfree(work);
9702                         return -EBUSY;
9703                 }
9704         }
9705         intel_crtc->unpin_work = work;
9706         spin_unlock_irq(&dev->event_lock);
9707
9708         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9709                 flush_workqueue(dev_priv->wq);
9710
9711         ret = i915_mutex_lock_interruptible(dev);
9712         if (ret)
9713                 goto cleanup;
9714
9715         /* Reference the objects for the scheduled work. */
9716         drm_gem_object_reference(&work->old_fb_obj->base);
9717         drm_gem_object_reference(&obj->base);
9718
9719         crtc->primary->fb = fb;
9720
9721         work->pending_flip_obj = obj;
9722
9723         atomic_inc(&intel_crtc->unpin_work_count);
9724         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9725
9726         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9727                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9728
9729         if (IS_VALLEYVIEW(dev)) {
9730                 ring = &dev_priv->ring[BCS];
9731                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9732                         /* vlv: DISPLAY_FLIP fails to change tiling */
9733                         ring = NULL;
9734         } else if (IS_IVYBRIDGE(dev)) {
9735                 ring = &dev_priv->ring[BCS];
9736         } else if (INTEL_INFO(dev)->gen >= 7) {
9737                 ring = obj->ring;
9738                 if (ring == NULL || ring->id != RCS)
9739                         ring = &dev_priv->ring[BCS];
9740         } else {
9741                 ring = &dev_priv->ring[RCS];
9742         }
9743
9744         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9745         if (ret)
9746                 goto cleanup_pending;
9747
9748         work->gtt_offset =
9749                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9750
9751         if (use_mmio_flip(ring, obj)) {
9752                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9753                                             page_flip_flags);
9754                 if (ret)
9755                         goto cleanup_unpin;
9756
9757                 work->flip_queued_seqno = obj->last_write_seqno;
9758                 work->flip_queued_ring = obj->ring;
9759         } else {
9760                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9761                                                    page_flip_flags);
9762                 if (ret)
9763                         goto cleanup_unpin;
9764
9765                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9766                 work->flip_queued_ring = ring;
9767         }
9768
9769         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9770         work->enable_stall_check = true;
9771
9772         i915_gem_track_fb(work->old_fb_obj, obj,
9773                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9774
9775         intel_disable_fbc(dev);
9776         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9777         mutex_unlock(&dev->struct_mutex);
9778
9779         trace_i915_flip_request(intel_crtc->plane, obj);
9780
9781         return 0;
9782
9783 cleanup_unpin:
9784         intel_unpin_fb_obj(obj);
9785 cleanup_pending:
9786         atomic_dec(&intel_crtc->unpin_work_count);
9787         crtc->primary->fb = old_fb;
9788         drm_gem_object_unreference(&work->old_fb_obj->base);
9789         drm_gem_object_unreference(&obj->base);
9790         mutex_unlock(&dev->struct_mutex);
9791
9792 cleanup:
9793         spin_lock_irq(&dev->event_lock);
9794         intel_crtc->unpin_work = NULL;
9795         spin_unlock_irq(&dev->event_lock);
9796
9797         drm_crtc_vblank_put(crtc);
9798 free_work:
9799         kfree(work);
9800
9801         if (ret == -EIO) {
9802 out_hang:
9803                 intel_crtc_wait_for_pending_flips(crtc);
9804                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9805                 if (ret == 0 && event) {
9806                         spin_lock_irq(&dev->event_lock);
9807                         drm_send_vblank_event(dev, pipe, event);
9808                         spin_unlock_irq(&dev->event_lock);
9809                 }
9810         }
9811         return ret;
9812 }
9813
9814 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9815         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9816         .load_lut = intel_crtc_load_lut,
9817 };
9818
9819 /**
9820  * intel_modeset_update_staged_output_state
9821  *
9822  * Updates the staged output configuration state, e.g. after we've read out the
9823  * current hw state.
9824  */
9825 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9826 {
9827         struct intel_crtc *crtc;
9828         struct intel_encoder *encoder;
9829         struct intel_connector *connector;
9830
9831         list_for_each_entry(connector, &dev->mode_config.connector_list,
9832                             base.head) {
9833                 connector->new_encoder =
9834                         to_intel_encoder(connector->base.encoder);
9835         }
9836
9837         for_each_intel_encoder(dev, encoder) {
9838                 encoder->new_crtc =
9839                         to_intel_crtc(encoder->base.crtc);
9840         }
9841
9842         for_each_intel_crtc(dev, crtc) {
9843                 crtc->new_enabled = crtc->base.enabled;
9844
9845                 if (crtc->new_enabled)
9846                         crtc->new_config = &crtc->config;
9847                 else
9848                         crtc->new_config = NULL;
9849         }
9850 }
9851
9852 /**
9853  * intel_modeset_commit_output_state
9854  *
9855  * This function copies the stage display pipe configuration to the real one.
9856  */
9857 static void intel_modeset_commit_output_state(struct drm_device *dev)
9858 {
9859         struct intel_crtc *crtc;
9860         struct intel_encoder *encoder;
9861         struct intel_connector *connector;
9862
9863         list_for_each_entry(connector, &dev->mode_config.connector_list,
9864                             base.head) {
9865                 connector->base.encoder = &connector->new_encoder->base;
9866         }
9867
9868         for_each_intel_encoder(dev, encoder) {
9869                 encoder->base.crtc = &encoder->new_crtc->base;
9870         }
9871
9872         for_each_intel_crtc(dev, crtc) {
9873                 crtc->base.enabled = crtc->new_enabled;
9874         }
9875 }
9876
9877 static void
9878 connected_sink_compute_bpp(struct intel_connector *connector,
9879                            struct intel_crtc_config *pipe_config)
9880 {
9881         int bpp = pipe_config->pipe_bpp;
9882
9883         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9884                 connector->base.base.id,
9885                 connector->base.name);
9886
9887         /* Don't use an invalid EDID bpc value */
9888         if (connector->base.display_info.bpc &&
9889             connector->base.display_info.bpc * 3 < bpp) {
9890                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9891                               bpp, connector->base.display_info.bpc*3);
9892                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9893         }
9894
9895         /* Clamp bpp to 8 on screens without EDID 1.4 */
9896         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9897                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9898                               bpp);
9899                 pipe_config->pipe_bpp = 24;
9900         }
9901 }
9902
9903 static int
9904 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9905                           struct drm_framebuffer *fb,
9906                           struct intel_crtc_config *pipe_config)
9907 {
9908         struct drm_device *dev = crtc->base.dev;
9909         struct intel_connector *connector;
9910         int bpp;
9911
9912         switch (fb->pixel_format) {
9913         case DRM_FORMAT_C8:
9914                 bpp = 8*3; /* since we go through a colormap */
9915                 break;
9916         case DRM_FORMAT_XRGB1555:
9917         case DRM_FORMAT_ARGB1555:
9918                 /* checked in intel_framebuffer_init already */
9919                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9920                         return -EINVAL;
9921         case DRM_FORMAT_RGB565:
9922                 bpp = 6*3; /* min is 18bpp */
9923                 break;
9924         case DRM_FORMAT_XBGR8888:
9925         case DRM_FORMAT_ABGR8888:
9926                 /* checked in intel_framebuffer_init already */
9927                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9928                         return -EINVAL;
9929         case DRM_FORMAT_XRGB8888:
9930         case DRM_FORMAT_ARGB8888:
9931                 bpp = 8*3;
9932                 break;
9933         case DRM_FORMAT_XRGB2101010:
9934         case DRM_FORMAT_ARGB2101010:
9935         case DRM_FORMAT_XBGR2101010:
9936         case DRM_FORMAT_ABGR2101010:
9937                 /* checked in intel_framebuffer_init already */
9938                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9939                         return -EINVAL;
9940                 bpp = 10*3;
9941                 break;
9942         /* TODO: gen4+ supports 16 bpc floating point, too. */
9943         default:
9944                 DRM_DEBUG_KMS("unsupported depth\n");
9945                 return -EINVAL;
9946         }
9947
9948         pipe_config->pipe_bpp = bpp;
9949
9950         /* Clamp display bpp to EDID value */
9951         list_for_each_entry(connector, &dev->mode_config.connector_list,
9952                             base.head) {
9953                 if (!connector->new_encoder ||
9954                     connector->new_encoder->new_crtc != crtc)
9955                         continue;
9956
9957                 connected_sink_compute_bpp(connector, pipe_config);
9958         }
9959
9960         return bpp;
9961 }
9962
9963 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9964 {
9965         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9966                         "type: 0x%x flags: 0x%x\n",
9967                 mode->crtc_clock,
9968                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9969                 mode->crtc_hsync_end, mode->crtc_htotal,
9970                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9971                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9972 }
9973
9974 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9975                                    struct intel_crtc_config *pipe_config,
9976                                    const char *context)
9977 {
9978         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9979                       context, pipe_name(crtc->pipe));
9980
9981         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9982         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9983                       pipe_config->pipe_bpp, pipe_config->dither);
9984         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9985                       pipe_config->has_pch_encoder,
9986                       pipe_config->fdi_lanes,
9987                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9988                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9989                       pipe_config->fdi_m_n.tu);
9990         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9991                       pipe_config->has_dp_encoder,
9992                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9993                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9994                       pipe_config->dp_m_n.tu);
9995
9996         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9997                       pipe_config->has_dp_encoder,
9998                       pipe_config->dp_m2_n2.gmch_m,
9999                       pipe_config->dp_m2_n2.gmch_n,
10000                       pipe_config->dp_m2_n2.link_m,
10001                       pipe_config->dp_m2_n2.link_n,
10002                       pipe_config->dp_m2_n2.tu);
10003
10004         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10005                       pipe_config->has_audio,
10006                       pipe_config->has_infoframe);
10007
10008         DRM_DEBUG_KMS("requested mode:\n");
10009         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10010         DRM_DEBUG_KMS("adjusted mode:\n");
10011         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10012         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10013         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10014         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10015                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10016         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10017                       pipe_config->gmch_pfit.control,
10018                       pipe_config->gmch_pfit.pgm_ratios,
10019                       pipe_config->gmch_pfit.lvds_border_bits);
10020         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10021                       pipe_config->pch_pfit.pos,
10022                       pipe_config->pch_pfit.size,
10023                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10024         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10025         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10026 }
10027
10028 static bool encoders_cloneable(const struct intel_encoder *a,
10029                                const struct intel_encoder *b)
10030 {
10031         /* masks could be asymmetric, so check both ways */
10032         return a == b || (a->cloneable & (1 << b->type) &&
10033                           b->cloneable & (1 << a->type));
10034 }
10035
10036 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10037                                          struct intel_encoder *encoder)
10038 {
10039         struct drm_device *dev = crtc->base.dev;
10040         struct intel_encoder *source_encoder;
10041
10042         for_each_intel_encoder(dev, source_encoder) {
10043                 if (source_encoder->new_crtc != crtc)
10044                         continue;
10045
10046                 if (!encoders_cloneable(encoder, source_encoder))
10047                         return false;
10048         }
10049
10050         return true;
10051 }
10052
10053 static bool check_encoder_cloning(struct intel_crtc *crtc)
10054 {
10055         struct drm_device *dev = crtc->base.dev;
10056         struct intel_encoder *encoder;
10057
10058         for_each_intel_encoder(dev, encoder) {
10059                 if (encoder->new_crtc != crtc)
10060                         continue;
10061
10062                 if (!check_single_encoder_cloning(crtc, encoder))
10063                         return false;
10064         }
10065
10066         return true;
10067 }
10068
10069 static struct intel_crtc_config *
10070 intel_modeset_pipe_config(struct drm_crtc *crtc,
10071                           struct drm_framebuffer *fb,
10072                           struct drm_display_mode *mode)
10073 {
10074         struct drm_device *dev = crtc->dev;
10075         struct intel_encoder *encoder;
10076         struct intel_crtc_config *pipe_config;
10077         int plane_bpp, ret = -EINVAL;
10078         bool retry = true;
10079
10080         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10081                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10082                 return ERR_PTR(-EINVAL);
10083         }
10084
10085         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10086         if (!pipe_config)
10087                 return ERR_PTR(-ENOMEM);
10088
10089         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10090         drm_mode_copy(&pipe_config->requested_mode, mode);
10091
10092         pipe_config->cpu_transcoder =
10093                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10094         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10095
10096         /*
10097          * Sanitize sync polarity flags based on requested ones. If neither
10098          * positive or negative polarity is requested, treat this as meaning
10099          * negative polarity.
10100          */
10101         if (!(pipe_config->adjusted_mode.flags &
10102               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10103                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10104
10105         if (!(pipe_config->adjusted_mode.flags &
10106               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10107                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10108
10109         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10110          * plane pixel format and any sink constraints into account. Returns the
10111          * source plane bpp so that dithering can be selected on mismatches
10112          * after encoders and crtc also have had their say. */
10113         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10114                                               fb, pipe_config);
10115         if (plane_bpp < 0)
10116                 goto fail;
10117
10118         /*
10119          * Determine the real pipe dimensions. Note that stereo modes can
10120          * increase the actual pipe size due to the frame doubling and
10121          * insertion of additional space for blanks between the frame. This
10122          * is stored in the crtc timings. We use the requested mode to do this
10123          * computation to clearly distinguish it from the adjusted mode, which
10124          * can be changed by the connectors in the below retry loop.
10125          */
10126         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10127         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10128         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10129
10130 encoder_retry:
10131         /* Ensure the port clock defaults are reset when retrying. */
10132         pipe_config->port_clock = 0;
10133         pipe_config->pixel_multiplier = 1;
10134
10135         /* Fill in default crtc timings, allow encoders to overwrite them. */
10136         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10137
10138         /* Pass our mode to the connectors and the CRTC to give them a chance to
10139          * adjust it according to limitations or connector properties, and also
10140          * a chance to reject the mode entirely.
10141          */
10142         for_each_intel_encoder(dev, encoder) {
10143
10144                 if (&encoder->new_crtc->base != crtc)
10145                         continue;
10146
10147                 if (!(encoder->compute_config(encoder, pipe_config))) {
10148                         DRM_DEBUG_KMS("Encoder config failure\n");
10149                         goto fail;
10150                 }
10151         }
10152
10153         /* Set default port clock if not overwritten by the encoder. Needs to be
10154          * done afterwards in case the encoder adjusts the mode. */
10155         if (!pipe_config->port_clock)
10156                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10157                         * pipe_config->pixel_multiplier;
10158
10159         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10160         if (ret < 0) {
10161                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10162                 goto fail;
10163         }
10164
10165         if (ret == RETRY) {
10166                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10167                         ret = -EINVAL;
10168                         goto fail;
10169                 }
10170
10171                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10172                 retry = false;
10173                 goto encoder_retry;
10174         }
10175
10176         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10177         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10178                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10179
10180         return pipe_config;
10181 fail:
10182         kfree(pipe_config);
10183         return ERR_PTR(ret);
10184 }
10185
10186 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10187  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10188 static void
10189 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10190                              unsigned *prepare_pipes, unsigned *disable_pipes)
10191 {
10192         struct intel_crtc *intel_crtc;
10193         struct drm_device *dev = crtc->dev;
10194         struct intel_encoder *encoder;
10195         struct intel_connector *connector;
10196         struct drm_crtc *tmp_crtc;
10197
10198         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10199
10200         /* Check which crtcs have changed outputs connected to them, these need
10201          * to be part of the prepare_pipes mask. We don't (yet) support global
10202          * modeset across multiple crtcs, so modeset_pipes will only have one
10203          * bit set at most. */
10204         list_for_each_entry(connector, &dev->mode_config.connector_list,
10205                             base.head) {
10206                 if (connector->base.encoder == &connector->new_encoder->base)
10207                         continue;
10208
10209                 if (connector->base.encoder) {
10210                         tmp_crtc = connector->base.encoder->crtc;
10211
10212                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10213                 }
10214
10215                 if (connector->new_encoder)
10216                         *prepare_pipes |=
10217                                 1 << connector->new_encoder->new_crtc->pipe;
10218         }
10219
10220         for_each_intel_encoder(dev, encoder) {
10221                 if (encoder->base.crtc == &encoder->new_crtc->base)
10222                         continue;
10223
10224                 if (encoder->base.crtc) {
10225                         tmp_crtc = encoder->base.crtc;
10226
10227                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10228                 }
10229
10230                 if (encoder->new_crtc)
10231                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10232         }
10233
10234         /* Check for pipes that will be enabled/disabled ... */
10235         for_each_intel_crtc(dev, intel_crtc) {
10236                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10237                         continue;
10238
10239                 if (!intel_crtc->new_enabled)
10240                         *disable_pipes |= 1 << intel_crtc->pipe;
10241                 else
10242                         *prepare_pipes |= 1 << intel_crtc->pipe;
10243         }
10244
10245
10246         /* set_mode is also used to update properties on life display pipes. */
10247         intel_crtc = to_intel_crtc(crtc);
10248         if (intel_crtc->new_enabled)
10249                 *prepare_pipes |= 1 << intel_crtc->pipe;
10250
10251         /*
10252          * For simplicity do a full modeset on any pipe where the output routing
10253          * changed. We could be more clever, but that would require us to be
10254          * more careful with calling the relevant encoder->mode_set functions.
10255          */
10256         if (*prepare_pipes)
10257                 *modeset_pipes = *prepare_pipes;
10258
10259         /* ... and mask these out. */
10260         *modeset_pipes &= ~(*disable_pipes);
10261         *prepare_pipes &= ~(*disable_pipes);
10262
10263         /*
10264          * HACK: We don't (yet) fully support global modesets. intel_set_config
10265          * obies this rule, but the modeset restore mode of
10266          * intel_modeset_setup_hw_state does not.
10267          */
10268         *modeset_pipes &= 1 << intel_crtc->pipe;
10269         *prepare_pipes &= 1 << intel_crtc->pipe;
10270
10271         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10272                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10273 }
10274
10275 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10276 {
10277         struct drm_encoder *encoder;
10278         struct drm_device *dev = crtc->dev;
10279
10280         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10281                 if (encoder->crtc == crtc)
10282                         return true;
10283
10284         return false;
10285 }
10286
10287 static void
10288 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10289 {
10290         struct drm_i915_private *dev_priv = dev->dev_private;
10291         struct intel_encoder *intel_encoder;
10292         struct intel_crtc *intel_crtc;
10293         struct drm_connector *connector;
10294
10295         intel_shared_dpll_commit(dev_priv);
10296
10297         for_each_intel_encoder(dev, intel_encoder) {
10298                 if (!intel_encoder->base.crtc)
10299                         continue;
10300
10301                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10302
10303                 if (prepare_pipes & (1 << intel_crtc->pipe))
10304                         intel_encoder->connectors_active = false;
10305         }
10306
10307         intel_modeset_commit_output_state(dev);
10308
10309         /* Double check state. */
10310         for_each_intel_crtc(dev, intel_crtc) {
10311                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10312                 WARN_ON(intel_crtc->new_config &&
10313                         intel_crtc->new_config != &intel_crtc->config);
10314                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10315         }
10316
10317         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10318                 if (!connector->encoder || !connector->encoder->crtc)
10319                         continue;
10320
10321                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10322
10323                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10324                         struct drm_property *dpms_property =
10325                                 dev->mode_config.dpms_property;
10326
10327                         connector->dpms = DRM_MODE_DPMS_ON;
10328                         drm_object_property_set_value(&connector->base,
10329                                                          dpms_property,
10330                                                          DRM_MODE_DPMS_ON);
10331
10332                         intel_encoder = to_intel_encoder(connector->encoder);
10333                         intel_encoder->connectors_active = true;
10334                 }
10335         }
10336
10337 }
10338
10339 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10340 {
10341         int diff;
10342
10343         if (clock1 == clock2)
10344                 return true;
10345
10346         if (!clock1 || !clock2)
10347                 return false;
10348
10349         diff = abs(clock1 - clock2);
10350
10351         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10352                 return true;
10353
10354         return false;
10355 }
10356
10357 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10358         list_for_each_entry((intel_crtc), \
10359                             &(dev)->mode_config.crtc_list, \
10360                             base.head) \
10361                 if (mask & (1 <<(intel_crtc)->pipe))
10362
10363 static bool
10364 intel_pipe_config_compare(struct drm_device *dev,
10365                           struct intel_crtc_config *current_config,
10366                           struct intel_crtc_config *pipe_config)
10367 {
10368 #define PIPE_CONF_CHECK_X(name) \
10369         if (current_config->name != pipe_config->name) { \
10370                 DRM_ERROR("mismatch in " #name " " \
10371                           "(expected 0x%08x, found 0x%08x)\n", \
10372                           current_config->name, \
10373                           pipe_config->name); \
10374                 return false; \
10375         }
10376
10377 #define PIPE_CONF_CHECK_I(name) \
10378         if (current_config->name != pipe_config->name) { \
10379                 DRM_ERROR("mismatch in " #name " " \
10380                           "(expected %i, found %i)\n", \
10381                           current_config->name, \
10382                           pipe_config->name); \
10383                 return false; \
10384         }
10385
10386 /* This is required for BDW+ where there is only one set of registers for
10387  * switching between high and low RR.
10388  * This macro can be used whenever a comparison has to be made between one
10389  * hw state and multiple sw state variables.
10390  */
10391 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10392         if ((current_config->name != pipe_config->name) && \
10393                 (current_config->alt_name != pipe_config->name)) { \
10394                         DRM_ERROR("mismatch in " #name " " \
10395                                   "(expected %i or %i, found %i)\n", \
10396                                   current_config->name, \
10397                                   current_config->alt_name, \
10398                                   pipe_config->name); \
10399                         return false; \
10400         }
10401
10402 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10403         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10404                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10405                           "(expected %i, found %i)\n", \
10406                           current_config->name & (mask), \
10407                           pipe_config->name & (mask)); \
10408                 return false; \
10409         }
10410
10411 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10412         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10413                 DRM_ERROR("mismatch in " #name " " \
10414                           "(expected %i, found %i)\n", \
10415                           current_config->name, \
10416                           pipe_config->name); \
10417                 return false; \
10418         }
10419
10420 #define PIPE_CONF_QUIRK(quirk)  \
10421         ((current_config->quirks | pipe_config->quirks) & (quirk))
10422
10423         PIPE_CONF_CHECK_I(cpu_transcoder);
10424
10425         PIPE_CONF_CHECK_I(has_pch_encoder);
10426         PIPE_CONF_CHECK_I(fdi_lanes);
10427         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10428         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10429         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10430         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10431         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10432
10433         PIPE_CONF_CHECK_I(has_dp_encoder);
10434
10435         if (INTEL_INFO(dev)->gen < 8) {
10436                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10437                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10438                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10439                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10440                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10441
10442                 if (current_config->has_drrs) {
10443                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10444                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10445                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10446                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10447                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10448                 }
10449         } else {
10450                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10451                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10452                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10453                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10454                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10455         }
10456
10457         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10458         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10459         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10460         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10461         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10462         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10463
10464         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10465         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10466         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10467         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10468         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10469         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10470
10471         PIPE_CONF_CHECK_I(pixel_multiplier);
10472         PIPE_CONF_CHECK_I(has_hdmi_sink);
10473         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10474             IS_VALLEYVIEW(dev))
10475                 PIPE_CONF_CHECK_I(limited_color_range);
10476         PIPE_CONF_CHECK_I(has_infoframe);
10477
10478         PIPE_CONF_CHECK_I(has_audio);
10479
10480         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10481                               DRM_MODE_FLAG_INTERLACE);
10482
10483         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10484                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10485                                       DRM_MODE_FLAG_PHSYNC);
10486                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10487                                       DRM_MODE_FLAG_NHSYNC);
10488                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10489                                       DRM_MODE_FLAG_PVSYNC);
10490                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10491                                       DRM_MODE_FLAG_NVSYNC);
10492         }
10493
10494         PIPE_CONF_CHECK_I(pipe_src_w);
10495         PIPE_CONF_CHECK_I(pipe_src_h);
10496
10497         /*
10498          * FIXME: BIOS likes to set up a cloned config with lvds+external
10499          * screen. Since we don't yet re-compute the pipe config when moving
10500          * just the lvds port away to another pipe the sw tracking won't match.
10501          *
10502          * Proper atomic modesets with recomputed global state will fix this.
10503          * Until then just don't check gmch state for inherited modes.
10504          */
10505         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10506                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10507                 /* pfit ratios are autocomputed by the hw on gen4+ */
10508                 if (INTEL_INFO(dev)->gen < 4)
10509                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10510                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10511         }
10512
10513         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10514         if (current_config->pch_pfit.enabled) {
10515                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10516                 PIPE_CONF_CHECK_I(pch_pfit.size);
10517         }
10518
10519         /* BDW+ don't expose a synchronous way to read the state */
10520         if (IS_HASWELL(dev))
10521                 PIPE_CONF_CHECK_I(ips_enabled);
10522
10523         PIPE_CONF_CHECK_I(double_wide);
10524
10525         PIPE_CONF_CHECK_X(ddi_pll_sel);
10526
10527         PIPE_CONF_CHECK_I(shared_dpll);
10528         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10529         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10530         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10531         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10532         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10533         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10534         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10535         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10536
10537         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10538                 PIPE_CONF_CHECK_I(pipe_bpp);
10539
10540         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10541         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10542
10543 #undef PIPE_CONF_CHECK_X
10544 #undef PIPE_CONF_CHECK_I
10545 #undef PIPE_CONF_CHECK_I_ALT
10546 #undef PIPE_CONF_CHECK_FLAGS
10547 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10548 #undef PIPE_CONF_QUIRK
10549
10550         return true;
10551 }
10552
10553 static void check_wm_state(struct drm_device *dev)
10554 {
10555         struct drm_i915_private *dev_priv = dev->dev_private;
10556         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10557         struct intel_crtc *intel_crtc;
10558         int plane;
10559
10560         if (INTEL_INFO(dev)->gen < 9)
10561                 return;
10562
10563         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10564         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10565
10566         for_each_intel_crtc(dev, intel_crtc) {
10567                 struct skl_ddb_entry *hw_entry, *sw_entry;
10568                 const enum pipe pipe = intel_crtc->pipe;
10569
10570                 if (!intel_crtc->active)
10571                         continue;
10572
10573                 /* planes */
10574                 for_each_plane(pipe, plane) {
10575                         hw_entry = &hw_ddb.plane[pipe][plane];
10576                         sw_entry = &sw_ddb->plane[pipe][plane];
10577
10578                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10579                                 continue;
10580
10581                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10582                                   "(expected (%u,%u), found (%u,%u))\n",
10583                                   pipe_name(pipe), plane + 1,
10584                                   sw_entry->start, sw_entry->end,
10585                                   hw_entry->start, hw_entry->end);
10586                 }
10587
10588                 /* cursor */
10589                 hw_entry = &hw_ddb.cursor[pipe];
10590                 sw_entry = &sw_ddb->cursor[pipe];
10591
10592                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10593                         continue;
10594
10595                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10596                           "(expected (%u,%u), found (%u,%u))\n",
10597                           pipe_name(pipe),
10598                           sw_entry->start, sw_entry->end,
10599                           hw_entry->start, hw_entry->end);
10600         }
10601 }
10602
10603 static void
10604 check_connector_state(struct drm_device *dev)
10605 {
10606         struct intel_connector *connector;
10607
10608         list_for_each_entry(connector, &dev->mode_config.connector_list,
10609                             base.head) {
10610                 /* This also checks the encoder/connector hw state with the
10611                  * ->get_hw_state callbacks. */
10612                 intel_connector_check_state(connector);
10613
10614                 WARN(&connector->new_encoder->base != connector->base.encoder,
10615                      "connector's staged encoder doesn't match current encoder\n");
10616         }
10617 }
10618
10619 static void
10620 check_encoder_state(struct drm_device *dev)
10621 {
10622         struct intel_encoder *encoder;
10623         struct intel_connector *connector;
10624
10625         for_each_intel_encoder(dev, encoder) {
10626                 bool enabled = false;
10627                 bool active = false;
10628                 enum pipe pipe, tracked_pipe;
10629
10630                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10631                               encoder->base.base.id,
10632                               encoder->base.name);
10633
10634                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10635                      "encoder's stage crtc doesn't match current crtc\n");
10636                 WARN(encoder->connectors_active && !encoder->base.crtc,
10637                      "encoder's active_connectors set, but no crtc\n");
10638
10639                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10640                                     base.head) {
10641                         if (connector->base.encoder != &encoder->base)
10642                                 continue;
10643                         enabled = true;
10644                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10645                                 active = true;
10646                 }
10647                 /*
10648                  * for MST connectors if we unplug the connector is gone
10649                  * away but the encoder is still connected to a crtc
10650                  * until a modeset happens in response to the hotplug.
10651                  */
10652                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10653                         continue;
10654
10655                 WARN(!!encoder->base.crtc != enabled,
10656                      "encoder's enabled state mismatch "
10657                      "(expected %i, found %i)\n",
10658                      !!encoder->base.crtc, enabled);
10659                 WARN(active && !encoder->base.crtc,
10660                      "active encoder with no crtc\n");
10661
10662                 WARN(encoder->connectors_active != active,
10663                      "encoder's computed active state doesn't match tracked active state "
10664                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10665
10666                 active = encoder->get_hw_state(encoder, &pipe);
10667                 WARN(active != encoder->connectors_active,
10668                      "encoder's hw state doesn't match sw tracking "
10669                      "(expected %i, found %i)\n",
10670                      encoder->connectors_active, active);
10671
10672                 if (!encoder->base.crtc)
10673                         continue;
10674
10675                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10676                 WARN(active && pipe != tracked_pipe,
10677                      "active encoder's pipe doesn't match"
10678                      "(expected %i, found %i)\n",
10679                      tracked_pipe, pipe);
10680
10681         }
10682 }
10683
10684 static void
10685 check_crtc_state(struct drm_device *dev)
10686 {
10687         struct drm_i915_private *dev_priv = dev->dev_private;
10688         struct intel_crtc *crtc;
10689         struct intel_encoder *encoder;
10690         struct intel_crtc_config pipe_config;
10691
10692         for_each_intel_crtc(dev, crtc) {
10693                 bool enabled = false;
10694                 bool active = false;
10695
10696                 memset(&pipe_config, 0, sizeof(pipe_config));
10697
10698                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10699                               crtc->base.base.id);
10700
10701                 WARN(crtc->active && !crtc->base.enabled,
10702                      "active crtc, but not enabled in sw tracking\n");
10703
10704                 for_each_intel_encoder(dev, encoder) {
10705                         if (encoder->base.crtc != &crtc->base)
10706                                 continue;
10707                         enabled = true;
10708                         if (encoder->connectors_active)
10709                                 active = true;
10710                 }
10711
10712                 WARN(active != crtc->active,
10713                      "crtc's computed active state doesn't match tracked active state "
10714                      "(expected %i, found %i)\n", active, crtc->active);
10715                 WARN(enabled != crtc->base.enabled,
10716                      "crtc's computed enabled state doesn't match tracked enabled state "
10717                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10718
10719                 active = dev_priv->display.get_pipe_config(crtc,
10720                                                            &pipe_config);
10721
10722                 /* hw state is inconsistent with the pipe quirk */
10723                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10724                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10725                         active = crtc->active;
10726
10727                 for_each_intel_encoder(dev, encoder) {
10728                         enum pipe pipe;
10729                         if (encoder->base.crtc != &crtc->base)
10730                                 continue;
10731                         if (encoder->get_hw_state(encoder, &pipe))
10732                                 encoder->get_config(encoder, &pipe_config);
10733                 }
10734
10735                 WARN(crtc->active != active,
10736                      "crtc active state doesn't match with hw state "
10737                      "(expected %i, found %i)\n", crtc->active, active);
10738
10739                 if (active &&
10740                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10741                         WARN(1, "pipe state doesn't match!\n");
10742                         intel_dump_pipe_config(crtc, &pipe_config,
10743                                                "[hw state]");
10744                         intel_dump_pipe_config(crtc, &crtc->config,
10745                                                "[sw state]");
10746                 }
10747         }
10748 }
10749
10750 static void
10751 check_shared_dpll_state(struct drm_device *dev)
10752 {
10753         struct drm_i915_private *dev_priv = dev->dev_private;
10754         struct intel_crtc *crtc;
10755         struct intel_dpll_hw_state dpll_hw_state;
10756         int i;
10757
10758         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10759                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10760                 int enabled_crtcs = 0, active_crtcs = 0;
10761                 bool active;
10762
10763                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10764
10765                 DRM_DEBUG_KMS("%s\n", pll->name);
10766
10767                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10768
10769                 WARN(pll->active > hweight32(pll->config.crtc_mask),
10770                      "more active pll users than references: %i vs %i\n",
10771                      pll->active, hweight32(pll->config.crtc_mask));
10772                 WARN(pll->active && !pll->on,
10773                      "pll in active use but not on in sw tracking\n");
10774                 WARN(pll->on && !pll->active,
10775                      "pll in on but not on in use in sw tracking\n");
10776                 WARN(pll->on != active,
10777                      "pll on state mismatch (expected %i, found %i)\n",
10778                      pll->on, active);
10779
10780                 for_each_intel_crtc(dev, crtc) {
10781                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10782                                 enabled_crtcs++;
10783                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10784                                 active_crtcs++;
10785                 }
10786                 WARN(pll->active != active_crtcs,
10787                      "pll active crtcs mismatch (expected %i, found %i)\n",
10788                      pll->active, active_crtcs);
10789                 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10790                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10791                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10792
10793                 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10794                                        sizeof(dpll_hw_state)),
10795                      "pll hw state mismatch\n");
10796         }
10797 }
10798
10799 void
10800 intel_modeset_check_state(struct drm_device *dev)
10801 {
10802         check_wm_state(dev);
10803         check_connector_state(dev);
10804         check_encoder_state(dev);
10805         check_crtc_state(dev);
10806         check_shared_dpll_state(dev);
10807 }
10808
10809 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10810                                      int dotclock)
10811 {
10812         /*
10813          * FDI already provided one idea for the dotclock.
10814          * Yell if the encoder disagrees.
10815          */
10816         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10817              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10818              pipe_config->adjusted_mode.crtc_clock, dotclock);
10819 }
10820
10821 static void update_scanline_offset(struct intel_crtc *crtc)
10822 {
10823         struct drm_device *dev = crtc->base.dev;
10824
10825         /*
10826          * The scanline counter increments at the leading edge of hsync.
10827          *
10828          * On most platforms it starts counting from vtotal-1 on the
10829          * first active line. That means the scanline counter value is
10830          * always one less than what we would expect. Ie. just after
10831          * start of vblank, which also occurs at start of hsync (on the
10832          * last active line), the scanline counter will read vblank_start-1.
10833          *
10834          * On gen2 the scanline counter starts counting from 1 instead
10835          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10836          * to keep the value positive), instead of adding one.
10837          *
10838          * On HSW+ the behaviour of the scanline counter depends on the output
10839          * type. For DP ports it behaves like most other platforms, but on HDMI
10840          * there's an extra 1 line difference. So we need to add two instead of
10841          * one to the value.
10842          */
10843         if (IS_GEN2(dev)) {
10844                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10845                 int vtotal;
10846
10847                 vtotal = mode->crtc_vtotal;
10848                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10849                         vtotal /= 2;
10850
10851                 crtc->scanline_offset = vtotal - 1;
10852         } else if (HAS_DDI(dev) &&
10853                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10854                 crtc->scanline_offset = 2;
10855         } else
10856                 crtc->scanline_offset = 1;
10857 }
10858
10859 static struct intel_crtc_config *
10860 intel_modeset_compute_config(struct drm_crtc *crtc,
10861                              struct drm_display_mode *mode,
10862                              struct drm_framebuffer *fb,
10863                              unsigned *modeset_pipes,
10864                              unsigned *prepare_pipes,
10865                              unsigned *disable_pipes)
10866 {
10867         struct intel_crtc_config *pipe_config = NULL;
10868
10869         intel_modeset_affected_pipes(crtc, modeset_pipes,
10870                                      prepare_pipes, disable_pipes);
10871
10872         if ((*modeset_pipes) == 0)
10873                 goto out;
10874
10875         /*
10876          * Note this needs changes when we start tracking multiple modes
10877          * and crtcs.  At that point we'll need to compute the whole config
10878          * (i.e. one pipe_config for each crtc) rather than just the one
10879          * for this crtc.
10880          */
10881         pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10882         if (IS_ERR(pipe_config)) {
10883                 goto out;
10884         }
10885         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10886                                "[modeset]");
10887         to_intel_crtc(crtc)->new_config = pipe_config;
10888
10889 out:
10890         return pipe_config;
10891 }
10892
10893 static int __intel_set_mode(struct drm_crtc *crtc,
10894                             struct drm_display_mode *mode,
10895                             int x, int y, struct drm_framebuffer *fb,
10896                             struct intel_crtc_config *pipe_config,
10897                             unsigned modeset_pipes,
10898                             unsigned prepare_pipes,
10899                             unsigned disable_pipes)
10900 {
10901         struct drm_device *dev = crtc->dev;
10902         struct drm_i915_private *dev_priv = dev->dev_private;
10903         struct drm_display_mode *saved_mode;
10904         struct intel_crtc *intel_crtc;
10905         int ret = 0;
10906
10907         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10908         if (!saved_mode)
10909                 return -ENOMEM;
10910
10911         *saved_mode = crtc->mode;
10912
10913         /*
10914          * See if the config requires any additional preparation, e.g.
10915          * to adjust global state with pipes off.  We need to do this
10916          * here so we can get the modeset_pipe updated config for the new
10917          * mode set on this crtc.  For other crtcs we need to use the
10918          * adjusted_mode bits in the crtc directly.
10919          */
10920         if (IS_VALLEYVIEW(dev)) {
10921                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10922
10923                 /* may have added more to prepare_pipes than we should */
10924                 prepare_pipes &= ~disable_pipes;
10925         }
10926
10927         if (dev_priv->display.crtc_compute_clock) {
10928                 unsigned clear_pipes = modeset_pipes | disable_pipes;
10929
10930                 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10931                 if (ret)
10932                         goto done;
10933
10934                 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10935                         ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10936                         if (ret) {
10937                                 intel_shared_dpll_abort_config(dev_priv);
10938                                 goto done;
10939                         }
10940                 }
10941         }
10942
10943         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10944                 intel_crtc_disable(&intel_crtc->base);
10945
10946         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10947                 if (intel_crtc->base.enabled)
10948                         dev_priv->display.crtc_disable(&intel_crtc->base);
10949         }
10950
10951         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10952          * to set it here already despite that we pass it down the callchain.
10953          *
10954          * Note we'll need to fix this up when we start tracking multiple
10955          * pipes; here we assume a single modeset_pipe and only track the
10956          * single crtc and mode.
10957          */
10958         if (modeset_pipes) {
10959                 crtc->mode = *mode;
10960                 /* mode_set/enable/disable functions rely on a correct pipe
10961                  * config. */
10962                 to_intel_crtc(crtc)->config = *pipe_config;
10963                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10964
10965                 /*
10966                  * Calculate and store various constants which
10967                  * are later needed by vblank and swap-completion
10968                  * timestamping. They are derived from true hwmode.
10969                  */
10970                 drm_calc_timestamping_constants(crtc,
10971                                                 &pipe_config->adjusted_mode);
10972         }
10973
10974         /* Only after disabling all output pipelines that will be changed can we
10975          * update the the output configuration. */
10976         intel_modeset_update_state(dev, prepare_pipes);
10977
10978         modeset_update_crtc_power_domains(dev);
10979
10980         /* Set up the DPLL and any encoders state that needs to adjust or depend
10981          * on the DPLL.
10982          */
10983         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10984                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10985                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10986                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10987
10988                 mutex_lock(&dev->struct_mutex);
10989                 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
10990                 if (ret != 0) {
10991                         DRM_ERROR("pin & fence failed\n");
10992                         mutex_unlock(&dev->struct_mutex);
10993                         goto done;
10994                 }
10995                 if (old_fb)
10996                         intel_unpin_fb_obj(old_obj);
10997                 i915_gem_track_fb(old_obj, obj,
10998                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10999                 mutex_unlock(&dev->struct_mutex);
11000
11001                 crtc->primary->fb = fb;
11002                 crtc->x = x;
11003                 crtc->y = y;
11004         }
11005
11006         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11007         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11008                 update_scanline_offset(intel_crtc);
11009
11010                 dev_priv->display.crtc_enable(&intel_crtc->base);
11011         }
11012
11013         /* FIXME: add subpixel order */
11014 done:
11015         if (ret && crtc->enabled)
11016                 crtc->mode = *saved_mode;
11017
11018         kfree(pipe_config);
11019         kfree(saved_mode);
11020         return ret;
11021 }
11022
11023 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11024                                 struct drm_display_mode *mode,
11025                                 int x, int y, struct drm_framebuffer *fb,
11026                                 struct intel_crtc_config *pipe_config,
11027                                 unsigned modeset_pipes,
11028                                 unsigned prepare_pipes,
11029                                 unsigned disable_pipes)
11030 {
11031         int ret;
11032
11033         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11034                                prepare_pipes, disable_pipes);
11035
11036         if (ret == 0)
11037                 intel_modeset_check_state(crtc->dev);
11038
11039         return ret;
11040 }
11041
11042 static int intel_set_mode(struct drm_crtc *crtc,
11043                           struct drm_display_mode *mode,
11044                           int x, int y, struct drm_framebuffer *fb)
11045 {
11046         struct intel_crtc_config *pipe_config;
11047         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11048
11049         pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11050                                                    &modeset_pipes,
11051                                                    &prepare_pipes,
11052                                                    &disable_pipes);
11053
11054         if (IS_ERR(pipe_config))
11055                 return PTR_ERR(pipe_config);
11056
11057         return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11058                                     modeset_pipes, prepare_pipes,
11059                                     disable_pipes);
11060 }
11061
11062 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11063 {
11064         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11065 }
11066
11067 #undef for_each_intel_crtc_masked
11068
11069 static void intel_set_config_free(struct intel_set_config *config)
11070 {
11071         if (!config)
11072                 return;
11073
11074         kfree(config->save_connector_encoders);
11075         kfree(config->save_encoder_crtcs);
11076         kfree(config->save_crtc_enabled);
11077         kfree(config);
11078 }
11079
11080 static int intel_set_config_save_state(struct drm_device *dev,
11081                                        struct intel_set_config *config)
11082 {
11083         struct drm_crtc *crtc;
11084         struct drm_encoder *encoder;
11085         struct drm_connector *connector;
11086         int count;
11087
11088         config->save_crtc_enabled =
11089                 kcalloc(dev->mode_config.num_crtc,
11090                         sizeof(bool), GFP_KERNEL);
11091         if (!config->save_crtc_enabled)
11092                 return -ENOMEM;
11093
11094         config->save_encoder_crtcs =
11095                 kcalloc(dev->mode_config.num_encoder,
11096                         sizeof(struct drm_crtc *), GFP_KERNEL);
11097         if (!config->save_encoder_crtcs)
11098                 return -ENOMEM;
11099
11100         config->save_connector_encoders =
11101                 kcalloc(dev->mode_config.num_connector,
11102                         sizeof(struct drm_encoder *), GFP_KERNEL);
11103         if (!config->save_connector_encoders)
11104                 return -ENOMEM;
11105
11106         /* Copy data. Note that driver private data is not affected.
11107          * Should anything bad happen only the expected state is
11108          * restored, not the drivers personal bookkeeping.
11109          */
11110         count = 0;
11111         for_each_crtc(dev, crtc) {
11112                 config->save_crtc_enabled[count++] = crtc->enabled;
11113         }
11114
11115         count = 0;
11116         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11117                 config->save_encoder_crtcs[count++] = encoder->crtc;
11118         }
11119
11120         count = 0;
11121         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11122                 config->save_connector_encoders[count++] = connector->encoder;
11123         }
11124
11125         return 0;
11126 }
11127
11128 static void intel_set_config_restore_state(struct drm_device *dev,
11129                                            struct intel_set_config *config)
11130 {
11131         struct intel_crtc *crtc;
11132         struct intel_encoder *encoder;
11133         struct intel_connector *connector;
11134         int count;
11135
11136         count = 0;
11137         for_each_intel_crtc(dev, crtc) {
11138                 crtc->new_enabled = config->save_crtc_enabled[count++];
11139
11140                 if (crtc->new_enabled)
11141                         crtc->new_config = &crtc->config;
11142                 else
11143                         crtc->new_config = NULL;
11144         }
11145
11146         count = 0;
11147         for_each_intel_encoder(dev, encoder) {
11148                 encoder->new_crtc =
11149                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11150         }
11151
11152         count = 0;
11153         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11154                 connector->new_encoder =
11155                         to_intel_encoder(config->save_connector_encoders[count++]);
11156         }
11157 }
11158
11159 static bool
11160 is_crtc_connector_off(struct drm_mode_set *set)
11161 {
11162         int i;
11163
11164         if (set->num_connectors == 0)
11165                 return false;
11166
11167         if (WARN_ON(set->connectors == NULL))
11168                 return false;
11169
11170         for (i = 0; i < set->num_connectors; i++)
11171                 if (set->connectors[i]->encoder &&
11172                     set->connectors[i]->encoder->crtc == set->crtc &&
11173                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11174                         return true;
11175
11176         return false;
11177 }
11178
11179 static void
11180 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11181                                       struct intel_set_config *config)
11182 {
11183
11184         /* We should be able to check here if the fb has the same properties
11185          * and then just flip_or_move it */
11186         if (is_crtc_connector_off(set)) {
11187                 config->mode_changed = true;
11188         } else if (set->crtc->primary->fb != set->fb) {
11189                 /*
11190                  * If we have no fb, we can only flip as long as the crtc is
11191                  * active, otherwise we need a full mode set.  The crtc may
11192                  * be active if we've only disabled the primary plane, or
11193                  * in fastboot situations.
11194                  */
11195                 if (set->crtc->primary->fb == NULL) {
11196                         struct intel_crtc *intel_crtc =
11197                                 to_intel_crtc(set->crtc);
11198
11199                         if (intel_crtc->active) {
11200                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11201                                 config->fb_changed = true;
11202                         } else {
11203                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11204                                 config->mode_changed = true;
11205                         }
11206                 } else if (set->fb == NULL) {
11207                         config->mode_changed = true;
11208                 } else if (set->fb->pixel_format !=
11209                            set->crtc->primary->fb->pixel_format) {
11210                         config->mode_changed = true;
11211                 } else {
11212                         config->fb_changed = true;
11213                 }
11214         }
11215
11216         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11217                 config->fb_changed = true;
11218
11219         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11220                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11221                 drm_mode_debug_printmodeline(&set->crtc->mode);
11222                 drm_mode_debug_printmodeline(set->mode);
11223                 config->mode_changed = true;
11224         }
11225
11226         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11227                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11228 }
11229
11230 static int
11231 intel_modeset_stage_output_state(struct drm_device *dev,
11232                                  struct drm_mode_set *set,
11233                                  struct intel_set_config *config)
11234 {
11235         struct intel_connector *connector;
11236         struct intel_encoder *encoder;
11237         struct intel_crtc *crtc;
11238         int ro;
11239
11240         /* The upper layers ensure that we either disable a crtc or have a list
11241          * of connectors. For paranoia, double-check this. */
11242         WARN_ON(!set->fb && (set->num_connectors != 0));
11243         WARN_ON(set->fb && (set->num_connectors == 0));
11244
11245         list_for_each_entry(connector, &dev->mode_config.connector_list,
11246                             base.head) {
11247                 /* Otherwise traverse passed in connector list and get encoders
11248                  * for them. */
11249                 for (ro = 0; ro < set->num_connectors; ro++) {
11250                         if (set->connectors[ro] == &connector->base) {
11251                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11252                                 break;
11253                         }
11254                 }
11255
11256                 /* If we disable the crtc, disable all its connectors. Also, if
11257                  * the connector is on the changing crtc but not on the new
11258                  * connector list, disable it. */
11259                 if ((!set->fb || ro == set->num_connectors) &&
11260                     connector->base.encoder &&
11261                     connector->base.encoder->crtc == set->crtc) {
11262                         connector->new_encoder = NULL;
11263
11264                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11265                                 connector->base.base.id,
11266                                 connector->base.name);
11267                 }
11268
11269
11270                 if (&connector->new_encoder->base != connector->base.encoder) {
11271                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11272                         config->mode_changed = true;
11273                 }
11274         }
11275         /* connector->new_encoder is now updated for all connectors. */
11276
11277         /* Update crtc of enabled connectors. */
11278         list_for_each_entry(connector, &dev->mode_config.connector_list,
11279                             base.head) {
11280                 struct drm_crtc *new_crtc;
11281
11282                 if (!connector->new_encoder)
11283                         continue;
11284
11285                 new_crtc = connector->new_encoder->base.crtc;
11286
11287                 for (ro = 0; ro < set->num_connectors; ro++) {
11288                         if (set->connectors[ro] == &connector->base)
11289                                 new_crtc = set->crtc;
11290                 }
11291
11292                 /* Make sure the new CRTC will work with the encoder */
11293                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11294                                          new_crtc)) {
11295                         return -EINVAL;
11296                 }
11297                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11298
11299                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11300                         connector->base.base.id,
11301                         connector->base.name,
11302                         new_crtc->base.id);
11303         }
11304
11305         /* Check for any encoders that needs to be disabled. */
11306         for_each_intel_encoder(dev, encoder) {
11307                 int num_connectors = 0;
11308                 list_for_each_entry(connector,
11309                                     &dev->mode_config.connector_list,
11310                                     base.head) {
11311                         if (connector->new_encoder == encoder) {
11312                                 WARN_ON(!connector->new_encoder->new_crtc);
11313                                 num_connectors++;
11314                         }
11315                 }
11316
11317                 if (num_connectors == 0)
11318                         encoder->new_crtc = NULL;
11319                 else if (num_connectors > 1)
11320                         return -EINVAL;
11321
11322                 /* Only now check for crtc changes so we don't miss encoders
11323                  * that will be disabled. */
11324                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11325                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11326                         config->mode_changed = true;
11327                 }
11328         }
11329         /* Now we've also updated encoder->new_crtc for all encoders. */
11330         list_for_each_entry(connector, &dev->mode_config.connector_list,
11331                             base.head) {
11332                 if (connector->new_encoder)
11333                         if (connector->new_encoder != connector->encoder)
11334                                 connector->encoder = connector->new_encoder;
11335         }
11336         for_each_intel_crtc(dev, crtc) {
11337                 crtc->new_enabled = false;
11338
11339                 for_each_intel_encoder(dev, encoder) {
11340                         if (encoder->new_crtc == crtc) {
11341                                 crtc->new_enabled = true;
11342                                 break;
11343                         }
11344                 }
11345
11346                 if (crtc->new_enabled != crtc->base.enabled) {
11347                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11348                                       crtc->new_enabled ? "en" : "dis");
11349                         config->mode_changed = true;
11350                 }
11351
11352                 if (crtc->new_enabled)
11353                         crtc->new_config = &crtc->config;
11354                 else
11355                         crtc->new_config = NULL;
11356         }
11357
11358         return 0;
11359 }
11360
11361 static void disable_crtc_nofb(struct intel_crtc *crtc)
11362 {
11363         struct drm_device *dev = crtc->base.dev;
11364         struct intel_encoder *encoder;
11365         struct intel_connector *connector;
11366
11367         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11368                       pipe_name(crtc->pipe));
11369
11370         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11371                 if (connector->new_encoder &&
11372                     connector->new_encoder->new_crtc == crtc)
11373                         connector->new_encoder = NULL;
11374         }
11375
11376         for_each_intel_encoder(dev, encoder) {
11377                 if (encoder->new_crtc == crtc)
11378                         encoder->new_crtc = NULL;
11379         }
11380
11381         crtc->new_enabled = false;
11382         crtc->new_config = NULL;
11383 }
11384
11385 static int intel_crtc_set_config(struct drm_mode_set *set)
11386 {
11387         struct drm_device *dev;
11388         struct drm_mode_set save_set;
11389         struct intel_set_config *config;
11390         struct intel_crtc_config *pipe_config;
11391         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11392         int ret;
11393
11394         BUG_ON(!set);
11395         BUG_ON(!set->crtc);
11396         BUG_ON(!set->crtc->helper_private);
11397
11398         /* Enforce sane interface api - has been abused by the fb helper. */
11399         BUG_ON(!set->mode && set->fb);
11400         BUG_ON(set->fb && set->num_connectors == 0);
11401
11402         if (set->fb) {
11403                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11404                                 set->crtc->base.id, set->fb->base.id,
11405                                 (int)set->num_connectors, set->x, set->y);
11406         } else {
11407                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11408         }
11409
11410         dev = set->crtc->dev;
11411
11412         ret = -ENOMEM;
11413         config = kzalloc(sizeof(*config), GFP_KERNEL);
11414         if (!config)
11415                 goto out_config;
11416
11417         ret = intel_set_config_save_state(dev, config);
11418         if (ret)
11419                 goto out_config;
11420
11421         save_set.crtc = set->crtc;
11422         save_set.mode = &set->crtc->mode;
11423         save_set.x = set->crtc->x;
11424         save_set.y = set->crtc->y;
11425         save_set.fb = set->crtc->primary->fb;
11426
11427         /* Compute whether we need a full modeset, only an fb base update or no
11428          * change at all. In the future we might also check whether only the
11429          * mode changed, e.g. for LVDS where we only change the panel fitter in
11430          * such cases. */
11431         intel_set_config_compute_mode_changes(set, config);
11432
11433         ret = intel_modeset_stage_output_state(dev, set, config);
11434         if (ret)
11435                 goto fail;
11436
11437         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11438                                                    set->fb,
11439                                                    &modeset_pipes,
11440                                                    &prepare_pipes,
11441                                                    &disable_pipes);
11442         if (IS_ERR(pipe_config)) {
11443                 ret = PTR_ERR(pipe_config);
11444                 goto fail;
11445         } else if (pipe_config) {
11446                 if (to_intel_crtc(set->crtc)->new_config->has_audio !=
11447                     to_intel_crtc(set->crtc)->config.has_audio)
11448                         config->mode_changed = true;
11449
11450                 /* Force mode sets for any infoframe stuff */
11451                 if (to_intel_crtc(set->crtc)->new_config->has_infoframe ||
11452                     to_intel_crtc(set->crtc)->config.has_infoframe)
11453                         config->mode_changed = true;
11454         }
11455
11456         /* set_mode will free it in the mode_changed case */
11457         if (!config->mode_changed)
11458                 kfree(pipe_config);
11459
11460         intel_update_pipe_size(to_intel_crtc(set->crtc));
11461
11462         if (config->mode_changed) {
11463                 ret = intel_set_mode_pipes(set->crtc, set->mode,
11464                                            set->x, set->y, set->fb, pipe_config,
11465                                            modeset_pipes, prepare_pipes,
11466                                            disable_pipes);
11467         } else if (config->fb_changed) {
11468                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11469
11470                 intel_crtc_wait_for_pending_flips(set->crtc);
11471
11472                 ret = intel_pipe_set_base(set->crtc,
11473                                           set->x, set->y, set->fb);
11474
11475                 /*
11476                  * We need to make sure the primary plane is re-enabled if it
11477                  * has previously been turned off.
11478                  */
11479                 if (!intel_crtc->primary_enabled && ret == 0) {
11480                         WARN_ON(!intel_crtc->active);
11481                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11482                 }
11483
11484                 /*
11485                  * In the fastboot case this may be our only check of the
11486                  * state after boot.  It would be better to only do it on
11487                  * the first update, but we don't have a nice way of doing that
11488                  * (and really, set_config isn't used much for high freq page
11489                  * flipping, so increasing its cost here shouldn't be a big
11490                  * deal).
11491                  */
11492                 if (i915.fastboot && ret == 0)
11493                         intel_modeset_check_state(set->crtc->dev);
11494         }
11495
11496         if (ret) {
11497                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11498                               set->crtc->base.id, ret);
11499 fail:
11500                 intel_set_config_restore_state(dev, config);
11501
11502                 /*
11503                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11504                  * force the pipe off to avoid oopsing in the modeset code
11505                  * due to fb==NULL. This should only happen during boot since
11506                  * we don't yet reconstruct the FB from the hardware state.
11507                  */
11508                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11509                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11510
11511                 /* Try to restore the config */
11512                 if (config->mode_changed &&
11513                     intel_set_mode(save_set.crtc, save_set.mode,
11514                                    save_set.x, save_set.y, save_set.fb))
11515                         DRM_ERROR("failed to restore config after modeset failure\n");
11516         }
11517
11518 out_config:
11519         intel_set_config_free(config);
11520         return ret;
11521 }
11522
11523 static const struct drm_crtc_funcs intel_crtc_funcs = {
11524         .gamma_set = intel_crtc_gamma_set,
11525         .set_config = intel_crtc_set_config,
11526         .destroy = intel_crtc_destroy,
11527         .page_flip = intel_crtc_page_flip,
11528 };
11529
11530 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11531                                       struct intel_shared_dpll *pll,
11532                                       struct intel_dpll_hw_state *hw_state)
11533 {
11534         uint32_t val;
11535
11536         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11537                 return false;
11538
11539         val = I915_READ(PCH_DPLL(pll->id));
11540         hw_state->dpll = val;
11541         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11542         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11543
11544         return val & DPLL_VCO_ENABLE;
11545 }
11546
11547 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11548                                   struct intel_shared_dpll *pll)
11549 {
11550         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11551         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11552 }
11553
11554 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11555                                 struct intel_shared_dpll *pll)
11556 {
11557         /* PCH refclock must be enabled first */
11558         ibx_assert_pch_refclk_enabled(dev_priv);
11559
11560         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11561
11562         /* Wait for the clocks to stabilize. */
11563         POSTING_READ(PCH_DPLL(pll->id));
11564         udelay(150);
11565
11566         /* The pixel multiplier can only be updated once the
11567          * DPLL is enabled and the clocks are stable.
11568          *
11569          * So write it again.
11570          */
11571         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11572         POSTING_READ(PCH_DPLL(pll->id));
11573         udelay(200);
11574 }
11575
11576 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11577                                  struct intel_shared_dpll *pll)
11578 {
11579         struct drm_device *dev = dev_priv->dev;
11580         struct intel_crtc *crtc;
11581
11582         /* Make sure no transcoder isn't still depending on us. */
11583         for_each_intel_crtc(dev, crtc) {
11584                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11585                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11586         }
11587
11588         I915_WRITE(PCH_DPLL(pll->id), 0);
11589         POSTING_READ(PCH_DPLL(pll->id));
11590         udelay(200);
11591 }
11592
11593 static char *ibx_pch_dpll_names[] = {
11594         "PCH DPLL A",
11595         "PCH DPLL B",
11596 };
11597
11598 static void ibx_pch_dpll_init(struct drm_device *dev)
11599 {
11600         struct drm_i915_private *dev_priv = dev->dev_private;
11601         int i;
11602
11603         dev_priv->num_shared_dpll = 2;
11604
11605         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11606                 dev_priv->shared_dplls[i].id = i;
11607                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11608                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11609                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11610                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11611                 dev_priv->shared_dplls[i].get_hw_state =
11612                         ibx_pch_dpll_get_hw_state;
11613         }
11614 }
11615
11616 static void intel_shared_dpll_init(struct drm_device *dev)
11617 {
11618         struct drm_i915_private *dev_priv = dev->dev_private;
11619
11620         if (HAS_DDI(dev))
11621                 intel_ddi_pll_init(dev);
11622         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11623                 ibx_pch_dpll_init(dev);
11624         else
11625                 dev_priv->num_shared_dpll = 0;
11626
11627         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11628 }
11629
11630 static int
11631 intel_primary_plane_disable(struct drm_plane *plane)
11632 {
11633         struct drm_device *dev = plane->dev;
11634         struct intel_crtc *intel_crtc;
11635
11636         if (!plane->fb)
11637                 return 0;
11638
11639         BUG_ON(!plane->crtc);
11640
11641         intel_crtc = to_intel_crtc(plane->crtc);
11642
11643         /*
11644          * Even though we checked plane->fb above, it's still possible that
11645          * the primary plane has been implicitly disabled because the crtc
11646          * coordinates given weren't visible, or because we detected
11647          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11648          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11649          * In either case, we need to unpin the FB and let the fb pointer get
11650          * updated, but otherwise we don't need to touch the hardware.
11651          */
11652         if (!intel_crtc->primary_enabled)
11653                 goto disable_unpin;
11654
11655         intel_crtc_wait_for_pending_flips(plane->crtc);
11656         intel_disable_primary_hw_plane(plane, plane->crtc);
11657
11658 disable_unpin:
11659         mutex_lock(&dev->struct_mutex);
11660         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11661                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11662         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11663         mutex_unlock(&dev->struct_mutex);
11664         plane->fb = NULL;
11665
11666         return 0;
11667 }
11668
11669 static int
11670 intel_check_primary_plane(struct drm_plane *plane,
11671                           struct intel_plane_state *state)
11672 {
11673         struct drm_crtc *crtc = state->crtc;
11674         struct drm_framebuffer *fb = state->fb;
11675         struct drm_rect *dest = &state->dst;
11676         struct drm_rect *src = &state->src;
11677         const struct drm_rect *clip = &state->clip;
11678
11679         return drm_plane_helper_check_update(plane, crtc, fb,
11680                                              src, dest, clip,
11681                                              DRM_PLANE_HELPER_NO_SCALING,
11682                                              DRM_PLANE_HELPER_NO_SCALING,
11683                                              false, true, &state->visible);
11684 }
11685
11686 static int
11687 intel_prepare_primary_plane(struct drm_plane *plane,
11688                             struct intel_plane_state *state)
11689 {
11690         struct drm_crtc *crtc = state->crtc;
11691         struct drm_framebuffer *fb = state->fb;
11692         struct drm_device *dev = crtc->dev;
11693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11694         enum pipe pipe = intel_crtc->pipe;
11695         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11696         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11697         int ret;
11698
11699         intel_crtc_wait_for_pending_flips(crtc);
11700
11701         if (intel_crtc_has_pending_flip(crtc)) {
11702                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11703                 return -EBUSY;
11704         }
11705
11706         if (old_obj != obj) {
11707                 mutex_lock(&dev->struct_mutex);
11708                 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11709                 if (ret == 0)
11710                         i915_gem_track_fb(old_obj, obj,
11711                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11712                 mutex_unlock(&dev->struct_mutex);
11713                 if (ret != 0) {
11714                         DRM_DEBUG_KMS("pin & fence failed\n");
11715                         return ret;
11716                 }
11717         }
11718
11719         return 0;
11720 }
11721
11722 static void
11723 intel_commit_primary_plane(struct drm_plane *plane,
11724                            struct intel_plane_state *state)
11725 {
11726         struct drm_crtc *crtc = state->crtc;
11727         struct drm_framebuffer *fb = state->fb;
11728         struct drm_device *dev = crtc->dev;
11729         struct drm_i915_private *dev_priv = dev->dev_private;
11730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11731         enum pipe pipe = intel_crtc->pipe;
11732         struct drm_framebuffer *old_fb = plane->fb;
11733         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11734         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11735         struct intel_plane *intel_plane = to_intel_plane(plane);
11736         struct drm_rect *src = &state->src;
11737
11738         crtc->primary->fb = fb;
11739         crtc->x = src->x1 >> 16;
11740         crtc->y = src->y1 >> 16;
11741
11742         intel_plane->crtc_x = state->orig_dst.x1;
11743         intel_plane->crtc_y = state->orig_dst.y1;
11744         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11745         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11746         intel_plane->src_x = state->orig_src.x1;
11747         intel_plane->src_y = state->orig_src.y1;
11748         intel_plane->src_w = drm_rect_width(&state->orig_src);
11749         intel_plane->src_h = drm_rect_height(&state->orig_src);
11750         intel_plane->obj = obj;
11751
11752         if (intel_crtc->active) {
11753                 /*
11754                  * FBC does not work on some platforms for rotated
11755                  * planes, so disable it when rotation is not 0 and
11756                  * update it when rotation is set back to 0.
11757                  *
11758                  * FIXME: This is redundant with the fbc update done in
11759                  * the primary plane enable function except that that
11760                  * one is done too late. We eventually need to unify
11761                  * this.
11762                  */
11763                 if (intel_crtc->primary_enabled &&
11764                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11765                     dev_priv->fbc.plane == intel_crtc->plane &&
11766                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11767                         intel_disable_fbc(dev);
11768                 }
11769
11770                 if (state->visible) {
11771                         bool was_enabled = intel_crtc->primary_enabled;
11772
11773                         /* FIXME: kill this fastboot hack */
11774                         intel_update_pipe_size(intel_crtc);
11775
11776                         intel_crtc->primary_enabled = true;
11777
11778                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11779                                         crtc->x, crtc->y);
11780
11781                         /*
11782                          * BDW signals flip done immediately if the plane
11783                          * is disabled, even if the plane enable is already
11784                          * armed to occur at the next vblank :(
11785                          */
11786                         if (IS_BROADWELL(dev) && !was_enabled)
11787                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11788                 } else {
11789                         /*
11790                          * If clipping results in a non-visible primary plane,
11791                          * we'll disable the primary plane.  Note that this is
11792                          * a bit different than what happens if userspace
11793                          * explicitly disables the plane by passing fb=0
11794                          * because plane->fb still gets set and pinned.
11795                          */
11796                         intel_disable_primary_hw_plane(plane, crtc);
11797                 }
11798
11799                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11800
11801                 mutex_lock(&dev->struct_mutex);
11802                 intel_update_fbc(dev);
11803                 mutex_unlock(&dev->struct_mutex);
11804         }
11805
11806         if (old_fb && old_fb != fb) {
11807                 if (intel_crtc->active)
11808                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11809
11810                 mutex_lock(&dev->struct_mutex);
11811                 intel_unpin_fb_obj(old_obj);
11812                 mutex_unlock(&dev->struct_mutex);
11813         }
11814 }
11815
11816 static int
11817 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11818                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11819                              unsigned int crtc_w, unsigned int crtc_h,
11820                              uint32_t src_x, uint32_t src_y,
11821                              uint32_t src_w, uint32_t src_h)
11822 {
11823         struct intel_plane_state state;
11824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11825         int ret;
11826
11827         state.crtc = crtc;
11828         state.fb = fb;
11829
11830         /* sample coordinates in 16.16 fixed point */
11831         state.src.x1 = src_x;
11832         state.src.x2 = src_x + src_w;
11833         state.src.y1 = src_y;
11834         state.src.y2 = src_y + src_h;
11835
11836         /* integer pixels */
11837         state.dst.x1 = crtc_x;
11838         state.dst.x2 = crtc_x + crtc_w;
11839         state.dst.y1 = crtc_y;
11840         state.dst.y2 = crtc_y + crtc_h;
11841
11842         state.clip.x1 = 0;
11843         state.clip.y1 = 0;
11844         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11845         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11846
11847         state.orig_src = state.src;
11848         state.orig_dst = state.dst;
11849
11850         ret = intel_check_primary_plane(plane, &state);
11851         if (ret)
11852                 return ret;
11853
11854         ret = intel_prepare_primary_plane(plane, &state);
11855         if (ret)
11856                 return ret;
11857
11858         intel_commit_primary_plane(plane, &state);
11859
11860         return 0;
11861 }
11862
11863 /* Common destruction function for both primary and cursor planes */
11864 static void intel_plane_destroy(struct drm_plane *plane)
11865 {
11866         struct intel_plane *intel_plane = to_intel_plane(plane);
11867         drm_plane_cleanup(plane);
11868         kfree(intel_plane);
11869 }
11870
11871 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11872         .update_plane = intel_primary_plane_setplane,
11873         .disable_plane = intel_primary_plane_disable,
11874         .destroy = intel_plane_destroy,
11875         .set_property = intel_plane_set_property
11876 };
11877
11878 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11879                                                     int pipe)
11880 {
11881         struct intel_plane *primary;
11882         const uint32_t *intel_primary_formats;
11883         int num_formats;
11884
11885         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11886         if (primary == NULL)
11887                 return NULL;
11888
11889         primary->can_scale = false;
11890         primary->max_downscale = 1;
11891         primary->pipe = pipe;
11892         primary->plane = pipe;
11893         primary->rotation = BIT(DRM_ROTATE_0);
11894         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11895                 primary->plane = !pipe;
11896
11897         if (INTEL_INFO(dev)->gen <= 3) {
11898                 intel_primary_formats = intel_primary_formats_gen2;
11899                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11900         } else {
11901                 intel_primary_formats = intel_primary_formats_gen4;
11902                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11903         }
11904
11905         drm_universal_plane_init(dev, &primary->base, 0,
11906                                  &intel_primary_plane_funcs,
11907                                  intel_primary_formats, num_formats,
11908                                  DRM_PLANE_TYPE_PRIMARY);
11909
11910         if (INTEL_INFO(dev)->gen >= 4) {
11911                 if (!dev->mode_config.rotation_property)
11912                         dev->mode_config.rotation_property =
11913                                 drm_mode_create_rotation_property(dev,
11914                                                         BIT(DRM_ROTATE_0) |
11915                                                         BIT(DRM_ROTATE_180));
11916                 if (dev->mode_config.rotation_property)
11917                         drm_object_attach_property(&primary->base.base,
11918                                 dev->mode_config.rotation_property,
11919                                 primary->rotation);
11920         }
11921
11922         return &primary->base;
11923 }
11924
11925 static int
11926 intel_cursor_plane_disable(struct drm_plane *plane)
11927 {
11928         if (!plane->fb)
11929                 return 0;
11930
11931         BUG_ON(!plane->crtc);
11932
11933         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11934 }
11935
11936 static int
11937 intel_check_cursor_plane(struct drm_plane *plane,
11938                          struct intel_plane_state *state)
11939 {
11940         struct drm_crtc *crtc = state->crtc;
11941         struct drm_device *dev = crtc->dev;
11942         struct drm_framebuffer *fb = state->fb;
11943         struct drm_rect *dest = &state->dst;
11944         struct drm_rect *src = &state->src;
11945         const struct drm_rect *clip = &state->clip;
11946         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11947         int crtc_w, crtc_h;
11948         unsigned stride;
11949         int ret;
11950
11951         ret = drm_plane_helper_check_update(plane, crtc, fb,
11952                                             src, dest, clip,
11953                                             DRM_PLANE_HELPER_NO_SCALING,
11954                                             DRM_PLANE_HELPER_NO_SCALING,
11955                                             true, true, &state->visible);
11956         if (ret)
11957                 return ret;
11958
11959
11960         /* if we want to turn off the cursor ignore width and height */
11961         if (!obj)
11962                 return 0;
11963
11964         /* Check for which cursor types we support */
11965         crtc_w = drm_rect_width(&state->orig_dst);
11966         crtc_h = drm_rect_height(&state->orig_dst);
11967         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11968                 DRM_DEBUG("Cursor dimension not supported\n");
11969                 return -EINVAL;
11970         }
11971
11972         stride = roundup_pow_of_two(crtc_w) * 4;
11973         if (obj->base.size < stride * crtc_h) {
11974                 DRM_DEBUG_KMS("buffer is too small\n");
11975                 return -ENOMEM;
11976         }
11977
11978         if (fb == crtc->cursor->fb)
11979                 return 0;
11980
11981         /* we only need to pin inside GTT if cursor is non-phy */
11982         mutex_lock(&dev->struct_mutex);
11983         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11984                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11985                 ret = -EINVAL;
11986         }
11987         mutex_unlock(&dev->struct_mutex);
11988
11989         return ret;
11990 }
11991
11992 static int
11993 intel_commit_cursor_plane(struct drm_plane *plane,
11994                           struct intel_plane_state *state)
11995 {
11996         struct drm_crtc *crtc = state->crtc;
11997         struct drm_framebuffer *fb = state->fb;
11998         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11999         struct intel_plane *intel_plane = to_intel_plane(plane);
12000         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12001         struct drm_i915_gem_object *obj = intel_fb->obj;
12002         int crtc_w, crtc_h;
12003
12004         crtc->cursor_x = state->orig_dst.x1;
12005         crtc->cursor_y = state->orig_dst.y1;
12006
12007         intel_plane->crtc_x = state->orig_dst.x1;
12008         intel_plane->crtc_y = state->orig_dst.y1;
12009         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
12010         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
12011         intel_plane->src_x = state->orig_src.x1;
12012         intel_plane->src_y = state->orig_src.y1;
12013         intel_plane->src_w = drm_rect_width(&state->orig_src);
12014         intel_plane->src_h = drm_rect_height(&state->orig_src);
12015         intel_plane->obj = obj;
12016
12017         if (fb != crtc->cursor->fb) {
12018                 crtc_w = drm_rect_width(&state->orig_dst);
12019                 crtc_h = drm_rect_height(&state->orig_dst);
12020                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12021         } else {
12022                 intel_crtc_update_cursor(crtc, state->visible);
12023
12024                 intel_frontbuffer_flip(crtc->dev,
12025                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12026
12027                 return 0;
12028         }
12029 }
12030
12031 static int
12032 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12033                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12034                           unsigned int crtc_w, unsigned int crtc_h,
12035                           uint32_t src_x, uint32_t src_y,
12036                           uint32_t src_w, uint32_t src_h)
12037 {
12038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12039         struct intel_plane_state state;
12040         int ret;
12041
12042         state.crtc = crtc;
12043         state.fb = fb;
12044
12045         /* sample coordinates in 16.16 fixed point */
12046         state.src.x1 = src_x;
12047         state.src.x2 = src_x + src_w;
12048         state.src.y1 = src_y;
12049         state.src.y2 = src_y + src_h;
12050
12051         /* integer pixels */
12052         state.dst.x1 = crtc_x;
12053         state.dst.x2 = crtc_x + crtc_w;
12054         state.dst.y1 = crtc_y;
12055         state.dst.y2 = crtc_y + crtc_h;
12056
12057         state.clip.x1 = 0;
12058         state.clip.y1 = 0;
12059         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12060         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12061
12062         state.orig_src = state.src;
12063         state.orig_dst = state.dst;
12064
12065         ret = intel_check_cursor_plane(plane, &state);
12066         if (ret)
12067                 return ret;
12068
12069         return intel_commit_cursor_plane(plane, &state);
12070 }
12071
12072 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12073         .update_plane = intel_cursor_plane_update,
12074         .disable_plane = intel_cursor_plane_disable,
12075         .destroy = intel_plane_destroy,
12076         .set_property = intel_plane_set_property,
12077 };
12078
12079 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12080                                                    int pipe)
12081 {
12082         struct intel_plane *cursor;
12083
12084         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12085         if (cursor == NULL)
12086                 return NULL;
12087
12088         cursor->can_scale = false;
12089         cursor->max_downscale = 1;
12090         cursor->pipe = pipe;
12091         cursor->plane = pipe;
12092         cursor->rotation = BIT(DRM_ROTATE_0);
12093
12094         drm_universal_plane_init(dev, &cursor->base, 0,
12095                                  &intel_cursor_plane_funcs,
12096                                  intel_cursor_formats,
12097                                  ARRAY_SIZE(intel_cursor_formats),
12098                                  DRM_PLANE_TYPE_CURSOR);
12099
12100         if (INTEL_INFO(dev)->gen >= 4) {
12101                 if (!dev->mode_config.rotation_property)
12102                         dev->mode_config.rotation_property =
12103                                 drm_mode_create_rotation_property(dev,
12104                                                         BIT(DRM_ROTATE_0) |
12105                                                         BIT(DRM_ROTATE_180));
12106                 if (dev->mode_config.rotation_property)
12107                         drm_object_attach_property(&cursor->base.base,
12108                                 dev->mode_config.rotation_property,
12109                                 cursor->rotation);
12110         }
12111
12112         return &cursor->base;
12113 }
12114
12115 static void intel_crtc_init(struct drm_device *dev, int pipe)
12116 {
12117         struct drm_i915_private *dev_priv = dev->dev_private;
12118         struct intel_crtc *intel_crtc;
12119         struct drm_plane *primary = NULL;
12120         struct drm_plane *cursor = NULL;
12121         int i, ret;
12122
12123         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12124         if (intel_crtc == NULL)
12125                 return;
12126
12127         primary = intel_primary_plane_create(dev, pipe);
12128         if (!primary)
12129                 goto fail;
12130
12131         cursor = intel_cursor_plane_create(dev, pipe);
12132         if (!cursor)
12133                 goto fail;
12134
12135         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12136                                         cursor, &intel_crtc_funcs);
12137         if (ret)
12138                 goto fail;
12139
12140         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12141         for (i = 0; i < 256; i++) {
12142                 intel_crtc->lut_r[i] = i;
12143                 intel_crtc->lut_g[i] = i;
12144                 intel_crtc->lut_b[i] = i;
12145         }
12146
12147         /*
12148          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12149          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12150          */
12151         intel_crtc->pipe = pipe;
12152         intel_crtc->plane = pipe;
12153         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12154                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12155                 intel_crtc->plane = !pipe;
12156         }
12157
12158         intel_crtc->cursor_base = ~0;
12159         intel_crtc->cursor_cntl = ~0;
12160         intel_crtc->cursor_size = ~0;
12161
12162         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12163                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12164         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12165         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12166
12167         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12168
12169         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12170
12171         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12172         return;
12173
12174 fail:
12175         if (primary)
12176                 drm_plane_cleanup(primary);
12177         if (cursor)
12178                 drm_plane_cleanup(cursor);
12179         kfree(intel_crtc);
12180 }
12181
12182 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12183 {
12184         struct drm_encoder *encoder = connector->base.encoder;
12185         struct drm_device *dev = connector->base.dev;
12186
12187         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12188
12189         if (!encoder || WARN_ON(!encoder->crtc))
12190                 return INVALID_PIPE;
12191
12192         return to_intel_crtc(encoder->crtc)->pipe;
12193 }
12194
12195 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12196                                 struct drm_file *file)
12197 {
12198         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12199         struct drm_crtc *drmmode_crtc;
12200         struct intel_crtc *crtc;
12201
12202         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12203                 return -ENODEV;
12204
12205         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12206
12207         if (!drmmode_crtc) {
12208                 DRM_ERROR("no such CRTC id\n");
12209                 return -ENOENT;
12210         }
12211
12212         crtc = to_intel_crtc(drmmode_crtc);
12213         pipe_from_crtc_id->pipe = crtc->pipe;
12214
12215         return 0;
12216 }
12217
12218 static int intel_encoder_clones(struct intel_encoder *encoder)
12219 {
12220         struct drm_device *dev = encoder->base.dev;
12221         struct intel_encoder *source_encoder;
12222         int index_mask = 0;
12223         int entry = 0;
12224
12225         for_each_intel_encoder(dev, source_encoder) {
12226                 if (encoders_cloneable(encoder, source_encoder))
12227                         index_mask |= (1 << entry);
12228
12229                 entry++;
12230         }
12231
12232         return index_mask;
12233 }
12234
12235 static bool has_edp_a(struct drm_device *dev)
12236 {
12237         struct drm_i915_private *dev_priv = dev->dev_private;
12238
12239         if (!IS_MOBILE(dev))
12240                 return false;
12241
12242         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12243                 return false;
12244
12245         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12246                 return false;
12247
12248         return true;
12249 }
12250
12251 const char *intel_output_name(int output)
12252 {
12253         static const char *names[] = {
12254                 [INTEL_OUTPUT_UNUSED] = "Unused",
12255                 [INTEL_OUTPUT_ANALOG] = "Analog",
12256                 [INTEL_OUTPUT_DVO] = "DVO",
12257                 [INTEL_OUTPUT_SDVO] = "SDVO",
12258                 [INTEL_OUTPUT_LVDS] = "LVDS",
12259                 [INTEL_OUTPUT_TVOUT] = "TV",
12260                 [INTEL_OUTPUT_HDMI] = "HDMI",
12261                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12262                 [INTEL_OUTPUT_EDP] = "eDP",
12263                 [INTEL_OUTPUT_DSI] = "DSI",
12264                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12265         };
12266
12267         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12268                 return "Invalid";
12269
12270         return names[output];
12271 }
12272
12273 static bool intel_crt_present(struct drm_device *dev)
12274 {
12275         struct drm_i915_private *dev_priv = dev->dev_private;
12276
12277         if (INTEL_INFO(dev)->gen >= 9)
12278                 return false;
12279
12280         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12281                 return false;
12282
12283         if (IS_CHERRYVIEW(dev))
12284                 return false;
12285
12286         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12287                 return false;
12288
12289         return true;
12290 }
12291
12292 static void intel_setup_outputs(struct drm_device *dev)
12293 {
12294         struct drm_i915_private *dev_priv = dev->dev_private;
12295         struct intel_encoder *encoder;
12296         bool dpd_is_edp = false;
12297
12298         intel_lvds_init(dev);
12299
12300         if (intel_crt_present(dev))
12301                 intel_crt_init(dev);
12302
12303         if (HAS_DDI(dev)) {
12304                 int found;
12305
12306                 /* Haswell uses DDI functions to detect digital outputs */
12307                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12308                 /* DDI A only supports eDP */
12309                 if (found)
12310                         intel_ddi_init(dev, PORT_A);
12311
12312                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12313                  * register */
12314                 found = I915_READ(SFUSE_STRAP);
12315
12316                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12317                         intel_ddi_init(dev, PORT_B);
12318                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12319                         intel_ddi_init(dev, PORT_C);
12320                 if (found & SFUSE_STRAP_DDID_DETECTED)
12321                         intel_ddi_init(dev, PORT_D);
12322         } else if (HAS_PCH_SPLIT(dev)) {
12323                 int found;
12324                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12325
12326                 if (has_edp_a(dev))
12327                         intel_dp_init(dev, DP_A, PORT_A);
12328
12329                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12330                         /* PCH SDVOB multiplex with HDMIB */
12331                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12332                         if (!found)
12333                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12334                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12335                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12336                 }
12337
12338                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12339                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12340
12341                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12342                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12343
12344                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12345                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12346
12347                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12348                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12349         } else if (IS_VALLEYVIEW(dev)) {
12350                 /*
12351                  * The DP_DETECTED bit is the latched state of the DDC
12352                  * SDA pin at boot. However since eDP doesn't require DDC
12353                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12354                  * eDP ports may have been muxed to an alternate function.
12355                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12356                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12357                  * detect eDP ports.
12358                  */
12359                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12360                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12361                                         PORT_B);
12362                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12363                     intel_dp_is_edp(dev, PORT_B))
12364                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12365
12366                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12367                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12368                                         PORT_C);
12369                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12370                     intel_dp_is_edp(dev, PORT_C))
12371                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12372
12373                 if (IS_CHERRYVIEW(dev)) {
12374                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12375                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12376                                                 PORT_D);
12377                         /* eDP not supported on port D, so don't check VBT */
12378                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12379                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12380                 }
12381
12382                 intel_dsi_init(dev);
12383         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12384                 bool found = false;
12385
12386                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12387                         DRM_DEBUG_KMS("probing SDVOB\n");
12388                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12389                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12390                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12391                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12392                         }
12393
12394                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12395                                 intel_dp_init(dev, DP_B, PORT_B);
12396                 }
12397
12398                 /* Before G4X SDVOC doesn't have its own detect register */
12399
12400                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12401                         DRM_DEBUG_KMS("probing SDVOC\n");
12402                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12403                 }
12404
12405                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12406
12407                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12408                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12409                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12410                         }
12411                         if (SUPPORTS_INTEGRATED_DP(dev))
12412                                 intel_dp_init(dev, DP_C, PORT_C);
12413                 }
12414
12415                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12416                     (I915_READ(DP_D) & DP_DETECTED))
12417                         intel_dp_init(dev, DP_D, PORT_D);
12418         } else if (IS_GEN2(dev))
12419                 intel_dvo_init(dev);
12420
12421         if (SUPPORTS_TV(dev))
12422                 intel_tv_init(dev);
12423
12424         intel_psr_init(dev);
12425
12426         for_each_intel_encoder(dev, encoder) {
12427                 encoder->base.possible_crtcs = encoder->crtc_mask;
12428                 encoder->base.possible_clones =
12429                         intel_encoder_clones(encoder);
12430         }
12431
12432         intel_init_pch_refclk(dev);
12433
12434         drm_helper_move_panel_connectors_to_head(dev);
12435 }
12436
12437 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12438 {
12439         struct drm_device *dev = fb->dev;
12440         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12441
12442         drm_framebuffer_cleanup(fb);
12443         mutex_lock(&dev->struct_mutex);
12444         WARN_ON(!intel_fb->obj->framebuffer_references--);
12445         drm_gem_object_unreference(&intel_fb->obj->base);
12446         mutex_unlock(&dev->struct_mutex);
12447         kfree(intel_fb);
12448 }
12449
12450 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12451                                                 struct drm_file *file,
12452                                                 unsigned int *handle)
12453 {
12454         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12455         struct drm_i915_gem_object *obj = intel_fb->obj;
12456
12457         return drm_gem_handle_create(file, &obj->base, handle);
12458 }
12459
12460 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12461         .destroy = intel_user_framebuffer_destroy,
12462         .create_handle = intel_user_framebuffer_create_handle,
12463 };
12464
12465 static int intel_framebuffer_init(struct drm_device *dev,
12466                                   struct intel_framebuffer *intel_fb,
12467                                   struct drm_mode_fb_cmd2 *mode_cmd,
12468                                   struct drm_i915_gem_object *obj)
12469 {
12470         int aligned_height;
12471         int pitch_limit;
12472         int ret;
12473
12474         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12475
12476         if (obj->tiling_mode == I915_TILING_Y) {
12477                 DRM_DEBUG("hardware does not support tiling Y\n");
12478                 return -EINVAL;
12479         }
12480
12481         if (mode_cmd->pitches[0] & 63) {
12482                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12483                           mode_cmd->pitches[0]);
12484                 return -EINVAL;
12485         }
12486
12487         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12488                 pitch_limit = 32*1024;
12489         } else if (INTEL_INFO(dev)->gen >= 4) {
12490                 if (obj->tiling_mode)
12491                         pitch_limit = 16*1024;
12492                 else
12493                         pitch_limit = 32*1024;
12494         } else if (INTEL_INFO(dev)->gen >= 3) {
12495                 if (obj->tiling_mode)
12496                         pitch_limit = 8*1024;
12497                 else
12498                         pitch_limit = 16*1024;
12499         } else
12500                 /* XXX DSPC is limited to 4k tiled */
12501                 pitch_limit = 8*1024;
12502
12503         if (mode_cmd->pitches[0] > pitch_limit) {
12504                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12505                           obj->tiling_mode ? "tiled" : "linear",
12506                           mode_cmd->pitches[0], pitch_limit);
12507                 return -EINVAL;
12508         }
12509
12510         if (obj->tiling_mode != I915_TILING_NONE &&
12511             mode_cmd->pitches[0] != obj->stride) {
12512                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12513                           mode_cmd->pitches[0], obj->stride);
12514                 return -EINVAL;
12515         }
12516
12517         /* Reject formats not supported by any plane early. */
12518         switch (mode_cmd->pixel_format) {
12519         case DRM_FORMAT_C8:
12520         case DRM_FORMAT_RGB565:
12521         case DRM_FORMAT_XRGB8888:
12522         case DRM_FORMAT_ARGB8888:
12523                 break;
12524         case DRM_FORMAT_XRGB1555:
12525         case DRM_FORMAT_ARGB1555:
12526                 if (INTEL_INFO(dev)->gen > 3) {
12527                         DRM_DEBUG("unsupported pixel format: %s\n",
12528                                   drm_get_format_name(mode_cmd->pixel_format));
12529                         return -EINVAL;
12530                 }
12531                 break;
12532         case DRM_FORMAT_XBGR8888:
12533         case DRM_FORMAT_ABGR8888:
12534         case DRM_FORMAT_XRGB2101010:
12535         case DRM_FORMAT_ARGB2101010:
12536         case DRM_FORMAT_XBGR2101010:
12537         case DRM_FORMAT_ABGR2101010:
12538                 if (INTEL_INFO(dev)->gen < 4) {
12539                         DRM_DEBUG("unsupported pixel format: %s\n",
12540                                   drm_get_format_name(mode_cmd->pixel_format));
12541                         return -EINVAL;
12542                 }
12543                 break;
12544         case DRM_FORMAT_YUYV:
12545         case DRM_FORMAT_UYVY:
12546         case DRM_FORMAT_YVYU:
12547         case DRM_FORMAT_VYUY:
12548                 if (INTEL_INFO(dev)->gen < 5) {
12549                         DRM_DEBUG("unsupported pixel format: %s\n",
12550                                   drm_get_format_name(mode_cmd->pixel_format));
12551                         return -EINVAL;
12552                 }
12553                 break;
12554         default:
12555                 DRM_DEBUG("unsupported pixel format: %s\n",
12556                           drm_get_format_name(mode_cmd->pixel_format));
12557                 return -EINVAL;
12558         }
12559
12560         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12561         if (mode_cmd->offsets[0] != 0)
12562                 return -EINVAL;
12563
12564         aligned_height = intel_align_height(dev, mode_cmd->height,
12565                                             obj->tiling_mode);
12566         /* FIXME drm helper for size checks (especially planar formats)? */
12567         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12568                 return -EINVAL;
12569
12570         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12571         intel_fb->obj = obj;
12572         intel_fb->obj->framebuffer_references++;
12573
12574         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12575         if (ret) {
12576                 DRM_ERROR("framebuffer init failed %d\n", ret);
12577                 return ret;
12578         }
12579
12580         return 0;
12581 }
12582
12583 static struct drm_framebuffer *
12584 intel_user_framebuffer_create(struct drm_device *dev,
12585                               struct drm_file *filp,
12586                               struct drm_mode_fb_cmd2 *mode_cmd)
12587 {
12588         struct drm_i915_gem_object *obj;
12589
12590         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12591                                                 mode_cmd->handles[0]));
12592         if (&obj->base == NULL)
12593                 return ERR_PTR(-ENOENT);
12594
12595         return intel_framebuffer_create(dev, mode_cmd, obj);
12596 }
12597
12598 #ifndef CONFIG_DRM_I915_FBDEV
12599 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12600 {
12601 }
12602 #endif
12603
12604 static const struct drm_mode_config_funcs intel_mode_funcs = {
12605         .fb_create = intel_user_framebuffer_create,
12606         .output_poll_changed = intel_fbdev_output_poll_changed,
12607 };
12608
12609 /* Set up chip specific display functions */
12610 static void intel_init_display(struct drm_device *dev)
12611 {
12612         struct drm_i915_private *dev_priv = dev->dev_private;
12613
12614         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12615                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12616         else if (IS_CHERRYVIEW(dev))
12617                 dev_priv->display.find_dpll = chv_find_best_dpll;
12618         else if (IS_VALLEYVIEW(dev))
12619                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12620         else if (IS_PINEVIEW(dev))
12621                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12622         else
12623                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12624
12625         if (HAS_DDI(dev)) {
12626                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12627                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12628                 dev_priv->display.crtc_compute_clock =
12629                         haswell_crtc_compute_clock;
12630                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12631                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12632                 dev_priv->display.off = ironlake_crtc_off;
12633                 if (INTEL_INFO(dev)->gen >= 9)
12634                         dev_priv->display.update_primary_plane =
12635                                 skylake_update_primary_plane;
12636                 else
12637                         dev_priv->display.update_primary_plane =
12638                                 ironlake_update_primary_plane;
12639         } else if (HAS_PCH_SPLIT(dev)) {
12640                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12641                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12642                 dev_priv->display.crtc_compute_clock =
12643                         ironlake_crtc_compute_clock;
12644                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12645                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12646                 dev_priv->display.off = ironlake_crtc_off;
12647                 dev_priv->display.update_primary_plane =
12648                         ironlake_update_primary_plane;
12649         } else if (IS_VALLEYVIEW(dev)) {
12650                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12651                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12652                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12653                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12654                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12655                 dev_priv->display.off = i9xx_crtc_off;
12656                 dev_priv->display.update_primary_plane =
12657                         i9xx_update_primary_plane;
12658         } else {
12659                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12660                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12661                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12662                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12663                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12664                 dev_priv->display.off = i9xx_crtc_off;
12665                 dev_priv->display.update_primary_plane =
12666                         i9xx_update_primary_plane;
12667         }
12668
12669         /* Returns the core display clock speed */
12670         if (IS_VALLEYVIEW(dev))
12671                 dev_priv->display.get_display_clock_speed =
12672                         valleyview_get_display_clock_speed;
12673         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12674                 dev_priv->display.get_display_clock_speed =
12675                         i945_get_display_clock_speed;
12676         else if (IS_I915G(dev))
12677                 dev_priv->display.get_display_clock_speed =
12678                         i915_get_display_clock_speed;
12679         else if (IS_I945GM(dev) || IS_845G(dev))
12680                 dev_priv->display.get_display_clock_speed =
12681                         i9xx_misc_get_display_clock_speed;
12682         else if (IS_PINEVIEW(dev))
12683                 dev_priv->display.get_display_clock_speed =
12684                         pnv_get_display_clock_speed;
12685         else if (IS_I915GM(dev))
12686                 dev_priv->display.get_display_clock_speed =
12687                         i915gm_get_display_clock_speed;
12688         else if (IS_I865G(dev))
12689                 dev_priv->display.get_display_clock_speed =
12690                         i865_get_display_clock_speed;
12691         else if (IS_I85X(dev))
12692                 dev_priv->display.get_display_clock_speed =
12693                         i855_get_display_clock_speed;
12694         else /* 852, 830 */
12695                 dev_priv->display.get_display_clock_speed =
12696                         i830_get_display_clock_speed;
12697
12698         if (IS_GEN5(dev)) {
12699                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12700         } else if (IS_GEN6(dev)) {
12701                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12702         } else if (IS_IVYBRIDGE(dev)) {
12703                 /* FIXME: detect B0+ stepping and use auto training */
12704                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12705                 dev_priv->display.modeset_global_resources =
12706                         ivb_modeset_global_resources;
12707         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12708                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12709         } else if (IS_VALLEYVIEW(dev)) {
12710                 dev_priv->display.modeset_global_resources =
12711                         valleyview_modeset_global_resources;
12712         }
12713
12714         /* Default just returns -ENODEV to indicate unsupported */
12715         dev_priv->display.queue_flip = intel_default_queue_flip;
12716
12717         switch (INTEL_INFO(dev)->gen) {
12718         case 2:
12719                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12720                 break;
12721
12722         case 3:
12723                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12724                 break;
12725
12726         case 4:
12727         case 5:
12728                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12729                 break;
12730
12731         case 6:
12732                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12733                 break;
12734         case 7:
12735         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12736                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12737                 break;
12738         case 9:
12739                 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12740                 break;
12741         }
12742
12743         intel_panel_init_backlight_funcs(dev);
12744
12745         mutex_init(&dev_priv->pps_mutex);
12746 }
12747
12748 /*
12749  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12750  * resume, or other times.  This quirk makes sure that's the case for
12751  * affected systems.
12752  */
12753 static void quirk_pipea_force(struct drm_device *dev)
12754 {
12755         struct drm_i915_private *dev_priv = dev->dev_private;
12756
12757         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12758         DRM_INFO("applying pipe a force quirk\n");
12759 }
12760
12761 static void quirk_pipeb_force(struct drm_device *dev)
12762 {
12763         struct drm_i915_private *dev_priv = dev->dev_private;
12764
12765         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12766         DRM_INFO("applying pipe b force quirk\n");
12767 }
12768
12769 /*
12770  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12771  */
12772 static void quirk_ssc_force_disable(struct drm_device *dev)
12773 {
12774         struct drm_i915_private *dev_priv = dev->dev_private;
12775         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12776         DRM_INFO("applying lvds SSC disable quirk\n");
12777 }
12778
12779 /*
12780  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12781  * brightness value
12782  */
12783 static void quirk_invert_brightness(struct drm_device *dev)
12784 {
12785         struct drm_i915_private *dev_priv = dev->dev_private;
12786         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12787         DRM_INFO("applying inverted panel brightness quirk\n");
12788 }
12789
12790 /* Some VBT's incorrectly indicate no backlight is present */
12791 static void quirk_backlight_present(struct drm_device *dev)
12792 {
12793         struct drm_i915_private *dev_priv = dev->dev_private;
12794         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12795         DRM_INFO("applying backlight present quirk\n");
12796 }
12797
12798 struct intel_quirk {
12799         int device;
12800         int subsystem_vendor;
12801         int subsystem_device;
12802         void (*hook)(struct drm_device *dev);
12803 };
12804
12805 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12806 struct intel_dmi_quirk {
12807         void (*hook)(struct drm_device *dev);
12808         const struct dmi_system_id (*dmi_id_list)[];
12809 };
12810
12811 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12812 {
12813         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12814         return 1;
12815 }
12816
12817 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12818         {
12819                 .dmi_id_list = &(const struct dmi_system_id[]) {
12820                         {
12821                                 .callback = intel_dmi_reverse_brightness,
12822                                 .ident = "NCR Corporation",
12823                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12824                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12825                                 },
12826                         },
12827                         { }  /* terminating entry */
12828                 },
12829                 .hook = quirk_invert_brightness,
12830         },
12831 };
12832
12833 static struct intel_quirk intel_quirks[] = {
12834         /* HP Mini needs pipe A force quirk (LP: #322104) */
12835         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12836
12837         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12838         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12839
12840         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12841         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12842
12843         /* 830 needs to leave pipe A & dpll A up */
12844         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12845
12846         /* 830 needs to leave pipe B & dpll B up */
12847         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12848
12849         /* Lenovo U160 cannot use SSC on LVDS */
12850         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12851
12852         /* Sony Vaio Y cannot use SSC on LVDS */
12853         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12854
12855         /* Acer Aspire 5734Z must invert backlight brightness */
12856         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12857
12858         /* Acer/eMachines G725 */
12859         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12860
12861         /* Acer/eMachines e725 */
12862         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12863
12864         /* Acer/Packard Bell NCL20 */
12865         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12866
12867         /* Acer Aspire 4736Z */
12868         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12869
12870         /* Acer Aspire 5336 */
12871         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12872
12873         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12874         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12875
12876         /* Acer C720 Chromebook (Core i3 4005U) */
12877         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12878
12879         /* Apple Macbook 2,1 (Core 2 T7400) */
12880         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
12881
12882         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12883         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12884
12885         /* HP Chromebook 14 (Celeron 2955U) */
12886         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12887 };
12888
12889 static void intel_init_quirks(struct drm_device *dev)
12890 {
12891         struct pci_dev *d = dev->pdev;
12892         int i;
12893
12894         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12895                 struct intel_quirk *q = &intel_quirks[i];
12896
12897                 if (d->device == q->device &&
12898                     (d->subsystem_vendor == q->subsystem_vendor ||
12899                      q->subsystem_vendor == PCI_ANY_ID) &&
12900                     (d->subsystem_device == q->subsystem_device ||
12901                      q->subsystem_device == PCI_ANY_ID))
12902                         q->hook(dev);
12903         }
12904         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12905                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12906                         intel_dmi_quirks[i].hook(dev);
12907         }
12908 }
12909
12910 /* Disable the VGA plane that we never use */
12911 static void i915_disable_vga(struct drm_device *dev)
12912 {
12913         struct drm_i915_private *dev_priv = dev->dev_private;
12914         u8 sr1;
12915         u32 vga_reg = i915_vgacntrl_reg(dev);
12916
12917         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12918         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12919         outb(SR01, VGA_SR_INDEX);
12920         sr1 = inb(VGA_SR_DATA);
12921         outb(sr1 | 1<<5, VGA_SR_DATA);
12922         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12923         udelay(300);
12924
12925         /*
12926          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12927          * from S3 without preserving (some of?) the other bits.
12928          */
12929         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12930         POSTING_READ(vga_reg);
12931 }
12932
12933 void intel_modeset_init_hw(struct drm_device *dev)
12934 {
12935         intel_prepare_ddi(dev);
12936
12937         if (IS_VALLEYVIEW(dev))
12938                 vlv_update_cdclk(dev);
12939
12940         intel_init_clock_gating(dev);
12941
12942         intel_enable_gt_powersave(dev);
12943 }
12944
12945 void intel_modeset_init(struct drm_device *dev)
12946 {
12947         struct drm_i915_private *dev_priv = dev->dev_private;
12948         int sprite, ret;
12949         enum pipe pipe;
12950         struct intel_crtc *crtc;
12951
12952         drm_mode_config_init(dev);
12953
12954         dev->mode_config.min_width = 0;
12955         dev->mode_config.min_height = 0;
12956
12957         dev->mode_config.preferred_depth = 24;
12958         dev->mode_config.prefer_shadow = 1;
12959
12960         dev->mode_config.funcs = &intel_mode_funcs;
12961
12962         intel_init_quirks(dev);
12963
12964         intel_init_pm(dev);
12965
12966         if (INTEL_INFO(dev)->num_pipes == 0)
12967                 return;
12968
12969         intel_init_display(dev);
12970         intel_init_audio(dev);
12971
12972         if (IS_GEN2(dev)) {
12973                 dev->mode_config.max_width = 2048;
12974                 dev->mode_config.max_height = 2048;
12975         } else if (IS_GEN3(dev)) {
12976                 dev->mode_config.max_width = 4096;
12977                 dev->mode_config.max_height = 4096;
12978         } else {
12979                 dev->mode_config.max_width = 8192;
12980                 dev->mode_config.max_height = 8192;
12981         }
12982
12983         if (IS_845G(dev) || IS_I865G(dev)) {
12984                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12985                 dev->mode_config.cursor_height = 1023;
12986         } else if (IS_GEN2(dev)) {
12987                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12988                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12989         } else {
12990                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12991                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12992         }
12993
12994         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12995
12996         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12997                       INTEL_INFO(dev)->num_pipes,
12998                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12999
13000         for_each_pipe(dev_priv, pipe) {
13001                 intel_crtc_init(dev, pipe);
13002                 for_each_sprite(pipe, sprite) {
13003                         ret = intel_plane_init(dev, pipe, sprite);
13004                         if (ret)
13005                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13006                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13007                 }
13008         }
13009
13010         intel_init_dpio(dev);
13011
13012         intel_shared_dpll_init(dev);
13013
13014         /* save the BIOS value before clobbering it */
13015         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13016         /* Just disable it once at startup */
13017         i915_disable_vga(dev);
13018         intel_setup_outputs(dev);
13019
13020         /* Just in case the BIOS is doing something questionable. */
13021         intel_disable_fbc(dev);
13022
13023         drm_modeset_lock_all(dev);
13024         intel_modeset_setup_hw_state(dev, false);
13025         drm_modeset_unlock_all(dev);
13026
13027         for_each_intel_crtc(dev, crtc) {
13028                 if (!crtc->active)
13029                         continue;
13030
13031                 /*
13032                  * Note that reserving the BIOS fb up front prevents us
13033                  * from stuffing other stolen allocations like the ring
13034                  * on top.  This prevents some ugliness at boot time, and
13035                  * can even allow for smooth boot transitions if the BIOS
13036                  * fb is large enough for the active pipe configuration.
13037                  */
13038                 if (dev_priv->display.get_plane_config) {
13039                         dev_priv->display.get_plane_config(crtc,
13040                                                            &crtc->plane_config);
13041                         /*
13042                          * If the fb is shared between multiple heads, we'll
13043                          * just get the first one.
13044                          */
13045                         intel_find_plane_obj(crtc, &crtc->plane_config);
13046                 }
13047         }
13048 }
13049
13050 static void intel_enable_pipe_a(struct drm_device *dev)
13051 {
13052         struct intel_connector *connector;
13053         struct drm_connector *crt = NULL;
13054         struct intel_load_detect_pipe load_detect_temp;
13055         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13056
13057         /* We can't just switch on the pipe A, we need to set things up with a
13058          * proper mode and output configuration. As a gross hack, enable pipe A
13059          * by enabling the load detect pipe once. */
13060         list_for_each_entry(connector,
13061                             &dev->mode_config.connector_list,
13062                             base.head) {
13063                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13064                         crt = &connector->base;
13065                         break;
13066                 }
13067         }
13068
13069         if (!crt)
13070                 return;
13071
13072         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13073                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13074 }
13075
13076 static bool
13077 intel_check_plane_mapping(struct intel_crtc *crtc)
13078 {
13079         struct drm_device *dev = crtc->base.dev;
13080         struct drm_i915_private *dev_priv = dev->dev_private;
13081         u32 reg, val;
13082
13083         if (INTEL_INFO(dev)->num_pipes == 1)
13084                 return true;
13085
13086         reg = DSPCNTR(!crtc->plane);
13087         val = I915_READ(reg);
13088
13089         if ((val & DISPLAY_PLANE_ENABLE) &&
13090             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13091                 return false;
13092
13093         return true;
13094 }
13095
13096 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13097 {
13098         struct drm_device *dev = crtc->base.dev;
13099         struct drm_i915_private *dev_priv = dev->dev_private;
13100         u32 reg;
13101
13102         /* Clear any frame start delays used for debugging left by the BIOS */
13103         reg = PIPECONF(crtc->config.cpu_transcoder);
13104         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13105
13106         /* restore vblank interrupts to correct state */
13107         if (crtc->active) {
13108                 update_scanline_offset(crtc);
13109                 drm_vblank_on(dev, crtc->pipe);
13110         } else
13111                 drm_vblank_off(dev, crtc->pipe);
13112
13113         /* We need to sanitize the plane -> pipe mapping first because this will
13114          * disable the crtc (and hence change the state) if it is wrong. Note
13115          * that gen4+ has a fixed plane -> pipe mapping.  */
13116         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13117                 struct intel_connector *connector;
13118                 bool plane;
13119
13120                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13121                               crtc->base.base.id);
13122
13123                 /* Pipe has the wrong plane attached and the plane is active.
13124                  * Temporarily change the plane mapping and disable everything
13125                  * ...  */
13126                 plane = crtc->plane;
13127                 crtc->plane = !plane;
13128                 crtc->primary_enabled = true;
13129                 dev_priv->display.crtc_disable(&crtc->base);
13130                 crtc->plane = plane;
13131
13132                 /* ... and break all links. */
13133                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13134                                     base.head) {
13135                         if (connector->encoder->base.crtc != &crtc->base)
13136                                 continue;
13137
13138                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13139                         connector->base.encoder = NULL;
13140                 }
13141                 /* multiple connectors may have the same encoder:
13142                  *  handle them and break crtc link separately */
13143                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13144                                     base.head)
13145                         if (connector->encoder->base.crtc == &crtc->base) {
13146                                 connector->encoder->base.crtc = NULL;
13147                                 connector->encoder->connectors_active = false;
13148                         }
13149
13150                 WARN_ON(crtc->active);
13151                 crtc->base.enabled = false;
13152         }
13153
13154         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13155             crtc->pipe == PIPE_A && !crtc->active) {
13156                 /* BIOS forgot to enable pipe A, this mostly happens after
13157                  * resume. Force-enable the pipe to fix this, the update_dpms
13158                  * call below we restore the pipe to the right state, but leave
13159                  * the required bits on. */
13160                 intel_enable_pipe_a(dev);
13161         }
13162
13163         /* Adjust the state of the output pipe according to whether we
13164          * have active connectors/encoders. */
13165         intel_crtc_update_dpms(&crtc->base);
13166
13167         if (crtc->active != crtc->base.enabled) {
13168                 struct intel_encoder *encoder;
13169
13170                 /* This can happen either due to bugs in the get_hw_state
13171                  * functions or because the pipe is force-enabled due to the
13172                  * pipe A quirk. */
13173                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13174                               crtc->base.base.id,
13175                               crtc->base.enabled ? "enabled" : "disabled",
13176                               crtc->active ? "enabled" : "disabled");
13177
13178                 crtc->base.enabled = crtc->active;
13179
13180                 /* Because we only establish the connector -> encoder ->
13181                  * crtc links if something is active, this means the
13182                  * crtc is now deactivated. Break the links. connector
13183                  * -> encoder links are only establish when things are
13184                  *  actually up, hence no need to break them. */
13185                 WARN_ON(crtc->active);
13186
13187                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13188                         WARN_ON(encoder->connectors_active);
13189                         encoder->base.crtc = NULL;
13190                 }
13191         }
13192
13193         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13194                 /*
13195                  * We start out with underrun reporting disabled to avoid races.
13196                  * For correct bookkeeping mark this on active crtcs.
13197                  *
13198                  * Also on gmch platforms we dont have any hardware bits to
13199                  * disable the underrun reporting. Which means we need to start
13200                  * out with underrun reporting disabled also on inactive pipes,
13201                  * since otherwise we'll complain about the garbage we read when
13202                  * e.g. coming up after runtime pm.
13203                  *
13204                  * No protection against concurrent access is required - at
13205                  * worst a fifo underrun happens which also sets this to false.
13206                  */
13207                 crtc->cpu_fifo_underrun_disabled = true;
13208                 crtc->pch_fifo_underrun_disabled = true;
13209         }
13210 }
13211
13212 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13213 {
13214         struct intel_connector *connector;
13215         struct drm_device *dev = encoder->base.dev;
13216
13217         /* We need to check both for a crtc link (meaning that the
13218          * encoder is active and trying to read from a pipe) and the
13219          * pipe itself being active. */
13220         bool has_active_crtc = encoder->base.crtc &&
13221                 to_intel_crtc(encoder->base.crtc)->active;
13222
13223         if (encoder->connectors_active && !has_active_crtc) {
13224                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13225                               encoder->base.base.id,
13226                               encoder->base.name);
13227
13228                 /* Connector is active, but has no active pipe. This is
13229                  * fallout from our resume register restoring. Disable
13230                  * the encoder manually again. */
13231                 if (encoder->base.crtc) {
13232                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13233                                       encoder->base.base.id,
13234                                       encoder->base.name);
13235                         encoder->disable(encoder);
13236                         if (encoder->post_disable)
13237                                 encoder->post_disable(encoder);
13238                 }
13239                 encoder->base.crtc = NULL;
13240                 encoder->connectors_active = false;
13241
13242                 /* Inconsistent output/port/pipe state happens presumably due to
13243                  * a bug in one of the get_hw_state functions. Or someplace else
13244                  * in our code, like the register restore mess on resume. Clamp
13245                  * things to off as a safer default. */
13246                 list_for_each_entry(connector,
13247                                     &dev->mode_config.connector_list,
13248                                     base.head) {
13249                         if (connector->encoder != encoder)
13250                                 continue;
13251                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13252                         connector->base.encoder = NULL;
13253                 }
13254         }
13255         /* Enabled encoders without active connectors will be fixed in
13256          * the crtc fixup. */
13257 }
13258
13259 void i915_redisable_vga_power_on(struct drm_device *dev)
13260 {
13261         struct drm_i915_private *dev_priv = dev->dev_private;
13262         u32 vga_reg = i915_vgacntrl_reg(dev);
13263
13264         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13265                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13266                 i915_disable_vga(dev);
13267         }
13268 }
13269
13270 void i915_redisable_vga(struct drm_device *dev)
13271 {
13272         struct drm_i915_private *dev_priv = dev->dev_private;
13273
13274         /* This function can be called both from intel_modeset_setup_hw_state or
13275          * at a very early point in our resume sequence, where the power well
13276          * structures are not yet restored. Since this function is at a very
13277          * paranoid "someone might have enabled VGA while we were not looking"
13278          * level, just check if the power well is enabled instead of trying to
13279          * follow the "don't touch the power well if we don't need it" policy
13280          * the rest of the driver uses. */
13281         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13282                 return;
13283
13284         i915_redisable_vga_power_on(dev);
13285 }
13286
13287 static bool primary_get_hw_state(struct intel_crtc *crtc)
13288 {
13289         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13290
13291         if (!crtc->active)
13292                 return false;
13293
13294         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13295 }
13296
13297 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13298 {
13299         struct drm_i915_private *dev_priv = dev->dev_private;
13300         enum pipe pipe;
13301         struct intel_crtc *crtc;
13302         struct intel_encoder *encoder;
13303         struct intel_connector *connector;
13304         int i;
13305
13306         for_each_intel_crtc(dev, crtc) {
13307                 memset(&crtc->config, 0, sizeof(crtc->config));
13308
13309                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13310
13311                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13312                                                                  &crtc->config);
13313
13314                 crtc->base.enabled = crtc->active;
13315                 crtc->primary_enabled = primary_get_hw_state(crtc);
13316
13317                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13318                               crtc->base.base.id,
13319                               crtc->active ? "enabled" : "disabled");
13320         }
13321
13322         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13323                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13324
13325                 pll->on = pll->get_hw_state(dev_priv, pll,
13326                                             &pll->config.hw_state);
13327                 pll->active = 0;
13328                 pll->config.crtc_mask = 0;
13329                 for_each_intel_crtc(dev, crtc) {
13330                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13331                                 pll->active++;
13332                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13333                         }
13334                 }
13335
13336                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13337                               pll->name, pll->config.crtc_mask, pll->on);
13338
13339                 if (pll->config.crtc_mask)
13340                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13341         }
13342
13343         for_each_intel_encoder(dev, encoder) {
13344                 pipe = 0;
13345
13346                 if (encoder->get_hw_state(encoder, &pipe)) {
13347                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13348                         encoder->base.crtc = &crtc->base;
13349                         encoder->get_config(encoder, &crtc->config);
13350                 } else {
13351                         encoder->base.crtc = NULL;
13352                 }
13353
13354                 encoder->connectors_active = false;
13355                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13356                               encoder->base.base.id,
13357                               encoder->base.name,
13358                               encoder->base.crtc ? "enabled" : "disabled",
13359                               pipe_name(pipe));
13360         }
13361
13362         list_for_each_entry(connector, &dev->mode_config.connector_list,
13363                             base.head) {
13364                 if (connector->get_hw_state(connector)) {
13365                         connector->base.dpms = DRM_MODE_DPMS_ON;
13366                         connector->encoder->connectors_active = true;
13367                         connector->base.encoder = &connector->encoder->base;
13368                 } else {
13369                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13370                         connector->base.encoder = NULL;
13371                 }
13372                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13373                               connector->base.base.id,
13374                               connector->base.name,
13375                               connector->base.encoder ? "enabled" : "disabled");
13376         }
13377 }
13378
13379 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13380  * and i915 state tracking structures. */
13381 void intel_modeset_setup_hw_state(struct drm_device *dev,
13382                                   bool force_restore)
13383 {
13384         struct drm_i915_private *dev_priv = dev->dev_private;
13385         enum pipe pipe;
13386         struct intel_crtc *crtc;
13387         struct intel_encoder *encoder;
13388         int i;
13389
13390         intel_modeset_readout_hw_state(dev);
13391
13392         /*
13393          * Now that we have the config, copy it to each CRTC struct
13394          * Note that this could go away if we move to using crtc_config
13395          * checking everywhere.
13396          */
13397         for_each_intel_crtc(dev, crtc) {
13398                 if (crtc->active && i915.fastboot) {
13399                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13400                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13401                                       crtc->base.base.id);
13402                         drm_mode_debug_printmodeline(&crtc->base.mode);
13403                 }
13404         }
13405
13406         /* HW state is read out, now we need to sanitize this mess. */
13407         for_each_intel_encoder(dev, encoder) {
13408                 intel_sanitize_encoder(encoder);
13409         }
13410
13411         for_each_pipe(dev_priv, pipe) {
13412                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13413                 intel_sanitize_crtc(crtc);
13414                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13415         }
13416
13417         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13418                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13419
13420                 if (!pll->on || pll->active)
13421                         continue;
13422
13423                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13424
13425                 pll->disable(dev_priv, pll);
13426                 pll->on = false;
13427         }
13428
13429         if (IS_GEN9(dev))
13430                 skl_wm_get_hw_state(dev);
13431         else if (HAS_PCH_SPLIT(dev))
13432                 ilk_wm_get_hw_state(dev);
13433
13434         if (force_restore) {
13435                 i915_redisable_vga(dev);
13436
13437                 /*
13438                  * We need to use raw interfaces for restoring state to avoid
13439                  * checking (bogus) intermediate states.
13440                  */
13441                 for_each_pipe(dev_priv, pipe) {
13442                         struct drm_crtc *crtc =
13443                                 dev_priv->pipe_to_crtc_mapping[pipe];
13444
13445                         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13446                                        crtc->primary->fb);
13447                 }
13448         } else {
13449                 intel_modeset_update_staged_output_state(dev);
13450         }
13451
13452         intel_modeset_check_state(dev);
13453 }
13454
13455 void intel_modeset_gem_init(struct drm_device *dev)
13456 {
13457         struct drm_i915_private *dev_priv = dev->dev_private;
13458         struct drm_crtc *c;
13459         struct drm_i915_gem_object *obj;
13460
13461         mutex_lock(&dev->struct_mutex);
13462         intel_init_gt_powersave(dev);
13463         mutex_unlock(&dev->struct_mutex);
13464
13465         /*
13466          * There may be no VBT; and if the BIOS enabled SSC we can
13467          * just keep using it to avoid unnecessary flicker.  Whereas if the
13468          * BIOS isn't using it, don't assume it will work even if the VBT
13469          * indicates as much.
13470          */
13471         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13472                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13473                                                 DREF_SSC1_ENABLE);
13474
13475         intel_modeset_init_hw(dev);
13476
13477         intel_setup_overlay(dev);
13478
13479         /*
13480          * Make sure any fbs we allocated at startup are properly
13481          * pinned & fenced.  When we do the allocation it's too early
13482          * for this.
13483          */
13484         mutex_lock(&dev->struct_mutex);
13485         for_each_crtc(dev, c) {
13486                 obj = intel_fb_obj(c->primary->fb);
13487                 if (obj == NULL)
13488                         continue;
13489
13490                 if (intel_pin_and_fence_fb_obj(c->primary,
13491                                                c->primary->fb,
13492                                                NULL)) {
13493                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13494                                   to_intel_crtc(c)->pipe);
13495                         drm_framebuffer_unreference(c->primary->fb);
13496                         c->primary->fb = NULL;
13497                 }
13498         }
13499         mutex_unlock(&dev->struct_mutex);
13500
13501         intel_backlight_register(dev);
13502 }
13503
13504 void intel_connector_unregister(struct intel_connector *intel_connector)
13505 {
13506         struct drm_connector *connector = &intel_connector->base;
13507
13508         intel_panel_destroy_backlight(connector);
13509         drm_connector_unregister(connector);
13510 }
13511
13512 void intel_modeset_cleanup(struct drm_device *dev)
13513 {
13514         struct drm_i915_private *dev_priv = dev->dev_private;
13515         struct drm_connector *connector;
13516
13517         intel_disable_gt_powersave(dev);
13518
13519         intel_backlight_unregister(dev);
13520
13521         /*
13522          * Interrupts and polling as the first thing to avoid creating havoc.
13523          * Too much stuff here (turning of connectors, ...) would
13524          * experience fancy races otherwise.
13525          */
13526         intel_irq_uninstall(dev_priv);
13527
13528         /*
13529          * Due to the hpd irq storm handling the hotplug work can re-arm the
13530          * poll handlers. Hence disable polling after hpd handling is shut down.
13531          */
13532         drm_kms_helper_poll_fini(dev);
13533
13534         mutex_lock(&dev->struct_mutex);
13535
13536         intel_unregister_dsm_handler();
13537
13538         intel_disable_fbc(dev);
13539
13540         ironlake_teardown_rc6(dev);
13541
13542         mutex_unlock(&dev->struct_mutex);
13543
13544         /* flush any delayed tasks or pending work */
13545         flush_scheduled_work();
13546
13547         /* destroy the backlight and sysfs files before encoders/connectors */
13548         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13549                 struct intel_connector *intel_connector;
13550
13551                 intel_connector = to_intel_connector(connector);
13552                 intel_connector->unregister(intel_connector);
13553         }
13554
13555         drm_mode_config_cleanup(dev);
13556
13557         intel_cleanup_overlay(dev);
13558
13559         mutex_lock(&dev->struct_mutex);
13560         intel_cleanup_gt_powersave(dev);
13561         mutex_unlock(&dev->struct_mutex);
13562 }
13563
13564 /*
13565  * Return which encoder is currently attached for connector.
13566  */
13567 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13568 {
13569         return &intel_attached_encoder(connector)->base;
13570 }
13571
13572 void intel_connector_attach_encoder(struct intel_connector *connector,
13573                                     struct intel_encoder *encoder)
13574 {
13575         connector->encoder = encoder;
13576         drm_mode_connector_attach_encoder(&connector->base,
13577                                           &encoder->base);
13578 }
13579
13580 /*
13581  * set vga decode state - true == enable VGA decode
13582  */
13583 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13584 {
13585         struct drm_i915_private *dev_priv = dev->dev_private;
13586         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13587         u16 gmch_ctrl;
13588
13589         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13590                 DRM_ERROR("failed to read control word\n");
13591                 return -EIO;
13592         }
13593
13594         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13595                 return 0;
13596
13597         if (state)
13598                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13599         else
13600                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13601
13602         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13603                 DRM_ERROR("failed to write control word\n");
13604                 return -EIO;
13605         }
13606
13607         return 0;
13608 }
13609
13610 struct intel_display_error_state {
13611
13612         u32 power_well_driver;
13613
13614         int num_transcoders;
13615
13616         struct intel_cursor_error_state {
13617                 u32 control;
13618                 u32 position;
13619                 u32 base;
13620                 u32 size;
13621         } cursor[I915_MAX_PIPES];
13622
13623         struct intel_pipe_error_state {
13624                 bool power_domain_on;
13625                 u32 source;
13626                 u32 stat;
13627         } pipe[I915_MAX_PIPES];
13628
13629         struct intel_plane_error_state {
13630                 u32 control;
13631                 u32 stride;
13632                 u32 size;
13633                 u32 pos;
13634                 u32 addr;
13635                 u32 surface;
13636                 u32 tile_offset;
13637         } plane[I915_MAX_PIPES];
13638
13639         struct intel_transcoder_error_state {
13640                 bool power_domain_on;
13641                 enum transcoder cpu_transcoder;
13642
13643                 u32 conf;
13644
13645                 u32 htotal;
13646                 u32 hblank;
13647                 u32 hsync;
13648                 u32 vtotal;
13649                 u32 vblank;
13650                 u32 vsync;
13651         } transcoder[4];
13652 };
13653
13654 struct intel_display_error_state *
13655 intel_display_capture_error_state(struct drm_device *dev)
13656 {
13657         struct drm_i915_private *dev_priv = dev->dev_private;
13658         struct intel_display_error_state *error;
13659         int transcoders[] = {
13660                 TRANSCODER_A,
13661                 TRANSCODER_B,
13662                 TRANSCODER_C,
13663                 TRANSCODER_EDP,
13664         };
13665         int i;
13666
13667         if (INTEL_INFO(dev)->num_pipes == 0)
13668                 return NULL;
13669
13670         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13671         if (error == NULL)
13672                 return NULL;
13673
13674         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13675                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13676
13677         for_each_pipe(dev_priv, i) {
13678                 error->pipe[i].power_domain_on =
13679                         __intel_display_power_is_enabled(dev_priv,
13680                                                          POWER_DOMAIN_PIPE(i));
13681                 if (!error->pipe[i].power_domain_on)
13682                         continue;
13683
13684                 error->cursor[i].control = I915_READ(CURCNTR(i));
13685                 error->cursor[i].position = I915_READ(CURPOS(i));
13686                 error->cursor[i].base = I915_READ(CURBASE(i));
13687
13688                 error->plane[i].control = I915_READ(DSPCNTR(i));
13689                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13690                 if (INTEL_INFO(dev)->gen <= 3) {
13691                         error->plane[i].size = I915_READ(DSPSIZE(i));
13692                         error->plane[i].pos = I915_READ(DSPPOS(i));
13693                 }
13694                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13695                         error->plane[i].addr = I915_READ(DSPADDR(i));
13696                 if (INTEL_INFO(dev)->gen >= 4) {
13697                         error->plane[i].surface = I915_READ(DSPSURF(i));
13698                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13699                 }
13700
13701                 error->pipe[i].source = I915_READ(PIPESRC(i));
13702
13703                 if (HAS_GMCH_DISPLAY(dev))
13704                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13705         }
13706
13707         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13708         if (HAS_DDI(dev_priv->dev))
13709                 error->num_transcoders++; /* Account for eDP. */
13710
13711         for (i = 0; i < error->num_transcoders; i++) {
13712                 enum transcoder cpu_transcoder = transcoders[i];
13713
13714                 error->transcoder[i].power_domain_on =
13715                         __intel_display_power_is_enabled(dev_priv,
13716                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13717                 if (!error->transcoder[i].power_domain_on)
13718                         continue;
13719
13720                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13721
13722                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13723                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13724                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13725                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13726                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13727                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13728                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13729         }
13730
13731         return error;
13732 }
13733
13734 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13735
13736 void
13737 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13738                                 struct drm_device *dev,
13739                                 struct intel_display_error_state *error)
13740 {
13741         struct drm_i915_private *dev_priv = dev->dev_private;
13742         int i;
13743
13744         if (!error)
13745                 return;
13746
13747         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13748         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13749                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13750                            error->power_well_driver);
13751         for_each_pipe(dev_priv, i) {
13752                 err_printf(m, "Pipe [%d]:\n", i);
13753                 err_printf(m, "  Power: %s\n",
13754                            error->pipe[i].power_domain_on ? "on" : "off");
13755                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13756                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13757
13758                 err_printf(m, "Plane [%d]:\n", i);
13759                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13760                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13761                 if (INTEL_INFO(dev)->gen <= 3) {
13762                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13763                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13764                 }
13765                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13766                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13767                 if (INTEL_INFO(dev)->gen >= 4) {
13768                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13769                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13770                 }
13771
13772                 err_printf(m, "Cursor [%d]:\n", i);
13773                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13774                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13775                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13776         }
13777
13778         for (i = 0; i < error->num_transcoders; i++) {
13779                 err_printf(m, "CPU transcoder: %c\n",
13780                            transcoder_name(error->transcoder[i].cpu_transcoder));
13781                 err_printf(m, "  Power: %s\n",
13782                            error->transcoder[i].power_domain_on ? "on" : "off");
13783                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13784                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13785                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13786                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13787                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13788                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13789                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13790         }
13791 }
13792
13793 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13794 {
13795         struct intel_crtc *crtc;
13796
13797         for_each_intel_crtc(dev, crtc) {
13798                 struct intel_unpin_work *work;
13799
13800                 spin_lock_irq(&dev->event_lock);
13801
13802                 work = crtc->unpin_work;
13803
13804                 if (work && work->event &&
13805                     work->event->base.file_priv == file) {
13806                         kfree(work->event);
13807                         work->event = NULL;
13808                 }
13809
13810                 spin_unlock_irq(&dev->event_lock);
13811         }
13812 }