drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static inline u32 /* units of 100MHz */
 102 intel_fdi_link_freq(struct drm_device *dev)
 103 {
 104         if (IS_GEN5(dev)) {
 105                 struct drm_i915_private *dev_priv = dev->dev_private;
 106                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 107         } else
 108                 return 27;
 109 }
 110
 111 static const intel_limit_t intel_limits_i8xx_dvo = {
 112         .dot = { .min = 25000, .max = 350000 },
 113         .vco = { .min = 930000, .max = 1400000 },
 114         .n = { .min = 3, .max = 16 },
 115         .m = { .min = 96, .max = 140 },
 116         .m1 = { .min = 18, .max = 26 },
 117         .m2 = { .min = 6, .max = 16 },
 118         .p = { .min = 4, .max = 128 },
 119         .p1 = { .min = 2, .max = 33 },
 120         .p2 = { .dot_limit = 165000,
 121                 .p2_slow = 4, .p2_fast = 2 },
 122         .find_pll = intel_find_best_PLL,
 123 };
 124
 125 static const intel_limit_t intel_limits_i8xx_lvds = {
 126         .dot = { .min = 25000, .max = 350000 },
 127         .vco = { .min = 930000, .max = 1400000 },
 128         .n = { .min = 3, .max = 16 },
 129         .m = { .min = 96, .max = 140 },
 130         .m1 = { .min = 18, .max = 26 },
 131         .m2 = { .min = 6, .max = 16 },
 132         .p = { .min = 4, .max = 128 },
 133         .p1 = { .min = 1, .max = 6 },
 134         .p2 = { .dot_limit = 165000,
 135                 .p2_slow = 14, .p2_fast = 7 },
 136         .find_pll = intel_find_best_PLL,
 137 };
 138
 139 static const intel_limit_t intel_limits_i9xx_sdvo = {
 140         .dot = { .min = 20000, .max = 400000 },
 141         .vco = { .min = 1400000, .max = 2800000 },
 142         .n = { .min = 1, .max = 6 },
 143         .m = { .min = 70, .max = 120 },
 144         .m1 = { .min = 10, .max = 22 },
 145         .m2 = { .min = 5, .max = 9 },
 146         .p = { .min = 5, .max = 80 },
 147         .p1 = { .min = 1, .max = 8 },
 148         .p2 = { .dot_limit = 200000,
 149                 .p2_slow = 10, .p2_fast = 5 },
 150         .find_pll = intel_find_best_PLL,
 151 };
 152
 153 static const intel_limit_t intel_limits_i9xx_lvds = {
 154         .dot = { .min = 20000, .max = 400000 },
 155         .vco = { .min = 1400000, .max = 2800000 },
 156         .n = { .min = 1, .max = 6 },
 157         .m = { .min = 70, .max = 120 },
 158         .m1 = { .min = 10, .max = 22 },
 159         .m2 = { .min = 5, .max = 9 },
 160         .p = { .min = 7, .max = 98 },
 161         .p1 = { .min = 1, .max = 8 },
 162         .p2 = { .dot_limit = 112000,
 163                 .p2_slow = 14, .p2_fast = 7 },
 164         .find_pll = intel_find_best_PLL,
 165 };
 166
 167
 168 static const intel_limit_t intel_limits_g4x_sdvo = {
 169         .dot = { .min = 25000, .max = 270000 },
 170         .vco = { .min = 1750000, .max = 3500000},
 171         .n = { .min = 1, .max = 4 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 10, .max = 30 },
 176         .p1 = { .min = 1, .max = 3},
 177         .p2 = { .dot_limit = 270000,
 178                 .p2_slow = 10,
 179                 .p2_fast = 10
 180         },
 181         .find_pll = intel_g4x_find_best_PLL,
 182 };
 183
 184 static const intel_limit_t intel_limits_g4x_hdmi = {
 185         .dot = { .min = 22000, .max = 400000 },
 186         .vco = { .min = 1750000, .max = 3500000},
 187         .n = { .min = 1, .max = 4 },
 188         .m = { .min = 104, .max = 138 },
 189         .m1 = { .min = 16, .max = 23 },
 190         .m2 = { .min = 5, .max = 11 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8},
 193         .p2 = { .dot_limit = 165000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195         .find_pll = intel_g4x_find_best_PLL,
 196 };
 197
 198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 199         .dot = { .min = 20000, .max = 115000 },
 200         .vco = { .min = 1750000, .max = 3500000 },
 201         .n = { .min = 1, .max = 3 },
 202         .m = { .min = 104, .max = 138 },
 203         .m1 = { .min = 17, .max = 23 },
 204         .m2 = { .min = 5, .max = 11 },
 205         .p = { .min = 28, .max = 112 },
 206         .p1 = { .min = 2, .max = 8 },
 207         .p2 = { .dot_limit = 0,
 208                 .p2_slow = 14, .p2_fast = 14
 209         },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 214         .dot = { .min = 80000, .max = 224000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 14, .max = 42 },
 221         .p1 = { .min = 2, .max = 6 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 7, .p2_fast = 7
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_display_port = {
 229         .dot = { .min = 161670, .max = 227000 },
 230         .vco = { .min = 1750000, .max = 3500000},
 231         .n = { .min = 1, .max = 2 },
 232         .m = { .min = 97, .max = 108 },
 233         .m1 = { .min = 0x10, .max = 0x12 },
 234         .m2 = { .min = 0x05, .max = 0x06 },
 235         .p = { .min = 10, .max = 20 },
 236         .p1 = { .min = 1, .max = 2},
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 10, .p2_fast = 10 },
 239         .find_pll = intel_find_pll_g4x_dp,
 240 };
 241
 242 static const intel_limit_t intel_limits_pineview_sdvo = {
 243         .dot = { .min = 20000, .max = 400000},
 244         .vco = { .min = 1700000, .max = 3500000 },
 245         /* Pineview's Ncounter is a ring counter */
 246         .n = { .min = 3, .max = 6 },
 247         .m = { .min = 2, .max = 256 },
 248         /* Pineview only has one combined m divider, which we treat as m2. */
 249         .m1 = { .min = 0, .max = 0 },
 250         .m2 = { .min = 0, .max = 254 },
 251         .p = { .min = 5, .max = 80 },
 252         .p1 = { .min = 1, .max = 8 },
 253         .p2 = { .dot_limit = 200000,
 254                 .p2_slow = 10, .p2_fast = 5 },
 255         .find_pll = intel_find_best_PLL,
 256 };
 257
 258 static const intel_limit_t intel_limits_pineview_lvds = {
 259         .dot = { .min = 20000, .max = 400000 },
 260         .vco = { .min = 1700000, .max = 3500000 },
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         .m1 = { .min = 0, .max = 0 },
 264         .m2 = { .min = 0, .max = 254 },
 265         .p = { .min = 7, .max = 112 },
 266         .p1 = { .min = 1, .max = 8 },
 267         .p2 = { .dot_limit = 112000,
 268                 .p2_slow = 14, .p2_fast = 14 },
 269         .find_pll = intel_find_best_PLL,
 270 };
 271
 272 /* Ironlake / Sandybridge
 273  *
 274  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 275  * the range value for them is (actual_value - 2).
 276  */
 277 static const intel_limit_t intel_limits_ironlake_dac = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 1760000, .max = 3510000 },
 280         .n = { .min = 1, .max = 5 },
 281         .m = { .min = 79, .max = 127 },
 282         .m1 = { .min = 12, .max = 22 },
 283         .m2 = { .min = 5, .max = 9 },
 284         .p = { .min = 5, .max = 80 },
 285         .p1 = { .min = 1, .max = 8 },
 286         .p2 = { .dot_limit = 225000,
 287                 .p2_slow = 10, .p2_fast = 5 },
 288         .find_pll = intel_g4x_find_best_PLL,
 289 };
 290
 291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 292         .dot = { .min = 25000, .max = 350000 },
 293         .vco = { .min = 1760000, .max = 3510000 },
 294         .n = { .min = 1, .max = 3 },
 295         .m = { .min = 79, .max = 118 },
 296         .m1 = { .min = 12, .max = 22 },
 297         .m2 = { .min = 5, .max = 9 },
 298         .p = { .min = 28, .max = 112 },
 299         .p1 = { .min = 2, .max = 8 },
 300         .p2 = { .dot_limit = 225000,
 301                 .p2_slow = 14, .p2_fast = 14 },
 302         .find_pll = intel_g4x_find_best_PLL,
 303 };
 304
 305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 3 },
 309         .m = { .min = 79, .max = 127 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 14, .max = 56 },
 313         .p1 = { .min = 2, .max = 8 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 7, .p2_fast = 7 },
 316         .find_pll = intel_g4x_find_best_PLL,
 317 };
 318
 319 /* LVDS 100mhz refclk limits. */
 320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 2 },
 324         .m = { .min = 79, .max = 126 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 14, .p2_fast = 14 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 335         .dot = { .min = 25000, .max = 350000 },
 336         .vco = { .min = 1760000, .max = 3510000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 79, .max = 126 },
 339         .m1 = { .min = 12, .max = 22 },
 340         .m2 = { .min = 5, .max = 9 },
 341         .p = { .min = 14, .max = 42 },
 342         .p1 = { .min = 2, .max = 6 },
 343         .p2 = { .dot_limit = 225000,
 344                 .p2_slow = 7, .p2_fast = 7 },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 static const intel_limit_t intel_limits_ironlake_display_port = {
 349         .dot = { .min = 25000, .max = 350000 },
 350         .vco = { .min = 1760000, .max = 3510000},
 351         .n = { .min = 1, .max = 2 },
 352         .m = { .min = 81, .max = 90 },
 353         .m1 = { .min = 12, .max = 22 },
 354         .m2 = { .min = 5, .max = 9 },
 355         .p = { .min = 10, .max = 20 },
 356         .p1 = { .min = 1, .max = 2},
 357         .p2 = { .dot_limit = 0,
 358                 .p2_slow = 10, .p2_fast = 10 },
 359         .find_pll = intel_find_pll_ironlake_dp,
 360 };
 361
 362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 363 {
 364         unsigned long flags;
 365         u32 val = 0;
 366
 367         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 368         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 369                 DRM_ERROR("DPIO idle wait timed out\n");
 370                 goto out_unlock;
 371         }
 372
 373         I915_WRITE(DPIO_REG, reg);
 374         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 375                    DPIO_BYTE);
 376         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 377                 DRM_ERROR("DPIO read wait timed out\n");
 378                 goto out_unlock;
 379         }
 380         val = I915_READ(DPIO_DATA);
 381
 382 out_unlock:
 383         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 384         return val;
 385 }
 386
 387 static void vlv_init_dpio(struct drm_device *dev)
 388 {
 389         struct drm_i915_private *dev_priv = dev->dev_private;
 390
 391         /* Reset the DPIO config */
 392         I915_WRITE(DPIO_CTL, 0);
 393         POSTING_READ(DPIO_CTL);
 394         I915_WRITE(DPIO_CTL, 1);
 395         POSTING_READ(DPIO_CTL);
 396 }
 397
 398 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 399 {
 400         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 401         return 1;
 402 }
 403
 404 static const struct dmi_system_id intel_dual_link_lvds[] = {
 405         {
 406                 .callback = intel_dual_link_lvds_callback,
 407                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 408                 .matches = {
 409                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 410                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 411                 },
 412         },
 413         { }     /* terminating entry */
 414 };
 415
 416 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 417                               unsigned int reg)
 418 {
 419         unsigned int val;
 420
 421         /* use the module option value if specified */
 422         if (i915_lvds_channel_mode > 0)
 423                 return i915_lvds_channel_mode == 2;
 424
 425         if (dmi_check_system(intel_dual_link_lvds))
 426                 return true;
 427
 428         if (dev_priv->lvds_val)
 429                 val = dev_priv->lvds_val;
 430         else {
 431                 /* BIOS should set the proper LVDS register value at boot, but
 432                  * in reality, it doesn't set the value when the lid is closed;
 433                  * we need to check "the value to be set" in VBT when LVDS
 434                  * register is uninitialized.
 435                  */
 436                 val = I915_READ(reg);
 437                 if (!(val & ~LVDS_DETECTED))
 438                         val = dev_priv->bios_lvds_val;
 439                 dev_priv->lvds_val = val;
 440         }
 441         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 442 }
 443
 444 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 445                                                 int refclk)
 446 {
 447         struct drm_device *dev = crtc->dev;
 448         struct drm_i915_private *dev_priv = dev->dev_private;
 449         const intel_limit_t *limit;
 450
 451         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 452                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 453                         /* LVDS dual channel */
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_dual_lvds;
 458                 } else {
 459                         if (refclk == 100000)
 460                                 limit = &intel_limits_ironlake_single_lvds_100m;
 461                         else
 462                                 limit = &intel_limits_ironlake_single_lvds;
 463                 }
 464         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 465                         HAS_eDP)
 466                 limit = &intel_limits_ironlake_display_port;
 467         else
 468                 limit = &intel_limits_ironlake_dac;
 469
 470         return limit;
 471 }
 472
 473 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 474 {
 475         struct drm_device *dev = crtc->dev;
 476         struct drm_i915_private *dev_priv = dev->dev_private;
 477         const intel_limit_t *limit;
 478
 479         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 480                 if (is_dual_link_lvds(dev_priv, LVDS))
 481                         /* LVDS with dual channel */
 482                         limit = &intel_limits_g4x_dual_channel_lvds;
 483                 else
 484                         /* LVDS with dual channel */
 485                         limit = &intel_limits_g4x_single_channel_lvds;
 486         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 487                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 488                 limit = &intel_limits_g4x_hdmi;
 489         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 490                 limit = &intel_limits_g4x_sdvo;
 491         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 492                 limit = &intel_limits_g4x_display_port;
 493         } else /* The option is for other outputs */
 494                 limit = &intel_limits_i9xx_sdvo;
 495
 496         return limit;
 497 }
 498
 499 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 500 {
 501         struct drm_device *dev = crtc->dev;
 502         const intel_limit_t *limit;
 503
 504         if (HAS_PCH_SPLIT(dev))
 505                 limit = intel_ironlake_limit(crtc, refclk);
 506         else if (IS_G4X(dev)) {
 507                 limit = intel_g4x_limit(crtc);
 508         } else if (IS_PINEVIEW(dev)) {
 509                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 510                         limit = &intel_limits_pineview_lvds;
 511                 else
 512                         limit = &intel_limits_pineview_sdvo;
 513         } else if (!IS_GEN2(dev)) {
 514                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 515                         limit = &intel_limits_i9xx_lvds;
 516                 else
 517                         limit = &intel_limits_i9xx_sdvo;
 518         } else {
 519                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 520                         limit = &intel_limits_i8xx_lvds;
 521                 else
 522                         limit = &intel_limits_i8xx_dvo;
 523         }
 524         return limit;
 525 }
 526
 527 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 528 static void pineview_clock(int refclk, intel_clock_t *clock)
 529 {
 530         clock->m = clock->m2 + 2;
 531         clock->p = clock->p1 * clock->p2;
 532         clock->vco = refclk * clock->m / clock->n;
 533         clock->dot = clock->vco / clock->p;
 534 }
 535
 536 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 537 {
 538         if (IS_PINEVIEW(dev)) {
 539                 pineview_clock(refclk, clock);
 540                 return;
 541         }
 542         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 543         clock->p = clock->p1 * clock->p2;
 544         clock->vco = refclk * clock->m / (clock->n + 2);
 545         clock->dot = clock->vco / clock->p;
 546 }
 547
 548 /**
 549  * Returns whether any output on the specified pipe is of the specified type
 550  */
 551 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 552 {
 553         struct drm_device *dev = crtc->dev;
 554         struct drm_mode_config *mode_config = &dev->mode_config;
 555         struct intel_encoder *encoder;
 556
 557         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 558                 if (encoder->base.crtc == crtc && encoder->type == type)
 559                         return true;
 560
 561         return false;
 562 }
 563
 564 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 565 /**
 566  * Returns whether the given set of divisors are valid for a given refclk with
 567  * the given connectors.
 568  */
 569
 570 static bool intel_PLL_is_valid(struct drm_device *dev,
 571                                const intel_limit_t *limit,
 572                                const intel_clock_t *clock)
 573 {
 574         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 575                 INTELPllInvalid("p1 out of range\n");
 576         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 577                 INTELPllInvalid("p out of range\n");
 578         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 579                 INTELPllInvalid("m2 out of range\n");
 580         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 581                 INTELPllInvalid("m1 out of range\n");
 582         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 583                 INTELPllInvalid("m1 <= m2\n");
 584         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 585                 INTELPllInvalid("m out of range\n");
 586         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 587                 INTELPllInvalid("n out of range\n");
 588         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 589                 INTELPllInvalid("vco out of range\n");
 590         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 591          * connector, etc., rather than just a single range.
 592          */
 593         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 594                 INTELPllInvalid("dot out of range\n");
 595
 596         return true;
 597 }
 598
 599 static bool
 600 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 601                     int target, int refclk, intel_clock_t *match_clock,
 602                     intel_clock_t *best_clock)
 603
 604 {
 605         struct drm_device *dev = crtc->dev;
 606         struct drm_i915_private *dev_priv = dev->dev_private;
 607         intel_clock_t clock;
 608         int err = target;
 609
 610         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 611             (I915_READ(LVDS)) != 0) {
 612                 /*
 613                  * For LVDS, if the panel is on, just rely on its current
 614                  * settings for dual-channel.  We haven't figured out how to
 615                  * reliably set up different single/dual channel state, if we
 616                  * even can.
 617                  */
 618                 if (is_dual_link_lvds(dev_priv, LVDS))
 619                         clock.p2 = limit->p2.p2_fast;
 620                 else
 621                         clock.p2 = limit->p2.p2_slow;
 622         } else {
 623                 if (target < limit->p2.dot_limit)
 624                         clock.p2 = limit->p2.p2_slow;
 625                 else
 626                         clock.p2 = limit->p2.p2_fast;
 627         }
 628
 629         memset(best_clock, 0, sizeof(*best_clock));
 630
 631         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 632              clock.m1++) {
 633                 for (clock.m2 = limit->m2.min;
 634                      clock.m2 <= limit->m2.max; clock.m2++) {
 635                         /* m1 is always 0 in Pineview */
 636                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 637                                 break;
 638                         for (clock.n = limit->n.min;
 639                              clock.n <= limit->n.max; clock.n++) {
 640                                 for (clock.p1 = limit->p1.min;
 641                                         clock.p1 <= limit->p1.max; clock.p1++) {
 642                                         int this_err;
 643
 644                                         intel_clock(dev, refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648                                         if (match_clock &&
 649                                             clock.p != match_clock->p)
 650                                                 continue;
 651
 652                                         this_err = abs(clock.dot - target);
 653                                         if (this_err < err) {
 654                                                 *best_clock = clock;
 655                                                 err = this_err;
 656                                         }
 657                                 }
 658                         }
 659                 }
 660         }
 661
 662         return (err != target);
 663 }
 664
 665 static bool
 666 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 667                         int target, int refclk, intel_clock_t *match_clock,
 668                         intel_clock_t *best_clock)
 669 {
 670         struct drm_device *dev = crtc->dev;
 671         struct drm_i915_private *dev_priv = dev->dev_private;
 672         intel_clock_t clock;
 673         int max_n;
 674         bool found;
 675         /* approximately equals target * 0.00585 */
 676         int err_most = (target >> 8) + (target >> 9);
 677         found = false;
 678
 679         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 680                 int lvds_reg;
 681
 682                 if (HAS_PCH_SPLIT(dev))
 683                         lvds_reg = PCH_LVDS;
 684                 else
 685                         lvds_reg = LVDS;
 686                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 687                     LVDS_CLKB_POWER_UP)
 688                         clock.p2 = limit->p2.p2_fast;
 689                 else
 690                         clock.p2 = limit->p2.p2_slow;
 691         } else {
 692                 if (target < limit->p2.dot_limit)
 693                         clock.p2 = limit->p2.p2_slow;
 694                 else
 695                         clock.p2 = limit->p2.p2_fast;
 696         }
 697
 698         memset(best_clock, 0, sizeof(*best_clock));
 699         max_n = limit->n.max;
 700         /* based on hardware requirement, prefer smaller n to precision */
 701         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 702                 /* based on hardware requirement, prefere larger m1,m2 */
 703                 for (clock.m1 = limit->m1.max;
 704                      clock.m1 >= limit->m1.min; clock.m1--) {
 705                         for (clock.m2 = limit->m2.max;
 706                              clock.m2 >= limit->m2.min; clock.m2--) {
 707                                 for (clock.p1 = limit->p1.max;
 708                                      clock.p1 >= limit->p1.min; clock.p1--) {
 709                                         int this_err;
 710
 711                                         intel_clock(dev, refclk, &clock);
 712                                         if (!intel_PLL_is_valid(dev, limit,
 713                                                                 &clock))
 714                                                 continue;
 715                                         if (match_clock &&
 716                                             clock.p != match_clock->p)
 717                                                 continue;
 718
 719                                         this_err = abs(clock.dot - target);
 720                                         if (this_err < err_most) {
 721                                                 *best_clock = clock;
 722                                                 err_most = this_err;
 723                                                 max_n = clock.n;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730         return found;
 731 }
 732
 733 static bool
 734 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 735                            int target, int refclk, intel_clock_t *match_clock,
 736                            intel_clock_t *best_clock)
 737 {
 738         struct drm_device *dev = crtc->dev;
 739         intel_clock_t clock;
 740
 741         if (target < 200000) {
 742                 clock.n = 1;
 743                 clock.p1 = 2;
 744                 clock.p2 = 10;
 745                 clock.m1 = 12;
 746                 clock.m2 = 9;
 747         } else {
 748                 clock.n = 2;
 749                 clock.p1 = 1;
 750                 clock.p2 = 10;
 751                 clock.m1 = 14;
 752                 clock.m2 = 8;
 753         }
 754         intel_clock(dev, refclk, &clock);
 755         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 756         return true;
 757 }
 758
 759 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 760 static bool
 761 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 762                       int target, int refclk, intel_clock_t *match_clock,
 763                       intel_clock_t *best_clock)
 764 {
 765         intel_clock_t clock;
 766         if (target < 200000) {
 767                 clock.p1 = 2;
 768                 clock.p2 = 10;
 769                 clock.n = 2;
 770                 clock.m1 = 23;
 771                 clock.m2 = 8;
 772         } else {
 773                 clock.p1 = 1;
 774                 clock.p2 = 10;
 775                 clock.n = 1;
 776                 clock.m1 = 14;
 777                 clock.m2 = 2;
 778         }
 779         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 780         clock.p = (clock.p1 * clock.p2);
 781         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 782         clock.vco = 0;
 783         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 784         return true;
 785 }
 786
 787 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 788 {
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790         u32 frame, frame_reg = PIPEFRAME(pipe);
 791
 792         frame = I915_READ(frame_reg);
 793
 794         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 795                 DRM_DEBUG_KMS("vblank wait timed out\n");
 796 }
 797
 798 /**
 799  * intel_wait_for_vblank - wait for vblank on a given pipe
 800  * @dev: drm device
 801  * @pipe: pipe to wait for
 802  *
 803  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 804  * mode setting code.
 805  */
 806 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 807 {
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         int pipestat_reg = PIPESTAT(pipe);
 810
 811         if (INTEL_INFO(dev)->gen >= 5) {
 812                 ironlake_wait_for_vblank(dev, pipe);
 813                 return;
 814         }
 815
 816         /* Clear existing vblank status. Note this will clear any other
 817          * sticky status fields as well.
 818          *
 819          * This races with i915_driver_irq_handler() with the result
 820          * that either function could miss a vblank event.  Here it is not
 821          * fatal, as we will either wait upon the next vblank interrupt or
 822          * timeout.  Generally speaking intel_wait_for_vblank() is only
 823          * called during modeset at which time the GPU should be idle and
 824          * should *not* be performing page flips and thus not waiting on
 825          * vblanks...
 826          * Currently, the result of us stealing a vblank from the irq
 827          * handler is that a single frame will be skipped during swapbuffers.
 828          */
 829         I915_WRITE(pipestat_reg,
 830                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 831
 832         /* Wait for vblank interrupt bit to set */
 833         if (wait_for(I915_READ(pipestat_reg) &
 834                      PIPE_VBLANK_INTERRUPT_STATUS,
 835                      50))
 836                 DRM_DEBUG_KMS("vblank wait timed out\n");
 837 }
 838
 839 /*
 840  * intel_wait_for_pipe_off - wait for pipe to turn off
 841  * @dev: drm device
 842  * @pipe: pipe to wait for
 843  *
 844  * After disabling a pipe, we can't wait for vblank in the usual way,
 845  * spinning on the vblank interrupt status bit, since we won't actually
 846  * see an interrupt when the pipe is disabled.
 847  *
 848  * On Gen4 and above:
 849  *   wait for the pipe register state bit to turn off
 850  *
 851  * Otherwise:
 852  *   wait for the display line value to settle (it usually
 853  *   ends up stopping at the start of the next frame).
 854  *
 855  */
 856 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 857 {
 858         struct drm_i915_private *dev_priv = dev->dev_private;
 859
 860         if (INTEL_INFO(dev)->gen >= 4) {
 861                 int reg = PIPECONF(pipe);
 862
 863                 /* Wait for the Pipe State to go off */
 864                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 865                              100))
 866                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 867         } else {
 868                 u32 last_line, line_mask;
 869                 int reg = PIPEDSL(pipe);
 870                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 871
 872                 if (IS_GEN2(dev))
 873                         line_mask = DSL_LINEMASK_GEN2;
 874                 else
 875                         line_mask = DSL_LINEMASK_GEN3;
 876
 877                 /* Wait for the display line to settle */
 878                 do {
 879                         last_line = I915_READ(reg) & line_mask;
 880                         mdelay(5);
 881                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 882                          time_after(timeout, jiffies));
 883                 if (time_after(jiffies, timeout))
 884                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 885         }
 886 }
 887
 888 static const char *state_string(bool enabled)
 889 {
 890         return enabled ? "on" : "off";
 891 }
 892
 893 /* Only for pre-ILK configs */
 894 static void assert_pll(struct drm_i915_private *dev_priv,
 895                        enum pipe pipe, bool state)
 896 {
 897         int reg;
 898         u32 val;
 899         bool cur_state;
 900
 901         reg = DPLL(pipe);
 902         val = I915_READ(reg);
 903         cur_state = !!(val & DPLL_VCO_ENABLE);
 904         WARN(cur_state != state,
 905              "PLL state assertion failure (expected %s, current %s)\n",
 906              state_string(state), state_string(cur_state));
 907 }
 908 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 909 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 910
 911 /* For ILK+ */
 912 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 913                            struct intel_crtc *intel_crtc, bool state)
 914 {
 915         int reg;
 916         u32 val;
 917         bool cur_state;
 918
 919         if (HAS_PCH_LPT(dev_priv->dev)) {
 920                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 921                 return;
 922         }
 923
 924         if (!intel_crtc->pch_pll) {
 925                 WARN(1, "asserting PCH PLL enabled with no PLL\n");
 926                 return;
 927         }
 928
 929         if (HAS_PCH_CPT(dev_priv->dev)) {
 930                 u32 pch_dpll;
 931
 932                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 933
 934                 /* Make sure the selected PLL is enabled to the transcoder */
 935                 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
 936                      "transcoder %d PLL not enabled\n", intel_crtc->pipe);
 937         }
 938
 939         reg = intel_crtc->pch_pll->pll_reg;
 940         val = I915_READ(reg);
 941         cur_state = !!(val & DPLL_VCO_ENABLE);
 942         WARN(cur_state != state,
 943              "PCH PLL state assertion failure (expected %s, current %s)\n",
 944              state_string(state), state_string(cur_state));
 945 }
 946 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 947 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 948
 949 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 950                           enum pipe pipe, bool state)
 951 {
 952         int reg;
 953         u32 val;
 954         bool cur_state;
 955
 956         if (IS_HASWELL(dev_priv->dev)) {
 957                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
 958                 reg = DDI_FUNC_CTL(pipe);
 959                 val = I915_READ(reg);
 960                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
 961         } else {
 962                 reg = FDI_TX_CTL(pipe);
 963                 val = I915_READ(reg);
 964                 cur_state = !!(val & FDI_TX_ENABLE);
 965         }
 966         WARN(cur_state != state,
 967              "FDI TX state assertion failure (expected %s, current %s)\n",
 968              state_string(state), state_string(cur_state));
 969 }
 970 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 971 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 972
 973 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 974                           enum pipe pipe, bool state)
 975 {
 976         int reg;
 977         u32 val;
 978         bool cur_state;
 979
 980         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
 981                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
 982                         return;
 983         } else {
 984                 reg = FDI_RX_CTL(pipe);
 985                 val = I915_READ(reg);
 986                 cur_state = !!(val & FDI_RX_ENABLE);
 987         }
 988         WARN(cur_state != state,
 989              "FDI RX state assertion failure (expected %s, current %s)\n",
 990              state_string(state), state_string(cur_state));
 991 }
 992 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 993 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 994
 995 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 996                                       enum pipe pipe)
 997 {
 998         int reg;
 999         u32 val;
1000
1001         /* ILK FDI PLL is always enabled */
1002         if (dev_priv->info->gen == 5)
1003                 return;
1004
1005         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1006         if (IS_HASWELL(dev_priv->dev))
1007                 return;
1008
1009         reg = FDI_TX_CTL(pipe);
1010         val = I915_READ(reg);
1011         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1012 }
1013
1014 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1015                                       enum pipe pipe)
1016 {
1017         int reg;
1018         u32 val;
1019
1020         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1021                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1022                 return;
1023         }
1024         reg = FDI_RX_CTL(pipe);
1025         val = I915_READ(reg);
1026         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1027 }
1028
1029 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1030                                   enum pipe pipe)
1031 {
1032         int pp_reg, lvds_reg;
1033         u32 val;
1034         enum pipe panel_pipe = PIPE_A;
1035         bool locked = true;
1036
1037         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1038                 pp_reg = PCH_PP_CONTROL;
1039                 lvds_reg = PCH_LVDS;
1040         } else {
1041                 pp_reg = PP_CONTROL;
1042                 lvds_reg = LVDS;
1043         }
1044
1045         val = I915_READ(pp_reg);
1046         if (!(val & PANEL_POWER_ON) ||
1047             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1048                 locked = false;
1049
1050         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1051                 panel_pipe = PIPE_B;
1052
1053         WARN(panel_pipe == pipe && locked,
1054              "panel assertion failure, pipe %c regs locked\n",
1055              pipe_name(pipe));
1056 }
1057
1058 void assert_pipe(struct drm_i915_private *dev_priv,
1059                  enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         /* if we need the pipe A quirk it must be always on */
1066         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1067                 state = true;
1068
1069         reg = PIPECONF(pipe);
1070         val = I915_READ(reg);
1071         cur_state = !!(val & PIPECONF_ENABLE);
1072         WARN(cur_state != state,
1073              "pipe %c assertion failure (expected %s, current %s)\n",
1074              pipe_name(pipe), state_string(state), state_string(cur_state));
1075 }
1076
1077 static void assert_plane(struct drm_i915_private *dev_priv,
1078                          enum plane plane, bool state)
1079 {
1080         int reg;
1081         u32 val;
1082         bool cur_state;
1083
1084         reg = DSPCNTR(plane);
1085         val = I915_READ(reg);
1086         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087         WARN(cur_state != state,
1088              "plane %c assertion failure (expected %s, current %s)\n",
1089              plane_name(plane), state_string(state), state_string(cur_state));
1090 }
1091
1092 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
1095 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096                                    enum pipe pipe)
1097 {
1098         int reg, i;
1099         u32 val;
1100         int cur_pipe;
1101
1102         /* Planes are fixed to pipes on ILK+ */
1103         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1104                 reg = DSPCNTR(pipe);
1105                 val = I915_READ(reg);
1106                 WARN((val & DISPLAY_PLANE_ENABLE),
1107                      "plane %c assertion failure, should be disabled but not\n",
1108                      plane_name(pipe));
1109                 return;
1110         }
1111
1112         /* Need to check both planes against the pipe */
1113         for (i = 0; i < 2; i++) {
1114                 reg = DSPCNTR(i);
1115                 val = I915_READ(reg);
1116                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1117                         DISPPLANE_SEL_PIPE_SHIFT;
1118                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1119                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1120                      plane_name(i), pipe_name(pipe));
1121         }
1122 }
1123
1124 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1125 {
1126         u32 val;
1127         bool enabled;
1128
1129         if (HAS_PCH_LPT(dev_priv->dev)) {
1130                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1131                 return;
1132         }
1133
1134         val = I915_READ(PCH_DREF_CONTROL);
1135         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1136                             DREF_SUPERSPREAD_SOURCE_MASK));
1137         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1138 }
1139
1140 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1141                                        enum pipe pipe)
1142 {
1143         int reg;
1144         u32 val;
1145         bool enabled;
1146
1147         reg = TRANSCONF(pipe);
1148         val = I915_READ(reg);
1149         enabled = !!(val & TRANS_ENABLE);
1150         WARN(enabled,
1151              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1152              pipe_name(pipe));
1153 }
1154
1155 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1156                             enum pipe pipe, u32 port_sel, u32 val)
1157 {
1158         if ((val & DP_PORT_EN) == 0)
1159                 return false;
1160
1161         if (HAS_PCH_CPT(dev_priv->dev)) {
1162                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1163                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1164                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1165                         return false;
1166         } else {
1167                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1168                         return false;
1169         }
1170         return true;
1171 }
1172
1173 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1174                               enum pipe pipe, u32 val)
1175 {
1176         if ((val & PORT_ENABLE) == 0)
1177                 return false;
1178
1179         if (HAS_PCH_CPT(dev_priv->dev)) {
1180                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1181                         return false;
1182         } else {
1183                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1184                         return false;
1185         }
1186         return true;
1187 }
1188
1189 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1190                               enum pipe pipe, u32 val)
1191 {
1192         if ((val & LVDS_PORT_EN) == 0)
1193                 return false;
1194
1195         if (HAS_PCH_CPT(dev_priv->dev)) {
1196                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1197                         return false;
1198         } else {
1199                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1200                         return false;
1201         }
1202         return true;
1203 }
1204
1205 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1206                               enum pipe pipe, u32 val)
1207 {
1208         if ((val & ADPA_DAC_ENABLE) == 0)
1209                 return false;
1210         if (HAS_PCH_CPT(dev_priv->dev)) {
1211                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1212                         return false;
1213         } else {
1214                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1215                         return false;
1216         }
1217         return true;
1218 }
1219
1220 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1221                                    enum pipe pipe, int reg, u32 port_sel)
1222 {
1223         u32 val = I915_READ(reg);
1224         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1225              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1226              reg, pipe_name(pipe));
1227 }
1228
1229 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1230                                      enum pipe pipe, int reg)
1231 {
1232         u32 val = I915_READ(reg);
1233         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1234              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1235              reg, pipe_name(pipe));
1236 }
1237
1238 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1239                                       enum pipe pipe)
1240 {
1241         int reg;
1242         u32 val;
1243
1244         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1245         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1246         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1247
1248         reg = PCH_ADPA;
1249         val = I915_READ(reg);
1250         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1251              "PCH VGA enabled on transcoder %c, should be disabled\n",
1252              pipe_name(pipe));
1253
1254         reg = PCH_LVDS;
1255         val = I915_READ(reg);
1256         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1257              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1258              pipe_name(pipe));
1259
1260         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1261         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1262         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1263 }
1264
1265 /**
1266  * intel_enable_pll - enable a PLL
1267  * @dev_priv: i915 private structure
1268  * @pipe: pipe PLL to enable
1269  *
1270  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1271  * make sure the PLL reg is writable first though, since the panel write
1272  * protect mechanism may be enabled.
1273  *
1274  * Note!  This is for pre-ILK only.
1275  */
1276 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1277 {
1278         int reg;
1279         u32 val;
1280
1281         /* No really, not for ILK+ */
1282         BUG_ON(dev_priv->info->gen >= 5);
1283
1284         /* PLL is protected by panel, make sure we can write it */
1285         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1286                 assert_panel_unlocked(dev_priv, pipe);
1287
1288         reg = DPLL(pipe);
1289         val = I915_READ(reg);
1290         val |= DPLL_VCO_ENABLE;
1291
1292         /* We do this three times for luck */
1293         I915_WRITE(reg, val);
1294         POSTING_READ(reg);
1295         udelay(150); /* wait for warmup */
1296         I915_WRITE(reg, val);
1297         POSTING_READ(reg);
1298         udelay(150); /* wait for warmup */
1299         I915_WRITE(reg, val);
1300         POSTING_READ(reg);
1301         udelay(150); /* wait for warmup */
1302 }
1303
1304 /**
1305  * intel_disable_pll - disable a PLL
1306  * @dev_priv: i915 private structure
1307  * @pipe: pipe PLL to disable
1308  *
1309  * Disable the PLL for @pipe, making sure the pipe is off first.
1310  *
1311  * Note!  This is for pre-ILK only.
1312  */
1313 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1314 {
1315         int reg;
1316         u32 val;
1317
1318         /* Don't disable pipe A or pipe A PLLs if needed */
1319         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1320                 return;
1321
1322         /* Make sure the pipe isn't still relying on us */
1323         assert_pipe_disabled(dev_priv, pipe);
1324
1325         reg = DPLL(pipe);
1326         val = I915_READ(reg);
1327         val &= ~DPLL_VCO_ENABLE;
1328         I915_WRITE(reg, val);
1329         POSTING_READ(reg);
1330 }
1331
1332 /* SBI access */
1333 static void
1334 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1335 {
1336         unsigned long flags;
1337
1338         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1339         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1340                                 100)) {
1341                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1342                 goto out_unlock;
1343         }
1344
1345         I915_WRITE(SBI_ADDR,
1346                         (reg << 16));
1347         I915_WRITE(SBI_DATA,
1348                         value);
1349         I915_WRITE(SBI_CTL_STAT,
1350                         SBI_BUSY |
1351                         SBI_CTL_OP_CRWR);
1352
1353         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1354                                 100)) {
1355                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1356                 goto out_unlock;
1357         }
1358
1359 out_unlock:
1360         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1361 }
1362
1363 static u32
1364 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1365 {
1366         unsigned long flags;
1367         u32 value;
1368
1369         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1370         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1371                                 100)) {
1372                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1373                 goto out_unlock;
1374         }
1375
1376         I915_WRITE(SBI_ADDR,
1377                         (reg << 16));
1378         I915_WRITE(SBI_CTL_STAT,
1379                         SBI_BUSY |
1380                         SBI_CTL_OP_CRRD);
1381
1382         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1383                                 100)) {
1384                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1385                 goto out_unlock;
1386         }
1387
1388         value = I915_READ(SBI_DATA);
1389
1390 out_unlock:
1391         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1392         return value;
1393 }
1394
1395 /**
1396  * intel_enable_pch_pll - enable PCH PLL
1397  * @dev_priv: i915 private structure
1398  * @pipe: pipe PLL to enable
1399  *
1400  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1401  * drives the transcoder clock.
1402  */
1403 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1404 {
1405         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1406         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1407         int reg;
1408         u32 val;
1409
1410         /* PCH only available on ILK+ */
1411         BUG_ON(dev_priv->info->gen < 5);
1412         BUG_ON(pll == NULL);
1413         BUG_ON(pll->refcount == 0);
1414
1415         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1416                       pll->pll_reg, pll->active, pll->on,
1417                       intel_crtc->base.base.id);
1418
1419         /* PCH refclock must be enabled first */
1420         assert_pch_refclk_enabled(dev_priv);
1421
1422         if (pll->active++ && pll->on) {
1423                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1424                 return;
1425         }
1426
1427         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1428
1429         reg = pll->pll_reg;
1430         val = I915_READ(reg);
1431         val |= DPLL_VCO_ENABLE;
1432         I915_WRITE(reg, val);
1433         POSTING_READ(reg);
1434         udelay(200);
1435
1436         pll->on = true;
1437 }
1438
1439 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1440 {
1441         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1442         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1443         int reg;
1444         u32 val;
1445
1446         /* PCH only available on ILK+ */
1447         BUG_ON(dev_priv->info->gen < 5);
1448         if (pll == NULL)
1449                return;
1450
1451         BUG_ON(pll->refcount == 0);
1452
1453         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1454                       pll->pll_reg, pll->active, pll->on,
1455                       intel_crtc->base.base.id);
1456
1457         BUG_ON(pll->active == 0);
1458         if (--pll->active) {
1459                 assert_pch_pll_enabled(dev_priv, intel_crtc);
1460                 return;
1461         }
1462
1463         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1464
1465         /* Make sure transcoder isn't still depending on us */
1466         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1467
1468         reg = pll->pll_reg;
1469         val = I915_READ(reg);
1470         val &= ~DPLL_VCO_ENABLE;
1471         I915_WRITE(reg, val);
1472         POSTING_READ(reg);
1473         udelay(200);
1474
1475         pll->on = false;
1476 }
1477
1478 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1479                                     enum pipe pipe)
1480 {
1481         int reg;
1482         u32 val, pipeconf_val;
1483         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1484
1485         /* PCH only available on ILK+ */
1486         BUG_ON(dev_priv->info->gen < 5);
1487
1488         /* Make sure PCH DPLL is enabled */
1489         assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
1490
1491         /* FDI must be feeding us bits for PCH ports */
1492         assert_fdi_tx_enabled(dev_priv, pipe);
1493         assert_fdi_rx_enabled(dev_priv, pipe);
1494
1495         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1496                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1497                 return;
1498         }
1499         reg = TRANSCONF(pipe);
1500         val = I915_READ(reg);
1501         pipeconf_val = I915_READ(PIPECONF(pipe));
1502
1503         if (HAS_PCH_IBX(dev_priv->dev)) {
1504                 /*
1505                  * make the BPC in transcoder be consistent with
1506                  * that in pipeconf reg.
1507                  */
1508                 val &= ~PIPE_BPC_MASK;
1509                 val |= pipeconf_val & PIPE_BPC_MASK;
1510         }
1511
1512         val &= ~TRANS_INTERLACE_MASK;
1513         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1514                 if (HAS_PCH_IBX(dev_priv->dev) &&
1515                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1516                         val |= TRANS_LEGACY_INTERLACED_ILK;
1517                 else
1518                         val |= TRANS_INTERLACED;
1519         else
1520                 val |= TRANS_PROGRESSIVE;
1521
1522         I915_WRITE(reg, val | TRANS_ENABLE);
1523         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1524                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1525 }
1526
1527 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1528                                      enum pipe pipe)
1529 {
1530         int reg;
1531         u32 val;
1532
1533         /* FDI relies on the transcoder */
1534         assert_fdi_tx_disabled(dev_priv, pipe);
1535         assert_fdi_rx_disabled(dev_priv, pipe);
1536
1537         /* Ports must be off as well */
1538         assert_pch_ports_disabled(dev_priv, pipe);
1539
1540         reg = TRANSCONF(pipe);
1541         val = I915_READ(reg);
1542         val &= ~TRANS_ENABLE;
1543         I915_WRITE(reg, val);
1544         /* wait for PCH transcoder off, transcoder state */
1545         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1546                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1547 }
1548
1549 /**
1550  * intel_enable_pipe - enable a pipe, asserting requirements
1551  * @dev_priv: i915 private structure
1552  * @pipe: pipe to enable
1553  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1554  *
1555  * Enable @pipe, making sure that various hardware specific requirements
1556  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1557  *
1558  * @pipe should be %PIPE_A or %PIPE_B.
1559  *
1560  * Will wait until the pipe is actually running (i.e. first vblank) before
1561  * returning.
1562  */
1563 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1564                               bool pch_port)
1565 {
1566         int reg;
1567         u32 val;
1568
1569         /*
1570          * A pipe without a PLL won't actually be able to drive bits from
1571          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1572          * need the check.
1573          */
1574         if (!HAS_PCH_SPLIT(dev_priv->dev))
1575                 assert_pll_enabled(dev_priv, pipe);
1576         else {
1577                 if (pch_port) {
1578                         /* if driving the PCH, we need FDI enabled */
1579                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1580                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1581                 }
1582                 /* FIXME: assert CPU port conditions for SNB+ */
1583         }
1584
1585         reg = PIPECONF(pipe);
1586         val = I915_READ(reg);
1587         if (val & PIPECONF_ENABLE)
1588                 return;
1589
1590         I915_WRITE(reg, val | PIPECONF_ENABLE);
1591         intel_wait_for_vblank(dev_priv->dev, pipe);
1592 }
1593
1594 /**
1595  * intel_disable_pipe - disable a pipe, asserting requirements
1596  * @dev_priv: i915 private structure
1597  * @pipe: pipe to disable
1598  *
1599  * Disable @pipe, making sure that various hardware specific requirements
1600  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1601  *
1602  * @pipe should be %PIPE_A or %PIPE_B.
1603  *
1604  * Will wait until the pipe has shut down before returning.
1605  */
1606 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1607                                enum pipe pipe)
1608 {
1609         int reg;
1610         u32 val;
1611
1612         /*
1613          * Make sure planes won't keep trying to pump pixels to us,
1614          * or we might hang the display.
1615          */
1616         assert_planes_disabled(dev_priv, pipe);
1617
1618         /* Don't disable pipe A or pipe A PLLs if needed */
1619         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1620                 return;
1621
1622         reg = PIPECONF(pipe);
1623         val = I915_READ(reg);
1624         if ((val & PIPECONF_ENABLE) == 0)
1625                 return;
1626
1627         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1628         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1629 }
1630
1631 /*
1632  * Plane regs are double buffered, going from enabled->disabled needs a
1633  * trigger in order to latch.  The display address reg provides this.
1634  */
1635 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1636                                       enum plane plane)
1637 {
1638         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1639         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1640 }
1641
1642 /**
1643  * intel_enable_plane - enable a display plane on a given pipe
1644  * @dev_priv: i915 private structure
1645  * @plane: plane to enable
1646  * @pipe: pipe being fed
1647  *
1648  * Enable @plane on @pipe, making sure that @pipe is running first.
1649  */
1650 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1651                                enum plane plane, enum pipe pipe)
1652 {
1653         int reg;
1654         u32 val;
1655
1656         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1657         assert_pipe_enabled(dev_priv, pipe);
1658
1659         reg = DSPCNTR(plane);
1660         val = I915_READ(reg);
1661         if (val & DISPLAY_PLANE_ENABLE)
1662                 return;
1663
1664         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1665         intel_flush_display_plane(dev_priv, plane);
1666         intel_wait_for_vblank(dev_priv->dev, pipe);
1667 }
1668
1669 /**
1670  * intel_disable_plane - disable a display plane
1671  * @dev_priv: i915 private structure
1672  * @plane: plane to disable
1673  * @pipe: pipe consuming the data
1674  *
1675  * Disable @plane; should be an independent operation.
1676  */
1677 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1678                                 enum plane plane, enum pipe pipe)
1679 {
1680         int reg;
1681         u32 val;
1682
1683         reg = DSPCNTR(plane);
1684         val = I915_READ(reg);
1685         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1686                 return;
1687
1688         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1689         intel_flush_display_plane(dev_priv, plane);
1690         intel_wait_for_vblank(dev_priv->dev, pipe);
1691 }
1692
1693 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1694                            enum pipe pipe, int reg, u32 port_sel)
1695 {
1696         u32 val = I915_READ(reg);
1697         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1698                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1699                 I915_WRITE(reg, val & ~DP_PORT_EN);
1700         }
1701 }
1702
1703 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1704                              enum pipe pipe, int reg)
1705 {
1706         u32 val = I915_READ(reg);
1707         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1708                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1709                               reg, pipe);
1710                 I915_WRITE(reg, val & ~PORT_ENABLE);
1711         }
1712 }
1713
1714 /* Disable any ports connected to this transcoder */
1715 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1716                                     enum pipe pipe)
1717 {
1718         u32 reg, val;
1719
1720         val = I915_READ(PCH_PP_CONTROL);
1721         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1722
1723         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1724         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1725         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1726
1727         reg = PCH_ADPA;
1728         val = I915_READ(reg);
1729         if (adpa_pipe_enabled(dev_priv, val, pipe))
1730                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1731
1732         reg = PCH_LVDS;
1733         val = I915_READ(reg);
1734         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1735                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1736                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1737                 POSTING_READ(reg);
1738                 udelay(100);
1739         }
1740
1741         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1742         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1743         disable_pch_hdmi(dev_priv, pipe, HDMID);
1744 }
1745
1746 int
1747 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1748                            struct drm_i915_gem_object *obj,
1749                            struct intel_ring_buffer *pipelined)
1750 {
1751         struct drm_i915_private *dev_priv = dev->dev_private;
1752         u32 alignment;
1753         int ret;
1754
1755         switch (obj->tiling_mode) {
1756         case I915_TILING_NONE:
1757                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1758                         alignment = 128 * 1024;
1759                 else if (INTEL_INFO(dev)->gen >= 4)
1760                         alignment = 4 * 1024;
1761                 else
1762                         alignment = 64 * 1024;
1763                 break;
1764         case I915_TILING_X:
1765                 /* pin() will align the object as required by fence */
1766                 alignment = 0;
1767                 break;
1768         case I915_TILING_Y:
1769                 /* FIXME: Is this true? */
1770                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1771                 return -EINVAL;
1772         default:
1773                 BUG();
1774         }
1775
1776         dev_priv->mm.interruptible = false;
1777         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1778         if (ret)
1779                 goto err_interruptible;
1780
1781         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1782          * fence, whereas 965+ only requires a fence if using
1783          * framebuffer compression.  For simplicity, we always install
1784          * a fence as the cost is not that onerous.
1785          */
1786         ret = i915_gem_object_get_fence(obj);
1787         if (ret)
1788                 goto err_unpin;
1789
1790         i915_gem_object_pin_fence(obj);
1791
1792         dev_priv->mm.interruptible = true;
1793         return 0;
1794
1795 err_unpin:
1796         i915_gem_object_unpin(obj);
1797 err_interruptible:
1798         dev_priv->mm.interruptible = true;
1799         return ret;
1800 }
1801
1802 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1803 {
1804         i915_gem_object_unpin_fence(obj);
1805         i915_gem_object_unpin(obj);
1806 }
1807
1808 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1809                              int x, int y)
1810 {
1811         struct drm_device *dev = crtc->dev;
1812         struct drm_i915_private *dev_priv = dev->dev_private;
1813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1814         struct intel_framebuffer *intel_fb;
1815         struct drm_i915_gem_object *obj;
1816         int plane = intel_crtc->plane;
1817         unsigned long Start, Offset;
1818         u32 dspcntr;
1819         u32 reg;
1820
1821         switch (plane) {
1822         case 0:
1823         case 1:
1824                 break;
1825         default:
1826                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1827                 return -EINVAL;
1828         }
1829
1830         intel_fb = to_intel_framebuffer(fb);
1831         obj = intel_fb->obj;
1832
1833         reg = DSPCNTR(plane);
1834         dspcntr = I915_READ(reg);
1835         /* Mask out pixel format bits in case we change it */
1836         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1837         switch (fb->bits_per_pixel) {
1838         case 8:
1839                 dspcntr |= DISPPLANE_8BPP;
1840                 break;
1841         case 16:
1842                 if (fb->depth == 15)
1843                         dspcntr |= DISPPLANE_15_16BPP;
1844                 else
1845                         dspcntr |= DISPPLANE_16BPP;
1846                 break;
1847         case 24:
1848         case 32:
1849                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1850                 break;
1851         default:
1852                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1853                 return -EINVAL;
1854         }
1855         if (INTEL_INFO(dev)->gen >= 4) {
1856                 if (obj->tiling_mode != I915_TILING_NONE)
1857                         dspcntr |= DISPPLANE_TILED;
1858                 else
1859                         dspcntr &= ~DISPPLANE_TILED;
1860         }
1861
1862         I915_WRITE(reg, dspcntr);
1863
1864         Start = obj->gtt_offset;
1865         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1866
1867         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1868                       Start, Offset, x, y, fb->pitches[0]);
1869         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1870         if (INTEL_INFO(dev)->gen >= 4) {
1871                 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1872                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1873                 I915_WRITE(DSPADDR(plane), Offset);
1874         } else
1875                 I915_WRITE(DSPADDR(plane), Start + Offset);
1876         POSTING_READ(reg);
1877
1878         return 0;
1879 }
1880
1881 static int ironlake_update_plane(struct drm_crtc *crtc,
1882                                  struct drm_framebuffer *fb, int x, int y)
1883 {
1884         struct drm_device *dev = crtc->dev;
1885         struct drm_i915_private *dev_priv = dev->dev_private;
1886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1887         struct intel_framebuffer *intel_fb;
1888         struct drm_i915_gem_object *obj;
1889         int plane = intel_crtc->plane;
1890         unsigned long Start, Offset;
1891         u32 dspcntr;
1892         u32 reg;
1893
1894         switch (plane) {
1895         case 0:
1896         case 1:
1897         case 2:
1898                 break;
1899         default:
1900                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1901                 return -EINVAL;
1902         }
1903
1904         intel_fb = to_intel_framebuffer(fb);
1905         obj = intel_fb->obj;
1906
1907         reg = DSPCNTR(plane);
1908         dspcntr = I915_READ(reg);
1909         /* Mask out pixel format bits in case we change it */
1910         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1911         switch (fb->bits_per_pixel) {
1912         case 8:
1913                 dspcntr |= DISPPLANE_8BPP;
1914                 break;
1915         case 16:
1916                 if (fb->depth != 16)
1917                         return -EINVAL;
1918
1919                 dspcntr |= DISPPLANE_16BPP;
1920                 break;
1921         case 24:
1922         case 32:
1923                 if (fb->depth == 24)
1924                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1925                 else if (fb->depth == 30)
1926                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1927                 else
1928                         return -EINVAL;
1929                 break;
1930         default:
1931                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1932                 return -EINVAL;
1933         }
1934
1935         if (obj->tiling_mode != I915_TILING_NONE)
1936                 dspcntr |= DISPPLANE_TILED;
1937         else
1938                 dspcntr &= ~DISPPLANE_TILED;
1939
1940         /* must disable */
1941         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1942
1943         I915_WRITE(reg, dspcntr);
1944
1945         Start = obj->gtt_offset;
1946         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1947
1948         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1949                       Start, Offset, x, y, fb->pitches[0]);
1950         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1951         I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1952         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1953         I915_WRITE(DSPADDR(plane), Offset);
1954         POSTING_READ(reg);
1955
1956         return 0;
1957 }
1958
1959 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1960 static int
1961 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1962                            int x, int y, enum mode_set_atomic state)
1963 {
1964         struct drm_device *dev = crtc->dev;
1965         struct drm_i915_private *dev_priv = dev->dev_private;
1966
1967         if (dev_priv->display.disable_fbc)
1968                 dev_priv->display.disable_fbc(dev);
1969         intel_increase_pllclock(crtc);
1970
1971         return dev_priv->display.update_plane(crtc, fb, x, y);
1972 }
1973
1974 static int
1975 intel_finish_fb(struct drm_framebuffer *old_fb)
1976 {
1977         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1978         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1979         bool was_interruptible = dev_priv->mm.interruptible;
1980         int ret;
1981
1982         wait_event(dev_priv->pending_flip_queue,
1983                    atomic_read(&dev_priv->mm.wedged) ||
1984                    atomic_read(&obj->pending_flip) == 0);
1985
1986         /* Big Hammer, we also need to ensure that any pending
1987          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1988          * current scanout is retired before unpinning the old
1989          * framebuffer.
1990          *
1991          * This should only fail upon a hung GPU, in which case we
1992          * can safely continue.
1993          */
1994         dev_priv->mm.interruptible = false;
1995         ret = i915_gem_object_finish_gpu(obj);
1996         dev_priv->mm.interruptible = was_interruptible;
1997
1998         return ret;
1999 }
2000
2001 static int
2002 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2003                     struct drm_framebuffer *old_fb)
2004 {
2005         struct drm_device *dev = crtc->dev;
2006         struct drm_i915_private *dev_priv = dev->dev_private;
2007         struct drm_i915_master_private *master_priv;
2008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2009         int ret;
2010
2011         /* no fb bound */
2012         if (!crtc->fb) {
2013                 DRM_ERROR("No FB bound\n");
2014                 return 0;
2015         }
2016
2017         if(intel_crtc->plane > dev_priv->num_pipe) {
2018                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2019                                 intel_crtc->plane,
2020                                 dev_priv->num_pipe);
2021                 return -EINVAL;
2022         }
2023
2024         mutex_lock(&dev->struct_mutex);
2025         ret = intel_pin_and_fence_fb_obj(dev,
2026                                          to_intel_framebuffer(crtc->fb)->obj,
2027                                          NULL);
2028         if (ret != 0) {
2029                 mutex_unlock(&dev->struct_mutex);
2030                 DRM_ERROR("pin & fence failed\n");
2031                 return ret;
2032         }
2033
2034         if (old_fb)
2035                 intel_finish_fb(old_fb);
2036
2037         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2038         if (ret) {
2039                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2040                 mutex_unlock(&dev->struct_mutex);
2041                 DRM_ERROR("failed to update base address\n");
2042                 return ret;
2043         }
2044
2045         if (old_fb) {
2046                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2047                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2048         }
2049
2050         intel_update_fbc(dev);
2051         mutex_unlock(&dev->struct_mutex);
2052
2053         if (!dev->primary->master)
2054                 return 0;
2055
2056         master_priv = dev->primary->master->driver_priv;
2057         if (!master_priv->sarea_priv)
2058                 return 0;
2059
2060         if (intel_crtc->pipe) {
2061                 master_priv->sarea_priv->pipeB_x = x;
2062                 master_priv->sarea_priv->pipeB_y = y;
2063         } else {
2064                 master_priv->sarea_priv->pipeA_x = x;
2065                 master_priv->sarea_priv->pipeA_y = y;
2066         }
2067
2068         return 0;
2069 }
2070
2071 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2072 {
2073         struct drm_device *dev = crtc->dev;
2074         struct drm_i915_private *dev_priv = dev->dev_private;
2075         u32 dpa_ctl;
2076
2077         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2078         dpa_ctl = I915_READ(DP_A);
2079         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2080
2081         if (clock < 200000) {
2082                 u32 temp;
2083                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2084                 /* workaround for 160Mhz:
2085                    1) program 0x4600c bits 15:0 = 0x8124
2086                    2) program 0x46010 bit 0 = 1
2087                    3) program 0x46034 bit 24 = 1
2088                    4) program 0x64000 bit 14 = 1
2089                    */
2090                 temp = I915_READ(0x4600c);
2091                 temp &= 0xffff0000;
2092                 I915_WRITE(0x4600c, temp | 0x8124);
2093
2094                 temp = I915_READ(0x46010);
2095                 I915_WRITE(0x46010, temp | 1);
2096
2097                 temp = I915_READ(0x46034);
2098                 I915_WRITE(0x46034, temp | (1 << 24));
2099         } else {
2100                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2101         }
2102         I915_WRITE(DP_A, dpa_ctl);
2103
2104         POSTING_READ(DP_A);
2105         udelay(500);
2106 }
2107
2108 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2109 {
2110         struct drm_device *dev = crtc->dev;
2111         struct drm_i915_private *dev_priv = dev->dev_private;
2112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2113         int pipe = intel_crtc->pipe;
2114         u32 reg, temp;
2115
2116         /* enable normal train */
2117         reg = FDI_TX_CTL(pipe);
2118         temp = I915_READ(reg);
2119         if (IS_IVYBRIDGE(dev)) {
2120                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2121                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2122         } else {
2123                 temp &= ~FDI_LINK_TRAIN_NONE;
2124                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2125         }
2126         I915_WRITE(reg, temp);
2127
2128         reg = FDI_RX_CTL(pipe);
2129         temp = I915_READ(reg);
2130         if (HAS_PCH_CPT(dev)) {
2131                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2132                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2133         } else {
2134                 temp &= ~FDI_LINK_TRAIN_NONE;
2135                 temp |= FDI_LINK_TRAIN_NONE;
2136         }
2137         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2138
2139         /* wait one idle pattern time */
2140         POSTING_READ(reg);
2141         udelay(1000);
2142
2143         /* IVB wants error correction enabled */
2144         if (IS_IVYBRIDGE(dev))
2145                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2146                            FDI_FE_ERRC_ENABLE);
2147 }
2148
2149 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2150 {
2151         struct drm_i915_private *dev_priv = dev->dev_private;
2152         u32 flags = I915_READ(SOUTH_CHICKEN1);
2153
2154         flags |= FDI_PHASE_SYNC_OVR(pipe);
2155         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2156         flags |= FDI_PHASE_SYNC_EN(pipe);
2157         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2158         POSTING_READ(SOUTH_CHICKEN1);
2159 }
2160
2161 /* The FDI link training functions for ILK/Ibexpeak. */
2162 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = crtc->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167         int pipe = intel_crtc->pipe;
2168         int plane = intel_crtc->plane;
2169         u32 reg, temp, tries;
2170
2171         /* FDI needs bits from pipe & plane first */
2172         assert_pipe_enabled(dev_priv, pipe);
2173         assert_plane_enabled(dev_priv, plane);
2174
2175         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2176            for train result */
2177         reg = FDI_RX_IMR(pipe);
2178         temp = I915_READ(reg);
2179         temp &= ~FDI_RX_SYMBOL_LOCK;
2180         temp &= ~FDI_RX_BIT_LOCK;
2181         I915_WRITE(reg, temp);
2182         I915_READ(reg);
2183         udelay(150);
2184
2185         /* enable CPU FDI TX and PCH FDI RX */
2186         reg = FDI_TX_CTL(pipe);
2187         temp = I915_READ(reg);
2188         temp &= ~(7 << 19);
2189         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2190         temp &= ~FDI_LINK_TRAIN_NONE;
2191         temp |= FDI_LINK_TRAIN_PATTERN_1;
2192         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2193
2194         reg = FDI_RX_CTL(pipe);
2195         temp = I915_READ(reg);
2196         temp &= ~FDI_LINK_TRAIN_NONE;
2197         temp |= FDI_LINK_TRAIN_PATTERN_1;
2198         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2199
2200         POSTING_READ(reg);
2201         udelay(150);
2202
2203         /* Ironlake workaround, enable clock pointer after FDI enable*/
2204         if (HAS_PCH_IBX(dev)) {
2205                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2206                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2207                            FDI_RX_PHASE_SYNC_POINTER_EN);
2208         }
2209
2210         reg = FDI_RX_IIR(pipe);
2211         for (tries = 0; tries < 5; tries++) {
2212                 temp = I915_READ(reg);
2213                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2214
2215                 if ((temp & FDI_RX_BIT_LOCK)) {
2216                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2217                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2218                         break;
2219                 }
2220         }
2221         if (tries == 5)
2222                 DRM_ERROR("FDI train 1 fail!\n");
2223
2224         /* Train 2 */
2225         reg = FDI_TX_CTL(pipe);
2226         temp = I915_READ(reg);
2227         temp &= ~FDI_LINK_TRAIN_NONE;
2228         temp |= FDI_LINK_TRAIN_PATTERN_2;
2229         I915_WRITE(reg, temp);
2230
2231         reg = FDI_RX_CTL(pipe);
2232         temp = I915_READ(reg);
2233         temp &= ~FDI_LINK_TRAIN_NONE;
2234         temp |= FDI_LINK_TRAIN_PATTERN_2;
2235         I915_WRITE(reg, temp);
2236
2237         POSTING_READ(reg);
2238         udelay(150);
2239
2240         reg = FDI_RX_IIR(pipe);
2241         for (tries = 0; tries < 5; tries++) {
2242                 temp = I915_READ(reg);
2243                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2244
2245                 if (temp & FDI_RX_SYMBOL_LOCK) {
2246                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2247                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2248                         break;
2249                 }
2250         }
2251         if (tries == 5)
2252                 DRM_ERROR("FDI train 2 fail!\n");
2253
2254         DRM_DEBUG_KMS("FDI train done\n");
2255
2256 }
2257
2258 static const int snb_b_fdi_train_param[] = {
2259         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2260         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2261         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2262         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2263 };
2264
2265 /* The FDI link training functions for SNB/Cougarpoint. */
2266 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2267 {
2268         struct drm_device *dev = crtc->dev;
2269         struct drm_i915_private *dev_priv = dev->dev_private;
2270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271         int pipe = intel_crtc->pipe;
2272         u32 reg, temp, i, retry;
2273
2274         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2275            for train result */
2276         reg = FDI_RX_IMR(pipe);
2277         temp = I915_READ(reg);
2278         temp &= ~FDI_RX_SYMBOL_LOCK;
2279         temp &= ~FDI_RX_BIT_LOCK;
2280         I915_WRITE(reg, temp);
2281
2282         POSTING_READ(reg);
2283         udelay(150);
2284
2285         /* enable CPU FDI TX and PCH FDI RX */
2286         reg = FDI_TX_CTL(pipe);
2287         temp = I915_READ(reg);
2288         temp &= ~(7 << 19);
2289         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2290         temp &= ~FDI_LINK_TRAIN_NONE;
2291         temp |= FDI_LINK_TRAIN_PATTERN_1;
2292         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2293         /* SNB-B */
2294         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2295         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2296
2297         reg = FDI_RX_CTL(pipe);
2298         temp = I915_READ(reg);
2299         if (HAS_PCH_CPT(dev)) {
2300                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2301                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2302         } else {
2303                 temp &= ~FDI_LINK_TRAIN_NONE;
2304                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2305         }
2306         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2307
2308         POSTING_READ(reg);
2309         udelay(150);
2310
2311         if (HAS_PCH_CPT(dev))
2312                 cpt_phase_pointer_enable(dev, pipe);
2313
2314         for (i = 0; i < 4; i++) {
2315                 reg = FDI_TX_CTL(pipe);
2316                 temp = I915_READ(reg);
2317                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2318                 temp |= snb_b_fdi_train_param[i];
2319                 I915_WRITE(reg, temp);
2320
2321                 POSTING_READ(reg);
2322                 udelay(500);
2323
2324                 for (retry = 0; retry < 5; retry++) {
2325                         reg = FDI_RX_IIR(pipe);
2326                         temp = I915_READ(reg);
2327                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2328                         if (temp & FDI_RX_BIT_LOCK) {
2329                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2330                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2331                                 break;
2332                         }
2333                         udelay(50);
2334                 }
2335                 if (retry < 5)
2336                         break;
2337         }
2338         if (i == 4)
2339                 DRM_ERROR("FDI train 1 fail!\n");
2340
2341         /* Train 2 */
2342         reg = FDI_TX_CTL(pipe);
2343         temp = I915_READ(reg);
2344         temp &= ~FDI_LINK_TRAIN_NONE;
2345         temp |= FDI_LINK_TRAIN_PATTERN_2;
2346         if (IS_GEN6(dev)) {
2347                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2348                 /* SNB-B */
2349                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2350         }
2351         I915_WRITE(reg, temp);
2352
2353         reg = FDI_RX_CTL(pipe);
2354         temp = I915_READ(reg);
2355         if (HAS_PCH_CPT(dev)) {
2356                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2357                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2358         } else {
2359                 temp &= ~FDI_LINK_TRAIN_NONE;
2360                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2361         }
2362         I915_WRITE(reg, temp);
2363
2364         POSTING_READ(reg);
2365         udelay(150);
2366
2367         for (i = 0; i < 4; i++) {
2368                 reg = FDI_TX_CTL(pipe);
2369                 temp = I915_READ(reg);
2370                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2371                 temp |= snb_b_fdi_train_param[i];
2372                 I915_WRITE(reg, temp);
2373
2374                 POSTING_READ(reg);
2375                 udelay(500);
2376
2377                 for (retry = 0; retry < 5; retry++) {
2378                         reg = FDI_RX_IIR(pipe);
2379                         temp = I915_READ(reg);
2380                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2381                         if (temp & FDI_RX_SYMBOL_LOCK) {
2382                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2383                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2384                                 break;
2385                         }
2386                         udelay(50);
2387                 }
2388                 if (retry < 5)
2389                         break;
2390         }
2391         if (i == 4)
2392                 DRM_ERROR("FDI train 2 fail!\n");
2393
2394         DRM_DEBUG_KMS("FDI train done.\n");
2395 }
2396
2397 /* Manual link training for Ivy Bridge A0 parts */
2398 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2399 {
2400         struct drm_device *dev = crtc->dev;
2401         struct drm_i915_private *dev_priv = dev->dev_private;
2402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403         int pipe = intel_crtc->pipe;
2404         u32 reg, temp, i;
2405
2406         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2407            for train result */
2408         reg = FDI_RX_IMR(pipe);
2409         temp = I915_READ(reg);
2410         temp &= ~FDI_RX_SYMBOL_LOCK;
2411         temp &= ~FDI_RX_BIT_LOCK;
2412         I915_WRITE(reg, temp);
2413
2414         POSTING_READ(reg);
2415         udelay(150);
2416
2417         /* enable CPU FDI TX and PCH FDI RX */
2418         reg = FDI_TX_CTL(pipe);
2419         temp = I915_READ(reg);
2420         temp &= ~(7 << 19);
2421         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2422         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2423         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2424         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2425         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2426         temp |= FDI_COMPOSITE_SYNC;
2427         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2428
2429         reg = FDI_RX_CTL(pipe);
2430         temp = I915_READ(reg);
2431         temp &= ~FDI_LINK_TRAIN_AUTO;
2432         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2433         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2434         temp |= FDI_COMPOSITE_SYNC;
2435         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2436
2437         POSTING_READ(reg);
2438         udelay(150);
2439
2440         if (HAS_PCH_CPT(dev))
2441                 cpt_phase_pointer_enable(dev, pipe);
2442
2443         for (i = 0; i < 4; i++) {
2444                 reg = FDI_TX_CTL(pipe);
2445                 temp = I915_READ(reg);
2446                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2447                 temp |= snb_b_fdi_train_param[i];
2448                 I915_WRITE(reg, temp);
2449
2450                 POSTING_READ(reg);
2451                 udelay(500);
2452
2453                 reg = FDI_RX_IIR(pipe);
2454                 temp = I915_READ(reg);
2455                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2456
2457                 if (temp & FDI_RX_BIT_LOCK ||
2458                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2459                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2460                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2461                         break;
2462                 }
2463         }
2464         if (i == 4)
2465                 DRM_ERROR("FDI train 1 fail!\n");
2466
2467         /* Train 2 */
2468         reg = FDI_TX_CTL(pipe);
2469         temp = I915_READ(reg);
2470         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2471         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2472         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2473         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2474         I915_WRITE(reg, temp);
2475
2476         reg = FDI_RX_CTL(pipe);
2477         temp = I915_READ(reg);
2478         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2480         I915_WRITE(reg, temp);
2481
2482         POSTING_READ(reg);
2483         udelay(150);
2484
2485         for (i = 0; i < 4; i++) {
2486                 reg = FDI_TX_CTL(pipe);
2487                 temp = I915_READ(reg);
2488                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2489                 temp |= snb_b_fdi_train_param[i];
2490                 I915_WRITE(reg, temp);
2491
2492                 POSTING_READ(reg);
2493                 udelay(500);
2494
2495                 reg = FDI_RX_IIR(pipe);
2496                 temp = I915_READ(reg);
2497                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2498
2499                 if (temp & FDI_RX_SYMBOL_LOCK) {
2500                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2501                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2502                         break;
2503                 }
2504         }
2505         if (i == 4)
2506                 DRM_ERROR("FDI train 2 fail!\n");
2507
2508         DRM_DEBUG_KMS("FDI train done.\n");
2509 }
2510
2511 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2512 {
2513         struct drm_device *dev = crtc->dev;
2514         struct drm_i915_private *dev_priv = dev->dev_private;
2515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516         int pipe = intel_crtc->pipe;
2517         u32 reg, temp;
2518
2519         /* Write the TU size bits so error detection works */
2520         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2521                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2522
2523         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2524         reg = FDI_RX_CTL(pipe);
2525         temp = I915_READ(reg);
2526         temp &= ~((0x7 << 19) | (0x7 << 16));
2527         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2528         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2529         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2530
2531         POSTING_READ(reg);
2532         udelay(200);
2533
2534         /* Switch from Rawclk to PCDclk */
2535         temp = I915_READ(reg);
2536         I915_WRITE(reg, temp | FDI_PCDCLK);
2537
2538         POSTING_READ(reg);
2539         udelay(200);
2540
2541         /* On Haswell, the PLL configuration for ports and pipes is handled
2542          * separately, as part of DDI setup */
2543         if (!IS_HASWELL(dev)) {
2544                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2545                 reg = FDI_TX_CTL(pipe);
2546                 temp = I915_READ(reg);
2547                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2548                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2549
2550                         POSTING_READ(reg);
2551                         udelay(100);
2552                 }
2553         }
2554 }
2555
2556 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2557 {
2558         struct drm_i915_private *dev_priv = dev->dev_private;
2559         u32 flags = I915_READ(SOUTH_CHICKEN1);
2560
2561         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2562         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2563         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2564         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2565         POSTING_READ(SOUTH_CHICKEN1);
2566 }
2567 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2568 {
2569         struct drm_device *dev = crtc->dev;
2570         struct drm_i915_private *dev_priv = dev->dev_private;
2571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2572         int pipe = intel_crtc->pipe;
2573         u32 reg, temp;
2574
2575         /* disable CPU FDI tx and PCH FDI rx */
2576         reg = FDI_TX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2579         POSTING_READ(reg);
2580
2581         reg = FDI_RX_CTL(pipe);
2582         temp = I915_READ(reg);
2583         temp &= ~(0x7 << 16);
2584         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2585         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2586
2587         POSTING_READ(reg);
2588         udelay(100);
2589
2590         /* Ironlake workaround, disable clock pointer after downing FDI */
2591         if (HAS_PCH_IBX(dev)) {
2592                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2593                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2594                            I915_READ(FDI_RX_CHICKEN(pipe) &
2595                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2596         } else if (HAS_PCH_CPT(dev)) {
2597                 cpt_phase_pointer_disable(dev, pipe);
2598         }
2599
2600         /* still set train pattern 1 */
2601         reg = FDI_TX_CTL(pipe);
2602         temp = I915_READ(reg);
2603         temp &= ~FDI_LINK_TRAIN_NONE;
2604         temp |= FDI_LINK_TRAIN_PATTERN_1;
2605         I915_WRITE(reg, temp);
2606
2607         reg = FDI_RX_CTL(pipe);
2608         temp = I915_READ(reg);
2609         if (HAS_PCH_CPT(dev)) {
2610                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2611                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2612         } else {
2613                 temp &= ~FDI_LINK_TRAIN_NONE;
2614                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2615         }
2616         /* BPC in FDI rx is consistent with that in PIPECONF */
2617         temp &= ~(0x07 << 16);
2618         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2619         I915_WRITE(reg, temp);
2620
2621         POSTING_READ(reg);
2622         udelay(100);
2623 }
2624
2625 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2626 {
2627         struct drm_device *dev = crtc->dev;
2628
2629         if (crtc->fb == NULL)
2630                 return;
2631
2632         mutex_lock(&dev->struct_mutex);
2633         intel_finish_fb(crtc->fb);
2634         mutex_unlock(&dev->struct_mutex);
2635 }
2636
2637 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2638 {
2639         struct drm_device *dev = crtc->dev;
2640         struct drm_mode_config *mode_config = &dev->mode_config;
2641         struct intel_encoder *encoder;
2642
2643         /*
2644          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2645          * must be driven by its own crtc; no sharing is possible.
2646          */
2647         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2648                 if (encoder->base.crtc != crtc)
2649                         continue;
2650
2651                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2652                  * CPU handles all others */
2653                 if (IS_HASWELL(dev)) {
2654                         /* It is still unclear how this will work on PPT, so throw up a warning */
2655                         WARN_ON(!HAS_PCH_LPT(dev));
2656
2657                         if (encoder->type == DRM_MODE_ENCODER_DAC) {
2658                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2659                                 return true;
2660                         } else {
2661                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2662                                                 encoder->type);
2663                                 return false;
2664                         }
2665                 }
2666
2667                 switch (encoder->type) {
2668                 case INTEL_OUTPUT_EDP:
2669                         if (!intel_encoder_is_pch_edp(&encoder->base))
2670                                 return false;
2671                         continue;
2672                 }
2673         }
2674
2675         return true;
2676 }
2677
2678 /* Program iCLKIP clock to the desired frequency */
2679 static void lpt_program_iclkip(struct drm_crtc *crtc)
2680 {
2681         struct drm_device *dev = crtc->dev;
2682         struct drm_i915_private *dev_priv = dev->dev_private;
2683         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2684         u32 temp;
2685
2686         /* It is necessary to ungate the pixclk gate prior to programming
2687          * the divisors, and gate it back when it is done.
2688          */
2689         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2690
2691         /* Disable SSCCTL */
2692         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2693                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2694                                         SBI_SSCCTL_DISABLE);
2695
2696         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2697         if (crtc->mode.clock == 20000) {
2698                 auxdiv = 1;
2699                 divsel = 0x41;
2700                 phaseinc = 0x20;
2701         } else {
2702                 /* The iCLK virtual clock root frequency is in MHz,
2703                  * but the crtc->mode.clock in in KHz. To get the divisors,
2704                  * it is necessary to divide one by another, so we
2705                  * convert the virtual clock precision to KHz here for higher
2706                  * precision.
2707                  */
2708                 u32 iclk_virtual_root_freq = 172800 * 1000;
2709                 u32 iclk_pi_range = 64;
2710                 u32 desired_divisor, msb_divisor_value, pi_value;
2711
2712                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2713                 msb_divisor_value = desired_divisor / iclk_pi_range;
2714                 pi_value = desired_divisor % iclk_pi_range;
2715
2716                 auxdiv = 0;
2717                 divsel = msb_divisor_value - 2;
2718                 phaseinc = pi_value;
2719         }
2720
2721         /* This should not happen with any sane values */
2722         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2723                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2724         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2725                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2726
2727         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2728                         crtc->mode.clock,
2729                         auxdiv,
2730                         divsel,
2731                         phasedir,
2732                         phaseinc);
2733
2734         /* Program SSCDIVINTPHASE6 */
2735         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2736         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2737         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2738         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2739         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2740         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2741         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2742
2743         intel_sbi_write(dev_priv,
2744                         SBI_SSCDIVINTPHASE6,
2745                         temp);
2746
2747         /* Program SSCAUXDIV */
2748         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2749         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2750         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2751         intel_sbi_write(dev_priv,
2752                         SBI_SSCAUXDIV6,
2753                         temp);
2754
2755
2756         /* Enable modulator and associated divider */
2757         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2758         temp &= ~SBI_SSCCTL_DISABLE;
2759         intel_sbi_write(dev_priv,
2760                         SBI_SSCCTL6,
2761                         temp);
2762
2763         /* Wait for initialization time */
2764         udelay(24);
2765
2766         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2767 }
2768
2769 /*
2770  * Enable PCH resources required for PCH ports:
2771  *   - PCH PLLs
2772  *   - FDI training & RX/TX
2773  *   - update transcoder timings
2774  *   - DP transcoding bits
2775  *   - transcoder
2776  */
2777 static void ironlake_pch_enable(struct drm_crtc *crtc)
2778 {
2779         struct drm_device *dev = crtc->dev;
2780         struct drm_i915_private *dev_priv = dev->dev_private;
2781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782         int pipe = intel_crtc->pipe;
2783         u32 reg, temp;
2784
2785         assert_transcoder_disabled(dev_priv, pipe);
2786
2787         /* For PCH output, training FDI link */
2788         dev_priv->display.fdi_link_train(crtc);
2789
2790         if (HAS_PCH_LPT(dev)) {
2791                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2792                 lpt_program_iclkip(crtc);
2793         } else if (HAS_PCH_CPT(dev)) {
2794                 u32 sel;
2795
2796                 intel_enable_pch_pll(intel_crtc);
2797
2798                 temp = I915_READ(PCH_DPLL_SEL);
2799                 switch (pipe) {
2800                 default:
2801                 case 0:
2802                         temp |= TRANSA_DPLL_ENABLE;
2803                         sel = TRANSA_DPLLB_SEL;
2804                         break;
2805                 case 1:
2806                         temp |= TRANSB_DPLL_ENABLE;
2807                         sel = TRANSB_DPLLB_SEL;
2808                         break;
2809                 case 2:
2810                         temp |= TRANSC_DPLL_ENABLE;
2811                         sel = TRANSC_DPLLB_SEL;
2812                         break;
2813                 }
2814                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2815                         temp |= sel;
2816                 else
2817                         temp &= ~sel;
2818                 I915_WRITE(PCH_DPLL_SEL, temp);
2819         }
2820
2821         /* set transcoder timing, panel must allow it */
2822         assert_panel_unlocked(dev_priv, pipe);
2823         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2824         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2825         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2826
2827         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2828         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2829         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2830         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
2831
2832         if (!IS_HASWELL(dev))
2833                 intel_fdi_normal_train(crtc);
2834
2835         /* For PCH DP, enable TRANS_DP_CTL */
2836         if (HAS_PCH_CPT(dev) &&
2837             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2838              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2839                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2840                 reg = TRANS_DP_CTL(pipe);
2841                 temp = I915_READ(reg);
2842                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2843                           TRANS_DP_SYNC_MASK |
2844                           TRANS_DP_BPC_MASK);
2845                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2846                          TRANS_DP_ENH_FRAMING);
2847                 temp |= bpc << 9; /* same format but at 11:9 */
2848
2849                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2850                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2851                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2852                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2853
2854                 switch (intel_trans_dp_port_sel(crtc)) {
2855                 case PCH_DP_B:
2856                         temp |= TRANS_DP_PORT_SEL_B;
2857                         break;
2858                 case PCH_DP_C:
2859                         temp |= TRANS_DP_PORT_SEL_C;
2860                         break;
2861                 case PCH_DP_D:
2862                         temp |= TRANS_DP_PORT_SEL_D;
2863                         break;
2864                 default:
2865                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2866                         temp |= TRANS_DP_PORT_SEL_B;
2867                         break;
2868                 }
2869
2870                 I915_WRITE(reg, temp);
2871         }
2872
2873         intel_enable_transcoder(dev_priv, pipe);
2874 }
2875
2876 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2877 {
2878         struct intel_pch_pll *pll = intel_crtc->pch_pll;
2879
2880         if (pll == NULL)
2881                 return;
2882
2883         if (pll->refcount == 0) {
2884                 WARN(1, "bad PCH PLL refcount\n");
2885                 return;
2886         }
2887
2888         --pll->refcount;
2889         intel_crtc->pch_pll = NULL;
2890 }
2891
2892 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2893 {
2894         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2895         struct intel_pch_pll *pll;
2896         int i;
2897
2898         pll = intel_crtc->pch_pll;
2899         if (pll) {
2900                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2901                               intel_crtc->base.base.id, pll->pll_reg);
2902                 goto prepare;
2903         }
2904
2905         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2906                 pll = &dev_priv->pch_plls[i];
2907
2908                 /* Only want to check enabled timings first */
2909                 if (pll->refcount == 0)
2910                         continue;
2911
2912                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2913                     fp == I915_READ(pll->fp0_reg)) {
2914                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2915                                       intel_crtc->base.base.id,
2916                                       pll->pll_reg, pll->refcount, pll->active);
2917
2918                         goto found;
2919                 }
2920         }
2921
2922         /* Ok no matching timings, maybe there's a free one? */
2923         for (i = 0; i < dev_priv->num_pch_pll; i++) {
2924                 pll = &dev_priv->pch_plls[i];
2925                 if (pll->refcount == 0) {
2926                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2927                                       intel_crtc->base.base.id, pll->pll_reg);
2928                         goto found;
2929                 }
2930         }
2931
2932         return NULL;
2933
2934 found:
2935         intel_crtc->pch_pll = pll;
2936         pll->refcount++;
2937         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2938 prepare: /* separate function? */
2939         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2940
2941         /* Wait for the clocks to stabilize before rewriting the regs */
2942         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2943         POSTING_READ(pll->pll_reg);
2944         udelay(150);
2945
2946         I915_WRITE(pll->fp0_reg, fp);
2947         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2948         pll->on = false;
2949         return pll;
2950 }
2951
2952 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2953 {
2954         struct drm_i915_private *dev_priv = dev->dev_private;
2955         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2956         u32 temp;
2957
2958         temp = I915_READ(dslreg);
2959         udelay(500);
2960         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2961                 /* Without this, mode sets may fail silently on FDI */
2962                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2963                 udelay(250);
2964                 I915_WRITE(tc2reg, 0);
2965                 if (wait_for(I915_READ(dslreg) != temp, 5))
2966                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2967         }
2968 }
2969
2970 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2971 {
2972         struct drm_device *dev = crtc->dev;
2973         struct drm_i915_private *dev_priv = dev->dev_private;
2974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2975         int pipe = intel_crtc->pipe;
2976         int plane = intel_crtc->plane;
2977         u32 temp;
2978         bool is_pch_port;
2979
2980         if (intel_crtc->active)
2981                 return;
2982
2983         intel_crtc->active = true;
2984         intel_update_watermarks(dev);
2985
2986         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2987                 temp = I915_READ(PCH_LVDS);
2988                 if ((temp & LVDS_PORT_EN) == 0)
2989                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2990         }
2991
2992         is_pch_port = intel_crtc_driving_pch(crtc);
2993
2994         if (is_pch_port)
2995                 ironlake_fdi_pll_enable(crtc);
2996         else
2997                 ironlake_fdi_disable(crtc);
2998
2999         /* Enable panel fitting for LVDS */
3000         if (dev_priv->pch_pf_size &&
3001             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3002                 /* Force use of hard-coded filter coefficients
3003                  * as some pre-programmed values are broken,
3004                  * e.g. x201.
3005                  */
3006                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3007                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3008                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3009         }
3010
3011         /*
3012          * On ILK+ LUT must be loaded before the pipe is running but with
3013          * clocks enabled
3014          */
3015         intel_crtc_load_lut(crtc);
3016
3017         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3018         intel_enable_plane(dev_priv, plane, pipe);
3019
3020         if (is_pch_port)
3021                 ironlake_pch_enable(crtc);
3022
3023         mutex_lock(&dev->struct_mutex);
3024         intel_update_fbc(dev);
3025         mutex_unlock(&dev->struct_mutex);
3026
3027         intel_crtc_update_cursor(crtc, true);
3028 }
3029
3030 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3031 {
3032         struct drm_device *dev = crtc->dev;
3033         struct drm_i915_private *dev_priv = dev->dev_private;
3034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035         int pipe = intel_crtc->pipe;
3036         int plane = intel_crtc->plane;
3037         u32 reg, temp;
3038
3039         if (!intel_crtc->active)
3040                 return;
3041
3042         intel_crtc_wait_for_pending_flips(crtc);
3043         drm_vblank_off(dev, pipe);
3044         intel_crtc_update_cursor(crtc, false);
3045
3046         intel_disable_plane(dev_priv, plane, pipe);
3047
3048         if (dev_priv->cfb_plane == plane)
3049                 intel_disable_fbc(dev);
3050
3051         intel_disable_pipe(dev_priv, pipe);
3052
3053         /* Disable PF */
3054         I915_WRITE(PF_CTL(pipe), 0);
3055         I915_WRITE(PF_WIN_SZ(pipe), 0);
3056
3057         ironlake_fdi_disable(crtc);
3058
3059         /* This is a horrible layering violation; we should be doing this in
3060          * the connector/encoder ->prepare instead, but we don't always have
3061          * enough information there about the config to know whether it will
3062          * actually be necessary or just cause undesired flicker.
3063          */
3064         intel_disable_pch_ports(dev_priv, pipe);
3065
3066         intel_disable_transcoder(dev_priv, pipe);
3067
3068         if (HAS_PCH_CPT(dev)) {
3069                 /* disable TRANS_DP_CTL */
3070                 reg = TRANS_DP_CTL(pipe);
3071                 temp = I915_READ(reg);
3072                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3073                 temp |= TRANS_DP_PORT_SEL_NONE;
3074                 I915_WRITE(reg, temp);
3075
3076                 /* disable DPLL_SEL */
3077                 temp = I915_READ(PCH_DPLL_SEL);
3078                 switch (pipe) {
3079                 case 0:
3080                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3081                         break;
3082                 case 1:
3083                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3084                         break;
3085                 case 2:
3086                         /* C shares PLL A or B */
3087                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3088                         break;
3089                 default:
3090                         BUG(); /* wtf */
3091                 }
3092                 I915_WRITE(PCH_DPLL_SEL, temp);
3093         }
3094
3095         /* disable PCH DPLL */
3096         intel_disable_pch_pll(intel_crtc);
3097
3098         /* Switch from PCDclk to Rawclk */
3099         reg = FDI_RX_CTL(pipe);
3100         temp = I915_READ(reg);
3101         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3102
3103         /* Disable CPU FDI TX PLL */
3104         reg = FDI_TX_CTL(pipe);
3105         temp = I915_READ(reg);
3106         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3107
3108         POSTING_READ(reg);
3109         udelay(100);
3110
3111         reg = FDI_RX_CTL(pipe);
3112         temp = I915_READ(reg);
3113         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3114
3115         /* Wait for the clocks to turn off. */
3116         POSTING_READ(reg);
3117         udelay(100);
3118
3119         intel_crtc->active = false;
3120         intel_update_watermarks(dev);
3121
3122         mutex_lock(&dev->struct_mutex);
3123         intel_update_fbc(dev);
3124         mutex_unlock(&dev->struct_mutex);
3125 }
3126
3127 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3128 {
3129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3130         int pipe = intel_crtc->pipe;
3131         int plane = intel_crtc->plane;
3132
3133         /* XXX: When our outputs are all unaware of DPMS modes other than off
3134          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3135          */
3136         switch (mode) {
3137         case DRM_MODE_DPMS_ON:
3138         case DRM_MODE_DPMS_STANDBY:
3139         case DRM_MODE_DPMS_SUSPEND:
3140                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3141                 ironlake_crtc_enable(crtc);
3142                 break;
3143
3144         case DRM_MODE_DPMS_OFF:
3145                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3146                 ironlake_crtc_disable(crtc);
3147                 break;
3148         }
3149 }
3150
3151 static void ironlake_crtc_off(struct drm_crtc *crtc)
3152 {
3153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3154         intel_put_pch_pll(intel_crtc);
3155 }
3156
3157 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3158 {
3159         if (!enable && intel_crtc->overlay) {
3160                 struct drm_device *dev = intel_crtc->base.dev;
3161                 struct drm_i915_private *dev_priv = dev->dev_private;
3162
3163                 mutex_lock(&dev->struct_mutex);
3164                 dev_priv->mm.interruptible = false;
3165                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3166                 dev_priv->mm.interruptible = true;
3167                 mutex_unlock(&dev->struct_mutex);
3168         }
3169
3170         /* Let userspace switch the overlay on again. In most cases userspace
3171          * has to recompute where to put it anyway.
3172          */
3173 }
3174
3175 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3176 {
3177         struct drm_device *dev = crtc->dev;
3178         struct drm_i915_private *dev_priv = dev->dev_private;
3179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3180         int pipe = intel_crtc->pipe;
3181         int plane = intel_crtc->plane;
3182
3183         if (intel_crtc->active)
3184                 return;
3185
3186         intel_crtc->active = true;
3187         intel_update_watermarks(dev);
3188
3189         intel_enable_pll(dev_priv, pipe);
3190         intel_enable_pipe(dev_priv, pipe, false);
3191         intel_enable_plane(dev_priv, plane, pipe);
3192
3193         intel_crtc_load_lut(crtc);
3194         intel_update_fbc(dev);
3195
3196         /* Give the overlay scaler a chance to enable if it's on this pipe */
3197         intel_crtc_dpms_overlay(intel_crtc, true);
3198         intel_crtc_update_cursor(crtc, true);
3199 }
3200
3201 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3202 {
3203         struct drm_device *dev = crtc->dev;
3204         struct drm_i915_private *dev_priv = dev->dev_private;
3205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3206         int pipe = intel_crtc->pipe;
3207         int plane = intel_crtc->plane;
3208
3209         if (!intel_crtc->active)
3210                 return;
3211
3212         /* Give the overlay scaler a chance to disable if it's on this pipe */
3213         intel_crtc_wait_for_pending_flips(crtc);
3214         drm_vblank_off(dev, pipe);
3215         intel_crtc_dpms_overlay(intel_crtc, false);
3216         intel_crtc_update_cursor(crtc, false);
3217
3218         if (dev_priv->cfb_plane == plane)
3219                 intel_disable_fbc(dev);
3220
3221         intel_disable_plane(dev_priv, plane, pipe);
3222         intel_disable_pipe(dev_priv, pipe);
3223         intel_disable_pll(dev_priv, pipe);
3224
3225         intel_crtc->active = false;
3226         intel_update_fbc(dev);
3227         intel_update_watermarks(dev);
3228 }
3229
3230 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3231 {
3232         /* XXX: When our outputs are all unaware of DPMS modes other than off
3233          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3234          */
3235         switch (mode) {
3236         case DRM_MODE_DPMS_ON:
3237         case DRM_MODE_DPMS_STANDBY:
3238         case DRM_MODE_DPMS_SUSPEND:
3239                 i9xx_crtc_enable(crtc);
3240                 break;
3241         case DRM_MODE_DPMS_OFF:
3242                 i9xx_crtc_disable(crtc);
3243                 break;
3244         }
3245 }
3246
3247 static void i9xx_crtc_off(struct drm_crtc *crtc)
3248 {
3249 }
3250
3251 /**
3252  * Sets the power management mode of the pipe and plane.
3253  */
3254 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3255 {
3256         struct drm_device *dev = crtc->dev;
3257         struct drm_i915_private *dev_priv = dev->dev_private;
3258         struct drm_i915_master_private *master_priv;
3259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3260         int pipe = intel_crtc->pipe;
3261         bool enabled;
3262
3263         if (intel_crtc->dpms_mode == mode)
3264                 return;
3265
3266         intel_crtc->dpms_mode = mode;
3267
3268         dev_priv->display.dpms(crtc, mode);
3269
3270         if (!dev->primary->master)
3271                 return;
3272
3273         master_priv = dev->primary->master->driver_priv;
3274         if (!master_priv->sarea_priv)
3275                 return;
3276
3277         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3278
3279         switch (pipe) {
3280         case 0:
3281                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3282                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3283                 break;
3284         case 1:
3285                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3286                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3287                 break;
3288         default:
3289                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3290                 break;
3291         }
3292 }
3293
3294 static void intel_crtc_disable(struct drm_crtc *crtc)
3295 {
3296         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3297         struct drm_device *dev = crtc->dev;
3298         struct drm_i915_private *dev_priv = dev->dev_private;
3299
3300         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3301         dev_priv->display.off(crtc);
3302
3303         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3304         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3305
3306         if (crtc->fb) {
3307                 mutex_lock(&dev->struct_mutex);
3308                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3309                 mutex_unlock(&dev->struct_mutex);
3310         }
3311 }
3312
3313 /* Prepare for a mode set.
3314  *
3315  * Note we could be a lot smarter here.  We need to figure out which outputs
3316  * will be enabled, which disabled (in short, how the config will changes)
3317  * and perform the minimum necessary steps to accomplish that, e.g. updating
3318  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3319  * panel fitting is in the proper state, etc.
3320  */
3321 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3322 {
3323         i9xx_crtc_disable(crtc);
3324 }
3325
3326 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3327 {
3328         i9xx_crtc_enable(crtc);
3329 }
3330
3331 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3332 {
3333         ironlake_crtc_disable(crtc);
3334 }
3335
3336 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3337 {
3338         ironlake_crtc_enable(crtc);
3339 }
3340
3341 void intel_encoder_prepare(struct drm_encoder *encoder)
3342 {
3343         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3344         /* lvds has its own version of prepare see intel_lvds_prepare */
3345         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3346 }
3347
3348 void intel_encoder_commit(struct drm_encoder *encoder)
3349 {
3350         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3351         struct drm_device *dev = encoder->dev;
3352         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3353
3354         /* lvds has its own version of commit see intel_lvds_commit */
3355         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3356
3357         if (HAS_PCH_CPT(dev))
3358                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3359 }
3360
3361 void intel_encoder_destroy(struct drm_encoder *encoder)
3362 {
3363         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3364
3365         drm_encoder_cleanup(encoder);
3366         kfree(intel_encoder);
3367 }
3368
3369 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3370                                   struct drm_display_mode *mode,
3371                                   struct drm_display_mode *adjusted_mode)
3372 {
3373         struct drm_device *dev = crtc->dev;
3374
3375         if (HAS_PCH_SPLIT(dev)) {
3376                 /* FDI link clock is fixed at 2.7G */
3377                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3378                         return false;
3379         }
3380
3381         /* All interlaced capable intel hw wants timings in frames. Note though
3382          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3383          * timings, so we need to be careful not to clobber these.*/
3384         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3385                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3386
3387         return true;
3388 }
3389
3390 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3391 {
3392         return 400000; /* FIXME */
3393 }
3394
3395 static int i945_get_display_clock_speed(struct drm_device *dev)
3396 {
3397         return 400000;
3398 }
3399
3400 static int i915_get_display_clock_speed(struct drm_device *dev)
3401 {
3402         return 333000;
3403 }
3404
3405 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3406 {
3407         return 200000;
3408 }
3409
3410 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3411 {
3412         u16 gcfgc = 0;
3413
3414         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3415
3416         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3417                 return 133000;
3418         else {
3419                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3420                 case GC_DISPLAY_CLOCK_333_MHZ:
3421                         return 333000;
3422                 default:
3423                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3424                         return 190000;
3425                 }
3426         }
3427 }
3428
3429 static int i865_get_display_clock_speed(struct drm_device *dev)
3430 {
3431         return 266000;
3432 }
3433
3434 static int i855_get_display_clock_speed(struct drm_device *dev)
3435 {
3436         u16 hpllcc = 0;
3437         /* Assume that the hardware is in the high speed state.  This
3438          * should be the default.
3439          */
3440         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3441         case GC_CLOCK_133_200:
3442         case GC_CLOCK_100_200:
3443                 return 200000;
3444         case GC_CLOCK_166_250:
3445                 return 250000;
3446         case GC_CLOCK_100_133:
3447                 return 133000;
3448         }
3449
3450         /* Shouldn't happen */
3451         return 0;
3452 }
3453
3454 static int i830_get_display_clock_speed(struct drm_device *dev)
3455 {
3456         return 133000;
3457 }
3458
3459 struct fdi_m_n {
3460         u32        tu;
3461         u32        gmch_m;
3462         u32        gmch_n;
3463         u32        link_m;
3464         u32        link_n;
3465 };
3466
3467 static void
3468 fdi_reduce_ratio(u32 *num, u32 *den)
3469 {
3470         while (*num > 0xffffff || *den > 0xffffff) {
3471                 *num >>= 1;
3472                 *den >>= 1;
3473         }
3474 }
3475
3476 static void
3477 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3478                      int link_clock, struct fdi_m_n *m_n)
3479 {
3480         m_n->tu = 64; /* default size */
3481
3482         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3483         m_n->gmch_m = bits_per_pixel * pixel_clock;
3484         m_n->gmch_n = link_clock * nlanes * 8;
3485         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3486
3487         m_n->link_m = pixel_clock;
3488         m_n->link_n = link_clock;
3489         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3490 }
3491
3492 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3493 {
3494         if (i915_panel_use_ssc >= 0)
3495                 return i915_panel_use_ssc != 0;
3496         return dev_priv->lvds_use_ssc
3497                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3498 }
3499
3500 /**
3501  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3502  * @crtc: CRTC structure
3503  * @mode: requested mode
3504  *
3505  * A pipe may be connected to one or more outputs.  Based on the depth of the
3506  * attached framebuffer, choose a good color depth to use on the pipe.
3507  *
3508  * If possible, match the pipe depth to the fb depth.  In some cases, this
3509  * isn't ideal, because the connected output supports a lesser or restricted
3510  * set of depths.  Resolve that here:
3511  *    LVDS typically supports only 6bpc, so clamp down in that case
3512  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3513  *    Displays may support a restricted set as well, check EDID and clamp as
3514  *      appropriate.
3515  *    DP may want to dither down to 6bpc to fit larger modes
3516  *
3517  * RETURNS:
3518  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3519  * true if they don't match).
3520  */
3521 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3522                                          unsigned int *pipe_bpp,
3523                                          struct drm_display_mode *mode)
3524 {
3525         struct drm_device *dev = crtc->dev;
3526         struct drm_i915_private *dev_priv = dev->dev_private;
3527         struct drm_encoder *encoder;
3528         struct drm_connector *connector;
3529         unsigned int display_bpc = UINT_MAX, bpc;
3530
3531         /* Walk the encoders & connectors on this crtc, get min bpc */
3532         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3533                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3534
3535                 if (encoder->crtc != crtc)
3536                         continue;
3537
3538                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3539                         unsigned int lvds_bpc;
3540
3541                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3542                             LVDS_A3_POWER_UP)
3543                                 lvds_bpc = 8;
3544                         else
3545                                 lvds_bpc = 6;
3546
3547                         if (lvds_bpc < display_bpc) {
3548                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3549                                 display_bpc = lvds_bpc;
3550                         }
3551                         continue;
3552                 }
3553
3554                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3555                         /* Use VBT settings if we have an eDP panel */
3556                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3557
3558                         if (edp_bpc < display_bpc) {
3559                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3560                                 display_bpc = edp_bpc;
3561                         }
3562                         continue;
3563                 }
3564
3565                 /* Not one of the known troublemakers, check the EDID */
3566                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3567                                     head) {
3568                         if (connector->encoder != encoder)
3569                                 continue;
3570
3571                         /* Don't use an invalid EDID bpc value */
3572                         if (connector->display_info.bpc &&
3573                             connector->display_info.bpc < display_bpc) {
3574                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3575                                 display_bpc = connector->display_info.bpc;
3576                         }
3577                 }
3578
3579                 /*
3580                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3581                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3582                  */
3583                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3584                         if (display_bpc > 8 && display_bpc < 12) {
3585                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3586                                 display_bpc = 12;
3587                         } else {
3588                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3589                                 display_bpc = 8;
3590                         }
3591                 }
3592         }
3593
3594         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3595                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3596                 display_bpc = 6;
3597         }
3598
3599         /*
3600          * We could just drive the pipe at the highest bpc all the time and
3601          * enable dithering as needed, but that costs bandwidth.  So choose
3602          * the minimum value that expresses the full color range of the fb but
3603          * also stays within the max display bpc discovered above.
3604          */
3605
3606         switch (crtc->fb->depth) {
3607         case 8:
3608                 bpc = 8; /* since we go through a colormap */
3609                 break;
3610         case 15:
3611         case 16:
3612                 bpc = 6; /* min is 18bpp */
3613                 break;
3614         case 24:
3615                 bpc = 8;
3616                 break;
3617         case 30:
3618                 bpc = 10;
3619                 break;
3620         case 48:
3621                 bpc = 12;
3622                 break;
3623         default:
3624                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3625                 bpc = min((unsigned int)8, display_bpc);
3626                 break;
3627         }
3628
3629         display_bpc = min(display_bpc, bpc);
3630
3631         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3632                       bpc, display_bpc);
3633
3634         *pipe_bpp = display_bpc * 3;
3635
3636         return display_bpc != bpc;
3637 }
3638
3639 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3640 {
3641         struct drm_device *dev = crtc->dev;
3642         struct drm_i915_private *dev_priv = dev->dev_private;
3643         int refclk;
3644
3645         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3646             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3647                 refclk = dev_priv->lvds_ssc_freq * 1000;
3648                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3649                               refclk / 1000);
3650         } else if (!IS_GEN2(dev)) {
3651                 refclk = 96000;
3652         } else {
3653                 refclk = 48000;
3654         }
3655
3656         return refclk;
3657 }
3658
3659 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3660                                       intel_clock_t *clock)
3661 {
3662         /* SDVO TV has fixed PLL values depend on its clock range,
3663            this mirrors vbios setting. */
3664         if (adjusted_mode->clock >= 100000
3665             && adjusted_mode->clock < 140500) {
3666                 clock->p1 = 2;
3667                 clock->p2 = 10;
3668                 clock->n = 3;
3669                 clock->m1 = 16;
3670                 clock->m2 = 8;
3671         } else if (adjusted_mode->clock >= 140500
3672                    && adjusted_mode->clock <= 200000) {
3673                 clock->p1 = 1;
3674                 clock->p2 = 10;
3675                 clock->n = 6;
3676                 clock->m1 = 12;
3677                 clock->m2 = 8;
3678         }
3679 }
3680
3681 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3682                                      intel_clock_t *clock,
3683                                      intel_clock_t *reduced_clock)
3684 {
3685         struct drm_device *dev = crtc->dev;
3686         struct drm_i915_private *dev_priv = dev->dev_private;
3687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3688         int pipe = intel_crtc->pipe;
3689         u32 fp, fp2 = 0;
3690
3691         if (IS_PINEVIEW(dev)) {
3692                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3693                 if (reduced_clock)
3694                         fp2 = (1 << reduced_clock->n) << 16 |
3695                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3696         } else {
3697                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3698                 if (reduced_clock)
3699                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3700                                 reduced_clock->m2;
3701         }
3702
3703         I915_WRITE(FP0(pipe), fp);
3704
3705         intel_crtc->lowfreq_avail = false;
3706         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3707             reduced_clock && i915_powersave) {
3708                 I915_WRITE(FP1(pipe), fp2);
3709                 intel_crtc->lowfreq_avail = true;
3710         } else {
3711                 I915_WRITE(FP1(pipe), fp);
3712         }
3713 }
3714
3715 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3716                               struct drm_display_mode *adjusted_mode)
3717 {
3718         struct drm_device *dev = crtc->dev;
3719         struct drm_i915_private *dev_priv = dev->dev_private;
3720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3721         int pipe = intel_crtc->pipe;
3722         u32 temp;
3723
3724         temp = I915_READ(LVDS);
3725         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3726         if (pipe == 1) {
3727                 temp |= LVDS_PIPEB_SELECT;
3728         } else {
3729                 temp &= ~LVDS_PIPEB_SELECT;
3730         }
3731         /* set the corresponsding LVDS_BORDER bit */
3732         temp |= dev_priv->lvds_border_bits;
3733         /* Set the B0-B3 data pairs corresponding to whether we're going to
3734          * set the DPLLs for dual-channel mode or not.
3735          */
3736         if (clock->p2 == 7)
3737                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3738         else
3739                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3740
3741         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3742          * appropriately here, but we need to look more thoroughly into how
3743          * panels behave in the two modes.
3744          */
3745         /* set the dithering flag on LVDS as needed */
3746         if (INTEL_INFO(dev)->gen >= 4) {
3747                 if (dev_priv->lvds_dither)
3748                         temp |= LVDS_ENABLE_DITHER;
3749                 else
3750                         temp &= ~LVDS_ENABLE_DITHER;
3751         }
3752         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3753         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3754                 temp |= LVDS_HSYNC_POLARITY;
3755         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3756                 temp |= LVDS_VSYNC_POLARITY;
3757         I915_WRITE(LVDS, temp);
3758 }
3759
3760 static void i9xx_update_pll(struct drm_crtc *crtc,
3761                             struct drm_display_mode *mode,
3762                             struct drm_display_mode *adjusted_mode,
3763                             intel_clock_t *clock, intel_clock_t *reduced_clock,
3764                             int num_connectors)
3765 {
3766         struct drm_device *dev = crtc->dev;
3767         struct drm_i915_private *dev_priv = dev->dev_private;
3768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3769         int pipe = intel_crtc->pipe;
3770         u32 dpll;
3771         bool is_sdvo;
3772
3773         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3774                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3775
3776         dpll = DPLL_VGA_MODE_DIS;
3777
3778         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3779                 dpll |= DPLLB_MODE_LVDS;
3780         else
3781                 dpll |= DPLLB_MODE_DAC_SERIAL;
3782         if (is_sdvo) {
3783                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3784                 if (pixel_multiplier > 1) {
3785                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3786                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3787                 }
3788                 dpll |= DPLL_DVO_HIGH_SPEED;
3789         }
3790         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3791                 dpll |= DPLL_DVO_HIGH_SPEED;
3792
3793         /* compute bitmask from p1 value */
3794         if (IS_PINEVIEW(dev))
3795                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3796         else {
3797                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3798                 if (IS_G4X(dev) && reduced_clock)
3799                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3800         }
3801         switch (clock->p2) {
3802         case 5:
3803                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3804                 break;
3805         case 7:
3806                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3807                 break;
3808         case 10:
3809                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3810                 break;
3811         case 14:
3812                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3813                 break;
3814         }
3815         if (INTEL_INFO(dev)->gen >= 4)
3816                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3817
3818         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3819                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3820         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3821                 /* XXX: just matching BIOS for now */
3822                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3823                 dpll |= 3;
3824         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3825                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3826                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3827         else
3828                 dpll |= PLL_REF_INPUT_DREFCLK;
3829
3830         dpll |= DPLL_VCO_ENABLE;
3831         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3832         POSTING_READ(DPLL(pipe));
3833         udelay(150);
3834
3835         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3836          * This is an exception to the general rule that mode_set doesn't turn
3837          * things on.
3838          */
3839         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3840                 intel_update_lvds(crtc, clock, adjusted_mode);
3841
3842         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3843                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3844
3845         I915_WRITE(DPLL(pipe), dpll);
3846
3847         /* Wait for the clocks to stabilize. */
3848         POSTING_READ(DPLL(pipe));
3849         udelay(150);
3850
3851         if (INTEL_INFO(dev)->gen >= 4) {
3852                 u32 temp = 0;
3853                 if (is_sdvo) {
3854                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3855                         if (temp > 1)
3856                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3857                         else
3858                                 temp = 0;
3859                 }
3860                 I915_WRITE(DPLL_MD(pipe), temp);
3861         } else {
3862                 /* The pixel multiplier can only be updated once the
3863                  * DPLL is enabled and the clocks are stable.
3864                  *
3865                  * So write it again.
3866                  */
3867                 I915_WRITE(DPLL(pipe), dpll);
3868         }
3869 }
3870
3871 static void i8xx_update_pll(struct drm_crtc *crtc,
3872                             struct drm_display_mode *adjusted_mode,
3873                             intel_clock_t *clock,
3874                             int num_connectors)
3875 {
3876         struct drm_device *dev = crtc->dev;
3877         struct drm_i915_private *dev_priv = dev->dev_private;
3878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3879         int pipe = intel_crtc->pipe;
3880         u32 dpll;
3881
3882         dpll = DPLL_VGA_MODE_DIS;
3883
3884         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3885                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3886         } else {
3887                 if (clock->p1 == 2)
3888                         dpll |= PLL_P1_DIVIDE_BY_TWO;
3889                 else
3890                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3891                 if (clock->p2 == 4)
3892                         dpll |= PLL_P2_DIVIDE_BY_4;
3893         }
3894
3895         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3896                 /* XXX: just matching BIOS for now */
3897                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3898                 dpll |= 3;
3899         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3900                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3901                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3902         else
3903                 dpll |= PLL_REF_INPUT_DREFCLK;
3904
3905         dpll |= DPLL_VCO_ENABLE;
3906         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3907         POSTING_READ(DPLL(pipe));
3908         udelay(150);
3909
3910         I915_WRITE(DPLL(pipe), dpll);
3911
3912         /* Wait for the clocks to stabilize. */
3913         POSTING_READ(DPLL(pipe));
3914         udelay(150);
3915
3916         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3917          * This is an exception to the general rule that mode_set doesn't turn
3918          * things on.
3919          */
3920         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3921                 intel_update_lvds(crtc, clock, adjusted_mode);
3922
3923         /* The pixel multiplier can only be updated once the
3924          * DPLL is enabled and the clocks are stable.
3925          *
3926          * So write it again.
3927          */
3928         I915_WRITE(DPLL(pipe), dpll);
3929 }
3930
3931 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3932                               struct drm_display_mode *mode,
3933                               struct drm_display_mode *adjusted_mode,
3934                               int x, int y,
3935                               struct drm_framebuffer *old_fb)
3936 {
3937         struct drm_device *dev = crtc->dev;
3938         struct drm_i915_private *dev_priv = dev->dev_private;
3939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3940         int pipe = intel_crtc->pipe;
3941         int plane = intel_crtc->plane;
3942         int refclk, num_connectors = 0;
3943         intel_clock_t clock, reduced_clock;
3944         u32 dspcntr, pipeconf, vsyncshift;
3945         bool ok, has_reduced_clock = false, is_sdvo = false;
3946         bool is_lvds = false, is_tv = false, is_dp = false;
3947         struct drm_mode_config *mode_config = &dev->mode_config;
3948         struct intel_encoder *encoder;
3949         const intel_limit_t *limit;
3950         int ret;
3951
3952         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3953                 if (encoder->base.crtc != crtc)
3954                         continue;
3955
3956                 switch (encoder->type) {
3957                 case INTEL_OUTPUT_LVDS:
3958                         is_lvds = true;
3959                         break;
3960                 case INTEL_OUTPUT_SDVO:
3961                 case INTEL_OUTPUT_HDMI:
3962                         is_sdvo = true;
3963                         if (encoder->needs_tv_clock)
3964                                 is_tv = true;
3965                         break;
3966                 case INTEL_OUTPUT_TVOUT:
3967                         is_tv = true;
3968                         break;
3969                 case INTEL_OUTPUT_DISPLAYPORT:
3970                         is_dp = true;
3971                         break;
3972                 }
3973
3974                 num_connectors++;
3975         }
3976
3977         refclk = i9xx_get_refclk(crtc, num_connectors);
3978
3979         /*
3980          * Returns a set of divisors for the desired target clock with the given
3981          * refclk, or FALSE.  The returned values represent the clock equation:
3982          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3983          */
3984         limit = intel_limit(crtc, refclk);
3985         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3986                              &clock);
3987         if (!ok) {
3988                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3989                 return -EINVAL;
3990         }
3991
3992         /* Ensure that the cursor is valid for the new mode before changing... */
3993         intel_crtc_update_cursor(crtc, true);
3994
3995         if (is_lvds && dev_priv->lvds_downclock_avail) {
3996                 /*
3997                  * Ensure we match the reduced clock's P to the target clock.
3998                  * If the clocks don't match, we can't switch the display clock
3999                  * by using the FP0/FP1. In such case we will disable the LVDS
4000                  * downclock feature.
4001                 */
4002                 has_reduced_clock = limit->find_pll(limit, crtc,
4003                                                     dev_priv->lvds_downclock,
4004                                                     refclk,
4005                                                     &clock,
4006                                                     &reduced_clock);
4007         }
4008
4009         if (is_sdvo && is_tv)
4010                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4011
4012         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4013                                  &reduced_clock : NULL);
4014
4015         if (IS_GEN2(dev))
4016                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4017         else
4018                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4019                                 has_reduced_clock ? &reduced_clock : NULL,
4020                                 num_connectors);
4021
4022         /* setup pipeconf */
4023         pipeconf = I915_READ(PIPECONF(pipe));
4024
4025         /* Set up the display plane register */
4026         dspcntr = DISPPLANE_GAMMA_ENABLE;
4027
4028         if (pipe == 0)
4029                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4030         else
4031                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4032
4033         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4034                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4035                  * core speed.
4036                  *
4037                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4038                  * pipe == 0 check?
4039                  */
4040                 if (mode->clock >
4041                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4042                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4043                 else
4044                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4045         }
4046
4047         /* default to 8bpc */
4048         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4049         if (is_dp) {
4050                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4051                         pipeconf |= PIPECONF_BPP_6 |
4052                                     PIPECONF_DITHER_EN |
4053                                     PIPECONF_DITHER_TYPE_SP;
4054                 }
4055         }
4056
4057         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4058         drm_mode_debug_printmodeline(mode);
4059
4060         if (HAS_PIPE_CXSR(dev)) {
4061                 if (intel_crtc->lowfreq_avail) {
4062                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4063                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4064                 } else {
4065                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4066                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4067                 }
4068         }
4069
4070         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4071         if (!IS_GEN2(dev) &&
4072             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4073                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4074                 /* the chip adds 2 halflines automatically */
4075                 adjusted_mode->crtc_vtotal -= 1;
4076                 adjusted_mode->crtc_vblank_end -= 1;
4077                 vsyncshift = adjusted_mode->crtc_hsync_start
4078                              - adjusted_mode->crtc_htotal/2;
4079         } else {
4080                 pipeconf |= PIPECONF_PROGRESSIVE;
4081                 vsyncshift = 0;
4082         }
4083
4084         if (!IS_GEN3(dev))
4085                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4086
4087         I915_WRITE(HTOTAL(pipe),
4088                    (adjusted_mode->crtc_hdisplay - 1) |
4089                    ((adjusted_mode->crtc_htotal - 1) << 16));
4090         I915_WRITE(HBLANK(pipe),
4091                    (adjusted_mode->crtc_hblank_start - 1) |
4092                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4093         I915_WRITE(HSYNC(pipe),
4094                    (adjusted_mode->crtc_hsync_start - 1) |
4095                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4096
4097         I915_WRITE(VTOTAL(pipe),
4098                    (adjusted_mode->crtc_vdisplay - 1) |
4099                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4100         I915_WRITE(VBLANK(pipe),
4101                    (adjusted_mode->crtc_vblank_start - 1) |
4102                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4103         I915_WRITE(VSYNC(pipe),
4104                    (adjusted_mode->crtc_vsync_start - 1) |
4105                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4106
4107         /* pipesrc and dspsize control the size that is scaled from,
4108          * which should always be the user's requested size.
4109          */
4110         I915_WRITE(DSPSIZE(plane),
4111                    ((mode->vdisplay - 1) << 16) |
4112                    (mode->hdisplay - 1));
4113         I915_WRITE(DSPPOS(plane), 0);
4114         I915_WRITE(PIPESRC(pipe),
4115                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4116
4117         I915_WRITE(PIPECONF(pipe), pipeconf);
4118         POSTING_READ(PIPECONF(pipe));
4119         intel_enable_pipe(dev_priv, pipe, false);
4120
4121         intel_wait_for_vblank(dev, pipe);
4122
4123         I915_WRITE(DSPCNTR(plane), dspcntr);
4124         POSTING_READ(DSPCNTR(plane));
4125
4126         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4127
4128         intel_update_watermarks(dev);
4129
4130         return ret;
4131 }
4132
4133 /*
4134  * Initialize reference clocks when the driver loads
4135  */
4136 void ironlake_init_pch_refclk(struct drm_device *dev)
4137 {
4138         struct drm_i915_private *dev_priv = dev->dev_private;
4139         struct drm_mode_config *mode_config = &dev->mode_config;
4140         struct intel_encoder *encoder;
4141         u32 temp;
4142         bool has_lvds = false;
4143         bool has_cpu_edp = false;
4144         bool has_pch_edp = false;
4145         bool has_panel = false;
4146         bool has_ck505 = false;
4147         bool can_ssc = false;
4148
4149         /* We need to take the global config into account */
4150         list_for_each_entry(encoder, &mode_config->encoder_list,
4151                             base.head) {
4152                 switch (encoder->type) {
4153                 case INTEL_OUTPUT_LVDS:
4154                         has_panel = true;
4155                         has_lvds = true;
4156                         break;
4157                 case INTEL_OUTPUT_EDP:
4158                         has_panel = true;
4159                         if (intel_encoder_is_pch_edp(&encoder->base))
4160                                 has_pch_edp = true;
4161                         else
4162                                 has_cpu_edp = true;
4163                         break;
4164                 }
4165         }
4166
4167         if (HAS_PCH_IBX(dev)) {
4168                 has_ck505 = dev_priv->display_clock_mode;
4169                 can_ssc = has_ck505;
4170         } else {
4171                 has_ck505 = false;
4172                 can_ssc = true;
4173         }
4174
4175         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4176                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4177                       has_ck505);
4178
4179         /* Ironlake: try to setup display ref clock before DPLL
4180          * enabling. This is only under driver's control after
4181          * PCH B stepping, previous chipset stepping should be
4182          * ignoring this setting.
4183          */
4184         temp = I915_READ(PCH_DREF_CONTROL);
4185         /* Always enable nonspread source */
4186         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4187
4188         if (has_ck505)
4189                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4190         else
4191                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4192
4193         if (has_panel) {
4194                 temp &= ~DREF_SSC_SOURCE_MASK;
4195                 temp |= DREF_SSC_SOURCE_ENABLE;
4196
4197                 /* SSC must be turned on before enabling the CPU output  */
4198                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4199                         DRM_DEBUG_KMS("Using SSC on panel\n");
4200                         temp |= DREF_SSC1_ENABLE;
4201                 } else
4202                         temp &= ~DREF_SSC1_ENABLE;
4203
4204                 /* Get SSC going before enabling the outputs */
4205                 I915_WRITE(PCH_DREF_CONTROL, temp);
4206                 POSTING_READ(PCH_DREF_CONTROL);
4207                 udelay(200);
4208
4209                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4210
4211                 /* Enable CPU source on CPU attached eDP */
4212                 if (has_cpu_edp) {
4213                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4214                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4215                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4216                         }
4217                         else
4218                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4219                 } else
4220                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4221
4222                 I915_WRITE(PCH_DREF_CONTROL, temp);
4223                 POSTING_READ(PCH_DREF_CONTROL);
4224                 udelay(200);
4225         } else {
4226                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4227
4228                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4229
4230                 /* Turn off CPU output */
4231                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4232
4233                 I915_WRITE(PCH_DREF_CONTROL, temp);
4234                 POSTING_READ(PCH_DREF_CONTROL);
4235                 udelay(200);
4236
4237                 /* Turn off the SSC source */
4238                 temp &= ~DREF_SSC_SOURCE_MASK;
4239                 temp |= DREF_SSC_SOURCE_DISABLE;
4240
4241                 /* Turn off SSC1 */
4242                 temp &= ~ DREF_SSC1_ENABLE;
4243
4244                 I915_WRITE(PCH_DREF_CONTROL, temp);
4245                 POSTING_READ(PCH_DREF_CONTROL);
4246                 udelay(200);
4247         }
4248 }
4249
4250 static int ironlake_get_refclk(struct drm_crtc *crtc)
4251 {
4252         struct drm_device *dev = crtc->dev;
4253         struct drm_i915_private *dev_priv = dev->dev_private;
4254         struct intel_encoder *encoder;
4255         struct drm_mode_config *mode_config = &dev->mode_config;
4256         struct intel_encoder *edp_encoder = NULL;
4257         int num_connectors = 0;
4258         bool is_lvds = false;
4259
4260         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4261                 if (encoder->base.crtc != crtc)
4262                         continue;
4263
4264                 switch (encoder->type) {
4265                 case INTEL_OUTPUT_LVDS:
4266                         is_lvds = true;
4267                         break;
4268                 case INTEL_OUTPUT_EDP:
4269                         edp_encoder = encoder;
4270                         break;
4271                 }
4272                 num_connectors++;
4273         }
4274
4275         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4276                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4277                               dev_priv->lvds_ssc_freq);
4278                 return dev_priv->lvds_ssc_freq * 1000;
4279         }
4280
4281         return 120000;
4282 }
4283
4284 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4285                                   struct drm_display_mode *mode,
4286                                   struct drm_display_mode *adjusted_mode,
4287                                   int x, int y,
4288                                   struct drm_framebuffer *old_fb)
4289 {
4290         struct drm_device *dev = crtc->dev;
4291         struct drm_i915_private *dev_priv = dev->dev_private;
4292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4293         int pipe = intel_crtc->pipe;
4294         int plane = intel_crtc->plane;
4295         int refclk, num_connectors = 0;
4296         intel_clock_t clock, reduced_clock;
4297         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4298         bool ok, has_reduced_clock = false, is_sdvo = false;
4299         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4300         struct drm_mode_config *mode_config = &dev->mode_config;
4301         struct intel_encoder *encoder, *edp_encoder = NULL;
4302         const intel_limit_t *limit;
4303         int ret;
4304         struct fdi_m_n m_n = {0};
4305         u32 temp;
4306         int target_clock, pixel_multiplier, lane, link_bw, factor;
4307         unsigned int pipe_bpp;
4308         bool dither;
4309         bool is_cpu_edp = false, is_pch_edp = false;
4310
4311         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4312                 if (encoder->base.crtc != crtc)
4313                         continue;
4314
4315                 switch (encoder->type) {
4316                 case INTEL_OUTPUT_LVDS:
4317                         is_lvds = true;
4318                         break;
4319                 case INTEL_OUTPUT_SDVO:
4320                 case INTEL_OUTPUT_HDMI:
4321                         is_sdvo = true;
4322                         if (encoder->needs_tv_clock)
4323                                 is_tv = true;
4324                         break;
4325                 case INTEL_OUTPUT_TVOUT:
4326                         is_tv = true;
4327                         break;
4328                 case INTEL_OUTPUT_ANALOG:
4329                         is_crt = true;
4330                         break;
4331                 case INTEL_OUTPUT_DISPLAYPORT:
4332                         is_dp = true;
4333                         break;
4334                 case INTEL_OUTPUT_EDP:
4335                         is_dp = true;
4336                         if (intel_encoder_is_pch_edp(&encoder->base))
4337                                 is_pch_edp = true;
4338                         else
4339                                 is_cpu_edp = true;
4340                         edp_encoder = encoder;
4341                         break;
4342                 }
4343
4344                 num_connectors++;
4345         }
4346
4347         refclk = ironlake_get_refclk(crtc);
4348
4349         /*
4350          * Returns a set of divisors for the desired target clock with the given
4351          * refclk, or FALSE.  The returned values represent the clock equation:
4352          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4353          */
4354         limit = intel_limit(crtc, refclk);
4355         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4356                              &clock);
4357         if (!ok) {
4358                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4359                 return -EINVAL;
4360         }
4361
4362         /* Ensure that the cursor is valid for the new mode before changing... */
4363         intel_crtc_update_cursor(crtc, true);
4364
4365         if (is_lvds && dev_priv->lvds_downclock_avail) {
4366                 /*
4367                  * Ensure we match the reduced clock's P to the target clock.
4368                  * If the clocks don't match, we can't switch the display clock
4369                  * by using the FP0/FP1. In such case we will disable the LVDS
4370                  * downclock feature.
4371                 */
4372                 has_reduced_clock = limit->find_pll(limit, crtc,
4373                                                     dev_priv->lvds_downclock,
4374                                                     refclk,
4375                                                     &clock,
4376                                                     &reduced_clock);
4377         }
4378         /* SDVO TV has fixed PLL values depend on its clock range,
4379            this mirrors vbios setting. */
4380         if (is_sdvo && is_tv) {
4381                 if (adjusted_mode->clock >= 100000
4382                     && adjusted_mode->clock < 140500) {
4383                         clock.p1 = 2;
4384                         clock.p2 = 10;
4385                         clock.n = 3;
4386                         clock.m1 = 16;
4387                         clock.m2 = 8;
4388                 } else if (adjusted_mode->clock >= 140500
4389                            && adjusted_mode->clock <= 200000) {
4390                         clock.p1 = 1;
4391                         clock.p2 = 10;
4392                         clock.n = 6;
4393                         clock.m1 = 12;
4394                         clock.m2 = 8;
4395                 }
4396         }
4397
4398         /* FDI link */
4399         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4400         lane = 0;
4401         /* CPU eDP doesn't require FDI link, so just set DP M/N
4402            according to current link config */
4403         if (is_cpu_edp) {
4404                 target_clock = mode->clock;
4405                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4406         } else {
4407                 /* [e]DP over FDI requires target mode clock
4408                    instead of link clock */
4409                 if (is_dp)
4410                         target_clock = mode->clock;
4411                 else
4412                         target_clock = adjusted_mode->clock;
4413
4414                 /* FDI is a binary signal running at ~2.7GHz, encoding
4415                  * each output octet as 10 bits. The actual frequency
4416                  * is stored as a divider into a 100MHz clock, and the
4417                  * mode pixel clock is stored in units of 1KHz.
4418                  * Hence the bw of each lane in terms of the mode signal
4419                  * is:
4420                  */
4421                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4422         }
4423
4424         /* determine panel color depth */
4425         temp = I915_READ(PIPECONF(pipe));
4426         temp &= ~PIPE_BPC_MASK;
4427         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4428         switch (pipe_bpp) {
4429         case 18:
4430                 temp |= PIPE_6BPC;
4431                 break;
4432         case 24:
4433                 temp |= PIPE_8BPC;
4434                 break;
4435         case 30:
4436                 temp |= PIPE_10BPC;
4437                 break;
4438         case 36:
4439                 temp |= PIPE_12BPC;
4440                 break;
4441         default:
4442                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4443                         pipe_bpp);
4444                 temp |= PIPE_8BPC;
4445                 pipe_bpp = 24;
4446                 break;
4447         }
4448
4449         intel_crtc->bpp = pipe_bpp;
4450         I915_WRITE(PIPECONF(pipe), temp);
4451
4452         if (!lane) {
4453                 /*
4454                  * Account for spread spectrum to avoid
4455                  * oversubscribing the link. Max center spread
4456                  * is 2.5%; use 5% for safety's sake.
4457                  */
4458                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4459                 lane = bps / (link_bw * 8) + 1;
4460         }
4461
4462         intel_crtc->fdi_lanes = lane;
4463
4464         if (pixel_multiplier > 1)
4465                 link_bw *= pixel_multiplier;
4466         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4467                              &m_n);
4468
4469         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4470         if (has_reduced_clock)
4471                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4472                         reduced_clock.m2;
4473
4474         /* Enable autotuning of the PLL clock (if permissible) */
4475         factor = 21;
4476         if (is_lvds) {
4477                 if ((intel_panel_use_ssc(dev_priv) &&
4478                      dev_priv->lvds_ssc_freq == 100) ||
4479                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4480                         factor = 25;
4481         } else if (is_sdvo && is_tv)
4482                 factor = 20;
4483
4484         if (clock.m < factor * clock.n)
4485                 fp |= FP_CB_TUNE;
4486
4487         dpll = 0;
4488
4489         if (is_lvds)
4490                 dpll |= DPLLB_MODE_LVDS;
4491         else
4492                 dpll |= DPLLB_MODE_DAC_SERIAL;
4493         if (is_sdvo) {
4494                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4495                 if (pixel_multiplier > 1) {
4496                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4497                 }
4498                 dpll |= DPLL_DVO_HIGH_SPEED;
4499         }
4500         if (is_dp && !is_cpu_edp)
4501                 dpll |= DPLL_DVO_HIGH_SPEED;
4502
4503         /* compute bitmask from p1 value */
4504         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4505         /* also FPA1 */
4506         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4507
4508         switch (clock.p2) {
4509         case 5:
4510                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4511                 break;
4512         case 7:
4513                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4514                 break;
4515         case 10:
4516                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4517                 break;
4518         case 14:
4519                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4520                 break;
4521         }
4522
4523         if (is_sdvo && is_tv)
4524                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4525         else if (is_tv)
4526                 /* XXX: just matching BIOS for now */
4527                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4528                 dpll |= 3;
4529         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4530                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4531         else
4532                 dpll |= PLL_REF_INPUT_DREFCLK;
4533
4534         /* setup pipeconf */
4535         pipeconf = I915_READ(PIPECONF(pipe));
4536
4537         /* Set up the display plane register */
4538         dspcntr = DISPPLANE_GAMMA_ENABLE;
4539
4540         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4541         drm_mode_debug_printmodeline(mode);
4542
4543         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4544          * pre-Haswell/LPT generation */
4545         if (HAS_PCH_LPT(dev)) {
4546                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4547                                 pipe);
4548         } else if (!is_cpu_edp) {
4549                 struct intel_pch_pll *pll;
4550
4551                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4552                 if (pll == NULL) {
4553                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4554                                          pipe);
4555                         return -EINVAL;
4556                 }
4557         } else
4558                 intel_put_pch_pll(intel_crtc);
4559
4560         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4561          * This is an exception to the general rule that mode_set doesn't turn
4562          * things on.
4563          */
4564         if (is_lvds) {
4565                 temp = I915_READ(PCH_LVDS);
4566                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4567                 if (HAS_PCH_CPT(dev)) {
4568                         temp &= ~PORT_TRANS_SEL_MASK;
4569                         temp |= PORT_TRANS_SEL_CPT(pipe);
4570                 } else {
4571                         if (pipe == 1)
4572                                 temp |= LVDS_PIPEB_SELECT;
4573                         else
4574                                 temp &= ~LVDS_PIPEB_SELECT;
4575                 }
4576
4577                 /* set the corresponsding LVDS_BORDER bit */
4578                 temp |= dev_priv->lvds_border_bits;
4579                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4580                  * set the DPLLs for dual-channel mode or not.
4581                  */
4582                 if (clock.p2 == 7)
4583                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4584                 else
4585                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4586
4587                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4588                  * appropriately here, but we need to look more thoroughly into how
4589                  * panels behave in the two modes.
4590                  */
4591                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4592                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4593                         temp |= LVDS_HSYNC_POLARITY;
4594                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4595                         temp |= LVDS_VSYNC_POLARITY;
4596                 I915_WRITE(PCH_LVDS, temp);
4597         }
4598
4599         pipeconf &= ~PIPECONF_DITHER_EN;
4600         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4601         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4602                 pipeconf |= PIPECONF_DITHER_EN;
4603                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4604         }
4605         if (is_dp && !is_cpu_edp) {
4606                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4607         } else {
4608                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4609                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4610                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4611                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4612                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4613         }
4614
4615         if (intel_crtc->pch_pll) {
4616                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4617
4618                 /* Wait for the clocks to stabilize. */
4619                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4620                 udelay(150);
4621
4622                 /* The pixel multiplier can only be updated once the
4623                  * DPLL is enabled and the clocks are stable.
4624                  *
4625                  * So write it again.
4626                  */
4627                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4628         }
4629
4630         intel_crtc->lowfreq_avail = false;
4631         if (intel_crtc->pch_pll) {
4632                 if (is_lvds && has_reduced_clock && i915_powersave) {
4633                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4634                         intel_crtc->lowfreq_avail = true;
4635                         if (HAS_PIPE_CXSR(dev)) {
4636                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4637                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4638                         }
4639                 } else {
4640                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4641                         if (HAS_PIPE_CXSR(dev)) {
4642                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4643                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4644                         }
4645                 }
4646         }
4647
4648         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4649         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4650                 pipeconf |= PIPECONF_INTERLACED_ILK;
4651                 /* the chip adds 2 halflines automatically */
4652                 adjusted_mode->crtc_vtotal -= 1;
4653                 adjusted_mode->crtc_vblank_end -= 1;
4654                 I915_WRITE(VSYNCSHIFT(pipe),
4655                            adjusted_mode->crtc_hsync_start
4656                            - adjusted_mode->crtc_htotal/2);
4657         } else {
4658                 pipeconf |= PIPECONF_PROGRESSIVE;
4659                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4660         }
4661
4662         I915_WRITE(HTOTAL(pipe),
4663                    (adjusted_mode->crtc_hdisplay - 1) |
4664                    ((adjusted_mode->crtc_htotal - 1) << 16));
4665         I915_WRITE(HBLANK(pipe),
4666                    (adjusted_mode->crtc_hblank_start - 1) |
4667                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4668         I915_WRITE(HSYNC(pipe),
4669                    (adjusted_mode->crtc_hsync_start - 1) |
4670                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4671
4672         I915_WRITE(VTOTAL(pipe),
4673                    (adjusted_mode->crtc_vdisplay - 1) |
4674                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4675         I915_WRITE(VBLANK(pipe),
4676                    (adjusted_mode->crtc_vblank_start - 1) |
4677                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4678         I915_WRITE(VSYNC(pipe),
4679                    (adjusted_mode->crtc_vsync_start - 1) |
4680                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4681
4682         /* pipesrc controls the size that is scaled from, which should
4683          * always be the user's requested size.
4684          */
4685         I915_WRITE(PIPESRC(pipe),
4686                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4687
4688         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4689         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4690         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4691         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4692
4693         if (is_cpu_edp)
4694                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4695
4696         I915_WRITE(PIPECONF(pipe), pipeconf);
4697         POSTING_READ(PIPECONF(pipe));
4698
4699         intel_wait_for_vblank(dev, pipe);
4700
4701         I915_WRITE(DSPCNTR(plane), dspcntr);
4702         POSTING_READ(DSPCNTR(plane));
4703
4704         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4705
4706         intel_update_watermarks(dev);
4707
4708         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4709
4710         return ret;
4711 }
4712
4713 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4714                                struct drm_display_mode *mode,
4715                                struct drm_display_mode *adjusted_mode,
4716                                int x, int y,
4717                                struct drm_framebuffer *old_fb)
4718 {
4719         struct drm_device *dev = crtc->dev;
4720         struct drm_i915_private *dev_priv = dev->dev_private;
4721         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4722         int pipe = intel_crtc->pipe;
4723         int ret;
4724
4725         drm_vblank_pre_modeset(dev, pipe);
4726
4727         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4728                                               x, y, old_fb);
4729         drm_vblank_post_modeset(dev, pipe);
4730
4731         if (ret)
4732                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4733         else
4734                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4735
4736         return ret;
4737 }
4738
4739 static bool intel_eld_uptodate(struct drm_connector *connector,
4740                                int reg_eldv, uint32_t bits_eldv,
4741                                int reg_elda, uint32_t bits_elda,
4742                                int reg_edid)
4743 {
4744         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4745         uint8_t *eld = connector->eld;
4746         uint32_t i;
4747
4748         i = I915_READ(reg_eldv);
4749         i &= bits_eldv;
4750
4751         if (!eld[0])
4752                 return !i;
4753
4754         if (!i)
4755                 return false;
4756
4757         i = I915_READ(reg_elda);
4758         i &= ~bits_elda;
4759         I915_WRITE(reg_elda, i);
4760
4761         for (i = 0; i < eld[2]; i++)
4762                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4763                         return false;
4764
4765         return true;
4766 }
4767
4768 static void g4x_write_eld(struct drm_connector *connector,
4769                           struct drm_crtc *crtc)
4770 {
4771         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4772         uint8_t *eld = connector->eld;
4773         uint32_t eldv;
4774         uint32_t len;
4775         uint32_t i;
4776
4777         i = I915_READ(G4X_AUD_VID_DID);
4778
4779         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4780                 eldv = G4X_ELDV_DEVCL_DEVBLC;
4781         else
4782                 eldv = G4X_ELDV_DEVCTG;
4783
4784         if (intel_eld_uptodate(connector,
4785                                G4X_AUD_CNTL_ST, eldv,
4786                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4787                                G4X_HDMIW_HDMIEDID))
4788                 return;
4789
4790         i = I915_READ(G4X_AUD_CNTL_ST);
4791         i &= ~(eldv | G4X_ELD_ADDR);
4792         len = (i >> 9) & 0x1f;          /* ELD buffer size */
4793         I915_WRITE(G4X_AUD_CNTL_ST, i);
4794
4795         if (!eld[0])
4796                 return;
4797
4798         len = min_t(uint8_t, eld[2], len);
4799         DRM_DEBUG_DRIVER("ELD size %d\n", len);
4800         for (i = 0; i < len; i++)
4801                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4802
4803         i = I915_READ(G4X_AUD_CNTL_ST);
4804         i |= eldv;
4805         I915_WRITE(G4X_AUD_CNTL_ST, i);
4806 }
4807
4808 static void ironlake_write_eld(struct drm_connector *connector,
4809                                      struct drm_crtc *crtc)
4810 {
4811         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4812         uint8_t *eld = connector->eld;
4813         uint32_t eldv;
4814         uint32_t i;
4815         int len;
4816         int hdmiw_hdmiedid;
4817         int aud_config;
4818         int aud_cntl_st;
4819         int aud_cntrl_st2;
4820
4821         if (HAS_PCH_IBX(connector->dev)) {
4822                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4823                 aud_config = IBX_AUD_CONFIG_A;
4824                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4825                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4826         } else {
4827                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4828                 aud_config = CPT_AUD_CONFIG_A;
4829                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4830                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4831         }
4832
4833         i = to_intel_crtc(crtc)->pipe;
4834         hdmiw_hdmiedid += i * 0x100;
4835         aud_cntl_st += i * 0x100;
4836         aud_config += i * 0x100;
4837
4838         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4839
4840         i = I915_READ(aud_cntl_st);
4841         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
4842         if (!i) {
4843                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4844                 /* operate blindly on all ports */
4845                 eldv = IBX_ELD_VALIDB;
4846                 eldv |= IBX_ELD_VALIDB << 4;
4847                 eldv |= IBX_ELD_VALIDB << 8;
4848         } else {
4849                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4850                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4851         }
4852
4853         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4854                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4855                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
4856                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4857         } else
4858                 I915_WRITE(aud_config, 0);
4859
4860         if (intel_eld_uptodate(connector,
4861                                aud_cntrl_st2, eldv,
4862                                aud_cntl_st, IBX_ELD_ADDRESS,
4863                                hdmiw_hdmiedid))
4864                 return;
4865
4866         i = I915_READ(aud_cntrl_st2);
4867         i &= ~eldv;
4868         I915_WRITE(aud_cntrl_st2, i);
4869
4870         if (!eld[0])
4871                 return;
4872
4873         i = I915_READ(aud_cntl_st);
4874         i &= ~IBX_ELD_ADDRESS;
4875         I915_WRITE(aud_cntl_st, i);
4876
4877         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
4878         DRM_DEBUG_DRIVER("ELD size %d\n", len);
4879         for (i = 0; i < len; i++)
4880                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4881
4882         i = I915_READ(aud_cntrl_st2);
4883         i |= eldv;
4884         I915_WRITE(aud_cntrl_st2, i);
4885 }
4886
4887 void intel_write_eld(struct drm_encoder *encoder,
4888                      struct drm_display_mode *mode)
4889 {
4890         struct drm_crtc *crtc = encoder->crtc;
4891         struct drm_connector *connector;
4892         struct drm_device *dev = encoder->dev;
4893         struct drm_i915_private *dev_priv = dev->dev_private;
4894
4895         connector = drm_select_eld(encoder, mode);
4896         if (!connector)
4897                 return;
4898
4899         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4900                          connector->base.id,
4901                          drm_get_connector_name(connector),
4902                          connector->encoder->base.id,
4903                          drm_get_encoder_name(connector->encoder));
4904
4905         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4906
4907         if (dev_priv->display.write_eld)
4908                 dev_priv->display.write_eld(connector, crtc);
4909 }
4910
4911 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4912 void intel_crtc_load_lut(struct drm_crtc *crtc)
4913 {
4914         struct drm_device *dev = crtc->dev;
4915         struct drm_i915_private *dev_priv = dev->dev_private;
4916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4917         int palreg = PALETTE(intel_crtc->pipe);
4918         int i;
4919
4920         /* The clocks have to be on to load the palette. */
4921         if (!crtc->enabled || !intel_crtc->active)
4922                 return;
4923
4924         /* use legacy palette for Ironlake */
4925         if (HAS_PCH_SPLIT(dev))
4926                 palreg = LGC_PALETTE(intel_crtc->pipe);
4927
4928         for (i = 0; i < 256; i++) {
4929                 I915_WRITE(palreg + 4 * i,
4930                            (intel_crtc->lut_r[i] << 16) |
4931                            (intel_crtc->lut_g[i] << 8) |
4932                            intel_crtc->lut_b[i]);
4933         }
4934 }
4935
4936 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4937 {
4938         struct drm_device *dev = crtc->dev;
4939         struct drm_i915_private *dev_priv = dev->dev_private;
4940         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4941         bool visible = base != 0;
4942         u32 cntl;
4943
4944         if (intel_crtc->cursor_visible == visible)
4945                 return;
4946
4947         cntl = I915_READ(_CURACNTR);
4948         if (visible) {
4949                 /* On these chipsets we can only modify the base whilst
4950                  * the cursor is disabled.
4951                  */
4952                 I915_WRITE(_CURABASE, base);
4953
4954                 cntl &= ~(CURSOR_FORMAT_MASK);
4955                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4956                 cntl |= CURSOR_ENABLE |
4957                         CURSOR_GAMMA_ENABLE |
4958                         CURSOR_FORMAT_ARGB;
4959         } else
4960                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4961         I915_WRITE(_CURACNTR, cntl);
4962
4963         intel_crtc->cursor_visible = visible;
4964 }
4965
4966 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4967 {
4968         struct drm_device *dev = crtc->dev;
4969         struct drm_i915_private *dev_priv = dev->dev_private;
4970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4971         int pipe = intel_crtc->pipe;
4972         bool visible = base != 0;
4973
4974         if (intel_crtc->cursor_visible != visible) {
4975                 uint32_t cntl = I915_READ(CURCNTR(pipe));
4976                 if (base) {
4977                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4978                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4979                         cntl |= pipe << 28; /* Connect to correct pipe */
4980                 } else {
4981                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4982                         cntl |= CURSOR_MODE_DISABLE;
4983                 }
4984                 I915_WRITE(CURCNTR(pipe), cntl);
4985
4986                 intel_crtc->cursor_visible = visible;
4987         }
4988         /* and commit changes on next vblank */
4989         I915_WRITE(CURBASE(pipe), base);
4990 }
4991
4992 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4993 {
4994         struct drm_device *dev = crtc->dev;
4995         struct drm_i915_private *dev_priv = dev->dev_private;
4996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4997         int pipe = intel_crtc->pipe;
4998         bool visible = base != 0;
4999
5000         if (intel_crtc->cursor_visible != visible) {
5001                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5002                 if (base) {
5003                         cntl &= ~CURSOR_MODE;
5004                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5005                 } else {
5006                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5007                         cntl |= CURSOR_MODE_DISABLE;
5008                 }
5009                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5010
5011                 intel_crtc->cursor_visible = visible;
5012         }
5013         /* and commit changes on next vblank */
5014         I915_WRITE(CURBASE_IVB(pipe), base);
5015 }
5016
5017 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5018 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5019                                      bool on)
5020 {
5021         struct drm_device *dev = crtc->dev;
5022         struct drm_i915_private *dev_priv = dev->dev_private;
5023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5024         int pipe = intel_crtc->pipe;
5025         int x = intel_crtc->cursor_x;
5026         int y = intel_crtc->cursor_y;
5027         u32 base, pos;
5028         bool visible;
5029
5030         pos = 0;
5031
5032         if (on && crtc->enabled && crtc->fb) {
5033                 base = intel_crtc->cursor_addr;
5034                 if (x > (int) crtc->fb->width)
5035                         base = 0;
5036
5037                 if (y > (int) crtc->fb->height)
5038                         base = 0;
5039         } else
5040                 base = 0;
5041
5042         if (x < 0) {
5043                 if (x + intel_crtc->cursor_width < 0)
5044                         base = 0;
5045
5046                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5047                 x = -x;
5048         }
5049         pos |= x << CURSOR_X_SHIFT;
5050
5051         if (y < 0) {
5052                 if (y + intel_crtc->cursor_height < 0)
5053                         base = 0;
5054
5055                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5056                 y = -y;
5057         }
5058         pos |= y << CURSOR_Y_SHIFT;
5059
5060         visible = base != 0;
5061         if (!visible && !intel_crtc->cursor_visible)
5062                 return;
5063
5064         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5065                 I915_WRITE(CURPOS_IVB(pipe), pos);
5066                 ivb_update_cursor(crtc, base);
5067         } else {
5068                 I915_WRITE(CURPOS(pipe), pos);
5069                 if (IS_845G(dev) || IS_I865G(dev))
5070                         i845_update_cursor(crtc, base);
5071                 else
5072                         i9xx_update_cursor(crtc, base);
5073         }
5074 }
5075
5076 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5077                                  struct drm_file *file,
5078                                  uint32_t handle,
5079                                  uint32_t width, uint32_t height)
5080 {
5081         struct drm_device *dev = crtc->dev;
5082         struct drm_i915_private *dev_priv = dev->dev_private;
5083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5084         struct drm_i915_gem_object *obj;
5085         uint32_t addr;
5086         int ret;
5087
5088         DRM_DEBUG_KMS("\n");
5089
5090         /* if we want to turn off the cursor ignore width and height */
5091         if (!handle) {
5092                 DRM_DEBUG_KMS("cursor off\n");
5093                 addr = 0;
5094                 obj = NULL;
5095                 mutex_lock(&dev->struct_mutex);
5096                 goto finish;
5097         }
5098
5099         /* Currently we only support 64x64 cursors */
5100         if (width != 64 || height != 64) {
5101                 DRM_ERROR("we currently only support 64x64 cursors\n");
5102                 return -EINVAL;
5103         }
5104
5105         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5106         if (&obj->base == NULL)
5107                 return -ENOENT;
5108
5109         if (obj->base.size < width * height * 4) {
5110                 DRM_ERROR("buffer is to small\n");
5111                 ret = -ENOMEM;
5112                 goto fail;
5113         }
5114
5115         /* we only need to pin inside GTT if cursor is non-phy */
5116         mutex_lock(&dev->struct_mutex);
5117         if (!dev_priv->info->cursor_needs_physical) {
5118                 if (obj->tiling_mode) {
5119                         DRM_ERROR("cursor cannot be tiled\n");
5120                         ret = -EINVAL;
5121                         goto fail_locked;
5122                 }
5123
5124                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5125                 if (ret) {
5126                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5127                         goto fail_locked;
5128                 }
5129
5130                 ret = i915_gem_object_put_fence(obj);
5131                 if (ret) {
5132                         DRM_ERROR("failed to release fence for cursor");
5133                         goto fail_unpin;
5134                 }
5135
5136                 addr = obj->gtt_offset;
5137         } else {
5138                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5139                 ret = i915_gem_attach_phys_object(dev, obj,
5140                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5141                                                   align);
5142                 if (ret) {
5143                         DRM_ERROR("failed to attach phys object\n");
5144                         goto fail_locked;
5145                 }
5146                 addr = obj->phys_obj->handle->busaddr;
5147         }
5148
5149         if (IS_GEN2(dev))
5150                 I915_WRITE(CURSIZE, (height << 12) | width);
5151
5152  finish:
5153         if (intel_crtc->cursor_bo) {
5154                 if (dev_priv->info->cursor_needs_physical) {
5155                         if (intel_crtc->cursor_bo != obj)
5156                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5157                 } else
5158                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5159                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5160         }
5161
5162         mutex_unlock(&dev->struct_mutex);
5163
5164         intel_crtc->cursor_addr = addr;
5165         intel_crtc->cursor_bo = obj;
5166         intel_crtc->cursor_width = width;
5167         intel_crtc->cursor_height = height;
5168
5169         intel_crtc_update_cursor(crtc, true);
5170
5171         return 0;
5172 fail_unpin:
5173         i915_gem_object_unpin(obj);
5174 fail_locked:
5175         mutex_unlock(&dev->struct_mutex);
5176 fail:
5177         drm_gem_object_unreference_unlocked(&obj->base);
5178         return ret;
5179 }
5180
5181 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5182 {
5183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5184
5185         intel_crtc->cursor_x = x;
5186         intel_crtc->cursor_y = y;
5187
5188         intel_crtc_update_cursor(crtc, true);
5189
5190         return 0;
5191 }
5192
5193 /** Sets the color ramps on behalf of RandR */
5194 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5195                                  u16 blue, int regno)
5196 {
5197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5198
5199         intel_crtc->lut_r[regno] = red >> 8;
5200         intel_crtc->lut_g[regno] = green >> 8;
5201         intel_crtc->lut_b[regno] = blue >> 8;
5202 }
5203
5204 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5205                              u16 *blue, int regno)
5206 {
5207         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5208
5209         *red = intel_crtc->lut_r[regno] << 8;
5210         *green = intel_crtc->lut_g[regno] << 8;
5211         *blue = intel_crtc->lut_b[regno] << 8;
5212 }
5213
5214 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5215                                  u16 *blue, uint32_t start, uint32_t size)
5216 {
5217         int end = (start + size > 256) ? 256 : start + size, i;
5218         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5219
5220         for (i = start; i < end; i++) {
5221                 intel_crtc->lut_r[i] = red[i] >> 8;
5222                 intel_crtc->lut_g[i] = green[i] >> 8;
5223                 intel_crtc->lut_b[i] = blue[i] >> 8;
5224         }
5225
5226         intel_crtc_load_lut(crtc);
5227 }
5228
5229 /**
5230  * Get a pipe with a simple mode set on it for doing load-based monitor
5231  * detection.
5232  *
5233  * It will be up to the load-detect code to adjust the pipe as appropriate for
5234  * its requirements.  The pipe will be connected to no other encoders.
5235  *
5236  * Currently this code will only succeed if there is a pipe with no encoders
5237  * configured for it.  In the future, it could choose to temporarily disable
5238  * some outputs to free up a pipe for its use.
5239  *
5240  * \return crtc, or NULL if no pipes are available.
5241  */
5242
5243 /* VESA 640x480x72Hz mode to set on the pipe */
5244 static struct drm_display_mode load_detect_mode = {
5245         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5246                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5247 };
5248
5249 static struct drm_framebuffer *
5250 intel_framebuffer_create(struct drm_device *dev,
5251                          struct drm_mode_fb_cmd2 *mode_cmd,
5252                          struct drm_i915_gem_object *obj)
5253 {
5254         struct intel_framebuffer *intel_fb;
5255         int ret;
5256
5257         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5258         if (!intel_fb) {
5259                 drm_gem_object_unreference_unlocked(&obj->base);
5260                 return ERR_PTR(-ENOMEM);
5261         }
5262
5263         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5264         if (ret) {
5265                 drm_gem_object_unreference_unlocked(&obj->base);
5266                 kfree(intel_fb);
5267                 return ERR_PTR(ret);
5268         }
5269
5270         return &intel_fb->base;
5271 }
5272
5273 static u32
5274 intel_framebuffer_pitch_for_width(int width, int bpp)
5275 {
5276         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5277         return ALIGN(pitch, 64);
5278 }
5279
5280 static u32
5281 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5282 {
5283         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5284         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5285 }
5286
5287 static struct drm_framebuffer *
5288 intel_framebuffer_create_for_mode(struct drm_device *dev,
5289                                   struct drm_display_mode *mode,
5290                                   int depth, int bpp)
5291 {
5292         struct drm_i915_gem_object *obj;
5293         struct drm_mode_fb_cmd2 mode_cmd;
5294
5295         obj = i915_gem_alloc_object(dev,
5296                                     intel_framebuffer_size_for_mode(mode, bpp));
5297         if (obj == NULL)
5298                 return ERR_PTR(-ENOMEM);
5299
5300         mode_cmd.width = mode->hdisplay;
5301         mode_cmd.height = mode->vdisplay;
5302         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5303                                                                 bpp);
5304         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5305
5306         return intel_framebuffer_create(dev, &mode_cmd, obj);
5307 }
5308
5309 static struct drm_framebuffer *
5310 mode_fits_in_fbdev(struct drm_device *dev,
5311                    struct drm_display_mode *mode)
5312 {
5313         struct drm_i915_private *dev_priv = dev->dev_private;
5314         struct drm_i915_gem_object *obj;
5315         struct drm_framebuffer *fb;
5316
5317         if (dev_priv->fbdev == NULL)
5318                 return NULL;
5319
5320         obj = dev_priv->fbdev->ifb.obj;
5321         if (obj == NULL)
5322                 return NULL;
5323
5324         fb = &dev_priv->fbdev->ifb.base;
5325         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5326                                                                fb->bits_per_pixel))
5327                 return NULL;
5328
5329         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5330                 return NULL;
5331
5332         return fb;
5333 }
5334
5335 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5336                                 struct drm_connector *connector,
5337                                 struct drm_display_mode *mode,
5338                                 struct intel_load_detect_pipe *old)
5339 {
5340         struct intel_crtc *intel_crtc;
5341         struct drm_crtc *possible_crtc;
5342         struct drm_encoder *encoder = &intel_encoder->base;
5343         struct drm_crtc *crtc = NULL;
5344         struct drm_device *dev = encoder->dev;
5345         struct drm_framebuffer *old_fb;
5346         int i = -1;
5347
5348         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5349                       connector->base.id, drm_get_connector_name(connector),
5350                       encoder->base.id, drm_get_encoder_name(encoder));
5351
5352         /*
5353          * Algorithm gets a little messy:
5354          *
5355          *   - if the connector already has an assigned crtc, use it (but make
5356          *     sure it's on first)
5357          *
5358          *   - try to find the first unused crtc that can drive this connector,
5359          *     and use that if we find one
5360          */
5361
5362         /* See if we already have a CRTC for this connector */
5363         if (encoder->crtc) {
5364                 crtc = encoder->crtc;
5365
5366                 intel_crtc = to_intel_crtc(crtc);
5367                 old->dpms_mode = intel_crtc->dpms_mode;
5368                 old->load_detect_temp = false;
5369
5370                 /* Make sure the crtc and connector are running */
5371                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5372                         struct drm_encoder_helper_funcs *encoder_funcs;
5373                         struct drm_crtc_helper_funcs *crtc_funcs;
5374
5375                         crtc_funcs = crtc->helper_private;
5376                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5377
5378                         encoder_funcs = encoder->helper_private;
5379                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5380                 }
5381
5382                 return true;
5383         }
5384
5385         /* Find an unused one (if possible) */
5386         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5387                 i++;
5388                 if (!(encoder->possible_crtcs & (1 << i)))
5389                         continue;
5390                 if (!possible_crtc->enabled) {
5391                         crtc = possible_crtc;
5392                         break;
5393                 }
5394         }
5395
5396         /*
5397          * If we didn't find an unused CRTC, don't use any.
5398          */
5399         if (!crtc) {
5400                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5401                 return false;
5402         }
5403
5404         encoder->crtc = crtc;
5405         connector->encoder = encoder;
5406
5407         intel_crtc = to_intel_crtc(crtc);
5408         old->dpms_mode = intel_crtc->dpms_mode;
5409         old->load_detect_temp = true;
5410         old->release_fb = NULL;
5411
5412         if (!mode)
5413                 mode = &load_detect_mode;
5414
5415         old_fb = crtc->fb;
5416
5417         /* We need a framebuffer large enough to accommodate all accesses
5418          * that the plane may generate whilst we perform load detection.
5419          * We can not rely on the fbcon either being present (we get called
5420          * during its initialisation to detect all boot displays, or it may
5421          * not even exist) or that it is large enough to satisfy the
5422          * requested mode.
5423          */
5424         crtc->fb = mode_fits_in_fbdev(dev, mode);
5425         if (crtc->fb == NULL) {
5426                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5427                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5428                 old->release_fb = crtc->fb;
5429         } else
5430                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5431         if (IS_ERR(crtc->fb)) {
5432                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5433                 crtc->fb = old_fb;
5434                 return false;
5435         }
5436
5437         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5438                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5439                 if (old->release_fb)
5440                         old->release_fb->funcs->destroy(old->release_fb);
5441                 crtc->fb = old_fb;
5442                 return false;
5443         }
5444
5445         /* let the connector get through one full cycle before testing */
5446         intel_wait_for_vblank(dev, intel_crtc->pipe);
5447
5448         return true;
5449 }
5450
5451 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5452                                     struct drm_connector *connector,
5453                                     struct intel_load_detect_pipe *old)
5454 {
5455         struct drm_encoder *encoder = &intel_encoder->base;
5456         struct drm_device *dev = encoder->dev;
5457         struct drm_crtc *crtc = encoder->crtc;
5458         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5459         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5460
5461         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5462                       connector->base.id, drm_get_connector_name(connector),
5463                       encoder->base.id, drm_get_encoder_name(encoder));
5464
5465         if (old->load_detect_temp) {
5466                 connector->encoder = NULL;
5467                 drm_helper_disable_unused_functions(dev);
5468
5469                 if (old->release_fb)
5470                         old->release_fb->funcs->destroy(old->release_fb);
5471
5472                 return;
5473         }
5474
5475         /* Switch crtc and encoder back off if necessary */
5476         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5477                 encoder_funcs->dpms(encoder, old->dpms_mode);
5478                 crtc_funcs->dpms(crtc, old->dpms_mode);
5479         }
5480 }
5481
5482 /* Returns the clock of the currently programmed mode of the given pipe. */
5483 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5484 {
5485         struct drm_i915_private *dev_priv = dev->dev_private;
5486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5487         int pipe = intel_crtc->pipe;
5488         u32 dpll = I915_READ(DPLL(pipe));
5489         u32 fp;
5490         intel_clock_t clock;
5491
5492         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5493                 fp = I915_READ(FP0(pipe));
5494         else
5495                 fp = I915_READ(FP1(pipe));
5496
5497         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5498         if (IS_PINEVIEW(dev)) {
5499                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5500                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5501         } else {
5502                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5503                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5504         }
5505
5506         if (!IS_GEN2(dev)) {
5507                 if (IS_PINEVIEW(dev))
5508                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5509                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5510                 else
5511                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5512                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5513
5514                 switch (dpll & DPLL_MODE_MASK) {
5515                 case DPLLB_MODE_DAC_SERIAL:
5516                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5517                                 5 : 10;
5518                         break;
5519                 case DPLLB_MODE_LVDS:
5520                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5521                                 7 : 14;
5522                         break;
5523                 default:
5524                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5525                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5526                         return 0;
5527                 }
5528
5529                 /* XXX: Handle the 100Mhz refclk */
5530                 intel_clock(dev, 96000, &clock);
5531         } else {
5532                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5533
5534                 if (is_lvds) {
5535                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5536                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5537                         clock.p2 = 14;
5538
5539                         if ((dpll & PLL_REF_INPUT_MASK) ==
5540                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5541                                 /* XXX: might not be 66MHz */
5542                                 intel_clock(dev, 66000, &clock);
5543                         } else
5544                                 intel_clock(dev, 48000, &clock);
5545                 } else {
5546                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5547                                 clock.p1 = 2;
5548                         else {
5549                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5550                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5551                         }
5552                         if (dpll & PLL_P2_DIVIDE_BY_4)
5553                                 clock.p2 = 4;
5554                         else
5555                                 clock.p2 = 2;
5556
5557                         intel_clock(dev, 48000, &clock);
5558                 }
5559         }
5560
5561         /* XXX: It would be nice to validate the clocks, but we can't reuse
5562          * i830PllIsValid() because it relies on the xf86_config connector
5563          * configuration being accurate, which it isn't necessarily.
5564          */
5565
5566         return clock.dot;
5567 }
5568
5569 /** Returns the currently programmed mode of the given pipe. */
5570 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5571                                              struct drm_crtc *crtc)
5572 {
5573         struct drm_i915_private *dev_priv = dev->dev_private;
5574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5575         int pipe = intel_crtc->pipe;
5576         struct drm_display_mode *mode;
5577         int htot = I915_READ(HTOTAL(pipe));
5578         int hsync = I915_READ(HSYNC(pipe));
5579         int vtot = I915_READ(VTOTAL(pipe));
5580         int vsync = I915_READ(VSYNC(pipe));
5581
5582         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5583         if (!mode)
5584                 return NULL;
5585
5586         mode->clock = intel_crtc_clock_get(dev, crtc);
5587         mode->hdisplay = (htot & 0xffff) + 1;
5588         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5589         mode->hsync_start = (hsync & 0xffff) + 1;
5590         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5591         mode->vdisplay = (vtot & 0xffff) + 1;
5592         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5593         mode->vsync_start = (vsync & 0xffff) + 1;
5594         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5595
5596         drm_mode_set_name(mode);
5597
5598         return mode;
5599 }
5600
5601 #define GPU_IDLE_TIMEOUT 500 /* ms */
5602
5603 /* When this timer fires, we've been idle for awhile */
5604 static void intel_gpu_idle_timer(unsigned long arg)
5605 {
5606         struct drm_device *dev = (struct drm_device *)arg;
5607         drm_i915_private_t *dev_priv = dev->dev_private;
5608
5609         if (!list_empty(&dev_priv->mm.active_list)) {
5610                 /* Still processing requests, so just re-arm the timer. */
5611                 mod_timer(&dev_priv->idle_timer, jiffies +
5612                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5613                 return;
5614         }
5615
5616         dev_priv->busy = false;
5617         queue_work(dev_priv->wq, &dev_priv->idle_work);
5618 }
5619
5620 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5621
5622 static void intel_crtc_idle_timer(unsigned long arg)
5623 {
5624         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5625         struct drm_crtc *crtc = &intel_crtc->base;
5626         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5627         struct intel_framebuffer *intel_fb;
5628
5629         intel_fb = to_intel_framebuffer(crtc->fb);
5630         if (intel_fb && intel_fb->obj->active) {
5631                 /* The framebuffer is still being accessed by the GPU. */
5632                 mod_timer(&intel_crtc->idle_timer, jiffies +
5633                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5634                 return;
5635         }
5636
5637         intel_crtc->busy = false;
5638         queue_work(dev_priv->wq, &dev_priv->idle_work);
5639 }
5640
5641 static void intel_increase_pllclock(struct drm_crtc *crtc)
5642 {
5643         struct drm_device *dev = crtc->dev;
5644         drm_i915_private_t *dev_priv = dev->dev_private;
5645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5646         int pipe = intel_crtc->pipe;
5647         int dpll_reg = DPLL(pipe);
5648         int dpll;
5649
5650         if (HAS_PCH_SPLIT(dev))
5651                 return;
5652
5653         if (!dev_priv->lvds_downclock_avail)
5654                 return;
5655
5656         dpll = I915_READ(dpll_reg);
5657         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5658                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5659
5660                 assert_panel_unlocked(dev_priv, pipe);
5661
5662                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5663                 I915_WRITE(dpll_reg, dpll);
5664                 intel_wait_for_vblank(dev, pipe);
5665
5666                 dpll = I915_READ(dpll_reg);
5667                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5668                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5669         }
5670
5671         /* Schedule downclock */
5672         mod_timer(&intel_crtc->idle_timer, jiffies +
5673                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5674 }
5675
5676 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5677 {
5678         struct drm_device *dev = crtc->dev;
5679         drm_i915_private_t *dev_priv = dev->dev_private;
5680         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5681
5682         if (HAS_PCH_SPLIT(dev))
5683                 return;
5684
5685         if (!dev_priv->lvds_downclock_avail)
5686                 return;
5687
5688         /*
5689          * Since this is called by a timer, we should never get here in
5690          * the manual case.
5691          */
5692         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5693                 int pipe = intel_crtc->pipe;
5694                 int dpll_reg = DPLL(pipe);
5695                 int dpll;
5696
5697                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5698
5699                 assert_panel_unlocked(dev_priv, pipe);
5700
5701                 dpll = I915_READ(dpll_reg);
5702                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5703                 I915_WRITE(dpll_reg, dpll);
5704                 intel_wait_for_vblank(dev, pipe);
5705                 dpll = I915_READ(dpll_reg);
5706                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5707                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5708         }
5709
5710 }
5711
5712 /**
5713  * intel_idle_update - adjust clocks for idleness
5714  * @work: work struct
5715  *
5716  * Either the GPU or display (or both) went idle.  Check the busy status
5717  * here and adjust the CRTC and GPU clocks as necessary.
5718  */
5719 static void intel_idle_update(struct work_struct *work)
5720 {
5721         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5722                                                     idle_work);
5723         struct drm_device *dev = dev_priv->dev;
5724         struct drm_crtc *crtc;
5725         struct intel_crtc *intel_crtc;
5726
5727         if (!i915_powersave)
5728                 return;
5729
5730         mutex_lock(&dev->struct_mutex);
5731
5732         i915_update_gfx_val(dev_priv);
5733
5734         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5735                 /* Skip inactive CRTCs */
5736                 if (!crtc->fb)
5737                         continue;
5738
5739                 intel_crtc = to_intel_crtc(crtc);
5740                 if (!intel_crtc->busy)
5741                         intel_decrease_pllclock(crtc);
5742         }
5743
5744
5745         mutex_unlock(&dev->struct_mutex);
5746 }
5747
5748 /**
5749  * intel_mark_busy - mark the GPU and possibly the display busy
5750  * @dev: drm device
5751  * @obj: object we're operating on
5752  *
5753  * Callers can use this function to indicate that the GPU is busy processing
5754  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5755  * buffer), we'll also mark the display as busy, so we know to increase its
5756  * clock frequency.
5757  */
5758 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5759 {
5760         drm_i915_private_t *dev_priv = dev->dev_private;
5761         struct drm_crtc *crtc = NULL;
5762         struct intel_framebuffer *intel_fb;
5763         struct intel_crtc *intel_crtc;
5764
5765         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5766                 return;
5767
5768         if (!dev_priv->busy) {
5769                 intel_sanitize_pm(dev);
5770                 dev_priv->busy = true;
5771         } else
5772                 mod_timer(&dev_priv->idle_timer, jiffies +
5773                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5774
5775         if (obj == NULL)
5776                 return;
5777
5778         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5779                 if (!crtc->fb)
5780                         continue;
5781
5782                 intel_crtc = to_intel_crtc(crtc);
5783                 intel_fb = to_intel_framebuffer(crtc->fb);
5784                 if (intel_fb->obj == obj) {
5785                         if (!intel_crtc->busy) {
5786                                 /* Non-busy -> busy, upclock */
5787                                 intel_increase_pllclock(crtc);
5788                                 intel_crtc->busy = true;
5789                         } else {
5790                                 /* Busy -> busy, put off timer */
5791                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5792                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5793                         }
5794                 }
5795         }
5796 }
5797
5798 static void intel_crtc_destroy(struct drm_crtc *crtc)
5799 {
5800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5801         struct drm_device *dev = crtc->dev;
5802         struct intel_unpin_work *work;
5803         unsigned long flags;
5804
5805         spin_lock_irqsave(&dev->event_lock, flags);
5806         work = intel_crtc->unpin_work;
5807         intel_crtc->unpin_work = NULL;
5808         spin_unlock_irqrestore(&dev->event_lock, flags);
5809
5810         if (work) {
5811                 cancel_work_sync(&work->work);
5812                 kfree(work);
5813         }
5814
5815         drm_crtc_cleanup(crtc);
5816
5817         kfree(intel_crtc);
5818 }
5819
5820 static void intel_unpin_work_fn(struct work_struct *__work)
5821 {
5822         struct intel_unpin_work *work =
5823                 container_of(__work, struct intel_unpin_work, work);
5824
5825         mutex_lock(&work->dev->struct_mutex);
5826         intel_unpin_fb_obj(work->old_fb_obj);
5827         drm_gem_object_unreference(&work->pending_flip_obj->base);
5828         drm_gem_object_unreference(&work->old_fb_obj->base);
5829
5830         intel_update_fbc(work->dev);
5831         mutex_unlock(&work->dev->struct_mutex);
5832         kfree(work);
5833 }
5834
5835 static void do_intel_finish_page_flip(struct drm_device *dev,
5836                                       struct drm_crtc *crtc)
5837 {
5838         drm_i915_private_t *dev_priv = dev->dev_private;
5839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5840         struct intel_unpin_work *work;
5841         struct drm_i915_gem_object *obj;
5842         struct drm_pending_vblank_event *e;
5843         struct timeval tnow, tvbl;
5844         unsigned long flags;
5845
5846         /* Ignore early vblank irqs */
5847         if (intel_crtc == NULL)
5848                 return;
5849
5850         do_gettimeofday(&tnow);
5851
5852         spin_lock_irqsave(&dev->event_lock, flags);
5853         work = intel_crtc->unpin_work;
5854         if (work == NULL || !work->pending) {
5855                 spin_unlock_irqrestore(&dev->event_lock, flags);
5856                 return;
5857         }
5858
5859         intel_crtc->unpin_work = NULL;
5860
5861         if (work->event) {
5862                 e = work->event;
5863                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5864
5865                 /* Called before vblank count and timestamps have
5866                  * been updated for the vblank interval of flip
5867                  * completion? Need to increment vblank count and
5868                  * add one videorefresh duration to returned timestamp
5869                  * to account for this. We assume this happened if we
5870                  * get called over 0.9 frame durations after the last
5871                  * timestamped vblank.
5872                  *
5873                  * This calculation can not be used with vrefresh rates
5874                  * below 5Hz (10Hz to be on the safe side) without
5875                  * promoting to 64 integers.
5876                  */
5877                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5878                     9 * crtc->framedur_ns) {
5879                         e->event.sequence++;
5880                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5881                                              crtc->framedur_ns);
5882                 }
5883
5884                 e->event.tv_sec = tvbl.tv_sec;
5885                 e->event.tv_usec = tvbl.tv_usec;
5886
5887                 list_add_tail(&e->base.link,
5888                               &e->base.file_priv->event_list);
5889                 wake_up_interruptible(&e->base.file_priv->event_wait);
5890         }
5891
5892         drm_vblank_put(dev, intel_crtc->pipe);
5893
5894         spin_unlock_irqrestore(&dev->event_lock, flags);
5895
5896         obj = work->old_fb_obj;
5897
5898         atomic_clear_mask(1 << intel_crtc->plane,
5899                           &obj->pending_flip.counter);
5900         if (atomic_read(&obj->pending_flip) == 0)
5901                 wake_up(&dev_priv->pending_flip_queue);
5902
5903         schedule_work(&work->work);
5904
5905         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5906 }
5907
5908 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5909 {
5910         drm_i915_private_t *dev_priv = dev->dev_private;
5911         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5912
5913         do_intel_finish_page_flip(dev, crtc);
5914 }
5915
5916 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5917 {
5918         drm_i915_private_t *dev_priv = dev->dev_private;
5919         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5920
5921         do_intel_finish_page_flip(dev, crtc);
5922 }
5923
5924 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5925 {
5926         drm_i915_private_t *dev_priv = dev->dev_private;
5927         struct intel_crtc *intel_crtc =
5928                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5929         unsigned long flags;
5930
5931         spin_lock_irqsave(&dev->event_lock, flags);
5932         if (intel_crtc->unpin_work) {
5933                 if ((++intel_crtc->unpin_work->pending) > 1)
5934                         DRM_ERROR("Prepared flip multiple times\n");
5935         } else {
5936                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5937         }
5938         spin_unlock_irqrestore(&dev->event_lock, flags);
5939 }
5940
5941 static int intel_gen2_queue_flip(struct drm_device *dev,
5942                                  struct drm_crtc *crtc,
5943                                  struct drm_framebuffer *fb,
5944                                  struct drm_i915_gem_object *obj)
5945 {
5946         struct drm_i915_private *dev_priv = dev->dev_private;
5947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5948         unsigned long offset;
5949         u32 flip_mask;
5950         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5951         int ret;
5952
5953         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5954         if (ret)
5955                 goto err;
5956
5957         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5958         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5959
5960         ret = intel_ring_begin(ring, 6);
5961         if (ret)
5962                 goto err_unpin;
5963
5964         /* Can't queue multiple flips, so wait for the previous
5965          * one to finish before executing the next.
5966          */
5967         if (intel_crtc->plane)
5968                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5969         else
5970                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5971         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5972         intel_ring_emit(ring, MI_NOOP);
5973         intel_ring_emit(ring, MI_DISPLAY_FLIP |
5974                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5975         intel_ring_emit(ring, fb->pitches[0]);
5976         intel_ring_emit(ring, obj->gtt_offset + offset);
5977         intel_ring_emit(ring, 0); /* aux display base address, unused */
5978         intel_ring_advance(ring);
5979         return 0;
5980
5981 err_unpin:
5982         intel_unpin_fb_obj(obj);
5983 err:
5984         return ret;
5985 }
5986
5987 static int intel_gen3_queue_flip(struct drm_device *dev,
5988                                  struct drm_crtc *crtc,
5989                                  struct drm_framebuffer *fb,
5990                                  struct drm_i915_gem_object *obj)
5991 {
5992         struct drm_i915_private *dev_priv = dev->dev_private;
5993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5994         unsigned long offset;
5995         u32 flip_mask;
5996         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5997         int ret;
5998
5999         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6000         if (ret)
6001                 goto err;
6002
6003         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6004         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
6005
6006         ret = intel_ring_begin(ring, 6);
6007         if (ret)
6008                 goto err_unpin;
6009
6010         if (intel_crtc->plane)
6011                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6012         else
6013                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6014         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6015         intel_ring_emit(ring, MI_NOOP);
6016         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6017                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6018         intel_ring_emit(ring, fb->pitches[0]);
6019         intel_ring_emit(ring, obj->gtt_offset + offset);
6020         intel_ring_emit(ring, MI_NOOP);
6021
6022         intel_ring_advance(ring);
6023         return 0;
6024
6025 err_unpin:
6026         intel_unpin_fb_obj(obj);
6027 err:
6028         return ret;
6029 }
6030
6031 static int intel_gen4_queue_flip(struct drm_device *dev,
6032                                  struct drm_crtc *crtc,
6033                                  struct drm_framebuffer *fb,
6034                                  struct drm_i915_gem_object *obj)
6035 {
6036         struct drm_i915_private *dev_priv = dev->dev_private;
6037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6038         uint32_t pf, pipesrc;
6039         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6040         int ret;
6041
6042         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6043         if (ret)
6044                 goto err;
6045
6046         ret = intel_ring_begin(ring, 4);
6047         if (ret)
6048                 goto err_unpin;
6049
6050         /* i965+ uses the linear or tiled offsets from the
6051          * Display Registers (which do not change across a page-flip)
6052          * so we need only reprogram the base address.
6053          */
6054         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6055                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6056         intel_ring_emit(ring, fb->pitches[0]);
6057         intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
6058
6059         /* XXX Enabling the panel-fitter across page-flip is so far
6060          * untested on non-native modes, so ignore it for now.
6061          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6062          */
6063         pf = 0;
6064         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6065         intel_ring_emit(ring, pf | pipesrc);
6066         intel_ring_advance(ring);
6067         return 0;
6068
6069 err_unpin:
6070         intel_unpin_fb_obj(obj);
6071 err:
6072         return ret;
6073 }
6074
6075 static int intel_gen6_queue_flip(struct drm_device *dev,
6076                                  struct drm_crtc *crtc,
6077                                  struct drm_framebuffer *fb,
6078                                  struct drm_i915_gem_object *obj)
6079 {
6080         struct drm_i915_private *dev_priv = dev->dev_private;
6081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6082         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6083         uint32_t pf, pipesrc;
6084         int ret;
6085
6086         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6087         if (ret)
6088                 goto err;
6089
6090         ret = intel_ring_begin(ring, 4);
6091         if (ret)
6092                 goto err_unpin;
6093
6094         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6095                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6096         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6097         intel_ring_emit(ring, obj->gtt_offset);
6098
6099         /* Contrary to the suggestions in the documentation,
6100          * "Enable Panel Fitter" does not seem to be required when page
6101          * flipping with a non-native mode, and worse causes a normal
6102          * modeset to fail.
6103          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6104          */
6105         pf = 0;
6106         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6107         intel_ring_emit(ring, pf | pipesrc);
6108         intel_ring_advance(ring);
6109         return 0;
6110
6111 err_unpin:
6112         intel_unpin_fb_obj(obj);
6113 err:
6114         return ret;
6115 }
6116
6117 /*
6118  * On gen7 we currently use the blit ring because (in early silicon at least)
6119  * the render ring doesn't give us interrpts for page flip completion, which
6120  * means clients will hang after the first flip is queued.  Fortunately the
6121  * blit ring generates interrupts properly, so use it instead.
6122  */
6123 static int intel_gen7_queue_flip(struct drm_device *dev,
6124                                  struct drm_crtc *crtc,
6125                                  struct drm_framebuffer *fb,
6126                                  struct drm_i915_gem_object *obj)
6127 {
6128         struct drm_i915_private *dev_priv = dev->dev_private;
6129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6130         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6131         int ret;
6132
6133         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6134         if (ret)
6135                 goto err;
6136
6137         ret = intel_ring_begin(ring, 4);
6138         if (ret)
6139                 goto err_unpin;
6140
6141         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6142         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6143         intel_ring_emit(ring, (obj->gtt_offset));
6144         intel_ring_emit(ring, (MI_NOOP));
6145         intel_ring_advance(ring);
6146         return 0;
6147
6148 err_unpin:
6149         intel_unpin_fb_obj(obj);
6150 err:
6151         return ret;
6152 }
6153
6154 static int intel_default_queue_flip(struct drm_device *dev,
6155                                     struct drm_crtc *crtc,
6156                                     struct drm_framebuffer *fb,
6157                                     struct drm_i915_gem_object *obj)
6158 {
6159         return -ENODEV;
6160 }
6161
6162 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6163                                 struct drm_framebuffer *fb,
6164                                 struct drm_pending_vblank_event *event)
6165 {
6166         struct drm_device *dev = crtc->dev;
6167         struct drm_i915_private *dev_priv = dev->dev_private;
6168         struct intel_framebuffer *intel_fb;
6169         struct drm_i915_gem_object *obj;
6170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6171         struct intel_unpin_work *work;
6172         unsigned long flags;
6173         int ret;
6174
6175         work = kzalloc(sizeof *work, GFP_KERNEL);
6176         if (work == NULL)
6177                 return -ENOMEM;
6178
6179         work->event = event;
6180         work->dev = crtc->dev;
6181         intel_fb = to_intel_framebuffer(crtc->fb);
6182         work->old_fb_obj = intel_fb->obj;
6183         INIT_WORK(&work->work, intel_unpin_work_fn);
6184
6185         ret = drm_vblank_get(dev, intel_crtc->pipe);
6186         if (ret)
6187                 goto free_work;
6188
6189         /* We borrow the event spin lock for protecting unpin_work */
6190         spin_lock_irqsave(&dev->event_lock, flags);
6191         if (intel_crtc->unpin_work) {
6192                 spin_unlock_irqrestore(&dev->event_lock, flags);
6193                 kfree(work);
6194                 drm_vblank_put(dev, intel_crtc->pipe);
6195
6196                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6197                 return -EBUSY;
6198         }
6199         intel_crtc->unpin_work = work;
6200         spin_unlock_irqrestore(&dev->event_lock, flags);
6201
6202         intel_fb = to_intel_framebuffer(fb);
6203         obj = intel_fb->obj;
6204
6205         mutex_lock(&dev->struct_mutex);
6206
6207         /* Reference the objects for the scheduled work. */
6208         drm_gem_object_reference(&work->old_fb_obj->base);
6209         drm_gem_object_reference(&obj->base);
6210
6211         crtc->fb = fb;
6212
6213         work->pending_flip_obj = obj;
6214
6215         work->enable_stall_check = true;
6216
6217         /* Block clients from rendering to the new back buffer until
6218          * the flip occurs and the object is no longer visible.
6219          */
6220         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6221
6222         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6223         if (ret)
6224                 goto cleanup_pending;
6225
6226         intel_disable_fbc(dev);
6227         intel_mark_busy(dev, obj);
6228         mutex_unlock(&dev->struct_mutex);
6229
6230         trace_i915_flip_request(intel_crtc->plane, obj);
6231
6232         return 0;
6233
6234 cleanup_pending:
6235         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6236         drm_gem_object_unreference(&work->old_fb_obj->base);
6237         drm_gem_object_unreference(&obj->base);
6238         mutex_unlock(&dev->struct_mutex);
6239
6240         spin_lock_irqsave(&dev->event_lock, flags);
6241         intel_crtc->unpin_work = NULL;
6242         spin_unlock_irqrestore(&dev->event_lock, flags);
6243
6244         drm_vblank_put(dev, intel_crtc->pipe);
6245 free_work:
6246         kfree(work);
6247
6248         return ret;
6249 }
6250
6251 static void intel_sanitize_modesetting(struct drm_device *dev,
6252                                        int pipe, int plane)
6253 {
6254         struct drm_i915_private *dev_priv = dev->dev_private;
6255         u32 reg, val;
6256         int i;
6257
6258         /* Clear any frame start delays used for debugging left by the BIOS */
6259         for_each_pipe(i) {
6260                 reg = PIPECONF(i);
6261                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6262         }
6263
6264         if (HAS_PCH_SPLIT(dev))
6265                 return;
6266
6267         /* Who knows what state these registers were left in by the BIOS or
6268          * grub?
6269          *
6270          * If we leave the registers in a conflicting state (e.g. with the
6271          * display plane reading from the other pipe than the one we intend
6272          * to use) then when we attempt to teardown the active mode, we will
6273          * not disable the pipes and planes in the correct order -- leaving
6274          * a plane reading from a disabled pipe and possibly leading to
6275          * undefined behaviour.
6276          */
6277
6278         reg = DSPCNTR(plane);
6279         val = I915_READ(reg);
6280
6281         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6282                 return;
6283         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6284                 return;
6285
6286         /* This display plane is active and attached to the other CPU pipe. */
6287         pipe = !pipe;
6288
6289         /* Disable the plane and wait for it to stop reading from the pipe. */
6290         intel_disable_plane(dev_priv, plane, pipe);
6291         intel_disable_pipe(dev_priv, pipe);
6292 }
6293
6294 static void intel_crtc_reset(struct drm_crtc *crtc)
6295 {
6296         struct drm_device *dev = crtc->dev;
6297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6298
6299         /* Reset flags back to the 'unknown' status so that they
6300          * will be correctly set on the initial modeset.
6301          */
6302         intel_crtc->dpms_mode = -1;
6303
6304         /* We need to fix up any BIOS configuration that conflicts with
6305          * our expectations.
6306          */
6307         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6308 }
6309
6310 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6311         .dpms = intel_crtc_dpms,
6312         .mode_fixup = intel_crtc_mode_fixup,
6313         .mode_set = intel_crtc_mode_set,
6314         .mode_set_base = intel_pipe_set_base,
6315         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6316         .load_lut = intel_crtc_load_lut,
6317         .disable = intel_crtc_disable,
6318 };
6319
6320 static const struct drm_crtc_funcs intel_crtc_funcs = {
6321         .reset = intel_crtc_reset,
6322         .cursor_set = intel_crtc_cursor_set,
6323         .cursor_move = intel_crtc_cursor_move,
6324         .gamma_set = intel_crtc_gamma_set,
6325         .set_config = drm_crtc_helper_set_config,
6326         .destroy = intel_crtc_destroy,
6327         .page_flip = intel_crtc_page_flip,
6328 };
6329
6330 static void intel_pch_pll_init(struct drm_device *dev)
6331 {
6332         drm_i915_private_t *dev_priv = dev->dev_private;
6333         int i;
6334
6335         if (dev_priv->num_pch_pll == 0) {
6336                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6337                 return;
6338         }
6339
6340         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6341                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6342                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6343                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6344         }
6345 }
6346
6347 static void intel_crtc_init(struct drm_device *dev, int pipe)
6348 {
6349         drm_i915_private_t *dev_priv = dev->dev_private;
6350         struct intel_crtc *intel_crtc;
6351         int i;
6352
6353         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6354         if (intel_crtc == NULL)
6355                 return;
6356
6357         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6358
6359         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6360         for (i = 0; i < 256; i++) {
6361                 intel_crtc->lut_r[i] = i;
6362                 intel_crtc->lut_g[i] = i;
6363                 intel_crtc->lut_b[i] = i;
6364         }
6365
6366         /* Swap pipes & planes for FBC on pre-965 */
6367         intel_crtc->pipe = pipe;
6368         intel_crtc->plane = pipe;
6369         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6370                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6371                 intel_crtc->plane = !pipe;
6372         }
6373
6374         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6375                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6376         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6377         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6378
6379         intel_crtc_reset(&intel_crtc->base);
6380         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6381         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6382
6383         if (HAS_PCH_SPLIT(dev)) {
6384                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6385                 intel_helper_funcs.commit = ironlake_crtc_commit;
6386         } else {
6387                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6388                 intel_helper_funcs.commit = i9xx_crtc_commit;
6389         }
6390
6391         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6392
6393         intel_crtc->busy = false;
6394
6395         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6396                     (unsigned long)intel_crtc);
6397 }
6398
6399 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6400                                 struct drm_file *file)
6401 {
6402         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6403         struct drm_mode_object *drmmode_obj;
6404         struct intel_crtc *crtc;
6405
6406         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6407                 return -ENODEV;
6408
6409         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6410                         DRM_MODE_OBJECT_CRTC);
6411
6412         if (!drmmode_obj) {
6413                 DRM_ERROR("no such CRTC id\n");
6414                 return -EINVAL;
6415         }
6416
6417         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6418         pipe_from_crtc_id->pipe = crtc->pipe;
6419
6420         return 0;
6421 }
6422
6423 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6424 {
6425         struct intel_encoder *encoder;
6426         int index_mask = 0;
6427         int entry = 0;
6428
6429         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6430                 if (type_mask & encoder->clone_mask)
6431                         index_mask |= (1 << entry);
6432                 entry++;
6433         }
6434
6435         return index_mask;
6436 }
6437
6438 static bool has_edp_a(struct drm_device *dev)
6439 {
6440         struct drm_i915_private *dev_priv = dev->dev_private;
6441
6442         if (!IS_MOBILE(dev))
6443                 return false;
6444
6445         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6446                 return false;
6447
6448         if (IS_GEN5(dev) &&
6449             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6450                 return false;
6451
6452         return true;
6453 }
6454
6455 static void intel_setup_outputs(struct drm_device *dev)
6456 {
6457         struct drm_i915_private *dev_priv = dev->dev_private;
6458         struct intel_encoder *encoder;
6459         bool dpd_is_edp = false;
6460         bool has_lvds;
6461
6462         has_lvds = intel_lvds_init(dev);
6463         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6464                 /* disable the panel fitter on everything but LVDS */
6465                 I915_WRITE(PFIT_CONTROL, 0);
6466         }
6467
6468         if (HAS_PCH_SPLIT(dev)) {
6469                 dpd_is_edp = intel_dpd_is_edp(dev);
6470
6471                 if (has_edp_a(dev))
6472                         intel_dp_init(dev, DP_A);
6473
6474                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6475                         intel_dp_init(dev, PCH_DP_D);
6476         }
6477
6478         intel_crt_init(dev);
6479
6480         if (IS_HASWELL(dev)) {
6481                 int found;
6482
6483                 /* Haswell uses DDI functions to detect digital outputs */
6484                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6485                 /* DDI A only supports eDP */
6486                 if (found)
6487                         intel_ddi_init(dev, PORT_A);
6488
6489                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6490                  * register */
6491                 found = I915_READ(SFUSE_STRAP);
6492
6493                 if (found & SFUSE_STRAP_DDIB_DETECTED)
6494                         intel_ddi_init(dev, PORT_B);
6495                 if (found & SFUSE_STRAP_DDIC_DETECTED)
6496                         intel_ddi_init(dev, PORT_C);
6497                 if (found & SFUSE_STRAP_DDID_DETECTED)
6498                         intel_ddi_init(dev, PORT_D);
6499         } else if (HAS_PCH_SPLIT(dev)) {
6500                 int found;
6501
6502                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6503                         /* PCH SDVOB multiplex with HDMIB */
6504                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
6505                         if (!found)
6506                                 intel_hdmi_init(dev, HDMIB);
6507                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6508                                 intel_dp_init(dev, PCH_DP_B);
6509                 }
6510
6511                 if (I915_READ(HDMIC) & PORT_DETECTED)
6512                         intel_hdmi_init(dev, HDMIC);
6513
6514                 if (I915_READ(HDMID) & PORT_DETECTED)
6515                         intel_hdmi_init(dev, HDMID);
6516
6517                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6518                         intel_dp_init(dev, PCH_DP_C);
6519
6520                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6521                         intel_dp_init(dev, PCH_DP_D);
6522
6523         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6524                 bool found = false;
6525
6526                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6527                         DRM_DEBUG_KMS("probing SDVOB\n");
6528                         found = intel_sdvo_init(dev, SDVOB, true);
6529                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6530                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6531                                 intel_hdmi_init(dev, SDVOB);
6532                         }
6533
6534                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6535                                 DRM_DEBUG_KMS("probing DP_B\n");
6536                                 intel_dp_init(dev, DP_B);
6537                         }
6538                 }
6539
6540                 /* Before G4X SDVOC doesn't have its own detect register */
6541
6542                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6543                         DRM_DEBUG_KMS("probing SDVOC\n");
6544                         found = intel_sdvo_init(dev, SDVOC, false);
6545                 }
6546
6547                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6548
6549                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6550                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6551                                 intel_hdmi_init(dev, SDVOC);
6552                         }
6553                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6554                                 DRM_DEBUG_KMS("probing DP_C\n");
6555                                 intel_dp_init(dev, DP_C);
6556                         }
6557                 }
6558
6559                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6560                     (I915_READ(DP_D) & DP_DETECTED)) {
6561                         DRM_DEBUG_KMS("probing DP_D\n");
6562                         intel_dp_init(dev, DP_D);
6563                 }
6564         } else if (IS_GEN2(dev))
6565                 intel_dvo_init(dev);
6566
6567         if (SUPPORTS_TV(dev))
6568                 intel_tv_init(dev);
6569
6570         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6571                 encoder->base.possible_crtcs = encoder->crtc_mask;
6572                 encoder->base.possible_clones =
6573                         intel_encoder_clones(dev, encoder->clone_mask);
6574         }
6575
6576         /* disable all the possible outputs/crtcs before entering KMS mode */
6577         drm_helper_disable_unused_functions(dev);
6578
6579         if (HAS_PCH_SPLIT(dev))
6580                 ironlake_init_pch_refclk(dev);
6581 }
6582
6583 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6584 {
6585         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6586
6587         drm_framebuffer_cleanup(fb);
6588         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6589
6590         kfree(intel_fb);
6591 }
6592
6593 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6594                                                 struct drm_file *file,
6595                                                 unsigned int *handle)
6596 {
6597         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6598         struct drm_i915_gem_object *obj = intel_fb->obj;
6599
6600         return drm_gem_handle_create(file, &obj->base, handle);
6601 }
6602
6603 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6604         .destroy = intel_user_framebuffer_destroy,
6605         .create_handle = intel_user_framebuffer_create_handle,
6606 };
6607
6608 int intel_framebuffer_init(struct drm_device *dev,
6609                            struct intel_framebuffer *intel_fb,
6610                            struct drm_mode_fb_cmd2 *mode_cmd,
6611                            struct drm_i915_gem_object *obj)
6612 {
6613         int ret;
6614
6615         if (obj->tiling_mode == I915_TILING_Y)
6616                 return -EINVAL;
6617
6618         if (mode_cmd->pitches[0] & 63)
6619                 return -EINVAL;
6620
6621         switch (mode_cmd->pixel_format) {
6622         case DRM_FORMAT_RGB332:
6623         case DRM_FORMAT_RGB565:
6624         case DRM_FORMAT_XRGB8888:
6625         case DRM_FORMAT_XBGR8888:
6626         case DRM_FORMAT_ARGB8888:
6627         case DRM_FORMAT_XRGB2101010:
6628         case DRM_FORMAT_ARGB2101010:
6629                 /* RGB formats are common across chipsets */
6630                 break;
6631         case DRM_FORMAT_YUYV:
6632         case DRM_FORMAT_UYVY:
6633         case DRM_FORMAT_YVYU:
6634         case DRM_FORMAT_VYUY:
6635                 break;
6636         default:
6637                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6638                                 mode_cmd->pixel_format);
6639                 return -EINVAL;
6640         }
6641
6642         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6643         if (ret) {
6644                 DRM_ERROR("framebuffer init failed %d\n", ret);
6645                 return ret;
6646         }
6647
6648         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6649         intel_fb->obj = obj;
6650         return 0;
6651 }
6652
6653 static struct drm_framebuffer *
6654 intel_user_framebuffer_create(struct drm_device *dev,
6655                               struct drm_file *filp,
6656                               struct drm_mode_fb_cmd2 *mode_cmd)
6657 {
6658         struct drm_i915_gem_object *obj;
6659
6660         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6661                                                 mode_cmd->handles[0]));
6662         if (&obj->base == NULL)
6663                 return ERR_PTR(-ENOENT);
6664
6665         return intel_framebuffer_create(dev, mode_cmd, obj);
6666 }
6667
6668 static const struct drm_mode_config_funcs intel_mode_funcs = {
6669         .fb_create = intel_user_framebuffer_create,
6670         .output_poll_changed = intel_fb_output_poll_changed,
6671 };
6672
6673 /* Set up chip specific display functions */
6674 static void intel_init_display(struct drm_device *dev)
6675 {
6676         struct drm_i915_private *dev_priv = dev->dev_private;
6677
6678         /* We always want a DPMS function */
6679         if (HAS_PCH_SPLIT(dev)) {
6680                 dev_priv->display.dpms = ironlake_crtc_dpms;
6681                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6682                 dev_priv->display.off = ironlake_crtc_off;
6683                 dev_priv->display.update_plane = ironlake_update_plane;
6684         } else {
6685                 dev_priv->display.dpms = i9xx_crtc_dpms;
6686                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6687                 dev_priv->display.off = i9xx_crtc_off;
6688                 dev_priv->display.update_plane = i9xx_update_plane;
6689         }
6690
6691         /* Returns the core display clock speed */
6692         if (IS_VALLEYVIEW(dev))
6693                 dev_priv->display.get_display_clock_speed =
6694                         valleyview_get_display_clock_speed;
6695         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6696                 dev_priv->display.get_display_clock_speed =
6697                         i945_get_display_clock_speed;
6698         else if (IS_I915G(dev))
6699                 dev_priv->display.get_display_clock_speed =
6700                         i915_get_display_clock_speed;
6701         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6702                 dev_priv->display.get_display_clock_speed =
6703                         i9xx_misc_get_display_clock_speed;
6704         else if (IS_I915GM(dev))
6705                 dev_priv->display.get_display_clock_speed =
6706                         i915gm_get_display_clock_speed;
6707         else if (IS_I865G(dev))
6708                 dev_priv->display.get_display_clock_speed =
6709                         i865_get_display_clock_speed;
6710         else if (IS_I85X(dev))
6711                 dev_priv->display.get_display_clock_speed =
6712                         i855_get_display_clock_speed;
6713         else /* 852, 830 */
6714                 dev_priv->display.get_display_clock_speed =
6715                         i830_get_display_clock_speed;
6716
6717         if (HAS_PCH_SPLIT(dev)) {
6718                 if (IS_GEN5(dev)) {
6719                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6720                         dev_priv->display.write_eld = ironlake_write_eld;
6721                 } else if (IS_GEN6(dev)) {
6722                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6723                         dev_priv->display.write_eld = ironlake_write_eld;
6724                 } else if (IS_IVYBRIDGE(dev)) {
6725                         /* FIXME: detect B0+ stepping and use auto training */
6726                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6727                         dev_priv->display.write_eld = ironlake_write_eld;
6728                 } else if (IS_HASWELL(dev)) {
6729                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
6730                         dev_priv->display.write_eld = ironlake_write_eld;
6731                 } else
6732                         dev_priv->display.update_wm = NULL;
6733         } else if (IS_VALLEYVIEW(dev)) {
6734                 dev_priv->display.force_wake_get = vlv_force_wake_get;
6735                 dev_priv->display.force_wake_put = vlv_force_wake_put;
6736         } else if (IS_G4X(dev)) {
6737                 dev_priv->display.write_eld = g4x_write_eld;
6738         }
6739
6740         /* Default just returns -ENODEV to indicate unsupported */
6741         dev_priv->display.queue_flip = intel_default_queue_flip;
6742
6743         switch (INTEL_INFO(dev)->gen) {
6744         case 2:
6745                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6746                 break;
6747
6748         case 3:
6749                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6750                 break;
6751
6752         case 4:
6753         case 5:
6754                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6755                 break;
6756
6757         case 6:
6758                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6759                 break;
6760         case 7:
6761                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6762                 break;
6763         }
6764 }
6765
6766 /*
6767  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6768  * resume, or other times.  This quirk makes sure that's the case for
6769  * affected systems.
6770  */
6771 static void quirk_pipea_force(struct drm_device *dev)
6772 {
6773         struct drm_i915_private *dev_priv = dev->dev_private;
6774
6775         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6776         DRM_INFO("applying pipe a force quirk\n");
6777 }
6778
6779 /*
6780  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6781  */
6782 static void quirk_ssc_force_disable(struct drm_device *dev)
6783 {
6784         struct drm_i915_private *dev_priv = dev->dev_private;
6785         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6786         DRM_INFO("applying lvds SSC disable quirk\n");
6787 }
6788
6789 /*
6790  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6791  * brightness value
6792  */
6793 static void quirk_invert_brightness(struct drm_device *dev)
6794 {
6795         struct drm_i915_private *dev_priv = dev->dev_private;
6796         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6797         DRM_INFO("applying inverted panel brightness quirk\n");
6798 }
6799
6800 struct intel_quirk {
6801         int device;
6802         int subsystem_vendor;
6803         int subsystem_device;
6804         void (*hook)(struct drm_device *dev);
6805 };
6806
6807 static struct intel_quirk intel_quirks[] = {
6808         /* HP Mini needs pipe A force quirk (LP: #322104) */
6809         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6810
6811         /* Thinkpad R31 needs pipe A force quirk */
6812         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6813         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6814         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6815
6816         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6817         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6818         /* ThinkPad X40 needs pipe A force quirk */
6819
6820         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6821         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6822
6823         /* 855 & before need to leave pipe A & dpll A up */
6824         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6825         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6826
6827         /* Lenovo U160 cannot use SSC on LVDS */
6828         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6829
6830         /* Sony Vaio Y cannot use SSC on LVDS */
6831         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6832
6833         /* Acer Aspire 5734Z must invert backlight brightness */
6834         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6835 };
6836
6837 static void intel_init_quirks(struct drm_device *dev)
6838 {
6839         struct pci_dev *d = dev->pdev;
6840         int i;
6841
6842         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6843                 struct intel_quirk *q = &intel_quirks[i];
6844
6845                 if (d->device == q->device &&
6846                     (d->subsystem_vendor == q->subsystem_vendor ||
6847                      q->subsystem_vendor == PCI_ANY_ID) &&
6848                     (d->subsystem_device == q->subsystem_device ||
6849                      q->subsystem_device == PCI_ANY_ID))
6850                         q->hook(dev);
6851         }
6852 }
6853
6854 /* Disable the VGA plane that we never use */
6855 static void i915_disable_vga(struct drm_device *dev)
6856 {
6857         struct drm_i915_private *dev_priv = dev->dev_private;
6858         u8 sr1;
6859         u32 vga_reg;
6860
6861         if (HAS_PCH_SPLIT(dev))
6862                 vga_reg = CPU_VGACNTRL;
6863         else
6864                 vga_reg = VGACNTRL;
6865
6866         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6867         outb(SR01, VGA_SR_INDEX);
6868         sr1 = inb(VGA_SR_DATA);
6869         outb(sr1 | 1<<5, VGA_SR_DATA);
6870         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6871         udelay(300);
6872
6873         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6874         POSTING_READ(vga_reg);
6875 }
6876
6877 static void ivb_pch_pwm_override(struct drm_device *dev)
6878 {
6879         struct drm_i915_private *dev_priv = dev->dev_private;
6880
6881         /*
6882          * IVB has CPU eDP backlight regs too, set things up to let the
6883          * PCH regs control the backlight
6884          */
6885         I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6886         I915_WRITE(BLC_PWM_CPU_CTL, 0);
6887         I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6888 }
6889
6890 void intel_modeset_init_hw(struct drm_device *dev)
6891 {
6892         struct drm_i915_private *dev_priv = dev->dev_private;
6893
6894         intel_init_clock_gating(dev);
6895
6896         if (IS_IRONLAKE_M(dev)) {
6897                 ironlake_enable_drps(dev);
6898                 ironlake_enable_rc6(dev);
6899                 intel_init_emon(dev);
6900         }
6901
6902         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6903                 gen6_enable_rps(dev_priv);
6904                 gen6_update_ring_freq(dev_priv);
6905         }
6906
6907         if (IS_IVYBRIDGE(dev))
6908                 ivb_pch_pwm_override(dev);
6909 }
6910
6911 void intel_modeset_init(struct drm_device *dev)
6912 {
6913         struct drm_i915_private *dev_priv = dev->dev_private;
6914         int i, ret;
6915
6916         drm_mode_config_init(dev);
6917
6918         dev->mode_config.min_width = 0;
6919         dev->mode_config.min_height = 0;
6920
6921         dev->mode_config.preferred_depth = 24;
6922         dev->mode_config.prefer_shadow = 1;
6923
6924         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6925
6926         intel_init_quirks(dev);
6927
6928         intel_init_pm(dev);
6929
6930         intel_prepare_ddi(dev);
6931
6932         intel_init_display(dev);
6933
6934         if (IS_GEN2(dev)) {
6935                 dev->mode_config.max_width = 2048;
6936                 dev->mode_config.max_height = 2048;
6937         } else if (IS_GEN3(dev)) {
6938                 dev->mode_config.max_width = 4096;
6939                 dev->mode_config.max_height = 4096;
6940         } else {
6941                 dev->mode_config.max_width = 8192;
6942                 dev->mode_config.max_height = 8192;
6943         }
6944         dev->mode_config.fb_base = dev->agp->base;
6945
6946         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6947                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6948
6949         for (i = 0; i < dev_priv->num_pipe; i++) {
6950                 intel_crtc_init(dev, i);
6951                 ret = intel_plane_init(dev, i);
6952                 if (ret)
6953                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6954         }
6955
6956         intel_pch_pll_init(dev);
6957
6958         /* Just disable it once at startup */
6959         i915_disable_vga(dev);
6960         intel_setup_outputs(dev);
6961
6962         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6963         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6964                     (unsigned long)dev);
6965 }
6966
6967 void intel_modeset_gem_init(struct drm_device *dev)
6968 {
6969         intel_modeset_init_hw(dev);
6970
6971         intel_setup_overlay(dev);
6972 }
6973
6974 void intel_modeset_cleanup(struct drm_device *dev)
6975 {
6976         struct drm_i915_private *dev_priv = dev->dev_private;
6977         struct drm_crtc *crtc;
6978         struct intel_crtc *intel_crtc;
6979
6980         drm_kms_helper_poll_fini(dev);
6981         mutex_lock(&dev->struct_mutex);
6982
6983         intel_unregister_dsm_handler();
6984
6985
6986         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6987                 /* Skip inactive CRTCs */
6988                 if (!crtc->fb)
6989                         continue;
6990
6991                 intel_crtc = to_intel_crtc(crtc);
6992                 intel_increase_pllclock(crtc);
6993         }
6994
6995         intel_disable_fbc(dev);
6996
6997         if (IS_IRONLAKE_M(dev))
6998                 ironlake_disable_drps(dev);
6999         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
7000                 gen6_disable_rps(dev);
7001
7002         if (IS_IRONLAKE_M(dev))
7003                 ironlake_disable_rc6(dev);
7004
7005         if (IS_VALLEYVIEW(dev))
7006                 vlv_init_dpio(dev);
7007
7008         mutex_unlock(&dev->struct_mutex);
7009
7010         /* Disable the irq before mode object teardown, for the irq might
7011          * enqueue unpin/hotplug work. */
7012         drm_irq_uninstall(dev);
7013         cancel_work_sync(&dev_priv->hotplug_work);
7014         cancel_work_sync(&dev_priv->rps_work);
7015
7016         /* flush any delayed tasks or pending work */
7017         flush_scheduled_work();
7018
7019         /* Shut off idle work before the crtcs get freed. */
7020         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7021                 intel_crtc = to_intel_crtc(crtc);
7022                 del_timer_sync(&intel_crtc->idle_timer);
7023         }
7024         del_timer_sync(&dev_priv->idle_timer);
7025         cancel_work_sync(&dev_priv->idle_work);
7026
7027         drm_mode_config_cleanup(dev);
7028 }
7029
7030 /*
7031  * Return which encoder is currently attached for connector.
7032  */
7033 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7034 {
7035         return &intel_attached_encoder(connector)->base;
7036 }
7037
7038 void intel_connector_attach_encoder(struct intel_connector *connector,
7039                                     struct intel_encoder *encoder)
7040 {
7041         connector->encoder = encoder;
7042         drm_mode_connector_attach_encoder(&connector->base,
7043                                           &encoder->base);
7044 }
7045
7046 /*
7047  * set vga decode state - true == enable VGA decode
7048  */
7049 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7050 {
7051         struct drm_i915_private *dev_priv = dev->dev_private;
7052         u16 gmch_ctrl;
7053
7054         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7055         if (state)
7056                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7057         else
7058                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7059         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7060         return 0;
7061 }
7062
7063 #ifdef CONFIG_DEBUG_FS
7064 #include <linux/seq_file.h>
7065
7066 struct intel_display_error_state {
7067         struct intel_cursor_error_state {
7068                 u32 control;
7069                 u32 position;
7070                 u32 base;
7071                 u32 size;
7072         } cursor[2];
7073
7074         struct intel_pipe_error_state {
7075                 u32 conf;
7076                 u32 source;
7077
7078                 u32 htotal;
7079                 u32 hblank;
7080                 u32 hsync;
7081                 u32 vtotal;
7082                 u32 vblank;
7083                 u32 vsync;
7084         } pipe[2];
7085
7086         struct intel_plane_error_state {
7087                 u32 control;
7088                 u32 stride;
7089                 u32 size;
7090                 u32 pos;
7091                 u32 addr;
7092                 u32 surface;
7093                 u32 tile_offset;
7094         } plane[2];
7095 };
7096
7097 struct intel_display_error_state *
7098 intel_display_capture_error_state(struct drm_device *dev)
7099 {
7100         drm_i915_private_t *dev_priv = dev->dev_private;
7101         struct intel_display_error_state *error;
7102         int i;
7103
7104         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7105         if (error == NULL)
7106                 return NULL;
7107
7108         for (i = 0; i < 2; i++) {
7109                 error->cursor[i].control = I915_READ(CURCNTR(i));
7110                 error->cursor[i].position = I915_READ(CURPOS(i));
7111                 error->cursor[i].base = I915_READ(CURBASE(i));
7112
7113                 error->plane[i].control = I915_READ(DSPCNTR(i));
7114                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7115                 error->plane[i].size = I915_READ(DSPSIZE(i));
7116                 error->plane[i].pos = I915_READ(DSPPOS(i));
7117                 error->plane[i].addr = I915_READ(DSPADDR(i));
7118                 if (INTEL_INFO(dev)->gen >= 4) {
7119                         error->plane[i].surface = I915_READ(DSPSURF(i));
7120                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7121                 }
7122
7123                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7124                 error->pipe[i].source = I915_READ(PIPESRC(i));
7125                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7126                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7127                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7128                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7129                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7130                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7131         }
7132
7133         return error;
7134 }
7135
7136 void
7137 intel_display_print_error_state(struct seq_file *m,
7138                                 struct drm_device *dev,
7139                                 struct intel_display_error_state *error)
7140 {
7141         int i;
7142
7143         for (i = 0; i < 2; i++) {
7144                 seq_printf(m, "Pipe [%d]:\n", i);
7145                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7146                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7147                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7148                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7149                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7150                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7151                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7152                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7153
7154                 seq_printf(m, "Plane [%d]:\n", i);
7155                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7156                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7157                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7158                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7159                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7160                 if (INTEL_INFO(dev)->gen >= 4) {
7161                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7162                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7163                 }
7164
7165                 seq_printf(m, "Cursor [%d]:\n", i);
7166                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7167                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7168                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7169         }
7170 }
7171 #endif