drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 /* FDI */
  80 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  81
  82 static bool
  83 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  84                     int target, int refclk, intel_clock_t *best_clock);
  85 static bool
  86 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  87                         int target, int refclk, intel_clock_t *best_clock);
  88
  89 static bool
  90 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  91                       int target, int refclk, intel_clock_t *best_clock);
  92 static bool
  93 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                            int target, int refclk, intel_clock_t *best_clock);
  95
  96 static inline u32 /* units of 100MHz */
  97 intel_fdi_link_freq(struct drm_device *dev)
  98 {
  99         if (IS_GEN5(dev)) {
 100                 struct drm_i915_private *dev_priv = dev->dev_private;
 101                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 102         } else
 103                 return 27;
 104 }
 105
 106 static const intel_limit_t intel_limits_i8xx_dvo = {
 107         .dot = { .min = 25000, .max = 350000 },
 108         .vco = { .min = 930000, .max = 1400000 },
 109         .n = { .min = 3, .max = 16 },
 110         .m = { .min = 96, .max = 140 },
 111         .m1 = { .min = 18, .max = 26 },
 112         .m2 = { .min = 6, .max = 16 },
 113         .p = { .min = 4, .max = 128 },
 114         .p1 = { .min = 2, .max = 33 },
 115         .p2 = { .dot_limit = 165000,
 116                 .p2_slow = 4, .p2_fast = 2 },
 117         .find_pll = intel_find_best_PLL,
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 930000, .max = 1400000 },
 123         .n = { .min = 3, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131         .find_pll = intel_find_best_PLL,
 132 };
 133
 134 static const intel_limit_t intel_limits_i9xx_sdvo = {
 135         .dot = { .min = 20000, .max = 400000 },
 136         .vco = { .min = 1400000, .max = 2800000 },
 137         .n = { .min = 1, .max = 6 },
 138         .m = { .min = 70, .max = 120 },
 139         .m1 = { .min = 10, .max = 22 },
 140         .m2 = { .min = 5, .max = 9 },
 141         .p = { .min = 5, .max = 80 },
 142         .p1 = { .min = 1, .max = 8 },
 143         .p2 = { .dot_limit = 200000,
 144                 .p2_slow = 10, .p2_fast = 5 },
 145         .find_pll = intel_find_best_PLL,
 146 };
 147
 148 static const intel_limit_t intel_limits_i9xx_lvds = {
 149         .dot = { .min = 20000, .max = 400000 },
 150         .vco = { .min = 1400000, .max = 2800000 },
 151         .n = { .min = 1, .max = 6 },
 152         .m = { .min = 70, .max = 120 },
 153         .m1 = { .min = 10, .max = 22 },
 154         .m2 = { .min = 5, .max = 9 },
 155         .p = { .min = 7, .max = 98 },
 156         .p1 = { .min = 1, .max = 8 },
 157         .p2 = { .dot_limit = 112000,
 158                 .p2_slow = 14, .p2_fast = 7 },
 159         .find_pll = intel_find_best_PLL,
 160 };
 161
 162
 163 static const intel_limit_t intel_limits_g4x_sdvo = {
 164         .dot = { .min = 25000, .max = 270000 },
 165         .vco = { .min = 1750000, .max = 3500000},
 166         .n = { .min = 1, .max = 4 },
 167         .m = { .min = 104, .max = 138 },
 168         .m1 = { .min = 17, .max = 23 },
 169         .m2 = { .min = 5, .max = 11 },
 170         .p = { .min = 10, .max = 30 },
 171         .p1 = { .min = 1, .max = 3},
 172         .p2 = { .dot_limit = 270000,
 173                 .p2_slow = 10,
 174                 .p2_fast = 10
 175         },
 176         .find_pll = intel_g4x_find_best_PLL,
 177 };
 178
 179 static const intel_limit_t intel_limits_g4x_hdmi = {
 180         .dot = { .min = 22000, .max = 400000 },
 181         .vco = { .min = 1750000, .max = 3500000},
 182         .n = { .min = 1, .max = 4 },
 183         .m = { .min = 104, .max = 138 },
 184         .m1 = { .min = 16, .max = 23 },
 185         .m2 = { .min = 5, .max = 11 },
 186         .p = { .min = 5, .max = 80 },
 187         .p1 = { .min = 1, .max = 8},
 188         .p2 = { .dot_limit = 165000,
 189                 .p2_slow = 10, .p2_fast = 5 },
 190         .find_pll = intel_g4x_find_best_PLL,
 191 };
 192
 193 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 194         .dot = { .min = 20000, .max = 115000 },
 195         .vco = { .min = 1750000, .max = 3500000 },
 196         .n = { .min = 1, .max = 3 },
 197         .m = { .min = 104, .max = 138 },
 198         .m1 = { .min = 17, .max = 23 },
 199         .m2 = { .min = 5, .max = 11 },
 200         .p = { .min = 28, .max = 112 },
 201         .p1 = { .min = 2, .max = 8 },
 202         .p2 = { .dot_limit = 0,
 203                 .p2_slow = 14, .p2_fast = 14
 204         },
 205         .find_pll = intel_g4x_find_best_PLL,
 206 };
 207
 208 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 209         .dot = { .min = 80000, .max = 224000 },
 210         .vco = { .min = 1750000, .max = 3500000 },
 211         .n = { .min = 1, .max = 3 },
 212         .m = { .min = 104, .max = 138 },
 213         .m1 = { .min = 17, .max = 23 },
 214         .m2 = { .min = 5, .max = 11 },
 215         .p = { .min = 14, .max = 42 },
 216         .p1 = { .min = 2, .max = 6 },
 217         .p2 = { .dot_limit = 0,
 218                 .p2_slow = 7, .p2_fast = 7
 219         },
 220         .find_pll = intel_g4x_find_best_PLL,
 221 };
 222
 223 static const intel_limit_t intel_limits_g4x_display_port = {
 224         .dot = { .min = 161670, .max = 227000 },
 225         .vco = { .min = 1750000, .max = 3500000},
 226         .n = { .min = 1, .max = 2 },
 227         .m = { .min = 97, .max = 108 },
 228         .m1 = { .min = 0x10, .max = 0x12 },
 229         .m2 = { .min = 0x05, .max = 0x06 },
 230         .p = { .min = 10, .max = 20 },
 231         .p1 = { .min = 1, .max = 2},
 232         .p2 = { .dot_limit = 0,
 233                 .p2_slow = 10, .p2_fast = 10 },
 234         .find_pll = intel_find_pll_g4x_dp,
 235 };
 236
 237 static const intel_limit_t intel_limits_pineview_sdvo = {
 238         .dot = { .min = 20000, .max = 400000},
 239         .vco = { .min = 1700000, .max = 3500000 },
 240         /* Pineview's Ncounter is a ring counter */
 241         .n = { .min = 3, .max = 6 },
 242         .m = { .min = 2, .max = 256 },
 243         /* Pineview only has one combined m divider, which we treat as m2. */
 244         .m1 = { .min = 0, .max = 0 },
 245         .m2 = { .min = 0, .max = 254 },
 246         .p = { .min = 5, .max = 80 },
 247         .p1 = { .min = 1, .max = 8 },
 248         .p2 = { .dot_limit = 200000,
 249                 .p2_slow = 10, .p2_fast = 5 },
 250         .find_pll = intel_find_best_PLL,
 251 };
 252
 253 static const intel_limit_t intel_limits_pineview_lvds = {
 254         .dot = { .min = 20000, .max = 400000 },
 255         .vco = { .min = 1700000, .max = 3500000 },
 256         .n = { .min = 3, .max = 6 },
 257         .m = { .min = 2, .max = 256 },
 258         .m1 = { .min = 0, .max = 0 },
 259         .m2 = { .min = 0, .max = 254 },
 260         .p = { .min = 7, .max = 112 },
 261         .p1 = { .min = 1, .max = 8 },
 262         .p2 = { .dot_limit = 112000,
 263                 .p2_slow = 14, .p2_fast = 14 },
 264         .find_pll = intel_find_best_PLL,
 265 };
 266
 267 /* Ironlake / Sandybridge
 268  *
 269  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 270  * the range value for them is (actual_value - 2).
 271  */
 272 static const intel_limit_t intel_limits_ironlake_dac = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 5 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283         .find_pll = intel_g4x_find_best_PLL,
 284 };
 285
 286 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 3 },
 290         .m = { .min = 79, .max = 118 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297         .find_pll = intel_g4x_find_best_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 3 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 14, .max = 56 },
 308         .p1 = { .min = 2, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 7, .p2_fast = 7 },
 311         .find_pll = intel_g4x_find_best_PLL,
 312 };
 313
 314 /* LVDS 100mhz refclk limits. */
 315 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 316         .dot = { .min = 25000, .max = 350000 },
 317         .vco = { .min = 1760000, .max = 3510000 },
 318         .n = { .min = 1, .max = 2 },
 319         .m = { .min = 79, .max = 126 },
 320         .m1 = { .min = 12, .max = 22 },
 321         .m2 = { .min = 5, .max = 9 },
 322         .p = { .min = 28, .max = 112 },
 323         .p1 = { .min = 2,.max = 8 },
 324         .p2 = { .dot_limit = 225000,
 325                 .p2_slow = 14, .p2_fast = 14 },
 326         .find_pll = intel_g4x_find_best_PLL,
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 126 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 42 },
 337         .p1 = { .min = 2,.max = 6 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340         .find_pll = intel_g4x_find_best_PLL,
 341 };
 342
 343 static const intel_limit_t intel_limits_ironlake_display_port = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000},
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 81, .max = 90 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 10, .max = 20 },
 351         .p1 = { .min = 1, .max = 2},
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 10, .p2_fast = 10 },
 354         .find_pll = intel_find_pll_ironlake_dp,
 355 };
 356
 357 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 358                                                 int refclk)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         struct drm_i915_private *dev_priv = dev->dev_private;
 362         const intel_limit_t *limit;
 363
 364         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 365                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 366                     LVDS_CLKB_POWER_UP) {
 367                         /* LVDS dual channel */
 368                         if (refclk == 100000)
 369                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 370                         else
 371                                 limit = &intel_limits_ironlake_dual_lvds;
 372                 } else {
 373                         if (refclk == 100000)
 374                                 limit = &intel_limits_ironlake_single_lvds_100m;
 375                         else
 376                                 limit = &intel_limits_ironlake_single_lvds;
 377                 }
 378         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 379                         HAS_eDP)
 380                 limit = &intel_limits_ironlake_display_port;
 381         else
 382                 limit = &intel_limits_ironlake_dac;
 383
 384         return limit;
 385 }
 386
 387 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 388 {
 389         struct drm_device *dev = crtc->dev;
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         const intel_limit_t *limit;
 392
 393         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 394                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 395                     LVDS_CLKB_POWER_UP)
 396                         /* LVDS with dual channel */
 397                         limit = &intel_limits_g4x_dual_channel_lvds;
 398                 else
 399                         /* LVDS with dual channel */
 400                         limit = &intel_limits_g4x_single_channel_lvds;
 401         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 402                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 403                 limit = &intel_limits_g4x_hdmi;
 404         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 405                 limit = &intel_limits_g4x_sdvo;
 406         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 407                 limit = &intel_limits_g4x_display_port;
 408         } else /* The option is for other outputs */
 409                 limit = &intel_limits_i9xx_sdvo;
 410
 411         return limit;
 412 }
 413
 414 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 415 {
 416         struct drm_device *dev = crtc->dev;
 417         const intel_limit_t *limit;
 418
 419         if (HAS_PCH_SPLIT(dev))
 420                 limit = intel_ironlake_limit(crtc, refclk);
 421         else if (IS_G4X(dev)) {
 422                 limit = intel_g4x_limit(crtc);
 423         } else if (IS_PINEVIEW(dev)) {
 424                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 425                         limit = &intel_limits_pineview_lvds;
 426                 else
 427                         limit = &intel_limits_pineview_sdvo;
 428         } else if (!IS_GEN2(dev)) {
 429                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 430                         limit = &intel_limits_i9xx_lvds;
 431                 else
 432                         limit = &intel_limits_i9xx_sdvo;
 433         } else {
 434                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 435                         limit = &intel_limits_i8xx_lvds;
 436                 else
 437                         limit = &intel_limits_i8xx_dvo;
 438         }
 439         return limit;
 440 }
 441
 442 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 443 static void pineview_clock(int refclk, intel_clock_t *clock)
 444 {
 445         clock->m = clock->m2 + 2;
 446         clock->p = clock->p1 * clock->p2;
 447         clock->vco = refclk * clock->m / clock->n;
 448         clock->dot = clock->vco / clock->p;
 449 }
 450
 451 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 452 {
 453         if (IS_PINEVIEW(dev)) {
 454                 pineview_clock(refclk, clock);
 455                 return;
 456         }
 457         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 458         clock->p = clock->p1 * clock->p2;
 459         clock->vco = refclk * clock->m / (clock->n + 2);
 460         clock->dot = clock->vco / clock->p;
 461 }
 462
 463 /**
 464  * Returns whether any output on the specified pipe is of the specified type
 465  */
 466 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 467 {
 468         struct drm_device *dev = crtc->dev;
 469         struct drm_mode_config *mode_config = &dev->mode_config;
 470         struct intel_encoder *encoder;
 471
 472         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 473                 if (encoder->base.crtc == crtc && encoder->type == type)
 474                         return true;
 475
 476         return false;
 477 }
 478
 479 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 480 /**
 481  * Returns whether the given set of divisors are valid for a given refclk with
 482  * the given connectors.
 483  */
 484
 485 static bool intel_PLL_is_valid(struct drm_device *dev,
 486                                const intel_limit_t *limit,
 487                                const intel_clock_t *clock)
 488 {
 489         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 490                 INTELPllInvalid ("p1 out of range\n");
 491         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 492                 INTELPllInvalid ("p out of range\n");
 493         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 494                 INTELPllInvalid ("m2 out of range\n");
 495         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 496                 INTELPllInvalid ("m1 out of range\n");
 497         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 498                 INTELPllInvalid ("m1 <= m2\n");
 499         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 500                 INTELPllInvalid ("m out of range\n");
 501         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 502                 INTELPllInvalid ("n out of range\n");
 503         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 504                 INTELPllInvalid ("vco out of range\n");
 505         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 506          * connector, etc., rather than just a single range.
 507          */
 508         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 509                 INTELPllInvalid ("dot out of range\n");
 510
 511         return true;
 512 }
 513
 514 static bool
 515 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 516                     int target, int refclk, intel_clock_t *best_clock)
 517
 518 {
 519         struct drm_device *dev = crtc->dev;
 520         struct drm_i915_private *dev_priv = dev->dev_private;
 521         intel_clock_t clock;
 522         int err = target;
 523
 524         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 525             (I915_READ(LVDS)) != 0) {
 526                 /*
 527                  * For LVDS, if the panel is on, just rely on its current
 528                  * settings for dual-channel.  We haven't figured out how to
 529                  * reliably set up different single/dual channel state, if we
 530                  * even can.
 531                  */
 532                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 533                     LVDS_CLKB_POWER_UP)
 534                         clock.p2 = limit->p2.p2_fast;
 535                 else
 536                         clock.p2 = limit->p2.p2_slow;
 537         } else {
 538                 if (target < limit->p2.dot_limit)
 539                         clock.p2 = limit->p2.p2_slow;
 540                 else
 541                         clock.p2 = limit->p2.p2_fast;
 542         }
 543
 544         memset (best_clock, 0, sizeof (*best_clock));
 545
 546         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 547              clock.m1++) {
 548                 for (clock.m2 = limit->m2.min;
 549                      clock.m2 <= limit->m2.max; clock.m2++) {
 550                         /* m1 is always 0 in Pineview */
 551                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 552                                 break;
 553                         for (clock.n = limit->n.min;
 554                              clock.n <= limit->n.max; clock.n++) {
 555                                 for (clock.p1 = limit->p1.min;
 556                                         clock.p1 <= limit->p1.max; clock.p1++) {
 557                                         int this_err;
 558
 559                                         intel_clock(dev, refclk, &clock);
 560                                         if (!intel_PLL_is_valid(dev, limit,
 561                                                                 &clock))
 562                                                 continue;
 563
 564                                         this_err = abs(clock.dot - target);
 565                                         if (this_err < err) {
 566                                                 *best_clock = clock;
 567                                                 err = this_err;
 568                                         }
 569                                 }
 570                         }
 571                 }
 572         }
 573
 574         return (err != target);
 575 }
 576
 577 static bool
 578 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 579                         int target, int refclk, intel_clock_t *best_clock)
 580 {
 581         struct drm_device *dev = crtc->dev;
 582         struct drm_i915_private *dev_priv = dev->dev_private;
 583         intel_clock_t clock;
 584         int max_n;
 585         bool found;
 586         /* approximately equals target * 0.00585 */
 587         int err_most = (target >> 8) + (target >> 9);
 588         found = false;
 589
 590         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 591                 int lvds_reg;
 592
 593                 if (HAS_PCH_SPLIT(dev))
 594                         lvds_reg = PCH_LVDS;
 595                 else
 596                         lvds_reg = LVDS;
 597                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 598                     LVDS_CLKB_POWER_UP)
 599                         clock.p2 = limit->p2.p2_fast;
 600                 else
 601                         clock.p2 = limit->p2.p2_slow;
 602         } else {
 603                 if (target < limit->p2.dot_limit)
 604                         clock.p2 = limit->p2.p2_slow;
 605                 else
 606                         clock.p2 = limit->p2.p2_fast;
 607         }
 608
 609         memset(best_clock, 0, sizeof(*best_clock));
 610         max_n = limit->n.max;
 611         /* based on hardware requirement, prefer smaller n to precision */
 612         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 613                 /* based on hardware requirement, prefere larger m1,m2 */
 614                 for (clock.m1 = limit->m1.max;
 615                      clock.m1 >= limit->m1.min; clock.m1--) {
 616                         for (clock.m2 = limit->m2.max;
 617                              clock.m2 >= limit->m2.min; clock.m2--) {
 618                                 for (clock.p1 = limit->p1.max;
 619                                      clock.p1 >= limit->p1.min; clock.p1--) {
 620                                         int this_err;
 621
 622                                         intel_clock(dev, refclk, &clock);
 623                                         if (!intel_PLL_is_valid(dev, limit,
 624                                                                 &clock))
 625                                                 continue;
 626
 627                                         this_err = abs(clock.dot - target);
 628                                         if (this_err < err_most) {
 629                                                 *best_clock = clock;
 630                                                 err_most = this_err;
 631                                                 max_n = clock.n;
 632                                                 found = true;
 633                                         }
 634                                 }
 635                         }
 636                 }
 637         }
 638         return found;
 639 }
 640
 641 static bool
 642 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 643                            int target, int refclk, intel_clock_t *best_clock)
 644 {
 645         struct drm_device *dev = crtc->dev;
 646         intel_clock_t clock;
 647
 648         if (target < 200000) {
 649                 clock.n = 1;
 650                 clock.p1 = 2;
 651                 clock.p2 = 10;
 652                 clock.m1 = 12;
 653                 clock.m2 = 9;
 654         } else {
 655                 clock.n = 2;
 656                 clock.p1 = 1;
 657                 clock.p2 = 10;
 658                 clock.m1 = 14;
 659                 clock.m2 = 8;
 660         }
 661         intel_clock(dev, refclk, &clock);
 662         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 663         return true;
 664 }
 665
 666 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 667 static bool
 668 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 669                       int target, int refclk, intel_clock_t *best_clock)
 670 {
 671         intel_clock_t clock;
 672         if (target < 200000) {
 673                 clock.p1 = 2;
 674                 clock.p2 = 10;
 675                 clock.n = 2;
 676                 clock.m1 = 23;
 677                 clock.m2 = 8;
 678         } else {
 679                 clock.p1 = 1;
 680                 clock.p2 = 10;
 681                 clock.n = 1;
 682                 clock.m1 = 14;
 683                 clock.m2 = 2;
 684         }
 685         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 686         clock.p = (clock.p1 * clock.p2);
 687         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 688         clock.vco = 0;
 689         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 690         return true;
 691 }
 692
 693 /**
 694  * intel_wait_for_vblank - wait for vblank on a given pipe
 695  * @dev: drm device
 696  * @pipe: pipe to wait for
 697  *
 698  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 699  * mode setting code.
 700  */
 701 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 702 {
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704         int pipestat_reg = PIPESTAT(pipe);
 705
 706         /* Clear existing vblank status. Note this will clear any other
 707          * sticky status fields as well.
 708          *
 709          * This races with i915_driver_irq_handler() with the result
 710          * that either function could miss a vblank event.  Here it is not
 711          * fatal, as we will either wait upon the next vblank interrupt or
 712          * timeout.  Generally speaking intel_wait_for_vblank() is only
 713          * called during modeset at which time the GPU should be idle and
 714          * should *not* be performing page flips and thus not waiting on
 715          * vblanks...
 716          * Currently, the result of us stealing a vblank from the irq
 717          * handler is that a single frame will be skipped during swapbuffers.
 718          */
 719         I915_WRITE(pipestat_reg,
 720                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 721
 722         /* Wait for vblank interrupt bit to set */
 723         if (wait_for(I915_READ(pipestat_reg) &
 724                      PIPE_VBLANK_INTERRUPT_STATUS,
 725                      50))
 726                 DRM_DEBUG_KMS("vblank wait timed out\n");
 727 }
 728
 729 /*
 730  * intel_wait_for_pipe_off - wait for pipe to turn off
 731  * @dev: drm device
 732  * @pipe: pipe to wait for
 733  *
 734  * After disabling a pipe, we can't wait for vblank in the usual way,
 735  * spinning on the vblank interrupt status bit, since we won't actually
 736  * see an interrupt when the pipe is disabled.
 737  *
 738  * On Gen4 and above:
 739  *   wait for the pipe register state bit to turn off
 740  *
 741  * Otherwise:
 742  *   wait for the display line value to settle (it usually
 743  *   ends up stopping at the start of the next frame).
 744  *
 745  */
 746 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 747 {
 748         struct drm_i915_private *dev_priv = dev->dev_private;
 749
 750         if (INTEL_INFO(dev)->gen >= 4) {
 751                 int reg = PIPECONF(pipe);
 752
 753                 /* Wait for the Pipe State to go off */
 754                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 755                              100))
 756                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 757         } else {
 758                 u32 last_line;
 759                 int reg = PIPEDSL(pipe);
 760                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 761
 762                 /* Wait for the display line to settle */
 763                 do {
 764                         last_line = I915_READ(reg) & DSL_LINEMASK;
 765                         mdelay(5);
 766                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 767                          time_after(timeout, jiffies));
 768                 if (time_after(jiffies, timeout))
 769                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 770         }
 771 }
 772
 773 static const char *state_string(bool enabled)
 774 {
 775         return enabled ? "on" : "off";
 776 }
 777
 778 /* Only for pre-ILK configs */
 779 static void assert_pll(struct drm_i915_private *dev_priv,
 780                        enum pipe pipe, bool state)
 781 {
 782         int reg;
 783         u32 val;
 784         bool cur_state;
 785
 786         reg = DPLL(pipe);
 787         val = I915_READ(reg);
 788         cur_state = !!(val & DPLL_VCO_ENABLE);
 789         WARN(cur_state != state,
 790              "PLL state assertion failure (expected %s, current %s)\n",
 791              state_string(state), state_string(cur_state));
 792 }
 793 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 794 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 795
 796 /* For ILK+ */
 797 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 798                            enum pipe pipe, bool state)
 799 {
 800         int reg;
 801         u32 val;
 802         bool cur_state;
 803
 804         reg = PCH_DPLL(pipe);
 805         val = I915_READ(reg);
 806         cur_state = !!(val & DPLL_VCO_ENABLE);
 807         WARN(cur_state != state,
 808              "PCH PLL state assertion failure (expected %s, current %s)\n",
 809              state_string(state), state_string(cur_state));
 810 }
 811 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 812 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 813
 814 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 815                           enum pipe pipe, bool state)
 816 {
 817         int reg;
 818         u32 val;
 819         bool cur_state;
 820
 821         reg = FDI_TX_CTL(pipe);
 822         val = I915_READ(reg);
 823         cur_state = !!(val & FDI_TX_ENABLE);
 824         WARN(cur_state != state,
 825              "FDI TX state assertion failure (expected %s, current %s)\n",
 826              state_string(state), state_string(cur_state));
 827 }
 828 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 829 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 830
 831 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 832                           enum pipe pipe, bool state)
 833 {
 834         int reg;
 835         u32 val;
 836         bool cur_state;
 837
 838         reg = FDI_RX_CTL(pipe);
 839         val = I915_READ(reg);
 840         cur_state = !!(val & FDI_RX_ENABLE);
 841         WARN(cur_state != state,
 842              "FDI RX state assertion failure (expected %s, current %s)\n",
 843              state_string(state), state_string(cur_state));
 844 }
 845 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 846 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 847
 848 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 849                                       enum pipe pipe)
 850 {
 851         int reg;
 852         u32 val;
 853
 854         /* ILK FDI PLL is always enabled */
 855         if (dev_priv->info->gen == 5)
 856                 return;
 857
 858         reg = FDI_TX_CTL(pipe);
 859         val = I915_READ(reg);
 860         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 861 }
 862
 863 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 864                                       enum pipe pipe)
 865 {
 866         int reg;
 867         u32 val;
 868
 869         reg = FDI_RX_CTL(pipe);
 870         val = I915_READ(reg);
 871         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 872 }
 873
 874 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 875                                   enum pipe pipe)
 876 {
 877         int pp_reg, lvds_reg;
 878         u32 val;
 879         enum pipe panel_pipe = PIPE_A;
 880         bool locked = locked;
 881
 882         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 883                 pp_reg = PCH_PP_CONTROL;
 884                 lvds_reg = PCH_LVDS;
 885         } else {
 886                 pp_reg = PP_CONTROL;
 887                 lvds_reg = LVDS;
 888         }
 889
 890         val = I915_READ(pp_reg);
 891         if (!(val & PANEL_POWER_ON) ||
 892             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 893                 locked = false;
 894
 895         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 896                 panel_pipe = PIPE_B;
 897
 898         WARN(panel_pipe == pipe && locked,
 899              "panel assertion failure, pipe %c regs locked\n",
 900              pipe_name(pipe));
 901 }
 902
 903 static void assert_pipe(struct drm_i915_private *dev_priv,
 904                         enum pipe pipe, bool state)
 905 {
 906         int reg;
 907         u32 val;
 908         bool cur_state;
 909
 910         reg = PIPECONF(pipe);
 911         val = I915_READ(reg);
 912         cur_state = !!(val & PIPECONF_ENABLE);
 913         WARN(cur_state != state,
 914              "pipe %c assertion failure (expected %s, current %s)\n",
 915              pipe_name(pipe), state_string(state), state_string(cur_state));
 916 }
 917 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 918 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 919
 920 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 921                                  enum plane plane)
 922 {
 923         int reg;
 924         u32 val;
 925
 926         reg = DSPCNTR(plane);
 927         val = I915_READ(reg);
 928         WARN(!(val & DISPLAY_PLANE_ENABLE),
 929              "plane %c assertion failure, should be active but is disabled\n",
 930              plane_name(plane));
 931 }
 932
 933 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 934                                    enum pipe pipe)
 935 {
 936         int reg, i;
 937         u32 val;
 938         int cur_pipe;
 939
 940         /* Planes are fixed to pipes on ILK+ */
 941         if (HAS_PCH_SPLIT(dev_priv->dev))
 942                 return;
 943
 944         /* Need to check both planes against the pipe */
 945         for (i = 0; i < 2; i++) {
 946                 reg = DSPCNTR(i);
 947                 val = I915_READ(reg);
 948                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 949                         DISPPLANE_SEL_PIPE_SHIFT;
 950                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 951                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 952                      plane_name(i), pipe_name(pipe));
 953         }
 954 }
 955
 956 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 957 {
 958         u32 val;
 959         bool enabled;
 960
 961         val = I915_READ(PCH_DREF_CONTROL);
 962         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 963                             DREF_SUPERSPREAD_SOURCE_MASK));
 964         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 965 }
 966
 967 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 968                                        enum pipe pipe)
 969 {
 970         int reg;
 971         u32 val;
 972         bool enabled;
 973
 974         reg = TRANSCONF(pipe);
 975         val = I915_READ(reg);
 976         enabled = !!(val & TRANS_ENABLE);
 977         WARN(enabled,
 978              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 979              pipe_name(pipe));
 980 }
 981
 982 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
 983                                    enum pipe pipe, int reg)
 984 {
 985         u32 val = I915_READ(reg);
 986         WARN(DP_PIPE_ENABLED(val, pipe),
 987              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 988              reg, pipe_name(pipe));
 989 }
 990
 991 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 992                                      enum pipe pipe, int reg)
 993 {
 994         u32 val = I915_READ(reg);
 995         WARN(HDMI_PIPE_ENABLED(val, pipe),
 996              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
 997              reg, pipe_name(pipe));
 998 }
 999
1000 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1001                                       enum pipe pipe)
1002 {
1003         int reg;
1004         u32 val;
1005
1006         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1007         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1008         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1009
1010         reg = PCH_ADPA;
1011         val = I915_READ(reg);
1012         WARN(ADPA_PIPE_ENABLED(val, pipe),
1013              "PCH VGA enabled on transcoder %c, should be disabled\n",
1014              pipe_name(pipe));
1015
1016         reg = PCH_LVDS;
1017         val = I915_READ(reg);
1018         WARN(LVDS_PIPE_ENABLED(val, pipe),
1019              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1020              pipe_name(pipe));
1021
1022         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1023         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1024         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1025 }
1026
1027 /**
1028  * intel_enable_pll - enable a PLL
1029  * @dev_priv: i915 private structure
1030  * @pipe: pipe PLL to enable
1031  *
1032  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1033  * make sure the PLL reg is writable first though, since the panel write
1034  * protect mechanism may be enabled.
1035  *
1036  * Note!  This is for pre-ILK only.
1037  */
1038 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1039 {
1040         int reg;
1041         u32 val;
1042
1043         /* No really, not for ILK+ */
1044         BUG_ON(dev_priv->info->gen >= 5);
1045
1046         /* PLL is protected by panel, make sure we can write it */
1047         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1048                 assert_panel_unlocked(dev_priv, pipe);
1049
1050         reg = DPLL(pipe);
1051         val = I915_READ(reg);
1052         val |= DPLL_VCO_ENABLE;
1053
1054         /* We do this three times for luck */
1055         I915_WRITE(reg, val);
1056         POSTING_READ(reg);
1057         udelay(150); /* wait for warmup */
1058         I915_WRITE(reg, val);
1059         POSTING_READ(reg);
1060         udelay(150); /* wait for warmup */
1061         I915_WRITE(reg, val);
1062         POSTING_READ(reg);
1063         udelay(150); /* wait for warmup */
1064 }
1065
1066 /**
1067  * intel_disable_pll - disable a PLL
1068  * @dev_priv: i915 private structure
1069  * @pipe: pipe PLL to disable
1070  *
1071  * Disable the PLL for @pipe, making sure the pipe is off first.
1072  *
1073  * Note!  This is for pre-ILK only.
1074  */
1075 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1076 {
1077         int reg;
1078         u32 val;
1079
1080         /* Don't disable pipe A or pipe A PLLs if needed */
1081         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1082                 return;
1083
1084         /* Make sure the pipe isn't still relying on us */
1085         assert_pipe_disabled(dev_priv, pipe);
1086
1087         reg = DPLL(pipe);
1088         val = I915_READ(reg);
1089         val &= ~DPLL_VCO_ENABLE;
1090         I915_WRITE(reg, val);
1091         POSTING_READ(reg);
1092 }
1093
1094 /**
1095  * intel_enable_pch_pll - enable PCH PLL
1096  * @dev_priv: i915 private structure
1097  * @pipe: pipe PLL to enable
1098  *
1099  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1100  * drives the transcoder clock.
1101  */
1102 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1103                                  enum pipe pipe)
1104 {
1105         int reg;
1106         u32 val;
1107
1108         /* PCH only available on ILK+ */
1109         BUG_ON(dev_priv->info->gen < 5);
1110
1111         /* PCH refclock must be enabled first */
1112         assert_pch_refclk_enabled(dev_priv);
1113
1114         reg = PCH_DPLL(pipe);
1115         val = I915_READ(reg);
1116         val |= DPLL_VCO_ENABLE;
1117         I915_WRITE(reg, val);
1118         POSTING_READ(reg);
1119         udelay(200);
1120 }
1121
1122 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1123                                   enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* PCH only available on ILK+ */
1129         BUG_ON(dev_priv->info->gen < 5);
1130
1131         /* Make sure transcoder isn't still depending on us */
1132         assert_transcoder_disabled(dev_priv, pipe);
1133
1134         reg = PCH_DPLL(pipe);
1135         val = I915_READ(reg);
1136         val &= ~DPLL_VCO_ENABLE;
1137         I915_WRITE(reg, val);
1138         POSTING_READ(reg);
1139         udelay(200);
1140 }
1141
1142 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1143                                     enum pipe pipe)
1144 {
1145         int reg;
1146         u32 val;
1147
1148         /* PCH only available on ILK+ */
1149         BUG_ON(dev_priv->info->gen < 5);
1150
1151         /* Make sure PCH DPLL is enabled */
1152         assert_pch_pll_enabled(dev_priv, pipe);
1153
1154         /* FDI must be feeding us bits for PCH ports */
1155         assert_fdi_tx_enabled(dev_priv, pipe);
1156         assert_fdi_rx_enabled(dev_priv, pipe);
1157
1158         reg = TRANSCONF(pipe);
1159         val = I915_READ(reg);
1160         /*
1161          * make the BPC in transcoder be consistent with
1162          * that in pipeconf reg.
1163          */
1164         val &= ~PIPE_BPC_MASK;
1165         val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1166         I915_WRITE(reg, val | TRANS_ENABLE);
1167         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1168                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1169 }
1170
1171 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1172                                      enum pipe pipe)
1173 {
1174         int reg;
1175         u32 val;
1176
1177         /* FDI relies on the transcoder */
1178         assert_fdi_tx_disabled(dev_priv, pipe);
1179         assert_fdi_rx_disabled(dev_priv, pipe);
1180
1181         /* Ports must be off as well */
1182         assert_pch_ports_disabled(dev_priv, pipe);
1183
1184         reg = TRANSCONF(pipe);
1185         val = I915_READ(reg);
1186         val &= ~TRANS_ENABLE;
1187         I915_WRITE(reg, val);
1188         /* wait for PCH transcoder off, transcoder state */
1189         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1190                 DRM_ERROR("failed to disable transcoder\n");
1191 }
1192
1193 /**
1194  * intel_enable_pipe - enable a pipe, asserting requirements
1195  * @dev_priv: i915 private structure
1196  * @pipe: pipe to enable
1197  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1198  *
1199  * Enable @pipe, making sure that various hardware specific requirements
1200  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1201  *
1202  * @pipe should be %PIPE_A or %PIPE_B.
1203  *
1204  * Will wait until the pipe is actually running (i.e. first vblank) before
1205  * returning.
1206  */
1207 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1208                               bool pch_port)
1209 {
1210         int reg;
1211         u32 val;
1212
1213         /*
1214          * A pipe without a PLL won't actually be able to drive bits from
1215          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1216          * need the check.
1217          */
1218         if (!HAS_PCH_SPLIT(dev_priv->dev))
1219                 assert_pll_enabled(dev_priv, pipe);
1220         else {
1221                 if (pch_port) {
1222                         /* if driving the PCH, we need FDI enabled */
1223                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1224                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1225                 }
1226                 /* FIXME: assert CPU port conditions for SNB+ */
1227         }
1228
1229         reg = PIPECONF(pipe);
1230         val = I915_READ(reg);
1231         if (val & PIPECONF_ENABLE)
1232                 return;
1233
1234         I915_WRITE(reg, val | PIPECONF_ENABLE);
1235         intel_wait_for_vblank(dev_priv->dev, pipe);
1236 }
1237
1238 /**
1239  * intel_disable_pipe - disable a pipe, asserting requirements
1240  * @dev_priv: i915 private structure
1241  * @pipe: pipe to disable
1242  *
1243  * Disable @pipe, making sure that various hardware specific requirements
1244  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1245  *
1246  * @pipe should be %PIPE_A or %PIPE_B.
1247  *
1248  * Will wait until the pipe has shut down before returning.
1249  */
1250 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1251                                enum pipe pipe)
1252 {
1253         int reg;
1254         u32 val;
1255
1256         /*
1257          * Make sure planes won't keep trying to pump pixels to us,
1258          * or we might hang the display.
1259          */
1260         assert_planes_disabled(dev_priv, pipe);
1261
1262         /* Don't disable pipe A or pipe A PLLs if needed */
1263         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1264                 return;
1265
1266         reg = PIPECONF(pipe);
1267         val = I915_READ(reg);
1268         if ((val & PIPECONF_ENABLE) == 0)
1269                 return;
1270
1271         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1272         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1273 }
1274
1275 /**
1276  * intel_enable_plane - enable a display plane on a given pipe
1277  * @dev_priv: i915 private structure
1278  * @plane: plane to enable
1279  * @pipe: pipe being fed
1280  *
1281  * Enable @plane on @pipe, making sure that @pipe is running first.
1282  */
1283 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1284                                enum plane plane, enum pipe pipe)
1285 {
1286         int reg;
1287         u32 val;
1288
1289         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1290         assert_pipe_enabled(dev_priv, pipe);
1291
1292         reg = DSPCNTR(plane);
1293         val = I915_READ(reg);
1294         if (val & DISPLAY_PLANE_ENABLE)
1295                 return;
1296
1297         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1298         intel_wait_for_vblank(dev_priv->dev, pipe);
1299 }
1300
1301 /*
1302  * Plane regs are double buffered, going from enabled->disabled needs a
1303  * trigger in order to latch.  The display address reg provides this.
1304  */
1305 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1306                                       enum plane plane)
1307 {
1308         u32 reg = DSPADDR(plane);
1309         I915_WRITE(reg, I915_READ(reg));
1310 }
1311
1312 /**
1313  * intel_disable_plane - disable a display plane
1314  * @dev_priv: i915 private structure
1315  * @plane: plane to disable
1316  * @pipe: pipe consuming the data
1317  *
1318  * Disable @plane; should be an independent operation.
1319  */
1320 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1321                                 enum plane plane, enum pipe pipe)
1322 {
1323         int reg;
1324         u32 val;
1325
1326         reg = DSPCNTR(plane);
1327         val = I915_READ(reg);
1328         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1329                 return;
1330
1331         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1332         intel_flush_display_plane(dev_priv, plane);
1333         intel_wait_for_vblank(dev_priv->dev, pipe);
1334 }
1335
1336 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1337                            enum pipe pipe, int reg)
1338 {
1339         u32 val = I915_READ(reg);
1340         if (DP_PIPE_ENABLED(val, pipe))
1341                 I915_WRITE(reg, val & ~DP_PORT_EN);
1342 }
1343
1344 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1345                              enum pipe pipe, int reg)
1346 {
1347         u32 val = I915_READ(reg);
1348         if (HDMI_PIPE_ENABLED(val, pipe))
1349                 I915_WRITE(reg, val & ~PORT_ENABLE);
1350 }
1351
1352 /* Disable any ports connected to this transcoder */
1353 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1354                                     enum pipe pipe)
1355 {
1356         u32 reg, val;
1357
1358         val = I915_READ(PCH_PP_CONTROL);
1359         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1360
1361         disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1362         disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1363         disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1364
1365         reg = PCH_ADPA;
1366         val = I915_READ(reg);
1367         if (ADPA_PIPE_ENABLED(val, pipe))
1368                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1369
1370         reg = PCH_LVDS;
1371         val = I915_READ(reg);
1372         if (LVDS_PIPE_ENABLED(val, pipe)) {
1373                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1374                 POSTING_READ(reg);
1375                 udelay(100);
1376         }
1377
1378         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1379         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1380         disable_pch_hdmi(dev_priv, pipe, HDMID);
1381 }
1382
1383 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1384 {
1385         struct drm_device *dev = crtc->dev;
1386         struct drm_i915_private *dev_priv = dev->dev_private;
1387         struct drm_framebuffer *fb = crtc->fb;
1388         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1389         struct drm_i915_gem_object *obj = intel_fb->obj;
1390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1391         int plane, i;
1392         u32 fbc_ctl, fbc_ctl2;
1393
1394         if (fb->pitch == dev_priv->cfb_pitch &&
1395             obj->fence_reg == dev_priv->cfb_fence &&
1396             intel_crtc->plane == dev_priv->cfb_plane &&
1397             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1398                 return;
1399
1400         i8xx_disable_fbc(dev);
1401
1402         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1403
1404         if (fb->pitch < dev_priv->cfb_pitch)
1405                 dev_priv->cfb_pitch = fb->pitch;
1406
1407         /* FBC_CTL wants 64B units */
1408         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1409         dev_priv->cfb_fence = obj->fence_reg;
1410         dev_priv->cfb_plane = intel_crtc->plane;
1411         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1412
1413         /* Clear old tags */
1414         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1415                 I915_WRITE(FBC_TAG + (i * 4), 0);
1416
1417         /* Set it up... */
1418         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1419         if (obj->tiling_mode != I915_TILING_NONE)
1420                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1421         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1422         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1423
1424         /* enable it... */
1425         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1426         if (IS_I945GM(dev))
1427                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1428         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1429         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1430         if (obj->tiling_mode != I915_TILING_NONE)
1431                 fbc_ctl |= dev_priv->cfb_fence;
1432         I915_WRITE(FBC_CONTROL, fbc_ctl);
1433
1434         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1435                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1436 }
1437
1438 void i8xx_disable_fbc(struct drm_device *dev)
1439 {
1440         struct drm_i915_private *dev_priv = dev->dev_private;
1441         u32 fbc_ctl;
1442
1443         /* Disable compression */
1444         fbc_ctl = I915_READ(FBC_CONTROL);
1445         if ((fbc_ctl & FBC_CTL_EN) == 0)
1446                 return;
1447
1448         fbc_ctl &= ~FBC_CTL_EN;
1449         I915_WRITE(FBC_CONTROL, fbc_ctl);
1450
1451         /* Wait for compressing bit to clear */
1452         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1453                 DRM_DEBUG_KMS("FBC idle timed out\n");
1454                 return;
1455         }
1456
1457         DRM_DEBUG_KMS("disabled FBC\n");
1458 }
1459
1460 static bool i8xx_fbc_enabled(struct drm_device *dev)
1461 {
1462         struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1465 }
1466
1467 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1468 {
1469         struct drm_device *dev = crtc->dev;
1470         struct drm_i915_private *dev_priv = dev->dev_private;
1471         struct drm_framebuffer *fb = crtc->fb;
1472         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1473         struct drm_i915_gem_object *obj = intel_fb->obj;
1474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1475         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1476         unsigned long stall_watermark = 200;
1477         u32 dpfc_ctl;
1478
1479         dpfc_ctl = I915_READ(DPFC_CONTROL);
1480         if (dpfc_ctl & DPFC_CTL_EN) {
1481                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1482                     dev_priv->cfb_fence == obj->fence_reg &&
1483                     dev_priv->cfb_plane == intel_crtc->plane &&
1484                     dev_priv->cfb_y == crtc->y)
1485                         return;
1486
1487                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1488                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1489         }
1490
1491         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1492         dev_priv->cfb_fence = obj->fence_reg;
1493         dev_priv->cfb_plane = intel_crtc->plane;
1494         dev_priv->cfb_y = crtc->y;
1495
1496         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1497         if (obj->tiling_mode != I915_TILING_NONE) {
1498                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1499                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1500         } else {
1501                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1502         }
1503
1504         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1505                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1506                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1507         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1508
1509         /* enable it... */
1510         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1511
1512         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1513 }
1514
1515 void g4x_disable_fbc(struct drm_device *dev)
1516 {
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518         u32 dpfc_ctl;
1519
1520         /* Disable compression */
1521         dpfc_ctl = I915_READ(DPFC_CONTROL);
1522         if (dpfc_ctl & DPFC_CTL_EN) {
1523                 dpfc_ctl &= ~DPFC_CTL_EN;
1524                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1525
1526                 DRM_DEBUG_KMS("disabled FBC\n");
1527         }
1528 }
1529
1530 static bool g4x_fbc_enabled(struct drm_device *dev)
1531 {
1532         struct drm_i915_private *dev_priv = dev->dev_private;
1533
1534         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1535 }
1536
1537 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1538 {
1539         struct drm_i915_private *dev_priv = dev->dev_private;
1540         u32 blt_ecoskpd;
1541
1542         /* Make sure blitter notifies FBC of writes */
1543         gen6_gt_force_wake_get(dev_priv);
1544         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1545         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1546                 GEN6_BLITTER_LOCK_SHIFT;
1547         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1548         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1549         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1550         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1551                          GEN6_BLITTER_LOCK_SHIFT);
1552         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1553         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1554         gen6_gt_force_wake_put(dev_priv);
1555 }
1556
1557 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1558 {
1559         struct drm_device *dev = crtc->dev;
1560         struct drm_i915_private *dev_priv = dev->dev_private;
1561         struct drm_framebuffer *fb = crtc->fb;
1562         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1563         struct drm_i915_gem_object *obj = intel_fb->obj;
1564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1565         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1566         unsigned long stall_watermark = 200;
1567         u32 dpfc_ctl;
1568
1569         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1570         if (dpfc_ctl & DPFC_CTL_EN) {
1571                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1572                     dev_priv->cfb_fence == obj->fence_reg &&
1573                     dev_priv->cfb_plane == intel_crtc->plane &&
1574                     dev_priv->cfb_offset == obj->gtt_offset &&
1575                     dev_priv->cfb_y == crtc->y)
1576                         return;
1577
1578                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1579                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1580         }
1581
1582         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1583         dev_priv->cfb_fence = obj->fence_reg;
1584         dev_priv->cfb_plane = intel_crtc->plane;
1585         dev_priv->cfb_offset = obj->gtt_offset;
1586         dev_priv->cfb_y = crtc->y;
1587
1588         dpfc_ctl &= DPFC_RESERVED;
1589         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1590         if (obj->tiling_mode != I915_TILING_NONE) {
1591                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1592                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1593         } else {
1594                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1595         }
1596
1597         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1598                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1599                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1600         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1601         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1602         /* enable it... */
1603         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1604
1605         if (IS_GEN6(dev)) {
1606                 I915_WRITE(SNB_DPFC_CTL_SA,
1607                            SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1608                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1609                 sandybridge_blit_fbc_update(dev);
1610         }
1611
1612         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1613 }
1614
1615 void ironlake_disable_fbc(struct drm_device *dev)
1616 {
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618         u32 dpfc_ctl;
1619
1620         /* Disable compression */
1621         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1622         if (dpfc_ctl & DPFC_CTL_EN) {
1623                 dpfc_ctl &= ~DPFC_CTL_EN;
1624                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1625
1626                 DRM_DEBUG_KMS("disabled FBC\n");
1627         }
1628 }
1629
1630 static bool ironlake_fbc_enabled(struct drm_device *dev)
1631 {
1632         struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1635 }
1636
1637 bool intel_fbc_enabled(struct drm_device *dev)
1638 {
1639         struct drm_i915_private *dev_priv = dev->dev_private;
1640
1641         if (!dev_priv->display.fbc_enabled)
1642                 return false;
1643
1644         return dev_priv->display.fbc_enabled(dev);
1645 }
1646
1647 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1648 {
1649         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1650
1651         if (!dev_priv->display.enable_fbc)
1652                 return;
1653
1654         dev_priv->display.enable_fbc(crtc, interval);
1655 }
1656
1657 void intel_disable_fbc(struct drm_device *dev)
1658 {
1659         struct drm_i915_private *dev_priv = dev->dev_private;
1660
1661         if (!dev_priv->display.disable_fbc)
1662                 return;
1663
1664         dev_priv->display.disable_fbc(dev);
1665 }
1666
1667 /**
1668  * intel_update_fbc - enable/disable FBC as needed
1669  * @dev: the drm_device
1670  *
1671  * Set up the framebuffer compression hardware at mode set time.  We
1672  * enable it if possible:
1673  *   - plane A only (on pre-965)
1674  *   - no pixel mulitply/line duplication
1675  *   - no alpha buffer discard
1676  *   - no dual wide
1677  *   - framebuffer <= 2048 in width, 1536 in height
1678  *
1679  * We can't assume that any compression will take place (worst case),
1680  * so the compressed buffer has to be the same size as the uncompressed
1681  * one.  It also must reside (along with the line length buffer) in
1682  * stolen memory.
1683  *
1684  * We need to enable/disable FBC on a global basis.
1685  */
1686 static void intel_update_fbc(struct drm_device *dev)
1687 {
1688         struct drm_i915_private *dev_priv = dev->dev_private;
1689         struct drm_crtc *crtc = NULL, *tmp_crtc;
1690         struct intel_crtc *intel_crtc;
1691         struct drm_framebuffer *fb;
1692         struct intel_framebuffer *intel_fb;
1693         struct drm_i915_gem_object *obj;
1694
1695         DRM_DEBUG_KMS("\n");
1696
1697         if (!i915_powersave)
1698                 return;
1699
1700         if (!I915_HAS_FBC(dev))
1701                 return;
1702
1703         /*
1704          * If FBC is already on, we just have to verify that we can
1705          * keep it that way...
1706          * Need to disable if:
1707          *   - more than one pipe is active
1708          *   - changing FBC params (stride, fence, mode)
1709          *   - new fb is too large to fit in compressed buffer
1710          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1711          */
1712         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1713                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1714                         if (crtc) {
1715                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1716                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1717                                 goto out_disable;
1718                         }
1719                         crtc = tmp_crtc;
1720                 }
1721         }
1722
1723         if (!crtc || crtc->fb == NULL) {
1724                 DRM_DEBUG_KMS("no output, disabling\n");
1725                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1726                 goto out_disable;
1727         }
1728
1729         intel_crtc = to_intel_crtc(crtc);
1730         fb = crtc->fb;
1731         intel_fb = to_intel_framebuffer(fb);
1732         obj = intel_fb->obj;
1733
1734         if (!i915_enable_fbc) {
1735                 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1736                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1737                 goto out_disable;
1738         }
1739         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1740                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1741                               "compression\n");
1742                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1743                 goto out_disable;
1744         }
1745         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1746             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1747                 DRM_DEBUG_KMS("mode incompatible with compression, "
1748                               "disabling\n");
1749                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1750                 goto out_disable;
1751         }
1752         if ((crtc->mode.hdisplay > 2048) ||
1753             (crtc->mode.vdisplay > 1536)) {
1754                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1755                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1756                 goto out_disable;
1757         }
1758         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1759                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1760                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1761                 goto out_disable;
1762         }
1763         if (obj->tiling_mode != I915_TILING_X) {
1764                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1765                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1766                 goto out_disable;
1767         }
1768
1769         /* If the kernel debugger is active, always disable compression */
1770         if (in_dbg_master())
1771                 goto out_disable;
1772
1773         intel_enable_fbc(crtc, 500);
1774         return;
1775
1776 out_disable:
1777         /* Multiple disables should be harmless */
1778         if (intel_fbc_enabled(dev)) {
1779                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1780                 intel_disable_fbc(dev);
1781         }
1782 }
1783
1784 int
1785 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1786                            struct drm_i915_gem_object *obj,
1787                            struct intel_ring_buffer *pipelined)
1788 {
1789         struct drm_i915_private *dev_priv = dev->dev_private;
1790         u32 alignment;
1791         int ret;
1792
1793         switch (obj->tiling_mode) {
1794         case I915_TILING_NONE:
1795                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1796                         alignment = 128 * 1024;
1797                 else if (INTEL_INFO(dev)->gen >= 4)
1798                         alignment = 4 * 1024;
1799                 else
1800                         alignment = 64 * 1024;
1801                 break;
1802         case I915_TILING_X:
1803                 /* pin() will align the object as required by fence */
1804                 alignment = 0;
1805                 break;
1806         case I915_TILING_Y:
1807                 /* FIXME: Is this true? */
1808                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1809                 return -EINVAL;
1810         default:
1811                 BUG();
1812         }
1813
1814         dev_priv->mm.interruptible = false;
1815         ret = i915_gem_object_pin(obj, alignment, true);
1816         if (ret)
1817                 goto err_interruptible;
1818
1819         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1820         if (ret)
1821                 goto err_unpin;
1822
1823         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1824          * fence, whereas 965+ only requires a fence if using
1825          * framebuffer compression.  For simplicity, we always install
1826          * a fence as the cost is not that onerous.
1827          */
1828         if (obj->tiling_mode != I915_TILING_NONE) {
1829                 ret = i915_gem_object_get_fence(obj, pipelined);
1830                 if (ret)
1831                         goto err_unpin;
1832         }
1833
1834         dev_priv->mm.interruptible = true;
1835         return 0;
1836
1837 err_unpin:
1838         i915_gem_object_unpin(obj);
1839 err_interruptible:
1840         dev_priv->mm.interruptible = true;
1841         return ret;
1842 }
1843
1844 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1845 static int
1846 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1847                            int x, int y, enum mode_set_atomic state)
1848 {
1849         struct drm_device *dev = crtc->dev;
1850         struct drm_i915_private *dev_priv = dev->dev_private;
1851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1852         struct intel_framebuffer *intel_fb;
1853         struct drm_i915_gem_object *obj;
1854         int plane = intel_crtc->plane;
1855         unsigned long Start, Offset;
1856         u32 dspcntr;
1857         u32 reg;
1858
1859         switch (plane) {
1860         case 0:
1861         case 1:
1862                 break;
1863         default:
1864                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1865                 return -EINVAL;
1866         }
1867
1868         intel_fb = to_intel_framebuffer(fb);
1869         obj = intel_fb->obj;
1870
1871         reg = DSPCNTR(plane);
1872         dspcntr = I915_READ(reg);
1873         /* Mask out pixel format bits in case we change it */
1874         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1875         switch (fb->bits_per_pixel) {
1876         case 8:
1877                 dspcntr |= DISPPLANE_8BPP;
1878                 break;
1879         case 16:
1880                 if (fb->depth == 15)
1881                         dspcntr |= DISPPLANE_15_16BPP;
1882                 else
1883                         dspcntr |= DISPPLANE_16BPP;
1884                 break;
1885         case 24:
1886         case 32:
1887                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1888                 break;
1889         default:
1890                 DRM_ERROR("Unknown color depth\n");
1891                 return -EINVAL;
1892         }
1893         if (INTEL_INFO(dev)->gen >= 4) {
1894                 if (obj->tiling_mode != I915_TILING_NONE)
1895                         dspcntr |= DISPPLANE_TILED;
1896                 else
1897                         dspcntr &= ~DISPPLANE_TILED;
1898         }
1899
1900         if (HAS_PCH_SPLIT(dev))
1901                 /* must disable */
1902                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1903
1904         I915_WRITE(reg, dspcntr);
1905
1906         Start = obj->gtt_offset;
1907         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1908
1909         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1910                       Start, Offset, x, y, fb->pitch);
1911         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1912         if (INTEL_INFO(dev)->gen >= 4) {
1913                 I915_WRITE(DSPSURF(plane), Start);
1914                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1915                 I915_WRITE(DSPADDR(plane), Offset);
1916         } else
1917                 I915_WRITE(DSPADDR(plane), Start + Offset);
1918         POSTING_READ(reg);
1919
1920         intel_update_fbc(dev);
1921         intel_increase_pllclock(crtc);
1922
1923         return 0;
1924 }
1925
1926 static int
1927 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1928                     struct drm_framebuffer *old_fb)
1929 {
1930         struct drm_device *dev = crtc->dev;
1931         struct drm_i915_master_private *master_priv;
1932         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1933         int ret;
1934
1935         /* no fb bound */
1936         if (!crtc->fb) {
1937                 DRM_DEBUG_KMS("No FB bound\n");
1938                 return 0;
1939         }
1940
1941         switch (intel_crtc->plane) {
1942         case 0:
1943         case 1:
1944                 break;
1945         default:
1946                 return -EINVAL;
1947         }
1948
1949         mutex_lock(&dev->struct_mutex);
1950         ret = intel_pin_and_fence_fb_obj(dev,
1951                                          to_intel_framebuffer(crtc->fb)->obj,
1952                                          NULL);
1953         if (ret != 0) {
1954                 mutex_unlock(&dev->struct_mutex);
1955                 return ret;
1956         }
1957
1958         if (old_fb) {
1959                 struct drm_i915_private *dev_priv = dev->dev_private;
1960                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1961
1962                 wait_event(dev_priv->pending_flip_queue,
1963                            atomic_read(&dev_priv->mm.wedged) ||
1964                            atomic_read(&obj->pending_flip) == 0);
1965
1966                 /* Big Hammer, we also need to ensure that any pending
1967                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1968                  * current scanout is retired before unpinning the old
1969                  * framebuffer.
1970                  *
1971                  * This should only fail upon a hung GPU, in which case we
1972                  * can safely continue.
1973                  */
1974                 ret = i915_gem_object_flush_gpu(obj);
1975                 (void) ret;
1976         }
1977
1978         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1979                                          LEAVE_ATOMIC_MODE_SET);
1980         if (ret) {
1981                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1982                 mutex_unlock(&dev->struct_mutex);
1983                 return ret;
1984         }
1985
1986         if (old_fb) {
1987                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1988                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1989         }
1990
1991         mutex_unlock(&dev->struct_mutex);
1992
1993         if (!dev->primary->master)
1994                 return 0;
1995
1996         master_priv = dev->primary->master->driver_priv;
1997         if (!master_priv->sarea_priv)
1998                 return 0;
1999
2000         if (intel_crtc->pipe) {
2001                 master_priv->sarea_priv->pipeB_x = x;
2002                 master_priv->sarea_priv->pipeB_y = y;
2003         } else {
2004                 master_priv->sarea_priv->pipeA_x = x;
2005                 master_priv->sarea_priv->pipeA_y = y;
2006         }
2007
2008         return 0;
2009 }
2010
2011 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2012 {
2013         struct drm_device *dev = crtc->dev;
2014         struct drm_i915_private *dev_priv = dev->dev_private;
2015         u32 dpa_ctl;
2016
2017         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2018         dpa_ctl = I915_READ(DP_A);
2019         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2020
2021         if (clock < 200000) {
2022                 u32 temp;
2023                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2024                 /* workaround for 160Mhz:
2025                    1) program 0x4600c bits 15:0 = 0x8124
2026                    2) program 0x46010 bit 0 = 1
2027                    3) program 0x46034 bit 24 = 1
2028                    4) program 0x64000 bit 14 = 1
2029                    */
2030                 temp = I915_READ(0x4600c);
2031                 temp &= 0xffff0000;
2032                 I915_WRITE(0x4600c, temp | 0x8124);
2033
2034                 temp = I915_READ(0x46010);
2035                 I915_WRITE(0x46010, temp | 1);
2036
2037                 temp = I915_READ(0x46034);
2038                 I915_WRITE(0x46034, temp | (1 << 24));
2039         } else {
2040                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2041         }
2042         I915_WRITE(DP_A, dpa_ctl);
2043
2044         POSTING_READ(DP_A);
2045         udelay(500);
2046 }
2047
2048 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2049 {
2050         struct drm_device *dev = crtc->dev;
2051         struct drm_i915_private *dev_priv = dev->dev_private;
2052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2053         int pipe = intel_crtc->pipe;
2054         u32 reg, temp;
2055
2056         /* enable normal train */
2057         reg = FDI_TX_CTL(pipe);
2058         temp = I915_READ(reg);
2059         if (IS_IVYBRIDGE(dev)) {
2060                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2061                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2062         } else {
2063                 temp &= ~FDI_LINK_TRAIN_NONE;
2064                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2065         }
2066         I915_WRITE(reg, temp);
2067
2068         reg = FDI_RX_CTL(pipe);
2069         temp = I915_READ(reg);
2070         if (HAS_PCH_CPT(dev)) {
2071                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2072                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2073         } else {
2074                 temp &= ~FDI_LINK_TRAIN_NONE;
2075                 temp |= FDI_LINK_TRAIN_NONE;
2076         }
2077         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2078
2079         /* wait one idle pattern time */
2080         POSTING_READ(reg);
2081         udelay(1000);
2082
2083         /* IVB wants error correction enabled */
2084         if (IS_IVYBRIDGE(dev))
2085                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2086                            FDI_FE_ERRC_ENABLE);
2087 }
2088
2089 /* The FDI link training functions for ILK/Ibexpeak. */
2090 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2091 {
2092         struct drm_device *dev = crtc->dev;
2093         struct drm_i915_private *dev_priv = dev->dev_private;
2094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2095         int pipe = intel_crtc->pipe;
2096         int plane = intel_crtc->plane;
2097         u32 reg, temp, tries;
2098
2099         /* FDI needs bits from pipe & plane first */
2100         assert_pipe_enabled(dev_priv, pipe);
2101         assert_plane_enabled(dev_priv, plane);
2102
2103         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2104            for train result */
2105         reg = FDI_RX_IMR(pipe);
2106         temp = I915_READ(reg);
2107         temp &= ~FDI_RX_SYMBOL_LOCK;
2108         temp &= ~FDI_RX_BIT_LOCK;
2109         I915_WRITE(reg, temp);
2110         I915_READ(reg);
2111         udelay(150);
2112
2113         /* enable CPU FDI TX and PCH FDI RX */
2114         reg = FDI_TX_CTL(pipe);
2115         temp = I915_READ(reg);
2116         temp &= ~(7 << 19);
2117         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2118         temp &= ~FDI_LINK_TRAIN_NONE;
2119         temp |= FDI_LINK_TRAIN_PATTERN_1;
2120         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2121
2122         reg = FDI_RX_CTL(pipe);
2123         temp = I915_READ(reg);
2124         temp &= ~FDI_LINK_TRAIN_NONE;
2125         temp |= FDI_LINK_TRAIN_PATTERN_1;
2126         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2127
2128         POSTING_READ(reg);
2129         udelay(150);
2130
2131         /* Ironlake workaround, enable clock pointer after FDI enable*/
2132         if (HAS_PCH_IBX(dev)) {
2133                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2134                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2135                            FDI_RX_PHASE_SYNC_POINTER_EN);
2136         }
2137
2138         reg = FDI_RX_IIR(pipe);
2139         for (tries = 0; tries < 5; tries++) {
2140                 temp = I915_READ(reg);
2141                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2142
2143                 if ((temp & FDI_RX_BIT_LOCK)) {
2144                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2145                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2146                         break;
2147                 }
2148         }
2149         if (tries == 5)
2150                 DRM_ERROR("FDI train 1 fail!\n");
2151
2152         /* Train 2 */
2153         reg = FDI_TX_CTL(pipe);
2154         temp = I915_READ(reg);
2155         temp &= ~FDI_LINK_TRAIN_NONE;
2156         temp |= FDI_LINK_TRAIN_PATTERN_2;
2157         I915_WRITE(reg, temp);
2158
2159         reg = FDI_RX_CTL(pipe);
2160         temp = I915_READ(reg);
2161         temp &= ~FDI_LINK_TRAIN_NONE;
2162         temp |= FDI_LINK_TRAIN_PATTERN_2;
2163         I915_WRITE(reg, temp);
2164
2165         POSTING_READ(reg);
2166         udelay(150);
2167
2168         reg = FDI_RX_IIR(pipe);
2169         for (tries = 0; tries < 5; tries++) {
2170                 temp = I915_READ(reg);
2171                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2172
2173                 if (temp & FDI_RX_SYMBOL_LOCK) {
2174                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2175                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2176                         break;
2177                 }
2178         }
2179         if (tries == 5)
2180                 DRM_ERROR("FDI train 2 fail!\n");
2181
2182         DRM_DEBUG_KMS("FDI train done\n");
2183
2184 }
2185
2186 static const int snb_b_fdi_train_param [] = {
2187         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2188         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2189         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2190         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2191 };
2192
2193 /* The FDI link training functions for SNB/Cougarpoint. */
2194 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2195 {
2196         struct drm_device *dev = crtc->dev;
2197         struct drm_i915_private *dev_priv = dev->dev_private;
2198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2199         int pipe = intel_crtc->pipe;
2200         u32 reg, temp, i;
2201
2202         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2203            for train result */
2204         reg = FDI_RX_IMR(pipe);
2205         temp = I915_READ(reg);
2206         temp &= ~FDI_RX_SYMBOL_LOCK;
2207         temp &= ~FDI_RX_BIT_LOCK;
2208         I915_WRITE(reg, temp);
2209
2210         POSTING_READ(reg);
2211         udelay(150);
2212
2213         /* enable CPU FDI TX and PCH FDI RX */
2214         reg = FDI_TX_CTL(pipe);
2215         temp = I915_READ(reg);
2216         temp &= ~(7 << 19);
2217         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2218         temp &= ~FDI_LINK_TRAIN_NONE;
2219         temp |= FDI_LINK_TRAIN_PATTERN_1;
2220         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2221         /* SNB-B */
2222         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2223         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2224
2225         reg = FDI_RX_CTL(pipe);
2226         temp = I915_READ(reg);
2227         if (HAS_PCH_CPT(dev)) {
2228                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2229                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2230         } else {
2231                 temp &= ~FDI_LINK_TRAIN_NONE;
2232                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2233         }
2234         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2235
2236         POSTING_READ(reg);
2237         udelay(150);
2238
2239         for (i = 0; i < 4; i++ ) {
2240                 reg = FDI_TX_CTL(pipe);
2241                 temp = I915_READ(reg);
2242                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2243                 temp |= snb_b_fdi_train_param[i];
2244                 I915_WRITE(reg, temp);
2245
2246                 POSTING_READ(reg);
2247                 udelay(500);
2248
2249                 reg = FDI_RX_IIR(pipe);
2250                 temp = I915_READ(reg);
2251                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2252
2253                 if (temp & FDI_RX_BIT_LOCK) {
2254                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2255                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2256                         break;
2257                 }
2258         }
2259         if (i == 4)
2260                 DRM_ERROR("FDI train 1 fail!\n");
2261
2262         /* Train 2 */
2263         reg = FDI_TX_CTL(pipe);
2264         temp = I915_READ(reg);
2265         temp &= ~FDI_LINK_TRAIN_NONE;
2266         temp |= FDI_LINK_TRAIN_PATTERN_2;
2267         if (IS_GEN6(dev)) {
2268                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2269                 /* SNB-B */
2270                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2271         }
2272         I915_WRITE(reg, temp);
2273
2274         reg = FDI_RX_CTL(pipe);
2275         temp = I915_READ(reg);
2276         if (HAS_PCH_CPT(dev)) {
2277                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2278                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2279         } else {
2280                 temp &= ~FDI_LINK_TRAIN_NONE;
2281                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2282         }
2283         I915_WRITE(reg, temp);
2284
2285         POSTING_READ(reg);
2286         udelay(150);
2287
2288         for (i = 0; i < 4; i++ ) {
2289                 reg = FDI_TX_CTL(pipe);
2290                 temp = I915_READ(reg);
2291                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2292                 temp |= snb_b_fdi_train_param[i];
2293                 I915_WRITE(reg, temp);
2294
2295                 POSTING_READ(reg);
2296                 udelay(500);
2297
2298                 reg = FDI_RX_IIR(pipe);
2299                 temp = I915_READ(reg);
2300                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2301
2302                 if (temp & FDI_RX_SYMBOL_LOCK) {
2303                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2304                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2305                         break;
2306                 }
2307         }
2308         if (i == 4)
2309                 DRM_ERROR("FDI train 2 fail!\n");
2310
2311         DRM_DEBUG_KMS("FDI train done.\n");
2312 }
2313
2314 /* Manual link training for Ivy Bridge A0 parts */
2315 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2316 {
2317         struct drm_device *dev = crtc->dev;
2318         struct drm_i915_private *dev_priv = dev->dev_private;
2319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2320         int pipe = intel_crtc->pipe;
2321         u32 reg, temp, i;
2322
2323         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2324            for train result */
2325         reg = FDI_RX_IMR(pipe);
2326         temp = I915_READ(reg);
2327         temp &= ~FDI_RX_SYMBOL_LOCK;
2328         temp &= ~FDI_RX_BIT_LOCK;
2329         I915_WRITE(reg, temp);
2330
2331         POSTING_READ(reg);
2332         udelay(150);
2333
2334         /* enable CPU FDI TX and PCH FDI RX */
2335         reg = FDI_TX_CTL(pipe);
2336         temp = I915_READ(reg);
2337         temp &= ~(7 << 19);
2338         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2339         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2340         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2341         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2342         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2343         temp |= FDI_COMPOSITE_SYNC;
2344         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2345
2346         reg = FDI_RX_CTL(pipe);
2347         temp = I915_READ(reg);
2348         temp &= ~FDI_LINK_TRAIN_AUTO;
2349         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2350         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2351         temp |= FDI_COMPOSITE_SYNC;
2352         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2353
2354         POSTING_READ(reg);
2355         udelay(150);
2356
2357         for (i = 0; i < 4; i++ ) {
2358                 reg = FDI_TX_CTL(pipe);
2359                 temp = I915_READ(reg);
2360                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2361                 temp |= snb_b_fdi_train_param[i];
2362                 I915_WRITE(reg, temp);
2363
2364                 POSTING_READ(reg);
2365                 udelay(500);
2366
2367                 reg = FDI_RX_IIR(pipe);
2368                 temp = I915_READ(reg);
2369                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2370
2371                 if (temp & FDI_RX_BIT_LOCK ||
2372                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2373                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2374                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2375                         break;
2376                 }
2377         }
2378         if (i == 4)
2379                 DRM_ERROR("FDI train 1 fail!\n");
2380
2381         /* Train 2 */
2382         reg = FDI_TX_CTL(pipe);
2383         temp = I915_READ(reg);
2384         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2385         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2386         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2387         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2388         I915_WRITE(reg, temp);
2389
2390         reg = FDI_RX_CTL(pipe);
2391         temp = I915_READ(reg);
2392         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2393         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2394         I915_WRITE(reg, temp);
2395
2396         POSTING_READ(reg);
2397         udelay(150);
2398
2399         for (i = 0; i < 4; i++ ) {
2400                 reg = FDI_TX_CTL(pipe);
2401                 temp = I915_READ(reg);
2402                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2403                 temp |= snb_b_fdi_train_param[i];
2404                 I915_WRITE(reg, temp);
2405
2406                 POSTING_READ(reg);
2407                 udelay(500);
2408
2409                 reg = FDI_RX_IIR(pipe);
2410                 temp = I915_READ(reg);
2411                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2412
2413                 if (temp & FDI_RX_SYMBOL_LOCK) {
2414                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2415                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2416                         break;
2417                 }
2418         }
2419         if (i == 4)
2420                 DRM_ERROR("FDI train 2 fail!\n");
2421
2422         DRM_DEBUG_KMS("FDI train done.\n");
2423 }
2424
2425 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2426 {
2427         struct drm_device *dev = crtc->dev;
2428         struct drm_i915_private *dev_priv = dev->dev_private;
2429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2430         int pipe = intel_crtc->pipe;
2431         u32 reg, temp;
2432
2433         /* Write the TU size bits so error detection works */
2434         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2435                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2436
2437         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2438         reg = FDI_RX_CTL(pipe);
2439         temp = I915_READ(reg);
2440         temp &= ~((0x7 << 19) | (0x7 << 16));
2441         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2442         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2443         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2444
2445         POSTING_READ(reg);
2446         udelay(200);
2447
2448         /* Switch from Rawclk to PCDclk */
2449         temp = I915_READ(reg);
2450         I915_WRITE(reg, temp | FDI_PCDCLK);
2451
2452         POSTING_READ(reg);
2453         udelay(200);
2454
2455         /* Enable CPU FDI TX PLL, always on for Ironlake */
2456         reg = FDI_TX_CTL(pipe);
2457         temp = I915_READ(reg);
2458         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2459                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2460
2461                 POSTING_READ(reg);
2462                 udelay(100);
2463         }
2464 }
2465
2466 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2467 {
2468         struct drm_device *dev = crtc->dev;
2469         struct drm_i915_private *dev_priv = dev->dev_private;
2470         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2471         int pipe = intel_crtc->pipe;
2472         u32 reg, temp;
2473
2474         /* disable CPU FDI tx and PCH FDI rx */
2475         reg = FDI_TX_CTL(pipe);
2476         temp = I915_READ(reg);
2477         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2478         POSTING_READ(reg);
2479
2480         reg = FDI_RX_CTL(pipe);
2481         temp = I915_READ(reg);
2482         temp &= ~(0x7 << 16);
2483         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2484         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2485
2486         POSTING_READ(reg);
2487         udelay(100);
2488
2489         /* Ironlake workaround, disable clock pointer after downing FDI */
2490         if (HAS_PCH_IBX(dev)) {
2491                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2492                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2493                            I915_READ(FDI_RX_CHICKEN(pipe) &
2494                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2495         }
2496
2497         /* still set train pattern 1 */
2498         reg = FDI_TX_CTL(pipe);
2499         temp = I915_READ(reg);
2500         temp &= ~FDI_LINK_TRAIN_NONE;
2501         temp |= FDI_LINK_TRAIN_PATTERN_1;
2502         I915_WRITE(reg, temp);
2503
2504         reg = FDI_RX_CTL(pipe);
2505         temp = I915_READ(reg);
2506         if (HAS_PCH_CPT(dev)) {
2507                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2508                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2509         } else {
2510                 temp &= ~FDI_LINK_TRAIN_NONE;
2511                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2512         }
2513         /* BPC in FDI rx is consistent with that in PIPECONF */
2514         temp &= ~(0x07 << 16);
2515         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2516         I915_WRITE(reg, temp);
2517
2518         POSTING_READ(reg);
2519         udelay(100);
2520 }
2521
2522 /*
2523  * When we disable a pipe, we need to clear any pending scanline wait events
2524  * to avoid hanging the ring, which we assume we are waiting on.
2525  */
2526 static void intel_clear_scanline_wait(struct drm_device *dev)
2527 {
2528         struct drm_i915_private *dev_priv = dev->dev_private;
2529         struct intel_ring_buffer *ring;
2530         u32 tmp;
2531
2532         if (IS_GEN2(dev))
2533                 /* Can't break the hang on i8xx */
2534                 return;
2535
2536         ring = LP_RING(dev_priv);
2537         tmp = I915_READ_CTL(ring);
2538         if (tmp & RING_WAIT)
2539                 I915_WRITE_CTL(ring, tmp);
2540 }
2541
2542 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2543 {
2544         struct drm_i915_gem_object *obj;
2545         struct drm_i915_private *dev_priv;
2546
2547         if (crtc->fb == NULL)
2548                 return;
2549
2550         obj = to_intel_framebuffer(crtc->fb)->obj;
2551         dev_priv = crtc->dev->dev_private;
2552         wait_event(dev_priv->pending_flip_queue,
2553                    atomic_read(&obj->pending_flip) == 0);
2554 }
2555
2556 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2557 {
2558         struct drm_device *dev = crtc->dev;
2559         struct drm_mode_config *mode_config = &dev->mode_config;
2560         struct intel_encoder *encoder;
2561
2562         /*
2563          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2564          * must be driven by its own crtc; no sharing is possible.
2565          */
2566         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2567                 if (encoder->base.crtc != crtc)
2568                         continue;
2569
2570                 switch (encoder->type) {
2571                 case INTEL_OUTPUT_EDP:
2572                         if (!intel_encoder_is_pch_edp(&encoder->base))
2573                                 return false;
2574                         continue;
2575                 }
2576         }
2577
2578         return true;
2579 }
2580
2581 /*
2582  * Enable PCH resources required for PCH ports:
2583  *   - PCH PLLs
2584  *   - FDI training & RX/TX
2585  *   - update transcoder timings
2586  *   - DP transcoding bits
2587  *   - transcoder
2588  */
2589 static void ironlake_pch_enable(struct drm_crtc *crtc)
2590 {
2591         struct drm_device *dev = crtc->dev;
2592         struct drm_i915_private *dev_priv = dev->dev_private;
2593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2594         int pipe = intel_crtc->pipe;
2595         u32 reg, temp;
2596
2597         /* For PCH output, training FDI link */
2598         dev_priv->display.fdi_link_train(crtc);
2599
2600         intel_enable_pch_pll(dev_priv, pipe);
2601
2602         if (HAS_PCH_CPT(dev)) {
2603                 /* Be sure PCH DPLL SEL is set */
2604                 temp = I915_READ(PCH_DPLL_SEL);
2605                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2606                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2607                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2608                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2609                 I915_WRITE(PCH_DPLL_SEL, temp);
2610         }
2611
2612         /* set transcoder timing, panel must allow it */
2613         assert_panel_unlocked(dev_priv, pipe);
2614         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2615         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2616         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2617
2618         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2619         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2620         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2621
2622         intel_fdi_normal_train(crtc);
2623
2624         /* For PCH DP, enable TRANS_DP_CTL */
2625         if (HAS_PCH_CPT(dev) &&
2626             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2627                 reg = TRANS_DP_CTL(pipe);
2628                 temp = I915_READ(reg);
2629                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2630                           TRANS_DP_SYNC_MASK |
2631                           TRANS_DP_BPC_MASK);
2632                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2633                          TRANS_DP_ENH_FRAMING);
2634                 temp |= TRANS_DP_8BPC;
2635
2636                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2637                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2638                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2639                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2640
2641                 switch (intel_trans_dp_port_sel(crtc)) {
2642                 case PCH_DP_B:
2643                         temp |= TRANS_DP_PORT_SEL_B;
2644                         break;
2645                 case PCH_DP_C:
2646                         temp |= TRANS_DP_PORT_SEL_C;
2647                         break;
2648                 case PCH_DP_D:
2649                         temp |= TRANS_DP_PORT_SEL_D;
2650                         break;
2651                 default:
2652                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2653                         temp |= TRANS_DP_PORT_SEL_B;
2654                         break;
2655                 }
2656
2657                 I915_WRITE(reg, temp);
2658         }
2659
2660         intel_enable_transcoder(dev_priv, pipe);
2661 }
2662
2663 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2664 {
2665         struct drm_device *dev = crtc->dev;
2666         struct drm_i915_private *dev_priv = dev->dev_private;
2667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2668         int pipe = intel_crtc->pipe;
2669         int plane = intel_crtc->plane;
2670         u32 temp;
2671         bool is_pch_port;
2672
2673         if (intel_crtc->active)
2674                 return;
2675
2676         intel_crtc->active = true;
2677         intel_update_watermarks(dev);
2678
2679         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2680                 temp = I915_READ(PCH_LVDS);
2681                 if ((temp & LVDS_PORT_EN) == 0)
2682                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2683         }
2684
2685         is_pch_port = intel_crtc_driving_pch(crtc);
2686
2687         if (is_pch_port)
2688                 ironlake_fdi_pll_enable(crtc);
2689         else
2690                 ironlake_fdi_disable(crtc);
2691
2692         /* Enable panel fitting for LVDS */
2693         if (dev_priv->pch_pf_size &&
2694             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2695                 /* Force use of hard-coded filter coefficients
2696                  * as some pre-programmed values are broken,
2697                  * e.g. x201.
2698                  */
2699                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2700                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2701                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2702         }
2703
2704         /*
2705          * On ILK+ LUT must be loaded before the pipe is running but with
2706          * clocks enabled
2707          */
2708         intel_crtc_load_lut(crtc);
2709
2710         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2711         intel_enable_plane(dev_priv, plane, pipe);
2712
2713         if (is_pch_port)
2714                 ironlake_pch_enable(crtc);
2715
2716         mutex_lock(&dev->struct_mutex);
2717         intel_update_fbc(dev);
2718         mutex_unlock(&dev->struct_mutex);
2719
2720         intel_crtc_update_cursor(crtc, true);
2721 }
2722
2723 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2724 {
2725         struct drm_device *dev = crtc->dev;
2726         struct drm_i915_private *dev_priv = dev->dev_private;
2727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2728         int pipe = intel_crtc->pipe;
2729         int plane = intel_crtc->plane;
2730         u32 reg, temp;
2731
2732         if (!intel_crtc->active)
2733                 return;
2734
2735         intel_crtc_wait_for_pending_flips(crtc);
2736         drm_vblank_off(dev, pipe);
2737         intel_crtc_update_cursor(crtc, false);
2738
2739         intel_disable_plane(dev_priv, plane, pipe);
2740
2741         if (dev_priv->cfb_plane == plane &&
2742             dev_priv->display.disable_fbc)
2743                 dev_priv->display.disable_fbc(dev);
2744
2745         intel_disable_pipe(dev_priv, pipe);
2746
2747         /* Disable PF */
2748         I915_WRITE(PF_CTL(pipe), 0);
2749         I915_WRITE(PF_WIN_SZ(pipe), 0);
2750
2751         ironlake_fdi_disable(crtc);
2752
2753         /* This is a horrible layering violation; we should be doing this in
2754          * the connector/encoder ->prepare instead, but we don't always have
2755          * enough information there about the config to know whether it will
2756          * actually be necessary or just cause undesired flicker.
2757          */
2758         intel_disable_pch_ports(dev_priv, pipe);
2759
2760         intel_disable_transcoder(dev_priv, pipe);
2761
2762         if (HAS_PCH_CPT(dev)) {
2763                 /* disable TRANS_DP_CTL */
2764                 reg = TRANS_DP_CTL(pipe);
2765                 temp = I915_READ(reg);
2766                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2767                 temp |= TRANS_DP_PORT_SEL_NONE;
2768                 I915_WRITE(reg, temp);
2769
2770                 /* disable DPLL_SEL */
2771                 temp = I915_READ(PCH_DPLL_SEL);
2772                 switch (pipe) {
2773                 case 0:
2774                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2775                         break;
2776                 case 1:
2777                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2778                         break;
2779                 case 2:
2780                         /* FIXME: manage transcoder PLLs? */
2781                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2782                         break;
2783                 default:
2784                         BUG(); /* wtf */
2785                 }
2786                 I915_WRITE(PCH_DPLL_SEL, temp);
2787         }
2788
2789         /* disable PCH DPLL */
2790         intel_disable_pch_pll(dev_priv, pipe);
2791
2792         /* Switch from PCDclk to Rawclk */
2793         reg = FDI_RX_CTL(pipe);
2794         temp = I915_READ(reg);
2795         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2796
2797         /* Disable CPU FDI TX PLL */
2798         reg = FDI_TX_CTL(pipe);
2799         temp = I915_READ(reg);
2800         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2801
2802         POSTING_READ(reg);
2803         udelay(100);
2804
2805         reg = FDI_RX_CTL(pipe);
2806         temp = I915_READ(reg);
2807         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2808
2809         /* Wait for the clocks to turn off. */
2810         POSTING_READ(reg);
2811         udelay(100);
2812
2813         intel_crtc->active = false;
2814         intel_update_watermarks(dev);
2815
2816         mutex_lock(&dev->struct_mutex);
2817         intel_update_fbc(dev);
2818         intel_clear_scanline_wait(dev);
2819         mutex_unlock(&dev->struct_mutex);
2820 }
2821
2822 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2823 {
2824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825         int pipe = intel_crtc->pipe;
2826         int plane = intel_crtc->plane;
2827
2828         /* XXX: When our outputs are all unaware of DPMS modes other than off
2829          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2830          */
2831         switch (mode) {
2832         case DRM_MODE_DPMS_ON:
2833         case DRM_MODE_DPMS_STANDBY:
2834         case DRM_MODE_DPMS_SUSPEND:
2835                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2836                 ironlake_crtc_enable(crtc);
2837                 break;
2838
2839         case DRM_MODE_DPMS_OFF:
2840                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2841                 ironlake_crtc_disable(crtc);
2842                 break;
2843         }
2844 }
2845
2846 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2847 {
2848         if (!enable && intel_crtc->overlay) {
2849                 struct drm_device *dev = intel_crtc->base.dev;
2850                 struct drm_i915_private *dev_priv = dev->dev_private;
2851
2852                 mutex_lock(&dev->struct_mutex);
2853                 dev_priv->mm.interruptible = false;
2854                 (void) intel_overlay_switch_off(intel_crtc->overlay);
2855                 dev_priv->mm.interruptible = true;
2856                 mutex_unlock(&dev->struct_mutex);
2857         }
2858
2859         /* Let userspace switch the overlay on again. In most cases userspace
2860          * has to recompute where to put it anyway.
2861          */
2862 }
2863
2864 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2865 {
2866         struct drm_device *dev = crtc->dev;
2867         struct drm_i915_private *dev_priv = dev->dev_private;
2868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2869         int pipe = intel_crtc->pipe;
2870         int plane = intel_crtc->plane;
2871
2872         if (intel_crtc->active)
2873                 return;
2874
2875         intel_crtc->active = true;
2876         intel_update_watermarks(dev);
2877
2878         intel_enable_pll(dev_priv, pipe);
2879         intel_enable_pipe(dev_priv, pipe, false);
2880         intel_enable_plane(dev_priv, plane, pipe);
2881
2882         intel_crtc_load_lut(crtc);
2883         intel_update_fbc(dev);
2884
2885         /* Give the overlay scaler a chance to enable if it's on this pipe */
2886         intel_crtc_dpms_overlay(intel_crtc, true);
2887         intel_crtc_update_cursor(crtc, true);
2888 }
2889
2890 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2891 {
2892         struct drm_device *dev = crtc->dev;
2893         struct drm_i915_private *dev_priv = dev->dev_private;
2894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895         int pipe = intel_crtc->pipe;
2896         int plane = intel_crtc->plane;
2897
2898         if (!intel_crtc->active)
2899                 return;
2900
2901         /* Give the overlay scaler a chance to disable if it's on this pipe */
2902         intel_crtc_wait_for_pending_flips(crtc);
2903         drm_vblank_off(dev, pipe);
2904         intel_crtc_dpms_overlay(intel_crtc, false);
2905         intel_crtc_update_cursor(crtc, false);
2906
2907         if (dev_priv->cfb_plane == plane &&
2908             dev_priv->display.disable_fbc)
2909                 dev_priv->display.disable_fbc(dev);
2910
2911         intel_disable_plane(dev_priv, plane, pipe);
2912         intel_disable_pipe(dev_priv, pipe);
2913         intel_disable_pll(dev_priv, pipe);
2914
2915         intel_crtc->active = false;
2916         intel_update_fbc(dev);
2917         intel_update_watermarks(dev);
2918         intel_clear_scanline_wait(dev);
2919 }
2920
2921 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2922 {
2923         /* XXX: When our outputs are all unaware of DPMS modes other than off
2924          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2925          */
2926         switch (mode) {
2927         case DRM_MODE_DPMS_ON:
2928         case DRM_MODE_DPMS_STANDBY:
2929         case DRM_MODE_DPMS_SUSPEND:
2930                 i9xx_crtc_enable(crtc);
2931                 break;
2932         case DRM_MODE_DPMS_OFF:
2933                 i9xx_crtc_disable(crtc);
2934                 break;
2935         }
2936 }
2937
2938 /**
2939  * Sets the power management mode of the pipe and plane.
2940  */
2941 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2942 {
2943         struct drm_device *dev = crtc->dev;
2944         struct drm_i915_private *dev_priv = dev->dev_private;
2945         struct drm_i915_master_private *master_priv;
2946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2947         int pipe = intel_crtc->pipe;
2948         bool enabled;
2949
2950         if (intel_crtc->dpms_mode == mode)
2951                 return;
2952
2953         intel_crtc->dpms_mode = mode;
2954
2955         dev_priv->display.dpms(crtc, mode);
2956
2957         if (!dev->primary->master)
2958                 return;
2959
2960         master_priv = dev->primary->master->driver_priv;
2961         if (!master_priv->sarea_priv)
2962                 return;
2963
2964         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2965
2966         switch (pipe) {
2967         case 0:
2968                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2969                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2970                 break;
2971         case 1:
2972                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2973                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2974                 break;
2975         default:
2976                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
2977                 break;
2978         }
2979 }
2980
2981 static void intel_crtc_disable(struct drm_crtc *crtc)
2982 {
2983         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2984         struct drm_device *dev = crtc->dev;
2985
2986         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2987
2988         if (crtc->fb) {
2989                 mutex_lock(&dev->struct_mutex);
2990                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2991                 mutex_unlock(&dev->struct_mutex);
2992         }
2993 }
2994
2995 /* Prepare for a mode set.
2996  *
2997  * Note we could be a lot smarter here.  We need to figure out which outputs
2998  * will be enabled, which disabled (in short, how the config will changes)
2999  * and perform the minimum necessary steps to accomplish that, e.g. updating
3000  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3001  * panel fitting is in the proper state, etc.
3002  */
3003 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3004 {
3005         i9xx_crtc_disable(crtc);
3006 }
3007
3008 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3009 {
3010         i9xx_crtc_enable(crtc);
3011 }
3012
3013 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3014 {
3015         ironlake_crtc_disable(crtc);
3016 }
3017
3018 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3019 {
3020         ironlake_crtc_enable(crtc);
3021 }
3022
3023 void intel_encoder_prepare (struct drm_encoder *encoder)
3024 {
3025         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3026         /* lvds has its own version of prepare see intel_lvds_prepare */
3027         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3028 }
3029
3030 void intel_encoder_commit (struct drm_encoder *encoder)
3031 {
3032         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3033         /* lvds has its own version of commit see intel_lvds_commit */
3034         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3035 }
3036
3037 void intel_encoder_destroy(struct drm_encoder *encoder)
3038 {
3039         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3040
3041         drm_encoder_cleanup(encoder);
3042         kfree(intel_encoder);
3043 }
3044
3045 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3046                                   struct drm_display_mode *mode,
3047                                   struct drm_display_mode *adjusted_mode)
3048 {
3049         struct drm_device *dev = crtc->dev;
3050
3051         if (HAS_PCH_SPLIT(dev)) {
3052                 /* FDI link clock is fixed at 2.7G */
3053                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3054                         return false;
3055         }
3056
3057         /* XXX some encoders set the crtcinfo, others don't.
3058          * Obviously we need some form of conflict resolution here...
3059          */
3060         if (adjusted_mode->crtc_htotal == 0)
3061                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3062
3063         return true;
3064 }
3065
3066 static int i945_get_display_clock_speed(struct drm_device *dev)
3067 {
3068         return 400000;
3069 }
3070
3071 static int i915_get_display_clock_speed(struct drm_device *dev)
3072 {
3073         return 333000;
3074 }
3075
3076 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3077 {
3078         return 200000;
3079 }
3080
3081 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3082 {
3083         u16 gcfgc = 0;
3084
3085         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3086
3087         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3088                 return 133000;
3089         else {
3090                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3091                 case GC_DISPLAY_CLOCK_333_MHZ:
3092                         return 333000;
3093                 default:
3094                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3095                         return 190000;
3096                 }
3097         }
3098 }
3099
3100 static int i865_get_display_clock_speed(struct drm_device *dev)
3101 {
3102         return 266000;
3103 }
3104
3105 static int i855_get_display_clock_speed(struct drm_device *dev)
3106 {
3107         u16 hpllcc = 0;
3108         /* Assume that the hardware is in the high speed state.  This
3109          * should be the default.
3110          */
3111         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3112         case GC_CLOCK_133_200:
3113         case GC_CLOCK_100_200:
3114                 return 200000;
3115         case GC_CLOCK_166_250:
3116                 return 250000;
3117         case GC_CLOCK_100_133:
3118                 return 133000;
3119         }
3120
3121         /* Shouldn't happen */
3122         return 0;
3123 }
3124
3125 static int i830_get_display_clock_speed(struct drm_device *dev)
3126 {
3127         return 133000;
3128 }
3129
3130 struct fdi_m_n {
3131         u32        tu;
3132         u32        gmch_m;
3133         u32        gmch_n;
3134         u32        link_m;
3135         u32        link_n;
3136 };
3137
3138 static void
3139 fdi_reduce_ratio(u32 *num, u32 *den)
3140 {
3141         while (*num > 0xffffff || *den > 0xffffff) {
3142                 *num >>= 1;
3143                 *den >>= 1;
3144         }
3145 }
3146
3147 static void
3148 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3149                      int link_clock, struct fdi_m_n *m_n)
3150 {
3151         m_n->tu = 64; /* default size */
3152
3153         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3154         m_n->gmch_m = bits_per_pixel * pixel_clock;
3155         m_n->gmch_n = link_clock * nlanes * 8;
3156         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3157
3158         m_n->link_m = pixel_clock;
3159         m_n->link_n = link_clock;
3160         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3161 }
3162
3163
3164 struct intel_watermark_params {
3165         unsigned long fifo_size;
3166         unsigned long max_wm;
3167         unsigned long default_wm;
3168         unsigned long guard_size;
3169         unsigned long cacheline_size;
3170 };
3171
3172 /* Pineview has different values for various configs */
3173 static const struct intel_watermark_params pineview_display_wm = {
3174         PINEVIEW_DISPLAY_FIFO,
3175         PINEVIEW_MAX_WM,
3176         PINEVIEW_DFT_WM,
3177         PINEVIEW_GUARD_WM,
3178         PINEVIEW_FIFO_LINE_SIZE
3179 };
3180 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3181         PINEVIEW_DISPLAY_FIFO,
3182         PINEVIEW_MAX_WM,
3183         PINEVIEW_DFT_HPLLOFF_WM,
3184         PINEVIEW_GUARD_WM,
3185         PINEVIEW_FIFO_LINE_SIZE
3186 };
3187 static const struct intel_watermark_params pineview_cursor_wm = {
3188         PINEVIEW_CURSOR_FIFO,
3189         PINEVIEW_CURSOR_MAX_WM,
3190         PINEVIEW_CURSOR_DFT_WM,
3191         PINEVIEW_CURSOR_GUARD_WM,
3192         PINEVIEW_FIFO_LINE_SIZE,
3193 };
3194 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3195         PINEVIEW_CURSOR_FIFO,
3196         PINEVIEW_CURSOR_MAX_WM,
3197         PINEVIEW_CURSOR_DFT_WM,
3198         PINEVIEW_CURSOR_GUARD_WM,
3199         PINEVIEW_FIFO_LINE_SIZE
3200 };
3201 static const struct intel_watermark_params g4x_wm_info = {
3202         G4X_FIFO_SIZE,
3203         G4X_MAX_WM,
3204         G4X_MAX_WM,
3205         2,
3206         G4X_FIFO_LINE_SIZE,
3207 };
3208 static const struct intel_watermark_params g4x_cursor_wm_info = {
3209         I965_CURSOR_FIFO,
3210         I965_CURSOR_MAX_WM,
3211         I965_CURSOR_DFT_WM,
3212         2,
3213         G4X_FIFO_LINE_SIZE,
3214 };
3215 static const struct intel_watermark_params i965_cursor_wm_info = {
3216         I965_CURSOR_FIFO,
3217         I965_CURSOR_MAX_WM,
3218         I965_CURSOR_DFT_WM,
3219         2,
3220         I915_FIFO_LINE_SIZE,
3221 };
3222 static const struct intel_watermark_params i945_wm_info = {
3223         I945_FIFO_SIZE,
3224         I915_MAX_WM,
3225         1,
3226         2,
3227         I915_FIFO_LINE_SIZE
3228 };
3229 static const struct intel_watermark_params i915_wm_info = {
3230         I915_FIFO_SIZE,
3231         I915_MAX_WM,
3232         1,
3233         2,
3234         I915_FIFO_LINE_SIZE
3235 };
3236 static const struct intel_watermark_params i855_wm_info = {
3237         I855GM_FIFO_SIZE,
3238         I915_MAX_WM,
3239         1,
3240         2,
3241         I830_FIFO_LINE_SIZE
3242 };
3243 static const struct intel_watermark_params i830_wm_info = {
3244         I830_FIFO_SIZE,
3245         I915_MAX_WM,
3246         1,
3247         2,
3248         I830_FIFO_LINE_SIZE
3249 };
3250
3251 static const struct intel_watermark_params ironlake_display_wm_info = {
3252         ILK_DISPLAY_FIFO,
3253         ILK_DISPLAY_MAXWM,
3254         ILK_DISPLAY_DFTWM,
3255         2,
3256         ILK_FIFO_LINE_SIZE
3257 };
3258 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3259         ILK_CURSOR_FIFO,
3260         ILK_CURSOR_MAXWM,
3261         ILK_CURSOR_DFTWM,
3262         2,
3263         ILK_FIFO_LINE_SIZE
3264 };
3265 static const struct intel_watermark_params ironlake_display_srwm_info = {
3266         ILK_DISPLAY_SR_FIFO,
3267         ILK_DISPLAY_MAX_SRWM,
3268         ILK_DISPLAY_DFT_SRWM,
3269         2,
3270         ILK_FIFO_LINE_SIZE
3271 };
3272 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3273         ILK_CURSOR_SR_FIFO,
3274         ILK_CURSOR_MAX_SRWM,
3275         ILK_CURSOR_DFT_SRWM,
3276         2,
3277         ILK_FIFO_LINE_SIZE
3278 };
3279
3280 static const struct intel_watermark_params sandybridge_display_wm_info = {
3281         SNB_DISPLAY_FIFO,
3282         SNB_DISPLAY_MAXWM,
3283         SNB_DISPLAY_DFTWM,
3284         2,
3285         SNB_FIFO_LINE_SIZE
3286 };
3287 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3288         SNB_CURSOR_FIFO,
3289         SNB_CURSOR_MAXWM,
3290         SNB_CURSOR_DFTWM,
3291         2,
3292         SNB_FIFO_LINE_SIZE
3293 };
3294 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3295         SNB_DISPLAY_SR_FIFO,
3296         SNB_DISPLAY_MAX_SRWM,
3297         SNB_DISPLAY_DFT_SRWM,
3298         2,
3299         SNB_FIFO_LINE_SIZE
3300 };
3301 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3302         SNB_CURSOR_SR_FIFO,
3303         SNB_CURSOR_MAX_SRWM,
3304         SNB_CURSOR_DFT_SRWM,
3305         2,
3306         SNB_FIFO_LINE_SIZE
3307 };
3308
3309
3310 /**
3311  * intel_calculate_wm - calculate watermark level
3312  * @clock_in_khz: pixel clock
3313  * @wm: chip FIFO params
3314  * @pixel_size: display pixel size
3315  * @latency_ns: memory latency for the platform
3316  *
3317  * Calculate the watermark level (the level at which the display plane will
3318  * start fetching from memory again).  Each chip has a different display
3319  * FIFO size and allocation, so the caller needs to figure that out and pass
3320  * in the correct intel_watermark_params structure.
3321  *
3322  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3323  * on the pixel size.  When it reaches the watermark level, it'll start
3324  * fetching FIFO line sized based chunks from memory until the FIFO fills
3325  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3326  * will occur, and a display engine hang could result.
3327  */
3328 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3329                                         const struct intel_watermark_params *wm,
3330                                         int fifo_size,
3331                                         int pixel_size,
3332                                         unsigned long latency_ns)
3333 {
3334         long entries_required, wm_size;
3335
3336         /*
3337          * Note: we need to make sure we don't overflow for various clock &
3338          * latency values.
3339          * clocks go from a few thousand to several hundred thousand.
3340          * latency is usually a few thousand
3341          */
3342         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3343                 1000;
3344         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3345
3346         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3347
3348         wm_size = fifo_size - (entries_required + wm->guard_size);
3349
3350         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3351
3352         /* Don't promote wm_size to unsigned... */
3353         if (wm_size > (long)wm->max_wm)
3354                 wm_size = wm->max_wm;
3355         if (wm_size <= 0)
3356                 wm_size = wm->default_wm;
3357         return wm_size;
3358 }
3359
3360 struct cxsr_latency {
3361         int is_desktop;
3362         int is_ddr3;
3363         unsigned long fsb_freq;
3364         unsigned long mem_freq;
3365         unsigned long display_sr;
3366         unsigned long display_hpll_disable;
3367         unsigned long cursor_sr;
3368         unsigned long cursor_hpll_disable;
3369 };
3370
3371 static const struct cxsr_latency cxsr_latency_table[] = {
3372         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3373         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3374         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3375         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3376         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3377
3378         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3379         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3380         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3381         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3382         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3383
3384         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3385         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3386         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3387         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3388         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3389
3390         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3391         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3392         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3393         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3394         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3395
3396         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3397         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3398         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3399         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3400         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3401
3402         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3403         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3404         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3405         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3406         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3407 };
3408
3409 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3410                                                          int is_ddr3,
3411                                                          int fsb,
3412                                                          int mem)
3413 {
3414         const struct cxsr_latency *latency;
3415         int i;
3416
3417         if (fsb == 0 || mem == 0)
3418                 return NULL;
3419
3420         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3421                 latency = &cxsr_latency_table[i];
3422                 if (is_desktop == latency->is_desktop &&
3423                     is_ddr3 == latency->is_ddr3 &&
3424                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3425                         return latency;
3426         }
3427
3428         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3429
3430         return NULL;
3431 }
3432
3433 static void pineview_disable_cxsr(struct drm_device *dev)
3434 {
3435         struct drm_i915_private *dev_priv = dev->dev_private;
3436
3437         /* deactivate cxsr */
3438         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3439 }
3440
3441 /*
3442  * Latency for FIFO fetches is dependent on several factors:
3443  *   - memory configuration (speed, channels)
3444  *   - chipset
3445  *   - current MCH state
3446  * It can be fairly high in some situations, so here we assume a fairly
3447  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3448  * set this value too high, the FIFO will fetch frequently to stay full)
3449  * and power consumption (set it too low to save power and we might see
3450  * FIFO underruns and display "flicker").
3451  *
3452  * A value of 5us seems to be a good balance; safe for very low end
3453  * platforms but not overly aggressive on lower latency configs.
3454  */
3455 static const int latency_ns = 5000;
3456
3457 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3458 {
3459         struct drm_i915_private *dev_priv = dev->dev_private;
3460         uint32_t dsparb = I915_READ(DSPARB);
3461         int size;
3462
3463         size = dsparb & 0x7f;
3464         if (plane)
3465                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3466
3467         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3468                       plane ? "B" : "A", size);
3469
3470         return size;
3471 }
3472
3473 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3474 {
3475         struct drm_i915_private *dev_priv = dev->dev_private;
3476         uint32_t dsparb = I915_READ(DSPARB);
3477         int size;
3478
3479         size = dsparb & 0x1ff;
3480         if (plane)
3481                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3482         size >>= 1; /* Convert to cachelines */
3483
3484         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3485                       plane ? "B" : "A", size);
3486
3487         return size;
3488 }
3489
3490 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3491 {
3492         struct drm_i915_private *dev_priv = dev->dev_private;
3493         uint32_t dsparb = I915_READ(DSPARB);
3494         int size;
3495
3496         size = dsparb & 0x7f;
3497         size >>= 2; /* Convert to cachelines */
3498
3499         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3500                       plane ? "B" : "A",
3501                       size);
3502
3503         return size;
3504 }
3505
3506 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3507 {
3508         struct drm_i915_private *dev_priv = dev->dev_private;
3509         uint32_t dsparb = I915_READ(DSPARB);
3510         int size;
3511
3512         size = dsparb & 0x7f;
3513         size >>= 1; /* Convert to cachelines */
3514
3515         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3516                       plane ? "B" : "A", size);
3517
3518         return size;
3519 }
3520
3521 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3522 {
3523         struct drm_crtc *crtc, *enabled = NULL;
3524
3525         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3526                 if (crtc->enabled && crtc->fb) {
3527                         if (enabled)
3528                                 return NULL;
3529                         enabled = crtc;
3530                 }
3531         }
3532
3533         return enabled;
3534 }
3535
3536 static void pineview_update_wm(struct drm_device *dev)
3537 {
3538         struct drm_i915_private *dev_priv = dev->dev_private;
3539         struct drm_crtc *crtc;
3540         const struct cxsr_latency *latency;
3541         u32 reg;
3542         unsigned long wm;
3543
3544         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3545                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3546         if (!latency) {
3547                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3548                 pineview_disable_cxsr(dev);
3549                 return;
3550         }
3551
3552         crtc = single_enabled_crtc(dev);
3553         if (crtc) {
3554                 int clock = crtc->mode.clock;
3555                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3556
3557                 /* Display SR */
3558                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3559                                         pineview_display_wm.fifo_size,
3560                                         pixel_size, latency->display_sr);
3561                 reg = I915_READ(DSPFW1);
3562                 reg &= ~DSPFW_SR_MASK;
3563                 reg |= wm << DSPFW_SR_SHIFT;
3564                 I915_WRITE(DSPFW1, reg);
3565                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3566
3567                 /* cursor SR */
3568                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3569                                         pineview_display_wm.fifo_size,
3570                                         pixel_size, latency->cursor_sr);
3571                 reg = I915_READ(DSPFW3);
3572                 reg &= ~DSPFW_CURSOR_SR_MASK;
3573                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3574                 I915_WRITE(DSPFW3, reg);
3575
3576                 /* Display HPLL off SR */
3577                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3578                                         pineview_display_hplloff_wm.fifo_size,
3579                                         pixel_size, latency->display_hpll_disable);
3580                 reg = I915_READ(DSPFW3);
3581                 reg &= ~DSPFW_HPLL_SR_MASK;
3582                 reg |= wm & DSPFW_HPLL_SR_MASK;
3583                 I915_WRITE(DSPFW3, reg);
3584
3585                 /* cursor HPLL off SR */
3586                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3587                                         pineview_display_hplloff_wm.fifo_size,
3588                                         pixel_size, latency->cursor_hpll_disable);
3589                 reg = I915_READ(DSPFW3);
3590                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3591                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3592                 I915_WRITE(DSPFW3, reg);
3593                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3594
3595                 /* activate cxsr */
3596                 I915_WRITE(DSPFW3,
3597                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3598                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3599         } else {
3600                 pineview_disable_cxsr(dev);
3601                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3602         }
3603 }
3604
3605 static bool g4x_compute_wm0(struct drm_device *dev,
3606                             int plane,
3607                             const struct intel_watermark_params *display,
3608                             int display_latency_ns,
3609                             const struct intel_watermark_params *cursor,
3610                             int cursor_latency_ns,
3611                             int *plane_wm,
3612                             int *cursor_wm)
3613 {
3614         struct drm_crtc *crtc;
3615         int htotal, hdisplay, clock, pixel_size;
3616         int line_time_us, line_count;
3617         int entries, tlb_miss;
3618
3619         crtc = intel_get_crtc_for_plane(dev, plane);
3620         if (crtc->fb == NULL || !crtc->enabled) {
3621                 *cursor_wm = cursor->guard_size;
3622                 *plane_wm = display->guard_size;
3623                 return false;
3624         }
3625
3626         htotal = crtc->mode.htotal;
3627         hdisplay = crtc->mode.hdisplay;
3628         clock = crtc->mode.clock;
3629         pixel_size = crtc->fb->bits_per_pixel / 8;
3630
3631         /* Use the small buffer method to calculate plane watermark */
3632         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3633         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3634         if (tlb_miss > 0)
3635                 entries += tlb_miss;
3636         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3637         *plane_wm = entries + display->guard_size;
3638         if (*plane_wm > (int)display->max_wm)
3639                 *plane_wm = display->max_wm;
3640
3641         /* Use the large buffer method to calculate cursor watermark */
3642         line_time_us = ((htotal * 1000) / clock);
3643         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3644         entries = line_count * 64 * pixel_size;
3645         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3646         if (tlb_miss > 0)
3647                 entries += tlb_miss;
3648         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3649         *cursor_wm = entries + cursor->guard_size;
3650         if (*cursor_wm > (int)cursor->max_wm)
3651                 *cursor_wm = (int)cursor->max_wm;
3652
3653         return true;
3654 }
3655
3656 /*
3657  * Check the wm result.
3658  *
3659  * If any calculated watermark values is larger than the maximum value that
3660  * can be programmed into the associated watermark register, that watermark
3661  * must be disabled.
3662  */
3663 static bool g4x_check_srwm(struct drm_device *dev,
3664                            int display_wm, int cursor_wm,
3665                            const struct intel_watermark_params *display,
3666                            const struct intel_watermark_params *cursor)
3667 {
3668         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3669                       display_wm, cursor_wm);
3670
3671         if (display_wm > display->max_wm) {
3672                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3673                               display_wm, display->max_wm);
3674                 return false;
3675         }
3676
3677         if (cursor_wm > cursor->max_wm) {
3678                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3679                               cursor_wm, cursor->max_wm);
3680                 return false;
3681         }
3682
3683         if (!(display_wm || cursor_wm)) {
3684                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3685                 return false;
3686         }
3687
3688         return true;
3689 }
3690
3691 static bool g4x_compute_srwm(struct drm_device *dev,
3692                              int plane,
3693                              int latency_ns,
3694                              const struct intel_watermark_params *display,
3695                              const struct intel_watermark_params *cursor,
3696                              int *display_wm, int *cursor_wm)
3697 {
3698         struct drm_crtc *crtc;
3699         int hdisplay, htotal, pixel_size, clock;
3700         unsigned long line_time_us;
3701         int line_count, line_size;
3702         int small, large;
3703         int entries;
3704
3705         if (!latency_ns) {
3706                 *display_wm = *cursor_wm = 0;
3707                 return false;
3708         }
3709
3710         crtc = intel_get_crtc_for_plane(dev, plane);
3711         hdisplay = crtc->mode.hdisplay;
3712         htotal = crtc->mode.htotal;
3713         clock = crtc->mode.clock;
3714         pixel_size = crtc->fb->bits_per_pixel / 8;
3715
3716         line_time_us = (htotal * 1000) / clock;
3717         line_count = (latency_ns / line_time_us + 1000) / 1000;
3718         line_size = hdisplay * pixel_size;
3719
3720         /* Use the minimum of the small and large buffer method for primary */
3721         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3722         large = line_count * line_size;
3723
3724         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3725         *display_wm = entries + display->guard_size;
3726
3727         /* calculate the self-refresh watermark for display cursor */
3728         entries = line_count * pixel_size * 64;
3729         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3730         *cursor_wm = entries + cursor->guard_size;
3731
3732         return g4x_check_srwm(dev,
3733                               *display_wm, *cursor_wm,
3734                               display, cursor);
3735 }
3736
3737 #define single_plane_enabled(mask) is_power_of_2(mask)
3738
3739 static void g4x_update_wm(struct drm_device *dev)
3740 {
3741         static const int sr_latency_ns = 12000;
3742         struct drm_i915_private *dev_priv = dev->dev_private;
3743         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3744         int plane_sr, cursor_sr;
3745         unsigned int enabled = 0;
3746
3747         if (g4x_compute_wm0(dev, 0,
3748                             &g4x_wm_info, latency_ns,
3749                             &g4x_cursor_wm_info, latency_ns,
3750                             &planea_wm, &cursora_wm))
3751                 enabled |= 1;
3752
3753         if (g4x_compute_wm0(dev, 1,
3754                             &g4x_wm_info, latency_ns,
3755                             &g4x_cursor_wm_info, latency_ns,
3756                             &planeb_wm, &cursorb_wm))
3757                 enabled |= 2;
3758
3759         plane_sr = cursor_sr = 0;
3760         if (single_plane_enabled(enabled) &&
3761             g4x_compute_srwm(dev, ffs(enabled) - 1,
3762                              sr_latency_ns,
3763                              &g4x_wm_info,
3764                              &g4x_cursor_wm_info,
3765                              &plane_sr, &cursor_sr))
3766                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3767         else
3768                 I915_WRITE(FW_BLC_SELF,
3769                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3770
3771         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3772                       planea_wm, cursora_wm,
3773                       planeb_wm, cursorb_wm,
3774                       plane_sr, cursor_sr);
3775
3776         I915_WRITE(DSPFW1,
3777                    (plane_sr << DSPFW_SR_SHIFT) |
3778                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3779                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
3780                    planea_wm);
3781         I915_WRITE(DSPFW2,
3782                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3783                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3784         /* HPLL off in SR has some issues on G4x... disable it */
3785         I915_WRITE(DSPFW3,
3786                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3787                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3788 }
3789
3790 static void i965_update_wm(struct drm_device *dev)
3791 {
3792         struct drm_i915_private *dev_priv = dev->dev_private;
3793         struct drm_crtc *crtc;
3794         int srwm = 1;
3795         int cursor_sr = 16;
3796
3797         /* Calc sr entries for one plane configs */
3798         crtc = single_enabled_crtc(dev);
3799         if (crtc) {
3800                 /* self-refresh has much higher latency */
3801                 static const int sr_latency_ns = 12000;
3802                 int clock = crtc->mode.clock;
3803                 int htotal = crtc->mode.htotal;
3804                 int hdisplay = crtc->mode.hdisplay;
3805                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3806                 unsigned long line_time_us;
3807                 int entries;
3808
3809                 line_time_us = ((htotal * 1000) / clock);
3810
3811                 /* Use ns/us then divide to preserve precision */
3812                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3813                         pixel_size * hdisplay;
3814                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3815                 srwm = I965_FIFO_SIZE - entries;
3816                 if (srwm < 0)
3817                         srwm = 1;
3818                 srwm &= 0x1ff;
3819                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3820                               entries, srwm);
3821
3822                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3823                         pixel_size * 64;
3824                 entries = DIV_ROUND_UP(entries,
3825                                           i965_cursor_wm_info.cacheline_size);
3826                 cursor_sr = i965_cursor_wm_info.fifo_size -
3827                         (entries + i965_cursor_wm_info.guard_size);
3828
3829                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3830                         cursor_sr = i965_cursor_wm_info.max_wm;
3831
3832                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3833                               "cursor %d\n", srwm, cursor_sr);
3834
3835                 if (IS_CRESTLINE(dev))
3836                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3837         } else {
3838                 /* Turn off self refresh if both pipes are enabled */
3839                 if (IS_CRESTLINE(dev))
3840                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3841                                    & ~FW_BLC_SELF_EN);
3842         }
3843
3844         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3845                       srwm);
3846
3847         /* 965 has limitations... */
3848         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3849                    (8 << 16) | (8 << 8) | (8 << 0));
3850         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3851         /* update cursor SR watermark */
3852         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3853 }
3854
3855 static void i9xx_update_wm(struct drm_device *dev)
3856 {
3857         struct drm_i915_private *dev_priv = dev->dev_private;
3858         const struct intel_watermark_params *wm_info;
3859         uint32_t fwater_lo;
3860         uint32_t fwater_hi;
3861         int cwm, srwm = 1;
3862         int fifo_size;
3863         int planea_wm, planeb_wm;
3864         struct drm_crtc *crtc, *enabled = NULL;
3865
3866         if (IS_I945GM(dev))
3867                 wm_info = &i945_wm_info;
3868         else if (!IS_GEN2(dev))
3869                 wm_info = &i915_wm_info;
3870         else
3871                 wm_info = &i855_wm_info;
3872
3873         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3874         crtc = intel_get_crtc_for_plane(dev, 0);
3875         if (crtc->enabled && crtc->fb) {
3876                 planea_wm = intel_calculate_wm(crtc->mode.clock,
3877                                                wm_info, fifo_size,
3878                                                crtc->fb->bits_per_pixel / 8,
3879                                                latency_ns);
3880                 enabled = crtc;
3881         } else
3882                 planea_wm = fifo_size - wm_info->guard_size;
3883
3884         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3885         crtc = intel_get_crtc_for_plane(dev, 1);
3886         if (crtc->enabled && crtc->fb) {
3887                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3888                                                wm_info, fifo_size,
3889                                                crtc->fb->bits_per_pixel / 8,
3890                                                latency_ns);
3891                 if (enabled == NULL)
3892                         enabled = crtc;
3893                 else
3894                         enabled = NULL;
3895         } else
3896                 planeb_wm = fifo_size - wm_info->guard_size;
3897
3898         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3899
3900         /*
3901          * Overlay gets an aggressive default since video jitter is bad.
3902          */
3903         cwm = 2;
3904
3905         /* Play safe and disable self-refresh before adjusting watermarks. */
3906         if (IS_I945G(dev) || IS_I945GM(dev))
3907                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3908         else if (IS_I915GM(dev))
3909                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3910
3911         /* Calc sr entries for one plane configs */
3912         if (HAS_FW_BLC(dev) && enabled) {
3913                 /* self-refresh has much higher latency */
3914                 static const int sr_latency_ns = 6000;
3915                 int clock = enabled->mode.clock;
3916                 int htotal = enabled->mode.htotal;
3917                 int hdisplay = enabled->mode.hdisplay;
3918                 int pixel_size = enabled->fb->bits_per_pixel / 8;
3919                 unsigned long line_time_us;
3920                 int entries;
3921
3922                 line_time_us = (htotal * 1000) / clock;
3923
3924                 /* Use ns/us then divide to preserve precision */
3925                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3926                         pixel_size * hdisplay;
3927                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3928                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3929                 srwm = wm_info->fifo_size - entries;
3930                 if (srwm < 0)
3931                         srwm = 1;
3932
3933                 if (IS_I945G(dev) || IS_I945GM(dev))
3934                         I915_WRITE(FW_BLC_SELF,
3935                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3936                 else if (IS_I915GM(dev))
3937                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3938         }
3939
3940         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3941                       planea_wm, planeb_wm, cwm, srwm);
3942
3943         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3944         fwater_hi = (cwm & 0x1f);
3945
3946         /* Set request length to 8 cachelines per fetch */
3947         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3948         fwater_hi = fwater_hi | (1 << 8);
3949
3950         I915_WRITE(FW_BLC, fwater_lo);
3951         I915_WRITE(FW_BLC2, fwater_hi);
3952
3953         if (HAS_FW_BLC(dev)) {
3954                 if (enabled) {
3955                         if (IS_I945G(dev) || IS_I945GM(dev))
3956                                 I915_WRITE(FW_BLC_SELF,
3957                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3958                         else if (IS_I915GM(dev))
3959                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3960                         DRM_DEBUG_KMS("memory self refresh enabled\n");
3961                 } else
3962                         DRM_DEBUG_KMS("memory self refresh disabled\n");
3963         }
3964 }
3965
3966 static void i830_update_wm(struct drm_device *dev)
3967 {
3968         struct drm_i915_private *dev_priv = dev->dev_private;
3969         struct drm_crtc *crtc;
3970         uint32_t fwater_lo;
3971         int planea_wm;
3972
3973         crtc = single_enabled_crtc(dev);
3974         if (crtc == NULL)
3975                 return;
3976
3977         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3978                                        dev_priv->display.get_fifo_size(dev, 0),
3979                                        crtc->fb->bits_per_pixel / 8,
3980                                        latency_ns);
3981         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3982         fwater_lo |= (3<<8) | planea_wm;
3983
3984         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3985
3986         I915_WRITE(FW_BLC, fwater_lo);
3987 }
3988
3989 #define ILK_LP0_PLANE_LATENCY           700
3990 #define ILK_LP0_CURSOR_LATENCY          1300
3991
3992 /*
3993  * Check the wm result.
3994  *
3995  * If any calculated watermark values is larger than the maximum value that
3996  * can be programmed into the associated watermark register, that watermark
3997  * must be disabled.
3998  */
3999 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4000                                 int fbc_wm, int display_wm, int cursor_wm,
4001                                 const struct intel_watermark_params *display,
4002                                 const struct intel_watermark_params *cursor)
4003 {
4004         struct drm_i915_private *dev_priv = dev->dev_private;
4005
4006         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4007                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4008
4009         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4010                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4011                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4012
4013                 /* fbc has it's own way to disable FBC WM */
4014                 I915_WRITE(DISP_ARB_CTL,
4015                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4016                 return false;
4017         }
4018
4019         if (display_wm > display->max_wm) {
4020                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4021                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4022                 return false;
4023         }
4024
4025         if (cursor_wm > cursor->max_wm) {
4026                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4027                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4028                 return false;
4029         }
4030
4031         if (!(fbc_wm || display_wm || cursor_wm)) {
4032                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4033                 return false;
4034         }
4035
4036         return true;
4037 }
4038
4039 /*
4040  * Compute watermark values of WM[1-3],
4041  */
4042 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4043                                   int latency_ns,
4044                                   const struct intel_watermark_params *display,
4045                                   const struct intel_watermark_params *cursor,
4046                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4047 {
4048         struct drm_crtc *crtc;
4049         unsigned long line_time_us;
4050         int hdisplay, htotal, pixel_size, clock;
4051         int line_count, line_size;
4052         int small, large;
4053         int entries;
4054
4055         if (!latency_ns) {
4056                 *fbc_wm = *display_wm = *cursor_wm = 0;
4057                 return false;
4058         }
4059
4060         crtc = intel_get_crtc_for_plane(dev, plane);
4061         hdisplay = crtc->mode.hdisplay;
4062         htotal = crtc->mode.htotal;
4063         clock = crtc->mode.clock;
4064         pixel_size = crtc->fb->bits_per_pixel / 8;
4065
4066         line_time_us = (htotal * 1000) / clock;
4067         line_count = (latency_ns / line_time_us + 1000) / 1000;
4068         line_size = hdisplay * pixel_size;
4069
4070         /* Use the minimum of the small and large buffer method for primary */
4071         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4072         large = line_count * line_size;
4073
4074         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4075         *display_wm = entries + display->guard_size;
4076
4077         /*
4078          * Spec says:
4079          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4080          */
4081         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4082
4083         /* calculate the self-refresh watermark for display cursor */
4084         entries = line_count * pixel_size * 64;
4085         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4086         *cursor_wm = entries + cursor->guard_size;
4087
4088         return ironlake_check_srwm(dev, level,
4089                                    *fbc_wm, *display_wm, *cursor_wm,
4090                                    display, cursor);
4091 }
4092
4093 static void ironlake_update_wm(struct drm_device *dev)
4094 {
4095         struct drm_i915_private *dev_priv = dev->dev_private;
4096         int fbc_wm, plane_wm, cursor_wm;
4097         unsigned int enabled;
4098
4099         enabled = 0;
4100         if (g4x_compute_wm0(dev, 0,
4101                             &ironlake_display_wm_info,
4102                             ILK_LP0_PLANE_LATENCY,
4103                             &ironlake_cursor_wm_info,
4104                             ILK_LP0_CURSOR_LATENCY,
4105                             &plane_wm, &cursor_wm)) {
4106                 I915_WRITE(WM0_PIPEA_ILK,
4107                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4108                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4109                               " plane %d, " "cursor: %d\n",
4110                               plane_wm, cursor_wm);
4111                 enabled |= 1;
4112         }
4113
4114         if (g4x_compute_wm0(dev, 1,
4115                             &ironlake_display_wm_info,
4116                             ILK_LP0_PLANE_LATENCY,
4117                             &ironlake_cursor_wm_info,
4118                             ILK_LP0_CURSOR_LATENCY,
4119                             &plane_wm, &cursor_wm)) {
4120                 I915_WRITE(WM0_PIPEB_ILK,
4121                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4122                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4123                               " plane %d, cursor: %d\n",
4124                               plane_wm, cursor_wm);
4125                 enabled |= 2;
4126         }
4127
4128         /*
4129          * Calculate and update the self-refresh watermark only when one
4130          * display plane is used.
4131          */
4132         I915_WRITE(WM3_LP_ILK, 0);
4133         I915_WRITE(WM2_LP_ILK, 0);
4134         I915_WRITE(WM1_LP_ILK, 0);
4135
4136         if (!single_plane_enabled(enabled))
4137                 return;
4138         enabled = ffs(enabled) - 1;
4139
4140         /* WM1 */
4141         if (!ironlake_compute_srwm(dev, 1, enabled,
4142                                    ILK_READ_WM1_LATENCY() * 500,
4143                                    &ironlake_display_srwm_info,
4144                                    &ironlake_cursor_srwm_info,
4145                                    &fbc_wm, &plane_wm, &cursor_wm))
4146                 return;
4147
4148         I915_WRITE(WM1_LP_ILK,
4149                    WM1_LP_SR_EN |
4150                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4151                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4152                    (plane_wm << WM1_LP_SR_SHIFT) |
4153                    cursor_wm);
4154
4155         /* WM2 */
4156         if (!ironlake_compute_srwm(dev, 2, enabled,
4157                                    ILK_READ_WM2_LATENCY() * 500,
4158                                    &ironlake_display_srwm_info,
4159                                    &ironlake_cursor_srwm_info,
4160                                    &fbc_wm, &plane_wm, &cursor_wm))
4161                 return;
4162
4163         I915_WRITE(WM2_LP_ILK,
4164                    WM2_LP_EN |
4165                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4166                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4167                    (plane_wm << WM1_LP_SR_SHIFT) |
4168                    cursor_wm);
4169
4170         /*
4171          * WM3 is unsupported on ILK, probably because we don't have latency
4172          * data for that power state
4173          */
4174 }
4175
4176 static void sandybridge_update_wm(struct drm_device *dev)
4177 {
4178         struct drm_i915_private *dev_priv = dev->dev_private;
4179         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4180         int fbc_wm, plane_wm, cursor_wm;
4181         unsigned int enabled;
4182
4183         enabled = 0;
4184         if (g4x_compute_wm0(dev, 0,
4185                             &sandybridge_display_wm_info, latency,
4186                             &sandybridge_cursor_wm_info, latency,
4187                             &plane_wm, &cursor_wm)) {
4188                 I915_WRITE(WM0_PIPEA_ILK,
4189                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4190                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4191                               " plane %d, " "cursor: %d\n",
4192                               plane_wm, cursor_wm);
4193                 enabled |= 1;
4194         }
4195
4196         if (g4x_compute_wm0(dev, 1,
4197                             &sandybridge_display_wm_info, latency,
4198                             &sandybridge_cursor_wm_info, latency,
4199                             &plane_wm, &cursor_wm)) {
4200                 I915_WRITE(WM0_PIPEB_ILK,
4201                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4202                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4203                               " plane %d, cursor: %d\n",
4204                               plane_wm, cursor_wm);
4205                 enabled |= 2;
4206         }
4207
4208         /*
4209          * Calculate and update the self-refresh watermark only when one
4210          * display plane is used.
4211          *
4212          * SNB support 3 levels of watermark.
4213          *
4214          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4215          * and disabled in the descending order
4216          *
4217          */
4218         I915_WRITE(WM3_LP_ILK, 0);
4219         I915_WRITE(WM2_LP_ILK, 0);
4220         I915_WRITE(WM1_LP_ILK, 0);
4221
4222         if (!single_plane_enabled(enabled))
4223                 return;
4224         enabled = ffs(enabled) - 1;
4225
4226         /* WM1 */
4227         if (!ironlake_compute_srwm(dev, 1, enabled,
4228                                    SNB_READ_WM1_LATENCY() * 500,
4229                                    &sandybridge_display_srwm_info,
4230                                    &sandybridge_cursor_srwm_info,
4231                                    &fbc_wm, &plane_wm, &cursor_wm))
4232                 return;
4233
4234         I915_WRITE(WM1_LP_ILK,
4235                    WM1_LP_SR_EN |
4236                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4237                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4238                    (plane_wm << WM1_LP_SR_SHIFT) |
4239                    cursor_wm);
4240
4241         /* WM2 */
4242         if (!ironlake_compute_srwm(dev, 2, enabled,
4243                                    SNB_READ_WM2_LATENCY() * 500,
4244                                    &sandybridge_display_srwm_info,
4245                                    &sandybridge_cursor_srwm_info,
4246                                    &fbc_wm, &plane_wm, &cursor_wm))
4247                 return;
4248
4249         I915_WRITE(WM2_LP_ILK,
4250                    WM2_LP_EN |
4251                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4252                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4253                    (plane_wm << WM1_LP_SR_SHIFT) |
4254                    cursor_wm);
4255
4256         /* WM3 */
4257         if (!ironlake_compute_srwm(dev, 3, enabled,
4258                                    SNB_READ_WM3_LATENCY() * 500,
4259                                    &sandybridge_display_srwm_info,
4260                                    &sandybridge_cursor_srwm_info,
4261                                    &fbc_wm, &plane_wm, &cursor_wm))
4262                 return;
4263
4264         I915_WRITE(WM3_LP_ILK,
4265                    WM3_LP_EN |
4266                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4267                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4268                    (plane_wm << WM1_LP_SR_SHIFT) |
4269                    cursor_wm);
4270 }
4271
4272 /**
4273  * intel_update_watermarks - update FIFO watermark values based on current modes
4274  *
4275  * Calculate watermark values for the various WM regs based on current mode
4276  * and plane configuration.
4277  *
4278  * There are several cases to deal with here:
4279  *   - normal (i.e. non-self-refresh)
4280  *   - self-refresh (SR) mode
4281  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4282  *   - lines are small relative to FIFO size (buffer can hold more than 2
4283  *     lines), so need to account for TLB latency
4284  *
4285  *   The normal calculation is:
4286  *     watermark = dotclock * bytes per pixel * latency
4287  *   where latency is platform & configuration dependent (we assume pessimal
4288  *   values here).
4289  *
4290  *   The SR calculation is:
4291  *     watermark = (trunc(latency/line time)+1) * surface width *
4292  *       bytes per pixel
4293  *   where
4294  *     line time = htotal / dotclock
4295  *     surface width = hdisplay for normal plane and 64 for cursor
4296  *   and latency is assumed to be high, as above.
4297  *
4298  * The final value programmed to the register should always be rounded up,
4299  * and include an extra 2 entries to account for clock crossings.
4300  *
4301  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4302  * to set the non-SR watermarks to 8.
4303  */
4304 static void intel_update_watermarks(struct drm_device *dev)
4305 {
4306         struct drm_i915_private *dev_priv = dev->dev_private;
4307
4308         if (dev_priv->display.update_wm)
4309                 dev_priv->display.update_wm(dev);
4310 }
4311
4312 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4313 {
4314         return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4315                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4316 }
4317
4318 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4319                               struct drm_display_mode *mode,
4320                               struct drm_display_mode *adjusted_mode,
4321                               int x, int y,
4322                               struct drm_framebuffer *old_fb)
4323 {
4324         struct drm_device *dev = crtc->dev;
4325         struct drm_i915_private *dev_priv = dev->dev_private;
4326         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4327         int pipe = intel_crtc->pipe;
4328         int plane = intel_crtc->plane;
4329         int refclk, num_connectors = 0;
4330         intel_clock_t clock, reduced_clock;
4331         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4332         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4333         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4334         struct drm_mode_config *mode_config = &dev->mode_config;
4335         struct intel_encoder *encoder;
4336         const intel_limit_t *limit;
4337         int ret;
4338         u32 temp;
4339         u32 lvds_sync = 0;
4340
4341         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4342                 if (encoder->base.crtc != crtc)
4343                         continue;
4344
4345                 switch (encoder->type) {
4346                 case INTEL_OUTPUT_LVDS:
4347                         is_lvds = true;
4348                         break;
4349                 case INTEL_OUTPUT_SDVO:
4350                 case INTEL_OUTPUT_HDMI:
4351                         is_sdvo = true;
4352                         if (encoder->needs_tv_clock)
4353                                 is_tv = true;
4354                         break;
4355                 case INTEL_OUTPUT_DVO:
4356                         is_dvo = true;
4357                         break;
4358                 case INTEL_OUTPUT_TVOUT:
4359                         is_tv = true;
4360                         break;
4361                 case INTEL_OUTPUT_ANALOG:
4362                         is_crt = true;
4363                         break;
4364                 case INTEL_OUTPUT_DISPLAYPORT:
4365                         is_dp = true;
4366                         break;
4367                 }
4368
4369                 num_connectors++;
4370         }
4371
4372         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4373                 refclk = dev_priv->lvds_ssc_freq * 1000;
4374                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4375                               refclk / 1000);
4376         } else if (!IS_GEN2(dev)) {
4377                 refclk = 96000;
4378         } else {
4379                 refclk = 48000;
4380         }
4381
4382         /*
4383          * Returns a set of divisors for the desired target clock with the given
4384          * refclk, or FALSE.  The returned values represent the clock equation:
4385          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4386          */
4387         limit = intel_limit(crtc, refclk);
4388         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4389         if (!ok) {
4390                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4391                 return -EINVAL;
4392         }
4393
4394         /* Ensure that the cursor is valid for the new mode before changing... */
4395         intel_crtc_update_cursor(crtc, true);
4396
4397         if (is_lvds && dev_priv->lvds_downclock_avail) {
4398                 has_reduced_clock = limit->find_pll(limit, crtc,
4399                                                     dev_priv->lvds_downclock,
4400                                                     refclk,
4401                                                     &reduced_clock);
4402                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4403                         /*
4404                          * If the different P is found, it means that we can't
4405                          * switch the display clock by using the FP0/FP1.
4406                          * In such case we will disable the LVDS downclock
4407                          * feature.
4408                          */
4409                         DRM_DEBUG_KMS("Different P is found for "
4410                                       "LVDS clock/downclock\n");
4411                         has_reduced_clock = 0;
4412                 }
4413         }
4414         /* SDVO TV has fixed PLL values depend on its clock range,
4415            this mirrors vbios setting. */
4416         if (is_sdvo && is_tv) {
4417                 if (adjusted_mode->clock >= 100000
4418                     && adjusted_mode->clock < 140500) {
4419                         clock.p1 = 2;
4420                         clock.p2 = 10;
4421                         clock.n = 3;
4422                         clock.m1 = 16;
4423                         clock.m2 = 8;
4424                 } else if (adjusted_mode->clock >= 140500
4425                            && adjusted_mode->clock <= 200000) {
4426                         clock.p1 = 1;
4427                         clock.p2 = 10;
4428                         clock.n = 6;
4429                         clock.m1 = 12;
4430                         clock.m2 = 8;
4431                 }
4432         }
4433
4434         if (IS_PINEVIEW(dev)) {
4435                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4436                 if (has_reduced_clock)
4437                         fp2 = (1 << reduced_clock.n) << 16 |
4438                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4439         } else {
4440                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4441                 if (has_reduced_clock)
4442                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4443                                 reduced_clock.m2;
4444         }
4445
4446         dpll = DPLL_VGA_MODE_DIS;
4447
4448         if (!IS_GEN2(dev)) {
4449                 if (is_lvds)
4450                         dpll |= DPLLB_MODE_LVDS;
4451                 else
4452                         dpll |= DPLLB_MODE_DAC_SERIAL;
4453                 if (is_sdvo) {
4454                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4455                         if (pixel_multiplier > 1) {
4456                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4457                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4458                         }
4459                         dpll |= DPLL_DVO_HIGH_SPEED;
4460                 }
4461                 if (is_dp)
4462                         dpll |= DPLL_DVO_HIGH_SPEED;
4463
4464                 /* compute bitmask from p1 value */
4465                 if (IS_PINEVIEW(dev))
4466                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4467                 else {
4468                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4469                         if (IS_G4X(dev) && has_reduced_clock)
4470                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4471                 }
4472                 switch (clock.p2) {
4473                 case 5:
4474                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4475                         break;
4476                 case 7:
4477                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4478                         break;
4479                 case 10:
4480                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4481                         break;
4482                 case 14:
4483                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4484                         break;
4485                 }
4486                 if (INTEL_INFO(dev)->gen >= 4)
4487                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4488         } else {
4489                 if (is_lvds) {
4490                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4491                 } else {
4492                         if (clock.p1 == 2)
4493                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4494                         else
4495                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4496                         if (clock.p2 == 4)
4497                                 dpll |= PLL_P2_DIVIDE_BY_4;
4498                 }
4499         }
4500
4501         if (is_sdvo && is_tv)
4502                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4503         else if (is_tv)
4504                 /* XXX: just matching BIOS for now */
4505                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4506                 dpll |= 3;
4507         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4508                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4509         else
4510                 dpll |= PLL_REF_INPUT_DREFCLK;
4511
4512         /* setup pipeconf */
4513         pipeconf = I915_READ(PIPECONF(pipe));
4514
4515         /* Set up the display plane register */
4516         dspcntr = DISPPLANE_GAMMA_ENABLE;
4517
4518         /* Ironlake's plane is forced to pipe, bit 24 is to
4519            enable color space conversion */
4520         if (pipe == 0)
4521                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4522         else
4523                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4524
4525         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4526                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4527                  * core speed.
4528                  *
4529                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4530                  * pipe == 0 check?
4531                  */
4532                 if (mode->clock >
4533                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4534                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4535                 else
4536                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4537         }
4538
4539         dpll |= DPLL_VCO_ENABLE;
4540
4541         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4542         drm_mode_debug_printmodeline(mode);
4543
4544         I915_WRITE(FP0(pipe), fp);
4545         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4546
4547         POSTING_READ(DPLL(pipe));
4548         udelay(150);
4549
4550         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4551          * This is an exception to the general rule that mode_set doesn't turn
4552          * things on.
4553          */
4554         if (is_lvds) {
4555                 temp = I915_READ(LVDS);
4556                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4557                 if (pipe == 1) {
4558                         temp |= LVDS_PIPEB_SELECT;
4559                 } else {
4560                         temp &= ~LVDS_PIPEB_SELECT;
4561                 }
4562                 /* set the corresponsding LVDS_BORDER bit */
4563                 temp |= dev_priv->lvds_border_bits;
4564                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4565                  * set the DPLLs for dual-channel mode or not.
4566                  */
4567                 if (clock.p2 == 7)
4568                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4569                 else
4570                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4571
4572                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4573                  * appropriately here, but we need to look more thoroughly into how
4574                  * panels behave in the two modes.
4575                  */
4576                 /* set the dithering flag on LVDS as needed */
4577                 if (INTEL_INFO(dev)->gen >= 4) {
4578                         if (dev_priv->lvds_dither)
4579                                 temp |= LVDS_ENABLE_DITHER;
4580                         else
4581                                 temp &= ~LVDS_ENABLE_DITHER;
4582                 }
4583                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4584                         lvds_sync |= LVDS_HSYNC_POLARITY;
4585                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4586                         lvds_sync |= LVDS_VSYNC_POLARITY;
4587                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4588                     != lvds_sync) {
4589                         char flags[2] = "-+";
4590                         DRM_INFO("Changing LVDS panel from "
4591                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4592                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
4593                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
4594                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4595                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4596                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4597                         temp |= lvds_sync;
4598                 }
4599                 I915_WRITE(LVDS, temp);
4600         }
4601
4602         if (is_dp) {
4603                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4604         }
4605
4606         I915_WRITE(DPLL(pipe), dpll);
4607
4608         /* Wait for the clocks to stabilize. */
4609         POSTING_READ(DPLL(pipe));
4610         udelay(150);
4611
4612         if (INTEL_INFO(dev)->gen >= 4) {
4613                 temp = 0;
4614                 if (is_sdvo) {
4615                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4616                         if (temp > 1)
4617                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4618                         else
4619                                 temp = 0;
4620                 }
4621                 I915_WRITE(DPLL_MD(pipe), temp);
4622         } else {
4623                 /* The pixel multiplier can only be updated once the
4624                  * DPLL is enabled and the clocks are stable.
4625                  *
4626                  * So write it again.
4627                  */
4628                 I915_WRITE(DPLL(pipe), dpll);
4629         }
4630
4631         intel_crtc->lowfreq_avail = false;
4632         if (is_lvds && has_reduced_clock && i915_powersave) {
4633                 I915_WRITE(FP1(pipe), fp2);
4634                 intel_crtc->lowfreq_avail = true;
4635                 if (HAS_PIPE_CXSR(dev)) {
4636                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4637                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4638                 }
4639         } else {
4640                 I915_WRITE(FP1(pipe), fp);
4641                 if (HAS_PIPE_CXSR(dev)) {
4642                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4643                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4644                 }
4645         }
4646
4647         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4648                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4649                 /* the chip adds 2 halflines automatically */
4650                 adjusted_mode->crtc_vdisplay -= 1;
4651                 adjusted_mode->crtc_vtotal -= 1;
4652                 adjusted_mode->crtc_vblank_start -= 1;
4653                 adjusted_mode->crtc_vblank_end -= 1;
4654                 adjusted_mode->crtc_vsync_end -= 1;
4655                 adjusted_mode->crtc_vsync_start -= 1;
4656         } else
4657                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4658
4659         I915_WRITE(HTOTAL(pipe),
4660                    (adjusted_mode->crtc_hdisplay - 1) |
4661                    ((adjusted_mode->crtc_htotal - 1) << 16));
4662         I915_WRITE(HBLANK(pipe),
4663                    (adjusted_mode->crtc_hblank_start - 1) |
4664                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4665         I915_WRITE(HSYNC(pipe),
4666                    (adjusted_mode->crtc_hsync_start - 1) |
4667                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4668
4669         I915_WRITE(VTOTAL(pipe),
4670                    (adjusted_mode->crtc_vdisplay - 1) |
4671                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4672         I915_WRITE(VBLANK(pipe),
4673                    (adjusted_mode->crtc_vblank_start - 1) |
4674                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4675         I915_WRITE(VSYNC(pipe),
4676                    (adjusted_mode->crtc_vsync_start - 1) |
4677                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4678
4679         /* pipesrc and dspsize control the size that is scaled from,
4680          * which should always be the user's requested size.
4681          */
4682         I915_WRITE(DSPSIZE(plane),
4683                    ((mode->vdisplay - 1) << 16) |
4684                    (mode->hdisplay - 1));
4685         I915_WRITE(DSPPOS(plane), 0);
4686         I915_WRITE(PIPESRC(pipe),
4687                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4688
4689         I915_WRITE(PIPECONF(pipe), pipeconf);
4690         POSTING_READ(PIPECONF(pipe));
4691         intel_enable_pipe(dev_priv, pipe, false);
4692
4693         intel_wait_for_vblank(dev, pipe);
4694
4695         I915_WRITE(DSPCNTR(plane), dspcntr);
4696         POSTING_READ(DSPCNTR(plane));
4697         intel_enable_plane(dev_priv, plane, pipe);
4698
4699         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4700
4701         intel_update_watermarks(dev);
4702
4703         return ret;
4704 }
4705
4706 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4707                                   struct drm_display_mode *mode,
4708                                   struct drm_display_mode *adjusted_mode,
4709                                   int x, int y,
4710                                   struct drm_framebuffer *old_fb)
4711 {
4712         struct drm_device *dev = crtc->dev;
4713         struct drm_i915_private *dev_priv = dev->dev_private;
4714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4715         int pipe = intel_crtc->pipe;
4716         int plane = intel_crtc->plane;
4717         int refclk, num_connectors = 0;
4718         intel_clock_t clock, reduced_clock;
4719         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4720         bool ok, has_reduced_clock = false, is_sdvo = false;
4721         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4722         struct intel_encoder *has_edp_encoder = NULL;
4723         struct drm_mode_config *mode_config = &dev->mode_config;
4724         struct intel_encoder *encoder;
4725         const intel_limit_t *limit;
4726         int ret;
4727         struct fdi_m_n m_n = {0};
4728         u32 temp;
4729         u32 lvds_sync = 0;
4730         int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
4731
4732         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4733                 if (encoder->base.crtc != crtc)
4734                         continue;
4735
4736                 switch (encoder->type) {
4737                 case INTEL_OUTPUT_LVDS:
4738                         is_lvds = true;
4739                         break;
4740                 case INTEL_OUTPUT_SDVO:
4741                 case INTEL_OUTPUT_HDMI:
4742                         is_sdvo = true;
4743                         if (encoder->needs_tv_clock)
4744                                 is_tv = true;
4745                         break;
4746                 case INTEL_OUTPUT_TVOUT:
4747                         is_tv = true;
4748                         break;
4749                 case INTEL_OUTPUT_ANALOG:
4750                         is_crt = true;
4751                         break;
4752                 case INTEL_OUTPUT_DISPLAYPORT:
4753                         is_dp = true;
4754                         break;
4755                 case INTEL_OUTPUT_EDP:
4756                         has_edp_encoder = encoder;
4757                         break;
4758                 }
4759
4760                 num_connectors++;
4761         }
4762
4763         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4764                 refclk = dev_priv->lvds_ssc_freq * 1000;
4765                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4766                               refclk / 1000);
4767         } else {
4768                 refclk = 96000;
4769                 if (!has_edp_encoder ||
4770                     intel_encoder_is_pch_edp(&has_edp_encoder->base))
4771                         refclk = 120000; /* 120Mhz refclk */
4772         }
4773
4774         /*
4775          * Returns a set of divisors for the desired target clock with the given
4776          * refclk, or FALSE.  The returned values represent the clock equation:
4777          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4778          */
4779         limit = intel_limit(crtc, refclk);
4780         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4781         if (!ok) {
4782                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4783                 return -EINVAL;
4784         }
4785
4786         /* Ensure that the cursor is valid for the new mode before changing... */
4787         intel_crtc_update_cursor(crtc, true);
4788
4789         if (is_lvds && dev_priv->lvds_downclock_avail) {
4790                 has_reduced_clock = limit->find_pll(limit, crtc,
4791                                                     dev_priv->lvds_downclock,
4792                                                     refclk,
4793                                                     &reduced_clock);
4794                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4795                         /*
4796                          * If the different P is found, it means that we can't
4797                          * switch the display clock by using the FP0/FP1.
4798                          * In such case we will disable the LVDS downclock
4799                          * feature.
4800                          */
4801                         DRM_DEBUG_KMS("Different P is found for "
4802                                       "LVDS clock/downclock\n");
4803                         has_reduced_clock = 0;
4804                 }
4805         }
4806         /* SDVO TV has fixed PLL values depend on its clock range,
4807            this mirrors vbios setting. */
4808         if (is_sdvo && is_tv) {
4809                 if (adjusted_mode->clock >= 100000
4810                     && adjusted_mode->clock < 140500) {
4811                         clock.p1 = 2;
4812                         clock.p2 = 10;
4813                         clock.n = 3;
4814                         clock.m1 = 16;
4815                         clock.m2 = 8;
4816                 } else if (adjusted_mode->clock >= 140500
4817                            && adjusted_mode->clock <= 200000) {
4818                         clock.p1 = 1;
4819                         clock.p2 = 10;
4820                         clock.n = 6;
4821                         clock.m1 = 12;
4822                         clock.m2 = 8;
4823                 }
4824         }
4825
4826         /* FDI link */
4827         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4828         lane = 0;
4829         /* CPU eDP doesn't require FDI link, so just set DP M/N
4830            according to current link config */
4831         if (has_edp_encoder &&
4832             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4833                 target_clock = mode->clock;
4834                 intel_edp_link_config(has_edp_encoder,
4835                                       &lane, &link_bw);
4836         } else {
4837                 /* [e]DP over FDI requires target mode clock
4838                    instead of link clock */
4839                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4840                         target_clock = mode->clock;
4841                 else
4842                         target_clock = adjusted_mode->clock;
4843
4844                 /* FDI is a binary signal running at ~2.7GHz, encoding
4845                  * each output octet as 10 bits. The actual frequency
4846                  * is stored as a divider into a 100MHz clock, and the
4847                  * mode pixel clock is stored in units of 1KHz.
4848                  * Hence the bw of each lane in terms of the mode signal
4849                  * is:
4850                  */
4851                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4852         }
4853
4854         /* determine panel color depth */
4855         temp = I915_READ(PIPECONF(pipe));
4856         temp &= ~PIPE_BPC_MASK;
4857         if (is_lvds) {
4858                 /* the BPC will be 6 if it is 18-bit LVDS panel */
4859                 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4860                         temp |= PIPE_8BPC;
4861                 else
4862                         temp |= PIPE_6BPC;
4863         } else if (has_edp_encoder) {
4864                 switch (dev_priv->edp.bpp/3) {
4865                 case 8:
4866                         temp |= PIPE_8BPC;
4867                         break;
4868                 case 10:
4869                         temp |= PIPE_10BPC;
4870                         break;
4871                 case 6:
4872                         temp |= PIPE_6BPC;
4873                         break;
4874                 case 12:
4875                         temp |= PIPE_12BPC;
4876                         break;
4877                 }
4878         } else
4879                 temp |= PIPE_8BPC;
4880         I915_WRITE(PIPECONF(pipe), temp);
4881
4882         switch (temp & PIPE_BPC_MASK) {
4883         case PIPE_8BPC:
4884                 bpp = 24;
4885                 break;
4886         case PIPE_10BPC:
4887                 bpp = 30;
4888                 break;
4889         case PIPE_6BPC:
4890                 bpp = 18;
4891                 break;
4892         case PIPE_12BPC:
4893                 bpp = 36;
4894                 break;
4895         default:
4896                 DRM_ERROR("unknown pipe bpc value\n");
4897                 bpp = 24;
4898         }
4899
4900         if (!lane) {
4901                 /*
4902                  * Account for spread spectrum to avoid
4903                  * oversubscribing the link. Max center spread
4904                  * is 2.5%; use 5% for safety's sake.
4905                  */
4906                 u32 bps = target_clock * bpp * 21 / 20;
4907                 lane = bps / (link_bw * 8) + 1;
4908         }
4909
4910         intel_crtc->fdi_lanes = lane;
4911
4912         if (pixel_multiplier > 1)
4913                 link_bw *= pixel_multiplier;
4914         ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4915
4916         /* Ironlake: try to setup display ref clock before DPLL
4917          * enabling. This is only under driver's control after
4918          * PCH B stepping, previous chipset stepping should be
4919          * ignoring this setting.
4920          */
4921         temp = I915_READ(PCH_DREF_CONTROL);
4922         /* Always enable nonspread source */
4923         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4924         temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4925         temp &= ~DREF_SSC_SOURCE_MASK;
4926         temp |= DREF_SSC_SOURCE_ENABLE;
4927         I915_WRITE(PCH_DREF_CONTROL, temp);
4928
4929         POSTING_READ(PCH_DREF_CONTROL);
4930         udelay(200);
4931
4932         if (has_edp_encoder) {
4933                 if (intel_panel_use_ssc(dev_priv)) {
4934                         temp |= DREF_SSC1_ENABLE;
4935                         I915_WRITE(PCH_DREF_CONTROL, temp);
4936
4937                         POSTING_READ(PCH_DREF_CONTROL);
4938                         udelay(200);
4939                 }
4940                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4941
4942                 /* Enable CPU source on CPU attached eDP */
4943                 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4944                         if (intel_panel_use_ssc(dev_priv))
4945                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4946                         else
4947                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4948                 } else {
4949                         /* Enable SSC on PCH eDP if needed */
4950                         if (intel_panel_use_ssc(dev_priv)) {
4951                                 DRM_ERROR("enabling SSC on PCH\n");
4952                                 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4953                         }
4954                 }
4955                 I915_WRITE(PCH_DREF_CONTROL, temp);
4956                 POSTING_READ(PCH_DREF_CONTROL);
4957                 udelay(200);
4958         }
4959
4960         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4961         if (has_reduced_clock)
4962                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4963                         reduced_clock.m2;
4964
4965         /* Enable autotuning of the PLL clock (if permissible) */
4966         factor = 21;
4967         if (is_lvds) {
4968                 if ((intel_panel_use_ssc(dev_priv) &&
4969                      dev_priv->lvds_ssc_freq == 100) ||
4970                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4971                         factor = 25;
4972         } else if (is_sdvo && is_tv)
4973                 factor = 20;
4974
4975         if (clock.m < factor * clock.n)
4976                 fp |= FP_CB_TUNE;
4977
4978         dpll = 0;
4979
4980         if (is_lvds)
4981                 dpll |= DPLLB_MODE_LVDS;
4982         else
4983                 dpll |= DPLLB_MODE_DAC_SERIAL;
4984         if (is_sdvo) {
4985                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4986                 if (pixel_multiplier > 1) {
4987                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4988                 }
4989                 dpll |= DPLL_DVO_HIGH_SPEED;
4990         }
4991         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4992                 dpll |= DPLL_DVO_HIGH_SPEED;
4993
4994         /* compute bitmask from p1 value */
4995         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4996         /* also FPA1 */
4997         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4998
4999         switch (clock.p2) {
5000         case 5:
5001                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5002                 break;
5003         case 7:
5004                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5005                 break;
5006         case 10:
5007                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5008                 break;
5009         case 14:
5010                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5011                 break;
5012         }
5013
5014         if (is_sdvo && is_tv)
5015                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5016         else if (is_tv)
5017                 /* XXX: just matching BIOS for now */
5018                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5019                 dpll |= 3;
5020         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5021                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5022         else
5023                 dpll |= PLL_REF_INPUT_DREFCLK;
5024
5025         /* setup pipeconf */
5026         pipeconf = I915_READ(PIPECONF(pipe));
5027
5028         /* Set up the display plane register */
5029         dspcntr = DISPPLANE_GAMMA_ENABLE;
5030
5031         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5032         drm_mode_debug_printmodeline(mode);
5033
5034         /* PCH eDP needs FDI, but CPU eDP does not */
5035         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5036                 I915_WRITE(PCH_FP0(pipe), fp);
5037                 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5038
5039                 POSTING_READ(PCH_DPLL(pipe));
5040                 udelay(150);
5041         }
5042
5043         /* enable transcoder DPLL */
5044         if (HAS_PCH_CPT(dev)) {
5045                 temp = I915_READ(PCH_DPLL_SEL);
5046                 switch (pipe) {
5047                 case 0:
5048                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5049                         break;
5050                 case 1:
5051                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5052                         break;
5053                 case 2:
5054                         /* FIXME: manage transcoder PLLs? */
5055                         temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5056                         break;
5057                 default:
5058                         BUG();
5059                 }
5060                 I915_WRITE(PCH_DPLL_SEL, temp);
5061
5062                 POSTING_READ(PCH_DPLL_SEL);
5063                 udelay(150);
5064         }
5065
5066         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5067          * This is an exception to the general rule that mode_set doesn't turn
5068          * things on.
5069          */
5070         if (is_lvds) {
5071                 temp = I915_READ(PCH_LVDS);
5072                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5073                 if (pipe == 1) {
5074                         if (HAS_PCH_CPT(dev))
5075                                 temp |= PORT_TRANS_B_SEL_CPT;
5076                         else
5077                                 temp |= LVDS_PIPEB_SELECT;
5078                 } else {
5079                         if (HAS_PCH_CPT(dev))
5080                                 temp &= ~PORT_TRANS_SEL_MASK;
5081                         else
5082                                 temp &= ~LVDS_PIPEB_SELECT;
5083                 }
5084                 /* set the corresponsding LVDS_BORDER bit */
5085                 temp |= dev_priv->lvds_border_bits;
5086                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5087                  * set the DPLLs for dual-channel mode or not.
5088                  */
5089                 if (clock.p2 == 7)
5090                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5091                 else
5092                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5093
5094                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5095                  * appropriately here, but we need to look more thoroughly into how
5096                  * panels behave in the two modes.
5097                  */
5098                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5099                         lvds_sync |= LVDS_HSYNC_POLARITY;
5100                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5101                         lvds_sync |= LVDS_VSYNC_POLARITY;
5102                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5103                     != lvds_sync) {
5104                         char flags[2] = "-+";
5105                         DRM_INFO("Changing LVDS panel from "
5106                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5107                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5108                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5109                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5110                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5111                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5112                         temp |= lvds_sync;
5113                 }
5114                 I915_WRITE(PCH_LVDS, temp);
5115         }
5116
5117         /* set the dithering flag and clear for anything other than a panel. */
5118         pipeconf &= ~PIPECONF_DITHER_EN;
5119         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5120         if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5121                 pipeconf |= PIPECONF_DITHER_EN;
5122                 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5123         }
5124
5125         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5126                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5127         } else {
5128                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5129                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5130                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5131                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5132                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5133         }
5134
5135         if (!has_edp_encoder ||
5136             intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5137                 I915_WRITE(PCH_DPLL(pipe), dpll);
5138
5139                 /* Wait for the clocks to stabilize. */
5140                 POSTING_READ(PCH_DPLL(pipe));
5141                 udelay(150);
5142
5143                 /* The pixel multiplier can only be updated once the
5144                  * DPLL is enabled and the clocks are stable.
5145                  *
5146                  * So write it again.
5147                  */
5148                 I915_WRITE(PCH_DPLL(pipe), dpll);
5149         }
5150
5151         intel_crtc->lowfreq_avail = false;
5152         if (is_lvds && has_reduced_clock && i915_powersave) {
5153                 I915_WRITE(PCH_FP1(pipe), fp2);
5154                 intel_crtc->lowfreq_avail = true;
5155                 if (HAS_PIPE_CXSR(dev)) {
5156                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5157                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5158                 }
5159         } else {
5160                 I915_WRITE(PCH_FP1(pipe), fp);
5161                 if (HAS_PIPE_CXSR(dev)) {
5162                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5163                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5164                 }
5165         }
5166
5167         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5168                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5169                 /* the chip adds 2 halflines automatically */
5170                 adjusted_mode->crtc_vdisplay -= 1;
5171                 adjusted_mode->crtc_vtotal -= 1;
5172                 adjusted_mode->crtc_vblank_start -= 1;
5173                 adjusted_mode->crtc_vblank_end -= 1;
5174                 adjusted_mode->crtc_vsync_end -= 1;
5175                 adjusted_mode->crtc_vsync_start -= 1;
5176         } else
5177                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5178
5179         I915_WRITE(HTOTAL(pipe),
5180                    (adjusted_mode->crtc_hdisplay - 1) |
5181                    ((adjusted_mode->crtc_htotal - 1) << 16));
5182         I915_WRITE(HBLANK(pipe),
5183                    (adjusted_mode->crtc_hblank_start - 1) |
5184                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5185         I915_WRITE(HSYNC(pipe),
5186                    (adjusted_mode->crtc_hsync_start - 1) |
5187                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5188
5189         I915_WRITE(VTOTAL(pipe),
5190                    (adjusted_mode->crtc_vdisplay - 1) |
5191                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5192         I915_WRITE(VBLANK(pipe),
5193                    (adjusted_mode->crtc_vblank_start - 1) |
5194                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5195         I915_WRITE(VSYNC(pipe),
5196                    (adjusted_mode->crtc_vsync_start - 1) |
5197                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5198
5199         /* pipesrc controls the size that is scaled from, which should
5200          * always be the user's requested size.
5201          */
5202         I915_WRITE(PIPESRC(pipe),
5203                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5204
5205         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5206         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5207         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5208         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5209
5210         if (has_edp_encoder &&
5211             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5212                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5213         }
5214
5215         I915_WRITE(PIPECONF(pipe), pipeconf);
5216         POSTING_READ(PIPECONF(pipe));
5217
5218         intel_wait_for_vblank(dev, pipe);
5219
5220         if (IS_GEN5(dev)) {
5221                 /* enable address swizzle for tiling buffer */
5222                 temp = I915_READ(DISP_ARB_CTL);
5223                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5224         }
5225
5226         I915_WRITE(DSPCNTR(plane), dspcntr);
5227         POSTING_READ(DSPCNTR(plane));
5228
5229         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5230
5231         intel_update_watermarks(dev);
5232
5233         return ret;
5234 }
5235
5236 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5237                                struct drm_display_mode *mode,
5238                                struct drm_display_mode *adjusted_mode,
5239                                int x, int y,
5240                                struct drm_framebuffer *old_fb)
5241 {
5242         struct drm_device *dev = crtc->dev;
5243         struct drm_i915_private *dev_priv = dev->dev_private;
5244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5245         int pipe = intel_crtc->pipe;
5246         int ret;
5247
5248         drm_vblank_pre_modeset(dev, pipe);
5249
5250         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5251                                               x, y, old_fb);
5252
5253         drm_vblank_post_modeset(dev, pipe);
5254
5255         return ret;
5256 }
5257
5258 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5259 void intel_crtc_load_lut(struct drm_crtc *crtc)
5260 {
5261         struct drm_device *dev = crtc->dev;
5262         struct drm_i915_private *dev_priv = dev->dev_private;
5263         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5264         int palreg = PALETTE(intel_crtc->pipe);
5265         int i;
5266
5267         /* The clocks have to be on to load the palette. */
5268         if (!crtc->enabled || !intel_crtc->active)
5269                 return;
5270
5271         /* use legacy palette for Ironlake */
5272         if (HAS_PCH_SPLIT(dev))
5273                 palreg = LGC_PALETTE(intel_crtc->pipe);
5274
5275         for (i = 0; i < 256; i++) {
5276                 I915_WRITE(palreg + 4 * i,
5277                            (intel_crtc->lut_r[i] << 16) |
5278                            (intel_crtc->lut_g[i] << 8) |
5279                            intel_crtc->lut_b[i]);
5280         }
5281 }
5282
5283 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5284 {
5285         struct drm_device *dev = crtc->dev;
5286         struct drm_i915_private *dev_priv = dev->dev_private;
5287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5288         bool visible = base != 0;
5289         u32 cntl;
5290
5291         if (intel_crtc->cursor_visible == visible)
5292                 return;
5293
5294         cntl = I915_READ(_CURACNTR);
5295         if (visible) {
5296                 /* On these chipsets we can only modify the base whilst
5297                  * the cursor is disabled.
5298                  */
5299                 I915_WRITE(_CURABASE, base);
5300
5301                 cntl &= ~(CURSOR_FORMAT_MASK);
5302                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5303                 cntl |= CURSOR_ENABLE |
5304                         CURSOR_GAMMA_ENABLE |
5305                         CURSOR_FORMAT_ARGB;
5306         } else
5307                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5308         I915_WRITE(_CURACNTR, cntl);
5309
5310         intel_crtc->cursor_visible = visible;
5311 }
5312
5313 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5314 {
5315         struct drm_device *dev = crtc->dev;
5316         struct drm_i915_private *dev_priv = dev->dev_private;
5317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5318         int pipe = intel_crtc->pipe;
5319         bool visible = base != 0;
5320
5321         if (intel_crtc->cursor_visible != visible) {
5322                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5323                 if (base) {
5324                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5325                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5326                         cntl |= pipe << 28; /* Connect to correct pipe */
5327                 } else {
5328                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5329                         cntl |= CURSOR_MODE_DISABLE;
5330                 }
5331                 I915_WRITE(CURCNTR(pipe), cntl);
5332
5333                 intel_crtc->cursor_visible = visible;
5334         }
5335         /* and commit changes on next vblank */
5336         I915_WRITE(CURBASE(pipe), base);
5337 }
5338
5339 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5340 {
5341         struct drm_device *dev = crtc->dev;
5342         struct drm_i915_private *dev_priv = dev->dev_private;
5343         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5344         int pipe = intel_crtc->pipe;
5345         bool visible = base != 0;
5346
5347         if (intel_crtc->cursor_visible != visible) {
5348                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5349                 if (base) {
5350                         cntl &= ~CURSOR_MODE;
5351                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5352                 } else {
5353                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5354                         cntl |= CURSOR_MODE_DISABLE;
5355                 }
5356                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5357
5358                 intel_crtc->cursor_visible = visible;
5359         }
5360         /* and commit changes on next vblank */
5361         I915_WRITE(CURBASE_IVB(pipe), base);
5362 }
5363
5364 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5365 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5366                                      bool on)
5367 {
5368         struct drm_device *dev = crtc->dev;
5369         struct drm_i915_private *dev_priv = dev->dev_private;
5370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5371         int pipe = intel_crtc->pipe;
5372         int x = intel_crtc->cursor_x;
5373         int y = intel_crtc->cursor_y;
5374         u32 base, pos;
5375         bool visible;
5376
5377         pos = 0;
5378
5379         if (on && crtc->enabled && crtc->fb) {
5380                 base = intel_crtc->cursor_addr;
5381                 if (x > (int) crtc->fb->width)
5382                         base = 0;
5383
5384                 if (y > (int) crtc->fb->height)
5385                         base = 0;
5386         } else
5387                 base = 0;
5388
5389         if (x < 0) {
5390                 if (x + intel_crtc->cursor_width < 0)
5391                         base = 0;
5392
5393                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5394                 x = -x;
5395         }
5396         pos |= x << CURSOR_X_SHIFT;
5397
5398         if (y < 0) {
5399                 if (y + intel_crtc->cursor_height < 0)
5400                         base = 0;
5401
5402                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5403                 y = -y;
5404         }
5405         pos |= y << CURSOR_Y_SHIFT;
5406
5407         visible = base != 0;
5408         if (!visible && !intel_crtc->cursor_visible)
5409                 return;
5410
5411         if (IS_IVYBRIDGE(dev)) {
5412                 I915_WRITE(CURPOS_IVB(pipe), pos);
5413                 ivb_update_cursor(crtc, base);
5414         } else {
5415                 I915_WRITE(CURPOS(pipe), pos);
5416                 if (IS_845G(dev) || IS_I865G(dev))
5417                         i845_update_cursor(crtc, base);
5418                 else
5419                         i9xx_update_cursor(crtc, base);
5420         }
5421
5422         if (visible)
5423                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5424 }
5425
5426 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5427                                  struct drm_file *file,
5428                                  uint32_t handle,
5429                                  uint32_t width, uint32_t height)
5430 {
5431         struct drm_device *dev = crtc->dev;
5432         struct drm_i915_private *dev_priv = dev->dev_private;
5433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5434         struct drm_i915_gem_object *obj;
5435         uint32_t addr;
5436         int ret;
5437
5438         DRM_DEBUG_KMS("\n");
5439
5440         /* if we want to turn off the cursor ignore width and height */
5441         if (!handle) {
5442                 DRM_DEBUG_KMS("cursor off\n");
5443                 addr = 0;
5444                 obj = NULL;
5445                 mutex_lock(&dev->struct_mutex);
5446                 goto finish;
5447         }
5448
5449         /* Currently we only support 64x64 cursors */
5450         if (width != 64 || height != 64) {
5451                 DRM_ERROR("we currently only support 64x64 cursors\n");
5452                 return -EINVAL;
5453         }
5454
5455         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5456         if (&obj->base == NULL)
5457                 return -ENOENT;
5458
5459         if (obj->base.size < width * height * 4) {
5460                 DRM_ERROR("buffer is to small\n");
5461                 ret = -ENOMEM;
5462                 goto fail;
5463         }
5464
5465         /* we only need to pin inside GTT if cursor is non-phy */
5466         mutex_lock(&dev->struct_mutex);
5467         if (!dev_priv->info->cursor_needs_physical) {
5468                 if (obj->tiling_mode) {
5469                         DRM_ERROR("cursor cannot be tiled\n");
5470                         ret = -EINVAL;
5471                         goto fail_locked;
5472                 }
5473
5474                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
5475                 if (ret) {
5476                         DRM_ERROR("failed to pin cursor bo\n");
5477                         goto fail_locked;
5478                 }
5479
5480                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
5481                 if (ret) {
5482                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5483                         goto fail_unpin;
5484                 }
5485
5486                 ret = i915_gem_object_put_fence(obj);
5487                 if (ret) {
5488                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5489                         goto fail_unpin;
5490                 }
5491
5492                 addr = obj->gtt_offset;
5493         } else {
5494                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5495                 ret = i915_gem_attach_phys_object(dev, obj,
5496                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5497                                                   align);
5498                 if (ret) {
5499                         DRM_ERROR("failed to attach phys object\n");
5500                         goto fail_locked;
5501                 }
5502                 addr = obj->phys_obj->handle->busaddr;
5503         }
5504
5505         if (IS_GEN2(dev))
5506                 I915_WRITE(CURSIZE, (height << 12) | width);
5507
5508  finish:
5509         if (intel_crtc->cursor_bo) {
5510                 if (dev_priv->info->cursor_needs_physical) {
5511                         if (intel_crtc->cursor_bo != obj)
5512                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5513                 } else
5514                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5515                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5516         }
5517
5518         mutex_unlock(&dev->struct_mutex);
5519
5520         intel_crtc->cursor_addr = addr;
5521         intel_crtc->cursor_bo = obj;
5522         intel_crtc->cursor_width = width;
5523         intel_crtc->cursor_height = height;
5524
5525         intel_crtc_update_cursor(crtc, true);
5526
5527         return 0;
5528 fail_unpin:
5529         i915_gem_object_unpin(obj);
5530 fail_locked:
5531         mutex_unlock(&dev->struct_mutex);
5532 fail:
5533         drm_gem_object_unreference_unlocked(&obj->base);
5534         return ret;
5535 }
5536
5537 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5538 {
5539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5540
5541         intel_crtc->cursor_x = x;
5542         intel_crtc->cursor_y = y;
5543
5544         intel_crtc_update_cursor(crtc, true);
5545
5546         return 0;
5547 }
5548
5549 /** Sets the color ramps on behalf of RandR */
5550 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5551                                  u16 blue, int regno)
5552 {
5553         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5554
5555         intel_crtc->lut_r[regno] = red >> 8;
5556         intel_crtc->lut_g[regno] = green >> 8;
5557         intel_crtc->lut_b[regno] = blue >> 8;
5558 }
5559
5560 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5561                              u16 *blue, int regno)
5562 {
5563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5564
5565         *red = intel_crtc->lut_r[regno] << 8;
5566         *green = intel_crtc->lut_g[regno] << 8;
5567         *blue = intel_crtc->lut_b[regno] << 8;
5568 }
5569
5570 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5571                                  u16 *blue, uint32_t start, uint32_t size)
5572 {
5573         int end = (start + size > 256) ? 256 : start + size, i;
5574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5575
5576         for (i = start; i < end; i++) {
5577                 intel_crtc->lut_r[i] = red[i] >> 8;
5578                 intel_crtc->lut_g[i] = green[i] >> 8;
5579                 intel_crtc->lut_b[i] = blue[i] >> 8;
5580         }
5581
5582         intel_crtc_load_lut(crtc);
5583 }
5584
5585 /**
5586  * Get a pipe with a simple mode set on it for doing load-based monitor
5587  * detection.
5588  *
5589  * It will be up to the load-detect code to adjust the pipe as appropriate for
5590  * its requirements.  The pipe will be connected to no other encoders.
5591  *
5592  * Currently this code will only succeed if there is a pipe with no encoders
5593  * configured for it.  In the future, it could choose to temporarily disable
5594  * some outputs to free up a pipe for its use.
5595  *
5596  * \return crtc, or NULL if no pipes are available.
5597  */
5598
5599 /* VESA 640x480x72Hz mode to set on the pipe */
5600 static struct drm_display_mode load_detect_mode = {
5601         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5602                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5603 };
5604
5605 static struct drm_framebuffer *
5606 intel_framebuffer_create(struct drm_device *dev,
5607                          struct drm_mode_fb_cmd *mode_cmd,
5608                          struct drm_i915_gem_object *obj)
5609 {
5610         struct intel_framebuffer *intel_fb;
5611         int ret;
5612
5613         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5614         if (!intel_fb) {
5615                 drm_gem_object_unreference_unlocked(&obj->base);
5616                 return ERR_PTR(-ENOMEM);
5617         }
5618
5619         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5620         if (ret) {
5621                 drm_gem_object_unreference_unlocked(&obj->base);
5622                 kfree(intel_fb);
5623                 return ERR_PTR(ret);
5624         }
5625
5626         return &intel_fb->base;
5627 }
5628
5629 static u32
5630 intel_framebuffer_pitch_for_width(int width, int bpp)
5631 {
5632         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5633         return ALIGN(pitch, 64);
5634 }
5635
5636 static u32
5637 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5638 {
5639         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5640         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5641 }
5642
5643 static struct drm_framebuffer *
5644 intel_framebuffer_create_for_mode(struct drm_device *dev,
5645                                   struct drm_display_mode *mode,
5646                                   int depth, int bpp)
5647 {
5648         struct drm_i915_gem_object *obj;
5649         struct drm_mode_fb_cmd mode_cmd;
5650
5651         obj = i915_gem_alloc_object(dev,
5652                                     intel_framebuffer_size_for_mode(mode, bpp));
5653         if (obj == NULL)
5654                 return ERR_PTR(-ENOMEM);
5655
5656         mode_cmd.width = mode->hdisplay;
5657         mode_cmd.height = mode->vdisplay;
5658         mode_cmd.depth = depth;
5659         mode_cmd.bpp = bpp;
5660         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5661
5662         return intel_framebuffer_create(dev, &mode_cmd, obj);
5663 }
5664
5665 static struct drm_framebuffer *
5666 mode_fits_in_fbdev(struct drm_device *dev,
5667                    struct drm_display_mode *mode)
5668 {
5669         struct drm_i915_private *dev_priv = dev->dev_private;
5670         struct drm_i915_gem_object *obj;
5671         struct drm_framebuffer *fb;
5672
5673         if (dev_priv->fbdev == NULL)
5674                 return NULL;
5675
5676         obj = dev_priv->fbdev->ifb.obj;
5677         if (obj == NULL)
5678                 return NULL;
5679
5680         fb = &dev_priv->fbdev->ifb.base;
5681         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5682                                                           fb->bits_per_pixel))
5683                 return NULL;
5684
5685         if (obj->base.size < mode->vdisplay * fb->pitch)
5686                 return NULL;
5687
5688         return fb;
5689 }
5690
5691 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5692                                 struct drm_connector *connector,
5693                                 struct drm_display_mode *mode,
5694                                 struct intel_load_detect_pipe *old)
5695 {
5696         struct intel_crtc *intel_crtc;
5697         struct drm_crtc *possible_crtc;
5698         struct drm_encoder *encoder = &intel_encoder->base;
5699         struct drm_crtc *crtc = NULL;
5700         struct drm_device *dev = encoder->dev;
5701         struct drm_framebuffer *old_fb;
5702         int i = -1;
5703
5704         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5705                       connector->base.id, drm_get_connector_name(connector),
5706                       encoder->base.id, drm_get_encoder_name(encoder));
5707
5708         /*
5709          * Algorithm gets a little messy:
5710          *
5711          *   - if the connector already has an assigned crtc, use it (but make
5712          *     sure it's on first)
5713          *
5714          *   - try to find the first unused crtc that can drive this connector,
5715          *     and use that if we find one
5716          */
5717
5718         /* See if we already have a CRTC for this connector */
5719         if (encoder->crtc) {
5720                 crtc = encoder->crtc;
5721
5722                 intel_crtc = to_intel_crtc(crtc);
5723                 old->dpms_mode = intel_crtc->dpms_mode;
5724                 old->load_detect_temp = false;
5725
5726                 /* Make sure the crtc and connector are running */
5727                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5728                         struct drm_encoder_helper_funcs *encoder_funcs;
5729                         struct drm_crtc_helper_funcs *crtc_funcs;
5730
5731                         crtc_funcs = crtc->helper_private;
5732                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5733
5734                         encoder_funcs = encoder->helper_private;
5735                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5736                 }
5737
5738                 return true;
5739         }
5740
5741         /* Find an unused one (if possible) */
5742         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5743                 i++;
5744                 if (!(encoder->possible_crtcs & (1 << i)))
5745                         continue;
5746                 if (!possible_crtc->enabled) {
5747                         crtc = possible_crtc;
5748                         break;
5749                 }
5750         }
5751
5752         /*
5753          * If we didn't find an unused CRTC, don't use any.
5754          */
5755         if (!crtc) {
5756                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5757                 return false;
5758         }
5759
5760         encoder->crtc = crtc;
5761         connector->encoder = encoder;
5762
5763         intel_crtc = to_intel_crtc(crtc);
5764         old->dpms_mode = intel_crtc->dpms_mode;
5765         old->load_detect_temp = true;
5766         old->release_fb = NULL;
5767
5768         if (!mode)
5769                 mode = &load_detect_mode;
5770
5771         old_fb = crtc->fb;
5772
5773         /* We need a framebuffer large enough to accommodate all accesses
5774          * that the plane may generate whilst we perform load detection.
5775          * We can not rely on the fbcon either being present (we get called
5776          * during its initialisation to detect all boot displays, or it may
5777          * not even exist) or that it is large enough to satisfy the
5778          * requested mode.
5779          */
5780         crtc->fb = mode_fits_in_fbdev(dev, mode);
5781         if (crtc->fb == NULL) {
5782                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5783                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5784                 old->release_fb = crtc->fb;
5785         } else
5786                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5787         if (IS_ERR(crtc->fb)) {
5788                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5789                 crtc->fb = old_fb;
5790                 return false;
5791         }
5792
5793         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5794                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5795                 if (old->release_fb)
5796                         old->release_fb->funcs->destroy(old->release_fb);
5797                 crtc->fb = old_fb;
5798                 return false;
5799         }
5800
5801         /* let the connector get through one full cycle before testing */
5802         intel_wait_for_vblank(dev, intel_crtc->pipe);
5803
5804         return true;
5805 }
5806
5807 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5808                                     struct drm_connector *connector,
5809                                     struct intel_load_detect_pipe *old)
5810 {
5811         struct drm_encoder *encoder = &intel_encoder->base;
5812         struct drm_device *dev = encoder->dev;
5813         struct drm_crtc *crtc = encoder->crtc;
5814         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5815         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5816
5817         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5818                       connector->base.id, drm_get_connector_name(connector),
5819                       encoder->base.id, drm_get_encoder_name(encoder));
5820
5821         if (old->load_detect_temp) {
5822                 connector->encoder = NULL;
5823                 drm_helper_disable_unused_functions(dev);
5824
5825                 if (old->release_fb)
5826                         old->release_fb->funcs->destroy(old->release_fb);
5827
5828                 return;
5829         }
5830
5831         /* Switch crtc and encoder back off if necessary */
5832         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5833                 encoder_funcs->dpms(encoder, old->dpms_mode);
5834                 crtc_funcs->dpms(crtc, old->dpms_mode);
5835         }
5836 }
5837
5838 /* Returns the clock of the currently programmed mode of the given pipe. */
5839 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5840 {
5841         struct drm_i915_private *dev_priv = dev->dev_private;
5842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5843         int pipe = intel_crtc->pipe;
5844         u32 dpll = I915_READ(DPLL(pipe));
5845         u32 fp;
5846         intel_clock_t clock;
5847
5848         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5849                 fp = I915_READ(FP0(pipe));
5850         else
5851                 fp = I915_READ(FP1(pipe));
5852
5853         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5854         if (IS_PINEVIEW(dev)) {
5855                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5856                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5857         } else {
5858                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5859                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5860         }
5861
5862         if (!IS_GEN2(dev)) {
5863                 if (IS_PINEVIEW(dev))
5864                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5865                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5866                 else
5867                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5868                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5869
5870                 switch (dpll & DPLL_MODE_MASK) {
5871                 case DPLLB_MODE_DAC_SERIAL:
5872                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5873                                 5 : 10;
5874                         break;
5875                 case DPLLB_MODE_LVDS:
5876                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5877                                 7 : 14;
5878                         break;
5879                 default:
5880                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5881                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5882                         return 0;
5883                 }
5884
5885                 /* XXX: Handle the 100Mhz refclk */
5886                 intel_clock(dev, 96000, &clock);
5887         } else {
5888                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5889
5890                 if (is_lvds) {
5891                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5892                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5893                         clock.p2 = 14;
5894
5895                         if ((dpll & PLL_REF_INPUT_MASK) ==
5896                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5897                                 /* XXX: might not be 66MHz */
5898                                 intel_clock(dev, 66000, &clock);
5899                         } else
5900                                 intel_clock(dev, 48000, &clock);
5901                 } else {
5902                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5903                                 clock.p1 = 2;
5904                         else {
5905                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5906                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5907                         }
5908                         if (dpll & PLL_P2_DIVIDE_BY_4)
5909                                 clock.p2 = 4;
5910                         else
5911                                 clock.p2 = 2;
5912
5913                         intel_clock(dev, 48000, &clock);
5914                 }
5915         }
5916
5917         /* XXX: It would be nice to validate the clocks, but we can't reuse
5918          * i830PllIsValid() because it relies on the xf86_config connector
5919          * configuration being accurate, which it isn't necessarily.
5920          */
5921
5922         return clock.dot;
5923 }
5924
5925 /** Returns the currently programmed mode of the given pipe. */
5926 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5927                                              struct drm_crtc *crtc)
5928 {
5929         struct drm_i915_private *dev_priv = dev->dev_private;
5930         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5931         int pipe = intel_crtc->pipe;
5932         struct drm_display_mode *mode;
5933         int htot = I915_READ(HTOTAL(pipe));
5934         int hsync = I915_READ(HSYNC(pipe));
5935         int vtot = I915_READ(VTOTAL(pipe));
5936         int vsync = I915_READ(VSYNC(pipe));
5937
5938         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5939         if (!mode)
5940                 return NULL;
5941
5942         mode->clock = intel_crtc_clock_get(dev, crtc);
5943         mode->hdisplay = (htot & 0xffff) + 1;
5944         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5945         mode->hsync_start = (hsync & 0xffff) + 1;
5946         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5947         mode->vdisplay = (vtot & 0xffff) + 1;
5948         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5949         mode->vsync_start = (vsync & 0xffff) + 1;
5950         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5951
5952         drm_mode_set_name(mode);
5953         drm_mode_set_crtcinfo(mode, 0);
5954
5955         return mode;
5956 }
5957
5958 #define GPU_IDLE_TIMEOUT 500 /* ms */
5959
5960 /* When this timer fires, we've been idle for awhile */
5961 static void intel_gpu_idle_timer(unsigned long arg)
5962 {
5963         struct drm_device *dev = (struct drm_device *)arg;
5964         drm_i915_private_t *dev_priv = dev->dev_private;
5965
5966         if (!list_empty(&dev_priv->mm.active_list)) {
5967                 /* Still processing requests, so just re-arm the timer. */
5968                 mod_timer(&dev_priv->idle_timer, jiffies +
5969                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5970                 return;
5971         }
5972
5973         dev_priv->busy = false;
5974         queue_work(dev_priv->wq, &dev_priv->idle_work);
5975 }
5976
5977 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5978
5979 static void intel_crtc_idle_timer(unsigned long arg)
5980 {
5981         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5982         struct drm_crtc *crtc = &intel_crtc->base;
5983         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5984         struct intel_framebuffer *intel_fb;
5985
5986         intel_fb = to_intel_framebuffer(crtc->fb);
5987         if (intel_fb && intel_fb->obj->active) {
5988                 /* The framebuffer is still being accessed by the GPU. */
5989                 mod_timer(&intel_crtc->idle_timer, jiffies +
5990                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5991                 return;
5992         }
5993
5994         intel_crtc->busy = false;
5995         queue_work(dev_priv->wq, &dev_priv->idle_work);
5996 }
5997
5998 static void intel_increase_pllclock(struct drm_crtc *crtc)
5999 {
6000         struct drm_device *dev = crtc->dev;
6001         drm_i915_private_t *dev_priv = dev->dev_private;
6002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6003         int pipe = intel_crtc->pipe;
6004         int dpll_reg = DPLL(pipe);
6005         int dpll;
6006
6007         if (HAS_PCH_SPLIT(dev))
6008                 return;
6009
6010         if (!dev_priv->lvds_downclock_avail)
6011                 return;
6012
6013         dpll = I915_READ(dpll_reg);
6014         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6015                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6016
6017                 /* Unlock panel regs */
6018                 I915_WRITE(PP_CONTROL,
6019                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6020
6021                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6022                 I915_WRITE(dpll_reg, dpll);
6023                 intel_wait_for_vblank(dev, pipe);
6024
6025                 dpll = I915_READ(dpll_reg);
6026                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6027                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6028
6029                 /* ...and lock them again */
6030                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6031         }
6032
6033         /* Schedule downclock */
6034         mod_timer(&intel_crtc->idle_timer, jiffies +
6035                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6036 }
6037
6038 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6039 {
6040         struct drm_device *dev = crtc->dev;
6041         drm_i915_private_t *dev_priv = dev->dev_private;
6042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6043         int pipe = intel_crtc->pipe;
6044         int dpll_reg = DPLL(pipe);
6045         int dpll = I915_READ(dpll_reg);
6046
6047         if (HAS_PCH_SPLIT(dev))
6048                 return;
6049
6050         if (!dev_priv->lvds_downclock_avail)
6051                 return;
6052
6053         /*
6054          * Since this is called by a timer, we should never get here in
6055          * the manual case.
6056          */
6057         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6058                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6059
6060                 /* Unlock panel regs */
6061                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6062                            PANEL_UNLOCK_REGS);
6063
6064                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6065                 I915_WRITE(dpll_reg, dpll);
6066                 intel_wait_for_vblank(dev, pipe);
6067                 dpll = I915_READ(dpll_reg);
6068                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6069                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6070
6071                 /* ...and lock them again */
6072                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6073         }
6074
6075 }
6076
6077 /**
6078  * intel_idle_update - adjust clocks for idleness
6079  * @work: work struct
6080  *
6081  * Either the GPU or display (or both) went idle.  Check the busy status
6082  * here and adjust the CRTC and GPU clocks as necessary.
6083  */
6084 static void intel_idle_update(struct work_struct *work)
6085 {
6086         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6087                                                     idle_work);
6088         struct drm_device *dev = dev_priv->dev;
6089         struct drm_crtc *crtc;
6090         struct intel_crtc *intel_crtc;
6091
6092         if (!i915_powersave)
6093                 return;
6094
6095         mutex_lock(&dev->struct_mutex);
6096
6097         i915_update_gfx_val(dev_priv);
6098
6099         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6100                 /* Skip inactive CRTCs */
6101                 if (!crtc->fb)
6102                         continue;
6103
6104                 intel_crtc = to_intel_crtc(crtc);
6105                 if (!intel_crtc->busy)
6106                         intel_decrease_pllclock(crtc);
6107         }
6108
6109
6110         mutex_unlock(&dev->struct_mutex);
6111 }
6112
6113 /**
6114  * intel_mark_busy - mark the GPU and possibly the display busy
6115  * @dev: drm device
6116  * @obj: object we're operating on
6117  *
6118  * Callers can use this function to indicate that the GPU is busy processing
6119  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6120  * buffer), we'll also mark the display as busy, so we know to increase its
6121  * clock frequency.
6122  */
6123 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6124 {
6125         drm_i915_private_t *dev_priv = dev->dev_private;
6126         struct drm_crtc *crtc = NULL;
6127         struct intel_framebuffer *intel_fb;
6128         struct intel_crtc *intel_crtc;
6129
6130         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6131                 return;
6132
6133         if (!dev_priv->busy)
6134                 dev_priv->busy = true;
6135         else
6136                 mod_timer(&dev_priv->idle_timer, jiffies +
6137                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6138
6139         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6140                 if (!crtc->fb)
6141                         continue;
6142
6143                 intel_crtc = to_intel_crtc(crtc);
6144                 intel_fb = to_intel_framebuffer(crtc->fb);
6145                 if (intel_fb->obj == obj) {
6146                         if (!intel_crtc->busy) {
6147                                 /* Non-busy -> busy, upclock */
6148                                 intel_increase_pllclock(crtc);
6149                                 intel_crtc->busy = true;
6150                         } else {
6151                                 /* Busy -> busy, put off timer */
6152                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6153                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6154                         }
6155                 }
6156         }
6157 }
6158
6159 static void intel_crtc_destroy(struct drm_crtc *crtc)
6160 {
6161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6162         struct drm_device *dev = crtc->dev;
6163         struct intel_unpin_work *work;
6164         unsigned long flags;
6165
6166         spin_lock_irqsave(&dev->event_lock, flags);
6167         work = intel_crtc->unpin_work;
6168         intel_crtc->unpin_work = NULL;
6169         spin_unlock_irqrestore(&dev->event_lock, flags);
6170
6171         if (work) {
6172                 cancel_work_sync(&work->work);
6173                 kfree(work);
6174         }
6175
6176         drm_crtc_cleanup(crtc);
6177
6178         kfree(intel_crtc);
6179 }
6180
6181 static void intel_unpin_work_fn(struct work_struct *__work)
6182 {
6183         struct intel_unpin_work *work =
6184                 container_of(__work, struct intel_unpin_work, work);
6185
6186         mutex_lock(&work->dev->struct_mutex);
6187         i915_gem_object_unpin(work->old_fb_obj);
6188         drm_gem_object_unreference(&work->pending_flip_obj->base);
6189         drm_gem_object_unreference(&work->old_fb_obj->base);
6190
6191         mutex_unlock(&work->dev->struct_mutex);
6192         kfree(work);
6193 }
6194
6195 static void do_intel_finish_page_flip(struct drm_device *dev,
6196                                       struct drm_crtc *crtc)
6197 {
6198         drm_i915_private_t *dev_priv = dev->dev_private;
6199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6200         struct intel_unpin_work *work;
6201         struct drm_i915_gem_object *obj;
6202         struct drm_pending_vblank_event *e;
6203         struct timeval tnow, tvbl;
6204         unsigned long flags;
6205
6206         /* Ignore early vblank irqs */
6207         if (intel_crtc == NULL)
6208                 return;
6209
6210         do_gettimeofday(&tnow);
6211
6212         spin_lock_irqsave(&dev->event_lock, flags);
6213         work = intel_crtc->unpin_work;
6214         if (work == NULL || !work->pending) {
6215                 spin_unlock_irqrestore(&dev->event_lock, flags);
6216                 return;
6217         }
6218
6219         intel_crtc->unpin_work = NULL;
6220
6221         if (work->event) {
6222                 e = work->event;
6223                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6224
6225                 /* Called before vblank count and timestamps have
6226                  * been updated for the vblank interval of flip
6227                  * completion? Need to increment vblank count and
6228                  * add one videorefresh duration to returned timestamp
6229                  * to account for this. We assume this happened if we
6230                  * get called over 0.9 frame durations after the last
6231                  * timestamped vblank.
6232                  *
6233                  * This calculation can not be used with vrefresh rates
6234                  * below 5Hz (10Hz to be on the safe side) without
6235                  * promoting to 64 integers.
6236                  */
6237                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6238                     9 * crtc->framedur_ns) {
6239                         e->event.sequence++;
6240                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6241                                              crtc->framedur_ns);
6242                 }
6243
6244                 e->event.tv_sec = tvbl.tv_sec;
6245                 e->event.tv_usec = tvbl.tv_usec;
6246
6247                 list_add_tail(&e->base.link,
6248                               &e->base.file_priv->event_list);
6249                 wake_up_interruptible(&e->base.file_priv->event_wait);
6250         }
6251
6252         drm_vblank_put(dev, intel_crtc->pipe);
6253
6254         spin_unlock_irqrestore(&dev->event_lock, flags);
6255
6256         obj = work->old_fb_obj;
6257
6258         atomic_clear_mask(1 << intel_crtc->plane,
6259                           &obj->pending_flip.counter);
6260         if (atomic_read(&obj->pending_flip) == 0)
6261                 wake_up(&dev_priv->pending_flip_queue);
6262
6263         schedule_work(&work->work);
6264
6265         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6266 }
6267
6268 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6269 {
6270         drm_i915_private_t *dev_priv = dev->dev_private;
6271         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6272
6273         do_intel_finish_page_flip(dev, crtc);
6274 }
6275
6276 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6277 {
6278         drm_i915_private_t *dev_priv = dev->dev_private;
6279         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6280
6281         do_intel_finish_page_flip(dev, crtc);
6282 }
6283
6284 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6285 {
6286         drm_i915_private_t *dev_priv = dev->dev_private;
6287         struct intel_crtc *intel_crtc =
6288                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6289         unsigned long flags;
6290
6291         spin_lock_irqsave(&dev->event_lock, flags);
6292         if (intel_crtc->unpin_work) {
6293                 if ((++intel_crtc->unpin_work->pending) > 1)
6294                         DRM_ERROR("Prepared flip multiple times\n");
6295         } else {
6296                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6297         }
6298         spin_unlock_irqrestore(&dev->event_lock, flags);
6299 }
6300
6301 static int intel_gen2_queue_flip(struct drm_device *dev,
6302                                  struct drm_crtc *crtc,
6303                                  struct drm_framebuffer *fb,
6304                                  struct drm_i915_gem_object *obj)
6305 {
6306         struct drm_i915_private *dev_priv = dev->dev_private;
6307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6308         unsigned long offset;
6309         u32 flip_mask;
6310         int ret;
6311
6312         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6313         if (ret)
6314                 goto out;
6315
6316         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6317         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6318
6319         ret = BEGIN_LP_RING(6);
6320         if (ret)
6321                 goto out;
6322
6323         /* Can't queue multiple flips, so wait for the previous
6324          * one to finish before executing the next.
6325          */
6326         if (intel_crtc->plane)
6327                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6328         else
6329                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6330         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6331         OUT_RING(MI_NOOP);
6332         OUT_RING(MI_DISPLAY_FLIP |
6333                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6334         OUT_RING(fb->pitch);
6335         OUT_RING(obj->gtt_offset + offset);
6336         OUT_RING(MI_NOOP);
6337         ADVANCE_LP_RING();
6338 out:
6339         return ret;
6340 }
6341
6342 static int intel_gen3_queue_flip(struct drm_device *dev,
6343                                  struct drm_crtc *crtc,
6344                                  struct drm_framebuffer *fb,
6345                                  struct drm_i915_gem_object *obj)
6346 {
6347         struct drm_i915_private *dev_priv = dev->dev_private;
6348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6349         unsigned long offset;
6350         u32 flip_mask;
6351         int ret;
6352
6353         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6354         if (ret)
6355                 goto out;
6356
6357         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6358         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6359
6360         ret = BEGIN_LP_RING(6);
6361         if (ret)
6362                 goto out;
6363
6364         if (intel_crtc->plane)
6365                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6366         else
6367                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6368         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6369         OUT_RING(MI_NOOP);
6370         OUT_RING(MI_DISPLAY_FLIP_I915 |
6371                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6372         OUT_RING(fb->pitch);
6373         OUT_RING(obj->gtt_offset + offset);
6374         OUT_RING(MI_NOOP);
6375
6376         ADVANCE_LP_RING();
6377 out:
6378         return ret;
6379 }
6380
6381 static int intel_gen4_queue_flip(struct drm_device *dev,
6382                                  struct drm_crtc *crtc,
6383                                  struct drm_framebuffer *fb,
6384                                  struct drm_i915_gem_object *obj)
6385 {
6386         struct drm_i915_private *dev_priv = dev->dev_private;
6387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6388         uint32_t pf, pipesrc;
6389         int ret;
6390
6391         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6392         if (ret)
6393                 goto out;
6394
6395         ret = BEGIN_LP_RING(4);
6396         if (ret)
6397                 goto out;
6398
6399         /* i965+ uses the linear or tiled offsets from the
6400          * Display Registers (which do not change across a page-flip)
6401          * so we need only reprogram the base address.
6402          */
6403         OUT_RING(MI_DISPLAY_FLIP |
6404                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6405         OUT_RING(fb->pitch);
6406         OUT_RING(obj->gtt_offset | obj->tiling_mode);
6407
6408         /* XXX Enabling the panel-fitter across page-flip is so far
6409          * untested on non-native modes, so ignore it for now.
6410          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6411          */
6412         pf = 0;
6413         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6414         OUT_RING(pf | pipesrc);
6415         ADVANCE_LP_RING();
6416 out:
6417         return ret;
6418 }
6419
6420 static int intel_gen6_queue_flip(struct drm_device *dev,
6421                                  struct drm_crtc *crtc,
6422                                  struct drm_framebuffer *fb,
6423                                  struct drm_i915_gem_object *obj)
6424 {
6425         struct drm_i915_private *dev_priv = dev->dev_private;
6426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6427         uint32_t pf, pipesrc;
6428         int ret;
6429
6430         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6431         if (ret)
6432                 goto out;
6433
6434         ret = BEGIN_LP_RING(4);
6435         if (ret)
6436                 goto out;
6437
6438         OUT_RING(MI_DISPLAY_FLIP |
6439                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6440         OUT_RING(fb->pitch | obj->tiling_mode);
6441         OUT_RING(obj->gtt_offset);
6442
6443         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6444         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6445         OUT_RING(pf | pipesrc);
6446         ADVANCE_LP_RING();
6447 out:
6448         return ret;
6449 }
6450
6451 /*
6452  * On gen7 we currently use the blit ring because (in early silicon at least)
6453  * the render ring doesn't give us interrpts for page flip completion, which
6454  * means clients will hang after the first flip is queued.  Fortunately the
6455  * blit ring generates interrupts properly, so use it instead.
6456  */
6457 static int intel_gen7_queue_flip(struct drm_device *dev,
6458                                  struct drm_crtc *crtc,
6459                                  struct drm_framebuffer *fb,
6460                                  struct drm_i915_gem_object *obj)
6461 {
6462         struct drm_i915_private *dev_priv = dev->dev_private;
6463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6464         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6465         int ret;
6466
6467         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6468         if (ret)
6469                 goto out;
6470
6471         ret = intel_ring_begin(ring, 4);
6472         if (ret)
6473                 goto out;
6474
6475         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6476         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6477         intel_ring_emit(ring, (obj->gtt_offset));
6478         intel_ring_emit(ring, (MI_NOOP));
6479         intel_ring_advance(ring);
6480 out:
6481         return ret;
6482 }
6483
6484 static int intel_default_queue_flip(struct drm_device *dev,
6485                                     struct drm_crtc *crtc,
6486                                     struct drm_framebuffer *fb,
6487                                     struct drm_i915_gem_object *obj)
6488 {
6489         return -ENODEV;
6490 }
6491
6492 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6493                                 struct drm_framebuffer *fb,
6494                                 struct drm_pending_vblank_event *event)
6495 {
6496         struct drm_device *dev = crtc->dev;
6497         struct drm_i915_private *dev_priv = dev->dev_private;
6498         struct intel_framebuffer *intel_fb;
6499         struct drm_i915_gem_object *obj;
6500         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6501         struct intel_unpin_work *work;
6502         unsigned long flags;
6503         int ret;
6504
6505         work = kzalloc(sizeof *work, GFP_KERNEL);
6506         if (work == NULL)
6507                 return -ENOMEM;
6508
6509         work->event = event;
6510         work->dev = crtc->dev;
6511         intel_fb = to_intel_framebuffer(crtc->fb);
6512         work->old_fb_obj = intel_fb->obj;
6513         INIT_WORK(&work->work, intel_unpin_work_fn);
6514
6515         /* We borrow the event spin lock for protecting unpin_work */
6516         spin_lock_irqsave(&dev->event_lock, flags);
6517         if (intel_crtc->unpin_work) {
6518                 spin_unlock_irqrestore(&dev->event_lock, flags);
6519                 kfree(work);
6520
6521                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6522                 return -EBUSY;
6523         }
6524         intel_crtc->unpin_work = work;
6525         spin_unlock_irqrestore(&dev->event_lock, flags);
6526
6527         intel_fb = to_intel_framebuffer(fb);
6528         obj = intel_fb->obj;
6529
6530         mutex_lock(&dev->struct_mutex);
6531
6532         /* Reference the objects for the scheduled work. */
6533         drm_gem_object_reference(&work->old_fb_obj->base);
6534         drm_gem_object_reference(&obj->base);
6535
6536         crtc->fb = fb;
6537
6538         ret = drm_vblank_get(dev, intel_crtc->pipe);
6539         if (ret)
6540                 goto cleanup_objs;
6541
6542         work->pending_flip_obj = obj;
6543
6544         work->enable_stall_check = true;
6545
6546         /* Block clients from rendering to the new back buffer until
6547          * the flip occurs and the object is no longer visible.
6548          */
6549         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6550
6551         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6552         if (ret)
6553                 goto cleanup_pending;
6554
6555         mutex_unlock(&dev->struct_mutex);
6556
6557         trace_i915_flip_request(intel_crtc->plane, obj);
6558
6559         return 0;
6560
6561 cleanup_pending:
6562         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6563 cleanup_objs:
6564         drm_gem_object_unreference(&work->old_fb_obj->base);
6565         drm_gem_object_unreference(&obj->base);
6566         mutex_unlock(&dev->struct_mutex);
6567
6568         spin_lock_irqsave(&dev->event_lock, flags);
6569         intel_crtc->unpin_work = NULL;
6570         spin_unlock_irqrestore(&dev->event_lock, flags);
6571
6572         kfree(work);
6573
6574         return ret;
6575 }
6576
6577 static void intel_sanitize_modesetting(struct drm_device *dev,
6578                                        int pipe, int plane)
6579 {
6580         struct drm_i915_private *dev_priv = dev->dev_private;
6581         u32 reg, val;
6582
6583         /* Clear any frame start delays used for debugging left by the BIOS */
6584         for_each_pipe(pipe) {
6585                 reg = PIPECONF(pipe);
6586                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6587         }
6588
6589         if (HAS_PCH_SPLIT(dev))
6590                 return;
6591
6592         /* Who knows what state these registers were left in by the BIOS or
6593          * grub?
6594          *
6595          * If we leave the registers in a conflicting state (e.g. with the
6596          * display plane reading from the other pipe than the one we intend
6597          * to use) then when we attempt to teardown the active mode, we will
6598          * not disable the pipes and planes in the correct order -- leaving
6599          * a plane reading from a disabled pipe and possibly leading to
6600          * undefined behaviour.
6601          */
6602
6603         reg = DSPCNTR(plane);
6604         val = I915_READ(reg);
6605
6606         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6607                 return;
6608         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6609                 return;
6610
6611         /* This display plane is active and attached to the other CPU pipe. */
6612         pipe = !pipe;
6613
6614         /* Disable the plane and wait for it to stop reading from the pipe. */
6615         intel_disable_plane(dev_priv, plane, pipe);
6616         intel_disable_pipe(dev_priv, pipe);
6617 }
6618
6619 static void intel_crtc_reset(struct drm_crtc *crtc)
6620 {
6621         struct drm_device *dev = crtc->dev;
6622         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6623
6624         /* Reset flags back to the 'unknown' status so that they
6625          * will be correctly set on the initial modeset.
6626          */
6627         intel_crtc->dpms_mode = -1;
6628
6629         /* We need to fix up any BIOS configuration that conflicts with
6630          * our expectations.
6631          */
6632         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6633 }
6634
6635 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6636         .dpms = intel_crtc_dpms,
6637         .mode_fixup = intel_crtc_mode_fixup,
6638         .mode_set = intel_crtc_mode_set,
6639         .mode_set_base = intel_pipe_set_base,
6640         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6641         .load_lut = intel_crtc_load_lut,
6642         .disable = intel_crtc_disable,
6643 };
6644
6645 static const struct drm_crtc_funcs intel_crtc_funcs = {
6646         .reset = intel_crtc_reset,
6647         .cursor_set = intel_crtc_cursor_set,
6648         .cursor_move = intel_crtc_cursor_move,
6649         .gamma_set = intel_crtc_gamma_set,
6650         .set_config = drm_crtc_helper_set_config,
6651         .destroy = intel_crtc_destroy,
6652         .page_flip = intel_crtc_page_flip,
6653 };
6654
6655 static void intel_crtc_init(struct drm_device *dev, int pipe)
6656 {
6657         drm_i915_private_t *dev_priv = dev->dev_private;
6658         struct intel_crtc *intel_crtc;
6659         int i;
6660
6661         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6662         if (intel_crtc == NULL)
6663                 return;
6664
6665         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6666
6667         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6668         for (i = 0; i < 256; i++) {
6669                 intel_crtc->lut_r[i] = i;
6670                 intel_crtc->lut_g[i] = i;
6671                 intel_crtc->lut_b[i] = i;
6672         }
6673
6674         /* Swap pipes & planes for FBC on pre-965 */
6675         intel_crtc->pipe = pipe;
6676         intel_crtc->plane = pipe;
6677         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6678                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6679                 intel_crtc->plane = !pipe;
6680         }
6681
6682         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6683                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6684         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6685         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6686
6687         intel_crtc_reset(&intel_crtc->base);
6688         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6689
6690         if (HAS_PCH_SPLIT(dev)) {
6691                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6692                 intel_helper_funcs.commit = ironlake_crtc_commit;
6693         } else {
6694                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6695                 intel_helper_funcs.commit = i9xx_crtc_commit;
6696         }
6697
6698         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6699
6700         intel_crtc->busy = false;
6701
6702         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6703                     (unsigned long)intel_crtc);
6704 }
6705
6706 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6707                                 struct drm_file *file)
6708 {
6709         drm_i915_private_t *dev_priv = dev->dev_private;
6710         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6711         struct drm_mode_object *drmmode_obj;
6712         struct intel_crtc *crtc;
6713
6714         if (!dev_priv) {
6715                 DRM_ERROR("called with no initialization\n");
6716                 return -EINVAL;
6717         }
6718
6719         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6720                         DRM_MODE_OBJECT_CRTC);
6721
6722         if (!drmmode_obj) {
6723                 DRM_ERROR("no such CRTC id\n");
6724                 return -EINVAL;
6725         }
6726
6727         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6728         pipe_from_crtc_id->pipe = crtc->pipe;
6729
6730         return 0;
6731 }
6732
6733 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6734 {
6735         struct intel_encoder *encoder;
6736         int index_mask = 0;
6737         int entry = 0;
6738
6739         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6740                 if (type_mask & encoder->clone_mask)
6741                         index_mask |= (1 << entry);
6742                 entry++;
6743         }
6744
6745         return index_mask;
6746 }
6747
6748 static bool has_edp_a(struct drm_device *dev)
6749 {
6750         struct drm_i915_private *dev_priv = dev->dev_private;
6751
6752         if (!IS_MOBILE(dev))
6753                 return false;
6754
6755         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6756                 return false;
6757
6758         if (IS_GEN5(dev) &&
6759             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6760                 return false;
6761
6762         return true;
6763 }
6764
6765 static void intel_setup_outputs(struct drm_device *dev)
6766 {
6767         struct drm_i915_private *dev_priv = dev->dev_private;
6768         struct intel_encoder *encoder;
6769         bool dpd_is_edp = false;
6770         bool has_lvds = false;
6771
6772         if (IS_MOBILE(dev) && !IS_I830(dev))
6773                 has_lvds = intel_lvds_init(dev);
6774         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6775                 /* disable the panel fitter on everything but LVDS */
6776                 I915_WRITE(PFIT_CONTROL, 0);
6777         }
6778
6779         if (HAS_PCH_SPLIT(dev)) {
6780                 dpd_is_edp = intel_dpd_is_edp(dev);
6781
6782                 if (has_edp_a(dev))
6783                         intel_dp_init(dev, DP_A);
6784
6785                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6786                         intel_dp_init(dev, PCH_DP_D);
6787         }
6788
6789         intel_crt_init(dev);
6790
6791         if (HAS_PCH_SPLIT(dev)) {
6792                 int found;
6793
6794                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6795                         /* PCH SDVOB multiplex with HDMIB */
6796                         found = intel_sdvo_init(dev, PCH_SDVOB);
6797                         if (!found)
6798                                 intel_hdmi_init(dev, HDMIB);
6799                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6800                                 intel_dp_init(dev, PCH_DP_B);
6801                 }
6802
6803                 if (I915_READ(HDMIC) & PORT_DETECTED)
6804                         intel_hdmi_init(dev, HDMIC);
6805
6806                 if (I915_READ(HDMID) & PORT_DETECTED)
6807                         intel_hdmi_init(dev, HDMID);
6808
6809                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6810                         intel_dp_init(dev, PCH_DP_C);
6811
6812                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6813                         intel_dp_init(dev, PCH_DP_D);
6814
6815         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6816                 bool found = false;
6817
6818                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6819                         DRM_DEBUG_KMS("probing SDVOB\n");
6820                         found = intel_sdvo_init(dev, SDVOB);
6821                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6822                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6823                                 intel_hdmi_init(dev, SDVOB);
6824                         }
6825
6826                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6827                                 DRM_DEBUG_KMS("probing DP_B\n");
6828                                 intel_dp_init(dev, DP_B);
6829                         }
6830                 }
6831
6832                 /* Before G4X SDVOC doesn't have its own detect register */
6833
6834                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6835                         DRM_DEBUG_KMS("probing SDVOC\n");
6836                         found = intel_sdvo_init(dev, SDVOC);
6837                 }
6838
6839                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6840
6841                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6842                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6843                                 intel_hdmi_init(dev, SDVOC);
6844                         }
6845                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6846                                 DRM_DEBUG_KMS("probing DP_C\n");
6847                                 intel_dp_init(dev, DP_C);
6848                         }
6849                 }
6850
6851                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6852                     (I915_READ(DP_D) & DP_DETECTED)) {
6853                         DRM_DEBUG_KMS("probing DP_D\n");
6854                         intel_dp_init(dev, DP_D);
6855                 }
6856         } else if (IS_GEN2(dev))
6857                 intel_dvo_init(dev);
6858
6859         if (SUPPORTS_TV(dev))
6860                 intel_tv_init(dev);
6861
6862         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6863                 encoder->base.possible_crtcs = encoder->crtc_mask;
6864                 encoder->base.possible_clones =
6865                         intel_encoder_clones(dev, encoder->clone_mask);
6866         }
6867
6868         intel_panel_setup_backlight(dev);
6869
6870         /* disable all the possible outputs/crtcs before entering KMS mode */
6871         drm_helper_disable_unused_functions(dev);
6872 }
6873
6874 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6875 {
6876         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6877
6878         drm_framebuffer_cleanup(fb);
6879         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6880
6881         kfree(intel_fb);
6882 }
6883
6884 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6885                                                 struct drm_file *file,
6886                                                 unsigned int *handle)
6887 {
6888         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6889         struct drm_i915_gem_object *obj = intel_fb->obj;
6890
6891         return drm_gem_handle_create(file, &obj->base, handle);
6892 }
6893
6894 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6895         .destroy = intel_user_framebuffer_destroy,
6896         .create_handle = intel_user_framebuffer_create_handle,
6897 };
6898
6899 int intel_framebuffer_init(struct drm_device *dev,
6900                            struct intel_framebuffer *intel_fb,
6901                            struct drm_mode_fb_cmd *mode_cmd,
6902                            struct drm_i915_gem_object *obj)
6903 {
6904         int ret;
6905
6906         if (obj->tiling_mode == I915_TILING_Y)
6907                 return -EINVAL;
6908
6909         if (mode_cmd->pitch & 63)
6910                 return -EINVAL;
6911
6912         switch (mode_cmd->bpp) {
6913         case 8:
6914         case 16:
6915         case 24:
6916         case 32:
6917                 break;
6918         default:
6919                 return -EINVAL;
6920         }
6921
6922         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6923         if (ret) {
6924                 DRM_ERROR("framebuffer init failed %d\n", ret);
6925                 return ret;
6926         }
6927
6928         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6929         intel_fb->obj = obj;
6930         return 0;
6931 }
6932
6933 static struct drm_framebuffer *
6934 intel_user_framebuffer_create(struct drm_device *dev,
6935                               struct drm_file *filp,
6936                               struct drm_mode_fb_cmd *mode_cmd)
6937 {
6938         struct drm_i915_gem_object *obj;
6939
6940         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6941         if (&obj->base == NULL)
6942                 return ERR_PTR(-ENOENT);
6943
6944         return intel_framebuffer_create(dev, mode_cmd, obj);
6945 }
6946
6947 static const struct drm_mode_config_funcs intel_mode_funcs = {
6948         .fb_create = intel_user_framebuffer_create,
6949         .output_poll_changed = intel_fb_output_poll_changed,
6950 };
6951
6952 static struct drm_i915_gem_object *
6953 intel_alloc_context_page(struct drm_device *dev)
6954 {
6955         struct drm_i915_gem_object *ctx;
6956         int ret;
6957
6958         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6959
6960         ctx = i915_gem_alloc_object(dev, 4096);
6961         if (!ctx) {
6962                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6963                 return NULL;
6964         }
6965
6966         ret = i915_gem_object_pin(ctx, 4096, true);
6967         if (ret) {
6968                 DRM_ERROR("failed to pin power context: %d\n", ret);
6969                 goto err_unref;
6970         }
6971
6972         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6973         if (ret) {
6974                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6975                 goto err_unpin;
6976         }
6977
6978         return ctx;
6979
6980 err_unpin:
6981         i915_gem_object_unpin(ctx);
6982 err_unref:
6983         drm_gem_object_unreference(&ctx->base);
6984         mutex_unlock(&dev->struct_mutex);
6985         return NULL;
6986 }
6987
6988 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6989 {
6990         struct drm_i915_private *dev_priv = dev->dev_private;
6991         u16 rgvswctl;
6992
6993         rgvswctl = I915_READ16(MEMSWCTL);
6994         if (rgvswctl & MEMCTL_CMD_STS) {
6995                 DRM_DEBUG("gpu busy, RCS change rejected\n");
6996                 return false; /* still busy with another command */
6997         }
6998
6999         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7000                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7001         I915_WRITE16(MEMSWCTL, rgvswctl);
7002         POSTING_READ16(MEMSWCTL);
7003
7004         rgvswctl |= MEMCTL_CMD_STS;
7005         I915_WRITE16(MEMSWCTL, rgvswctl);
7006
7007         return true;
7008 }
7009
7010 void ironlake_enable_drps(struct drm_device *dev)
7011 {
7012         struct drm_i915_private *dev_priv = dev->dev_private;
7013         u32 rgvmodectl = I915_READ(MEMMODECTL);
7014         u8 fmax, fmin, fstart, vstart;
7015
7016         /* Enable temp reporting */
7017         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7018         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7019
7020         /* 100ms RC evaluation intervals */
7021         I915_WRITE(RCUPEI, 100000);
7022         I915_WRITE(RCDNEI, 100000);
7023
7024         /* Set max/min thresholds to 90ms and 80ms respectively */
7025         I915_WRITE(RCBMAXAVG, 90000);
7026         I915_WRITE(RCBMINAVG, 80000);
7027
7028         I915_WRITE(MEMIHYST, 1);
7029
7030         /* Set up min, max, and cur for interrupt handling */
7031         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7032         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7033         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7034                 MEMMODE_FSTART_SHIFT;
7035
7036         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7037                 PXVFREQ_PX_SHIFT;
7038
7039         dev_priv->fmax = fmax; /* IPS callback will increase this */
7040         dev_priv->fstart = fstart;
7041
7042         dev_priv->max_delay = fstart;
7043         dev_priv->min_delay = fmin;
7044         dev_priv->cur_delay = fstart;
7045
7046         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7047                          fmax, fmin, fstart);
7048
7049         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7050
7051         /*
7052          * Interrupts will be enabled in ironlake_irq_postinstall
7053          */
7054
7055         I915_WRITE(VIDSTART, vstart);
7056         POSTING_READ(VIDSTART);
7057
7058         rgvmodectl |= MEMMODE_SWMODE_EN;
7059         I915_WRITE(MEMMODECTL, rgvmodectl);
7060
7061         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7062                 DRM_ERROR("stuck trying to change perf mode\n");
7063         msleep(1);
7064
7065         ironlake_set_drps(dev, fstart);
7066
7067         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7068                 I915_READ(0x112e0);
7069         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7070         dev_priv->last_count2 = I915_READ(0x112f4);
7071         getrawmonotonic(&dev_priv->last_time2);
7072 }
7073
7074 void ironlake_disable_drps(struct drm_device *dev)
7075 {
7076         struct drm_i915_private *dev_priv = dev->dev_private;
7077         u16 rgvswctl = I915_READ16(MEMSWCTL);
7078
7079         /* Ack interrupts, disable EFC interrupt */
7080         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7081         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7082         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7083         I915_WRITE(DEIIR, DE_PCU_EVENT);
7084         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7085
7086         /* Go back to the starting frequency */
7087         ironlake_set_drps(dev, dev_priv->fstart);
7088         msleep(1);
7089         rgvswctl |= MEMCTL_CMD_STS;
7090         I915_WRITE(MEMSWCTL, rgvswctl);
7091         msleep(1);
7092
7093 }
7094
7095 void gen6_set_rps(struct drm_device *dev, u8 val)
7096 {
7097         struct drm_i915_private *dev_priv = dev->dev_private;
7098         u32 swreq;
7099
7100         swreq = (val & 0x3ff) << 25;
7101         I915_WRITE(GEN6_RPNSWREQ, swreq);
7102 }
7103
7104 void gen6_disable_rps(struct drm_device *dev)
7105 {
7106         struct drm_i915_private *dev_priv = dev->dev_private;
7107
7108         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7109         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7110         I915_WRITE(GEN6_PMIER, 0);
7111
7112         spin_lock_irq(&dev_priv->rps_lock);
7113         dev_priv->pm_iir = 0;
7114         spin_unlock_irq(&dev_priv->rps_lock);
7115
7116         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7117 }
7118
7119 static unsigned long intel_pxfreq(u32 vidfreq)
7120 {
7121         unsigned long freq;
7122         int div = (vidfreq & 0x3f0000) >> 16;
7123         int post = (vidfreq & 0x3000) >> 12;
7124         int pre = (vidfreq & 0x7);
7125
7126         if (!pre)
7127                 return 0;
7128
7129         freq = ((div * 133333) / ((1<<post) * pre));
7130
7131         return freq;
7132 }
7133
7134 void intel_init_emon(struct drm_device *dev)
7135 {
7136         struct drm_i915_private *dev_priv = dev->dev_private;
7137         u32 lcfuse;
7138         u8 pxw[16];
7139         int i;
7140
7141         /* Disable to program */
7142         I915_WRITE(ECR, 0);
7143         POSTING_READ(ECR);
7144
7145         /* Program energy weights for various events */
7146         I915_WRITE(SDEW, 0x15040d00);
7147         I915_WRITE(CSIEW0, 0x007f0000);
7148         I915_WRITE(CSIEW1, 0x1e220004);
7149         I915_WRITE(CSIEW2, 0x04000004);
7150
7151         for (i = 0; i < 5; i++)
7152                 I915_WRITE(PEW + (i * 4), 0);
7153         for (i = 0; i < 3; i++)
7154                 I915_WRITE(DEW + (i * 4), 0);
7155
7156         /* Program P-state weights to account for frequency power adjustment */
7157         for (i = 0; i < 16; i++) {
7158                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7159                 unsigned long freq = intel_pxfreq(pxvidfreq);
7160                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7161                         PXVFREQ_PX_SHIFT;
7162                 unsigned long val;
7163
7164                 val = vid * vid;
7165                 val *= (freq / 1000);
7166                 val *= 255;
7167                 val /= (127*127*900);
7168                 if (val > 0xff)
7169                         DRM_ERROR("bad pxval: %ld\n", val);
7170                 pxw[i] = val;
7171         }
7172         /* Render standby states get 0 weight */
7173         pxw[14] = 0;
7174         pxw[15] = 0;
7175
7176         for (i = 0; i < 4; i++) {
7177                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7178                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7179                 I915_WRITE(PXW + (i * 4), val);
7180         }
7181
7182         /* Adjust magic regs to magic values (more experimental results) */
7183         I915_WRITE(OGW0, 0);
7184         I915_WRITE(OGW1, 0);
7185         I915_WRITE(EG0, 0x00007f00);
7186         I915_WRITE(EG1, 0x0000000e);
7187         I915_WRITE(EG2, 0x000e0000);
7188         I915_WRITE(EG3, 0x68000300);
7189         I915_WRITE(EG4, 0x42000000);
7190         I915_WRITE(EG5, 0x00140031);
7191         I915_WRITE(EG6, 0);
7192         I915_WRITE(EG7, 0);
7193
7194         for (i = 0; i < 8; i++)
7195                 I915_WRITE(PXWL + (i * 4), 0);
7196
7197         /* Enable PMON + select events */
7198         I915_WRITE(ECR, 0x80000019);
7199
7200         lcfuse = I915_READ(LCFUSE02);
7201
7202         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7203 }
7204
7205 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7206 {
7207         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7208         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7209         u32 pcu_mbox, rc6_mask = 0;
7210         int cur_freq, min_freq, max_freq;
7211         int i;
7212
7213         /* Here begins a magic sequence of register writes to enable
7214          * auto-downclocking.
7215          *
7216          * Perhaps there might be some value in exposing these to
7217          * userspace...
7218          */
7219         I915_WRITE(GEN6_RC_STATE, 0);
7220         mutex_lock(&dev_priv->dev->struct_mutex);
7221         gen6_gt_force_wake_get(dev_priv);
7222
7223         /* disable the counters and set deterministic thresholds */
7224         I915_WRITE(GEN6_RC_CONTROL, 0);
7225
7226         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7227         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7228         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7229         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7230         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7231
7232         for (i = 0; i < I915_NUM_RINGS; i++)
7233                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7234
7235         I915_WRITE(GEN6_RC_SLEEP, 0);
7236         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7237         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7238         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7239         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7240
7241         if (i915_enable_rc6)
7242                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7243                         GEN6_RC_CTL_RC6_ENABLE;
7244
7245         I915_WRITE(GEN6_RC_CONTROL,
7246                    rc6_mask |
7247                    GEN6_RC_CTL_EI_MODE(1) |
7248                    GEN6_RC_CTL_HW_ENABLE);
7249
7250         I915_WRITE(GEN6_RPNSWREQ,
7251                    GEN6_FREQUENCY(10) |
7252                    GEN6_OFFSET(0) |
7253                    GEN6_AGGRESSIVE_TURBO);
7254         I915_WRITE(GEN6_RC_VIDEO_FREQ,
7255                    GEN6_FREQUENCY(12));
7256
7257         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7258         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7259                    18 << 24 |
7260                    6 << 16);
7261         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7262         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7263         I915_WRITE(GEN6_RP_UP_EI, 100000);
7264         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7265         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7266         I915_WRITE(GEN6_RP_CONTROL,
7267                    GEN6_RP_MEDIA_TURBO |
7268                    GEN6_RP_USE_NORMAL_FREQ |
7269                    GEN6_RP_MEDIA_IS_GFX |
7270                    GEN6_RP_ENABLE |
7271                    GEN6_RP_UP_BUSY_AVG |
7272                    GEN6_RP_DOWN_IDLE_CONT);
7273
7274         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7275                      500))
7276                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7277
7278         I915_WRITE(GEN6_PCODE_DATA, 0);
7279         I915_WRITE(GEN6_PCODE_MAILBOX,
7280                    GEN6_PCODE_READY |
7281                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7282         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7283                      500))
7284                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7285
7286         min_freq = (rp_state_cap & 0xff0000) >> 16;
7287         max_freq = rp_state_cap & 0xff;
7288         cur_freq = (gt_perf_status & 0xff00) >> 8;
7289
7290         /* Check for overclock support */
7291         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7292                      500))
7293                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7294         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7295         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7296         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7297                      500))
7298                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7299         if (pcu_mbox & (1<<31)) { /* OC supported */
7300                 max_freq = pcu_mbox & 0xff;
7301                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7302         }
7303
7304         /* In units of 100MHz */
7305         dev_priv->max_delay = max_freq;
7306         dev_priv->min_delay = min_freq;
7307         dev_priv->cur_delay = cur_freq;
7308
7309         /* requires MSI enabled */
7310         I915_WRITE(GEN6_PMIER,
7311                    GEN6_PM_MBOX_EVENT |
7312                    GEN6_PM_THERMAL_EVENT |
7313                    GEN6_PM_RP_DOWN_TIMEOUT |
7314                    GEN6_PM_RP_UP_THRESHOLD |
7315                    GEN6_PM_RP_DOWN_THRESHOLD |
7316                    GEN6_PM_RP_UP_EI_EXPIRED |
7317                    GEN6_PM_RP_DOWN_EI_EXPIRED);
7318         spin_lock_irq(&dev_priv->rps_lock);
7319         WARN_ON(dev_priv->pm_iir != 0);
7320         I915_WRITE(GEN6_PMIMR, 0);
7321         spin_unlock_irq(&dev_priv->rps_lock);
7322         /* enable all PM interrupts */
7323         I915_WRITE(GEN6_PMINTRMSK, 0);
7324
7325         gen6_gt_force_wake_put(dev_priv);
7326         mutex_unlock(&dev_priv->dev->struct_mutex);
7327 }
7328
7329 static void ironlake_init_clock_gating(struct drm_device *dev)
7330 {
7331         struct drm_i915_private *dev_priv = dev->dev_private;
7332         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7333
7334         /* Required for FBC */
7335         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7336                 DPFCRUNIT_CLOCK_GATE_DISABLE |
7337                 DPFDUNIT_CLOCK_GATE_DISABLE;
7338         /* Required for CxSR */
7339         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7340
7341         I915_WRITE(PCH_3DCGDIS0,
7342                    MARIUNIT_CLOCK_GATE_DISABLE |
7343                    SVSMUNIT_CLOCK_GATE_DISABLE);
7344         I915_WRITE(PCH_3DCGDIS1,
7345                    VFMUNIT_CLOCK_GATE_DISABLE);
7346
7347         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7348
7349         /*
7350          * According to the spec the following bits should be set in
7351          * order to enable memory self-refresh
7352          * The bit 22/21 of 0x42004
7353          * The bit 5 of 0x42020
7354          * The bit 15 of 0x45000
7355          */
7356         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7357                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
7358                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7359         I915_WRITE(ILK_DSPCLK_GATE,
7360                    (I915_READ(ILK_DSPCLK_GATE) |
7361                     ILK_DPARB_CLK_GATE));
7362         I915_WRITE(DISP_ARB_CTL,
7363                    (I915_READ(DISP_ARB_CTL) |
7364                     DISP_FBC_WM_DIS));
7365         I915_WRITE(WM3_LP_ILK, 0);
7366         I915_WRITE(WM2_LP_ILK, 0);
7367         I915_WRITE(WM1_LP_ILK, 0);
7368
7369         /*
7370          * Based on the document from hardware guys the following bits
7371          * should be set unconditionally in order to enable FBC.
7372          * The bit 22 of 0x42000
7373          * The bit 22 of 0x42004
7374          * The bit 7,8,9 of 0x42020.
7375          */
7376         if (IS_IRONLAKE_M(dev)) {
7377                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7378                            I915_READ(ILK_DISPLAY_CHICKEN1) |
7379                            ILK_FBCQ_DIS);
7380                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7381                            I915_READ(ILK_DISPLAY_CHICKEN2) |
7382                            ILK_DPARB_GATE);
7383                 I915_WRITE(ILK_DSPCLK_GATE,
7384                            I915_READ(ILK_DSPCLK_GATE) |
7385                            ILK_DPFC_DIS1 |
7386                            ILK_DPFC_DIS2 |
7387                            ILK_CLK_FBC);
7388         }
7389
7390         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7391                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7392                    ILK_ELPIN_409_SELECT);
7393         I915_WRITE(_3D_CHICKEN2,
7394                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7395                    _3D_CHICKEN2_WM_READ_PIPELINED);
7396 }
7397
7398 static void gen6_init_clock_gating(struct drm_device *dev)
7399 {
7400         struct drm_i915_private *dev_priv = dev->dev_private;
7401         int pipe;
7402         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7403
7404         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7405
7406         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7407                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7408                    ILK_ELPIN_409_SELECT);
7409
7410         I915_WRITE(WM3_LP_ILK, 0);
7411         I915_WRITE(WM2_LP_ILK, 0);
7412         I915_WRITE(WM1_LP_ILK, 0);
7413
7414         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7415          * gating disable must be set.  Failure to set it results in
7416          * flickering pixels due to Z write ordering failures after
7417          * some amount of runtime in the Mesa "fire" demo, and Unigine
7418          * Sanctuary and Tropics, and apparently anything else with
7419          * alpha test or pixel discard.
7420          *
7421          * According to the spec, bit 11 (RCCUNIT) must also be set,
7422          * but we didn't debug actual testcases to find it out.
7423          */
7424         I915_WRITE(GEN6_UCGCTL2,
7425                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7426                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7427
7428         /*
7429          * According to the spec the following bits should be
7430          * set in order to enable memory self-refresh and fbc:
7431          * The bit21 and bit22 of 0x42000
7432          * The bit21 and bit22 of 0x42004
7433          * The bit5 and bit7 of 0x42020
7434          * The bit14 of 0x70180
7435          * The bit14 of 0x71180
7436          */
7437         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7438                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7439                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7440         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7441                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7442                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7443         I915_WRITE(ILK_DSPCLK_GATE,
7444                    I915_READ(ILK_DSPCLK_GATE) |
7445                    ILK_DPARB_CLK_GATE  |
7446                    ILK_DPFD_CLK_GATE);
7447
7448         for_each_pipe(pipe)
7449                 I915_WRITE(DSPCNTR(pipe),
7450                            I915_READ(DSPCNTR(pipe)) |
7451                            DISPPLANE_TRICKLE_FEED_DISABLE);
7452 }
7453
7454 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7455 {
7456         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7457
7458         reg &= ~GEN7_FF_SCHED_MASK;
7459         reg |= GEN7_FF_TS_SCHED_HW;
7460         reg |= GEN7_FF_VS_SCHED_HW;
7461         reg |= GEN7_FF_DS_SCHED_HW;
7462
7463         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7464 }
7465
7466 static void ivybridge_init_clock_gating(struct drm_device *dev)
7467 {
7468         struct drm_i915_private *dev_priv = dev->dev_private;
7469         int pipe;
7470         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7471
7472         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7473
7474         I915_WRITE(WM3_LP_ILK, 0);
7475         I915_WRITE(WM2_LP_ILK, 0);
7476         I915_WRITE(WM1_LP_ILK, 0);
7477
7478         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7479          * This implements the WaDisableRCZUnitClockGating workaround.
7480          */
7481         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7482
7483         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7484
7485         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
7486         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7487                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7488
7489         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
7490         I915_WRITE(GEN7_L3CNTLREG1,
7491                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7492         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7493                         GEN7_WA_L3_CHICKEN_MODE);
7494
7495         /* This is required by WaCatErrorRejectionIssue */
7496         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7497                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7498                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7499
7500         for_each_pipe(pipe)
7501                 I915_WRITE(DSPCNTR(pipe),
7502                            I915_READ(DSPCNTR(pipe)) |
7503                            DISPPLANE_TRICKLE_FEED_DISABLE);
7504 }
7505
7506 static void g4x_init_clock_gating(struct drm_device *dev)
7507 {
7508         struct drm_i915_private *dev_priv = dev->dev_private;
7509         uint32_t dspclk_gate;
7510
7511         I915_WRITE(RENCLK_GATE_D1, 0);
7512         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7513                    GS_UNIT_CLOCK_GATE_DISABLE |
7514                    CL_UNIT_CLOCK_GATE_DISABLE);
7515         I915_WRITE(RAMCLK_GATE_D, 0);
7516         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7517                 OVRUNIT_CLOCK_GATE_DISABLE |
7518                 OVCUNIT_CLOCK_GATE_DISABLE;
7519         if (IS_GM45(dev))
7520                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7521         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7522 }
7523
7524 static void crestline_init_clock_gating(struct drm_device *dev)
7525 {
7526         struct drm_i915_private *dev_priv = dev->dev_private;
7527
7528         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7529         I915_WRITE(RENCLK_GATE_D2, 0);
7530         I915_WRITE(DSPCLK_GATE_D, 0);
7531         I915_WRITE(RAMCLK_GATE_D, 0);
7532         I915_WRITE16(DEUC, 0);
7533 }
7534
7535 static void broadwater_init_clock_gating(struct drm_device *dev)
7536 {
7537         struct drm_i915_private *dev_priv = dev->dev_private;
7538
7539         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7540                    I965_RCC_CLOCK_GATE_DISABLE |
7541                    I965_RCPB_CLOCK_GATE_DISABLE |
7542                    I965_ISC_CLOCK_GATE_DISABLE |
7543                    I965_FBC_CLOCK_GATE_DISABLE);
7544         I915_WRITE(RENCLK_GATE_D2, 0);
7545 }
7546
7547 static void gen3_init_clock_gating(struct drm_device *dev)
7548 {
7549         struct drm_i915_private *dev_priv = dev->dev_private;
7550         u32 dstate = I915_READ(D_STATE);
7551
7552         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7553                 DSTATE_DOT_CLOCK_GATING;
7554         I915_WRITE(D_STATE, dstate);
7555 }
7556
7557 static void i85x_init_clock_gating(struct drm_device *dev)
7558 {
7559         struct drm_i915_private *dev_priv = dev->dev_private;
7560
7561         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7562 }
7563
7564 static void i830_init_clock_gating(struct drm_device *dev)
7565 {
7566         struct drm_i915_private *dev_priv = dev->dev_private;
7567
7568         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7569 }
7570
7571 static void ibx_init_clock_gating(struct drm_device *dev)
7572 {
7573         struct drm_i915_private *dev_priv = dev->dev_private;
7574
7575         /*
7576          * On Ibex Peak and Cougar Point, we need to disable clock
7577          * gating for the panel power sequencer or it will fail to
7578          * start up when no ports are active.
7579          */
7580         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7581 }
7582
7583 static void cpt_init_clock_gating(struct drm_device *dev)
7584 {
7585         struct drm_i915_private *dev_priv = dev->dev_private;
7586
7587         /*
7588          * On Ibex Peak and Cougar Point, we need to disable clock
7589          * gating for the panel power sequencer or it will fail to
7590          * start up when no ports are active.
7591          */
7592         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7593         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7594                    DPLS_EDP_PPS_FIX_DIS);
7595 }
7596
7597 static void ironlake_teardown_rc6(struct drm_device *dev)
7598 {
7599         struct drm_i915_private *dev_priv = dev->dev_private;
7600
7601         if (dev_priv->renderctx) {
7602                 i915_gem_object_unpin(dev_priv->renderctx);
7603                 drm_gem_object_unreference(&dev_priv->renderctx->base);
7604                 dev_priv->renderctx = NULL;
7605         }
7606
7607         if (dev_priv->pwrctx) {
7608                 i915_gem_object_unpin(dev_priv->pwrctx);
7609                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7610                 dev_priv->pwrctx = NULL;
7611         }
7612
7613         gen7_setup_fixed_func_scheduler(dev_priv);
7614 }
7615
7616 static void ironlake_disable_rc6(struct drm_device *dev)
7617 {
7618         struct drm_i915_private *dev_priv = dev->dev_private;
7619
7620         if (I915_READ(PWRCTXA)) {
7621                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7622                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7623                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7624                          50);
7625
7626                 I915_WRITE(PWRCTXA, 0);
7627                 POSTING_READ(PWRCTXA);
7628
7629                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7630                 POSTING_READ(RSTDBYCTL);
7631         }
7632
7633         ironlake_teardown_rc6(dev);
7634 }
7635
7636 static int ironlake_setup_rc6(struct drm_device *dev)
7637 {
7638         struct drm_i915_private *dev_priv = dev->dev_private;
7639
7640         if (dev_priv->renderctx == NULL)
7641                 dev_priv->renderctx = intel_alloc_context_page(dev);
7642         if (!dev_priv->renderctx)
7643                 return -ENOMEM;
7644
7645         if (dev_priv->pwrctx == NULL)
7646                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7647         if (!dev_priv->pwrctx) {
7648                 ironlake_teardown_rc6(dev);
7649                 return -ENOMEM;
7650         }
7651
7652         return 0;
7653 }
7654
7655 void ironlake_enable_rc6(struct drm_device *dev)
7656 {
7657         struct drm_i915_private *dev_priv = dev->dev_private;
7658         int ret;
7659
7660         /* rc6 disabled by default due to repeated reports of hanging during
7661          * boot and resume.
7662          */
7663         if (!i915_enable_rc6)
7664                 return;
7665
7666         mutex_lock(&dev->struct_mutex);
7667         ret = ironlake_setup_rc6(dev);
7668         if (ret) {
7669                 mutex_unlock(&dev->struct_mutex);
7670                 return;
7671         }
7672
7673         /*
7674          * GPU can automatically power down the render unit if given a page
7675          * to save state.
7676          */
7677         ret = BEGIN_LP_RING(6);
7678         if (ret) {
7679                 ironlake_teardown_rc6(dev);
7680                 mutex_unlock(&dev->struct_mutex);
7681                 return;
7682         }
7683
7684         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7685         OUT_RING(MI_SET_CONTEXT);
7686         OUT_RING(dev_priv->renderctx->gtt_offset |
7687                  MI_MM_SPACE_GTT |
7688                  MI_SAVE_EXT_STATE_EN |
7689                  MI_RESTORE_EXT_STATE_EN |
7690                  MI_RESTORE_INHIBIT);
7691         OUT_RING(MI_SUSPEND_FLUSH);
7692         OUT_RING(MI_NOOP);
7693         OUT_RING(MI_FLUSH);
7694         ADVANCE_LP_RING();
7695
7696         /*
7697          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7698          * does an implicit flush, combined with MI_FLUSH above, it should be
7699          * safe to assume that renderctx is valid
7700          */
7701         ret = intel_wait_ring_idle(LP_RING(dev_priv));
7702         if (ret) {
7703                 DRM_ERROR("failed to enable ironlake power power savings\n");
7704                 ironlake_teardown_rc6(dev);
7705                 mutex_unlock(&dev->struct_mutex);
7706                 return;
7707         }
7708
7709         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7710         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7711         mutex_unlock(&dev->struct_mutex);
7712 }
7713
7714 void intel_init_clock_gating(struct drm_device *dev)
7715 {
7716         struct drm_i915_private *dev_priv = dev->dev_private;
7717
7718         dev_priv->display.init_clock_gating(dev);
7719
7720         if (dev_priv->display.init_pch_clock_gating)
7721                 dev_priv->display.init_pch_clock_gating(dev);
7722 }
7723
7724 /* Set up chip specific display functions */
7725 static void intel_init_display(struct drm_device *dev)
7726 {
7727         struct drm_i915_private *dev_priv = dev->dev_private;
7728
7729         /* We always want a DPMS function */
7730         if (HAS_PCH_SPLIT(dev)) {
7731                 dev_priv->display.dpms = ironlake_crtc_dpms;
7732                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7733         } else {
7734                 dev_priv->display.dpms = i9xx_crtc_dpms;
7735                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7736         }
7737
7738         if (I915_HAS_FBC(dev)) {
7739                 if (HAS_PCH_SPLIT(dev)) {
7740                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7741                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
7742                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
7743                 } else if (IS_GM45(dev)) {
7744                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7745                         dev_priv->display.enable_fbc = g4x_enable_fbc;
7746                         dev_priv->display.disable_fbc = g4x_disable_fbc;
7747                 } else if (IS_CRESTLINE(dev)) {
7748                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7749                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
7750                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
7751                 }
7752                 /* 855GM needs testing */
7753         }
7754
7755         /* Returns the core display clock speed */
7756         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7757                 dev_priv->display.get_display_clock_speed =
7758                         i945_get_display_clock_speed;
7759         else if (IS_I915G(dev))
7760                 dev_priv->display.get_display_clock_speed =
7761                         i915_get_display_clock_speed;
7762         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7763                 dev_priv->display.get_display_clock_speed =
7764                         i9xx_misc_get_display_clock_speed;
7765         else if (IS_I915GM(dev))
7766                 dev_priv->display.get_display_clock_speed =
7767                         i915gm_get_display_clock_speed;
7768         else if (IS_I865G(dev))
7769                 dev_priv->display.get_display_clock_speed =
7770                         i865_get_display_clock_speed;
7771         else if (IS_I85X(dev))
7772                 dev_priv->display.get_display_clock_speed =
7773                         i855_get_display_clock_speed;
7774         else /* 852, 830 */
7775                 dev_priv->display.get_display_clock_speed =
7776                         i830_get_display_clock_speed;
7777
7778         /* For FIFO watermark updates */
7779         if (HAS_PCH_SPLIT(dev)) {
7780                 if (HAS_PCH_IBX(dev))
7781                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7782                 else if (HAS_PCH_CPT(dev))
7783                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7784
7785                 if (IS_GEN5(dev)) {
7786                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7787                                 dev_priv->display.update_wm = ironlake_update_wm;
7788                         else {
7789                                 DRM_DEBUG_KMS("Failed to get proper latency. "
7790                                               "Disable CxSR\n");
7791                                 dev_priv->display.update_wm = NULL;
7792                         }
7793                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7794                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7795                 } else if (IS_GEN6(dev)) {
7796                         if (SNB_READ_WM0_LATENCY()) {
7797                                 dev_priv->display.update_wm = sandybridge_update_wm;
7798                         } else {
7799                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7800                                               "Disable CxSR\n");
7801                                 dev_priv->display.update_wm = NULL;
7802                         }
7803                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7804                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7805                 } else if (IS_IVYBRIDGE(dev)) {
7806                         /* FIXME: detect B0+ stepping and use auto training */
7807                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7808                         if (SNB_READ_WM0_LATENCY()) {
7809                                 dev_priv->display.update_wm = sandybridge_update_wm;
7810                         } else {
7811                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7812                                               "Disable CxSR\n");
7813                                 dev_priv->display.update_wm = NULL;
7814                         }
7815                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7816
7817                 } else
7818                         dev_priv->display.update_wm = NULL;
7819         } else if (IS_PINEVIEW(dev)) {
7820                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7821                                             dev_priv->is_ddr3,
7822                                             dev_priv->fsb_freq,
7823                                             dev_priv->mem_freq)) {
7824                         DRM_INFO("failed to find known CxSR latency "
7825                                  "(found ddr%s fsb freq %d, mem freq %d), "
7826                                  "disabling CxSR\n",
7827                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
7828                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7829                         /* Disable CxSR and never update its watermark again */
7830                         pineview_disable_cxsr(dev);
7831                         dev_priv->display.update_wm = NULL;
7832                 } else
7833                         dev_priv->display.update_wm = pineview_update_wm;
7834                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7835         } else if (IS_G4X(dev)) {
7836                 dev_priv->display.update_wm = g4x_update_wm;
7837                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7838         } else if (IS_GEN4(dev)) {
7839                 dev_priv->display.update_wm = i965_update_wm;
7840                 if (IS_CRESTLINE(dev))
7841                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7842                 else if (IS_BROADWATER(dev))
7843                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7844         } else if (IS_GEN3(dev)) {
7845                 dev_priv->display.update_wm = i9xx_update_wm;
7846                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7847                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7848         } else if (IS_I865G(dev)) {
7849                 dev_priv->display.update_wm = i830_update_wm;
7850                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7851                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7852         } else if (IS_I85X(dev)) {
7853                 dev_priv->display.update_wm = i9xx_update_wm;
7854                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7855                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7856         } else {
7857                 dev_priv->display.update_wm = i830_update_wm;
7858                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7859                 if (IS_845G(dev))
7860                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7861                 else
7862                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7863         }
7864
7865         /* Default just returns -ENODEV to indicate unsupported */
7866         dev_priv->display.queue_flip = intel_default_queue_flip;
7867
7868         switch (INTEL_INFO(dev)->gen) {
7869         case 2:
7870                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7871                 break;
7872
7873         case 3:
7874                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7875                 break;
7876
7877         case 4:
7878         case 5:
7879                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7880                 break;
7881
7882         case 6:
7883                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7884                 break;
7885         case 7:
7886                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7887                 break;
7888         }
7889 }
7890
7891 /*
7892  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7893  * resume, or other times.  This quirk makes sure that's the case for
7894  * affected systems.
7895  */
7896 static void quirk_pipea_force (struct drm_device *dev)
7897 {
7898         struct drm_i915_private *dev_priv = dev->dev_private;
7899
7900         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7901         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7902 }
7903
7904 /*
7905  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7906  */
7907 static void quirk_ssc_force_disable(struct drm_device *dev)
7908 {
7909         struct drm_i915_private *dev_priv = dev->dev_private;
7910         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7911 }
7912
7913 struct intel_quirk {
7914         int device;
7915         int subsystem_vendor;
7916         int subsystem_device;
7917         void (*hook)(struct drm_device *dev);
7918 };
7919
7920 struct intel_quirk intel_quirks[] = {
7921         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7922         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7923         /* HP Mini needs pipe A force quirk (LP: #322104) */
7924         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7925
7926         /* Thinkpad R31 needs pipe A force quirk */
7927         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7928         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7929         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7930
7931         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7932         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
7933         /* ThinkPad X40 needs pipe A force quirk */
7934
7935         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7936         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7937
7938         /* 855 & before need to leave pipe A & dpll A up */
7939         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7940         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7941
7942         /* Lenovo U160 cannot use SSC on LVDS */
7943         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7944 };
7945
7946 static void intel_init_quirks(struct drm_device *dev)
7947 {
7948         struct pci_dev *d = dev->pdev;
7949         int i;
7950
7951         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7952                 struct intel_quirk *q = &intel_quirks[i];
7953
7954                 if (d->device == q->device &&
7955                     (d->subsystem_vendor == q->subsystem_vendor ||
7956                      q->subsystem_vendor == PCI_ANY_ID) &&
7957                     (d->subsystem_device == q->subsystem_device ||
7958                      q->subsystem_device == PCI_ANY_ID))
7959                         q->hook(dev);
7960         }
7961 }
7962
7963 /* Disable the VGA plane that we never use */
7964 static void i915_disable_vga(struct drm_device *dev)
7965 {
7966         struct drm_i915_private *dev_priv = dev->dev_private;
7967         u8 sr1;
7968         u32 vga_reg;
7969
7970         if (HAS_PCH_SPLIT(dev))
7971                 vga_reg = CPU_VGACNTRL;
7972         else
7973                 vga_reg = VGACNTRL;
7974
7975         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7976         outb(1, VGA_SR_INDEX);
7977         sr1 = inb(VGA_SR_DATA);
7978         outb(sr1 | 1<<5, VGA_SR_DATA);
7979         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7980         udelay(300);
7981
7982         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7983         POSTING_READ(vga_reg);
7984 }
7985
7986 void intel_modeset_init(struct drm_device *dev)
7987 {
7988         struct drm_i915_private *dev_priv = dev->dev_private;
7989         int i;
7990
7991         drm_mode_config_init(dev);
7992
7993         dev->mode_config.min_width = 0;
7994         dev->mode_config.min_height = 0;
7995
7996         dev->mode_config.funcs = (void *)&intel_mode_funcs;
7997
7998         intel_init_quirks(dev);
7999
8000         intel_init_display(dev);
8001
8002         if (IS_GEN2(dev)) {
8003                 dev->mode_config.max_width = 2048;
8004                 dev->mode_config.max_height = 2048;
8005         } else if (IS_GEN3(dev)) {
8006                 dev->mode_config.max_width = 4096;
8007                 dev->mode_config.max_height = 4096;
8008         } else {
8009                 dev->mode_config.max_width = 8192;
8010                 dev->mode_config.max_height = 8192;
8011         }
8012         dev->mode_config.fb_base = dev->agp->base;
8013
8014         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8015                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8016
8017         for (i = 0; i < dev_priv->num_pipe; i++) {
8018                 intel_crtc_init(dev, i);
8019         }
8020
8021         /* Just disable it once at startup */
8022         i915_disable_vga(dev);
8023         intel_setup_outputs(dev);
8024
8025         intel_init_clock_gating(dev);
8026
8027         if (IS_IRONLAKE_M(dev)) {
8028                 ironlake_enable_drps(dev);
8029                 intel_init_emon(dev);
8030         }
8031
8032         if (IS_GEN6(dev) || IS_GEN7(dev))
8033                 gen6_enable_rps(dev_priv);
8034
8035         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8036         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8037                     (unsigned long)dev);
8038 }
8039
8040 void intel_modeset_gem_init(struct drm_device *dev)
8041 {
8042         if (IS_IRONLAKE_M(dev))
8043                 ironlake_enable_rc6(dev);
8044
8045         intel_setup_overlay(dev);
8046 }
8047
8048 void intel_modeset_cleanup(struct drm_device *dev)
8049 {
8050         struct drm_i915_private *dev_priv = dev->dev_private;
8051         struct drm_crtc *crtc;
8052         struct intel_crtc *intel_crtc;
8053
8054         drm_kms_helper_poll_fini(dev);
8055         mutex_lock(&dev->struct_mutex);
8056
8057         intel_unregister_dsm_handler();
8058
8059
8060         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8061                 /* Skip inactive CRTCs */
8062                 if (!crtc->fb)
8063                         continue;
8064
8065                 intel_crtc = to_intel_crtc(crtc);
8066                 intel_increase_pllclock(crtc);
8067         }
8068
8069         if (dev_priv->display.disable_fbc)
8070                 dev_priv->display.disable_fbc(dev);
8071
8072         if (IS_IRONLAKE_M(dev))
8073                 ironlake_disable_drps(dev);
8074         if (IS_GEN6(dev) || IS_GEN7(dev))
8075                 gen6_disable_rps(dev);
8076
8077         if (IS_IRONLAKE_M(dev))
8078                 ironlake_disable_rc6(dev);
8079
8080         mutex_unlock(&dev->struct_mutex);
8081
8082         /* Disable the irq before mode object teardown, for the irq might
8083          * enqueue unpin/hotplug work. */
8084         drm_irq_uninstall(dev);
8085         cancel_work_sync(&dev_priv->hotplug_work);
8086
8087         /* Shut off idle work before the crtcs get freed. */
8088         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8089                 intel_crtc = to_intel_crtc(crtc);
8090                 del_timer_sync(&intel_crtc->idle_timer);
8091         }
8092         del_timer_sync(&dev_priv->idle_timer);
8093         cancel_work_sync(&dev_priv->idle_work);
8094
8095         drm_mode_config_cleanup(dev);
8096 }
8097
8098 /*
8099  * Return which encoder is currently attached for connector.
8100  */
8101 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8102 {
8103         return &intel_attached_encoder(connector)->base;
8104 }
8105
8106 void intel_connector_attach_encoder(struct intel_connector *connector,
8107                                     struct intel_encoder *encoder)
8108 {
8109         connector->encoder = encoder;
8110         drm_mode_connector_attach_encoder(&connector->base,
8111                                           &encoder->base);
8112 }
8113
8114 /*
8115  * set vga decode state - true == enable VGA decode
8116  */
8117 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8118 {
8119         struct drm_i915_private *dev_priv = dev->dev_private;
8120         u16 gmch_ctrl;
8121
8122         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8123         if (state)
8124                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8125         else
8126                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8127         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8128         return 0;
8129 }
8130
8131 #ifdef CONFIG_DEBUG_FS
8132 #include <linux/seq_file.h>
8133
8134 struct intel_display_error_state {
8135         struct intel_cursor_error_state {
8136                 u32 control;
8137                 u32 position;
8138                 u32 base;
8139                 u32 size;
8140         } cursor[2];
8141
8142         struct intel_pipe_error_state {
8143                 u32 conf;
8144                 u32 source;
8145
8146                 u32 htotal;
8147                 u32 hblank;
8148                 u32 hsync;
8149                 u32 vtotal;
8150                 u32 vblank;
8151                 u32 vsync;
8152         } pipe[2];
8153
8154         struct intel_plane_error_state {
8155                 u32 control;
8156                 u32 stride;
8157                 u32 size;
8158                 u32 pos;
8159                 u32 addr;
8160                 u32 surface;
8161                 u32 tile_offset;
8162         } plane[2];
8163 };
8164
8165 struct intel_display_error_state *
8166 intel_display_capture_error_state(struct drm_device *dev)
8167 {
8168         drm_i915_private_t *dev_priv = dev->dev_private;
8169         struct intel_display_error_state *error;
8170         int i;
8171
8172         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8173         if (error == NULL)
8174                 return NULL;
8175
8176         for (i = 0; i < 2; i++) {
8177                 error->cursor[i].control = I915_READ(CURCNTR(i));
8178                 error->cursor[i].position = I915_READ(CURPOS(i));
8179                 error->cursor[i].base = I915_READ(CURBASE(i));
8180
8181                 error->plane[i].control = I915_READ(DSPCNTR(i));
8182                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8183                 error->plane[i].size = I915_READ(DSPSIZE(i));
8184                 error->plane[i].pos= I915_READ(DSPPOS(i));
8185                 error->plane[i].addr = I915_READ(DSPADDR(i));
8186                 if (INTEL_INFO(dev)->gen >= 4) {
8187                         error->plane[i].surface = I915_READ(DSPSURF(i));
8188                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8189                 }
8190
8191                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8192                 error->pipe[i].source = I915_READ(PIPESRC(i));
8193                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8194                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8195                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8196                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8197                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8198                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8199         }
8200
8201         return error;
8202 }
8203
8204 void
8205 intel_display_print_error_state(struct seq_file *m,
8206                                 struct drm_device *dev,
8207                                 struct intel_display_error_state *error)
8208 {
8209         int i;
8210
8211         for (i = 0; i < 2; i++) {
8212                 seq_printf(m, "Pipe [%d]:\n", i);
8213                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8214                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8215                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8216                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8217                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8218                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8219                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8220                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8221
8222                 seq_printf(m, "Plane [%d]:\n", i);
8223                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8224                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8225                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8226                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8227                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8228                 if (INTEL_INFO(dev)->gen >= 4) {
8229                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8230                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8231                 }
8232
8233                 seq_printf(m, "Cursor [%d]:\n", i);
8234                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8235                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8236                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8237         }
8238 }
8239 #endif