2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
65 typedef struct intel_limit intel_limit_t;
67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
72 intel_pch_rawclk(struct drm_device *dev)
74 struct drm_i915_private *dev_priv = dev->dev_private;
76 WARN_ON(!HAS_PCH_SPLIT(dev));
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
81 static inline u32 /* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device *dev)
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac = {
92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds = {
118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo = {
131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds = {
144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo = {
158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi = {
173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
213 static const intel_limit_t intel_limits_pineview_sdvo = {
214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
228 static const intel_limit_t intel_limits_pineview_lvds = {
229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac = {
247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
307 .p1 = { .min = 2, .max = 6 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
312 static const intel_limit_t intel_limits_vlv = {
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
320 .vco = { .min = 4000000, .max = 6000000 },
321 .n = { .min = 1, .max = 7 },
322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
324 .p1 = { .min = 2, .max = 3 },
325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
328 static void vlv_clock(int refclk, intel_clock_t *clock)
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
332 clock->vco = refclk * clock->m / clock->n;
333 clock->dot = clock->vco / clock->p;
337 * Returns whether any output on the specified pipe is of the specified type
339 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
341 struct drm_device *dev = crtc->dev;
342 struct intel_encoder *encoder;
344 for_each_encoder_on_crtc(dev, crtc, encoder)
345 if (encoder->type == type)
351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 struct drm_device *dev = crtc->dev;
355 const intel_limit_t *limit;
357 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
358 if (intel_is_dual_link_lvds(dev)) {
359 if (refclk == 100000)
360 limit = &intel_limits_ironlake_dual_lvds_100m;
362 limit = &intel_limits_ironlake_dual_lvds;
364 if (refclk == 100000)
365 limit = &intel_limits_ironlake_single_lvds_100m;
367 limit = &intel_limits_ironlake_single_lvds;
370 limit = &intel_limits_ironlake_dac;
375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
377 struct drm_device *dev = crtc->dev;
378 const intel_limit_t *limit;
380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
381 if (intel_is_dual_link_lvds(dev))
382 limit = &intel_limits_g4x_dual_channel_lvds;
384 limit = &intel_limits_g4x_single_channel_lvds;
385 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
386 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
387 limit = &intel_limits_g4x_hdmi;
388 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
389 limit = &intel_limits_g4x_sdvo;
390 } else /* The option is for other outputs */
391 limit = &intel_limits_i9xx_sdvo;
396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
398 struct drm_device *dev = crtc->dev;
399 const intel_limit_t *limit;
401 if (HAS_PCH_SPLIT(dev))
402 limit = intel_ironlake_limit(crtc, refclk);
403 else if (IS_G4X(dev)) {
404 limit = intel_g4x_limit(crtc);
405 } else if (IS_PINEVIEW(dev)) {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_pineview_lvds;
409 limit = &intel_limits_pineview_sdvo;
410 } else if (IS_VALLEYVIEW(dev)) {
411 limit = &intel_limits_vlv;
412 } else if (!IS_GEN2(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
414 limit = &intel_limits_i9xx_lvds;
416 limit = &intel_limits_i9xx_sdvo;
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i8xx_lvds;
420 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
421 limit = &intel_limits_i8xx_dvo;
423 limit = &intel_limits_i8xx_dac;
428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
429 static void pineview_clock(int refclk, intel_clock_t *clock)
431 clock->m = clock->m2 + 2;
432 clock->p = clock->p1 * clock->p2;
433 clock->vco = refclk * clock->m / clock->n;
434 clock->dot = clock->vco / clock->p;
437 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
439 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
442 static void i9xx_clock(int refclk, intel_clock_t *clock)
444 clock->m = i9xx_dpll_compute_m(clock);
445 clock->p = clock->p1 * clock->p2;
446 clock->vco = refclk * clock->m / (clock->n + 2);
447 clock->dot = clock->vco / clock->p;
450 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
452 * Returns whether the given set of divisors are valid for a given refclk with
453 * the given connectors.
456 static bool intel_PLL_is_valid(struct drm_device *dev,
457 const intel_limit_t *limit,
458 const intel_clock_t *clock)
460 if (clock->n < limit->n.min || limit->n.max < clock->n)
461 INTELPllInvalid("n out of range\n");
462 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
463 INTELPllInvalid("p1 out of range\n");
464 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
465 INTELPllInvalid("m2 out of range\n");
466 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
467 INTELPllInvalid("m1 out of range\n");
469 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
470 if (clock->m1 <= clock->m2)
471 INTELPllInvalid("m1 <= m2\n");
473 if (!IS_VALLEYVIEW(dev)) {
474 if (clock->p < limit->p.min || limit->p.max < clock->p)
475 INTELPllInvalid("p out of range\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
481 INTELPllInvalid("vco out of range\n");
482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
486 INTELPllInvalid("dot out of range\n");
492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
496 struct drm_device *dev = crtc->dev;
500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
506 if (intel_is_dual_link_lvds(dev))
507 clock.p2 = limit->p2.p2_fast;
509 clock.p2 = limit->p2.p2_slow;
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
514 clock.p2 = limit->p2.p2_fast;
517 memset(best_clock, 0, sizeof(*best_clock));
519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
523 if (clock.m2 >= clock.m1)
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
536 clock.p != match_clock->p)
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
549 return (err != target);
553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
557 struct drm_device *dev = crtc->dev;
561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
567 if (intel_is_dual_link_lvds(dev))
568 clock.p2 = limit->p2.p2_fast;
570 clock.p2 = limit->p2.p2_slow;
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
575 clock.p2 = limit->p2.p2_fast;
578 memset(best_clock, 0, sizeof(*best_clock));
580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
590 pineview_clock(refclk, &clock);
591 if (!intel_PLL_is_valid(dev, limit,
595 clock.p != match_clock->p)
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
608 return (err != target);
612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
616 struct drm_device *dev = crtc->dev;
620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
625 if (intel_is_dual_link_lvds(dev))
626 clock.p2 = limit->p2.p2_fast;
628 clock.p2 = limit->p2.p2_slow;
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
633 clock.p2 = limit->p2.p2_fast;
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
638 /* based on hardware requirement, prefer smaller n to precision */
639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
640 /* based on hardware requirement, prefere larger m1,m2 */
641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
649 i9xx_clock(refclk, &clock);
650 if (!intel_PLL_is_valid(dev, limit,
654 this_err = abs(clock.dot - target);
655 if (this_err < err_most) {
669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
673 struct drm_device *dev = crtc->dev;
675 unsigned int bestppm = 1000000;
676 /* min update 19.2 MHz */
677 int max_n = min(limit->n.max, refclk / 19200);
680 target *= 5; /* fast clock */
682 memset(best_clock, 0, sizeof(*best_clock));
684 /* based on hardware requirement, prefer smaller n to precision */
685 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
686 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
687 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
688 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
689 clock.p = clock.p1 * clock.p2;
690 /* based on hardware requirement, prefer bigger m1,m2 values */
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
692 unsigned int ppm, diff;
694 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
697 vlv_clock(refclk, &clock);
699 if (!intel_PLL_is_valid(dev, limit,
703 diff = abs(clock.dot - target);
704 ppm = div_u64(1000000ULL * diff, target);
706 if (ppm < 100 && clock.p > best_clock->p) {
712 if (bestppm >= 10 && ppm < bestppm - 10) {
725 bool intel_crtc_active(struct drm_crtc *crtc)
727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
729 /* Be paranoid as we can arrive here with only partial
730 * state retrieved from the hardware during setup.
732 * We can ditch the adjusted_mode.crtc_clock check as soon
733 * as Haswell has gained clock readout/fastboot support.
735 * We can ditch the crtc->fb check as soon as we can
736 * properly reconstruct framebuffers.
738 return intel_crtc->active && crtc->fb &&
739 intel_crtc->config.adjusted_mode.crtc_clock;
742 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
745 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
748 return intel_crtc->config.cpu_transcoder;
751 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 u32 frame, frame_reg = PIPEFRAME(pipe);
756 frame = I915_READ(frame_reg);
758 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
759 DRM_DEBUG_KMS("vblank wait timed out\n");
763 * intel_wait_for_vblank - wait for vblank on a given pipe
765 * @pipe: pipe to wait for
767 * Wait for vblank to occur on a given pipe. Needed for various bits of
770 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
772 struct drm_i915_private *dev_priv = dev->dev_private;
773 int pipestat_reg = PIPESTAT(pipe);
775 if (INTEL_INFO(dev)->gen >= 5) {
776 ironlake_wait_for_vblank(dev, pipe);
780 /* Clear existing vblank status. Note this will clear any other
781 * sticky status fields as well.
783 * This races with i915_driver_irq_handler() with the result
784 * that either function could miss a vblank event. Here it is not
785 * fatal, as we will either wait upon the next vblank interrupt or
786 * timeout. Generally speaking intel_wait_for_vblank() is only
787 * called during modeset at which time the GPU should be idle and
788 * should *not* be performing page flips and thus not waiting on
790 * Currently, the result of us stealing a vblank from the irq
791 * handler is that a single frame will be skipped during swapbuffers.
793 I915_WRITE(pipestat_reg,
794 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
796 /* Wait for vblank interrupt bit to set */
797 if (wait_for(I915_READ(pipestat_reg) &
798 PIPE_VBLANK_INTERRUPT_STATUS,
800 DRM_DEBUG_KMS("vblank wait timed out\n");
804 * intel_wait_for_pipe_off - wait for pipe to turn off
806 * @pipe: pipe to wait for
808 * After disabling a pipe, we can't wait for vblank in the usual way,
809 * spinning on the vblank interrupt status bit, since we won't actually
810 * see an interrupt when the pipe is disabled.
813 * wait for the pipe register state bit to turn off
816 * wait for the display line value to settle (it usually
817 * ends up stopping at the start of the next frame).
820 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
822 struct drm_i915_private *dev_priv = dev->dev_private;
823 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
826 if (INTEL_INFO(dev)->gen >= 4) {
827 int reg = PIPECONF(cpu_transcoder);
829 /* Wait for the Pipe State to go off */
830 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
832 WARN(1, "pipe_off wait timed out\n");
834 u32 last_line, line_mask;
835 int reg = PIPEDSL(pipe);
836 unsigned long timeout = jiffies + msecs_to_jiffies(100);
839 line_mask = DSL_LINEMASK_GEN2;
841 line_mask = DSL_LINEMASK_GEN3;
843 /* Wait for the display line to settle */
845 last_line = I915_READ(reg) & line_mask;
847 } while (((I915_READ(reg) & line_mask) != last_line) &&
848 time_after(timeout, jiffies));
849 if (time_after(jiffies, timeout))
850 WARN(1, "pipe_off wait timed out\n");
855 * ibx_digital_port_connected - is the specified port connected?
856 * @dev_priv: i915 private structure
857 * @port: the port to test
859 * Returns true if @port is connected, false otherwise.
861 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
862 struct intel_digital_port *port)
866 if (HAS_PCH_IBX(dev_priv->dev)) {
869 bit = SDE_PORTB_HOTPLUG;
872 bit = SDE_PORTC_HOTPLUG;
875 bit = SDE_PORTD_HOTPLUG;
883 bit = SDE_PORTB_HOTPLUG_CPT;
886 bit = SDE_PORTC_HOTPLUG_CPT;
889 bit = SDE_PORTD_HOTPLUG_CPT;
896 return I915_READ(SDEISR) & bit;
899 static const char *state_string(bool enabled)
901 return enabled ? "on" : "off";
904 /* Only for pre-ILK configs */
905 void assert_pll(struct drm_i915_private *dev_priv,
906 enum pipe pipe, bool state)
913 val = I915_READ(reg);
914 cur_state = !!(val & DPLL_VCO_ENABLE);
915 WARN(cur_state != state,
916 "PLL state assertion failure (expected %s, current %s)\n",
917 state_string(state), state_string(cur_state));
920 /* XXX: the dsi pll is shared between MIPI DSI ports */
921 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
926 mutex_lock(&dev_priv->dpio_lock);
927 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
928 mutex_unlock(&dev_priv->dpio_lock);
930 cur_state = val & DSI_PLL_VCO_EN;
931 WARN(cur_state != state,
932 "DSI PLL state assertion failure (expected %s, current %s)\n",
933 state_string(state), state_string(cur_state));
935 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
936 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
938 struct intel_shared_dpll *
939 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
941 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
943 if (crtc->config.shared_dpll < 0)
946 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
950 void assert_shared_dpll(struct drm_i915_private *dev_priv,
951 struct intel_shared_dpll *pll,
955 struct intel_dpll_hw_state hw_state;
957 if (HAS_PCH_LPT(dev_priv->dev)) {
958 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
963 "asserting DPLL %s with no DPLL\n", state_string(state)))
966 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
967 WARN(cur_state != state,
968 "%s assertion failure (expected %s, current %s)\n",
969 pll->name, state_string(state), state_string(cur_state));
972 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
973 enum pipe pipe, bool state)
978 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
981 if (HAS_DDI(dev_priv->dev)) {
982 /* DDI does not have a specific FDI_TX register */
983 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
984 val = I915_READ(reg);
985 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
987 reg = FDI_TX_CTL(pipe);
988 val = I915_READ(reg);
989 cur_state = !!(val & FDI_TX_ENABLE);
991 WARN(cur_state != state,
992 "FDI TX state assertion failure (expected %s, current %s)\n",
993 state_string(state), state_string(cur_state));
995 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
996 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
998 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1005 reg = FDI_RX_CTL(pipe);
1006 val = I915_READ(reg);
1007 cur_state = !!(val & FDI_RX_ENABLE);
1008 WARN(cur_state != state,
1009 "FDI RX state assertion failure (expected %s, current %s)\n",
1010 state_string(state), state_string(cur_state));
1012 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1013 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1015 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1021 /* ILK FDI PLL is always enabled */
1022 if (dev_priv->info->gen == 5)
1025 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1026 if (HAS_DDI(dev_priv->dev))
1029 reg = FDI_TX_CTL(pipe);
1030 val = I915_READ(reg);
1031 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1034 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, bool state)
1041 reg = FDI_RX_CTL(pipe);
1042 val = I915_READ(reg);
1043 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1044 WARN(cur_state != state,
1045 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1046 state_string(state), state_string(cur_state));
1049 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1052 int pp_reg, lvds_reg;
1054 enum pipe panel_pipe = PIPE_A;
1057 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1058 pp_reg = PCH_PP_CONTROL;
1059 lvds_reg = PCH_LVDS;
1061 pp_reg = PP_CONTROL;
1065 val = I915_READ(pp_reg);
1066 if (!(val & PANEL_POWER_ON) ||
1067 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1070 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1071 panel_pipe = PIPE_B;
1073 WARN(panel_pipe == pipe && locked,
1074 "panel assertion failure, pipe %c regs locked\n",
1078 static void assert_cursor(struct drm_i915_private *dev_priv,
1079 enum pipe pipe, bool state)
1081 struct drm_device *dev = dev_priv->dev;
1084 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1085 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1086 else if (IS_845G(dev) || IS_I865G(dev))
1087 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1089 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1091 WARN(cur_state != state,
1092 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1093 pipe_name(pipe), state_string(state), state_string(cur_state));
1095 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1096 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1098 void assert_pipe(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, bool state)
1104 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107 /* if we need the pipe A quirk it must be always on */
1108 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111 if (!intel_display_power_enabled(dev_priv->dev,
1112 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1115 reg = PIPECONF(cpu_transcoder);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & PIPECONF_ENABLE);
1120 WARN(cur_state != state,
1121 "pipe %c assertion failure (expected %s, current %s)\n",
1122 pipe_name(pipe), state_string(state), state_string(cur_state));
1125 static void assert_plane(struct drm_i915_private *dev_priv,
1126 enum plane plane, bool state)
1132 reg = DSPCNTR(plane);
1133 val = I915_READ(reg);
1134 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1135 WARN(cur_state != state,
1136 "plane %c assertion failure (expected %s, current %s)\n",
1137 plane_name(plane), state_string(state), state_string(cur_state));
1140 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1141 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1143 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146 struct drm_device *dev = dev_priv->dev;
1151 /* Primary planes are fixed to pipes on gen4+ */
1152 if (INTEL_INFO(dev)->gen >= 4) {
1153 reg = DSPCNTR(pipe);
1154 val = I915_READ(reg);
1155 WARN((val & DISPLAY_PLANE_ENABLE),
1156 "plane %c assertion failure, should be disabled but not\n",
1161 /* Need to check both planes against the pipe */
1164 val = I915_READ(reg);
1165 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1166 DISPPLANE_SEL_PIPE_SHIFT;
1167 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1168 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1169 plane_name(i), pipe_name(pipe));
1173 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1176 struct drm_device *dev = dev_priv->dev;
1180 if (IS_VALLEYVIEW(dev)) {
1181 for (i = 0; i < dev_priv->num_plane; i++) {
1182 reg = SPCNTR(pipe, i);
1183 val = I915_READ(reg);
1184 WARN((val & SP_ENABLE),
1185 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1186 sprite_name(pipe, i), pipe_name(pipe));
1188 } else if (INTEL_INFO(dev)->gen >= 7) {
1190 val = I915_READ(reg);
1191 WARN((val & SPRITE_ENABLE),
1192 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1193 plane_name(pipe), pipe_name(pipe));
1194 } else if (INTEL_INFO(dev)->gen >= 5) {
1195 reg = DVSCNTR(pipe);
1196 val = I915_READ(reg);
1197 WARN((val & DVS_ENABLE),
1198 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1199 plane_name(pipe), pipe_name(pipe));
1203 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1208 if (HAS_PCH_LPT(dev_priv->dev)) {
1209 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1213 val = I915_READ(PCH_DREF_CONTROL);
1214 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1215 DREF_SUPERSPREAD_SOURCE_MASK));
1216 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1219 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1226 reg = PCH_TRANSCONF(pipe);
1227 val = I915_READ(reg);
1228 enabled = !!(val & TRANS_ENABLE);
1230 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1234 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1235 enum pipe pipe, u32 port_sel, u32 val)
1237 if ((val & DP_PORT_EN) == 0)
1240 if (HAS_PCH_CPT(dev_priv->dev)) {
1241 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1242 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1243 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1246 if ((val & DP_PIPE_MASK) != (pipe << 30))
1252 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1253 enum pipe pipe, u32 val)
1255 if ((val & SDVO_ENABLE) == 0)
1258 if (HAS_PCH_CPT(dev_priv->dev)) {
1259 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1262 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1268 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1269 enum pipe pipe, u32 val)
1271 if ((val & LVDS_PORT_EN) == 0)
1274 if (HAS_PCH_CPT(dev_priv->dev)) {
1275 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1278 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1284 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1285 enum pipe pipe, u32 val)
1287 if ((val & ADPA_DAC_ENABLE) == 0)
1289 if (HAS_PCH_CPT(dev_priv->dev)) {
1290 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1293 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1299 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1300 enum pipe pipe, int reg, u32 port_sel)
1302 u32 val = I915_READ(reg);
1303 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1304 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1305 reg, pipe_name(pipe));
1307 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1308 && (val & DP_PIPEB_SELECT),
1309 "IBX PCH dp port still using transcoder B\n");
1312 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1313 enum pipe pipe, int reg)
1315 u32 val = I915_READ(reg);
1316 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1317 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1318 reg, pipe_name(pipe));
1320 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1321 && (val & SDVO_PIPE_B_SELECT),
1322 "IBX PCH hdmi port still using transcoder B\n");
1325 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1331 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1332 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1333 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1336 val = I915_READ(reg);
1337 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1338 "PCH VGA enabled on transcoder %c, should be disabled\n",
1342 val = I915_READ(reg);
1343 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1344 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1347 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1348 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1349 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1352 static void intel_init_dpio(struct drm_device *dev)
1354 struct drm_i915_private *dev_priv = dev->dev_private;
1356 if (!IS_VALLEYVIEW(dev))
1360 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1361 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1362 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1363 * b. The other bits such as sfr settings / modesel may all be set
1366 * This should only be done on init and resume from S3 with both
1367 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1369 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1372 static void vlv_enable_pll(struct intel_crtc *crtc)
1374 struct drm_device *dev = crtc->base.dev;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int reg = DPLL(crtc->pipe);
1377 u32 dpll = crtc->config.dpll_hw_state.dpll;
1379 assert_pipe_disabled(dev_priv, crtc->pipe);
1381 /* No really, not for ILK+ */
1382 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1384 /* PLL is protected by panel, make sure we can write it */
1385 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1386 assert_panel_unlocked(dev_priv, crtc->pipe);
1388 I915_WRITE(reg, dpll);
1392 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1393 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1395 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1396 POSTING_READ(DPLL_MD(crtc->pipe));
1398 /* We do this three times for luck */
1399 I915_WRITE(reg, dpll);
1401 udelay(150); /* wait for warmup */
1402 I915_WRITE(reg, dpll);
1404 udelay(150); /* wait for warmup */
1405 I915_WRITE(reg, dpll);
1407 udelay(150); /* wait for warmup */
1410 static void i9xx_enable_pll(struct intel_crtc *crtc)
1412 struct drm_device *dev = crtc->base.dev;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 int reg = DPLL(crtc->pipe);
1415 u32 dpll = crtc->config.dpll_hw_state.dpll;
1417 assert_pipe_disabled(dev_priv, crtc->pipe);
1419 /* No really, not for ILK+ */
1420 BUG_ON(dev_priv->info->gen >= 5);
1422 /* PLL is protected by panel, make sure we can write it */
1423 if (IS_MOBILE(dev) && !IS_I830(dev))
1424 assert_panel_unlocked(dev_priv, crtc->pipe);
1426 I915_WRITE(reg, dpll);
1428 /* Wait for the clocks to stabilize. */
1432 if (INTEL_INFO(dev)->gen >= 4) {
1433 I915_WRITE(DPLL_MD(crtc->pipe),
1434 crtc->config.dpll_hw_state.dpll_md);
1436 /* The pixel multiplier can only be updated once the
1437 * DPLL is enabled and the clocks are stable.
1439 * So write it again.
1441 I915_WRITE(reg, dpll);
1444 /* We do this three times for luck */
1445 I915_WRITE(reg, dpll);
1447 udelay(150); /* wait for warmup */
1448 I915_WRITE(reg, dpll);
1450 udelay(150); /* wait for warmup */
1451 I915_WRITE(reg, dpll);
1453 udelay(150); /* wait for warmup */
1457 * i9xx_disable_pll - disable a PLL
1458 * @dev_priv: i915 private structure
1459 * @pipe: pipe PLL to disable
1461 * Disable the PLL for @pipe, making sure the pipe is off first.
1463 * Note! This is for pre-ILK only.
1465 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1467 /* Don't disable pipe A or pipe A PLLs if needed */
1468 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1471 /* Make sure the pipe isn't still relying on us */
1472 assert_pipe_disabled(dev_priv, pipe);
1474 I915_WRITE(DPLL(pipe), 0);
1475 POSTING_READ(DPLL(pipe));
1478 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1482 /* Make sure the pipe isn't still relying on us */
1483 assert_pipe_disabled(dev_priv, pipe);
1485 /* Leave integrated clock source enabled */
1487 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1488 I915_WRITE(DPLL(pipe), val);
1489 POSTING_READ(DPLL(pipe));
1492 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1497 port_mask = DPLL_PORTB_READY_MASK;
1499 port_mask = DPLL_PORTC_READY_MASK;
1501 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1502 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1503 'B' + port, I915_READ(DPLL(0)));
1507 * ironlake_enable_shared_dpll - enable PCH PLL
1508 * @dev_priv: i915 private structure
1509 * @pipe: pipe PLL to enable
1511 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1512 * drives the transcoder clock.
1514 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1516 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1517 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1519 /* PCH PLLs only available on ILK, SNB and IVB */
1520 BUG_ON(dev_priv->info->gen < 5);
1521 if (WARN_ON(pll == NULL))
1524 if (WARN_ON(pll->refcount == 0))
1527 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1528 pll->name, pll->active, pll->on,
1529 crtc->base.base.id);
1531 if (pll->active++) {
1533 assert_shared_dpll_enabled(dev_priv, pll);
1538 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1539 pll->enable(dev_priv, pll);
1543 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1545 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1546 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1548 /* PCH only available on ILK+ */
1549 BUG_ON(dev_priv->info->gen < 5);
1550 if (WARN_ON(pll == NULL))
1553 if (WARN_ON(pll->refcount == 0))
1556 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1557 pll->name, pll->active, pll->on,
1558 crtc->base.base.id);
1560 if (WARN_ON(pll->active == 0)) {
1561 assert_shared_dpll_disabled(dev_priv, pll);
1565 assert_shared_dpll_enabled(dev_priv, pll);
1570 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1571 pll->disable(dev_priv, pll);
1575 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1578 struct drm_device *dev = dev_priv->dev;
1579 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1581 uint32_t reg, val, pipeconf_val;
1583 /* PCH only available on ILK+ */
1584 BUG_ON(dev_priv->info->gen < 5);
1586 /* Make sure PCH DPLL is enabled */
1587 assert_shared_dpll_enabled(dev_priv,
1588 intel_crtc_to_shared_dpll(intel_crtc));
1590 /* FDI must be feeding us bits for PCH ports */
1591 assert_fdi_tx_enabled(dev_priv, pipe);
1592 assert_fdi_rx_enabled(dev_priv, pipe);
1594 if (HAS_PCH_CPT(dev)) {
1595 /* Workaround: Set the timing override bit before enabling the
1596 * pch transcoder. */
1597 reg = TRANS_CHICKEN2(pipe);
1598 val = I915_READ(reg);
1599 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1600 I915_WRITE(reg, val);
1603 reg = PCH_TRANSCONF(pipe);
1604 val = I915_READ(reg);
1605 pipeconf_val = I915_READ(PIPECONF(pipe));
1607 if (HAS_PCH_IBX(dev_priv->dev)) {
1609 * make the BPC in transcoder be consistent with
1610 * that in pipeconf reg.
1612 val &= ~PIPECONF_BPC_MASK;
1613 val |= pipeconf_val & PIPECONF_BPC_MASK;
1616 val &= ~TRANS_INTERLACE_MASK;
1617 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1618 if (HAS_PCH_IBX(dev_priv->dev) &&
1619 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1620 val |= TRANS_LEGACY_INTERLACED_ILK;
1622 val |= TRANS_INTERLACED;
1624 val |= TRANS_PROGRESSIVE;
1626 I915_WRITE(reg, val | TRANS_ENABLE);
1627 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1628 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1631 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1632 enum transcoder cpu_transcoder)
1634 u32 val, pipeconf_val;
1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
1639 /* FDI must be feeding us bits for PCH ports */
1640 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1641 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1643 /* Workaround: set timing override bit. */
1644 val = I915_READ(_TRANSA_CHICKEN2);
1645 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1646 I915_WRITE(_TRANSA_CHICKEN2, val);
1649 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1651 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1652 PIPECONF_INTERLACED_ILK)
1653 val |= TRANS_INTERLACED;
1655 val |= TRANS_PROGRESSIVE;
1657 I915_WRITE(LPT_TRANSCONF, val);
1658 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1659 DRM_ERROR("Failed to enable PCH transcoder\n");
1662 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1665 struct drm_device *dev = dev_priv->dev;
1668 /* FDI relies on the transcoder */
1669 assert_fdi_tx_disabled(dev_priv, pipe);
1670 assert_fdi_rx_disabled(dev_priv, pipe);
1672 /* Ports must be off as well */
1673 assert_pch_ports_disabled(dev_priv, pipe);
1675 reg = PCH_TRANSCONF(pipe);
1676 val = I915_READ(reg);
1677 val &= ~TRANS_ENABLE;
1678 I915_WRITE(reg, val);
1679 /* wait for PCH transcoder off, transcoder state */
1680 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1681 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1683 if (!HAS_PCH_IBX(dev)) {
1684 /* Workaround: Clear the timing override chicken bit again. */
1685 reg = TRANS_CHICKEN2(pipe);
1686 val = I915_READ(reg);
1687 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1688 I915_WRITE(reg, val);
1692 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1696 val = I915_READ(LPT_TRANSCONF);
1697 val &= ~TRANS_ENABLE;
1698 I915_WRITE(LPT_TRANSCONF, val);
1699 /* wait for PCH transcoder off, transcoder state */
1700 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1701 DRM_ERROR("Failed to disable PCH transcoder\n");
1703 /* Workaround: clear timing override bit. */
1704 val = I915_READ(_TRANSA_CHICKEN2);
1705 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1706 I915_WRITE(_TRANSA_CHICKEN2, val);
1710 * intel_enable_pipe - enable a pipe, asserting requirements
1711 * @dev_priv: i915 private structure
1712 * @pipe: pipe to enable
1713 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1715 * Enable @pipe, making sure that various hardware specific requirements
1716 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1718 * @pipe should be %PIPE_A or %PIPE_B.
1720 * Will wait until the pipe is actually running (i.e. first vblank) before
1723 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1724 bool pch_port, bool dsi)
1726 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1728 enum pipe pch_transcoder;
1732 assert_planes_disabled(dev_priv, pipe);
1733 assert_cursor_disabled(dev_priv, pipe);
1734 assert_sprites_disabled(dev_priv, pipe);
1736 if (HAS_PCH_LPT(dev_priv->dev))
1737 pch_transcoder = TRANSCODER_A;
1739 pch_transcoder = pipe;
1742 * A pipe without a PLL won't actually be able to drive bits from
1743 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1746 if (!HAS_PCH_SPLIT(dev_priv->dev))
1748 assert_dsi_pll_enabled(dev_priv);
1750 assert_pll_enabled(dev_priv, pipe);
1753 /* if driving the PCH, we need FDI enabled */
1754 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1755 assert_fdi_tx_pll_enabled(dev_priv,
1756 (enum pipe) cpu_transcoder);
1758 /* FIXME: assert CPU port conditions for SNB+ */
1761 reg = PIPECONF(cpu_transcoder);
1762 val = I915_READ(reg);
1763 if (val & PIPECONF_ENABLE)
1766 I915_WRITE(reg, val | PIPECONF_ENABLE);
1767 intel_wait_for_vblank(dev_priv->dev, pipe);
1771 * intel_disable_pipe - disable a pipe, asserting requirements
1772 * @dev_priv: i915 private structure
1773 * @pipe: pipe to disable
1775 * Disable @pipe, making sure that various hardware specific requirements
1776 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778 * @pipe should be %PIPE_A or %PIPE_B.
1780 * Will wait until the pipe has shut down before returning.
1782 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1785 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1791 * Make sure planes won't keep trying to pump pixels to us,
1792 * or we might hang the display.
1794 assert_planes_disabled(dev_priv, pipe);
1795 assert_cursor_disabled(dev_priv, pipe);
1796 assert_sprites_disabled(dev_priv, pipe);
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1802 reg = PIPECONF(cpu_transcoder);
1803 val = I915_READ(reg);
1804 if ((val & PIPECONF_ENABLE) == 0)
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1815 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1818 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1820 I915_WRITE(reg, I915_READ(reg));
1825 * intel_enable_primary_plane - enable the primary plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1832 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
1835 struct intel_crtc *intel_crtc =
1836 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1840 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1841 assert_pipe_enabled(dev_priv, pipe);
1843 WARN(!intel_crtc->primary_disabled, "Primary plane already enabled\n");
1845 intel_crtc->primary_disabled = false;
1847 reg = DSPCNTR(plane);
1848 val = I915_READ(reg);
1849 if (val & DISPLAY_PLANE_ENABLE)
1852 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1853 intel_flush_primary_plane(dev_priv, plane);
1854 intel_wait_for_vblank(dev_priv->dev, pipe);
1858 * intel_disable_primary_plane - disable the primary plane
1859 * @dev_priv: i915 private structure
1860 * @plane: plane to disable
1861 * @pipe: pipe consuming the data
1863 * Disable @plane; should be an independent operation.
1865 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1866 enum plane plane, enum pipe pipe)
1868 struct intel_crtc *intel_crtc =
1869 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1873 WARN(intel_crtc->primary_disabled, "Primary plane already disabled\n");
1875 intel_crtc->primary_disabled = true;
1877 reg = DSPCNTR(plane);
1878 val = I915_READ(reg);
1879 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1882 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1883 intel_flush_primary_plane(dev_priv, plane);
1884 intel_wait_for_vblank(dev_priv->dev, pipe);
1887 static bool need_vtd_wa(struct drm_device *dev)
1889 #ifdef CONFIG_INTEL_IOMMU
1890 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1897 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1898 struct drm_i915_gem_object *obj,
1899 struct intel_ring_buffer *pipelined)
1901 struct drm_i915_private *dev_priv = dev->dev_private;
1905 switch (obj->tiling_mode) {
1906 case I915_TILING_NONE:
1907 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1908 alignment = 128 * 1024;
1909 else if (INTEL_INFO(dev)->gen >= 4)
1910 alignment = 4 * 1024;
1912 alignment = 64 * 1024;
1915 /* pin() will align the object as required by fence */
1919 /* Despite that we check this in framebuffer_init userspace can
1920 * screw us over and change the tiling after the fact. Only
1921 * pinned buffers can't change their tiling. */
1922 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1928 /* Note that the w/a also requires 64 PTE of padding following the
1929 * bo. We currently fill all unused PTE with the shadow page and so
1930 * we should always have valid PTE following the scanout preventing
1933 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1934 alignment = 256 * 1024;
1936 dev_priv->mm.interruptible = false;
1937 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1939 goto err_interruptible;
1941 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1942 * fence, whereas 965+ only requires a fence if using
1943 * framebuffer compression. For simplicity, we always install
1944 * a fence as the cost is not that onerous.
1946 ret = i915_gem_object_get_fence(obj);
1950 i915_gem_object_pin_fence(obj);
1952 dev_priv->mm.interruptible = true;
1956 i915_gem_object_unpin_from_display_plane(obj);
1958 dev_priv->mm.interruptible = true;
1962 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1964 i915_gem_object_unpin_fence(obj);
1965 i915_gem_object_unpin_from_display_plane(obj);
1968 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1969 * is assumed to be a power-of-two. */
1970 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1971 unsigned int tiling_mode,
1975 if (tiling_mode != I915_TILING_NONE) {
1976 unsigned int tile_rows, tiles;
1981 tiles = *x / (512/cpp);
1984 return tile_rows * pitch * 8 + tiles * 4096;
1986 unsigned int offset;
1988 offset = *y * pitch + *x * cpp;
1990 *x = (offset & 4095) / cpp;
1991 return offset & -4096;
1995 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1998 struct drm_device *dev = crtc->dev;
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2001 struct intel_framebuffer *intel_fb;
2002 struct drm_i915_gem_object *obj;
2003 int plane = intel_crtc->plane;
2004 unsigned long linear_offset;
2013 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2017 intel_fb = to_intel_framebuffer(fb);
2018 obj = intel_fb->obj;
2020 reg = DSPCNTR(plane);
2021 dspcntr = I915_READ(reg);
2022 /* Mask out pixel format bits in case we change it */
2023 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2024 switch (fb->pixel_format) {
2026 dspcntr |= DISPPLANE_8BPP;
2028 case DRM_FORMAT_XRGB1555:
2029 case DRM_FORMAT_ARGB1555:
2030 dspcntr |= DISPPLANE_BGRX555;
2032 case DRM_FORMAT_RGB565:
2033 dspcntr |= DISPPLANE_BGRX565;
2035 case DRM_FORMAT_XRGB8888:
2036 case DRM_FORMAT_ARGB8888:
2037 dspcntr |= DISPPLANE_BGRX888;
2039 case DRM_FORMAT_XBGR8888:
2040 case DRM_FORMAT_ABGR8888:
2041 dspcntr |= DISPPLANE_RGBX888;
2043 case DRM_FORMAT_XRGB2101010:
2044 case DRM_FORMAT_ARGB2101010:
2045 dspcntr |= DISPPLANE_BGRX101010;
2047 case DRM_FORMAT_XBGR2101010:
2048 case DRM_FORMAT_ABGR2101010:
2049 dspcntr |= DISPPLANE_RGBX101010;
2055 if (INTEL_INFO(dev)->gen >= 4) {
2056 if (obj->tiling_mode != I915_TILING_NONE)
2057 dspcntr |= DISPPLANE_TILED;
2059 dspcntr &= ~DISPPLANE_TILED;
2063 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2065 I915_WRITE(reg, dspcntr);
2067 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2069 if (INTEL_INFO(dev)->gen >= 4) {
2070 intel_crtc->dspaddr_offset =
2071 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2072 fb->bits_per_pixel / 8,
2074 linear_offset -= intel_crtc->dspaddr_offset;
2076 intel_crtc->dspaddr_offset = linear_offset;
2079 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2080 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2082 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2083 if (INTEL_INFO(dev)->gen >= 4) {
2084 I915_MODIFY_DISPBASE(DSPSURF(plane),
2085 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2086 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2087 I915_WRITE(DSPLINOFF(plane), linear_offset);
2089 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2095 static int ironlake_update_plane(struct drm_crtc *crtc,
2096 struct drm_framebuffer *fb, int x, int y)
2098 struct drm_device *dev = crtc->dev;
2099 struct drm_i915_private *dev_priv = dev->dev_private;
2100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2101 struct intel_framebuffer *intel_fb;
2102 struct drm_i915_gem_object *obj;
2103 int plane = intel_crtc->plane;
2104 unsigned long linear_offset;
2114 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2118 intel_fb = to_intel_framebuffer(fb);
2119 obj = intel_fb->obj;
2121 reg = DSPCNTR(plane);
2122 dspcntr = I915_READ(reg);
2123 /* Mask out pixel format bits in case we change it */
2124 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2125 switch (fb->pixel_format) {
2127 dspcntr |= DISPPLANE_8BPP;
2129 case DRM_FORMAT_RGB565:
2130 dspcntr |= DISPPLANE_BGRX565;
2132 case DRM_FORMAT_XRGB8888:
2133 case DRM_FORMAT_ARGB8888:
2134 dspcntr |= DISPPLANE_BGRX888;
2136 case DRM_FORMAT_XBGR8888:
2137 case DRM_FORMAT_ABGR8888:
2138 dspcntr |= DISPPLANE_RGBX888;
2140 case DRM_FORMAT_XRGB2101010:
2141 case DRM_FORMAT_ARGB2101010:
2142 dspcntr |= DISPPLANE_BGRX101010;
2144 case DRM_FORMAT_XBGR2101010:
2145 case DRM_FORMAT_ABGR2101010:
2146 dspcntr |= DISPPLANE_RGBX101010;
2152 if (obj->tiling_mode != I915_TILING_NONE)
2153 dspcntr |= DISPPLANE_TILED;
2155 dspcntr &= ~DISPPLANE_TILED;
2157 if (IS_HASWELL(dev))
2158 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2160 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2162 I915_WRITE(reg, dspcntr);
2164 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2165 intel_crtc->dspaddr_offset =
2166 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2167 fb->bits_per_pixel / 8,
2169 linear_offset -= intel_crtc->dspaddr_offset;
2171 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2172 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2174 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2175 I915_MODIFY_DISPBASE(DSPSURF(plane),
2176 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2177 if (IS_HASWELL(dev)) {
2178 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2180 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2181 I915_WRITE(DSPLINOFF(plane), linear_offset);
2188 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2190 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2191 int x, int y, enum mode_set_atomic state)
2193 struct drm_device *dev = crtc->dev;
2194 struct drm_i915_private *dev_priv = dev->dev_private;
2196 if (dev_priv->display.disable_fbc)
2197 dev_priv->display.disable_fbc(dev);
2198 intel_increase_pllclock(crtc);
2200 return dev_priv->display.update_plane(crtc, fb, x, y);
2203 void intel_display_handle_reset(struct drm_device *dev)
2205 struct drm_i915_private *dev_priv = dev->dev_private;
2206 struct drm_crtc *crtc;
2209 * Flips in the rings have been nuked by the reset,
2210 * so complete all pending flips so that user space
2211 * will get its events and not get stuck.
2213 * Also update the base address of all primary
2214 * planes to the the last fb to make sure we're
2215 * showing the correct fb after a reset.
2217 * Need to make two loops over the crtcs so that we
2218 * don't try to grab a crtc mutex before the
2219 * pending_flip_queue really got woken up.
2222 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2224 enum plane plane = intel_crtc->plane;
2226 intel_prepare_page_flip(dev, plane);
2227 intel_finish_page_flip_plane(dev, plane);
2230 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2233 mutex_lock(&crtc->mutex);
2234 if (intel_crtc->active)
2235 dev_priv->display.update_plane(crtc, crtc->fb,
2237 mutex_unlock(&crtc->mutex);
2242 intel_finish_fb(struct drm_framebuffer *old_fb)
2244 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2245 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2246 bool was_interruptible = dev_priv->mm.interruptible;
2249 /* Big Hammer, we also need to ensure that any pending
2250 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2251 * current scanout is retired before unpinning the old
2254 * This should only fail upon a hung GPU, in which case we
2255 * can safely continue.
2257 dev_priv->mm.interruptible = false;
2258 ret = i915_gem_object_finish_gpu(obj);
2259 dev_priv->mm.interruptible = was_interruptible;
2264 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2266 struct drm_device *dev = crtc->dev;
2267 struct drm_i915_master_private *master_priv;
2268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2270 if (!dev->primary->master)
2273 master_priv = dev->primary->master->driver_priv;
2274 if (!master_priv->sarea_priv)
2277 switch (intel_crtc->pipe) {
2279 master_priv->sarea_priv->pipeA_x = x;
2280 master_priv->sarea_priv->pipeA_y = y;
2283 master_priv->sarea_priv->pipeB_x = x;
2284 master_priv->sarea_priv->pipeB_y = y;
2292 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2293 struct drm_framebuffer *fb)
2295 struct drm_device *dev = crtc->dev;
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298 struct drm_framebuffer *old_fb;
2303 DRM_ERROR("No FB bound\n");
2307 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2308 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2309 plane_name(intel_crtc->plane),
2310 INTEL_INFO(dev)->num_pipes);
2314 mutex_lock(&dev->struct_mutex);
2315 ret = intel_pin_and_fence_fb_obj(dev,
2316 to_intel_framebuffer(fb)->obj,
2319 mutex_unlock(&dev->struct_mutex);
2320 DRM_ERROR("pin & fence failed\n");
2325 * Update pipe size and adjust fitter if needed: the reason for this is
2326 * that in compute_mode_changes we check the native mode (not the pfit
2327 * mode) to see if we can flip rather than do a full mode set. In the
2328 * fastboot case, we'll flip, but if we don't update the pipesrc and
2329 * pfit state, we'll end up with a big fb scanned out into the wrong
2332 * To fix this properly, we need to hoist the checks up into
2333 * compute_mode_changes (or above), check the actual pfit state and
2334 * whether the platform allows pfit disable with pipe active, and only
2335 * then update the pipesrc and pfit state, even on the flip path.
2337 if (i915_fastboot) {
2338 const struct drm_display_mode *adjusted_mode =
2339 &intel_crtc->config.adjusted_mode;
2341 I915_WRITE(PIPESRC(intel_crtc->pipe),
2342 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2343 (adjusted_mode->crtc_vdisplay - 1));
2344 if (!intel_crtc->config.pch_pfit.enabled &&
2345 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2346 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2347 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2348 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2349 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2353 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2355 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2356 mutex_unlock(&dev->struct_mutex);
2357 DRM_ERROR("failed to update base address\n");
2367 if (intel_crtc->active && old_fb != fb)
2368 intel_wait_for_vblank(dev, intel_crtc->pipe);
2369 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2372 intel_update_fbc(dev);
2373 intel_edp_psr_update(dev);
2374 mutex_unlock(&dev->struct_mutex);
2376 intel_crtc_update_sarea_pos(crtc, x, y);
2381 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2383 struct drm_device *dev = crtc->dev;
2384 struct drm_i915_private *dev_priv = dev->dev_private;
2385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2386 int pipe = intel_crtc->pipe;
2389 /* enable normal train */
2390 reg = FDI_TX_CTL(pipe);
2391 temp = I915_READ(reg);
2392 if (IS_IVYBRIDGE(dev)) {
2393 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2394 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2396 temp &= ~FDI_LINK_TRAIN_NONE;
2397 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2399 I915_WRITE(reg, temp);
2401 reg = FDI_RX_CTL(pipe);
2402 temp = I915_READ(reg);
2403 if (HAS_PCH_CPT(dev)) {
2404 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2405 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2407 temp &= ~FDI_LINK_TRAIN_NONE;
2408 temp |= FDI_LINK_TRAIN_NONE;
2410 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2412 /* wait one idle pattern time */
2416 /* IVB wants error correction enabled */
2417 if (IS_IVYBRIDGE(dev))
2418 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2419 FDI_FE_ERRC_ENABLE);
2422 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2424 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2427 static void ivb_modeset_global_resources(struct drm_device *dev)
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 struct intel_crtc *pipe_B_crtc =
2431 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2432 struct intel_crtc *pipe_C_crtc =
2433 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2437 * When everything is off disable fdi C so that we could enable fdi B
2438 * with all lanes. Note that we don't care about enabled pipes without
2439 * an enabled pch encoder.
2441 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2442 !pipe_has_enabled_pch(pipe_C_crtc)) {
2443 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2444 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2446 temp = I915_READ(SOUTH_CHICKEN1);
2447 temp &= ~FDI_BC_BIFURCATION_SELECT;
2448 DRM_DEBUG_KMS("disabling fdi C rx\n");
2449 I915_WRITE(SOUTH_CHICKEN1, temp);
2453 /* The FDI link training functions for ILK/Ibexpeak. */
2454 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2456 struct drm_device *dev = crtc->dev;
2457 struct drm_i915_private *dev_priv = dev->dev_private;
2458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2459 int pipe = intel_crtc->pipe;
2460 int plane = intel_crtc->plane;
2461 u32 reg, temp, tries;
2463 /* FDI needs bits from pipe & plane first */
2464 assert_pipe_enabled(dev_priv, pipe);
2465 assert_plane_enabled(dev_priv, plane);
2467 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2469 reg = FDI_RX_IMR(pipe);
2470 temp = I915_READ(reg);
2471 temp &= ~FDI_RX_SYMBOL_LOCK;
2472 temp &= ~FDI_RX_BIT_LOCK;
2473 I915_WRITE(reg, temp);
2477 /* enable CPU FDI TX and PCH FDI RX */
2478 reg = FDI_TX_CTL(pipe);
2479 temp = I915_READ(reg);
2480 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2481 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2482 temp &= ~FDI_LINK_TRAIN_NONE;
2483 temp |= FDI_LINK_TRAIN_PATTERN_1;
2484 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2486 reg = FDI_RX_CTL(pipe);
2487 temp = I915_READ(reg);
2488 temp &= ~FDI_LINK_TRAIN_NONE;
2489 temp |= FDI_LINK_TRAIN_PATTERN_1;
2490 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2495 /* Ironlake workaround, enable clock pointer after FDI enable*/
2496 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2497 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2498 FDI_RX_PHASE_SYNC_POINTER_EN);
2500 reg = FDI_RX_IIR(pipe);
2501 for (tries = 0; tries < 5; tries++) {
2502 temp = I915_READ(reg);
2503 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2505 if ((temp & FDI_RX_BIT_LOCK)) {
2506 DRM_DEBUG_KMS("FDI train 1 done.\n");
2507 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2512 DRM_ERROR("FDI train 1 fail!\n");
2515 reg = FDI_TX_CTL(pipe);
2516 temp = I915_READ(reg);
2517 temp &= ~FDI_LINK_TRAIN_NONE;
2518 temp |= FDI_LINK_TRAIN_PATTERN_2;
2519 I915_WRITE(reg, temp);
2521 reg = FDI_RX_CTL(pipe);
2522 temp = I915_READ(reg);
2523 temp &= ~FDI_LINK_TRAIN_NONE;
2524 temp |= FDI_LINK_TRAIN_PATTERN_2;
2525 I915_WRITE(reg, temp);
2530 reg = FDI_RX_IIR(pipe);
2531 for (tries = 0; tries < 5; tries++) {
2532 temp = I915_READ(reg);
2533 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2535 if (temp & FDI_RX_SYMBOL_LOCK) {
2536 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2537 DRM_DEBUG_KMS("FDI train 2 done.\n");
2542 DRM_ERROR("FDI train 2 fail!\n");
2544 DRM_DEBUG_KMS("FDI train done\n");
2548 static const int snb_b_fdi_train_param[] = {
2549 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2550 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2551 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2552 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2555 /* The FDI link training functions for SNB/Cougarpoint. */
2556 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2558 struct drm_device *dev = crtc->dev;
2559 struct drm_i915_private *dev_priv = dev->dev_private;
2560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2561 int pipe = intel_crtc->pipe;
2562 u32 reg, temp, i, retry;
2564 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2566 reg = FDI_RX_IMR(pipe);
2567 temp = I915_READ(reg);
2568 temp &= ~FDI_RX_SYMBOL_LOCK;
2569 temp &= ~FDI_RX_BIT_LOCK;
2570 I915_WRITE(reg, temp);
2575 /* enable CPU FDI TX and PCH FDI RX */
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
2578 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2579 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2580 temp &= ~FDI_LINK_TRAIN_NONE;
2581 temp |= FDI_LINK_TRAIN_PATTERN_1;
2582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2584 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2585 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2587 I915_WRITE(FDI_RX_MISC(pipe),
2588 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2590 reg = FDI_RX_CTL(pipe);
2591 temp = I915_READ(reg);
2592 if (HAS_PCH_CPT(dev)) {
2593 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2594 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2596 temp &= ~FDI_LINK_TRAIN_NONE;
2597 temp |= FDI_LINK_TRAIN_PATTERN_1;
2599 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2604 for (i = 0; i < 4; i++) {
2605 reg = FDI_TX_CTL(pipe);
2606 temp = I915_READ(reg);
2607 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2608 temp |= snb_b_fdi_train_param[i];
2609 I915_WRITE(reg, temp);
2614 for (retry = 0; retry < 5; retry++) {
2615 reg = FDI_RX_IIR(pipe);
2616 temp = I915_READ(reg);
2617 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2618 if (temp & FDI_RX_BIT_LOCK) {
2619 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2620 DRM_DEBUG_KMS("FDI train 1 done.\n");
2629 DRM_ERROR("FDI train 1 fail!\n");
2632 reg = FDI_TX_CTL(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~FDI_LINK_TRAIN_NONE;
2635 temp |= FDI_LINK_TRAIN_PATTERN_2;
2637 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2641 I915_WRITE(reg, temp);
2643 reg = FDI_RX_CTL(pipe);
2644 temp = I915_READ(reg);
2645 if (HAS_PCH_CPT(dev)) {
2646 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2647 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2649 temp &= ~FDI_LINK_TRAIN_NONE;
2650 temp |= FDI_LINK_TRAIN_PATTERN_2;
2652 I915_WRITE(reg, temp);
2657 for (i = 0; i < 4; i++) {
2658 reg = FDI_TX_CTL(pipe);
2659 temp = I915_READ(reg);
2660 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2661 temp |= snb_b_fdi_train_param[i];
2662 I915_WRITE(reg, temp);
2667 for (retry = 0; retry < 5; retry++) {
2668 reg = FDI_RX_IIR(pipe);
2669 temp = I915_READ(reg);
2670 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2671 if (temp & FDI_RX_SYMBOL_LOCK) {
2672 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2673 DRM_DEBUG_KMS("FDI train 2 done.\n");
2682 DRM_ERROR("FDI train 2 fail!\n");
2684 DRM_DEBUG_KMS("FDI train done.\n");
2687 /* Manual link training for Ivy Bridge A0 parts */
2688 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2690 struct drm_device *dev = crtc->dev;
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2693 int pipe = intel_crtc->pipe;
2694 u32 reg, temp, i, j;
2696 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2698 reg = FDI_RX_IMR(pipe);
2699 temp = I915_READ(reg);
2700 temp &= ~FDI_RX_SYMBOL_LOCK;
2701 temp &= ~FDI_RX_BIT_LOCK;
2702 I915_WRITE(reg, temp);
2707 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2708 I915_READ(FDI_RX_IIR(pipe)));
2710 /* Try each vswing and preemphasis setting twice before moving on */
2711 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2712 /* disable first in case we need to retry */
2713 reg = FDI_TX_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2716 temp &= ~FDI_TX_ENABLE;
2717 I915_WRITE(reg, temp);
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~FDI_LINK_TRAIN_AUTO;
2722 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2723 temp &= ~FDI_RX_ENABLE;
2724 I915_WRITE(reg, temp);
2726 /* enable CPU FDI TX and PCH FDI RX */
2727 reg = FDI_TX_CTL(pipe);
2728 temp = I915_READ(reg);
2729 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2730 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2731 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2732 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2733 temp |= snb_b_fdi_train_param[j/2];
2734 temp |= FDI_COMPOSITE_SYNC;
2735 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2737 I915_WRITE(FDI_RX_MISC(pipe),
2738 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2740 reg = FDI_RX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2743 temp |= FDI_COMPOSITE_SYNC;
2744 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2747 udelay(1); /* should be 0.5us */
2749 for (i = 0; i < 4; i++) {
2750 reg = FDI_RX_IIR(pipe);
2751 temp = I915_READ(reg);
2752 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2754 if (temp & FDI_RX_BIT_LOCK ||
2755 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2756 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2757 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2761 udelay(1); /* should be 0.5us */
2764 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2772 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2773 I915_WRITE(reg, temp);
2775 reg = FDI_RX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2778 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2779 I915_WRITE(reg, temp);
2782 udelay(2); /* should be 1.5us */
2784 for (i = 0; i < 4; i++) {
2785 reg = FDI_RX_IIR(pipe);
2786 temp = I915_READ(reg);
2787 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2789 if (temp & FDI_RX_SYMBOL_LOCK ||
2790 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2791 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2792 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2796 udelay(2); /* should be 1.5us */
2799 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2803 DRM_DEBUG_KMS("FDI train done.\n");
2806 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2808 struct drm_device *dev = intel_crtc->base.dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 int pipe = intel_crtc->pipe;
2814 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2815 reg = FDI_RX_CTL(pipe);
2816 temp = I915_READ(reg);
2817 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2818 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2819 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2820 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2825 /* Switch from Rawclk to PCDclk */
2826 temp = I915_READ(reg);
2827 I915_WRITE(reg, temp | FDI_PCDCLK);
2832 /* Enable CPU FDI TX PLL, always on for Ironlake */
2833 reg = FDI_TX_CTL(pipe);
2834 temp = I915_READ(reg);
2835 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2836 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2843 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2845 struct drm_device *dev = intel_crtc->base.dev;
2846 struct drm_i915_private *dev_priv = dev->dev_private;
2847 int pipe = intel_crtc->pipe;
2850 /* Switch from PCDclk to Rawclk */
2851 reg = FDI_RX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2855 /* Disable CPU FDI TX PLL */
2856 reg = FDI_TX_CTL(pipe);
2857 temp = I915_READ(reg);
2858 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2863 reg = FDI_RX_CTL(pipe);
2864 temp = I915_READ(reg);
2865 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2867 /* Wait for the clocks to turn off. */
2872 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2874 struct drm_device *dev = crtc->dev;
2875 struct drm_i915_private *dev_priv = dev->dev_private;
2876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2877 int pipe = intel_crtc->pipe;
2880 /* disable CPU FDI tx and PCH FDI rx */
2881 reg = FDI_TX_CTL(pipe);
2882 temp = I915_READ(reg);
2883 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2886 reg = FDI_RX_CTL(pipe);
2887 temp = I915_READ(reg);
2888 temp &= ~(0x7 << 16);
2889 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2890 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2895 /* Ironlake workaround, disable clock pointer after downing FDI */
2896 if (HAS_PCH_IBX(dev)) {
2897 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2900 /* still set train pattern 1 */
2901 reg = FDI_TX_CTL(pipe);
2902 temp = I915_READ(reg);
2903 temp &= ~FDI_LINK_TRAIN_NONE;
2904 temp |= FDI_LINK_TRAIN_PATTERN_1;
2905 I915_WRITE(reg, temp);
2907 reg = FDI_RX_CTL(pipe);
2908 temp = I915_READ(reg);
2909 if (HAS_PCH_CPT(dev)) {
2910 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2911 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2913 temp &= ~FDI_LINK_TRAIN_NONE;
2914 temp |= FDI_LINK_TRAIN_PATTERN_1;
2916 /* BPC in FDI rx is consistent with that in PIPECONF */
2917 temp &= ~(0x07 << 16);
2918 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2919 I915_WRITE(reg, temp);
2925 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2927 struct drm_device *dev = crtc->dev;
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2930 unsigned long flags;
2933 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2934 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2937 spin_lock_irqsave(&dev->event_lock, flags);
2938 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2939 spin_unlock_irqrestore(&dev->event_lock, flags);
2944 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2946 struct drm_device *dev = crtc->dev;
2947 struct drm_i915_private *dev_priv = dev->dev_private;
2949 if (crtc->fb == NULL)
2952 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2954 wait_event(dev_priv->pending_flip_queue,
2955 !intel_crtc_has_pending_flip(crtc));
2957 mutex_lock(&dev->struct_mutex);
2958 intel_finish_fb(crtc->fb);
2959 mutex_unlock(&dev->struct_mutex);
2962 /* Program iCLKIP clock to the desired frequency */
2963 static void lpt_program_iclkip(struct drm_crtc *crtc)
2965 struct drm_device *dev = crtc->dev;
2966 struct drm_i915_private *dev_priv = dev->dev_private;
2967 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2968 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2971 mutex_lock(&dev_priv->dpio_lock);
2973 /* It is necessary to ungate the pixclk gate prior to programming
2974 * the divisors, and gate it back when it is done.
2976 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2978 /* Disable SSCCTL */
2979 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2980 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2984 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2985 if (clock == 20000) {
2990 /* The iCLK virtual clock root frequency is in MHz,
2991 * but the adjusted_mode->crtc_clock in in KHz. To get the
2992 * divisors, it is necessary to divide one by another, so we
2993 * convert the virtual clock precision to KHz here for higher
2996 u32 iclk_virtual_root_freq = 172800 * 1000;
2997 u32 iclk_pi_range = 64;
2998 u32 desired_divisor, msb_divisor_value, pi_value;
3000 desired_divisor = (iclk_virtual_root_freq / clock);
3001 msb_divisor_value = desired_divisor / iclk_pi_range;
3002 pi_value = desired_divisor % iclk_pi_range;
3005 divsel = msb_divisor_value - 2;
3006 phaseinc = pi_value;
3009 /* This should not happen with any sane values */
3010 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3011 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3012 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3013 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3015 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3022 /* Program SSCDIVINTPHASE6 */
3023 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3024 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3025 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3026 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3027 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3028 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3029 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3030 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3032 /* Program SSCAUXDIV */
3033 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3034 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3035 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3036 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3038 /* Enable modulator and associated divider */
3039 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3040 temp &= ~SBI_SSCCTL_DISABLE;
3041 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3043 /* Wait for initialization time */
3046 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3048 mutex_unlock(&dev_priv->dpio_lock);
3051 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3052 enum pipe pch_transcoder)
3054 struct drm_device *dev = crtc->base.dev;
3055 struct drm_i915_private *dev_priv = dev->dev_private;
3056 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3058 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3059 I915_READ(HTOTAL(cpu_transcoder)));
3060 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3061 I915_READ(HBLANK(cpu_transcoder)));
3062 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3063 I915_READ(HSYNC(cpu_transcoder)));
3065 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3066 I915_READ(VTOTAL(cpu_transcoder)));
3067 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3068 I915_READ(VBLANK(cpu_transcoder)));
3069 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3070 I915_READ(VSYNC(cpu_transcoder)));
3071 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3072 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3076 * Enable PCH resources required for PCH ports:
3078 * - FDI training & RX/TX
3079 * - update transcoder timings
3080 * - DP transcoding bits
3083 static void ironlake_pch_enable(struct drm_crtc *crtc)
3085 struct drm_device *dev = crtc->dev;
3086 struct drm_i915_private *dev_priv = dev->dev_private;
3087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3088 int pipe = intel_crtc->pipe;
3091 assert_pch_transcoder_disabled(dev_priv, pipe);
3093 /* Write the TU size bits before fdi link training, so that error
3094 * detection works. */
3095 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3096 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3098 /* For PCH output, training FDI link */
3099 dev_priv->display.fdi_link_train(crtc);
3101 /* We need to program the right clock selection before writing the pixel
3102 * mutliplier into the DPLL. */
3103 if (HAS_PCH_CPT(dev)) {
3106 temp = I915_READ(PCH_DPLL_SEL);
3107 temp |= TRANS_DPLL_ENABLE(pipe);
3108 sel = TRANS_DPLLB_SEL(pipe);
3109 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3113 I915_WRITE(PCH_DPLL_SEL, temp);
3116 /* XXX: pch pll's can be enabled any time before we enable the PCH
3117 * transcoder, and we actually should do this to not upset any PCH
3118 * transcoder that already use the clock when we share it.
3120 * Note that enable_shared_dpll tries to do the right thing, but
3121 * get_shared_dpll unconditionally resets the pll - we need that to have
3122 * the right LVDS enable sequence. */
3123 ironlake_enable_shared_dpll(intel_crtc);
3125 /* set transcoder timing, panel must allow it */
3126 assert_panel_unlocked(dev_priv, pipe);
3127 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3129 intel_fdi_normal_train(crtc);
3131 /* For PCH DP, enable TRANS_DP_CTL */
3132 if (HAS_PCH_CPT(dev) &&
3133 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3134 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3135 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3136 reg = TRANS_DP_CTL(pipe);
3137 temp = I915_READ(reg);
3138 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3139 TRANS_DP_SYNC_MASK |
3141 temp |= (TRANS_DP_OUTPUT_ENABLE |
3142 TRANS_DP_ENH_FRAMING);
3143 temp |= bpc << 9; /* same format but at 11:9 */
3145 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3146 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3147 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3148 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3150 switch (intel_trans_dp_port_sel(crtc)) {
3152 temp |= TRANS_DP_PORT_SEL_B;
3155 temp |= TRANS_DP_PORT_SEL_C;
3158 temp |= TRANS_DP_PORT_SEL_D;
3164 I915_WRITE(reg, temp);
3167 ironlake_enable_pch_transcoder(dev_priv, pipe);
3170 static void lpt_pch_enable(struct drm_crtc *crtc)
3172 struct drm_device *dev = crtc->dev;
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3175 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3177 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3179 lpt_program_iclkip(crtc);
3181 /* Set transcoder timing. */
3182 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3184 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3187 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3189 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3194 if (pll->refcount == 0) {
3195 WARN(1, "bad %s refcount\n", pll->name);
3199 if (--pll->refcount == 0) {
3201 WARN_ON(pll->active);
3204 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3207 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3209 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3210 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3211 enum intel_dpll_id i;
3214 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3215 crtc->base.base.id, pll->name);
3216 intel_put_shared_dpll(crtc);
3219 if (HAS_PCH_IBX(dev_priv->dev)) {
3220 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3221 i = (enum intel_dpll_id) crtc->pipe;
3222 pll = &dev_priv->shared_dplls[i];
3224 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3225 crtc->base.base.id, pll->name);
3230 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3231 pll = &dev_priv->shared_dplls[i];
3233 /* Only want to check enabled timings first */
3234 if (pll->refcount == 0)
3237 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3238 sizeof(pll->hw_state)) == 0) {
3239 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3241 pll->name, pll->refcount, pll->active);
3247 /* Ok no matching timings, maybe there's a free one? */
3248 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3249 pll = &dev_priv->shared_dplls[i];
3250 if (pll->refcount == 0) {
3251 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3252 crtc->base.base.id, pll->name);
3260 crtc->config.shared_dpll = i;
3261 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3262 pipe_name(crtc->pipe));
3264 if (pll->active == 0) {
3265 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3266 sizeof(pll->hw_state));
3268 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3270 assert_shared_dpll_disabled(dev_priv, pll);
3272 pll->mode_set(dev_priv, pll);
3279 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3281 struct drm_i915_private *dev_priv = dev->dev_private;
3282 int dslreg = PIPEDSL(pipe);
3285 temp = I915_READ(dslreg);
3287 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3288 if (wait_for(I915_READ(dslreg) != temp, 5))
3289 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3293 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3295 struct drm_device *dev = crtc->base.dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 int pipe = crtc->pipe;
3299 if (crtc->config.pch_pfit.enabled) {
3300 /* Force use of hard-coded filter coefficients
3301 * as some pre-programmed values are broken,
3304 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3305 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3306 PF_PIPE_SEL_IVB(pipe));
3308 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3309 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3310 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3314 static void intel_enable_planes(struct drm_crtc *crtc)
3316 struct drm_device *dev = crtc->dev;
3317 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3318 struct intel_plane *intel_plane;
3320 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3321 if (intel_plane->pipe == pipe)
3322 intel_plane_restore(&intel_plane->base);
3325 static void intel_disable_planes(struct drm_crtc *crtc)
3327 struct drm_device *dev = crtc->dev;
3328 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3329 struct intel_plane *intel_plane;
3331 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3332 if (intel_plane->pipe == pipe)
3333 intel_plane_disable(&intel_plane->base);
3336 void hsw_enable_ips(struct intel_crtc *crtc)
3338 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3340 if (!crtc->config.ips_enabled)
3343 /* We can only enable IPS after we enable a plane and wait for a vblank.
3344 * We guarantee that the plane is enabled by calling intel_enable_ips
3345 * only after intel_enable_plane. And intel_enable_plane already waits
3346 * for a vblank, so all we need to do here is to enable the IPS bit. */
3347 assert_plane_enabled(dev_priv, crtc->plane);
3348 I915_WRITE(IPS_CTL, IPS_ENABLE);
3351 void hsw_disable_ips(struct intel_crtc *crtc)
3353 struct drm_device *dev = crtc->base.dev;
3354 struct drm_i915_private *dev_priv = dev->dev_private;
3356 if (!crtc->config.ips_enabled)
3359 assert_plane_enabled(dev_priv, crtc->plane);
3360 I915_WRITE(IPS_CTL, 0);
3361 POSTING_READ(IPS_CTL);
3363 /* We need to wait for a vblank before we can disable the plane. */
3364 intel_wait_for_vblank(dev, crtc->pipe);
3367 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3368 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3370 struct drm_device *dev = crtc->dev;
3371 struct drm_i915_private *dev_priv = dev->dev_private;
3372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3373 enum pipe pipe = intel_crtc->pipe;
3374 int palreg = PALETTE(pipe);
3376 bool reenable_ips = false;
3378 /* The clocks have to be on to load the palette. */
3379 if (!crtc->enabled || !intel_crtc->active)
3382 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3383 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3384 assert_dsi_pll_enabled(dev_priv);
3386 assert_pll_enabled(dev_priv, pipe);
3389 /* use legacy palette for Ironlake */
3390 if (HAS_PCH_SPLIT(dev))
3391 palreg = LGC_PALETTE(pipe);
3393 /* Workaround : Do not read or write the pipe palette/gamma data while
3394 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3396 if (intel_crtc->config.ips_enabled &&
3397 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3398 GAMMA_MODE_MODE_SPLIT)) {
3399 hsw_disable_ips(intel_crtc);
3400 reenable_ips = true;
3403 for (i = 0; i < 256; i++) {
3404 I915_WRITE(palreg + 4 * i,
3405 (intel_crtc->lut_r[i] << 16) |
3406 (intel_crtc->lut_g[i] << 8) |
3407 intel_crtc->lut_b[i]);
3411 hsw_enable_ips(intel_crtc);
3414 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3416 struct drm_device *dev = crtc->dev;
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3419 struct intel_encoder *encoder;
3420 int pipe = intel_crtc->pipe;
3421 int plane = intel_crtc->plane;
3423 WARN_ON(!crtc->enabled);
3425 if (intel_crtc->active)
3428 intel_crtc->active = true;
3430 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3431 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3433 for_each_encoder_on_crtc(dev, crtc, encoder)
3434 if (encoder->pre_enable)
3435 encoder->pre_enable(encoder);
3437 if (intel_crtc->config.has_pch_encoder) {
3438 /* Note: FDI PLL enabling _must_ be done before we enable the
3439 * cpu pipes, hence this is separate from all the other fdi/pch
3441 ironlake_fdi_pll_enable(intel_crtc);
3443 assert_fdi_tx_disabled(dev_priv, pipe);
3444 assert_fdi_rx_disabled(dev_priv, pipe);
3447 ironlake_pfit_enable(intel_crtc);
3450 * On ILK+ LUT must be loaded before the pipe is running but with
3453 intel_crtc_load_lut(crtc);
3455 intel_update_watermarks(crtc);
3456 intel_enable_pipe(dev_priv, pipe,
3457 intel_crtc->config.has_pch_encoder, false);
3458 intel_enable_primary_plane(dev_priv, plane, pipe);
3459 intel_enable_planes(crtc);
3460 intel_crtc_update_cursor(crtc, true);
3462 if (intel_crtc->config.has_pch_encoder)
3463 ironlake_pch_enable(crtc);
3465 mutex_lock(&dev->struct_mutex);
3466 intel_update_fbc(dev);
3467 mutex_unlock(&dev->struct_mutex);
3469 for_each_encoder_on_crtc(dev, crtc, encoder)
3470 encoder->enable(encoder);
3472 if (HAS_PCH_CPT(dev))
3473 cpt_verify_modeset(dev, intel_crtc->pipe);
3476 * There seems to be a race in PCH platform hw (at least on some
3477 * outputs) where an enabled pipe still completes any pageflip right
3478 * away (as if the pipe is off) instead of waiting for vblank. As soon
3479 * as the first vblank happend, everything works as expected. Hence just
3480 * wait for one vblank before returning to avoid strange things
3483 intel_wait_for_vblank(dev, intel_crtc->pipe);
3486 /* IPS only exists on ULT machines and is tied to pipe A. */
3487 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3489 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3492 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 int pipe = intel_crtc->pipe;
3498 int plane = intel_crtc->plane;
3500 intel_enable_primary_plane(dev_priv, plane, pipe);
3501 intel_enable_planes(crtc);
3502 intel_crtc_update_cursor(crtc, true);
3504 hsw_enable_ips(intel_crtc);
3506 mutex_lock(&dev->struct_mutex);
3507 intel_update_fbc(dev);
3508 mutex_unlock(&dev->struct_mutex);
3511 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3513 struct drm_device *dev = crtc->dev;
3514 struct drm_i915_private *dev_priv = dev->dev_private;
3515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516 int pipe = intel_crtc->pipe;
3517 int plane = intel_crtc->plane;
3519 intel_crtc_wait_for_pending_flips(crtc);
3520 drm_vblank_off(dev, pipe);
3522 /* FBC must be disabled before disabling the plane on HSW. */
3523 if (dev_priv->fbc.plane == plane)
3524 intel_disable_fbc(dev);
3526 hsw_disable_ips(intel_crtc);
3528 intel_crtc_update_cursor(crtc, false);
3529 intel_disable_planes(crtc);
3530 intel_disable_primary_plane(dev_priv, plane, pipe);
3534 * This implements the workaround described in the "notes" section of the mode
3535 * set sequence documentation. When going from no pipes or single pipe to
3536 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3537 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3539 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3541 struct drm_device *dev = crtc->base.dev;
3542 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3544 /* We want to get the other_active_crtc only if there's only 1 other
3546 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3547 if (!crtc_it->active || crtc_it == crtc)
3550 if (other_active_crtc)
3553 other_active_crtc = crtc_it;
3555 if (!other_active_crtc)
3558 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3559 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3562 static void haswell_crtc_enable(struct drm_crtc *crtc)
3564 struct drm_device *dev = crtc->dev;
3565 struct drm_i915_private *dev_priv = dev->dev_private;
3566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3567 struct intel_encoder *encoder;
3568 int pipe = intel_crtc->pipe;
3570 WARN_ON(!crtc->enabled);
3572 if (intel_crtc->active)
3575 intel_crtc->active = true;
3577 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3578 if (intel_crtc->config.has_pch_encoder)
3579 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3581 if (intel_crtc->config.has_pch_encoder)
3582 dev_priv->display.fdi_link_train(crtc);
3584 for_each_encoder_on_crtc(dev, crtc, encoder)
3585 if (encoder->pre_enable)
3586 encoder->pre_enable(encoder);
3588 intel_ddi_enable_pipe_clock(intel_crtc);
3590 ironlake_pfit_enable(intel_crtc);
3593 * On ILK+ LUT must be loaded before the pipe is running but with
3596 intel_crtc_load_lut(crtc);
3598 intel_ddi_set_pipe_settings(crtc);
3599 intel_ddi_enable_transcoder_func(crtc);
3601 intel_update_watermarks(crtc);
3602 intel_enable_pipe(dev_priv, pipe,
3603 intel_crtc->config.has_pch_encoder, false);
3605 if (intel_crtc->config.has_pch_encoder)
3606 lpt_pch_enable(crtc);
3608 for_each_encoder_on_crtc(dev, crtc, encoder) {
3609 encoder->enable(encoder);
3610 intel_opregion_notify_encoder(encoder, true);
3613 /* If we change the relative order between pipe/planes enabling, we need
3614 * to change the workaround. */
3615 haswell_mode_set_planes_workaround(intel_crtc);
3616 haswell_crtc_enable_planes(crtc);
3619 * There seems to be a race in PCH platform hw (at least on some
3620 * outputs) where an enabled pipe still completes any pageflip right
3621 * away (as if the pipe is off) instead of waiting for vblank. As soon
3622 * as the first vblank happend, everything works as expected. Hence just
3623 * wait for one vblank before returning to avoid strange things
3626 intel_wait_for_vblank(dev, intel_crtc->pipe);
3629 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3631 struct drm_device *dev = crtc->base.dev;
3632 struct drm_i915_private *dev_priv = dev->dev_private;
3633 int pipe = crtc->pipe;
3635 /* To avoid upsetting the power well on haswell only disable the pfit if
3636 * it's in use. The hw state code will make sure we get this right. */
3637 if (crtc->config.pch_pfit.enabled) {
3638 I915_WRITE(PF_CTL(pipe), 0);
3639 I915_WRITE(PF_WIN_POS(pipe), 0);
3640 I915_WRITE(PF_WIN_SZ(pipe), 0);
3644 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3646 struct drm_device *dev = crtc->dev;
3647 struct drm_i915_private *dev_priv = dev->dev_private;
3648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3649 struct intel_encoder *encoder;
3650 int pipe = intel_crtc->pipe;
3651 int plane = intel_crtc->plane;
3655 if (!intel_crtc->active)
3658 for_each_encoder_on_crtc(dev, crtc, encoder)
3659 encoder->disable(encoder);
3661 intel_crtc_wait_for_pending_flips(crtc);
3662 drm_vblank_off(dev, pipe);
3664 if (dev_priv->fbc.plane == plane)
3665 intel_disable_fbc(dev);
3667 intel_crtc_update_cursor(crtc, false);
3668 intel_disable_planes(crtc);
3669 intel_disable_primary_plane(dev_priv, plane, pipe);
3671 if (intel_crtc->config.has_pch_encoder)
3672 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3674 intel_disable_pipe(dev_priv, pipe);
3676 ironlake_pfit_disable(intel_crtc);
3678 for_each_encoder_on_crtc(dev, crtc, encoder)
3679 if (encoder->post_disable)
3680 encoder->post_disable(encoder);
3682 if (intel_crtc->config.has_pch_encoder) {
3683 ironlake_fdi_disable(crtc);
3685 ironlake_disable_pch_transcoder(dev_priv, pipe);
3686 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3688 if (HAS_PCH_CPT(dev)) {
3689 /* disable TRANS_DP_CTL */
3690 reg = TRANS_DP_CTL(pipe);
3691 temp = I915_READ(reg);
3692 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3693 TRANS_DP_PORT_SEL_MASK);
3694 temp |= TRANS_DP_PORT_SEL_NONE;
3695 I915_WRITE(reg, temp);
3697 /* disable DPLL_SEL */
3698 temp = I915_READ(PCH_DPLL_SEL);
3699 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3700 I915_WRITE(PCH_DPLL_SEL, temp);
3703 /* disable PCH DPLL */
3704 intel_disable_shared_dpll(intel_crtc);
3706 ironlake_fdi_pll_disable(intel_crtc);
3709 intel_crtc->active = false;
3710 intel_update_watermarks(crtc);
3712 mutex_lock(&dev->struct_mutex);
3713 intel_update_fbc(dev);
3714 mutex_unlock(&dev->struct_mutex);
3717 static void haswell_crtc_disable(struct drm_crtc *crtc)
3719 struct drm_device *dev = crtc->dev;
3720 struct drm_i915_private *dev_priv = dev->dev_private;
3721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3722 struct intel_encoder *encoder;
3723 int pipe = intel_crtc->pipe;
3724 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3726 if (!intel_crtc->active)
3729 haswell_crtc_disable_planes(crtc);
3731 for_each_encoder_on_crtc(dev, crtc, encoder) {
3732 intel_opregion_notify_encoder(encoder, false);
3733 encoder->disable(encoder);
3736 if (intel_crtc->config.has_pch_encoder)
3737 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3738 intel_disable_pipe(dev_priv, pipe);
3740 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3742 ironlake_pfit_disable(intel_crtc);
3744 intel_ddi_disable_pipe_clock(intel_crtc);
3746 for_each_encoder_on_crtc(dev, crtc, encoder)
3747 if (encoder->post_disable)
3748 encoder->post_disable(encoder);
3750 if (intel_crtc->config.has_pch_encoder) {
3751 lpt_disable_pch_transcoder(dev_priv);
3752 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3753 intel_ddi_fdi_disable(crtc);
3756 intel_crtc->active = false;
3757 intel_update_watermarks(crtc);
3759 mutex_lock(&dev->struct_mutex);
3760 intel_update_fbc(dev);
3761 mutex_unlock(&dev->struct_mutex);
3764 static void ironlake_crtc_off(struct drm_crtc *crtc)
3766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3767 intel_put_shared_dpll(intel_crtc);
3770 static void haswell_crtc_off(struct drm_crtc *crtc)
3772 intel_ddi_put_crtc_pll(crtc);
3775 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3777 if (!enable && intel_crtc->overlay) {
3778 struct drm_device *dev = intel_crtc->base.dev;
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3781 mutex_lock(&dev->struct_mutex);
3782 dev_priv->mm.interruptible = false;
3783 (void) intel_overlay_switch_off(intel_crtc->overlay);
3784 dev_priv->mm.interruptible = true;
3785 mutex_unlock(&dev->struct_mutex);
3788 /* Let userspace switch the overlay on again. In most cases userspace
3789 * has to recompute where to put it anyway.
3794 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3795 * cursor plane briefly if not already running after enabling the display
3797 * This workaround avoids occasional blank screens when self refresh is
3801 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3803 u32 cntl = I915_READ(CURCNTR(pipe));
3805 if ((cntl & CURSOR_MODE) == 0) {
3806 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3808 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3809 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3810 intel_wait_for_vblank(dev_priv->dev, pipe);
3811 I915_WRITE(CURCNTR(pipe), cntl);
3812 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3813 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3817 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3819 struct drm_device *dev = crtc->base.dev;
3820 struct drm_i915_private *dev_priv = dev->dev_private;
3821 struct intel_crtc_config *pipe_config = &crtc->config;
3823 if (!crtc->config.gmch_pfit.control)
3827 * The panel fitter should only be adjusted whilst the pipe is disabled,
3828 * according to register description and PRM.
3830 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3831 assert_pipe_disabled(dev_priv, crtc->pipe);
3833 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3834 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3836 /* Border color in case we don't scale up to the full screen. Black by
3837 * default, change to something else for debugging. */
3838 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3841 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3843 struct drm_device *dev = crtc->dev;
3844 struct drm_i915_private *dev_priv = dev->dev_private;
3845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3846 struct intel_encoder *encoder;
3847 int pipe = intel_crtc->pipe;
3848 int plane = intel_crtc->plane;
3851 WARN_ON(!crtc->enabled);
3853 if (intel_crtc->active)
3856 intel_crtc->active = true;
3858 for_each_encoder_on_crtc(dev, crtc, encoder)
3859 if (encoder->pre_pll_enable)
3860 encoder->pre_pll_enable(encoder);
3862 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3865 vlv_enable_pll(intel_crtc);
3867 for_each_encoder_on_crtc(dev, crtc, encoder)
3868 if (encoder->pre_enable)
3869 encoder->pre_enable(encoder);
3871 i9xx_pfit_enable(intel_crtc);
3873 intel_crtc_load_lut(crtc);
3875 intel_update_watermarks(crtc);
3876 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3877 intel_enable_primary_plane(dev_priv, plane, pipe);
3878 intel_enable_planes(crtc);
3879 intel_crtc_update_cursor(crtc, true);
3881 intel_update_fbc(dev);
3883 for_each_encoder_on_crtc(dev, crtc, encoder)
3884 encoder->enable(encoder);
3887 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3889 struct drm_device *dev = crtc->dev;
3890 struct drm_i915_private *dev_priv = dev->dev_private;
3891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3892 struct intel_encoder *encoder;
3893 int pipe = intel_crtc->pipe;
3894 int plane = intel_crtc->plane;
3896 WARN_ON(!crtc->enabled);
3898 if (intel_crtc->active)
3901 intel_crtc->active = true;
3903 for_each_encoder_on_crtc(dev, crtc, encoder)
3904 if (encoder->pre_enable)
3905 encoder->pre_enable(encoder);
3907 i9xx_enable_pll(intel_crtc);
3909 i9xx_pfit_enable(intel_crtc);
3911 intel_crtc_load_lut(crtc);
3913 intel_update_watermarks(crtc);
3914 intel_enable_pipe(dev_priv, pipe, false, false);
3915 intel_enable_primary_plane(dev_priv, plane, pipe);
3916 intel_enable_planes(crtc);
3917 /* The fixup needs to happen before cursor is enabled */
3919 g4x_fixup_plane(dev_priv, pipe);
3920 intel_crtc_update_cursor(crtc, true);
3922 /* Give the overlay scaler a chance to enable if it's on this pipe */
3923 intel_crtc_dpms_overlay(intel_crtc, true);
3925 intel_update_fbc(dev);
3927 for_each_encoder_on_crtc(dev, crtc, encoder)
3928 encoder->enable(encoder);
3931 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3933 struct drm_device *dev = crtc->base.dev;
3934 struct drm_i915_private *dev_priv = dev->dev_private;
3936 if (!crtc->config.gmch_pfit.control)
3939 assert_pipe_disabled(dev_priv, crtc->pipe);
3941 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3942 I915_READ(PFIT_CONTROL));
3943 I915_WRITE(PFIT_CONTROL, 0);
3946 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3948 struct drm_device *dev = crtc->dev;
3949 struct drm_i915_private *dev_priv = dev->dev_private;
3950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3951 struct intel_encoder *encoder;
3952 int pipe = intel_crtc->pipe;
3953 int plane = intel_crtc->plane;
3955 if (!intel_crtc->active)
3958 for_each_encoder_on_crtc(dev, crtc, encoder)
3959 encoder->disable(encoder);
3961 /* Give the overlay scaler a chance to disable if it's on this pipe */
3962 intel_crtc_wait_for_pending_flips(crtc);
3963 drm_vblank_off(dev, pipe);
3965 if (dev_priv->fbc.plane == plane)
3966 intel_disable_fbc(dev);
3968 intel_crtc_dpms_overlay(intel_crtc, false);
3969 intel_crtc_update_cursor(crtc, false);
3970 intel_disable_planes(crtc);
3971 intel_disable_primary_plane(dev_priv, plane, pipe);
3973 intel_disable_pipe(dev_priv, pipe);
3975 i9xx_pfit_disable(intel_crtc);
3977 for_each_encoder_on_crtc(dev, crtc, encoder)
3978 if (encoder->post_disable)
3979 encoder->post_disable(encoder);
3981 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3982 vlv_disable_pll(dev_priv, pipe);
3983 else if (!IS_VALLEYVIEW(dev))
3984 i9xx_disable_pll(dev_priv, pipe);
3986 intel_crtc->active = false;
3987 intel_update_watermarks(crtc);
3989 intel_update_fbc(dev);
3992 static void i9xx_crtc_off(struct drm_crtc *crtc)
3996 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3999 struct drm_device *dev = crtc->dev;
4000 struct drm_i915_master_private *master_priv;
4001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4002 int pipe = intel_crtc->pipe;
4004 if (!dev->primary->master)
4007 master_priv = dev->primary->master->driver_priv;
4008 if (!master_priv->sarea_priv)
4013 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4014 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4017 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4018 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4021 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4027 * Sets the power management mode of the pipe and plane.
4029 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4031 struct drm_device *dev = crtc->dev;
4032 struct drm_i915_private *dev_priv = dev->dev_private;
4033 struct intel_encoder *intel_encoder;
4034 bool enable = false;
4036 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4037 enable |= intel_encoder->connectors_active;
4040 dev_priv->display.crtc_enable(crtc);
4042 dev_priv->display.crtc_disable(crtc);
4044 intel_crtc_update_sarea(crtc, enable);
4047 static void intel_crtc_disable(struct drm_crtc *crtc)
4049 struct drm_device *dev = crtc->dev;
4050 struct drm_connector *connector;
4051 struct drm_i915_private *dev_priv = dev->dev_private;
4052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4054 /* crtc should still be enabled when we disable it. */
4055 WARN_ON(!crtc->enabled);
4057 dev_priv->display.crtc_disable(crtc);
4058 intel_crtc->eld_vld = false;
4059 intel_crtc_update_sarea(crtc, false);
4060 dev_priv->display.off(crtc);
4062 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4063 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4064 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4067 mutex_lock(&dev->struct_mutex);
4068 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4069 mutex_unlock(&dev->struct_mutex);
4073 /* Update computed state. */
4074 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4075 if (!connector->encoder || !connector->encoder->crtc)
4078 if (connector->encoder->crtc != crtc)
4081 connector->dpms = DRM_MODE_DPMS_OFF;
4082 to_intel_encoder(connector->encoder)->connectors_active = false;
4086 void intel_encoder_destroy(struct drm_encoder *encoder)
4088 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4090 drm_encoder_cleanup(encoder);
4091 kfree(intel_encoder);
4094 /* Simple dpms helper for encoders with just one connector, no cloning and only
4095 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4096 * state of the entire output pipe. */
4097 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4099 if (mode == DRM_MODE_DPMS_ON) {
4100 encoder->connectors_active = true;
4102 intel_crtc_update_dpms(encoder->base.crtc);
4104 encoder->connectors_active = false;
4106 intel_crtc_update_dpms(encoder->base.crtc);
4110 /* Cross check the actual hw state with our own modeset state tracking (and it's
4111 * internal consistency). */
4112 static void intel_connector_check_state(struct intel_connector *connector)
4114 if (connector->get_hw_state(connector)) {
4115 struct intel_encoder *encoder = connector->encoder;
4116 struct drm_crtc *crtc;
4117 bool encoder_enabled;
4120 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4121 connector->base.base.id,
4122 drm_get_connector_name(&connector->base));
4124 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4125 "wrong connector dpms state\n");
4126 WARN(connector->base.encoder != &encoder->base,
4127 "active connector not linked to encoder\n");
4128 WARN(!encoder->connectors_active,
4129 "encoder->connectors_active not set\n");
4131 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4132 WARN(!encoder_enabled, "encoder not enabled\n");
4133 if (WARN_ON(!encoder->base.crtc))
4136 crtc = encoder->base.crtc;
4138 WARN(!crtc->enabled, "crtc not enabled\n");
4139 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4140 WARN(pipe != to_intel_crtc(crtc)->pipe,
4141 "encoder active on the wrong pipe\n");
4145 /* Even simpler default implementation, if there's really no special case to
4147 void intel_connector_dpms(struct drm_connector *connector, int mode)
4149 struct intel_encoder *encoder = intel_attached_encoder(connector);
4151 /* All the simple cases only support two dpms states. */
4152 if (mode != DRM_MODE_DPMS_ON)
4153 mode = DRM_MODE_DPMS_OFF;
4155 if (mode == connector->dpms)
4158 connector->dpms = mode;
4160 /* Only need to change hw state when actually enabled */
4161 if (encoder->base.crtc)
4162 intel_encoder_dpms(encoder, mode);
4164 WARN_ON(encoder->connectors_active != false);
4166 intel_modeset_check_state(connector->dev);
4169 /* Simple connector->get_hw_state implementation for encoders that support only
4170 * one connector and no cloning and hence the encoder state determines the state
4171 * of the connector. */
4172 bool intel_connector_get_hw_state(struct intel_connector *connector)
4175 struct intel_encoder *encoder = connector->encoder;
4177 return encoder->get_hw_state(encoder, &pipe);
4180 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4181 struct intel_crtc_config *pipe_config)
4183 struct drm_i915_private *dev_priv = dev->dev_private;
4184 struct intel_crtc *pipe_B_crtc =
4185 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4187 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4188 pipe_name(pipe), pipe_config->fdi_lanes);
4189 if (pipe_config->fdi_lanes > 4) {
4190 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4191 pipe_name(pipe), pipe_config->fdi_lanes);
4195 if (IS_HASWELL(dev)) {
4196 if (pipe_config->fdi_lanes > 2) {
4197 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4198 pipe_config->fdi_lanes);
4205 if (INTEL_INFO(dev)->num_pipes == 2)
4208 /* Ivybridge 3 pipe is really complicated */
4213 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4214 pipe_config->fdi_lanes > 2) {
4215 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4216 pipe_name(pipe), pipe_config->fdi_lanes);
4221 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4222 pipe_B_crtc->config.fdi_lanes <= 2) {
4223 if (pipe_config->fdi_lanes > 2) {
4224 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4225 pipe_name(pipe), pipe_config->fdi_lanes);
4229 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4239 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4240 struct intel_crtc_config *pipe_config)
4242 struct drm_device *dev = intel_crtc->base.dev;
4243 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4244 int lane, link_bw, fdi_dotclock;
4245 bool setup_ok, needs_recompute = false;
4248 /* FDI is a binary signal running at ~2.7GHz, encoding
4249 * each output octet as 10 bits. The actual frequency
4250 * is stored as a divider into a 100MHz clock, and the
4251 * mode pixel clock is stored in units of 1KHz.
4252 * Hence the bw of each lane in terms of the mode signal
4255 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4257 fdi_dotclock = adjusted_mode->crtc_clock;
4259 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4260 pipe_config->pipe_bpp);
4262 pipe_config->fdi_lanes = lane;
4264 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4265 link_bw, &pipe_config->fdi_m_n);
4267 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4268 intel_crtc->pipe, pipe_config);
4269 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4270 pipe_config->pipe_bpp -= 2*3;
4271 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4272 pipe_config->pipe_bpp);
4273 needs_recompute = true;
4274 pipe_config->bw_constrained = true;
4279 if (needs_recompute)
4282 return setup_ok ? 0 : -EINVAL;
4285 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4286 struct intel_crtc_config *pipe_config)
4288 pipe_config->ips_enabled = i915_enable_ips &&
4289 hsw_crtc_supports_ips(crtc) &&
4290 pipe_config->pipe_bpp <= 24;
4293 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4294 struct intel_crtc_config *pipe_config)
4296 struct drm_device *dev = crtc->base.dev;
4297 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4299 /* FIXME should check pixel clock limits on all platforms */
4300 if (INTEL_INFO(dev)->gen < 4) {
4301 struct drm_i915_private *dev_priv = dev->dev_private;
4303 dev_priv->display.get_display_clock_speed(dev);
4306 * Enable pixel doubling when the dot clock
4307 * is > 90% of the (display) core speed.
4309 * GDG double wide on either pipe,
4310 * otherwise pipe A only.
4312 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4313 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4315 pipe_config->double_wide = true;
4318 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4323 * Pipe horizontal size must be even in:
4325 * - LVDS dual channel mode
4326 * - Double wide pipe
4328 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4329 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4330 pipe_config->pipe_src_w &= ~1;
4332 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4333 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4335 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4336 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4339 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4340 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4341 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4342 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4344 pipe_config->pipe_bpp = 8*3;
4348 hsw_compute_ips_config(crtc, pipe_config);
4350 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4351 * clock survives for now. */
4352 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4353 pipe_config->shared_dpll = crtc->config.shared_dpll;
4355 if (pipe_config->has_pch_encoder)
4356 return ironlake_fdi_compute_config(crtc, pipe_config);
4361 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4363 return 400000; /* FIXME */
4366 static int i945_get_display_clock_speed(struct drm_device *dev)
4371 static int i915_get_display_clock_speed(struct drm_device *dev)
4376 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4381 static int pnv_get_display_clock_speed(struct drm_device *dev)
4385 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4387 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4388 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4390 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4392 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4394 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4397 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4398 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4400 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4405 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4409 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4411 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4414 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4415 case GC_DISPLAY_CLOCK_333_MHZ:
4418 case GC_DISPLAY_CLOCK_190_200_MHZ:
4424 static int i865_get_display_clock_speed(struct drm_device *dev)
4429 static int i855_get_display_clock_speed(struct drm_device *dev)
4432 /* Assume that the hardware is in the high speed state. This
4433 * should be the default.
4435 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4436 case GC_CLOCK_133_200:
4437 case GC_CLOCK_100_200:
4439 case GC_CLOCK_166_250:
4441 case GC_CLOCK_100_133:
4445 /* Shouldn't happen */
4449 static int i830_get_display_clock_speed(struct drm_device *dev)
4455 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4457 while (*num > DATA_LINK_M_N_MASK ||
4458 *den > DATA_LINK_M_N_MASK) {
4464 static void compute_m_n(unsigned int m, unsigned int n,
4465 uint32_t *ret_m, uint32_t *ret_n)
4467 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4468 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4469 intel_reduce_m_n_ratio(ret_m, ret_n);
4473 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4474 int pixel_clock, int link_clock,
4475 struct intel_link_m_n *m_n)
4479 compute_m_n(bits_per_pixel * pixel_clock,
4480 link_clock * nlanes * 8,
4481 &m_n->gmch_m, &m_n->gmch_n);
4483 compute_m_n(pixel_clock, link_clock,
4484 &m_n->link_m, &m_n->link_n);
4487 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4489 if (i915_panel_use_ssc >= 0)
4490 return i915_panel_use_ssc != 0;
4491 return dev_priv->vbt.lvds_use_ssc
4492 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4495 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4497 struct drm_device *dev = crtc->dev;
4498 struct drm_i915_private *dev_priv = dev->dev_private;
4501 if (IS_VALLEYVIEW(dev)) {
4503 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4504 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4505 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4506 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4508 } else if (!IS_GEN2(dev)) {
4517 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4519 return (1 << dpll->n) << 16 | dpll->m2;
4522 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4524 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4527 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4528 intel_clock_t *reduced_clock)
4530 struct drm_device *dev = crtc->base.dev;
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4532 int pipe = crtc->pipe;
4535 if (IS_PINEVIEW(dev)) {
4536 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4538 fp2 = pnv_dpll_compute_fp(reduced_clock);
4540 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4542 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4545 I915_WRITE(FP0(pipe), fp);
4546 crtc->config.dpll_hw_state.fp0 = fp;
4548 crtc->lowfreq_avail = false;
4549 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4550 reduced_clock && i915_powersave) {
4551 I915_WRITE(FP1(pipe), fp2);
4552 crtc->config.dpll_hw_state.fp1 = fp2;
4553 crtc->lowfreq_avail = true;
4555 I915_WRITE(FP1(pipe), fp);
4556 crtc->config.dpll_hw_state.fp1 = fp;
4560 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4566 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4567 * and set it to a reasonable value instead.
4569 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4570 reg_val &= 0xffffff00;
4571 reg_val |= 0x00000030;
4572 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4574 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4575 reg_val &= 0x8cffffff;
4576 reg_val = 0x8c000000;
4577 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4579 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4580 reg_val &= 0xffffff00;
4581 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4583 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4584 reg_val &= 0x00ffffff;
4585 reg_val |= 0xb0000000;
4586 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4589 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4590 struct intel_link_m_n *m_n)
4592 struct drm_device *dev = crtc->base.dev;
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594 int pipe = crtc->pipe;
4596 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4597 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4598 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4599 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4602 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4603 struct intel_link_m_n *m_n)
4605 struct drm_device *dev = crtc->base.dev;
4606 struct drm_i915_private *dev_priv = dev->dev_private;
4607 int pipe = crtc->pipe;
4608 enum transcoder transcoder = crtc->config.cpu_transcoder;
4610 if (INTEL_INFO(dev)->gen >= 5) {
4611 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4612 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4613 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4614 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4616 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4617 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4618 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4619 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4623 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4625 if (crtc->config.has_pch_encoder)
4626 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4628 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4631 static void vlv_update_pll(struct intel_crtc *crtc)
4633 struct drm_device *dev = crtc->base.dev;
4634 struct drm_i915_private *dev_priv = dev->dev_private;
4635 int pipe = crtc->pipe;
4637 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4638 u32 coreclk, reg_val, dpll_md;
4640 mutex_lock(&dev_priv->dpio_lock);
4642 bestn = crtc->config.dpll.n;
4643 bestm1 = crtc->config.dpll.m1;
4644 bestm2 = crtc->config.dpll.m2;
4645 bestp1 = crtc->config.dpll.p1;
4646 bestp2 = crtc->config.dpll.p2;
4648 /* See eDP HDMI DPIO driver vbios notes doc */
4650 /* PLL B needs special handling */
4652 vlv_pllb_recal_opamp(dev_priv, pipe);
4654 /* Set up Tx target for periodic Rcomp update */
4655 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4657 /* Disable target IRef on PLL */
4658 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4659 reg_val &= 0x00ffffff;
4660 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4662 /* Disable fast lock */
4663 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4665 /* Set idtafcrecal before PLL is enabled */
4666 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4667 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4668 mdiv |= ((bestn << DPIO_N_SHIFT));
4669 mdiv |= (1 << DPIO_K_SHIFT);
4672 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4673 * but we don't support that).
4674 * Note: don't use the DAC post divider as it seems unstable.
4676 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4677 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4679 mdiv |= DPIO_ENABLE_CALIBRATION;
4680 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4682 /* Set HBR and RBR LPF coefficients */
4683 if (crtc->config.port_clock == 162000 ||
4684 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4685 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4686 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4689 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4692 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4693 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4694 /* Use SSC source */
4696 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4699 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4701 } else { /* HDMI or VGA */
4702 /* Use bend source */
4704 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4707 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4711 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4712 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4713 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4714 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4715 coreclk |= 0x01000000;
4716 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4718 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4720 /* Enable DPIO clock input */
4721 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4722 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4723 /* We should never disable this, set it here for state tracking */
4725 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4726 dpll |= DPLL_VCO_ENABLE;
4727 crtc->config.dpll_hw_state.dpll = dpll;
4729 dpll_md = (crtc->config.pixel_multiplier - 1)
4730 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4731 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4733 if (crtc->config.has_dp_encoder)
4734 intel_dp_set_m_n(crtc);
4736 mutex_unlock(&dev_priv->dpio_lock);
4739 static void i9xx_update_pll(struct intel_crtc *crtc,
4740 intel_clock_t *reduced_clock,
4743 struct drm_device *dev = crtc->base.dev;
4744 struct drm_i915_private *dev_priv = dev->dev_private;
4747 struct dpll *clock = &crtc->config.dpll;
4749 i9xx_update_pll_dividers(crtc, reduced_clock);
4751 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4752 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4754 dpll = DPLL_VGA_MODE_DIS;
4756 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4757 dpll |= DPLLB_MODE_LVDS;
4759 dpll |= DPLLB_MODE_DAC_SERIAL;
4761 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4762 dpll |= (crtc->config.pixel_multiplier - 1)
4763 << SDVO_MULTIPLIER_SHIFT_HIRES;
4767 dpll |= DPLL_SDVO_HIGH_SPEED;
4769 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4770 dpll |= DPLL_SDVO_HIGH_SPEED;
4772 /* compute bitmask from p1 value */
4773 if (IS_PINEVIEW(dev))
4774 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4776 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4777 if (IS_G4X(dev) && reduced_clock)
4778 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4780 switch (clock->p2) {
4782 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4785 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4788 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4791 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4794 if (INTEL_INFO(dev)->gen >= 4)
4795 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4797 if (crtc->config.sdvo_tv_clock)
4798 dpll |= PLL_REF_INPUT_TVCLKINBC;
4799 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4800 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4801 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4803 dpll |= PLL_REF_INPUT_DREFCLK;
4805 dpll |= DPLL_VCO_ENABLE;
4806 crtc->config.dpll_hw_state.dpll = dpll;
4808 if (INTEL_INFO(dev)->gen >= 4) {
4809 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4810 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4811 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4814 if (crtc->config.has_dp_encoder)
4815 intel_dp_set_m_n(crtc);
4818 static void i8xx_update_pll(struct intel_crtc *crtc,
4819 intel_clock_t *reduced_clock,
4822 struct drm_device *dev = crtc->base.dev;
4823 struct drm_i915_private *dev_priv = dev->dev_private;
4825 struct dpll *clock = &crtc->config.dpll;
4827 i9xx_update_pll_dividers(crtc, reduced_clock);
4829 dpll = DPLL_VGA_MODE_DIS;
4831 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4832 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4835 dpll |= PLL_P1_DIVIDE_BY_TWO;
4837 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4839 dpll |= PLL_P2_DIVIDE_BY_4;
4842 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4843 dpll |= DPLL_DVO_2X_MODE;
4845 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4846 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4847 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4849 dpll |= PLL_REF_INPUT_DREFCLK;
4851 dpll |= DPLL_VCO_ENABLE;
4852 crtc->config.dpll_hw_state.dpll = dpll;
4855 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4857 struct drm_device *dev = intel_crtc->base.dev;
4858 struct drm_i915_private *dev_priv = dev->dev_private;
4859 enum pipe pipe = intel_crtc->pipe;
4860 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4861 struct drm_display_mode *adjusted_mode =
4862 &intel_crtc->config.adjusted_mode;
4863 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4865 /* We need to be careful not to changed the adjusted mode, for otherwise
4866 * the hw state checker will get angry at the mismatch. */
4867 crtc_vtotal = adjusted_mode->crtc_vtotal;
4868 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4870 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4871 /* the chip adds 2 halflines automatically */
4873 crtc_vblank_end -= 1;
4874 vsyncshift = adjusted_mode->crtc_hsync_start
4875 - adjusted_mode->crtc_htotal / 2;
4880 if (INTEL_INFO(dev)->gen > 3)
4881 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4883 I915_WRITE(HTOTAL(cpu_transcoder),
4884 (adjusted_mode->crtc_hdisplay - 1) |
4885 ((adjusted_mode->crtc_htotal - 1) << 16));
4886 I915_WRITE(HBLANK(cpu_transcoder),
4887 (adjusted_mode->crtc_hblank_start - 1) |
4888 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4889 I915_WRITE(HSYNC(cpu_transcoder),
4890 (adjusted_mode->crtc_hsync_start - 1) |
4891 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4893 I915_WRITE(VTOTAL(cpu_transcoder),
4894 (adjusted_mode->crtc_vdisplay - 1) |
4895 ((crtc_vtotal - 1) << 16));
4896 I915_WRITE(VBLANK(cpu_transcoder),
4897 (adjusted_mode->crtc_vblank_start - 1) |
4898 ((crtc_vblank_end - 1) << 16));
4899 I915_WRITE(VSYNC(cpu_transcoder),
4900 (adjusted_mode->crtc_vsync_start - 1) |
4901 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4903 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4904 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4905 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4907 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4908 (pipe == PIPE_B || pipe == PIPE_C))
4909 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4911 /* pipesrc controls the size that is scaled from, which should
4912 * always be the user's requested size.
4914 I915_WRITE(PIPESRC(pipe),
4915 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4916 (intel_crtc->config.pipe_src_h - 1));
4919 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4920 struct intel_crtc_config *pipe_config)
4922 struct drm_device *dev = crtc->base.dev;
4923 struct drm_i915_private *dev_priv = dev->dev_private;
4924 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4927 tmp = I915_READ(HTOTAL(cpu_transcoder));
4928 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4929 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4930 tmp = I915_READ(HBLANK(cpu_transcoder));
4931 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4932 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4933 tmp = I915_READ(HSYNC(cpu_transcoder));
4934 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4935 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4937 tmp = I915_READ(VTOTAL(cpu_transcoder));
4938 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4939 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4940 tmp = I915_READ(VBLANK(cpu_transcoder));
4941 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4942 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4943 tmp = I915_READ(VSYNC(cpu_transcoder));
4944 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4945 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4947 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4948 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4949 pipe_config->adjusted_mode.crtc_vtotal += 1;
4950 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4953 tmp = I915_READ(PIPESRC(crtc->pipe));
4954 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4955 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4957 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4958 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4961 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4962 struct intel_crtc_config *pipe_config)
4964 struct drm_crtc *crtc = &intel_crtc->base;
4966 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4967 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4968 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4969 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4971 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4972 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4973 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4974 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4976 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4978 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
4979 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4982 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4984 struct drm_device *dev = intel_crtc->base.dev;
4985 struct drm_i915_private *dev_priv = dev->dev_private;
4990 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4991 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4992 pipeconf |= PIPECONF_ENABLE;
4994 if (intel_crtc->config.double_wide)
4995 pipeconf |= PIPECONF_DOUBLE_WIDE;
4997 /* only g4x and later have fancy bpc/dither controls */
4998 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4999 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5000 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5001 pipeconf |= PIPECONF_DITHER_EN |
5002 PIPECONF_DITHER_TYPE_SP;
5004 switch (intel_crtc->config.pipe_bpp) {
5006 pipeconf |= PIPECONF_6BPC;
5009 pipeconf |= PIPECONF_8BPC;
5012 pipeconf |= PIPECONF_10BPC;
5015 /* Case prevented by intel_choose_pipe_bpp_dither. */
5020 if (HAS_PIPE_CXSR(dev)) {
5021 if (intel_crtc->lowfreq_avail) {
5022 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5023 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5025 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5029 if (!IS_GEN2(dev) &&
5030 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5031 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5033 pipeconf |= PIPECONF_PROGRESSIVE;
5035 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5036 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5038 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5039 POSTING_READ(PIPECONF(intel_crtc->pipe));
5042 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5044 struct drm_framebuffer *fb)
5046 struct drm_device *dev = crtc->dev;
5047 struct drm_i915_private *dev_priv = dev->dev_private;
5048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5049 int pipe = intel_crtc->pipe;
5050 int plane = intel_crtc->plane;
5051 int refclk, num_connectors = 0;
5052 intel_clock_t clock, reduced_clock;
5054 bool ok, has_reduced_clock = false;
5055 bool is_lvds = false, is_dsi = false;
5056 struct intel_encoder *encoder;
5057 const intel_limit_t *limit;
5060 for_each_encoder_on_crtc(dev, crtc, encoder) {
5061 switch (encoder->type) {
5062 case INTEL_OUTPUT_LVDS:
5065 case INTEL_OUTPUT_DSI:
5076 if (!intel_crtc->config.clock_set) {
5077 refclk = i9xx_get_refclk(crtc, num_connectors);
5080 * Returns a set of divisors for the desired target clock with
5081 * the given refclk, or FALSE. The returned values represent
5082 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5085 limit = intel_limit(crtc, refclk);
5086 ok = dev_priv->display.find_dpll(limit, crtc,
5087 intel_crtc->config.port_clock,
5088 refclk, NULL, &clock);
5090 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5094 if (is_lvds && dev_priv->lvds_downclock_avail) {
5096 * Ensure we match the reduced clock's P to the target
5097 * clock. If the clocks don't match, we can't switch
5098 * the display clock by using the FP0/FP1. In such case
5099 * we will disable the LVDS downclock feature.
5102 dev_priv->display.find_dpll(limit, crtc,
5103 dev_priv->lvds_downclock,
5107 /* Compat-code for transition, will disappear. */
5108 intel_crtc->config.dpll.n = clock.n;
5109 intel_crtc->config.dpll.m1 = clock.m1;
5110 intel_crtc->config.dpll.m2 = clock.m2;
5111 intel_crtc->config.dpll.p1 = clock.p1;
5112 intel_crtc->config.dpll.p2 = clock.p2;
5116 i8xx_update_pll(intel_crtc,
5117 has_reduced_clock ? &reduced_clock : NULL,
5119 } else if (IS_VALLEYVIEW(dev)) {
5120 vlv_update_pll(intel_crtc);
5122 i9xx_update_pll(intel_crtc,
5123 has_reduced_clock ? &reduced_clock : NULL,
5128 /* Set up the display plane register */
5129 dspcntr = DISPPLANE_GAMMA_ENABLE;
5131 if (!IS_VALLEYVIEW(dev)) {
5133 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5135 dspcntr |= DISPPLANE_SEL_PIPE_B;
5138 intel_set_pipe_timings(intel_crtc);
5140 /* pipesrc and dspsize control the size that is scaled from,
5141 * which should always be the user's requested size.
5143 I915_WRITE(DSPSIZE(plane),
5144 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5145 (intel_crtc->config.pipe_src_w - 1));
5146 I915_WRITE(DSPPOS(plane), 0);
5148 i9xx_set_pipeconf(intel_crtc);
5150 I915_WRITE(DSPCNTR(plane), dspcntr);
5151 POSTING_READ(DSPCNTR(plane));
5153 ret = intel_pipe_set_base(crtc, x, y, fb);
5158 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5159 struct intel_crtc_config *pipe_config)
5161 struct drm_device *dev = crtc->base.dev;
5162 struct drm_i915_private *dev_priv = dev->dev_private;
5165 tmp = I915_READ(PFIT_CONTROL);
5166 if (!(tmp & PFIT_ENABLE))
5169 /* Check whether the pfit is attached to our pipe. */
5170 if (INTEL_INFO(dev)->gen < 4) {
5171 if (crtc->pipe != PIPE_B)
5174 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5178 pipe_config->gmch_pfit.control = tmp;
5179 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5180 if (INTEL_INFO(dev)->gen < 5)
5181 pipe_config->gmch_pfit.lvds_border_bits =
5182 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5185 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5186 struct intel_crtc_config *pipe_config)
5188 struct drm_device *dev = crtc->base.dev;
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 int pipe = pipe_config->cpu_transcoder;
5191 intel_clock_t clock;
5193 int refclk = 100000;
5195 mutex_lock(&dev_priv->dpio_lock);
5196 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5197 mutex_unlock(&dev_priv->dpio_lock);
5199 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5200 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5201 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5202 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5203 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5205 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5206 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
5208 pipe_config->port_clock = clock.dot / 10;
5211 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5212 struct intel_crtc_config *pipe_config)
5214 struct drm_device *dev = crtc->base.dev;
5215 struct drm_i915_private *dev_priv = dev->dev_private;
5218 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5219 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5221 tmp = I915_READ(PIPECONF(crtc->pipe));
5222 if (!(tmp & PIPECONF_ENABLE))
5225 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5226 switch (tmp & PIPECONF_BPC_MASK) {
5228 pipe_config->pipe_bpp = 18;
5231 pipe_config->pipe_bpp = 24;
5233 case PIPECONF_10BPC:
5234 pipe_config->pipe_bpp = 30;
5241 if (INTEL_INFO(dev)->gen < 4)
5242 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5244 intel_get_pipe_timings(crtc, pipe_config);
5246 i9xx_get_pfit_config(crtc, pipe_config);
5248 if (INTEL_INFO(dev)->gen >= 4) {
5249 tmp = I915_READ(DPLL_MD(crtc->pipe));
5250 pipe_config->pixel_multiplier =
5251 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5252 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5253 pipe_config->dpll_hw_state.dpll_md = tmp;
5254 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5255 tmp = I915_READ(DPLL(crtc->pipe));
5256 pipe_config->pixel_multiplier =
5257 ((tmp & SDVO_MULTIPLIER_MASK)
5258 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5260 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5261 * port and will be fixed up in the encoder->get_config
5263 pipe_config->pixel_multiplier = 1;
5265 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5266 if (!IS_VALLEYVIEW(dev)) {
5267 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5268 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5270 /* Mask out read-only status bits. */
5271 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5272 DPLL_PORTC_READY_MASK |
5273 DPLL_PORTB_READY_MASK);
5276 if (IS_VALLEYVIEW(dev))
5277 vlv_crtc_clock_get(crtc, pipe_config);
5279 i9xx_crtc_clock_get(crtc, pipe_config);
5284 static void ironlake_init_pch_refclk(struct drm_device *dev)
5286 struct drm_i915_private *dev_priv = dev->dev_private;
5287 struct drm_mode_config *mode_config = &dev->mode_config;
5288 struct intel_encoder *encoder;
5290 bool has_lvds = false;
5291 bool has_cpu_edp = false;
5292 bool has_panel = false;
5293 bool has_ck505 = false;
5294 bool can_ssc = false;
5296 /* We need to take the global config into account */
5297 list_for_each_entry(encoder, &mode_config->encoder_list,
5299 switch (encoder->type) {
5300 case INTEL_OUTPUT_LVDS:
5304 case INTEL_OUTPUT_EDP:
5306 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5312 if (HAS_PCH_IBX(dev)) {
5313 has_ck505 = dev_priv->vbt.display_clock_mode;
5314 can_ssc = has_ck505;
5320 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5321 has_panel, has_lvds, has_ck505);
5323 /* Ironlake: try to setup display ref clock before DPLL
5324 * enabling. This is only under driver's control after
5325 * PCH B stepping, previous chipset stepping should be
5326 * ignoring this setting.
5328 val = I915_READ(PCH_DREF_CONTROL);
5330 /* As we must carefully and slowly disable/enable each source in turn,
5331 * compute the final state we want first and check if we need to
5332 * make any changes at all.
5335 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5337 final |= DREF_NONSPREAD_CK505_ENABLE;
5339 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5341 final &= ~DREF_SSC_SOURCE_MASK;
5342 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5343 final &= ~DREF_SSC1_ENABLE;
5346 final |= DREF_SSC_SOURCE_ENABLE;
5348 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5349 final |= DREF_SSC1_ENABLE;
5352 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5353 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5355 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5357 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5359 final |= DREF_SSC_SOURCE_DISABLE;
5360 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5366 /* Always enable nonspread source */
5367 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5370 val |= DREF_NONSPREAD_CK505_ENABLE;
5372 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5375 val &= ~DREF_SSC_SOURCE_MASK;
5376 val |= DREF_SSC_SOURCE_ENABLE;
5378 /* SSC must be turned on before enabling the CPU output */
5379 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5380 DRM_DEBUG_KMS("Using SSC on panel\n");
5381 val |= DREF_SSC1_ENABLE;
5383 val &= ~DREF_SSC1_ENABLE;
5385 /* Get SSC going before enabling the outputs */
5386 I915_WRITE(PCH_DREF_CONTROL, val);
5387 POSTING_READ(PCH_DREF_CONTROL);
5390 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5392 /* Enable CPU source on CPU attached eDP */
5394 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5395 DRM_DEBUG_KMS("Using SSC on eDP\n");
5396 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5399 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5401 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5403 I915_WRITE(PCH_DREF_CONTROL, val);
5404 POSTING_READ(PCH_DREF_CONTROL);
5407 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5409 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5411 /* Turn off CPU output */
5412 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5414 I915_WRITE(PCH_DREF_CONTROL, val);
5415 POSTING_READ(PCH_DREF_CONTROL);
5418 /* Turn off the SSC source */
5419 val &= ~DREF_SSC_SOURCE_MASK;
5420 val |= DREF_SSC_SOURCE_DISABLE;
5423 val &= ~DREF_SSC1_ENABLE;
5425 I915_WRITE(PCH_DREF_CONTROL, val);
5426 POSTING_READ(PCH_DREF_CONTROL);
5430 BUG_ON(val != final);
5433 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5437 tmp = I915_READ(SOUTH_CHICKEN2);
5438 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5439 I915_WRITE(SOUTH_CHICKEN2, tmp);
5441 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5442 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5443 DRM_ERROR("FDI mPHY reset assert timeout\n");
5445 tmp = I915_READ(SOUTH_CHICKEN2);
5446 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5447 I915_WRITE(SOUTH_CHICKEN2, tmp);
5449 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5450 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5451 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5454 /* WaMPhyProgramming:hsw */
5455 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5459 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5460 tmp &= ~(0xFF << 24);
5461 tmp |= (0x12 << 24);
5462 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5464 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5466 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5468 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5470 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5472 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5473 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5474 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5476 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5477 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5478 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5480 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5483 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5485 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5488 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5490 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5493 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5495 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5498 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5500 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5501 tmp &= ~(0xFF << 16);
5502 tmp |= (0x1C << 16);
5503 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5505 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5506 tmp &= ~(0xFF << 16);
5507 tmp |= (0x1C << 16);
5508 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5510 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5512 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5514 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5516 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5518 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5519 tmp &= ~(0xF << 28);
5521 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5523 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5524 tmp &= ~(0xF << 28);
5526 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5529 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5530 * Programming" based on the parameters passed:
5531 * - Sequence to enable CLKOUT_DP
5532 * - Sequence to enable CLKOUT_DP without spread
5533 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5535 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5538 struct drm_i915_private *dev_priv = dev->dev_private;
5541 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5543 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5544 with_fdi, "LP PCH doesn't have FDI\n"))
5547 mutex_lock(&dev_priv->dpio_lock);
5549 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5550 tmp &= ~SBI_SSCCTL_DISABLE;
5551 tmp |= SBI_SSCCTL_PATHALT;
5552 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5557 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5558 tmp &= ~SBI_SSCCTL_PATHALT;
5559 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5562 lpt_reset_fdi_mphy(dev_priv);
5563 lpt_program_fdi_mphy(dev_priv);
5567 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5568 SBI_GEN0 : SBI_DBUFF0;
5569 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5570 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5571 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5573 mutex_unlock(&dev_priv->dpio_lock);
5576 /* Sequence to disable CLKOUT_DP */
5577 static void lpt_disable_clkout_dp(struct drm_device *dev)
5579 struct drm_i915_private *dev_priv = dev->dev_private;
5582 mutex_lock(&dev_priv->dpio_lock);
5584 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5585 SBI_GEN0 : SBI_DBUFF0;
5586 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5587 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5588 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5590 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5591 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5592 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5593 tmp |= SBI_SSCCTL_PATHALT;
5594 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5597 tmp |= SBI_SSCCTL_DISABLE;
5598 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5601 mutex_unlock(&dev_priv->dpio_lock);
5604 static void lpt_init_pch_refclk(struct drm_device *dev)
5606 struct drm_mode_config *mode_config = &dev->mode_config;
5607 struct intel_encoder *encoder;
5608 bool has_vga = false;
5610 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5611 switch (encoder->type) {
5612 case INTEL_OUTPUT_ANALOG:
5619 lpt_enable_clkout_dp(dev, true, true);
5621 lpt_disable_clkout_dp(dev);
5625 * Initialize reference clocks when the driver loads
5627 void intel_init_pch_refclk(struct drm_device *dev)
5629 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5630 ironlake_init_pch_refclk(dev);
5631 else if (HAS_PCH_LPT(dev))
5632 lpt_init_pch_refclk(dev);
5635 static int ironlake_get_refclk(struct drm_crtc *crtc)
5637 struct drm_device *dev = crtc->dev;
5638 struct drm_i915_private *dev_priv = dev->dev_private;
5639 struct intel_encoder *encoder;
5640 int num_connectors = 0;
5641 bool is_lvds = false;
5643 for_each_encoder_on_crtc(dev, crtc, encoder) {
5644 switch (encoder->type) {
5645 case INTEL_OUTPUT_LVDS:
5652 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5653 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5654 dev_priv->vbt.lvds_ssc_freq);
5655 return dev_priv->vbt.lvds_ssc_freq * 1000;
5661 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5663 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5665 int pipe = intel_crtc->pipe;
5670 switch (intel_crtc->config.pipe_bpp) {
5672 val |= PIPECONF_6BPC;
5675 val |= PIPECONF_8BPC;
5678 val |= PIPECONF_10BPC;
5681 val |= PIPECONF_12BPC;
5684 /* Case prevented by intel_choose_pipe_bpp_dither. */
5688 if (intel_crtc->config.dither)
5689 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5691 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5692 val |= PIPECONF_INTERLACED_ILK;
5694 val |= PIPECONF_PROGRESSIVE;
5696 if (intel_crtc->config.limited_color_range)
5697 val |= PIPECONF_COLOR_RANGE_SELECT;
5699 I915_WRITE(PIPECONF(pipe), val);
5700 POSTING_READ(PIPECONF(pipe));
5704 * Set up the pipe CSC unit.
5706 * Currently only full range RGB to limited range RGB conversion
5707 * is supported, but eventually this should handle various
5708 * RGB<->YCbCr scenarios as well.
5710 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5712 struct drm_device *dev = crtc->dev;
5713 struct drm_i915_private *dev_priv = dev->dev_private;
5714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5715 int pipe = intel_crtc->pipe;
5716 uint16_t coeff = 0x7800; /* 1.0 */
5719 * TODO: Check what kind of values actually come out of the pipe
5720 * with these coeff/postoff values and adjust to get the best
5721 * accuracy. Perhaps we even need to take the bpc value into
5725 if (intel_crtc->config.limited_color_range)
5726 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5729 * GY/GU and RY/RU should be the other way around according
5730 * to BSpec, but reality doesn't agree. Just set them up in
5731 * a way that results in the correct picture.
5733 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5734 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5736 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5737 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5739 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5740 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5742 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5743 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5744 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5746 if (INTEL_INFO(dev)->gen > 6) {
5747 uint16_t postoff = 0;
5749 if (intel_crtc->config.limited_color_range)
5750 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5752 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5753 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5754 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5756 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5758 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5760 if (intel_crtc->config.limited_color_range)
5761 mode |= CSC_BLACK_SCREEN_OFFSET;
5763 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5767 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5769 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5771 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5776 if (intel_crtc->config.dither)
5777 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5779 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5780 val |= PIPECONF_INTERLACED_ILK;
5782 val |= PIPECONF_PROGRESSIVE;
5784 I915_WRITE(PIPECONF(cpu_transcoder), val);
5785 POSTING_READ(PIPECONF(cpu_transcoder));
5787 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5788 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5791 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5792 intel_clock_t *clock,
5793 bool *has_reduced_clock,
5794 intel_clock_t *reduced_clock)
5796 struct drm_device *dev = crtc->dev;
5797 struct drm_i915_private *dev_priv = dev->dev_private;
5798 struct intel_encoder *intel_encoder;
5800 const intel_limit_t *limit;
5801 bool ret, is_lvds = false;
5803 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5804 switch (intel_encoder->type) {
5805 case INTEL_OUTPUT_LVDS:
5811 refclk = ironlake_get_refclk(crtc);
5814 * Returns a set of divisors for the desired target clock with the given
5815 * refclk, or FALSE. The returned values represent the clock equation:
5816 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5818 limit = intel_limit(crtc, refclk);
5819 ret = dev_priv->display.find_dpll(limit, crtc,
5820 to_intel_crtc(crtc)->config.port_clock,
5821 refclk, NULL, clock);
5825 if (is_lvds && dev_priv->lvds_downclock_avail) {
5827 * Ensure we match the reduced clock's P to the target clock.
5828 * If the clocks don't match, we can't switch the display clock
5829 * by using the FP0/FP1. In such case we will disable the LVDS
5830 * downclock feature.
5832 *has_reduced_clock =
5833 dev_priv->display.find_dpll(limit, crtc,
5834 dev_priv->lvds_downclock,
5842 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5844 struct drm_i915_private *dev_priv = dev->dev_private;
5847 temp = I915_READ(SOUTH_CHICKEN1);
5848 if (temp & FDI_BC_BIFURCATION_SELECT)
5851 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5852 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5854 temp |= FDI_BC_BIFURCATION_SELECT;
5855 DRM_DEBUG_KMS("enabling fdi C rx\n");
5856 I915_WRITE(SOUTH_CHICKEN1, temp);
5857 POSTING_READ(SOUTH_CHICKEN1);
5860 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5862 struct drm_device *dev = intel_crtc->base.dev;
5863 struct drm_i915_private *dev_priv = dev->dev_private;
5865 switch (intel_crtc->pipe) {
5869 if (intel_crtc->config.fdi_lanes > 2)
5870 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5872 cpt_enable_fdi_bc_bifurcation(dev);
5876 cpt_enable_fdi_bc_bifurcation(dev);
5884 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5887 * Account for spread spectrum to avoid
5888 * oversubscribing the link. Max center spread
5889 * is 2.5%; use 5% for safety's sake.
5891 u32 bps = target_clock * bpp * 21 / 20;
5892 return bps / (link_bw * 8) + 1;
5895 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5897 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5900 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5902 intel_clock_t *reduced_clock, u32 *fp2)
5904 struct drm_crtc *crtc = &intel_crtc->base;
5905 struct drm_device *dev = crtc->dev;
5906 struct drm_i915_private *dev_priv = dev->dev_private;
5907 struct intel_encoder *intel_encoder;
5909 int factor, num_connectors = 0;
5910 bool is_lvds = false, is_sdvo = false;
5912 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5913 switch (intel_encoder->type) {
5914 case INTEL_OUTPUT_LVDS:
5917 case INTEL_OUTPUT_SDVO:
5918 case INTEL_OUTPUT_HDMI:
5926 /* Enable autotuning of the PLL clock (if permissible) */
5929 if ((intel_panel_use_ssc(dev_priv) &&
5930 dev_priv->vbt.lvds_ssc_freq == 100) ||
5931 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5933 } else if (intel_crtc->config.sdvo_tv_clock)
5936 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5939 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5945 dpll |= DPLLB_MODE_LVDS;
5947 dpll |= DPLLB_MODE_DAC_SERIAL;
5949 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5950 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5953 dpll |= DPLL_SDVO_HIGH_SPEED;
5954 if (intel_crtc->config.has_dp_encoder)
5955 dpll |= DPLL_SDVO_HIGH_SPEED;
5957 /* compute bitmask from p1 value */
5958 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5960 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5962 switch (intel_crtc->config.dpll.p2) {
5964 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5967 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5970 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5973 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5977 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5978 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5980 dpll |= PLL_REF_INPUT_DREFCLK;
5982 return dpll | DPLL_VCO_ENABLE;
5985 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5987 struct drm_framebuffer *fb)
5989 struct drm_device *dev = crtc->dev;
5990 struct drm_i915_private *dev_priv = dev->dev_private;
5991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5992 int pipe = intel_crtc->pipe;
5993 int plane = intel_crtc->plane;
5994 int num_connectors = 0;
5995 intel_clock_t clock, reduced_clock;
5996 u32 dpll = 0, fp = 0, fp2 = 0;
5997 bool ok, has_reduced_clock = false;
5998 bool is_lvds = false;
5999 struct intel_encoder *encoder;
6000 struct intel_shared_dpll *pll;
6003 for_each_encoder_on_crtc(dev, crtc, encoder) {
6004 switch (encoder->type) {
6005 case INTEL_OUTPUT_LVDS:
6013 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6014 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6016 ok = ironlake_compute_clocks(crtc, &clock,
6017 &has_reduced_clock, &reduced_clock);
6018 if (!ok && !intel_crtc->config.clock_set) {
6019 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6022 /* Compat-code for transition, will disappear. */
6023 if (!intel_crtc->config.clock_set) {
6024 intel_crtc->config.dpll.n = clock.n;
6025 intel_crtc->config.dpll.m1 = clock.m1;
6026 intel_crtc->config.dpll.m2 = clock.m2;
6027 intel_crtc->config.dpll.p1 = clock.p1;
6028 intel_crtc->config.dpll.p2 = clock.p2;
6031 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6032 if (intel_crtc->config.has_pch_encoder) {
6033 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6034 if (has_reduced_clock)
6035 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6037 dpll = ironlake_compute_dpll(intel_crtc,
6038 &fp, &reduced_clock,
6039 has_reduced_clock ? &fp2 : NULL);
6041 intel_crtc->config.dpll_hw_state.dpll = dpll;
6042 intel_crtc->config.dpll_hw_state.fp0 = fp;
6043 if (has_reduced_clock)
6044 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6046 intel_crtc->config.dpll_hw_state.fp1 = fp;
6048 pll = intel_get_shared_dpll(intel_crtc);
6050 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6055 intel_put_shared_dpll(intel_crtc);
6057 if (intel_crtc->config.has_dp_encoder)
6058 intel_dp_set_m_n(intel_crtc);
6060 if (is_lvds && has_reduced_clock && i915_powersave)
6061 intel_crtc->lowfreq_avail = true;
6063 intel_crtc->lowfreq_avail = false;
6065 if (intel_crtc->config.has_pch_encoder) {
6066 pll = intel_crtc_to_shared_dpll(intel_crtc);
6070 intel_set_pipe_timings(intel_crtc);
6072 if (intel_crtc->config.has_pch_encoder) {
6073 intel_cpu_transcoder_set_m_n(intel_crtc,
6074 &intel_crtc->config.fdi_m_n);
6077 if (IS_IVYBRIDGE(dev))
6078 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
6080 ironlake_set_pipeconf(crtc);
6082 /* Set up the display plane register */
6083 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6084 POSTING_READ(DSPCNTR(plane));
6086 ret = intel_pipe_set_base(crtc, x, y, fb);
6091 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6092 struct intel_link_m_n *m_n)
6094 struct drm_device *dev = crtc->base.dev;
6095 struct drm_i915_private *dev_priv = dev->dev_private;
6096 enum pipe pipe = crtc->pipe;
6098 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6099 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6100 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6102 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6103 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6104 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6107 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6108 enum transcoder transcoder,
6109 struct intel_link_m_n *m_n)
6111 struct drm_device *dev = crtc->base.dev;
6112 struct drm_i915_private *dev_priv = dev->dev_private;
6113 enum pipe pipe = crtc->pipe;
6115 if (INTEL_INFO(dev)->gen >= 5) {
6116 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6117 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6118 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6120 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6121 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6122 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6124 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6125 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6126 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6128 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6129 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6130 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6134 void intel_dp_get_m_n(struct intel_crtc *crtc,
6135 struct intel_crtc_config *pipe_config)
6137 if (crtc->config.has_pch_encoder)
6138 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6140 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6141 &pipe_config->dp_m_n);
6144 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6145 struct intel_crtc_config *pipe_config)
6147 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6148 &pipe_config->fdi_m_n);
6151 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6152 struct intel_crtc_config *pipe_config)
6154 struct drm_device *dev = crtc->base.dev;
6155 struct drm_i915_private *dev_priv = dev->dev_private;
6158 tmp = I915_READ(PF_CTL(crtc->pipe));
6160 if (tmp & PF_ENABLE) {
6161 pipe_config->pch_pfit.enabled = true;
6162 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6163 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6165 /* We currently do not free assignements of panel fitters on
6166 * ivb/hsw (since we don't use the higher upscaling modes which
6167 * differentiates them) so just WARN about this case for now. */
6169 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6170 PF_PIPE_SEL_IVB(crtc->pipe));
6175 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6176 struct intel_crtc_config *pipe_config)
6178 struct drm_device *dev = crtc->base.dev;
6179 struct drm_i915_private *dev_priv = dev->dev_private;
6182 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6183 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6185 tmp = I915_READ(PIPECONF(crtc->pipe));
6186 if (!(tmp & PIPECONF_ENABLE))
6189 switch (tmp & PIPECONF_BPC_MASK) {
6191 pipe_config->pipe_bpp = 18;
6194 pipe_config->pipe_bpp = 24;
6196 case PIPECONF_10BPC:
6197 pipe_config->pipe_bpp = 30;
6199 case PIPECONF_12BPC:
6200 pipe_config->pipe_bpp = 36;
6206 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6207 struct intel_shared_dpll *pll;
6209 pipe_config->has_pch_encoder = true;
6211 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6212 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6213 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6215 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6217 if (HAS_PCH_IBX(dev_priv->dev)) {
6218 pipe_config->shared_dpll =
6219 (enum intel_dpll_id) crtc->pipe;
6221 tmp = I915_READ(PCH_DPLL_SEL);
6222 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6223 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6225 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6228 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6230 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6231 &pipe_config->dpll_hw_state));
6233 tmp = pipe_config->dpll_hw_state.dpll;
6234 pipe_config->pixel_multiplier =
6235 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6236 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6238 ironlake_pch_clock_get(crtc, pipe_config);
6240 pipe_config->pixel_multiplier = 1;
6243 intel_get_pipe_timings(crtc, pipe_config);
6245 ironlake_get_pfit_config(crtc, pipe_config);
6250 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6252 struct drm_device *dev = dev_priv->dev;
6253 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6254 struct intel_crtc *crtc;
6255 unsigned long irqflags;
6258 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6259 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6260 pipe_name(crtc->pipe));
6262 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6263 WARN(plls->spll_refcount, "SPLL enabled\n");
6264 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6265 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6266 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6267 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6268 "CPU PWM1 enabled\n");
6269 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6270 "CPU PWM2 enabled\n");
6271 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6272 "PCH PWM1 enabled\n");
6273 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6274 "Utility pin enabled\n");
6275 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6277 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6278 val = I915_READ(DEIMR);
6279 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6280 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6281 val = I915_READ(SDEIMR);
6282 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6283 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6284 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6288 * This function implements pieces of two sequences from BSpec:
6289 * - Sequence for display software to disable LCPLL
6290 * - Sequence for display software to allow package C8+
6291 * The steps implemented here are just the steps that actually touch the LCPLL
6292 * register. Callers should take care of disabling all the display engine
6293 * functions, doing the mode unset, fixing interrupts, etc.
6295 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6296 bool switch_to_fclk, bool allow_power_down)
6300 assert_can_disable_lcpll(dev_priv);
6302 val = I915_READ(LCPLL_CTL);
6304 if (switch_to_fclk) {
6305 val |= LCPLL_CD_SOURCE_FCLK;
6306 I915_WRITE(LCPLL_CTL, val);
6308 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6309 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6310 DRM_ERROR("Switching to FCLK failed\n");
6312 val = I915_READ(LCPLL_CTL);
6315 val |= LCPLL_PLL_DISABLE;
6316 I915_WRITE(LCPLL_CTL, val);
6317 POSTING_READ(LCPLL_CTL);
6319 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6320 DRM_ERROR("LCPLL still locked\n");
6322 val = I915_READ(D_COMP);
6323 val |= D_COMP_COMP_DISABLE;
6324 mutex_lock(&dev_priv->rps.hw_lock);
6325 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6326 DRM_ERROR("Failed to disable D_COMP\n");
6327 mutex_unlock(&dev_priv->rps.hw_lock);
6328 POSTING_READ(D_COMP);
6331 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6332 DRM_ERROR("D_COMP RCOMP still in progress\n");
6334 if (allow_power_down) {
6335 val = I915_READ(LCPLL_CTL);
6336 val |= LCPLL_POWER_DOWN_ALLOW;
6337 I915_WRITE(LCPLL_CTL, val);
6338 POSTING_READ(LCPLL_CTL);
6343 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6346 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6350 val = I915_READ(LCPLL_CTL);
6352 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6353 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6356 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6357 * we'll hang the machine! */
6358 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6360 if (val & LCPLL_POWER_DOWN_ALLOW) {
6361 val &= ~LCPLL_POWER_DOWN_ALLOW;
6362 I915_WRITE(LCPLL_CTL, val);
6363 POSTING_READ(LCPLL_CTL);
6366 val = I915_READ(D_COMP);
6367 val |= D_COMP_COMP_FORCE;
6368 val &= ~D_COMP_COMP_DISABLE;
6369 mutex_lock(&dev_priv->rps.hw_lock);
6370 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6371 DRM_ERROR("Failed to enable D_COMP\n");
6372 mutex_unlock(&dev_priv->rps.hw_lock);
6373 POSTING_READ(D_COMP);
6375 val = I915_READ(LCPLL_CTL);
6376 val &= ~LCPLL_PLL_DISABLE;
6377 I915_WRITE(LCPLL_CTL, val);
6379 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6380 DRM_ERROR("LCPLL not locked yet\n");
6382 if (val & LCPLL_CD_SOURCE_FCLK) {
6383 val = I915_READ(LCPLL_CTL);
6384 val &= ~LCPLL_CD_SOURCE_FCLK;
6385 I915_WRITE(LCPLL_CTL, val);
6387 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6388 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6389 DRM_ERROR("Switching back to LCPLL failed\n");
6392 dev_priv->uncore.funcs.force_wake_put(dev_priv);
6395 void hsw_enable_pc8_work(struct work_struct *__work)
6397 struct drm_i915_private *dev_priv =
6398 container_of(to_delayed_work(__work), struct drm_i915_private,
6400 struct drm_device *dev = dev_priv->dev;
6403 if (dev_priv->pc8.enabled)
6406 DRM_DEBUG_KMS("Enabling package C8+\n");
6408 dev_priv->pc8.enabled = true;
6410 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6411 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6412 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6413 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6416 lpt_disable_clkout_dp(dev);
6417 hsw_pc8_disable_interrupts(dev);
6418 hsw_disable_lcpll(dev_priv, true, true);
6421 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6423 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6424 WARN(dev_priv->pc8.disable_count < 1,
6425 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6427 dev_priv->pc8.disable_count--;
6428 if (dev_priv->pc8.disable_count != 0)
6431 schedule_delayed_work(&dev_priv->pc8.enable_work,
6432 msecs_to_jiffies(i915_pc8_timeout));
6435 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6437 struct drm_device *dev = dev_priv->dev;
6440 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6441 WARN(dev_priv->pc8.disable_count < 0,
6442 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6444 dev_priv->pc8.disable_count++;
6445 if (dev_priv->pc8.disable_count != 1)
6448 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6449 if (!dev_priv->pc8.enabled)
6452 DRM_DEBUG_KMS("Disabling package C8+\n");
6454 hsw_restore_lcpll(dev_priv);
6455 hsw_pc8_restore_interrupts(dev);
6456 lpt_init_pch_refclk(dev);
6458 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6459 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6460 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6461 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6464 intel_prepare_ddi(dev);
6465 i915_gem_init_swizzling(dev);
6466 mutex_lock(&dev_priv->rps.hw_lock);
6467 gen6_update_ring_freq(dev);
6468 mutex_unlock(&dev_priv->rps.hw_lock);
6469 dev_priv->pc8.enabled = false;
6472 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6474 mutex_lock(&dev_priv->pc8.lock);
6475 __hsw_enable_package_c8(dev_priv);
6476 mutex_unlock(&dev_priv->pc8.lock);
6479 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6481 mutex_lock(&dev_priv->pc8.lock);
6482 __hsw_disable_package_c8(dev_priv);
6483 mutex_unlock(&dev_priv->pc8.lock);
6486 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6488 struct drm_device *dev = dev_priv->dev;
6489 struct intel_crtc *crtc;
6492 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6493 if (crtc->base.enabled)
6496 /* This case is still possible since we have the i915.disable_power_well
6497 * parameter and also the KVMr or something else might be requesting the
6499 val = I915_READ(HSW_PWR_WELL_DRIVER);
6501 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6508 /* Since we're called from modeset_global_resources there's no way to
6509 * symmetrically increase and decrease the refcount, so we use
6510 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6513 static void hsw_update_package_c8(struct drm_device *dev)
6515 struct drm_i915_private *dev_priv = dev->dev_private;
6518 if (!i915_enable_pc8)
6521 mutex_lock(&dev_priv->pc8.lock);
6523 allow = hsw_can_enable_package_c8(dev_priv);
6525 if (allow == dev_priv->pc8.requirements_met)
6528 dev_priv->pc8.requirements_met = allow;
6531 __hsw_enable_package_c8(dev_priv);
6533 __hsw_disable_package_c8(dev_priv);
6536 mutex_unlock(&dev_priv->pc8.lock);
6539 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6541 if (!dev_priv->pc8.gpu_idle) {
6542 dev_priv->pc8.gpu_idle = true;
6543 hsw_enable_package_c8(dev_priv);
6547 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6549 if (dev_priv->pc8.gpu_idle) {
6550 dev_priv->pc8.gpu_idle = false;
6551 hsw_disable_package_c8(dev_priv);
6555 static void haswell_modeset_global_resources(struct drm_device *dev)
6557 bool enable = false;
6558 struct intel_crtc *crtc;
6560 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6561 if (!crtc->base.enabled)
6564 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6565 crtc->config.cpu_transcoder != TRANSCODER_EDP)
6569 intel_set_power_well(dev, enable);
6571 hsw_update_package_c8(dev);
6574 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6576 struct drm_framebuffer *fb)
6578 struct drm_device *dev = crtc->dev;
6579 struct drm_i915_private *dev_priv = dev->dev_private;
6580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6581 int plane = intel_crtc->plane;
6584 if (!intel_ddi_pll_mode_set(crtc))
6587 if (intel_crtc->config.has_dp_encoder)
6588 intel_dp_set_m_n(intel_crtc);
6590 intel_crtc->lowfreq_avail = false;
6592 intel_set_pipe_timings(intel_crtc);
6594 if (intel_crtc->config.has_pch_encoder) {
6595 intel_cpu_transcoder_set_m_n(intel_crtc,
6596 &intel_crtc->config.fdi_m_n);
6599 haswell_set_pipeconf(crtc);
6601 intel_set_pipe_csc(crtc);
6603 /* Set up the display plane register */
6604 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6605 POSTING_READ(DSPCNTR(plane));
6607 ret = intel_pipe_set_base(crtc, x, y, fb);
6612 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6613 struct intel_crtc_config *pipe_config)
6615 struct drm_device *dev = crtc->base.dev;
6616 struct drm_i915_private *dev_priv = dev->dev_private;
6617 enum intel_display_power_domain pfit_domain;
6620 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6621 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6623 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6624 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6625 enum pipe trans_edp_pipe;
6626 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6628 WARN(1, "unknown pipe linked to edp transcoder\n");
6629 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6630 case TRANS_DDI_EDP_INPUT_A_ON:
6631 trans_edp_pipe = PIPE_A;
6633 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6634 trans_edp_pipe = PIPE_B;
6636 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6637 trans_edp_pipe = PIPE_C;
6641 if (trans_edp_pipe == crtc->pipe)
6642 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6645 if (!intel_display_power_enabled(dev,
6646 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6649 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6650 if (!(tmp & PIPECONF_ENABLE))
6654 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6655 * DDI E. So just check whether this pipe is wired to DDI E and whether
6656 * the PCH transcoder is on.
6658 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6659 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6660 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6661 pipe_config->has_pch_encoder = true;
6663 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6664 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6665 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6667 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6670 intel_get_pipe_timings(crtc, pipe_config);
6672 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6673 if (intel_display_power_enabled(dev, pfit_domain))
6674 ironlake_get_pfit_config(crtc, pipe_config);
6676 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6677 (I915_READ(IPS_CTL) & IPS_ENABLE);
6679 pipe_config->pixel_multiplier = 1;
6684 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6686 struct drm_framebuffer *fb)
6688 struct drm_device *dev = crtc->dev;
6689 struct drm_i915_private *dev_priv = dev->dev_private;
6690 struct intel_encoder *encoder;
6691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6692 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6693 int pipe = intel_crtc->pipe;
6696 drm_vblank_pre_modeset(dev, pipe);
6698 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6700 drm_vblank_post_modeset(dev, pipe);
6705 for_each_encoder_on_crtc(dev, crtc, encoder) {
6706 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6707 encoder->base.base.id,
6708 drm_get_encoder_name(&encoder->base),
6709 mode->base.id, mode->name);
6710 encoder->mode_set(encoder);
6716 static bool intel_eld_uptodate(struct drm_connector *connector,
6717 int reg_eldv, uint32_t bits_eldv,
6718 int reg_elda, uint32_t bits_elda,
6721 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6722 uint8_t *eld = connector->eld;
6725 i = I915_READ(reg_eldv);
6734 i = I915_READ(reg_elda);
6736 I915_WRITE(reg_elda, i);
6738 for (i = 0; i < eld[2]; i++)
6739 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6745 static void g4x_write_eld(struct drm_connector *connector,
6746 struct drm_crtc *crtc)
6748 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6749 uint8_t *eld = connector->eld;
6754 i = I915_READ(G4X_AUD_VID_DID);
6756 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6757 eldv = G4X_ELDV_DEVCL_DEVBLC;
6759 eldv = G4X_ELDV_DEVCTG;
6761 if (intel_eld_uptodate(connector,
6762 G4X_AUD_CNTL_ST, eldv,
6763 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6764 G4X_HDMIW_HDMIEDID))
6767 i = I915_READ(G4X_AUD_CNTL_ST);
6768 i &= ~(eldv | G4X_ELD_ADDR);
6769 len = (i >> 9) & 0x1f; /* ELD buffer size */
6770 I915_WRITE(G4X_AUD_CNTL_ST, i);
6775 len = min_t(uint8_t, eld[2], len);
6776 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6777 for (i = 0; i < len; i++)
6778 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6780 i = I915_READ(G4X_AUD_CNTL_ST);
6782 I915_WRITE(G4X_AUD_CNTL_ST, i);
6785 static void haswell_write_eld(struct drm_connector *connector,
6786 struct drm_crtc *crtc)
6788 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6789 uint8_t *eld = connector->eld;
6790 struct drm_device *dev = crtc->dev;
6791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6795 int pipe = to_intel_crtc(crtc)->pipe;
6798 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6799 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6800 int aud_config = HSW_AUD_CFG(pipe);
6801 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6804 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6806 /* Audio output enable */
6807 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6808 tmp = I915_READ(aud_cntrl_st2);
6809 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6810 I915_WRITE(aud_cntrl_st2, tmp);
6812 /* Wait for 1 vertical blank */
6813 intel_wait_for_vblank(dev, pipe);
6815 /* Set ELD valid state */
6816 tmp = I915_READ(aud_cntrl_st2);
6817 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6818 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6819 I915_WRITE(aud_cntrl_st2, tmp);
6820 tmp = I915_READ(aud_cntrl_st2);
6821 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6823 /* Enable HDMI mode */
6824 tmp = I915_READ(aud_config);
6825 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6826 /* clear N_programing_enable and N_value_index */
6827 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6828 I915_WRITE(aud_config, tmp);
6830 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6832 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6833 intel_crtc->eld_vld = true;
6835 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6836 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6837 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6838 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6840 I915_WRITE(aud_config, 0);
6842 if (intel_eld_uptodate(connector,
6843 aud_cntrl_st2, eldv,
6844 aud_cntl_st, IBX_ELD_ADDRESS,
6848 i = I915_READ(aud_cntrl_st2);
6850 I915_WRITE(aud_cntrl_st2, i);
6855 i = I915_READ(aud_cntl_st);
6856 i &= ~IBX_ELD_ADDRESS;
6857 I915_WRITE(aud_cntl_st, i);
6858 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6859 DRM_DEBUG_DRIVER("port num:%d\n", i);
6861 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6862 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6863 for (i = 0; i < len; i++)
6864 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6866 i = I915_READ(aud_cntrl_st2);
6868 I915_WRITE(aud_cntrl_st2, i);
6872 static void ironlake_write_eld(struct drm_connector *connector,
6873 struct drm_crtc *crtc)
6875 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6876 uint8_t *eld = connector->eld;
6884 int pipe = to_intel_crtc(crtc)->pipe;
6886 if (HAS_PCH_IBX(connector->dev)) {
6887 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6888 aud_config = IBX_AUD_CFG(pipe);
6889 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6890 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6892 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6893 aud_config = CPT_AUD_CFG(pipe);
6894 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6895 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6898 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6900 i = I915_READ(aud_cntl_st);
6901 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6903 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6904 /* operate blindly on all ports */
6905 eldv = IBX_ELD_VALIDB;
6906 eldv |= IBX_ELD_VALIDB << 4;
6907 eldv |= IBX_ELD_VALIDB << 8;
6909 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6910 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6913 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6914 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6915 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6916 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6918 I915_WRITE(aud_config, 0);
6920 if (intel_eld_uptodate(connector,
6921 aud_cntrl_st2, eldv,
6922 aud_cntl_st, IBX_ELD_ADDRESS,
6926 i = I915_READ(aud_cntrl_st2);
6928 I915_WRITE(aud_cntrl_st2, i);
6933 i = I915_READ(aud_cntl_st);
6934 i &= ~IBX_ELD_ADDRESS;
6935 I915_WRITE(aud_cntl_st, i);
6937 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6938 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6939 for (i = 0; i < len; i++)
6940 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6942 i = I915_READ(aud_cntrl_st2);
6944 I915_WRITE(aud_cntrl_st2, i);
6947 void intel_write_eld(struct drm_encoder *encoder,
6948 struct drm_display_mode *mode)
6950 struct drm_crtc *crtc = encoder->crtc;
6951 struct drm_connector *connector;
6952 struct drm_device *dev = encoder->dev;
6953 struct drm_i915_private *dev_priv = dev->dev_private;
6955 connector = drm_select_eld(encoder, mode);
6959 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6961 drm_get_connector_name(connector),
6962 connector->encoder->base.id,
6963 drm_get_encoder_name(connector->encoder));
6965 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6967 if (dev_priv->display.write_eld)
6968 dev_priv->display.write_eld(connector, crtc);
6971 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6973 struct drm_device *dev = crtc->dev;
6974 struct drm_i915_private *dev_priv = dev->dev_private;
6975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6976 bool visible = base != 0;
6979 if (intel_crtc->cursor_visible == visible)
6982 cntl = I915_READ(_CURACNTR);
6984 /* On these chipsets we can only modify the base whilst
6985 * the cursor is disabled.
6987 I915_WRITE(_CURABASE, base);
6989 cntl &= ~(CURSOR_FORMAT_MASK);
6990 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6991 cntl |= CURSOR_ENABLE |
6992 CURSOR_GAMMA_ENABLE |
6995 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6996 I915_WRITE(_CURACNTR, cntl);
6998 intel_crtc->cursor_visible = visible;
7001 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7003 struct drm_device *dev = crtc->dev;
7004 struct drm_i915_private *dev_priv = dev->dev_private;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7006 int pipe = intel_crtc->pipe;
7007 bool visible = base != 0;
7009 if (intel_crtc->cursor_visible != visible) {
7010 uint32_t cntl = I915_READ(CURCNTR(pipe));
7012 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7013 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7014 cntl |= pipe << 28; /* Connect to correct pipe */
7016 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7017 cntl |= CURSOR_MODE_DISABLE;
7019 I915_WRITE(CURCNTR(pipe), cntl);
7021 intel_crtc->cursor_visible = visible;
7023 /* and commit changes on next vblank */
7024 I915_WRITE(CURBASE(pipe), base);
7027 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7029 struct drm_device *dev = crtc->dev;
7030 struct drm_i915_private *dev_priv = dev->dev_private;
7031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7032 int pipe = intel_crtc->pipe;
7033 bool visible = base != 0;
7035 if (intel_crtc->cursor_visible != visible) {
7036 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7038 cntl &= ~CURSOR_MODE;
7039 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7041 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7042 cntl |= CURSOR_MODE_DISABLE;
7044 if (IS_HASWELL(dev)) {
7045 cntl |= CURSOR_PIPE_CSC_ENABLE;
7046 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7048 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7050 intel_crtc->cursor_visible = visible;
7052 /* and commit changes on next vblank */
7053 I915_WRITE(CURBASE_IVB(pipe), base);
7056 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7057 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7060 struct drm_device *dev = crtc->dev;
7061 struct drm_i915_private *dev_priv = dev->dev_private;
7062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7063 int pipe = intel_crtc->pipe;
7064 int x = intel_crtc->cursor_x;
7065 int y = intel_crtc->cursor_y;
7066 u32 base = 0, pos = 0;
7070 base = intel_crtc->cursor_addr;
7072 if (x >= intel_crtc->config.pipe_src_w)
7075 if (y >= intel_crtc->config.pipe_src_h)
7079 if (x + intel_crtc->cursor_width <= 0)
7082 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7085 pos |= x << CURSOR_X_SHIFT;
7088 if (y + intel_crtc->cursor_height <= 0)
7091 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7094 pos |= y << CURSOR_Y_SHIFT;
7096 visible = base != 0;
7097 if (!visible && !intel_crtc->cursor_visible)
7100 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7101 I915_WRITE(CURPOS_IVB(pipe), pos);
7102 ivb_update_cursor(crtc, base);
7104 I915_WRITE(CURPOS(pipe), pos);
7105 if (IS_845G(dev) || IS_I865G(dev))
7106 i845_update_cursor(crtc, base);
7108 i9xx_update_cursor(crtc, base);
7112 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7113 struct drm_file *file,
7115 uint32_t width, uint32_t height)
7117 struct drm_device *dev = crtc->dev;
7118 struct drm_i915_private *dev_priv = dev->dev_private;
7119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7120 struct drm_i915_gem_object *obj;
7124 /* if we want to turn off the cursor ignore width and height */
7126 DRM_DEBUG_KMS("cursor off\n");
7129 mutex_lock(&dev->struct_mutex);
7133 /* Currently we only support 64x64 cursors */
7134 if (width != 64 || height != 64) {
7135 DRM_ERROR("we currently only support 64x64 cursors\n");
7139 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7140 if (&obj->base == NULL)
7143 if (obj->base.size < width * height * 4) {
7144 DRM_ERROR("buffer is to small\n");
7149 /* we only need to pin inside GTT if cursor is non-phy */
7150 mutex_lock(&dev->struct_mutex);
7151 if (!dev_priv->info->cursor_needs_physical) {
7154 if (obj->tiling_mode) {
7155 DRM_ERROR("cursor cannot be tiled\n");
7160 /* Note that the w/a also requires 2 PTE of padding following
7161 * the bo. We currently fill all unused PTE with the shadow
7162 * page and so we should always have valid PTE following the
7163 * cursor preventing the VT-d warning.
7166 if (need_vtd_wa(dev))
7167 alignment = 64*1024;
7169 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7171 DRM_ERROR("failed to move cursor bo into the GTT\n");
7175 ret = i915_gem_object_put_fence(obj);
7177 DRM_ERROR("failed to release fence for cursor");
7181 addr = i915_gem_obj_ggtt_offset(obj);
7183 int align = IS_I830(dev) ? 16 * 1024 : 256;
7184 ret = i915_gem_attach_phys_object(dev, obj,
7185 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7188 DRM_ERROR("failed to attach phys object\n");
7191 addr = obj->phys_obj->handle->busaddr;
7195 I915_WRITE(CURSIZE, (height << 12) | width);
7198 if (intel_crtc->cursor_bo) {
7199 if (dev_priv->info->cursor_needs_physical) {
7200 if (intel_crtc->cursor_bo != obj)
7201 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7203 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7204 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7207 mutex_unlock(&dev->struct_mutex);
7209 intel_crtc->cursor_addr = addr;
7210 intel_crtc->cursor_bo = obj;
7211 intel_crtc->cursor_width = width;
7212 intel_crtc->cursor_height = height;
7214 if (intel_crtc->active)
7215 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7219 i915_gem_object_unpin_from_display_plane(obj);
7221 mutex_unlock(&dev->struct_mutex);
7223 drm_gem_object_unreference_unlocked(&obj->base);
7227 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7231 intel_crtc->cursor_x = x;
7232 intel_crtc->cursor_y = y;
7234 if (intel_crtc->active)
7235 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7240 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7241 u16 *blue, uint32_t start, uint32_t size)
7243 int end = (start + size > 256) ? 256 : start + size, i;
7244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7246 for (i = start; i < end; i++) {
7247 intel_crtc->lut_r[i] = red[i] >> 8;
7248 intel_crtc->lut_g[i] = green[i] >> 8;
7249 intel_crtc->lut_b[i] = blue[i] >> 8;
7252 intel_crtc_load_lut(crtc);
7255 /* VESA 640x480x72Hz mode to set on the pipe */
7256 static struct drm_display_mode load_detect_mode = {
7257 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7258 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7261 static struct drm_framebuffer *
7262 intel_framebuffer_create(struct drm_device *dev,
7263 struct drm_mode_fb_cmd2 *mode_cmd,
7264 struct drm_i915_gem_object *obj)
7266 struct intel_framebuffer *intel_fb;
7269 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7271 drm_gem_object_unreference_unlocked(&obj->base);
7272 return ERR_PTR(-ENOMEM);
7275 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7277 drm_gem_object_unreference_unlocked(&obj->base);
7279 return ERR_PTR(ret);
7282 return &intel_fb->base;
7286 intel_framebuffer_pitch_for_width(int width, int bpp)
7288 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7289 return ALIGN(pitch, 64);
7293 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7295 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7296 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7299 static struct drm_framebuffer *
7300 intel_framebuffer_create_for_mode(struct drm_device *dev,
7301 struct drm_display_mode *mode,
7304 struct drm_i915_gem_object *obj;
7305 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7307 obj = i915_gem_alloc_object(dev,
7308 intel_framebuffer_size_for_mode(mode, bpp));
7310 return ERR_PTR(-ENOMEM);
7312 mode_cmd.width = mode->hdisplay;
7313 mode_cmd.height = mode->vdisplay;
7314 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7316 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7318 return intel_framebuffer_create(dev, &mode_cmd, obj);
7321 static struct drm_framebuffer *
7322 mode_fits_in_fbdev(struct drm_device *dev,
7323 struct drm_display_mode *mode)
7325 struct drm_i915_private *dev_priv = dev->dev_private;
7326 struct drm_i915_gem_object *obj;
7327 struct drm_framebuffer *fb;
7329 if (dev_priv->fbdev == NULL)
7332 obj = dev_priv->fbdev->ifb.obj;
7336 fb = &dev_priv->fbdev->ifb.base;
7337 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7338 fb->bits_per_pixel))
7341 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7347 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7348 struct drm_display_mode *mode,
7349 struct intel_load_detect_pipe *old)
7351 struct intel_crtc *intel_crtc;
7352 struct intel_encoder *intel_encoder =
7353 intel_attached_encoder(connector);
7354 struct drm_crtc *possible_crtc;
7355 struct drm_encoder *encoder = &intel_encoder->base;
7356 struct drm_crtc *crtc = NULL;
7357 struct drm_device *dev = encoder->dev;
7358 struct drm_framebuffer *fb;
7361 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7362 connector->base.id, drm_get_connector_name(connector),
7363 encoder->base.id, drm_get_encoder_name(encoder));
7366 * Algorithm gets a little messy:
7368 * - if the connector already has an assigned crtc, use it (but make
7369 * sure it's on first)
7371 * - try to find the first unused crtc that can drive this connector,
7372 * and use that if we find one
7375 /* See if we already have a CRTC for this connector */
7376 if (encoder->crtc) {
7377 crtc = encoder->crtc;
7379 mutex_lock(&crtc->mutex);
7381 old->dpms_mode = connector->dpms;
7382 old->load_detect_temp = false;
7384 /* Make sure the crtc and connector are running */
7385 if (connector->dpms != DRM_MODE_DPMS_ON)
7386 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7391 /* Find an unused one (if possible) */
7392 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7394 if (!(encoder->possible_crtcs & (1 << i)))
7396 if (!possible_crtc->enabled) {
7397 crtc = possible_crtc;
7403 * If we didn't find an unused CRTC, don't use any.
7406 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7410 mutex_lock(&crtc->mutex);
7411 intel_encoder->new_crtc = to_intel_crtc(crtc);
7412 to_intel_connector(connector)->new_encoder = intel_encoder;
7414 intel_crtc = to_intel_crtc(crtc);
7415 old->dpms_mode = connector->dpms;
7416 old->load_detect_temp = true;
7417 old->release_fb = NULL;
7420 mode = &load_detect_mode;
7422 /* We need a framebuffer large enough to accommodate all accesses
7423 * that the plane may generate whilst we perform load detection.
7424 * We can not rely on the fbcon either being present (we get called
7425 * during its initialisation to detect all boot displays, or it may
7426 * not even exist) or that it is large enough to satisfy the
7429 fb = mode_fits_in_fbdev(dev, mode);
7431 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7432 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7433 old->release_fb = fb;
7435 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7437 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7438 mutex_unlock(&crtc->mutex);
7442 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7443 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7444 if (old->release_fb)
7445 old->release_fb->funcs->destroy(old->release_fb);
7446 mutex_unlock(&crtc->mutex);
7450 /* let the connector get through one full cycle before testing */
7451 intel_wait_for_vblank(dev, intel_crtc->pipe);
7455 void intel_release_load_detect_pipe(struct drm_connector *connector,
7456 struct intel_load_detect_pipe *old)
7458 struct intel_encoder *intel_encoder =
7459 intel_attached_encoder(connector);
7460 struct drm_encoder *encoder = &intel_encoder->base;
7461 struct drm_crtc *crtc = encoder->crtc;
7463 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7464 connector->base.id, drm_get_connector_name(connector),
7465 encoder->base.id, drm_get_encoder_name(encoder));
7467 if (old->load_detect_temp) {
7468 to_intel_connector(connector)->new_encoder = NULL;
7469 intel_encoder->new_crtc = NULL;
7470 intel_set_mode(crtc, NULL, 0, 0, NULL);
7472 if (old->release_fb) {
7473 drm_framebuffer_unregister_private(old->release_fb);
7474 drm_framebuffer_unreference(old->release_fb);
7477 mutex_unlock(&crtc->mutex);
7481 /* Switch crtc and encoder back off if necessary */
7482 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7483 connector->funcs->dpms(connector, old->dpms_mode);
7485 mutex_unlock(&crtc->mutex);
7488 static int i9xx_pll_refclk(struct drm_device *dev,
7489 const struct intel_crtc_config *pipe_config)
7491 struct drm_i915_private *dev_priv = dev->dev_private;
7492 u32 dpll = pipe_config->dpll_hw_state.dpll;
7494 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7495 return dev_priv->vbt.lvds_ssc_freq * 1000;
7496 else if (HAS_PCH_SPLIT(dev))
7498 else if (!IS_GEN2(dev))
7504 /* Returns the clock of the currently programmed mode of the given pipe. */
7505 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7506 struct intel_crtc_config *pipe_config)
7508 struct drm_device *dev = crtc->base.dev;
7509 struct drm_i915_private *dev_priv = dev->dev_private;
7510 int pipe = pipe_config->cpu_transcoder;
7511 u32 dpll = pipe_config->dpll_hw_state.dpll;
7513 intel_clock_t clock;
7514 int refclk = i9xx_pll_refclk(dev, pipe_config);
7516 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7517 fp = pipe_config->dpll_hw_state.fp0;
7519 fp = pipe_config->dpll_hw_state.fp1;
7521 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7522 if (IS_PINEVIEW(dev)) {
7523 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7524 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7526 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7527 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7530 if (!IS_GEN2(dev)) {
7531 if (IS_PINEVIEW(dev))
7532 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7533 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7535 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7536 DPLL_FPA01_P1_POST_DIV_SHIFT);
7538 switch (dpll & DPLL_MODE_MASK) {
7539 case DPLLB_MODE_DAC_SERIAL:
7540 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7543 case DPLLB_MODE_LVDS:
7544 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7548 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7549 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7553 if (IS_PINEVIEW(dev))
7554 pineview_clock(refclk, &clock);
7556 i9xx_clock(refclk, &clock);
7558 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7561 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7562 DPLL_FPA01_P1_POST_DIV_SHIFT);
7565 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7568 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7569 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7571 if (dpll & PLL_P2_DIVIDE_BY_4)
7577 i9xx_clock(refclk, &clock);
7581 * This value includes pixel_multiplier. We will use
7582 * port_clock to compute adjusted_mode.crtc_clock in the
7583 * encoder's get_config() function.
7585 pipe_config->port_clock = clock.dot;
7588 int intel_dotclock_calculate(int link_freq,
7589 const struct intel_link_m_n *m_n)
7592 * The calculation for the data clock is:
7593 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7594 * But we want to avoid losing precison if possible, so:
7595 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7597 * and the link clock is simpler:
7598 * link_clock = (m * link_clock) / n
7604 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7607 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7608 struct intel_crtc_config *pipe_config)
7610 struct drm_device *dev = crtc->base.dev;
7612 /* read out port_clock from the DPLL */
7613 i9xx_crtc_clock_get(crtc, pipe_config);
7616 * This value does not include pixel_multiplier.
7617 * We will check that port_clock and adjusted_mode.crtc_clock
7618 * agree once we know their relationship in the encoder's
7619 * get_config() function.
7621 pipe_config->adjusted_mode.crtc_clock =
7622 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7623 &pipe_config->fdi_m_n);
7626 /** Returns the currently programmed mode of the given pipe. */
7627 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7628 struct drm_crtc *crtc)
7630 struct drm_i915_private *dev_priv = dev->dev_private;
7631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7632 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7633 struct drm_display_mode *mode;
7634 struct intel_crtc_config pipe_config;
7635 int htot = I915_READ(HTOTAL(cpu_transcoder));
7636 int hsync = I915_READ(HSYNC(cpu_transcoder));
7637 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7638 int vsync = I915_READ(VSYNC(cpu_transcoder));
7639 enum pipe pipe = intel_crtc->pipe;
7641 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7646 * Construct a pipe_config sufficient for getting the clock info
7647 * back out of crtc_clock_get.
7649 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7650 * to use a real value here instead.
7652 pipe_config.cpu_transcoder = (enum transcoder) pipe;
7653 pipe_config.pixel_multiplier = 1;
7654 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7655 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7656 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7657 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7659 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
7660 mode->hdisplay = (htot & 0xffff) + 1;
7661 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7662 mode->hsync_start = (hsync & 0xffff) + 1;
7663 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7664 mode->vdisplay = (vtot & 0xffff) + 1;
7665 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7666 mode->vsync_start = (vsync & 0xffff) + 1;
7667 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7669 drm_mode_set_name(mode);
7674 static void intel_increase_pllclock(struct drm_crtc *crtc)
7676 struct drm_device *dev = crtc->dev;
7677 drm_i915_private_t *dev_priv = dev->dev_private;
7678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7679 int pipe = intel_crtc->pipe;
7680 int dpll_reg = DPLL(pipe);
7683 if (HAS_PCH_SPLIT(dev))
7686 if (!dev_priv->lvds_downclock_avail)
7689 dpll = I915_READ(dpll_reg);
7690 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7691 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7693 assert_panel_unlocked(dev_priv, pipe);
7695 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7696 I915_WRITE(dpll_reg, dpll);
7697 intel_wait_for_vblank(dev, pipe);
7699 dpll = I915_READ(dpll_reg);
7700 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7701 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7705 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7707 struct drm_device *dev = crtc->dev;
7708 drm_i915_private_t *dev_priv = dev->dev_private;
7709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7711 if (HAS_PCH_SPLIT(dev))
7714 if (!dev_priv->lvds_downclock_avail)
7718 * Since this is called by a timer, we should never get here in
7721 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7722 int pipe = intel_crtc->pipe;
7723 int dpll_reg = DPLL(pipe);
7726 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7728 assert_panel_unlocked(dev_priv, pipe);
7730 dpll = I915_READ(dpll_reg);
7731 dpll |= DISPLAY_RATE_SELECT_FPA1;
7732 I915_WRITE(dpll_reg, dpll);
7733 intel_wait_for_vblank(dev, pipe);
7734 dpll = I915_READ(dpll_reg);
7735 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7736 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7741 void intel_mark_busy(struct drm_device *dev)
7743 struct drm_i915_private *dev_priv = dev->dev_private;
7745 hsw_package_c8_gpu_busy(dev_priv);
7746 i915_update_gfx_val(dev_priv);
7749 void intel_mark_idle(struct drm_device *dev)
7751 struct drm_i915_private *dev_priv = dev->dev_private;
7752 struct drm_crtc *crtc;
7754 hsw_package_c8_gpu_idle(dev_priv);
7756 if (!i915_powersave)
7759 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7763 intel_decrease_pllclock(crtc);
7766 if (dev_priv->info->gen >= 6)
7767 gen6_rps_idle(dev->dev_private);
7770 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7771 struct intel_ring_buffer *ring)
7773 struct drm_device *dev = obj->base.dev;
7774 struct drm_crtc *crtc;
7776 if (!i915_powersave)
7779 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7783 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7786 intel_increase_pllclock(crtc);
7787 if (ring && intel_fbc_enabled(dev))
7788 ring->fbc_dirty = true;
7792 static void intel_crtc_destroy(struct drm_crtc *crtc)
7794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7795 struct drm_device *dev = crtc->dev;
7796 struct intel_unpin_work *work;
7797 unsigned long flags;
7799 spin_lock_irqsave(&dev->event_lock, flags);
7800 work = intel_crtc->unpin_work;
7801 intel_crtc->unpin_work = NULL;
7802 spin_unlock_irqrestore(&dev->event_lock, flags);
7805 cancel_work_sync(&work->work);
7809 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7811 drm_crtc_cleanup(crtc);
7816 static void intel_unpin_work_fn(struct work_struct *__work)
7818 struct intel_unpin_work *work =
7819 container_of(__work, struct intel_unpin_work, work);
7820 struct drm_device *dev = work->crtc->dev;
7822 mutex_lock(&dev->struct_mutex);
7823 intel_unpin_fb_obj(work->old_fb_obj);
7824 drm_gem_object_unreference(&work->pending_flip_obj->base);
7825 drm_gem_object_unreference(&work->old_fb_obj->base);
7827 intel_update_fbc(dev);
7828 mutex_unlock(&dev->struct_mutex);
7830 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7831 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7836 static void do_intel_finish_page_flip(struct drm_device *dev,
7837 struct drm_crtc *crtc)
7839 drm_i915_private_t *dev_priv = dev->dev_private;
7840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7841 struct intel_unpin_work *work;
7842 unsigned long flags;
7844 /* Ignore early vblank irqs */
7845 if (intel_crtc == NULL)
7848 spin_lock_irqsave(&dev->event_lock, flags);
7849 work = intel_crtc->unpin_work;
7851 /* Ensure we don't miss a work->pending update ... */
7854 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7855 spin_unlock_irqrestore(&dev->event_lock, flags);
7859 /* and that the unpin work is consistent wrt ->pending. */
7862 intel_crtc->unpin_work = NULL;
7865 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7867 drm_vblank_put(dev, intel_crtc->pipe);
7869 spin_unlock_irqrestore(&dev->event_lock, flags);
7871 wake_up_all(&dev_priv->pending_flip_queue);
7873 queue_work(dev_priv->wq, &work->work);
7875 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7878 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7880 drm_i915_private_t *dev_priv = dev->dev_private;
7881 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7883 do_intel_finish_page_flip(dev, crtc);
7886 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7888 drm_i915_private_t *dev_priv = dev->dev_private;
7889 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7891 do_intel_finish_page_flip(dev, crtc);
7894 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7896 drm_i915_private_t *dev_priv = dev->dev_private;
7897 struct intel_crtc *intel_crtc =
7898 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7899 unsigned long flags;
7901 /* NB: An MMIO update of the plane base pointer will also
7902 * generate a page-flip completion irq, i.e. every modeset
7903 * is also accompanied by a spurious intel_prepare_page_flip().
7905 spin_lock_irqsave(&dev->event_lock, flags);
7906 if (intel_crtc->unpin_work)
7907 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7908 spin_unlock_irqrestore(&dev->event_lock, flags);
7911 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7913 /* Ensure that the work item is consistent when activating it ... */
7915 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7916 /* and that it is marked active as soon as the irq could fire. */
7920 static int intel_gen2_queue_flip(struct drm_device *dev,
7921 struct drm_crtc *crtc,
7922 struct drm_framebuffer *fb,
7923 struct drm_i915_gem_object *obj,
7926 struct drm_i915_private *dev_priv = dev->dev_private;
7927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7929 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7932 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7936 ret = intel_ring_begin(ring, 6);
7940 /* Can't queue multiple flips, so wait for the previous
7941 * one to finish before executing the next.
7943 if (intel_crtc->plane)
7944 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7946 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7947 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7948 intel_ring_emit(ring, MI_NOOP);
7949 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7950 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7951 intel_ring_emit(ring, fb->pitches[0]);
7952 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7953 intel_ring_emit(ring, 0); /* aux display base address, unused */
7955 intel_mark_page_flip_active(intel_crtc);
7956 __intel_ring_advance(ring);
7960 intel_unpin_fb_obj(obj);
7965 static int intel_gen3_queue_flip(struct drm_device *dev,
7966 struct drm_crtc *crtc,
7967 struct drm_framebuffer *fb,
7968 struct drm_i915_gem_object *obj,
7971 struct drm_i915_private *dev_priv = dev->dev_private;
7972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7974 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7977 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7981 ret = intel_ring_begin(ring, 6);
7985 if (intel_crtc->plane)
7986 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7988 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7989 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7990 intel_ring_emit(ring, MI_NOOP);
7991 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7992 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7993 intel_ring_emit(ring, fb->pitches[0]);
7994 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7995 intel_ring_emit(ring, MI_NOOP);
7997 intel_mark_page_flip_active(intel_crtc);
7998 __intel_ring_advance(ring);
8002 intel_unpin_fb_obj(obj);
8007 static int intel_gen4_queue_flip(struct drm_device *dev,
8008 struct drm_crtc *crtc,
8009 struct drm_framebuffer *fb,
8010 struct drm_i915_gem_object *obj,
8013 struct drm_i915_private *dev_priv = dev->dev_private;
8014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8015 uint32_t pf, pipesrc;
8016 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8019 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8023 ret = intel_ring_begin(ring, 4);
8027 /* i965+ uses the linear or tiled offsets from the
8028 * Display Registers (which do not change across a page-flip)
8029 * so we need only reprogram the base address.
8031 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8032 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8033 intel_ring_emit(ring, fb->pitches[0]);
8034 intel_ring_emit(ring,
8035 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8038 /* XXX Enabling the panel-fitter across page-flip is so far
8039 * untested on non-native modes, so ignore it for now.
8040 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8043 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8044 intel_ring_emit(ring, pf | pipesrc);
8046 intel_mark_page_flip_active(intel_crtc);
8047 __intel_ring_advance(ring);
8051 intel_unpin_fb_obj(obj);
8056 static int intel_gen6_queue_flip(struct drm_device *dev,
8057 struct drm_crtc *crtc,
8058 struct drm_framebuffer *fb,
8059 struct drm_i915_gem_object *obj,
8062 struct drm_i915_private *dev_priv = dev->dev_private;
8063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8064 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8065 uint32_t pf, pipesrc;
8068 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8072 ret = intel_ring_begin(ring, 4);
8076 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8077 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8078 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8079 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8081 /* Contrary to the suggestions in the documentation,
8082 * "Enable Panel Fitter" does not seem to be required when page
8083 * flipping with a non-native mode, and worse causes a normal
8085 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8088 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8089 intel_ring_emit(ring, pf | pipesrc);
8091 intel_mark_page_flip_active(intel_crtc);
8092 __intel_ring_advance(ring);
8096 intel_unpin_fb_obj(obj);
8101 static int intel_gen7_queue_flip(struct drm_device *dev,
8102 struct drm_crtc *crtc,
8103 struct drm_framebuffer *fb,
8104 struct drm_i915_gem_object *obj,
8107 struct drm_i915_private *dev_priv = dev->dev_private;
8108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8109 struct intel_ring_buffer *ring;
8110 uint32_t plane_bit = 0;
8114 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8115 ring = &dev_priv->ring[BCS];
8117 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8121 switch(intel_crtc->plane) {
8123 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8126 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8129 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8132 WARN_ONCE(1, "unknown plane in flip command\n");
8138 if (ring->id == RCS)
8141 ret = intel_ring_begin(ring, len);
8145 /* Unmask the flip-done completion message. Note that the bspec says that
8146 * we should do this for both the BCS and RCS, and that we must not unmask
8147 * more than one flip event at any time (or ensure that one flip message
8148 * can be sent by waiting for flip-done prior to queueing new flips).
8149 * Experimentation says that BCS works despite DERRMR masking all
8150 * flip-done completion events and that unmasking all planes at once
8151 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8152 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8154 if (ring->id == RCS) {
8155 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8156 intel_ring_emit(ring, DERRMR);
8157 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8158 DERRMR_PIPEB_PRI_FLIP_DONE |
8159 DERRMR_PIPEC_PRI_FLIP_DONE));
8160 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8161 intel_ring_emit(ring, DERRMR);
8162 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8165 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8166 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8167 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8168 intel_ring_emit(ring, (MI_NOOP));
8170 intel_mark_page_flip_active(intel_crtc);
8171 __intel_ring_advance(ring);
8175 intel_unpin_fb_obj(obj);
8180 static int intel_default_queue_flip(struct drm_device *dev,
8181 struct drm_crtc *crtc,
8182 struct drm_framebuffer *fb,
8183 struct drm_i915_gem_object *obj,
8189 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8190 struct drm_framebuffer *fb,
8191 struct drm_pending_vblank_event *event,
8192 uint32_t page_flip_flags)
8194 struct drm_device *dev = crtc->dev;
8195 struct drm_i915_private *dev_priv = dev->dev_private;
8196 struct drm_framebuffer *old_fb = crtc->fb;
8197 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8199 struct intel_unpin_work *work;
8200 unsigned long flags;
8203 /* Can't change pixel format via MI display flips. */
8204 if (fb->pixel_format != crtc->fb->pixel_format)
8208 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8209 * Note that pitch changes could also affect these register.
8211 if (INTEL_INFO(dev)->gen > 3 &&
8212 (fb->offsets[0] != crtc->fb->offsets[0] ||
8213 fb->pitches[0] != crtc->fb->pitches[0]))
8216 work = kzalloc(sizeof(*work), GFP_KERNEL);
8220 work->event = event;
8222 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8223 INIT_WORK(&work->work, intel_unpin_work_fn);
8225 ret = drm_vblank_get(dev, intel_crtc->pipe);
8229 /* We borrow the event spin lock for protecting unpin_work */
8230 spin_lock_irqsave(&dev->event_lock, flags);
8231 if (intel_crtc->unpin_work) {
8232 spin_unlock_irqrestore(&dev->event_lock, flags);
8234 drm_vblank_put(dev, intel_crtc->pipe);
8236 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8239 intel_crtc->unpin_work = work;
8240 spin_unlock_irqrestore(&dev->event_lock, flags);
8242 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8243 flush_workqueue(dev_priv->wq);
8245 ret = i915_mutex_lock_interruptible(dev);
8249 /* Reference the objects for the scheduled work. */
8250 drm_gem_object_reference(&work->old_fb_obj->base);
8251 drm_gem_object_reference(&obj->base);
8255 work->pending_flip_obj = obj;
8257 work->enable_stall_check = true;
8259 atomic_inc(&intel_crtc->unpin_work_count);
8260 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8262 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8264 goto cleanup_pending;
8266 intel_disable_fbc(dev);
8267 intel_mark_fb_busy(obj, NULL);
8268 mutex_unlock(&dev->struct_mutex);
8270 trace_i915_flip_request(intel_crtc->plane, obj);
8275 atomic_dec(&intel_crtc->unpin_work_count);
8277 drm_gem_object_unreference(&work->old_fb_obj->base);
8278 drm_gem_object_unreference(&obj->base);
8279 mutex_unlock(&dev->struct_mutex);
8282 spin_lock_irqsave(&dev->event_lock, flags);
8283 intel_crtc->unpin_work = NULL;
8284 spin_unlock_irqrestore(&dev->event_lock, flags);
8286 drm_vblank_put(dev, intel_crtc->pipe);
8293 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8294 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8295 .load_lut = intel_crtc_load_lut,
8298 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8299 struct drm_crtc *crtc)
8301 struct drm_device *dev;
8302 struct drm_crtc *tmp;
8305 WARN(!crtc, "checking null crtc?\n");
8309 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8315 if (encoder->possible_crtcs & crtc_mask)
8321 * intel_modeset_update_staged_output_state
8323 * Updates the staged output configuration state, e.g. after we've read out the
8326 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8328 struct intel_encoder *encoder;
8329 struct intel_connector *connector;
8331 list_for_each_entry(connector, &dev->mode_config.connector_list,
8333 connector->new_encoder =
8334 to_intel_encoder(connector->base.encoder);
8337 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8340 to_intel_crtc(encoder->base.crtc);
8345 * intel_modeset_commit_output_state
8347 * This function copies the stage display pipe configuration to the real one.
8349 static void intel_modeset_commit_output_state(struct drm_device *dev)
8351 struct intel_encoder *encoder;
8352 struct intel_connector *connector;
8354 list_for_each_entry(connector, &dev->mode_config.connector_list,
8356 connector->base.encoder = &connector->new_encoder->base;
8359 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8361 encoder->base.crtc = &encoder->new_crtc->base;
8366 connected_sink_compute_bpp(struct intel_connector * connector,
8367 struct intel_crtc_config *pipe_config)
8369 int bpp = pipe_config->pipe_bpp;
8371 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8372 connector->base.base.id,
8373 drm_get_connector_name(&connector->base));
8375 /* Don't use an invalid EDID bpc value */
8376 if (connector->base.display_info.bpc &&
8377 connector->base.display_info.bpc * 3 < bpp) {
8378 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8379 bpp, connector->base.display_info.bpc*3);
8380 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8383 /* Clamp bpp to 8 on screens without EDID 1.4 */
8384 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8385 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8387 pipe_config->pipe_bpp = 24;
8392 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8393 struct drm_framebuffer *fb,
8394 struct intel_crtc_config *pipe_config)
8396 struct drm_device *dev = crtc->base.dev;
8397 struct intel_connector *connector;
8400 switch (fb->pixel_format) {
8402 bpp = 8*3; /* since we go through a colormap */
8404 case DRM_FORMAT_XRGB1555:
8405 case DRM_FORMAT_ARGB1555:
8406 /* checked in intel_framebuffer_init already */
8407 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8409 case DRM_FORMAT_RGB565:
8410 bpp = 6*3; /* min is 18bpp */
8412 case DRM_FORMAT_XBGR8888:
8413 case DRM_FORMAT_ABGR8888:
8414 /* checked in intel_framebuffer_init already */
8415 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8417 case DRM_FORMAT_XRGB8888:
8418 case DRM_FORMAT_ARGB8888:
8421 case DRM_FORMAT_XRGB2101010:
8422 case DRM_FORMAT_ARGB2101010:
8423 case DRM_FORMAT_XBGR2101010:
8424 case DRM_FORMAT_ABGR2101010:
8425 /* checked in intel_framebuffer_init already */
8426 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8430 /* TODO: gen4+ supports 16 bpc floating point, too. */
8432 DRM_DEBUG_KMS("unsupported depth\n");
8436 pipe_config->pipe_bpp = bpp;
8438 /* Clamp display bpp to EDID value */
8439 list_for_each_entry(connector, &dev->mode_config.connector_list,
8441 if (!connector->new_encoder ||
8442 connector->new_encoder->new_crtc != crtc)
8445 connected_sink_compute_bpp(connector, pipe_config);
8451 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8453 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8454 "type: 0x%x flags: 0x%x\n",
8456 mode->crtc_hdisplay, mode->crtc_hsync_start,
8457 mode->crtc_hsync_end, mode->crtc_htotal,
8458 mode->crtc_vdisplay, mode->crtc_vsync_start,
8459 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8462 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8463 struct intel_crtc_config *pipe_config,
8464 const char *context)
8466 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8467 context, pipe_name(crtc->pipe));
8469 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8470 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8471 pipe_config->pipe_bpp, pipe_config->dither);
8472 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8473 pipe_config->has_pch_encoder,
8474 pipe_config->fdi_lanes,
8475 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8476 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8477 pipe_config->fdi_m_n.tu);
8478 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8479 pipe_config->has_dp_encoder,
8480 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8481 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8482 pipe_config->dp_m_n.tu);
8483 DRM_DEBUG_KMS("requested mode:\n");
8484 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8485 DRM_DEBUG_KMS("adjusted mode:\n");
8486 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8487 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8488 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8489 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8490 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8491 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8492 pipe_config->gmch_pfit.control,
8493 pipe_config->gmch_pfit.pgm_ratios,
8494 pipe_config->gmch_pfit.lvds_border_bits);
8495 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8496 pipe_config->pch_pfit.pos,
8497 pipe_config->pch_pfit.size,
8498 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8499 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8500 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8503 static bool check_encoder_cloning(struct drm_crtc *crtc)
8505 int num_encoders = 0;
8506 bool uncloneable_encoders = false;
8507 struct intel_encoder *encoder;
8509 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8511 if (&encoder->new_crtc->base != crtc)
8515 if (!encoder->cloneable)
8516 uncloneable_encoders = true;
8519 return !(num_encoders > 1 && uncloneable_encoders);
8522 static struct intel_crtc_config *
8523 intel_modeset_pipe_config(struct drm_crtc *crtc,
8524 struct drm_framebuffer *fb,
8525 struct drm_display_mode *mode)
8527 struct drm_device *dev = crtc->dev;
8528 struct intel_encoder *encoder;
8529 struct intel_crtc_config *pipe_config;
8530 int plane_bpp, ret = -EINVAL;
8533 if (!check_encoder_cloning(crtc)) {
8534 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8535 return ERR_PTR(-EINVAL);
8538 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8540 return ERR_PTR(-ENOMEM);
8542 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8543 drm_mode_copy(&pipe_config->requested_mode, mode);
8545 pipe_config->cpu_transcoder =
8546 (enum transcoder) to_intel_crtc(crtc)->pipe;
8547 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8550 * Sanitize sync polarity flags based on requested ones. If neither
8551 * positive or negative polarity is requested, treat this as meaning
8552 * negative polarity.
8554 if (!(pipe_config->adjusted_mode.flags &
8555 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8556 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8558 if (!(pipe_config->adjusted_mode.flags &
8559 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8560 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8562 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8563 * plane pixel format and any sink constraints into account. Returns the
8564 * source plane bpp so that dithering can be selected on mismatches
8565 * after encoders and crtc also have had their say. */
8566 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8572 * Determine the real pipe dimensions. Note that stereo modes can
8573 * increase the actual pipe size due to the frame doubling and
8574 * insertion of additional space for blanks between the frame. This
8575 * is stored in the crtc timings. We use the requested mode to do this
8576 * computation to clearly distinguish it from the adjusted mode, which
8577 * can be changed by the connectors in the below retry loop.
8579 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8580 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8581 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8584 /* Ensure the port clock defaults are reset when retrying. */
8585 pipe_config->port_clock = 0;
8586 pipe_config->pixel_multiplier = 1;
8588 /* Fill in default crtc timings, allow encoders to overwrite them. */
8589 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8591 /* Pass our mode to the connectors and the CRTC to give them a chance to
8592 * adjust it according to limitations or connector properties, and also
8593 * a chance to reject the mode entirely.
8595 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8598 if (&encoder->new_crtc->base != crtc)
8601 if (!(encoder->compute_config(encoder, pipe_config))) {
8602 DRM_DEBUG_KMS("Encoder config failure\n");
8607 /* Set default port clock if not overwritten by the encoder. Needs to be
8608 * done afterwards in case the encoder adjusts the mode. */
8609 if (!pipe_config->port_clock)
8610 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8611 * pipe_config->pixel_multiplier;
8613 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8615 DRM_DEBUG_KMS("CRTC fixup failed\n");
8620 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8625 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8630 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8631 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8632 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8637 return ERR_PTR(ret);
8640 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8641 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8643 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8644 unsigned *prepare_pipes, unsigned *disable_pipes)
8646 struct intel_crtc *intel_crtc;
8647 struct drm_device *dev = crtc->dev;
8648 struct intel_encoder *encoder;
8649 struct intel_connector *connector;
8650 struct drm_crtc *tmp_crtc;
8652 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8654 /* Check which crtcs have changed outputs connected to them, these need
8655 * to be part of the prepare_pipes mask. We don't (yet) support global
8656 * modeset across multiple crtcs, so modeset_pipes will only have one
8657 * bit set at most. */
8658 list_for_each_entry(connector, &dev->mode_config.connector_list,
8660 if (connector->base.encoder == &connector->new_encoder->base)
8663 if (connector->base.encoder) {
8664 tmp_crtc = connector->base.encoder->crtc;
8666 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8669 if (connector->new_encoder)
8671 1 << connector->new_encoder->new_crtc->pipe;
8674 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8676 if (encoder->base.crtc == &encoder->new_crtc->base)
8679 if (encoder->base.crtc) {
8680 tmp_crtc = encoder->base.crtc;
8682 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8685 if (encoder->new_crtc)
8686 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8689 /* Check for any pipes that will be fully disabled ... */
8690 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8694 /* Don't try to disable disabled crtcs. */
8695 if (!intel_crtc->base.enabled)
8698 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8700 if (encoder->new_crtc == intel_crtc)
8705 *disable_pipes |= 1 << intel_crtc->pipe;
8709 /* set_mode is also used to update properties on life display pipes. */
8710 intel_crtc = to_intel_crtc(crtc);
8712 *prepare_pipes |= 1 << intel_crtc->pipe;
8715 * For simplicity do a full modeset on any pipe where the output routing
8716 * changed. We could be more clever, but that would require us to be
8717 * more careful with calling the relevant encoder->mode_set functions.
8720 *modeset_pipes = *prepare_pipes;
8722 /* ... and mask these out. */
8723 *modeset_pipes &= ~(*disable_pipes);
8724 *prepare_pipes &= ~(*disable_pipes);
8727 * HACK: We don't (yet) fully support global modesets. intel_set_config
8728 * obies this rule, but the modeset restore mode of
8729 * intel_modeset_setup_hw_state does not.
8731 *modeset_pipes &= 1 << intel_crtc->pipe;
8732 *prepare_pipes &= 1 << intel_crtc->pipe;
8734 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8735 *modeset_pipes, *prepare_pipes, *disable_pipes);
8738 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8740 struct drm_encoder *encoder;
8741 struct drm_device *dev = crtc->dev;
8743 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8744 if (encoder->crtc == crtc)
8751 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8753 struct intel_encoder *intel_encoder;
8754 struct intel_crtc *intel_crtc;
8755 struct drm_connector *connector;
8757 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8759 if (!intel_encoder->base.crtc)
8762 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8764 if (prepare_pipes & (1 << intel_crtc->pipe))
8765 intel_encoder->connectors_active = false;
8768 intel_modeset_commit_output_state(dev);
8770 /* Update computed state. */
8771 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8773 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8776 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8777 if (!connector->encoder || !connector->encoder->crtc)
8780 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8782 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8783 struct drm_property *dpms_property =
8784 dev->mode_config.dpms_property;
8786 connector->dpms = DRM_MODE_DPMS_ON;
8787 drm_object_property_set_value(&connector->base,
8791 intel_encoder = to_intel_encoder(connector->encoder);
8792 intel_encoder->connectors_active = true;
8798 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8802 if (clock1 == clock2)
8805 if (!clock1 || !clock2)
8808 diff = abs(clock1 - clock2);
8810 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8816 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8817 list_for_each_entry((intel_crtc), \
8818 &(dev)->mode_config.crtc_list, \
8820 if (mask & (1 <<(intel_crtc)->pipe))
8823 intel_pipe_config_compare(struct drm_device *dev,
8824 struct intel_crtc_config *current_config,
8825 struct intel_crtc_config *pipe_config)
8827 #define PIPE_CONF_CHECK_X(name) \
8828 if (current_config->name != pipe_config->name) { \
8829 DRM_ERROR("mismatch in " #name " " \
8830 "(expected 0x%08x, found 0x%08x)\n", \
8831 current_config->name, \
8832 pipe_config->name); \
8836 #define PIPE_CONF_CHECK_I(name) \
8837 if (current_config->name != pipe_config->name) { \
8838 DRM_ERROR("mismatch in " #name " " \
8839 "(expected %i, found %i)\n", \
8840 current_config->name, \
8841 pipe_config->name); \
8845 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8846 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8847 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8848 "(expected %i, found %i)\n", \
8849 current_config->name & (mask), \
8850 pipe_config->name & (mask)); \
8854 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8855 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8856 DRM_ERROR("mismatch in " #name " " \
8857 "(expected %i, found %i)\n", \
8858 current_config->name, \
8859 pipe_config->name); \
8863 #define PIPE_CONF_QUIRK(quirk) \
8864 ((current_config->quirks | pipe_config->quirks) & (quirk))
8866 PIPE_CONF_CHECK_I(cpu_transcoder);
8868 PIPE_CONF_CHECK_I(has_pch_encoder);
8869 PIPE_CONF_CHECK_I(fdi_lanes);
8870 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8871 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8872 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8873 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8874 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8876 PIPE_CONF_CHECK_I(has_dp_encoder);
8877 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8878 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8879 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8880 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8881 PIPE_CONF_CHECK_I(dp_m_n.tu);
8883 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8884 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8885 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8886 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8887 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8888 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8890 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8891 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8892 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8893 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8894 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8895 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8897 PIPE_CONF_CHECK_I(pixel_multiplier);
8899 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8900 DRM_MODE_FLAG_INTERLACE);
8902 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8903 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8904 DRM_MODE_FLAG_PHSYNC);
8905 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8906 DRM_MODE_FLAG_NHSYNC);
8907 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8908 DRM_MODE_FLAG_PVSYNC);
8909 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8910 DRM_MODE_FLAG_NVSYNC);
8913 PIPE_CONF_CHECK_I(pipe_src_w);
8914 PIPE_CONF_CHECK_I(pipe_src_h);
8916 PIPE_CONF_CHECK_I(gmch_pfit.control);
8917 /* pfit ratios are autocomputed by the hw on gen4+ */
8918 if (INTEL_INFO(dev)->gen < 4)
8919 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8920 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8921 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8922 if (current_config->pch_pfit.enabled) {
8923 PIPE_CONF_CHECK_I(pch_pfit.pos);
8924 PIPE_CONF_CHECK_I(pch_pfit.size);
8927 PIPE_CONF_CHECK_I(ips_enabled);
8929 PIPE_CONF_CHECK_I(double_wide);
8931 PIPE_CONF_CHECK_I(shared_dpll);
8932 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8933 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8934 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8935 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8937 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8938 PIPE_CONF_CHECK_I(pipe_bpp);
8940 if (!IS_HASWELL(dev)) {
8941 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
8942 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8945 #undef PIPE_CONF_CHECK_X
8946 #undef PIPE_CONF_CHECK_I
8947 #undef PIPE_CONF_CHECK_FLAGS
8948 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8949 #undef PIPE_CONF_QUIRK
8955 check_connector_state(struct drm_device *dev)
8957 struct intel_connector *connector;
8959 list_for_each_entry(connector, &dev->mode_config.connector_list,
8961 /* This also checks the encoder/connector hw state with the
8962 * ->get_hw_state callbacks. */
8963 intel_connector_check_state(connector);
8965 WARN(&connector->new_encoder->base != connector->base.encoder,
8966 "connector's staged encoder doesn't match current encoder\n");
8971 check_encoder_state(struct drm_device *dev)
8973 struct intel_encoder *encoder;
8974 struct intel_connector *connector;
8976 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8978 bool enabled = false;
8979 bool active = false;
8980 enum pipe pipe, tracked_pipe;
8982 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8983 encoder->base.base.id,
8984 drm_get_encoder_name(&encoder->base));
8986 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8987 "encoder's stage crtc doesn't match current crtc\n");
8988 WARN(encoder->connectors_active && !encoder->base.crtc,
8989 "encoder's active_connectors set, but no crtc\n");
8991 list_for_each_entry(connector, &dev->mode_config.connector_list,
8993 if (connector->base.encoder != &encoder->base)
8996 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8999 WARN(!!encoder->base.crtc != enabled,
9000 "encoder's enabled state mismatch "
9001 "(expected %i, found %i)\n",
9002 !!encoder->base.crtc, enabled);
9003 WARN(active && !encoder->base.crtc,
9004 "active encoder with no crtc\n");
9006 WARN(encoder->connectors_active != active,
9007 "encoder's computed active state doesn't match tracked active state "
9008 "(expected %i, found %i)\n", active, encoder->connectors_active);
9010 active = encoder->get_hw_state(encoder, &pipe);
9011 WARN(active != encoder->connectors_active,
9012 "encoder's hw state doesn't match sw tracking "
9013 "(expected %i, found %i)\n",
9014 encoder->connectors_active, active);
9016 if (!encoder->base.crtc)
9019 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9020 WARN(active && pipe != tracked_pipe,
9021 "active encoder's pipe doesn't match"
9022 "(expected %i, found %i)\n",
9023 tracked_pipe, pipe);
9029 check_crtc_state(struct drm_device *dev)
9031 drm_i915_private_t *dev_priv = dev->dev_private;
9032 struct intel_crtc *crtc;
9033 struct intel_encoder *encoder;
9034 struct intel_crtc_config pipe_config;
9036 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9038 bool enabled = false;
9039 bool active = false;
9041 memset(&pipe_config, 0, sizeof(pipe_config));
9043 DRM_DEBUG_KMS("[CRTC:%d]\n",
9044 crtc->base.base.id);
9046 WARN(crtc->active && !crtc->base.enabled,
9047 "active crtc, but not enabled in sw tracking\n");
9049 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9051 if (encoder->base.crtc != &crtc->base)
9054 if (encoder->connectors_active)
9058 WARN(active != crtc->active,
9059 "crtc's computed active state doesn't match tracked active state "
9060 "(expected %i, found %i)\n", active, crtc->active);
9061 WARN(enabled != crtc->base.enabled,
9062 "crtc's computed enabled state doesn't match tracked enabled state "
9063 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9065 active = dev_priv->display.get_pipe_config(crtc,
9068 /* hw state is inconsistent with the pipe A quirk */
9069 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9070 active = crtc->active;
9072 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9075 if (encoder->base.crtc != &crtc->base)
9077 if (encoder->get_config &&
9078 encoder->get_hw_state(encoder, &pipe))
9079 encoder->get_config(encoder, &pipe_config);
9082 WARN(crtc->active != active,
9083 "crtc active state doesn't match with hw state "
9084 "(expected %i, found %i)\n", crtc->active, active);
9087 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9088 WARN(1, "pipe state doesn't match!\n");
9089 intel_dump_pipe_config(crtc, &pipe_config,
9091 intel_dump_pipe_config(crtc, &crtc->config,
9098 check_shared_dpll_state(struct drm_device *dev)
9100 drm_i915_private_t *dev_priv = dev->dev_private;
9101 struct intel_crtc *crtc;
9102 struct intel_dpll_hw_state dpll_hw_state;
9105 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9106 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9107 int enabled_crtcs = 0, active_crtcs = 0;
9110 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9112 DRM_DEBUG_KMS("%s\n", pll->name);
9114 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9116 WARN(pll->active > pll->refcount,
9117 "more active pll users than references: %i vs %i\n",
9118 pll->active, pll->refcount);
9119 WARN(pll->active && !pll->on,
9120 "pll in active use but not on in sw tracking\n");
9121 WARN(pll->on && !pll->active,
9122 "pll in on but not on in use in sw tracking\n");
9123 WARN(pll->on != active,
9124 "pll on state mismatch (expected %i, found %i)\n",
9127 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9129 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9131 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9134 WARN(pll->active != active_crtcs,
9135 "pll active crtcs mismatch (expected %i, found %i)\n",
9136 pll->active, active_crtcs);
9137 WARN(pll->refcount != enabled_crtcs,
9138 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9139 pll->refcount, enabled_crtcs);
9141 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9142 sizeof(dpll_hw_state)),
9143 "pll hw state mismatch\n");
9148 intel_modeset_check_state(struct drm_device *dev)
9150 check_connector_state(dev);
9151 check_encoder_state(dev);
9152 check_crtc_state(dev);
9153 check_shared_dpll_state(dev);
9156 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9160 * FDI already provided one idea for the dotclock.
9161 * Yell if the encoder disagrees.
9163 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9164 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9165 pipe_config->adjusted_mode.crtc_clock, dotclock);
9168 static int __intel_set_mode(struct drm_crtc *crtc,
9169 struct drm_display_mode *mode,
9170 int x, int y, struct drm_framebuffer *fb)
9172 struct drm_device *dev = crtc->dev;
9173 drm_i915_private_t *dev_priv = dev->dev_private;
9174 struct drm_display_mode *saved_mode, *saved_hwmode;
9175 struct intel_crtc_config *pipe_config = NULL;
9176 struct intel_crtc *intel_crtc;
9177 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9180 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9183 saved_hwmode = saved_mode + 1;
9185 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9186 &prepare_pipes, &disable_pipes);
9188 *saved_hwmode = crtc->hwmode;
9189 *saved_mode = crtc->mode;
9191 /* Hack: Because we don't (yet) support global modeset on multiple
9192 * crtcs, we don't keep track of the new mode for more than one crtc.
9193 * Hence simply check whether any bit is set in modeset_pipes in all the
9194 * pieces of code that are not yet converted to deal with mutliple crtcs
9195 * changing their mode at the same time. */
9196 if (modeset_pipes) {
9197 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9198 if (IS_ERR(pipe_config)) {
9199 ret = PTR_ERR(pipe_config);
9204 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9208 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9209 intel_crtc_disable(&intel_crtc->base);
9211 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9212 if (intel_crtc->base.enabled)
9213 dev_priv->display.crtc_disable(&intel_crtc->base);
9216 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9217 * to set it here already despite that we pass it down the callchain.
9219 if (modeset_pipes) {
9221 /* mode_set/enable/disable functions rely on a correct pipe
9223 to_intel_crtc(crtc)->config = *pipe_config;
9226 /* Only after disabling all output pipelines that will be changed can we
9227 * update the the output configuration. */
9228 intel_modeset_update_state(dev, prepare_pipes);
9230 if (dev_priv->display.modeset_global_resources)
9231 dev_priv->display.modeset_global_resources(dev);
9233 /* Set up the DPLL and any encoders state that needs to adjust or depend
9236 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9237 ret = intel_crtc_mode_set(&intel_crtc->base,
9243 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9244 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9245 dev_priv->display.crtc_enable(&intel_crtc->base);
9247 if (modeset_pipes) {
9248 /* Store real post-adjustment hardware mode. */
9249 crtc->hwmode = pipe_config->adjusted_mode;
9251 /* Calculate and store various constants which
9252 * are later needed by vblank and swap-completion
9253 * timestamping. They are derived from true hwmode.
9255 drm_calc_timestamping_constants(crtc);
9258 /* FIXME: add subpixel order */
9260 if (ret && crtc->enabled) {
9261 crtc->hwmode = *saved_hwmode;
9262 crtc->mode = *saved_mode;
9271 static int intel_set_mode(struct drm_crtc *crtc,
9272 struct drm_display_mode *mode,
9273 int x, int y, struct drm_framebuffer *fb)
9277 ret = __intel_set_mode(crtc, mode, x, y, fb);
9280 intel_modeset_check_state(crtc->dev);
9285 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9287 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9290 #undef for_each_intel_crtc_masked
9292 static void intel_set_config_free(struct intel_set_config *config)
9297 kfree(config->save_connector_encoders);
9298 kfree(config->save_encoder_crtcs);
9302 static int intel_set_config_save_state(struct drm_device *dev,
9303 struct intel_set_config *config)
9305 struct drm_encoder *encoder;
9306 struct drm_connector *connector;
9309 config->save_encoder_crtcs =
9310 kcalloc(dev->mode_config.num_encoder,
9311 sizeof(struct drm_crtc *), GFP_KERNEL);
9312 if (!config->save_encoder_crtcs)
9315 config->save_connector_encoders =
9316 kcalloc(dev->mode_config.num_connector,
9317 sizeof(struct drm_encoder *), GFP_KERNEL);
9318 if (!config->save_connector_encoders)
9321 /* Copy data. Note that driver private data is not affected.
9322 * Should anything bad happen only the expected state is
9323 * restored, not the drivers personal bookkeeping.
9326 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9327 config->save_encoder_crtcs[count++] = encoder->crtc;
9331 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9332 config->save_connector_encoders[count++] = connector->encoder;
9338 static void intel_set_config_restore_state(struct drm_device *dev,
9339 struct intel_set_config *config)
9341 struct intel_encoder *encoder;
9342 struct intel_connector *connector;
9346 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9348 to_intel_crtc(config->save_encoder_crtcs[count++]);
9352 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9353 connector->new_encoder =
9354 to_intel_encoder(config->save_connector_encoders[count++]);
9359 is_crtc_connector_off(struct drm_mode_set *set)
9363 if (set->num_connectors == 0)
9366 if (WARN_ON(set->connectors == NULL))
9369 for (i = 0; i < set->num_connectors; i++)
9370 if (set->connectors[i]->encoder &&
9371 set->connectors[i]->encoder->crtc == set->crtc &&
9372 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9379 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9380 struct intel_set_config *config)
9383 /* We should be able to check here if the fb has the same properties
9384 * and then just flip_or_move it */
9385 if (is_crtc_connector_off(set)) {
9386 config->mode_changed = true;
9387 } else if (set->crtc->fb != set->fb) {
9388 /* If we have no fb then treat it as a full mode set */
9389 if (set->crtc->fb == NULL) {
9390 struct intel_crtc *intel_crtc =
9391 to_intel_crtc(set->crtc);
9393 if (intel_crtc->active && i915_fastboot) {
9394 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9395 config->fb_changed = true;
9397 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9398 config->mode_changed = true;
9400 } else if (set->fb == NULL) {
9401 config->mode_changed = true;
9402 } else if (set->fb->pixel_format !=
9403 set->crtc->fb->pixel_format) {
9404 config->mode_changed = true;
9406 config->fb_changed = true;
9410 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9411 config->fb_changed = true;
9413 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9414 DRM_DEBUG_KMS("modes are different, full mode set\n");
9415 drm_mode_debug_printmodeline(&set->crtc->mode);
9416 drm_mode_debug_printmodeline(set->mode);
9417 config->mode_changed = true;
9420 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9421 set->crtc->base.id, config->mode_changed, config->fb_changed);
9425 intel_modeset_stage_output_state(struct drm_device *dev,
9426 struct drm_mode_set *set,
9427 struct intel_set_config *config)
9429 struct drm_crtc *new_crtc;
9430 struct intel_connector *connector;
9431 struct intel_encoder *encoder;
9434 /* The upper layers ensure that we either disable a crtc or have a list
9435 * of connectors. For paranoia, double-check this. */
9436 WARN_ON(!set->fb && (set->num_connectors != 0));
9437 WARN_ON(set->fb && (set->num_connectors == 0));
9439 list_for_each_entry(connector, &dev->mode_config.connector_list,
9441 /* Otherwise traverse passed in connector list and get encoders
9443 for (ro = 0; ro < set->num_connectors; ro++) {
9444 if (set->connectors[ro] == &connector->base) {
9445 connector->new_encoder = connector->encoder;
9450 /* If we disable the crtc, disable all its connectors. Also, if
9451 * the connector is on the changing crtc but not on the new
9452 * connector list, disable it. */
9453 if ((!set->fb || ro == set->num_connectors) &&
9454 connector->base.encoder &&
9455 connector->base.encoder->crtc == set->crtc) {
9456 connector->new_encoder = NULL;
9458 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9459 connector->base.base.id,
9460 drm_get_connector_name(&connector->base));
9464 if (&connector->new_encoder->base != connector->base.encoder) {
9465 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9466 config->mode_changed = true;
9469 /* connector->new_encoder is now updated for all connectors. */
9471 /* Update crtc of enabled connectors. */
9472 list_for_each_entry(connector, &dev->mode_config.connector_list,
9474 if (!connector->new_encoder)
9477 new_crtc = connector->new_encoder->base.crtc;
9479 for (ro = 0; ro < set->num_connectors; ro++) {
9480 if (set->connectors[ro] == &connector->base)
9481 new_crtc = set->crtc;
9484 /* Make sure the new CRTC will work with the encoder */
9485 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9489 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9491 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9492 connector->base.base.id,
9493 drm_get_connector_name(&connector->base),
9497 /* Check for any encoders that needs to be disabled. */
9498 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9500 list_for_each_entry(connector,
9501 &dev->mode_config.connector_list,
9503 if (connector->new_encoder == encoder) {
9504 WARN_ON(!connector->new_encoder->new_crtc);
9509 encoder->new_crtc = NULL;
9511 /* Only now check for crtc changes so we don't miss encoders
9512 * that will be disabled. */
9513 if (&encoder->new_crtc->base != encoder->base.crtc) {
9514 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9515 config->mode_changed = true;
9518 /* Now we've also updated encoder->new_crtc for all encoders. */
9523 static int intel_crtc_set_config(struct drm_mode_set *set)
9525 struct drm_device *dev;
9526 struct drm_mode_set save_set;
9527 struct intel_set_config *config;
9532 BUG_ON(!set->crtc->helper_private);
9534 /* Enforce sane interface api - has been abused by the fb helper. */
9535 BUG_ON(!set->mode && set->fb);
9536 BUG_ON(set->fb && set->num_connectors == 0);
9539 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9540 set->crtc->base.id, set->fb->base.id,
9541 (int)set->num_connectors, set->x, set->y);
9543 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9546 dev = set->crtc->dev;
9549 config = kzalloc(sizeof(*config), GFP_KERNEL);
9553 ret = intel_set_config_save_state(dev, config);
9557 save_set.crtc = set->crtc;
9558 save_set.mode = &set->crtc->mode;
9559 save_set.x = set->crtc->x;
9560 save_set.y = set->crtc->y;
9561 save_set.fb = set->crtc->fb;
9563 /* Compute whether we need a full modeset, only an fb base update or no
9564 * change at all. In the future we might also check whether only the
9565 * mode changed, e.g. for LVDS where we only change the panel fitter in
9567 intel_set_config_compute_mode_changes(set, config);
9569 ret = intel_modeset_stage_output_state(dev, set, config);
9573 if (config->mode_changed) {
9574 ret = intel_set_mode(set->crtc, set->mode,
9575 set->x, set->y, set->fb);
9576 } else if (config->fb_changed) {
9577 intel_crtc_wait_for_pending_flips(set->crtc);
9579 ret = intel_pipe_set_base(set->crtc,
9580 set->x, set->y, set->fb);
9584 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9585 set->crtc->base.id, ret);
9587 intel_set_config_restore_state(dev, config);
9589 /* Try to restore the config */
9590 if (config->mode_changed &&
9591 intel_set_mode(save_set.crtc, save_set.mode,
9592 save_set.x, save_set.y, save_set.fb))
9593 DRM_ERROR("failed to restore config after modeset failure\n");
9597 intel_set_config_free(config);
9601 static const struct drm_crtc_funcs intel_crtc_funcs = {
9602 .cursor_set = intel_crtc_cursor_set,
9603 .cursor_move = intel_crtc_cursor_move,
9604 .gamma_set = intel_crtc_gamma_set,
9605 .set_config = intel_crtc_set_config,
9606 .destroy = intel_crtc_destroy,
9607 .page_flip = intel_crtc_page_flip,
9610 static void intel_cpu_pll_init(struct drm_device *dev)
9613 intel_ddi_pll_init(dev);
9616 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9617 struct intel_shared_dpll *pll,
9618 struct intel_dpll_hw_state *hw_state)
9622 val = I915_READ(PCH_DPLL(pll->id));
9623 hw_state->dpll = val;
9624 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9625 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9627 return val & DPLL_VCO_ENABLE;
9630 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9631 struct intel_shared_dpll *pll)
9633 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9634 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9637 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9638 struct intel_shared_dpll *pll)
9640 /* PCH refclock must be enabled first */
9641 assert_pch_refclk_enabled(dev_priv);
9643 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9645 /* Wait for the clocks to stabilize. */
9646 POSTING_READ(PCH_DPLL(pll->id));
9649 /* The pixel multiplier can only be updated once the
9650 * DPLL is enabled and the clocks are stable.
9652 * So write it again.
9654 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9655 POSTING_READ(PCH_DPLL(pll->id));
9659 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9660 struct intel_shared_dpll *pll)
9662 struct drm_device *dev = dev_priv->dev;
9663 struct intel_crtc *crtc;
9665 /* Make sure no transcoder isn't still depending on us. */
9666 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9667 if (intel_crtc_to_shared_dpll(crtc) == pll)
9668 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9671 I915_WRITE(PCH_DPLL(pll->id), 0);
9672 POSTING_READ(PCH_DPLL(pll->id));
9676 static char *ibx_pch_dpll_names[] = {
9681 static void ibx_pch_dpll_init(struct drm_device *dev)
9683 struct drm_i915_private *dev_priv = dev->dev_private;
9686 dev_priv->num_shared_dpll = 2;
9688 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9689 dev_priv->shared_dplls[i].id = i;
9690 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9691 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9692 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9693 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9694 dev_priv->shared_dplls[i].get_hw_state =
9695 ibx_pch_dpll_get_hw_state;
9699 static void intel_shared_dpll_init(struct drm_device *dev)
9701 struct drm_i915_private *dev_priv = dev->dev_private;
9703 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9704 ibx_pch_dpll_init(dev);
9706 dev_priv->num_shared_dpll = 0;
9708 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9709 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9710 dev_priv->num_shared_dpll);
9713 static void intel_crtc_init(struct drm_device *dev, int pipe)
9715 drm_i915_private_t *dev_priv = dev->dev_private;
9716 struct intel_crtc *intel_crtc;
9719 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
9720 if (intel_crtc == NULL)
9723 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9725 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9726 for (i = 0; i < 256; i++) {
9727 intel_crtc->lut_r[i] = i;
9728 intel_crtc->lut_g[i] = i;
9729 intel_crtc->lut_b[i] = i;
9732 /* Swap pipes & planes for FBC on pre-965 */
9733 intel_crtc->pipe = pipe;
9734 intel_crtc->plane = pipe;
9735 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9736 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9737 intel_crtc->plane = !pipe;
9740 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9741 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9742 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9743 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9745 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9748 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9749 struct drm_file *file)
9751 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9752 struct drm_mode_object *drmmode_obj;
9753 struct intel_crtc *crtc;
9755 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9758 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9759 DRM_MODE_OBJECT_CRTC);
9762 DRM_ERROR("no such CRTC id\n");
9766 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9767 pipe_from_crtc_id->pipe = crtc->pipe;
9772 static int intel_encoder_clones(struct intel_encoder *encoder)
9774 struct drm_device *dev = encoder->base.dev;
9775 struct intel_encoder *source_encoder;
9779 list_for_each_entry(source_encoder,
9780 &dev->mode_config.encoder_list, base.head) {
9782 if (encoder == source_encoder)
9783 index_mask |= (1 << entry);
9785 /* Intel hw has only one MUX where enocoders could be cloned. */
9786 if (encoder->cloneable && source_encoder->cloneable)
9787 index_mask |= (1 << entry);
9795 static bool has_edp_a(struct drm_device *dev)
9797 struct drm_i915_private *dev_priv = dev->dev_private;
9799 if (!IS_MOBILE(dev))
9802 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9806 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9812 static void intel_setup_outputs(struct drm_device *dev)
9814 struct drm_i915_private *dev_priv = dev->dev_private;
9815 struct intel_encoder *encoder;
9816 bool dpd_is_edp = false;
9818 intel_lvds_init(dev);
9821 intel_crt_init(dev);
9826 /* Haswell uses DDI functions to detect digital outputs */
9827 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9828 /* DDI A only supports eDP */
9830 intel_ddi_init(dev, PORT_A);
9832 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9834 found = I915_READ(SFUSE_STRAP);
9836 if (found & SFUSE_STRAP_DDIB_DETECTED)
9837 intel_ddi_init(dev, PORT_B);
9838 if (found & SFUSE_STRAP_DDIC_DETECTED)
9839 intel_ddi_init(dev, PORT_C);
9840 if (found & SFUSE_STRAP_DDID_DETECTED)
9841 intel_ddi_init(dev, PORT_D);
9842 } else if (HAS_PCH_SPLIT(dev)) {
9844 dpd_is_edp = intel_dpd_is_edp(dev);
9847 intel_dp_init(dev, DP_A, PORT_A);
9849 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9850 /* PCH SDVOB multiplex with HDMIB */
9851 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9853 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9854 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9855 intel_dp_init(dev, PCH_DP_B, PORT_B);
9858 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9859 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9861 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9862 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9864 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9865 intel_dp_init(dev, PCH_DP_C, PORT_C);
9867 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9868 intel_dp_init(dev, PCH_DP_D, PORT_D);
9869 } else if (IS_VALLEYVIEW(dev)) {
9870 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9871 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9872 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9874 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9875 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9879 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9880 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9882 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9883 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9886 intel_dsi_init(dev);
9887 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9890 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9891 DRM_DEBUG_KMS("probing SDVOB\n");
9892 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9893 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9894 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9895 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9898 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9899 intel_dp_init(dev, DP_B, PORT_B);
9902 /* Before G4X SDVOC doesn't have its own detect register */
9904 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9905 DRM_DEBUG_KMS("probing SDVOC\n");
9906 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9909 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9911 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9912 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9913 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9915 if (SUPPORTS_INTEGRATED_DP(dev))
9916 intel_dp_init(dev, DP_C, PORT_C);
9919 if (SUPPORTS_INTEGRATED_DP(dev) &&
9920 (I915_READ(DP_D) & DP_DETECTED))
9921 intel_dp_init(dev, DP_D, PORT_D);
9922 } else if (IS_GEN2(dev))
9923 intel_dvo_init(dev);
9925 if (SUPPORTS_TV(dev))
9928 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9929 encoder->base.possible_crtcs = encoder->crtc_mask;
9930 encoder->base.possible_clones =
9931 intel_encoder_clones(encoder);
9934 intel_init_pch_refclk(dev);
9936 drm_helper_move_panel_connectors_to_head(dev);
9939 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9941 drm_framebuffer_cleanup(&fb->base);
9942 drm_gem_object_unreference_unlocked(&fb->obj->base);
9945 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9947 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9949 intel_framebuffer_fini(intel_fb);
9953 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9954 struct drm_file *file,
9955 unsigned int *handle)
9957 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9958 struct drm_i915_gem_object *obj = intel_fb->obj;
9960 return drm_gem_handle_create(file, &obj->base, handle);
9963 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9964 .destroy = intel_user_framebuffer_destroy,
9965 .create_handle = intel_user_framebuffer_create_handle,
9968 int intel_framebuffer_init(struct drm_device *dev,
9969 struct intel_framebuffer *intel_fb,
9970 struct drm_mode_fb_cmd2 *mode_cmd,
9971 struct drm_i915_gem_object *obj)
9976 if (obj->tiling_mode == I915_TILING_Y) {
9977 DRM_DEBUG("hardware does not support tiling Y\n");
9981 if (mode_cmd->pitches[0] & 63) {
9982 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9983 mode_cmd->pitches[0]);
9987 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9988 pitch_limit = 32*1024;
9989 } else if (INTEL_INFO(dev)->gen >= 4) {
9990 if (obj->tiling_mode)
9991 pitch_limit = 16*1024;
9993 pitch_limit = 32*1024;
9994 } else if (INTEL_INFO(dev)->gen >= 3) {
9995 if (obj->tiling_mode)
9996 pitch_limit = 8*1024;
9998 pitch_limit = 16*1024;
10000 /* XXX DSPC is limited to 4k tiled */
10001 pitch_limit = 8*1024;
10003 if (mode_cmd->pitches[0] > pitch_limit) {
10004 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10005 obj->tiling_mode ? "tiled" : "linear",
10006 mode_cmd->pitches[0], pitch_limit);
10010 if (obj->tiling_mode != I915_TILING_NONE &&
10011 mode_cmd->pitches[0] != obj->stride) {
10012 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10013 mode_cmd->pitches[0], obj->stride);
10017 /* Reject formats not supported by any plane early. */
10018 switch (mode_cmd->pixel_format) {
10019 case DRM_FORMAT_C8:
10020 case DRM_FORMAT_RGB565:
10021 case DRM_FORMAT_XRGB8888:
10022 case DRM_FORMAT_ARGB8888:
10024 case DRM_FORMAT_XRGB1555:
10025 case DRM_FORMAT_ARGB1555:
10026 if (INTEL_INFO(dev)->gen > 3) {
10027 DRM_DEBUG("unsupported pixel format: %s\n",
10028 drm_get_format_name(mode_cmd->pixel_format));
10032 case DRM_FORMAT_XBGR8888:
10033 case DRM_FORMAT_ABGR8888:
10034 case DRM_FORMAT_XRGB2101010:
10035 case DRM_FORMAT_ARGB2101010:
10036 case DRM_FORMAT_XBGR2101010:
10037 case DRM_FORMAT_ABGR2101010:
10038 if (INTEL_INFO(dev)->gen < 4) {
10039 DRM_DEBUG("unsupported pixel format: %s\n",
10040 drm_get_format_name(mode_cmd->pixel_format));
10044 case DRM_FORMAT_YUYV:
10045 case DRM_FORMAT_UYVY:
10046 case DRM_FORMAT_YVYU:
10047 case DRM_FORMAT_VYUY:
10048 if (INTEL_INFO(dev)->gen < 5) {
10049 DRM_DEBUG("unsupported pixel format: %s\n",
10050 drm_get_format_name(mode_cmd->pixel_format));
10055 DRM_DEBUG("unsupported pixel format: %s\n",
10056 drm_get_format_name(mode_cmd->pixel_format));
10060 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10061 if (mode_cmd->offsets[0] != 0)
10064 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10065 intel_fb->obj = obj;
10067 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10069 DRM_ERROR("framebuffer init failed %d\n", ret);
10076 static struct drm_framebuffer *
10077 intel_user_framebuffer_create(struct drm_device *dev,
10078 struct drm_file *filp,
10079 struct drm_mode_fb_cmd2 *mode_cmd)
10081 struct drm_i915_gem_object *obj;
10083 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10084 mode_cmd->handles[0]));
10085 if (&obj->base == NULL)
10086 return ERR_PTR(-ENOENT);
10088 return intel_framebuffer_create(dev, mode_cmd, obj);
10091 static const struct drm_mode_config_funcs intel_mode_funcs = {
10092 .fb_create = intel_user_framebuffer_create,
10093 .output_poll_changed = intel_fb_output_poll_changed,
10096 /* Set up chip specific display functions */
10097 static void intel_init_display(struct drm_device *dev)
10099 struct drm_i915_private *dev_priv = dev->dev_private;
10101 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10102 dev_priv->display.find_dpll = g4x_find_best_dpll;
10103 else if (IS_VALLEYVIEW(dev))
10104 dev_priv->display.find_dpll = vlv_find_best_dpll;
10105 else if (IS_PINEVIEW(dev))
10106 dev_priv->display.find_dpll = pnv_find_best_dpll;
10108 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10110 if (HAS_DDI(dev)) {
10111 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10112 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10113 dev_priv->display.crtc_enable = haswell_crtc_enable;
10114 dev_priv->display.crtc_disable = haswell_crtc_disable;
10115 dev_priv->display.off = haswell_crtc_off;
10116 dev_priv->display.update_plane = ironlake_update_plane;
10117 } else if (HAS_PCH_SPLIT(dev)) {
10118 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10119 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10120 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10121 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10122 dev_priv->display.off = ironlake_crtc_off;
10123 dev_priv->display.update_plane = ironlake_update_plane;
10124 } else if (IS_VALLEYVIEW(dev)) {
10125 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10126 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10127 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10128 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10129 dev_priv->display.off = i9xx_crtc_off;
10130 dev_priv->display.update_plane = i9xx_update_plane;
10132 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10133 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10134 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10135 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10136 dev_priv->display.off = i9xx_crtc_off;
10137 dev_priv->display.update_plane = i9xx_update_plane;
10140 /* Returns the core display clock speed */
10141 if (IS_VALLEYVIEW(dev))
10142 dev_priv->display.get_display_clock_speed =
10143 valleyview_get_display_clock_speed;
10144 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10145 dev_priv->display.get_display_clock_speed =
10146 i945_get_display_clock_speed;
10147 else if (IS_I915G(dev))
10148 dev_priv->display.get_display_clock_speed =
10149 i915_get_display_clock_speed;
10150 else if (IS_I945GM(dev) || IS_845G(dev))
10151 dev_priv->display.get_display_clock_speed =
10152 i9xx_misc_get_display_clock_speed;
10153 else if (IS_PINEVIEW(dev))
10154 dev_priv->display.get_display_clock_speed =
10155 pnv_get_display_clock_speed;
10156 else if (IS_I915GM(dev))
10157 dev_priv->display.get_display_clock_speed =
10158 i915gm_get_display_clock_speed;
10159 else if (IS_I865G(dev))
10160 dev_priv->display.get_display_clock_speed =
10161 i865_get_display_clock_speed;
10162 else if (IS_I85X(dev))
10163 dev_priv->display.get_display_clock_speed =
10164 i855_get_display_clock_speed;
10165 else /* 852, 830 */
10166 dev_priv->display.get_display_clock_speed =
10167 i830_get_display_clock_speed;
10169 if (HAS_PCH_SPLIT(dev)) {
10170 if (IS_GEN5(dev)) {
10171 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10172 dev_priv->display.write_eld = ironlake_write_eld;
10173 } else if (IS_GEN6(dev)) {
10174 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10175 dev_priv->display.write_eld = ironlake_write_eld;
10176 } else if (IS_IVYBRIDGE(dev)) {
10177 /* FIXME: detect B0+ stepping and use auto training */
10178 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10179 dev_priv->display.write_eld = ironlake_write_eld;
10180 dev_priv->display.modeset_global_resources =
10181 ivb_modeset_global_resources;
10182 } else if (IS_HASWELL(dev)) {
10183 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10184 dev_priv->display.write_eld = haswell_write_eld;
10185 dev_priv->display.modeset_global_resources =
10186 haswell_modeset_global_resources;
10188 } else if (IS_G4X(dev)) {
10189 dev_priv->display.write_eld = g4x_write_eld;
10192 /* Default just returns -ENODEV to indicate unsupported */
10193 dev_priv->display.queue_flip = intel_default_queue_flip;
10195 switch (INTEL_INFO(dev)->gen) {
10197 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10201 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10206 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10210 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10213 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10219 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10220 * resume, or other times. This quirk makes sure that's the case for
10221 * affected systems.
10223 static void quirk_pipea_force(struct drm_device *dev)
10225 struct drm_i915_private *dev_priv = dev->dev_private;
10227 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10228 DRM_INFO("applying pipe a force quirk\n");
10232 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10234 static void quirk_ssc_force_disable(struct drm_device *dev)
10236 struct drm_i915_private *dev_priv = dev->dev_private;
10237 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10238 DRM_INFO("applying lvds SSC disable quirk\n");
10242 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10245 static void quirk_invert_brightness(struct drm_device *dev)
10247 struct drm_i915_private *dev_priv = dev->dev_private;
10248 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10249 DRM_INFO("applying inverted panel brightness quirk\n");
10253 * Some machines (Dell XPS13) suffer broken backlight controls if
10254 * BLM_PCH_PWM_ENABLE is set.
10256 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10258 struct drm_i915_private *dev_priv = dev->dev_private;
10259 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10260 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10263 struct intel_quirk {
10265 int subsystem_vendor;
10266 int subsystem_device;
10267 void (*hook)(struct drm_device *dev);
10270 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10271 struct intel_dmi_quirk {
10272 void (*hook)(struct drm_device *dev);
10273 const struct dmi_system_id (*dmi_id_list)[];
10276 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10278 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10282 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10284 .dmi_id_list = &(const struct dmi_system_id[]) {
10286 .callback = intel_dmi_reverse_brightness,
10287 .ident = "NCR Corporation",
10288 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10289 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10292 { } /* terminating entry */
10294 .hook = quirk_invert_brightness,
10298 static struct intel_quirk intel_quirks[] = {
10299 /* HP Mini needs pipe A force quirk (LP: #322104) */
10300 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10302 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10303 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10305 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10306 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10308 /* 830 needs to leave pipe A & dpll A up */
10309 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10311 /* Lenovo U160 cannot use SSC on LVDS */
10312 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10314 /* Sony Vaio Y cannot use SSC on LVDS */
10315 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10318 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10319 * seem to use inverted backlight PWM.
10321 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10323 /* Dell XPS13 HD Sandy Bridge */
10324 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10325 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10326 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10329 static void intel_init_quirks(struct drm_device *dev)
10331 struct pci_dev *d = dev->pdev;
10334 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10335 struct intel_quirk *q = &intel_quirks[i];
10337 if (d->device == q->device &&
10338 (d->subsystem_vendor == q->subsystem_vendor ||
10339 q->subsystem_vendor == PCI_ANY_ID) &&
10340 (d->subsystem_device == q->subsystem_device ||
10341 q->subsystem_device == PCI_ANY_ID))
10344 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10345 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10346 intel_dmi_quirks[i].hook(dev);
10350 /* Disable the VGA plane that we never use */
10351 static void i915_disable_vga(struct drm_device *dev)
10353 struct drm_i915_private *dev_priv = dev->dev_private;
10355 u32 vga_reg = i915_vgacntrl_reg(dev);
10357 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10358 outb(SR01, VGA_SR_INDEX);
10359 sr1 = inb(VGA_SR_DATA);
10360 outb(sr1 | 1<<5, VGA_SR_DATA);
10361 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10364 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10365 POSTING_READ(vga_reg);
10368 static void i915_enable_vga_mem(struct drm_device *dev)
10370 /* Enable VGA memory on Intel HD */
10371 if (HAS_PCH_SPLIT(dev)) {
10372 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10373 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10374 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10375 VGA_RSRC_LEGACY_MEM |
10376 VGA_RSRC_NORMAL_IO |
10377 VGA_RSRC_NORMAL_MEM);
10378 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10382 void i915_disable_vga_mem(struct drm_device *dev)
10384 /* Disable VGA memory on Intel HD */
10385 if (HAS_PCH_SPLIT(dev)) {
10386 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10387 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10388 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10389 VGA_RSRC_NORMAL_IO |
10390 VGA_RSRC_NORMAL_MEM);
10391 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10395 void intel_modeset_init_hw(struct drm_device *dev)
10397 struct drm_i915_private *dev_priv = dev->dev_private;
10399 intel_prepare_ddi(dev);
10401 intel_init_clock_gating(dev);
10403 /* Enable the CRI clock source so we can get at the display */
10404 if (IS_VALLEYVIEW(dev))
10405 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10406 DPLL_INTEGRATED_CRI_CLK_VLV);
10408 intel_init_dpio(dev);
10410 mutex_lock(&dev->struct_mutex);
10411 intel_enable_gt_powersave(dev);
10412 mutex_unlock(&dev->struct_mutex);
10415 void intel_modeset_suspend_hw(struct drm_device *dev)
10417 intel_suspend_hw(dev);
10420 void intel_modeset_init(struct drm_device *dev)
10422 struct drm_i915_private *dev_priv = dev->dev_private;
10425 drm_mode_config_init(dev);
10427 dev->mode_config.min_width = 0;
10428 dev->mode_config.min_height = 0;
10430 dev->mode_config.preferred_depth = 24;
10431 dev->mode_config.prefer_shadow = 1;
10433 dev->mode_config.funcs = &intel_mode_funcs;
10435 intel_init_quirks(dev);
10437 intel_init_pm(dev);
10439 if (INTEL_INFO(dev)->num_pipes == 0)
10442 intel_init_display(dev);
10444 if (IS_GEN2(dev)) {
10445 dev->mode_config.max_width = 2048;
10446 dev->mode_config.max_height = 2048;
10447 } else if (IS_GEN3(dev)) {
10448 dev->mode_config.max_width = 4096;
10449 dev->mode_config.max_height = 4096;
10451 dev->mode_config.max_width = 8192;
10452 dev->mode_config.max_height = 8192;
10454 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10456 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10457 INTEL_INFO(dev)->num_pipes,
10458 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10461 intel_crtc_init(dev, i);
10462 for (j = 0; j < dev_priv->num_plane; j++) {
10463 ret = intel_plane_init(dev, i, j);
10465 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10466 pipe_name(i), sprite_name(i, j), ret);
10470 intel_cpu_pll_init(dev);
10471 intel_shared_dpll_init(dev);
10473 /* Just disable it once at startup */
10474 i915_disable_vga(dev);
10475 intel_setup_outputs(dev);
10477 /* Just in case the BIOS is doing something questionable. */
10478 intel_disable_fbc(dev);
10482 intel_connector_break_all_links(struct intel_connector *connector)
10484 connector->base.dpms = DRM_MODE_DPMS_OFF;
10485 connector->base.encoder = NULL;
10486 connector->encoder->connectors_active = false;
10487 connector->encoder->base.crtc = NULL;
10490 static void intel_enable_pipe_a(struct drm_device *dev)
10492 struct intel_connector *connector;
10493 struct drm_connector *crt = NULL;
10494 struct intel_load_detect_pipe load_detect_temp;
10496 /* We can't just switch on the pipe A, we need to set things up with a
10497 * proper mode and output configuration. As a gross hack, enable pipe A
10498 * by enabling the load detect pipe once. */
10499 list_for_each_entry(connector,
10500 &dev->mode_config.connector_list,
10502 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10503 crt = &connector->base;
10511 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10512 intel_release_load_detect_pipe(crt, &load_detect_temp);
10518 intel_check_plane_mapping(struct intel_crtc *crtc)
10520 struct drm_device *dev = crtc->base.dev;
10521 struct drm_i915_private *dev_priv = dev->dev_private;
10524 if (INTEL_INFO(dev)->num_pipes == 1)
10527 reg = DSPCNTR(!crtc->plane);
10528 val = I915_READ(reg);
10530 if ((val & DISPLAY_PLANE_ENABLE) &&
10531 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10537 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10539 struct drm_device *dev = crtc->base.dev;
10540 struct drm_i915_private *dev_priv = dev->dev_private;
10543 /* Clear any frame start delays used for debugging left by the BIOS */
10544 reg = PIPECONF(crtc->config.cpu_transcoder);
10545 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10547 /* We need to sanitize the plane -> pipe mapping first because this will
10548 * disable the crtc (and hence change the state) if it is wrong. Note
10549 * that gen4+ has a fixed plane -> pipe mapping. */
10550 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10551 struct intel_connector *connector;
10554 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10555 crtc->base.base.id);
10557 /* Pipe has the wrong plane attached and the plane is active.
10558 * Temporarily change the plane mapping and disable everything
10560 plane = crtc->plane;
10561 crtc->plane = !plane;
10562 dev_priv->display.crtc_disable(&crtc->base);
10563 crtc->plane = plane;
10565 /* ... and break all links. */
10566 list_for_each_entry(connector, &dev->mode_config.connector_list,
10568 if (connector->encoder->base.crtc != &crtc->base)
10571 intel_connector_break_all_links(connector);
10574 WARN_ON(crtc->active);
10575 crtc->base.enabled = false;
10578 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10579 crtc->pipe == PIPE_A && !crtc->active) {
10580 /* BIOS forgot to enable pipe A, this mostly happens after
10581 * resume. Force-enable the pipe to fix this, the update_dpms
10582 * call below we restore the pipe to the right state, but leave
10583 * the required bits on. */
10584 intel_enable_pipe_a(dev);
10587 /* Adjust the state of the output pipe according to whether we
10588 * have active connectors/encoders. */
10589 intel_crtc_update_dpms(&crtc->base);
10591 if (crtc->active != crtc->base.enabled) {
10592 struct intel_encoder *encoder;
10594 /* This can happen either due to bugs in the get_hw_state
10595 * functions or because the pipe is force-enabled due to the
10597 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10598 crtc->base.base.id,
10599 crtc->base.enabled ? "enabled" : "disabled",
10600 crtc->active ? "enabled" : "disabled");
10602 crtc->base.enabled = crtc->active;
10604 /* Because we only establish the connector -> encoder ->
10605 * crtc links if something is active, this means the
10606 * crtc is now deactivated. Break the links. connector
10607 * -> encoder links are only establish when things are
10608 * actually up, hence no need to break them. */
10609 WARN_ON(crtc->active);
10611 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10612 WARN_ON(encoder->connectors_active);
10613 encoder->base.crtc = NULL;
10618 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10620 struct intel_connector *connector;
10621 struct drm_device *dev = encoder->base.dev;
10623 /* We need to check both for a crtc link (meaning that the
10624 * encoder is active and trying to read from a pipe) and the
10625 * pipe itself being active. */
10626 bool has_active_crtc = encoder->base.crtc &&
10627 to_intel_crtc(encoder->base.crtc)->active;
10629 if (encoder->connectors_active && !has_active_crtc) {
10630 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10631 encoder->base.base.id,
10632 drm_get_encoder_name(&encoder->base));
10634 /* Connector is active, but has no active pipe. This is
10635 * fallout from our resume register restoring. Disable
10636 * the encoder manually again. */
10637 if (encoder->base.crtc) {
10638 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10639 encoder->base.base.id,
10640 drm_get_encoder_name(&encoder->base));
10641 encoder->disable(encoder);
10644 /* Inconsistent output/port/pipe state happens presumably due to
10645 * a bug in one of the get_hw_state functions. Or someplace else
10646 * in our code, like the register restore mess on resume. Clamp
10647 * things to off as a safer default. */
10648 list_for_each_entry(connector,
10649 &dev->mode_config.connector_list,
10651 if (connector->encoder != encoder)
10654 intel_connector_break_all_links(connector);
10657 /* Enabled encoders without active connectors will be fixed in
10658 * the crtc fixup. */
10661 void i915_redisable_vga(struct drm_device *dev)
10663 struct drm_i915_private *dev_priv = dev->dev_private;
10664 u32 vga_reg = i915_vgacntrl_reg(dev);
10666 /* This function can be called both from intel_modeset_setup_hw_state or
10667 * at a very early point in our resume sequence, where the power well
10668 * structures are not yet restored. Since this function is at a very
10669 * paranoid "someone might have enabled VGA while we were not looking"
10670 * level, just check if the power well is enabled instead of trying to
10671 * follow the "don't touch the power well if we don't need it" policy
10672 * the rest of the driver uses. */
10673 if (HAS_POWER_WELL(dev) &&
10674 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10677 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
10678 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10679 i915_disable_vga(dev);
10680 i915_disable_vga_mem(dev);
10684 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10686 struct drm_i915_private *dev_priv = dev->dev_private;
10688 struct intel_crtc *crtc;
10689 struct intel_encoder *encoder;
10690 struct intel_connector *connector;
10693 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10695 memset(&crtc->config, 0, sizeof(crtc->config));
10697 crtc->active = dev_priv->display.get_pipe_config(crtc,
10700 crtc->base.enabled = crtc->active;
10702 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10703 crtc->base.base.id,
10704 crtc->active ? "enabled" : "disabled");
10707 /* FIXME: Smash this into the new shared dpll infrastructure. */
10709 intel_ddi_setup_hw_pll_state(dev);
10711 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10712 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10714 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10716 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10718 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10721 pll->refcount = pll->active;
10723 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10724 pll->name, pll->refcount, pll->on);
10727 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10731 if (encoder->get_hw_state(encoder, &pipe)) {
10732 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10733 encoder->base.crtc = &crtc->base;
10734 if (encoder->get_config)
10735 encoder->get_config(encoder, &crtc->config);
10737 encoder->base.crtc = NULL;
10740 encoder->connectors_active = false;
10741 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10742 encoder->base.base.id,
10743 drm_get_encoder_name(&encoder->base),
10744 encoder->base.crtc ? "enabled" : "disabled",
10748 list_for_each_entry(connector, &dev->mode_config.connector_list,
10750 if (connector->get_hw_state(connector)) {
10751 connector->base.dpms = DRM_MODE_DPMS_ON;
10752 connector->encoder->connectors_active = true;
10753 connector->base.encoder = &connector->encoder->base;
10755 connector->base.dpms = DRM_MODE_DPMS_OFF;
10756 connector->base.encoder = NULL;
10758 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10759 connector->base.base.id,
10760 drm_get_connector_name(&connector->base),
10761 connector->base.encoder ? "enabled" : "disabled");
10765 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10766 * and i915 state tracking structures. */
10767 void intel_modeset_setup_hw_state(struct drm_device *dev,
10768 bool force_restore)
10770 struct drm_i915_private *dev_priv = dev->dev_private;
10772 struct intel_crtc *crtc;
10773 struct intel_encoder *encoder;
10776 intel_modeset_readout_hw_state(dev);
10779 * Now that we have the config, copy it to each CRTC struct
10780 * Note that this could go away if we move to using crtc_config
10781 * checking everywhere.
10783 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10785 if (crtc->active && i915_fastboot) {
10786 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10788 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10789 crtc->base.base.id);
10790 drm_mode_debug_printmodeline(&crtc->base.mode);
10794 /* HW state is read out, now we need to sanitize this mess. */
10795 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10797 intel_sanitize_encoder(encoder);
10800 for_each_pipe(pipe) {
10801 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10802 intel_sanitize_crtc(crtc);
10803 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10806 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10807 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10809 if (!pll->on || pll->active)
10812 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10814 pll->disable(dev_priv, pll);
10818 if (force_restore) {
10819 i915_redisable_vga(dev);
10822 * We need to use raw interfaces for restoring state to avoid
10823 * checking (bogus) intermediate states.
10825 for_each_pipe(pipe) {
10826 struct drm_crtc *crtc =
10827 dev_priv->pipe_to_crtc_mapping[pipe];
10829 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10833 intel_modeset_update_staged_output_state(dev);
10836 intel_modeset_check_state(dev);
10838 drm_mode_config_reset(dev);
10841 void intel_modeset_gem_init(struct drm_device *dev)
10843 intel_modeset_init_hw(dev);
10845 intel_setup_overlay(dev);
10847 intel_modeset_setup_hw_state(dev, false);
10850 void intel_modeset_cleanup(struct drm_device *dev)
10852 struct drm_i915_private *dev_priv = dev->dev_private;
10853 struct drm_crtc *crtc;
10854 struct drm_connector *connector;
10857 * Interrupts and polling as the first thing to avoid creating havoc.
10858 * Too much stuff here (turning of rps, connectors, ...) would
10859 * experience fancy races otherwise.
10861 drm_irq_uninstall(dev);
10862 cancel_work_sync(&dev_priv->hotplug_work);
10864 * Due to the hpd irq storm handling the hotplug work can re-arm the
10865 * poll handlers. Hence disable polling after hpd handling is shut down.
10867 drm_kms_helper_poll_fini(dev);
10869 mutex_lock(&dev->struct_mutex);
10871 intel_unregister_dsm_handler();
10873 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10874 /* Skip inactive CRTCs */
10878 intel_increase_pllclock(crtc);
10881 intel_disable_fbc(dev);
10883 i915_enable_vga_mem(dev);
10885 intel_disable_gt_powersave(dev);
10887 ironlake_teardown_rc6(dev);
10889 mutex_unlock(&dev->struct_mutex);
10891 /* flush any delayed tasks or pending work */
10892 flush_scheduled_work();
10894 /* destroy backlight, if any, before the connectors */
10895 intel_panel_destroy_backlight(dev);
10897 /* destroy the sysfs files before encoders/connectors */
10898 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10899 drm_sysfs_connector_remove(connector);
10901 drm_mode_config_cleanup(dev);
10903 intel_cleanup_overlay(dev);
10907 * Return which encoder is currently attached for connector.
10909 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10911 return &intel_attached_encoder(connector)->base;
10914 void intel_connector_attach_encoder(struct intel_connector *connector,
10915 struct intel_encoder *encoder)
10917 connector->encoder = encoder;
10918 drm_mode_connector_attach_encoder(&connector->base,
10923 * set vga decode state - true == enable VGA decode
10925 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10927 struct drm_i915_private *dev_priv = dev->dev_private;
10930 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10932 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10934 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10935 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10939 struct intel_display_error_state {
10941 u32 power_well_driver;
10943 int num_transcoders;
10945 struct intel_cursor_error_state {
10950 } cursor[I915_MAX_PIPES];
10952 struct intel_pipe_error_state {
10954 } pipe[I915_MAX_PIPES];
10956 struct intel_plane_error_state {
10964 } plane[I915_MAX_PIPES];
10966 struct intel_transcoder_error_state {
10967 enum transcoder cpu_transcoder;
10980 struct intel_display_error_state *
10981 intel_display_capture_error_state(struct drm_device *dev)
10983 drm_i915_private_t *dev_priv = dev->dev_private;
10984 struct intel_display_error_state *error;
10985 int transcoders[] = {
10993 if (INTEL_INFO(dev)->num_pipes == 0)
10996 error = kmalloc(sizeof(*error), GFP_ATOMIC);
11000 if (HAS_POWER_WELL(dev))
11001 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11004 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11005 error->cursor[i].control = I915_READ(CURCNTR(i));
11006 error->cursor[i].position = I915_READ(CURPOS(i));
11007 error->cursor[i].base = I915_READ(CURBASE(i));
11009 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11010 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11011 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11014 error->plane[i].control = I915_READ(DSPCNTR(i));
11015 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11016 if (INTEL_INFO(dev)->gen <= 3) {
11017 error->plane[i].size = I915_READ(DSPSIZE(i));
11018 error->plane[i].pos = I915_READ(DSPPOS(i));
11020 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11021 error->plane[i].addr = I915_READ(DSPADDR(i));
11022 if (INTEL_INFO(dev)->gen >= 4) {
11023 error->plane[i].surface = I915_READ(DSPSURF(i));
11024 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11027 error->pipe[i].source = I915_READ(PIPESRC(i));
11030 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11031 if (HAS_DDI(dev_priv->dev))
11032 error->num_transcoders++; /* Account for eDP. */
11034 for (i = 0; i < error->num_transcoders; i++) {
11035 enum transcoder cpu_transcoder = transcoders[i];
11037 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11039 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11040 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11041 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11042 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11043 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11044 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11045 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11048 /* In the code above we read the registers without checking if the power
11049 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11050 * prevent the next I915_WRITE from detecting it and printing an error
11052 intel_uncore_clear_errors(dev);
11057 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11060 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11061 struct drm_device *dev,
11062 struct intel_display_error_state *error)
11069 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11070 if (HAS_POWER_WELL(dev))
11071 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11072 error->power_well_driver);
11074 err_printf(m, "Pipe [%d]:\n", i);
11075 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
11077 err_printf(m, "Plane [%d]:\n", i);
11078 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11079 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
11080 if (INTEL_INFO(dev)->gen <= 3) {
11081 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11082 err_printf(m, " POS: %08x\n", error->plane[i].pos);
11084 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11085 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
11086 if (INTEL_INFO(dev)->gen >= 4) {
11087 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11088 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
11091 err_printf(m, "Cursor [%d]:\n", i);
11092 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11093 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11094 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
11097 for (i = 0; i < error->num_transcoders; i++) {
11098 err_printf(m, " CPU transcoder: %c\n",
11099 transcoder_name(error->transcoder[i].cpu_transcoder));
11100 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11101 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11102 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11103 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11104 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11105 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11106 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);