drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54 static int intel_framebuffer_init(struct drm_device *dev,
  55                                   struct intel_framebuffer *ifb,
  56                                   struct drm_mode_fb_cmd2 *mode_cmd,
  57                                   struct drm_i915_gem_object *obj);
  58
  59 typedef struct {
  60         int     min, max;
  61 } intel_range_t;
  62
  63 typedef struct {
  64         int     dot_limit;
  65         int     p2_slow, p2_fast;
  66 } intel_p2_t;
  67
  68 typedef struct intel_limit intel_limit_t;
  69 struct intel_limit {
  70         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  71         intel_p2_t          p2;
  72 };
  73
  74 int
  75 intel_pch_rawclk(struct drm_device *dev)
  76 {
  77         struct drm_i915_private *dev_priv = dev->dev_private;
  78
  79         WARN_ON(!HAS_PCH_SPLIT(dev));
  80
  81         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  82 }
  83
  84 static inline u32 /* units of 100MHz */
  85 intel_fdi_link_freq(struct drm_device *dev)
  86 {
  87         if (IS_GEN5(dev)) {
  88                 struct drm_i915_private *dev_priv = dev->dev_private;
  89                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  90         } else
  91                 return 27;
  92 }
  93
  94 static const intel_limit_t intel_limits_i8xx_dac = {
  95         .dot = { .min = 25000, .max = 350000 },
  96         .vco = { .min = 908000, .max = 1512000 },
  97         .n = { .min = 2, .max = 16 },
  98         .m = { .min = 96, .max = 140 },
  99         .m1 = { .min = 18, .max = 26 },
 100         .m2 = { .min = 6, .max = 16 },
 101         .p = { .min = 4, .max = 128 },
 102         .p1 = { .min = 2, .max = 33 },
 103         .p2 = { .dot_limit = 165000,
 104                 .p2_slow = 4, .p2_fast = 2 },
 105 };
 106
 107 static const intel_limit_t intel_limits_i8xx_dvo = {
 108         .dot = { .min = 25000, .max = 350000 },
 109         .vco = { .min = 908000, .max = 1512000 },
 110         .n = { .min = 2, .max = 16 },
 111         .m = { .min = 96, .max = 140 },
 112         .m1 = { .min = 18, .max = 26 },
 113         .m2 = { .min = 6, .max = 16 },
 114         .p = { .min = 4, .max = 128 },
 115         .p1 = { .min = 2, .max = 33 },
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 4, .p2_fast = 4 },
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 908000, .max = 1512000 },
 123         .n = { .min = 2, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131 };
 132
 133 static const intel_limit_t intel_limits_i9xx_sdvo = {
 134         .dot = { .min = 20000, .max = 400000 },
 135         .vco = { .min = 1400000, .max = 2800000 },
 136         .n = { .min = 1, .max = 6 },
 137         .m = { .min = 70, .max = 120 },
 138         .m1 = { .min = 8, .max = 18 },
 139         .m2 = { .min = 3, .max = 7 },
 140         .p = { .min = 5, .max = 80 },
 141         .p1 = { .min = 1, .max = 8 },
 142         .p2 = { .dot_limit = 200000,
 143                 .p2_slow = 10, .p2_fast = 5 },
 144 };
 145
 146 static const intel_limit_t intel_limits_i9xx_lvds = {
 147         .dot = { .min = 20000, .max = 400000 },
 148         .vco = { .min = 1400000, .max = 2800000 },
 149         .n = { .min = 1, .max = 6 },
 150         .m = { .min = 70, .max = 120 },
 151         .m1 = { .min = 8, .max = 18 },
 152         .m2 = { .min = 3, .max = 7 },
 153         .p = { .min = 7, .max = 98 },
 154         .p1 = { .min = 1, .max = 8 },
 155         .p2 = { .dot_limit = 112000,
 156                 .p2_slow = 14, .p2_fast = 7 },
 157 };
 158
 159
 160 static const intel_limit_t intel_limits_g4x_sdvo = {
 161         .dot = { .min = 25000, .max = 270000 },
 162         .vco = { .min = 1750000, .max = 3500000},
 163         .n = { .min = 1, .max = 4 },
 164         .m = { .min = 104, .max = 138 },
 165         .m1 = { .min = 17, .max = 23 },
 166         .m2 = { .min = 5, .max = 11 },
 167         .p = { .min = 10, .max = 30 },
 168         .p1 = { .min = 1, .max = 3},
 169         .p2 = { .dot_limit = 270000,
 170                 .p2_slow = 10,
 171                 .p2_fast = 10
 172         },
 173 };
 174
 175 static const intel_limit_t intel_limits_g4x_hdmi = {
 176         .dot = { .min = 22000, .max = 400000 },
 177         .vco = { .min = 1750000, .max = 3500000},
 178         .n = { .min = 1, .max = 4 },
 179         .m = { .min = 104, .max = 138 },
 180         .m1 = { .min = 16, .max = 23 },
 181         .m2 = { .min = 5, .max = 11 },
 182         .p = { .min = 5, .max = 80 },
 183         .p1 = { .min = 1, .max = 8},
 184         .p2 = { .dot_limit = 165000,
 185                 .p2_slow = 10, .p2_fast = 5 },
 186 };
 187
 188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 189         .dot = { .min = 20000, .max = 115000 },
 190         .vco = { .min = 1750000, .max = 3500000 },
 191         .n = { .min = 1, .max = 3 },
 192         .m = { .min = 104, .max = 138 },
 193         .m1 = { .min = 17, .max = 23 },
 194         .m2 = { .min = 5, .max = 11 },
 195         .p = { .min = 28, .max = 112 },
 196         .p1 = { .min = 2, .max = 8 },
 197         .p2 = { .dot_limit = 0,
 198                 .p2_slow = 14, .p2_fast = 14
 199         },
 200 };
 201
 202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 203         .dot = { .min = 80000, .max = 224000 },
 204         .vco = { .min = 1750000, .max = 3500000 },
 205         .n = { .min = 1, .max = 3 },
 206         .m = { .min = 104, .max = 138 },
 207         .m1 = { .min = 17, .max = 23 },
 208         .m2 = { .min = 5, .max = 11 },
 209         .p = { .min = 14, .max = 42 },
 210         .p1 = { .min = 2, .max = 6 },
 211         .p2 = { .dot_limit = 0,
 212                 .p2_slow = 7, .p2_fast = 7
 213         },
 214 };
 215
 216 static const intel_limit_t intel_limits_pineview_sdvo = {
 217         .dot = { .min = 20000, .max = 400000},
 218         .vco = { .min = 1700000, .max = 3500000 },
 219         /* Pineview's Ncounter is a ring counter */
 220         .n = { .min = 3, .max = 6 },
 221         .m = { .min = 2, .max = 256 },
 222         /* Pineview only has one combined m divider, which we treat as m2. */
 223         .m1 = { .min = 0, .max = 0 },
 224         .m2 = { .min = 0, .max = 254 },
 225         .p = { .min = 5, .max = 80 },
 226         .p1 = { .min = 1, .max = 8 },
 227         .p2 = { .dot_limit = 200000,
 228                 .p2_slow = 10, .p2_fast = 5 },
 229 };
 230
 231 static const intel_limit_t intel_limits_pineview_lvds = {
 232         .dot = { .min = 20000, .max = 400000 },
 233         .vco = { .min = 1700000, .max = 3500000 },
 234         .n = { .min = 3, .max = 6 },
 235         .m = { .min = 2, .max = 256 },
 236         .m1 = { .min = 0, .max = 0 },
 237         .m2 = { .min = 0, .max = 254 },
 238         .p = { .min = 7, .max = 112 },
 239         .p1 = { .min = 1, .max = 8 },
 240         .p2 = { .dot_limit = 112000,
 241                 .p2_slow = 14, .p2_fast = 14 },
 242 };
 243
 244 /* Ironlake / Sandybridge
 245  *
 246  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 247  * the range value for them is (actual_value - 2).
 248  */
 249 static const intel_limit_t intel_limits_ironlake_dac = {
 250         .dot = { .min = 25000, .max = 350000 },
 251         .vco = { .min = 1760000, .max = 3510000 },
 252         .n = { .min = 1, .max = 5 },
 253         .m = { .min = 79, .max = 127 },
 254         .m1 = { .min = 12, .max = 22 },
 255         .m2 = { .min = 5, .max = 9 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 225000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260 };
 261
 262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 263         .dot = { .min = 25000, .max = 350000 },
 264         .vco = { .min = 1760000, .max = 3510000 },
 265         .n = { .min = 1, .max = 3 },
 266         .m = { .min = 79, .max = 118 },
 267         .m1 = { .min = 12, .max = 22 },
 268         .m2 = { .min = 5, .max = 9 },
 269         .p = { .min = 28, .max = 112 },
 270         .p1 = { .min = 2, .max = 8 },
 271         .p2 = { .dot_limit = 225000,
 272                 .p2_slow = 14, .p2_fast = 14 },
 273 };
 274
 275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 276         .dot = { .min = 25000, .max = 350000 },
 277         .vco = { .min = 1760000, .max = 3510000 },
 278         .n = { .min = 1, .max = 3 },
 279         .m = { .min = 79, .max = 127 },
 280         .m1 = { .min = 12, .max = 22 },
 281         .m2 = { .min = 5, .max = 9 },
 282         .p = { .min = 14, .max = 56 },
 283         .p1 = { .min = 2, .max = 8 },
 284         .p2 = { .dot_limit = 225000,
 285                 .p2_slow = 7, .p2_fast = 7 },
 286 };
 287
 288 /* LVDS 100mhz refclk limits. */
 289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 1760000, .max = 3510000 },
 292         .n = { .min = 1, .max = 2 },
 293         .m = { .min = 79, .max = 126 },
 294         .m1 = { .min = 12, .max = 22 },
 295         .m2 = { .min = 5, .max = 9 },
 296         .p = { .min = 28, .max = 112 },
 297         .p1 = { .min = 2, .max = 8 },
 298         .p2 = { .dot_limit = 225000,
 299                 .p2_slow = 14, .p2_fast = 14 },
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 126 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 42 },
 310         .p1 = { .min = 2, .max = 6 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313 };
 314
 315 static const intel_limit_t intel_limits_vlv = {
 316          /*
 317           * These are the data rate limits (measured in fast clocks)
 318           * since those are the strictest limits we have. The fast
 319           * clock and actual rate limits are more relaxed, so checking
 320           * them would make no difference.
 321           */
 322         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m1 = { .min = 2, .max = 3 },
 326         .m2 = { .min = 11, .max = 156 },
 327         .p1 = { .min = 2, .max = 3 },
 328         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 329 };
 330
 331 static void vlv_clock(int refclk, intel_clock_t *clock)
 332 {
 333         clock->m = clock->m1 * clock->m2;
 334         clock->p = clock->p1 * clock->p2;
 335         if (WARN_ON(clock->n == 0 || clock->p == 0))
 336                 return;
 337         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 338         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 339 }
 340
 341 /**
 342  * Returns whether any output on the specified pipe is of the specified type
 343  */
 344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 345 {
 346         struct drm_device *dev = crtc->dev;
 347         struct intel_encoder *encoder;
 348
 349         for_each_encoder_on_crtc(dev, crtc, encoder)
 350                 if (encoder->type == type)
 351                         return true;
 352
 353         return false;
 354 }
 355
 356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 357                                                 int refclk)
 358 {
 359         struct drm_device *dev = crtc->dev;
 360         const intel_limit_t *limit;
 361
 362         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 363                 if (intel_is_dual_link_lvds(dev)) {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_dual_lvds;
 368                 } else {
 369                         if (refclk == 100000)
 370                                 limit = &intel_limits_ironlake_single_lvds_100m;
 371                         else
 372                                 limit = &intel_limits_ironlake_single_lvds;
 373                 }
 374         } else
 375                 limit = &intel_limits_ironlake_dac;
 376
 377         return limit;
 378 }
 379
 380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 381 {
 382         struct drm_device *dev = crtc->dev;
 383         const intel_limit_t *limit;
 384
 385         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 386                 if (intel_is_dual_link_lvds(dev))
 387                         limit = &intel_limits_g4x_dual_channel_lvds;
 388                 else
 389                         limit = &intel_limits_g4x_single_channel_lvds;
 390         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 391                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 392                 limit = &intel_limits_g4x_hdmi;
 393         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 394                 limit = &intel_limits_g4x_sdvo;
 395         } else /* The option is for other outputs */
 396                 limit = &intel_limits_i9xx_sdvo;
 397
 398         return limit;
 399 }
 400
 401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 402 {
 403         struct drm_device *dev = crtc->dev;
 404         const intel_limit_t *limit;
 405
 406         if (HAS_PCH_SPLIT(dev))
 407                 limit = intel_ironlake_limit(crtc, refclk);
 408         else if (IS_G4X(dev)) {
 409                 limit = intel_g4x_limit(crtc);
 410         } else if (IS_PINEVIEW(dev)) {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 412                         limit = &intel_limits_pineview_lvds;
 413                 else
 414                         limit = &intel_limits_pineview_sdvo;
 415         } else if (IS_VALLEYVIEW(dev)) {
 416                 limit = &intel_limits_vlv;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         if (WARN_ON(clock->n == 0 || clock->p == 0))
 439                 return;
 440         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 441         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 442 }
 443
 444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 445 {
 446         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 447 }
 448
 449 static void i9xx_clock(int refclk, intel_clock_t *clock)
 450 {
 451         clock->m = i9xx_dpll_compute_m(clock);
 452         clock->p = clock->p1 * clock->p2;
 453         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 454                 return;
 455         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 456         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 457 }
 458
 459 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 460 /**
 461  * Returns whether the given set of divisors are valid for a given refclk with
 462  * the given connectors.
 463  */
 464
 465 static bool intel_PLL_is_valid(struct drm_device *dev,
 466                                const intel_limit_t *limit,
 467                                const intel_clock_t *clock)
 468 {
 469         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 470                 INTELPllInvalid("n out of range\n");
 471         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 472                 INTELPllInvalid("p1 out of range\n");
 473         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 474                 INTELPllInvalid("m2 out of range\n");
 475         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 476                 INTELPllInvalid("m1 out of range\n");
 477
 478         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 479                 if (clock->m1 <= clock->m2)
 480                         INTELPllInvalid("m1 <= m2\n");
 481
 482         if (!IS_VALLEYVIEW(dev)) {
 483                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 484                         INTELPllInvalid("p out of range\n");
 485                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 486                         INTELPllInvalid("m out of range\n");
 487         }
 488
 489         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 490                 INTELPllInvalid("vco out of range\n");
 491         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 492          * connector, etc., rather than just a single range.
 493          */
 494         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 495                 INTELPllInvalid("dot out of range\n");
 496
 497         return true;
 498 }
 499
 500 static bool
 501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 502                     int target, int refclk, intel_clock_t *match_clock,
 503                     intel_clock_t *best_clock)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         intel_clock_t clock;
 507         int err = target;
 508
 509         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 510                 /*
 511                  * For LVDS just rely on its current settings for dual-channel.
 512                  * We haven't figured out how to reliably set up different
 513                  * single/dual channel state, if we even can.
 514                  */
 515                 if (intel_is_dual_link_lvds(dev))
 516                         clock.p2 = limit->p2.p2_fast;
 517                 else
 518                         clock.p2 = limit->p2.p2_slow;
 519         } else {
 520                 if (target < limit->p2.dot_limit)
 521                         clock.p2 = limit->p2.p2_slow;
 522                 else
 523                         clock.p2 = limit->p2.p2_fast;
 524         }
 525
 526         memset(best_clock, 0, sizeof(*best_clock));
 527
 528         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 529              clock.m1++) {
 530                 for (clock.m2 = limit->m2.min;
 531                      clock.m2 <= limit->m2.max; clock.m2++) {
 532                         if (clock.m2 >= clock.m1)
 533                                 break;
 534                         for (clock.n = limit->n.min;
 535                              clock.n <= limit->n.max; clock.n++) {
 536                                 for (clock.p1 = limit->p1.min;
 537                                         clock.p1 <= limit->p1.max; clock.p1++) {
 538                                         int this_err;
 539
 540                                         i9xx_clock(refclk, &clock);
 541                                         if (!intel_PLL_is_valid(dev, limit,
 542                                                                 &clock))
 543                                                 continue;
 544                                         if (match_clock &&
 545                                             clock.p != match_clock->p)
 546                                                 continue;
 547
 548                                         this_err = abs(clock.dot - target);
 549                                         if (this_err < err) {
 550                                                 *best_clock = clock;
 551                                                 err = this_err;
 552                                         }
 553                                 }
 554                         }
 555                 }
 556         }
 557
 558         return (err != target);
 559 }
 560
 561 static bool
 562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 563                    int target, int refclk, intel_clock_t *match_clock,
 564                    intel_clock_t *best_clock)
 565 {
 566         struct drm_device *dev = crtc->dev;
 567         intel_clock_t clock;
 568         int err = target;
 569
 570         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 571                 /*
 572                  * For LVDS just rely on its current settings for dual-channel.
 573                  * We haven't figured out how to reliably set up different
 574                  * single/dual channel state, if we even can.
 575                  */
 576                 if (intel_is_dual_link_lvds(dev))
 577                         clock.p2 = limit->p2.p2_fast;
 578                 else
 579                         clock.p2 = limit->p2.p2_slow;
 580         } else {
 581                 if (target < limit->p2.dot_limit)
 582                         clock.p2 = limit->p2.p2_slow;
 583                 else
 584                         clock.p2 = limit->p2.p2_fast;
 585         }
 586
 587         memset(best_clock, 0, sizeof(*best_clock));
 588
 589         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 590              clock.m1++) {
 591                 for (clock.m2 = limit->m2.min;
 592                      clock.m2 <= limit->m2.max; clock.m2++) {
 593                         for (clock.n = limit->n.min;
 594                              clock.n <= limit->n.max; clock.n++) {
 595                                 for (clock.p1 = limit->p1.min;
 596                                         clock.p1 <= limit->p1.max; clock.p1++) {
 597                                         int this_err;
 598
 599                                         pineview_clock(refclk, &clock);
 600                                         if (!intel_PLL_is_valid(dev, limit,
 601                                                                 &clock))
 602                                                 continue;
 603                                         if (match_clock &&
 604                                             clock.p != match_clock->p)
 605                                                 continue;
 606
 607                                         this_err = abs(clock.dot - target);
 608                                         if (this_err < err) {
 609                                                 *best_clock = clock;
 610                                                 err = this_err;
 611                                         }
 612                                 }
 613                         }
 614                 }
 615         }
 616
 617         return (err != target);
 618 }
 619
 620 static bool
 621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 622                    int target, int refclk, intel_clock_t *match_clock,
 623                    intel_clock_t *best_clock)
 624 {
 625         struct drm_device *dev = crtc->dev;
 626         intel_clock_t clock;
 627         int max_n;
 628         bool found;
 629         /* approximately equals target * 0.00585 */
 630         int err_most = (target >> 8) + (target >> 9);
 631         found = false;
 632
 633         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 634                 if (intel_is_dual_link_lvds(dev))
 635                         clock.p2 = limit->p2.p2_fast;
 636                 else
 637                         clock.p2 = limit->p2.p2_slow;
 638         } else {
 639                 if (target < limit->p2.dot_limit)
 640                         clock.p2 = limit->p2.p2_slow;
 641                 else
 642                         clock.p2 = limit->p2.p2_fast;
 643         }
 644
 645         memset(best_clock, 0, sizeof(*best_clock));
 646         max_n = limit->n.max;
 647         /* based on hardware requirement, prefer smaller n to precision */
 648         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 649                 /* based on hardware requirement, prefere larger m1,m2 */
 650                 for (clock.m1 = limit->m1.max;
 651                      clock.m1 >= limit->m1.min; clock.m1--) {
 652                         for (clock.m2 = limit->m2.max;
 653                              clock.m2 >= limit->m2.min; clock.m2--) {
 654                                 for (clock.p1 = limit->p1.max;
 655                                      clock.p1 >= limit->p1.min; clock.p1--) {
 656                                         int this_err;
 657
 658                                         i9xx_clock(refclk, &clock);
 659                                         if (!intel_PLL_is_valid(dev, limit,
 660                                                                 &clock))
 661                                                 continue;
 662
 663                                         this_err = abs(clock.dot - target);
 664                                         if (this_err < err_most) {
 665                                                 *best_clock = clock;
 666                                                 err_most = this_err;
 667                                                 max_n = clock.n;
 668                                                 found = true;
 669                                         }
 670                                 }
 671                         }
 672                 }
 673         }
 674         return found;
 675 }
 676
 677 static bool
 678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                    int target, int refclk, intel_clock_t *match_clock,
 680                    intel_clock_t *best_clock)
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         intel_clock_t clock;
 684         unsigned int bestppm = 1000000;
 685         /* min update 19.2 MHz */
 686         int max_n = min(limit->n.max, refclk / 19200);
 687         bool found = false;
 688
 689         target *= 5; /* fast clock */
 690
 691         memset(best_clock, 0, sizeof(*best_clock));
 692
 693         /* based on hardware requirement, prefer smaller n to precision */
 694         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 695                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 696                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 697                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 698                                 clock.p = clock.p1 * clock.p2;
 699                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 700                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 701                                         unsigned int ppm, diff;
 702
 703                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 704                                                                      refclk * clock.m1);
 705
 706                                         vlv_clock(refclk, &clock);
 707
 708                                         if (!intel_PLL_is_valid(dev, limit,
 709                                                                 &clock))
 710                                                 continue;
 711
 712                                         diff = abs(clock.dot - target);
 713                                         ppm = div_u64(1000000ULL * diff, target);
 714
 715                                         if (ppm < 100 && clock.p > best_clock->p) {
 716                                                 bestppm = 0;
 717                                                 *best_clock = clock;
 718                                                 found = true;
 719                                         }
 720
 721                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 722                                                 bestppm = ppm;
 723                                                 *best_clock = clock;
 724                                                 found = true;
 725                                         }
 726                                 }
 727                         }
 728                 }
 729         }
 730
 731         return found;
 732 }
 733
 734 bool intel_crtc_active(struct drm_crtc *crtc)
 735 {
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         /* Be paranoid as we can arrive here with only partial
 739          * state retrieved from the hardware during setup.
 740          *
 741          * We can ditch the adjusted_mode.crtc_clock check as soon
 742          * as Haswell has gained clock readout/fastboot support.
 743          *
 744          * We can ditch the crtc->primary->fb check as soon as we can
 745          * properly reconstruct framebuffers.
 746          */
 747         return intel_crtc->active && crtc->primary->fb &&
 748                 intel_crtc->config.adjusted_mode.crtc_clock;
 749 }
 750
 751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 752                                              enum pipe pipe)
 753 {
 754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 756
 757         return intel_crtc->config.cpu_transcoder;
 758 }
 759
 760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 764
 765         frame = I915_READ(frame_reg);
 766
 767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 768                 WARN(1, "vblank wait timed out\n");
 769 }
 770
 771 /**
 772  * intel_wait_for_vblank - wait for vblank on a given pipe
 773  * @dev: drm device
 774  * @pipe: pipe to wait for
 775  *
 776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 777  * mode setting code.
 778  */
 779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int pipestat_reg = PIPESTAT(pipe);
 783
 784         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 785                 g4x_wait_for_vblank(dev, pipe);
 786                 return;
 787         }
 788
 789         /* Clear existing vblank status. Note this will clear any other
 790          * sticky status fields as well.
 791          *
 792          * This races with i915_driver_irq_handler() with the result
 793          * that either function could miss a vblank event.  Here it is not
 794          * fatal, as we will either wait upon the next vblank interrupt or
 795          * timeout.  Generally speaking intel_wait_for_vblank() is only
 796          * called during modeset at which time the GPU should be idle and
 797          * should *not* be performing page flips and thus not waiting on
 798          * vblanks...
 799          * Currently, the result of us stealing a vblank from the irq
 800          * handler is that a single frame will be skipped during swapbuffers.
 801          */
 802         I915_WRITE(pipestat_reg,
 803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 804
 805         /* Wait for vblank interrupt bit to set */
 806         if (wait_for(I915_READ(pipestat_reg) &
 807                      PIPE_VBLANK_INTERRUPT_STATUS,
 808                      50))
 809                 DRM_DEBUG_KMS("vblank wait timed out\n");
 810 }
 811
 812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 813 {
 814         struct drm_i915_private *dev_priv = dev->dev_private;
 815         u32 reg = PIPEDSL(pipe);
 816         u32 line1, line2;
 817         u32 line_mask;
 818
 819         if (IS_GEN2(dev))
 820                 line_mask = DSL_LINEMASK_GEN2;
 821         else
 822                 line_mask = DSL_LINEMASK_GEN3;
 823
 824         line1 = I915_READ(reg) & line_mask;
 825         mdelay(5);
 826         line2 = I915_READ(reg) & line_mask;
 827
 828         return line1 == line2;
 829 }
 830
 831 /*
 832  * intel_wait_for_pipe_off - wait for pipe to turn off
 833  * @dev: drm device
 834  * @pipe: pipe to wait for
 835  *
 836  * After disabling a pipe, we can't wait for vblank in the usual way,
 837  * spinning on the vblank interrupt status bit, since we won't actually
 838  * see an interrupt when the pipe is disabled.
 839  *
 840  * On Gen4 and above:
 841  *   wait for the pipe register state bit to turn off
 842  *
 843  * Otherwise:
 844  *   wait for the display line value to settle (it usually
 845  *   ends up stopping at the start of the next frame).
 846  *
 847  */
 848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 852                                                                       pipe);
 853
 854         if (INTEL_INFO(dev)->gen >= 4) {
 855                 int reg = PIPECONF(cpu_transcoder);
 856
 857                 /* Wait for the Pipe State to go off */
 858                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 859                              100))
 860                         WARN(1, "pipe_off wait timed out\n");
 861         } else {
 862                 /* Wait for the display line to settle */
 863                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 864                         WARN(1, "pipe_off wait timed out\n");
 865         }
 866 }
 867
 868 /*
 869  * ibx_digital_port_connected - is the specified port connected?
 870  * @dev_priv: i915 private structure
 871  * @port: the port to test
 872  *
 873  * Returns true if @port is connected, false otherwise.
 874  */
 875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 876                                 struct intel_digital_port *port)
 877 {
 878         u32 bit;
 879
 880         if (HAS_PCH_IBX(dev_priv->dev)) {
 881                 switch(port->port) {
 882                 case PORT_B:
 883                         bit = SDE_PORTB_HOTPLUG;
 884                         break;
 885                 case PORT_C:
 886                         bit = SDE_PORTC_HOTPLUG;
 887                         break;
 888                 case PORT_D:
 889                         bit = SDE_PORTD_HOTPLUG;
 890                         break;
 891                 default:
 892                         return true;
 893                 }
 894         } else {
 895                 switch(port->port) {
 896                 case PORT_B:
 897                         bit = SDE_PORTB_HOTPLUG_CPT;
 898                         break;
 899                 case PORT_C:
 900                         bit = SDE_PORTC_HOTPLUG_CPT;
 901                         break;
 902                 case PORT_D:
 903                         bit = SDE_PORTD_HOTPLUG_CPT;
 904                         break;
 905                 default:
 906                         return true;
 907                 }
 908         }
 909
 910         return I915_READ(SDEISR) & bit;
 911 }
 912
 913 static const char *state_string(bool enabled)
 914 {
 915         return enabled ? "on" : "off";
 916 }
 917
 918 /* Only for pre-ILK configs */
 919 void assert_pll(struct drm_i915_private *dev_priv,
 920                 enum pipe pipe, bool state)
 921 {
 922         int reg;
 923         u32 val;
 924         bool cur_state;
 925
 926         reg = DPLL(pipe);
 927         val = I915_READ(reg);
 928         cur_state = !!(val & DPLL_VCO_ENABLE);
 929         WARN(cur_state != state,
 930              "PLL state assertion failure (expected %s, current %s)\n",
 931              state_string(state), state_string(cur_state));
 932 }
 933
 934 /* XXX: the dsi pll is shared between MIPI DSI ports */
 935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 936 {
 937         u32 val;
 938         bool cur_state;
 939
 940         mutex_lock(&dev_priv->dpio_lock);
 941         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 942         mutex_unlock(&dev_priv->dpio_lock);
 943
 944         cur_state = val & DSI_PLL_VCO_EN;
 945         WARN(cur_state != state,
 946              "DSI PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 951
 952 struct intel_shared_dpll *
 953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 954 {
 955         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 956
 957         if (crtc->config.shared_dpll < 0)
 958                 return NULL;
 959
 960         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 961 }
 962
 963 /* For ILK+ */
 964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 965                         struct intel_shared_dpll *pll,
 966                         bool state)
 967 {
 968         bool cur_state;
 969         struct intel_dpll_hw_state hw_state;
 970
 971         if (HAS_PCH_LPT(dev_priv->dev)) {
 972                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 973                 return;
 974         }
 975
 976         if (WARN (!pll,
 977                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 978                 return;
 979
 980         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 981         WARN(cur_state != state,
 982              "%s assertion failure (expected %s, current %s)\n",
 983              pll->name, state_string(state), state_string(cur_state));
 984 }
 985
 986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 987                           enum pipe pipe, bool state)
 988 {
 989         int reg;
 990         u32 val;
 991         bool cur_state;
 992         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 993                                                                       pipe);
 994
 995         if (HAS_DDI(dev_priv->dev)) {
 996                 /* DDI does not have a specific FDI_TX register */
 997                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 998                 val = I915_READ(reg);
 999                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000         } else {
1001                 reg = FDI_TX_CTL(pipe);
1002                 val = I915_READ(reg);
1003                 cur_state = !!(val & FDI_TX_ENABLE);
1004         }
1005         WARN(cur_state != state,
1006              "FDI TX state assertion failure (expected %s, current %s)\n",
1007              state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013                           enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = FDI_RX_CTL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & FDI_RX_ENABLE);
1022         WARN(cur_state != state,
1023              "FDI RX state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030                                       enum pipe pipe)
1031 {
1032         int reg;
1033         u32 val;
1034
1035         /* ILK FDI PLL is always enabled */
1036         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037                 return;
1038
1039         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040         if (HAS_DDI(dev_priv->dev))
1041                 return;
1042
1043         reg = FDI_TX_CTL(pipe);
1044         val = I915_READ(reg);
1045         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049                        enum pipe pipe, bool state)
1050 {
1051         int reg;
1052         u32 val;
1053         bool cur_state;
1054
1055         reg = FDI_RX_CTL(pipe);
1056         val = I915_READ(reg);
1057         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058         WARN(cur_state != state,
1059              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060              state_string(state), state_string(cur_state));
1061 }
1062
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064                                   enum pipe pipe)
1065 {
1066         int pp_reg, lvds_reg;
1067         u32 val;
1068         enum pipe panel_pipe = PIPE_A;
1069         bool locked = true;
1070
1071         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072                 pp_reg = PCH_PP_CONTROL;
1073                 lvds_reg = PCH_LVDS;
1074         } else {
1075                 pp_reg = PP_CONTROL;
1076                 lvds_reg = LVDS;
1077         }
1078
1079         val = I915_READ(pp_reg);
1080         if (!(val & PANEL_POWER_ON) ||
1081             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082                 locked = false;
1083
1084         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085                 panel_pipe = PIPE_B;
1086
1087         WARN(panel_pipe == pipe && locked,
1088              "panel assertion failure, pipe %c regs locked\n",
1089              pipe_name(pipe));
1090 }
1091
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         struct drm_device *dev = dev_priv->dev;
1096         bool cur_state;
1097
1098         if (IS_845G(dev) || IS_I865G(dev))
1099                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1101                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102         else
1103                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1104
1105         WARN(cur_state != state,
1106              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107              pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113                  enum pipe pipe, bool state)
1114 {
1115         int reg;
1116         u32 val;
1117         bool cur_state;
1118         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119                                                                       pipe);
1120
1121         /* if we need the pipe A quirk it must be always on */
1122         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123                 state = true;
1124
1125         if (!intel_display_power_enabled(dev_priv,
1126                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127                 cur_state = false;
1128         } else {
1129                 reg = PIPECONF(cpu_transcoder);
1130                 val = I915_READ(reg);
1131                 cur_state = !!(val & PIPECONF_ENABLE);
1132         }
1133
1134         WARN(cur_state != state,
1135              "pipe %c assertion failure (expected %s, current %s)\n",
1136              pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140                          enum plane plane, bool state)
1141 {
1142         int reg;
1143         u32 val;
1144         bool cur_state;
1145
1146         reg = DSPCNTR(plane);
1147         val = I915_READ(reg);
1148         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149         WARN(cur_state != state,
1150              "plane %c assertion failure (expected %s, current %s)\n",
1151              plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158                                    enum pipe pipe)
1159 {
1160         struct drm_device *dev = dev_priv->dev;
1161         int reg, i;
1162         u32 val;
1163         int cur_pipe;
1164
1165         /* Primary planes are fixed to pipes on gen4+ */
1166         if (INTEL_INFO(dev)->gen >= 4) {
1167                 reg = DSPCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN(val & DISPLAY_PLANE_ENABLE,
1170                      "plane %c assertion failure, should be disabled but not\n",
1171                      plane_name(pipe));
1172                 return;
1173         }
1174
1175         /* Need to check both planes against the pipe */
1176         for_each_pipe(i) {
1177                 reg = DSPCNTR(i);
1178                 val = I915_READ(reg);
1179                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180                         DISPPLANE_SEL_PIPE_SHIFT;
1181                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183                      plane_name(i), pipe_name(pipe));
1184         }
1185 }
1186
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188                                     enum pipe pipe)
1189 {
1190         struct drm_device *dev = dev_priv->dev;
1191         int reg, sprite;
1192         u32 val;
1193
1194         if (IS_VALLEYVIEW(dev)) {
1195                 for_each_sprite(pipe, sprite) {
1196                         reg = SPCNTR(pipe, sprite);
1197                         val = I915_READ(reg);
1198                         WARN(val & SP_ENABLE,
1199                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200                              sprite_name(pipe, sprite), pipe_name(pipe));
1201                 }
1202         } else if (INTEL_INFO(dev)->gen >= 7) {
1203                 reg = SPRCTL(pipe);
1204                 val = I915_READ(reg);
1205                 WARN(val & SPRITE_ENABLE,
1206                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207                      plane_name(pipe), pipe_name(pipe));
1208         } else if (INTEL_INFO(dev)->gen >= 5) {
1209                 reg = DVSCNTR(pipe);
1210                 val = I915_READ(reg);
1211                 WARN(val & DVS_ENABLE,
1212                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213                      plane_name(pipe), pipe_name(pipe));
1214         }
1215 }
1216
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219         u32 val;
1220         bool enabled;
1221
1222         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223
1224         val = I915_READ(PCH_DREF_CONTROL);
1225         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226                             DREF_SUPERSPREAD_SOURCE_MASK));
1227         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231                                            enum pipe pipe)
1232 {
1233         int reg;
1234         u32 val;
1235         bool enabled;
1236
1237         reg = PCH_TRANSCONF(pipe);
1238         val = I915_READ(reg);
1239         enabled = !!(val & TRANS_ENABLE);
1240         WARN(enabled,
1241              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246                             enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248         if ((val & DP_PORT_EN) == 0)
1249                 return false;
1250
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255                         return false;
1256         } else {
1257                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258                         return false;
1259         }
1260         return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264                               enum pipe pipe, u32 val)
1265 {
1266         if ((val & SDVO_ENABLE) == 0)
1267                 return false;
1268
1269         if (HAS_PCH_CPT(dev_priv->dev)) {
1270                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271                         return false;
1272         } else {
1273                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274                         return false;
1275         }
1276         return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280                               enum pipe pipe, u32 val)
1281 {
1282         if ((val & LVDS_PORT_EN) == 0)
1283                 return false;
1284
1285         if (HAS_PCH_CPT(dev_priv->dev)) {
1286                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287                         return false;
1288         } else {
1289                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290                         return false;
1291         }
1292         return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296                               enum pipe pipe, u32 val)
1297 {
1298         if ((val & ADPA_DAC_ENABLE) == 0)
1299                 return false;
1300         if (HAS_PCH_CPT(dev_priv->dev)) {
1301                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302                         return false;
1303         } else {
1304                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305                         return false;
1306         }
1307         return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311                                    enum pipe pipe, int reg, u32 port_sel)
1312 {
1313         u32 val = I915_READ(reg);
1314         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316              reg, pipe_name(pipe));
1317
1318         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319              && (val & DP_PIPEB_SELECT),
1320              "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324                                      enum pipe pipe, int reg)
1325 {
1326         u32 val = I915_READ(reg);
1327         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329              reg, pipe_name(pipe));
1330
1331         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332              && (val & SDVO_PIPE_B_SELECT),
1333              "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337                                       enum pipe pipe)
1338 {
1339         int reg;
1340         u32 val;
1341
1342         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346         reg = PCH_ADPA;
1347         val = I915_READ(reg);
1348         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349              "PCH VGA enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         reg = PCH_LVDS;
1353         val = I915_READ(reg);
1354         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356              pipe_name(pipe));
1357
1358         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (!IS_VALLEYVIEW(dev))
1368                 return;
1369
1370         DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1371 }
1372
1373 static void intel_reset_dpio(struct drm_device *dev)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376
1377         if (!IS_VALLEYVIEW(dev))
1378                 return;
1379
1380         /*
1381          * Enable the CRI clock source so we can get at the display and the
1382          * reference clock for VGA hotplug / manual detection.
1383          */
1384         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1385                    DPLL_REFA_CLK_ENABLE_VLV |
1386                    DPLL_INTEGRATED_CRI_CLK_VLV);
1387
1388         /*
1389          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1390          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1391          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1392          *   b. The other bits such as sfr settings / modesel may all be set
1393          *      to 0.
1394          *
1395          * This should only be done on init and resume from S3 with both
1396          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1397          */
1398         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1399 }
1400
1401 static void vlv_enable_pll(struct intel_crtc *crtc)
1402 {
1403         struct drm_device *dev = crtc->base.dev;
1404         struct drm_i915_private *dev_priv = dev->dev_private;
1405         int reg = DPLL(crtc->pipe);
1406         u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408         assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410         /* No really, not for ILK+ */
1411         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1412
1413         /* PLL is protected by panel, make sure we can write it */
1414         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1415                 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417         I915_WRITE(reg, dpll);
1418         POSTING_READ(reg);
1419         udelay(150);
1420
1421         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1422                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1423
1424         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1425         POSTING_READ(DPLL_MD(crtc->pipe));
1426
1427         /* We do this three times for luck */
1428         I915_WRITE(reg, dpll);
1429         POSTING_READ(reg);
1430         udelay(150); /* wait for warmup */
1431         I915_WRITE(reg, dpll);
1432         POSTING_READ(reg);
1433         udelay(150); /* wait for warmup */
1434         I915_WRITE(reg, dpll);
1435         POSTING_READ(reg);
1436         udelay(150); /* wait for warmup */
1437 }
1438
1439 static void i9xx_enable_pll(struct intel_crtc *crtc)
1440 {
1441         struct drm_device *dev = crtc->base.dev;
1442         struct drm_i915_private *dev_priv = dev->dev_private;
1443         int reg = DPLL(crtc->pipe);
1444         u32 dpll = crtc->config.dpll_hw_state.dpll;
1445
1446         assert_pipe_disabled(dev_priv, crtc->pipe);
1447
1448         /* No really, not for ILK+ */
1449         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1450
1451         /* PLL is protected by panel, make sure we can write it */
1452         if (IS_MOBILE(dev) && !IS_I830(dev))
1453                 assert_panel_unlocked(dev_priv, crtc->pipe);
1454
1455         I915_WRITE(reg, dpll);
1456
1457         /* Wait for the clocks to stabilize. */
1458         POSTING_READ(reg);
1459         udelay(150);
1460
1461         if (INTEL_INFO(dev)->gen >= 4) {
1462                 I915_WRITE(DPLL_MD(crtc->pipe),
1463                            crtc->config.dpll_hw_state.dpll_md);
1464         } else {
1465                 /* The pixel multiplier can only be updated once the
1466                  * DPLL is enabled and the clocks are stable.
1467                  *
1468                  * So write it again.
1469                  */
1470                 I915_WRITE(reg, dpll);
1471         }
1472
1473         /* We do this three times for luck */
1474         I915_WRITE(reg, dpll);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477         I915_WRITE(reg, dpll);
1478         POSTING_READ(reg);
1479         udelay(150); /* wait for warmup */
1480         I915_WRITE(reg, dpll);
1481         POSTING_READ(reg);
1482         udelay(150); /* wait for warmup */
1483 }
1484
1485 /**
1486  * i9xx_disable_pll - disable a PLL
1487  * @dev_priv: i915 private structure
1488  * @pipe: pipe PLL to disable
1489  *
1490  * Disable the PLL for @pipe, making sure the pipe is off first.
1491  *
1492  * Note!  This is for pre-ILK only.
1493  */
1494 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1495 {
1496         /* Don't disable pipe A or pipe A PLLs if needed */
1497         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1498                 return;
1499
1500         /* Make sure the pipe isn't still relying on us */
1501         assert_pipe_disabled(dev_priv, pipe);
1502
1503         I915_WRITE(DPLL(pipe), 0);
1504         POSTING_READ(DPLL(pipe));
1505 }
1506
1507 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1508 {
1509         u32 val = 0;
1510
1511         /* Make sure the pipe isn't still relying on us */
1512         assert_pipe_disabled(dev_priv, pipe);
1513
1514         /*
1515          * Leave integrated clock source and reference clock enabled for pipe B.
1516          * The latter is needed for VGA hotplug / manual detection.
1517          */
1518         if (pipe == PIPE_B)
1519                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1520         I915_WRITE(DPLL(pipe), val);
1521         POSTING_READ(DPLL(pipe));
1522 }
1523
1524 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1525                 struct intel_digital_port *dport)
1526 {
1527         u32 port_mask;
1528
1529         switch (dport->port) {
1530         case PORT_B:
1531                 port_mask = DPLL_PORTB_READY_MASK;
1532                 break;
1533         case PORT_C:
1534                 port_mask = DPLL_PORTC_READY_MASK;
1535                 break;
1536         default:
1537                 BUG();
1538         }
1539
1540         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1541                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1542                      port_name(dport->port), I915_READ(DPLL(0)));
1543 }
1544
1545 /**
1546  * ironlake_enable_shared_dpll - enable PCH PLL
1547  * @dev_priv: i915 private structure
1548  * @pipe: pipe PLL to enable
1549  *
1550  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1551  * drives the transcoder clock.
1552  */
1553 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1554 {
1555         struct drm_device *dev = crtc->base.dev;
1556         struct drm_i915_private *dev_priv = dev->dev_private;
1557         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1558
1559         /* PCH PLLs only available on ILK, SNB and IVB */
1560         BUG_ON(INTEL_INFO(dev)->gen < 5);
1561         if (WARN_ON(pll == NULL))
1562                 return;
1563
1564         if (WARN_ON(pll->refcount == 0))
1565                 return;
1566
1567         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1568                       pll->name, pll->active, pll->on,
1569                       crtc->base.base.id);
1570
1571         if (pll->active++) {
1572                 WARN_ON(!pll->on);
1573                 assert_shared_dpll_enabled(dev_priv, pll);
1574                 return;
1575         }
1576         WARN_ON(pll->on);
1577
1578         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1579         pll->enable(dev_priv, pll);
1580         pll->on = true;
1581 }
1582
1583 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1584 {
1585         struct drm_device *dev = crtc->base.dev;
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1588
1589         /* PCH only available on ILK+ */
1590         BUG_ON(INTEL_INFO(dev)->gen < 5);
1591         if (WARN_ON(pll == NULL))
1592                return;
1593
1594         if (WARN_ON(pll->refcount == 0))
1595                 return;
1596
1597         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1598                       pll->name, pll->active, pll->on,
1599                       crtc->base.base.id);
1600
1601         if (WARN_ON(pll->active == 0)) {
1602                 assert_shared_dpll_disabled(dev_priv, pll);
1603                 return;
1604         }
1605
1606         assert_shared_dpll_enabled(dev_priv, pll);
1607         WARN_ON(!pll->on);
1608         if (--pll->active)
1609                 return;
1610
1611         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1612         pll->disable(dev_priv, pll);
1613         pll->on = false;
1614 }
1615
1616 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1617                                            enum pipe pipe)
1618 {
1619         struct drm_device *dev = dev_priv->dev;
1620         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1622         uint32_t reg, val, pipeconf_val;
1623
1624         /* PCH only available on ILK+ */
1625         BUG_ON(INTEL_INFO(dev)->gen < 5);
1626
1627         /* Make sure PCH DPLL is enabled */
1628         assert_shared_dpll_enabled(dev_priv,
1629                                    intel_crtc_to_shared_dpll(intel_crtc));
1630
1631         /* FDI must be feeding us bits for PCH ports */
1632         assert_fdi_tx_enabled(dev_priv, pipe);
1633         assert_fdi_rx_enabled(dev_priv, pipe);
1634
1635         if (HAS_PCH_CPT(dev)) {
1636                 /* Workaround: Set the timing override bit before enabling the
1637                  * pch transcoder. */
1638                 reg = TRANS_CHICKEN2(pipe);
1639                 val = I915_READ(reg);
1640                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641                 I915_WRITE(reg, val);
1642         }
1643
1644         reg = PCH_TRANSCONF(pipe);
1645         val = I915_READ(reg);
1646         pipeconf_val = I915_READ(PIPECONF(pipe));
1647
1648         if (HAS_PCH_IBX(dev_priv->dev)) {
1649                 /*
1650                  * make the BPC in transcoder be consistent with
1651                  * that in pipeconf reg.
1652                  */
1653                 val &= ~PIPECONF_BPC_MASK;
1654                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1655         }
1656
1657         val &= ~TRANS_INTERLACE_MASK;
1658         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1659                 if (HAS_PCH_IBX(dev_priv->dev) &&
1660                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1661                         val |= TRANS_LEGACY_INTERLACED_ILK;
1662                 else
1663                         val |= TRANS_INTERLACED;
1664         else
1665                 val |= TRANS_PROGRESSIVE;
1666
1667         I915_WRITE(reg, val | TRANS_ENABLE);
1668         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1669                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1670 }
1671
1672 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1673                                       enum transcoder cpu_transcoder)
1674 {
1675         u32 val, pipeconf_val;
1676
1677         /* PCH only available on ILK+ */
1678         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1679
1680         /* FDI must be feeding us bits for PCH ports */
1681         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1682         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1683
1684         /* Workaround: set timing override bit. */
1685         val = I915_READ(_TRANSA_CHICKEN2);
1686         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687         I915_WRITE(_TRANSA_CHICKEN2, val);
1688
1689         val = TRANS_ENABLE;
1690         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1691
1692         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1693             PIPECONF_INTERLACED_ILK)
1694                 val |= TRANS_INTERLACED;
1695         else
1696                 val |= TRANS_PROGRESSIVE;
1697
1698         I915_WRITE(LPT_TRANSCONF, val);
1699         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1700                 DRM_ERROR("Failed to enable PCH transcoder\n");
1701 }
1702
1703 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1704                                             enum pipe pipe)
1705 {
1706         struct drm_device *dev = dev_priv->dev;
1707         uint32_t reg, val;
1708
1709         /* FDI relies on the transcoder */
1710         assert_fdi_tx_disabled(dev_priv, pipe);
1711         assert_fdi_rx_disabled(dev_priv, pipe);
1712
1713         /* Ports must be off as well */
1714         assert_pch_ports_disabled(dev_priv, pipe);
1715
1716         reg = PCH_TRANSCONF(pipe);
1717         val = I915_READ(reg);
1718         val &= ~TRANS_ENABLE;
1719         I915_WRITE(reg, val);
1720         /* wait for PCH transcoder off, transcoder state */
1721         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1722                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1723
1724         if (!HAS_PCH_IBX(dev)) {
1725                 /* Workaround: Clear the timing override chicken bit again. */
1726                 reg = TRANS_CHICKEN2(pipe);
1727                 val = I915_READ(reg);
1728                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729                 I915_WRITE(reg, val);
1730         }
1731 }
1732
1733 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1734 {
1735         u32 val;
1736
1737         val = I915_READ(LPT_TRANSCONF);
1738         val &= ~TRANS_ENABLE;
1739         I915_WRITE(LPT_TRANSCONF, val);
1740         /* wait for PCH transcoder off, transcoder state */
1741         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1742                 DRM_ERROR("Failed to disable PCH transcoder\n");
1743
1744         /* Workaround: clear timing override bit. */
1745         val = I915_READ(_TRANSA_CHICKEN2);
1746         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1747         I915_WRITE(_TRANSA_CHICKEN2, val);
1748 }
1749
1750 /**
1751  * intel_enable_pipe - enable a pipe, asserting requirements
1752  * @crtc: crtc responsible for the pipe
1753  *
1754  * Enable @crtc's pipe, making sure that various hardware specific requirements
1755  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1756  */
1757 static void intel_enable_pipe(struct intel_crtc *crtc)
1758 {
1759         struct drm_device *dev = crtc->base.dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         enum pipe pipe = crtc->pipe;
1762         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763                                                                       pipe);
1764         enum pipe pch_transcoder;
1765         int reg;
1766         u32 val;
1767
1768         assert_planes_disabled(dev_priv, pipe);
1769         assert_cursor_disabled(dev_priv, pipe);
1770         assert_sprites_disabled(dev_priv, pipe);
1771
1772         if (HAS_PCH_LPT(dev_priv->dev))
1773                 pch_transcoder = TRANSCODER_A;
1774         else
1775                 pch_transcoder = pipe;
1776
1777         /*
1778          * A pipe without a PLL won't actually be able to drive bits from
1779          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1780          * need the check.
1781          */
1782         if (!HAS_PCH_SPLIT(dev_priv->dev))
1783                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784                         assert_dsi_pll_enabled(dev_priv);
1785                 else
1786                         assert_pll_enabled(dev_priv, pipe);
1787         else {
1788                 if (crtc->config.has_pch_encoder) {
1789                         /* if driving the PCH, we need FDI enabled */
1790                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791                         assert_fdi_tx_pll_enabled(dev_priv,
1792                                                   (enum pipe) cpu_transcoder);
1793                 }
1794                 /* FIXME: assert CPU port conditions for SNB+ */
1795         }
1796
1797         reg = PIPECONF(cpu_transcoder);
1798         val = I915_READ(reg);
1799         if (val & PIPECONF_ENABLE) {
1800                 WARN_ON(!(pipe == PIPE_A &&
1801                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1802                 return;
1803         }
1804
1805         I915_WRITE(reg, val | PIPECONF_ENABLE);
1806         POSTING_READ(reg);
1807
1808         /*
1809          * There's no guarantee the pipe will really start running now. It
1810          * depends on the Gen, the output type and the relative order between
1811          * pipe and plane enabling. Avoid waiting on HSW+ since it's not
1812          * necessary.
1813          * TODO: audit the previous gens.
1814          */
1815         if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
1816                 intel_wait_for_vblank(dev_priv->dev, pipe);
1817 }
1818
1819 /**
1820  * intel_disable_pipe - disable a pipe, asserting requirements
1821  * @dev_priv: i915 private structure
1822  * @pipe: pipe to disable
1823  *
1824  * Disable @pipe, making sure that various hardware specific requirements
1825  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1826  *
1827  * @pipe should be %PIPE_A or %PIPE_B.
1828  *
1829  * Will wait until the pipe has shut down before returning.
1830  */
1831 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1832                                enum pipe pipe)
1833 {
1834         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1835                                                                       pipe);
1836         int reg;
1837         u32 val;
1838
1839         /*
1840          * Make sure planes won't keep trying to pump pixels to us,
1841          * or we might hang the display.
1842          */
1843         assert_planes_disabled(dev_priv, pipe);
1844         assert_cursor_disabled(dev_priv, pipe);
1845         assert_sprites_disabled(dev_priv, pipe);
1846
1847         /* Don't disable pipe A or pipe A PLLs if needed */
1848         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1849                 return;
1850
1851         reg = PIPECONF(cpu_transcoder);
1852         val = I915_READ(reg);
1853         if ((val & PIPECONF_ENABLE) == 0)
1854                 return;
1855
1856         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1857         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1858 }
1859
1860 /*
1861  * Plane regs are double buffered, going from enabled->disabled needs a
1862  * trigger in order to latch.  The display address reg provides this.
1863  */
1864 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1865                                enum plane plane)
1866 {
1867         struct drm_device *dev = dev_priv->dev;
1868         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1869
1870         I915_WRITE(reg, I915_READ(reg));
1871         POSTING_READ(reg);
1872 }
1873
1874 /**
1875  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
1876  * @dev_priv: i915 private structure
1877  * @plane: plane to enable
1878  * @pipe: pipe being fed
1879  *
1880  * Enable @plane on @pipe, making sure that @pipe is running first.
1881  */
1882 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1883                                           enum plane plane, enum pipe pipe)
1884 {
1885         struct intel_crtc *intel_crtc =
1886                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1887         int reg;
1888         u32 val;
1889
1890         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1891         assert_pipe_enabled(dev_priv, pipe);
1892
1893         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1894
1895         intel_crtc->primary_enabled = true;
1896
1897         reg = DSPCNTR(plane);
1898         val = I915_READ(reg);
1899         if (val & DISPLAY_PLANE_ENABLE)
1900                 return;
1901
1902         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1903         intel_flush_primary_plane(dev_priv, plane);
1904         intel_wait_for_vblank(dev_priv->dev, pipe);
1905 }
1906
1907 /**
1908  * intel_disable_primary_hw_plane - disable the primary hardware plane
1909  * @dev_priv: i915 private structure
1910  * @plane: plane to disable
1911  * @pipe: pipe consuming the data
1912  *
1913  * Disable @plane; should be an independent operation.
1914  */
1915 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1916                                            enum plane plane, enum pipe pipe)
1917 {
1918         struct intel_crtc *intel_crtc =
1919                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1920         int reg;
1921         u32 val;
1922
1923         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1924
1925         intel_crtc->primary_enabled = false;
1926
1927         reg = DSPCNTR(plane);
1928         val = I915_READ(reg);
1929         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1930                 return;
1931
1932         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1933         intel_flush_primary_plane(dev_priv, plane);
1934         intel_wait_for_vblank(dev_priv->dev, pipe);
1935 }
1936
1937 static bool need_vtd_wa(struct drm_device *dev)
1938 {
1939 #ifdef CONFIG_INTEL_IOMMU
1940         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1941                 return true;
1942 #endif
1943         return false;
1944 }
1945
1946 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1947 {
1948         int tile_height;
1949
1950         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1951         return ALIGN(height, tile_height);
1952 }
1953
1954 int
1955 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1956                            struct drm_i915_gem_object *obj,
1957                            struct intel_ring_buffer *pipelined)
1958 {
1959         struct drm_i915_private *dev_priv = dev->dev_private;
1960         u32 alignment;
1961         int ret;
1962
1963         switch (obj->tiling_mode) {
1964         case I915_TILING_NONE:
1965                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1966                         alignment = 128 * 1024;
1967                 else if (INTEL_INFO(dev)->gen >= 4)
1968                         alignment = 4 * 1024;
1969                 else
1970                         alignment = 64 * 1024;
1971                 break;
1972         case I915_TILING_X:
1973                 /* pin() will align the object as required by fence */
1974                 alignment = 0;
1975                 break;
1976         case I915_TILING_Y:
1977                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1978                 return -EINVAL;
1979         default:
1980                 BUG();
1981         }
1982
1983         /* Note that the w/a also requires 64 PTE of padding following the
1984          * bo. We currently fill all unused PTE with the shadow page and so
1985          * we should always have valid PTE following the scanout preventing
1986          * the VT-d warning.
1987          */
1988         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1989                 alignment = 256 * 1024;
1990
1991         dev_priv->mm.interruptible = false;
1992         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1993         if (ret)
1994                 goto err_interruptible;
1995
1996         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1997          * fence, whereas 965+ only requires a fence if using
1998          * framebuffer compression.  For simplicity, we always install
1999          * a fence as the cost is not that onerous.
2000          */
2001         ret = i915_gem_object_get_fence(obj);
2002         if (ret)
2003                 goto err_unpin;
2004
2005         i915_gem_object_pin_fence(obj);
2006
2007         dev_priv->mm.interruptible = true;
2008         return 0;
2009
2010 err_unpin:
2011         i915_gem_object_unpin_from_display_plane(obj);
2012 err_interruptible:
2013         dev_priv->mm.interruptible = true;
2014         return ret;
2015 }
2016
2017 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2018 {
2019         i915_gem_object_unpin_fence(obj);
2020         i915_gem_object_unpin_from_display_plane(obj);
2021 }
2022
2023 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2024  * is assumed to be a power-of-two. */
2025 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2026                                              unsigned int tiling_mode,
2027                                              unsigned int cpp,
2028                                              unsigned int pitch)
2029 {
2030         if (tiling_mode != I915_TILING_NONE) {
2031                 unsigned int tile_rows, tiles;
2032
2033                 tile_rows = *y / 8;
2034                 *y %= 8;
2035
2036                 tiles = *x / (512/cpp);
2037                 *x %= 512/cpp;
2038
2039                 return tile_rows * pitch * 8 + tiles * 4096;
2040         } else {
2041                 unsigned int offset;
2042
2043                 offset = *y * pitch + *x * cpp;
2044                 *y = 0;
2045                 *x = (offset & 4095) / cpp;
2046                 return offset & -4096;
2047         }
2048 }
2049
2050 int intel_format_to_fourcc(int format)
2051 {
2052         switch (format) {
2053         case DISPPLANE_8BPP:
2054                 return DRM_FORMAT_C8;
2055         case DISPPLANE_BGRX555:
2056                 return DRM_FORMAT_XRGB1555;
2057         case DISPPLANE_BGRX565:
2058                 return DRM_FORMAT_RGB565;
2059         default:
2060         case DISPPLANE_BGRX888:
2061                 return DRM_FORMAT_XRGB8888;
2062         case DISPPLANE_RGBX888:
2063                 return DRM_FORMAT_XBGR8888;
2064         case DISPPLANE_BGRX101010:
2065                 return DRM_FORMAT_XRGB2101010;
2066         case DISPPLANE_RGBX101010:
2067                 return DRM_FORMAT_XBGR2101010;
2068         }
2069 }
2070
2071 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2072                                   struct intel_plane_config *plane_config)
2073 {
2074         struct drm_device *dev = crtc->base.dev;
2075         struct drm_i915_gem_object *obj = NULL;
2076         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2077         u32 base = plane_config->base;
2078
2079         if (plane_config->size == 0)
2080                 return false;
2081
2082         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2083                                                              plane_config->size);
2084         if (!obj)
2085                 return false;
2086
2087         if (plane_config->tiled) {
2088                 obj->tiling_mode = I915_TILING_X;
2089                 obj->stride = crtc->base.primary->fb->pitches[0];
2090         }
2091
2092         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2093         mode_cmd.width = crtc->base.primary->fb->width;
2094         mode_cmd.height = crtc->base.primary->fb->height;
2095         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2096
2097         mutex_lock(&dev->struct_mutex);
2098
2099         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2100                                    &mode_cmd, obj)) {
2101                 DRM_DEBUG_KMS("intel fb init failed\n");
2102                 goto out_unref_obj;
2103         }
2104
2105         mutex_unlock(&dev->struct_mutex);
2106
2107         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2108         return true;
2109
2110 out_unref_obj:
2111         drm_gem_object_unreference(&obj->base);
2112         mutex_unlock(&dev->struct_mutex);
2113         return false;
2114 }
2115
2116 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2117                                  struct intel_plane_config *plane_config)
2118 {
2119         struct drm_device *dev = intel_crtc->base.dev;
2120         struct drm_crtc *c;
2121         struct intel_crtc *i;
2122         struct intel_framebuffer *fb;
2123
2124         if (!intel_crtc->base.primary->fb)
2125                 return;
2126
2127         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2128                 return;
2129
2130         kfree(intel_crtc->base.primary->fb);
2131         intel_crtc->base.primary->fb = NULL;
2132
2133         /*
2134          * Failed to alloc the obj, check to see if we should share
2135          * an fb with another CRTC instead
2136          */
2137         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2138                 i = to_intel_crtc(c);
2139
2140                 if (c == &intel_crtc->base)
2141                         continue;
2142
2143                 if (!i->active || !c->primary->fb)
2144                         continue;
2145
2146                 fb = to_intel_framebuffer(c->primary->fb);
2147                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2148                         drm_framebuffer_reference(c->primary->fb);
2149                         intel_crtc->base.primary->fb = c->primary->fb;
2150                         break;
2151                 }
2152         }
2153 }
2154
2155 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2156                                      struct drm_framebuffer *fb,
2157                                      int x, int y)
2158 {
2159         struct drm_device *dev = crtc->dev;
2160         struct drm_i915_private *dev_priv = dev->dev_private;
2161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2162         struct intel_framebuffer *intel_fb;
2163         struct drm_i915_gem_object *obj;
2164         int plane = intel_crtc->plane;
2165         unsigned long linear_offset;
2166         u32 dspcntr;
2167         u32 reg;
2168
2169         intel_fb = to_intel_framebuffer(fb);
2170         obj = intel_fb->obj;
2171
2172         reg = DSPCNTR(plane);
2173         dspcntr = I915_READ(reg);
2174         /* Mask out pixel format bits in case we change it */
2175         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2176         switch (fb->pixel_format) {
2177         case DRM_FORMAT_C8:
2178                 dspcntr |= DISPPLANE_8BPP;
2179                 break;
2180         case DRM_FORMAT_XRGB1555:
2181         case DRM_FORMAT_ARGB1555:
2182                 dspcntr |= DISPPLANE_BGRX555;
2183                 break;
2184         case DRM_FORMAT_RGB565:
2185                 dspcntr |= DISPPLANE_BGRX565;
2186                 break;
2187         case DRM_FORMAT_XRGB8888:
2188         case DRM_FORMAT_ARGB8888:
2189                 dspcntr |= DISPPLANE_BGRX888;
2190                 break;
2191         case DRM_FORMAT_XBGR8888:
2192         case DRM_FORMAT_ABGR8888:
2193                 dspcntr |= DISPPLANE_RGBX888;
2194                 break;
2195         case DRM_FORMAT_XRGB2101010:
2196         case DRM_FORMAT_ARGB2101010:
2197                 dspcntr |= DISPPLANE_BGRX101010;
2198                 break;
2199         case DRM_FORMAT_XBGR2101010:
2200         case DRM_FORMAT_ABGR2101010:
2201                 dspcntr |= DISPPLANE_RGBX101010;
2202                 break;
2203         default:
2204                 BUG();
2205         }
2206
2207         if (INTEL_INFO(dev)->gen >= 4) {
2208                 if (obj->tiling_mode != I915_TILING_NONE)
2209                         dspcntr |= DISPPLANE_TILED;
2210                 else
2211                         dspcntr &= ~DISPPLANE_TILED;
2212         }
2213
2214         if (IS_G4X(dev))
2215                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2216
2217         I915_WRITE(reg, dspcntr);
2218
2219         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2220
2221         if (INTEL_INFO(dev)->gen >= 4) {
2222                 intel_crtc->dspaddr_offset =
2223                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2224                                                        fb->bits_per_pixel / 8,
2225                                                        fb->pitches[0]);
2226                 linear_offset -= intel_crtc->dspaddr_offset;
2227         } else {
2228                 intel_crtc->dspaddr_offset = linear_offset;
2229         }
2230
2231         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2232                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2233                       fb->pitches[0]);
2234         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2235         if (INTEL_INFO(dev)->gen >= 4) {
2236                 I915_WRITE(DSPSURF(plane),
2237                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2238                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2239                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2240         } else
2241                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2242         POSTING_READ(reg);
2243
2244         return 0;
2245 }
2246
2247 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2248                                          struct drm_framebuffer *fb,
2249                                          int x, int y)
2250 {
2251         struct drm_device *dev = crtc->dev;
2252         struct drm_i915_private *dev_priv = dev->dev_private;
2253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2254         struct intel_framebuffer *intel_fb;
2255         struct drm_i915_gem_object *obj;
2256         int plane = intel_crtc->plane;
2257         unsigned long linear_offset;
2258         u32 dspcntr;
2259         u32 reg;
2260
2261         intel_fb = to_intel_framebuffer(fb);
2262         obj = intel_fb->obj;
2263
2264         reg = DSPCNTR(plane);
2265         dspcntr = I915_READ(reg);
2266         /* Mask out pixel format bits in case we change it */
2267         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2268         switch (fb->pixel_format) {
2269         case DRM_FORMAT_C8:
2270                 dspcntr |= DISPPLANE_8BPP;
2271                 break;
2272         case DRM_FORMAT_RGB565:
2273                 dspcntr |= DISPPLANE_BGRX565;
2274                 break;
2275         case DRM_FORMAT_XRGB8888:
2276         case DRM_FORMAT_ARGB8888:
2277                 dspcntr |= DISPPLANE_BGRX888;
2278                 break;
2279         case DRM_FORMAT_XBGR8888:
2280         case DRM_FORMAT_ABGR8888:
2281                 dspcntr |= DISPPLANE_RGBX888;
2282                 break;
2283         case DRM_FORMAT_XRGB2101010:
2284         case DRM_FORMAT_ARGB2101010:
2285                 dspcntr |= DISPPLANE_BGRX101010;
2286                 break;
2287         case DRM_FORMAT_XBGR2101010:
2288         case DRM_FORMAT_ABGR2101010:
2289                 dspcntr |= DISPPLANE_RGBX101010;
2290                 break;
2291         default:
2292                 BUG();
2293         }
2294
2295         if (obj->tiling_mode != I915_TILING_NONE)
2296                 dspcntr |= DISPPLANE_TILED;
2297         else
2298                 dspcntr &= ~DISPPLANE_TILED;
2299
2300         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2301                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2302         else
2303                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2304
2305         I915_WRITE(reg, dspcntr);
2306
2307         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2308         intel_crtc->dspaddr_offset =
2309                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2310                                                fb->bits_per_pixel / 8,
2311                                                fb->pitches[0]);
2312         linear_offset -= intel_crtc->dspaddr_offset;
2313
2314         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2315                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2316                       fb->pitches[0]);
2317         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2318         I915_WRITE(DSPSURF(plane),
2319                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2320         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2321                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2322         } else {
2323                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2324                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2325         }
2326         POSTING_READ(reg);
2327
2328         return 0;
2329 }
2330
2331 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2332 static int
2333 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2334                            int x, int y, enum mode_set_atomic state)
2335 {
2336         struct drm_device *dev = crtc->dev;
2337         struct drm_i915_private *dev_priv = dev->dev_private;
2338
2339         if (dev_priv->display.disable_fbc)
2340                 dev_priv->display.disable_fbc(dev);
2341         intel_increase_pllclock(crtc);
2342
2343         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2344 }
2345
2346 void intel_display_handle_reset(struct drm_device *dev)
2347 {
2348         struct drm_i915_private *dev_priv = dev->dev_private;
2349         struct drm_crtc *crtc;
2350
2351         /*
2352          * Flips in the rings have been nuked by the reset,
2353          * so complete all pending flips so that user space
2354          * will get its events and not get stuck.
2355          *
2356          * Also update the base address of all primary
2357          * planes to the the last fb to make sure we're
2358          * showing the correct fb after a reset.
2359          *
2360          * Need to make two loops over the crtcs so that we
2361          * don't try to grab a crtc mutex before the
2362          * pending_flip_queue really got woken up.
2363          */
2364
2365         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2366                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2367                 enum plane plane = intel_crtc->plane;
2368
2369                 intel_prepare_page_flip(dev, plane);
2370                 intel_finish_page_flip_plane(dev, plane);
2371         }
2372
2373         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2374                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2375
2376                 mutex_lock(&crtc->mutex);
2377                 /*
2378                  * FIXME: Once we have proper support for primary planes (and
2379                  * disabling them without disabling the entire crtc) allow again
2380                  * a NULL crtc->primary->fb.
2381                  */
2382                 if (intel_crtc->active && crtc->primary->fb)
2383                         dev_priv->display.update_primary_plane(crtc,
2384                                                                crtc->primary->fb,
2385                                                                crtc->x,
2386                                                                crtc->y);
2387                 mutex_unlock(&crtc->mutex);
2388         }
2389 }
2390
2391 static int
2392 intel_finish_fb(struct drm_framebuffer *old_fb)
2393 {
2394         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2395         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2396         bool was_interruptible = dev_priv->mm.interruptible;
2397         int ret;
2398
2399         /* Big Hammer, we also need to ensure that any pending
2400          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2401          * current scanout is retired before unpinning the old
2402          * framebuffer.
2403          *
2404          * This should only fail upon a hung GPU, in which case we
2405          * can safely continue.
2406          */
2407         dev_priv->mm.interruptible = false;
2408         ret = i915_gem_object_finish_gpu(obj);
2409         dev_priv->mm.interruptible = was_interruptible;
2410
2411         return ret;
2412 }
2413
2414 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2415 {
2416         struct drm_device *dev = crtc->dev;
2417         struct drm_i915_private *dev_priv = dev->dev_private;
2418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2419         unsigned long flags;
2420         bool pending;
2421
2422         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2423             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2424                 return false;
2425
2426         spin_lock_irqsave(&dev->event_lock, flags);
2427         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2428         spin_unlock_irqrestore(&dev->event_lock, flags);
2429
2430         return pending;
2431 }
2432
2433 static int
2434 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2435                     struct drm_framebuffer *fb)
2436 {
2437         struct drm_device *dev = crtc->dev;
2438         struct drm_i915_private *dev_priv = dev->dev_private;
2439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2440         struct drm_framebuffer *old_fb;
2441         int ret;
2442
2443         if (intel_crtc_has_pending_flip(crtc)) {
2444                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2445                 return -EBUSY;
2446         }
2447
2448         /* no fb bound */
2449         if (!fb) {
2450                 DRM_ERROR("No FB bound\n");
2451                 return 0;
2452         }
2453
2454         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2455                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2456                           plane_name(intel_crtc->plane),
2457                           INTEL_INFO(dev)->num_pipes);
2458                 return -EINVAL;
2459         }
2460
2461         mutex_lock(&dev->struct_mutex);
2462         ret = intel_pin_and_fence_fb_obj(dev,
2463                                          to_intel_framebuffer(fb)->obj,
2464                                          NULL);
2465         mutex_unlock(&dev->struct_mutex);
2466         if (ret != 0) {
2467                 DRM_ERROR("pin & fence failed\n");
2468                 return ret;
2469         }
2470
2471         /*
2472          * Update pipe size and adjust fitter if needed: the reason for this is
2473          * that in compute_mode_changes we check the native mode (not the pfit
2474          * mode) to see if we can flip rather than do a full mode set. In the
2475          * fastboot case, we'll flip, but if we don't update the pipesrc and
2476          * pfit state, we'll end up with a big fb scanned out into the wrong
2477          * sized surface.
2478          *
2479          * To fix this properly, we need to hoist the checks up into
2480          * compute_mode_changes (or above), check the actual pfit state and
2481          * whether the platform allows pfit disable with pipe active, and only
2482          * then update the pipesrc and pfit state, even on the flip path.
2483          */
2484         if (i915.fastboot) {
2485                 const struct drm_display_mode *adjusted_mode =
2486                         &intel_crtc->config.adjusted_mode;
2487
2488                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2489                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2490                            (adjusted_mode->crtc_vdisplay - 1));
2491                 if (!intel_crtc->config.pch_pfit.enabled &&
2492                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2493                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2494                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2495                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2496                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2497                 }
2498                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2499                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2500         }
2501
2502         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2503         if (ret) {
2504                 mutex_lock(&dev->struct_mutex);
2505                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2506                 mutex_unlock(&dev->struct_mutex);
2507                 DRM_ERROR("failed to update base address\n");
2508                 return ret;
2509         }
2510
2511         old_fb = crtc->primary->fb;
2512         crtc->primary->fb = fb;
2513         crtc->x = x;
2514         crtc->y = y;
2515
2516         if (old_fb) {
2517                 if (intel_crtc->active && old_fb != fb)
2518                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2519                 mutex_lock(&dev->struct_mutex);
2520                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2521                 mutex_unlock(&dev->struct_mutex);
2522         }
2523
2524         mutex_lock(&dev->struct_mutex);
2525         intel_update_fbc(dev);
2526         intel_edp_psr_update(dev);
2527         mutex_unlock(&dev->struct_mutex);
2528
2529         return 0;
2530 }
2531
2532 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2533 {
2534         struct drm_device *dev = crtc->dev;
2535         struct drm_i915_private *dev_priv = dev->dev_private;
2536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2537         int pipe = intel_crtc->pipe;
2538         u32 reg, temp;
2539
2540         /* enable normal train */
2541         reg = FDI_TX_CTL(pipe);
2542         temp = I915_READ(reg);
2543         if (IS_IVYBRIDGE(dev)) {
2544                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2545                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2546         } else {
2547                 temp &= ~FDI_LINK_TRAIN_NONE;
2548                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2549         }
2550         I915_WRITE(reg, temp);
2551
2552         reg = FDI_RX_CTL(pipe);
2553         temp = I915_READ(reg);
2554         if (HAS_PCH_CPT(dev)) {
2555                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2556                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2557         } else {
2558                 temp &= ~FDI_LINK_TRAIN_NONE;
2559                 temp |= FDI_LINK_TRAIN_NONE;
2560         }
2561         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2562
2563         /* wait one idle pattern time */
2564         POSTING_READ(reg);
2565         udelay(1000);
2566
2567         /* IVB wants error correction enabled */
2568         if (IS_IVYBRIDGE(dev))
2569                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2570                            FDI_FE_ERRC_ENABLE);
2571 }
2572
2573 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2574 {
2575         return crtc->base.enabled && crtc->active &&
2576                 crtc->config.has_pch_encoder;
2577 }
2578
2579 static void ivb_modeset_global_resources(struct drm_device *dev)
2580 {
2581         struct drm_i915_private *dev_priv = dev->dev_private;
2582         struct intel_crtc *pipe_B_crtc =
2583                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2584         struct intel_crtc *pipe_C_crtc =
2585                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2586         uint32_t temp;
2587
2588         /*
2589          * When everything is off disable fdi C so that we could enable fdi B
2590          * with all lanes. Note that we don't care about enabled pipes without
2591          * an enabled pch encoder.
2592          */
2593         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2594             !pipe_has_enabled_pch(pipe_C_crtc)) {
2595                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2596                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2597
2598                 temp = I915_READ(SOUTH_CHICKEN1);
2599                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2600                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2601                 I915_WRITE(SOUTH_CHICKEN1, temp);
2602         }
2603 }
2604
2605 /* The FDI link training functions for ILK/Ibexpeak. */
2606 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2607 {
2608         struct drm_device *dev = crtc->dev;
2609         struct drm_i915_private *dev_priv = dev->dev_private;
2610         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2611         int pipe = intel_crtc->pipe;
2612         int plane = intel_crtc->plane;
2613         u32 reg, temp, tries;
2614
2615         /* FDI needs bits from pipe & plane first */
2616         assert_pipe_enabled(dev_priv, pipe);
2617         assert_plane_enabled(dev_priv, plane);
2618
2619         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2620            for train result */
2621         reg = FDI_RX_IMR(pipe);
2622         temp = I915_READ(reg);
2623         temp &= ~FDI_RX_SYMBOL_LOCK;
2624         temp &= ~FDI_RX_BIT_LOCK;
2625         I915_WRITE(reg, temp);
2626         I915_READ(reg);
2627         udelay(150);
2628
2629         /* enable CPU FDI TX and PCH FDI RX */
2630         reg = FDI_TX_CTL(pipe);
2631         temp = I915_READ(reg);
2632         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2633         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2634         temp &= ~FDI_LINK_TRAIN_NONE;
2635         temp |= FDI_LINK_TRAIN_PATTERN_1;
2636         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2637
2638         reg = FDI_RX_CTL(pipe);
2639         temp = I915_READ(reg);
2640         temp &= ~FDI_LINK_TRAIN_NONE;
2641         temp |= FDI_LINK_TRAIN_PATTERN_1;
2642         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2643
2644         POSTING_READ(reg);
2645         udelay(150);
2646
2647         /* Ironlake workaround, enable clock pointer after FDI enable*/
2648         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2649         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2650                    FDI_RX_PHASE_SYNC_POINTER_EN);
2651
2652         reg = FDI_RX_IIR(pipe);
2653         for (tries = 0; tries < 5; tries++) {
2654                 temp = I915_READ(reg);
2655                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656
2657                 if ((temp & FDI_RX_BIT_LOCK)) {
2658                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2659                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2660                         break;
2661                 }
2662         }
2663         if (tries == 5)
2664                 DRM_ERROR("FDI train 1 fail!\n");
2665
2666         /* Train 2 */
2667         reg = FDI_TX_CTL(pipe);
2668         temp = I915_READ(reg);
2669         temp &= ~FDI_LINK_TRAIN_NONE;
2670         temp |= FDI_LINK_TRAIN_PATTERN_2;
2671         I915_WRITE(reg, temp);
2672
2673         reg = FDI_RX_CTL(pipe);
2674         temp = I915_READ(reg);
2675         temp &= ~FDI_LINK_TRAIN_NONE;
2676         temp |= FDI_LINK_TRAIN_PATTERN_2;
2677         I915_WRITE(reg, temp);
2678
2679         POSTING_READ(reg);
2680         udelay(150);
2681
2682         reg = FDI_RX_IIR(pipe);
2683         for (tries = 0; tries < 5; tries++) {
2684                 temp = I915_READ(reg);
2685                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2686
2687                 if (temp & FDI_RX_SYMBOL_LOCK) {
2688                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2689                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2690                         break;
2691                 }
2692         }
2693         if (tries == 5)
2694                 DRM_ERROR("FDI train 2 fail!\n");
2695
2696         DRM_DEBUG_KMS("FDI train done\n");
2697
2698 }
2699
2700 static const int snb_b_fdi_train_param[] = {
2701         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2702         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2703         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2704         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2705 };
2706
2707 /* The FDI link training functions for SNB/Cougarpoint. */
2708 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2709 {
2710         struct drm_device *dev = crtc->dev;
2711         struct drm_i915_private *dev_priv = dev->dev_private;
2712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2713         int pipe = intel_crtc->pipe;
2714         u32 reg, temp, i, retry;
2715
2716         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2717            for train result */
2718         reg = FDI_RX_IMR(pipe);
2719         temp = I915_READ(reg);
2720         temp &= ~FDI_RX_SYMBOL_LOCK;
2721         temp &= ~FDI_RX_BIT_LOCK;
2722         I915_WRITE(reg, temp);
2723
2724         POSTING_READ(reg);
2725         udelay(150);
2726
2727         /* enable CPU FDI TX and PCH FDI RX */
2728         reg = FDI_TX_CTL(pipe);
2729         temp = I915_READ(reg);
2730         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2731         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2732         temp &= ~FDI_LINK_TRAIN_NONE;
2733         temp |= FDI_LINK_TRAIN_PATTERN_1;
2734         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2735         /* SNB-B */
2736         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2737         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2738
2739         I915_WRITE(FDI_RX_MISC(pipe),
2740                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2741
2742         reg = FDI_RX_CTL(pipe);
2743         temp = I915_READ(reg);
2744         if (HAS_PCH_CPT(dev)) {
2745                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2746                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2747         } else {
2748                 temp &= ~FDI_LINK_TRAIN_NONE;
2749                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2750         }
2751         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2752
2753         POSTING_READ(reg);
2754         udelay(150);
2755
2756         for (i = 0; i < 4; i++) {
2757                 reg = FDI_TX_CTL(pipe);
2758                 temp = I915_READ(reg);
2759                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2760                 temp |= snb_b_fdi_train_param[i];
2761                 I915_WRITE(reg, temp);
2762
2763                 POSTING_READ(reg);
2764                 udelay(500);
2765
2766                 for (retry = 0; retry < 5; retry++) {
2767                         reg = FDI_RX_IIR(pipe);
2768                         temp = I915_READ(reg);
2769                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2770                         if (temp & FDI_RX_BIT_LOCK) {
2771                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2772                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2773                                 break;
2774                         }
2775                         udelay(50);
2776                 }
2777                 if (retry < 5)
2778                         break;
2779         }
2780         if (i == 4)
2781                 DRM_ERROR("FDI train 1 fail!\n");
2782
2783         /* Train 2 */
2784         reg = FDI_TX_CTL(pipe);
2785         temp = I915_READ(reg);
2786         temp &= ~FDI_LINK_TRAIN_NONE;
2787         temp |= FDI_LINK_TRAIN_PATTERN_2;
2788         if (IS_GEN6(dev)) {
2789                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2790                 /* SNB-B */
2791                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2792         }
2793         I915_WRITE(reg, temp);
2794
2795         reg = FDI_RX_CTL(pipe);
2796         temp = I915_READ(reg);
2797         if (HAS_PCH_CPT(dev)) {
2798                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2799                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2800         } else {
2801                 temp &= ~FDI_LINK_TRAIN_NONE;
2802                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2803         }
2804         I915_WRITE(reg, temp);
2805
2806         POSTING_READ(reg);
2807         udelay(150);
2808
2809         for (i = 0; i < 4; i++) {
2810                 reg = FDI_TX_CTL(pipe);
2811                 temp = I915_READ(reg);
2812                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2813                 temp |= snb_b_fdi_train_param[i];
2814                 I915_WRITE(reg, temp);
2815
2816                 POSTING_READ(reg);
2817                 udelay(500);
2818
2819                 for (retry = 0; retry < 5; retry++) {
2820                         reg = FDI_RX_IIR(pipe);
2821                         temp = I915_READ(reg);
2822                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2823                         if (temp & FDI_RX_SYMBOL_LOCK) {
2824                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2825                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2826                                 break;
2827                         }
2828                         udelay(50);
2829                 }
2830                 if (retry < 5)
2831                         break;
2832         }
2833         if (i == 4)
2834                 DRM_ERROR("FDI train 2 fail!\n");
2835
2836         DRM_DEBUG_KMS("FDI train done.\n");
2837 }
2838
2839 /* Manual link training for Ivy Bridge A0 parts */
2840 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2841 {
2842         struct drm_device *dev = crtc->dev;
2843         struct drm_i915_private *dev_priv = dev->dev_private;
2844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2845         int pipe = intel_crtc->pipe;
2846         u32 reg, temp, i, j;
2847
2848         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2849            for train result */
2850         reg = FDI_RX_IMR(pipe);
2851         temp = I915_READ(reg);
2852         temp &= ~FDI_RX_SYMBOL_LOCK;
2853         temp &= ~FDI_RX_BIT_LOCK;
2854         I915_WRITE(reg, temp);
2855
2856         POSTING_READ(reg);
2857         udelay(150);
2858
2859         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2860                       I915_READ(FDI_RX_IIR(pipe)));
2861
2862         /* Try each vswing and preemphasis setting twice before moving on */
2863         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2864                 /* disable first in case we need to retry */
2865                 reg = FDI_TX_CTL(pipe);
2866                 temp = I915_READ(reg);
2867                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2868                 temp &= ~FDI_TX_ENABLE;
2869                 I915_WRITE(reg, temp);
2870
2871                 reg = FDI_RX_CTL(pipe);
2872                 temp = I915_READ(reg);
2873                 temp &= ~FDI_LINK_TRAIN_AUTO;
2874                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2875                 temp &= ~FDI_RX_ENABLE;
2876                 I915_WRITE(reg, temp);
2877
2878                 /* enable CPU FDI TX and PCH FDI RX */
2879                 reg = FDI_TX_CTL(pipe);
2880                 temp = I915_READ(reg);
2881                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2882                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2883                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2884                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2885                 temp |= snb_b_fdi_train_param[j/2];
2886                 temp |= FDI_COMPOSITE_SYNC;
2887                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2888
2889                 I915_WRITE(FDI_RX_MISC(pipe),
2890                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2891
2892                 reg = FDI_RX_CTL(pipe);
2893                 temp = I915_READ(reg);
2894                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2895                 temp |= FDI_COMPOSITE_SYNC;
2896                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2897
2898                 POSTING_READ(reg);
2899                 udelay(1); /* should be 0.5us */
2900
2901                 for (i = 0; i < 4; i++) {
2902                         reg = FDI_RX_IIR(pipe);
2903                         temp = I915_READ(reg);
2904                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2905
2906                         if (temp & FDI_RX_BIT_LOCK ||
2907                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2908                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2909                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2910                                               i);
2911                                 break;
2912                         }
2913                         udelay(1); /* should be 0.5us */
2914                 }
2915                 if (i == 4) {
2916                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2917                         continue;
2918                 }
2919
2920                 /* Train 2 */
2921                 reg = FDI_TX_CTL(pipe);
2922                 temp = I915_READ(reg);
2923                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2924                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2925                 I915_WRITE(reg, temp);
2926
2927                 reg = FDI_RX_CTL(pipe);
2928                 temp = I915_READ(reg);
2929                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2930                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2931                 I915_WRITE(reg, temp);
2932
2933                 POSTING_READ(reg);
2934                 udelay(2); /* should be 1.5us */
2935
2936                 for (i = 0; i < 4; i++) {
2937                         reg = FDI_RX_IIR(pipe);
2938                         temp = I915_READ(reg);
2939                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2940
2941                         if (temp & FDI_RX_SYMBOL_LOCK ||
2942                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2943                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2944                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2945                                               i);
2946                                 goto train_done;
2947                         }
2948                         udelay(2); /* should be 1.5us */
2949                 }
2950                 if (i == 4)
2951                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2952         }
2953
2954 train_done:
2955         DRM_DEBUG_KMS("FDI train done.\n");
2956 }
2957
2958 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2959 {
2960         struct drm_device *dev = intel_crtc->base.dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962         int pipe = intel_crtc->pipe;
2963         u32 reg, temp;
2964
2965
2966         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2967         reg = FDI_RX_CTL(pipe);
2968         temp = I915_READ(reg);
2969         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2970         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2971         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2972         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2973
2974         POSTING_READ(reg);
2975         udelay(200);
2976
2977         /* Switch from Rawclk to PCDclk */
2978         temp = I915_READ(reg);
2979         I915_WRITE(reg, temp | FDI_PCDCLK);
2980
2981         POSTING_READ(reg);
2982         udelay(200);
2983
2984         /* Enable CPU FDI TX PLL, always on for Ironlake */
2985         reg = FDI_TX_CTL(pipe);
2986         temp = I915_READ(reg);
2987         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2988                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2989
2990                 POSTING_READ(reg);
2991                 udelay(100);
2992         }
2993 }
2994
2995 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2996 {
2997         struct drm_device *dev = intel_crtc->base.dev;
2998         struct drm_i915_private *dev_priv = dev->dev_private;
2999         int pipe = intel_crtc->pipe;
3000         u32 reg, temp;
3001
3002         /* Switch from PCDclk to Rawclk */
3003         reg = FDI_RX_CTL(pipe);
3004         temp = I915_READ(reg);
3005         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3006
3007         /* Disable CPU FDI TX PLL */
3008         reg = FDI_TX_CTL(pipe);
3009         temp = I915_READ(reg);
3010         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3011
3012         POSTING_READ(reg);
3013         udelay(100);
3014
3015         reg = FDI_RX_CTL(pipe);
3016         temp = I915_READ(reg);
3017         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3018
3019         /* Wait for the clocks to turn off. */
3020         POSTING_READ(reg);
3021         udelay(100);
3022 }
3023
3024 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3025 {
3026         struct drm_device *dev = crtc->dev;
3027         struct drm_i915_private *dev_priv = dev->dev_private;
3028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029         int pipe = intel_crtc->pipe;
3030         u32 reg, temp;
3031
3032         /* disable CPU FDI tx and PCH FDI rx */
3033         reg = FDI_TX_CTL(pipe);
3034         temp = I915_READ(reg);
3035         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3036         POSTING_READ(reg);
3037
3038         reg = FDI_RX_CTL(pipe);
3039         temp = I915_READ(reg);
3040         temp &= ~(0x7 << 16);
3041         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3042         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3043
3044         POSTING_READ(reg);
3045         udelay(100);
3046
3047         /* Ironlake workaround, disable clock pointer after downing FDI */
3048         if (HAS_PCH_IBX(dev)) {
3049                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3050         }
3051
3052         /* still set train pattern 1 */
3053         reg = FDI_TX_CTL(pipe);
3054         temp = I915_READ(reg);
3055         temp &= ~FDI_LINK_TRAIN_NONE;
3056         temp |= FDI_LINK_TRAIN_PATTERN_1;
3057         I915_WRITE(reg, temp);
3058
3059         reg = FDI_RX_CTL(pipe);
3060         temp = I915_READ(reg);
3061         if (HAS_PCH_CPT(dev)) {
3062                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3063                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3064         } else {
3065                 temp &= ~FDI_LINK_TRAIN_NONE;
3066                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3067         }
3068         /* BPC in FDI rx is consistent with that in PIPECONF */
3069         temp &= ~(0x07 << 16);
3070         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3071         I915_WRITE(reg, temp);
3072
3073         POSTING_READ(reg);
3074         udelay(100);
3075 }
3076
3077 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3078 {
3079         struct intel_crtc *crtc;
3080
3081         /* Note that we don't need to be called with mode_config.lock here
3082          * as our list of CRTC objects is static for the lifetime of the
3083          * device and so cannot disappear as we iterate. Similarly, we can
3084          * happily treat the predicates as racy, atomic checks as userspace
3085          * cannot claim and pin a new fb without at least acquring the
3086          * struct_mutex and so serialising with us.
3087          */
3088         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3089                 if (atomic_read(&crtc->unpin_work_count) == 0)
3090                         continue;
3091
3092                 if (crtc->unpin_work)
3093                         intel_wait_for_vblank(dev, crtc->pipe);
3094
3095                 return true;
3096         }
3097
3098         return false;
3099 }
3100
3101 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3102 {
3103         struct drm_device *dev = crtc->dev;
3104         struct drm_i915_private *dev_priv = dev->dev_private;
3105
3106         if (crtc->primary->fb == NULL)
3107                 return;
3108
3109         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3110
3111         wait_event(dev_priv->pending_flip_queue,
3112                    !intel_crtc_has_pending_flip(crtc));
3113
3114         mutex_lock(&dev->struct_mutex);
3115         intel_finish_fb(crtc->primary->fb);
3116         mutex_unlock(&dev->struct_mutex);
3117 }
3118
3119 /* Program iCLKIP clock to the desired frequency */
3120 static void lpt_program_iclkip(struct drm_crtc *crtc)
3121 {
3122         struct drm_device *dev = crtc->dev;
3123         struct drm_i915_private *dev_priv = dev->dev_private;
3124         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3125         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3126         u32 temp;
3127
3128         mutex_lock(&dev_priv->dpio_lock);
3129
3130         /* It is necessary to ungate the pixclk gate prior to programming
3131          * the divisors, and gate it back when it is done.
3132          */
3133         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3134
3135         /* Disable SSCCTL */
3136         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3137                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3138                                 SBI_SSCCTL_DISABLE,
3139                         SBI_ICLK);
3140
3141         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3142         if (clock == 20000) {
3143                 auxdiv = 1;
3144                 divsel = 0x41;
3145                 phaseinc = 0x20;
3146         } else {
3147                 /* The iCLK virtual clock root frequency is in MHz,
3148                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3149                  * divisors, it is necessary to divide one by another, so we
3150                  * convert the virtual clock precision to KHz here for higher
3151                  * precision.
3152                  */
3153                 u32 iclk_virtual_root_freq = 172800 * 1000;
3154                 u32 iclk_pi_range = 64;
3155                 u32 desired_divisor, msb_divisor_value, pi_value;
3156
3157                 desired_divisor = (iclk_virtual_root_freq / clock);
3158                 msb_divisor_value = desired_divisor / iclk_pi_range;
3159                 pi_value = desired_divisor % iclk_pi_range;
3160
3161                 auxdiv = 0;
3162                 divsel = msb_divisor_value - 2;
3163                 phaseinc = pi_value;
3164         }
3165
3166         /* This should not happen with any sane values */
3167         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3168                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3169         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3170                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3171
3172         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3173                         clock,
3174                         auxdiv,
3175                         divsel,
3176                         phasedir,
3177                         phaseinc);
3178
3179         /* Program SSCDIVINTPHASE6 */
3180         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3181         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3182         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3183         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3184         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3185         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3186         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3187         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3188
3189         /* Program SSCAUXDIV */
3190         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3191         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3192         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3193         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3194
3195         /* Enable modulator and associated divider */
3196         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3197         temp &= ~SBI_SSCCTL_DISABLE;
3198         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3199
3200         /* Wait for initialization time */
3201         udelay(24);
3202
3203         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3204
3205         mutex_unlock(&dev_priv->dpio_lock);
3206 }
3207
3208 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3209                                                 enum pipe pch_transcoder)
3210 {
3211         struct drm_device *dev = crtc->base.dev;
3212         struct drm_i915_private *dev_priv = dev->dev_private;
3213         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3214
3215         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3216                    I915_READ(HTOTAL(cpu_transcoder)));
3217         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3218                    I915_READ(HBLANK(cpu_transcoder)));
3219         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3220                    I915_READ(HSYNC(cpu_transcoder)));
3221
3222         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3223                    I915_READ(VTOTAL(cpu_transcoder)));
3224         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3225                    I915_READ(VBLANK(cpu_transcoder)));
3226         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3227                    I915_READ(VSYNC(cpu_transcoder)));
3228         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3229                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3230 }
3231
3232 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3233 {
3234         struct drm_i915_private *dev_priv = dev->dev_private;
3235         uint32_t temp;
3236
3237         temp = I915_READ(SOUTH_CHICKEN1);
3238         if (temp & FDI_BC_BIFURCATION_SELECT)
3239                 return;
3240
3241         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3242         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3243
3244         temp |= FDI_BC_BIFURCATION_SELECT;
3245         DRM_DEBUG_KMS("enabling fdi C rx\n");
3246         I915_WRITE(SOUTH_CHICKEN1, temp);
3247         POSTING_READ(SOUTH_CHICKEN1);
3248 }
3249
3250 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3251 {
3252         struct drm_device *dev = intel_crtc->base.dev;
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254
3255         switch (intel_crtc->pipe) {
3256         case PIPE_A:
3257                 break;
3258         case PIPE_B:
3259                 if (intel_crtc->config.fdi_lanes > 2)
3260                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3261                 else
3262                         cpt_enable_fdi_bc_bifurcation(dev);
3263
3264                 break;
3265         case PIPE_C:
3266                 cpt_enable_fdi_bc_bifurcation(dev);
3267
3268                 break;
3269         default:
3270                 BUG();
3271         }
3272 }
3273
3274 /*
3275  * Enable PCH resources required for PCH ports:
3276  *   - PCH PLLs
3277  *   - FDI training & RX/TX
3278  *   - update transcoder timings
3279  *   - DP transcoding bits
3280  *   - transcoder
3281  */
3282 static void ironlake_pch_enable(struct drm_crtc *crtc)
3283 {
3284         struct drm_device *dev = crtc->dev;
3285         struct drm_i915_private *dev_priv = dev->dev_private;
3286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3287         int pipe = intel_crtc->pipe;
3288         u32 reg, temp;
3289
3290         assert_pch_transcoder_disabled(dev_priv, pipe);
3291
3292         if (IS_IVYBRIDGE(dev))
3293                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3294
3295         /* Write the TU size bits before fdi link training, so that error
3296          * detection works. */
3297         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3298                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3299
3300         /* For PCH output, training FDI link */
3301         dev_priv->display.fdi_link_train(crtc);
3302
3303         /* We need to program the right clock selection before writing the pixel
3304          * mutliplier into the DPLL. */
3305         if (HAS_PCH_CPT(dev)) {
3306                 u32 sel;
3307
3308                 temp = I915_READ(PCH_DPLL_SEL);
3309                 temp |= TRANS_DPLL_ENABLE(pipe);
3310                 sel = TRANS_DPLLB_SEL(pipe);
3311                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3312                         temp |= sel;
3313                 else
3314                         temp &= ~sel;
3315                 I915_WRITE(PCH_DPLL_SEL, temp);
3316         }
3317
3318         /* XXX: pch pll's can be enabled any time before we enable the PCH
3319          * transcoder, and we actually should do this to not upset any PCH
3320          * transcoder that already use the clock when we share it.
3321          *
3322          * Note that enable_shared_dpll tries to do the right thing, but
3323          * get_shared_dpll unconditionally resets the pll - we need that to have
3324          * the right LVDS enable sequence. */
3325         ironlake_enable_shared_dpll(intel_crtc);
3326
3327         /* set transcoder timing, panel must allow it */
3328         assert_panel_unlocked(dev_priv, pipe);
3329         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3330
3331         intel_fdi_normal_train(crtc);
3332
3333         /* For PCH DP, enable TRANS_DP_CTL */
3334         if (HAS_PCH_CPT(dev) &&
3335             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3336              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3337                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3338                 reg = TRANS_DP_CTL(pipe);
3339                 temp = I915_READ(reg);
3340                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3341                           TRANS_DP_SYNC_MASK |
3342                           TRANS_DP_BPC_MASK);
3343                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3344                          TRANS_DP_ENH_FRAMING);
3345                 temp |= bpc << 9; /* same format but at 11:9 */
3346
3347                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3348                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3349                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3350                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3351
3352                 switch (intel_trans_dp_port_sel(crtc)) {
3353                 case PCH_DP_B:
3354                         temp |= TRANS_DP_PORT_SEL_B;
3355                         break;
3356                 case PCH_DP_C:
3357                         temp |= TRANS_DP_PORT_SEL_C;
3358                         break;
3359                 case PCH_DP_D:
3360                         temp |= TRANS_DP_PORT_SEL_D;
3361                         break;
3362                 default:
3363                         BUG();
3364                 }
3365
3366                 I915_WRITE(reg, temp);
3367         }
3368
3369         ironlake_enable_pch_transcoder(dev_priv, pipe);
3370 }
3371
3372 static void lpt_pch_enable(struct drm_crtc *crtc)
3373 {
3374         struct drm_device *dev = crtc->dev;
3375         struct drm_i915_private *dev_priv = dev->dev_private;
3376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3377         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3378
3379         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3380
3381         lpt_program_iclkip(crtc);
3382
3383         /* Set transcoder timing. */
3384         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3385
3386         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3387 }
3388
3389 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3390 {
3391         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3392
3393         if (pll == NULL)
3394                 return;
3395
3396         if (pll->refcount == 0) {
3397                 WARN(1, "bad %s refcount\n", pll->name);
3398                 return;
3399         }
3400
3401         if (--pll->refcount == 0) {
3402                 WARN_ON(pll->on);
3403                 WARN_ON(pll->active);
3404         }
3405
3406         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3407 }
3408
3409 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3410 {
3411         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3412         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3413         enum intel_dpll_id i;
3414
3415         if (pll) {
3416                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3417                               crtc->base.base.id, pll->name);
3418                 intel_put_shared_dpll(crtc);
3419         }
3420
3421         if (HAS_PCH_IBX(dev_priv->dev)) {
3422                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3423                 i = (enum intel_dpll_id) crtc->pipe;
3424                 pll = &dev_priv->shared_dplls[i];
3425
3426                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3427                               crtc->base.base.id, pll->name);
3428
3429                 goto found;
3430         }
3431
3432         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3433                 pll = &dev_priv->shared_dplls[i];
3434
3435                 /* Only want to check enabled timings first */
3436                 if (pll->refcount == 0)
3437                         continue;
3438
3439                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3440                            sizeof(pll->hw_state)) == 0) {
3441                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3442                                       crtc->base.base.id,
3443                                       pll->name, pll->refcount, pll->active);
3444
3445                         goto found;
3446                 }
3447         }
3448
3449         /* Ok no matching timings, maybe there's a free one? */
3450         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3451                 pll = &dev_priv->shared_dplls[i];
3452                 if (pll->refcount == 0) {
3453                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3454                                       crtc->base.base.id, pll->name);
3455                         goto found;
3456                 }
3457         }
3458
3459         return NULL;
3460
3461 found:
3462         crtc->config.shared_dpll = i;
3463         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3464                          pipe_name(crtc->pipe));
3465
3466         if (pll->active == 0) {
3467                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3468                        sizeof(pll->hw_state));
3469
3470                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3471                 WARN_ON(pll->on);
3472                 assert_shared_dpll_disabled(dev_priv, pll);
3473
3474                 pll->mode_set(dev_priv, pll);
3475         }
3476         pll->refcount++;
3477
3478         return pll;
3479 }
3480
3481 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3482 {
3483         struct drm_i915_private *dev_priv = dev->dev_private;
3484         int dslreg = PIPEDSL(pipe);
3485         u32 temp;
3486
3487         temp = I915_READ(dslreg);
3488         udelay(500);
3489         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3490                 if (wait_for(I915_READ(dslreg) != temp, 5))
3491                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3492         }
3493 }
3494
3495 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3496 {
3497         struct drm_device *dev = crtc->base.dev;
3498         struct drm_i915_private *dev_priv = dev->dev_private;
3499         int pipe = crtc->pipe;
3500
3501         if (crtc->config.pch_pfit.enabled) {
3502                 /* Force use of hard-coded filter coefficients
3503                  * as some pre-programmed values are broken,
3504                  * e.g. x201.
3505                  */
3506                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3507                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3508                                                  PF_PIPE_SEL_IVB(pipe));
3509                 else
3510                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3511                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3512                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3513         }
3514 }
3515
3516 static void intel_enable_planes(struct drm_crtc *crtc)
3517 {
3518         struct drm_device *dev = crtc->dev;
3519         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3520         struct drm_plane *plane;
3521         struct intel_plane *intel_plane;
3522
3523         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3524                 intel_plane = to_intel_plane(plane);
3525                 if (intel_plane->pipe == pipe)
3526                         intel_plane_restore(&intel_plane->base);
3527         }
3528 }
3529
3530 static void intel_disable_planes(struct drm_crtc *crtc)
3531 {
3532         struct drm_device *dev = crtc->dev;
3533         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3534         struct drm_plane *plane;
3535         struct intel_plane *intel_plane;
3536
3537         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3538                 intel_plane = to_intel_plane(plane);
3539                 if (intel_plane->pipe == pipe)
3540                         intel_plane_disable(&intel_plane->base);
3541         }
3542 }
3543
3544 void hsw_enable_ips(struct intel_crtc *crtc)
3545 {
3546         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3547
3548         if (!crtc->config.ips_enabled)
3549                 return;
3550
3551         /* We can only enable IPS after we enable a plane and wait for a vblank.
3552          * We guarantee that the plane is enabled by calling intel_enable_ips
3553          * only after intel_enable_plane. And intel_enable_plane already waits
3554          * for a vblank, so all we need to do here is to enable the IPS bit. */
3555         assert_plane_enabled(dev_priv, crtc->plane);
3556         if (IS_BROADWELL(crtc->base.dev)) {
3557                 mutex_lock(&dev_priv->rps.hw_lock);
3558                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3559                 mutex_unlock(&dev_priv->rps.hw_lock);
3560                 /* Quoting Art Runyan: "its not safe to expect any particular
3561                  * value in IPS_CTL bit 31 after enabling IPS through the
3562                  * mailbox." Moreover, the mailbox may return a bogus state,
3563                  * so we need to just enable it and continue on.
3564                  */
3565         } else {
3566                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3567                 /* The bit only becomes 1 in the next vblank, so this wait here
3568                  * is essentially intel_wait_for_vblank. If we don't have this
3569                  * and don't wait for vblanks until the end of crtc_enable, then
3570                  * the HW state readout code will complain that the expected
3571                  * IPS_CTL value is not the one we read. */
3572                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3573                         DRM_ERROR("Timed out waiting for IPS enable\n");
3574         }
3575 }
3576
3577 void hsw_disable_ips(struct intel_crtc *crtc)
3578 {
3579         struct drm_device *dev = crtc->base.dev;
3580         struct drm_i915_private *dev_priv = dev->dev_private;
3581
3582         if (!crtc->config.ips_enabled)
3583                 return;
3584
3585         assert_plane_enabled(dev_priv, crtc->plane);
3586         if (IS_BROADWELL(crtc->base.dev)) {
3587                 mutex_lock(&dev_priv->rps.hw_lock);
3588                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3589                 mutex_unlock(&dev_priv->rps.hw_lock);
3590         } else {
3591                 I915_WRITE(IPS_CTL, 0);
3592                 POSTING_READ(IPS_CTL);
3593         }
3594
3595         /* We need to wait for a vblank before we can disable the plane. */
3596         intel_wait_for_vblank(dev, crtc->pipe);
3597 }
3598
3599 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3600 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3601 {
3602         struct drm_device *dev = crtc->dev;
3603         struct drm_i915_private *dev_priv = dev->dev_private;
3604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3605         enum pipe pipe = intel_crtc->pipe;
3606         int palreg = PALETTE(pipe);
3607         int i;
3608         bool reenable_ips = false;
3609
3610         /* The clocks have to be on to load the palette. */
3611         if (!crtc->enabled || !intel_crtc->active)
3612                 return;
3613
3614         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3615                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3616                         assert_dsi_pll_enabled(dev_priv);
3617                 else
3618                         assert_pll_enabled(dev_priv, pipe);
3619         }
3620
3621         /* use legacy palette for Ironlake */
3622         if (HAS_PCH_SPLIT(dev))
3623                 palreg = LGC_PALETTE(pipe);
3624
3625         /* Workaround : Do not read or write the pipe palette/gamma data while
3626          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3627          */
3628         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3629             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3630              GAMMA_MODE_MODE_SPLIT)) {
3631                 hsw_disable_ips(intel_crtc);
3632                 reenable_ips = true;
3633         }
3634
3635         for (i = 0; i < 256; i++) {
3636                 I915_WRITE(palreg + 4 * i,
3637                            (intel_crtc->lut_r[i] << 16) |
3638                            (intel_crtc->lut_g[i] << 8) |
3639                            intel_crtc->lut_b[i]);
3640         }
3641
3642         if (reenable_ips)
3643                 hsw_enable_ips(intel_crtc);
3644 }
3645
3646 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3647 {
3648         struct drm_device *dev = crtc->dev;
3649         struct drm_i915_private *dev_priv = dev->dev_private;
3650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3651         struct intel_encoder *encoder;
3652         int pipe = intel_crtc->pipe;
3653         int plane = intel_crtc->plane;
3654
3655         WARN_ON(!crtc->enabled);
3656
3657         if (intel_crtc->active)
3658                 return;
3659
3660         intel_crtc->active = true;
3661
3662         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3663         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3664
3665         for_each_encoder_on_crtc(dev, crtc, encoder)
3666                 if (encoder->pre_enable)
3667                         encoder->pre_enable(encoder);
3668
3669         if (intel_crtc->config.has_pch_encoder) {
3670                 /* Note: FDI PLL enabling _must_ be done before we enable the
3671                  * cpu pipes, hence this is separate from all the other fdi/pch
3672                  * enabling. */
3673                 ironlake_fdi_pll_enable(intel_crtc);
3674         } else {
3675                 assert_fdi_tx_disabled(dev_priv, pipe);
3676                 assert_fdi_rx_disabled(dev_priv, pipe);
3677         }
3678
3679         ironlake_pfit_enable(intel_crtc);
3680
3681         /*
3682          * On ILK+ LUT must be loaded before the pipe is running but with
3683          * clocks enabled
3684          */
3685         intel_crtc_load_lut(crtc);
3686
3687         intel_update_watermarks(crtc);
3688         intel_enable_pipe(intel_crtc);
3689         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3690         intel_enable_planes(crtc);
3691         intel_crtc_update_cursor(crtc, true);
3692
3693         if (intel_crtc->config.has_pch_encoder)
3694                 ironlake_pch_enable(crtc);
3695
3696         mutex_lock(&dev->struct_mutex);
3697         intel_update_fbc(dev);
3698         mutex_unlock(&dev->struct_mutex);
3699
3700         for_each_encoder_on_crtc(dev, crtc, encoder)
3701                 encoder->enable(encoder);
3702
3703         if (HAS_PCH_CPT(dev))
3704                 cpt_verify_modeset(dev, intel_crtc->pipe);
3705
3706         /*
3707          * There seems to be a race in PCH platform hw (at least on some
3708          * outputs) where an enabled pipe still completes any pageflip right
3709          * away (as if the pipe is off) instead of waiting for vblank. As soon
3710          * as the first vblank happend, everything works as expected. Hence just
3711          * wait for one vblank before returning to avoid strange things
3712          * happening.
3713          */
3714         intel_wait_for_vblank(dev, intel_crtc->pipe);
3715 }
3716
3717 /* IPS only exists on ULT machines and is tied to pipe A. */
3718 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3719 {
3720         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3721 }
3722
3723 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3724 {
3725         struct drm_device *dev = crtc->dev;
3726         struct drm_i915_private *dev_priv = dev->dev_private;
3727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3728         int pipe = intel_crtc->pipe;
3729         int plane = intel_crtc->plane;
3730
3731         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3732         intel_enable_planes(crtc);
3733         intel_crtc_update_cursor(crtc, true);
3734
3735         hsw_enable_ips(intel_crtc);
3736
3737         mutex_lock(&dev->struct_mutex);
3738         intel_update_fbc(dev);
3739         mutex_unlock(&dev->struct_mutex);
3740 }
3741
3742 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3743 {
3744         struct drm_device *dev = crtc->dev;
3745         struct drm_i915_private *dev_priv = dev->dev_private;
3746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3747         int pipe = intel_crtc->pipe;
3748         int plane = intel_crtc->plane;
3749
3750         intel_crtc_wait_for_pending_flips(crtc);
3751         drm_vblank_off(dev, pipe);
3752
3753         /* FBC must be disabled before disabling the plane on HSW. */
3754         if (dev_priv->fbc.plane == plane)
3755                 intel_disable_fbc(dev);
3756
3757         hsw_disable_ips(intel_crtc);
3758
3759         intel_crtc_update_cursor(crtc, false);
3760         intel_disable_planes(crtc);
3761         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3762 }
3763
3764 /*
3765  * This implements the workaround described in the "notes" section of the mode
3766  * set sequence documentation. When going from no pipes or single pipe to
3767  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3768  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3769  */
3770 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3771 {
3772         struct drm_device *dev = crtc->base.dev;
3773         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3774
3775         /* We want to get the other_active_crtc only if there's only 1 other
3776          * active crtc. */
3777         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3778                 if (!crtc_it->active || crtc_it == crtc)
3779                         continue;
3780
3781                 if (other_active_crtc)
3782                         return;
3783
3784                 other_active_crtc = crtc_it;
3785         }
3786         if (!other_active_crtc)
3787                 return;
3788
3789         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3790         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3791 }
3792
3793 static void haswell_crtc_enable(struct drm_crtc *crtc)
3794 {
3795         struct drm_device *dev = crtc->dev;
3796         struct drm_i915_private *dev_priv = dev->dev_private;
3797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798         struct intel_encoder *encoder;
3799         int pipe = intel_crtc->pipe;
3800
3801         WARN_ON(!crtc->enabled);
3802
3803         if (intel_crtc->active)
3804                 return;
3805
3806         intel_crtc->active = true;
3807
3808         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3809         if (intel_crtc->config.has_pch_encoder)
3810                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3811
3812         if (intel_crtc->config.has_pch_encoder)
3813                 dev_priv->display.fdi_link_train(crtc);
3814
3815         for_each_encoder_on_crtc(dev, crtc, encoder)
3816                 if (encoder->pre_enable)
3817                         encoder->pre_enable(encoder);
3818
3819         intel_ddi_enable_pipe_clock(intel_crtc);
3820
3821         ironlake_pfit_enable(intel_crtc);
3822
3823         /*
3824          * On ILK+ LUT must be loaded before the pipe is running but with
3825          * clocks enabled
3826          */
3827         intel_crtc_load_lut(crtc);
3828
3829         intel_ddi_set_pipe_settings(crtc);
3830         intel_ddi_enable_transcoder_func(crtc);
3831
3832         intel_update_watermarks(crtc);
3833         intel_enable_pipe(intel_crtc);
3834
3835         if (intel_crtc->config.has_pch_encoder)
3836                 lpt_pch_enable(crtc);
3837
3838         for_each_encoder_on_crtc(dev, crtc, encoder) {
3839                 encoder->enable(encoder);
3840                 intel_opregion_notify_encoder(encoder, true);
3841         }
3842
3843         /* If we change the relative order between pipe/planes enabling, we need
3844          * to change the workaround. */
3845         haswell_mode_set_planes_workaround(intel_crtc);
3846         haswell_crtc_enable_planes(crtc);
3847 }
3848
3849 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3850 {
3851         struct drm_device *dev = crtc->base.dev;
3852         struct drm_i915_private *dev_priv = dev->dev_private;
3853         int pipe = crtc->pipe;
3854
3855         /* To avoid upsetting the power well on haswell only disable the pfit if
3856          * it's in use. The hw state code will make sure we get this right. */
3857         if (crtc->config.pch_pfit.enabled) {
3858                 I915_WRITE(PF_CTL(pipe), 0);
3859                 I915_WRITE(PF_WIN_POS(pipe), 0);
3860                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3861         }
3862 }
3863
3864 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3865 {
3866         struct drm_device *dev = crtc->dev;
3867         struct drm_i915_private *dev_priv = dev->dev_private;
3868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3869         struct intel_encoder *encoder;
3870         int pipe = intel_crtc->pipe;
3871         int plane = intel_crtc->plane;
3872         u32 reg, temp;
3873
3874
3875         if (!intel_crtc->active)
3876                 return;
3877
3878         for_each_encoder_on_crtc(dev, crtc, encoder)
3879                 encoder->disable(encoder);
3880
3881         intel_crtc_wait_for_pending_flips(crtc);
3882         drm_vblank_off(dev, pipe);
3883
3884         if (dev_priv->fbc.plane == plane)
3885                 intel_disable_fbc(dev);
3886
3887         intel_crtc_update_cursor(crtc, false);
3888         intel_disable_planes(crtc);
3889         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3890
3891         if (intel_crtc->config.has_pch_encoder)
3892                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3893
3894         intel_disable_pipe(dev_priv, pipe);
3895
3896         ironlake_pfit_disable(intel_crtc);
3897
3898         for_each_encoder_on_crtc(dev, crtc, encoder)
3899                 if (encoder->post_disable)
3900                         encoder->post_disable(encoder);
3901
3902         if (intel_crtc->config.has_pch_encoder) {
3903                 ironlake_fdi_disable(crtc);
3904
3905                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3906                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3907
3908                 if (HAS_PCH_CPT(dev)) {
3909                         /* disable TRANS_DP_CTL */
3910                         reg = TRANS_DP_CTL(pipe);
3911                         temp = I915_READ(reg);
3912                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3913                                   TRANS_DP_PORT_SEL_MASK);
3914                         temp |= TRANS_DP_PORT_SEL_NONE;
3915                         I915_WRITE(reg, temp);
3916
3917                         /* disable DPLL_SEL */
3918                         temp = I915_READ(PCH_DPLL_SEL);
3919                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3920                         I915_WRITE(PCH_DPLL_SEL, temp);
3921                 }
3922
3923                 /* disable PCH DPLL */
3924                 intel_disable_shared_dpll(intel_crtc);
3925
3926                 ironlake_fdi_pll_disable(intel_crtc);
3927         }
3928
3929         intel_crtc->active = false;
3930         intel_update_watermarks(crtc);
3931
3932         mutex_lock(&dev->struct_mutex);
3933         intel_update_fbc(dev);
3934         mutex_unlock(&dev->struct_mutex);
3935 }
3936
3937 static void haswell_crtc_disable(struct drm_crtc *crtc)
3938 {
3939         struct drm_device *dev = crtc->dev;
3940         struct drm_i915_private *dev_priv = dev->dev_private;
3941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3942         struct intel_encoder *encoder;
3943         int pipe = intel_crtc->pipe;
3944         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3945
3946         if (!intel_crtc->active)
3947                 return;
3948
3949         haswell_crtc_disable_planes(crtc);
3950
3951         for_each_encoder_on_crtc(dev, crtc, encoder) {
3952                 intel_opregion_notify_encoder(encoder, false);
3953                 encoder->disable(encoder);
3954         }
3955
3956         if (intel_crtc->config.has_pch_encoder)
3957                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3958         intel_disable_pipe(dev_priv, pipe);
3959
3960         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3961
3962         ironlake_pfit_disable(intel_crtc);
3963
3964         intel_ddi_disable_pipe_clock(intel_crtc);
3965
3966         for_each_encoder_on_crtc(dev, crtc, encoder)
3967                 if (encoder->post_disable)
3968                         encoder->post_disable(encoder);
3969
3970         if (intel_crtc->config.has_pch_encoder) {
3971                 lpt_disable_pch_transcoder(dev_priv);
3972                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3973                 intel_ddi_fdi_disable(crtc);
3974         }
3975
3976         intel_crtc->active = false;
3977         intel_update_watermarks(crtc);
3978
3979         mutex_lock(&dev->struct_mutex);
3980         intel_update_fbc(dev);
3981         mutex_unlock(&dev->struct_mutex);
3982 }
3983
3984 static void ironlake_crtc_off(struct drm_crtc *crtc)
3985 {
3986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3987         intel_put_shared_dpll(intel_crtc);
3988 }
3989
3990 static void haswell_crtc_off(struct drm_crtc *crtc)
3991 {
3992         intel_ddi_put_crtc_pll(crtc);
3993 }
3994
3995 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3996 {
3997         if (!enable && intel_crtc->overlay) {
3998                 struct drm_device *dev = intel_crtc->base.dev;
3999                 struct drm_i915_private *dev_priv = dev->dev_private;
4000
4001                 mutex_lock(&dev->struct_mutex);
4002                 dev_priv->mm.interruptible = false;
4003                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4004                 dev_priv->mm.interruptible = true;
4005                 mutex_unlock(&dev->struct_mutex);
4006         }
4007
4008         /* Let userspace switch the overlay on again. In most cases userspace
4009          * has to recompute where to put it anyway.
4010          */
4011 }
4012
4013 /**
4014  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
4015  * cursor plane briefly if not already running after enabling the display
4016  * plane.
4017  * This workaround avoids occasional blank screens when self refresh is
4018  * enabled.
4019  */
4020 static void
4021 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
4022 {
4023         u32 cntl = I915_READ(CURCNTR(pipe));
4024
4025         if ((cntl & CURSOR_MODE) == 0) {
4026                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
4027
4028                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
4029                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
4030                 intel_wait_for_vblank(dev_priv->dev, pipe);
4031                 I915_WRITE(CURCNTR(pipe), cntl);
4032                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
4033                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
4034         }
4035 }
4036
4037 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4038 {
4039         struct drm_device *dev = crtc->base.dev;
4040         struct drm_i915_private *dev_priv = dev->dev_private;
4041         struct intel_crtc_config *pipe_config = &crtc->config;
4042
4043         if (!crtc->config.gmch_pfit.control)
4044                 return;
4045
4046         /*
4047          * The panel fitter should only be adjusted whilst the pipe is disabled,
4048          * according to register description and PRM.
4049          */
4050         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4051         assert_pipe_disabled(dev_priv, crtc->pipe);
4052
4053         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4054         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4055
4056         /* Border color in case we don't scale up to the full screen. Black by
4057          * default, change to something else for debugging. */
4058         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4059 }
4060
4061 #define for_each_power_domain(domain, mask)                             \
4062         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4063                 if ((1 << (domain)) & (mask))
4064
4065 enum intel_display_power_domain
4066 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4067 {
4068         struct drm_device *dev = intel_encoder->base.dev;
4069         struct intel_digital_port *intel_dig_port;
4070
4071         switch (intel_encoder->type) {
4072         case INTEL_OUTPUT_UNKNOWN:
4073                 /* Only DDI platforms should ever use this output type */
4074                 WARN_ON_ONCE(!HAS_DDI(dev));
4075         case INTEL_OUTPUT_DISPLAYPORT:
4076         case INTEL_OUTPUT_HDMI:
4077         case INTEL_OUTPUT_EDP:
4078                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4079                 switch (intel_dig_port->port) {
4080                 case PORT_A:
4081                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4082                 case PORT_B:
4083                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4084                 case PORT_C:
4085                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4086                 case PORT_D:
4087                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4088                 default:
4089                         WARN_ON_ONCE(1);
4090                         return POWER_DOMAIN_PORT_OTHER;
4091                 }
4092         case INTEL_OUTPUT_ANALOG:
4093                 return POWER_DOMAIN_PORT_CRT;
4094         case INTEL_OUTPUT_DSI:
4095                 return POWER_DOMAIN_PORT_DSI;
4096         default:
4097                 return POWER_DOMAIN_PORT_OTHER;
4098         }
4099 }
4100
4101 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4102 {
4103         struct drm_device *dev = crtc->dev;
4104         struct intel_encoder *intel_encoder;
4105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4106         enum pipe pipe = intel_crtc->pipe;
4107         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4108         unsigned long mask;
4109         enum transcoder transcoder;
4110
4111         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4112
4113         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4114         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4115         if (pfit_enabled)
4116                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4117
4118         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4119                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4120
4121         return mask;
4122 }
4123
4124 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4125                                   bool enable)
4126 {
4127         if (dev_priv->power_domains.init_power_on == enable)
4128                 return;
4129
4130         if (enable)
4131                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4132         else
4133                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4134
4135         dev_priv->power_domains.init_power_on = enable;
4136 }
4137
4138 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4139 {
4140         struct drm_i915_private *dev_priv = dev->dev_private;
4141         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4142         struct intel_crtc *crtc;
4143
4144         /*
4145          * First get all needed power domains, then put all unneeded, to avoid
4146          * any unnecessary toggling of the power wells.
4147          */
4148         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4149                 enum intel_display_power_domain domain;
4150
4151                 if (!crtc->base.enabled)
4152                         continue;
4153
4154                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4155
4156                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4157                         intel_display_power_get(dev_priv, domain);
4158         }
4159
4160         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4161                 enum intel_display_power_domain domain;
4162
4163                 for_each_power_domain(domain, crtc->enabled_power_domains)
4164                         intel_display_power_put(dev_priv, domain);
4165
4166                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4167         }
4168
4169         intel_display_set_init_power(dev_priv, false);
4170 }
4171
4172 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4173 {
4174         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4175
4176         /* Obtain SKU information */
4177         mutex_lock(&dev_priv->dpio_lock);
4178         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4179                 CCK_FUSE_HPLL_FREQ_MASK;
4180         mutex_unlock(&dev_priv->dpio_lock);
4181
4182         return vco_freq[hpll_freq];
4183 }
4184
4185 /* Adjust CDclk dividers to allow high res or save power if possible */
4186 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4187 {
4188         struct drm_i915_private *dev_priv = dev->dev_private;
4189         u32 val, cmd;
4190
4191         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4192         dev_priv->vlv_cdclk_freq = cdclk;
4193
4194         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4195                 cmd = 2;
4196         else if (cdclk == 266)
4197                 cmd = 1;
4198         else
4199                 cmd = 0;
4200
4201         mutex_lock(&dev_priv->rps.hw_lock);
4202         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4203         val &= ~DSPFREQGUAR_MASK;
4204         val |= (cmd << DSPFREQGUAR_SHIFT);
4205         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4206         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4207                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4208                      50)) {
4209                 DRM_ERROR("timed out waiting for CDclk change\n");
4210         }
4211         mutex_unlock(&dev_priv->rps.hw_lock);
4212
4213         if (cdclk == 400) {
4214                 u32 divider, vco;
4215
4216                 vco = valleyview_get_vco(dev_priv);
4217                 divider = ((vco << 1) / cdclk) - 1;
4218
4219                 mutex_lock(&dev_priv->dpio_lock);
4220                 /* adjust cdclk divider */
4221                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4222                 val &= ~0xf;
4223                 val |= divider;
4224                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4225                 mutex_unlock(&dev_priv->dpio_lock);
4226         }
4227
4228         mutex_lock(&dev_priv->dpio_lock);
4229         /* adjust self-refresh exit latency value */
4230         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4231         val &= ~0x7f;
4232
4233         /*
4234          * For high bandwidth configs, we set a higher latency in the bunit
4235          * so that the core display fetch happens in time to avoid underruns.
4236          */
4237         if (cdclk == 400)
4238                 val |= 4500 / 250; /* 4.5 usec */
4239         else
4240                 val |= 3000 / 250; /* 3.0 usec */
4241         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4242         mutex_unlock(&dev_priv->dpio_lock);
4243
4244         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4245         intel_i2c_reset(dev);
4246 }
4247
4248 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4249 {
4250         int cur_cdclk, vco;
4251         int divider;
4252
4253         vco = valleyview_get_vco(dev_priv);
4254
4255         mutex_lock(&dev_priv->dpio_lock);
4256         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4257         mutex_unlock(&dev_priv->dpio_lock);
4258
4259         divider &= 0xf;
4260
4261         cur_cdclk = (vco << 1) / (divider + 1);
4262
4263         return cur_cdclk;
4264 }
4265
4266 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4267                                  int max_pixclk)
4268 {
4269         /*
4270          * Really only a few cases to deal with, as only 4 CDclks are supported:
4271          *   200MHz
4272          *   267MHz
4273          *   320MHz
4274          *   400MHz
4275          * So we check to see whether we're above 90% of the lower bin and
4276          * adjust if needed.
4277          */
4278         if (max_pixclk > 288000) {
4279                 return 400;
4280         } else if (max_pixclk > 240000) {
4281                 return 320;
4282         } else
4283                 return 266;
4284         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4285 }
4286
4287 /* compute the max pixel clock for new configuration */
4288 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4289 {
4290         struct drm_device *dev = dev_priv->dev;
4291         struct intel_crtc *intel_crtc;
4292         int max_pixclk = 0;
4293
4294         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4295                             base.head) {
4296                 if (intel_crtc->new_enabled)
4297                         max_pixclk = max(max_pixclk,
4298                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4299         }
4300
4301         return max_pixclk;
4302 }
4303
4304 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4305                                             unsigned *prepare_pipes)
4306 {
4307         struct drm_i915_private *dev_priv = dev->dev_private;
4308         struct intel_crtc *intel_crtc;
4309         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4310
4311         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4312             dev_priv->vlv_cdclk_freq)
4313                 return;
4314
4315         /* disable/enable all currently active pipes while we change cdclk */
4316         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4317                             base.head)
4318                 if (intel_crtc->base.enabled)
4319                         *prepare_pipes |= (1 << intel_crtc->pipe);
4320 }
4321
4322 static void valleyview_modeset_global_resources(struct drm_device *dev)
4323 {
4324         struct drm_i915_private *dev_priv = dev->dev_private;
4325         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4326         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4327
4328         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4329                 valleyview_set_cdclk(dev, req_cdclk);
4330         modeset_update_crtc_power_domains(dev);
4331 }
4332
4333 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4334 {
4335         struct drm_device *dev = crtc->dev;
4336         struct drm_i915_private *dev_priv = dev->dev_private;
4337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4338         struct intel_encoder *encoder;
4339         int pipe = intel_crtc->pipe;
4340         int plane = intel_crtc->plane;
4341         bool is_dsi;
4342
4343         WARN_ON(!crtc->enabled);
4344
4345         if (intel_crtc->active)
4346                 return;
4347
4348         intel_crtc->active = true;
4349
4350         for_each_encoder_on_crtc(dev, crtc, encoder)
4351                 if (encoder->pre_pll_enable)
4352                         encoder->pre_pll_enable(encoder);
4353
4354         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4355
4356         if (!is_dsi)
4357                 vlv_enable_pll(intel_crtc);
4358
4359         for_each_encoder_on_crtc(dev, crtc, encoder)
4360                 if (encoder->pre_enable)
4361                         encoder->pre_enable(encoder);
4362
4363         i9xx_pfit_enable(intel_crtc);
4364
4365         intel_crtc_load_lut(crtc);
4366
4367         intel_update_watermarks(crtc);
4368         intel_enable_pipe(intel_crtc);
4369         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4370         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4371         intel_enable_planes(crtc);
4372         intel_crtc_update_cursor(crtc, true);
4373
4374         intel_update_fbc(dev);
4375
4376         for_each_encoder_on_crtc(dev, crtc, encoder)
4377                 encoder->enable(encoder);
4378 }
4379
4380 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4381 {
4382         struct drm_device *dev = crtc->dev;
4383         struct drm_i915_private *dev_priv = dev->dev_private;
4384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4385         struct intel_encoder *encoder;
4386         int pipe = intel_crtc->pipe;
4387         int plane = intel_crtc->plane;
4388
4389         WARN_ON(!crtc->enabled);
4390
4391         if (intel_crtc->active)
4392                 return;
4393
4394         intel_crtc->active = true;
4395
4396         for_each_encoder_on_crtc(dev, crtc, encoder)
4397                 if (encoder->pre_enable)
4398                         encoder->pre_enable(encoder);
4399
4400         i9xx_enable_pll(intel_crtc);
4401
4402         i9xx_pfit_enable(intel_crtc);
4403
4404         intel_crtc_load_lut(crtc);
4405
4406         intel_update_watermarks(crtc);
4407         intel_enable_pipe(intel_crtc);
4408         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4409         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4410         intel_enable_planes(crtc);
4411         /* The fixup needs to happen before cursor is enabled */
4412         if (IS_G4X(dev))
4413                 g4x_fixup_plane(dev_priv, pipe);
4414         intel_crtc_update_cursor(crtc, true);
4415
4416         /* Give the overlay scaler a chance to enable if it's on this pipe */
4417         intel_crtc_dpms_overlay(intel_crtc, true);
4418
4419         intel_update_fbc(dev);
4420
4421         for_each_encoder_on_crtc(dev, crtc, encoder)
4422                 encoder->enable(encoder);
4423 }
4424
4425 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4426 {
4427         struct drm_device *dev = crtc->base.dev;
4428         struct drm_i915_private *dev_priv = dev->dev_private;
4429
4430         if (!crtc->config.gmch_pfit.control)
4431                 return;
4432
4433         assert_pipe_disabled(dev_priv, crtc->pipe);
4434
4435         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4436                          I915_READ(PFIT_CONTROL));
4437         I915_WRITE(PFIT_CONTROL, 0);
4438 }
4439
4440 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4441 {
4442         struct drm_device *dev = crtc->dev;
4443         struct drm_i915_private *dev_priv = dev->dev_private;
4444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4445         struct intel_encoder *encoder;
4446         int pipe = intel_crtc->pipe;
4447         int plane = intel_crtc->plane;
4448
4449         if (!intel_crtc->active)
4450                 return;
4451
4452         for_each_encoder_on_crtc(dev, crtc, encoder)
4453                 encoder->disable(encoder);
4454
4455         /* Give the overlay scaler a chance to disable if it's on this pipe */
4456         intel_crtc_wait_for_pending_flips(crtc);
4457         drm_vblank_off(dev, pipe);
4458
4459         if (dev_priv->fbc.plane == plane)
4460                 intel_disable_fbc(dev);
4461
4462         intel_crtc_dpms_overlay(intel_crtc, false);
4463         intel_crtc_update_cursor(crtc, false);
4464         intel_disable_planes(crtc);
4465         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
4466
4467         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4468         intel_disable_pipe(dev_priv, pipe);
4469
4470         i9xx_pfit_disable(intel_crtc);
4471
4472         for_each_encoder_on_crtc(dev, crtc, encoder)
4473                 if (encoder->post_disable)
4474                         encoder->post_disable(encoder);
4475
4476         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4477                 vlv_disable_pll(dev_priv, pipe);
4478         else if (!IS_VALLEYVIEW(dev))
4479                 i9xx_disable_pll(dev_priv, pipe);
4480
4481         intel_crtc->active = false;
4482         intel_update_watermarks(crtc);
4483
4484         intel_update_fbc(dev);
4485 }
4486
4487 static void i9xx_crtc_off(struct drm_crtc *crtc)
4488 {
4489 }
4490
4491 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4492                                     bool enabled)
4493 {
4494         struct drm_device *dev = crtc->dev;
4495         struct drm_i915_master_private *master_priv;
4496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4497         int pipe = intel_crtc->pipe;
4498
4499         if (!dev->primary->master)
4500                 return;
4501
4502         master_priv = dev->primary->master->driver_priv;
4503         if (!master_priv->sarea_priv)
4504                 return;
4505
4506         switch (pipe) {
4507         case 0:
4508                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4509                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4510                 break;
4511         case 1:
4512                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4513                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4514                 break;
4515         default:
4516                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4517                 break;
4518         }
4519 }
4520
4521 /**
4522  * Sets the power management mode of the pipe and plane.
4523  */
4524 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4525 {
4526         struct drm_device *dev = crtc->dev;
4527         struct drm_i915_private *dev_priv = dev->dev_private;
4528         struct intel_encoder *intel_encoder;
4529         bool enable = false;
4530
4531         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4532                 enable |= intel_encoder->connectors_active;
4533
4534         if (enable)
4535                 dev_priv->display.crtc_enable(crtc);
4536         else
4537                 dev_priv->display.crtc_disable(crtc);
4538
4539         intel_crtc_update_sarea(crtc, enable);
4540 }
4541
4542 static void intel_crtc_disable(struct drm_crtc *crtc)
4543 {
4544         struct drm_device *dev = crtc->dev;
4545         struct drm_connector *connector;
4546         struct drm_i915_private *dev_priv = dev->dev_private;
4547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4548
4549         /* crtc should still be enabled when we disable it. */
4550         WARN_ON(!crtc->enabled);
4551
4552         dev_priv->display.crtc_disable(crtc);
4553         intel_crtc->eld_vld = false;
4554         intel_crtc_update_sarea(crtc, false);
4555         dev_priv->display.off(crtc);
4556
4557         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4558         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4559         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4560
4561         if (crtc->primary->fb) {
4562                 mutex_lock(&dev->struct_mutex);
4563                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4564                 mutex_unlock(&dev->struct_mutex);
4565                 crtc->primary->fb = NULL;
4566         }
4567
4568         /* Update computed state. */
4569         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4570                 if (!connector->encoder || !connector->encoder->crtc)
4571                         continue;
4572
4573                 if (connector->encoder->crtc != crtc)
4574                         continue;
4575
4576                 connector->dpms = DRM_MODE_DPMS_OFF;
4577                 to_intel_encoder(connector->encoder)->connectors_active = false;
4578         }
4579 }
4580
4581 void intel_encoder_destroy(struct drm_encoder *encoder)
4582 {
4583         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4584
4585         drm_encoder_cleanup(encoder);
4586         kfree(intel_encoder);
4587 }
4588
4589 /* Simple dpms helper for encoders with just one connector, no cloning and only
4590  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4591  * state of the entire output pipe. */
4592 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4593 {
4594         if (mode == DRM_MODE_DPMS_ON) {
4595                 encoder->connectors_active = true;
4596
4597                 intel_crtc_update_dpms(encoder->base.crtc);
4598         } else {
4599                 encoder->connectors_active = false;
4600
4601                 intel_crtc_update_dpms(encoder->base.crtc);
4602         }
4603 }
4604
4605 /* Cross check the actual hw state with our own modeset state tracking (and it's
4606  * internal consistency). */
4607 static void intel_connector_check_state(struct intel_connector *connector)
4608 {
4609         if (connector->get_hw_state(connector)) {
4610                 struct intel_encoder *encoder = connector->encoder;
4611                 struct drm_crtc *crtc;
4612                 bool encoder_enabled;
4613                 enum pipe pipe;
4614
4615                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4616                               connector->base.base.id,
4617                               drm_get_connector_name(&connector->base));
4618
4619                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4620                      "wrong connector dpms state\n");
4621                 WARN(connector->base.encoder != &encoder->base,
4622                      "active connector not linked to encoder\n");
4623                 WARN(!encoder->connectors_active,
4624                      "encoder->connectors_active not set\n");
4625
4626                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4627                 WARN(!encoder_enabled, "encoder not enabled\n");
4628                 if (WARN_ON(!encoder->base.crtc))
4629                         return;
4630
4631                 crtc = encoder->base.crtc;
4632
4633                 WARN(!crtc->enabled, "crtc not enabled\n");
4634                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4635                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4636                      "encoder active on the wrong pipe\n");
4637         }
4638 }
4639
4640 /* Even simpler default implementation, if there's really no special case to
4641  * consider. */
4642 void intel_connector_dpms(struct drm_connector *connector, int mode)
4643 {
4644         /* All the simple cases only support two dpms states. */
4645         if (mode != DRM_MODE_DPMS_ON)
4646                 mode = DRM_MODE_DPMS_OFF;
4647
4648         if (mode == connector->dpms)
4649                 return;
4650
4651         connector->dpms = mode;
4652
4653         /* Only need to change hw state when actually enabled */
4654         if (connector->encoder)
4655                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4656
4657         intel_modeset_check_state(connector->dev);
4658 }
4659
4660 /* Simple connector->get_hw_state implementation for encoders that support only
4661  * one connector and no cloning and hence the encoder state determines the state
4662  * of the connector. */
4663 bool intel_connector_get_hw_state(struct intel_connector *connector)
4664 {
4665         enum pipe pipe = 0;
4666         struct intel_encoder *encoder = connector->encoder;
4667
4668         return encoder->get_hw_state(encoder, &pipe);
4669 }
4670
4671 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4672                                      struct intel_crtc_config *pipe_config)
4673 {
4674         struct drm_i915_private *dev_priv = dev->dev_private;
4675         struct intel_crtc *pipe_B_crtc =
4676                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4677
4678         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4679                       pipe_name(pipe), pipe_config->fdi_lanes);
4680         if (pipe_config->fdi_lanes > 4) {
4681                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4682                               pipe_name(pipe), pipe_config->fdi_lanes);
4683                 return false;
4684         }
4685
4686         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4687                 if (pipe_config->fdi_lanes > 2) {
4688                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4689                                       pipe_config->fdi_lanes);
4690                         return false;
4691                 } else {
4692                         return true;
4693                 }
4694         }
4695
4696         if (INTEL_INFO(dev)->num_pipes == 2)
4697                 return true;
4698
4699         /* Ivybridge 3 pipe is really complicated */
4700         switch (pipe) {
4701         case PIPE_A:
4702                 return true;
4703         case PIPE_B:
4704                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4705                     pipe_config->fdi_lanes > 2) {
4706                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4707                                       pipe_name(pipe), pipe_config->fdi_lanes);
4708                         return false;
4709                 }
4710                 return true;
4711         case PIPE_C:
4712                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4713                     pipe_B_crtc->config.fdi_lanes <= 2) {
4714                         if (pipe_config->fdi_lanes > 2) {
4715                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4716                                               pipe_name(pipe), pipe_config->fdi_lanes);
4717                                 return false;
4718                         }
4719                 } else {
4720                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4721                         return false;
4722                 }
4723                 return true;
4724         default:
4725                 BUG();
4726         }
4727 }
4728
4729 #define RETRY 1
4730 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4731                                        struct intel_crtc_config *pipe_config)
4732 {
4733         struct drm_device *dev = intel_crtc->base.dev;
4734         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4735         int lane, link_bw, fdi_dotclock;
4736         bool setup_ok, needs_recompute = false;
4737
4738 retry:
4739         /* FDI is a binary signal running at ~2.7GHz, encoding
4740          * each output octet as 10 bits. The actual frequency
4741          * is stored as a divider into a 100MHz clock, and the
4742          * mode pixel clock is stored in units of 1KHz.
4743          * Hence the bw of each lane in terms of the mode signal
4744          * is:
4745          */
4746         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4747
4748         fdi_dotclock = adjusted_mode->crtc_clock;
4749
4750         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4751                                            pipe_config->pipe_bpp);
4752
4753         pipe_config->fdi_lanes = lane;
4754
4755         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4756                                link_bw, &pipe_config->fdi_m_n);
4757
4758         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4759                                             intel_crtc->pipe, pipe_config);
4760         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4761                 pipe_config->pipe_bpp -= 2*3;
4762                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4763                               pipe_config->pipe_bpp);
4764                 needs_recompute = true;
4765                 pipe_config->bw_constrained = true;
4766
4767                 goto retry;
4768         }
4769
4770         if (needs_recompute)
4771                 return RETRY;
4772
4773         return setup_ok ? 0 : -EINVAL;
4774 }
4775
4776 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4777                                    struct intel_crtc_config *pipe_config)
4778 {
4779         pipe_config->ips_enabled = i915.enable_ips &&
4780                                    hsw_crtc_supports_ips(crtc) &&
4781                                    pipe_config->pipe_bpp <= 24;
4782 }
4783
4784 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4785                                      struct intel_crtc_config *pipe_config)
4786 {
4787         struct drm_device *dev = crtc->base.dev;
4788         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4789
4790         /* FIXME should check pixel clock limits on all platforms */
4791         if (INTEL_INFO(dev)->gen < 4) {
4792                 struct drm_i915_private *dev_priv = dev->dev_private;
4793                 int clock_limit =
4794                         dev_priv->display.get_display_clock_speed(dev);
4795
4796                 /*
4797                  * Enable pixel doubling when the dot clock
4798                  * is > 90% of the (display) core speed.
4799                  *
4800                  * GDG double wide on either pipe,
4801                  * otherwise pipe A only.
4802                  */
4803                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4804                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4805                         clock_limit *= 2;
4806                         pipe_config->double_wide = true;
4807                 }
4808
4809                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4810                         return -EINVAL;
4811         }
4812
4813         /*
4814          * Pipe horizontal size must be even in:
4815          * - DVO ganged mode
4816          * - LVDS dual channel mode
4817          * - Double wide pipe
4818          */
4819         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4820              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4821                 pipe_config->pipe_src_w &= ~1;
4822
4823         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4824          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4825          */
4826         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4827                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4828                 return -EINVAL;
4829
4830         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4831                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4832         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4833                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4834                  * for lvds. */
4835                 pipe_config->pipe_bpp = 8*3;
4836         }
4837
4838         if (HAS_IPS(dev))
4839                 hsw_compute_ips_config(crtc, pipe_config);
4840
4841         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4842          * clock survives for now. */
4843         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4844                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4845
4846         if (pipe_config->has_pch_encoder)
4847                 return ironlake_fdi_compute_config(crtc, pipe_config);
4848
4849         return 0;
4850 }
4851
4852 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4853 {
4854         return 400000; /* FIXME */
4855 }
4856
4857 static int i945_get_display_clock_speed(struct drm_device *dev)
4858 {
4859         return 400000;
4860 }
4861
4862 static int i915_get_display_clock_speed(struct drm_device *dev)
4863 {
4864         return 333000;
4865 }
4866
4867 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4868 {
4869         return 200000;
4870 }
4871
4872 static int pnv_get_display_clock_speed(struct drm_device *dev)
4873 {
4874         u16 gcfgc = 0;
4875
4876         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4877
4878         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4879         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4880                 return 267000;
4881         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4882                 return 333000;
4883         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4884                 return 444000;
4885         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4886                 return 200000;
4887         default:
4888                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4889         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4890                 return 133000;
4891         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4892                 return 167000;
4893         }
4894 }
4895
4896 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4897 {
4898         u16 gcfgc = 0;
4899
4900         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4901
4902         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4903                 return 133000;
4904         else {
4905                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4906                 case GC_DISPLAY_CLOCK_333_MHZ:
4907                         return 333000;
4908                 default:
4909                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4910                         return 190000;
4911                 }
4912         }
4913 }
4914
4915 static int i865_get_display_clock_speed(struct drm_device *dev)
4916 {
4917         return 266000;
4918 }
4919
4920 static int i855_get_display_clock_speed(struct drm_device *dev)
4921 {
4922         u16 hpllcc = 0;
4923         /* Assume that the hardware is in the high speed state.  This
4924          * should be the default.
4925          */
4926         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4927         case GC_CLOCK_133_200:
4928         case GC_CLOCK_100_200:
4929                 return 200000;
4930         case GC_CLOCK_166_250:
4931                 return 250000;
4932         case GC_CLOCK_100_133:
4933                 return 133000;
4934         }
4935
4936         /* Shouldn't happen */
4937         return 0;
4938 }
4939
4940 static int i830_get_display_clock_speed(struct drm_device *dev)
4941 {
4942         return 133000;
4943 }
4944
4945 static void
4946 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4947 {
4948         while (*num > DATA_LINK_M_N_MASK ||
4949                *den > DATA_LINK_M_N_MASK) {
4950                 *num >>= 1;
4951                 *den >>= 1;
4952         }
4953 }
4954
4955 static void compute_m_n(unsigned int m, unsigned int n,
4956                         uint32_t *ret_m, uint32_t *ret_n)
4957 {
4958         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4959         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4960         intel_reduce_m_n_ratio(ret_m, ret_n);
4961 }
4962
4963 void
4964 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4965                        int pixel_clock, int link_clock,
4966                        struct intel_link_m_n *m_n)
4967 {
4968         m_n->tu = 64;
4969
4970         compute_m_n(bits_per_pixel * pixel_clock,
4971                     link_clock * nlanes * 8,
4972                     &m_n->gmch_m, &m_n->gmch_n);
4973
4974         compute_m_n(pixel_clock, link_clock,
4975                     &m_n->link_m, &m_n->link_n);
4976 }
4977
4978 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4979 {
4980         if (i915.panel_use_ssc >= 0)
4981                 return i915.panel_use_ssc != 0;
4982         return dev_priv->vbt.lvds_use_ssc
4983                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4984 }
4985
4986 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4987 {
4988         struct drm_device *dev = crtc->dev;
4989         struct drm_i915_private *dev_priv = dev->dev_private;
4990         int refclk;
4991
4992         if (IS_VALLEYVIEW(dev)) {
4993                 refclk = 100000;
4994         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4995             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4996                 refclk = dev_priv->vbt.lvds_ssc_freq;
4997                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4998         } else if (!IS_GEN2(dev)) {
4999                 refclk = 96000;
5000         } else {
5001                 refclk = 48000;
5002         }
5003
5004         return refclk;
5005 }
5006
5007 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5008 {
5009         return (1 << dpll->n) << 16 | dpll->m2;
5010 }
5011
5012 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5013 {
5014         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5015 }
5016
5017 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5018                                      intel_clock_t *reduced_clock)
5019 {
5020         struct drm_device *dev = crtc->base.dev;
5021         struct drm_i915_private *dev_priv = dev->dev_private;
5022         int pipe = crtc->pipe;
5023         u32 fp, fp2 = 0;
5024
5025         if (IS_PINEVIEW(dev)) {
5026                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5027                 if (reduced_clock)
5028                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5029         } else {
5030                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5031                 if (reduced_clock)
5032                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5033         }
5034
5035         I915_WRITE(FP0(pipe), fp);
5036         crtc->config.dpll_hw_state.fp0 = fp;
5037
5038         crtc->lowfreq_avail = false;
5039         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5040             reduced_clock && i915.powersave) {
5041                 I915_WRITE(FP1(pipe), fp2);
5042                 crtc->config.dpll_hw_state.fp1 = fp2;
5043                 crtc->lowfreq_avail = true;
5044         } else {
5045                 I915_WRITE(FP1(pipe), fp);
5046                 crtc->config.dpll_hw_state.fp1 = fp;
5047         }
5048 }
5049
5050 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5051                 pipe)
5052 {
5053         u32 reg_val;
5054
5055         /*
5056          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5057          * and set it to a reasonable value instead.
5058          */
5059         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5060         reg_val &= 0xffffff00;
5061         reg_val |= 0x00000030;
5062         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5063
5064         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5065         reg_val &= 0x8cffffff;
5066         reg_val = 0x8c000000;
5067         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5068
5069         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5070         reg_val &= 0xffffff00;
5071         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5072
5073         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5074         reg_val &= 0x00ffffff;
5075         reg_val |= 0xb0000000;
5076         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5077 }
5078
5079 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5080                                          struct intel_link_m_n *m_n)
5081 {
5082         struct drm_device *dev = crtc->base.dev;
5083         struct drm_i915_private *dev_priv = dev->dev_private;
5084         int pipe = crtc->pipe;
5085
5086         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5087         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5088         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5089         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5090 }
5091
5092 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5093                                          struct intel_link_m_n *m_n)
5094 {
5095         struct drm_device *dev = crtc->base.dev;
5096         struct drm_i915_private *dev_priv = dev->dev_private;
5097         int pipe = crtc->pipe;
5098         enum transcoder transcoder = crtc->config.cpu_transcoder;
5099
5100         if (INTEL_INFO(dev)->gen >= 5) {
5101                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5102                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5103                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5104                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5105         } else {
5106                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5107                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5108                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5109                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5110         }
5111 }
5112
5113 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5114 {
5115         if (crtc->config.has_pch_encoder)
5116                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5117         else
5118                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5119 }
5120
5121 static void vlv_update_pll(struct intel_crtc *crtc)
5122 {
5123         struct drm_device *dev = crtc->base.dev;
5124         struct drm_i915_private *dev_priv = dev->dev_private;
5125         int pipe = crtc->pipe;
5126         u32 dpll, mdiv;
5127         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5128         u32 coreclk, reg_val, dpll_md;
5129
5130         mutex_lock(&dev_priv->dpio_lock);
5131
5132         bestn = crtc->config.dpll.n;
5133         bestm1 = crtc->config.dpll.m1;
5134         bestm2 = crtc->config.dpll.m2;
5135         bestp1 = crtc->config.dpll.p1;
5136         bestp2 = crtc->config.dpll.p2;
5137
5138         /* See eDP HDMI DPIO driver vbios notes doc */
5139
5140         /* PLL B needs special handling */
5141         if (pipe)
5142                 vlv_pllb_recal_opamp(dev_priv, pipe);
5143
5144         /* Set up Tx target for periodic Rcomp update */
5145         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5146
5147         /* Disable target IRef on PLL */
5148         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5149         reg_val &= 0x00ffffff;
5150         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5151
5152         /* Disable fast lock */
5153         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5154
5155         /* Set idtafcrecal before PLL is enabled */
5156         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5157         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5158         mdiv |= ((bestn << DPIO_N_SHIFT));
5159         mdiv |= (1 << DPIO_K_SHIFT);
5160
5161         /*
5162          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5163          * but we don't support that).
5164          * Note: don't use the DAC post divider as it seems unstable.
5165          */
5166         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5167         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5168
5169         mdiv |= DPIO_ENABLE_CALIBRATION;
5170         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5171
5172         /* Set HBR and RBR LPF coefficients */
5173         if (crtc->config.port_clock == 162000 ||
5174             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5175             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5176                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5177                                  0x009f0003);
5178         else
5179                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5180                                  0x00d0000f);
5181
5182         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5183             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5184                 /* Use SSC source */
5185                 if (!pipe)
5186                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5187                                          0x0df40000);
5188                 else
5189                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5190                                          0x0df70000);
5191         } else { /* HDMI or VGA */
5192                 /* Use bend source */
5193                 if (!pipe)
5194                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5195                                          0x0df70000);
5196                 else
5197                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5198                                          0x0df40000);
5199         }
5200
5201         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5202         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5203         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5204             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5205                 coreclk |= 0x01000000;
5206         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5207
5208         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5209
5210         /*
5211          * Enable DPIO clock input. We should never disable the reference
5212          * clock for pipe B, since VGA hotplug / manual detection depends
5213          * on it.
5214          */
5215         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5216                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5217         /* We should never disable this, set it here for state tracking */
5218         if (pipe == PIPE_B)
5219                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5220         dpll |= DPLL_VCO_ENABLE;
5221         crtc->config.dpll_hw_state.dpll = dpll;
5222
5223         dpll_md = (crtc->config.pixel_multiplier - 1)
5224                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5225         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5226
5227         mutex_unlock(&dev_priv->dpio_lock);
5228 }
5229
5230 static void i9xx_update_pll(struct intel_crtc *crtc,
5231                             intel_clock_t *reduced_clock,
5232                             int num_connectors)
5233 {
5234         struct drm_device *dev = crtc->base.dev;
5235         struct drm_i915_private *dev_priv = dev->dev_private;
5236         u32 dpll;
5237         bool is_sdvo;
5238         struct dpll *clock = &crtc->config.dpll;
5239
5240         i9xx_update_pll_dividers(crtc, reduced_clock);
5241
5242         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5243                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5244
5245         dpll = DPLL_VGA_MODE_DIS;
5246
5247         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5248                 dpll |= DPLLB_MODE_LVDS;
5249         else
5250                 dpll |= DPLLB_MODE_DAC_SERIAL;
5251
5252         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5253                 dpll |= (crtc->config.pixel_multiplier - 1)
5254                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5255         }
5256
5257         if (is_sdvo)
5258                 dpll |= DPLL_SDVO_HIGH_SPEED;
5259
5260         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5261                 dpll |= DPLL_SDVO_HIGH_SPEED;
5262
5263         /* compute bitmask from p1 value */
5264         if (IS_PINEVIEW(dev))
5265                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5266         else {
5267                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5268                 if (IS_G4X(dev) && reduced_clock)
5269                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5270         }
5271         switch (clock->p2) {
5272         case 5:
5273                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5274                 break;
5275         case 7:
5276                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5277                 break;
5278         case 10:
5279                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5280                 break;
5281         case 14:
5282                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5283                 break;
5284         }
5285         if (INTEL_INFO(dev)->gen >= 4)
5286                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5287
5288         if (crtc->config.sdvo_tv_clock)
5289                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5290         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5291                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5292                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5293         else
5294                 dpll |= PLL_REF_INPUT_DREFCLK;
5295
5296         dpll |= DPLL_VCO_ENABLE;
5297         crtc->config.dpll_hw_state.dpll = dpll;
5298
5299         if (INTEL_INFO(dev)->gen >= 4) {
5300                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5301                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5302                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5303         }
5304 }
5305
5306 static void i8xx_update_pll(struct intel_crtc *crtc,
5307                             intel_clock_t *reduced_clock,
5308                             int num_connectors)
5309 {
5310         struct drm_device *dev = crtc->base.dev;
5311         struct drm_i915_private *dev_priv = dev->dev_private;
5312         u32 dpll;
5313         struct dpll *clock = &crtc->config.dpll;
5314
5315         i9xx_update_pll_dividers(crtc, reduced_clock);
5316
5317         dpll = DPLL_VGA_MODE_DIS;
5318
5319         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5320                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5321         } else {
5322                 if (clock->p1 == 2)
5323                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5324                 else
5325                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5326                 if (clock->p2 == 4)
5327                         dpll |= PLL_P2_DIVIDE_BY_4;
5328         }
5329
5330         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5331                 dpll |= DPLL_DVO_2X_MODE;
5332
5333         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5334                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5335                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5336         else
5337                 dpll |= PLL_REF_INPUT_DREFCLK;
5338
5339         dpll |= DPLL_VCO_ENABLE;
5340         crtc->config.dpll_hw_state.dpll = dpll;
5341 }
5342
5343 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5344 {
5345         struct drm_device *dev = intel_crtc->base.dev;
5346         struct drm_i915_private *dev_priv = dev->dev_private;
5347         enum pipe pipe = intel_crtc->pipe;
5348         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5349         struct drm_display_mode *adjusted_mode =
5350                 &intel_crtc->config.adjusted_mode;
5351         uint32_t crtc_vtotal, crtc_vblank_end;
5352         int vsyncshift = 0;
5353
5354         /* We need to be careful not to changed the adjusted mode, for otherwise
5355          * the hw state checker will get angry at the mismatch. */
5356         crtc_vtotal = adjusted_mode->crtc_vtotal;
5357         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5358
5359         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5360                 /* the chip adds 2 halflines automatically */
5361                 crtc_vtotal -= 1;
5362                 crtc_vblank_end -= 1;
5363
5364                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5365                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5366                 else
5367                         vsyncshift = adjusted_mode->crtc_hsync_start -
5368                                 adjusted_mode->crtc_htotal / 2;
5369                 if (vsyncshift < 0)
5370                         vsyncshift += adjusted_mode->crtc_htotal;
5371         }
5372
5373         if (INTEL_INFO(dev)->gen > 3)
5374                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5375
5376         I915_WRITE(HTOTAL(cpu_transcoder),
5377                    (adjusted_mode->crtc_hdisplay - 1) |
5378                    ((adjusted_mode->crtc_htotal - 1) << 16));
5379         I915_WRITE(HBLANK(cpu_transcoder),
5380                    (adjusted_mode->crtc_hblank_start - 1) |
5381                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5382         I915_WRITE(HSYNC(cpu_transcoder),
5383                    (adjusted_mode->crtc_hsync_start - 1) |
5384                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5385
5386         I915_WRITE(VTOTAL(cpu_transcoder),
5387                    (adjusted_mode->crtc_vdisplay - 1) |
5388                    ((crtc_vtotal - 1) << 16));
5389         I915_WRITE(VBLANK(cpu_transcoder),
5390                    (adjusted_mode->crtc_vblank_start - 1) |
5391                    ((crtc_vblank_end - 1) << 16));
5392         I915_WRITE(VSYNC(cpu_transcoder),
5393                    (adjusted_mode->crtc_vsync_start - 1) |
5394                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5395
5396         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5397          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5398          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5399          * bits. */
5400         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5401             (pipe == PIPE_B || pipe == PIPE_C))
5402                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5403
5404         /* pipesrc controls the size that is scaled from, which should
5405          * always be the user's requested size.
5406          */
5407         I915_WRITE(PIPESRC(pipe),
5408                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5409                    (intel_crtc->config.pipe_src_h - 1));
5410 }
5411
5412 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5413                                    struct intel_crtc_config *pipe_config)
5414 {
5415         struct drm_device *dev = crtc->base.dev;
5416         struct drm_i915_private *dev_priv = dev->dev_private;
5417         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5418         uint32_t tmp;
5419
5420         tmp = I915_READ(HTOTAL(cpu_transcoder));
5421         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5422         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5423         tmp = I915_READ(HBLANK(cpu_transcoder));
5424         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5425         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5426         tmp = I915_READ(HSYNC(cpu_transcoder));
5427         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5428         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5429
5430         tmp = I915_READ(VTOTAL(cpu_transcoder));
5431         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5432         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5433         tmp = I915_READ(VBLANK(cpu_transcoder));
5434         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5435         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5436         tmp = I915_READ(VSYNC(cpu_transcoder));
5437         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5438         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5439
5440         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5441                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5442                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5443                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5444         }
5445
5446         tmp = I915_READ(PIPESRC(crtc->pipe));
5447         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5448         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5449
5450         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5451         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5452 }
5453
5454 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5455                                  struct intel_crtc_config *pipe_config)
5456 {
5457         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5458         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5459         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5460         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5461
5462         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5463         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5464         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5465         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5466
5467         mode->flags = pipe_config->adjusted_mode.flags;
5468
5469         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5470         mode->flags |= pipe_config->adjusted_mode.flags;
5471 }
5472
5473 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5474 {
5475         struct drm_device *dev = intel_crtc->base.dev;
5476         struct drm_i915_private *dev_priv = dev->dev_private;
5477         uint32_t pipeconf;
5478
5479         pipeconf = 0;
5480
5481         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5482             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5483                 pipeconf |= PIPECONF_ENABLE;
5484
5485         if (intel_crtc->config.double_wide)
5486                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5487
5488         /* only g4x and later have fancy bpc/dither controls */
5489         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5490                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5491                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5492                         pipeconf |= PIPECONF_DITHER_EN |
5493                                     PIPECONF_DITHER_TYPE_SP;
5494
5495                 switch (intel_crtc->config.pipe_bpp) {
5496                 case 18:
5497                         pipeconf |= PIPECONF_6BPC;
5498                         break;
5499                 case 24:
5500                         pipeconf |= PIPECONF_8BPC;
5501                         break;
5502                 case 30:
5503                         pipeconf |= PIPECONF_10BPC;
5504                         break;
5505                 default:
5506                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5507                         BUG();
5508                 }
5509         }
5510
5511         if (HAS_PIPE_CXSR(dev)) {
5512                 if (intel_crtc->lowfreq_avail) {
5513                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5514                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5515                 } else {
5516                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5517                 }
5518         }
5519
5520         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5521                 if (INTEL_INFO(dev)->gen < 4 ||
5522                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5523                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5524                 else
5525                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5526         } else
5527                 pipeconf |= PIPECONF_PROGRESSIVE;
5528
5529         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5530                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5531
5532         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5533         POSTING_READ(PIPECONF(intel_crtc->pipe));
5534 }
5535
5536 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5537                               int x, int y,
5538                               struct drm_framebuffer *fb)
5539 {
5540         struct drm_device *dev = crtc->dev;
5541         struct drm_i915_private *dev_priv = dev->dev_private;
5542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5543         int pipe = intel_crtc->pipe;
5544         int plane = intel_crtc->plane;
5545         int refclk, num_connectors = 0;
5546         intel_clock_t clock, reduced_clock;
5547         u32 dspcntr;
5548         bool ok, has_reduced_clock = false;
5549         bool is_lvds = false, is_dsi = false;
5550         struct intel_encoder *encoder;
5551         const intel_limit_t *limit;
5552         int ret;
5553
5554         for_each_encoder_on_crtc(dev, crtc, encoder) {
5555                 switch (encoder->type) {
5556                 case INTEL_OUTPUT_LVDS:
5557                         is_lvds = true;
5558                         break;
5559                 case INTEL_OUTPUT_DSI:
5560                         is_dsi = true;
5561                         break;
5562                 }
5563
5564                 num_connectors++;
5565         }
5566
5567         if (is_dsi)
5568                 goto skip_dpll;
5569
5570         if (!intel_crtc->config.clock_set) {
5571                 refclk = i9xx_get_refclk(crtc, num_connectors);
5572
5573                 /*
5574                  * Returns a set of divisors for the desired target clock with
5575                  * the given refclk, or FALSE.  The returned values represent
5576                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5577                  * 2) / p1 / p2.
5578                  */
5579                 limit = intel_limit(crtc, refclk);
5580                 ok = dev_priv->display.find_dpll(limit, crtc,
5581                                                  intel_crtc->config.port_clock,
5582                                                  refclk, NULL, &clock);
5583                 if (!ok) {
5584                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5585                         return -EINVAL;
5586                 }
5587
5588                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5589                         /*
5590                          * Ensure we match the reduced clock's P to the target
5591                          * clock.  If the clocks don't match, we can't switch
5592                          * the display clock by using the FP0/FP1. In such case
5593                          * we will disable the LVDS downclock feature.
5594                          */
5595                         has_reduced_clock =
5596                                 dev_priv->display.find_dpll(limit, crtc,
5597                                                             dev_priv->lvds_downclock,
5598                                                             refclk, &clock,
5599                                                             &reduced_clock);
5600                 }
5601                 /* Compat-code for transition, will disappear. */
5602                 intel_crtc->config.dpll.n = clock.n;
5603                 intel_crtc->config.dpll.m1 = clock.m1;
5604                 intel_crtc->config.dpll.m2 = clock.m2;
5605                 intel_crtc->config.dpll.p1 = clock.p1;
5606                 intel_crtc->config.dpll.p2 = clock.p2;
5607         }
5608
5609         if (IS_GEN2(dev)) {
5610                 i8xx_update_pll(intel_crtc,
5611                                 has_reduced_clock ? &reduced_clock : NULL,
5612                                 num_connectors);
5613         } else if (IS_VALLEYVIEW(dev)) {
5614                 vlv_update_pll(intel_crtc);
5615         } else {
5616                 i9xx_update_pll(intel_crtc,
5617                                 has_reduced_clock ? &reduced_clock : NULL,
5618                                 num_connectors);
5619         }
5620
5621 skip_dpll:
5622         /* Set up the display plane register */
5623         dspcntr = DISPPLANE_GAMMA_ENABLE;
5624
5625         if (!IS_VALLEYVIEW(dev)) {
5626                 if (pipe == 0)
5627                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5628                 else
5629                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5630         }
5631
5632         if (intel_crtc->config.has_dp_encoder)
5633                 intel_dp_set_m_n(intel_crtc);
5634
5635         intel_set_pipe_timings(intel_crtc);
5636
5637         /* pipesrc and dspsize control the size that is scaled from,
5638          * which should always be the user's requested size.
5639          */
5640         I915_WRITE(DSPSIZE(plane),
5641                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5642                    (intel_crtc->config.pipe_src_w - 1));
5643         I915_WRITE(DSPPOS(plane), 0);
5644
5645         i9xx_set_pipeconf(intel_crtc);
5646
5647         I915_WRITE(DSPCNTR(plane), dspcntr);
5648         POSTING_READ(DSPCNTR(plane));
5649
5650         ret = intel_pipe_set_base(crtc, x, y, fb);
5651
5652         return ret;
5653 }
5654
5655 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5656                                  struct intel_crtc_config *pipe_config)
5657 {
5658         struct drm_device *dev = crtc->base.dev;
5659         struct drm_i915_private *dev_priv = dev->dev_private;
5660         uint32_t tmp;
5661
5662         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5663                 return;
5664
5665         tmp = I915_READ(PFIT_CONTROL);
5666         if (!(tmp & PFIT_ENABLE))
5667                 return;
5668
5669         /* Check whether the pfit is attached to our pipe. */
5670         if (INTEL_INFO(dev)->gen < 4) {
5671                 if (crtc->pipe != PIPE_B)
5672                         return;
5673         } else {
5674                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5675                         return;
5676         }
5677
5678         pipe_config->gmch_pfit.control = tmp;
5679         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5680         if (INTEL_INFO(dev)->gen < 5)
5681                 pipe_config->gmch_pfit.lvds_border_bits =
5682                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5683 }
5684
5685 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5686                                struct intel_crtc_config *pipe_config)
5687 {
5688         struct drm_device *dev = crtc->base.dev;
5689         struct drm_i915_private *dev_priv = dev->dev_private;
5690         int pipe = pipe_config->cpu_transcoder;
5691         intel_clock_t clock;
5692         u32 mdiv;
5693         int refclk = 100000;
5694
5695         mutex_lock(&dev_priv->dpio_lock);
5696         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5697         mutex_unlock(&dev_priv->dpio_lock);
5698
5699         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5700         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5701         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5702         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5703         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5704
5705         vlv_clock(refclk, &clock);
5706
5707         /* clock.dot is the fast clock */
5708         pipe_config->port_clock = clock.dot / 5;
5709 }
5710
5711 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5712                                   struct intel_plane_config *plane_config)
5713 {
5714         struct drm_device *dev = crtc->base.dev;
5715         struct drm_i915_private *dev_priv = dev->dev_private;
5716         u32 val, base, offset;
5717         int pipe = crtc->pipe, plane = crtc->plane;
5718         int fourcc, pixel_format;
5719         int aligned_height;
5720
5721         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5722         if (!crtc->base.primary->fb) {
5723                 DRM_DEBUG_KMS("failed to alloc fb\n");
5724                 return;
5725         }
5726
5727         val = I915_READ(DSPCNTR(plane));
5728
5729         if (INTEL_INFO(dev)->gen >= 4)
5730                 if (val & DISPPLANE_TILED)
5731                         plane_config->tiled = true;
5732
5733         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5734         fourcc = intel_format_to_fourcc(pixel_format);
5735         crtc->base.primary->fb->pixel_format = fourcc;
5736         crtc->base.primary->fb->bits_per_pixel =
5737                 drm_format_plane_cpp(fourcc, 0) * 8;
5738
5739         if (INTEL_INFO(dev)->gen >= 4) {
5740                 if (plane_config->tiled)
5741                         offset = I915_READ(DSPTILEOFF(plane));
5742                 else
5743                         offset = I915_READ(DSPLINOFF(plane));
5744                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5745         } else {
5746                 base = I915_READ(DSPADDR(plane));
5747         }
5748         plane_config->base = base;
5749
5750         val = I915_READ(PIPESRC(pipe));
5751         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5752         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5753
5754         val = I915_READ(DSPSTRIDE(pipe));
5755         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5756
5757         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5758                                             plane_config->tiled);
5759
5760         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5761                                    aligned_height, PAGE_SIZE);
5762
5763         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5764                       pipe, plane, crtc->base.primary->fb->width,
5765                       crtc->base.primary->fb->height,
5766                       crtc->base.primary->fb->bits_per_pixel, base,
5767                       crtc->base.primary->fb->pitches[0],
5768                       plane_config->size);
5769
5770 }
5771
5772 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5773                                  struct intel_crtc_config *pipe_config)
5774 {
5775         struct drm_device *dev = crtc->base.dev;
5776         struct drm_i915_private *dev_priv = dev->dev_private;
5777         uint32_t tmp;
5778
5779         if (!intel_display_power_enabled(dev_priv,
5780                                          POWER_DOMAIN_PIPE(crtc->pipe)))
5781                 return false;
5782
5783         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5784         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5785
5786         tmp = I915_READ(PIPECONF(crtc->pipe));
5787         if (!(tmp & PIPECONF_ENABLE))
5788                 return false;
5789
5790         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5791                 switch (tmp & PIPECONF_BPC_MASK) {
5792                 case PIPECONF_6BPC:
5793                         pipe_config->pipe_bpp = 18;
5794                         break;
5795                 case PIPECONF_8BPC:
5796                         pipe_config->pipe_bpp = 24;
5797                         break;
5798                 case PIPECONF_10BPC:
5799                         pipe_config->pipe_bpp = 30;
5800                         break;
5801                 default:
5802                         break;
5803                 }
5804         }
5805
5806         if (INTEL_INFO(dev)->gen < 4)
5807                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5808
5809         intel_get_pipe_timings(crtc, pipe_config);
5810
5811         i9xx_get_pfit_config(crtc, pipe_config);
5812
5813         if (INTEL_INFO(dev)->gen >= 4) {
5814                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5815                 pipe_config->pixel_multiplier =
5816                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5817                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5818                 pipe_config->dpll_hw_state.dpll_md = tmp;
5819         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5820                 tmp = I915_READ(DPLL(crtc->pipe));
5821                 pipe_config->pixel_multiplier =
5822                         ((tmp & SDVO_MULTIPLIER_MASK)
5823                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5824         } else {
5825                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5826                  * port and will be fixed up in the encoder->get_config
5827                  * function. */
5828                 pipe_config->pixel_multiplier = 1;
5829         }
5830         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5831         if (!IS_VALLEYVIEW(dev)) {
5832                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5833                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5834         } else {
5835                 /* Mask out read-only status bits. */
5836                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5837                                                      DPLL_PORTC_READY_MASK |
5838                                                      DPLL_PORTB_READY_MASK);
5839         }
5840
5841         if (IS_VALLEYVIEW(dev))
5842                 vlv_crtc_clock_get(crtc, pipe_config);
5843         else
5844                 i9xx_crtc_clock_get(crtc, pipe_config);
5845
5846         return true;
5847 }
5848
5849 static void ironlake_init_pch_refclk(struct drm_device *dev)
5850 {
5851         struct drm_i915_private *dev_priv = dev->dev_private;
5852         struct drm_mode_config *mode_config = &dev->mode_config;
5853         struct intel_encoder *encoder;
5854         u32 val, final;
5855         bool has_lvds = false;
5856         bool has_cpu_edp = false;
5857         bool has_panel = false;
5858         bool has_ck505 = false;
5859         bool can_ssc = false;
5860
5861         /* We need to take the global config into account */
5862         list_for_each_entry(encoder, &mode_config->encoder_list,
5863                             base.head) {
5864                 switch (encoder->type) {
5865                 case INTEL_OUTPUT_LVDS:
5866                         has_panel = true;
5867                         has_lvds = true;
5868                         break;
5869                 case INTEL_OUTPUT_EDP:
5870                         has_panel = true;
5871                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5872                                 has_cpu_edp = true;
5873                         break;
5874                 }
5875         }
5876
5877         if (HAS_PCH_IBX(dev)) {
5878                 has_ck505 = dev_priv->vbt.display_clock_mode;
5879                 can_ssc = has_ck505;
5880         } else {
5881                 has_ck505 = false;
5882                 can_ssc = true;
5883         }
5884
5885         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5886                       has_panel, has_lvds, has_ck505);
5887
5888         /* Ironlake: try to setup display ref clock before DPLL
5889          * enabling. This is only under driver's control after
5890          * PCH B stepping, previous chipset stepping should be
5891          * ignoring this setting.
5892          */
5893         val = I915_READ(PCH_DREF_CONTROL);
5894
5895         /* As we must carefully and slowly disable/enable each source in turn,
5896          * compute the final state we want first and check if we need to
5897          * make any changes at all.
5898          */
5899         final = val;
5900         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5901         if (has_ck505)
5902                 final |= DREF_NONSPREAD_CK505_ENABLE;
5903         else
5904                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5905
5906         final &= ~DREF_SSC_SOURCE_MASK;
5907         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5908         final &= ~DREF_SSC1_ENABLE;
5909
5910         if (has_panel) {
5911                 final |= DREF_SSC_SOURCE_ENABLE;
5912
5913                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5914                         final |= DREF_SSC1_ENABLE;
5915
5916                 if (has_cpu_edp) {
5917                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5918                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5919                         else
5920                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5921                 } else
5922                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5923         } else {
5924                 final |= DREF_SSC_SOURCE_DISABLE;
5925                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5926         }
5927
5928         if (final == val)
5929                 return;
5930
5931         /* Always enable nonspread source */
5932         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5933
5934         if (has_ck505)
5935                 val |= DREF_NONSPREAD_CK505_ENABLE;
5936         else
5937                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5938
5939         if (has_panel) {
5940                 val &= ~DREF_SSC_SOURCE_MASK;
5941                 val |= DREF_SSC_SOURCE_ENABLE;
5942
5943                 /* SSC must be turned on before enabling the CPU output  */
5944                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5945                         DRM_DEBUG_KMS("Using SSC on panel\n");
5946                         val |= DREF_SSC1_ENABLE;
5947                 } else
5948                         val &= ~DREF_SSC1_ENABLE;
5949
5950                 /* Get SSC going before enabling the outputs */
5951                 I915_WRITE(PCH_DREF_CONTROL, val);
5952                 POSTING_READ(PCH_DREF_CONTROL);
5953                 udelay(200);
5954
5955                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5956
5957                 /* Enable CPU source on CPU attached eDP */
5958                 if (has_cpu_edp) {
5959                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5960                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5961                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5962                         }
5963                         else
5964                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5965                 } else
5966                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5967
5968                 I915_WRITE(PCH_DREF_CONTROL, val);
5969                 POSTING_READ(PCH_DREF_CONTROL);
5970                 udelay(200);
5971         } else {
5972                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5973
5974                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5975
5976                 /* Turn off CPU output */
5977                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5978
5979                 I915_WRITE(PCH_DREF_CONTROL, val);
5980                 POSTING_READ(PCH_DREF_CONTROL);
5981                 udelay(200);
5982
5983                 /* Turn off the SSC source */
5984                 val &= ~DREF_SSC_SOURCE_MASK;
5985                 val |= DREF_SSC_SOURCE_DISABLE;
5986
5987                 /* Turn off SSC1 */
5988                 val &= ~DREF_SSC1_ENABLE;
5989
5990                 I915_WRITE(PCH_DREF_CONTROL, val);
5991                 POSTING_READ(PCH_DREF_CONTROL);
5992                 udelay(200);
5993         }
5994
5995         BUG_ON(val != final);
5996 }
5997
5998 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5999 {
6000         uint32_t tmp;
6001
6002         tmp = I915_READ(SOUTH_CHICKEN2);
6003         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6004         I915_WRITE(SOUTH_CHICKEN2, tmp);
6005
6006         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6007                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6008                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6009
6010         tmp = I915_READ(SOUTH_CHICKEN2);
6011         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6012         I915_WRITE(SOUTH_CHICKEN2, tmp);
6013
6014         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6015                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6016                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6017 }
6018
6019 /* WaMPhyProgramming:hsw */
6020 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6021 {
6022         uint32_t tmp;
6023
6024         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6025         tmp &= ~(0xFF << 24);
6026         tmp |= (0x12 << 24);
6027         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6028
6029         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6030         tmp |= (1 << 11);
6031         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6032
6033         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6034         tmp |= (1 << 11);
6035         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6036
6037         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6038         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6039         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6040
6041         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6042         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6043         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6044
6045         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6046         tmp &= ~(7 << 13);
6047         tmp |= (5 << 13);
6048         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6049
6050         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6051         tmp &= ~(7 << 13);
6052         tmp |= (5 << 13);
6053         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6054
6055         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6056         tmp &= ~0xFF;
6057         tmp |= 0x1C;
6058         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6059
6060         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6061         tmp &= ~0xFF;
6062         tmp |= 0x1C;
6063         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6064
6065         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6066         tmp &= ~(0xFF << 16);
6067         tmp |= (0x1C << 16);
6068         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6069
6070         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6071         tmp &= ~(0xFF << 16);
6072         tmp |= (0x1C << 16);
6073         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6074
6075         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6076         tmp |= (1 << 27);
6077         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6078
6079         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6080         tmp |= (1 << 27);
6081         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6082
6083         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6084         tmp &= ~(0xF << 28);
6085         tmp |= (4 << 28);
6086         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6087
6088         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6089         tmp &= ~(0xF << 28);
6090         tmp |= (4 << 28);
6091         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6092 }
6093
6094 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6095  * Programming" based on the parameters passed:
6096  * - Sequence to enable CLKOUT_DP
6097  * - Sequence to enable CLKOUT_DP without spread
6098  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6099  */
6100 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6101                                  bool with_fdi)
6102 {
6103         struct drm_i915_private *dev_priv = dev->dev_private;
6104         uint32_t reg, tmp;
6105
6106         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6107                 with_spread = true;
6108         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6109                  with_fdi, "LP PCH doesn't have FDI\n"))
6110                 with_fdi = false;
6111
6112         mutex_lock(&dev_priv->dpio_lock);
6113
6114         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6115         tmp &= ~SBI_SSCCTL_DISABLE;
6116         tmp |= SBI_SSCCTL_PATHALT;
6117         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6118
6119         udelay(24);
6120
6121         if (with_spread) {
6122                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6123                 tmp &= ~SBI_SSCCTL_PATHALT;
6124                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6125
6126                 if (with_fdi) {
6127                         lpt_reset_fdi_mphy(dev_priv);
6128                         lpt_program_fdi_mphy(dev_priv);
6129                 }
6130         }
6131
6132         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6133                SBI_GEN0 : SBI_DBUFF0;
6134         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6135         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6136         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6137
6138         mutex_unlock(&dev_priv->dpio_lock);
6139 }
6140
6141 /* Sequence to disable CLKOUT_DP */
6142 static void lpt_disable_clkout_dp(struct drm_device *dev)
6143 {
6144         struct drm_i915_private *dev_priv = dev->dev_private;
6145         uint32_t reg, tmp;
6146
6147         mutex_lock(&dev_priv->dpio_lock);
6148
6149         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6150                SBI_GEN0 : SBI_DBUFF0;
6151         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6152         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6153         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6154
6155         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6156         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6157                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6158                         tmp |= SBI_SSCCTL_PATHALT;
6159                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6160                         udelay(32);
6161                 }
6162                 tmp |= SBI_SSCCTL_DISABLE;
6163                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6164         }
6165
6166         mutex_unlock(&dev_priv->dpio_lock);
6167 }
6168
6169 static void lpt_init_pch_refclk(struct drm_device *dev)
6170 {
6171         struct drm_mode_config *mode_config = &dev->mode_config;
6172         struct intel_encoder *encoder;
6173         bool has_vga = false;
6174
6175         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6176                 switch (encoder->type) {
6177                 case INTEL_OUTPUT_ANALOG:
6178                         has_vga = true;
6179                         break;
6180                 }
6181         }
6182
6183         if (has_vga)
6184                 lpt_enable_clkout_dp(dev, true, true);
6185         else
6186                 lpt_disable_clkout_dp(dev);
6187 }
6188
6189 /*
6190  * Initialize reference clocks when the driver loads
6191  */
6192 void intel_init_pch_refclk(struct drm_device *dev)
6193 {
6194         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6195                 ironlake_init_pch_refclk(dev);
6196         else if (HAS_PCH_LPT(dev))
6197                 lpt_init_pch_refclk(dev);
6198 }
6199
6200 static int ironlake_get_refclk(struct drm_crtc *crtc)
6201 {
6202         struct drm_device *dev = crtc->dev;
6203         struct drm_i915_private *dev_priv = dev->dev_private;
6204         struct intel_encoder *encoder;
6205         int num_connectors = 0;
6206         bool is_lvds = false;
6207
6208         for_each_encoder_on_crtc(dev, crtc, encoder) {
6209                 switch (encoder->type) {
6210                 case INTEL_OUTPUT_LVDS:
6211                         is_lvds = true;
6212                         break;
6213                 }
6214                 num_connectors++;
6215         }
6216
6217         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6218                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6219                               dev_priv->vbt.lvds_ssc_freq);
6220                 return dev_priv->vbt.lvds_ssc_freq;
6221         }
6222
6223         return 120000;
6224 }
6225
6226 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6227 {
6228         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6230         int pipe = intel_crtc->pipe;
6231         uint32_t val;
6232
6233         val = 0;
6234
6235         switch (intel_crtc->config.pipe_bpp) {
6236         case 18:
6237                 val |= PIPECONF_6BPC;
6238                 break;
6239         case 24:
6240                 val |= PIPECONF_8BPC;
6241                 break;
6242         case 30:
6243                 val |= PIPECONF_10BPC;
6244                 break;
6245         case 36:
6246                 val |= PIPECONF_12BPC;
6247                 break;
6248         default:
6249                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6250                 BUG();
6251         }
6252
6253         if (intel_crtc->config.dither)
6254                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6255
6256         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6257                 val |= PIPECONF_INTERLACED_ILK;
6258         else
6259                 val |= PIPECONF_PROGRESSIVE;
6260
6261         if (intel_crtc->config.limited_color_range)
6262                 val |= PIPECONF_COLOR_RANGE_SELECT;
6263
6264         I915_WRITE(PIPECONF(pipe), val);
6265         POSTING_READ(PIPECONF(pipe));
6266 }
6267
6268 /*
6269  * Set up the pipe CSC unit.
6270  *
6271  * Currently only full range RGB to limited range RGB conversion
6272  * is supported, but eventually this should handle various
6273  * RGB<->YCbCr scenarios as well.
6274  */
6275 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6276 {
6277         struct drm_device *dev = crtc->dev;
6278         struct drm_i915_private *dev_priv = dev->dev_private;
6279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6280         int pipe = intel_crtc->pipe;
6281         uint16_t coeff = 0x7800; /* 1.0 */
6282
6283         /*
6284          * TODO: Check what kind of values actually come out of the pipe
6285          * with these coeff/postoff values and adjust to get the best
6286          * accuracy. Perhaps we even need to take the bpc value into
6287          * consideration.
6288          */
6289
6290         if (intel_crtc->config.limited_color_range)
6291                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6292
6293         /*
6294          * GY/GU and RY/RU should be the other way around according
6295          * to BSpec, but reality doesn't agree. Just set them up in
6296          * a way that results in the correct picture.
6297          */
6298         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6299         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6300
6301         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6302         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6303
6304         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6305         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6306
6307         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6308         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6309         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6310
6311         if (INTEL_INFO(dev)->gen > 6) {
6312                 uint16_t postoff = 0;
6313
6314                 if (intel_crtc->config.limited_color_range)
6315                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6316
6317                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6318                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6319                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6320
6321                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6322         } else {
6323                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6324
6325                 if (intel_crtc->config.limited_color_range)
6326                         mode |= CSC_BLACK_SCREEN_OFFSET;
6327
6328                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6329         }
6330 }
6331
6332 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6333 {
6334         struct drm_device *dev = crtc->dev;
6335         struct drm_i915_private *dev_priv = dev->dev_private;
6336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6337         enum pipe pipe = intel_crtc->pipe;
6338         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6339         uint32_t val;
6340
6341         val = 0;
6342
6343         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6344                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6345
6346         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6347                 val |= PIPECONF_INTERLACED_ILK;
6348         else
6349                 val |= PIPECONF_PROGRESSIVE;
6350
6351         I915_WRITE(PIPECONF(cpu_transcoder), val);
6352         POSTING_READ(PIPECONF(cpu_transcoder));
6353
6354         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6355         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6356
6357         if (IS_BROADWELL(dev)) {
6358                 val = 0;
6359
6360                 switch (intel_crtc->config.pipe_bpp) {
6361                 case 18:
6362                         val |= PIPEMISC_DITHER_6_BPC;
6363                         break;
6364                 case 24:
6365                         val |= PIPEMISC_DITHER_8_BPC;
6366                         break;
6367                 case 30:
6368                         val |= PIPEMISC_DITHER_10_BPC;
6369                         break;
6370                 case 36:
6371                         val |= PIPEMISC_DITHER_12_BPC;
6372                         break;
6373                 default:
6374                         /* Case prevented by pipe_config_set_bpp. */
6375                         BUG();
6376                 }
6377
6378                 if (intel_crtc->config.dither)
6379                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6380
6381                 I915_WRITE(PIPEMISC(pipe), val);
6382         }
6383 }
6384
6385 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6386                                     intel_clock_t *clock,
6387                                     bool *has_reduced_clock,
6388                                     intel_clock_t *reduced_clock)
6389 {
6390         struct drm_device *dev = crtc->dev;
6391         struct drm_i915_private *dev_priv = dev->dev_private;
6392         struct intel_encoder *intel_encoder;
6393         int refclk;
6394         const intel_limit_t *limit;
6395         bool ret, is_lvds = false;
6396
6397         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6398                 switch (intel_encoder->type) {
6399                 case INTEL_OUTPUT_LVDS:
6400                         is_lvds = true;
6401                         break;
6402                 }
6403         }
6404
6405         refclk = ironlake_get_refclk(crtc);
6406
6407         /*
6408          * Returns a set of divisors for the desired target clock with the given
6409          * refclk, or FALSE.  The returned values represent the clock equation:
6410          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6411          */
6412         limit = intel_limit(crtc, refclk);
6413         ret = dev_priv->display.find_dpll(limit, crtc,
6414                                           to_intel_crtc(crtc)->config.port_clock,
6415                                           refclk, NULL, clock);
6416         if (!ret)
6417                 return false;
6418
6419         if (is_lvds && dev_priv->lvds_downclock_avail) {
6420                 /*
6421                  * Ensure we match the reduced clock's P to the target clock.
6422                  * If the clocks don't match, we can't switch the display clock
6423                  * by using the FP0/FP1. In such case we will disable the LVDS
6424                  * downclock feature.
6425                 */
6426                 *has_reduced_clock =
6427                         dev_priv->display.find_dpll(limit, crtc,
6428                                                     dev_priv->lvds_downclock,
6429                                                     refclk, clock,
6430                                                     reduced_clock);
6431         }
6432
6433         return true;
6434 }
6435
6436 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6437 {
6438         /*
6439          * Account for spread spectrum to avoid
6440          * oversubscribing the link. Max center spread
6441          * is 2.5%; use 5% for safety's sake.
6442          */
6443         u32 bps = target_clock * bpp * 21 / 20;
6444         return DIV_ROUND_UP(bps, link_bw * 8);
6445 }
6446
6447 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6448 {
6449         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6450 }
6451
6452 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6453                                       u32 *fp,
6454                                       intel_clock_t *reduced_clock, u32 *fp2)
6455 {
6456         struct drm_crtc *crtc = &intel_crtc->base;
6457         struct drm_device *dev = crtc->dev;
6458         struct drm_i915_private *dev_priv = dev->dev_private;
6459         struct intel_encoder *intel_encoder;
6460         uint32_t dpll;
6461         int factor, num_connectors = 0;
6462         bool is_lvds = false, is_sdvo = false;
6463
6464         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6465                 switch (intel_encoder->type) {
6466                 case INTEL_OUTPUT_LVDS:
6467                         is_lvds = true;
6468                         break;
6469                 case INTEL_OUTPUT_SDVO:
6470                 case INTEL_OUTPUT_HDMI:
6471                         is_sdvo = true;
6472                         break;
6473                 }
6474
6475                 num_connectors++;
6476         }
6477
6478         /* Enable autotuning of the PLL clock (if permissible) */
6479         factor = 21;
6480         if (is_lvds) {
6481                 if ((intel_panel_use_ssc(dev_priv) &&
6482                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6483                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6484                         factor = 25;
6485         } else if (intel_crtc->config.sdvo_tv_clock)
6486                 factor = 20;
6487
6488         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6489                 *fp |= FP_CB_TUNE;
6490
6491         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6492                 *fp2 |= FP_CB_TUNE;
6493
6494         dpll = 0;
6495
6496         if (is_lvds)
6497                 dpll |= DPLLB_MODE_LVDS;
6498         else
6499                 dpll |= DPLLB_MODE_DAC_SERIAL;
6500
6501         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6502                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6503
6504         if (is_sdvo)
6505                 dpll |= DPLL_SDVO_HIGH_SPEED;
6506         if (intel_crtc->config.has_dp_encoder)
6507                 dpll |= DPLL_SDVO_HIGH_SPEED;
6508
6509         /* compute bitmask from p1 value */
6510         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6511         /* also FPA1 */
6512         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6513
6514         switch (intel_crtc->config.dpll.p2) {
6515         case 5:
6516                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6517                 break;
6518         case 7:
6519                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6520                 break;
6521         case 10:
6522                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6523                 break;
6524         case 14:
6525                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6526                 break;
6527         }
6528
6529         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6530                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6531         else
6532                 dpll |= PLL_REF_INPUT_DREFCLK;
6533
6534         return dpll | DPLL_VCO_ENABLE;
6535 }
6536
6537 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6538                                   int x, int y,
6539                                   struct drm_framebuffer *fb)
6540 {
6541         struct drm_device *dev = crtc->dev;
6542         struct drm_i915_private *dev_priv = dev->dev_private;
6543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6544         int pipe = intel_crtc->pipe;
6545         int plane = intel_crtc->plane;
6546         int num_connectors = 0;
6547         intel_clock_t clock, reduced_clock;
6548         u32 dpll = 0, fp = 0, fp2 = 0;
6549         bool ok, has_reduced_clock = false;
6550         bool is_lvds = false;
6551         struct intel_encoder *encoder;
6552         struct intel_shared_dpll *pll;
6553         int ret;
6554
6555         for_each_encoder_on_crtc(dev, crtc, encoder) {
6556                 switch (encoder->type) {
6557                 case INTEL_OUTPUT_LVDS:
6558                         is_lvds = true;
6559                         break;
6560                 }
6561
6562                 num_connectors++;
6563         }
6564
6565         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6566              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6567
6568         ok = ironlake_compute_clocks(crtc, &clock,
6569                                      &has_reduced_clock, &reduced_clock);
6570         if (!ok && !intel_crtc->config.clock_set) {
6571                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6572                 return -EINVAL;
6573         }
6574         /* Compat-code for transition, will disappear. */
6575         if (!intel_crtc->config.clock_set) {
6576                 intel_crtc->config.dpll.n = clock.n;
6577                 intel_crtc->config.dpll.m1 = clock.m1;
6578                 intel_crtc->config.dpll.m2 = clock.m2;
6579                 intel_crtc->config.dpll.p1 = clock.p1;
6580                 intel_crtc->config.dpll.p2 = clock.p2;
6581         }
6582
6583         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6584         if (intel_crtc->config.has_pch_encoder) {
6585                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6586                 if (has_reduced_clock)
6587                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6588
6589                 dpll = ironlake_compute_dpll(intel_crtc,
6590                                              &fp, &reduced_clock,
6591                                              has_reduced_clock ? &fp2 : NULL);
6592
6593                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6594                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6595                 if (has_reduced_clock)
6596                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6597                 else
6598                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6599
6600                 pll = intel_get_shared_dpll(intel_crtc);
6601                 if (pll == NULL) {
6602                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6603                                          pipe_name(pipe));
6604                         return -EINVAL;
6605                 }
6606         } else
6607                 intel_put_shared_dpll(intel_crtc);
6608
6609         if (intel_crtc->config.has_dp_encoder)
6610                 intel_dp_set_m_n(intel_crtc);
6611
6612         if (is_lvds && has_reduced_clock && i915.powersave)
6613                 intel_crtc->lowfreq_avail = true;
6614         else
6615                 intel_crtc->lowfreq_avail = false;
6616
6617         intel_set_pipe_timings(intel_crtc);
6618
6619         if (intel_crtc->config.has_pch_encoder) {
6620                 intel_cpu_transcoder_set_m_n(intel_crtc,
6621                                              &intel_crtc->config.fdi_m_n);
6622         }
6623
6624         ironlake_set_pipeconf(crtc);
6625
6626         /* Set up the display plane register */
6627         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6628         POSTING_READ(DSPCNTR(plane));
6629
6630         ret = intel_pipe_set_base(crtc, x, y, fb);
6631
6632         return ret;
6633 }
6634
6635 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6636                                          struct intel_link_m_n *m_n)
6637 {
6638         struct drm_device *dev = crtc->base.dev;
6639         struct drm_i915_private *dev_priv = dev->dev_private;
6640         enum pipe pipe = crtc->pipe;
6641
6642         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6643         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6644         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6645                 & ~TU_SIZE_MASK;
6646         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6647         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6648                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6649 }
6650
6651 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6652                                          enum transcoder transcoder,
6653                                          struct intel_link_m_n *m_n)
6654 {
6655         struct drm_device *dev = crtc->base.dev;
6656         struct drm_i915_private *dev_priv = dev->dev_private;
6657         enum pipe pipe = crtc->pipe;
6658
6659         if (INTEL_INFO(dev)->gen >= 5) {
6660                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6661                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6662                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6663                         & ~TU_SIZE_MASK;
6664                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6665                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6666                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6667         } else {
6668                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6669                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6670                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6671                         & ~TU_SIZE_MASK;
6672                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6673                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6674                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6675         }
6676 }
6677
6678 void intel_dp_get_m_n(struct intel_crtc *crtc,
6679                       struct intel_crtc_config *pipe_config)
6680 {
6681         if (crtc->config.has_pch_encoder)
6682                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6683         else
6684                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6685                                              &pipe_config->dp_m_n);
6686 }
6687
6688 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6689                                         struct intel_crtc_config *pipe_config)
6690 {
6691         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6692                                      &pipe_config->fdi_m_n);
6693 }
6694
6695 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6696                                      struct intel_crtc_config *pipe_config)
6697 {
6698         struct drm_device *dev = crtc->base.dev;
6699         struct drm_i915_private *dev_priv = dev->dev_private;
6700         uint32_t tmp;
6701
6702         tmp = I915_READ(PF_CTL(crtc->pipe));
6703
6704         if (tmp & PF_ENABLE) {
6705                 pipe_config->pch_pfit.enabled = true;
6706                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6707                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6708
6709                 /* We currently do not free assignements of panel fitters on
6710                  * ivb/hsw (since we don't use the higher upscaling modes which
6711                  * differentiates them) so just WARN about this case for now. */
6712                 if (IS_GEN7(dev)) {
6713                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6714                                 PF_PIPE_SEL_IVB(crtc->pipe));
6715                 }
6716         }
6717 }
6718
6719 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6720                                       struct intel_plane_config *plane_config)
6721 {
6722         struct drm_device *dev = crtc->base.dev;
6723         struct drm_i915_private *dev_priv = dev->dev_private;
6724         u32 val, base, offset;
6725         int pipe = crtc->pipe, plane = crtc->plane;
6726         int fourcc, pixel_format;
6727         int aligned_height;
6728
6729         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6730         if (!crtc->base.primary->fb) {
6731                 DRM_DEBUG_KMS("failed to alloc fb\n");
6732                 return;
6733         }
6734
6735         val = I915_READ(DSPCNTR(plane));
6736
6737         if (INTEL_INFO(dev)->gen >= 4)
6738                 if (val & DISPPLANE_TILED)
6739                         plane_config->tiled = true;
6740
6741         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6742         fourcc = intel_format_to_fourcc(pixel_format);
6743         crtc->base.primary->fb->pixel_format = fourcc;
6744         crtc->base.primary->fb->bits_per_pixel =
6745                 drm_format_plane_cpp(fourcc, 0) * 8;
6746
6747         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6748         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6749                 offset = I915_READ(DSPOFFSET(plane));
6750         } else {
6751                 if (plane_config->tiled)
6752                         offset = I915_READ(DSPTILEOFF(plane));
6753                 else
6754                         offset = I915_READ(DSPLINOFF(plane));
6755         }
6756         plane_config->base = base;
6757
6758         val = I915_READ(PIPESRC(pipe));
6759         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6760         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6761
6762         val = I915_READ(DSPSTRIDE(pipe));
6763         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6764
6765         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6766                                             plane_config->tiled);
6767
6768         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6769                                    aligned_height, PAGE_SIZE);
6770
6771         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6772                       pipe, plane, crtc->base.primary->fb->width,
6773                       crtc->base.primary->fb->height,
6774                       crtc->base.primary->fb->bits_per_pixel, base,
6775                       crtc->base.primary->fb->pitches[0],
6776                       plane_config->size);
6777 }
6778
6779 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6780                                      struct intel_crtc_config *pipe_config)
6781 {
6782         struct drm_device *dev = crtc->base.dev;
6783         struct drm_i915_private *dev_priv = dev->dev_private;
6784         uint32_t tmp;
6785
6786         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6787         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6788
6789         tmp = I915_READ(PIPECONF(crtc->pipe));
6790         if (!(tmp & PIPECONF_ENABLE))
6791                 return false;
6792
6793         switch (tmp & PIPECONF_BPC_MASK) {
6794         case PIPECONF_6BPC:
6795                 pipe_config->pipe_bpp = 18;
6796                 break;
6797         case PIPECONF_8BPC:
6798                 pipe_config->pipe_bpp = 24;
6799                 break;
6800         case PIPECONF_10BPC:
6801                 pipe_config->pipe_bpp = 30;
6802                 break;
6803         case PIPECONF_12BPC:
6804                 pipe_config->pipe_bpp = 36;
6805                 break;
6806         default:
6807                 break;
6808         }
6809
6810         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6811                 struct intel_shared_dpll *pll;
6812
6813                 pipe_config->has_pch_encoder = true;
6814
6815                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6816                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6817                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6818
6819                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6820
6821                 if (HAS_PCH_IBX(dev_priv->dev)) {
6822                         pipe_config->shared_dpll =
6823                                 (enum intel_dpll_id) crtc->pipe;
6824                 } else {
6825                         tmp = I915_READ(PCH_DPLL_SEL);
6826                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6827                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6828                         else
6829                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6830                 }
6831
6832                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6833
6834                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6835                                            &pipe_config->dpll_hw_state));
6836
6837                 tmp = pipe_config->dpll_hw_state.dpll;
6838                 pipe_config->pixel_multiplier =
6839                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6840                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6841
6842                 ironlake_pch_clock_get(crtc, pipe_config);
6843         } else {
6844                 pipe_config->pixel_multiplier = 1;
6845         }
6846
6847         intel_get_pipe_timings(crtc, pipe_config);
6848
6849         ironlake_get_pfit_config(crtc, pipe_config);
6850
6851         return true;
6852 }
6853
6854 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6855 {
6856         struct drm_device *dev = dev_priv->dev;
6857         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6858         struct intel_crtc *crtc;
6859
6860         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6861                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6862                      pipe_name(crtc->pipe));
6863
6864         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6865         WARN(plls->spll_refcount, "SPLL enabled\n");
6866         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6867         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6868         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6869         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6870              "CPU PWM1 enabled\n");
6871         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6872              "CPU PWM2 enabled\n");
6873         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6874              "PCH PWM1 enabled\n");
6875         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6876              "Utility pin enabled\n");
6877         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6878
6879         /*
6880          * In theory we can still leave IRQs enabled, as long as only the HPD
6881          * interrupts remain enabled. We used to check for that, but since it's
6882          * gen-specific and since we only disable LCPLL after we fully disable
6883          * the interrupts, the check below should be enough.
6884          */
6885         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
6886 }
6887
6888 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
6889 {
6890         struct drm_device *dev = dev_priv->dev;
6891
6892         if (IS_HASWELL(dev)) {
6893                 mutex_lock(&dev_priv->rps.hw_lock);
6894                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
6895                                             val))
6896                         DRM_ERROR("Failed to disable D_COMP\n");
6897                 mutex_unlock(&dev_priv->rps.hw_lock);
6898         } else {
6899                 I915_WRITE(D_COMP, val);
6900         }
6901         POSTING_READ(D_COMP);
6902 }
6903
6904 /*
6905  * This function implements pieces of two sequences from BSpec:
6906  * - Sequence for display software to disable LCPLL
6907  * - Sequence for display software to allow package C8+
6908  * The steps implemented here are just the steps that actually touch the LCPLL
6909  * register. Callers should take care of disabling all the display engine
6910  * functions, doing the mode unset, fixing interrupts, etc.
6911  */
6912 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6913                               bool switch_to_fclk, bool allow_power_down)
6914 {
6915         uint32_t val;
6916
6917         assert_can_disable_lcpll(dev_priv);
6918
6919         val = I915_READ(LCPLL_CTL);
6920
6921         if (switch_to_fclk) {
6922                 val |= LCPLL_CD_SOURCE_FCLK;
6923                 I915_WRITE(LCPLL_CTL, val);
6924
6925                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6926                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6927                         DRM_ERROR("Switching to FCLK failed\n");
6928
6929                 val = I915_READ(LCPLL_CTL);
6930         }
6931
6932         val |= LCPLL_PLL_DISABLE;
6933         I915_WRITE(LCPLL_CTL, val);
6934         POSTING_READ(LCPLL_CTL);
6935
6936         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6937                 DRM_ERROR("LCPLL still locked\n");
6938
6939         val = I915_READ(D_COMP);
6940         val |= D_COMP_COMP_DISABLE;
6941         hsw_write_dcomp(dev_priv, val);
6942         ndelay(100);
6943
6944         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6945                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6946
6947         if (allow_power_down) {
6948                 val = I915_READ(LCPLL_CTL);
6949                 val |= LCPLL_POWER_DOWN_ALLOW;
6950                 I915_WRITE(LCPLL_CTL, val);
6951                 POSTING_READ(LCPLL_CTL);
6952         }
6953 }
6954
6955 /*
6956  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6957  * source.
6958  */
6959 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6960 {
6961         uint32_t val;
6962         unsigned long irqflags;
6963
6964         val = I915_READ(LCPLL_CTL);
6965
6966         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6967                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6968                 return;
6969
6970         /*
6971          * Make sure we're not on PC8 state before disabling PC8, otherwise
6972          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
6973          *
6974          * The other problem is that hsw_restore_lcpll() is called as part of
6975          * the runtime PM resume sequence, so we can't just call
6976          * gen6_gt_force_wake_get() because that function calls
6977          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
6978          * while we are on the resume sequence. So to solve this problem we have
6979          * to call special forcewake code that doesn't touch runtime PM and
6980          * doesn't enable the forcewake delayed work.
6981          */
6982         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6983         if (dev_priv->uncore.forcewake_count++ == 0)
6984                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6985         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6986
6987         if (val & LCPLL_POWER_DOWN_ALLOW) {
6988                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6989                 I915_WRITE(LCPLL_CTL, val);
6990                 POSTING_READ(LCPLL_CTL);
6991         }
6992
6993         val = I915_READ(D_COMP);
6994         val |= D_COMP_COMP_FORCE;
6995         val &= ~D_COMP_COMP_DISABLE;
6996         hsw_write_dcomp(dev_priv, val);
6997
6998         val = I915_READ(LCPLL_CTL);
6999         val &= ~LCPLL_PLL_DISABLE;
7000         I915_WRITE(LCPLL_CTL, val);
7001
7002         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7003                 DRM_ERROR("LCPLL not locked yet\n");
7004
7005         if (val & LCPLL_CD_SOURCE_FCLK) {
7006                 val = I915_READ(LCPLL_CTL);
7007                 val &= ~LCPLL_CD_SOURCE_FCLK;
7008                 I915_WRITE(LCPLL_CTL, val);
7009
7010                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7011                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7012                         DRM_ERROR("Switching back to LCPLL failed\n");
7013         }
7014
7015         /* See the big comment above. */
7016         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7017         if (--dev_priv->uncore.forcewake_count == 0)
7018                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7019         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7020 }
7021
7022 /*
7023  * Package states C8 and deeper are really deep PC states that can only be
7024  * reached when all the devices on the system allow it, so even if the graphics
7025  * device allows PC8+, it doesn't mean the system will actually get to these
7026  * states. Our driver only allows PC8+ when going into runtime PM.
7027  *
7028  * The requirements for PC8+ are that all the outputs are disabled, the power
7029  * well is disabled and most interrupts are disabled, and these are also
7030  * requirements for runtime PM. When these conditions are met, we manually do
7031  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7032  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7033  * hang the machine.
7034  *
7035  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7036  * the state of some registers, so when we come back from PC8+ we need to
7037  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7038  * need to take care of the registers kept by RC6. Notice that this happens even
7039  * if we don't put the device in PCI D3 state (which is what currently happens
7040  * because of the runtime PM support).
7041  *
7042  * For more, read "Display Sequences for Package C8" on the hardware
7043  * documentation.
7044  */
7045 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7046 {
7047         struct drm_device *dev = dev_priv->dev;
7048         uint32_t val;
7049
7050         DRM_DEBUG_KMS("Enabling package C8+\n");
7051
7052         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7053                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7054                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7055                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7056         }
7057
7058         lpt_disable_clkout_dp(dev);
7059         intel_runtime_pm_disable_interrupts(dev);
7060         hsw_disable_lcpll(dev_priv, true, true);
7061 }
7062
7063 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7064 {
7065         struct drm_device *dev = dev_priv->dev;
7066         uint32_t val;
7067
7068         DRM_DEBUG_KMS("Disabling package C8+\n");
7069
7070         hsw_restore_lcpll(dev_priv);
7071         intel_runtime_pm_restore_interrupts(dev);
7072         lpt_init_pch_refclk(dev);
7073
7074         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7075                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7076                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7077                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7078         }
7079
7080         intel_prepare_ddi(dev);
7081         i915_gem_init_swizzling(dev);
7082         mutex_lock(&dev_priv->rps.hw_lock);
7083         gen6_update_ring_freq(dev);
7084         mutex_unlock(&dev_priv->rps.hw_lock);
7085 }
7086
7087 static void snb_modeset_global_resources(struct drm_device *dev)
7088 {
7089         modeset_update_crtc_power_domains(dev);
7090 }
7091
7092 static void haswell_modeset_global_resources(struct drm_device *dev)
7093 {
7094         modeset_update_crtc_power_domains(dev);
7095 }
7096
7097 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7098                                  int x, int y,
7099                                  struct drm_framebuffer *fb)
7100 {
7101         struct drm_device *dev = crtc->dev;
7102         struct drm_i915_private *dev_priv = dev->dev_private;
7103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7104         int plane = intel_crtc->plane;
7105         int ret;
7106
7107         if (!intel_ddi_pll_select(intel_crtc))
7108                 return -EINVAL;
7109         intel_ddi_pll_enable(intel_crtc);
7110
7111         if (intel_crtc->config.has_dp_encoder)
7112                 intel_dp_set_m_n(intel_crtc);
7113
7114         intel_crtc->lowfreq_avail = false;
7115
7116         intel_set_pipe_timings(intel_crtc);
7117
7118         if (intel_crtc->config.has_pch_encoder) {
7119                 intel_cpu_transcoder_set_m_n(intel_crtc,
7120                                              &intel_crtc->config.fdi_m_n);
7121         }
7122
7123         haswell_set_pipeconf(crtc);
7124
7125         intel_set_pipe_csc(crtc);
7126
7127         /* Set up the display plane register */
7128         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7129         POSTING_READ(DSPCNTR(plane));
7130
7131         ret = intel_pipe_set_base(crtc, x, y, fb);
7132
7133         return ret;
7134 }
7135
7136 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7137                                     struct intel_crtc_config *pipe_config)
7138 {
7139         struct drm_device *dev = crtc->base.dev;
7140         struct drm_i915_private *dev_priv = dev->dev_private;
7141         enum intel_display_power_domain pfit_domain;
7142         uint32_t tmp;
7143
7144         if (!intel_display_power_enabled(dev_priv,
7145                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7146                 return false;
7147
7148         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7149         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7150
7151         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7152         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7153                 enum pipe trans_edp_pipe;
7154                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7155                 default:
7156                         WARN(1, "unknown pipe linked to edp transcoder\n");
7157                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7158                 case TRANS_DDI_EDP_INPUT_A_ON:
7159                         trans_edp_pipe = PIPE_A;
7160                         break;
7161                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7162                         trans_edp_pipe = PIPE_B;
7163                         break;
7164                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7165                         trans_edp_pipe = PIPE_C;
7166                         break;
7167                 }
7168
7169                 if (trans_edp_pipe == crtc->pipe)
7170                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7171         }
7172
7173         if (!intel_display_power_enabled(dev_priv,
7174                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7175                 return false;
7176
7177         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7178         if (!(tmp & PIPECONF_ENABLE))
7179                 return false;
7180
7181         /*
7182          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7183          * DDI E. So just check whether this pipe is wired to DDI E and whether
7184          * the PCH transcoder is on.
7185          */
7186         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7187         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7188             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7189                 pipe_config->has_pch_encoder = true;
7190
7191                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7192                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7193                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7194
7195                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7196         }
7197
7198         intel_get_pipe_timings(crtc, pipe_config);
7199
7200         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7201         if (intel_display_power_enabled(dev_priv, pfit_domain))
7202                 ironlake_get_pfit_config(crtc, pipe_config);
7203
7204         if (IS_HASWELL(dev))
7205                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7206                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7207
7208         pipe_config->pixel_multiplier = 1;
7209
7210         return true;
7211 }
7212
7213 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7214                                int x, int y,
7215                                struct drm_framebuffer *fb)
7216 {
7217         struct drm_device *dev = crtc->dev;
7218         struct drm_i915_private *dev_priv = dev->dev_private;
7219         struct intel_encoder *encoder;
7220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7221         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7222         int pipe = intel_crtc->pipe;
7223         int ret;
7224
7225         drm_vblank_pre_modeset(dev, pipe);
7226
7227         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7228
7229         drm_vblank_post_modeset(dev, pipe);
7230
7231         if (ret != 0)
7232                 return ret;
7233
7234         for_each_encoder_on_crtc(dev, crtc, encoder) {
7235                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7236                         encoder->base.base.id,
7237                         drm_get_encoder_name(&encoder->base),
7238                         mode->base.id, mode->name);
7239                 encoder->mode_set(encoder);
7240         }
7241
7242         return 0;
7243 }
7244
7245 static struct {
7246         int clock;
7247         u32 config;
7248 } hdmi_audio_clock[] = {
7249         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7250         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7251         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7252         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7253         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7254         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7255         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7256         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7257         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7258         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7259 };
7260
7261 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7262 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7263 {
7264         int i;
7265
7266         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7267                 if (mode->clock == hdmi_audio_clock[i].clock)
7268                         break;
7269         }
7270
7271         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7272                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7273                 i = 1;
7274         }
7275
7276         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7277                       hdmi_audio_clock[i].clock,
7278                       hdmi_audio_clock[i].config);
7279
7280         return hdmi_audio_clock[i].config;
7281 }
7282
7283 static bool intel_eld_uptodate(struct drm_connector *connector,
7284                                int reg_eldv, uint32_t bits_eldv,
7285                                int reg_elda, uint32_t bits_elda,
7286                                int reg_edid)
7287 {
7288         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7289         uint8_t *eld = connector->eld;
7290         uint32_t i;
7291
7292         i = I915_READ(reg_eldv);
7293         i &= bits_eldv;
7294
7295         if (!eld[0])
7296                 return !i;
7297
7298         if (!i)
7299                 return false;
7300
7301         i = I915_READ(reg_elda);
7302         i &= ~bits_elda;
7303         I915_WRITE(reg_elda, i);
7304
7305         for (i = 0; i < eld[2]; i++)
7306                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7307                         return false;
7308
7309         return true;
7310 }
7311
7312 static void g4x_write_eld(struct drm_connector *connector,
7313                           struct drm_crtc *crtc,
7314                           struct drm_display_mode *mode)
7315 {
7316         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7317         uint8_t *eld = connector->eld;
7318         uint32_t eldv;
7319         uint32_t len;
7320         uint32_t i;
7321
7322         i = I915_READ(G4X_AUD_VID_DID);
7323
7324         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7325                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7326         else
7327                 eldv = G4X_ELDV_DEVCTG;
7328
7329         if (intel_eld_uptodate(connector,
7330                                G4X_AUD_CNTL_ST, eldv,
7331                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7332                                G4X_HDMIW_HDMIEDID))
7333                 return;
7334
7335         i = I915_READ(G4X_AUD_CNTL_ST);
7336         i &= ~(eldv | G4X_ELD_ADDR);
7337         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7338         I915_WRITE(G4X_AUD_CNTL_ST, i);
7339
7340         if (!eld[0])
7341                 return;
7342
7343         len = min_t(uint8_t, eld[2], len);
7344         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7345         for (i = 0; i < len; i++)
7346                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7347
7348         i = I915_READ(G4X_AUD_CNTL_ST);
7349         i |= eldv;
7350         I915_WRITE(G4X_AUD_CNTL_ST, i);
7351 }
7352
7353 static void haswell_write_eld(struct drm_connector *connector,
7354                               struct drm_crtc *crtc,
7355                               struct drm_display_mode *mode)
7356 {
7357         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7358         uint8_t *eld = connector->eld;
7359         struct drm_device *dev = crtc->dev;
7360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7361         uint32_t eldv;
7362         uint32_t i;
7363         int len;
7364         int pipe = to_intel_crtc(crtc)->pipe;
7365         int tmp;
7366
7367         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7368         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7369         int aud_config = HSW_AUD_CFG(pipe);
7370         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7371
7372
7373         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7374
7375         /* Audio output enable */
7376         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7377         tmp = I915_READ(aud_cntrl_st2);
7378         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7379         I915_WRITE(aud_cntrl_st2, tmp);
7380
7381         /* Wait for 1 vertical blank */
7382         intel_wait_for_vblank(dev, pipe);
7383
7384         /* Set ELD valid state */
7385         tmp = I915_READ(aud_cntrl_st2);
7386         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7387         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7388         I915_WRITE(aud_cntrl_st2, tmp);
7389         tmp = I915_READ(aud_cntrl_st2);
7390         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7391
7392         /* Enable HDMI mode */
7393         tmp = I915_READ(aud_config);
7394         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7395         /* clear N_programing_enable and N_value_index */
7396         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7397         I915_WRITE(aud_config, tmp);
7398
7399         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7400
7401         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7402         intel_crtc->eld_vld = true;
7403
7404         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7405                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7406                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7407                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7408         } else {
7409                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7410         }
7411
7412         if (intel_eld_uptodate(connector,
7413                                aud_cntrl_st2, eldv,
7414                                aud_cntl_st, IBX_ELD_ADDRESS,
7415                                hdmiw_hdmiedid))
7416                 return;
7417
7418         i = I915_READ(aud_cntrl_st2);
7419         i &= ~eldv;
7420         I915_WRITE(aud_cntrl_st2, i);
7421
7422         if (!eld[0])
7423                 return;
7424
7425         i = I915_READ(aud_cntl_st);
7426         i &= ~IBX_ELD_ADDRESS;
7427         I915_WRITE(aud_cntl_st, i);
7428         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7429         DRM_DEBUG_DRIVER("port num:%d\n", i);
7430
7431         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7432         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7433         for (i = 0; i < len; i++)
7434                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7435
7436         i = I915_READ(aud_cntrl_st2);
7437         i |= eldv;
7438         I915_WRITE(aud_cntrl_st2, i);
7439
7440 }
7441
7442 static void ironlake_write_eld(struct drm_connector *connector,
7443                                struct drm_crtc *crtc,
7444                                struct drm_display_mode *mode)
7445 {
7446         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7447         uint8_t *eld = connector->eld;
7448         uint32_t eldv;
7449         uint32_t i;
7450         int len;
7451         int hdmiw_hdmiedid;
7452         int aud_config;
7453         int aud_cntl_st;
7454         int aud_cntrl_st2;
7455         int pipe = to_intel_crtc(crtc)->pipe;
7456
7457         if (HAS_PCH_IBX(connector->dev)) {
7458                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7459                 aud_config = IBX_AUD_CFG(pipe);
7460                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7461                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7462         } else if (IS_VALLEYVIEW(connector->dev)) {
7463                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7464                 aud_config = VLV_AUD_CFG(pipe);
7465                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7466                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7467         } else {
7468                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7469                 aud_config = CPT_AUD_CFG(pipe);
7470                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7471                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7472         }
7473
7474         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7475
7476         if (IS_VALLEYVIEW(connector->dev))  {
7477                 struct intel_encoder *intel_encoder;
7478                 struct intel_digital_port *intel_dig_port;
7479
7480                 intel_encoder = intel_attached_encoder(connector);
7481                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7482                 i = intel_dig_port->port;
7483         } else {
7484                 i = I915_READ(aud_cntl_st);
7485                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7486                 /* DIP_Port_Select, 0x1 = PortB */
7487         }
7488
7489         if (!i) {
7490                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7491                 /* operate blindly on all ports */
7492                 eldv = IBX_ELD_VALIDB;
7493                 eldv |= IBX_ELD_VALIDB << 4;
7494                 eldv |= IBX_ELD_VALIDB << 8;
7495         } else {
7496                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7497                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7498         }
7499
7500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7501                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7502                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7503                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7504         } else {
7505                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7506         }
7507
7508         if (intel_eld_uptodate(connector,
7509                                aud_cntrl_st2, eldv,
7510                                aud_cntl_st, IBX_ELD_ADDRESS,
7511                                hdmiw_hdmiedid))
7512                 return;
7513
7514         i = I915_READ(aud_cntrl_st2);
7515         i &= ~eldv;
7516         I915_WRITE(aud_cntrl_st2, i);
7517
7518         if (!eld[0])
7519                 return;
7520
7521         i = I915_READ(aud_cntl_st);
7522         i &= ~IBX_ELD_ADDRESS;
7523         I915_WRITE(aud_cntl_st, i);
7524
7525         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7526         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7527         for (i = 0; i < len; i++)
7528                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7529
7530         i = I915_READ(aud_cntrl_st2);
7531         i |= eldv;
7532         I915_WRITE(aud_cntrl_st2, i);
7533 }
7534
7535 void intel_write_eld(struct drm_encoder *encoder,
7536                      struct drm_display_mode *mode)
7537 {
7538         struct drm_crtc *crtc = encoder->crtc;
7539         struct drm_connector *connector;
7540         struct drm_device *dev = encoder->dev;
7541         struct drm_i915_private *dev_priv = dev->dev_private;
7542
7543         connector = drm_select_eld(encoder, mode);
7544         if (!connector)
7545                 return;
7546
7547         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7548                          connector->base.id,
7549                          drm_get_connector_name(connector),
7550                          connector->encoder->base.id,
7551                          drm_get_encoder_name(connector->encoder));
7552
7553         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7554
7555         if (dev_priv->display.write_eld)
7556                 dev_priv->display.write_eld(connector, crtc, mode);
7557 }
7558
7559 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7560 {
7561         struct drm_device *dev = crtc->dev;
7562         struct drm_i915_private *dev_priv = dev->dev_private;
7563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7564         bool visible = base != 0;
7565         u32 cntl;
7566
7567         if (intel_crtc->cursor_visible == visible)
7568                 return;
7569
7570         cntl = I915_READ(_CURACNTR);
7571         if (visible) {
7572                 /* On these chipsets we can only modify the base whilst
7573                  * the cursor is disabled.
7574                  */
7575                 I915_WRITE(_CURABASE, base);
7576
7577                 cntl &= ~(CURSOR_FORMAT_MASK);
7578                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7579                 cntl |= CURSOR_ENABLE |
7580                         CURSOR_GAMMA_ENABLE |
7581                         CURSOR_FORMAT_ARGB;
7582         } else
7583                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7584         I915_WRITE(_CURACNTR, cntl);
7585
7586         intel_crtc->cursor_visible = visible;
7587 }
7588
7589 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7590 {
7591         struct drm_device *dev = crtc->dev;
7592         struct drm_i915_private *dev_priv = dev->dev_private;
7593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7594         int pipe = intel_crtc->pipe;
7595         bool visible = base != 0;
7596
7597         if (intel_crtc->cursor_visible != visible) {
7598                 int16_t width = intel_crtc->cursor_width;
7599                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7600                 if (base) {
7601                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7602                         cntl |= MCURSOR_GAMMA_ENABLE;
7603
7604                         switch (width) {
7605                         case 64:
7606                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7607                                 break;
7608                         case 128:
7609                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7610                                 break;
7611                         case 256:
7612                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7613                                 break;
7614                         default:
7615                                 WARN_ON(1);
7616                                 return;
7617                         }
7618                         cntl |= pipe << 28; /* Connect to correct pipe */
7619                 } else {
7620                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7621                         cntl |= CURSOR_MODE_DISABLE;
7622                 }
7623                 I915_WRITE(CURCNTR(pipe), cntl);
7624
7625                 intel_crtc->cursor_visible = visible;
7626         }
7627         /* and commit changes on next vblank */
7628         POSTING_READ(CURCNTR(pipe));
7629         I915_WRITE(CURBASE(pipe), base);
7630         POSTING_READ(CURBASE(pipe));
7631 }
7632
7633 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7634 {
7635         struct drm_device *dev = crtc->dev;
7636         struct drm_i915_private *dev_priv = dev->dev_private;
7637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7638         int pipe = intel_crtc->pipe;
7639         bool visible = base != 0;
7640
7641         if (intel_crtc->cursor_visible != visible) {
7642                 int16_t width = intel_crtc->cursor_width;
7643                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7644                 if (base) {
7645                         cntl &= ~CURSOR_MODE;
7646                         cntl |= MCURSOR_GAMMA_ENABLE;
7647                         switch (width) {
7648                         case 64:
7649                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7650                                 break;
7651                         case 128:
7652                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7653                                 break;
7654                         case 256:
7655                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7656                                 break;
7657                         default:
7658                                 WARN_ON(1);
7659                                 return;
7660                         }
7661                 } else {
7662                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7663                         cntl |= CURSOR_MODE_DISABLE;
7664                 }
7665                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7666                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7667                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7668                 }
7669                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7670
7671                 intel_crtc->cursor_visible = visible;
7672         }
7673         /* and commit changes on next vblank */
7674         POSTING_READ(CURCNTR_IVB(pipe));
7675         I915_WRITE(CURBASE_IVB(pipe), base);
7676         POSTING_READ(CURBASE_IVB(pipe));
7677 }
7678
7679 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7680 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7681                                      bool on)
7682 {
7683         struct drm_device *dev = crtc->dev;
7684         struct drm_i915_private *dev_priv = dev->dev_private;
7685         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7686         int pipe = intel_crtc->pipe;
7687         int x = intel_crtc->cursor_x;
7688         int y = intel_crtc->cursor_y;
7689         u32 base = 0, pos = 0;
7690         bool visible;
7691
7692         if (on)
7693                 base = intel_crtc->cursor_addr;
7694
7695         if (x >= intel_crtc->config.pipe_src_w)
7696                 base = 0;
7697
7698         if (y >= intel_crtc->config.pipe_src_h)
7699                 base = 0;
7700
7701         if (x < 0) {
7702                 if (x + intel_crtc->cursor_width <= 0)
7703                         base = 0;
7704
7705                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7706                 x = -x;
7707         }
7708         pos |= x << CURSOR_X_SHIFT;
7709
7710         if (y < 0) {
7711                 if (y + intel_crtc->cursor_height <= 0)
7712                         base = 0;
7713
7714                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7715                 y = -y;
7716         }
7717         pos |= y << CURSOR_Y_SHIFT;
7718
7719         visible = base != 0;
7720         if (!visible && !intel_crtc->cursor_visible)
7721                 return;
7722
7723         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7724                 I915_WRITE(CURPOS_IVB(pipe), pos);
7725                 ivb_update_cursor(crtc, base);
7726         } else {
7727                 I915_WRITE(CURPOS(pipe), pos);
7728                 if (IS_845G(dev) || IS_I865G(dev))
7729                         i845_update_cursor(crtc, base);
7730                 else
7731                         i9xx_update_cursor(crtc, base);
7732         }
7733 }
7734
7735 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7736                                  struct drm_file *file,
7737                                  uint32_t handle,
7738                                  uint32_t width, uint32_t height)
7739 {
7740         struct drm_device *dev = crtc->dev;
7741         struct drm_i915_private *dev_priv = dev->dev_private;
7742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7743         struct drm_i915_gem_object *obj;
7744         unsigned old_width;
7745         uint32_t addr;
7746         int ret;
7747
7748         /* if we want to turn off the cursor ignore width and height */
7749         if (!handle) {
7750                 DRM_DEBUG_KMS("cursor off\n");
7751                 addr = 0;
7752                 obj = NULL;
7753                 mutex_lock(&dev->struct_mutex);
7754                 goto finish;
7755         }
7756
7757         /* Check for which cursor types we support */
7758         if (!((width == 64 && height == 64) ||
7759                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7760                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7761                 DRM_DEBUG("Cursor dimension not supported\n");
7762                 return -EINVAL;
7763         }
7764
7765         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7766         if (&obj->base == NULL)
7767                 return -ENOENT;
7768
7769         if (obj->base.size < width * height * 4) {
7770                 DRM_DEBUG_KMS("buffer is to small\n");
7771                 ret = -ENOMEM;
7772                 goto fail;
7773         }
7774
7775         /* we only need to pin inside GTT if cursor is non-phy */
7776         mutex_lock(&dev->struct_mutex);
7777         if (!INTEL_INFO(dev)->cursor_needs_physical) {
7778                 unsigned alignment;
7779
7780                 if (obj->tiling_mode) {
7781                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
7782                         ret = -EINVAL;
7783                         goto fail_locked;
7784                 }
7785
7786                 /* Note that the w/a also requires 2 PTE of padding following
7787                  * the bo. We currently fill all unused PTE with the shadow
7788                  * page and so we should always have valid PTE following the
7789                  * cursor preventing the VT-d warning.
7790                  */
7791                 alignment = 0;
7792                 if (need_vtd_wa(dev))
7793                         alignment = 64*1024;
7794
7795                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7796                 if (ret) {
7797                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7798                         goto fail_locked;
7799                 }
7800
7801                 ret = i915_gem_object_put_fence(obj);
7802                 if (ret) {
7803                         DRM_DEBUG_KMS("failed to release fence for cursor");
7804                         goto fail_unpin;
7805                 }
7806
7807                 addr = i915_gem_obj_ggtt_offset(obj);
7808         } else {
7809                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7810                 ret = i915_gem_attach_phys_object(dev, obj,
7811                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7812                                                   align);
7813                 if (ret) {
7814                         DRM_DEBUG_KMS("failed to attach phys object\n");
7815                         goto fail_locked;
7816                 }
7817                 addr = obj->phys_obj->handle->busaddr;
7818         }
7819
7820         if (IS_GEN2(dev))
7821                 I915_WRITE(CURSIZE, (height << 12) | width);
7822
7823  finish:
7824         if (intel_crtc->cursor_bo) {
7825                 if (INTEL_INFO(dev)->cursor_needs_physical) {
7826                         if (intel_crtc->cursor_bo != obj)
7827                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7828                 } else
7829                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7830                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7831         }
7832
7833         mutex_unlock(&dev->struct_mutex);
7834
7835         old_width = intel_crtc->cursor_width;
7836
7837         intel_crtc->cursor_addr = addr;
7838         intel_crtc->cursor_bo = obj;
7839         intel_crtc->cursor_width = width;
7840         intel_crtc->cursor_height = height;
7841
7842         if (intel_crtc->active) {
7843                 if (old_width != width)
7844                         intel_update_watermarks(crtc);
7845                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7846         }
7847
7848         return 0;
7849 fail_unpin:
7850         i915_gem_object_unpin_from_display_plane(obj);
7851 fail_locked:
7852         mutex_unlock(&dev->struct_mutex);
7853 fail:
7854         drm_gem_object_unreference_unlocked(&obj->base);
7855         return ret;
7856 }
7857
7858 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7859 {
7860         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7861
7862         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7863         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7864
7865         if (intel_crtc->active)
7866                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7867
7868         return 0;
7869 }
7870
7871 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7872                                  u16 *blue, uint32_t start, uint32_t size)
7873 {
7874         int end = (start + size > 256) ? 256 : start + size, i;
7875         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7876
7877         for (i = start; i < end; i++) {
7878                 intel_crtc->lut_r[i] = red[i] >> 8;
7879                 intel_crtc->lut_g[i] = green[i] >> 8;
7880                 intel_crtc->lut_b[i] = blue[i] >> 8;
7881         }
7882
7883         intel_crtc_load_lut(crtc);
7884 }
7885
7886 /* VESA 640x480x72Hz mode to set on the pipe */
7887 static struct drm_display_mode load_detect_mode = {
7888         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7889                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7890 };
7891
7892 struct drm_framebuffer *
7893 __intel_framebuffer_create(struct drm_device *dev,
7894                            struct drm_mode_fb_cmd2 *mode_cmd,
7895                            struct drm_i915_gem_object *obj)
7896 {
7897         struct intel_framebuffer *intel_fb;
7898         int ret;
7899
7900         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7901         if (!intel_fb) {
7902                 drm_gem_object_unreference_unlocked(&obj->base);
7903                 return ERR_PTR(-ENOMEM);
7904         }
7905
7906         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7907         if (ret)
7908                 goto err;
7909
7910         return &intel_fb->base;
7911 err:
7912         drm_gem_object_unreference_unlocked(&obj->base);
7913         kfree(intel_fb);
7914
7915         return ERR_PTR(ret);
7916 }
7917
7918 static struct drm_framebuffer *
7919 intel_framebuffer_create(struct drm_device *dev,
7920                          struct drm_mode_fb_cmd2 *mode_cmd,
7921                          struct drm_i915_gem_object *obj)
7922 {
7923         struct drm_framebuffer *fb;
7924         int ret;
7925
7926         ret = i915_mutex_lock_interruptible(dev);
7927         if (ret)
7928                 return ERR_PTR(ret);
7929         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7930         mutex_unlock(&dev->struct_mutex);
7931
7932         return fb;
7933 }
7934
7935 static u32
7936 intel_framebuffer_pitch_for_width(int width, int bpp)
7937 {
7938         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7939         return ALIGN(pitch, 64);
7940 }
7941
7942 static u32
7943 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7944 {
7945         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7946         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7947 }
7948
7949 static struct drm_framebuffer *
7950 intel_framebuffer_create_for_mode(struct drm_device *dev,
7951                                   struct drm_display_mode *mode,
7952                                   int depth, int bpp)
7953 {
7954         struct drm_i915_gem_object *obj;
7955         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7956
7957         obj = i915_gem_alloc_object(dev,
7958                                     intel_framebuffer_size_for_mode(mode, bpp));
7959         if (obj == NULL)
7960                 return ERR_PTR(-ENOMEM);
7961
7962         mode_cmd.width = mode->hdisplay;
7963         mode_cmd.height = mode->vdisplay;
7964         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7965                                                                 bpp);
7966         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7967
7968         return intel_framebuffer_create(dev, &mode_cmd, obj);
7969 }
7970
7971 static struct drm_framebuffer *
7972 mode_fits_in_fbdev(struct drm_device *dev,
7973                    struct drm_display_mode *mode)
7974 {
7975 #ifdef CONFIG_DRM_I915_FBDEV
7976         struct drm_i915_private *dev_priv = dev->dev_private;
7977         struct drm_i915_gem_object *obj;
7978         struct drm_framebuffer *fb;
7979
7980         if (!dev_priv->fbdev)
7981                 return NULL;
7982
7983         if (!dev_priv->fbdev->fb)
7984                 return NULL;
7985
7986         obj = dev_priv->fbdev->fb->obj;
7987         BUG_ON(!obj);
7988
7989         fb = &dev_priv->fbdev->fb->base;
7990         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7991                                                                fb->bits_per_pixel))
7992                 return NULL;
7993
7994         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7995                 return NULL;
7996
7997         return fb;
7998 #else
7999         return NULL;
8000 #endif
8001 }
8002
8003 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8004                                 struct drm_display_mode *mode,
8005                                 struct intel_load_detect_pipe *old)
8006 {
8007         struct intel_crtc *intel_crtc;
8008         struct intel_encoder *intel_encoder =
8009                 intel_attached_encoder(connector);
8010         struct drm_crtc *possible_crtc;
8011         struct drm_encoder *encoder = &intel_encoder->base;
8012         struct drm_crtc *crtc = NULL;
8013         struct drm_device *dev = encoder->dev;
8014         struct drm_framebuffer *fb;
8015         int i = -1;
8016
8017         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8018                       connector->base.id, drm_get_connector_name(connector),
8019                       encoder->base.id, drm_get_encoder_name(encoder));
8020
8021         /*
8022          * Algorithm gets a little messy:
8023          *
8024          *   - if the connector already has an assigned crtc, use it (but make
8025          *     sure it's on first)
8026          *
8027          *   - try to find the first unused crtc that can drive this connector,
8028          *     and use that if we find one
8029          */
8030
8031         /* See if we already have a CRTC for this connector */
8032         if (encoder->crtc) {
8033                 crtc = encoder->crtc;
8034
8035                 mutex_lock(&crtc->mutex);
8036
8037                 old->dpms_mode = connector->dpms;
8038                 old->load_detect_temp = false;
8039
8040                 /* Make sure the crtc and connector are running */
8041                 if (connector->dpms != DRM_MODE_DPMS_ON)
8042                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8043
8044                 return true;
8045         }
8046
8047         /* Find an unused one (if possible) */
8048         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8049                 i++;
8050                 if (!(encoder->possible_crtcs & (1 << i)))
8051                         continue;
8052                 if (!possible_crtc->enabled) {
8053                         crtc = possible_crtc;
8054                         break;
8055                 }
8056         }
8057
8058         /*
8059          * If we didn't find an unused CRTC, don't use any.
8060          */
8061         if (!crtc) {
8062                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8063                 return false;
8064         }
8065
8066         mutex_lock(&crtc->mutex);
8067         intel_encoder->new_crtc = to_intel_crtc(crtc);
8068         to_intel_connector(connector)->new_encoder = intel_encoder;
8069
8070         intel_crtc = to_intel_crtc(crtc);
8071         intel_crtc->new_enabled = true;
8072         intel_crtc->new_config = &intel_crtc->config;
8073         old->dpms_mode = connector->dpms;
8074         old->load_detect_temp = true;
8075         old->release_fb = NULL;
8076
8077         if (!mode)
8078                 mode = &load_detect_mode;
8079
8080         /* We need a framebuffer large enough to accommodate all accesses
8081          * that the plane may generate whilst we perform load detection.
8082          * We can not rely on the fbcon either being present (we get called
8083          * during its initialisation to detect all boot displays, or it may
8084          * not even exist) or that it is large enough to satisfy the
8085          * requested mode.
8086          */
8087         fb = mode_fits_in_fbdev(dev, mode);
8088         if (fb == NULL) {
8089                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8090                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8091                 old->release_fb = fb;
8092         } else
8093                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8094         if (IS_ERR(fb)) {
8095                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8096                 goto fail;
8097         }
8098
8099         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8100                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8101                 if (old->release_fb)
8102                         old->release_fb->funcs->destroy(old->release_fb);
8103                 goto fail;
8104         }
8105
8106         /* let the connector get through one full cycle before testing */
8107         intel_wait_for_vblank(dev, intel_crtc->pipe);
8108         return true;
8109
8110  fail:
8111         intel_crtc->new_enabled = crtc->enabled;
8112         if (intel_crtc->new_enabled)
8113                 intel_crtc->new_config = &intel_crtc->config;
8114         else
8115                 intel_crtc->new_config = NULL;
8116         mutex_unlock(&crtc->mutex);
8117         return false;
8118 }
8119
8120 void intel_release_load_detect_pipe(struct drm_connector *connector,
8121                                     struct intel_load_detect_pipe *old)
8122 {
8123         struct intel_encoder *intel_encoder =
8124                 intel_attached_encoder(connector);
8125         struct drm_encoder *encoder = &intel_encoder->base;
8126         struct drm_crtc *crtc = encoder->crtc;
8127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8128
8129         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8130                       connector->base.id, drm_get_connector_name(connector),
8131                       encoder->base.id, drm_get_encoder_name(encoder));
8132
8133         if (old->load_detect_temp) {
8134                 to_intel_connector(connector)->new_encoder = NULL;
8135                 intel_encoder->new_crtc = NULL;
8136                 intel_crtc->new_enabled = false;
8137                 intel_crtc->new_config = NULL;
8138                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8139
8140                 if (old->release_fb) {
8141                         drm_framebuffer_unregister_private(old->release_fb);
8142                         drm_framebuffer_unreference(old->release_fb);
8143                 }
8144
8145                 mutex_unlock(&crtc->mutex);
8146                 return;
8147         }
8148
8149         /* Switch crtc and encoder back off if necessary */
8150         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8151                 connector->funcs->dpms(connector, old->dpms_mode);
8152
8153         mutex_unlock(&crtc->mutex);
8154 }
8155
8156 static int i9xx_pll_refclk(struct drm_device *dev,
8157                            const struct intel_crtc_config *pipe_config)
8158 {
8159         struct drm_i915_private *dev_priv = dev->dev_private;
8160         u32 dpll = pipe_config->dpll_hw_state.dpll;
8161
8162         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8163                 return dev_priv->vbt.lvds_ssc_freq;
8164         else if (HAS_PCH_SPLIT(dev))
8165                 return 120000;
8166         else if (!IS_GEN2(dev))
8167                 return 96000;
8168         else
8169                 return 48000;
8170 }
8171
8172 /* Returns the clock of the currently programmed mode of the given pipe. */
8173 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8174                                 struct intel_crtc_config *pipe_config)
8175 {
8176         struct drm_device *dev = crtc->base.dev;
8177         struct drm_i915_private *dev_priv = dev->dev_private;
8178         int pipe = pipe_config->cpu_transcoder;
8179         u32 dpll = pipe_config->dpll_hw_state.dpll;
8180         u32 fp;
8181         intel_clock_t clock;
8182         int refclk = i9xx_pll_refclk(dev, pipe_config);
8183
8184         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8185                 fp = pipe_config->dpll_hw_state.fp0;
8186         else
8187                 fp = pipe_config->dpll_hw_state.fp1;
8188
8189         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8190         if (IS_PINEVIEW(dev)) {
8191                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8192                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8193         } else {
8194                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8195                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8196         }
8197
8198         if (!IS_GEN2(dev)) {
8199                 if (IS_PINEVIEW(dev))
8200                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8201                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8202                 else
8203                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8204                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8205
8206                 switch (dpll & DPLL_MODE_MASK) {
8207                 case DPLLB_MODE_DAC_SERIAL:
8208                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8209                                 5 : 10;
8210                         break;
8211                 case DPLLB_MODE_LVDS:
8212                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8213                                 7 : 14;
8214                         break;
8215                 default:
8216                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8217                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8218                         return;
8219                 }
8220
8221                 if (IS_PINEVIEW(dev))
8222                         pineview_clock(refclk, &clock);
8223                 else
8224                         i9xx_clock(refclk, &clock);
8225         } else {
8226                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8227                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8228
8229                 if (is_lvds) {
8230                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8231                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8232
8233                         if (lvds & LVDS_CLKB_POWER_UP)
8234                                 clock.p2 = 7;
8235                         else
8236                                 clock.p2 = 14;
8237                 } else {
8238                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8239                                 clock.p1 = 2;
8240                         else {
8241                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8242                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8243                         }
8244                         if (dpll & PLL_P2_DIVIDE_BY_4)
8245                                 clock.p2 = 4;
8246                         else
8247                                 clock.p2 = 2;
8248                 }
8249
8250                 i9xx_clock(refclk, &clock);
8251         }
8252
8253         /*
8254          * This value includes pixel_multiplier. We will use
8255          * port_clock to compute adjusted_mode.crtc_clock in the
8256          * encoder's get_config() function.
8257          */
8258         pipe_config->port_clock = clock.dot;
8259 }
8260
8261 int intel_dotclock_calculate(int link_freq,
8262                              const struct intel_link_m_n *m_n)
8263 {
8264         /*
8265          * The calculation for the data clock is:
8266          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8267          * But we want to avoid losing precison if possible, so:
8268          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8269          *
8270          * and the link clock is simpler:
8271          * link_clock = (m * link_clock) / n
8272          */
8273
8274         if (!m_n->link_n)
8275                 return 0;
8276
8277         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8278 }
8279
8280 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8281                                    struct intel_crtc_config *pipe_config)
8282 {
8283         struct drm_device *dev = crtc->base.dev;
8284
8285         /* read out port_clock from the DPLL */
8286         i9xx_crtc_clock_get(crtc, pipe_config);
8287
8288         /*
8289          * This value does not include pixel_multiplier.
8290          * We will check that port_clock and adjusted_mode.crtc_clock
8291          * agree once we know their relationship in the encoder's
8292          * get_config() function.
8293          */
8294         pipe_config->adjusted_mode.crtc_clock =
8295                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8296                                          &pipe_config->fdi_m_n);
8297 }
8298
8299 /** Returns the currently programmed mode of the given pipe. */
8300 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8301                                              struct drm_crtc *crtc)
8302 {
8303         struct drm_i915_private *dev_priv = dev->dev_private;
8304         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8305         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8306         struct drm_display_mode *mode;
8307         struct intel_crtc_config pipe_config;
8308         int htot = I915_READ(HTOTAL(cpu_transcoder));
8309         int hsync = I915_READ(HSYNC(cpu_transcoder));
8310         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8311         int vsync = I915_READ(VSYNC(cpu_transcoder));
8312         enum pipe pipe = intel_crtc->pipe;
8313
8314         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8315         if (!mode)
8316                 return NULL;
8317
8318         /*
8319          * Construct a pipe_config sufficient for getting the clock info
8320          * back out of crtc_clock_get.
8321          *
8322          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8323          * to use a real value here instead.
8324          */
8325         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8326         pipe_config.pixel_multiplier = 1;
8327         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8328         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8329         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8330         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8331
8332         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8333         mode->hdisplay = (htot & 0xffff) + 1;
8334         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8335         mode->hsync_start = (hsync & 0xffff) + 1;
8336         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8337         mode->vdisplay = (vtot & 0xffff) + 1;
8338         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8339         mode->vsync_start = (vsync & 0xffff) + 1;
8340         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8341
8342         drm_mode_set_name(mode);
8343
8344         return mode;
8345 }
8346
8347 static void intel_increase_pllclock(struct drm_crtc *crtc)
8348 {
8349         struct drm_device *dev = crtc->dev;
8350         struct drm_i915_private *dev_priv = dev->dev_private;
8351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8352         int pipe = intel_crtc->pipe;
8353         int dpll_reg = DPLL(pipe);
8354         int dpll;
8355
8356         if (HAS_PCH_SPLIT(dev))
8357                 return;
8358
8359         if (!dev_priv->lvds_downclock_avail)
8360                 return;
8361
8362         dpll = I915_READ(dpll_reg);
8363         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8364                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8365
8366                 assert_panel_unlocked(dev_priv, pipe);
8367
8368                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8369                 I915_WRITE(dpll_reg, dpll);
8370                 intel_wait_for_vblank(dev, pipe);
8371
8372                 dpll = I915_READ(dpll_reg);
8373                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8374                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8375         }
8376 }
8377
8378 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8379 {
8380         struct drm_device *dev = crtc->dev;
8381         struct drm_i915_private *dev_priv = dev->dev_private;
8382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8383
8384         if (HAS_PCH_SPLIT(dev))
8385                 return;
8386
8387         if (!dev_priv->lvds_downclock_avail)
8388                 return;
8389
8390         /*
8391          * Since this is called by a timer, we should never get here in
8392          * the manual case.
8393          */
8394         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8395                 int pipe = intel_crtc->pipe;
8396                 int dpll_reg = DPLL(pipe);
8397                 int dpll;
8398
8399                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8400
8401                 assert_panel_unlocked(dev_priv, pipe);
8402
8403                 dpll = I915_READ(dpll_reg);
8404                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8405                 I915_WRITE(dpll_reg, dpll);
8406                 intel_wait_for_vblank(dev, pipe);
8407                 dpll = I915_READ(dpll_reg);
8408                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8409                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8410         }
8411
8412 }
8413
8414 void intel_mark_busy(struct drm_device *dev)
8415 {
8416         struct drm_i915_private *dev_priv = dev->dev_private;
8417
8418         if (dev_priv->mm.busy)
8419                 return;
8420
8421         intel_runtime_pm_get(dev_priv);
8422         i915_update_gfx_val(dev_priv);
8423         dev_priv->mm.busy = true;
8424 }
8425
8426 void intel_mark_idle(struct drm_device *dev)
8427 {
8428         struct drm_i915_private *dev_priv = dev->dev_private;
8429         struct drm_crtc *crtc;
8430
8431         if (!dev_priv->mm.busy)
8432                 return;
8433
8434         dev_priv->mm.busy = false;
8435
8436         if (!i915.powersave)
8437                 goto out;
8438
8439         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8440                 if (!crtc->primary->fb)
8441                         continue;
8442
8443                 intel_decrease_pllclock(crtc);
8444         }
8445
8446         if (INTEL_INFO(dev)->gen >= 6)
8447                 gen6_rps_idle(dev->dev_private);
8448
8449 out:
8450         intel_runtime_pm_put(dev_priv);
8451 }
8452
8453 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8454                         struct intel_ring_buffer *ring)
8455 {
8456         struct drm_device *dev = obj->base.dev;
8457         struct drm_crtc *crtc;
8458
8459         if (!i915.powersave)
8460                 return;
8461
8462         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8463                 if (!crtc->primary->fb)
8464                         continue;
8465
8466                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8467                         continue;
8468
8469                 intel_increase_pllclock(crtc);
8470                 if (ring && intel_fbc_enabled(dev))
8471                         ring->fbc_dirty = true;
8472         }
8473 }
8474
8475 static void intel_crtc_destroy(struct drm_crtc *crtc)
8476 {
8477         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8478         struct drm_device *dev = crtc->dev;
8479         struct intel_unpin_work *work;
8480         unsigned long flags;
8481
8482         spin_lock_irqsave(&dev->event_lock, flags);
8483         work = intel_crtc->unpin_work;
8484         intel_crtc->unpin_work = NULL;
8485         spin_unlock_irqrestore(&dev->event_lock, flags);
8486
8487         if (work) {
8488                 cancel_work_sync(&work->work);
8489                 kfree(work);
8490         }
8491
8492         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8493
8494         drm_crtc_cleanup(crtc);
8495
8496         kfree(intel_crtc);
8497 }
8498
8499 static void intel_unpin_work_fn(struct work_struct *__work)
8500 {
8501         struct intel_unpin_work *work =
8502                 container_of(__work, struct intel_unpin_work, work);
8503         struct drm_device *dev = work->crtc->dev;
8504
8505         mutex_lock(&dev->struct_mutex);
8506         intel_unpin_fb_obj(work->old_fb_obj);
8507         drm_gem_object_unreference(&work->pending_flip_obj->base);
8508         drm_gem_object_unreference(&work->old_fb_obj->base);
8509
8510         intel_update_fbc(dev);
8511         mutex_unlock(&dev->struct_mutex);
8512
8513         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8514         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8515
8516         kfree(work);
8517 }
8518
8519 static void do_intel_finish_page_flip(struct drm_device *dev,
8520                                       struct drm_crtc *crtc)
8521 {
8522         struct drm_i915_private *dev_priv = dev->dev_private;
8523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8524         struct intel_unpin_work *work;
8525         unsigned long flags;
8526
8527         /* Ignore early vblank irqs */
8528         if (intel_crtc == NULL)
8529                 return;
8530
8531         spin_lock_irqsave(&dev->event_lock, flags);
8532         work = intel_crtc->unpin_work;
8533
8534         /* Ensure we don't miss a work->pending update ... */
8535         smp_rmb();
8536
8537         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8538                 spin_unlock_irqrestore(&dev->event_lock, flags);
8539                 return;
8540         }
8541
8542         /* and that the unpin work is consistent wrt ->pending. */
8543         smp_rmb();
8544
8545         intel_crtc->unpin_work = NULL;
8546
8547         if (work->event)
8548                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8549
8550         drm_vblank_put(dev, intel_crtc->pipe);
8551
8552         spin_unlock_irqrestore(&dev->event_lock, flags);
8553
8554         wake_up_all(&dev_priv->pending_flip_queue);
8555
8556         queue_work(dev_priv->wq, &work->work);
8557
8558         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8559 }
8560
8561 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8562 {
8563         struct drm_i915_private *dev_priv = dev->dev_private;
8564         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8565
8566         do_intel_finish_page_flip(dev, crtc);
8567 }
8568
8569 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8570 {
8571         struct drm_i915_private *dev_priv = dev->dev_private;
8572         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8573
8574         do_intel_finish_page_flip(dev, crtc);
8575 }
8576
8577 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8578 {
8579         struct drm_i915_private *dev_priv = dev->dev_private;
8580         struct intel_crtc *intel_crtc =
8581                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8582         unsigned long flags;
8583
8584         /* NB: An MMIO update of the plane base pointer will also
8585          * generate a page-flip completion irq, i.e. every modeset
8586          * is also accompanied by a spurious intel_prepare_page_flip().
8587          */
8588         spin_lock_irqsave(&dev->event_lock, flags);
8589         if (intel_crtc->unpin_work)
8590                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8591         spin_unlock_irqrestore(&dev->event_lock, flags);
8592 }
8593
8594 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8595 {
8596         /* Ensure that the work item is consistent when activating it ... */
8597         smp_wmb();
8598         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8599         /* and that it is marked active as soon as the irq could fire. */
8600         smp_wmb();
8601 }
8602
8603 static int intel_gen2_queue_flip(struct drm_device *dev,
8604                                  struct drm_crtc *crtc,
8605                                  struct drm_framebuffer *fb,
8606                                  struct drm_i915_gem_object *obj,
8607                                  uint32_t flags)
8608 {
8609         struct drm_i915_private *dev_priv = dev->dev_private;
8610         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8611         u32 flip_mask;
8612         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8613         int ret;
8614
8615         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8616         if (ret)
8617                 goto err;
8618
8619         ret = intel_ring_begin(ring, 6);
8620         if (ret)
8621                 goto err_unpin;
8622
8623         /* Can't queue multiple flips, so wait for the previous
8624          * one to finish before executing the next.
8625          */
8626         if (intel_crtc->plane)
8627                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8628         else
8629                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8630         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8631         intel_ring_emit(ring, MI_NOOP);
8632         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8633                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8634         intel_ring_emit(ring, fb->pitches[0]);
8635         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8636         intel_ring_emit(ring, 0); /* aux display base address, unused */
8637
8638         intel_mark_page_flip_active(intel_crtc);
8639         __intel_ring_advance(ring);
8640         return 0;
8641
8642 err_unpin:
8643         intel_unpin_fb_obj(obj);
8644 err:
8645         return ret;
8646 }
8647
8648 static int intel_gen3_queue_flip(struct drm_device *dev,
8649                                  struct drm_crtc *crtc,
8650                                  struct drm_framebuffer *fb,
8651                                  struct drm_i915_gem_object *obj,
8652                                  uint32_t flags)
8653 {
8654         struct drm_i915_private *dev_priv = dev->dev_private;
8655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8656         u32 flip_mask;
8657         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8658         int ret;
8659
8660         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8661         if (ret)
8662                 goto err;
8663
8664         ret = intel_ring_begin(ring, 6);
8665         if (ret)
8666                 goto err_unpin;
8667
8668         if (intel_crtc->plane)
8669                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8670         else
8671                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8672         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8673         intel_ring_emit(ring, MI_NOOP);
8674         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8675                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8676         intel_ring_emit(ring, fb->pitches[0]);
8677         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8678         intel_ring_emit(ring, MI_NOOP);
8679
8680         intel_mark_page_flip_active(intel_crtc);
8681         __intel_ring_advance(ring);
8682         return 0;
8683
8684 err_unpin:
8685         intel_unpin_fb_obj(obj);
8686 err:
8687         return ret;
8688 }
8689
8690 static int intel_gen4_queue_flip(struct drm_device *dev,
8691                                  struct drm_crtc *crtc,
8692                                  struct drm_framebuffer *fb,
8693                                  struct drm_i915_gem_object *obj,
8694                                  uint32_t flags)
8695 {
8696         struct drm_i915_private *dev_priv = dev->dev_private;
8697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8698         uint32_t pf, pipesrc;
8699         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8700         int ret;
8701
8702         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8703         if (ret)
8704                 goto err;
8705
8706         ret = intel_ring_begin(ring, 4);
8707         if (ret)
8708                 goto err_unpin;
8709
8710         /* i965+ uses the linear or tiled offsets from the
8711          * Display Registers (which do not change across a page-flip)
8712          * so we need only reprogram the base address.
8713          */
8714         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8715                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8716         intel_ring_emit(ring, fb->pitches[0]);
8717         intel_ring_emit(ring,
8718                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8719                         obj->tiling_mode);
8720
8721         /* XXX Enabling the panel-fitter across page-flip is so far
8722          * untested on non-native modes, so ignore it for now.
8723          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8724          */
8725         pf = 0;
8726         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8727         intel_ring_emit(ring, pf | pipesrc);
8728
8729         intel_mark_page_flip_active(intel_crtc);
8730         __intel_ring_advance(ring);
8731         return 0;
8732
8733 err_unpin:
8734         intel_unpin_fb_obj(obj);
8735 err:
8736         return ret;
8737 }
8738
8739 static int intel_gen6_queue_flip(struct drm_device *dev,
8740                                  struct drm_crtc *crtc,
8741                                  struct drm_framebuffer *fb,
8742                                  struct drm_i915_gem_object *obj,
8743                                  uint32_t flags)
8744 {
8745         struct drm_i915_private *dev_priv = dev->dev_private;
8746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8747         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8748         uint32_t pf, pipesrc;
8749         int ret;
8750
8751         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8752         if (ret)
8753                 goto err;
8754
8755         ret = intel_ring_begin(ring, 4);
8756         if (ret)
8757                 goto err_unpin;
8758
8759         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8760                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8761         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8762         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8763
8764         /* Contrary to the suggestions in the documentation,
8765          * "Enable Panel Fitter" does not seem to be required when page
8766          * flipping with a non-native mode, and worse causes a normal
8767          * modeset to fail.
8768          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8769          */
8770         pf = 0;
8771         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8772         intel_ring_emit(ring, pf | pipesrc);
8773
8774         intel_mark_page_flip_active(intel_crtc);
8775         __intel_ring_advance(ring);
8776         return 0;
8777
8778 err_unpin:
8779         intel_unpin_fb_obj(obj);
8780 err:
8781         return ret;
8782 }
8783
8784 static int intel_gen7_queue_flip(struct drm_device *dev,
8785                                  struct drm_crtc *crtc,
8786                                  struct drm_framebuffer *fb,
8787                                  struct drm_i915_gem_object *obj,
8788                                  uint32_t flags)
8789 {
8790         struct drm_i915_private *dev_priv = dev->dev_private;
8791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8792         struct intel_ring_buffer *ring;
8793         uint32_t plane_bit = 0;
8794         int len, ret;
8795
8796         ring = obj->ring;
8797         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8798                 ring = &dev_priv->ring[BCS];
8799
8800         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8801         if (ret)
8802                 goto err;
8803
8804         switch(intel_crtc->plane) {
8805         case PLANE_A:
8806                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8807                 break;
8808         case PLANE_B:
8809                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8810                 break;
8811         case PLANE_C:
8812                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8813                 break;
8814         default:
8815                 WARN_ONCE(1, "unknown plane in flip command\n");
8816                 ret = -ENODEV;
8817                 goto err_unpin;
8818         }
8819
8820         len = 4;
8821         if (ring->id == RCS)
8822                 len += 6;
8823
8824         /*
8825          * BSpec MI_DISPLAY_FLIP for IVB:
8826          * "The full packet must be contained within the same cache line."
8827          *
8828          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8829          * cacheline, if we ever start emitting more commands before
8830          * the MI_DISPLAY_FLIP we may need to first emit everything else,
8831          * then do the cacheline alignment, and finally emit the
8832          * MI_DISPLAY_FLIP.
8833          */
8834         ret = intel_ring_cacheline_align(ring);
8835         if (ret)
8836                 goto err_unpin;
8837
8838         ret = intel_ring_begin(ring, len);
8839         if (ret)
8840                 goto err_unpin;
8841
8842         /* Unmask the flip-done completion message. Note that the bspec says that
8843          * we should do this for both the BCS and RCS, and that we must not unmask
8844          * more than one flip event at any time (or ensure that one flip message
8845          * can be sent by waiting for flip-done prior to queueing new flips).
8846          * Experimentation says that BCS works despite DERRMR masking all
8847          * flip-done completion events and that unmasking all planes at once
8848          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8849          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8850          */
8851         if (ring->id == RCS) {
8852                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8853                 intel_ring_emit(ring, DERRMR);
8854                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8855                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8856                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8857                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8858                                 MI_SRM_LRM_GLOBAL_GTT);
8859                 intel_ring_emit(ring, DERRMR);
8860                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8861         }
8862
8863         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8864         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8865         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8866         intel_ring_emit(ring, (MI_NOOP));
8867
8868         intel_mark_page_flip_active(intel_crtc);
8869         __intel_ring_advance(ring);
8870         return 0;
8871
8872 err_unpin:
8873         intel_unpin_fb_obj(obj);
8874 err:
8875         return ret;
8876 }
8877
8878 static int intel_default_queue_flip(struct drm_device *dev,
8879                                     struct drm_crtc *crtc,
8880                                     struct drm_framebuffer *fb,
8881                                     struct drm_i915_gem_object *obj,
8882                                     uint32_t flags)
8883 {
8884         return -ENODEV;
8885 }
8886
8887 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8888                                 struct drm_framebuffer *fb,
8889                                 struct drm_pending_vblank_event *event,
8890                                 uint32_t page_flip_flags)
8891 {
8892         struct drm_device *dev = crtc->dev;
8893         struct drm_i915_private *dev_priv = dev->dev_private;
8894         struct drm_framebuffer *old_fb = crtc->primary->fb;
8895         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8896         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8897         struct intel_unpin_work *work;
8898         unsigned long flags;
8899         int ret;
8900
8901         /* Can't change pixel format via MI display flips. */
8902         if (fb->pixel_format != crtc->primary->fb->pixel_format)
8903                 return -EINVAL;
8904
8905         /*
8906          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8907          * Note that pitch changes could also affect these register.
8908          */
8909         if (INTEL_INFO(dev)->gen > 3 &&
8910             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
8911              fb->pitches[0] != crtc->primary->fb->pitches[0]))
8912                 return -EINVAL;
8913
8914         if (i915_terminally_wedged(&dev_priv->gpu_error))
8915                 goto out_hang;
8916
8917         work = kzalloc(sizeof(*work), GFP_KERNEL);
8918         if (work == NULL)
8919                 return -ENOMEM;
8920
8921         work->event = event;
8922         work->crtc = crtc;
8923         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8924         INIT_WORK(&work->work, intel_unpin_work_fn);
8925
8926         ret = drm_vblank_get(dev, intel_crtc->pipe);
8927         if (ret)
8928                 goto free_work;
8929
8930         /* We borrow the event spin lock for protecting unpin_work */
8931         spin_lock_irqsave(&dev->event_lock, flags);
8932         if (intel_crtc->unpin_work) {
8933                 spin_unlock_irqrestore(&dev->event_lock, flags);
8934                 kfree(work);
8935                 drm_vblank_put(dev, intel_crtc->pipe);
8936
8937                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8938                 return -EBUSY;
8939         }
8940         intel_crtc->unpin_work = work;
8941         spin_unlock_irqrestore(&dev->event_lock, flags);
8942
8943         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8944                 flush_workqueue(dev_priv->wq);
8945
8946         ret = i915_mutex_lock_interruptible(dev);
8947         if (ret)
8948                 goto cleanup;
8949
8950         /* Reference the objects for the scheduled work. */
8951         drm_gem_object_reference(&work->old_fb_obj->base);
8952         drm_gem_object_reference(&obj->base);
8953
8954         crtc->primary->fb = fb;
8955
8956         work->pending_flip_obj = obj;
8957
8958         work->enable_stall_check = true;
8959
8960         atomic_inc(&intel_crtc->unpin_work_count);
8961         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8962
8963         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8964         if (ret)
8965                 goto cleanup_pending;
8966
8967         intel_disable_fbc(dev);
8968         intel_mark_fb_busy(obj, NULL);
8969         mutex_unlock(&dev->struct_mutex);
8970
8971         trace_i915_flip_request(intel_crtc->plane, obj);
8972
8973         return 0;
8974
8975 cleanup_pending:
8976         atomic_dec(&intel_crtc->unpin_work_count);
8977         crtc->primary->fb = old_fb;
8978         drm_gem_object_unreference(&work->old_fb_obj->base);
8979         drm_gem_object_unreference(&obj->base);
8980         mutex_unlock(&dev->struct_mutex);
8981
8982 cleanup:
8983         spin_lock_irqsave(&dev->event_lock, flags);
8984         intel_crtc->unpin_work = NULL;
8985         spin_unlock_irqrestore(&dev->event_lock, flags);
8986
8987         drm_vblank_put(dev, intel_crtc->pipe);
8988 free_work:
8989         kfree(work);
8990
8991         if (ret == -EIO) {
8992 out_hang:
8993                 intel_crtc_wait_for_pending_flips(crtc);
8994                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
8995                 if (ret == 0 && event)
8996                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
8997         }
8998         return ret;
8999 }
9000
9001 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9002         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9003         .load_lut = intel_crtc_load_lut,
9004 };
9005
9006 /**
9007  * intel_modeset_update_staged_output_state
9008  *
9009  * Updates the staged output configuration state, e.g. after we've read out the
9010  * current hw state.
9011  */
9012 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9013 {
9014         struct intel_crtc *crtc;
9015         struct intel_encoder *encoder;
9016         struct intel_connector *connector;
9017
9018         list_for_each_entry(connector, &dev->mode_config.connector_list,
9019                             base.head) {
9020                 connector->new_encoder =
9021                         to_intel_encoder(connector->base.encoder);
9022         }
9023
9024         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9025                             base.head) {
9026                 encoder->new_crtc =
9027                         to_intel_crtc(encoder->base.crtc);
9028         }
9029
9030         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9031                             base.head) {
9032                 crtc->new_enabled = crtc->base.enabled;
9033
9034                 if (crtc->new_enabled)
9035                         crtc->new_config = &crtc->config;
9036                 else
9037                         crtc->new_config = NULL;
9038         }
9039 }
9040
9041 /**
9042  * intel_modeset_commit_output_state
9043  *
9044  * This function copies the stage display pipe configuration to the real one.
9045  */
9046 static void intel_modeset_commit_output_state(struct drm_device *dev)
9047 {
9048         struct intel_crtc *crtc;
9049         struct intel_encoder *encoder;
9050         struct intel_connector *connector;
9051
9052         list_for_each_entry(connector, &dev->mode_config.connector_list,
9053                             base.head) {
9054                 connector->base.encoder = &connector->new_encoder->base;
9055         }
9056
9057         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9058                             base.head) {
9059                 encoder->base.crtc = &encoder->new_crtc->base;
9060         }
9061
9062         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9063                             base.head) {
9064                 crtc->base.enabled = crtc->new_enabled;
9065         }
9066 }
9067
9068 static void
9069 connected_sink_compute_bpp(struct intel_connector * connector,
9070                            struct intel_crtc_config *pipe_config)
9071 {
9072         int bpp = pipe_config->pipe_bpp;
9073
9074         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9075                 connector->base.base.id,
9076                 drm_get_connector_name(&connector->base));
9077
9078         /* Don't use an invalid EDID bpc value */
9079         if (connector->base.display_info.bpc &&
9080             connector->base.display_info.bpc * 3 < bpp) {
9081                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9082                               bpp, connector->base.display_info.bpc*3);
9083                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9084         }
9085
9086         /* Clamp bpp to 8 on screens without EDID 1.4 */
9087         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9088                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9089                               bpp);
9090                 pipe_config->pipe_bpp = 24;
9091         }
9092 }
9093
9094 static int
9095 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9096                           struct drm_framebuffer *fb,
9097                           struct intel_crtc_config *pipe_config)
9098 {
9099         struct drm_device *dev = crtc->base.dev;
9100         struct intel_connector *connector;
9101         int bpp;
9102
9103         switch (fb->pixel_format) {
9104         case DRM_FORMAT_C8:
9105                 bpp = 8*3; /* since we go through a colormap */
9106                 break;
9107         case DRM_FORMAT_XRGB1555:
9108         case DRM_FORMAT_ARGB1555:
9109                 /* checked in intel_framebuffer_init already */
9110                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9111                         return -EINVAL;
9112         case DRM_FORMAT_RGB565:
9113                 bpp = 6*3; /* min is 18bpp */
9114                 break;
9115         case DRM_FORMAT_XBGR8888:
9116         case DRM_FORMAT_ABGR8888:
9117                 /* checked in intel_framebuffer_init already */
9118                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9119                         return -EINVAL;
9120         case DRM_FORMAT_XRGB8888:
9121         case DRM_FORMAT_ARGB8888:
9122                 bpp = 8*3;
9123                 break;
9124         case DRM_FORMAT_XRGB2101010:
9125         case DRM_FORMAT_ARGB2101010:
9126         case DRM_FORMAT_XBGR2101010:
9127         case DRM_FORMAT_ABGR2101010:
9128                 /* checked in intel_framebuffer_init already */
9129                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9130                         return -EINVAL;
9131                 bpp = 10*3;
9132                 break;
9133         /* TODO: gen4+ supports 16 bpc floating point, too. */
9134         default:
9135                 DRM_DEBUG_KMS("unsupported depth\n");
9136                 return -EINVAL;
9137         }
9138
9139         pipe_config->pipe_bpp = bpp;
9140
9141         /* Clamp display bpp to EDID value */
9142         list_for_each_entry(connector, &dev->mode_config.connector_list,
9143                             base.head) {
9144                 if (!connector->new_encoder ||
9145                     connector->new_encoder->new_crtc != crtc)
9146                         continue;
9147
9148                 connected_sink_compute_bpp(connector, pipe_config);
9149         }
9150
9151         return bpp;
9152 }
9153
9154 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9155 {
9156         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9157                         "type: 0x%x flags: 0x%x\n",
9158                 mode->crtc_clock,
9159                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9160                 mode->crtc_hsync_end, mode->crtc_htotal,
9161                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9162                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9163 }
9164
9165 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9166                                    struct intel_crtc_config *pipe_config,
9167                                    const char *context)
9168 {
9169         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9170                       context, pipe_name(crtc->pipe));
9171
9172         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9173         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9174                       pipe_config->pipe_bpp, pipe_config->dither);
9175         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9176                       pipe_config->has_pch_encoder,
9177                       pipe_config->fdi_lanes,
9178                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9179                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9180                       pipe_config->fdi_m_n.tu);
9181         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9182                       pipe_config->has_dp_encoder,
9183                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9184                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9185                       pipe_config->dp_m_n.tu);
9186         DRM_DEBUG_KMS("requested mode:\n");
9187         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9188         DRM_DEBUG_KMS("adjusted mode:\n");
9189         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9190         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9191         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9192         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9193                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9194         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9195                       pipe_config->gmch_pfit.control,
9196                       pipe_config->gmch_pfit.pgm_ratios,
9197                       pipe_config->gmch_pfit.lvds_border_bits);
9198         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9199                       pipe_config->pch_pfit.pos,
9200                       pipe_config->pch_pfit.size,
9201                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9202         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9203         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9204 }
9205
9206 static bool encoders_cloneable(const struct intel_encoder *a,
9207                                const struct intel_encoder *b)
9208 {
9209         /* masks could be asymmetric, so check both ways */
9210         return a == b || (a->cloneable & (1 << b->type) &&
9211                           b->cloneable & (1 << a->type));
9212 }
9213
9214 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9215                                          struct intel_encoder *encoder)
9216 {
9217         struct drm_device *dev = crtc->base.dev;
9218         struct intel_encoder *source_encoder;
9219
9220         list_for_each_entry(source_encoder,
9221                             &dev->mode_config.encoder_list, base.head) {
9222                 if (source_encoder->new_crtc != crtc)
9223                         continue;
9224
9225                 if (!encoders_cloneable(encoder, source_encoder))
9226                         return false;
9227         }
9228
9229         return true;
9230 }
9231
9232 static bool check_encoder_cloning(struct intel_crtc *crtc)
9233 {
9234         struct drm_device *dev = crtc->base.dev;
9235         struct intel_encoder *encoder;
9236
9237         list_for_each_entry(encoder,
9238                             &dev->mode_config.encoder_list, base.head) {
9239                 if (encoder->new_crtc != crtc)
9240                         continue;
9241
9242                 if (!check_single_encoder_cloning(crtc, encoder))
9243                         return false;
9244         }
9245
9246         return true;
9247 }
9248
9249 static struct intel_crtc_config *
9250 intel_modeset_pipe_config(struct drm_crtc *crtc,
9251                           struct drm_framebuffer *fb,
9252                           struct drm_display_mode *mode)
9253 {
9254         struct drm_device *dev = crtc->dev;
9255         struct intel_encoder *encoder;
9256         struct intel_crtc_config *pipe_config;
9257         int plane_bpp, ret = -EINVAL;
9258         bool retry = true;
9259
9260         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9261                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9262                 return ERR_PTR(-EINVAL);
9263         }
9264
9265         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9266         if (!pipe_config)
9267                 return ERR_PTR(-ENOMEM);
9268
9269         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9270         drm_mode_copy(&pipe_config->requested_mode, mode);
9271
9272         pipe_config->cpu_transcoder =
9273                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9274         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9275
9276         /*
9277          * Sanitize sync polarity flags based on requested ones. If neither
9278          * positive or negative polarity is requested, treat this as meaning
9279          * negative polarity.
9280          */
9281         if (!(pipe_config->adjusted_mode.flags &
9282               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9283                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9284
9285         if (!(pipe_config->adjusted_mode.flags &
9286               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9287                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9288
9289         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9290          * plane pixel format and any sink constraints into account. Returns the
9291          * source plane bpp so that dithering can be selected on mismatches
9292          * after encoders and crtc also have had their say. */
9293         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9294                                               fb, pipe_config);
9295         if (plane_bpp < 0)
9296                 goto fail;
9297
9298         /*
9299          * Determine the real pipe dimensions. Note that stereo modes can
9300          * increase the actual pipe size due to the frame doubling and
9301          * insertion of additional space for blanks between the frame. This
9302          * is stored in the crtc timings. We use the requested mode to do this
9303          * computation to clearly distinguish it from the adjusted mode, which
9304          * can be changed by the connectors in the below retry loop.
9305          */
9306         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9307         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9308         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9309
9310 encoder_retry:
9311         /* Ensure the port clock defaults are reset when retrying. */
9312         pipe_config->port_clock = 0;
9313         pipe_config->pixel_multiplier = 1;
9314
9315         /* Fill in default crtc timings, allow encoders to overwrite them. */
9316         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9317
9318         /* Pass our mode to the connectors and the CRTC to give them a chance to
9319          * adjust it according to limitations or connector properties, and also
9320          * a chance to reject the mode entirely.
9321          */
9322         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9323                             base.head) {
9324
9325                 if (&encoder->new_crtc->base != crtc)
9326                         continue;
9327
9328                 if (!(encoder->compute_config(encoder, pipe_config))) {
9329                         DRM_DEBUG_KMS("Encoder config failure\n");
9330                         goto fail;
9331                 }
9332         }
9333
9334         /* Set default port clock if not overwritten by the encoder. Needs to be
9335          * done afterwards in case the encoder adjusts the mode. */
9336         if (!pipe_config->port_clock)
9337                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9338                         * pipe_config->pixel_multiplier;
9339
9340         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9341         if (ret < 0) {
9342                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9343                 goto fail;
9344         }
9345
9346         if (ret == RETRY) {
9347                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9348                         ret = -EINVAL;
9349                         goto fail;
9350                 }
9351
9352                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9353                 retry = false;
9354                 goto encoder_retry;
9355         }
9356
9357         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9358         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9359                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9360
9361         return pipe_config;
9362 fail:
9363         kfree(pipe_config);
9364         return ERR_PTR(ret);
9365 }
9366
9367 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9368  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9369 static void
9370 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9371                              unsigned *prepare_pipes, unsigned *disable_pipes)
9372 {
9373         struct intel_crtc *intel_crtc;
9374         struct drm_device *dev = crtc->dev;
9375         struct intel_encoder *encoder;
9376         struct intel_connector *connector;
9377         struct drm_crtc *tmp_crtc;
9378
9379         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9380
9381         /* Check which crtcs have changed outputs connected to them, these need
9382          * to be part of the prepare_pipes mask. We don't (yet) support global
9383          * modeset across multiple crtcs, so modeset_pipes will only have one
9384          * bit set at most. */
9385         list_for_each_entry(connector, &dev->mode_config.connector_list,
9386                             base.head) {
9387                 if (connector->base.encoder == &connector->new_encoder->base)
9388                         continue;
9389
9390                 if (connector->base.encoder) {
9391                         tmp_crtc = connector->base.encoder->crtc;
9392
9393                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9394                 }
9395
9396                 if (connector->new_encoder)
9397                         *prepare_pipes |=
9398                                 1 << connector->new_encoder->new_crtc->pipe;
9399         }
9400
9401         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9402                             base.head) {
9403                 if (encoder->base.crtc == &encoder->new_crtc->base)
9404                         continue;
9405
9406                 if (encoder->base.crtc) {
9407                         tmp_crtc = encoder->base.crtc;
9408
9409                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9410                 }
9411
9412                 if (encoder->new_crtc)
9413                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9414         }
9415
9416         /* Check for pipes that will be enabled/disabled ... */
9417         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9418                             base.head) {
9419                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9420                         continue;
9421
9422                 if (!intel_crtc->new_enabled)
9423                         *disable_pipes |= 1 << intel_crtc->pipe;
9424                 else
9425                         *prepare_pipes |= 1 << intel_crtc->pipe;
9426         }
9427
9428
9429         /* set_mode is also used to update properties on life display pipes. */
9430         intel_crtc = to_intel_crtc(crtc);
9431         if (intel_crtc->new_enabled)
9432                 *prepare_pipes |= 1 << intel_crtc->pipe;
9433
9434         /*
9435          * For simplicity do a full modeset on any pipe where the output routing
9436          * changed. We could be more clever, but that would require us to be
9437          * more careful with calling the relevant encoder->mode_set functions.
9438          */
9439         if (*prepare_pipes)
9440                 *modeset_pipes = *prepare_pipes;
9441
9442         /* ... and mask these out. */
9443         *modeset_pipes &= ~(*disable_pipes);
9444         *prepare_pipes &= ~(*disable_pipes);
9445
9446         /*
9447          * HACK: We don't (yet) fully support global modesets. intel_set_config
9448          * obies this rule, but the modeset restore mode of
9449          * intel_modeset_setup_hw_state does not.
9450          */
9451         *modeset_pipes &= 1 << intel_crtc->pipe;
9452         *prepare_pipes &= 1 << intel_crtc->pipe;
9453
9454         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9455                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9456 }
9457
9458 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9459 {
9460         struct drm_encoder *encoder;
9461         struct drm_device *dev = crtc->dev;
9462
9463         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9464                 if (encoder->crtc == crtc)
9465                         return true;
9466
9467         return false;
9468 }
9469
9470 static void
9471 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9472 {
9473         struct intel_encoder *intel_encoder;
9474         struct intel_crtc *intel_crtc;
9475         struct drm_connector *connector;
9476
9477         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9478                             base.head) {
9479                 if (!intel_encoder->base.crtc)
9480                         continue;
9481
9482                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9483
9484                 if (prepare_pipes & (1 << intel_crtc->pipe))
9485                         intel_encoder->connectors_active = false;
9486         }
9487
9488         intel_modeset_commit_output_state(dev);
9489
9490         /* Double check state. */
9491         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9492                             base.head) {
9493                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9494                 WARN_ON(intel_crtc->new_config &&
9495                         intel_crtc->new_config != &intel_crtc->config);
9496                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9497         }
9498
9499         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9500                 if (!connector->encoder || !connector->encoder->crtc)
9501                         continue;
9502
9503                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9504
9505                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9506                         struct drm_property *dpms_property =
9507                                 dev->mode_config.dpms_property;
9508
9509                         connector->dpms = DRM_MODE_DPMS_ON;
9510                         drm_object_property_set_value(&connector->base,
9511                                                          dpms_property,
9512                                                          DRM_MODE_DPMS_ON);
9513
9514                         intel_encoder = to_intel_encoder(connector->encoder);
9515                         intel_encoder->connectors_active = true;
9516                 }
9517         }
9518
9519 }
9520
9521 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9522 {
9523         int diff;
9524
9525         if (clock1 == clock2)
9526                 return true;
9527
9528         if (!clock1 || !clock2)
9529                 return false;
9530
9531         diff = abs(clock1 - clock2);
9532
9533         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9534                 return true;
9535
9536         return false;
9537 }
9538
9539 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9540         list_for_each_entry((intel_crtc), \
9541                             &(dev)->mode_config.crtc_list, \
9542                             base.head) \
9543                 if (mask & (1 <<(intel_crtc)->pipe))
9544
9545 static bool
9546 intel_pipe_config_compare(struct drm_device *dev,
9547                           struct intel_crtc_config *current_config,
9548                           struct intel_crtc_config *pipe_config)
9549 {
9550 #define PIPE_CONF_CHECK_X(name) \
9551         if (current_config->name != pipe_config->name) { \
9552                 DRM_ERROR("mismatch in " #name " " \
9553                           "(expected 0x%08x, found 0x%08x)\n", \
9554                           current_config->name, \
9555                           pipe_config->name); \
9556                 return false; \
9557         }
9558
9559 #define PIPE_CONF_CHECK_I(name) \
9560         if (current_config->name != pipe_config->name) { \
9561                 DRM_ERROR("mismatch in " #name " " \
9562                           "(expected %i, found %i)\n", \
9563                           current_config->name, \
9564                           pipe_config->name); \
9565                 return false; \
9566         }
9567
9568 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9569         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9570                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9571                           "(expected %i, found %i)\n", \
9572                           current_config->name & (mask), \
9573                           pipe_config->name & (mask)); \
9574                 return false; \
9575         }
9576
9577 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9578         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9579                 DRM_ERROR("mismatch in " #name " " \
9580                           "(expected %i, found %i)\n", \
9581                           current_config->name, \
9582                           pipe_config->name); \
9583                 return false; \
9584         }
9585
9586 #define PIPE_CONF_QUIRK(quirk)  \
9587         ((current_config->quirks | pipe_config->quirks) & (quirk))
9588
9589         PIPE_CONF_CHECK_I(cpu_transcoder);
9590
9591         PIPE_CONF_CHECK_I(has_pch_encoder);
9592         PIPE_CONF_CHECK_I(fdi_lanes);
9593         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9594         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9595         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9596         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9597         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9598
9599         PIPE_CONF_CHECK_I(has_dp_encoder);
9600         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9601         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9602         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9603         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9604         PIPE_CONF_CHECK_I(dp_m_n.tu);
9605
9606         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9607         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9608         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9609         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9610         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9611         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9612
9613         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9614         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9615         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9616         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9617         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9618         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9619
9620         PIPE_CONF_CHECK_I(pixel_multiplier);
9621
9622         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9623                               DRM_MODE_FLAG_INTERLACE);
9624
9625         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9626                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9627                                       DRM_MODE_FLAG_PHSYNC);
9628                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9629                                       DRM_MODE_FLAG_NHSYNC);
9630                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9631                                       DRM_MODE_FLAG_PVSYNC);
9632                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9633                                       DRM_MODE_FLAG_NVSYNC);
9634         }
9635
9636         PIPE_CONF_CHECK_I(pipe_src_w);
9637         PIPE_CONF_CHECK_I(pipe_src_h);
9638
9639         PIPE_CONF_CHECK_I(gmch_pfit.control);
9640         /* pfit ratios are autocomputed by the hw on gen4+ */
9641         if (INTEL_INFO(dev)->gen < 4)
9642                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9643         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9644         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9645         if (current_config->pch_pfit.enabled) {
9646                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9647                 PIPE_CONF_CHECK_I(pch_pfit.size);
9648         }
9649
9650         /* BDW+ don't expose a synchronous way to read the state */
9651         if (IS_HASWELL(dev))
9652                 PIPE_CONF_CHECK_I(ips_enabled);
9653
9654         PIPE_CONF_CHECK_I(double_wide);
9655
9656         PIPE_CONF_CHECK_I(shared_dpll);
9657         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9658         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9659         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9660         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9661
9662         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9663                 PIPE_CONF_CHECK_I(pipe_bpp);
9664
9665         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9666         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9667
9668 #undef PIPE_CONF_CHECK_X
9669 #undef PIPE_CONF_CHECK_I
9670 #undef PIPE_CONF_CHECK_FLAGS
9671 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9672 #undef PIPE_CONF_QUIRK
9673
9674         return true;
9675 }
9676
9677 static void
9678 check_connector_state(struct drm_device *dev)
9679 {
9680         struct intel_connector *connector;
9681
9682         list_for_each_entry(connector, &dev->mode_config.connector_list,
9683                             base.head) {
9684                 /* This also checks the encoder/connector hw state with the
9685                  * ->get_hw_state callbacks. */
9686                 intel_connector_check_state(connector);
9687
9688                 WARN(&connector->new_encoder->base != connector->base.encoder,
9689                      "connector's staged encoder doesn't match current encoder\n");
9690         }
9691 }
9692
9693 static void
9694 check_encoder_state(struct drm_device *dev)
9695 {
9696         struct intel_encoder *encoder;
9697         struct intel_connector *connector;
9698
9699         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9700                             base.head) {
9701                 bool enabled = false;
9702                 bool active = false;
9703                 enum pipe pipe, tracked_pipe;
9704
9705                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9706                               encoder->base.base.id,
9707                               drm_get_encoder_name(&encoder->base));
9708
9709                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9710                      "encoder's stage crtc doesn't match current crtc\n");
9711                 WARN(encoder->connectors_active && !encoder->base.crtc,
9712                      "encoder's active_connectors set, but no crtc\n");
9713
9714                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9715                                     base.head) {
9716                         if (connector->base.encoder != &encoder->base)
9717                                 continue;
9718                         enabled = true;
9719                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9720                                 active = true;
9721                 }
9722                 WARN(!!encoder->base.crtc != enabled,
9723                      "encoder's enabled state mismatch "
9724                      "(expected %i, found %i)\n",
9725                      !!encoder->base.crtc, enabled);
9726                 WARN(active && !encoder->base.crtc,
9727                      "active encoder with no crtc\n");
9728
9729                 WARN(encoder->connectors_active != active,
9730                      "encoder's computed active state doesn't match tracked active state "
9731                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9732
9733                 active = encoder->get_hw_state(encoder, &pipe);
9734                 WARN(active != encoder->connectors_active,
9735                      "encoder's hw state doesn't match sw tracking "
9736                      "(expected %i, found %i)\n",
9737                      encoder->connectors_active, active);
9738
9739                 if (!encoder->base.crtc)
9740                         continue;
9741
9742                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9743                 WARN(active && pipe != tracked_pipe,
9744                      "active encoder's pipe doesn't match"
9745                      "(expected %i, found %i)\n",
9746                      tracked_pipe, pipe);
9747
9748         }
9749 }
9750
9751 static void
9752 check_crtc_state(struct drm_device *dev)
9753 {
9754         struct drm_i915_private *dev_priv = dev->dev_private;
9755         struct intel_crtc *crtc;
9756         struct intel_encoder *encoder;
9757         struct intel_crtc_config pipe_config;
9758
9759         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9760                             base.head) {
9761                 bool enabled = false;
9762                 bool active = false;
9763
9764                 memset(&pipe_config, 0, sizeof(pipe_config));
9765
9766                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9767                               crtc->base.base.id);
9768
9769                 WARN(crtc->active && !crtc->base.enabled,
9770                      "active crtc, but not enabled in sw tracking\n");
9771
9772                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9773                                     base.head) {
9774                         if (encoder->base.crtc != &crtc->base)
9775                                 continue;
9776                         enabled = true;
9777                         if (encoder->connectors_active)
9778                                 active = true;
9779                 }
9780
9781                 WARN(active != crtc->active,
9782                      "crtc's computed active state doesn't match tracked active state "
9783                      "(expected %i, found %i)\n", active, crtc->active);
9784                 WARN(enabled != crtc->base.enabled,
9785                      "crtc's computed enabled state doesn't match tracked enabled state "
9786                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9787
9788                 active = dev_priv->display.get_pipe_config(crtc,
9789                                                            &pipe_config);
9790
9791                 /* hw state is inconsistent with the pipe A quirk */
9792                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9793                         active = crtc->active;
9794
9795                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9796                                     base.head) {
9797                         enum pipe pipe;
9798                         if (encoder->base.crtc != &crtc->base)
9799                                 continue;
9800                         if (encoder->get_hw_state(encoder, &pipe))
9801                                 encoder->get_config(encoder, &pipe_config);
9802                 }
9803
9804                 WARN(crtc->active != active,
9805                      "crtc active state doesn't match with hw state "
9806                      "(expected %i, found %i)\n", crtc->active, active);
9807
9808                 if (active &&
9809                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9810                         WARN(1, "pipe state doesn't match!\n");
9811                         intel_dump_pipe_config(crtc, &pipe_config,
9812                                                "[hw state]");
9813                         intel_dump_pipe_config(crtc, &crtc->config,
9814                                                "[sw state]");
9815                 }
9816         }
9817 }
9818
9819 static void
9820 check_shared_dpll_state(struct drm_device *dev)
9821 {
9822         struct drm_i915_private *dev_priv = dev->dev_private;
9823         struct intel_crtc *crtc;
9824         struct intel_dpll_hw_state dpll_hw_state;
9825         int i;
9826
9827         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9828                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9829                 int enabled_crtcs = 0, active_crtcs = 0;
9830                 bool active;
9831
9832                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9833
9834                 DRM_DEBUG_KMS("%s\n", pll->name);
9835
9836                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9837
9838                 WARN(pll->active > pll->refcount,
9839                      "more active pll users than references: %i vs %i\n",
9840                      pll->active, pll->refcount);
9841                 WARN(pll->active && !pll->on,
9842                      "pll in active use but not on in sw tracking\n");
9843                 WARN(pll->on && !pll->active,
9844                      "pll in on but not on in use in sw tracking\n");
9845                 WARN(pll->on != active,
9846                      "pll on state mismatch (expected %i, found %i)\n",
9847                      pll->on, active);
9848
9849                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9850                                     base.head) {
9851                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9852                                 enabled_crtcs++;
9853                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9854                                 active_crtcs++;
9855                 }
9856                 WARN(pll->active != active_crtcs,
9857                      "pll active crtcs mismatch (expected %i, found %i)\n",
9858                      pll->active, active_crtcs);
9859                 WARN(pll->refcount != enabled_crtcs,
9860                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9861                      pll->refcount, enabled_crtcs);
9862
9863                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9864                                        sizeof(dpll_hw_state)),
9865                      "pll hw state mismatch\n");
9866         }
9867 }
9868
9869 void
9870 intel_modeset_check_state(struct drm_device *dev)
9871 {
9872         check_connector_state(dev);
9873         check_encoder_state(dev);
9874         check_crtc_state(dev);
9875         check_shared_dpll_state(dev);
9876 }
9877
9878 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9879                                      int dotclock)
9880 {
9881         /*
9882          * FDI already provided one idea for the dotclock.
9883          * Yell if the encoder disagrees.
9884          */
9885         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9886              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9887              pipe_config->adjusted_mode.crtc_clock, dotclock);
9888 }
9889
9890 static int __intel_set_mode(struct drm_crtc *crtc,
9891                             struct drm_display_mode *mode,
9892                             int x, int y, struct drm_framebuffer *fb)
9893 {
9894         struct drm_device *dev = crtc->dev;
9895         struct drm_i915_private *dev_priv = dev->dev_private;
9896         struct drm_display_mode *saved_mode;
9897         struct intel_crtc_config *pipe_config = NULL;
9898         struct intel_crtc *intel_crtc;
9899         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9900         int ret = 0;
9901
9902         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9903         if (!saved_mode)
9904                 return -ENOMEM;
9905
9906         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9907                                      &prepare_pipes, &disable_pipes);
9908
9909         *saved_mode = crtc->mode;
9910
9911         /* Hack: Because we don't (yet) support global modeset on multiple
9912          * crtcs, we don't keep track of the new mode for more than one crtc.
9913          * Hence simply check whether any bit is set in modeset_pipes in all the
9914          * pieces of code that are not yet converted to deal with mutliple crtcs
9915          * changing their mode at the same time. */
9916         if (modeset_pipes) {
9917                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9918                 if (IS_ERR(pipe_config)) {
9919                         ret = PTR_ERR(pipe_config);
9920                         pipe_config = NULL;
9921
9922                         goto out;
9923                 }
9924                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9925                                        "[modeset]");
9926                 to_intel_crtc(crtc)->new_config = pipe_config;
9927         }
9928
9929         /*
9930          * See if the config requires any additional preparation, e.g.
9931          * to adjust global state with pipes off.  We need to do this
9932          * here so we can get the modeset_pipe updated config for the new
9933          * mode set on this crtc.  For other crtcs we need to use the
9934          * adjusted_mode bits in the crtc directly.
9935          */
9936         if (IS_VALLEYVIEW(dev)) {
9937                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9938
9939                 /* may have added more to prepare_pipes than we should */
9940                 prepare_pipes &= ~disable_pipes;
9941         }
9942
9943         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9944                 intel_crtc_disable(&intel_crtc->base);
9945
9946         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9947                 if (intel_crtc->base.enabled)
9948                         dev_priv->display.crtc_disable(&intel_crtc->base);
9949         }
9950
9951         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9952          * to set it here already despite that we pass it down the callchain.
9953          */
9954         if (modeset_pipes) {
9955                 crtc->mode = *mode;
9956                 /* mode_set/enable/disable functions rely on a correct pipe
9957                  * config. */
9958                 to_intel_crtc(crtc)->config = *pipe_config;
9959                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9960
9961                 /*
9962                  * Calculate and store various constants which
9963                  * are later needed by vblank and swap-completion
9964                  * timestamping. They are derived from true hwmode.
9965                  */
9966                 drm_calc_timestamping_constants(crtc,
9967                                                 &pipe_config->adjusted_mode);
9968         }
9969
9970         /* Only after disabling all output pipelines that will be changed can we
9971          * update the the output configuration. */
9972         intel_modeset_update_state(dev, prepare_pipes);
9973
9974         if (dev_priv->display.modeset_global_resources)
9975                 dev_priv->display.modeset_global_resources(dev);
9976
9977         /* Set up the DPLL and any encoders state that needs to adjust or depend
9978          * on the DPLL.
9979          */
9980         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9981                 ret = intel_crtc_mode_set(&intel_crtc->base,
9982                                           x, y, fb);
9983                 if (ret)
9984                         goto done;
9985         }
9986
9987         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9988         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9989                 dev_priv->display.crtc_enable(&intel_crtc->base);
9990
9991         /* FIXME: add subpixel order */
9992 done:
9993         if (ret && crtc->enabled)
9994                 crtc->mode = *saved_mode;
9995
9996 out:
9997         kfree(pipe_config);
9998         kfree(saved_mode);
9999         return ret;
10000 }
10001
10002 static int intel_set_mode(struct drm_crtc *crtc,
10003                           struct drm_display_mode *mode,
10004                           int x, int y, struct drm_framebuffer *fb)
10005 {
10006         int ret;
10007
10008         ret = __intel_set_mode(crtc, mode, x, y, fb);
10009
10010         if (ret == 0)
10011                 intel_modeset_check_state(crtc->dev);
10012
10013         return ret;
10014 }
10015
10016 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10017 {
10018         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10019 }
10020
10021 #undef for_each_intel_crtc_masked
10022
10023 static void intel_set_config_free(struct intel_set_config *config)
10024 {
10025         if (!config)
10026                 return;
10027
10028         kfree(config->save_connector_encoders);
10029         kfree(config->save_encoder_crtcs);
10030         kfree(config->save_crtc_enabled);
10031         kfree(config);
10032 }
10033
10034 static int intel_set_config_save_state(struct drm_device *dev,
10035                                        struct intel_set_config *config)
10036 {
10037         struct drm_crtc *crtc;
10038         struct drm_encoder *encoder;
10039         struct drm_connector *connector;
10040         int count;
10041
10042         config->save_crtc_enabled =
10043                 kcalloc(dev->mode_config.num_crtc,
10044                         sizeof(bool), GFP_KERNEL);
10045         if (!config->save_crtc_enabled)
10046                 return -ENOMEM;
10047
10048         config->save_encoder_crtcs =
10049                 kcalloc(dev->mode_config.num_encoder,
10050                         sizeof(struct drm_crtc *), GFP_KERNEL);
10051         if (!config->save_encoder_crtcs)
10052                 return -ENOMEM;
10053
10054         config->save_connector_encoders =
10055                 kcalloc(dev->mode_config.num_connector,
10056                         sizeof(struct drm_encoder *), GFP_KERNEL);
10057         if (!config->save_connector_encoders)
10058                 return -ENOMEM;
10059
10060         /* Copy data. Note that driver private data is not affected.
10061          * Should anything bad happen only the expected state is
10062          * restored, not the drivers personal bookkeeping.
10063          */
10064         count = 0;
10065         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10066                 config->save_crtc_enabled[count++] = crtc->enabled;
10067         }
10068
10069         count = 0;
10070         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10071                 config->save_encoder_crtcs[count++] = encoder->crtc;
10072         }
10073
10074         count = 0;
10075         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10076                 config->save_connector_encoders[count++] = connector->encoder;
10077         }
10078
10079         return 0;
10080 }
10081
10082 static void intel_set_config_restore_state(struct drm_device *dev,
10083                                            struct intel_set_config *config)
10084 {
10085         struct intel_crtc *crtc;
10086         struct intel_encoder *encoder;
10087         struct intel_connector *connector;
10088         int count;
10089
10090         count = 0;
10091         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10092                 crtc->new_enabled = config->save_crtc_enabled[count++];
10093
10094                 if (crtc->new_enabled)
10095                         crtc->new_config = &crtc->config;
10096                 else
10097                         crtc->new_config = NULL;
10098         }
10099
10100         count = 0;
10101         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10102                 encoder->new_crtc =
10103                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10104         }
10105
10106         count = 0;
10107         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10108                 connector->new_encoder =
10109                         to_intel_encoder(config->save_connector_encoders[count++]);
10110         }
10111 }
10112
10113 static bool
10114 is_crtc_connector_off(struct drm_mode_set *set)
10115 {
10116         int i;
10117
10118         if (set->num_connectors == 0)
10119                 return false;
10120
10121         if (WARN_ON(set->connectors == NULL))
10122                 return false;
10123
10124         for (i = 0; i < set->num_connectors; i++)
10125                 if (set->connectors[i]->encoder &&
10126                     set->connectors[i]->encoder->crtc == set->crtc &&
10127                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10128                         return true;
10129
10130         return false;
10131 }
10132
10133 static void
10134 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10135                                       struct intel_set_config *config)
10136 {
10137
10138         /* We should be able to check here if the fb has the same properties
10139          * and then just flip_or_move it */
10140         if (is_crtc_connector_off(set)) {
10141                 config->mode_changed = true;
10142         } else if (set->crtc->primary->fb != set->fb) {
10143                 /* If we have no fb then treat it as a full mode set */
10144                 if (set->crtc->primary->fb == NULL) {
10145                         struct intel_crtc *intel_crtc =
10146                                 to_intel_crtc(set->crtc);
10147
10148                         if (intel_crtc->active && i915.fastboot) {
10149                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10150                                 config->fb_changed = true;
10151                         } else {
10152                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10153                                 config->mode_changed = true;
10154                         }
10155                 } else if (set->fb == NULL) {
10156                         config->mode_changed = true;
10157                 } else if (set->fb->pixel_format !=
10158                            set->crtc->primary->fb->pixel_format) {
10159                         config->mode_changed = true;
10160                 } else {
10161                         config->fb_changed = true;
10162                 }
10163         }
10164
10165         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10166                 config->fb_changed = true;
10167
10168         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10169                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10170                 drm_mode_debug_printmodeline(&set->crtc->mode);
10171                 drm_mode_debug_printmodeline(set->mode);
10172                 config->mode_changed = true;
10173         }
10174
10175         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10176                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10177 }
10178
10179 static int
10180 intel_modeset_stage_output_state(struct drm_device *dev,
10181                                  struct drm_mode_set *set,
10182                                  struct intel_set_config *config)
10183 {
10184         struct intel_connector *connector;
10185         struct intel_encoder *encoder;
10186         struct intel_crtc *crtc;
10187         int ro;
10188
10189         /* The upper layers ensure that we either disable a crtc or have a list
10190          * of connectors. For paranoia, double-check this. */
10191         WARN_ON(!set->fb && (set->num_connectors != 0));
10192         WARN_ON(set->fb && (set->num_connectors == 0));
10193
10194         list_for_each_entry(connector, &dev->mode_config.connector_list,
10195                             base.head) {
10196                 /* Otherwise traverse passed in connector list and get encoders
10197                  * for them. */
10198                 for (ro = 0; ro < set->num_connectors; ro++) {
10199                         if (set->connectors[ro] == &connector->base) {
10200                                 connector->new_encoder = connector->encoder;
10201                                 break;
10202                         }
10203                 }
10204
10205                 /* If we disable the crtc, disable all its connectors. Also, if
10206                  * the connector is on the changing crtc but not on the new
10207                  * connector list, disable it. */
10208                 if ((!set->fb || ro == set->num_connectors) &&
10209                     connector->base.encoder &&
10210                     connector->base.encoder->crtc == set->crtc) {
10211                         connector->new_encoder = NULL;
10212
10213                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10214                                 connector->base.base.id,
10215                                 drm_get_connector_name(&connector->base));
10216                 }
10217
10218
10219                 if (&connector->new_encoder->base != connector->base.encoder) {
10220                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10221                         config->mode_changed = true;
10222                 }
10223         }
10224         /* connector->new_encoder is now updated for all connectors. */
10225
10226         /* Update crtc of enabled connectors. */
10227         list_for_each_entry(connector, &dev->mode_config.connector_list,
10228                             base.head) {
10229                 struct drm_crtc *new_crtc;
10230
10231                 if (!connector->new_encoder)
10232                         continue;
10233
10234                 new_crtc = connector->new_encoder->base.crtc;
10235
10236                 for (ro = 0; ro < set->num_connectors; ro++) {
10237                         if (set->connectors[ro] == &connector->base)
10238                                 new_crtc = set->crtc;
10239                 }
10240
10241                 /* Make sure the new CRTC will work with the encoder */
10242                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10243                                          new_crtc)) {
10244                         return -EINVAL;
10245                 }
10246                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10247
10248                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10249                         connector->base.base.id,
10250                         drm_get_connector_name(&connector->base),
10251                         new_crtc->base.id);
10252         }
10253
10254         /* Check for any encoders that needs to be disabled. */
10255         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10256                             base.head) {
10257                 int num_connectors = 0;
10258                 list_for_each_entry(connector,
10259                                     &dev->mode_config.connector_list,
10260                                     base.head) {
10261                         if (connector->new_encoder == encoder) {
10262                                 WARN_ON(!connector->new_encoder->new_crtc);
10263                                 num_connectors++;
10264                         }
10265                 }
10266
10267                 if (num_connectors == 0)
10268                         encoder->new_crtc = NULL;
10269                 else if (num_connectors > 1)
10270                         return -EINVAL;
10271
10272                 /* Only now check for crtc changes so we don't miss encoders
10273                  * that will be disabled. */
10274                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10275                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10276                         config->mode_changed = true;
10277                 }
10278         }
10279         /* Now we've also updated encoder->new_crtc for all encoders. */
10280
10281         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10282                             base.head) {
10283                 crtc->new_enabled = false;
10284
10285                 list_for_each_entry(encoder,
10286                                     &dev->mode_config.encoder_list,
10287                                     base.head) {
10288                         if (encoder->new_crtc == crtc) {
10289                                 crtc->new_enabled = true;
10290                                 break;
10291                         }
10292                 }
10293
10294                 if (crtc->new_enabled != crtc->base.enabled) {
10295                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10296                                       crtc->new_enabled ? "en" : "dis");
10297                         config->mode_changed = true;
10298                 }
10299
10300                 if (crtc->new_enabled)
10301                         crtc->new_config = &crtc->config;
10302                 else
10303                         crtc->new_config = NULL;
10304         }
10305
10306         return 0;
10307 }
10308
10309 static void disable_crtc_nofb(struct intel_crtc *crtc)
10310 {
10311         struct drm_device *dev = crtc->base.dev;
10312         struct intel_encoder *encoder;
10313         struct intel_connector *connector;
10314
10315         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10316                       pipe_name(crtc->pipe));
10317
10318         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10319                 if (connector->new_encoder &&
10320                     connector->new_encoder->new_crtc == crtc)
10321                         connector->new_encoder = NULL;
10322         }
10323
10324         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10325                 if (encoder->new_crtc == crtc)
10326                         encoder->new_crtc = NULL;
10327         }
10328
10329         crtc->new_enabled = false;
10330         crtc->new_config = NULL;
10331 }
10332
10333 static int intel_crtc_set_config(struct drm_mode_set *set)
10334 {
10335         struct drm_device *dev;
10336         struct drm_mode_set save_set;
10337         struct intel_set_config *config;
10338         int ret;
10339
10340         BUG_ON(!set);
10341         BUG_ON(!set->crtc);
10342         BUG_ON(!set->crtc->helper_private);
10343
10344         /* Enforce sane interface api - has been abused by the fb helper. */
10345         BUG_ON(!set->mode && set->fb);
10346         BUG_ON(set->fb && set->num_connectors == 0);
10347
10348         if (set->fb) {
10349                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10350                                 set->crtc->base.id, set->fb->base.id,
10351                                 (int)set->num_connectors, set->x, set->y);
10352         } else {
10353                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10354         }
10355
10356         dev = set->crtc->dev;
10357
10358         ret = -ENOMEM;
10359         config = kzalloc(sizeof(*config), GFP_KERNEL);
10360         if (!config)
10361                 goto out_config;
10362
10363         ret = intel_set_config_save_state(dev, config);
10364         if (ret)
10365                 goto out_config;
10366
10367         save_set.crtc = set->crtc;
10368         save_set.mode = &set->crtc->mode;
10369         save_set.x = set->crtc->x;
10370         save_set.y = set->crtc->y;
10371         save_set.fb = set->crtc->primary->fb;
10372
10373         /* Compute whether we need a full modeset, only an fb base update or no
10374          * change at all. In the future we might also check whether only the
10375          * mode changed, e.g. for LVDS where we only change the panel fitter in
10376          * such cases. */
10377         intel_set_config_compute_mode_changes(set, config);
10378
10379         ret = intel_modeset_stage_output_state(dev, set, config);
10380         if (ret)
10381                 goto fail;
10382
10383         if (config->mode_changed) {
10384                 ret = intel_set_mode(set->crtc, set->mode,
10385                                      set->x, set->y, set->fb);
10386         } else if (config->fb_changed) {
10387                 intel_crtc_wait_for_pending_flips(set->crtc);
10388
10389                 ret = intel_pipe_set_base(set->crtc,
10390                                           set->x, set->y, set->fb);
10391                 /*
10392                  * In the fastboot case this may be our only check of the
10393                  * state after boot.  It would be better to only do it on
10394                  * the first update, but we don't have a nice way of doing that
10395                  * (and really, set_config isn't used much for high freq page
10396                  * flipping, so increasing its cost here shouldn't be a big
10397                  * deal).
10398                  */
10399                 if (i915.fastboot && ret == 0)
10400                         intel_modeset_check_state(set->crtc->dev);
10401         }
10402
10403         if (ret) {
10404                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10405                               set->crtc->base.id, ret);
10406 fail:
10407                 intel_set_config_restore_state(dev, config);
10408
10409                 /*
10410                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10411                  * force the pipe off to avoid oopsing in the modeset code
10412                  * due to fb==NULL. This should only happen during boot since
10413                  * we don't yet reconstruct the FB from the hardware state.
10414                  */
10415                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10416                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10417
10418                 /* Try to restore the config */
10419                 if (config->mode_changed &&
10420                     intel_set_mode(save_set.crtc, save_set.mode,
10421                                    save_set.x, save_set.y, save_set.fb))
10422                         DRM_ERROR("failed to restore config after modeset failure\n");
10423         }
10424
10425 out_config:
10426         intel_set_config_free(config);
10427         return ret;
10428 }
10429
10430 static const struct drm_crtc_funcs intel_crtc_funcs = {
10431         .cursor_set = intel_crtc_cursor_set,
10432         .cursor_move = intel_crtc_cursor_move,
10433         .gamma_set = intel_crtc_gamma_set,
10434         .set_config = intel_crtc_set_config,
10435         .destroy = intel_crtc_destroy,
10436         .page_flip = intel_crtc_page_flip,
10437 };
10438
10439 static void intel_cpu_pll_init(struct drm_device *dev)
10440 {
10441         if (HAS_DDI(dev))
10442                 intel_ddi_pll_init(dev);
10443 }
10444
10445 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10446                                       struct intel_shared_dpll *pll,
10447                                       struct intel_dpll_hw_state *hw_state)
10448 {
10449         uint32_t val;
10450
10451         val = I915_READ(PCH_DPLL(pll->id));
10452         hw_state->dpll = val;
10453         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10454         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10455
10456         return val & DPLL_VCO_ENABLE;
10457 }
10458
10459 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10460                                   struct intel_shared_dpll *pll)
10461 {
10462         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10463         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10464 }
10465
10466 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10467                                 struct intel_shared_dpll *pll)
10468 {
10469         /* PCH refclock must be enabled first */
10470         ibx_assert_pch_refclk_enabled(dev_priv);
10471
10472         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10473
10474         /* Wait for the clocks to stabilize. */
10475         POSTING_READ(PCH_DPLL(pll->id));
10476         udelay(150);
10477
10478         /* The pixel multiplier can only be updated once the
10479          * DPLL is enabled and the clocks are stable.
10480          *
10481          * So write it again.
10482          */
10483         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10484         POSTING_READ(PCH_DPLL(pll->id));
10485         udelay(200);
10486 }
10487
10488 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10489                                  struct intel_shared_dpll *pll)
10490 {
10491         struct drm_device *dev = dev_priv->dev;
10492         struct intel_crtc *crtc;
10493
10494         /* Make sure no transcoder isn't still depending on us. */
10495         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10496                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10497                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10498         }
10499
10500         I915_WRITE(PCH_DPLL(pll->id), 0);
10501         POSTING_READ(PCH_DPLL(pll->id));
10502         udelay(200);
10503 }
10504
10505 static char *ibx_pch_dpll_names[] = {
10506         "PCH DPLL A",
10507         "PCH DPLL B",
10508 };
10509
10510 static void ibx_pch_dpll_init(struct drm_device *dev)
10511 {
10512         struct drm_i915_private *dev_priv = dev->dev_private;
10513         int i;
10514
10515         dev_priv->num_shared_dpll = 2;
10516
10517         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10518                 dev_priv->shared_dplls[i].id = i;
10519                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10520                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10521                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10522                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10523                 dev_priv->shared_dplls[i].get_hw_state =
10524                         ibx_pch_dpll_get_hw_state;
10525         }
10526 }
10527
10528 static void intel_shared_dpll_init(struct drm_device *dev)
10529 {
10530         struct drm_i915_private *dev_priv = dev->dev_private;
10531
10532         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10533                 ibx_pch_dpll_init(dev);
10534         else
10535                 dev_priv->num_shared_dpll = 0;
10536
10537         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10538 }
10539
10540 static void intel_crtc_init(struct drm_device *dev, int pipe)
10541 {
10542         struct drm_i915_private *dev_priv = dev->dev_private;
10543         struct intel_crtc *intel_crtc;
10544         int i;
10545
10546         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10547         if (intel_crtc == NULL)
10548                 return;
10549
10550         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10551
10552         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10553         for (i = 0; i < 256; i++) {
10554                 intel_crtc->lut_r[i] = i;
10555                 intel_crtc->lut_g[i] = i;
10556                 intel_crtc->lut_b[i] = i;
10557         }
10558
10559         /*
10560          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10561          * is hooked to plane B. Hence we want plane A feeding pipe B.
10562          */
10563         intel_crtc->pipe = pipe;
10564         intel_crtc->plane = pipe;
10565         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10566                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10567                 intel_crtc->plane = !pipe;
10568         }
10569
10570         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10571                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10572         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10573         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10574
10575         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10576 }
10577
10578 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10579 {
10580         struct drm_encoder *encoder = connector->base.encoder;
10581
10582         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10583
10584         if (!encoder)
10585                 return INVALID_PIPE;
10586
10587         return to_intel_crtc(encoder->crtc)->pipe;
10588 }
10589
10590 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10591                                 struct drm_file *file)
10592 {
10593         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10594         struct drm_mode_object *drmmode_obj;
10595         struct intel_crtc *crtc;
10596
10597         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10598                 return -ENODEV;
10599
10600         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10601                         DRM_MODE_OBJECT_CRTC);
10602
10603         if (!drmmode_obj) {
10604                 DRM_ERROR("no such CRTC id\n");
10605                 return -ENOENT;
10606         }
10607
10608         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10609         pipe_from_crtc_id->pipe = crtc->pipe;
10610
10611         return 0;
10612 }
10613
10614 static int intel_encoder_clones(struct intel_encoder *encoder)
10615 {
10616         struct drm_device *dev = encoder->base.dev;
10617         struct intel_encoder *source_encoder;
10618         int index_mask = 0;
10619         int entry = 0;
10620
10621         list_for_each_entry(source_encoder,
10622                             &dev->mode_config.encoder_list, base.head) {
10623                 if (encoders_cloneable(encoder, source_encoder))
10624                         index_mask |= (1 << entry);
10625
10626                 entry++;
10627         }
10628
10629         return index_mask;
10630 }
10631
10632 static bool has_edp_a(struct drm_device *dev)
10633 {
10634         struct drm_i915_private *dev_priv = dev->dev_private;
10635
10636         if (!IS_MOBILE(dev))
10637                 return false;
10638
10639         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10640                 return false;
10641
10642         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10643                 return false;
10644
10645         return true;
10646 }
10647
10648 const char *intel_output_name(int output)
10649 {
10650         static const char *names[] = {
10651                 [INTEL_OUTPUT_UNUSED] = "Unused",
10652                 [INTEL_OUTPUT_ANALOG] = "Analog",
10653                 [INTEL_OUTPUT_DVO] = "DVO",
10654                 [INTEL_OUTPUT_SDVO] = "SDVO",
10655                 [INTEL_OUTPUT_LVDS] = "LVDS",
10656                 [INTEL_OUTPUT_TVOUT] = "TV",
10657                 [INTEL_OUTPUT_HDMI] = "HDMI",
10658                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10659                 [INTEL_OUTPUT_EDP] = "eDP",
10660                 [INTEL_OUTPUT_DSI] = "DSI",
10661                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10662         };
10663
10664         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10665                 return "Invalid";
10666
10667         return names[output];
10668 }
10669
10670 static void intel_setup_outputs(struct drm_device *dev)
10671 {
10672         struct drm_i915_private *dev_priv = dev->dev_private;
10673         struct intel_encoder *encoder;
10674         bool dpd_is_edp = false;
10675
10676         intel_lvds_init(dev);
10677
10678         if (!IS_ULT(dev))
10679                 intel_crt_init(dev);
10680
10681         if (HAS_DDI(dev)) {
10682                 int found;
10683
10684                 /* Haswell uses DDI functions to detect digital outputs */
10685                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10686                 /* DDI A only supports eDP */
10687                 if (found)
10688                         intel_ddi_init(dev, PORT_A);
10689
10690                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10691                  * register */
10692                 found = I915_READ(SFUSE_STRAP);
10693
10694                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10695                         intel_ddi_init(dev, PORT_B);
10696                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10697                         intel_ddi_init(dev, PORT_C);
10698                 if (found & SFUSE_STRAP_DDID_DETECTED)
10699                         intel_ddi_init(dev, PORT_D);
10700         } else if (HAS_PCH_SPLIT(dev)) {
10701                 int found;
10702                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10703
10704                 if (has_edp_a(dev))
10705                         intel_dp_init(dev, DP_A, PORT_A);
10706
10707                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10708                         /* PCH SDVOB multiplex with HDMIB */
10709                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10710                         if (!found)
10711                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10712                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10713                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10714                 }
10715
10716                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10717                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10718
10719                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10720                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10721
10722                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10723                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10724
10725                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10726                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10727         } else if (IS_VALLEYVIEW(dev)) {
10728                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10729                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10730                                         PORT_B);
10731                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10732                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10733                 }
10734
10735                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10736                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10737                                         PORT_C);
10738                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10739                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10740                 }
10741
10742                 intel_dsi_init(dev);
10743         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10744                 bool found = false;
10745
10746                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10747                         DRM_DEBUG_KMS("probing SDVOB\n");
10748                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10749                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10750                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10751                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10752                         }
10753
10754                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10755                                 intel_dp_init(dev, DP_B, PORT_B);
10756                 }
10757
10758                 /* Before G4X SDVOC doesn't have its own detect register */
10759
10760                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10761                         DRM_DEBUG_KMS("probing SDVOC\n");
10762                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10763                 }
10764
10765                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10766
10767                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10768                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10769                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10770                         }
10771                         if (SUPPORTS_INTEGRATED_DP(dev))
10772                                 intel_dp_init(dev, DP_C, PORT_C);
10773                 }
10774
10775                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10776                     (I915_READ(DP_D) & DP_DETECTED))
10777                         intel_dp_init(dev, DP_D, PORT_D);
10778         } else if (IS_GEN2(dev))
10779                 intel_dvo_init(dev);
10780
10781         if (SUPPORTS_TV(dev))
10782                 intel_tv_init(dev);
10783
10784         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10785                 encoder->base.possible_crtcs = encoder->crtc_mask;
10786                 encoder->base.possible_clones =
10787                         intel_encoder_clones(encoder);
10788         }
10789
10790         intel_init_pch_refclk(dev);
10791
10792         drm_helper_move_panel_connectors_to_head(dev);
10793 }
10794
10795 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10796 {
10797         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10798
10799         drm_framebuffer_cleanup(fb);
10800         WARN_ON(!intel_fb->obj->framebuffer_references--);
10801         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10802         kfree(intel_fb);
10803 }
10804
10805 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10806                                                 struct drm_file *file,
10807                                                 unsigned int *handle)
10808 {
10809         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10810         struct drm_i915_gem_object *obj = intel_fb->obj;
10811
10812         return drm_gem_handle_create(file, &obj->base, handle);
10813 }
10814
10815 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10816         .destroy = intel_user_framebuffer_destroy,
10817         .create_handle = intel_user_framebuffer_create_handle,
10818 };
10819
10820 static int intel_framebuffer_init(struct drm_device *dev,
10821                                   struct intel_framebuffer *intel_fb,
10822                                   struct drm_mode_fb_cmd2 *mode_cmd,
10823                                   struct drm_i915_gem_object *obj)
10824 {
10825         int aligned_height;
10826         int pitch_limit;
10827         int ret;
10828
10829         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10830
10831         if (obj->tiling_mode == I915_TILING_Y) {
10832                 DRM_DEBUG("hardware does not support tiling Y\n");
10833                 return -EINVAL;
10834         }
10835
10836         if (mode_cmd->pitches[0] & 63) {
10837                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10838                           mode_cmd->pitches[0]);
10839                 return -EINVAL;
10840         }
10841
10842         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10843                 pitch_limit = 32*1024;
10844         } else if (INTEL_INFO(dev)->gen >= 4) {
10845                 if (obj->tiling_mode)
10846                         pitch_limit = 16*1024;
10847                 else
10848                         pitch_limit = 32*1024;
10849         } else if (INTEL_INFO(dev)->gen >= 3) {
10850                 if (obj->tiling_mode)
10851                         pitch_limit = 8*1024;
10852                 else
10853                         pitch_limit = 16*1024;
10854         } else
10855                 /* XXX DSPC is limited to 4k tiled */
10856                 pitch_limit = 8*1024;
10857
10858         if (mode_cmd->pitches[0] > pitch_limit) {
10859                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10860                           obj->tiling_mode ? "tiled" : "linear",
10861                           mode_cmd->pitches[0], pitch_limit);
10862                 return -EINVAL;
10863         }
10864
10865         if (obj->tiling_mode != I915_TILING_NONE &&
10866             mode_cmd->pitches[0] != obj->stride) {
10867                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10868                           mode_cmd->pitches[0], obj->stride);
10869                 return -EINVAL;
10870         }
10871
10872         /* Reject formats not supported by any plane early. */
10873         switch (mode_cmd->pixel_format) {
10874         case DRM_FORMAT_C8:
10875         case DRM_FORMAT_RGB565:
10876         case DRM_FORMAT_XRGB8888:
10877         case DRM_FORMAT_ARGB8888:
10878                 break;
10879         case DRM_FORMAT_XRGB1555:
10880         case DRM_FORMAT_ARGB1555:
10881                 if (INTEL_INFO(dev)->gen > 3) {
10882                         DRM_DEBUG("unsupported pixel format: %s\n",
10883                                   drm_get_format_name(mode_cmd->pixel_format));
10884                         return -EINVAL;
10885                 }
10886                 break;
10887         case DRM_FORMAT_XBGR8888:
10888         case DRM_FORMAT_ABGR8888:
10889         case DRM_FORMAT_XRGB2101010:
10890         case DRM_FORMAT_ARGB2101010:
10891         case DRM_FORMAT_XBGR2101010:
10892         case DRM_FORMAT_ABGR2101010:
10893                 if (INTEL_INFO(dev)->gen < 4) {
10894                         DRM_DEBUG("unsupported pixel format: %s\n",
10895                                   drm_get_format_name(mode_cmd->pixel_format));
10896                         return -EINVAL;
10897                 }
10898                 break;
10899         case DRM_FORMAT_YUYV:
10900         case DRM_FORMAT_UYVY:
10901         case DRM_FORMAT_YVYU:
10902         case DRM_FORMAT_VYUY:
10903                 if (INTEL_INFO(dev)->gen < 5) {
10904                         DRM_DEBUG("unsupported pixel format: %s\n",
10905                                   drm_get_format_name(mode_cmd->pixel_format));
10906                         return -EINVAL;
10907                 }
10908                 break;
10909         default:
10910                 DRM_DEBUG("unsupported pixel format: %s\n",
10911                           drm_get_format_name(mode_cmd->pixel_format));
10912                 return -EINVAL;
10913         }
10914
10915         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10916         if (mode_cmd->offsets[0] != 0)
10917                 return -EINVAL;
10918
10919         aligned_height = intel_align_height(dev, mode_cmd->height,
10920                                             obj->tiling_mode);
10921         /* FIXME drm helper for size checks (especially planar formats)? */
10922         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10923                 return -EINVAL;
10924
10925         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10926         intel_fb->obj = obj;
10927         intel_fb->obj->framebuffer_references++;
10928
10929         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10930         if (ret) {
10931                 DRM_ERROR("framebuffer init failed %d\n", ret);
10932                 return ret;
10933         }
10934
10935         return 0;
10936 }
10937
10938 static struct drm_framebuffer *
10939 intel_user_framebuffer_create(struct drm_device *dev,
10940                               struct drm_file *filp,
10941                               struct drm_mode_fb_cmd2 *mode_cmd)
10942 {
10943         struct drm_i915_gem_object *obj;
10944
10945         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10946                                                 mode_cmd->handles[0]));
10947         if (&obj->base == NULL)
10948                 return ERR_PTR(-ENOENT);
10949
10950         return intel_framebuffer_create(dev, mode_cmd, obj);
10951 }
10952
10953 #ifndef CONFIG_DRM_I915_FBDEV
10954 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10955 {
10956 }
10957 #endif
10958
10959 static const struct drm_mode_config_funcs intel_mode_funcs = {
10960         .fb_create = intel_user_framebuffer_create,
10961         .output_poll_changed = intel_fbdev_output_poll_changed,
10962 };
10963
10964 /* Set up chip specific display functions */
10965 static void intel_init_display(struct drm_device *dev)
10966 {
10967         struct drm_i915_private *dev_priv = dev->dev_private;
10968
10969         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10970                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10971         else if (IS_VALLEYVIEW(dev))
10972                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10973         else if (IS_PINEVIEW(dev))
10974                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10975         else
10976                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10977
10978         if (HAS_DDI(dev)) {
10979                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10980                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10981                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10982                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10983                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10984                 dev_priv->display.off = haswell_crtc_off;
10985                 dev_priv->display.update_primary_plane =
10986                         ironlake_update_primary_plane;
10987         } else if (HAS_PCH_SPLIT(dev)) {
10988                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10989                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10990                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10991                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10992                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10993                 dev_priv->display.off = ironlake_crtc_off;
10994                 dev_priv->display.update_primary_plane =
10995                         ironlake_update_primary_plane;
10996         } else if (IS_VALLEYVIEW(dev)) {
10997                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10998                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
10999                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11000                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11001                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11002                 dev_priv->display.off = i9xx_crtc_off;
11003                 dev_priv->display.update_primary_plane =
11004                         i9xx_update_primary_plane;
11005         } else {
11006                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11007                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11008                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11009                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11010                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11011                 dev_priv->display.off = i9xx_crtc_off;
11012                 dev_priv->display.update_primary_plane =
11013                         i9xx_update_primary_plane;
11014         }
11015
11016         /* Returns the core display clock speed */
11017         if (IS_VALLEYVIEW(dev))
11018                 dev_priv->display.get_display_clock_speed =
11019                         valleyview_get_display_clock_speed;
11020         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11021                 dev_priv->display.get_display_clock_speed =
11022                         i945_get_display_clock_speed;
11023         else if (IS_I915G(dev))
11024                 dev_priv->display.get_display_clock_speed =
11025                         i915_get_display_clock_speed;
11026         else if (IS_I945GM(dev) || IS_845G(dev))
11027                 dev_priv->display.get_display_clock_speed =
11028                         i9xx_misc_get_display_clock_speed;
11029         else if (IS_PINEVIEW(dev))
11030                 dev_priv->display.get_display_clock_speed =
11031                         pnv_get_display_clock_speed;
11032         else if (IS_I915GM(dev))
11033                 dev_priv->display.get_display_clock_speed =
11034                         i915gm_get_display_clock_speed;
11035         else if (IS_I865G(dev))
11036                 dev_priv->display.get_display_clock_speed =
11037                         i865_get_display_clock_speed;
11038         else if (IS_I85X(dev))
11039                 dev_priv->display.get_display_clock_speed =
11040                         i855_get_display_clock_speed;
11041         else /* 852, 830 */
11042                 dev_priv->display.get_display_clock_speed =
11043                         i830_get_display_clock_speed;
11044
11045         if (HAS_PCH_SPLIT(dev)) {
11046                 if (IS_GEN5(dev)) {
11047                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11048                         dev_priv->display.write_eld = ironlake_write_eld;
11049                 } else if (IS_GEN6(dev)) {
11050                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11051                         dev_priv->display.write_eld = ironlake_write_eld;
11052                         dev_priv->display.modeset_global_resources =
11053                                 snb_modeset_global_resources;
11054                 } else if (IS_IVYBRIDGE(dev)) {
11055                         /* FIXME: detect B0+ stepping and use auto training */
11056                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11057                         dev_priv->display.write_eld = ironlake_write_eld;
11058                         dev_priv->display.modeset_global_resources =
11059                                 ivb_modeset_global_resources;
11060                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11061                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11062                         dev_priv->display.write_eld = haswell_write_eld;
11063                         dev_priv->display.modeset_global_resources =
11064                                 haswell_modeset_global_resources;
11065                 }
11066         } else if (IS_G4X(dev)) {
11067                 dev_priv->display.write_eld = g4x_write_eld;
11068         } else if (IS_VALLEYVIEW(dev)) {
11069                 dev_priv->display.modeset_global_resources =
11070                         valleyview_modeset_global_resources;
11071                 dev_priv->display.write_eld = ironlake_write_eld;
11072         }
11073
11074         /* Default just returns -ENODEV to indicate unsupported */
11075         dev_priv->display.queue_flip = intel_default_queue_flip;
11076
11077         switch (INTEL_INFO(dev)->gen) {
11078         case 2:
11079                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11080                 break;
11081
11082         case 3:
11083                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11084                 break;
11085
11086         case 4:
11087         case 5:
11088                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11089                 break;
11090
11091         case 6:
11092                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11093                 break;
11094         case 7:
11095         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11096                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11097                 break;
11098         }
11099
11100         intel_panel_init_backlight_funcs(dev);
11101 }
11102
11103 /*
11104  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11105  * resume, or other times.  This quirk makes sure that's the case for
11106  * affected systems.
11107  */
11108 static void quirk_pipea_force(struct drm_device *dev)
11109 {
11110         struct drm_i915_private *dev_priv = dev->dev_private;
11111
11112         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11113         DRM_INFO("applying pipe a force quirk\n");
11114 }
11115
11116 /*
11117  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11118  */
11119 static void quirk_ssc_force_disable(struct drm_device *dev)
11120 {
11121         struct drm_i915_private *dev_priv = dev->dev_private;
11122         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11123         DRM_INFO("applying lvds SSC disable quirk\n");
11124 }
11125
11126 /*
11127  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11128  * brightness value
11129  */
11130 static void quirk_invert_brightness(struct drm_device *dev)
11131 {
11132         struct drm_i915_private *dev_priv = dev->dev_private;
11133         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11134         DRM_INFO("applying inverted panel brightness quirk\n");
11135 }
11136
11137 struct intel_quirk {
11138         int device;
11139         int subsystem_vendor;
11140         int subsystem_device;
11141         void (*hook)(struct drm_device *dev);
11142 };
11143
11144 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11145 struct intel_dmi_quirk {
11146         void (*hook)(struct drm_device *dev);
11147         const struct dmi_system_id (*dmi_id_list)[];
11148 };
11149
11150 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11151 {
11152         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11153         return 1;
11154 }
11155
11156 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11157         {
11158                 .dmi_id_list = &(const struct dmi_system_id[]) {
11159                         {
11160                                 .callback = intel_dmi_reverse_brightness,
11161                                 .ident = "NCR Corporation",
11162                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11163                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11164                                 },
11165                         },
11166                         { }  /* terminating entry */
11167                 },
11168                 .hook = quirk_invert_brightness,
11169         },
11170 };
11171
11172 static struct intel_quirk intel_quirks[] = {
11173         /* HP Mini needs pipe A force quirk (LP: #322104) */
11174         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11175
11176         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11177         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11178
11179         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11180         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11181
11182         /* 830 needs to leave pipe A & dpll A up */
11183         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11184
11185         /* Lenovo U160 cannot use SSC on LVDS */
11186         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11187
11188         /* Sony Vaio Y cannot use SSC on LVDS */
11189         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11190
11191         /* Acer Aspire 5734Z must invert backlight brightness */
11192         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11193
11194         /* Acer/eMachines G725 */
11195         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11196
11197         /* Acer/eMachines e725 */
11198         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11199
11200         /* Acer/Packard Bell NCL20 */
11201         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11202
11203         /* Acer Aspire 4736Z */
11204         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11205
11206         /* Acer Aspire 5336 */
11207         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11208 };
11209
11210 static void intel_init_quirks(struct drm_device *dev)
11211 {
11212         struct pci_dev *d = dev->pdev;
11213         int i;
11214
11215         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11216                 struct intel_quirk *q = &intel_quirks[i];
11217
11218                 if (d->device == q->device &&
11219                     (d->subsystem_vendor == q->subsystem_vendor ||
11220                      q->subsystem_vendor == PCI_ANY_ID) &&
11221                     (d->subsystem_device == q->subsystem_device ||
11222                      q->subsystem_device == PCI_ANY_ID))
11223                         q->hook(dev);
11224         }
11225         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11226                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11227                         intel_dmi_quirks[i].hook(dev);
11228         }
11229 }
11230
11231 /* Disable the VGA plane that we never use */
11232 static void i915_disable_vga(struct drm_device *dev)
11233 {
11234         struct drm_i915_private *dev_priv = dev->dev_private;
11235         u8 sr1;
11236         u32 vga_reg = i915_vgacntrl_reg(dev);
11237
11238         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11239         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11240         outb(SR01, VGA_SR_INDEX);
11241         sr1 = inb(VGA_SR_DATA);
11242         outb(sr1 | 1<<5, VGA_SR_DATA);
11243         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11244         udelay(300);
11245
11246         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11247         POSTING_READ(vga_reg);
11248 }
11249
11250 void intel_modeset_init_hw(struct drm_device *dev)
11251 {
11252         intel_prepare_ddi(dev);
11253
11254         intel_init_clock_gating(dev);
11255
11256         intel_reset_dpio(dev);
11257
11258         mutex_lock(&dev->struct_mutex);
11259         intel_enable_gt_powersave(dev);
11260         mutex_unlock(&dev->struct_mutex);
11261 }
11262
11263 void intel_modeset_suspend_hw(struct drm_device *dev)
11264 {
11265         intel_suspend_hw(dev);
11266 }
11267
11268 void intel_modeset_init(struct drm_device *dev)
11269 {
11270         struct drm_i915_private *dev_priv = dev->dev_private;
11271         int sprite, ret;
11272         enum pipe pipe;
11273         struct intel_crtc *crtc;
11274
11275         drm_mode_config_init(dev);
11276
11277         dev->mode_config.min_width = 0;
11278         dev->mode_config.min_height = 0;
11279
11280         dev->mode_config.preferred_depth = 24;
11281         dev->mode_config.prefer_shadow = 1;
11282
11283         dev->mode_config.funcs = &intel_mode_funcs;
11284
11285         intel_init_quirks(dev);
11286
11287         intel_init_pm(dev);
11288
11289         if (INTEL_INFO(dev)->num_pipes == 0)
11290                 return;
11291
11292         intel_init_display(dev);
11293
11294         if (IS_GEN2(dev)) {
11295                 dev->mode_config.max_width = 2048;
11296                 dev->mode_config.max_height = 2048;
11297         } else if (IS_GEN3(dev)) {
11298                 dev->mode_config.max_width = 4096;
11299                 dev->mode_config.max_height = 4096;
11300         } else {
11301                 dev->mode_config.max_width = 8192;
11302                 dev->mode_config.max_height = 8192;
11303         }
11304
11305         if (IS_GEN2(dev)) {
11306                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11307                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11308         } else {
11309                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11310                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11311         }
11312
11313         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11314
11315         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11316                       INTEL_INFO(dev)->num_pipes,
11317                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11318
11319         for_each_pipe(pipe) {
11320                 intel_crtc_init(dev, pipe);
11321                 for_each_sprite(pipe, sprite) {
11322                         ret = intel_plane_init(dev, pipe, sprite);
11323                         if (ret)
11324                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11325                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11326                 }
11327         }
11328
11329         intel_init_dpio(dev);
11330         intel_reset_dpio(dev);
11331
11332         intel_cpu_pll_init(dev);
11333         intel_shared_dpll_init(dev);
11334
11335         /* Just disable it once at startup */
11336         i915_disable_vga(dev);
11337         intel_setup_outputs(dev);
11338
11339         /* Just in case the BIOS is doing something questionable. */
11340         intel_disable_fbc(dev);
11341
11342         mutex_lock(&dev->mode_config.mutex);
11343         intel_modeset_setup_hw_state(dev, false);
11344         mutex_unlock(&dev->mode_config.mutex);
11345
11346         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11347                             base.head) {
11348                 if (!crtc->active)
11349                         continue;
11350
11351                 /*
11352                  * Note that reserving the BIOS fb up front prevents us
11353                  * from stuffing other stolen allocations like the ring
11354                  * on top.  This prevents some ugliness at boot time, and
11355                  * can even allow for smooth boot transitions if the BIOS
11356                  * fb is large enough for the active pipe configuration.
11357                  */
11358                 if (dev_priv->display.get_plane_config) {
11359                         dev_priv->display.get_plane_config(crtc,
11360                                                            &crtc->plane_config);
11361                         /*
11362                          * If the fb is shared between multiple heads, we'll
11363                          * just get the first one.
11364                          */
11365                         intel_find_plane_obj(crtc, &crtc->plane_config);
11366                 }
11367         }
11368 }
11369
11370 static void
11371 intel_connector_break_all_links(struct intel_connector *connector)
11372 {
11373         connector->base.dpms = DRM_MODE_DPMS_OFF;
11374         connector->base.encoder = NULL;
11375         connector->encoder->connectors_active = false;
11376         connector->encoder->base.crtc = NULL;
11377 }
11378
11379 static void intel_enable_pipe_a(struct drm_device *dev)
11380 {
11381         struct intel_connector *connector;
11382         struct drm_connector *crt = NULL;
11383         struct intel_load_detect_pipe load_detect_temp;
11384
11385         /* We can't just switch on the pipe A, we need to set things up with a
11386          * proper mode and output configuration. As a gross hack, enable pipe A
11387          * by enabling the load detect pipe once. */
11388         list_for_each_entry(connector,
11389                             &dev->mode_config.connector_list,
11390                             base.head) {
11391                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11392                         crt = &connector->base;
11393                         break;
11394                 }
11395         }
11396
11397         if (!crt)
11398                 return;
11399
11400         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11401                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11402
11403
11404 }
11405
11406 static bool
11407 intel_check_plane_mapping(struct intel_crtc *crtc)
11408 {
11409         struct drm_device *dev = crtc->base.dev;
11410         struct drm_i915_private *dev_priv = dev->dev_private;
11411         u32 reg, val;
11412
11413         if (INTEL_INFO(dev)->num_pipes == 1)
11414                 return true;
11415
11416         reg = DSPCNTR(!crtc->plane);
11417         val = I915_READ(reg);
11418
11419         if ((val & DISPLAY_PLANE_ENABLE) &&
11420             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11421                 return false;
11422
11423         return true;
11424 }
11425
11426 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11427 {
11428         struct drm_device *dev = crtc->base.dev;
11429         struct drm_i915_private *dev_priv = dev->dev_private;
11430         u32 reg;
11431
11432         /* Clear any frame start delays used for debugging left by the BIOS */
11433         reg = PIPECONF(crtc->config.cpu_transcoder);
11434         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11435
11436         /* We need to sanitize the plane -> pipe mapping first because this will
11437          * disable the crtc (and hence change the state) if it is wrong. Note
11438          * that gen4+ has a fixed plane -> pipe mapping.  */
11439         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11440                 struct intel_connector *connector;
11441                 bool plane;
11442
11443                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11444                               crtc->base.base.id);
11445
11446                 /* Pipe has the wrong plane attached and the plane is active.
11447                  * Temporarily change the plane mapping and disable everything
11448                  * ...  */
11449                 plane = crtc->plane;
11450                 crtc->plane = !plane;
11451                 dev_priv->display.crtc_disable(&crtc->base);
11452                 crtc->plane = plane;
11453
11454                 /* ... and break all links. */
11455                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11456                                     base.head) {
11457                         if (connector->encoder->base.crtc != &crtc->base)
11458                                 continue;
11459
11460                         intel_connector_break_all_links(connector);
11461                 }
11462
11463                 WARN_ON(crtc->active);
11464                 crtc->base.enabled = false;
11465         }
11466
11467         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11468             crtc->pipe == PIPE_A && !crtc->active) {
11469                 /* BIOS forgot to enable pipe A, this mostly happens after
11470                  * resume. Force-enable the pipe to fix this, the update_dpms
11471                  * call below we restore the pipe to the right state, but leave
11472                  * the required bits on. */
11473                 intel_enable_pipe_a(dev);
11474         }
11475
11476         /* Adjust the state of the output pipe according to whether we
11477          * have active connectors/encoders. */
11478         intel_crtc_update_dpms(&crtc->base);
11479
11480         if (crtc->active != crtc->base.enabled) {
11481                 struct intel_encoder *encoder;
11482
11483                 /* This can happen either due to bugs in the get_hw_state
11484                  * functions or because the pipe is force-enabled due to the
11485                  * pipe A quirk. */
11486                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11487                               crtc->base.base.id,
11488                               crtc->base.enabled ? "enabled" : "disabled",
11489                               crtc->active ? "enabled" : "disabled");
11490
11491                 crtc->base.enabled = crtc->active;
11492
11493                 /* Because we only establish the connector -> encoder ->
11494                  * crtc links if something is active, this means the
11495                  * crtc is now deactivated. Break the links. connector
11496                  * -> encoder links are only establish when things are
11497                  *  actually up, hence no need to break them. */
11498                 WARN_ON(crtc->active);
11499
11500                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11501                         WARN_ON(encoder->connectors_active);
11502                         encoder->base.crtc = NULL;
11503                 }
11504         }
11505         if (crtc->active) {
11506                 /*
11507                  * We start out with underrun reporting disabled to avoid races.
11508                  * For correct bookkeeping mark this on active crtcs.
11509                  *
11510                  * No protection against concurrent access is required - at
11511                  * worst a fifo underrun happens which also sets this to false.
11512                  */
11513                 crtc->cpu_fifo_underrun_disabled = true;
11514                 crtc->pch_fifo_underrun_disabled = true;
11515         }
11516 }
11517
11518 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11519 {
11520         struct intel_connector *connector;
11521         struct drm_device *dev = encoder->base.dev;
11522
11523         /* We need to check both for a crtc link (meaning that the
11524          * encoder is active and trying to read from a pipe) and the
11525          * pipe itself being active. */
11526         bool has_active_crtc = encoder->base.crtc &&
11527                 to_intel_crtc(encoder->base.crtc)->active;
11528
11529         if (encoder->connectors_active && !has_active_crtc) {
11530                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11531                               encoder->base.base.id,
11532                               drm_get_encoder_name(&encoder->base));
11533
11534                 /* Connector is active, but has no active pipe. This is
11535                  * fallout from our resume register restoring. Disable
11536                  * the encoder manually again. */
11537                 if (encoder->base.crtc) {
11538                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11539                                       encoder->base.base.id,
11540                                       drm_get_encoder_name(&encoder->base));
11541                         encoder->disable(encoder);
11542                 }
11543
11544                 /* Inconsistent output/port/pipe state happens presumably due to
11545                  * a bug in one of the get_hw_state functions. Or someplace else
11546                  * in our code, like the register restore mess on resume. Clamp
11547                  * things to off as a safer default. */
11548                 list_for_each_entry(connector,
11549                                     &dev->mode_config.connector_list,
11550                                     base.head) {
11551                         if (connector->encoder != encoder)
11552                                 continue;
11553
11554                         intel_connector_break_all_links(connector);
11555                 }
11556         }
11557         /* Enabled encoders without active connectors will be fixed in
11558          * the crtc fixup. */
11559 }
11560
11561 void i915_redisable_vga_power_on(struct drm_device *dev)
11562 {
11563         struct drm_i915_private *dev_priv = dev->dev_private;
11564         u32 vga_reg = i915_vgacntrl_reg(dev);
11565
11566         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11567                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11568                 i915_disable_vga(dev);
11569         }
11570 }
11571
11572 void i915_redisable_vga(struct drm_device *dev)
11573 {
11574         struct drm_i915_private *dev_priv = dev->dev_private;
11575
11576         /* This function can be called both from intel_modeset_setup_hw_state or
11577          * at a very early point in our resume sequence, where the power well
11578          * structures are not yet restored. Since this function is at a very
11579          * paranoid "someone might have enabled VGA while we were not looking"
11580          * level, just check if the power well is enabled instead of trying to
11581          * follow the "don't touch the power well if we don't need it" policy
11582          * the rest of the driver uses. */
11583         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11584                 return;
11585
11586         i915_redisable_vga_power_on(dev);
11587 }
11588
11589 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11590 {
11591         struct drm_i915_private *dev_priv = dev->dev_private;
11592         enum pipe pipe;
11593         struct intel_crtc *crtc;
11594         struct intel_encoder *encoder;
11595         struct intel_connector *connector;
11596         int i;
11597
11598         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11599                             base.head) {
11600                 memset(&crtc->config, 0, sizeof(crtc->config));
11601
11602                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11603                                                                  &crtc->config);
11604
11605                 crtc->base.enabled = crtc->active;
11606                 crtc->primary_enabled = crtc->active;
11607
11608                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11609                               crtc->base.base.id,
11610                               crtc->active ? "enabled" : "disabled");
11611         }
11612
11613         /* FIXME: Smash this into the new shared dpll infrastructure. */
11614         if (HAS_DDI(dev))
11615                 intel_ddi_setup_hw_pll_state(dev);
11616
11617         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11618                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11619
11620                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11621                 pll->active = 0;
11622                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11623                                     base.head) {
11624                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11625                                 pll->active++;
11626                 }
11627                 pll->refcount = pll->active;
11628
11629                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11630                               pll->name, pll->refcount, pll->on);
11631         }
11632
11633         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11634                             base.head) {
11635                 pipe = 0;
11636
11637                 if (encoder->get_hw_state(encoder, &pipe)) {
11638                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11639                         encoder->base.crtc = &crtc->base;
11640                         encoder->get_config(encoder, &crtc->config);
11641                 } else {
11642                         encoder->base.crtc = NULL;
11643                 }
11644
11645                 encoder->connectors_active = false;
11646                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11647                               encoder->base.base.id,
11648                               drm_get_encoder_name(&encoder->base),
11649                               encoder->base.crtc ? "enabled" : "disabled",
11650                               pipe_name(pipe));
11651         }
11652
11653         list_for_each_entry(connector, &dev->mode_config.connector_list,
11654                             base.head) {
11655                 if (connector->get_hw_state(connector)) {
11656                         connector->base.dpms = DRM_MODE_DPMS_ON;
11657                         connector->encoder->connectors_active = true;
11658                         connector->base.encoder = &connector->encoder->base;
11659                 } else {
11660                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11661                         connector->base.encoder = NULL;
11662                 }
11663                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11664                               connector->base.base.id,
11665                               drm_get_connector_name(&connector->base),
11666                               connector->base.encoder ? "enabled" : "disabled");
11667         }
11668 }
11669
11670 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11671  * and i915 state tracking structures. */
11672 void intel_modeset_setup_hw_state(struct drm_device *dev,
11673                                   bool force_restore)
11674 {
11675         struct drm_i915_private *dev_priv = dev->dev_private;
11676         enum pipe pipe;
11677         struct intel_crtc *crtc;
11678         struct intel_encoder *encoder;
11679         int i;
11680
11681         intel_modeset_readout_hw_state(dev);
11682
11683         /*
11684          * Now that we have the config, copy it to each CRTC struct
11685          * Note that this could go away if we move to using crtc_config
11686          * checking everywhere.
11687          */
11688         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11689                             base.head) {
11690                 if (crtc->active && i915.fastboot) {
11691                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11692                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11693                                       crtc->base.base.id);
11694                         drm_mode_debug_printmodeline(&crtc->base.mode);
11695                 }
11696         }
11697
11698         /* HW state is read out, now we need to sanitize this mess. */
11699         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11700                             base.head) {
11701                 intel_sanitize_encoder(encoder);
11702         }
11703
11704         for_each_pipe(pipe) {
11705                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11706                 intel_sanitize_crtc(crtc);
11707                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11708         }
11709
11710         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11711                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11712
11713                 if (!pll->on || pll->active)
11714                         continue;
11715
11716                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11717
11718                 pll->disable(dev_priv, pll);
11719                 pll->on = false;
11720         }
11721
11722         if (HAS_PCH_SPLIT(dev))
11723                 ilk_wm_get_hw_state(dev);
11724
11725         if (force_restore) {
11726                 i915_redisable_vga(dev);
11727
11728                 /*
11729                  * We need to use raw interfaces for restoring state to avoid
11730                  * checking (bogus) intermediate states.
11731                  */
11732                 for_each_pipe(pipe) {
11733                         struct drm_crtc *crtc =
11734                                 dev_priv->pipe_to_crtc_mapping[pipe];
11735
11736                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11737                                          crtc->primary->fb);
11738                 }
11739         } else {
11740                 intel_modeset_update_staged_output_state(dev);
11741         }
11742
11743         intel_modeset_check_state(dev);
11744 }
11745
11746 void intel_modeset_gem_init(struct drm_device *dev)
11747 {
11748         struct drm_crtc *c;
11749         struct intel_framebuffer *fb;
11750
11751         mutex_lock(&dev->struct_mutex);
11752         intel_init_gt_powersave(dev);
11753         mutex_unlock(&dev->struct_mutex);
11754
11755         intel_modeset_init_hw(dev);
11756
11757         intel_setup_overlay(dev);
11758
11759         /*
11760          * Make sure any fbs we allocated at startup are properly
11761          * pinned & fenced.  When we do the allocation it's too early
11762          * for this.
11763          */
11764         mutex_lock(&dev->struct_mutex);
11765         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
11766                 if (!c->primary->fb)
11767                         continue;
11768
11769                 fb = to_intel_framebuffer(c->primary->fb);
11770                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
11771                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
11772                                   to_intel_crtc(c)->pipe);
11773                         drm_framebuffer_unreference(c->primary->fb);
11774                         c->primary->fb = NULL;
11775                 }
11776         }
11777         mutex_unlock(&dev->struct_mutex);
11778 }
11779
11780 void intel_connector_unregister(struct intel_connector *intel_connector)
11781 {
11782         struct drm_connector *connector = &intel_connector->base;
11783
11784         intel_panel_destroy_backlight(connector);
11785         drm_sysfs_connector_remove(connector);
11786 }
11787
11788 void intel_modeset_cleanup(struct drm_device *dev)
11789 {
11790         struct drm_i915_private *dev_priv = dev->dev_private;
11791         struct drm_crtc *crtc;
11792         struct drm_connector *connector;
11793
11794         /*
11795          * Interrupts and polling as the first thing to avoid creating havoc.
11796          * Too much stuff here (turning of rps, connectors, ...) would
11797          * experience fancy races otherwise.
11798          */
11799         drm_irq_uninstall(dev);
11800         cancel_work_sync(&dev_priv->hotplug_work);
11801         /*
11802          * Due to the hpd irq storm handling the hotplug work can re-arm the
11803          * poll handlers. Hence disable polling after hpd handling is shut down.
11804          */
11805         drm_kms_helper_poll_fini(dev);
11806
11807         mutex_lock(&dev->struct_mutex);
11808
11809         intel_unregister_dsm_handler();
11810
11811         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11812                 /* Skip inactive CRTCs */
11813                 if (!crtc->primary->fb)
11814                         continue;
11815
11816                 intel_increase_pllclock(crtc);
11817         }
11818
11819         intel_disable_fbc(dev);
11820
11821         intel_disable_gt_powersave(dev);
11822
11823         ironlake_teardown_rc6(dev);
11824
11825         mutex_unlock(&dev->struct_mutex);
11826
11827         /* flush any delayed tasks or pending work */
11828         flush_scheduled_work();
11829
11830         /* destroy the backlight and sysfs files before encoders/connectors */
11831         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11832                 struct intel_connector *intel_connector;
11833
11834                 intel_connector = to_intel_connector(connector);
11835                 intel_connector->unregister(intel_connector);
11836         }
11837
11838         drm_mode_config_cleanup(dev);
11839
11840         intel_cleanup_overlay(dev);
11841
11842         mutex_lock(&dev->struct_mutex);
11843         intel_cleanup_gt_powersave(dev);
11844         mutex_unlock(&dev->struct_mutex);
11845 }
11846
11847 /*
11848  * Return which encoder is currently attached for connector.
11849  */
11850 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11851 {
11852         return &intel_attached_encoder(connector)->base;
11853 }
11854
11855 void intel_connector_attach_encoder(struct intel_connector *connector,
11856                                     struct intel_encoder *encoder)
11857 {
11858         connector->encoder = encoder;
11859         drm_mode_connector_attach_encoder(&connector->base,
11860                                           &encoder->base);
11861 }
11862
11863 /*
11864  * set vga decode state - true == enable VGA decode
11865  */
11866 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11867 {
11868         struct drm_i915_private *dev_priv = dev->dev_private;
11869         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11870         u16 gmch_ctrl;
11871
11872         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11873                 DRM_ERROR("failed to read control word\n");
11874                 return -EIO;
11875         }
11876
11877         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11878                 return 0;
11879
11880         if (state)
11881                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11882         else
11883                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11884
11885         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11886                 DRM_ERROR("failed to write control word\n");
11887                 return -EIO;
11888         }
11889
11890         return 0;
11891 }
11892
11893 struct intel_display_error_state {
11894
11895         u32 power_well_driver;
11896
11897         int num_transcoders;
11898
11899         struct intel_cursor_error_state {
11900                 u32 control;
11901                 u32 position;
11902                 u32 base;
11903                 u32 size;
11904         } cursor[I915_MAX_PIPES];
11905
11906         struct intel_pipe_error_state {
11907                 bool power_domain_on;
11908                 u32 source;
11909         } pipe[I915_MAX_PIPES];
11910
11911         struct intel_plane_error_state {
11912                 u32 control;
11913                 u32 stride;
11914                 u32 size;
11915                 u32 pos;
11916                 u32 addr;
11917                 u32 surface;
11918                 u32 tile_offset;
11919         } plane[I915_MAX_PIPES];
11920
11921         struct intel_transcoder_error_state {
11922                 bool power_domain_on;
11923                 enum transcoder cpu_transcoder;
11924
11925                 u32 conf;
11926
11927                 u32 htotal;
11928                 u32 hblank;
11929                 u32 hsync;
11930                 u32 vtotal;
11931                 u32 vblank;
11932                 u32 vsync;
11933         } transcoder[4];
11934 };
11935
11936 struct intel_display_error_state *
11937 intel_display_capture_error_state(struct drm_device *dev)
11938 {
11939         struct drm_i915_private *dev_priv = dev->dev_private;
11940         struct intel_display_error_state *error;
11941         int transcoders[] = {
11942                 TRANSCODER_A,
11943                 TRANSCODER_B,
11944                 TRANSCODER_C,
11945                 TRANSCODER_EDP,
11946         };
11947         int i;
11948
11949         if (INTEL_INFO(dev)->num_pipes == 0)
11950                 return NULL;
11951
11952         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11953         if (error == NULL)
11954                 return NULL;
11955
11956         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11957                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11958
11959         for_each_pipe(i) {
11960                 error->pipe[i].power_domain_on =
11961                         intel_display_power_enabled_sw(dev_priv,
11962                                                        POWER_DOMAIN_PIPE(i));
11963                 if (!error->pipe[i].power_domain_on)
11964                         continue;
11965
11966                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11967                         error->cursor[i].control = I915_READ(CURCNTR(i));
11968                         error->cursor[i].position = I915_READ(CURPOS(i));
11969                         error->cursor[i].base = I915_READ(CURBASE(i));
11970                 } else {
11971                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11972                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11973                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11974                 }
11975
11976                 error->plane[i].control = I915_READ(DSPCNTR(i));
11977                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11978                 if (INTEL_INFO(dev)->gen <= 3) {
11979                         error->plane[i].size = I915_READ(DSPSIZE(i));
11980                         error->plane[i].pos = I915_READ(DSPPOS(i));
11981                 }
11982                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11983                         error->plane[i].addr = I915_READ(DSPADDR(i));
11984                 if (INTEL_INFO(dev)->gen >= 4) {
11985                         error->plane[i].surface = I915_READ(DSPSURF(i));
11986                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11987                 }
11988
11989                 error->pipe[i].source = I915_READ(PIPESRC(i));
11990         }
11991
11992         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11993         if (HAS_DDI(dev_priv->dev))
11994                 error->num_transcoders++; /* Account for eDP. */
11995
11996         for (i = 0; i < error->num_transcoders; i++) {
11997                 enum transcoder cpu_transcoder = transcoders[i];
11998
11999                 error->transcoder[i].power_domain_on =
12000                         intel_display_power_enabled_sw(dev_priv,
12001                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12002                 if (!error->transcoder[i].power_domain_on)
12003                         continue;
12004
12005                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12006
12007                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12008                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12009                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12010                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12011                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12012                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12013                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12014         }
12015
12016         return error;
12017 }
12018
12019 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12020
12021 void
12022 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12023                                 struct drm_device *dev,
12024                                 struct intel_display_error_state *error)
12025 {
12026         int i;
12027
12028         if (!error)
12029                 return;
12030
12031         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12032         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12033                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12034                            error->power_well_driver);
12035         for_each_pipe(i) {
12036                 err_printf(m, "Pipe [%d]:\n", i);
12037                 err_printf(m, "  Power: %s\n",
12038                            error->pipe[i].power_domain_on ? "on" : "off");
12039                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12040
12041                 err_printf(m, "Plane [%d]:\n", i);
12042                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12043                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12044                 if (INTEL_INFO(dev)->gen <= 3) {
12045                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12046                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12047                 }
12048                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12049                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12050                 if (INTEL_INFO(dev)->gen >= 4) {
12051                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12052                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12053                 }
12054
12055                 err_printf(m, "Cursor [%d]:\n", i);
12056                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12057                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12058                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12059         }
12060
12061         for (i = 0; i < error->num_transcoders; i++) {
12062                 err_printf(m, "CPU transcoder: %c\n",
12063                            transcoder_name(error->transcoder[i].cpu_transcoder));
12064                 err_printf(m, "  Power: %s\n",
12065                            error->transcoder[i].power_domain_on ? "on" : "off");
12066                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12067                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12068                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12069                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12070                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12071                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12072                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12073         }
12074 }