drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62         /**
  63          * find_pll() - Find the best values for the PLL
  64          * @limit: limits for the PLL
  65          * @crtc: current CRTC
  66          * @target: target frequency in kHz
  67          * @refclk: reference clock frequency in kHz
  68          * @match_clock: if provided, @best_clock P divider must
  69          *               match the P divider from @match_clock
  70          *               used for LVDS downclocking
  71          * @best_clock: best PLL values found
  72          *
  73          * Returns true on success, false on failure.
  74          */
  75         bool (*find_pll)(const intel_limit_t *limit,
  76                          struct drm_crtc *crtc,
  77                          int target, int refclk,
  78                          intel_clock_t *match_clock,
  79                          intel_clock_t *best_clock);
  80 };
  81
  82 /* FDI */
  83 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  84
  85 int
  86 intel_pch_rawclk(struct drm_device *dev)
  87 {
  88         struct drm_i915_private *dev_priv = dev->dev_private;
  89
  90         WARN_ON(!HAS_PCH_SPLIT(dev));
  91
  92         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  93 }
  94
  95 static bool
  96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                     int target, int refclk, intel_clock_t *match_clock,
  98                     intel_clock_t *best_clock);
  99 static bool
 100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 101                         int target, int refclk, intel_clock_t *match_clock,
 102                         intel_clock_t *best_clock);
 103
 104 static bool
 105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 106                         int target, int refclk, intel_clock_t *match_clock,
 107                         intel_clock_t *best_clock);
 108
 109 static inline u32 /* units of 100MHz */
 110 intel_fdi_link_freq(struct drm_device *dev)
 111 {
 112         if (IS_GEN5(dev)) {
 113                 struct drm_i915_private *dev_priv = dev->dev_private;
 114                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 115         } else
 116                 return 27;
 117 }
 118
 119 static const intel_limit_t intel_limits_i8xx_dvo = {
 120         .dot = { .min = 25000, .max = 350000 },
 121         .vco = { .min = 930000, .max = 1400000 },
 122         .n = { .min = 3, .max = 16 },
 123         .m = { .min = 96, .max = 140 },
 124         .m1 = { .min = 18, .max = 26 },
 125         .m2 = { .min = 6, .max = 16 },
 126         .p = { .min = 4, .max = 128 },
 127         .p1 = { .min = 2, .max = 33 },
 128         .p2 = { .dot_limit = 165000,
 129                 .p2_slow = 4, .p2_fast = 2 },
 130         .find_pll = intel_find_best_PLL,
 131 };
 132
 133 static const intel_limit_t intel_limits_i8xx_lvds = {
 134         .dot = { .min = 25000, .max = 350000 },
 135         .vco = { .min = 930000, .max = 1400000 },
 136         .n = { .min = 3, .max = 16 },
 137         .m = { .min = 96, .max = 140 },
 138         .m1 = { .min = 18, .max = 26 },
 139         .m2 = { .min = 6, .max = 16 },
 140         .p = { .min = 4, .max = 128 },
 141         .p1 = { .min = 1, .max = 6 },
 142         .p2 = { .dot_limit = 165000,
 143                 .p2_slow = 14, .p2_fast = 7 },
 144         .find_pll = intel_find_best_PLL,
 145 };
 146
 147 static const intel_limit_t intel_limits_i9xx_sdvo = {
 148         .dot = { .min = 20000, .max = 400000 },
 149         .vco = { .min = 1400000, .max = 2800000 },
 150         .n = { .min = 1, .max = 6 },
 151         .m = { .min = 70, .max = 120 },
 152         .m1 = { .min = 8, .max = 18 },
 153         .m2 = { .min = 3, .max = 7 },
 154         .p = { .min = 5, .max = 80 },
 155         .p1 = { .min = 1, .max = 8 },
 156         .p2 = { .dot_limit = 200000,
 157                 .p2_slow = 10, .p2_fast = 5 },
 158         .find_pll = intel_find_best_PLL,
 159 };
 160
 161 static const intel_limit_t intel_limits_i9xx_lvds = {
 162         .dot = { .min = 20000, .max = 400000 },
 163         .vco = { .min = 1400000, .max = 2800000 },
 164         .n = { .min = 1, .max = 6 },
 165         .m = { .min = 70, .max = 120 },
 166         .m1 = { .min = 8, .max = 18 },
 167         .m2 = { .min = 3, .max = 7 },
 168         .p = { .min = 7, .max = 98 },
 169         .p1 = { .min = 1, .max = 8 },
 170         .p2 = { .dot_limit = 112000,
 171                 .p2_slow = 14, .p2_fast = 7 },
 172         .find_pll = intel_find_best_PLL,
 173 };
 174
 175
 176 static const intel_limit_t intel_limits_g4x_sdvo = {
 177         .dot = { .min = 25000, .max = 270000 },
 178         .vco = { .min = 1750000, .max = 3500000},
 179         .n = { .min = 1, .max = 4 },
 180         .m = { .min = 104, .max = 138 },
 181         .m1 = { .min = 17, .max = 23 },
 182         .m2 = { .min = 5, .max = 11 },
 183         .p = { .min = 10, .max = 30 },
 184         .p1 = { .min = 1, .max = 3},
 185         .p2 = { .dot_limit = 270000,
 186                 .p2_slow = 10,
 187                 .p2_fast = 10
 188         },
 189         .find_pll = intel_g4x_find_best_PLL,
 190 };
 191
 192 static const intel_limit_t intel_limits_g4x_hdmi = {
 193         .dot = { .min = 22000, .max = 400000 },
 194         .vco = { .min = 1750000, .max = 3500000},
 195         .n = { .min = 1, .max = 4 },
 196         .m = { .min = 104, .max = 138 },
 197         .m1 = { .min = 16, .max = 23 },
 198         .m2 = { .min = 5, .max = 11 },
 199         .p = { .min = 5, .max = 80 },
 200         .p1 = { .min = 1, .max = 8},
 201         .p2 = { .dot_limit = 165000,
 202                 .p2_slow = 10, .p2_fast = 5 },
 203         .find_pll = intel_g4x_find_best_PLL,
 204 };
 205
 206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 207         .dot = { .min = 20000, .max = 115000 },
 208         .vco = { .min = 1750000, .max = 3500000 },
 209         .n = { .min = 1, .max = 3 },
 210         .m = { .min = 104, .max = 138 },
 211         .m1 = { .min = 17, .max = 23 },
 212         .m2 = { .min = 5, .max = 11 },
 213         .p = { .min = 28, .max = 112 },
 214         .p1 = { .min = 2, .max = 8 },
 215         .p2 = { .dot_limit = 0,
 216                 .p2_slow = 14, .p2_fast = 14
 217         },
 218         .find_pll = intel_g4x_find_best_PLL,
 219 };
 220
 221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 222         .dot = { .min = 80000, .max = 224000 },
 223         .vco = { .min = 1750000, .max = 3500000 },
 224         .n = { .min = 1, .max = 3 },
 225         .m = { .min = 104, .max = 138 },
 226         .m1 = { .min = 17, .max = 23 },
 227         .m2 = { .min = 5, .max = 11 },
 228         .p = { .min = 14, .max = 42 },
 229         .p1 = { .min = 2, .max = 6 },
 230         .p2 = { .dot_limit = 0,
 231                 .p2_slow = 7, .p2_fast = 7
 232         },
 233         .find_pll = intel_g4x_find_best_PLL,
 234 };
 235
 236 static const intel_limit_t intel_limits_pineview_sdvo = {
 237         .dot = { .min = 20000, .max = 400000},
 238         .vco = { .min = 1700000, .max = 3500000 },
 239         /* Pineview's Ncounter is a ring counter */
 240         .n = { .min = 3, .max = 6 },
 241         .m = { .min = 2, .max = 256 },
 242         /* Pineview only has one combined m divider, which we treat as m2. */
 243         .m1 = { .min = 0, .max = 0 },
 244         .m2 = { .min = 0, .max = 254 },
 245         .p = { .min = 5, .max = 80 },
 246         .p1 = { .min = 1, .max = 8 },
 247         .p2 = { .dot_limit = 200000,
 248                 .p2_slow = 10, .p2_fast = 5 },
 249         .find_pll = intel_find_best_PLL,
 250 };
 251
 252 static const intel_limit_t intel_limits_pineview_lvds = {
 253         .dot = { .min = 20000, .max = 400000 },
 254         .vco = { .min = 1700000, .max = 3500000 },
 255         .n = { .min = 3, .max = 6 },
 256         .m = { .min = 2, .max = 256 },
 257         .m1 = { .min = 0, .max = 0 },
 258         .m2 = { .min = 0, .max = 254 },
 259         .p = { .min = 7, .max = 112 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 112000,
 262                 .p2_slow = 14, .p2_fast = 14 },
 263         .find_pll = intel_find_best_PLL,
 264 };
 265
 266 /* Ironlake / Sandybridge
 267  *
 268  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 269  * the range value for them is (actual_value - 2).
 270  */
 271 static const intel_limit_t intel_limits_ironlake_dac = {
 272         .dot = { .min = 25000, .max = 350000 },
 273         .vco = { .min = 1760000, .max = 3510000 },
 274         .n = { .min = 1, .max = 5 },
 275         .m = { .min = 79, .max = 127 },
 276         .m1 = { .min = 12, .max = 22 },
 277         .m2 = { .min = 5, .max = 9 },
 278         .p = { .min = 5, .max = 80 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 225000,
 281                 .p2_slow = 10, .p2_fast = 5 },
 282         .find_pll = intel_g4x_find_best_PLL,
 283 };
 284
 285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 286         .dot = { .min = 25000, .max = 350000 },
 287         .vco = { .min = 1760000, .max = 3510000 },
 288         .n = { .min = 1, .max = 3 },
 289         .m = { .min = 79, .max = 118 },
 290         .m1 = { .min = 12, .max = 22 },
 291         .m2 = { .min = 5, .max = 9 },
 292         .p = { .min = 28, .max = 112 },
 293         .p1 = { .min = 2, .max = 8 },
 294         .p2 = { .dot_limit = 225000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296         .find_pll = intel_g4x_find_best_PLL,
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 127 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 56 },
 307         .p1 = { .min = 2, .max = 8 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310         .find_pll = intel_g4x_find_best_PLL,
 311 };
 312
 313 /* LVDS 100mhz refclk limits. */
 314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 2 },
 318         .m = { .min = 79, .max = 126 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 28, .max = 112 },
 322         .p1 = { .min = 2, .max = 8 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 14, .p2_fast = 14 },
 325         .find_pll = intel_g4x_find_best_PLL,
 326 };
 327
 328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 329         .dot = { .min = 25000, .max = 350000 },
 330         .vco = { .min = 1760000, .max = 3510000 },
 331         .n = { .min = 1, .max = 3 },
 332         .m = { .min = 79, .max = 126 },
 333         .m1 = { .min = 12, .max = 22 },
 334         .m2 = { .min = 5, .max = 9 },
 335         .p = { .min = 14, .max = 42 },
 336         .p1 = { .min = 2, .max = 6 },
 337         .p2 = { .dot_limit = 225000,
 338                 .p2_slow = 7, .p2_fast = 7 },
 339         .find_pll = intel_g4x_find_best_PLL,
 340 };
 341
 342 static const intel_limit_t intel_limits_vlv_dac = {
 343         .dot = { .min = 25000, .max = 270000 },
 344         .vco = { .min = 4000000, .max = 6000000 },
 345         .n = { .min = 1, .max = 7 },
 346         .m = { .min = 22, .max = 450 }, /* guess */
 347         .m1 = { .min = 2, .max = 3 },
 348         .m2 = { .min = 11, .max = 156 },
 349         .p = { .min = 10, .max = 30 },
 350         .p1 = { .min = 1, .max = 3 },
 351         .p2 = { .dot_limit = 270000,
 352                 .p2_slow = 2, .p2_fast = 20 },
 353         .find_pll = intel_vlv_find_best_pll,
 354 };
 355
 356 static const intel_limit_t intel_limits_vlv_hdmi = {
 357         .dot = { .min = 25000, .max = 270000 },
 358         .vco = { .min = 4000000, .max = 6000000 },
 359         .n = { .min = 1, .max = 7 },
 360         .m = { .min = 60, .max = 300 }, /* guess */
 361         .m1 = { .min = 2, .max = 3 },
 362         .m2 = { .min = 11, .max = 156 },
 363         .p = { .min = 10, .max = 30 },
 364         .p1 = { .min = 2, .max = 3 },
 365         .p2 = { .dot_limit = 270000,
 366                 .p2_slow = 2, .p2_fast = 20 },
 367         .find_pll = intel_vlv_find_best_pll,
 368 };
 369
 370 static const intel_limit_t intel_limits_vlv_dp = {
 371         .dot = { .min = 25000, .max = 270000 },
 372         .vco = { .min = 4000000, .max = 6000000 },
 373         .n = { .min = 1, .max = 7 },
 374         .m = { .min = 22, .max = 450 },
 375         .m1 = { .min = 2, .max = 3 },
 376         .m2 = { .min = 11, .max = 156 },
 377         .p = { .min = 10, .max = 30 },
 378         .p1 = { .min = 1, .max = 3 },
 379         .p2 = { .dot_limit = 270000,
 380                 .p2_slow = 2, .p2_fast = 20 },
 381         .find_pll = intel_vlv_find_best_pll,
 382 };
 383
 384 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 385 {
 386         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 387
 388         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 389                 DRM_ERROR("DPIO idle wait timed out\n");
 390                 return 0;
 391         }
 392
 393         I915_WRITE(DPIO_REG, reg);
 394         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 395                    DPIO_BYTE);
 396         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 397                 DRM_ERROR("DPIO read wait timed out\n");
 398                 return 0;
 399         }
 400
 401         return I915_READ(DPIO_DATA);
 402 }
 403
 404 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
 405 {
 406         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 407
 408         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 409                 DRM_ERROR("DPIO idle wait timed out\n");
 410                 return;
 411         }
 412
 413         I915_WRITE(DPIO_DATA, val);
 414         I915_WRITE(DPIO_REG, reg);
 415         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 416                    DPIO_BYTE);
 417         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 418                 DRM_ERROR("DPIO write wait timed out\n");
 419 }
 420
 421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 422                                                 int refclk)
 423 {
 424         struct drm_device *dev = crtc->dev;
 425         const intel_limit_t *limit;
 426
 427         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 428                 if (intel_is_dual_link_lvds(dev)) {
 429                         if (refclk == 100000)
 430                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 431                         else
 432                                 limit = &intel_limits_ironlake_dual_lvds;
 433                 } else {
 434                         if (refclk == 100000)
 435                                 limit = &intel_limits_ironlake_single_lvds_100m;
 436                         else
 437                                 limit = &intel_limits_ironlake_single_lvds;
 438                 }
 439         } else
 440                 limit = &intel_limits_ironlake_dac;
 441
 442         return limit;
 443 }
 444
 445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 446 {
 447         struct drm_device *dev = crtc->dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev))
 452                         limit = &intel_limits_g4x_dual_channel_lvds;
 453                 else
 454                         limit = &intel_limits_g4x_single_channel_lvds;
 455         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 456                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 457                 limit = &intel_limits_g4x_hdmi;
 458         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 459                 limit = &intel_limits_g4x_sdvo;
 460         } else /* The option is for other outputs */
 461                 limit = &intel_limits_i9xx_sdvo;
 462
 463         return limit;
 464 }
 465
 466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 467 {
 468         struct drm_device *dev = crtc->dev;
 469         const intel_limit_t *limit;
 470
 471         if (HAS_PCH_SPLIT(dev))
 472                 limit = intel_ironlake_limit(crtc, refclk);
 473         else if (IS_G4X(dev)) {
 474                 limit = intel_g4x_limit(crtc);
 475         } else if (IS_PINEVIEW(dev)) {
 476                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 477                         limit = &intel_limits_pineview_lvds;
 478                 else
 479                         limit = &intel_limits_pineview_sdvo;
 480         } else if (IS_VALLEYVIEW(dev)) {
 481                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 482                         limit = &intel_limits_vlv_dac;
 483                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 484                         limit = &intel_limits_vlv_hdmi;
 485                 else
 486                         limit = &intel_limits_vlv_dp;
 487         } else if (!IS_GEN2(dev)) {
 488                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 489                         limit = &intel_limits_i9xx_lvds;
 490                 else
 491                         limit = &intel_limits_i9xx_sdvo;
 492         } else {
 493                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 494                         limit = &intel_limits_i8xx_lvds;
 495                 else
 496                         limit = &intel_limits_i8xx_dvo;
 497         }
 498         return limit;
 499 }
 500
 501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 502 static void pineview_clock(int refclk, intel_clock_t *clock)
 503 {
 504         clock->m = clock->m2 + 2;
 505         clock->p = clock->p1 * clock->p2;
 506         clock->vco = refclk * clock->m / clock->n;
 507         clock->dot = clock->vco / clock->p;
 508 }
 509
 510 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 511 {
 512         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 513 }
 514
 515 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 516 {
 517         if (IS_PINEVIEW(dev)) {
 518                 pineview_clock(refclk, clock);
 519                 return;
 520         }
 521         clock->m = i9xx_dpll_compute_m(clock);
 522         clock->p = clock->p1 * clock->p2;
 523         clock->vco = refclk * clock->m / (clock->n + 2);
 524         clock->dot = clock->vco / clock->p;
 525 }
 526
 527 /**
 528  * Returns whether any output on the specified pipe is of the specified type
 529  */
 530 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 531 {
 532         struct drm_device *dev = crtc->dev;
 533         struct intel_encoder *encoder;
 534
 535         for_each_encoder_on_crtc(dev, crtc, encoder)
 536                 if (encoder->type == type)
 537                         return true;
 538
 539         return false;
 540 }
 541
 542 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 543 /**
 544  * Returns whether the given set of divisors are valid for a given refclk with
 545  * the given connectors.
 546  */
 547
 548 static bool intel_PLL_is_valid(struct drm_device *dev,
 549                                const intel_limit_t *limit,
 550                                const intel_clock_t *clock)
 551 {
 552         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 553                 INTELPllInvalid("p1 out of range\n");
 554         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 555                 INTELPllInvalid("p out of range\n");
 556         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 557                 INTELPllInvalid("m2 out of range\n");
 558         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 559                 INTELPllInvalid("m1 out of range\n");
 560         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 561                 INTELPllInvalid("m1 <= m2\n");
 562         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 563                 INTELPllInvalid("m out of range\n");
 564         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 565                 INTELPllInvalid("n out of range\n");
 566         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 567                 INTELPllInvalid("vco out of range\n");
 568         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 569          * connector, etc., rather than just a single range.
 570          */
 571         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 572                 INTELPllInvalid("dot out of range\n");
 573
 574         return true;
 575 }
 576
 577 static bool
 578 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 579                     int target, int refclk, intel_clock_t *match_clock,
 580                     intel_clock_t *best_clock)
 581
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         intel_clock_t clock;
 585         int err = target;
 586
 587         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         clock.p2 = limit->p2.p2_fast;
 595                 else
 596                         clock.p2 = limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         clock.p2 = limit->p2.p2_slow;
 600                 else
 601                         clock.p2 = limit->p2.p2_fast;
 602         }
 603
 604         memset(best_clock, 0, sizeof(*best_clock));
 605
 606         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 607              clock.m1++) {
 608                 for (clock.m2 = limit->m2.min;
 609                      clock.m2 <= limit->m2.max; clock.m2++) {
 610                         /* m1 is always 0 in Pineview */
 611                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 612                                 break;
 613                         for (clock.n = limit->n.min;
 614                              clock.n <= limit->n.max; clock.n++) {
 615                                 for (clock.p1 = limit->p1.min;
 616                                         clock.p1 <= limit->p1.max; clock.p1++) {
 617                                         int this_err;
 618
 619                                         intel_clock(dev, refclk, &clock);
 620                                         if (!intel_PLL_is_valid(dev, limit,
 621                                                                 &clock))
 622                                                 continue;
 623                                         if (match_clock &&
 624                                             clock.p != match_clock->p)
 625                                                 continue;
 626
 627                                         this_err = abs(clock.dot - target);
 628                                         if (this_err < err) {
 629                                                 *best_clock = clock;
 630                                                 err = this_err;
 631                                         }
 632                                 }
 633                         }
 634                 }
 635         }
 636
 637         return (err != target);
 638 }
 639
 640 static bool
 641 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 642                         int target, int refclk, intel_clock_t *match_clock,
 643                         intel_clock_t *best_clock)
 644 {
 645         struct drm_device *dev = crtc->dev;
 646         intel_clock_t clock;
 647         int max_n;
 648         bool found;
 649         /* approximately equals target * 0.00585 */
 650         int err_most = (target >> 8) + (target >> 9);
 651         found = false;
 652
 653         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 654                 int lvds_reg;
 655
 656                 if (HAS_PCH_SPLIT(dev))
 657                         lvds_reg = PCH_LVDS;
 658                 else
 659                         lvds_reg = LVDS;
 660                 if (intel_is_dual_link_lvds(dev))
 661                         clock.p2 = limit->p2.p2_fast;
 662                 else
 663                         clock.p2 = limit->p2.p2_slow;
 664         } else {
 665                 if (target < limit->p2.dot_limit)
 666                         clock.p2 = limit->p2.p2_slow;
 667                 else
 668                         clock.p2 = limit->p2.p2_fast;
 669         }
 670
 671         memset(best_clock, 0, sizeof(*best_clock));
 672         max_n = limit->n.max;
 673         /* based on hardware requirement, prefer smaller n to precision */
 674         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 675                 /* based on hardware requirement, prefere larger m1,m2 */
 676                 for (clock.m1 = limit->m1.max;
 677                      clock.m1 >= limit->m1.min; clock.m1--) {
 678                         for (clock.m2 = limit->m2.max;
 679                              clock.m2 >= limit->m2.min; clock.m2--) {
 680                                 for (clock.p1 = limit->p1.max;
 681                                      clock.p1 >= limit->p1.min; clock.p1--) {
 682                                         int this_err;
 683
 684                                         intel_clock(dev, refclk, &clock);
 685                                         if (!intel_PLL_is_valid(dev, limit,
 686                                                                 &clock))
 687                                                 continue;
 688
 689                                         this_err = abs(clock.dot - target);
 690                                         if (this_err < err_most) {
 691                                                 *best_clock = clock;
 692                                                 err_most = this_err;
 693                                                 max_n = clock.n;
 694                                                 found = true;
 695                                         }
 696                                 }
 697                         }
 698                 }
 699         }
 700         return found;
 701 }
 702
 703 static bool
 704 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 705                         int target, int refclk, intel_clock_t *match_clock,
 706                         intel_clock_t *best_clock)
 707 {
 708         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 709         u32 m, n, fastclk;
 710         u32 updrate, minupdate, fracbits, p;
 711         unsigned long bestppm, ppm, absppm;
 712         int dotclk, flag;
 713
 714         flag = 0;
 715         dotclk = target * 1000;
 716         bestppm = 1000000;
 717         ppm = absppm = 0;
 718         fastclk = dotclk / (2*100);
 719         updrate = 0;
 720         minupdate = 19200;
 721         fracbits = 1;
 722         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 723         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 724
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 727                 updrate = refclk / n;
 728                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 729                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 730                                 if (p2 > 10)
 731                                         p2 = p2 - 1;
 732                                 p = p1 * p2;
 733                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 734                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 735                                         m2 = (((2*(fastclk * p * n / m1 )) +
 736                                                refclk) / (2*refclk));
 737                                         m = m1 * m2;
 738                                         vco = updrate * m;
 739                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 740                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 741                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 742                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 743                                                         bestppm = 0;
 744                                                         flag = 1;
 745                                                 }
 746                                                 if (absppm < bestppm - 10) {
 747                                                         bestppm = absppm;
 748                                                         flag = 1;
 749                                                 }
 750                                                 if (flag) {
 751                                                         bestn = n;
 752                                                         bestm1 = m1;
 753                                                         bestm2 = m2;
 754                                                         bestp1 = p1;
 755                                                         bestp2 = p2;
 756                                                         flag = 0;
 757                                                 }
 758                                         }
 759                                 }
 760                         }
 761                 }
 762         }
 763         best_clock->n = bestn;
 764         best_clock->m1 = bestm1;
 765         best_clock->m2 = bestm2;
 766         best_clock->p1 = bestp1;
 767         best_clock->p2 = bestp2;
 768
 769         return true;
 770 }
 771
 772 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 773                                              enum pipe pipe)
 774 {
 775         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 777
 778         return intel_crtc->config.cpu_transcoder;
 779 }
 780
 781 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 782 {
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         u32 frame, frame_reg = PIPEFRAME(pipe);
 785
 786         frame = I915_READ(frame_reg);
 787
 788         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 789                 DRM_DEBUG_KMS("vblank wait timed out\n");
 790 }
 791
 792 /**
 793  * intel_wait_for_vblank - wait for vblank on a given pipe
 794  * @dev: drm device
 795  * @pipe: pipe to wait for
 796  *
 797  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 798  * mode setting code.
 799  */
 800 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 801 {
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         int pipestat_reg = PIPESTAT(pipe);
 804
 805         if (INTEL_INFO(dev)->gen >= 5) {
 806                 ironlake_wait_for_vblank(dev, pipe);
 807                 return;
 808         }
 809
 810         /* Clear existing vblank status. Note this will clear any other
 811          * sticky status fields as well.
 812          *
 813          * This races with i915_driver_irq_handler() with the result
 814          * that either function could miss a vblank event.  Here it is not
 815          * fatal, as we will either wait upon the next vblank interrupt or
 816          * timeout.  Generally speaking intel_wait_for_vblank() is only
 817          * called during modeset at which time the GPU should be idle and
 818          * should *not* be performing page flips and thus not waiting on
 819          * vblanks...
 820          * Currently, the result of us stealing a vblank from the irq
 821          * handler is that a single frame will be skipped during swapbuffers.
 822          */
 823         I915_WRITE(pipestat_reg,
 824                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 825
 826         /* Wait for vblank interrupt bit to set */
 827         if (wait_for(I915_READ(pipestat_reg) &
 828                      PIPE_VBLANK_INTERRUPT_STATUS,
 829                      50))
 830                 DRM_DEBUG_KMS("vblank wait timed out\n");
 831 }
 832
 833 /*
 834  * intel_wait_for_pipe_off - wait for pipe to turn off
 835  * @dev: drm device
 836  * @pipe: pipe to wait for
 837  *
 838  * After disabling a pipe, we can't wait for vblank in the usual way,
 839  * spinning on the vblank interrupt status bit, since we won't actually
 840  * see an interrupt when the pipe is disabled.
 841  *
 842  * On Gen4 and above:
 843  *   wait for the pipe register state bit to turn off
 844  *
 845  * Otherwise:
 846  *   wait for the display line value to settle (it usually
 847  *   ends up stopping at the start of the next frame).
 848  *
 849  */
 850 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 851 {
 852         struct drm_i915_private *dev_priv = dev->dev_private;
 853         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 854                                                                       pipe);
 855
 856         if (INTEL_INFO(dev)->gen >= 4) {
 857                 int reg = PIPECONF(cpu_transcoder);
 858
 859                 /* Wait for the Pipe State to go off */
 860                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 861                              100))
 862                         WARN(1, "pipe_off wait timed out\n");
 863         } else {
 864                 u32 last_line, line_mask;
 865                 int reg = PIPEDSL(pipe);
 866                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 867
 868                 if (IS_GEN2(dev))
 869                         line_mask = DSL_LINEMASK_GEN2;
 870                 else
 871                         line_mask = DSL_LINEMASK_GEN3;
 872
 873                 /* Wait for the display line to settle */
 874                 do {
 875                         last_line = I915_READ(reg) & line_mask;
 876                         mdelay(5);
 877                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 878                          time_after(timeout, jiffies));
 879                 if (time_after(jiffies, timeout))
 880                         WARN(1, "pipe_off wait timed out\n");
 881         }
 882 }
 883
 884 /*
 885  * ibx_digital_port_connected - is the specified port connected?
 886  * @dev_priv: i915 private structure
 887  * @port: the port to test
 888  *
 889  * Returns true if @port is connected, false otherwise.
 890  */
 891 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 892                                 struct intel_digital_port *port)
 893 {
 894         u32 bit;
 895
 896         if (HAS_PCH_IBX(dev_priv->dev)) {
 897                 switch(port->port) {
 898                 case PORT_B:
 899                         bit = SDE_PORTB_HOTPLUG;
 900                         break;
 901                 case PORT_C:
 902                         bit = SDE_PORTC_HOTPLUG;
 903                         break;
 904                 case PORT_D:
 905                         bit = SDE_PORTD_HOTPLUG;
 906                         break;
 907                 default:
 908                         return true;
 909                 }
 910         } else {
 911                 switch(port->port) {
 912                 case PORT_B:
 913                         bit = SDE_PORTB_HOTPLUG_CPT;
 914                         break;
 915                 case PORT_C:
 916                         bit = SDE_PORTC_HOTPLUG_CPT;
 917                         break;
 918                 case PORT_D:
 919                         bit = SDE_PORTD_HOTPLUG_CPT;
 920                         break;
 921                 default:
 922                         return true;
 923                 }
 924         }
 925
 926         return I915_READ(SDEISR) & bit;
 927 }
 928
 929 static const char *state_string(bool enabled)
 930 {
 931         return enabled ? "on" : "off";
 932 }
 933
 934 /* Only for pre-ILK configs */
 935 static void assert_pll(struct drm_i915_private *dev_priv,
 936                        enum pipe pipe, bool state)
 937 {
 938         int reg;
 939         u32 val;
 940         bool cur_state;
 941
 942         reg = DPLL(pipe);
 943         val = I915_READ(reg);
 944         cur_state = !!(val & DPLL_VCO_ENABLE);
 945         WARN(cur_state != state,
 946              "PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 950 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 951
 952 /* For ILK+ */
 953 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 954                            struct intel_pch_pll *pll,
 955                            struct intel_crtc *crtc,
 956                            bool state)
 957 {
 958         u32 val;
 959         bool cur_state;
 960
 961         if (HAS_PCH_LPT(dev_priv->dev)) {
 962                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 963                 return;
 964         }
 965
 966         if (WARN (!pll,
 967                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 968                 return;
 969
 970         val = I915_READ(pll->pll_reg);
 971         cur_state = !!(val & DPLL_VCO_ENABLE);
 972         WARN(cur_state != state,
 973              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 974              pll->pll_reg, state_string(state), state_string(cur_state), val);
 975
 976         /* Make sure the selected PLL is correctly attached to the transcoder */
 977         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 978                 u32 pch_dpll;
 979
 980                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 981                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 982                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 983                           "PLL[%d] not attached to this transcoder %c: %08x\n",
 984                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 985                         cur_state = !!(val >> (4*crtc->pipe + 3));
 986                         WARN(cur_state != state,
 987                              "PLL[%d] not %s on this transcoder %c: %08x\n",
 988                              pll->pll_reg == _PCH_DPLL_B,
 989                              state_string(state),
 990                              pipe_name(crtc->pipe),
 991                              val);
 992                 }
 993         }
 994 }
 995 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 996 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 997
 998 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 999                           enum pipe pipe, bool state)
1000 {
1001         int reg;
1002         u32 val;
1003         bool cur_state;
1004         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1005                                                                       pipe);
1006
1007         if (HAS_DDI(dev_priv->dev)) {
1008                 /* DDI does not have a specific FDI_TX register */
1009                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1010                 val = I915_READ(reg);
1011                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1012         } else {
1013                 reg = FDI_TX_CTL(pipe);
1014                 val = I915_READ(reg);
1015                 cur_state = !!(val & FDI_TX_ENABLE);
1016         }
1017         WARN(cur_state != state,
1018              "FDI TX state assertion failure (expected %s, current %s)\n",
1019              state_string(state), state_string(cur_state));
1020 }
1021 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1023
1024 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025                           enum pipe pipe, bool state)
1026 {
1027         int reg;
1028         u32 val;
1029         bool cur_state;
1030
1031         reg = FDI_RX_CTL(pipe);
1032         val = I915_READ(reg);
1033         cur_state = !!(val & FDI_RX_ENABLE);
1034         WARN(cur_state != state,
1035              "FDI RX state assertion failure (expected %s, current %s)\n",
1036              state_string(state), state_string(cur_state));
1037 }
1038 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1040
1041 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1042                                       enum pipe pipe)
1043 {
1044         int reg;
1045         u32 val;
1046
1047         /* ILK FDI PLL is always enabled */
1048         if (dev_priv->info->gen == 5)
1049                 return;
1050
1051         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1052         if (HAS_DDI(dev_priv->dev))
1053                 return;
1054
1055         reg = FDI_TX_CTL(pipe);
1056         val = I915_READ(reg);
1057         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1058 }
1059
1060 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1061                                       enum pipe pipe)
1062 {
1063         int reg;
1064         u32 val;
1065
1066         reg = FDI_RX_CTL(pipe);
1067         val = I915_READ(reg);
1068         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1069 }
1070
1071 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1072                                   enum pipe pipe)
1073 {
1074         int pp_reg, lvds_reg;
1075         u32 val;
1076         enum pipe panel_pipe = PIPE_A;
1077         bool locked = true;
1078
1079         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080                 pp_reg = PCH_PP_CONTROL;
1081                 lvds_reg = PCH_LVDS;
1082         } else {
1083                 pp_reg = PP_CONTROL;
1084                 lvds_reg = LVDS;
1085         }
1086
1087         val = I915_READ(pp_reg);
1088         if (!(val & PANEL_POWER_ON) ||
1089             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1090                 locked = false;
1091
1092         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093                 panel_pipe = PIPE_B;
1094
1095         WARN(panel_pipe == pipe && locked,
1096              "panel assertion failure, pipe %c regs locked\n",
1097              pipe_name(pipe));
1098 }
1099
1100 void assert_pipe(struct drm_i915_private *dev_priv,
1101                  enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107                                                                       pipe);
1108
1109         /* if we need the pipe A quirk it must be always on */
1110         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111                 state = true;
1112
1113         if (!intel_using_power_well(dev_priv->dev) &&
1114             cpu_transcoder != TRANSCODER_EDP) {
1115                 cur_state = false;
1116         } else {
1117                 reg = PIPECONF(cpu_transcoder);
1118                 val = I915_READ(reg);
1119                 cur_state = !!(val & PIPECONF_ENABLE);
1120         }
1121
1122         WARN(cur_state != state,
1123              "pipe %c assertion failure (expected %s, current %s)\n",
1124              pipe_name(pipe), state_string(state), state_string(cur_state));
1125 }
1126
1127 static void assert_plane(struct drm_i915_private *dev_priv,
1128                          enum plane plane, bool state)
1129 {
1130         int reg;
1131         u32 val;
1132         bool cur_state;
1133
1134         reg = DSPCNTR(plane);
1135         val = I915_READ(reg);
1136         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137         WARN(cur_state != state,
1138              "plane %c assertion failure (expected %s, current %s)\n",
1139              plane_name(plane), state_string(state), state_string(cur_state));
1140 }
1141
1142 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
1145 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146                                    enum pipe pipe)
1147 {
1148         int reg, i;
1149         u32 val;
1150         int cur_pipe;
1151
1152         /* Planes are fixed to pipes on ILK+ */
1153         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1154                 reg = DSPCNTR(pipe);
1155                 val = I915_READ(reg);
1156                 WARN((val & DISPLAY_PLANE_ENABLE),
1157                      "plane %c assertion failure, should be disabled but not\n",
1158                      plane_name(pipe));
1159                 return;
1160         }
1161
1162         /* Need to check both planes against the pipe */
1163         for (i = 0; i < 2; i++) {
1164                 reg = DSPCNTR(i);
1165                 val = I915_READ(reg);
1166                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167                         DISPPLANE_SEL_PIPE_SHIFT;
1168                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1169                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170                      plane_name(i), pipe_name(pipe));
1171         }
1172 }
1173
1174 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1175                                     enum pipe pipe)
1176 {
1177         int reg, i;
1178         u32 val;
1179
1180         if (!IS_VALLEYVIEW(dev_priv->dev))
1181                 return;
1182
1183         /* Need to check both planes against the pipe */
1184         for (i = 0; i < dev_priv->num_plane; i++) {
1185                 reg = SPCNTR(pipe, i);
1186                 val = I915_READ(reg);
1187                 WARN((val & SP_ENABLE),
1188                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189                      sprite_name(pipe, i), pipe_name(pipe));
1190         }
1191 }
1192
1193 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1194 {
1195         u32 val;
1196         bool enabled;
1197
1198         if (HAS_PCH_LPT(dev_priv->dev)) {
1199                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1200                 return;
1201         }
1202
1203         val = I915_READ(PCH_DREF_CONTROL);
1204         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205                             DREF_SUPERSPREAD_SOURCE_MASK));
1206         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1207 }
1208
1209 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1210                                            enum pipe pipe)
1211 {
1212         int reg;
1213         u32 val;
1214         bool enabled;
1215
1216         reg = PCH_TRANSCONF(pipe);
1217         val = I915_READ(reg);
1218         enabled = !!(val & TRANS_ENABLE);
1219         WARN(enabled,
1220              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1221              pipe_name(pipe));
1222 }
1223
1224 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225                             enum pipe pipe, u32 port_sel, u32 val)
1226 {
1227         if ((val & DP_PORT_EN) == 0)
1228                 return false;
1229
1230         if (HAS_PCH_CPT(dev_priv->dev)) {
1231                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1234                         return false;
1235         } else {
1236                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1237                         return false;
1238         }
1239         return true;
1240 }
1241
1242 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243                               enum pipe pipe, u32 val)
1244 {
1245         if ((val & SDVO_ENABLE) == 0)
1246                 return false;
1247
1248         if (HAS_PCH_CPT(dev_priv->dev)) {
1249                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1250                         return false;
1251         } else {
1252                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1253                         return false;
1254         }
1255         return true;
1256 }
1257
1258 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259                               enum pipe pipe, u32 val)
1260 {
1261         if ((val & LVDS_PORT_EN) == 0)
1262                 return false;
1263
1264         if (HAS_PCH_CPT(dev_priv->dev)) {
1265                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266                         return false;
1267         } else {
1268                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1269                         return false;
1270         }
1271         return true;
1272 }
1273
1274 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275                               enum pipe pipe, u32 val)
1276 {
1277         if ((val & ADPA_DAC_ENABLE) == 0)
1278                 return false;
1279         if (HAS_PCH_CPT(dev_priv->dev)) {
1280                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281                         return false;
1282         } else {
1283                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1284                         return false;
1285         }
1286         return true;
1287 }
1288
1289 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1290                                    enum pipe pipe, int reg, u32 port_sel)
1291 {
1292         u32 val = I915_READ(reg);
1293         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1294              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1295              reg, pipe_name(pipe));
1296
1297         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298              && (val & DP_PIPEB_SELECT),
1299              "IBX PCH dp port still using transcoder B\n");
1300 }
1301
1302 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303                                      enum pipe pipe, int reg)
1304 {
1305         u32 val = I915_READ(reg);
1306         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1307              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1308              reg, pipe_name(pipe));
1309
1310         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1311              && (val & SDVO_PIPE_B_SELECT),
1312              "IBX PCH hdmi port still using transcoder B\n");
1313 }
1314
1315 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1316                                       enum pipe pipe)
1317 {
1318         int reg;
1319         u32 val;
1320
1321         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1324
1325         reg = PCH_ADPA;
1326         val = I915_READ(reg);
1327         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1328              "PCH VGA enabled on transcoder %c, should be disabled\n",
1329              pipe_name(pipe));
1330
1331         reg = PCH_LVDS;
1332         val = I915_READ(reg);
1333         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1334              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1335              pipe_name(pipe));
1336
1337         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1340 }
1341
1342 /**
1343  * intel_enable_pll - enable a PLL
1344  * @dev_priv: i915 private structure
1345  * @pipe: pipe PLL to enable
1346  *
1347  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1348  * make sure the PLL reg is writable first though, since the panel write
1349  * protect mechanism may be enabled.
1350  *
1351  * Note!  This is for pre-ILK only.
1352  *
1353  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1354  */
1355 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1356 {
1357         int reg;
1358         u32 val;
1359
1360         assert_pipe_disabled(dev_priv, pipe);
1361
1362         /* No really, not for ILK+ */
1363         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1364
1365         /* PLL is protected by panel, make sure we can write it */
1366         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367                 assert_panel_unlocked(dev_priv, pipe);
1368
1369         reg = DPLL(pipe);
1370         val = I915_READ(reg);
1371         val |= DPLL_VCO_ENABLE;
1372
1373         /* We do this three times for luck */
1374         I915_WRITE(reg, val);
1375         POSTING_READ(reg);
1376         udelay(150); /* wait for warmup */
1377         I915_WRITE(reg, val);
1378         POSTING_READ(reg);
1379         udelay(150); /* wait for warmup */
1380         I915_WRITE(reg, val);
1381         POSTING_READ(reg);
1382         udelay(150); /* wait for warmup */
1383 }
1384
1385 /**
1386  * intel_disable_pll - disable a PLL
1387  * @dev_priv: i915 private structure
1388  * @pipe: pipe PLL to disable
1389  *
1390  * Disable the PLL for @pipe, making sure the pipe is off first.
1391  *
1392  * Note!  This is for pre-ILK only.
1393  */
1394 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395 {
1396         int reg;
1397         u32 val;
1398
1399         /* Don't disable pipe A or pipe A PLLs if needed */
1400         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401                 return;
1402
1403         /* Make sure the pipe isn't still relying on us */
1404         assert_pipe_disabled(dev_priv, pipe);
1405
1406         reg = DPLL(pipe);
1407         val = I915_READ(reg);
1408         val &= ~DPLL_VCO_ENABLE;
1409         I915_WRITE(reg, val);
1410         POSTING_READ(reg);
1411 }
1412
1413 /* SBI access */
1414 static void
1415 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416                 enum intel_sbi_destination destination)
1417 {
1418         u32 tmp;
1419
1420         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1421
1422         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1423                                 100)) {
1424                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1425                 return;
1426         }
1427
1428         I915_WRITE(SBI_ADDR, (reg << 16));
1429         I915_WRITE(SBI_DATA, value);
1430
1431         if (destination == SBI_ICLK)
1432                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1433         else
1434                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1436
1437         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1438                                 100)) {
1439                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1440                 return;
1441         }
1442 }
1443
1444 static u32
1445 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446                enum intel_sbi_destination destination)
1447 {
1448         u32 value = 0;
1449         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1450
1451         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1452                                 100)) {
1453                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1454                 return 0;
1455         }
1456
1457         I915_WRITE(SBI_ADDR, (reg << 16));
1458
1459         if (destination == SBI_ICLK)
1460                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1461         else
1462                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1464
1465         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1466                                 100)) {
1467                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1468                 return 0;
1469         }
1470
1471         return I915_READ(SBI_DATA);
1472 }
1473
1474 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1475 {
1476         u32 port_mask;
1477
1478         if (!port)
1479                 port_mask = DPLL_PORTB_READY_MASK;
1480         else
1481                 port_mask = DPLL_PORTC_READY_MASK;
1482
1483         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485                      'B' + port, I915_READ(DPLL(0)));
1486 }
1487
1488 /**
1489  * ironlake_enable_pch_pll - enable PCH PLL
1490  * @dev_priv: i915 private structure
1491  * @pipe: pipe PLL to enable
1492  *
1493  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494  * drives the transcoder clock.
1495  */
1496 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1497 {
1498         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1499         struct intel_pch_pll *pll;
1500         int reg;
1501         u32 val;
1502
1503         /* PCH PLLs only available on ILK, SNB and IVB */
1504         BUG_ON(dev_priv->info->gen < 5);
1505         pll = intel_crtc->pch_pll;
1506         if (pll == NULL)
1507                 return;
1508
1509         if (WARN_ON(pll->refcount == 0))
1510                 return;
1511
1512         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513                       pll->pll_reg, pll->active, pll->on,
1514                       intel_crtc->base.base.id);
1515
1516         /* PCH refclock must be enabled first */
1517         assert_pch_refclk_enabled(dev_priv);
1518
1519         if (pll->active++ && pll->on) {
1520                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1521                 return;
1522         }
1523
1524         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1525
1526         reg = pll->pll_reg;
1527         val = I915_READ(reg);
1528         val |= DPLL_VCO_ENABLE;
1529         I915_WRITE(reg, val);
1530         POSTING_READ(reg);
1531         udelay(200);
1532
1533         pll->on = true;
1534 }
1535
1536 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1537 {
1538         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1540         int reg;
1541         u32 val;
1542
1543         /* PCH only available on ILK+ */
1544         BUG_ON(dev_priv->info->gen < 5);
1545         if (pll == NULL)
1546                return;
1547
1548         if (WARN_ON(pll->refcount == 0))
1549                 return;
1550
1551         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552                       pll->pll_reg, pll->active, pll->on,
1553                       intel_crtc->base.base.id);
1554
1555         if (WARN_ON(pll->active == 0)) {
1556                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1557                 return;
1558         }
1559
1560         if (--pll->active) {
1561                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1562                 return;
1563         }
1564
1565         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1566
1567         /* Make sure transcoder isn't still depending on us */
1568         assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1569
1570         reg = pll->pll_reg;
1571         val = I915_READ(reg);
1572         val &= ~DPLL_VCO_ENABLE;
1573         I915_WRITE(reg, val);
1574         POSTING_READ(reg);
1575         udelay(200);
1576
1577         pll->on = false;
1578 }
1579
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581                                            enum pipe pipe)
1582 {
1583         struct drm_device *dev = dev_priv->dev;
1584         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585         uint32_t reg, val, pipeconf_val;
1586
1587         /* PCH only available on ILK+ */
1588         BUG_ON(dev_priv->info->gen < 5);
1589
1590         /* Make sure PCH DPLL is enabled */
1591         assert_pch_pll_enabled(dev_priv,
1592                                to_intel_crtc(crtc)->pch_pll,
1593                                to_intel_crtc(crtc));
1594
1595         /* FDI must be feeding us bits for PCH ports */
1596         assert_fdi_tx_enabled(dev_priv, pipe);
1597         assert_fdi_rx_enabled(dev_priv, pipe);
1598
1599         if (HAS_PCH_CPT(dev)) {
1600                 /* Workaround: Set the timing override bit before enabling the
1601                  * pch transcoder. */
1602                 reg = TRANS_CHICKEN2(pipe);
1603                 val = I915_READ(reg);
1604                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605                 I915_WRITE(reg, val);
1606         }
1607
1608         reg = PCH_TRANSCONF(pipe);
1609         val = I915_READ(reg);
1610         pipeconf_val = I915_READ(PIPECONF(pipe));
1611
1612         if (HAS_PCH_IBX(dev_priv->dev)) {
1613                 /*
1614                  * make the BPC in transcoder be consistent with
1615                  * that in pipeconf reg.
1616                  */
1617                 val &= ~PIPECONF_BPC_MASK;
1618                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1619         }
1620
1621         val &= ~TRANS_INTERLACE_MASK;
1622         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623                 if (HAS_PCH_IBX(dev_priv->dev) &&
1624                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625                         val |= TRANS_LEGACY_INTERLACED_ILK;
1626                 else
1627                         val |= TRANS_INTERLACED;
1628         else
1629                 val |= TRANS_PROGRESSIVE;
1630
1631         I915_WRITE(reg, val | TRANS_ENABLE);
1632         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1634 }
1635
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637                                       enum transcoder cpu_transcoder)
1638 {
1639         u32 val, pipeconf_val;
1640
1641         /* PCH only available on ILK+ */
1642         BUG_ON(dev_priv->info->gen < 5);
1643
1644         /* FDI must be feeding us bits for PCH ports */
1645         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1647
1648         /* Workaround: set timing override bit. */
1649         val = I915_READ(_TRANSA_CHICKEN2);
1650         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651         I915_WRITE(_TRANSA_CHICKEN2, val);
1652
1653         val = TRANS_ENABLE;
1654         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1655
1656         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657             PIPECONF_INTERLACED_ILK)
1658                 val |= TRANS_INTERLACED;
1659         else
1660                 val |= TRANS_PROGRESSIVE;
1661
1662         I915_WRITE(LPT_TRANSCONF, val);
1663         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1664                 DRM_ERROR("Failed to enable PCH transcoder\n");
1665 }
1666
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668                                             enum pipe pipe)
1669 {
1670         struct drm_device *dev = dev_priv->dev;
1671         uint32_t reg, val;
1672
1673         /* FDI relies on the transcoder */
1674         assert_fdi_tx_disabled(dev_priv, pipe);
1675         assert_fdi_rx_disabled(dev_priv, pipe);
1676
1677         /* Ports must be off as well */
1678         assert_pch_ports_disabled(dev_priv, pipe);
1679
1680         reg = PCH_TRANSCONF(pipe);
1681         val = I915_READ(reg);
1682         val &= ~TRANS_ENABLE;
1683         I915_WRITE(reg, val);
1684         /* wait for PCH transcoder off, transcoder state */
1685         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1687
1688         if (!HAS_PCH_IBX(dev)) {
1689                 /* Workaround: Clear the timing override chicken bit again. */
1690                 reg = TRANS_CHICKEN2(pipe);
1691                 val = I915_READ(reg);
1692                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693                 I915_WRITE(reg, val);
1694         }
1695 }
1696
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1698 {
1699         u32 val;
1700
1701         val = I915_READ(LPT_TRANSCONF);
1702         val &= ~TRANS_ENABLE;
1703         I915_WRITE(LPT_TRANSCONF, val);
1704         /* wait for PCH transcoder off, transcoder state */
1705         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1706                 DRM_ERROR("Failed to disable PCH transcoder\n");
1707
1708         /* Workaround: clear timing override bit. */
1709         val = I915_READ(_TRANSA_CHICKEN2);
1710         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711         I915_WRITE(_TRANSA_CHICKEN2, val);
1712 }
1713
1714 /**
1715  * intel_enable_pipe - enable a pipe, asserting requirements
1716  * @dev_priv: i915 private structure
1717  * @pipe: pipe to enable
1718  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1719  *
1720  * Enable @pipe, making sure that various hardware specific requirements
1721  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722  *
1723  * @pipe should be %PIPE_A or %PIPE_B.
1724  *
1725  * Will wait until the pipe is actually running (i.e. first vblank) before
1726  * returning.
1727  */
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729                               bool pch_port)
1730 {
1731         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732                                                                       pipe);
1733         enum pipe pch_transcoder;
1734         int reg;
1735         u32 val;
1736
1737         assert_planes_disabled(dev_priv, pipe);
1738         assert_sprites_disabled(dev_priv, pipe);
1739
1740         if (HAS_PCH_LPT(dev_priv->dev))
1741                 pch_transcoder = TRANSCODER_A;
1742         else
1743                 pch_transcoder = pipe;
1744
1745         /*
1746          * A pipe without a PLL won't actually be able to drive bits from
1747          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1748          * need the check.
1749          */
1750         if (!HAS_PCH_SPLIT(dev_priv->dev))
1751                 assert_pll_enabled(dev_priv, pipe);
1752         else {
1753                 if (pch_port) {
1754                         /* if driving the PCH, we need FDI enabled */
1755                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1756                         assert_fdi_tx_pll_enabled(dev_priv,
1757                                                   (enum pipe) cpu_transcoder);
1758                 }
1759                 /* FIXME: assert CPU port conditions for SNB+ */
1760         }
1761
1762         reg = PIPECONF(cpu_transcoder);
1763         val = I915_READ(reg);
1764         if (val & PIPECONF_ENABLE)
1765                 return;
1766
1767         I915_WRITE(reg, val | PIPECONF_ENABLE);
1768         intel_wait_for_vblank(dev_priv->dev, pipe);
1769 }
1770
1771 /**
1772  * intel_disable_pipe - disable a pipe, asserting requirements
1773  * @dev_priv: i915 private structure
1774  * @pipe: pipe to disable
1775  *
1776  * Disable @pipe, making sure that various hardware specific requirements
1777  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778  *
1779  * @pipe should be %PIPE_A or %PIPE_B.
1780  *
1781  * Will wait until the pipe has shut down before returning.
1782  */
1783 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1784                                enum pipe pipe)
1785 {
1786         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787                                                                       pipe);
1788         int reg;
1789         u32 val;
1790
1791         /*
1792          * Make sure planes won't keep trying to pump pixels to us,
1793          * or we might hang the display.
1794          */
1795         assert_planes_disabled(dev_priv, pipe);
1796         assert_sprites_disabled(dev_priv, pipe);
1797
1798         /* Don't disable pipe A or pipe A PLLs if needed */
1799         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800                 return;
1801
1802         reg = PIPECONF(cpu_transcoder);
1803         val = I915_READ(reg);
1804         if ((val & PIPECONF_ENABLE) == 0)
1805                 return;
1806
1807         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1808         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809 }
1810
1811 /*
1812  * Plane regs are double buffered, going from enabled->disabled needs a
1813  * trigger in order to latch.  The display address reg provides this.
1814  */
1815 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1816                                       enum plane plane)
1817 {
1818         if (dev_priv->info->gen >= 4)
1819                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820         else
1821                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1822 }
1823
1824 /**
1825  * intel_enable_plane - enable a display plane on a given pipe
1826  * @dev_priv: i915 private structure
1827  * @plane: plane to enable
1828  * @pipe: pipe being fed
1829  *
1830  * Enable @plane on @pipe, making sure that @pipe is running first.
1831  */
1832 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833                                enum plane plane, enum pipe pipe)
1834 {
1835         int reg;
1836         u32 val;
1837
1838         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839         assert_pipe_enabled(dev_priv, pipe);
1840
1841         reg = DSPCNTR(plane);
1842         val = I915_READ(reg);
1843         if (val & DISPLAY_PLANE_ENABLE)
1844                 return;
1845
1846         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1847         intel_flush_display_plane(dev_priv, plane);
1848         intel_wait_for_vblank(dev_priv->dev, pipe);
1849 }
1850
1851 /**
1852  * intel_disable_plane - disable a display plane
1853  * @dev_priv: i915 private structure
1854  * @plane: plane to disable
1855  * @pipe: pipe consuming the data
1856  *
1857  * Disable @plane; should be an independent operation.
1858  */
1859 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860                                 enum plane plane, enum pipe pipe)
1861 {
1862         int reg;
1863         u32 val;
1864
1865         reg = DSPCNTR(plane);
1866         val = I915_READ(reg);
1867         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868                 return;
1869
1870         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1871         intel_flush_display_plane(dev_priv, plane);
1872         intel_wait_for_vblank(dev_priv->dev, pipe);
1873 }
1874
1875 static bool need_vtd_wa(struct drm_device *dev)
1876 {
1877 #ifdef CONFIG_INTEL_IOMMU
1878         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879                 return true;
1880 #endif
1881         return false;
1882 }
1883
1884 int
1885 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1886                            struct drm_i915_gem_object *obj,
1887                            struct intel_ring_buffer *pipelined)
1888 {
1889         struct drm_i915_private *dev_priv = dev->dev_private;
1890         u32 alignment;
1891         int ret;
1892
1893         switch (obj->tiling_mode) {
1894         case I915_TILING_NONE:
1895                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896                         alignment = 128 * 1024;
1897                 else if (INTEL_INFO(dev)->gen >= 4)
1898                         alignment = 4 * 1024;
1899                 else
1900                         alignment = 64 * 1024;
1901                 break;
1902         case I915_TILING_X:
1903                 /* pin() will align the object as required by fence */
1904                 alignment = 0;
1905                 break;
1906         case I915_TILING_Y:
1907                 /* Despite that we check this in framebuffer_init userspace can
1908                  * screw us over and change the tiling after the fact. Only
1909                  * pinned buffers can't change their tiling. */
1910                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1911                 return -EINVAL;
1912         default:
1913                 BUG();
1914         }
1915
1916         /* Note that the w/a also requires 64 PTE of padding following the
1917          * bo. We currently fill all unused PTE with the shadow page and so
1918          * we should always have valid PTE following the scanout preventing
1919          * the VT-d warning.
1920          */
1921         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922                 alignment = 256 * 1024;
1923
1924         dev_priv->mm.interruptible = false;
1925         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1926         if (ret)
1927                 goto err_interruptible;
1928
1929         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930          * fence, whereas 965+ only requires a fence if using
1931          * framebuffer compression.  For simplicity, we always install
1932          * a fence as the cost is not that onerous.
1933          */
1934         ret = i915_gem_object_get_fence(obj);
1935         if (ret)
1936                 goto err_unpin;
1937
1938         i915_gem_object_pin_fence(obj);
1939
1940         dev_priv->mm.interruptible = true;
1941         return 0;
1942
1943 err_unpin:
1944         i915_gem_object_unpin(obj);
1945 err_interruptible:
1946         dev_priv->mm.interruptible = true;
1947         return ret;
1948 }
1949
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951 {
1952         i915_gem_object_unpin_fence(obj);
1953         i915_gem_object_unpin(obj);
1954 }
1955
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957  * is assumed to be a power-of-two. */
1958 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959                                              unsigned int tiling_mode,
1960                                              unsigned int cpp,
1961                                              unsigned int pitch)
1962 {
1963         if (tiling_mode != I915_TILING_NONE) {
1964                 unsigned int tile_rows, tiles;
1965
1966                 tile_rows = *y / 8;
1967                 *y %= 8;
1968
1969                 tiles = *x / (512/cpp);
1970                 *x %= 512/cpp;
1971
1972                 return tile_rows * pitch * 8 + tiles * 4096;
1973         } else {
1974                 unsigned int offset;
1975
1976                 offset = *y * pitch + *x * cpp;
1977                 *y = 0;
1978                 *x = (offset & 4095) / cpp;
1979                 return offset & -4096;
1980         }
1981 }
1982
1983 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984                              int x, int y)
1985 {
1986         struct drm_device *dev = crtc->dev;
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989         struct intel_framebuffer *intel_fb;
1990         struct drm_i915_gem_object *obj;
1991         int plane = intel_crtc->plane;
1992         unsigned long linear_offset;
1993         u32 dspcntr;
1994         u32 reg;
1995
1996         switch (plane) {
1997         case 0:
1998         case 1:
1999                 break;
2000         default:
2001                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2002                 return -EINVAL;
2003         }
2004
2005         intel_fb = to_intel_framebuffer(fb);
2006         obj = intel_fb->obj;
2007
2008         reg = DSPCNTR(plane);
2009         dspcntr = I915_READ(reg);
2010         /* Mask out pixel format bits in case we change it */
2011         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2012         switch (fb->pixel_format) {
2013         case DRM_FORMAT_C8:
2014                 dspcntr |= DISPPLANE_8BPP;
2015                 break;
2016         case DRM_FORMAT_XRGB1555:
2017         case DRM_FORMAT_ARGB1555:
2018                 dspcntr |= DISPPLANE_BGRX555;
2019                 break;
2020         case DRM_FORMAT_RGB565:
2021                 dspcntr |= DISPPLANE_BGRX565;
2022                 break;
2023         case DRM_FORMAT_XRGB8888:
2024         case DRM_FORMAT_ARGB8888:
2025                 dspcntr |= DISPPLANE_BGRX888;
2026                 break;
2027         case DRM_FORMAT_XBGR8888:
2028         case DRM_FORMAT_ABGR8888:
2029                 dspcntr |= DISPPLANE_RGBX888;
2030                 break;
2031         case DRM_FORMAT_XRGB2101010:
2032         case DRM_FORMAT_ARGB2101010:
2033                 dspcntr |= DISPPLANE_BGRX101010;
2034                 break;
2035         case DRM_FORMAT_XBGR2101010:
2036         case DRM_FORMAT_ABGR2101010:
2037                 dspcntr |= DISPPLANE_RGBX101010;
2038                 break;
2039         default:
2040                 BUG();
2041         }
2042
2043         if (INTEL_INFO(dev)->gen >= 4) {
2044                 if (obj->tiling_mode != I915_TILING_NONE)
2045                         dspcntr |= DISPPLANE_TILED;
2046                 else
2047                         dspcntr &= ~DISPPLANE_TILED;
2048         }
2049
2050         I915_WRITE(reg, dspcntr);
2051
2052         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2053
2054         if (INTEL_INFO(dev)->gen >= 4) {
2055                 intel_crtc->dspaddr_offset =
2056                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057                                                        fb->bits_per_pixel / 8,
2058                                                        fb->pitches[0]);
2059                 linear_offset -= intel_crtc->dspaddr_offset;
2060         } else {
2061                 intel_crtc->dspaddr_offset = linear_offset;
2062         }
2063
2064         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2066         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2067         if (INTEL_INFO(dev)->gen >= 4) {
2068                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2070                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2071                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2072         } else
2073                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2074         POSTING_READ(reg);
2075
2076         return 0;
2077 }
2078
2079 static int ironlake_update_plane(struct drm_crtc *crtc,
2080                                  struct drm_framebuffer *fb, int x, int y)
2081 {
2082         struct drm_device *dev = crtc->dev;
2083         struct drm_i915_private *dev_priv = dev->dev_private;
2084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085         struct intel_framebuffer *intel_fb;
2086         struct drm_i915_gem_object *obj;
2087         int plane = intel_crtc->plane;
2088         unsigned long linear_offset;
2089         u32 dspcntr;
2090         u32 reg;
2091
2092         switch (plane) {
2093         case 0:
2094         case 1:
2095         case 2:
2096                 break;
2097         default:
2098                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2099                 return -EINVAL;
2100         }
2101
2102         intel_fb = to_intel_framebuffer(fb);
2103         obj = intel_fb->obj;
2104
2105         reg = DSPCNTR(plane);
2106         dspcntr = I915_READ(reg);
2107         /* Mask out pixel format bits in case we change it */
2108         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2109         switch (fb->pixel_format) {
2110         case DRM_FORMAT_C8:
2111                 dspcntr |= DISPPLANE_8BPP;
2112                 break;
2113         case DRM_FORMAT_RGB565:
2114                 dspcntr |= DISPPLANE_BGRX565;
2115                 break;
2116         case DRM_FORMAT_XRGB8888:
2117         case DRM_FORMAT_ARGB8888:
2118                 dspcntr |= DISPPLANE_BGRX888;
2119                 break;
2120         case DRM_FORMAT_XBGR8888:
2121         case DRM_FORMAT_ABGR8888:
2122                 dspcntr |= DISPPLANE_RGBX888;
2123                 break;
2124         case DRM_FORMAT_XRGB2101010:
2125         case DRM_FORMAT_ARGB2101010:
2126                 dspcntr |= DISPPLANE_BGRX101010;
2127                 break;
2128         case DRM_FORMAT_XBGR2101010:
2129         case DRM_FORMAT_ABGR2101010:
2130                 dspcntr |= DISPPLANE_RGBX101010;
2131                 break;
2132         default:
2133                 BUG();
2134         }
2135
2136         if (obj->tiling_mode != I915_TILING_NONE)
2137                 dspcntr |= DISPPLANE_TILED;
2138         else
2139                 dspcntr &= ~DISPPLANE_TILED;
2140
2141         /* must disable */
2142         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2143
2144         I915_WRITE(reg, dspcntr);
2145
2146         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2147         intel_crtc->dspaddr_offset =
2148                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149                                                fb->bits_per_pixel / 8,
2150                                                fb->pitches[0]);
2151         linear_offset -= intel_crtc->dspaddr_offset;
2152
2153         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2155         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2156         I915_MODIFY_DISPBASE(DSPSURF(plane),
2157                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2158         if (IS_HASWELL(dev)) {
2159                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2160         } else {
2161                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163         }
2164         POSTING_READ(reg);
2165
2166         return 0;
2167 }
2168
2169 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2170 static int
2171 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172                            int x, int y, enum mode_set_atomic state)
2173 {
2174         struct drm_device *dev = crtc->dev;
2175         struct drm_i915_private *dev_priv = dev->dev_private;
2176
2177         if (dev_priv->display.disable_fbc)
2178                 dev_priv->display.disable_fbc(dev);
2179         intel_increase_pllclock(crtc);
2180
2181         return dev_priv->display.update_plane(crtc, fb, x, y);
2182 }
2183
2184 void intel_display_handle_reset(struct drm_device *dev)
2185 {
2186         struct drm_i915_private *dev_priv = dev->dev_private;
2187         struct drm_crtc *crtc;
2188
2189         /*
2190          * Flips in the rings have been nuked by the reset,
2191          * so complete all pending flips so that user space
2192          * will get its events and not get stuck.
2193          *
2194          * Also update the base address of all primary
2195          * planes to the the last fb to make sure we're
2196          * showing the correct fb after a reset.
2197          *
2198          * Need to make two loops over the crtcs so that we
2199          * don't try to grab a crtc mutex before the
2200          * pending_flip_queue really got woken up.
2201          */
2202
2203         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205                 enum plane plane = intel_crtc->plane;
2206
2207                 intel_prepare_page_flip(dev, plane);
2208                 intel_finish_page_flip_plane(dev, plane);
2209         }
2210
2211         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214                 mutex_lock(&crtc->mutex);
2215                 if (intel_crtc->active)
2216                         dev_priv->display.update_plane(crtc, crtc->fb,
2217                                                        crtc->x, crtc->y);
2218                 mutex_unlock(&crtc->mutex);
2219         }
2220 }
2221
2222 static int
2223 intel_finish_fb(struct drm_framebuffer *old_fb)
2224 {
2225         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227         bool was_interruptible = dev_priv->mm.interruptible;
2228         int ret;
2229
2230         /* Big Hammer, we also need to ensure that any pending
2231          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232          * current scanout is retired before unpinning the old
2233          * framebuffer.
2234          *
2235          * This should only fail upon a hung GPU, in which case we
2236          * can safely continue.
2237          */
2238         dev_priv->mm.interruptible = false;
2239         ret = i915_gem_object_finish_gpu(obj);
2240         dev_priv->mm.interruptible = was_interruptible;
2241
2242         return ret;
2243 }
2244
2245 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246 {
2247         struct drm_device *dev = crtc->dev;
2248         struct drm_i915_master_private *master_priv;
2249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251         if (!dev->primary->master)
2252                 return;
2253
2254         master_priv = dev->primary->master->driver_priv;
2255         if (!master_priv->sarea_priv)
2256                 return;
2257
2258         switch (intel_crtc->pipe) {
2259         case 0:
2260                 master_priv->sarea_priv->pipeA_x = x;
2261                 master_priv->sarea_priv->pipeA_y = y;
2262                 break;
2263         case 1:
2264                 master_priv->sarea_priv->pipeB_x = x;
2265                 master_priv->sarea_priv->pipeB_y = y;
2266                 break;
2267         default:
2268                 break;
2269         }
2270 }
2271
2272 static int
2273 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2274                     struct drm_framebuffer *fb)
2275 {
2276         struct drm_device *dev = crtc->dev;
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279         struct drm_framebuffer *old_fb;
2280         int ret;
2281
2282         /* no fb bound */
2283         if (!fb) {
2284                 DRM_ERROR("No FB bound\n");
2285                 return 0;
2286         }
2287
2288         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2289                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290                           plane_name(intel_crtc->plane),
2291                           INTEL_INFO(dev)->num_pipes);
2292                 return -EINVAL;
2293         }
2294
2295         mutex_lock(&dev->struct_mutex);
2296         ret = intel_pin_and_fence_fb_obj(dev,
2297                                          to_intel_framebuffer(fb)->obj,
2298                                          NULL);
2299         if (ret != 0) {
2300                 mutex_unlock(&dev->struct_mutex);
2301                 DRM_ERROR("pin & fence failed\n");
2302                 return ret;
2303         }
2304
2305         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2306         if (ret) {
2307                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2308                 mutex_unlock(&dev->struct_mutex);
2309                 DRM_ERROR("failed to update base address\n");
2310                 return ret;
2311         }
2312
2313         old_fb = crtc->fb;
2314         crtc->fb = fb;
2315         crtc->x = x;
2316         crtc->y = y;
2317
2318         if (old_fb) {
2319                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2320                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2321         }
2322
2323         intel_update_fbc(dev);
2324         mutex_unlock(&dev->struct_mutex);
2325
2326         intel_crtc_update_sarea_pos(crtc, x, y);
2327
2328         return 0;
2329 }
2330
2331 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336         int pipe = intel_crtc->pipe;
2337         u32 reg, temp;
2338
2339         /* enable normal train */
2340         reg = FDI_TX_CTL(pipe);
2341         temp = I915_READ(reg);
2342         if (IS_IVYBRIDGE(dev)) {
2343                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2345         } else {
2346                 temp &= ~FDI_LINK_TRAIN_NONE;
2347                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2348         }
2349         I915_WRITE(reg, temp);
2350
2351         reg = FDI_RX_CTL(pipe);
2352         temp = I915_READ(reg);
2353         if (HAS_PCH_CPT(dev)) {
2354                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356         } else {
2357                 temp &= ~FDI_LINK_TRAIN_NONE;
2358                 temp |= FDI_LINK_TRAIN_NONE;
2359         }
2360         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362         /* wait one idle pattern time */
2363         POSTING_READ(reg);
2364         udelay(1000);
2365
2366         /* IVB wants error correction enabled */
2367         if (IS_IVYBRIDGE(dev))
2368                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369                            FDI_FE_ERRC_ENABLE);
2370 }
2371
2372 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373 {
2374         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375 }
2376
2377 static void ivb_modeset_global_resources(struct drm_device *dev)
2378 {
2379         struct drm_i915_private *dev_priv = dev->dev_private;
2380         struct intel_crtc *pipe_B_crtc =
2381                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382         struct intel_crtc *pipe_C_crtc =
2383                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384         uint32_t temp;
2385
2386         /*
2387          * When everything is off disable fdi C so that we could enable fdi B
2388          * with all lanes. Note that we don't care about enabled pipes without
2389          * an enabled pch encoder.
2390          */
2391         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392             !pipe_has_enabled_pch(pipe_C_crtc)) {
2393                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396                 temp = I915_READ(SOUTH_CHICKEN1);
2397                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399                 I915_WRITE(SOUTH_CHICKEN1, temp);
2400         }
2401 }
2402
2403 /* The FDI link training functions for ILK/Ibexpeak. */
2404 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405 {
2406         struct drm_device *dev = crtc->dev;
2407         struct drm_i915_private *dev_priv = dev->dev_private;
2408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409         int pipe = intel_crtc->pipe;
2410         int plane = intel_crtc->plane;
2411         u32 reg, temp, tries;
2412
2413         /* FDI needs bits from pipe & plane first */
2414         assert_pipe_enabled(dev_priv, pipe);
2415         assert_plane_enabled(dev_priv, plane);
2416
2417         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418            for train result */
2419         reg = FDI_RX_IMR(pipe);
2420         temp = I915_READ(reg);
2421         temp &= ~FDI_RX_SYMBOL_LOCK;
2422         temp &= ~FDI_RX_BIT_LOCK;
2423         I915_WRITE(reg, temp);
2424         I915_READ(reg);
2425         udelay(150);
2426
2427         /* enable CPU FDI TX and PCH FDI RX */
2428         reg = FDI_TX_CTL(pipe);
2429         temp = I915_READ(reg);
2430         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2432         temp &= ~FDI_LINK_TRAIN_NONE;
2433         temp |= FDI_LINK_TRAIN_PATTERN_1;
2434         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         temp &= ~FDI_LINK_TRAIN_NONE;
2439         temp |= FDI_LINK_TRAIN_PATTERN_1;
2440         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442         POSTING_READ(reg);
2443         udelay(150);
2444
2445         /* Ironlake workaround, enable clock pointer after FDI enable*/
2446         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448                    FDI_RX_PHASE_SYNC_POINTER_EN);
2449
2450         reg = FDI_RX_IIR(pipe);
2451         for (tries = 0; tries < 5; tries++) {
2452                 temp = I915_READ(reg);
2453                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455                 if ((temp & FDI_RX_BIT_LOCK)) {
2456                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2457                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2458                         break;
2459                 }
2460         }
2461         if (tries == 5)
2462                 DRM_ERROR("FDI train 1 fail!\n");
2463
2464         /* Train 2 */
2465         reg = FDI_TX_CTL(pipe);
2466         temp = I915_READ(reg);
2467         temp &= ~FDI_LINK_TRAIN_NONE;
2468         temp |= FDI_LINK_TRAIN_PATTERN_2;
2469         I915_WRITE(reg, temp);
2470
2471         reg = FDI_RX_CTL(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~FDI_LINK_TRAIN_NONE;
2474         temp |= FDI_LINK_TRAIN_PATTERN_2;
2475         I915_WRITE(reg, temp);
2476
2477         POSTING_READ(reg);
2478         udelay(150);
2479
2480         reg = FDI_RX_IIR(pipe);
2481         for (tries = 0; tries < 5; tries++) {
2482                 temp = I915_READ(reg);
2483                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485                 if (temp & FDI_RX_SYMBOL_LOCK) {
2486                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2487                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2488                         break;
2489                 }
2490         }
2491         if (tries == 5)
2492                 DRM_ERROR("FDI train 2 fail!\n");
2493
2494         DRM_DEBUG_KMS("FDI train done\n");
2495
2496 }
2497
2498 static const int snb_b_fdi_train_param[] = {
2499         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503 };
2504
2505 /* The FDI link training functions for SNB/Cougarpoint. */
2506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507 {
2508         struct drm_device *dev = crtc->dev;
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511         int pipe = intel_crtc->pipe;
2512         u32 reg, temp, i, retry;
2513
2514         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515            for train result */
2516         reg = FDI_RX_IMR(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~FDI_RX_SYMBOL_LOCK;
2519         temp &= ~FDI_RX_BIT_LOCK;
2520         I915_WRITE(reg, temp);
2521
2522         POSTING_READ(reg);
2523         udelay(150);
2524
2525         /* enable CPU FDI TX and PCH FDI RX */
2526         reg = FDI_TX_CTL(pipe);
2527         temp = I915_READ(reg);
2528         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2530         temp &= ~FDI_LINK_TRAIN_NONE;
2531         temp |= FDI_LINK_TRAIN_PATTERN_1;
2532         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533         /* SNB-B */
2534         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2535         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2536
2537         I915_WRITE(FDI_RX_MISC(pipe),
2538                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
2540         reg = FDI_RX_CTL(pipe);
2541         temp = I915_READ(reg);
2542         if (HAS_PCH_CPT(dev)) {
2543                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545         } else {
2546                 temp &= ~FDI_LINK_TRAIN_NONE;
2547                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548         }
2549         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551         POSTING_READ(reg);
2552         udelay(150);
2553
2554         for (i = 0; i < 4; i++) {
2555                 reg = FDI_TX_CTL(pipe);
2556                 temp = I915_READ(reg);
2557                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558                 temp |= snb_b_fdi_train_param[i];
2559                 I915_WRITE(reg, temp);
2560
2561                 POSTING_READ(reg);
2562                 udelay(500);
2563
2564                 for (retry = 0; retry < 5; retry++) {
2565                         reg = FDI_RX_IIR(pipe);
2566                         temp = I915_READ(reg);
2567                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568                         if (temp & FDI_RX_BIT_LOCK) {
2569                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571                                 break;
2572                         }
2573                         udelay(50);
2574                 }
2575                 if (retry < 5)
2576                         break;
2577         }
2578         if (i == 4)
2579                 DRM_ERROR("FDI train 1 fail!\n");
2580
2581         /* Train 2 */
2582         reg = FDI_TX_CTL(pipe);
2583         temp = I915_READ(reg);
2584         temp &= ~FDI_LINK_TRAIN_NONE;
2585         temp |= FDI_LINK_TRAIN_PATTERN_2;
2586         if (IS_GEN6(dev)) {
2587                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588                 /* SNB-B */
2589                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590         }
2591         I915_WRITE(reg, temp);
2592
2593         reg = FDI_RX_CTL(pipe);
2594         temp = I915_READ(reg);
2595         if (HAS_PCH_CPT(dev)) {
2596                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598         } else {
2599                 temp &= ~FDI_LINK_TRAIN_NONE;
2600                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601         }
2602         I915_WRITE(reg, temp);
2603
2604         POSTING_READ(reg);
2605         udelay(150);
2606
2607         for (i = 0; i < 4; i++) {
2608                 reg = FDI_TX_CTL(pipe);
2609                 temp = I915_READ(reg);
2610                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611                 temp |= snb_b_fdi_train_param[i];
2612                 I915_WRITE(reg, temp);
2613
2614                 POSTING_READ(reg);
2615                 udelay(500);
2616
2617                 for (retry = 0; retry < 5; retry++) {
2618                         reg = FDI_RX_IIR(pipe);
2619                         temp = I915_READ(reg);
2620                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621                         if (temp & FDI_RX_SYMBOL_LOCK) {
2622                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624                                 break;
2625                         }
2626                         udelay(50);
2627                 }
2628                 if (retry < 5)
2629                         break;
2630         }
2631         if (i == 4)
2632                 DRM_ERROR("FDI train 2 fail!\n");
2633
2634         DRM_DEBUG_KMS("FDI train done.\n");
2635 }
2636
2637 /* Manual link training for Ivy Bridge A0 parts */
2638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639 {
2640         struct drm_device *dev = crtc->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643         int pipe = intel_crtc->pipe;
2644         u32 reg, temp, i;
2645
2646         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647            for train result */
2648         reg = FDI_RX_IMR(pipe);
2649         temp = I915_READ(reg);
2650         temp &= ~FDI_RX_SYMBOL_LOCK;
2651         temp &= ~FDI_RX_BIT_LOCK;
2652         I915_WRITE(reg, temp);
2653
2654         POSTING_READ(reg);
2655         udelay(150);
2656
2657         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658                       I915_READ(FDI_RX_IIR(pipe)));
2659
2660         /* enable CPU FDI TX and PCH FDI RX */
2661         reg = FDI_TX_CTL(pipe);
2662         temp = I915_READ(reg);
2663         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2664         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2665         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2667         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2669         temp |= FDI_COMPOSITE_SYNC;
2670         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2671
2672         I915_WRITE(FDI_RX_MISC(pipe),
2673                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2674
2675         reg = FDI_RX_CTL(pipe);
2676         temp = I915_READ(reg);
2677         temp &= ~FDI_LINK_TRAIN_AUTO;
2678         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2680         temp |= FDI_COMPOSITE_SYNC;
2681         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2682
2683         POSTING_READ(reg);
2684         udelay(150);
2685
2686         for (i = 0; i < 4; i++) {
2687                 reg = FDI_TX_CTL(pipe);
2688                 temp = I915_READ(reg);
2689                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690                 temp |= snb_b_fdi_train_param[i];
2691                 I915_WRITE(reg, temp);
2692
2693                 POSTING_READ(reg);
2694                 udelay(500);
2695
2696                 reg = FDI_RX_IIR(pipe);
2697                 temp = I915_READ(reg);
2698                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700                 if (temp & FDI_RX_BIT_LOCK ||
2701                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2702                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2703                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2704                         break;
2705                 }
2706         }
2707         if (i == 4)
2708                 DRM_ERROR("FDI train 1 fail!\n");
2709
2710         /* Train 2 */
2711         reg = FDI_TX_CTL(pipe);
2712         temp = I915_READ(reg);
2713         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2715         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2717         I915_WRITE(reg, temp);
2718
2719         reg = FDI_RX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2723         I915_WRITE(reg, temp);
2724
2725         POSTING_READ(reg);
2726         udelay(150);
2727
2728         for (i = 0; i < 4; i++) {
2729                 reg = FDI_TX_CTL(pipe);
2730                 temp = I915_READ(reg);
2731                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732                 temp |= snb_b_fdi_train_param[i];
2733                 I915_WRITE(reg, temp);
2734
2735                 POSTING_READ(reg);
2736                 udelay(500);
2737
2738                 reg = FDI_RX_IIR(pipe);
2739                 temp = I915_READ(reg);
2740                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2741
2742                 if (temp & FDI_RX_SYMBOL_LOCK) {
2743                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2744                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2745                         break;
2746                 }
2747         }
2748         if (i == 4)
2749                 DRM_ERROR("FDI train 2 fail!\n");
2750
2751         DRM_DEBUG_KMS("FDI train done.\n");
2752 }
2753
2754 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2755 {
2756         struct drm_device *dev = intel_crtc->base.dev;
2757         struct drm_i915_private *dev_priv = dev->dev_private;
2758         int pipe = intel_crtc->pipe;
2759         u32 reg, temp;
2760
2761
2762         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2763         reg = FDI_RX_CTL(pipe);
2764         temp = I915_READ(reg);
2765         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2766         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2767         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2768         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2769
2770         POSTING_READ(reg);
2771         udelay(200);
2772
2773         /* Switch from Rawclk to PCDclk */
2774         temp = I915_READ(reg);
2775         I915_WRITE(reg, temp | FDI_PCDCLK);
2776
2777         POSTING_READ(reg);
2778         udelay(200);
2779
2780         /* Enable CPU FDI TX PLL, always on for Ironlake */
2781         reg = FDI_TX_CTL(pipe);
2782         temp = I915_READ(reg);
2783         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2784                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2785
2786                 POSTING_READ(reg);
2787                 udelay(100);
2788         }
2789 }
2790
2791 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2792 {
2793         struct drm_device *dev = intel_crtc->base.dev;
2794         struct drm_i915_private *dev_priv = dev->dev_private;
2795         int pipe = intel_crtc->pipe;
2796         u32 reg, temp;
2797
2798         /* Switch from PCDclk to Rawclk */
2799         reg = FDI_RX_CTL(pipe);
2800         temp = I915_READ(reg);
2801         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2802
2803         /* Disable CPU FDI TX PLL */
2804         reg = FDI_TX_CTL(pipe);
2805         temp = I915_READ(reg);
2806         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2807
2808         POSTING_READ(reg);
2809         udelay(100);
2810
2811         reg = FDI_RX_CTL(pipe);
2812         temp = I915_READ(reg);
2813         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2814
2815         /* Wait for the clocks to turn off. */
2816         POSTING_READ(reg);
2817         udelay(100);
2818 }
2819
2820 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2821 {
2822         struct drm_device *dev = crtc->dev;
2823         struct drm_i915_private *dev_priv = dev->dev_private;
2824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825         int pipe = intel_crtc->pipe;
2826         u32 reg, temp;
2827
2828         /* disable CPU FDI tx and PCH FDI rx */
2829         reg = FDI_TX_CTL(pipe);
2830         temp = I915_READ(reg);
2831         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2832         POSTING_READ(reg);
2833
2834         reg = FDI_RX_CTL(pipe);
2835         temp = I915_READ(reg);
2836         temp &= ~(0x7 << 16);
2837         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2838         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2839
2840         POSTING_READ(reg);
2841         udelay(100);
2842
2843         /* Ironlake workaround, disable clock pointer after downing FDI */
2844         if (HAS_PCH_IBX(dev)) {
2845                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2846         }
2847
2848         /* still set train pattern 1 */
2849         reg = FDI_TX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         temp &= ~FDI_LINK_TRAIN_NONE;
2852         temp |= FDI_LINK_TRAIN_PATTERN_1;
2853         I915_WRITE(reg, temp);
2854
2855         reg = FDI_RX_CTL(pipe);
2856         temp = I915_READ(reg);
2857         if (HAS_PCH_CPT(dev)) {
2858                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2859                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2860         } else {
2861                 temp &= ~FDI_LINK_TRAIN_NONE;
2862                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2863         }
2864         /* BPC in FDI rx is consistent with that in PIPECONF */
2865         temp &= ~(0x07 << 16);
2866         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2867         I915_WRITE(reg, temp);
2868
2869         POSTING_READ(reg);
2870         udelay(100);
2871 }
2872
2873 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2874 {
2875         struct drm_device *dev = crtc->dev;
2876         struct drm_i915_private *dev_priv = dev->dev_private;
2877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2878         unsigned long flags;
2879         bool pending;
2880
2881         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2882             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2883                 return false;
2884
2885         spin_lock_irqsave(&dev->event_lock, flags);
2886         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2887         spin_unlock_irqrestore(&dev->event_lock, flags);
2888
2889         return pending;
2890 }
2891
2892 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2893 {
2894         struct drm_device *dev = crtc->dev;
2895         struct drm_i915_private *dev_priv = dev->dev_private;
2896
2897         if (crtc->fb == NULL)
2898                 return;
2899
2900         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2901
2902         wait_event(dev_priv->pending_flip_queue,
2903                    !intel_crtc_has_pending_flip(crtc));
2904
2905         mutex_lock(&dev->struct_mutex);
2906         intel_finish_fb(crtc->fb);
2907         mutex_unlock(&dev->struct_mutex);
2908 }
2909
2910 /* Program iCLKIP clock to the desired frequency */
2911 static void lpt_program_iclkip(struct drm_crtc *crtc)
2912 {
2913         struct drm_device *dev = crtc->dev;
2914         struct drm_i915_private *dev_priv = dev->dev_private;
2915         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2916         u32 temp;
2917
2918         mutex_lock(&dev_priv->dpio_lock);
2919
2920         /* It is necessary to ungate the pixclk gate prior to programming
2921          * the divisors, and gate it back when it is done.
2922          */
2923         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2924
2925         /* Disable SSCCTL */
2926         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2927                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2928                                 SBI_SSCCTL_DISABLE,
2929                         SBI_ICLK);
2930
2931         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2932         if (crtc->mode.clock == 20000) {
2933                 auxdiv = 1;
2934                 divsel = 0x41;
2935                 phaseinc = 0x20;
2936         } else {
2937                 /* The iCLK virtual clock root frequency is in MHz,
2938                  * but the crtc->mode.clock in in KHz. To get the divisors,
2939                  * it is necessary to divide one by another, so we
2940                  * convert the virtual clock precision to KHz here for higher
2941                  * precision.
2942                  */
2943                 u32 iclk_virtual_root_freq = 172800 * 1000;
2944                 u32 iclk_pi_range = 64;
2945                 u32 desired_divisor, msb_divisor_value, pi_value;
2946
2947                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2948                 msb_divisor_value = desired_divisor / iclk_pi_range;
2949                 pi_value = desired_divisor % iclk_pi_range;
2950
2951                 auxdiv = 0;
2952                 divsel = msb_divisor_value - 2;
2953                 phaseinc = pi_value;
2954         }
2955
2956         /* This should not happen with any sane values */
2957         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2958                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2959         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2960                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2961
2962         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2963                         crtc->mode.clock,
2964                         auxdiv,
2965                         divsel,
2966                         phasedir,
2967                         phaseinc);
2968
2969         /* Program SSCDIVINTPHASE6 */
2970         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2971         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2972         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2973         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2974         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2975         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2976         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2977         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2978
2979         /* Program SSCAUXDIV */
2980         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2981         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2982         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2983         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2984
2985         /* Enable modulator and associated divider */
2986         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2987         temp &= ~SBI_SSCCTL_DISABLE;
2988         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2989
2990         /* Wait for initialization time */
2991         udelay(24);
2992
2993         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2994
2995         mutex_unlock(&dev_priv->dpio_lock);
2996 }
2997
2998 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2999                                                 enum pipe pch_transcoder)
3000 {
3001         struct drm_device *dev = crtc->base.dev;
3002         struct drm_i915_private *dev_priv = dev->dev_private;
3003         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3004
3005         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3006                    I915_READ(HTOTAL(cpu_transcoder)));
3007         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3008                    I915_READ(HBLANK(cpu_transcoder)));
3009         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3010                    I915_READ(HSYNC(cpu_transcoder)));
3011
3012         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3013                    I915_READ(VTOTAL(cpu_transcoder)));
3014         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3015                    I915_READ(VBLANK(cpu_transcoder)));
3016         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3017                    I915_READ(VSYNC(cpu_transcoder)));
3018         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3019                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3020 }
3021
3022 /*
3023  * Enable PCH resources required for PCH ports:
3024  *   - PCH PLLs
3025  *   - FDI training & RX/TX
3026  *   - update transcoder timings
3027  *   - DP transcoding bits
3028  *   - transcoder
3029  */
3030 static void ironlake_pch_enable(struct drm_crtc *crtc)
3031 {
3032         struct drm_device *dev = crtc->dev;
3033         struct drm_i915_private *dev_priv = dev->dev_private;
3034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035         int pipe = intel_crtc->pipe;
3036         u32 reg, temp;
3037
3038         assert_pch_transcoder_disabled(dev_priv, pipe);
3039
3040         /* Write the TU size bits before fdi link training, so that error
3041          * detection works. */
3042         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3043                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3044
3045         /* For PCH output, training FDI link */
3046         dev_priv->display.fdi_link_train(crtc);
3047
3048         /* XXX: pch pll's can be enabled any time before we enable the PCH
3049          * transcoder, and we actually should do this to not upset any PCH
3050          * transcoder that already use the clock when we share it.
3051          *
3052          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3053          * unconditionally resets the pll - we need that to have the right LVDS
3054          * enable sequence. */
3055         ironlake_enable_pch_pll(intel_crtc);
3056
3057         if (HAS_PCH_CPT(dev)) {
3058                 u32 sel;
3059
3060                 temp = I915_READ(PCH_DPLL_SEL);
3061                 switch (pipe) {
3062                 default:
3063                 case 0:
3064                         temp |= TRANSA_DPLL_ENABLE;
3065                         sel = TRANSA_DPLLB_SEL;
3066                         break;
3067                 case 1:
3068                         temp |= TRANSB_DPLL_ENABLE;
3069                         sel = TRANSB_DPLLB_SEL;
3070                         break;
3071                 case 2:
3072                         temp |= TRANSC_DPLL_ENABLE;
3073                         sel = TRANSC_DPLLB_SEL;
3074                         break;
3075                 }
3076                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3077                         temp |= sel;
3078                 else
3079                         temp &= ~sel;
3080                 I915_WRITE(PCH_DPLL_SEL, temp);
3081         }
3082
3083         /* set transcoder timing, panel must allow it */
3084         assert_panel_unlocked(dev_priv, pipe);
3085         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3086
3087         intel_fdi_normal_train(crtc);
3088
3089         /* For PCH DP, enable TRANS_DP_CTL */
3090         if (HAS_PCH_CPT(dev) &&
3091             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3092              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3093                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3094                 reg = TRANS_DP_CTL(pipe);
3095                 temp = I915_READ(reg);
3096                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3097                           TRANS_DP_SYNC_MASK |
3098                           TRANS_DP_BPC_MASK);
3099                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3100                          TRANS_DP_ENH_FRAMING);
3101                 temp |= bpc << 9; /* same format but at 11:9 */
3102
3103                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3104                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3105                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3106                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3107
3108                 switch (intel_trans_dp_port_sel(crtc)) {
3109                 case PCH_DP_B:
3110                         temp |= TRANS_DP_PORT_SEL_B;
3111                         break;
3112                 case PCH_DP_C:
3113                         temp |= TRANS_DP_PORT_SEL_C;
3114                         break;
3115                 case PCH_DP_D:
3116                         temp |= TRANS_DP_PORT_SEL_D;
3117                         break;
3118                 default:
3119                         BUG();
3120                 }
3121
3122                 I915_WRITE(reg, temp);
3123         }
3124
3125         ironlake_enable_pch_transcoder(dev_priv, pipe);
3126 }
3127
3128 static void lpt_pch_enable(struct drm_crtc *crtc)
3129 {
3130         struct drm_device *dev = crtc->dev;
3131         struct drm_i915_private *dev_priv = dev->dev_private;
3132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3133         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3134
3135         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3136
3137         lpt_program_iclkip(crtc);
3138
3139         /* Set transcoder timing. */
3140         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3141
3142         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3143 }
3144
3145 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3146 {
3147         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3148
3149         if (pll == NULL)
3150                 return;
3151
3152         if (pll->refcount == 0) {
3153                 WARN(1, "bad PCH PLL refcount\n");
3154                 return;
3155         }
3156
3157         --pll->refcount;
3158         intel_crtc->pch_pll = NULL;
3159 }
3160
3161 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3162 {
3163         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3164         struct intel_pch_pll *pll;
3165         int i;
3166
3167         pll = intel_crtc->pch_pll;
3168         if (pll) {
3169                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3170                               intel_crtc->base.base.id, pll->pll_reg);
3171                 goto prepare;
3172         }
3173
3174         if (HAS_PCH_IBX(dev_priv->dev)) {
3175                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3176                 i = intel_crtc->pipe;
3177                 pll = &dev_priv->pch_plls[i];
3178
3179                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3180                               intel_crtc->base.base.id, pll->pll_reg);
3181
3182                 goto found;
3183         }
3184
3185         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3186                 pll = &dev_priv->pch_plls[i];
3187
3188                 /* Only want to check enabled timings first */
3189                 if (pll->refcount == 0)
3190                         continue;
3191
3192                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3193                     fp == I915_READ(pll->fp0_reg)) {
3194                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3195                                       intel_crtc->base.base.id,
3196                                       pll->pll_reg, pll->refcount, pll->active);
3197
3198                         goto found;
3199                 }
3200         }
3201
3202         /* Ok no matching timings, maybe there's a free one? */
3203         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3204                 pll = &dev_priv->pch_plls[i];
3205                 if (pll->refcount == 0) {
3206                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3207                                       intel_crtc->base.base.id, pll->pll_reg);
3208                         goto found;
3209                 }
3210         }
3211
3212         return NULL;
3213
3214 found:
3215         intel_crtc->pch_pll = pll;
3216         pll->refcount++;
3217         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3218 prepare: /* separate function? */
3219         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3220
3221         /* Wait for the clocks to stabilize before rewriting the regs */
3222         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3223         POSTING_READ(pll->pll_reg);
3224         udelay(150);
3225
3226         I915_WRITE(pll->fp0_reg, fp);
3227         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3228         pll->on = false;
3229         return pll;
3230 }
3231
3232 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3233 {
3234         struct drm_i915_private *dev_priv = dev->dev_private;
3235         int dslreg = PIPEDSL(pipe);
3236         u32 temp;
3237
3238         temp = I915_READ(dslreg);
3239         udelay(500);
3240         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3241                 if (wait_for(I915_READ(dslreg) != temp, 5))
3242                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3243         }
3244 }
3245
3246 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3247 {
3248         struct drm_device *dev = crtc->base.dev;
3249         struct drm_i915_private *dev_priv = dev->dev_private;
3250         int pipe = crtc->pipe;
3251
3252         if (crtc->config.pch_pfit.size) {
3253                 /* Force use of hard-coded filter coefficients
3254                  * as some pre-programmed values are broken,
3255                  * e.g. x201.
3256                  */
3257                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3258                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3259                                                  PF_PIPE_SEL_IVB(pipe));
3260                 else
3261                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3262                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3263                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3264         }
3265 }
3266
3267 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3268 {
3269         struct drm_device *dev = crtc->dev;
3270         struct drm_i915_private *dev_priv = dev->dev_private;
3271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3272         struct intel_encoder *encoder;
3273         int pipe = intel_crtc->pipe;
3274         int plane = intel_crtc->plane;
3275         u32 temp;
3276
3277         WARN_ON(!crtc->enabled);
3278
3279         if (intel_crtc->active)
3280                 return;
3281
3282         intel_crtc->active = true;
3283
3284         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3285         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3286
3287         intel_update_watermarks(dev);
3288
3289         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3290                 temp = I915_READ(PCH_LVDS);
3291                 if ((temp & LVDS_PORT_EN) == 0)
3292                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3293         }
3294
3295
3296         if (intel_crtc->config.has_pch_encoder) {
3297                 /* Note: FDI PLL enabling _must_ be done before we enable the
3298                  * cpu pipes, hence this is separate from all the other fdi/pch
3299                  * enabling. */
3300                 ironlake_fdi_pll_enable(intel_crtc);
3301         } else {
3302                 assert_fdi_tx_disabled(dev_priv, pipe);
3303                 assert_fdi_rx_disabled(dev_priv, pipe);
3304         }
3305
3306         for_each_encoder_on_crtc(dev, crtc, encoder)
3307                 if (encoder->pre_enable)
3308                         encoder->pre_enable(encoder);
3309
3310         /* Enable panel fitting for LVDS */
3311         ironlake_pfit_enable(intel_crtc);
3312
3313         /*
3314          * On ILK+ LUT must be loaded before the pipe is running but with
3315          * clocks enabled
3316          */
3317         intel_crtc_load_lut(crtc);
3318
3319         intel_enable_pipe(dev_priv, pipe,
3320                           intel_crtc->config.has_pch_encoder);
3321         intel_enable_plane(dev_priv, plane, pipe);
3322
3323         if (intel_crtc->config.has_pch_encoder)
3324                 ironlake_pch_enable(crtc);
3325
3326         mutex_lock(&dev->struct_mutex);
3327         intel_update_fbc(dev);
3328         mutex_unlock(&dev->struct_mutex);
3329
3330         intel_crtc_update_cursor(crtc, true);
3331
3332         for_each_encoder_on_crtc(dev, crtc, encoder)
3333                 encoder->enable(encoder);
3334
3335         if (HAS_PCH_CPT(dev))
3336                 cpt_verify_modeset(dev, intel_crtc->pipe);
3337
3338         /*
3339          * There seems to be a race in PCH platform hw (at least on some
3340          * outputs) where an enabled pipe still completes any pageflip right
3341          * away (as if the pipe is off) instead of waiting for vblank. As soon
3342          * as the first vblank happend, everything works as expected. Hence just
3343          * wait for one vblank before returning to avoid strange things
3344          * happening.
3345          */
3346         intel_wait_for_vblank(dev, intel_crtc->pipe);
3347 }
3348
3349 static void haswell_crtc_enable(struct drm_crtc *crtc)
3350 {
3351         struct drm_device *dev = crtc->dev;
3352         struct drm_i915_private *dev_priv = dev->dev_private;
3353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354         struct intel_encoder *encoder;
3355         int pipe = intel_crtc->pipe;
3356         int plane = intel_crtc->plane;
3357
3358         WARN_ON(!crtc->enabled);
3359
3360         if (intel_crtc->active)
3361                 return;
3362
3363         intel_crtc->active = true;
3364
3365         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3366         if (intel_crtc->config.has_pch_encoder)
3367                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3368
3369         intel_update_watermarks(dev);
3370
3371         if (intel_crtc->config.has_pch_encoder)
3372                 dev_priv->display.fdi_link_train(crtc);
3373
3374         for_each_encoder_on_crtc(dev, crtc, encoder)
3375                 if (encoder->pre_enable)
3376                         encoder->pre_enable(encoder);
3377
3378         intel_ddi_enable_pipe_clock(intel_crtc);
3379
3380         /* Enable panel fitting for eDP */
3381         ironlake_pfit_enable(intel_crtc);
3382
3383         /*
3384          * On ILK+ LUT must be loaded before the pipe is running but with
3385          * clocks enabled
3386          */
3387         intel_crtc_load_lut(crtc);
3388
3389         intel_ddi_set_pipe_settings(crtc);
3390         intel_ddi_enable_transcoder_func(crtc);
3391
3392         intel_enable_pipe(dev_priv, pipe,
3393                           intel_crtc->config.has_pch_encoder);
3394         intel_enable_plane(dev_priv, plane, pipe);
3395
3396         if (intel_crtc->config.has_pch_encoder)
3397                 lpt_pch_enable(crtc);
3398
3399         mutex_lock(&dev->struct_mutex);
3400         intel_update_fbc(dev);
3401         mutex_unlock(&dev->struct_mutex);
3402
3403         intel_crtc_update_cursor(crtc, true);
3404
3405         for_each_encoder_on_crtc(dev, crtc, encoder)
3406                 encoder->enable(encoder);
3407
3408         /*
3409          * There seems to be a race in PCH platform hw (at least on some
3410          * outputs) where an enabled pipe still completes any pageflip right
3411          * away (as if the pipe is off) instead of waiting for vblank. As soon
3412          * as the first vblank happend, everything works as expected. Hence just
3413          * wait for one vblank before returning to avoid strange things
3414          * happening.
3415          */
3416         intel_wait_for_vblank(dev, intel_crtc->pipe);
3417 }
3418
3419 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3420 {
3421         struct drm_device *dev = crtc->dev;
3422         struct drm_i915_private *dev_priv = dev->dev_private;
3423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3424         struct intel_encoder *encoder;
3425         int pipe = intel_crtc->pipe;
3426         int plane = intel_crtc->plane;
3427         u32 reg, temp;
3428
3429
3430         if (!intel_crtc->active)
3431                 return;
3432
3433         for_each_encoder_on_crtc(dev, crtc, encoder)
3434                 encoder->disable(encoder);
3435
3436         intel_crtc_wait_for_pending_flips(crtc);
3437         drm_vblank_off(dev, pipe);
3438         intel_crtc_update_cursor(crtc, false);
3439
3440         intel_disable_plane(dev_priv, plane, pipe);
3441
3442         if (dev_priv->cfb_plane == plane)
3443                 intel_disable_fbc(dev);
3444
3445         intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3446         intel_disable_pipe(dev_priv, pipe);
3447
3448         /* Disable PF */
3449         I915_WRITE(PF_CTL(pipe), 0);
3450         I915_WRITE(PF_WIN_SZ(pipe), 0);
3451
3452         for_each_encoder_on_crtc(dev, crtc, encoder)
3453                 if (encoder->post_disable)
3454                         encoder->post_disable(encoder);
3455
3456         ironlake_fdi_disable(crtc);
3457
3458         ironlake_disable_pch_transcoder(dev_priv, pipe);
3459         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3460
3461         if (HAS_PCH_CPT(dev)) {
3462                 /* disable TRANS_DP_CTL */
3463                 reg = TRANS_DP_CTL(pipe);
3464                 temp = I915_READ(reg);
3465                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3466                 temp |= TRANS_DP_PORT_SEL_NONE;
3467                 I915_WRITE(reg, temp);
3468
3469                 /* disable DPLL_SEL */
3470                 temp = I915_READ(PCH_DPLL_SEL);
3471                 switch (pipe) {
3472                 case 0:
3473                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3474                         break;
3475                 case 1:
3476                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3477                         break;
3478                 case 2:
3479                         /* C shares PLL A or B */
3480                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3481                         break;
3482                 default:
3483                         BUG(); /* wtf */
3484                 }
3485                 I915_WRITE(PCH_DPLL_SEL, temp);
3486         }
3487
3488         /* disable PCH DPLL */
3489         intel_disable_pch_pll(intel_crtc);
3490
3491         ironlake_fdi_pll_disable(intel_crtc);
3492
3493         intel_crtc->active = false;
3494         intel_update_watermarks(dev);
3495
3496         mutex_lock(&dev->struct_mutex);
3497         intel_update_fbc(dev);
3498         mutex_unlock(&dev->struct_mutex);
3499 }
3500
3501 static void haswell_crtc_disable(struct drm_crtc *crtc)
3502 {
3503         struct drm_device *dev = crtc->dev;
3504         struct drm_i915_private *dev_priv = dev->dev_private;
3505         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3506         struct intel_encoder *encoder;
3507         int pipe = intel_crtc->pipe;
3508         int plane = intel_crtc->plane;
3509         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3510
3511         if (!intel_crtc->active)
3512                 return;
3513
3514         for_each_encoder_on_crtc(dev, crtc, encoder)
3515                 encoder->disable(encoder);
3516
3517         intel_crtc_wait_for_pending_flips(crtc);
3518         drm_vblank_off(dev, pipe);
3519         intel_crtc_update_cursor(crtc, false);
3520
3521         intel_disable_plane(dev_priv, plane, pipe);
3522
3523         if (dev_priv->cfb_plane == plane)
3524                 intel_disable_fbc(dev);
3525
3526         if (intel_crtc->config.has_pch_encoder)
3527                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3528         intel_disable_pipe(dev_priv, pipe);
3529
3530         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3531
3532         /* XXX: Once we have proper panel fitter state tracking implemented with
3533          * hardware state read/check support we should switch to only disable
3534          * the panel fitter when we know it's used. */
3535         if (intel_using_power_well(dev)) {
3536                 I915_WRITE(PF_CTL(pipe), 0);
3537                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3538         }
3539
3540         intel_ddi_disable_pipe_clock(intel_crtc);
3541
3542         for_each_encoder_on_crtc(dev, crtc, encoder)
3543                 if (encoder->post_disable)
3544                         encoder->post_disable(encoder);
3545
3546         if (intel_crtc->config.has_pch_encoder) {
3547                 lpt_disable_pch_transcoder(dev_priv);
3548                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3549                 intel_ddi_fdi_disable(crtc);
3550         }
3551
3552         intel_crtc->active = false;
3553         intel_update_watermarks(dev);
3554
3555         mutex_lock(&dev->struct_mutex);
3556         intel_update_fbc(dev);
3557         mutex_unlock(&dev->struct_mutex);
3558 }
3559
3560 static void ironlake_crtc_off(struct drm_crtc *crtc)
3561 {
3562         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3563         intel_put_pch_pll(intel_crtc);
3564 }
3565
3566 static void haswell_crtc_off(struct drm_crtc *crtc)
3567 {
3568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3569
3570         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3571          * start using it. */
3572         intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3573
3574         intel_ddi_put_crtc_pll(crtc);
3575 }
3576
3577 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3578 {
3579         if (!enable && intel_crtc->overlay) {
3580                 struct drm_device *dev = intel_crtc->base.dev;
3581                 struct drm_i915_private *dev_priv = dev->dev_private;
3582
3583                 mutex_lock(&dev->struct_mutex);
3584                 dev_priv->mm.interruptible = false;
3585                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3586                 dev_priv->mm.interruptible = true;
3587                 mutex_unlock(&dev->struct_mutex);
3588         }
3589
3590         /* Let userspace switch the overlay on again. In most cases userspace
3591          * has to recompute where to put it anyway.
3592          */
3593 }
3594
3595 /**
3596  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3597  * cursor plane briefly if not already running after enabling the display
3598  * plane.
3599  * This workaround avoids occasional blank screens when self refresh is
3600  * enabled.
3601  */
3602 static void
3603 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3604 {
3605         u32 cntl = I915_READ(CURCNTR(pipe));
3606
3607         if ((cntl & CURSOR_MODE) == 0) {
3608                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3609
3610                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3611                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3612                 intel_wait_for_vblank(dev_priv->dev, pipe);
3613                 I915_WRITE(CURCNTR(pipe), cntl);
3614                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3615                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3616         }
3617 }
3618
3619 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3620 {
3621         struct drm_device *dev = crtc->base.dev;
3622         struct drm_i915_private *dev_priv = dev->dev_private;
3623         struct intel_crtc_config *pipe_config = &crtc->config;
3624
3625         if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3626               intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3627                 return;
3628
3629         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3630         assert_pipe_disabled(dev_priv, crtc->pipe);
3631
3632         /*
3633          * Enable automatic panel scaling so that non-native modes
3634          * fill the screen.  The panel fitter should only be
3635          * adjusted whilst the pipe is disabled, according to
3636          * register description and PRM.
3637          */
3638         DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
3639                       pipe_config->gmch_pfit.control,
3640                       pipe_config->gmch_pfit.pgm_ratios);
3641
3642         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3643         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3644
3645         /* Border color in case we don't scale up to the full screen. Black by
3646          * default, change to something else for debugging. */
3647         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3648 }
3649
3650 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3651 {
3652         struct drm_device *dev = crtc->dev;
3653         struct drm_i915_private *dev_priv = dev->dev_private;
3654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655         struct intel_encoder *encoder;
3656         int pipe = intel_crtc->pipe;
3657         int plane = intel_crtc->plane;
3658
3659         WARN_ON(!crtc->enabled);
3660
3661         if (intel_crtc->active)
3662                 return;
3663
3664         intel_crtc->active = true;
3665         intel_update_watermarks(dev);
3666
3667         mutex_lock(&dev_priv->dpio_lock);
3668
3669         for_each_encoder_on_crtc(dev, crtc, encoder)
3670                 if (encoder->pre_pll_enable)
3671                         encoder->pre_pll_enable(encoder);
3672
3673         intel_enable_pll(dev_priv, pipe);
3674
3675         for_each_encoder_on_crtc(dev, crtc, encoder)
3676                 if (encoder->pre_enable)
3677                         encoder->pre_enable(encoder);
3678
3679         /* VLV wants encoder enabling _before_ the pipe is up. */
3680         for_each_encoder_on_crtc(dev, crtc, encoder)
3681                 encoder->enable(encoder);
3682
3683         /* Enable panel fitting for eDP */
3684         i9xx_pfit_enable(intel_crtc);
3685
3686         intel_enable_pipe(dev_priv, pipe, false);
3687         intel_enable_plane(dev_priv, plane, pipe);
3688
3689         intel_crtc_load_lut(crtc);
3690         intel_update_fbc(dev);
3691
3692         /* Give the overlay scaler a chance to enable if it's on this pipe */
3693         intel_crtc_dpms_overlay(intel_crtc, true);
3694         intel_crtc_update_cursor(crtc, true);
3695
3696         mutex_unlock(&dev_priv->dpio_lock);
3697 }
3698
3699 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3700 {
3701         struct drm_device *dev = crtc->dev;
3702         struct drm_i915_private *dev_priv = dev->dev_private;
3703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3704         struct intel_encoder *encoder;
3705         int pipe = intel_crtc->pipe;
3706         int plane = intel_crtc->plane;
3707
3708         WARN_ON(!crtc->enabled);
3709
3710         if (intel_crtc->active)
3711                 return;
3712
3713         intel_crtc->active = true;
3714         intel_update_watermarks(dev);
3715
3716         intel_enable_pll(dev_priv, pipe);
3717
3718         for_each_encoder_on_crtc(dev, crtc, encoder)
3719                 if (encoder->pre_enable)
3720                         encoder->pre_enable(encoder);
3721
3722         /* Enable panel fitting for LVDS */
3723         i9xx_pfit_enable(intel_crtc);
3724
3725         intel_enable_pipe(dev_priv, pipe, false);
3726         intel_enable_plane(dev_priv, plane, pipe);
3727         if (IS_G4X(dev))
3728                 g4x_fixup_plane(dev_priv, pipe);
3729
3730         intel_crtc_load_lut(crtc);
3731         intel_update_fbc(dev);
3732
3733         /* Give the overlay scaler a chance to enable if it's on this pipe */
3734         intel_crtc_dpms_overlay(intel_crtc, true);
3735         intel_crtc_update_cursor(crtc, true);
3736
3737         for_each_encoder_on_crtc(dev, crtc, encoder)
3738                 encoder->enable(encoder);
3739 }
3740
3741 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3742 {
3743         struct drm_device *dev = crtc->base.dev;
3744         struct drm_i915_private *dev_priv = dev->dev_private;
3745         enum pipe pipe;
3746         uint32_t pctl = I915_READ(PFIT_CONTROL);
3747
3748         assert_pipe_disabled(dev_priv, crtc->pipe);
3749
3750         if (INTEL_INFO(dev)->gen >= 4)
3751                 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3752         else
3753                 pipe = PIPE_B;
3754
3755         if (pipe == crtc->pipe) {
3756                 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3757                 I915_WRITE(PFIT_CONTROL, 0);
3758         }
3759 }
3760
3761 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3762 {
3763         struct drm_device *dev = crtc->dev;
3764         struct drm_i915_private *dev_priv = dev->dev_private;
3765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3766         struct intel_encoder *encoder;
3767         int pipe = intel_crtc->pipe;
3768         int plane = intel_crtc->plane;
3769
3770         if (!intel_crtc->active)
3771                 return;
3772
3773         for_each_encoder_on_crtc(dev, crtc, encoder)
3774                 encoder->disable(encoder);
3775
3776         /* Give the overlay scaler a chance to disable if it's on this pipe */
3777         intel_crtc_wait_for_pending_flips(crtc);
3778         drm_vblank_off(dev, pipe);
3779         intel_crtc_dpms_overlay(intel_crtc, false);
3780         intel_crtc_update_cursor(crtc, false);
3781
3782         if (dev_priv->cfb_plane == plane)
3783                 intel_disable_fbc(dev);
3784
3785         intel_disable_plane(dev_priv, plane, pipe);
3786         intel_disable_pipe(dev_priv, pipe);
3787
3788         i9xx_pfit_disable(intel_crtc);
3789
3790         for_each_encoder_on_crtc(dev, crtc, encoder)
3791                 if (encoder->post_disable)
3792                         encoder->post_disable(encoder);
3793
3794         intel_disable_pll(dev_priv, pipe);
3795
3796         intel_crtc->active = false;
3797         intel_update_fbc(dev);
3798         intel_update_watermarks(dev);
3799 }
3800
3801 static void i9xx_crtc_off(struct drm_crtc *crtc)
3802 {
3803 }
3804
3805 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3806                                     bool enabled)
3807 {
3808         struct drm_device *dev = crtc->dev;
3809         struct drm_i915_master_private *master_priv;
3810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3811         int pipe = intel_crtc->pipe;
3812
3813         if (!dev->primary->master)
3814                 return;
3815
3816         master_priv = dev->primary->master->driver_priv;
3817         if (!master_priv->sarea_priv)
3818                 return;
3819
3820         switch (pipe) {
3821         case 0:
3822                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3823                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3824                 break;
3825         case 1:
3826                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3827                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3828                 break;
3829         default:
3830                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3831                 break;
3832         }
3833 }
3834
3835 /**
3836  * Sets the power management mode of the pipe and plane.
3837  */
3838 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3839 {
3840         struct drm_device *dev = crtc->dev;
3841         struct drm_i915_private *dev_priv = dev->dev_private;
3842         struct intel_encoder *intel_encoder;
3843         bool enable = false;
3844
3845         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3846                 enable |= intel_encoder->connectors_active;
3847
3848         if (enable)
3849                 dev_priv->display.crtc_enable(crtc);
3850         else
3851                 dev_priv->display.crtc_disable(crtc);
3852
3853         intel_crtc_update_sarea(crtc, enable);
3854 }
3855
3856 static void intel_crtc_disable(struct drm_crtc *crtc)
3857 {
3858         struct drm_device *dev = crtc->dev;
3859         struct drm_connector *connector;
3860         struct drm_i915_private *dev_priv = dev->dev_private;
3861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3862
3863         /* crtc should still be enabled when we disable it. */
3864         WARN_ON(!crtc->enabled);
3865
3866         intel_crtc->eld_vld = false;
3867         dev_priv->display.crtc_disable(crtc);
3868         intel_crtc_update_sarea(crtc, false);
3869         dev_priv->display.off(crtc);
3870
3871         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3872         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3873
3874         if (crtc->fb) {
3875                 mutex_lock(&dev->struct_mutex);
3876                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3877                 mutex_unlock(&dev->struct_mutex);
3878                 crtc->fb = NULL;
3879         }
3880
3881         /* Update computed state. */
3882         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3883                 if (!connector->encoder || !connector->encoder->crtc)
3884                         continue;
3885
3886                 if (connector->encoder->crtc != crtc)
3887                         continue;
3888
3889                 connector->dpms = DRM_MODE_DPMS_OFF;
3890                 to_intel_encoder(connector->encoder)->connectors_active = false;
3891         }
3892 }
3893
3894 void intel_modeset_disable(struct drm_device *dev)
3895 {
3896         struct drm_crtc *crtc;
3897
3898         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3899                 if (crtc->enabled)
3900                         intel_crtc_disable(crtc);
3901         }
3902 }
3903
3904 void intel_encoder_destroy(struct drm_encoder *encoder)
3905 {
3906         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3907
3908         drm_encoder_cleanup(encoder);
3909         kfree(intel_encoder);
3910 }
3911
3912 /* Simple dpms helper for encodres with just one connector, no cloning and only
3913  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3914  * state of the entire output pipe. */
3915 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3916 {
3917         if (mode == DRM_MODE_DPMS_ON) {
3918                 encoder->connectors_active = true;
3919
3920                 intel_crtc_update_dpms(encoder->base.crtc);
3921         } else {
3922                 encoder->connectors_active = false;
3923
3924                 intel_crtc_update_dpms(encoder->base.crtc);
3925         }
3926 }
3927
3928 /* Cross check the actual hw state with our own modeset state tracking (and it's
3929  * internal consistency). */
3930 static void intel_connector_check_state(struct intel_connector *connector)
3931 {
3932         if (connector->get_hw_state(connector)) {
3933                 struct intel_encoder *encoder = connector->encoder;
3934                 struct drm_crtc *crtc;
3935                 bool encoder_enabled;
3936                 enum pipe pipe;
3937
3938                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3939                               connector->base.base.id,
3940                               drm_get_connector_name(&connector->base));
3941
3942                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3943                      "wrong connector dpms state\n");
3944                 WARN(connector->base.encoder != &encoder->base,
3945                      "active connector not linked to encoder\n");
3946                 WARN(!encoder->connectors_active,
3947                      "encoder->connectors_active not set\n");
3948
3949                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3950                 WARN(!encoder_enabled, "encoder not enabled\n");
3951                 if (WARN_ON(!encoder->base.crtc))
3952                         return;
3953
3954                 crtc = encoder->base.crtc;
3955
3956                 WARN(!crtc->enabled, "crtc not enabled\n");
3957                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3958                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3959                      "encoder active on the wrong pipe\n");
3960         }
3961 }
3962
3963 /* Even simpler default implementation, if there's really no special case to
3964  * consider. */
3965 void intel_connector_dpms(struct drm_connector *connector, int mode)
3966 {
3967         struct intel_encoder *encoder = intel_attached_encoder(connector);
3968
3969         /* All the simple cases only support two dpms states. */
3970         if (mode != DRM_MODE_DPMS_ON)
3971                 mode = DRM_MODE_DPMS_OFF;
3972
3973         if (mode == connector->dpms)
3974                 return;
3975
3976         connector->dpms = mode;
3977
3978         /* Only need to change hw state when actually enabled */
3979         if (encoder->base.crtc)
3980                 intel_encoder_dpms(encoder, mode);
3981         else
3982                 WARN_ON(encoder->connectors_active != false);
3983
3984         intel_modeset_check_state(connector->dev);
3985 }
3986
3987 /* Simple connector->get_hw_state implementation for encoders that support only
3988  * one connector and no cloning and hence the encoder state determines the state
3989  * of the connector. */
3990 bool intel_connector_get_hw_state(struct intel_connector *connector)
3991 {
3992         enum pipe pipe = 0;
3993         struct intel_encoder *encoder = connector->encoder;
3994
3995         return encoder->get_hw_state(encoder, &pipe);
3996 }
3997
3998 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3999                                      struct intel_crtc_config *pipe_config)
4000 {
4001         struct drm_i915_private *dev_priv = dev->dev_private;
4002         struct intel_crtc *pipe_B_crtc =
4003                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4004
4005         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4006                       pipe_name(pipe), pipe_config->fdi_lanes);
4007         if (pipe_config->fdi_lanes > 4) {
4008                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4009                               pipe_name(pipe), pipe_config->fdi_lanes);
4010                 return false;
4011         }
4012
4013         if (IS_HASWELL(dev)) {
4014                 if (pipe_config->fdi_lanes > 2) {
4015                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4016                                       pipe_config->fdi_lanes);
4017                         return false;
4018                 } else {
4019                         return true;
4020                 }
4021         }
4022
4023         if (INTEL_INFO(dev)->num_pipes == 2)
4024                 return true;
4025
4026         /* Ivybridge 3 pipe is really complicated */
4027         switch (pipe) {
4028         case PIPE_A:
4029                 return true;
4030         case PIPE_B:
4031                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4032                     pipe_config->fdi_lanes > 2) {
4033                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4034                                       pipe_name(pipe), pipe_config->fdi_lanes);
4035                         return false;
4036                 }
4037                 return true;
4038         case PIPE_C:
4039                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4040                     pipe_B_crtc->config.fdi_lanes <= 2) {
4041                         if (pipe_config->fdi_lanes > 2) {
4042                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4043                                               pipe_name(pipe), pipe_config->fdi_lanes);
4044                                 return false;
4045                         }
4046                 } else {
4047                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4048                         return false;
4049                 }
4050                 return true;
4051         default:
4052                 BUG();
4053         }
4054 }
4055
4056 #define RETRY 1
4057 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4058                                        struct intel_crtc_config *pipe_config)
4059 {
4060         struct drm_device *dev = intel_crtc->base.dev;
4061         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4062         int target_clock, lane, link_bw;
4063         bool setup_ok, needs_recompute = false;
4064
4065 retry:
4066         /* FDI is a binary signal running at ~2.7GHz, encoding
4067          * each output octet as 10 bits. The actual frequency
4068          * is stored as a divider into a 100MHz clock, and the
4069          * mode pixel clock is stored in units of 1KHz.
4070          * Hence the bw of each lane in terms of the mode signal
4071          * is:
4072          */
4073         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4074
4075         if (pipe_config->pixel_target_clock)
4076                 target_clock = pipe_config->pixel_target_clock;
4077         else
4078                 target_clock = adjusted_mode->clock;
4079
4080         lane = ironlake_get_lanes_required(target_clock, link_bw,
4081                                            pipe_config->pipe_bpp);
4082
4083         pipe_config->fdi_lanes = lane;
4084
4085         if (pipe_config->pixel_multiplier > 1)
4086                 link_bw *= pipe_config->pixel_multiplier;
4087         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4088                                link_bw, &pipe_config->fdi_m_n);
4089
4090         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4091                                             intel_crtc->pipe, pipe_config);
4092         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4093                 pipe_config->pipe_bpp -= 2*3;
4094                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4095                               pipe_config->pipe_bpp);
4096                 needs_recompute = true;
4097                 pipe_config->bw_constrained = true;
4098
4099                 goto retry;
4100         }
4101
4102         if (needs_recompute)
4103                 return RETRY;
4104
4105         return setup_ok ? 0 : -EINVAL;
4106 }
4107
4108 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4109                                      struct intel_crtc_config *pipe_config)
4110 {
4111         struct drm_device *dev = crtc->dev;
4112         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4113
4114         if (HAS_PCH_SPLIT(dev)) {
4115                 /* FDI link clock is fixed at 2.7G */
4116                 if (pipe_config->requested_mode.clock * 3
4117                     > IRONLAKE_FDI_FREQ * 4)
4118                         return -EINVAL;
4119         }
4120
4121         /* All interlaced capable intel hw wants timings in frames. Note though
4122          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4123          * timings, so we need to be careful not to clobber these.*/
4124         if (!pipe_config->timings_set)
4125                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4126
4127         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4128          * with a hsync front porch of 0.
4129          */
4130         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4131                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4132                 return -EINVAL;
4133
4134         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4135                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4136         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4137                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4138                  * for lvds. */
4139                 pipe_config->pipe_bpp = 8*3;
4140         }
4141
4142         if (pipe_config->has_pch_encoder)
4143                 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
4144
4145         return 0;
4146 }
4147
4148 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4149 {
4150         return 400000; /* FIXME */
4151 }
4152
4153 static int i945_get_display_clock_speed(struct drm_device *dev)
4154 {
4155         return 400000;
4156 }
4157
4158 static int i915_get_display_clock_speed(struct drm_device *dev)
4159 {
4160         return 333000;
4161 }
4162
4163 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4164 {
4165         return 200000;
4166 }
4167
4168 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4169 {
4170         u16 gcfgc = 0;
4171
4172         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4173
4174         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4175                 return 133000;
4176         else {
4177                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4178                 case GC_DISPLAY_CLOCK_333_MHZ:
4179                         return 333000;
4180                 default:
4181                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4182                         return 190000;
4183                 }
4184         }
4185 }
4186
4187 static int i865_get_display_clock_speed(struct drm_device *dev)
4188 {
4189         return 266000;
4190 }
4191
4192 static int i855_get_display_clock_speed(struct drm_device *dev)
4193 {
4194         u16 hpllcc = 0;
4195         /* Assume that the hardware is in the high speed state.  This
4196          * should be the default.
4197          */
4198         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4199         case GC_CLOCK_133_200:
4200         case GC_CLOCK_100_200:
4201                 return 200000;
4202         case GC_CLOCK_166_250:
4203                 return 250000;
4204         case GC_CLOCK_100_133:
4205                 return 133000;
4206         }
4207
4208         /* Shouldn't happen */
4209         return 0;
4210 }
4211
4212 static int i830_get_display_clock_speed(struct drm_device *dev)
4213 {
4214         return 133000;
4215 }
4216
4217 static void
4218 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4219 {
4220         while (*num > 0xffffff || *den > 0xffffff) {
4221                 *num >>= 1;
4222                 *den >>= 1;
4223         }
4224 }
4225
4226 void
4227 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4228                        int pixel_clock, int link_clock,
4229                        struct intel_link_m_n *m_n)
4230 {
4231         m_n->tu = 64;
4232         m_n->gmch_m = bits_per_pixel * pixel_clock;
4233         m_n->gmch_n = link_clock * nlanes * 8;
4234         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4235         m_n->link_m = pixel_clock;
4236         m_n->link_n = link_clock;
4237         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4238 }
4239
4240 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4241 {
4242         if (i915_panel_use_ssc >= 0)
4243                 return i915_panel_use_ssc != 0;
4244         return dev_priv->lvds_use_ssc
4245                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4246 }
4247
4248 static int vlv_get_refclk(struct drm_crtc *crtc)
4249 {
4250         struct drm_device *dev = crtc->dev;
4251         struct drm_i915_private *dev_priv = dev->dev_private;
4252         int refclk = 27000; /* for DP & HDMI */
4253
4254         return 100000; /* only one validated so far */
4255
4256         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4257                 refclk = 96000;
4258         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4259                 if (intel_panel_use_ssc(dev_priv))
4260                         refclk = 100000;
4261                 else
4262                         refclk = 96000;
4263         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4264                 refclk = 100000;
4265         }
4266
4267         return refclk;
4268 }
4269
4270 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4271 {
4272         struct drm_device *dev = crtc->dev;
4273         struct drm_i915_private *dev_priv = dev->dev_private;
4274         int refclk;
4275
4276         if (IS_VALLEYVIEW(dev)) {
4277                 refclk = vlv_get_refclk(crtc);
4278         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4279             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4280                 refclk = dev_priv->lvds_ssc_freq * 1000;
4281                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4282                               refclk / 1000);
4283         } else if (!IS_GEN2(dev)) {
4284                 refclk = 96000;
4285         } else {
4286                 refclk = 48000;
4287         }
4288
4289         return refclk;
4290 }
4291
4292 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4293 {
4294         unsigned dotclock = crtc->config.adjusted_mode.clock;
4295         struct dpll *clock = &crtc->config.dpll;
4296
4297         /* SDVO TV has fixed PLL values depend on its clock range,
4298            this mirrors vbios setting. */
4299         if (dotclock >= 100000 && dotclock < 140500) {
4300                 clock->p1 = 2;
4301                 clock->p2 = 10;
4302                 clock->n = 3;
4303                 clock->m1 = 16;
4304                 clock->m2 = 8;
4305         } else if (dotclock >= 140500 && dotclock <= 200000) {
4306                 clock->p1 = 1;
4307                 clock->p2 = 10;
4308                 clock->n = 6;
4309                 clock->m1 = 12;
4310                 clock->m2 = 8;
4311         }
4312
4313         crtc->config.clock_set = true;
4314 }
4315
4316 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4317 {
4318         return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4319 }
4320
4321 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4322 {
4323         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4324 }
4325
4326 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4327                                      intel_clock_t *reduced_clock)
4328 {
4329         struct drm_device *dev = crtc->base.dev;
4330         struct drm_i915_private *dev_priv = dev->dev_private;
4331         int pipe = crtc->pipe;
4332         u32 fp, fp2 = 0;
4333
4334         if (IS_PINEVIEW(dev)) {
4335                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4336                 if (reduced_clock)
4337                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4338         } else {
4339                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4340                 if (reduced_clock)
4341                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4342         }
4343
4344         I915_WRITE(FP0(pipe), fp);
4345
4346         crtc->lowfreq_avail = false;
4347         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4348             reduced_clock && i915_powersave) {
4349                 I915_WRITE(FP1(pipe), fp2);
4350                 crtc->lowfreq_avail = true;
4351         } else {
4352                 I915_WRITE(FP1(pipe), fp);
4353         }
4354 }
4355
4356 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4357 {
4358         u32 reg_val;
4359
4360         /*
4361          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4362          * and set it to a reasonable value instead.
4363          */
4364         reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4365         reg_val &= 0xffffff00;
4366         reg_val |= 0x00000030;
4367         intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4368
4369         reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4370         reg_val &= 0x8cffffff;
4371         reg_val = 0x8c000000;
4372         intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4373
4374         reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4375         reg_val &= 0xffffff00;
4376         intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4377
4378         reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4379         reg_val &= 0x00ffffff;
4380         reg_val |= 0xb0000000;
4381         intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4382 }
4383
4384 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4385                                          struct intel_link_m_n *m_n)
4386 {
4387         struct drm_device *dev = crtc->base.dev;
4388         struct drm_i915_private *dev_priv = dev->dev_private;
4389         int pipe = crtc->pipe;
4390
4391         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4392         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4393         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4394         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4395 }
4396
4397 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4398                                          struct intel_link_m_n *m_n)
4399 {
4400         struct drm_device *dev = crtc->base.dev;
4401         struct drm_i915_private *dev_priv = dev->dev_private;
4402         int pipe = crtc->pipe;
4403         enum transcoder transcoder = crtc->config.cpu_transcoder;
4404
4405         if (INTEL_INFO(dev)->gen >= 5) {
4406                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4407                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4408                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4409                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4410         } else {
4411                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4412                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4413                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4414                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4415         }
4416 }
4417
4418 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4419 {
4420         if (crtc->config.has_pch_encoder)
4421                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4422         else
4423                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4424 }
4425
4426 static void vlv_update_pll(struct intel_crtc *crtc)
4427 {
4428         struct drm_device *dev = crtc->base.dev;
4429         struct drm_i915_private *dev_priv = dev->dev_private;
4430         struct drm_display_mode *adjusted_mode =
4431                 &crtc->config.adjusted_mode;
4432         struct intel_encoder *encoder;
4433         int pipe = crtc->pipe;
4434         u32 dpll, mdiv;
4435         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4436         bool is_hdmi;
4437         u32 coreclk, reg_val, dpll_md;
4438
4439         mutex_lock(&dev_priv->dpio_lock);
4440
4441         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4442
4443         bestn = crtc->config.dpll.n;
4444         bestm1 = crtc->config.dpll.m1;
4445         bestm2 = crtc->config.dpll.m2;
4446         bestp1 = crtc->config.dpll.p1;
4447         bestp2 = crtc->config.dpll.p2;
4448
4449         /* See eDP HDMI DPIO driver vbios notes doc */
4450
4451         /* PLL B needs special handling */
4452         if (pipe)
4453                 vlv_pllb_recal_opamp(dev_priv);
4454
4455         /* Set up Tx target for periodic Rcomp update */
4456         intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4457
4458         /* Disable target IRef on PLL */
4459         reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4460         reg_val &= 0x00ffffff;
4461         intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4462
4463         /* Disable fast lock */
4464         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4465
4466         /* Set idtafcrecal before PLL is enabled */
4467         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4468         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4469         mdiv |= ((bestn << DPIO_N_SHIFT));
4470         mdiv |= (1 << DPIO_K_SHIFT);
4471
4472         /*
4473          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4474          * but we don't support that).
4475          * Note: don't use the DAC post divider as it seems unstable.
4476          */
4477         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4478         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4479
4480         mdiv |= DPIO_ENABLE_CALIBRATION;
4481         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4482
4483         /* Set HBR and RBR LPF coefficients */
4484         if (adjusted_mode->clock == 162000 ||
4485             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4486                 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4487                                  0x005f0021);
4488         else
4489                 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4490                                  0x00d0000f);
4491
4492         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4493             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4494                 /* Use SSC source */
4495                 if (!pipe)
4496                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4497                                          0x0df40000);
4498                 else
4499                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4500                                          0x0df70000);
4501         } else { /* HDMI or VGA */
4502                 /* Use bend source */
4503                 if (!pipe)
4504                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4505                                          0x0df70000);
4506                 else
4507                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4508                                          0x0df40000);
4509         }
4510
4511         coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4512         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4513         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4514             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4515                 coreclk |= 0x01000000;
4516         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4517
4518         intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4519
4520         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4521                 if (encoder->pre_pll_enable)
4522                         encoder->pre_pll_enable(encoder);
4523
4524         /* Enable DPIO clock input */
4525         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4526                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4527         if (pipe)
4528                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4529
4530         dpll |= DPLL_VCO_ENABLE;
4531         I915_WRITE(DPLL(pipe), dpll);
4532         POSTING_READ(DPLL(pipe));
4533         udelay(150);
4534
4535         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4536                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4537
4538         dpll_md = 0;
4539         if (crtc->config.pixel_multiplier > 1) {
4540                 dpll_md = (crtc->config.pixel_multiplier - 1)
4541                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4542         }
4543         I915_WRITE(DPLL_MD(pipe), dpll_md);
4544         POSTING_READ(DPLL_MD(pipe));
4545
4546         if (crtc->config.has_dp_encoder)
4547                 intel_dp_set_m_n(crtc);
4548
4549         mutex_unlock(&dev_priv->dpio_lock);
4550 }
4551
4552 static void i9xx_update_pll(struct intel_crtc *crtc,
4553                             intel_clock_t *reduced_clock,
4554                             int num_connectors)
4555 {
4556         struct drm_device *dev = crtc->base.dev;
4557         struct drm_i915_private *dev_priv = dev->dev_private;
4558         struct intel_encoder *encoder;
4559         int pipe = crtc->pipe;
4560         u32 dpll;
4561         bool is_sdvo;
4562         struct dpll *clock = &crtc->config.dpll;
4563
4564         i9xx_update_pll_dividers(crtc, reduced_clock);
4565
4566         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4567                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4568
4569         dpll = DPLL_VGA_MODE_DIS;
4570
4571         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4572                 dpll |= DPLLB_MODE_LVDS;
4573         else
4574                 dpll |= DPLLB_MODE_DAC_SERIAL;
4575
4576         if ((crtc->config.pixel_multiplier > 1) &&
4577             (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4578                 dpll |= (crtc->config.pixel_multiplier - 1)
4579                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4580         }
4581
4582         if (is_sdvo)
4583                 dpll |= DPLL_DVO_HIGH_SPEED;
4584
4585         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4586                 dpll |= DPLL_DVO_HIGH_SPEED;
4587
4588         /* compute bitmask from p1 value */
4589         if (IS_PINEVIEW(dev))
4590                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4591         else {
4592                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4593                 if (IS_G4X(dev) && reduced_clock)
4594                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4595         }
4596         switch (clock->p2) {
4597         case 5:
4598                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4599                 break;
4600         case 7:
4601                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4602                 break;
4603         case 10:
4604                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4605                 break;
4606         case 14:
4607                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4608                 break;
4609         }
4610         if (INTEL_INFO(dev)->gen >= 4)
4611                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4612
4613         if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4614                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4615         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4616                 /* XXX: just matching BIOS for now */
4617                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4618                 dpll |= 3;
4619         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4620                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4621                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4622         else
4623                 dpll |= PLL_REF_INPUT_DREFCLK;
4624
4625         dpll |= DPLL_VCO_ENABLE;
4626         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4627         POSTING_READ(DPLL(pipe));
4628         udelay(150);
4629
4630         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4631                 if (encoder->pre_pll_enable)
4632                         encoder->pre_pll_enable(encoder);
4633
4634         if (crtc->config.has_dp_encoder)
4635                 intel_dp_set_m_n(crtc);
4636
4637         I915_WRITE(DPLL(pipe), dpll);
4638
4639         /* Wait for the clocks to stabilize. */
4640         POSTING_READ(DPLL(pipe));
4641         udelay(150);
4642
4643         if (INTEL_INFO(dev)->gen >= 4) {
4644                 u32 dpll_md = 0;
4645                 if (crtc->config.pixel_multiplier > 1) {
4646                         dpll_md = (crtc->config.pixel_multiplier - 1)
4647                                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4648                 }
4649                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4650         } else {
4651                 /* The pixel multiplier can only be updated once the
4652                  * DPLL is enabled and the clocks are stable.
4653                  *
4654                  * So write it again.
4655                  */
4656                 I915_WRITE(DPLL(pipe), dpll);
4657         }
4658 }
4659
4660 static void i8xx_update_pll(struct intel_crtc *crtc,
4661                             struct drm_display_mode *adjusted_mode,
4662                             intel_clock_t *reduced_clock,
4663                             int num_connectors)
4664 {
4665         struct drm_device *dev = crtc->base.dev;
4666         struct drm_i915_private *dev_priv = dev->dev_private;
4667         struct intel_encoder *encoder;
4668         int pipe = crtc->pipe;
4669         u32 dpll;
4670         struct dpll *clock = &crtc->config.dpll;
4671
4672         i9xx_update_pll_dividers(crtc, reduced_clock);
4673
4674         dpll = DPLL_VGA_MODE_DIS;
4675
4676         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4677                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4678         } else {
4679                 if (clock->p1 == 2)
4680                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4681                 else
4682                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4683                 if (clock->p2 == 4)
4684                         dpll |= PLL_P2_DIVIDE_BY_4;
4685         }
4686
4687         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4688                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4689                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4690         else
4691                 dpll |= PLL_REF_INPUT_DREFCLK;
4692
4693         dpll |= DPLL_VCO_ENABLE;
4694         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4695         POSTING_READ(DPLL(pipe));
4696         udelay(150);
4697
4698         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4699                 if (encoder->pre_pll_enable)
4700                         encoder->pre_pll_enable(encoder);
4701
4702         I915_WRITE(DPLL(pipe), dpll);
4703
4704         /* Wait for the clocks to stabilize. */
4705         POSTING_READ(DPLL(pipe));
4706         udelay(150);
4707
4708         /* The pixel multiplier can only be updated once the
4709          * DPLL is enabled and the clocks are stable.
4710          *
4711          * So write it again.
4712          */
4713         I915_WRITE(DPLL(pipe), dpll);
4714 }
4715
4716 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4717                                    struct drm_display_mode *mode,
4718                                    struct drm_display_mode *adjusted_mode)
4719 {
4720         struct drm_device *dev = intel_crtc->base.dev;
4721         struct drm_i915_private *dev_priv = dev->dev_private;
4722         enum pipe pipe = intel_crtc->pipe;
4723         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4724         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4725
4726         /* We need to be careful not to changed the adjusted mode, for otherwise
4727          * the hw state checker will get angry at the mismatch. */
4728         crtc_vtotal = adjusted_mode->crtc_vtotal;
4729         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4730
4731         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4732                 /* the chip adds 2 halflines automatically */
4733                 crtc_vtotal -= 1;
4734                 crtc_vblank_end -= 1;
4735                 vsyncshift = adjusted_mode->crtc_hsync_start
4736                              - adjusted_mode->crtc_htotal / 2;
4737         } else {
4738                 vsyncshift = 0;
4739         }
4740
4741         if (INTEL_INFO(dev)->gen > 3)
4742                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4743
4744         I915_WRITE(HTOTAL(cpu_transcoder),
4745                    (adjusted_mode->crtc_hdisplay - 1) |
4746                    ((adjusted_mode->crtc_htotal - 1) << 16));
4747         I915_WRITE(HBLANK(cpu_transcoder),
4748                    (adjusted_mode->crtc_hblank_start - 1) |
4749                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4750         I915_WRITE(HSYNC(cpu_transcoder),
4751                    (adjusted_mode->crtc_hsync_start - 1) |
4752                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4753
4754         I915_WRITE(VTOTAL(cpu_transcoder),
4755                    (adjusted_mode->crtc_vdisplay - 1) |
4756                    ((crtc_vtotal - 1) << 16));
4757         I915_WRITE(VBLANK(cpu_transcoder),
4758                    (adjusted_mode->crtc_vblank_start - 1) |
4759                    ((crtc_vblank_end - 1) << 16));
4760         I915_WRITE(VSYNC(cpu_transcoder),
4761                    (adjusted_mode->crtc_vsync_start - 1) |
4762                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4763
4764         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4765          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4766          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4767          * bits. */
4768         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4769             (pipe == PIPE_B || pipe == PIPE_C))
4770                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4771
4772         /* pipesrc controls the size that is scaled from, which should
4773          * always be the user's requested size.
4774          */
4775         I915_WRITE(PIPESRC(pipe),
4776                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4777 }
4778
4779 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4780                                    struct intel_crtc_config *pipe_config)
4781 {
4782         struct drm_device *dev = crtc->base.dev;
4783         struct drm_i915_private *dev_priv = dev->dev_private;
4784         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4785         uint32_t tmp;
4786
4787         tmp = I915_READ(HTOTAL(cpu_transcoder));
4788         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4789         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4790         tmp = I915_READ(HBLANK(cpu_transcoder));
4791         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4792         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4793         tmp = I915_READ(HSYNC(cpu_transcoder));
4794         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4795         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4796
4797         tmp = I915_READ(VTOTAL(cpu_transcoder));
4798         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4799         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4800         tmp = I915_READ(VBLANK(cpu_transcoder));
4801         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4802         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4803         tmp = I915_READ(VSYNC(cpu_transcoder));
4804         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4805         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4806
4807         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4808                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4809                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4810                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4811         }
4812
4813         tmp = I915_READ(PIPESRC(crtc->pipe));
4814         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4815         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4816 }
4817
4818 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4819 {
4820         struct drm_device *dev = intel_crtc->base.dev;
4821         struct drm_i915_private *dev_priv = dev->dev_private;
4822         uint32_t pipeconf;
4823
4824         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4825
4826         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4827                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4828                  * core speed.
4829                  *
4830                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4831                  * pipe == 0 check?
4832                  */
4833                 if (intel_crtc->config.requested_mode.clock >
4834                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4835                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4836                 else
4837                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4838         }
4839
4840         /* only g4x and later have fancy bpc/dither controls */
4841         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4842                 pipeconf &= ~(PIPECONF_BPC_MASK |
4843                               PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4844
4845                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4846                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4847                         pipeconf |= PIPECONF_DITHER_EN |
4848                                     PIPECONF_DITHER_TYPE_SP;
4849
4850                 switch (intel_crtc->config.pipe_bpp) {
4851                 case 18:
4852                         pipeconf |= PIPECONF_6BPC;
4853                         break;
4854                 case 24:
4855                         pipeconf |= PIPECONF_8BPC;
4856                         break;
4857                 case 30:
4858                         pipeconf |= PIPECONF_10BPC;
4859                         break;
4860                 default:
4861                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4862                         BUG();
4863                 }
4864         }
4865
4866         if (HAS_PIPE_CXSR(dev)) {
4867                 if (intel_crtc->lowfreq_avail) {
4868                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4869                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4870                 } else {
4871                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4872                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4873                 }
4874         }
4875
4876         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4877         if (!IS_GEN2(dev) &&
4878             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4879                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4880         else
4881                 pipeconf |= PIPECONF_PROGRESSIVE;
4882
4883         if (IS_VALLEYVIEW(dev)) {
4884                 if (intel_crtc->config.limited_color_range)
4885                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4886                 else
4887                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4888         }
4889
4890         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4891         POSTING_READ(PIPECONF(intel_crtc->pipe));
4892 }
4893
4894 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4895                               int x, int y,
4896                               struct drm_framebuffer *fb)
4897 {
4898         struct drm_device *dev = crtc->dev;
4899         struct drm_i915_private *dev_priv = dev->dev_private;
4900         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4901         struct drm_display_mode *adjusted_mode =
4902                 &intel_crtc->config.adjusted_mode;
4903         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4904         int pipe = intel_crtc->pipe;
4905         int plane = intel_crtc->plane;
4906         int refclk, num_connectors = 0;
4907         intel_clock_t clock, reduced_clock;
4908         u32 dspcntr;
4909         bool ok, has_reduced_clock = false, is_sdvo = false;
4910         bool is_lvds = false, is_tv = false;
4911         struct intel_encoder *encoder;
4912         const intel_limit_t *limit;
4913         int ret;
4914
4915         for_each_encoder_on_crtc(dev, crtc, encoder) {
4916                 switch (encoder->type) {
4917                 case INTEL_OUTPUT_LVDS:
4918                         is_lvds = true;
4919                         break;
4920                 case INTEL_OUTPUT_SDVO:
4921                 case INTEL_OUTPUT_HDMI:
4922                         is_sdvo = true;
4923                         if (encoder->needs_tv_clock)
4924                                 is_tv = true;
4925                         break;
4926                 case INTEL_OUTPUT_TVOUT:
4927                         is_tv = true;
4928                         break;
4929                 }
4930
4931                 num_connectors++;
4932         }
4933
4934         refclk = i9xx_get_refclk(crtc, num_connectors);
4935
4936         /*
4937          * Returns a set of divisors for the desired target clock with the given
4938          * refclk, or FALSE.  The returned values represent the clock equation:
4939          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4940          */
4941         limit = intel_limit(crtc, refclk);
4942         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4943                              &clock);
4944         if (!ok) {
4945                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4946                 return -EINVAL;
4947         }
4948
4949         /* Ensure that the cursor is valid for the new mode before changing... */
4950         intel_crtc_update_cursor(crtc, true);
4951
4952         if (is_lvds && dev_priv->lvds_downclock_avail) {
4953                 /*
4954                  * Ensure we match the reduced clock's P to the target clock.
4955                  * If the clocks don't match, we can't switch the display clock
4956                  * by using the FP0/FP1. In such case we will disable the LVDS
4957                  * downclock feature.
4958                 */
4959                 has_reduced_clock = limit->find_pll(limit, crtc,
4960                                                     dev_priv->lvds_downclock,
4961                                                     refclk,
4962                                                     &clock,
4963                                                     &reduced_clock);
4964         }
4965         /* Compat-code for transition, will disappear. */
4966         if (!intel_crtc->config.clock_set) {
4967                 intel_crtc->config.dpll.n = clock.n;
4968                 intel_crtc->config.dpll.m1 = clock.m1;
4969                 intel_crtc->config.dpll.m2 = clock.m2;
4970                 intel_crtc->config.dpll.p1 = clock.p1;
4971                 intel_crtc->config.dpll.p2 = clock.p2;
4972         }
4973
4974         if (is_sdvo && is_tv)
4975                 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4976
4977         if (IS_GEN2(dev))
4978                 i8xx_update_pll(intel_crtc, adjusted_mode,
4979                                 has_reduced_clock ? &reduced_clock : NULL,
4980                                 num_connectors);
4981         else if (IS_VALLEYVIEW(dev))
4982                 vlv_update_pll(intel_crtc);
4983         else
4984                 i9xx_update_pll(intel_crtc,
4985                                 has_reduced_clock ? &reduced_clock : NULL,
4986                                 num_connectors);
4987
4988         /* Set up the display plane register */
4989         dspcntr = DISPPLANE_GAMMA_ENABLE;
4990
4991         if (!IS_VALLEYVIEW(dev)) {
4992                 if (pipe == 0)
4993                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4994                 else
4995                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4996         }
4997
4998         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4999         drm_mode_debug_printmodeline(mode);
5000
5001         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5002
5003         /* pipesrc and dspsize control the size that is scaled from,
5004          * which should always be the user's requested size.
5005          */
5006         I915_WRITE(DSPSIZE(plane),
5007                    ((mode->vdisplay - 1) << 16) |
5008                    (mode->hdisplay - 1));
5009         I915_WRITE(DSPPOS(plane), 0);
5010
5011         i9xx_set_pipeconf(intel_crtc);
5012
5013         I915_WRITE(DSPCNTR(plane), dspcntr);
5014         POSTING_READ(DSPCNTR(plane));
5015
5016         ret = intel_pipe_set_base(crtc, x, y, fb);
5017
5018         intel_update_watermarks(dev);
5019
5020         return ret;
5021 }
5022
5023 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5024                                  struct intel_crtc_config *pipe_config)
5025 {
5026         struct drm_device *dev = crtc->base.dev;
5027         struct drm_i915_private *dev_priv = dev->dev_private;
5028         uint32_t tmp;
5029
5030         tmp = I915_READ(PIPECONF(crtc->pipe));
5031         if (!(tmp & PIPECONF_ENABLE))
5032                 return false;
5033
5034         intel_get_pipe_timings(crtc, pipe_config);
5035
5036         return true;
5037 }
5038
5039 static void ironlake_init_pch_refclk(struct drm_device *dev)
5040 {
5041         struct drm_i915_private *dev_priv = dev->dev_private;
5042         struct drm_mode_config *mode_config = &dev->mode_config;
5043         struct intel_encoder *encoder;
5044         u32 val, final;
5045         bool has_lvds = false;
5046         bool has_cpu_edp = false;
5047         bool has_pch_edp = false;
5048         bool has_panel = false;
5049         bool has_ck505 = false;
5050         bool can_ssc = false;
5051
5052         /* We need to take the global config into account */
5053         list_for_each_entry(encoder, &mode_config->encoder_list,
5054                             base.head) {
5055                 switch (encoder->type) {
5056                 case INTEL_OUTPUT_LVDS:
5057                         has_panel = true;
5058                         has_lvds = true;
5059                         break;
5060                 case INTEL_OUTPUT_EDP:
5061                         has_panel = true;
5062                         if (intel_encoder_is_pch_edp(&encoder->base))
5063                                 has_pch_edp = true;
5064                         else
5065                                 has_cpu_edp = true;
5066                         break;
5067                 }
5068         }
5069
5070         if (HAS_PCH_IBX(dev)) {
5071                 has_ck505 = dev_priv->display_clock_mode;
5072                 can_ssc = has_ck505;
5073         } else {
5074                 has_ck505 = false;
5075                 can_ssc = true;
5076         }
5077
5078         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5079                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5080                       has_ck505);
5081
5082         /* Ironlake: try to setup display ref clock before DPLL
5083          * enabling. This is only under driver's control after
5084          * PCH B stepping, previous chipset stepping should be
5085          * ignoring this setting.
5086          */
5087         val = I915_READ(PCH_DREF_CONTROL);
5088
5089         /* As we must carefully and slowly disable/enable each source in turn,
5090          * compute the final state we want first and check if we need to
5091          * make any changes at all.
5092          */
5093         final = val;
5094         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5095         if (has_ck505)
5096                 final |= DREF_NONSPREAD_CK505_ENABLE;
5097         else
5098                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5099
5100         final &= ~DREF_SSC_SOURCE_MASK;
5101         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5102         final &= ~DREF_SSC1_ENABLE;
5103
5104         if (has_panel) {
5105                 final |= DREF_SSC_SOURCE_ENABLE;
5106
5107                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5108                         final |= DREF_SSC1_ENABLE;
5109
5110                 if (has_cpu_edp) {
5111                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5112                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5113                         else
5114                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5115                 } else
5116                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5117         } else {
5118                 final |= DREF_SSC_SOURCE_DISABLE;
5119                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5120         }
5121
5122         if (final == val)
5123                 return;
5124
5125         /* Always enable nonspread source */
5126         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5127
5128         if (has_ck505)
5129                 val |= DREF_NONSPREAD_CK505_ENABLE;
5130         else
5131                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5132
5133         if (has_panel) {
5134                 val &= ~DREF_SSC_SOURCE_MASK;
5135                 val |= DREF_SSC_SOURCE_ENABLE;
5136
5137                 /* SSC must be turned on before enabling the CPU output  */
5138                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5139                         DRM_DEBUG_KMS("Using SSC on panel\n");
5140                         val |= DREF_SSC1_ENABLE;
5141                 } else
5142                         val &= ~DREF_SSC1_ENABLE;
5143
5144                 /* Get SSC going before enabling the outputs */
5145                 I915_WRITE(PCH_DREF_CONTROL, val);
5146                 POSTING_READ(PCH_DREF_CONTROL);
5147                 udelay(200);
5148
5149                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5150
5151                 /* Enable CPU source on CPU attached eDP */
5152                 if (has_cpu_edp) {
5153                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5154                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5155                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5156                         }
5157                         else
5158                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5159                 } else
5160                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5161
5162                 I915_WRITE(PCH_DREF_CONTROL, val);
5163                 POSTING_READ(PCH_DREF_CONTROL);
5164                 udelay(200);
5165         } else {
5166                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5167
5168                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5169
5170                 /* Turn off CPU output */
5171                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5172
5173                 I915_WRITE(PCH_DREF_CONTROL, val);
5174                 POSTING_READ(PCH_DREF_CONTROL);
5175                 udelay(200);
5176
5177                 /* Turn off the SSC source */
5178                 val &= ~DREF_SSC_SOURCE_MASK;
5179                 val |= DREF_SSC_SOURCE_DISABLE;
5180
5181                 /* Turn off SSC1 */
5182                 val &= ~DREF_SSC1_ENABLE;
5183
5184                 I915_WRITE(PCH_DREF_CONTROL, val);
5185                 POSTING_READ(PCH_DREF_CONTROL);
5186                 udelay(200);
5187         }
5188
5189         BUG_ON(val != final);
5190 }
5191
5192 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5193 static void lpt_init_pch_refclk(struct drm_device *dev)
5194 {
5195         struct drm_i915_private *dev_priv = dev->dev_private;
5196         struct drm_mode_config *mode_config = &dev->mode_config;
5197         struct intel_encoder *encoder;
5198         bool has_vga = false;
5199         bool is_sdv = false;
5200         u32 tmp;
5201
5202         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5203                 switch (encoder->type) {
5204                 case INTEL_OUTPUT_ANALOG:
5205                         has_vga = true;
5206                         break;
5207                 }
5208         }
5209
5210         if (!has_vga)
5211                 return;
5212
5213         mutex_lock(&dev_priv->dpio_lock);
5214
5215         /* XXX: Rip out SDV support once Haswell ships for real. */
5216         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5217                 is_sdv = true;
5218
5219         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5220         tmp &= ~SBI_SSCCTL_DISABLE;
5221         tmp |= SBI_SSCCTL_PATHALT;
5222         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5223
5224         udelay(24);
5225
5226         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5227         tmp &= ~SBI_SSCCTL_PATHALT;
5228         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5229
5230         if (!is_sdv) {
5231                 tmp = I915_READ(SOUTH_CHICKEN2);
5232                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5233                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5234
5235                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5236                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5237                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5238
5239                 tmp = I915_READ(SOUTH_CHICKEN2);
5240                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5241                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5242
5243                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5244                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5245                                        100))
5246                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5247         }
5248
5249         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5250         tmp &= ~(0xFF << 24);
5251         tmp |= (0x12 << 24);
5252         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5253
5254         if (is_sdv) {
5255                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5256                 tmp |= 0x7FFF;
5257                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5258         }
5259
5260         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5261         tmp |= (1 << 11);
5262         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5263
5264         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5265         tmp |= (1 << 11);
5266         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5267
5268         if (is_sdv) {
5269                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5270                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5271                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5272
5273                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5274                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5275                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5276
5277                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5278                 tmp |= (0x3F << 8);
5279                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5280
5281                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5282                 tmp |= (0x3F << 8);
5283                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5284         }
5285
5286         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5287         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5288         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5289
5290         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5291         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5292         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5293
5294         if (!is_sdv) {
5295                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5296                 tmp &= ~(7 << 13);
5297                 tmp |= (5 << 13);
5298                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5299
5300                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5301                 tmp &= ~(7 << 13);
5302                 tmp |= (5 << 13);
5303                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5304         }
5305
5306         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5307         tmp &= ~0xFF;
5308         tmp |= 0x1C;
5309         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5310
5311         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5312         tmp &= ~0xFF;
5313         tmp |= 0x1C;
5314         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5315
5316         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5317         tmp &= ~(0xFF << 16);
5318         tmp |= (0x1C << 16);
5319         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5320
5321         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5322         tmp &= ~(0xFF << 16);
5323         tmp |= (0x1C << 16);
5324         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5325
5326         if (!is_sdv) {
5327                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5328                 tmp |= (1 << 27);
5329                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5330
5331                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5332                 tmp |= (1 << 27);
5333                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5334
5335                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5336                 tmp &= ~(0xF << 28);
5337                 tmp |= (4 << 28);
5338                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5339
5340                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5341                 tmp &= ~(0xF << 28);
5342                 tmp |= (4 << 28);
5343                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5344         }
5345
5346         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5347         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5348         tmp |= SBI_DBUFF0_ENABLE;
5349         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5350
5351         mutex_unlock(&dev_priv->dpio_lock);
5352 }
5353
5354 /*
5355  * Initialize reference clocks when the driver loads
5356  */
5357 void intel_init_pch_refclk(struct drm_device *dev)
5358 {
5359         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5360                 ironlake_init_pch_refclk(dev);
5361         else if (HAS_PCH_LPT(dev))
5362                 lpt_init_pch_refclk(dev);
5363 }
5364
5365 static int ironlake_get_refclk(struct drm_crtc *crtc)
5366 {
5367         struct drm_device *dev = crtc->dev;
5368         struct drm_i915_private *dev_priv = dev->dev_private;
5369         struct intel_encoder *encoder;
5370         struct intel_encoder *edp_encoder = NULL;
5371         int num_connectors = 0;
5372         bool is_lvds = false;
5373
5374         for_each_encoder_on_crtc(dev, crtc, encoder) {
5375                 switch (encoder->type) {
5376                 case INTEL_OUTPUT_LVDS:
5377                         is_lvds = true;
5378                         break;
5379                 case INTEL_OUTPUT_EDP:
5380                         edp_encoder = encoder;
5381                         break;
5382                 }
5383                 num_connectors++;
5384         }
5385
5386         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5387                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5388                               dev_priv->lvds_ssc_freq);
5389                 return dev_priv->lvds_ssc_freq * 1000;
5390         }
5391
5392         return 120000;
5393 }
5394
5395 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5396 {
5397         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5399         int pipe = intel_crtc->pipe;
5400         uint32_t val;
5401
5402         val = I915_READ(PIPECONF(pipe));
5403
5404         val &= ~PIPECONF_BPC_MASK;
5405         switch (intel_crtc->config.pipe_bpp) {
5406         case 18:
5407                 val |= PIPECONF_6BPC;
5408                 break;
5409         case 24:
5410                 val |= PIPECONF_8BPC;
5411                 break;
5412         case 30:
5413                 val |= PIPECONF_10BPC;
5414                 break;
5415         case 36:
5416                 val |= PIPECONF_12BPC;
5417                 break;
5418         default:
5419                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5420                 BUG();
5421         }
5422
5423         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5424         if (intel_crtc->config.dither)
5425                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5426
5427         val &= ~PIPECONF_INTERLACE_MASK;
5428         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5429                 val |= PIPECONF_INTERLACED_ILK;
5430         else
5431                 val |= PIPECONF_PROGRESSIVE;
5432
5433         if (intel_crtc->config.limited_color_range)
5434                 val |= PIPECONF_COLOR_RANGE_SELECT;
5435         else
5436                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5437
5438         I915_WRITE(PIPECONF(pipe), val);
5439         POSTING_READ(PIPECONF(pipe));
5440 }
5441
5442 /*
5443  * Set up the pipe CSC unit.
5444  *
5445  * Currently only full range RGB to limited range RGB conversion
5446  * is supported, but eventually this should handle various
5447  * RGB<->YCbCr scenarios as well.
5448  */
5449 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5450 {
5451         struct drm_device *dev = crtc->dev;
5452         struct drm_i915_private *dev_priv = dev->dev_private;
5453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5454         int pipe = intel_crtc->pipe;
5455         uint16_t coeff = 0x7800; /* 1.0 */
5456
5457         /*
5458          * TODO: Check what kind of values actually come out of the pipe
5459          * with these coeff/postoff values and adjust to get the best
5460          * accuracy. Perhaps we even need to take the bpc value into
5461          * consideration.
5462          */
5463
5464         if (intel_crtc->config.limited_color_range)
5465                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5466
5467         /*
5468          * GY/GU and RY/RU should be the other way around according
5469          * to BSpec, but reality doesn't agree. Just set them up in
5470          * a way that results in the correct picture.
5471          */
5472         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5473         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5474
5475         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5476         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5477
5478         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5479         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5480
5481         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5482         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5483         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5484
5485         if (INTEL_INFO(dev)->gen > 6) {
5486                 uint16_t postoff = 0;
5487
5488                 if (intel_crtc->config.limited_color_range)
5489                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5490
5491                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5492                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5493                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5494
5495                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5496         } else {
5497                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5498
5499                 if (intel_crtc->config.limited_color_range)
5500                         mode |= CSC_BLACK_SCREEN_OFFSET;
5501
5502                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5503         }
5504 }
5505
5506 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5507 {
5508         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5510         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5511         uint32_t val;
5512
5513         val = I915_READ(PIPECONF(cpu_transcoder));
5514
5515         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5516         if (intel_crtc->config.dither)
5517                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5518
5519         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5520         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5521                 val |= PIPECONF_INTERLACED_ILK;
5522         else
5523                 val |= PIPECONF_PROGRESSIVE;
5524
5525         I915_WRITE(PIPECONF(cpu_transcoder), val);
5526         POSTING_READ(PIPECONF(cpu_transcoder));
5527 }
5528
5529 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5530                                     struct drm_display_mode *adjusted_mode,
5531                                     intel_clock_t *clock,
5532                                     bool *has_reduced_clock,
5533                                     intel_clock_t *reduced_clock)
5534 {
5535         struct drm_device *dev = crtc->dev;
5536         struct drm_i915_private *dev_priv = dev->dev_private;
5537         struct intel_encoder *intel_encoder;
5538         int refclk;
5539         const intel_limit_t *limit;
5540         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5541
5542         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5543                 switch (intel_encoder->type) {
5544                 case INTEL_OUTPUT_LVDS:
5545                         is_lvds = true;
5546                         break;
5547                 case INTEL_OUTPUT_SDVO:
5548                 case INTEL_OUTPUT_HDMI:
5549                         is_sdvo = true;
5550                         if (intel_encoder->needs_tv_clock)
5551                                 is_tv = true;
5552                         break;
5553                 case INTEL_OUTPUT_TVOUT:
5554                         is_tv = true;
5555                         break;
5556                 }
5557         }
5558
5559         refclk = ironlake_get_refclk(crtc);
5560
5561         /*
5562          * Returns a set of divisors for the desired target clock with the given
5563          * refclk, or FALSE.  The returned values represent the clock equation:
5564          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5565          */
5566         limit = intel_limit(crtc, refclk);
5567         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5568                               clock);
5569         if (!ret)
5570                 return false;
5571
5572         if (is_lvds && dev_priv->lvds_downclock_avail) {
5573                 /*
5574                  * Ensure we match the reduced clock's P to the target clock.
5575                  * If the clocks don't match, we can't switch the display clock
5576                  * by using the FP0/FP1. In such case we will disable the LVDS
5577                  * downclock feature.
5578                 */
5579                 *has_reduced_clock = limit->find_pll(limit, crtc,
5580                                                      dev_priv->lvds_downclock,
5581                                                      refclk,
5582                                                      clock,
5583                                                      reduced_clock);
5584         }
5585
5586         if (is_sdvo && is_tv)
5587                 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5588
5589         return true;
5590 }
5591
5592 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5593 {
5594         struct drm_i915_private *dev_priv = dev->dev_private;
5595         uint32_t temp;
5596
5597         temp = I915_READ(SOUTH_CHICKEN1);
5598         if (temp & FDI_BC_BIFURCATION_SELECT)
5599                 return;
5600
5601         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5602         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5603
5604         temp |= FDI_BC_BIFURCATION_SELECT;
5605         DRM_DEBUG_KMS("enabling fdi C rx\n");
5606         I915_WRITE(SOUTH_CHICKEN1, temp);
5607         POSTING_READ(SOUTH_CHICKEN1);
5608 }
5609
5610 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5611 {
5612         struct drm_device *dev = intel_crtc->base.dev;
5613         struct drm_i915_private *dev_priv = dev->dev_private;
5614
5615         switch (intel_crtc->pipe) {
5616         case PIPE_A:
5617                 break;
5618         case PIPE_B:
5619                 if (intel_crtc->config.fdi_lanes > 2)
5620                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5621                 else
5622                         cpt_enable_fdi_bc_bifurcation(dev);
5623
5624                 break;
5625         case PIPE_C:
5626                 cpt_enable_fdi_bc_bifurcation(dev);
5627
5628                 break;
5629         default:
5630                 BUG();
5631         }
5632 }
5633
5634 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5635 {
5636         /*
5637          * Account for spread spectrum to avoid
5638          * oversubscribing the link. Max center spread
5639          * is 2.5%; use 5% for safety's sake.
5640          */
5641         u32 bps = target_clock * bpp * 21 / 20;
5642         return bps / (link_bw * 8) + 1;
5643 }
5644
5645 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5646 {
5647         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5648 }
5649
5650 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5651                                       u32 *fp,
5652                                       intel_clock_t *reduced_clock, u32 *fp2)
5653 {
5654         struct drm_crtc *crtc = &intel_crtc->base;
5655         struct drm_device *dev = crtc->dev;
5656         struct drm_i915_private *dev_priv = dev->dev_private;
5657         struct intel_encoder *intel_encoder;
5658         uint32_t dpll;
5659         int factor, num_connectors = 0;
5660         bool is_lvds = false, is_sdvo = false, is_tv = false;
5661
5662         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5663                 switch (intel_encoder->type) {
5664                 case INTEL_OUTPUT_LVDS:
5665                         is_lvds = true;
5666                         break;
5667                 case INTEL_OUTPUT_SDVO:
5668                 case INTEL_OUTPUT_HDMI:
5669                         is_sdvo = true;
5670                         if (intel_encoder->needs_tv_clock)
5671                                 is_tv = true;
5672                         break;
5673                 case INTEL_OUTPUT_TVOUT:
5674                         is_tv = true;
5675                         break;
5676                 }
5677
5678                 num_connectors++;
5679         }
5680
5681         /* Enable autotuning of the PLL clock (if permissible) */
5682         factor = 21;
5683         if (is_lvds) {
5684                 if ((intel_panel_use_ssc(dev_priv) &&
5685                      dev_priv->lvds_ssc_freq == 100) ||
5686                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5687                         factor = 25;
5688         } else if (is_sdvo && is_tv)
5689                 factor = 20;
5690
5691         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5692                 *fp |= FP_CB_TUNE;
5693
5694         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5695                 *fp2 |= FP_CB_TUNE;
5696
5697         dpll = 0;
5698
5699         if (is_lvds)
5700                 dpll |= DPLLB_MODE_LVDS;
5701         else
5702                 dpll |= DPLLB_MODE_DAC_SERIAL;
5703
5704         if (intel_crtc->config.pixel_multiplier > 1) {
5705                 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5706                         << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5707         }
5708
5709         if (is_sdvo)
5710                 dpll |= DPLL_DVO_HIGH_SPEED;
5711         if (intel_crtc->config.has_dp_encoder)
5712                 dpll |= DPLL_DVO_HIGH_SPEED;
5713
5714         /* compute bitmask from p1 value */
5715         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5716         /* also FPA1 */
5717         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5718
5719         switch (intel_crtc->config.dpll.p2) {
5720         case 5:
5721                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5722                 break;
5723         case 7:
5724                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5725                 break;
5726         case 10:
5727                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5728                 break;
5729         case 14:
5730                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5731                 break;
5732         }
5733
5734         if (is_sdvo && is_tv)
5735                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5736         else if (is_tv)
5737                 /* XXX: just matching BIOS for now */
5738                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5739                 dpll |= 3;
5740         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5741                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5742         else
5743                 dpll |= PLL_REF_INPUT_DREFCLK;
5744
5745         return dpll;
5746 }
5747
5748 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5749                                   int x, int y,
5750                                   struct drm_framebuffer *fb)
5751 {
5752         struct drm_device *dev = crtc->dev;
5753         struct drm_i915_private *dev_priv = dev->dev_private;
5754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5755         struct drm_display_mode *adjusted_mode =
5756                 &intel_crtc->config.adjusted_mode;
5757         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5758         int pipe = intel_crtc->pipe;
5759         int plane = intel_crtc->plane;
5760         int num_connectors = 0;
5761         intel_clock_t clock, reduced_clock;
5762         u32 dpll = 0, fp = 0, fp2 = 0;
5763         bool ok, has_reduced_clock = false;
5764         bool is_lvds = false;
5765         struct intel_encoder *encoder;
5766         int ret;
5767
5768         for_each_encoder_on_crtc(dev, crtc, encoder) {
5769                 switch (encoder->type) {
5770                 case INTEL_OUTPUT_LVDS:
5771                         is_lvds = true;
5772                         break;
5773                 }
5774
5775                 num_connectors++;
5776         }
5777
5778         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5779              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5780
5781         intel_crtc->config.cpu_transcoder = pipe;
5782
5783         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5784                                      &has_reduced_clock, &reduced_clock);
5785         if (!ok) {
5786                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5787                 return -EINVAL;
5788         }
5789         /* Compat-code for transition, will disappear. */
5790         if (!intel_crtc->config.clock_set) {
5791                 intel_crtc->config.dpll.n = clock.n;
5792                 intel_crtc->config.dpll.m1 = clock.m1;
5793                 intel_crtc->config.dpll.m2 = clock.m2;
5794                 intel_crtc->config.dpll.p1 = clock.p1;
5795                 intel_crtc->config.dpll.p2 = clock.p2;
5796         }
5797
5798         /* Ensure that the cursor is valid for the new mode before changing... */
5799         intel_crtc_update_cursor(crtc, true);
5800
5801         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5802         drm_mode_debug_printmodeline(mode);
5803
5804         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5805         if (intel_crtc->config.has_pch_encoder) {
5806                 struct intel_pch_pll *pll;
5807
5808                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5809                 if (has_reduced_clock)
5810                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5811
5812                 dpll = ironlake_compute_dpll(intel_crtc,
5813                                              &fp, &reduced_clock,
5814                                              has_reduced_clock ? &fp2 : NULL);
5815
5816                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5817                 if (pll == NULL) {
5818                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5819                                          pipe_name(pipe));
5820                         return -EINVAL;
5821                 }
5822         } else
5823                 intel_put_pch_pll(intel_crtc);
5824
5825         if (intel_crtc->config.has_dp_encoder)
5826                 intel_dp_set_m_n(intel_crtc);
5827
5828         for_each_encoder_on_crtc(dev, crtc, encoder)
5829                 if (encoder->pre_pll_enable)
5830                         encoder->pre_pll_enable(encoder);
5831
5832         if (intel_crtc->pch_pll) {
5833                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5834
5835                 /* Wait for the clocks to stabilize. */
5836                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5837                 udelay(150);
5838
5839                 /* The pixel multiplier can only be updated once the
5840                  * DPLL is enabled and the clocks are stable.
5841                  *
5842                  * So write it again.
5843                  */
5844                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5845         }
5846
5847         intel_crtc->lowfreq_avail = false;
5848         if (intel_crtc->pch_pll) {
5849                 if (is_lvds && has_reduced_clock && i915_powersave) {
5850                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5851                         intel_crtc->lowfreq_avail = true;
5852                 } else {
5853                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5854                 }
5855         }
5856
5857         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5858
5859         if (intel_crtc->config.has_pch_encoder) {
5860                 intel_cpu_transcoder_set_m_n(intel_crtc,
5861                                              &intel_crtc->config.fdi_m_n);
5862         }
5863
5864         if (IS_IVYBRIDGE(dev))
5865                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5866
5867         ironlake_set_pipeconf(crtc);
5868
5869         /* Set up the display plane register */
5870         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5871         POSTING_READ(DSPCNTR(plane));
5872
5873         ret = intel_pipe_set_base(crtc, x, y, fb);
5874
5875         intel_update_watermarks(dev);
5876
5877         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5878
5879         return ret;
5880 }
5881
5882 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5883                                         struct intel_crtc_config *pipe_config)
5884 {
5885         struct drm_device *dev = crtc->base.dev;
5886         struct drm_i915_private *dev_priv = dev->dev_private;
5887         enum transcoder transcoder = pipe_config->cpu_transcoder;
5888
5889         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5890         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5891         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5892                                         & ~TU_SIZE_MASK;
5893         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5894         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5895                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5896 }
5897
5898 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5899                                      struct intel_crtc_config *pipe_config)
5900 {
5901         struct drm_device *dev = crtc->base.dev;
5902         struct drm_i915_private *dev_priv = dev->dev_private;
5903         uint32_t tmp;
5904
5905         tmp = I915_READ(PIPECONF(crtc->pipe));
5906         if (!(tmp & PIPECONF_ENABLE))
5907                 return false;
5908
5909         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5910                 pipe_config->has_pch_encoder = true;
5911
5912                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5913                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5914                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5915
5916                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5917         }
5918
5919         intel_get_pipe_timings(crtc, pipe_config);
5920
5921         return true;
5922 }
5923
5924 static void haswell_modeset_global_resources(struct drm_device *dev)
5925 {
5926         bool enable = false;
5927         struct intel_crtc *crtc;
5928         struct intel_encoder *encoder;
5929
5930         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5931                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5932                         enable = true;
5933                 /* XXX: Should check for edp transcoder here, but thanks to init
5934                  * sequence that's not yet available. Just in case desktop eDP
5935                  * on PORT D is possible on haswell, too. */
5936                 /* Even the eDP panel fitter is outside the always-on well. */
5937                 if (crtc->config.pch_pfit.size && crtc->base.enabled)
5938                         enable = true;
5939         }
5940
5941         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5942                             base.head) {
5943                 if (encoder->type != INTEL_OUTPUT_EDP &&
5944                     encoder->connectors_active)
5945                         enable = true;
5946         }
5947
5948         intel_set_power_well(dev, enable);
5949 }
5950
5951 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5952                                  int x, int y,
5953                                  struct drm_framebuffer *fb)
5954 {
5955         struct drm_device *dev = crtc->dev;
5956         struct drm_i915_private *dev_priv = dev->dev_private;
5957         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5958         struct drm_display_mode *adjusted_mode =
5959                 &intel_crtc->config.adjusted_mode;
5960         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5961         int pipe = intel_crtc->pipe;
5962         int plane = intel_crtc->plane;
5963         int num_connectors = 0;
5964         bool is_cpu_edp = false;
5965         struct intel_encoder *encoder;
5966         int ret;
5967
5968         for_each_encoder_on_crtc(dev, crtc, encoder) {
5969                 switch (encoder->type) {
5970                 case INTEL_OUTPUT_EDP:
5971                         if (!intel_encoder_is_pch_edp(&encoder->base))
5972                                 is_cpu_edp = true;
5973                         break;
5974                 }
5975
5976                 num_connectors++;
5977         }
5978
5979         if (is_cpu_edp)
5980                 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5981         else
5982                 intel_crtc->config.cpu_transcoder = pipe;
5983
5984         /* We are not sure yet this won't happen. */
5985         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5986              INTEL_PCH_TYPE(dev));
5987
5988         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5989              num_connectors, pipe_name(pipe));
5990
5991         WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5992                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5993
5994         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5995
5996         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5997                 return -EINVAL;
5998
5999         /* Ensure that the cursor is valid for the new mode before changing... */
6000         intel_crtc_update_cursor(crtc, true);
6001
6002         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
6003         drm_mode_debug_printmodeline(mode);
6004
6005         if (intel_crtc->config.has_dp_encoder)
6006                 intel_dp_set_m_n(intel_crtc);
6007
6008         intel_crtc->lowfreq_avail = false;
6009
6010         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
6011
6012         if (intel_crtc->config.has_pch_encoder) {
6013                 intel_cpu_transcoder_set_m_n(intel_crtc,
6014                                              &intel_crtc->config.fdi_m_n);
6015         }
6016
6017         haswell_set_pipeconf(crtc);
6018
6019         intel_set_pipe_csc(crtc);
6020
6021         /* Set up the display plane register */
6022         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6023         POSTING_READ(DSPCNTR(plane));
6024
6025         ret = intel_pipe_set_base(crtc, x, y, fb);
6026
6027         intel_update_watermarks(dev);
6028
6029         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
6030
6031         return ret;
6032 }
6033
6034 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6035                                     struct intel_crtc_config *pipe_config)
6036 {
6037         struct drm_device *dev = crtc->base.dev;
6038         struct drm_i915_private *dev_priv = dev->dev_private;
6039         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
6040         uint32_t tmp;
6041
6042         if (!intel_using_power_well(dev_priv->dev) &&
6043             cpu_transcoder != TRANSCODER_EDP)
6044                 return false;
6045
6046         tmp = I915_READ(PIPECONF(cpu_transcoder));
6047         if (!(tmp & PIPECONF_ENABLE))
6048                 return false;
6049
6050         /*
6051          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6052          * DDI E. So just check whether this pipe is wired to DDI E and whether
6053          * the PCH transcoder is on.
6054          */
6055         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
6056         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6057             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6058                 pipe_config->has_pch_encoder = true;
6059
6060                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6061                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6062                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6063
6064                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6065         }
6066
6067         intel_get_pipe_timings(crtc, pipe_config);
6068
6069         return true;
6070 }
6071
6072 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6073                                int x, int y,
6074                                struct drm_framebuffer *fb)
6075 {
6076         struct drm_device *dev = crtc->dev;
6077         struct drm_i915_private *dev_priv = dev->dev_private;
6078         struct drm_encoder_helper_funcs *encoder_funcs;
6079         struct intel_encoder *encoder;
6080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6081         struct drm_display_mode *adjusted_mode =
6082                 &intel_crtc->config.adjusted_mode;
6083         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6084         int pipe = intel_crtc->pipe;
6085         int ret;
6086
6087         drm_vblank_pre_modeset(dev, pipe);
6088
6089         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6090
6091         drm_vblank_post_modeset(dev, pipe);
6092
6093         if (ret != 0)
6094                 return ret;
6095
6096         for_each_encoder_on_crtc(dev, crtc, encoder) {
6097                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6098                         encoder->base.base.id,
6099                         drm_get_encoder_name(&encoder->base),
6100                         mode->base.id, mode->name);
6101                 if (encoder->mode_set) {
6102                         encoder->mode_set(encoder);
6103                 } else {
6104                         encoder_funcs = encoder->base.helper_private;
6105                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6106                 }
6107         }
6108
6109         return 0;
6110 }
6111
6112 static bool intel_eld_uptodate(struct drm_connector *connector,
6113                                int reg_eldv, uint32_t bits_eldv,
6114                                int reg_elda, uint32_t bits_elda,
6115                                int reg_edid)
6116 {
6117         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6118         uint8_t *eld = connector->eld;
6119         uint32_t i;
6120
6121         i = I915_READ(reg_eldv);
6122         i &= bits_eldv;
6123
6124         if (!eld[0])
6125                 return !i;
6126
6127         if (!i)
6128                 return false;
6129
6130         i = I915_READ(reg_elda);
6131         i &= ~bits_elda;
6132         I915_WRITE(reg_elda, i);
6133
6134         for (i = 0; i < eld[2]; i++)
6135                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6136                         return false;
6137
6138         return true;
6139 }
6140
6141 static void g4x_write_eld(struct drm_connector *connector,
6142                           struct drm_crtc *crtc)
6143 {
6144         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6145         uint8_t *eld = connector->eld;
6146         uint32_t eldv;
6147         uint32_t len;
6148         uint32_t i;
6149
6150         i = I915_READ(G4X_AUD_VID_DID);
6151
6152         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6153                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6154         else
6155                 eldv = G4X_ELDV_DEVCTG;
6156
6157         if (intel_eld_uptodate(connector,
6158                                G4X_AUD_CNTL_ST, eldv,
6159                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6160                                G4X_HDMIW_HDMIEDID))
6161                 return;
6162
6163         i = I915_READ(G4X_AUD_CNTL_ST);
6164         i &= ~(eldv | G4X_ELD_ADDR);
6165         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6166         I915_WRITE(G4X_AUD_CNTL_ST, i);
6167
6168         if (!eld[0])
6169                 return;
6170
6171         len = min_t(uint8_t, eld[2], len);
6172         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6173         for (i = 0; i < len; i++)
6174                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6175
6176         i = I915_READ(G4X_AUD_CNTL_ST);
6177         i |= eldv;
6178         I915_WRITE(G4X_AUD_CNTL_ST, i);
6179 }
6180
6181 static void haswell_write_eld(struct drm_connector *connector,
6182                                      struct drm_crtc *crtc)
6183 {
6184         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6185         uint8_t *eld = connector->eld;
6186         struct drm_device *dev = crtc->dev;
6187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6188         uint32_t eldv;
6189         uint32_t i;
6190         int len;
6191         int pipe = to_intel_crtc(crtc)->pipe;
6192         int tmp;
6193
6194         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6195         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6196         int aud_config = HSW_AUD_CFG(pipe);
6197         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6198
6199
6200         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6201
6202         /* Audio output enable */
6203         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6204         tmp = I915_READ(aud_cntrl_st2);
6205         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6206         I915_WRITE(aud_cntrl_st2, tmp);
6207
6208         /* Wait for 1 vertical blank */
6209         intel_wait_for_vblank(dev, pipe);
6210
6211         /* Set ELD valid state */
6212         tmp = I915_READ(aud_cntrl_st2);
6213         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6214         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6215         I915_WRITE(aud_cntrl_st2, tmp);
6216         tmp = I915_READ(aud_cntrl_st2);
6217         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6218
6219         /* Enable HDMI mode */
6220         tmp = I915_READ(aud_config);
6221         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6222         /* clear N_programing_enable and N_value_index */
6223         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6224         I915_WRITE(aud_config, tmp);
6225
6226         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6227
6228         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6229         intel_crtc->eld_vld = true;
6230
6231         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6232                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6233                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6234                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6235         } else
6236                 I915_WRITE(aud_config, 0);
6237
6238         if (intel_eld_uptodate(connector,
6239                                aud_cntrl_st2, eldv,
6240                                aud_cntl_st, IBX_ELD_ADDRESS,
6241                                hdmiw_hdmiedid))
6242                 return;
6243
6244         i = I915_READ(aud_cntrl_st2);
6245         i &= ~eldv;
6246         I915_WRITE(aud_cntrl_st2, i);
6247
6248         if (!eld[0])
6249                 return;
6250
6251         i = I915_READ(aud_cntl_st);
6252         i &= ~IBX_ELD_ADDRESS;
6253         I915_WRITE(aud_cntl_st, i);
6254         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6255         DRM_DEBUG_DRIVER("port num:%d\n", i);
6256
6257         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6258         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6259         for (i = 0; i < len; i++)
6260                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6261
6262         i = I915_READ(aud_cntrl_st2);
6263         i |= eldv;
6264         I915_WRITE(aud_cntrl_st2, i);
6265
6266 }
6267
6268 static void ironlake_write_eld(struct drm_connector *connector,
6269                                      struct drm_crtc *crtc)
6270 {
6271         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6272         uint8_t *eld = connector->eld;
6273         uint32_t eldv;
6274         uint32_t i;
6275         int len;
6276         int hdmiw_hdmiedid;
6277         int aud_config;
6278         int aud_cntl_st;
6279         int aud_cntrl_st2;
6280         int pipe = to_intel_crtc(crtc)->pipe;
6281
6282         if (HAS_PCH_IBX(connector->dev)) {
6283                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6284                 aud_config = IBX_AUD_CFG(pipe);
6285                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6286                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6287         } else {
6288                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6289                 aud_config = CPT_AUD_CFG(pipe);
6290                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6291                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6292         }
6293
6294         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6295
6296         i = I915_READ(aud_cntl_st);
6297         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6298         if (!i) {
6299                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6300                 /* operate blindly on all ports */
6301                 eldv = IBX_ELD_VALIDB;
6302                 eldv |= IBX_ELD_VALIDB << 4;
6303                 eldv |= IBX_ELD_VALIDB << 8;
6304         } else {
6305                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6306                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6307         }
6308
6309         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6310                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6311                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6312                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6313         } else
6314                 I915_WRITE(aud_config, 0);
6315
6316         if (intel_eld_uptodate(connector,
6317                                aud_cntrl_st2, eldv,
6318                                aud_cntl_st, IBX_ELD_ADDRESS,
6319                                hdmiw_hdmiedid))
6320                 return;
6321
6322         i = I915_READ(aud_cntrl_st2);
6323         i &= ~eldv;
6324         I915_WRITE(aud_cntrl_st2, i);
6325
6326         if (!eld[0])
6327                 return;
6328
6329         i = I915_READ(aud_cntl_st);
6330         i &= ~IBX_ELD_ADDRESS;
6331         I915_WRITE(aud_cntl_st, i);
6332
6333         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6334         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6335         for (i = 0; i < len; i++)
6336                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6337
6338         i = I915_READ(aud_cntrl_st2);
6339         i |= eldv;
6340         I915_WRITE(aud_cntrl_st2, i);
6341 }
6342
6343 void intel_write_eld(struct drm_encoder *encoder,
6344                      struct drm_display_mode *mode)
6345 {
6346         struct drm_crtc *crtc = encoder->crtc;
6347         struct drm_connector *connector;
6348         struct drm_device *dev = encoder->dev;
6349         struct drm_i915_private *dev_priv = dev->dev_private;
6350
6351         connector = drm_select_eld(encoder, mode);
6352         if (!connector)
6353                 return;
6354
6355         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6356                          connector->base.id,
6357                          drm_get_connector_name(connector),
6358                          connector->encoder->base.id,
6359                          drm_get_encoder_name(connector->encoder));
6360
6361         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6362
6363         if (dev_priv->display.write_eld)
6364                 dev_priv->display.write_eld(connector, crtc);
6365 }
6366
6367 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6368 void intel_crtc_load_lut(struct drm_crtc *crtc)
6369 {
6370         struct drm_device *dev = crtc->dev;
6371         struct drm_i915_private *dev_priv = dev->dev_private;
6372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6373         int palreg = PALETTE(intel_crtc->pipe);
6374         int i;
6375
6376         /* The clocks have to be on to load the palette. */
6377         if (!crtc->enabled || !intel_crtc->active)
6378                 return;
6379
6380         /* use legacy palette for Ironlake */
6381         if (HAS_PCH_SPLIT(dev))
6382                 palreg = LGC_PALETTE(intel_crtc->pipe);
6383
6384         for (i = 0; i < 256; i++) {
6385                 I915_WRITE(palreg + 4 * i,
6386                            (intel_crtc->lut_r[i] << 16) |
6387                            (intel_crtc->lut_g[i] << 8) |
6388                            intel_crtc->lut_b[i]);
6389         }
6390 }
6391
6392 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6393 {
6394         struct drm_device *dev = crtc->dev;
6395         struct drm_i915_private *dev_priv = dev->dev_private;
6396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6397         bool visible = base != 0;
6398         u32 cntl;
6399
6400         if (intel_crtc->cursor_visible == visible)
6401                 return;
6402
6403         cntl = I915_READ(_CURACNTR);
6404         if (visible) {
6405                 /* On these chipsets we can only modify the base whilst
6406                  * the cursor is disabled.
6407                  */
6408                 I915_WRITE(_CURABASE, base);
6409
6410                 cntl &= ~(CURSOR_FORMAT_MASK);
6411                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6412                 cntl |= CURSOR_ENABLE |
6413                         CURSOR_GAMMA_ENABLE |
6414                         CURSOR_FORMAT_ARGB;
6415         } else
6416                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6417         I915_WRITE(_CURACNTR, cntl);
6418
6419         intel_crtc->cursor_visible = visible;
6420 }
6421
6422 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6423 {
6424         struct drm_device *dev = crtc->dev;
6425         struct drm_i915_private *dev_priv = dev->dev_private;
6426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6427         int pipe = intel_crtc->pipe;
6428         bool visible = base != 0;
6429
6430         if (intel_crtc->cursor_visible != visible) {
6431                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6432                 if (base) {
6433                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6434                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6435                         cntl |= pipe << 28; /* Connect to correct pipe */
6436                 } else {
6437                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6438                         cntl |= CURSOR_MODE_DISABLE;
6439                 }
6440                 I915_WRITE(CURCNTR(pipe), cntl);
6441
6442                 intel_crtc->cursor_visible = visible;
6443         }
6444         /* and commit changes on next vblank */
6445         I915_WRITE(CURBASE(pipe), base);
6446 }
6447
6448 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6449 {
6450         struct drm_device *dev = crtc->dev;
6451         struct drm_i915_private *dev_priv = dev->dev_private;
6452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6453         int pipe = intel_crtc->pipe;
6454         bool visible = base != 0;
6455
6456         if (intel_crtc->cursor_visible != visible) {
6457                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6458                 if (base) {
6459                         cntl &= ~CURSOR_MODE;
6460                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6461                 } else {
6462                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6463                         cntl |= CURSOR_MODE_DISABLE;
6464                 }
6465                 if (IS_HASWELL(dev))
6466                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6467                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6468
6469                 intel_crtc->cursor_visible = visible;
6470         }
6471         /* and commit changes on next vblank */
6472         I915_WRITE(CURBASE_IVB(pipe), base);
6473 }
6474
6475 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6476 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6477                                      bool on)
6478 {
6479         struct drm_device *dev = crtc->dev;
6480         struct drm_i915_private *dev_priv = dev->dev_private;
6481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6482         int pipe = intel_crtc->pipe;
6483         int x = intel_crtc->cursor_x;
6484         int y = intel_crtc->cursor_y;
6485         u32 base, pos;
6486         bool visible;
6487
6488         pos = 0;
6489
6490         if (on && crtc->enabled && crtc->fb) {
6491                 base = intel_crtc->cursor_addr;
6492                 if (x > (int) crtc->fb->width)
6493                         base = 0;
6494
6495                 if (y > (int) crtc->fb->height)
6496                         base = 0;
6497         } else
6498                 base = 0;
6499
6500         if (x < 0) {
6501                 if (x + intel_crtc->cursor_width < 0)
6502                         base = 0;
6503
6504                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6505                 x = -x;
6506         }
6507         pos |= x << CURSOR_X_SHIFT;
6508
6509         if (y < 0) {
6510                 if (y + intel_crtc->cursor_height < 0)
6511                         base = 0;
6512
6513                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6514                 y = -y;
6515         }
6516         pos |= y << CURSOR_Y_SHIFT;
6517
6518         visible = base != 0;
6519         if (!visible && !intel_crtc->cursor_visible)
6520                 return;
6521
6522         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6523                 I915_WRITE(CURPOS_IVB(pipe), pos);
6524                 ivb_update_cursor(crtc, base);
6525         } else {
6526                 I915_WRITE(CURPOS(pipe), pos);
6527                 if (IS_845G(dev) || IS_I865G(dev))
6528                         i845_update_cursor(crtc, base);
6529                 else
6530                         i9xx_update_cursor(crtc, base);
6531         }
6532 }
6533
6534 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6535                                  struct drm_file *file,
6536                                  uint32_t handle,
6537                                  uint32_t width, uint32_t height)
6538 {
6539         struct drm_device *dev = crtc->dev;
6540         struct drm_i915_private *dev_priv = dev->dev_private;
6541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6542         struct drm_i915_gem_object *obj;
6543         uint32_t addr;
6544         int ret;
6545
6546         /* if we want to turn off the cursor ignore width and height */
6547         if (!handle) {
6548                 DRM_DEBUG_KMS("cursor off\n");
6549                 addr = 0;
6550                 obj = NULL;
6551                 mutex_lock(&dev->struct_mutex);
6552                 goto finish;
6553         }
6554
6555         /* Currently we only support 64x64 cursors */
6556         if (width != 64 || height != 64) {
6557                 DRM_ERROR("we currently only support 64x64 cursors\n");
6558                 return -EINVAL;
6559         }
6560
6561         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6562         if (&obj->base == NULL)
6563                 return -ENOENT;
6564
6565         if (obj->base.size < width * height * 4) {
6566                 DRM_ERROR("buffer is to small\n");
6567                 ret = -ENOMEM;
6568                 goto fail;
6569         }
6570
6571         /* we only need to pin inside GTT if cursor is non-phy */
6572         mutex_lock(&dev->struct_mutex);
6573         if (!dev_priv->info->cursor_needs_physical) {
6574                 unsigned alignment;
6575
6576                 if (obj->tiling_mode) {
6577                         DRM_ERROR("cursor cannot be tiled\n");
6578                         ret = -EINVAL;
6579                         goto fail_locked;
6580                 }
6581
6582                 /* Note that the w/a also requires 2 PTE of padding following
6583                  * the bo. We currently fill all unused PTE with the shadow
6584                  * page and so we should always have valid PTE following the
6585                  * cursor preventing the VT-d warning.
6586                  */
6587                 alignment = 0;
6588                 if (need_vtd_wa(dev))
6589                         alignment = 64*1024;
6590
6591                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6592                 if (ret) {
6593                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6594                         goto fail_locked;
6595                 }
6596
6597                 ret = i915_gem_object_put_fence(obj);
6598                 if (ret) {
6599                         DRM_ERROR("failed to release fence for cursor");
6600                         goto fail_unpin;
6601                 }
6602
6603                 addr = obj->gtt_offset;
6604         } else {
6605                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6606                 ret = i915_gem_attach_phys_object(dev, obj,
6607                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6608                                                   align);
6609                 if (ret) {
6610                         DRM_ERROR("failed to attach phys object\n");
6611                         goto fail_locked;
6612                 }
6613                 addr = obj->phys_obj->handle->busaddr;
6614         }
6615
6616         if (IS_GEN2(dev))
6617                 I915_WRITE(CURSIZE, (height << 12) | width);
6618
6619  finish:
6620         if (intel_crtc->cursor_bo) {
6621                 if (dev_priv->info->cursor_needs_physical) {
6622                         if (intel_crtc->cursor_bo != obj)
6623                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6624                 } else
6625                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6626                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6627         }
6628
6629         mutex_unlock(&dev->struct_mutex);
6630
6631         intel_crtc->cursor_addr = addr;
6632         intel_crtc->cursor_bo = obj;
6633         intel_crtc->cursor_width = width;
6634         intel_crtc->cursor_height = height;
6635
6636         intel_crtc_update_cursor(crtc, true);
6637
6638         return 0;
6639 fail_unpin:
6640         i915_gem_object_unpin(obj);
6641 fail_locked:
6642         mutex_unlock(&dev->struct_mutex);
6643 fail:
6644         drm_gem_object_unreference_unlocked(&obj->base);
6645         return ret;
6646 }
6647
6648 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6649 {
6650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6651
6652         intel_crtc->cursor_x = x;
6653         intel_crtc->cursor_y = y;
6654
6655         intel_crtc_update_cursor(crtc, true);
6656
6657         return 0;
6658 }
6659
6660 /** Sets the color ramps on behalf of RandR */
6661 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6662                                  u16 blue, int regno)
6663 {
6664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6665
6666         intel_crtc->lut_r[regno] = red >> 8;
6667         intel_crtc->lut_g[regno] = green >> 8;
6668         intel_crtc->lut_b[regno] = blue >> 8;
6669 }
6670
6671 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6672                              u16 *blue, int regno)
6673 {
6674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6675
6676         *red = intel_crtc->lut_r[regno] << 8;
6677         *green = intel_crtc->lut_g[regno] << 8;
6678         *blue = intel_crtc->lut_b[regno] << 8;
6679 }
6680
6681 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6682                                  u16 *blue, uint32_t start, uint32_t size)
6683 {
6684         int end = (start + size > 256) ? 256 : start + size, i;
6685         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6686
6687         for (i = start; i < end; i++) {
6688                 intel_crtc->lut_r[i] = red[i] >> 8;
6689                 intel_crtc->lut_g[i] = green[i] >> 8;
6690                 intel_crtc->lut_b[i] = blue[i] >> 8;
6691         }
6692
6693         intel_crtc_load_lut(crtc);
6694 }
6695
6696 /* VESA 640x480x72Hz mode to set on the pipe */
6697 static struct drm_display_mode load_detect_mode = {
6698         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6699                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6700 };
6701
6702 static struct drm_framebuffer *
6703 intel_framebuffer_create(struct drm_device *dev,
6704                          struct drm_mode_fb_cmd2 *mode_cmd,
6705                          struct drm_i915_gem_object *obj)
6706 {
6707         struct intel_framebuffer *intel_fb;
6708         int ret;
6709
6710         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6711         if (!intel_fb) {
6712                 drm_gem_object_unreference_unlocked(&obj->base);
6713                 return ERR_PTR(-ENOMEM);
6714         }
6715
6716         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6717         if (ret) {
6718                 drm_gem_object_unreference_unlocked(&obj->base);
6719                 kfree(intel_fb);
6720                 return ERR_PTR(ret);
6721         }
6722
6723         return &intel_fb->base;
6724 }
6725
6726 static u32
6727 intel_framebuffer_pitch_for_width(int width, int bpp)
6728 {
6729         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6730         return ALIGN(pitch, 64);
6731 }
6732
6733 static u32
6734 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6735 {
6736         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6737         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6738 }
6739
6740 static struct drm_framebuffer *
6741 intel_framebuffer_create_for_mode(struct drm_device *dev,
6742                                   struct drm_display_mode *mode,
6743                                   int depth, int bpp)
6744 {
6745         struct drm_i915_gem_object *obj;
6746         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6747
6748         obj = i915_gem_alloc_object(dev,
6749                                     intel_framebuffer_size_for_mode(mode, bpp));
6750         if (obj == NULL)
6751                 return ERR_PTR(-ENOMEM);
6752
6753         mode_cmd.width = mode->hdisplay;
6754         mode_cmd.height = mode->vdisplay;
6755         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6756                                                                 bpp);
6757         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6758
6759         return intel_framebuffer_create(dev, &mode_cmd, obj);
6760 }
6761
6762 static struct drm_framebuffer *
6763 mode_fits_in_fbdev(struct drm_device *dev,
6764                    struct drm_display_mode *mode)
6765 {
6766         struct drm_i915_private *dev_priv = dev->dev_private;
6767         struct drm_i915_gem_object *obj;
6768         struct drm_framebuffer *fb;
6769
6770         if (dev_priv->fbdev == NULL)
6771                 return NULL;
6772
6773         obj = dev_priv->fbdev->ifb.obj;
6774         if (obj == NULL)
6775                 return NULL;
6776
6777         fb = &dev_priv->fbdev->ifb.base;
6778         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6779                                                                fb->bits_per_pixel))
6780                 return NULL;
6781
6782         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6783                 return NULL;
6784
6785         return fb;
6786 }
6787
6788 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6789                                 struct drm_display_mode *mode,
6790                                 struct intel_load_detect_pipe *old)
6791 {
6792         struct intel_crtc *intel_crtc;
6793         struct intel_encoder *intel_encoder =
6794                 intel_attached_encoder(connector);
6795         struct drm_crtc *possible_crtc;
6796         struct drm_encoder *encoder = &intel_encoder->base;
6797         struct drm_crtc *crtc = NULL;
6798         struct drm_device *dev = encoder->dev;
6799         struct drm_framebuffer *fb;
6800         int i = -1;
6801
6802         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6803                       connector->base.id, drm_get_connector_name(connector),
6804                       encoder->base.id, drm_get_encoder_name(encoder));
6805
6806         /*
6807          * Algorithm gets a little messy:
6808          *
6809          *   - if the connector already has an assigned crtc, use it (but make
6810          *     sure it's on first)
6811          *
6812          *   - try to find the first unused crtc that can drive this connector,
6813          *     and use that if we find one
6814          */
6815
6816         /* See if we already have a CRTC for this connector */
6817         if (encoder->crtc) {
6818                 crtc = encoder->crtc;
6819
6820                 mutex_lock(&crtc->mutex);
6821
6822                 old->dpms_mode = connector->dpms;
6823                 old->load_detect_temp = false;
6824
6825                 /* Make sure the crtc and connector are running */
6826                 if (connector->dpms != DRM_MODE_DPMS_ON)
6827                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6828
6829                 return true;
6830         }
6831
6832         /* Find an unused one (if possible) */
6833         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6834                 i++;
6835                 if (!(encoder->possible_crtcs & (1 << i)))
6836                         continue;
6837                 if (!possible_crtc->enabled) {
6838                         crtc = possible_crtc;
6839                         break;
6840                 }
6841         }
6842
6843         /*
6844          * If we didn't find an unused CRTC, don't use any.
6845          */
6846         if (!crtc) {
6847                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6848                 return false;
6849         }
6850
6851         mutex_lock(&crtc->mutex);
6852         intel_encoder->new_crtc = to_intel_crtc(crtc);
6853         to_intel_connector(connector)->new_encoder = intel_encoder;
6854
6855         intel_crtc = to_intel_crtc(crtc);
6856         old->dpms_mode = connector->dpms;
6857         old->load_detect_temp = true;
6858         old->release_fb = NULL;
6859
6860         if (!mode)
6861                 mode = &load_detect_mode;
6862
6863         /* We need a framebuffer large enough to accommodate all accesses
6864          * that the plane may generate whilst we perform load detection.
6865          * We can not rely on the fbcon either being present (we get called
6866          * during its initialisation to detect all boot displays, or it may
6867          * not even exist) or that it is large enough to satisfy the
6868          * requested mode.
6869          */
6870         fb = mode_fits_in_fbdev(dev, mode);
6871         if (fb == NULL) {
6872                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6873                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6874                 old->release_fb = fb;
6875         } else
6876                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6877         if (IS_ERR(fb)) {
6878                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6879                 mutex_unlock(&crtc->mutex);
6880                 return false;
6881         }
6882
6883         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6884                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6885                 if (old->release_fb)
6886                         old->release_fb->funcs->destroy(old->release_fb);
6887                 mutex_unlock(&crtc->mutex);
6888                 return false;
6889         }
6890
6891         /* let the connector get through one full cycle before testing */
6892         intel_wait_for_vblank(dev, intel_crtc->pipe);
6893         return true;
6894 }
6895
6896 void intel_release_load_detect_pipe(struct drm_connector *connector,
6897                                     struct intel_load_detect_pipe *old)
6898 {
6899         struct intel_encoder *intel_encoder =
6900                 intel_attached_encoder(connector);
6901         struct drm_encoder *encoder = &intel_encoder->base;
6902         struct drm_crtc *crtc = encoder->crtc;
6903
6904         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6905                       connector->base.id, drm_get_connector_name(connector),
6906                       encoder->base.id, drm_get_encoder_name(encoder));
6907
6908         if (old->load_detect_temp) {
6909                 to_intel_connector(connector)->new_encoder = NULL;
6910                 intel_encoder->new_crtc = NULL;
6911                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6912
6913                 if (old->release_fb) {
6914                         drm_framebuffer_unregister_private(old->release_fb);
6915                         drm_framebuffer_unreference(old->release_fb);
6916                 }
6917
6918                 mutex_unlock(&crtc->mutex);
6919                 return;
6920         }
6921
6922         /* Switch crtc and encoder back off if necessary */
6923         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6924                 connector->funcs->dpms(connector, old->dpms_mode);
6925
6926         mutex_unlock(&crtc->mutex);
6927 }
6928
6929 /* Returns the clock of the currently programmed mode of the given pipe. */
6930 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6931 {
6932         struct drm_i915_private *dev_priv = dev->dev_private;
6933         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6934         int pipe = intel_crtc->pipe;
6935         u32 dpll = I915_READ(DPLL(pipe));
6936         u32 fp;
6937         intel_clock_t clock;
6938
6939         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6940                 fp = I915_READ(FP0(pipe));
6941         else
6942                 fp = I915_READ(FP1(pipe));
6943
6944         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6945         if (IS_PINEVIEW(dev)) {
6946                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6947                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6948         } else {
6949                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6950                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6951         }
6952
6953         if (!IS_GEN2(dev)) {
6954                 if (IS_PINEVIEW(dev))
6955                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6956                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6957                 else
6958                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6959                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6960
6961                 switch (dpll & DPLL_MODE_MASK) {
6962                 case DPLLB_MODE_DAC_SERIAL:
6963                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6964                                 5 : 10;
6965                         break;
6966                 case DPLLB_MODE_LVDS:
6967                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6968                                 7 : 14;
6969                         break;
6970                 default:
6971                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6972                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6973                         return 0;
6974                 }
6975
6976                 /* XXX: Handle the 100Mhz refclk */
6977                 intel_clock(dev, 96000, &clock);
6978         } else {
6979                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6980
6981                 if (is_lvds) {
6982                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6983                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6984                         clock.p2 = 14;
6985
6986                         if ((dpll & PLL_REF_INPUT_MASK) ==
6987                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6988                                 /* XXX: might not be 66MHz */
6989                                 intel_clock(dev, 66000, &clock);
6990                         } else
6991                                 intel_clock(dev, 48000, &clock);
6992                 } else {
6993                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6994                                 clock.p1 = 2;
6995                         else {
6996                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6997                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6998                         }
6999                         if (dpll & PLL_P2_DIVIDE_BY_4)
7000                                 clock.p2 = 4;
7001                         else
7002                                 clock.p2 = 2;
7003
7004                         intel_clock(dev, 48000, &clock);
7005                 }
7006         }
7007
7008         /* XXX: It would be nice to validate the clocks, but we can't reuse
7009          * i830PllIsValid() because it relies on the xf86_config connector
7010          * configuration being accurate, which it isn't necessarily.
7011          */
7012
7013         return clock.dot;
7014 }
7015
7016 /** Returns the currently programmed mode of the given pipe. */
7017 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7018                                              struct drm_crtc *crtc)
7019 {
7020         struct drm_i915_private *dev_priv = dev->dev_private;
7021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7022         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7023         struct drm_display_mode *mode;
7024         int htot = I915_READ(HTOTAL(cpu_transcoder));
7025         int hsync = I915_READ(HSYNC(cpu_transcoder));
7026         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7027         int vsync = I915_READ(VSYNC(cpu_transcoder));
7028
7029         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7030         if (!mode)
7031                 return NULL;
7032
7033         mode->clock = intel_crtc_clock_get(dev, crtc);
7034         mode->hdisplay = (htot & 0xffff) + 1;
7035         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7036         mode->hsync_start = (hsync & 0xffff) + 1;
7037         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7038         mode->vdisplay = (vtot & 0xffff) + 1;
7039         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7040         mode->vsync_start = (vsync & 0xffff) + 1;
7041         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7042
7043         drm_mode_set_name(mode);
7044
7045         return mode;
7046 }
7047
7048 static void intel_increase_pllclock(struct drm_crtc *crtc)
7049 {
7050         struct drm_device *dev = crtc->dev;
7051         drm_i915_private_t *dev_priv = dev->dev_private;
7052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7053         int pipe = intel_crtc->pipe;
7054         int dpll_reg = DPLL(pipe);
7055         int dpll;
7056
7057         if (HAS_PCH_SPLIT(dev))
7058                 return;
7059
7060         if (!dev_priv->lvds_downclock_avail)
7061                 return;
7062
7063         dpll = I915_READ(dpll_reg);
7064         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7065                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7066
7067                 assert_panel_unlocked(dev_priv, pipe);
7068
7069                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7070                 I915_WRITE(dpll_reg, dpll);
7071                 intel_wait_for_vblank(dev, pipe);
7072
7073                 dpll = I915_READ(dpll_reg);
7074                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7075                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7076         }
7077 }
7078
7079 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7080 {
7081         struct drm_device *dev = crtc->dev;
7082         drm_i915_private_t *dev_priv = dev->dev_private;
7083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7084
7085         if (HAS_PCH_SPLIT(dev))
7086                 return;
7087
7088         if (!dev_priv->lvds_downclock_avail)
7089                 return;
7090
7091         /*
7092          * Since this is called by a timer, we should never get here in
7093          * the manual case.
7094          */
7095         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7096                 int pipe = intel_crtc->pipe;
7097                 int dpll_reg = DPLL(pipe);
7098                 int dpll;
7099
7100                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7101
7102                 assert_panel_unlocked(dev_priv, pipe);
7103
7104                 dpll = I915_READ(dpll_reg);
7105                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7106                 I915_WRITE(dpll_reg, dpll);
7107                 intel_wait_for_vblank(dev, pipe);
7108                 dpll = I915_READ(dpll_reg);
7109                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7110                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7111         }
7112
7113 }
7114
7115 void intel_mark_busy(struct drm_device *dev)
7116 {
7117         i915_update_gfx_val(dev->dev_private);
7118 }
7119
7120 void intel_mark_idle(struct drm_device *dev)
7121 {
7122         struct drm_crtc *crtc;
7123
7124         if (!i915_powersave)
7125                 return;
7126
7127         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7128                 if (!crtc->fb)
7129                         continue;
7130
7131                 intel_decrease_pllclock(crtc);
7132         }
7133 }
7134
7135 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7136 {
7137         struct drm_device *dev = obj->base.dev;
7138         struct drm_crtc *crtc;
7139
7140         if (!i915_powersave)
7141                 return;
7142
7143         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7144                 if (!crtc->fb)
7145                         continue;
7146
7147                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7148                         intel_increase_pllclock(crtc);
7149         }
7150 }
7151
7152 static void intel_crtc_destroy(struct drm_crtc *crtc)
7153 {
7154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7155         struct drm_device *dev = crtc->dev;
7156         struct intel_unpin_work *work;
7157         unsigned long flags;
7158
7159         spin_lock_irqsave(&dev->event_lock, flags);
7160         work = intel_crtc->unpin_work;
7161         intel_crtc->unpin_work = NULL;
7162         spin_unlock_irqrestore(&dev->event_lock, flags);
7163
7164         if (work) {
7165                 cancel_work_sync(&work->work);
7166                 kfree(work);
7167         }
7168
7169         drm_crtc_cleanup(crtc);
7170
7171         kfree(intel_crtc);
7172 }
7173
7174 static void intel_unpin_work_fn(struct work_struct *__work)
7175 {
7176         struct intel_unpin_work *work =
7177                 container_of(__work, struct intel_unpin_work, work);
7178         struct drm_device *dev = work->crtc->dev;
7179
7180         mutex_lock(&dev->struct_mutex);
7181         intel_unpin_fb_obj(work->old_fb_obj);
7182         drm_gem_object_unreference(&work->pending_flip_obj->base);
7183         drm_gem_object_unreference(&work->old_fb_obj->base);
7184
7185         intel_update_fbc(dev);
7186         mutex_unlock(&dev->struct_mutex);
7187
7188         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7189         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7190
7191         kfree(work);
7192 }
7193
7194 static void do_intel_finish_page_flip(struct drm_device *dev,
7195                                       struct drm_crtc *crtc)
7196 {
7197         drm_i915_private_t *dev_priv = dev->dev_private;
7198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7199         struct intel_unpin_work *work;
7200         unsigned long flags;
7201
7202         /* Ignore early vblank irqs */
7203         if (intel_crtc == NULL)
7204                 return;
7205
7206         spin_lock_irqsave(&dev->event_lock, flags);
7207         work = intel_crtc->unpin_work;
7208
7209         /* Ensure we don't miss a work->pending update ... */
7210         smp_rmb();
7211
7212         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7213                 spin_unlock_irqrestore(&dev->event_lock, flags);
7214                 return;
7215         }
7216
7217         /* and that the unpin work is consistent wrt ->pending. */
7218         smp_rmb();
7219
7220         intel_crtc->unpin_work = NULL;
7221
7222         if (work->event)
7223                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7224
7225         drm_vblank_put(dev, intel_crtc->pipe);
7226
7227         spin_unlock_irqrestore(&dev->event_lock, flags);
7228
7229         wake_up_all(&dev_priv->pending_flip_queue);
7230
7231         queue_work(dev_priv->wq, &work->work);
7232
7233         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7234 }
7235
7236 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7237 {
7238         drm_i915_private_t *dev_priv = dev->dev_private;
7239         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7240
7241         do_intel_finish_page_flip(dev, crtc);
7242 }
7243
7244 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7245 {
7246         drm_i915_private_t *dev_priv = dev->dev_private;
7247         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7248
7249         do_intel_finish_page_flip(dev, crtc);
7250 }
7251
7252 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7253 {
7254         drm_i915_private_t *dev_priv = dev->dev_private;
7255         struct intel_crtc *intel_crtc =
7256                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7257         unsigned long flags;
7258
7259         /* NB: An MMIO update of the plane base pointer will also
7260          * generate a page-flip completion irq, i.e. every modeset
7261          * is also accompanied by a spurious intel_prepare_page_flip().
7262          */
7263         spin_lock_irqsave(&dev->event_lock, flags);
7264         if (intel_crtc->unpin_work)
7265                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7266         spin_unlock_irqrestore(&dev->event_lock, flags);
7267 }
7268
7269 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7270 {
7271         /* Ensure that the work item is consistent when activating it ... */
7272         smp_wmb();
7273         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7274         /* and that it is marked active as soon as the irq could fire. */
7275         smp_wmb();
7276 }
7277
7278 static int intel_gen2_queue_flip(struct drm_device *dev,
7279                                  struct drm_crtc *crtc,
7280                                  struct drm_framebuffer *fb,
7281                                  struct drm_i915_gem_object *obj)
7282 {
7283         struct drm_i915_private *dev_priv = dev->dev_private;
7284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7285         u32 flip_mask;
7286         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7287         int ret;
7288
7289         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7290         if (ret)
7291                 goto err;
7292
7293         ret = intel_ring_begin(ring, 6);
7294         if (ret)
7295                 goto err_unpin;
7296
7297         /* Can't queue multiple flips, so wait for the previous
7298          * one to finish before executing the next.
7299          */
7300         if (intel_crtc->plane)
7301                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7302         else
7303                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7304         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7305         intel_ring_emit(ring, MI_NOOP);
7306         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7307                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7308         intel_ring_emit(ring, fb->pitches[0]);
7309         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7310         intel_ring_emit(ring, 0); /* aux display base address, unused */
7311
7312         intel_mark_page_flip_active(intel_crtc);
7313         intel_ring_advance(ring);
7314         return 0;
7315
7316 err_unpin:
7317         intel_unpin_fb_obj(obj);
7318 err:
7319         return ret;
7320 }
7321
7322 static int intel_gen3_queue_flip(struct drm_device *dev,
7323                                  struct drm_crtc *crtc,
7324                                  struct drm_framebuffer *fb,
7325                                  struct drm_i915_gem_object *obj)
7326 {
7327         struct drm_i915_private *dev_priv = dev->dev_private;
7328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7329         u32 flip_mask;
7330         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7331         int ret;
7332
7333         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7334         if (ret)
7335                 goto err;
7336
7337         ret = intel_ring_begin(ring, 6);
7338         if (ret)
7339                 goto err_unpin;
7340
7341         if (intel_crtc->plane)
7342                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7343         else
7344                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7345         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7346         intel_ring_emit(ring, MI_NOOP);
7347         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7348                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7349         intel_ring_emit(ring, fb->pitches[0]);
7350         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7351         intel_ring_emit(ring, MI_NOOP);
7352
7353         intel_mark_page_flip_active(intel_crtc);
7354         intel_ring_advance(ring);
7355         return 0;
7356
7357 err_unpin:
7358         intel_unpin_fb_obj(obj);
7359 err:
7360         return ret;
7361 }
7362
7363 static int intel_gen4_queue_flip(struct drm_device *dev,
7364                                  struct drm_crtc *crtc,
7365                                  struct drm_framebuffer *fb,
7366                                  struct drm_i915_gem_object *obj)
7367 {
7368         struct drm_i915_private *dev_priv = dev->dev_private;
7369         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7370         uint32_t pf, pipesrc;
7371         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7372         int ret;
7373
7374         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7375         if (ret)
7376                 goto err;
7377
7378         ret = intel_ring_begin(ring, 4);
7379         if (ret)
7380                 goto err_unpin;
7381
7382         /* i965+ uses the linear or tiled offsets from the
7383          * Display Registers (which do not change across a page-flip)
7384          * so we need only reprogram the base address.
7385          */
7386         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7387                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7388         intel_ring_emit(ring, fb->pitches[0]);
7389         intel_ring_emit(ring,
7390                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7391                         obj->tiling_mode);
7392
7393         /* XXX Enabling the panel-fitter across page-flip is so far
7394          * untested on non-native modes, so ignore it for now.
7395          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7396          */
7397         pf = 0;
7398         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7399         intel_ring_emit(ring, pf | pipesrc);
7400
7401         intel_mark_page_flip_active(intel_crtc);
7402         intel_ring_advance(ring);
7403         return 0;
7404
7405 err_unpin:
7406         intel_unpin_fb_obj(obj);
7407 err:
7408         return ret;
7409 }
7410
7411 static int intel_gen6_queue_flip(struct drm_device *dev,
7412                                  struct drm_crtc *crtc,
7413                                  struct drm_framebuffer *fb,
7414                                  struct drm_i915_gem_object *obj)
7415 {
7416         struct drm_i915_private *dev_priv = dev->dev_private;
7417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7418         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7419         uint32_t pf, pipesrc;
7420         int ret;
7421
7422         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7423         if (ret)
7424                 goto err;
7425
7426         ret = intel_ring_begin(ring, 4);
7427         if (ret)
7428                 goto err_unpin;
7429
7430         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7431                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7432         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7433         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7434
7435         /* Contrary to the suggestions in the documentation,
7436          * "Enable Panel Fitter" does not seem to be required when page
7437          * flipping with a non-native mode, and worse causes a normal
7438          * modeset to fail.
7439          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7440          */
7441         pf = 0;
7442         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7443         intel_ring_emit(ring, pf | pipesrc);
7444
7445         intel_mark_page_flip_active(intel_crtc);
7446         intel_ring_advance(ring);
7447         return 0;
7448
7449 err_unpin:
7450         intel_unpin_fb_obj(obj);
7451 err:
7452         return ret;
7453 }
7454
7455 /*
7456  * On gen7 we currently use the blit ring because (in early silicon at least)
7457  * the render ring doesn't give us interrpts for page flip completion, which
7458  * means clients will hang after the first flip is queued.  Fortunately the
7459  * blit ring generates interrupts properly, so use it instead.
7460  */
7461 static int intel_gen7_queue_flip(struct drm_device *dev,
7462                                  struct drm_crtc *crtc,
7463                                  struct drm_framebuffer *fb,
7464                                  struct drm_i915_gem_object *obj)
7465 {
7466         struct drm_i915_private *dev_priv = dev->dev_private;
7467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7468         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7469         uint32_t plane_bit = 0;
7470         int ret;
7471
7472         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7473         if (ret)
7474                 goto err;
7475
7476         switch(intel_crtc->plane) {
7477         case PLANE_A:
7478                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7479                 break;
7480         case PLANE_B:
7481                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7482                 break;
7483         case PLANE_C:
7484                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7485                 break;
7486         default:
7487                 WARN_ONCE(1, "unknown plane in flip command\n");
7488                 ret = -ENODEV;
7489                 goto err_unpin;
7490         }
7491
7492         ret = intel_ring_begin(ring, 4);
7493         if (ret)
7494                 goto err_unpin;
7495
7496         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7497         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7498         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7499         intel_ring_emit(ring, (MI_NOOP));
7500
7501         intel_mark_page_flip_active(intel_crtc);
7502         intel_ring_advance(ring);
7503         return 0;
7504
7505 err_unpin:
7506         intel_unpin_fb_obj(obj);
7507 err:
7508         return ret;
7509 }
7510
7511 static int intel_default_queue_flip(struct drm_device *dev,
7512                                     struct drm_crtc *crtc,
7513                                     struct drm_framebuffer *fb,
7514                                     struct drm_i915_gem_object *obj)
7515 {
7516         return -ENODEV;
7517 }
7518
7519 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7520                                 struct drm_framebuffer *fb,
7521                                 struct drm_pending_vblank_event *event)
7522 {
7523         struct drm_device *dev = crtc->dev;
7524         struct drm_i915_private *dev_priv = dev->dev_private;
7525         struct drm_framebuffer *old_fb = crtc->fb;
7526         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7528         struct intel_unpin_work *work;
7529         unsigned long flags;
7530         int ret;
7531
7532         /* Can't change pixel format via MI display flips. */
7533         if (fb->pixel_format != crtc->fb->pixel_format)
7534                 return -EINVAL;
7535
7536         /*
7537          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7538          * Note that pitch changes could also affect these register.
7539          */
7540         if (INTEL_INFO(dev)->gen > 3 &&
7541             (fb->offsets[0] != crtc->fb->offsets[0] ||
7542              fb->pitches[0] != crtc->fb->pitches[0]))
7543                 return -EINVAL;
7544
7545         work = kzalloc(sizeof *work, GFP_KERNEL);
7546         if (work == NULL)
7547                 return -ENOMEM;
7548
7549         work->event = event;
7550         work->crtc = crtc;
7551         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7552         INIT_WORK(&work->work, intel_unpin_work_fn);
7553
7554         ret = drm_vblank_get(dev, intel_crtc->pipe);
7555         if (ret)
7556                 goto free_work;
7557
7558         /* We borrow the event spin lock for protecting unpin_work */
7559         spin_lock_irqsave(&dev->event_lock, flags);
7560         if (intel_crtc->unpin_work) {
7561                 spin_unlock_irqrestore(&dev->event_lock, flags);
7562                 kfree(work);
7563                 drm_vblank_put(dev, intel_crtc->pipe);
7564
7565                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7566                 return -EBUSY;
7567         }
7568         intel_crtc->unpin_work = work;
7569         spin_unlock_irqrestore(&dev->event_lock, flags);
7570
7571         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7572                 flush_workqueue(dev_priv->wq);
7573
7574         ret = i915_mutex_lock_interruptible(dev);
7575         if (ret)
7576                 goto cleanup;
7577
7578         /* Reference the objects for the scheduled work. */
7579         drm_gem_object_reference(&work->old_fb_obj->base);
7580         drm_gem_object_reference(&obj->base);
7581
7582         crtc->fb = fb;
7583
7584         work->pending_flip_obj = obj;
7585
7586         work->enable_stall_check = true;
7587
7588         atomic_inc(&intel_crtc->unpin_work_count);
7589         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7590
7591         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7592         if (ret)
7593                 goto cleanup_pending;
7594
7595         intel_disable_fbc(dev);
7596         intel_mark_fb_busy(obj);
7597         mutex_unlock(&dev->struct_mutex);
7598
7599         trace_i915_flip_request(intel_crtc->plane, obj);
7600
7601         return 0;
7602
7603 cleanup_pending:
7604         atomic_dec(&intel_crtc->unpin_work_count);
7605         crtc->fb = old_fb;
7606         drm_gem_object_unreference(&work->old_fb_obj->base);
7607         drm_gem_object_unreference(&obj->base);
7608         mutex_unlock(&dev->struct_mutex);
7609
7610 cleanup:
7611         spin_lock_irqsave(&dev->event_lock, flags);
7612         intel_crtc->unpin_work = NULL;
7613         spin_unlock_irqrestore(&dev->event_lock, flags);
7614
7615         drm_vblank_put(dev, intel_crtc->pipe);
7616 free_work:
7617         kfree(work);
7618
7619         return ret;
7620 }
7621
7622 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7623         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7624         .load_lut = intel_crtc_load_lut,
7625 };
7626
7627 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7628 {
7629         struct intel_encoder *other_encoder;
7630         struct drm_crtc *crtc = &encoder->new_crtc->base;
7631
7632         if (WARN_ON(!crtc))
7633                 return false;
7634
7635         list_for_each_entry(other_encoder,
7636                             &crtc->dev->mode_config.encoder_list,
7637                             base.head) {
7638
7639                 if (&other_encoder->new_crtc->base != crtc ||
7640                     encoder == other_encoder)
7641                         continue;
7642                 else
7643                         return true;
7644         }
7645
7646         return false;
7647 }
7648
7649 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7650                                   struct drm_crtc *crtc)
7651 {
7652         struct drm_device *dev;
7653         struct drm_crtc *tmp;
7654         int crtc_mask = 1;
7655
7656         WARN(!crtc, "checking null crtc?\n");
7657
7658         dev = crtc->dev;
7659
7660         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7661                 if (tmp == crtc)
7662                         break;
7663                 crtc_mask <<= 1;
7664         }
7665
7666         if (encoder->possible_crtcs & crtc_mask)
7667                 return true;
7668         return false;
7669 }
7670
7671 /**
7672  * intel_modeset_update_staged_output_state
7673  *
7674  * Updates the staged output configuration state, e.g. after we've read out the
7675  * current hw state.
7676  */
7677 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7678 {
7679         struct intel_encoder *encoder;
7680         struct intel_connector *connector;
7681
7682         list_for_each_entry(connector, &dev->mode_config.connector_list,
7683                             base.head) {
7684                 connector->new_encoder =
7685                         to_intel_encoder(connector->base.encoder);
7686         }
7687
7688         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7689                             base.head) {
7690                 encoder->new_crtc =
7691                         to_intel_crtc(encoder->base.crtc);
7692         }
7693 }
7694
7695 /**
7696  * intel_modeset_commit_output_state
7697  *
7698  * This function copies the stage display pipe configuration to the real one.
7699  */
7700 static void intel_modeset_commit_output_state(struct drm_device *dev)
7701 {
7702         struct intel_encoder *encoder;
7703         struct intel_connector *connector;
7704
7705         list_for_each_entry(connector, &dev->mode_config.connector_list,
7706                             base.head) {
7707                 connector->base.encoder = &connector->new_encoder->base;
7708         }
7709
7710         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7711                             base.head) {
7712                 encoder->base.crtc = &encoder->new_crtc->base;
7713         }
7714 }
7715
7716 static int
7717 pipe_config_set_bpp(struct drm_crtc *crtc,
7718                     struct drm_framebuffer *fb,
7719                     struct intel_crtc_config *pipe_config)
7720 {
7721         struct drm_device *dev = crtc->dev;
7722         struct drm_connector *connector;
7723         int bpp;
7724
7725         switch (fb->pixel_format) {
7726         case DRM_FORMAT_C8:
7727                 bpp = 8*3; /* since we go through a colormap */
7728                 break;
7729         case DRM_FORMAT_XRGB1555:
7730         case DRM_FORMAT_ARGB1555:
7731                 /* checked in intel_framebuffer_init already */
7732                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7733                         return -EINVAL;
7734         case DRM_FORMAT_RGB565:
7735                 bpp = 6*3; /* min is 18bpp */
7736                 break;
7737         case DRM_FORMAT_XBGR8888:
7738         case DRM_FORMAT_ABGR8888:
7739                 /* checked in intel_framebuffer_init already */
7740                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7741                         return -EINVAL;
7742         case DRM_FORMAT_XRGB8888:
7743         case DRM_FORMAT_ARGB8888:
7744                 bpp = 8*3;
7745                 break;
7746         case DRM_FORMAT_XRGB2101010:
7747         case DRM_FORMAT_ARGB2101010:
7748         case DRM_FORMAT_XBGR2101010:
7749         case DRM_FORMAT_ABGR2101010:
7750                 /* checked in intel_framebuffer_init already */
7751                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7752                         return -EINVAL;
7753                 bpp = 10*3;
7754                 break;
7755         /* TODO: gen4+ supports 16 bpc floating point, too. */
7756         default:
7757                 DRM_DEBUG_KMS("unsupported depth\n");
7758                 return -EINVAL;
7759         }
7760
7761         pipe_config->pipe_bpp = bpp;
7762
7763         /* Clamp display bpp to EDID value */
7764         list_for_each_entry(connector, &dev->mode_config.connector_list,
7765                             head) {
7766                 if (connector->encoder && connector->encoder->crtc != crtc)
7767                         continue;
7768
7769                 /* Don't use an invalid EDID bpc value */
7770                 if (connector->display_info.bpc &&
7771                     connector->display_info.bpc * 3 < bpp) {
7772                         DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7773                                       bpp, connector->display_info.bpc*3);
7774                         pipe_config->pipe_bpp = connector->display_info.bpc*3;
7775                 }
7776
7777                 /* Clamp bpp to 8 on screens without EDID 1.4 */
7778                 if (connector->display_info.bpc == 0 && bpp > 24) {
7779                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7780                                       bpp);
7781                         pipe_config->pipe_bpp = 24;
7782                 }
7783         }
7784
7785         return bpp;
7786 }
7787
7788 static struct intel_crtc_config *
7789 intel_modeset_pipe_config(struct drm_crtc *crtc,
7790                           struct drm_framebuffer *fb,
7791                           struct drm_display_mode *mode)
7792 {
7793         struct drm_device *dev = crtc->dev;
7794         struct drm_encoder_helper_funcs *encoder_funcs;
7795         struct intel_encoder *encoder;
7796         struct intel_crtc_config *pipe_config;
7797         int plane_bpp, ret = -EINVAL;
7798         bool retry = true;
7799
7800         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7801         if (!pipe_config)
7802                 return ERR_PTR(-ENOMEM);
7803
7804         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7805         drm_mode_copy(&pipe_config->requested_mode, mode);
7806
7807         plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7808         if (plane_bpp < 0)
7809                 goto fail;
7810
7811 encoder_retry:
7812         /* Pass our mode to the connectors and the CRTC to give them a chance to
7813          * adjust it according to limitations or connector properties, and also
7814          * a chance to reject the mode entirely.
7815          */
7816         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7817                             base.head) {
7818
7819                 if (&encoder->new_crtc->base != crtc)
7820                         continue;
7821
7822                 if (encoder->compute_config) {
7823                         if (!(encoder->compute_config(encoder, pipe_config))) {
7824                                 DRM_DEBUG_KMS("Encoder config failure\n");
7825                                 goto fail;
7826                         }
7827
7828                         continue;
7829                 }
7830
7831                 encoder_funcs = encoder->base.helper_private;
7832                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7833                                                 &pipe_config->requested_mode,
7834                                                 &pipe_config->adjusted_mode))) {
7835                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7836                         goto fail;
7837                 }
7838         }
7839
7840         ret = intel_crtc_compute_config(crtc, pipe_config);
7841         if (ret < 0) {
7842                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7843                 goto fail;
7844         }
7845
7846         if (ret == RETRY) {
7847                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7848                         ret = -EINVAL;
7849                         goto fail;
7850                 }
7851
7852                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7853                 retry = false;
7854                 goto encoder_retry;
7855         }
7856
7857         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7858
7859         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7860         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7861                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7862
7863         return pipe_config;
7864 fail:
7865         kfree(pipe_config);
7866         return ERR_PTR(ret);
7867 }
7868
7869 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7870  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7871 static void
7872 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7873                              unsigned *prepare_pipes, unsigned *disable_pipes)
7874 {
7875         struct intel_crtc *intel_crtc;
7876         struct drm_device *dev = crtc->dev;
7877         struct intel_encoder *encoder;
7878         struct intel_connector *connector;
7879         struct drm_crtc *tmp_crtc;
7880
7881         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7882
7883         /* Check which crtcs have changed outputs connected to them, these need
7884          * to be part of the prepare_pipes mask. We don't (yet) support global
7885          * modeset across multiple crtcs, so modeset_pipes will only have one
7886          * bit set at most. */
7887         list_for_each_entry(connector, &dev->mode_config.connector_list,
7888                             base.head) {
7889                 if (connector->base.encoder == &connector->new_encoder->base)
7890                         continue;
7891
7892                 if (connector->base.encoder) {
7893                         tmp_crtc = connector->base.encoder->crtc;
7894
7895                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7896                 }
7897
7898                 if (connector->new_encoder)
7899                         *prepare_pipes |=
7900                                 1 << connector->new_encoder->new_crtc->pipe;
7901         }
7902
7903         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7904                             base.head) {
7905                 if (encoder->base.crtc == &encoder->new_crtc->base)
7906                         continue;
7907
7908                 if (encoder->base.crtc) {
7909                         tmp_crtc = encoder->base.crtc;
7910
7911                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7912                 }
7913
7914                 if (encoder->new_crtc)
7915                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7916         }
7917
7918         /* Check for any pipes that will be fully disabled ... */
7919         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7920                             base.head) {
7921                 bool used = false;
7922
7923                 /* Don't try to disable disabled crtcs. */
7924                 if (!intel_crtc->base.enabled)
7925                         continue;
7926
7927                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7928                                     base.head) {
7929                         if (encoder->new_crtc == intel_crtc)
7930                                 used = true;
7931                 }
7932
7933                 if (!used)
7934                         *disable_pipes |= 1 << intel_crtc->pipe;
7935         }
7936
7937
7938         /* set_mode is also used to update properties on life display pipes. */
7939         intel_crtc = to_intel_crtc(crtc);
7940         if (crtc->enabled)
7941                 *prepare_pipes |= 1 << intel_crtc->pipe;
7942
7943         /*
7944          * For simplicity do a full modeset on any pipe where the output routing
7945          * changed. We could be more clever, but that would require us to be
7946          * more careful with calling the relevant encoder->mode_set functions.
7947          */
7948         if (*prepare_pipes)
7949                 *modeset_pipes = *prepare_pipes;
7950
7951         /* ... and mask these out. */
7952         *modeset_pipes &= ~(*disable_pipes);
7953         *prepare_pipes &= ~(*disable_pipes);
7954
7955         /*
7956          * HACK: We don't (yet) fully support global modesets. intel_set_config
7957          * obies this rule, but the modeset restore mode of
7958          * intel_modeset_setup_hw_state does not.
7959          */
7960         *modeset_pipes &= 1 << intel_crtc->pipe;
7961         *prepare_pipes &= 1 << intel_crtc->pipe;
7962
7963         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7964                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7965 }
7966
7967 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7968 {
7969         struct drm_encoder *encoder;
7970         struct drm_device *dev = crtc->dev;
7971
7972         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7973                 if (encoder->crtc == crtc)
7974                         return true;
7975
7976         return false;
7977 }
7978
7979 static void
7980 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7981 {
7982         struct intel_encoder *intel_encoder;
7983         struct intel_crtc *intel_crtc;
7984         struct drm_connector *connector;
7985
7986         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7987                             base.head) {
7988                 if (!intel_encoder->base.crtc)
7989                         continue;
7990
7991                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7992
7993                 if (prepare_pipes & (1 << intel_crtc->pipe))
7994                         intel_encoder->connectors_active = false;
7995         }
7996
7997         intel_modeset_commit_output_state(dev);
7998
7999         /* Update computed state. */
8000         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8001                             base.head) {
8002                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8003         }
8004
8005         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8006                 if (!connector->encoder || !connector->encoder->crtc)
8007                         continue;
8008
8009                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8010
8011                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8012                         struct drm_property *dpms_property =
8013                                 dev->mode_config.dpms_property;
8014
8015                         connector->dpms = DRM_MODE_DPMS_ON;
8016                         drm_object_property_set_value(&connector->base,
8017                                                          dpms_property,
8018                                                          DRM_MODE_DPMS_ON);
8019
8020                         intel_encoder = to_intel_encoder(connector->encoder);
8021                         intel_encoder->connectors_active = true;
8022                 }
8023         }
8024
8025 }
8026
8027 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8028         list_for_each_entry((intel_crtc), \
8029                             &(dev)->mode_config.crtc_list, \
8030                             base.head) \
8031                 if (mask & (1 <<(intel_crtc)->pipe))
8032
8033 static bool
8034 intel_pipe_config_compare(struct intel_crtc_config *current_config,
8035                           struct intel_crtc_config *pipe_config)
8036 {
8037 #define PIPE_CONF_CHECK_I(name) \
8038         if (current_config->name != pipe_config->name) { \
8039                 DRM_ERROR("mismatch in " #name " " \
8040                           "(expected %i, found %i)\n", \
8041                           current_config->name, \
8042                           pipe_config->name); \
8043                 return false; \
8044         }
8045
8046 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8047         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8048                 DRM_ERROR("mismatch in " #name " " \
8049                           "(expected %i, found %i)\n", \
8050                           current_config->name & (mask), \
8051                           pipe_config->name & (mask)); \
8052                 return false; \
8053         }
8054
8055         PIPE_CONF_CHECK_I(has_pch_encoder);
8056         PIPE_CONF_CHECK_I(fdi_lanes);
8057         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8058         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8059         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8060         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8061         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8062
8063         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8064         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8065         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8066         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8067         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8068         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8069
8070         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8071         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8072         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8073         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8074         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8075         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8076
8077         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8078                               DRM_MODE_FLAG_INTERLACE);
8079
8080         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8081         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8082
8083 #undef PIPE_CONF_CHECK_I
8084 #undef PIPE_CONF_CHECK_FLAGS
8085
8086         return true;
8087 }
8088
8089 void
8090 intel_modeset_check_state(struct drm_device *dev)
8091 {
8092         drm_i915_private_t *dev_priv = dev->dev_private;
8093         struct intel_crtc *crtc;
8094         struct intel_encoder *encoder;
8095         struct intel_connector *connector;
8096         struct intel_crtc_config pipe_config;
8097
8098         list_for_each_entry(connector, &dev->mode_config.connector_list,
8099                             base.head) {
8100                 /* This also checks the encoder/connector hw state with the
8101                  * ->get_hw_state callbacks. */
8102                 intel_connector_check_state(connector);
8103
8104                 WARN(&connector->new_encoder->base != connector->base.encoder,
8105                      "connector's staged encoder doesn't match current encoder\n");
8106         }
8107
8108         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8109                             base.head) {
8110                 bool enabled = false;
8111                 bool active = false;
8112                 enum pipe pipe, tracked_pipe;
8113
8114                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8115                               encoder->base.base.id,
8116                               drm_get_encoder_name(&encoder->base));
8117
8118                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8119                      "encoder's stage crtc doesn't match current crtc\n");
8120                 WARN(encoder->connectors_active && !encoder->base.crtc,
8121                      "encoder's active_connectors set, but no crtc\n");
8122
8123                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8124                                     base.head) {
8125                         if (connector->base.encoder != &encoder->base)
8126                                 continue;
8127                         enabled = true;
8128                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8129                                 active = true;
8130                 }
8131                 WARN(!!encoder->base.crtc != enabled,
8132                      "encoder's enabled state mismatch "
8133                      "(expected %i, found %i)\n",
8134                      !!encoder->base.crtc, enabled);
8135                 WARN(active && !encoder->base.crtc,
8136                      "active encoder with no crtc\n");
8137
8138                 WARN(encoder->connectors_active != active,
8139                      "encoder's computed active state doesn't match tracked active state "
8140                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8141
8142                 active = encoder->get_hw_state(encoder, &pipe);
8143                 WARN(active != encoder->connectors_active,
8144                      "encoder's hw state doesn't match sw tracking "
8145                      "(expected %i, found %i)\n",
8146                      encoder->connectors_active, active);
8147
8148                 if (!encoder->base.crtc)
8149                         continue;
8150
8151                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8152                 WARN(active && pipe != tracked_pipe,
8153                      "active encoder's pipe doesn't match"
8154                      "(expected %i, found %i)\n",
8155                      tracked_pipe, pipe);
8156
8157         }
8158
8159         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8160                             base.head) {
8161                 bool enabled = false;
8162                 bool active = false;
8163
8164                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8165                               crtc->base.base.id);
8166
8167                 WARN(crtc->active && !crtc->base.enabled,
8168                      "active crtc, but not enabled in sw tracking\n");
8169
8170                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8171                                     base.head) {
8172                         if (encoder->base.crtc != &crtc->base)
8173                                 continue;
8174                         enabled = true;
8175                         if (encoder->connectors_active)
8176                                 active = true;
8177                 }
8178                 WARN(active != crtc->active,
8179                      "crtc's computed active state doesn't match tracked active state "
8180                      "(expected %i, found %i)\n", active, crtc->active);
8181                 WARN(enabled != crtc->base.enabled,
8182                      "crtc's computed enabled state doesn't match tracked enabled state "
8183                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8184
8185                 memset(&pipe_config, 0, sizeof(pipe_config));
8186                 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
8187                 active = dev_priv->display.get_pipe_config(crtc,
8188                                                            &pipe_config);
8189                 WARN(crtc->active != active,
8190                      "crtc active state doesn't match with hw state "
8191                      "(expected %i, found %i)\n", crtc->active, active);
8192
8193                 WARN(active &&
8194                      !intel_pipe_config_compare(&crtc->config, &pipe_config),
8195                      "pipe state doesn't match!\n");
8196         }
8197 }
8198
8199 static int __intel_set_mode(struct drm_crtc *crtc,
8200                             struct drm_display_mode *mode,
8201                             int x, int y, struct drm_framebuffer *fb)
8202 {
8203         struct drm_device *dev = crtc->dev;
8204         drm_i915_private_t *dev_priv = dev->dev_private;
8205         struct drm_display_mode *saved_mode, *saved_hwmode;
8206         struct intel_crtc_config *pipe_config = NULL;
8207         struct intel_crtc *intel_crtc;
8208         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8209         int ret = 0;
8210
8211         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8212         if (!saved_mode)
8213                 return -ENOMEM;
8214         saved_hwmode = saved_mode + 1;
8215
8216         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8217                                      &prepare_pipes, &disable_pipes);
8218
8219         *saved_hwmode = crtc->hwmode;
8220         *saved_mode = crtc->mode;
8221
8222         /* Hack: Because we don't (yet) support global modeset on multiple
8223          * crtcs, we don't keep track of the new mode for more than one crtc.
8224          * Hence simply check whether any bit is set in modeset_pipes in all the
8225          * pieces of code that are not yet converted to deal with mutliple crtcs
8226          * changing their mode at the same time. */
8227         if (modeset_pipes) {
8228                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8229                 if (IS_ERR(pipe_config)) {
8230                         ret = PTR_ERR(pipe_config);
8231                         pipe_config = NULL;
8232
8233                         goto out;
8234                 }
8235         }
8236
8237         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8238                 intel_crtc_disable(&intel_crtc->base);
8239
8240         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8241                 if (intel_crtc->base.enabled)
8242                         dev_priv->display.crtc_disable(&intel_crtc->base);
8243         }
8244
8245         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8246          * to set it here already despite that we pass it down the callchain.
8247          */
8248         if (modeset_pipes) {
8249                 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8250                 crtc->mode = *mode;
8251                 /* mode_set/enable/disable functions rely on a correct pipe
8252                  * config. */
8253                 to_intel_crtc(crtc)->config = *pipe_config;
8254                 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8255         }
8256
8257         /* Only after disabling all output pipelines that will be changed can we
8258          * update the the output configuration. */
8259         intel_modeset_update_state(dev, prepare_pipes);
8260
8261         if (dev_priv->display.modeset_global_resources)
8262                 dev_priv->display.modeset_global_resources(dev);
8263
8264         /* Set up the DPLL and any encoders state that needs to adjust or depend
8265          * on the DPLL.
8266          */
8267         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8268                 ret = intel_crtc_mode_set(&intel_crtc->base,
8269                                           x, y, fb);
8270                 if (ret)
8271                         goto done;
8272         }
8273
8274         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8275         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8276                 dev_priv->display.crtc_enable(&intel_crtc->base);
8277
8278         if (modeset_pipes) {
8279                 /* Store real post-adjustment hardware mode. */
8280                 crtc->hwmode = pipe_config->adjusted_mode;
8281
8282                 /* Calculate and store various constants which
8283                  * are later needed by vblank and swap-completion
8284                  * timestamping. They are derived from true hwmode.
8285                  */
8286                 drm_calc_timestamping_constants(crtc);
8287         }
8288
8289         /* FIXME: add subpixel order */
8290 done:
8291         if (ret && crtc->enabled) {
8292                 crtc->hwmode = *saved_hwmode;
8293                 crtc->mode = *saved_mode;
8294         }
8295
8296 out:
8297         kfree(pipe_config);
8298         kfree(saved_mode);
8299         return ret;
8300 }
8301
8302 int intel_set_mode(struct drm_crtc *crtc,
8303                      struct drm_display_mode *mode,
8304                      int x, int y, struct drm_framebuffer *fb)
8305 {
8306         int ret;
8307
8308         ret = __intel_set_mode(crtc, mode, x, y, fb);
8309
8310         if (ret == 0)
8311                 intel_modeset_check_state(crtc->dev);
8312
8313         return ret;
8314 }
8315
8316 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8317 {
8318         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8319 }
8320
8321 #undef for_each_intel_crtc_masked
8322
8323 static void intel_set_config_free(struct intel_set_config *config)
8324 {
8325         if (!config)
8326                 return;
8327
8328         kfree(config->save_connector_encoders);
8329         kfree(config->save_encoder_crtcs);
8330         kfree(config);
8331 }
8332
8333 static int intel_set_config_save_state(struct drm_device *dev,
8334                                        struct intel_set_config *config)
8335 {
8336         struct drm_encoder *encoder;
8337         struct drm_connector *connector;
8338         int count;
8339
8340         config->save_encoder_crtcs =
8341                 kcalloc(dev->mode_config.num_encoder,
8342                         sizeof(struct drm_crtc *), GFP_KERNEL);
8343         if (!config->save_encoder_crtcs)
8344                 return -ENOMEM;
8345
8346         config->save_connector_encoders =
8347                 kcalloc(dev->mode_config.num_connector,
8348                         sizeof(struct drm_encoder *), GFP_KERNEL);
8349         if (!config->save_connector_encoders)
8350                 return -ENOMEM;
8351
8352         /* Copy data. Note that driver private data is not affected.
8353          * Should anything bad happen only the expected state is
8354          * restored, not the drivers personal bookkeeping.
8355          */
8356         count = 0;
8357         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8358                 config->save_encoder_crtcs[count++] = encoder->crtc;
8359         }
8360
8361         count = 0;
8362         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8363                 config->save_connector_encoders[count++] = connector->encoder;
8364         }
8365
8366         return 0;
8367 }
8368
8369 static void intel_set_config_restore_state(struct drm_device *dev,
8370                                            struct intel_set_config *config)
8371 {
8372         struct intel_encoder *encoder;
8373         struct intel_connector *connector;
8374         int count;
8375
8376         count = 0;
8377         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8378                 encoder->new_crtc =
8379                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8380         }
8381
8382         count = 0;
8383         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8384                 connector->new_encoder =
8385                         to_intel_encoder(config->save_connector_encoders[count++]);
8386         }
8387 }
8388
8389 static void
8390 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8391                                       struct intel_set_config *config)
8392 {
8393
8394         /* We should be able to check here if the fb has the same properties
8395          * and then just flip_or_move it */
8396         if (set->crtc->fb != set->fb) {
8397                 /* If we have no fb then treat it as a full mode set */
8398                 if (set->crtc->fb == NULL) {
8399                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8400                         config->mode_changed = true;
8401                 } else if (set->fb == NULL) {
8402                         config->mode_changed = true;
8403                 } else if (set->fb->pixel_format !=
8404                            set->crtc->fb->pixel_format) {
8405                         config->mode_changed = true;
8406                 } else
8407                         config->fb_changed = true;
8408         }
8409
8410         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8411                 config->fb_changed = true;
8412
8413         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8414                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8415                 drm_mode_debug_printmodeline(&set->crtc->mode);
8416                 drm_mode_debug_printmodeline(set->mode);
8417                 config->mode_changed = true;
8418         }
8419 }
8420
8421 static int
8422 intel_modeset_stage_output_state(struct drm_device *dev,
8423                                  struct drm_mode_set *set,
8424                                  struct intel_set_config *config)
8425 {
8426         struct drm_crtc *new_crtc;
8427         struct intel_connector *connector;
8428         struct intel_encoder *encoder;
8429         int count, ro;
8430
8431         /* The upper layers ensure that we either disable a crtc or have a list
8432          * of connectors. For paranoia, double-check this. */
8433         WARN_ON(!set->fb && (set->num_connectors != 0));
8434         WARN_ON(set->fb && (set->num_connectors == 0));
8435
8436         count = 0;
8437         list_for_each_entry(connector, &dev->mode_config.connector_list,
8438                             base.head) {
8439                 /* Otherwise traverse passed in connector list and get encoders
8440                  * for them. */
8441                 for (ro = 0; ro < set->num_connectors; ro++) {
8442                         if (set->connectors[ro] == &connector->base) {
8443                                 connector->new_encoder = connector->encoder;
8444                                 break;
8445                         }
8446                 }
8447
8448                 /* If we disable the crtc, disable all its connectors. Also, if
8449                  * the connector is on the changing crtc but not on the new
8450                  * connector list, disable it. */
8451                 if ((!set->fb || ro == set->num_connectors) &&
8452                     connector->base.encoder &&
8453                     connector->base.encoder->crtc == set->crtc) {
8454                         connector->new_encoder = NULL;
8455
8456                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8457                                 connector->base.base.id,
8458                                 drm_get_connector_name(&connector->base));
8459                 }
8460
8461
8462                 if (&connector->new_encoder->base != connector->base.encoder) {
8463                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8464                         config->mode_changed = true;
8465                 }
8466         }
8467         /* connector->new_encoder is now updated for all connectors. */
8468
8469         /* Update crtc of enabled connectors. */
8470         count = 0;
8471         list_for_each_entry(connector, &dev->mode_config.connector_list,
8472                             base.head) {
8473                 if (!connector->new_encoder)
8474                         continue;
8475
8476                 new_crtc = connector->new_encoder->base.crtc;
8477
8478                 for (ro = 0; ro < set->num_connectors; ro++) {
8479                         if (set->connectors[ro] == &connector->base)
8480                                 new_crtc = set->crtc;
8481                 }
8482
8483                 /* Make sure the new CRTC will work with the encoder */
8484                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8485                                            new_crtc)) {
8486                         return -EINVAL;
8487                 }
8488                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8489
8490                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8491                         connector->base.base.id,
8492                         drm_get_connector_name(&connector->base),
8493                         new_crtc->base.id);
8494         }
8495
8496         /* Check for any encoders that needs to be disabled. */
8497         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8498                             base.head) {
8499                 list_for_each_entry(connector,
8500                                     &dev->mode_config.connector_list,
8501                                     base.head) {
8502                         if (connector->new_encoder == encoder) {
8503                                 WARN_ON(!connector->new_encoder->new_crtc);
8504
8505                                 goto next_encoder;
8506                         }
8507                 }
8508                 encoder->new_crtc = NULL;
8509 next_encoder:
8510                 /* Only now check for crtc changes so we don't miss encoders
8511                  * that will be disabled. */
8512                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8513                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8514                         config->mode_changed = true;
8515                 }
8516         }
8517         /* Now we've also updated encoder->new_crtc for all encoders. */
8518
8519         return 0;
8520 }
8521
8522 static int intel_crtc_set_config(struct drm_mode_set *set)
8523 {
8524         struct drm_device *dev;
8525         struct drm_mode_set save_set;
8526         struct intel_set_config *config;
8527         int ret;
8528
8529         BUG_ON(!set);
8530         BUG_ON(!set->crtc);
8531         BUG_ON(!set->crtc->helper_private);
8532
8533         /* Enforce sane interface api - has been abused by the fb helper. */
8534         BUG_ON(!set->mode && set->fb);
8535         BUG_ON(set->fb && set->num_connectors == 0);
8536
8537         if (set->fb) {
8538                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8539                                 set->crtc->base.id, set->fb->base.id,
8540                                 (int)set->num_connectors, set->x, set->y);
8541         } else {
8542                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8543         }
8544
8545         dev = set->crtc->dev;
8546
8547         ret = -ENOMEM;
8548         config = kzalloc(sizeof(*config), GFP_KERNEL);
8549         if (!config)
8550                 goto out_config;
8551
8552         ret = intel_set_config_save_state(dev, config);
8553         if (ret)
8554                 goto out_config;
8555
8556         save_set.crtc = set->crtc;
8557         save_set.mode = &set->crtc->mode;
8558         save_set.x = set->crtc->x;
8559         save_set.y = set->crtc->y;
8560         save_set.fb = set->crtc->fb;
8561
8562         /* Compute whether we need a full modeset, only an fb base update or no
8563          * change at all. In the future we might also check whether only the
8564          * mode changed, e.g. for LVDS where we only change the panel fitter in
8565          * such cases. */
8566         intel_set_config_compute_mode_changes(set, config);
8567
8568         ret = intel_modeset_stage_output_state(dev, set, config);
8569         if (ret)
8570                 goto fail;
8571
8572         if (config->mode_changed) {
8573                 if (set->mode) {
8574                         DRM_DEBUG_KMS("attempting to set mode from"
8575                                         " userspace\n");
8576                         drm_mode_debug_printmodeline(set->mode);
8577                 }
8578
8579                 ret = intel_set_mode(set->crtc, set->mode,
8580                                      set->x, set->y, set->fb);
8581                 if (ret) {
8582                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8583                                   set->crtc->base.id, ret);
8584                         goto fail;
8585                 }
8586         } else if (config->fb_changed) {
8587                 intel_crtc_wait_for_pending_flips(set->crtc);
8588
8589                 ret = intel_pipe_set_base(set->crtc,
8590                                           set->x, set->y, set->fb);
8591         }
8592
8593         intel_set_config_free(config);
8594
8595         return 0;
8596
8597 fail:
8598         intel_set_config_restore_state(dev, config);
8599
8600         /* Try to restore the config */
8601         if (config->mode_changed &&
8602             intel_set_mode(save_set.crtc, save_set.mode,
8603                            save_set.x, save_set.y, save_set.fb))
8604                 DRM_ERROR("failed to restore config after modeset failure\n");
8605
8606 out_config:
8607         intel_set_config_free(config);
8608         return ret;
8609 }
8610
8611 static const struct drm_crtc_funcs intel_crtc_funcs = {
8612         .cursor_set = intel_crtc_cursor_set,
8613         .cursor_move = intel_crtc_cursor_move,
8614         .gamma_set = intel_crtc_gamma_set,
8615         .set_config = intel_crtc_set_config,
8616         .destroy = intel_crtc_destroy,
8617         .page_flip = intel_crtc_page_flip,
8618 };
8619
8620 static void intel_cpu_pll_init(struct drm_device *dev)
8621 {
8622         if (HAS_DDI(dev))
8623                 intel_ddi_pll_init(dev);
8624 }
8625
8626 static void intel_pch_pll_init(struct drm_device *dev)
8627 {
8628         drm_i915_private_t *dev_priv = dev->dev_private;
8629         int i;
8630
8631         if (dev_priv->num_pch_pll == 0) {
8632                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8633                 return;
8634         }
8635
8636         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8637                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8638                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8639                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8640         }
8641 }
8642
8643 static void intel_crtc_init(struct drm_device *dev, int pipe)
8644 {
8645         drm_i915_private_t *dev_priv = dev->dev_private;
8646         struct intel_crtc *intel_crtc;
8647         int i;
8648
8649         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8650         if (intel_crtc == NULL)
8651                 return;
8652
8653         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8654
8655         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8656         for (i = 0; i < 256; i++) {
8657                 intel_crtc->lut_r[i] = i;
8658                 intel_crtc->lut_g[i] = i;
8659                 intel_crtc->lut_b[i] = i;
8660         }
8661
8662         /* Swap pipes & planes for FBC on pre-965 */
8663         intel_crtc->pipe = pipe;
8664         intel_crtc->plane = pipe;
8665         intel_crtc->config.cpu_transcoder = pipe;
8666         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8667                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8668                 intel_crtc->plane = !pipe;
8669         }
8670
8671         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8672                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8673         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8674         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8675
8676         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8677 }
8678
8679 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8680                                 struct drm_file *file)
8681 {
8682         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8683         struct drm_mode_object *drmmode_obj;
8684         struct intel_crtc *crtc;
8685
8686         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8687                 return -ENODEV;
8688
8689         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8690                         DRM_MODE_OBJECT_CRTC);
8691
8692         if (!drmmode_obj) {
8693                 DRM_ERROR("no such CRTC id\n");
8694                 return -EINVAL;
8695         }
8696
8697         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8698         pipe_from_crtc_id->pipe = crtc->pipe;
8699
8700         return 0;
8701 }
8702
8703 static int intel_encoder_clones(struct intel_encoder *encoder)
8704 {
8705         struct drm_device *dev = encoder->base.dev;
8706         struct intel_encoder *source_encoder;
8707         int index_mask = 0;
8708         int entry = 0;
8709
8710         list_for_each_entry(source_encoder,
8711                             &dev->mode_config.encoder_list, base.head) {
8712
8713                 if (encoder == source_encoder)
8714                         index_mask |= (1 << entry);
8715
8716                 /* Intel hw has only one MUX where enocoders could be cloned. */
8717                 if (encoder->cloneable && source_encoder->cloneable)
8718                         index_mask |= (1 << entry);
8719
8720                 entry++;
8721         }
8722
8723         return index_mask;
8724 }
8725
8726 static bool has_edp_a(struct drm_device *dev)
8727 {
8728         struct drm_i915_private *dev_priv = dev->dev_private;
8729
8730         if (!IS_MOBILE(dev))
8731                 return false;
8732
8733         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8734                 return false;
8735
8736         if (IS_GEN5(dev) &&
8737             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8738                 return false;
8739
8740         return true;
8741 }
8742
8743 static void intel_setup_outputs(struct drm_device *dev)
8744 {
8745         struct drm_i915_private *dev_priv = dev->dev_private;
8746         struct intel_encoder *encoder;
8747         bool dpd_is_edp = false;
8748         bool has_lvds;
8749
8750         has_lvds = intel_lvds_init(dev);
8751         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8752                 /* disable the panel fitter on everything but LVDS */
8753                 I915_WRITE(PFIT_CONTROL, 0);
8754         }
8755
8756         if (!IS_ULT(dev))
8757                 intel_crt_init(dev);
8758
8759         if (HAS_DDI(dev)) {
8760                 int found;
8761
8762                 /* Haswell uses DDI functions to detect digital outputs */
8763                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8764                 /* DDI A only supports eDP */
8765                 if (found)
8766                         intel_ddi_init(dev, PORT_A);
8767
8768                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8769                  * register */
8770                 found = I915_READ(SFUSE_STRAP);
8771
8772                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8773                         intel_ddi_init(dev, PORT_B);
8774                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8775                         intel_ddi_init(dev, PORT_C);
8776                 if (found & SFUSE_STRAP_DDID_DETECTED)
8777                         intel_ddi_init(dev, PORT_D);
8778         } else if (HAS_PCH_SPLIT(dev)) {
8779                 int found;
8780                 dpd_is_edp = intel_dpd_is_edp(dev);
8781
8782                 if (has_edp_a(dev))
8783                         intel_dp_init(dev, DP_A, PORT_A);
8784
8785                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8786                         /* PCH SDVOB multiplex with HDMIB */
8787                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8788                         if (!found)
8789                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8790                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8791                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8792                 }
8793
8794                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8795                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8796
8797                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8798                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8799
8800                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8801                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8802
8803                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8804                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8805         } else if (IS_VALLEYVIEW(dev)) {
8806                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8807                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8808                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8809
8810                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8811                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8812                                         PORT_B);
8813                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8814                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8815                 }
8816         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8817                 bool found = false;
8818
8819                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8820                         DRM_DEBUG_KMS("probing SDVOB\n");
8821                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8822                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8823                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8824                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8825                         }
8826
8827                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8828                                 DRM_DEBUG_KMS("probing DP_B\n");
8829                                 intel_dp_init(dev, DP_B, PORT_B);
8830                         }
8831                 }
8832
8833                 /* Before G4X SDVOC doesn't have its own detect register */
8834
8835                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8836                         DRM_DEBUG_KMS("probing SDVOC\n");
8837                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8838                 }
8839
8840                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8841
8842                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8843                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8844                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8845                         }
8846                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8847                                 DRM_DEBUG_KMS("probing DP_C\n");
8848                                 intel_dp_init(dev, DP_C, PORT_C);
8849                         }
8850                 }
8851
8852                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8853                     (I915_READ(DP_D) & DP_DETECTED)) {
8854                         DRM_DEBUG_KMS("probing DP_D\n");
8855                         intel_dp_init(dev, DP_D, PORT_D);
8856                 }
8857         } else if (IS_GEN2(dev))
8858                 intel_dvo_init(dev);
8859
8860         if (SUPPORTS_TV(dev))
8861                 intel_tv_init(dev);
8862
8863         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8864                 encoder->base.possible_crtcs = encoder->crtc_mask;
8865                 encoder->base.possible_clones =
8866                         intel_encoder_clones(encoder);
8867         }
8868
8869         intel_init_pch_refclk(dev);
8870
8871         drm_helper_move_panel_connectors_to_head(dev);
8872 }
8873
8874 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8875 {
8876         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8877
8878         drm_framebuffer_cleanup(fb);
8879         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8880
8881         kfree(intel_fb);
8882 }
8883
8884 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8885                                                 struct drm_file *file,
8886                                                 unsigned int *handle)
8887 {
8888         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8889         struct drm_i915_gem_object *obj = intel_fb->obj;
8890
8891         return drm_gem_handle_create(file, &obj->base, handle);
8892 }
8893
8894 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8895         .destroy = intel_user_framebuffer_destroy,
8896         .create_handle = intel_user_framebuffer_create_handle,
8897 };
8898
8899 int intel_framebuffer_init(struct drm_device *dev,
8900                            struct intel_framebuffer *intel_fb,
8901                            struct drm_mode_fb_cmd2 *mode_cmd,
8902                            struct drm_i915_gem_object *obj)
8903 {
8904         int ret;
8905
8906         if (obj->tiling_mode == I915_TILING_Y) {
8907                 DRM_DEBUG("hardware does not support tiling Y\n");
8908                 return -EINVAL;
8909         }
8910
8911         if (mode_cmd->pitches[0] & 63) {
8912                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8913                           mode_cmd->pitches[0]);
8914                 return -EINVAL;
8915         }
8916
8917         /* FIXME <= Gen4 stride limits are bit unclear */
8918         if (mode_cmd->pitches[0] > 32768) {
8919                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8920                           mode_cmd->pitches[0]);
8921                 return -EINVAL;
8922         }
8923
8924         if (obj->tiling_mode != I915_TILING_NONE &&
8925             mode_cmd->pitches[0] != obj->stride) {
8926                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8927                           mode_cmd->pitches[0], obj->stride);
8928                 return -EINVAL;
8929         }
8930
8931         /* Reject formats not supported by any plane early. */
8932         switch (mode_cmd->pixel_format) {
8933         case DRM_FORMAT_C8:
8934         case DRM_FORMAT_RGB565:
8935         case DRM_FORMAT_XRGB8888:
8936         case DRM_FORMAT_ARGB8888:
8937                 break;
8938         case DRM_FORMAT_XRGB1555:
8939         case DRM_FORMAT_ARGB1555:
8940                 if (INTEL_INFO(dev)->gen > 3) {
8941                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8942                         return -EINVAL;
8943                 }
8944                 break;
8945         case DRM_FORMAT_XBGR8888:
8946         case DRM_FORMAT_ABGR8888:
8947         case DRM_FORMAT_XRGB2101010:
8948         case DRM_FORMAT_ARGB2101010:
8949         case DRM_FORMAT_XBGR2101010:
8950         case DRM_FORMAT_ABGR2101010:
8951                 if (INTEL_INFO(dev)->gen < 4) {
8952                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8953                         return -EINVAL;
8954                 }
8955                 break;
8956         case DRM_FORMAT_YUYV:
8957         case DRM_FORMAT_UYVY:
8958         case DRM_FORMAT_YVYU:
8959         case DRM_FORMAT_VYUY:
8960                 if (INTEL_INFO(dev)->gen < 5) {
8961                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8962                         return -EINVAL;
8963                 }
8964                 break;
8965         default:
8966                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8967                 return -EINVAL;
8968         }
8969
8970         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8971         if (mode_cmd->offsets[0] != 0)
8972                 return -EINVAL;
8973
8974         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8975         intel_fb->obj = obj;
8976
8977         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8978         if (ret) {
8979                 DRM_ERROR("framebuffer init failed %d\n", ret);
8980                 return ret;
8981         }
8982
8983         return 0;
8984 }
8985
8986 static struct drm_framebuffer *
8987 intel_user_framebuffer_create(struct drm_device *dev,
8988                               struct drm_file *filp,
8989                               struct drm_mode_fb_cmd2 *mode_cmd)
8990 {
8991         struct drm_i915_gem_object *obj;
8992
8993         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8994                                                 mode_cmd->handles[0]));
8995         if (&obj->base == NULL)
8996                 return ERR_PTR(-ENOENT);
8997
8998         return intel_framebuffer_create(dev, mode_cmd, obj);
8999 }
9000
9001 static const struct drm_mode_config_funcs intel_mode_funcs = {
9002         .fb_create = intel_user_framebuffer_create,
9003         .output_poll_changed = intel_fb_output_poll_changed,
9004 };
9005
9006 /* Set up chip specific display functions */
9007 static void intel_init_display(struct drm_device *dev)
9008 {
9009         struct drm_i915_private *dev_priv = dev->dev_private;
9010
9011         if (HAS_DDI(dev)) {
9012                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9013                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9014                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9015                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9016                 dev_priv->display.off = haswell_crtc_off;
9017                 dev_priv->display.update_plane = ironlake_update_plane;
9018         } else if (HAS_PCH_SPLIT(dev)) {
9019                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9020                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9021                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9022                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9023                 dev_priv->display.off = ironlake_crtc_off;
9024                 dev_priv->display.update_plane = ironlake_update_plane;
9025         } else if (IS_VALLEYVIEW(dev)) {
9026                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9027                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9028                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9029                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9030                 dev_priv->display.off = i9xx_crtc_off;
9031                 dev_priv->display.update_plane = i9xx_update_plane;
9032         } else {
9033                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9034                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9035                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9036                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9037                 dev_priv->display.off = i9xx_crtc_off;
9038                 dev_priv->display.update_plane = i9xx_update_plane;
9039         }
9040
9041         /* Returns the core display clock speed */
9042         if (IS_VALLEYVIEW(dev))
9043                 dev_priv->display.get_display_clock_speed =
9044                         valleyview_get_display_clock_speed;
9045         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9046                 dev_priv->display.get_display_clock_speed =
9047                         i945_get_display_clock_speed;
9048         else if (IS_I915G(dev))
9049                 dev_priv->display.get_display_clock_speed =
9050                         i915_get_display_clock_speed;
9051         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9052                 dev_priv->display.get_display_clock_speed =
9053                         i9xx_misc_get_display_clock_speed;
9054         else if (IS_I915GM(dev))
9055                 dev_priv->display.get_display_clock_speed =
9056                         i915gm_get_display_clock_speed;
9057         else if (IS_I865G(dev))
9058                 dev_priv->display.get_display_clock_speed =
9059                         i865_get_display_clock_speed;
9060         else if (IS_I85X(dev))
9061                 dev_priv->display.get_display_clock_speed =
9062                         i855_get_display_clock_speed;
9063         else /* 852, 830 */
9064                 dev_priv->display.get_display_clock_speed =
9065                         i830_get_display_clock_speed;
9066
9067         if (HAS_PCH_SPLIT(dev)) {
9068                 if (IS_GEN5(dev)) {
9069                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9070                         dev_priv->display.write_eld = ironlake_write_eld;
9071                 } else if (IS_GEN6(dev)) {
9072                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9073                         dev_priv->display.write_eld = ironlake_write_eld;
9074                 } else if (IS_IVYBRIDGE(dev)) {
9075                         /* FIXME: detect B0+ stepping and use auto training */
9076                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9077                         dev_priv->display.write_eld = ironlake_write_eld;
9078                         dev_priv->display.modeset_global_resources =
9079                                 ivb_modeset_global_resources;
9080                 } else if (IS_HASWELL(dev)) {
9081                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9082                         dev_priv->display.write_eld = haswell_write_eld;
9083                         dev_priv->display.modeset_global_resources =
9084                                 haswell_modeset_global_resources;
9085                 }
9086         } else if (IS_G4X(dev)) {
9087                 dev_priv->display.write_eld = g4x_write_eld;
9088         }
9089
9090         /* Default just returns -ENODEV to indicate unsupported */
9091         dev_priv->display.queue_flip = intel_default_queue_flip;
9092
9093         switch (INTEL_INFO(dev)->gen) {
9094         case 2:
9095                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9096                 break;
9097
9098         case 3:
9099                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9100                 break;
9101
9102         case 4:
9103         case 5:
9104                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9105                 break;
9106
9107         case 6:
9108                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9109                 break;
9110         case 7:
9111                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9112                 break;
9113         }
9114 }
9115
9116 /*
9117  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9118  * resume, or other times.  This quirk makes sure that's the case for
9119  * affected systems.
9120  */
9121 static void quirk_pipea_force(struct drm_device *dev)
9122 {
9123         struct drm_i915_private *dev_priv = dev->dev_private;
9124
9125         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9126         DRM_INFO("applying pipe a force quirk\n");
9127 }
9128
9129 /*
9130  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9131  */
9132 static void quirk_ssc_force_disable(struct drm_device *dev)
9133 {
9134         struct drm_i915_private *dev_priv = dev->dev_private;
9135         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9136         DRM_INFO("applying lvds SSC disable quirk\n");
9137 }
9138
9139 /*
9140  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9141  * brightness value
9142  */
9143 static void quirk_invert_brightness(struct drm_device *dev)
9144 {
9145         struct drm_i915_private *dev_priv = dev->dev_private;
9146         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9147         DRM_INFO("applying inverted panel brightness quirk\n");
9148 }
9149
9150 struct intel_quirk {
9151         int device;
9152         int subsystem_vendor;
9153         int subsystem_device;
9154         void (*hook)(struct drm_device *dev);
9155 };
9156
9157 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9158 struct intel_dmi_quirk {
9159         void (*hook)(struct drm_device *dev);
9160         const struct dmi_system_id (*dmi_id_list)[];
9161 };
9162
9163 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9164 {
9165         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9166         return 1;
9167 }
9168
9169 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9170         {
9171                 .dmi_id_list = &(const struct dmi_system_id[]) {
9172                         {
9173                                 .callback = intel_dmi_reverse_brightness,
9174                                 .ident = "NCR Corporation",
9175                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9176                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9177                                 },
9178                         },
9179                         { }  /* terminating entry */
9180                 },
9181                 .hook = quirk_invert_brightness,
9182         },
9183 };
9184
9185 static struct intel_quirk intel_quirks[] = {
9186         /* HP Mini needs pipe A force quirk (LP: #322104) */
9187         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9188
9189         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9190         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9191
9192         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9193         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9194
9195         /* 830/845 need to leave pipe A & dpll A up */
9196         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9197         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9198
9199         /* Lenovo U160 cannot use SSC on LVDS */
9200         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9201
9202         /* Sony Vaio Y cannot use SSC on LVDS */
9203         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9204
9205         /* Acer Aspire 5734Z must invert backlight brightness */
9206         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9207
9208         /* Acer/eMachines G725 */
9209         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9210
9211         /* Acer/eMachines e725 */
9212         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9213
9214         /* Acer/Packard Bell NCL20 */
9215         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9216
9217         /* Acer Aspire 4736Z */
9218         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9219 };
9220
9221 static void intel_init_quirks(struct drm_device *dev)
9222 {
9223         struct pci_dev *d = dev->pdev;
9224         int i;
9225
9226         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9227                 struct intel_quirk *q = &intel_quirks[i];
9228
9229                 if (d->device == q->device &&
9230                     (d->subsystem_vendor == q->subsystem_vendor ||
9231                      q->subsystem_vendor == PCI_ANY_ID) &&
9232                     (d->subsystem_device == q->subsystem_device ||
9233                      q->subsystem_device == PCI_ANY_ID))
9234                         q->hook(dev);
9235         }
9236         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9237                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9238                         intel_dmi_quirks[i].hook(dev);
9239         }
9240 }
9241
9242 /* Disable the VGA plane that we never use */
9243 static void i915_disable_vga(struct drm_device *dev)
9244 {
9245         struct drm_i915_private *dev_priv = dev->dev_private;
9246         u8 sr1;
9247         u32 vga_reg = i915_vgacntrl_reg(dev);
9248
9249         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9250         outb(SR01, VGA_SR_INDEX);
9251         sr1 = inb(VGA_SR_DATA);
9252         outb(sr1 | 1<<5, VGA_SR_DATA);
9253         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9254         udelay(300);
9255
9256         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9257         POSTING_READ(vga_reg);
9258 }
9259
9260 void intel_modeset_init_hw(struct drm_device *dev)
9261 {
9262         intel_init_power_well(dev);
9263
9264         intel_prepare_ddi(dev);
9265
9266         intel_init_clock_gating(dev);
9267
9268         mutex_lock(&dev->struct_mutex);
9269         intel_enable_gt_powersave(dev);
9270         mutex_unlock(&dev->struct_mutex);
9271 }
9272
9273 void intel_modeset_init(struct drm_device *dev)
9274 {
9275         struct drm_i915_private *dev_priv = dev->dev_private;
9276         int i, j, ret;
9277
9278         drm_mode_config_init(dev);
9279
9280         dev->mode_config.min_width = 0;
9281         dev->mode_config.min_height = 0;
9282
9283         dev->mode_config.preferred_depth = 24;
9284         dev->mode_config.prefer_shadow = 1;
9285
9286         dev->mode_config.funcs = &intel_mode_funcs;
9287
9288         intel_init_quirks(dev);
9289
9290         intel_init_pm(dev);
9291
9292         if (INTEL_INFO(dev)->num_pipes == 0)
9293                 return;
9294
9295         intel_init_display(dev);
9296
9297         if (IS_GEN2(dev)) {
9298                 dev->mode_config.max_width = 2048;
9299                 dev->mode_config.max_height = 2048;
9300         } else if (IS_GEN3(dev)) {
9301                 dev->mode_config.max_width = 4096;
9302                 dev->mode_config.max_height = 4096;
9303         } else {
9304                 dev->mode_config.max_width = 8192;
9305                 dev->mode_config.max_height = 8192;
9306         }
9307         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9308
9309         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9310                       INTEL_INFO(dev)->num_pipes,
9311                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9312
9313         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9314                 intel_crtc_init(dev, i);
9315                 for (j = 0; j < dev_priv->num_plane; j++) {
9316                         ret = intel_plane_init(dev, i, j);
9317                         if (ret)
9318                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9319                                               pipe_name(i), sprite_name(i, j), ret);
9320                 }
9321         }
9322
9323         intel_cpu_pll_init(dev);
9324         intel_pch_pll_init(dev);
9325
9326         /* Just disable it once at startup */
9327         i915_disable_vga(dev);
9328         intel_setup_outputs(dev);
9329
9330         /* Just in case the BIOS is doing something questionable. */
9331         intel_disable_fbc(dev);
9332 }
9333
9334 static void
9335 intel_connector_break_all_links(struct intel_connector *connector)
9336 {
9337         connector->base.dpms = DRM_MODE_DPMS_OFF;
9338         connector->base.encoder = NULL;
9339         connector->encoder->connectors_active = false;
9340         connector->encoder->base.crtc = NULL;
9341 }
9342
9343 static void intel_enable_pipe_a(struct drm_device *dev)
9344 {
9345         struct intel_connector *connector;
9346         struct drm_connector *crt = NULL;
9347         struct intel_load_detect_pipe load_detect_temp;
9348
9349         /* We can't just switch on the pipe A, we need to set things up with a
9350          * proper mode and output configuration. As a gross hack, enable pipe A
9351          * by enabling the load detect pipe once. */
9352         list_for_each_entry(connector,
9353                             &dev->mode_config.connector_list,
9354                             base.head) {
9355                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9356                         crt = &connector->base;
9357                         break;
9358                 }
9359         }
9360
9361         if (!crt)
9362                 return;
9363
9364         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9365                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9366
9367
9368 }
9369
9370 static bool
9371 intel_check_plane_mapping(struct intel_crtc *crtc)
9372 {
9373         struct drm_device *dev = crtc->base.dev;
9374         struct drm_i915_private *dev_priv = dev->dev_private;
9375         u32 reg, val;
9376
9377         if (INTEL_INFO(dev)->num_pipes == 1)
9378                 return true;
9379
9380         reg = DSPCNTR(!crtc->plane);
9381         val = I915_READ(reg);
9382
9383         if ((val & DISPLAY_PLANE_ENABLE) &&
9384             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9385                 return false;
9386
9387         return true;
9388 }
9389
9390 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9391 {
9392         struct drm_device *dev = crtc->base.dev;
9393         struct drm_i915_private *dev_priv = dev->dev_private;
9394         u32 reg;
9395
9396         /* Clear any frame start delays used for debugging left by the BIOS */
9397         reg = PIPECONF(crtc->config.cpu_transcoder);
9398         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9399
9400         /* We need to sanitize the plane -> pipe mapping first because this will
9401          * disable the crtc (and hence change the state) if it is wrong. Note
9402          * that gen4+ has a fixed plane -> pipe mapping.  */
9403         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9404                 struct intel_connector *connector;
9405                 bool plane;
9406
9407                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9408                               crtc->base.base.id);
9409
9410                 /* Pipe has the wrong plane attached and the plane is active.
9411                  * Temporarily change the plane mapping and disable everything
9412                  * ...  */
9413                 plane = crtc->plane;
9414                 crtc->plane = !plane;
9415                 dev_priv->display.crtc_disable(&crtc->base);
9416                 crtc->plane = plane;
9417
9418                 /* ... and break all links. */
9419                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9420                                     base.head) {
9421                         if (connector->encoder->base.crtc != &crtc->base)
9422                                 continue;
9423
9424                         intel_connector_break_all_links(connector);
9425                 }
9426
9427                 WARN_ON(crtc->active);
9428                 crtc->base.enabled = false;
9429         }
9430
9431         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9432             crtc->pipe == PIPE_A && !crtc->active) {
9433                 /* BIOS forgot to enable pipe A, this mostly happens after
9434                  * resume. Force-enable the pipe to fix this, the update_dpms
9435                  * call below we restore the pipe to the right state, but leave
9436                  * the required bits on. */
9437                 intel_enable_pipe_a(dev);
9438         }
9439
9440         /* Adjust the state of the output pipe according to whether we
9441          * have active connectors/encoders. */
9442         intel_crtc_update_dpms(&crtc->base);
9443
9444         if (crtc->active != crtc->base.enabled) {
9445                 struct intel_encoder *encoder;
9446
9447                 /* This can happen either due to bugs in the get_hw_state
9448                  * functions or because the pipe is force-enabled due to the
9449                  * pipe A quirk. */
9450                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9451                               crtc->base.base.id,
9452                               crtc->base.enabled ? "enabled" : "disabled",
9453                               crtc->active ? "enabled" : "disabled");
9454
9455                 crtc->base.enabled = crtc->active;
9456
9457                 /* Because we only establish the connector -> encoder ->
9458                  * crtc links if something is active, this means the
9459                  * crtc is now deactivated. Break the links. connector
9460                  * -> encoder links are only establish when things are
9461                  *  actually up, hence no need to break them. */
9462                 WARN_ON(crtc->active);
9463
9464                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9465                         WARN_ON(encoder->connectors_active);
9466                         encoder->base.crtc = NULL;
9467                 }
9468         }
9469 }
9470
9471 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9472 {
9473         struct intel_connector *connector;
9474         struct drm_device *dev = encoder->base.dev;
9475
9476         /* We need to check both for a crtc link (meaning that the
9477          * encoder is active and trying to read from a pipe) and the
9478          * pipe itself being active. */
9479         bool has_active_crtc = encoder->base.crtc &&
9480                 to_intel_crtc(encoder->base.crtc)->active;
9481
9482         if (encoder->connectors_active && !has_active_crtc) {
9483                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9484                               encoder->base.base.id,
9485                               drm_get_encoder_name(&encoder->base));
9486
9487                 /* Connector is active, but has no active pipe. This is
9488                  * fallout from our resume register restoring. Disable
9489                  * the encoder manually again. */
9490                 if (encoder->base.crtc) {
9491                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9492                                       encoder->base.base.id,
9493                                       drm_get_encoder_name(&encoder->base));
9494                         encoder->disable(encoder);
9495                 }
9496
9497                 /* Inconsistent output/port/pipe state happens presumably due to
9498                  * a bug in one of the get_hw_state functions. Or someplace else
9499                  * in our code, like the register restore mess on resume. Clamp
9500                  * things to off as a safer default. */
9501                 list_for_each_entry(connector,
9502                                     &dev->mode_config.connector_list,
9503                                     base.head) {
9504                         if (connector->encoder != encoder)
9505                                 continue;
9506
9507                         intel_connector_break_all_links(connector);
9508                 }
9509         }
9510         /* Enabled encoders without active connectors will be fixed in
9511          * the crtc fixup. */
9512 }
9513
9514 void i915_redisable_vga(struct drm_device *dev)
9515 {
9516         struct drm_i915_private *dev_priv = dev->dev_private;
9517         u32 vga_reg = i915_vgacntrl_reg(dev);
9518
9519         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9520                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9521                 i915_disable_vga(dev);
9522         }
9523 }
9524
9525 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9526  * and i915 state tracking structures. */
9527 void intel_modeset_setup_hw_state(struct drm_device *dev,
9528                                   bool force_restore)
9529 {
9530         struct drm_i915_private *dev_priv = dev->dev_private;
9531         enum pipe pipe;
9532         u32 tmp;
9533         struct drm_plane *plane;
9534         struct intel_crtc *crtc;
9535         struct intel_encoder *encoder;
9536         struct intel_connector *connector;
9537
9538         if (HAS_DDI(dev)) {
9539                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9540
9541                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9542                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9543                         case TRANS_DDI_EDP_INPUT_A_ON:
9544                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9545                                 pipe = PIPE_A;
9546                                 break;
9547                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9548                                 pipe = PIPE_B;
9549                                 break;
9550                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9551                                 pipe = PIPE_C;
9552                                 break;
9553                         default:
9554                                 /* A bogus value has been programmed, disable
9555                                  * the transcoder */
9556                                 WARN(1, "Bogus eDP source %08x\n", tmp);
9557                                 intel_ddi_disable_transcoder_func(dev_priv,
9558                                                 TRANSCODER_EDP);
9559                                 goto setup_pipes;
9560                         }
9561
9562                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9563                         crtc->config.cpu_transcoder = TRANSCODER_EDP;
9564
9565                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9566                                       pipe_name(pipe));
9567                 }
9568         }
9569
9570 setup_pipes:
9571         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9572                             base.head) {
9573                 enum transcoder tmp = crtc->config.cpu_transcoder;
9574                 memset(&crtc->config, 0, sizeof(crtc->config));
9575                 crtc->config.cpu_transcoder = tmp;
9576
9577                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9578                                                                  &crtc->config);
9579
9580                 crtc->base.enabled = crtc->active;
9581
9582                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9583                               crtc->base.base.id,
9584                               crtc->active ? "enabled" : "disabled");
9585         }
9586
9587         if (HAS_DDI(dev))
9588                 intel_ddi_setup_hw_pll_state(dev);
9589
9590         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9591                             base.head) {
9592                 pipe = 0;
9593
9594                 if (encoder->get_hw_state(encoder, &pipe)) {
9595                         encoder->base.crtc =
9596                                 dev_priv->pipe_to_crtc_mapping[pipe];
9597                 } else {
9598                         encoder->base.crtc = NULL;
9599                 }
9600
9601                 encoder->connectors_active = false;
9602                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9603                               encoder->base.base.id,
9604                               drm_get_encoder_name(&encoder->base),
9605                               encoder->base.crtc ? "enabled" : "disabled",
9606                               pipe);
9607         }
9608
9609         list_for_each_entry(connector, &dev->mode_config.connector_list,
9610                             base.head) {
9611                 if (connector->get_hw_state(connector)) {
9612                         connector->base.dpms = DRM_MODE_DPMS_ON;
9613                         connector->encoder->connectors_active = true;
9614                         connector->base.encoder = &connector->encoder->base;
9615                 } else {
9616                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9617                         connector->base.encoder = NULL;
9618                 }
9619                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9620                               connector->base.base.id,
9621                               drm_get_connector_name(&connector->base),
9622                               connector->base.encoder ? "enabled" : "disabled");
9623         }
9624
9625         /* HW state is read out, now we need to sanitize this mess. */
9626         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9627                             base.head) {
9628                 intel_sanitize_encoder(encoder);
9629         }
9630
9631         for_each_pipe(pipe) {
9632                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9633                 intel_sanitize_crtc(crtc);
9634         }
9635
9636         if (force_restore) {
9637                 /*
9638                  * We need to use raw interfaces for restoring state to avoid
9639                  * checking (bogus) intermediate states.
9640                  */
9641                 for_each_pipe(pipe) {
9642                         struct drm_crtc *crtc =
9643                                 dev_priv->pipe_to_crtc_mapping[pipe];
9644
9645                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9646                                          crtc->fb);
9647                 }
9648                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9649                         intel_plane_restore(plane);
9650
9651                 i915_redisable_vga(dev);
9652         } else {
9653                 intel_modeset_update_staged_output_state(dev);
9654         }
9655
9656         intel_modeset_check_state(dev);
9657
9658         drm_mode_config_reset(dev);
9659 }
9660
9661 void intel_modeset_gem_init(struct drm_device *dev)
9662 {
9663         intel_modeset_init_hw(dev);
9664
9665         intel_setup_overlay(dev);
9666
9667         intel_modeset_setup_hw_state(dev, false);
9668 }
9669
9670 void intel_modeset_cleanup(struct drm_device *dev)
9671 {
9672         struct drm_i915_private *dev_priv = dev->dev_private;
9673         struct drm_crtc *crtc;
9674         struct intel_crtc *intel_crtc;
9675
9676         /*
9677          * Interrupts and polling as the first thing to avoid creating havoc.
9678          * Too much stuff here (turning of rps, connectors, ...) would
9679          * experience fancy races otherwise.
9680          */
9681         drm_irq_uninstall(dev);
9682         cancel_work_sync(&dev_priv->hotplug_work);
9683         /*
9684          * Due to the hpd irq storm handling the hotplug work can re-arm the
9685          * poll handlers. Hence disable polling after hpd handling is shut down.
9686          */
9687         drm_kms_helper_poll_fini(dev);
9688
9689         mutex_lock(&dev->struct_mutex);
9690
9691         intel_unregister_dsm_handler();
9692
9693         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9694                 /* Skip inactive CRTCs */
9695                 if (!crtc->fb)
9696                         continue;
9697
9698                 intel_crtc = to_intel_crtc(crtc);
9699                 intel_increase_pllclock(crtc);
9700         }
9701
9702         intel_disable_fbc(dev);
9703
9704         intel_disable_gt_powersave(dev);
9705
9706         ironlake_teardown_rc6(dev);
9707
9708         mutex_unlock(&dev->struct_mutex);
9709
9710         /* flush any delayed tasks or pending work */
9711         flush_scheduled_work();
9712
9713         /* destroy backlight, if any, before the connectors */
9714         intel_panel_destroy_backlight(dev);
9715
9716         drm_mode_config_cleanup(dev);
9717
9718         intel_cleanup_overlay(dev);
9719 }
9720
9721 /*
9722  * Return which encoder is currently attached for connector.
9723  */
9724 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9725 {
9726         return &intel_attached_encoder(connector)->base;
9727 }
9728
9729 void intel_connector_attach_encoder(struct intel_connector *connector,
9730                                     struct intel_encoder *encoder)
9731 {
9732         connector->encoder = encoder;
9733         drm_mode_connector_attach_encoder(&connector->base,
9734                                           &encoder->base);
9735 }
9736
9737 /*
9738  * set vga decode state - true == enable VGA decode
9739  */
9740 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9741 {
9742         struct drm_i915_private *dev_priv = dev->dev_private;
9743         u16 gmch_ctrl;
9744
9745         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9746         if (state)
9747                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9748         else
9749                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9750         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9751         return 0;
9752 }
9753
9754 #ifdef CONFIG_DEBUG_FS
9755 #include <linux/seq_file.h>
9756
9757 struct intel_display_error_state {
9758         struct intel_cursor_error_state {
9759                 u32 control;
9760                 u32 position;
9761                 u32 base;
9762                 u32 size;
9763         } cursor[I915_MAX_PIPES];
9764
9765         struct intel_pipe_error_state {
9766                 u32 conf;
9767                 u32 source;
9768
9769                 u32 htotal;
9770                 u32 hblank;
9771                 u32 hsync;
9772                 u32 vtotal;
9773                 u32 vblank;
9774                 u32 vsync;
9775         } pipe[I915_MAX_PIPES];
9776
9777         struct intel_plane_error_state {
9778                 u32 control;
9779                 u32 stride;
9780                 u32 size;
9781                 u32 pos;
9782                 u32 addr;
9783                 u32 surface;
9784                 u32 tile_offset;
9785         } plane[I915_MAX_PIPES];
9786 };
9787
9788 struct intel_display_error_state *
9789 intel_display_capture_error_state(struct drm_device *dev)
9790 {
9791         drm_i915_private_t *dev_priv = dev->dev_private;
9792         struct intel_display_error_state *error;
9793         enum transcoder cpu_transcoder;
9794         int i;
9795
9796         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9797         if (error == NULL)
9798                 return NULL;
9799
9800         for_each_pipe(i) {
9801                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9802
9803                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9804                         error->cursor[i].control = I915_READ(CURCNTR(i));
9805                         error->cursor[i].position = I915_READ(CURPOS(i));
9806                         error->cursor[i].base = I915_READ(CURBASE(i));
9807                 } else {
9808                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9809                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9810                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9811                 }
9812
9813                 error->plane[i].control = I915_READ(DSPCNTR(i));
9814                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9815                 if (INTEL_INFO(dev)->gen <= 3) {
9816                         error->plane[i].size = I915_READ(DSPSIZE(i));
9817                         error->plane[i].pos = I915_READ(DSPPOS(i));
9818                 }
9819                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9820                         error->plane[i].addr = I915_READ(DSPADDR(i));
9821                 if (INTEL_INFO(dev)->gen >= 4) {
9822                         error->plane[i].surface = I915_READ(DSPSURF(i));
9823                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9824                 }
9825
9826                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9827                 error->pipe[i].source = I915_READ(PIPESRC(i));
9828                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9829                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9830                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9831                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9832                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9833                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9834         }
9835
9836         return error;
9837 }
9838
9839 void
9840 intel_display_print_error_state(struct seq_file *m,
9841                                 struct drm_device *dev,
9842                                 struct intel_display_error_state *error)
9843 {
9844         int i;
9845
9846         seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9847         for_each_pipe(i) {
9848                 seq_printf(m, "Pipe [%d]:\n", i);
9849                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9850                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9851                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9852                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9853                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9854                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9855                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9856                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9857
9858                 seq_printf(m, "Plane [%d]:\n", i);
9859                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9860                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9861                 if (INTEL_INFO(dev)->gen <= 3) {
9862                         seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9863                         seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9864                 }
9865                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9866                         seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9867                 if (INTEL_INFO(dev)->gen >= 4) {
9868                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9869                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9870                 }
9871
9872                 seq_printf(m, "Cursor [%d]:\n", i);
9873                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9874                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9875                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9876         }
9877 }
9878 #endif