2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
101 static inline u32 /* units of 100MHz */
102 intel_fdi_link_freq(struct drm_device *dev)
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
111 static const intel_limit_t intel_limits_i8xx_dvo = {
112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
122 .find_pll = intel_find_best_PLL,
125 static const intel_limit_t intel_limits_i8xx_lvds = {
126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
136 .find_pll = intel_find_best_PLL,
139 static const intel_limit_t intel_limits_i9xx_sdvo = {
140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
150 .find_pll = intel_find_best_PLL,
153 static const intel_limit_t intel_limits_i9xx_lvds = {
154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
164 .find_pll = intel_find_best_PLL,
168 static const intel_limit_t intel_limits_g4x_sdvo = {
169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
181 .find_pll = intel_g4x_find_best_PLL,
184 static const intel_limit_t intel_limits_g4x_hdmi = {
185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
195 .find_pll = intel_g4x_find_best_PLL,
198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
210 .find_pll = intel_g4x_find_best_PLL,
213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
225 .find_pll = intel_g4x_find_best_PLL,
228 static const intel_limit_t intel_limits_g4x_display_port = {
229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 10, .p2_fast = 10 },
239 .find_pll = intel_find_pll_g4x_dp,
242 static const intel_limit_t intel_limits_pineview_sdvo = {
243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
245 /* Pineview's Ncounter is a ring counter */
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 /* Pineview only has one combined m divider, which we treat as m2. */
249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
255 .find_pll = intel_find_best_PLL,
258 static const intel_limit_t intel_limits_pineview_lvds = {
259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
269 .find_pll = intel_find_best_PLL,
272 /* Ironlake / Sandybridge
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
277 static const intel_limit_t intel_limits_ironlake_dac = {
278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
288 .find_pll = intel_g4x_find_best_PLL,
291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
302 .find_pll = intel_g4x_find_best_PLL,
305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
316 .find_pll = intel_g4x_find_best_PLL,
319 /* LVDS 100mhz refclk limits. */
320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
342 .p1 = { .min = 2, .max = 6 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
348 static const intel_limit_t intel_limits_ironlake_display_port = {
349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 10, .p2_fast = 10 },
359 .find_pll = intel_find_pll_ironlake_dp,
362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
380 val = I915_READ(DPIO_DATA);
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
387 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
392 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
393 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
394 DRM_ERROR("DPIO idle wait timed out\n");
398 I915_WRITE(DPIO_DATA, val);
399 I915_WRITE(DPIO_REG, reg);
400 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
402 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
403 DRM_ERROR("DPIO write wait timed out\n");
406 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
409 static void vlv_init_dpio(struct drm_device *dev)
411 struct drm_i915_private *dev_priv = dev->dev_private;
413 /* Reset the DPIO config */
414 I915_WRITE(DPIO_CTL, 0);
415 POSTING_READ(DPIO_CTL);
416 I915_WRITE(DPIO_CTL, 1);
417 POSTING_READ(DPIO_CTL);
420 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
422 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
426 static const struct dmi_system_id intel_dual_link_lvds[] = {
428 .callback = intel_dual_link_lvds_callback,
429 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
431 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
432 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
435 { } /* terminating entry */
438 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
443 /* use the module option value if specified */
444 if (i915_lvds_channel_mode > 0)
445 return i915_lvds_channel_mode == 2;
447 if (dmi_check_system(intel_dual_link_lvds))
450 if (dev_priv->lvds_val)
451 val = dev_priv->lvds_val;
453 /* BIOS should set the proper LVDS register value at boot, but
454 * in reality, it doesn't set the value when the lid is closed;
455 * we need to check "the value to be set" in VBT when LVDS
456 * register is uninitialized.
458 val = I915_READ(reg);
459 if (!(val & ~LVDS_DETECTED))
460 val = dev_priv->bios_lvds_val;
461 dev_priv->lvds_val = val;
463 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
466 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
469 struct drm_device *dev = crtc->dev;
470 struct drm_i915_private *dev_priv = dev->dev_private;
471 const intel_limit_t *limit;
473 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
475 /* LVDS dual channel */
476 if (refclk == 100000)
477 limit = &intel_limits_ironlake_dual_lvds_100m;
479 limit = &intel_limits_ironlake_dual_lvds;
481 if (refclk == 100000)
482 limit = &intel_limits_ironlake_single_lvds_100m;
484 limit = &intel_limits_ironlake_single_lvds;
486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
488 limit = &intel_limits_ironlake_display_port;
490 limit = &intel_limits_ironlake_dac;
495 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
497 struct drm_device *dev = crtc->dev;
498 struct drm_i915_private *dev_priv = dev->dev_private;
499 const intel_limit_t *limit;
501 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
502 if (is_dual_link_lvds(dev_priv, LVDS))
503 /* LVDS with dual channel */
504 limit = &intel_limits_g4x_dual_channel_lvds;
506 /* LVDS with dual channel */
507 limit = &intel_limits_g4x_single_channel_lvds;
508 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
509 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
510 limit = &intel_limits_g4x_hdmi;
511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
512 limit = &intel_limits_g4x_sdvo;
513 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
514 limit = &intel_limits_g4x_display_port;
515 } else /* The option is for other outputs */
516 limit = &intel_limits_i9xx_sdvo;
521 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
523 struct drm_device *dev = crtc->dev;
524 const intel_limit_t *limit;
526 if (HAS_PCH_SPLIT(dev))
527 limit = intel_ironlake_limit(crtc, refclk);
528 else if (IS_G4X(dev)) {
529 limit = intel_g4x_limit(crtc);
530 } else if (IS_PINEVIEW(dev)) {
531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
532 limit = &intel_limits_pineview_lvds;
534 limit = &intel_limits_pineview_sdvo;
535 } else if (!IS_GEN2(dev)) {
536 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
537 limit = &intel_limits_i9xx_lvds;
539 limit = &intel_limits_i9xx_sdvo;
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i8xx_lvds;
544 limit = &intel_limits_i8xx_dvo;
549 /* m1 is reserved as 0 in Pineview, n is a ring counter */
550 static void pineview_clock(int refclk, intel_clock_t *clock)
552 clock->m = clock->m2 + 2;
553 clock->p = clock->p1 * clock->p2;
554 clock->vco = refclk * clock->m / clock->n;
555 clock->dot = clock->vco / clock->p;
558 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
560 if (IS_PINEVIEW(dev)) {
561 pineview_clock(refclk, clock);
564 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
565 clock->p = clock->p1 * clock->p2;
566 clock->vco = refclk * clock->m / (clock->n + 2);
567 clock->dot = clock->vco / clock->p;
571 * Returns whether any output on the specified pipe is of the specified type
573 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
575 struct drm_device *dev = crtc->dev;
576 struct drm_mode_config *mode_config = &dev->mode_config;
577 struct intel_encoder *encoder;
579 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
580 if (encoder->base.crtc == crtc && encoder->type == type)
586 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
588 * Returns whether the given set of divisors are valid for a given refclk with
589 * the given connectors.
592 static bool intel_PLL_is_valid(struct drm_device *dev,
593 const intel_limit_t *limit,
594 const intel_clock_t *clock)
596 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
597 INTELPllInvalid("p1 out of range\n");
598 if (clock->p < limit->p.min || limit->p.max < clock->p)
599 INTELPllInvalid("p out of range\n");
600 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
601 INTELPllInvalid("m2 out of range\n");
602 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
603 INTELPllInvalid("m1 out of range\n");
604 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
605 INTELPllInvalid("m1 <= m2\n");
606 if (clock->m < limit->m.min || limit->m.max < clock->m)
607 INTELPllInvalid("m out of range\n");
608 if (clock->n < limit->n.min || limit->n.max < clock->n)
609 INTELPllInvalid("n out of range\n");
610 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
611 INTELPllInvalid("vco out of range\n");
612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613 * connector, etc., rather than just a single range.
615 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
616 INTELPllInvalid("dot out of range\n");
622 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
623 int target, int refclk, intel_clock_t *match_clock,
624 intel_clock_t *best_clock)
627 struct drm_device *dev = crtc->dev;
628 struct drm_i915_private *dev_priv = dev->dev_private;
632 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
633 (I915_READ(LVDS)) != 0) {
635 * For LVDS, if the panel is on, just rely on its current
636 * settings for dual-channel. We haven't figured out how to
637 * reliably set up different single/dual channel state, if we
640 if (is_dual_link_lvds(dev_priv, LVDS))
641 clock.p2 = limit->p2.p2_fast;
643 clock.p2 = limit->p2.p2_slow;
645 if (target < limit->p2.dot_limit)
646 clock.p2 = limit->p2.p2_slow;
648 clock.p2 = limit->p2.p2_fast;
651 memset(best_clock, 0, sizeof(*best_clock));
653 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 for (clock.m2 = limit->m2.min;
656 clock.m2 <= limit->m2.max; clock.m2++) {
657 /* m1 is always 0 in Pineview */
658 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
660 for (clock.n = limit->n.min;
661 clock.n <= limit->n.max; clock.n++) {
662 for (clock.p1 = limit->p1.min;
663 clock.p1 <= limit->p1.max; clock.p1++) {
666 intel_clock(dev, refclk, &clock);
667 if (!intel_PLL_is_valid(dev, limit,
671 clock.p != match_clock->p)
674 this_err = abs(clock.dot - target);
675 if (this_err < err) {
684 return (err != target);
688 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
689 int target, int refclk, intel_clock_t *match_clock,
690 intel_clock_t *best_clock)
692 struct drm_device *dev = crtc->dev;
693 struct drm_i915_private *dev_priv = dev->dev_private;
697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
704 if (HAS_PCH_SPLIT(dev))
708 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
710 clock.p2 = limit->p2.p2_fast;
712 clock.p2 = limit->p2.p2_slow;
714 if (target < limit->p2.dot_limit)
715 clock.p2 = limit->p2.p2_slow;
717 clock.p2 = limit->p2.p2_fast;
720 memset(best_clock, 0, sizeof(*best_clock));
721 max_n = limit->n.max;
722 /* based on hardware requirement, prefer smaller n to precision */
723 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
724 /* based on hardware requirement, prefere larger m1,m2 */
725 for (clock.m1 = limit->m1.max;
726 clock.m1 >= limit->m1.min; clock.m1--) {
727 for (clock.m2 = limit->m2.max;
728 clock.m2 >= limit->m2.min; clock.m2--) {
729 for (clock.p1 = limit->p1.max;
730 clock.p1 >= limit->p1.min; clock.p1--) {
733 intel_clock(dev, refclk, &clock);
734 if (!intel_PLL_is_valid(dev, limit,
738 clock.p != match_clock->p)
741 this_err = abs(clock.dot - target);
742 if (this_err < err_most) {
756 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
757 int target, int refclk, intel_clock_t *match_clock,
758 intel_clock_t *best_clock)
760 struct drm_device *dev = crtc->dev;
763 if (target < 200000) {
776 intel_clock(dev, refclk, &clock);
777 memcpy(best_clock, &clock, sizeof(intel_clock_t));
781 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
783 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
784 int target, int refclk, intel_clock_t *match_clock,
785 intel_clock_t *best_clock)
788 if (target < 200000) {
801 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
802 clock.p = (clock.p1 * clock.p2);
803 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
805 memcpy(best_clock, &clock, sizeof(intel_clock_t));
810 * intel_wait_for_vblank - wait for vblank on a given pipe
812 * @pipe: pipe to wait for
814 * Wait for vblank to occur on a given pipe. Needed for various bits of
817 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 int pipestat_reg = PIPESTAT(pipe);
822 /* Clear existing vblank status. Note this will clear any other
823 * sticky status fields as well.
825 * This races with i915_driver_irq_handler() with the result
826 * that either function could miss a vblank event. Here it is not
827 * fatal, as we will either wait upon the next vblank interrupt or
828 * timeout. Generally speaking intel_wait_for_vblank() is only
829 * called during modeset at which time the GPU should be idle and
830 * should *not* be performing page flips and thus not waiting on
832 * Currently, the result of us stealing a vblank from the irq
833 * handler is that a single frame will be skipped during swapbuffers.
835 I915_WRITE(pipestat_reg,
836 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
838 /* Wait for vblank interrupt bit to set */
839 if (wait_for(I915_READ(pipestat_reg) &
840 PIPE_VBLANK_INTERRUPT_STATUS,
842 DRM_DEBUG_KMS("vblank wait timed out\n");
846 * intel_wait_for_pipe_off - wait for pipe to turn off
848 * @pipe: pipe to wait for
850 * After disabling a pipe, we can't wait for vblank in the usual way,
851 * spinning on the vblank interrupt status bit, since we won't actually
852 * see an interrupt when the pipe is disabled.
855 * wait for the pipe register state bit to turn off
858 * wait for the display line value to settle (it usually
859 * ends up stopping at the start of the next frame).
862 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
864 struct drm_i915_private *dev_priv = dev->dev_private;
866 if (INTEL_INFO(dev)->gen >= 4) {
867 int reg = PIPECONF(pipe);
869 /* Wait for the Pipe State to go off */
870 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
872 DRM_DEBUG_KMS("pipe_off wait timed out\n");
875 int reg = PIPEDSL(pipe);
876 unsigned long timeout = jiffies + msecs_to_jiffies(100);
878 /* Wait for the display line to settle */
880 last_line = I915_READ(reg) & DSL_LINEMASK;
882 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
883 time_after(timeout, jiffies));
884 if (time_after(jiffies, timeout))
885 DRM_DEBUG_KMS("pipe_off wait timed out\n");
889 static const char *state_string(bool enabled)
891 return enabled ? "on" : "off";
894 /* Only for pre-ILK configs */
895 static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
913 static void assert_pch_pll(struct drm_i915_private *dev_priv,
914 struct intel_crtc *intel_crtc, bool state)
920 if (!intel_crtc->pch_pll) {
921 WARN(1, "asserting PCH PLL enabled with no PLL\n");
925 if (HAS_PCH_CPT(dev_priv->dev)) {
928 pch_dpll = I915_READ(PCH_DPLL_SEL);
930 /* Make sure the selected PLL is enabled to the transcoder */
931 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
932 "transcoder %d PLL not enabled\n", intel_crtc->pipe);
935 reg = intel_crtc->pch_pll->pll_reg;
936 val = I915_READ(reg);
937 cur_state = !!(val & DPLL_VCO_ENABLE);
938 WARN(cur_state != state,
939 "PCH PLL state assertion failure (expected %s, current %s)\n",
940 state_string(state), state_string(cur_state));
942 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
943 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
945 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
946 enum pipe pipe, bool state)
952 reg = FDI_TX_CTL(pipe);
953 val = I915_READ(reg);
954 cur_state = !!(val & FDI_TX_ENABLE);
955 WARN(cur_state != state,
956 "FDI TX state assertion failure (expected %s, current %s)\n",
957 state_string(state), state_string(cur_state));
959 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
960 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
962 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
963 enum pipe pipe, bool state)
969 reg = FDI_RX_CTL(pipe);
970 val = I915_READ(reg);
971 cur_state = !!(val & FDI_RX_ENABLE);
972 WARN(cur_state != state,
973 "FDI RX state assertion failure (expected %s, current %s)\n",
974 state_string(state), state_string(cur_state));
976 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
977 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
979 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
985 /* ILK FDI PLL is always enabled */
986 if (dev_priv->info->gen == 5)
989 reg = FDI_TX_CTL(pipe);
990 val = I915_READ(reg);
991 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
994 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1000 reg = FDI_RX_CTL(pipe);
1001 val = I915_READ(reg);
1002 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1005 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1008 int pp_reg, lvds_reg;
1010 enum pipe panel_pipe = PIPE_A;
1013 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1014 pp_reg = PCH_PP_CONTROL;
1015 lvds_reg = PCH_LVDS;
1017 pp_reg = PP_CONTROL;
1021 val = I915_READ(pp_reg);
1022 if (!(val & PANEL_POWER_ON) ||
1023 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1026 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1027 panel_pipe = PIPE_B;
1029 WARN(panel_pipe == pipe && locked,
1030 "panel assertion failure, pipe %c regs locked\n",
1034 void assert_pipe(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, bool state)
1041 /* if we need the pipe A quirk it must be always on */
1042 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1045 reg = PIPECONF(pipe);
1046 val = I915_READ(reg);
1047 cur_state = !!(val & PIPECONF_ENABLE);
1048 WARN(cur_state != state,
1049 "pipe %c assertion failure (expected %s, current %s)\n",
1050 pipe_name(pipe), state_string(state), state_string(cur_state));
1053 static void assert_plane(struct drm_i915_private *dev_priv,
1054 enum plane plane, bool state)
1060 reg = DSPCNTR(plane);
1061 val = I915_READ(reg);
1062 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1063 WARN(cur_state != state,
1064 "plane %c assertion failure (expected %s, current %s)\n",
1065 plane_name(plane), state_string(state), state_string(cur_state));
1068 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1069 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1071 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1078 /* Planes are fixed to pipes on ILK+ */
1079 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080 reg = DSPCNTR(pipe);
1081 val = I915_READ(reg);
1082 WARN((val & DISPLAY_PLANE_ENABLE),
1083 "plane %c assertion failure, should be disabled but not\n",
1088 /* Need to check both planes against the pipe */
1089 for (i = 0; i < 2; i++) {
1091 val = I915_READ(reg);
1092 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1093 DISPPLANE_SEL_PIPE_SHIFT;
1094 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1095 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1096 plane_name(i), pipe_name(pipe));
1100 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1105 val = I915_READ(PCH_DREF_CONTROL);
1106 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1107 DREF_SUPERSPREAD_SOURCE_MASK));
1108 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1111 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1118 reg = TRANSCONF(pipe);
1119 val = I915_READ(reg);
1120 enabled = !!(val & TRANS_ENABLE);
1122 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1126 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1127 enum pipe pipe, u32 port_sel, u32 val)
1129 if ((val & DP_PORT_EN) == 0)
1132 if (HAS_PCH_CPT(dev_priv->dev)) {
1133 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1134 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1135 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1138 if ((val & DP_PIPE_MASK) != (pipe << 30))
1144 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, u32 val)
1147 if ((val & PORT_ENABLE) == 0)
1150 if (HAS_PCH_CPT(dev_priv->dev)) {
1151 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1154 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1160 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1161 enum pipe pipe, u32 val)
1163 if ((val & LVDS_PORT_EN) == 0)
1166 if (HAS_PCH_CPT(dev_priv->dev)) {
1167 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1170 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1176 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1177 enum pipe pipe, u32 val)
1179 if ((val & ADPA_DAC_ENABLE) == 0)
1181 if (HAS_PCH_CPT(dev_priv->dev)) {
1182 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1185 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1191 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, int reg, u32 port_sel)
1194 u32 val = I915_READ(reg);
1195 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1196 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1197 reg, pipe_name(pipe));
1200 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1201 enum pipe pipe, int reg)
1203 u32 val = I915_READ(reg);
1204 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1205 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1206 reg, pipe_name(pipe));
1209 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1215 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1216 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1217 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1220 val = I915_READ(reg);
1221 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1222 "PCH VGA enabled on transcoder %c, should be disabled\n",
1226 val = I915_READ(reg);
1227 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1228 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1231 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1232 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1233 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1237 * intel_enable_pll - enable a PLL
1238 * @dev_priv: i915 private structure
1239 * @pipe: pipe PLL to enable
1241 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1242 * make sure the PLL reg is writable first though, since the panel write
1243 * protect mechanism may be enabled.
1245 * Note! This is for pre-ILK only.
1247 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1252 /* No really, not for ILK+ */
1253 BUG_ON(dev_priv->info->gen >= 5);
1255 /* PLL is protected by panel, make sure we can write it */
1256 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1257 assert_panel_unlocked(dev_priv, pipe);
1260 val = I915_READ(reg);
1261 val |= DPLL_VCO_ENABLE;
1263 /* We do this three times for luck */
1264 I915_WRITE(reg, val);
1266 udelay(150); /* wait for warmup */
1267 I915_WRITE(reg, val);
1269 udelay(150); /* wait for warmup */
1270 I915_WRITE(reg, val);
1272 udelay(150); /* wait for warmup */
1276 * intel_disable_pll - disable a PLL
1277 * @dev_priv: i915 private structure
1278 * @pipe: pipe PLL to disable
1280 * Disable the PLL for @pipe, making sure the pipe is off first.
1282 * Note! This is for pre-ILK only.
1284 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1289 /* Don't disable pipe A or pipe A PLLs if needed */
1290 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1293 /* Make sure the pipe isn't still relying on us */
1294 assert_pipe_disabled(dev_priv, pipe);
1297 val = I915_READ(reg);
1298 val &= ~DPLL_VCO_ENABLE;
1299 I915_WRITE(reg, val);
1304 * intel_enable_pch_pll - enable PCH PLL
1305 * @dev_priv: i915 private structure
1306 * @pipe: pipe PLL to enable
1308 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1309 * drives the transcoder clock.
1311 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1313 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1314 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1318 /* PCH only available on ILK+ */
1319 BUG_ON(dev_priv->info->gen < 5);
1320 BUG_ON(pll == NULL);
1321 BUG_ON(pll->refcount == 0);
1323 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1324 pll->pll_reg, pll->active, pll->on,
1325 intel_crtc->base.base.id);
1327 /* PCH refclock must be enabled first */
1328 assert_pch_refclk_enabled(dev_priv);
1330 if (pll->active++ && pll->on) {
1331 assert_pch_pll_enabled(dev_priv, intel_crtc);
1335 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1338 val = I915_READ(reg);
1339 val |= DPLL_VCO_ENABLE;
1340 I915_WRITE(reg, val);
1347 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1349 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1350 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1354 /* PCH only available on ILK+ */
1355 BUG_ON(dev_priv->info->gen < 5);
1359 BUG_ON(pll->refcount == 0);
1361 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1362 pll->pll_reg, pll->active, pll->on,
1363 intel_crtc->base.base.id);
1365 BUG_ON(pll->active == 0);
1366 if (--pll->active) {
1367 assert_pch_pll_enabled(dev_priv, intel_crtc);
1371 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1373 /* Make sure transcoder isn't still depending on us */
1374 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1377 val = I915_READ(reg);
1378 val &= ~DPLL_VCO_ENABLE;
1379 I915_WRITE(reg, val);
1386 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1390 u32 val, pipeconf_val;
1391 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1393 /* PCH only available on ILK+ */
1394 BUG_ON(dev_priv->info->gen < 5);
1396 /* Make sure PCH DPLL is enabled */
1397 assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
1399 /* FDI must be feeding us bits for PCH ports */
1400 assert_fdi_tx_enabled(dev_priv, pipe);
1401 assert_fdi_rx_enabled(dev_priv, pipe);
1403 reg = TRANSCONF(pipe);
1404 val = I915_READ(reg);
1405 pipeconf_val = I915_READ(PIPECONF(pipe));
1407 if (HAS_PCH_IBX(dev_priv->dev)) {
1409 * make the BPC in transcoder be consistent with
1410 * that in pipeconf reg.
1412 val &= ~PIPE_BPC_MASK;
1413 val |= pipeconf_val & PIPE_BPC_MASK;
1416 val &= ~TRANS_INTERLACE_MASK;
1417 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1418 if (HAS_PCH_IBX(dev_priv->dev) &&
1419 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1420 val |= TRANS_LEGACY_INTERLACED_ILK;
1422 val |= TRANS_INTERLACED;
1424 val |= TRANS_PROGRESSIVE;
1426 I915_WRITE(reg, val | TRANS_ENABLE);
1427 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1428 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1431 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1437 /* FDI relies on the transcoder */
1438 assert_fdi_tx_disabled(dev_priv, pipe);
1439 assert_fdi_rx_disabled(dev_priv, pipe);
1441 /* Ports must be off as well */
1442 assert_pch_ports_disabled(dev_priv, pipe);
1444 reg = TRANSCONF(pipe);
1445 val = I915_READ(reg);
1446 val &= ~TRANS_ENABLE;
1447 I915_WRITE(reg, val);
1448 /* wait for PCH transcoder off, transcoder state */
1449 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1450 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1454 * intel_enable_pipe - enable a pipe, asserting requirements
1455 * @dev_priv: i915 private structure
1456 * @pipe: pipe to enable
1457 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1459 * Enable @pipe, making sure that various hardware specific requirements
1460 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1462 * @pipe should be %PIPE_A or %PIPE_B.
1464 * Will wait until the pipe is actually running (i.e. first vblank) before
1467 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1474 * A pipe without a PLL won't actually be able to drive bits from
1475 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1478 if (!HAS_PCH_SPLIT(dev_priv->dev))
1479 assert_pll_enabled(dev_priv, pipe);
1482 /* if driving the PCH, we need FDI enabled */
1483 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1484 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1486 /* FIXME: assert CPU port conditions for SNB+ */
1489 reg = PIPECONF(pipe);
1490 val = I915_READ(reg);
1491 if (val & PIPECONF_ENABLE)
1494 I915_WRITE(reg, val | PIPECONF_ENABLE);
1495 intel_wait_for_vblank(dev_priv->dev, pipe);
1499 * intel_disable_pipe - disable a pipe, asserting requirements
1500 * @dev_priv: i915 private structure
1501 * @pipe: pipe to disable
1503 * Disable @pipe, making sure that various hardware specific requirements
1504 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1506 * @pipe should be %PIPE_A or %PIPE_B.
1508 * Will wait until the pipe has shut down before returning.
1510 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1517 * Make sure planes won't keep trying to pump pixels to us,
1518 * or we might hang the display.
1520 assert_planes_disabled(dev_priv, pipe);
1522 /* Don't disable pipe A or pipe A PLLs if needed */
1523 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1526 reg = PIPECONF(pipe);
1527 val = I915_READ(reg);
1528 if ((val & PIPECONF_ENABLE) == 0)
1531 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1532 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1536 * Plane regs are double buffered, going from enabled->disabled needs a
1537 * trigger in order to latch. The display address reg provides this.
1539 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1542 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1543 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1547 * intel_enable_plane - enable a display plane on a given pipe
1548 * @dev_priv: i915 private structure
1549 * @plane: plane to enable
1550 * @pipe: pipe being fed
1552 * Enable @plane on @pipe, making sure that @pipe is running first.
1554 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1555 enum plane plane, enum pipe pipe)
1560 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1561 assert_pipe_enabled(dev_priv, pipe);
1563 reg = DSPCNTR(plane);
1564 val = I915_READ(reg);
1565 if (val & DISPLAY_PLANE_ENABLE)
1568 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1569 intel_flush_display_plane(dev_priv, plane);
1570 intel_wait_for_vblank(dev_priv->dev, pipe);
1574 * intel_disable_plane - disable a display plane
1575 * @dev_priv: i915 private structure
1576 * @plane: plane to disable
1577 * @pipe: pipe consuming the data
1579 * Disable @plane; should be an independent operation.
1581 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1582 enum plane plane, enum pipe pipe)
1587 reg = DSPCNTR(plane);
1588 val = I915_READ(reg);
1589 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1592 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1593 intel_flush_display_plane(dev_priv, plane);
1594 intel_wait_for_vblank(dev_priv->dev, pipe);
1597 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1598 enum pipe pipe, int reg, u32 port_sel)
1600 u32 val = I915_READ(reg);
1601 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1602 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1603 I915_WRITE(reg, val & ~DP_PORT_EN);
1607 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1608 enum pipe pipe, int reg)
1610 u32 val = I915_READ(reg);
1611 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1612 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1614 I915_WRITE(reg, val & ~PORT_ENABLE);
1618 /* Disable any ports connected to this transcoder */
1619 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1624 val = I915_READ(PCH_PP_CONTROL);
1625 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1627 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1628 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1629 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1632 val = I915_READ(reg);
1633 if (adpa_pipe_enabled(dev_priv, val, pipe))
1634 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1637 val = I915_READ(reg);
1638 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1639 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1640 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1645 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1646 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1647 disable_pch_hdmi(dev_priv, pipe, HDMID);
1651 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1652 struct drm_i915_gem_object *obj,
1653 struct intel_ring_buffer *pipelined)
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1659 switch (obj->tiling_mode) {
1660 case I915_TILING_NONE:
1661 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1662 alignment = 128 * 1024;
1663 else if (INTEL_INFO(dev)->gen >= 4)
1664 alignment = 4 * 1024;
1666 alignment = 64 * 1024;
1669 /* pin() will align the object as required by fence */
1673 /* FIXME: Is this true? */
1674 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1680 dev_priv->mm.interruptible = false;
1681 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1683 goto err_interruptible;
1685 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1686 * fence, whereas 965+ only requires a fence if using
1687 * framebuffer compression. For simplicity, we always install
1688 * a fence as the cost is not that onerous.
1690 ret = i915_gem_object_get_fence(obj);
1694 i915_gem_object_pin_fence(obj);
1696 dev_priv->mm.interruptible = true;
1700 i915_gem_object_unpin(obj);
1702 dev_priv->mm.interruptible = true;
1706 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1708 i915_gem_object_unpin_fence(obj);
1709 i915_gem_object_unpin(obj);
1712 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1715 struct drm_device *dev = crtc->dev;
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1718 struct intel_framebuffer *intel_fb;
1719 struct drm_i915_gem_object *obj;
1720 int plane = intel_crtc->plane;
1721 unsigned long Start, Offset;
1730 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1734 intel_fb = to_intel_framebuffer(fb);
1735 obj = intel_fb->obj;
1737 reg = DSPCNTR(plane);
1738 dspcntr = I915_READ(reg);
1739 /* Mask out pixel format bits in case we change it */
1740 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1741 switch (fb->bits_per_pixel) {
1743 dspcntr |= DISPPLANE_8BPP;
1746 if (fb->depth == 15)
1747 dspcntr |= DISPPLANE_15_16BPP;
1749 dspcntr |= DISPPLANE_16BPP;
1753 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1756 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1759 if (INTEL_INFO(dev)->gen >= 4) {
1760 if (obj->tiling_mode != I915_TILING_NONE)
1761 dspcntr |= DISPPLANE_TILED;
1763 dspcntr &= ~DISPPLANE_TILED;
1766 I915_WRITE(reg, dspcntr);
1768 Start = obj->gtt_offset;
1769 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1771 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1772 Start, Offset, x, y, fb->pitches[0]);
1773 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1774 if (INTEL_INFO(dev)->gen >= 4) {
1775 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1776 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1777 I915_WRITE(DSPADDR(plane), Offset);
1779 I915_WRITE(DSPADDR(plane), Start + Offset);
1785 static int ironlake_update_plane(struct drm_crtc *crtc,
1786 struct drm_framebuffer *fb, int x, int y)
1788 struct drm_device *dev = crtc->dev;
1789 struct drm_i915_private *dev_priv = dev->dev_private;
1790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1791 struct intel_framebuffer *intel_fb;
1792 struct drm_i915_gem_object *obj;
1793 int plane = intel_crtc->plane;
1794 unsigned long Start, Offset;
1804 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1808 intel_fb = to_intel_framebuffer(fb);
1809 obj = intel_fb->obj;
1811 reg = DSPCNTR(plane);
1812 dspcntr = I915_READ(reg);
1813 /* Mask out pixel format bits in case we change it */
1814 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1815 switch (fb->bits_per_pixel) {
1817 dspcntr |= DISPPLANE_8BPP;
1820 if (fb->depth != 16)
1823 dspcntr |= DISPPLANE_16BPP;
1827 if (fb->depth == 24)
1828 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1829 else if (fb->depth == 30)
1830 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1835 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1839 if (obj->tiling_mode != I915_TILING_NONE)
1840 dspcntr |= DISPPLANE_TILED;
1842 dspcntr &= ~DISPPLANE_TILED;
1845 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1847 I915_WRITE(reg, dspcntr);
1849 Start = obj->gtt_offset;
1850 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1852 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1853 Start, Offset, x, y, fb->pitches[0]);
1854 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1855 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1856 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1857 I915_WRITE(DSPADDR(plane), Offset);
1863 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1865 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1866 int x, int y, enum mode_set_atomic state)
1868 struct drm_device *dev = crtc->dev;
1869 struct drm_i915_private *dev_priv = dev->dev_private;
1871 if (dev_priv->display.disable_fbc)
1872 dev_priv->display.disable_fbc(dev);
1873 intel_increase_pllclock(crtc);
1875 return dev_priv->display.update_plane(crtc, fb, x, y);
1879 intel_finish_fb(struct drm_framebuffer *old_fb)
1881 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1882 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1883 bool was_interruptible = dev_priv->mm.interruptible;
1886 wait_event(dev_priv->pending_flip_queue,
1887 atomic_read(&dev_priv->mm.wedged) ||
1888 atomic_read(&obj->pending_flip) == 0);
1890 /* Big Hammer, we also need to ensure that any pending
1891 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1892 * current scanout is retired before unpinning the old
1895 * This should only fail upon a hung GPU, in which case we
1896 * can safely continue.
1898 dev_priv->mm.interruptible = false;
1899 ret = i915_gem_object_finish_gpu(obj);
1900 dev_priv->mm.interruptible = was_interruptible;
1906 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1907 struct drm_framebuffer *old_fb)
1909 struct drm_device *dev = crtc->dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 struct drm_i915_master_private *master_priv;
1912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1917 DRM_ERROR("No FB bound\n");
1921 switch (intel_crtc->plane) {
1926 if (IS_IVYBRIDGE(dev))
1928 /* fall through otherwise */
1930 DRM_ERROR("no plane for crtc\n");
1934 mutex_lock(&dev->struct_mutex);
1935 ret = intel_pin_and_fence_fb_obj(dev,
1936 to_intel_framebuffer(crtc->fb)->obj,
1939 mutex_unlock(&dev->struct_mutex);
1940 DRM_ERROR("pin & fence failed\n");
1945 intel_finish_fb(old_fb);
1947 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
1949 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
1950 mutex_unlock(&dev->struct_mutex);
1951 DRM_ERROR("failed to update base address\n");
1956 intel_wait_for_vblank(dev, intel_crtc->pipe);
1957 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
1960 intel_update_fbc(dev);
1961 mutex_unlock(&dev->struct_mutex);
1963 if (!dev->primary->master)
1966 master_priv = dev->primary->master->driver_priv;
1967 if (!master_priv->sarea_priv)
1970 if (intel_crtc->pipe) {
1971 master_priv->sarea_priv->pipeB_x = x;
1972 master_priv->sarea_priv->pipeB_y = y;
1974 master_priv->sarea_priv->pipeA_x = x;
1975 master_priv->sarea_priv->pipeA_y = y;
1981 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1983 struct drm_device *dev = crtc->dev;
1984 struct drm_i915_private *dev_priv = dev->dev_private;
1987 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1988 dpa_ctl = I915_READ(DP_A);
1989 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1991 if (clock < 200000) {
1993 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1994 /* workaround for 160Mhz:
1995 1) program 0x4600c bits 15:0 = 0x8124
1996 2) program 0x46010 bit 0 = 1
1997 3) program 0x46034 bit 24 = 1
1998 4) program 0x64000 bit 14 = 1
2000 temp = I915_READ(0x4600c);
2002 I915_WRITE(0x4600c, temp | 0x8124);
2004 temp = I915_READ(0x46010);
2005 I915_WRITE(0x46010, temp | 1);
2007 temp = I915_READ(0x46034);
2008 I915_WRITE(0x46034, temp | (1 << 24));
2010 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2012 I915_WRITE(DP_A, dpa_ctl);
2018 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2020 struct drm_device *dev = crtc->dev;
2021 struct drm_i915_private *dev_priv = dev->dev_private;
2022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2023 int pipe = intel_crtc->pipe;
2026 /* enable normal train */
2027 reg = FDI_TX_CTL(pipe);
2028 temp = I915_READ(reg);
2029 if (IS_IVYBRIDGE(dev)) {
2030 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2031 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2033 temp &= ~FDI_LINK_TRAIN_NONE;
2034 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2036 I915_WRITE(reg, temp);
2038 reg = FDI_RX_CTL(pipe);
2039 temp = I915_READ(reg);
2040 if (HAS_PCH_CPT(dev)) {
2041 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2042 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2044 temp &= ~FDI_LINK_TRAIN_NONE;
2045 temp |= FDI_LINK_TRAIN_NONE;
2047 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2049 /* wait one idle pattern time */
2053 /* IVB wants error correction enabled */
2054 if (IS_IVYBRIDGE(dev))
2055 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2056 FDI_FE_ERRC_ENABLE);
2059 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2061 struct drm_i915_private *dev_priv = dev->dev_private;
2062 u32 flags = I915_READ(SOUTH_CHICKEN1);
2064 flags |= FDI_PHASE_SYNC_OVR(pipe);
2065 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2066 flags |= FDI_PHASE_SYNC_EN(pipe);
2067 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2068 POSTING_READ(SOUTH_CHICKEN1);
2071 /* The FDI link training functions for ILK/Ibexpeak. */
2072 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2074 struct drm_device *dev = crtc->dev;
2075 struct drm_i915_private *dev_priv = dev->dev_private;
2076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2077 int pipe = intel_crtc->pipe;
2078 int plane = intel_crtc->plane;
2079 u32 reg, temp, tries;
2081 /* FDI needs bits from pipe & plane first */
2082 assert_pipe_enabled(dev_priv, pipe);
2083 assert_plane_enabled(dev_priv, plane);
2085 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2087 reg = FDI_RX_IMR(pipe);
2088 temp = I915_READ(reg);
2089 temp &= ~FDI_RX_SYMBOL_LOCK;
2090 temp &= ~FDI_RX_BIT_LOCK;
2091 I915_WRITE(reg, temp);
2095 /* enable CPU FDI TX and PCH FDI RX */
2096 reg = FDI_TX_CTL(pipe);
2097 temp = I915_READ(reg);
2099 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2100 temp &= ~FDI_LINK_TRAIN_NONE;
2101 temp |= FDI_LINK_TRAIN_PATTERN_1;
2102 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2104 reg = FDI_RX_CTL(pipe);
2105 temp = I915_READ(reg);
2106 temp &= ~FDI_LINK_TRAIN_NONE;
2107 temp |= FDI_LINK_TRAIN_PATTERN_1;
2108 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2113 /* Ironlake workaround, enable clock pointer after FDI enable*/
2114 if (HAS_PCH_IBX(dev)) {
2115 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2116 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2117 FDI_RX_PHASE_SYNC_POINTER_EN);
2120 reg = FDI_RX_IIR(pipe);
2121 for (tries = 0; tries < 5; tries++) {
2122 temp = I915_READ(reg);
2123 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2125 if ((temp & FDI_RX_BIT_LOCK)) {
2126 DRM_DEBUG_KMS("FDI train 1 done.\n");
2127 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2132 DRM_ERROR("FDI train 1 fail!\n");
2135 reg = FDI_TX_CTL(pipe);
2136 temp = I915_READ(reg);
2137 temp &= ~FDI_LINK_TRAIN_NONE;
2138 temp |= FDI_LINK_TRAIN_PATTERN_2;
2139 I915_WRITE(reg, temp);
2141 reg = FDI_RX_CTL(pipe);
2142 temp = I915_READ(reg);
2143 temp &= ~FDI_LINK_TRAIN_NONE;
2144 temp |= FDI_LINK_TRAIN_PATTERN_2;
2145 I915_WRITE(reg, temp);
2150 reg = FDI_RX_IIR(pipe);
2151 for (tries = 0; tries < 5; tries++) {
2152 temp = I915_READ(reg);
2153 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2155 if (temp & FDI_RX_SYMBOL_LOCK) {
2156 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2157 DRM_DEBUG_KMS("FDI train 2 done.\n");
2162 DRM_ERROR("FDI train 2 fail!\n");
2164 DRM_DEBUG_KMS("FDI train done\n");
2168 static const int snb_b_fdi_train_param[] = {
2169 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2170 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2171 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2172 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2175 /* The FDI link training functions for SNB/Cougarpoint. */
2176 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2178 struct drm_device *dev = crtc->dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181 int pipe = intel_crtc->pipe;
2182 u32 reg, temp, i, retry;
2184 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2186 reg = FDI_RX_IMR(pipe);
2187 temp = I915_READ(reg);
2188 temp &= ~FDI_RX_SYMBOL_LOCK;
2189 temp &= ~FDI_RX_BIT_LOCK;
2190 I915_WRITE(reg, temp);
2195 /* enable CPU FDI TX and PCH FDI RX */
2196 reg = FDI_TX_CTL(pipe);
2197 temp = I915_READ(reg);
2199 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2200 temp &= ~FDI_LINK_TRAIN_NONE;
2201 temp |= FDI_LINK_TRAIN_PATTERN_1;
2202 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2204 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2205 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2207 reg = FDI_RX_CTL(pipe);
2208 temp = I915_READ(reg);
2209 if (HAS_PCH_CPT(dev)) {
2210 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2211 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2213 temp &= ~FDI_LINK_TRAIN_NONE;
2214 temp |= FDI_LINK_TRAIN_PATTERN_1;
2216 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2221 if (HAS_PCH_CPT(dev))
2222 cpt_phase_pointer_enable(dev, pipe);
2224 for (i = 0; i < 4; i++) {
2225 reg = FDI_TX_CTL(pipe);
2226 temp = I915_READ(reg);
2227 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2228 temp |= snb_b_fdi_train_param[i];
2229 I915_WRITE(reg, temp);
2234 for (retry = 0; retry < 5; retry++) {
2235 reg = FDI_RX_IIR(pipe);
2236 temp = I915_READ(reg);
2237 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2238 if (temp & FDI_RX_BIT_LOCK) {
2239 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2240 DRM_DEBUG_KMS("FDI train 1 done.\n");
2249 DRM_ERROR("FDI train 1 fail!\n");
2252 reg = FDI_TX_CTL(pipe);
2253 temp = I915_READ(reg);
2254 temp &= ~FDI_LINK_TRAIN_NONE;
2255 temp |= FDI_LINK_TRAIN_PATTERN_2;
2257 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2259 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2261 I915_WRITE(reg, temp);
2263 reg = FDI_RX_CTL(pipe);
2264 temp = I915_READ(reg);
2265 if (HAS_PCH_CPT(dev)) {
2266 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2267 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2269 temp &= ~FDI_LINK_TRAIN_NONE;
2270 temp |= FDI_LINK_TRAIN_PATTERN_2;
2272 I915_WRITE(reg, temp);
2277 for (i = 0; i < 4; i++) {
2278 reg = FDI_TX_CTL(pipe);
2279 temp = I915_READ(reg);
2280 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2281 temp |= snb_b_fdi_train_param[i];
2282 I915_WRITE(reg, temp);
2287 for (retry = 0; retry < 5; retry++) {
2288 reg = FDI_RX_IIR(pipe);
2289 temp = I915_READ(reg);
2290 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2291 if (temp & FDI_RX_SYMBOL_LOCK) {
2292 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2293 DRM_DEBUG_KMS("FDI train 2 done.\n");
2302 DRM_ERROR("FDI train 2 fail!\n");
2304 DRM_DEBUG_KMS("FDI train done.\n");
2307 /* Manual link training for Ivy Bridge A0 parts */
2308 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2310 struct drm_device *dev = crtc->dev;
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2313 int pipe = intel_crtc->pipe;
2316 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2318 reg = FDI_RX_IMR(pipe);
2319 temp = I915_READ(reg);
2320 temp &= ~FDI_RX_SYMBOL_LOCK;
2321 temp &= ~FDI_RX_BIT_LOCK;
2322 I915_WRITE(reg, temp);
2327 /* enable CPU FDI TX and PCH FDI RX */
2328 reg = FDI_TX_CTL(pipe);
2329 temp = I915_READ(reg);
2331 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2332 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2333 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2334 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2335 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2336 temp |= FDI_COMPOSITE_SYNC;
2337 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2339 reg = FDI_RX_CTL(pipe);
2340 temp = I915_READ(reg);
2341 temp &= ~FDI_LINK_TRAIN_AUTO;
2342 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2343 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2344 temp |= FDI_COMPOSITE_SYNC;
2345 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2350 if (HAS_PCH_CPT(dev))
2351 cpt_phase_pointer_enable(dev, pipe);
2353 for (i = 0; i < 4; i++) {
2354 reg = FDI_TX_CTL(pipe);
2355 temp = I915_READ(reg);
2356 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2357 temp |= snb_b_fdi_train_param[i];
2358 I915_WRITE(reg, temp);
2363 reg = FDI_RX_IIR(pipe);
2364 temp = I915_READ(reg);
2365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2367 if (temp & FDI_RX_BIT_LOCK ||
2368 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2369 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2370 DRM_DEBUG_KMS("FDI train 1 done.\n");
2375 DRM_ERROR("FDI train 1 fail!\n");
2378 reg = FDI_TX_CTL(pipe);
2379 temp = I915_READ(reg);
2380 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2381 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2382 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2383 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2384 I915_WRITE(reg, temp);
2386 reg = FDI_RX_CTL(pipe);
2387 temp = I915_READ(reg);
2388 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2389 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2390 I915_WRITE(reg, temp);
2395 for (i = 0; i < 4; i++) {
2396 reg = FDI_TX_CTL(pipe);
2397 temp = I915_READ(reg);
2398 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2399 temp |= snb_b_fdi_train_param[i];
2400 I915_WRITE(reg, temp);
2405 reg = FDI_RX_IIR(pipe);
2406 temp = I915_READ(reg);
2407 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2409 if (temp & FDI_RX_SYMBOL_LOCK) {
2410 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2411 DRM_DEBUG_KMS("FDI train 2 done.\n");
2416 DRM_ERROR("FDI train 2 fail!\n");
2418 DRM_DEBUG_KMS("FDI train done.\n");
2421 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2423 struct drm_device *dev = crtc->dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426 int pipe = intel_crtc->pipe;
2429 /* Write the TU size bits so error detection works */
2430 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2431 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2433 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2434 reg = FDI_RX_CTL(pipe);
2435 temp = I915_READ(reg);
2436 temp &= ~((0x7 << 19) | (0x7 << 16));
2437 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2438 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2439 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2444 /* Switch from Rawclk to PCDclk */
2445 temp = I915_READ(reg);
2446 I915_WRITE(reg, temp | FDI_PCDCLK);
2451 /* Enable CPU FDI TX PLL, always on for Ironlake */
2452 reg = FDI_TX_CTL(pipe);
2453 temp = I915_READ(reg);
2454 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2455 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2462 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2464 struct drm_i915_private *dev_priv = dev->dev_private;
2465 u32 flags = I915_READ(SOUTH_CHICKEN1);
2467 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2468 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2469 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2470 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2471 POSTING_READ(SOUTH_CHICKEN1);
2473 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2475 struct drm_device *dev = crtc->dev;
2476 struct drm_i915_private *dev_priv = dev->dev_private;
2477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2478 int pipe = intel_crtc->pipe;
2481 /* disable CPU FDI tx and PCH FDI rx */
2482 reg = FDI_TX_CTL(pipe);
2483 temp = I915_READ(reg);
2484 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2487 reg = FDI_RX_CTL(pipe);
2488 temp = I915_READ(reg);
2489 temp &= ~(0x7 << 16);
2490 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2491 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2496 /* Ironlake workaround, disable clock pointer after downing FDI */
2497 if (HAS_PCH_IBX(dev)) {
2498 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2499 I915_WRITE(FDI_RX_CHICKEN(pipe),
2500 I915_READ(FDI_RX_CHICKEN(pipe) &
2501 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2502 } else if (HAS_PCH_CPT(dev)) {
2503 cpt_phase_pointer_disable(dev, pipe);
2506 /* still set train pattern 1 */
2507 reg = FDI_TX_CTL(pipe);
2508 temp = I915_READ(reg);
2509 temp &= ~FDI_LINK_TRAIN_NONE;
2510 temp |= FDI_LINK_TRAIN_PATTERN_1;
2511 I915_WRITE(reg, temp);
2513 reg = FDI_RX_CTL(pipe);
2514 temp = I915_READ(reg);
2515 if (HAS_PCH_CPT(dev)) {
2516 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2517 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2519 temp &= ~FDI_LINK_TRAIN_NONE;
2520 temp |= FDI_LINK_TRAIN_PATTERN_1;
2522 /* BPC in FDI rx is consistent with that in PIPECONF */
2523 temp &= ~(0x07 << 16);
2524 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2525 I915_WRITE(reg, temp);
2532 * When we disable a pipe, we need to clear any pending scanline wait events
2533 * to avoid hanging the ring, which we assume we are waiting on.
2535 static void intel_clear_scanline_wait(struct drm_device *dev)
2537 struct drm_i915_private *dev_priv = dev->dev_private;
2538 struct intel_ring_buffer *ring;
2542 /* Can't break the hang on i8xx */
2545 ring = LP_RING(dev_priv);
2546 tmp = I915_READ_CTL(ring);
2547 if (tmp & RING_WAIT)
2548 I915_WRITE_CTL(ring, tmp);
2551 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2553 struct drm_device *dev = crtc->dev;
2555 if (crtc->fb == NULL)
2558 mutex_lock(&dev->struct_mutex);
2559 intel_finish_fb(crtc->fb);
2560 mutex_unlock(&dev->struct_mutex);
2563 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2565 struct drm_device *dev = crtc->dev;
2566 struct drm_mode_config *mode_config = &dev->mode_config;
2567 struct intel_encoder *encoder;
2570 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2571 * must be driven by its own crtc; no sharing is possible.
2573 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2574 if (encoder->base.crtc != crtc)
2577 switch (encoder->type) {
2578 case INTEL_OUTPUT_EDP:
2579 if (!intel_encoder_is_pch_edp(&encoder->base))
2589 * Enable PCH resources required for PCH ports:
2591 * - FDI training & RX/TX
2592 * - update transcoder timings
2593 * - DP transcoding bits
2596 static void ironlake_pch_enable(struct drm_crtc *crtc)
2598 struct drm_device *dev = crtc->dev;
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 int pipe = intel_crtc->pipe;
2604 /* For PCH output, training FDI link */
2605 dev_priv->display.fdi_link_train(crtc);
2607 intel_enable_pch_pll(intel_crtc);
2609 if (HAS_PCH_CPT(dev)) {
2612 temp = I915_READ(PCH_DPLL_SEL);
2616 temp |= TRANSA_DPLL_ENABLE;
2617 sel = TRANSA_DPLLB_SEL;
2620 temp |= TRANSB_DPLL_ENABLE;
2621 sel = TRANSB_DPLLB_SEL;
2624 temp |= TRANSC_DPLL_ENABLE;
2625 sel = TRANSC_DPLLB_SEL;
2628 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2632 I915_WRITE(PCH_DPLL_SEL, temp);
2635 /* set transcoder timing, panel must allow it */
2636 assert_panel_unlocked(dev_priv, pipe);
2637 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2638 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2639 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2641 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2642 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2643 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2644 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2646 intel_fdi_normal_train(crtc);
2648 /* For PCH DP, enable TRANS_DP_CTL */
2649 if (HAS_PCH_CPT(dev) &&
2650 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2651 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2652 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2653 reg = TRANS_DP_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2656 TRANS_DP_SYNC_MASK |
2658 temp |= (TRANS_DP_OUTPUT_ENABLE |
2659 TRANS_DP_ENH_FRAMING);
2660 temp |= bpc << 9; /* same format but at 11:9 */
2662 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2663 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2664 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2665 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2667 switch (intel_trans_dp_port_sel(crtc)) {
2669 temp |= TRANS_DP_PORT_SEL_B;
2672 temp |= TRANS_DP_PORT_SEL_C;
2675 temp |= TRANS_DP_PORT_SEL_D;
2678 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2679 temp |= TRANS_DP_PORT_SEL_B;
2683 I915_WRITE(reg, temp);
2686 intel_enable_transcoder(dev_priv, pipe);
2689 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2691 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2696 if (pll->refcount == 0) {
2697 WARN(1, "bad PCH PLL refcount\n");
2702 intel_crtc->pch_pll = NULL;
2705 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2707 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2708 struct intel_pch_pll *pll;
2711 pll = intel_crtc->pch_pll;
2713 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2714 intel_crtc->base.base.id, pll->pll_reg);
2718 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2719 pll = &dev_priv->pch_plls[i];
2721 /* Only want to check enabled timings first */
2722 if (pll->refcount == 0)
2725 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2726 fp == I915_READ(pll->fp0_reg)) {
2727 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2728 intel_crtc->base.base.id,
2729 pll->pll_reg, pll->refcount, pll->active);
2735 /* Ok no matching timings, maybe there's a free one? */
2736 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2737 pll = &dev_priv->pch_plls[i];
2738 if (pll->refcount == 0) {
2739 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2740 intel_crtc->base.base.id, pll->pll_reg);
2748 intel_crtc->pch_pll = pll;
2750 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2751 prepare: /* separate function? */
2752 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2753 I915_WRITE(pll->fp0_reg, fp);
2754 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2756 POSTING_READ(pll->pll_reg);
2762 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2764 struct drm_i915_private *dev_priv = dev->dev_private;
2765 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2768 temp = I915_READ(dslreg);
2770 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2771 /* Without this, mode sets may fail silently on FDI */
2772 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2774 I915_WRITE(tc2reg, 0);
2775 if (wait_for(I915_READ(dslreg) != temp, 5))
2776 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2780 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2782 struct drm_device *dev = crtc->dev;
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2785 int pipe = intel_crtc->pipe;
2786 int plane = intel_crtc->plane;
2790 if (intel_crtc->active)
2793 intel_crtc->active = true;
2794 intel_update_watermarks(dev);
2796 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2797 temp = I915_READ(PCH_LVDS);
2798 if ((temp & LVDS_PORT_EN) == 0)
2799 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2802 is_pch_port = intel_crtc_driving_pch(crtc);
2805 ironlake_fdi_pll_enable(crtc);
2807 ironlake_fdi_disable(crtc);
2809 /* Enable panel fitting for LVDS */
2810 if (dev_priv->pch_pf_size &&
2811 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2812 /* Force use of hard-coded filter coefficients
2813 * as some pre-programmed values are broken,
2816 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2817 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2818 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2822 * On ILK+ LUT must be loaded before the pipe is running but with
2825 intel_crtc_load_lut(crtc);
2827 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2828 intel_enable_plane(dev_priv, plane, pipe);
2831 ironlake_pch_enable(crtc);
2833 mutex_lock(&dev->struct_mutex);
2834 intel_update_fbc(dev);
2835 mutex_unlock(&dev->struct_mutex);
2837 intel_crtc_update_cursor(crtc, true);
2840 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2842 struct drm_device *dev = crtc->dev;
2843 struct drm_i915_private *dev_priv = dev->dev_private;
2844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2845 int pipe = intel_crtc->pipe;
2846 int plane = intel_crtc->plane;
2849 if (!intel_crtc->active)
2852 intel_crtc_wait_for_pending_flips(crtc);
2853 drm_vblank_off(dev, pipe);
2854 intel_crtc_update_cursor(crtc, false);
2856 intel_disable_plane(dev_priv, plane, pipe);
2858 if (dev_priv->cfb_plane == plane)
2859 intel_disable_fbc(dev);
2861 intel_disable_pipe(dev_priv, pipe);
2864 I915_WRITE(PF_CTL(pipe), 0);
2865 I915_WRITE(PF_WIN_SZ(pipe), 0);
2867 ironlake_fdi_disable(crtc);
2869 /* This is a horrible layering violation; we should be doing this in
2870 * the connector/encoder ->prepare instead, but we don't always have
2871 * enough information there about the config to know whether it will
2872 * actually be necessary or just cause undesired flicker.
2874 intel_disable_pch_ports(dev_priv, pipe);
2876 intel_disable_transcoder(dev_priv, pipe);
2878 if (HAS_PCH_CPT(dev)) {
2879 /* disable TRANS_DP_CTL */
2880 reg = TRANS_DP_CTL(pipe);
2881 temp = I915_READ(reg);
2882 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2883 temp |= TRANS_DP_PORT_SEL_NONE;
2884 I915_WRITE(reg, temp);
2886 /* disable DPLL_SEL */
2887 temp = I915_READ(PCH_DPLL_SEL);
2890 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2893 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2896 /* C shares PLL A or B */
2897 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2902 I915_WRITE(PCH_DPLL_SEL, temp);
2905 /* disable PCH DPLL */
2906 intel_disable_pch_pll(intel_crtc);
2908 /* Switch from PCDclk to Rawclk */
2909 reg = FDI_RX_CTL(pipe);
2910 temp = I915_READ(reg);
2911 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2913 /* Disable CPU FDI TX PLL */
2914 reg = FDI_TX_CTL(pipe);
2915 temp = I915_READ(reg);
2916 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2921 reg = FDI_RX_CTL(pipe);
2922 temp = I915_READ(reg);
2923 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2925 /* Wait for the clocks to turn off. */
2929 intel_crtc->active = false;
2930 intel_update_watermarks(dev);
2932 mutex_lock(&dev->struct_mutex);
2933 intel_update_fbc(dev);
2934 intel_clear_scanline_wait(dev);
2935 mutex_unlock(&dev->struct_mutex);
2938 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2941 int pipe = intel_crtc->pipe;
2942 int plane = intel_crtc->plane;
2944 /* XXX: When our outputs are all unaware of DPMS modes other than off
2945 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2948 case DRM_MODE_DPMS_ON:
2949 case DRM_MODE_DPMS_STANDBY:
2950 case DRM_MODE_DPMS_SUSPEND:
2951 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2952 ironlake_crtc_enable(crtc);
2955 case DRM_MODE_DPMS_OFF:
2956 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2957 ironlake_crtc_disable(crtc);
2962 static void ironlake_crtc_off(struct drm_crtc *crtc)
2964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965 intel_put_pch_pll(intel_crtc);
2968 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2970 if (!enable && intel_crtc->overlay) {
2971 struct drm_device *dev = intel_crtc->base.dev;
2972 struct drm_i915_private *dev_priv = dev->dev_private;
2974 mutex_lock(&dev->struct_mutex);
2975 dev_priv->mm.interruptible = false;
2976 (void) intel_overlay_switch_off(intel_crtc->overlay);
2977 dev_priv->mm.interruptible = true;
2978 mutex_unlock(&dev->struct_mutex);
2981 /* Let userspace switch the overlay on again. In most cases userspace
2982 * has to recompute where to put it anyway.
2986 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2988 struct drm_device *dev = crtc->dev;
2989 struct drm_i915_private *dev_priv = dev->dev_private;
2990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2991 int pipe = intel_crtc->pipe;
2992 int plane = intel_crtc->plane;
2994 if (intel_crtc->active)
2997 intel_crtc->active = true;
2998 intel_update_watermarks(dev);
3000 intel_enable_pll(dev_priv, pipe);
3001 intel_enable_pipe(dev_priv, pipe, false);
3002 intel_enable_plane(dev_priv, plane, pipe);
3004 intel_crtc_load_lut(crtc);
3005 intel_update_fbc(dev);
3007 /* Give the overlay scaler a chance to enable if it's on this pipe */
3008 intel_crtc_dpms_overlay(intel_crtc, true);
3009 intel_crtc_update_cursor(crtc, true);
3012 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3014 struct drm_device *dev = crtc->dev;
3015 struct drm_i915_private *dev_priv = dev->dev_private;
3016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3017 int pipe = intel_crtc->pipe;
3018 int plane = intel_crtc->plane;
3020 if (!intel_crtc->active)
3023 /* Give the overlay scaler a chance to disable if it's on this pipe */
3024 intel_crtc_wait_for_pending_flips(crtc);
3025 drm_vblank_off(dev, pipe);
3026 intel_crtc_dpms_overlay(intel_crtc, false);
3027 intel_crtc_update_cursor(crtc, false);
3029 if (dev_priv->cfb_plane == plane)
3030 intel_disable_fbc(dev);
3032 intel_disable_plane(dev_priv, plane, pipe);
3033 intel_disable_pipe(dev_priv, pipe);
3034 intel_disable_pll(dev_priv, pipe);
3036 intel_crtc->active = false;
3037 intel_update_fbc(dev);
3038 intel_update_watermarks(dev);
3039 intel_clear_scanline_wait(dev);
3042 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3044 /* XXX: When our outputs are all unaware of DPMS modes other than off
3045 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3048 case DRM_MODE_DPMS_ON:
3049 case DRM_MODE_DPMS_STANDBY:
3050 case DRM_MODE_DPMS_SUSPEND:
3051 i9xx_crtc_enable(crtc);
3053 case DRM_MODE_DPMS_OFF:
3054 i9xx_crtc_disable(crtc);
3059 static void i9xx_crtc_off(struct drm_crtc *crtc)
3064 * Sets the power management mode of the pipe and plane.
3066 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3068 struct drm_device *dev = crtc->dev;
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 struct drm_i915_master_private *master_priv;
3071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3072 int pipe = intel_crtc->pipe;
3075 if (intel_crtc->dpms_mode == mode)
3078 intel_crtc->dpms_mode = mode;
3080 dev_priv->display.dpms(crtc, mode);
3082 if (!dev->primary->master)
3085 master_priv = dev->primary->master->driver_priv;
3086 if (!master_priv->sarea_priv)
3089 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3093 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3094 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3097 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3098 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3101 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3106 static void intel_crtc_disable(struct drm_crtc *crtc)
3108 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3109 struct drm_device *dev = crtc->dev;
3110 struct drm_i915_private *dev_priv = dev->dev_private;
3112 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3113 dev_priv->display.off(crtc);
3115 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3116 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3119 mutex_lock(&dev->struct_mutex);
3120 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3121 mutex_unlock(&dev->struct_mutex);
3125 /* Prepare for a mode set.
3127 * Note we could be a lot smarter here. We need to figure out which outputs
3128 * will be enabled, which disabled (in short, how the config will changes)
3129 * and perform the minimum necessary steps to accomplish that, e.g. updating
3130 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3131 * panel fitting is in the proper state, etc.
3133 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3135 i9xx_crtc_disable(crtc);
3138 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3140 i9xx_crtc_enable(crtc);
3143 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3145 ironlake_crtc_disable(crtc);
3148 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3150 ironlake_crtc_enable(crtc);
3153 void intel_encoder_prepare(struct drm_encoder *encoder)
3155 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3156 /* lvds has its own version of prepare see intel_lvds_prepare */
3157 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3160 void intel_encoder_commit(struct drm_encoder *encoder)
3162 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3163 struct drm_device *dev = encoder->dev;
3164 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3165 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3167 /* lvds has its own version of commit see intel_lvds_commit */
3168 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3170 if (HAS_PCH_CPT(dev))
3171 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3174 void intel_encoder_destroy(struct drm_encoder *encoder)
3176 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3178 drm_encoder_cleanup(encoder);
3179 kfree(intel_encoder);
3182 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3183 struct drm_display_mode *mode,
3184 struct drm_display_mode *adjusted_mode)
3186 struct drm_device *dev = crtc->dev;
3188 if (HAS_PCH_SPLIT(dev)) {
3189 /* FDI link clock is fixed at 2.7G */
3190 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3194 /* All interlaced capable intel hw wants timings in frames. */
3195 drm_mode_set_crtcinfo(adjusted_mode, 0);
3200 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3202 return 400000; /* FIXME */
3205 static int i945_get_display_clock_speed(struct drm_device *dev)
3210 static int i915_get_display_clock_speed(struct drm_device *dev)
3215 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3220 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3224 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3226 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3229 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3230 case GC_DISPLAY_CLOCK_333_MHZ:
3233 case GC_DISPLAY_CLOCK_190_200_MHZ:
3239 static int i865_get_display_clock_speed(struct drm_device *dev)
3244 static int i855_get_display_clock_speed(struct drm_device *dev)
3247 /* Assume that the hardware is in the high speed state. This
3248 * should be the default.
3250 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3251 case GC_CLOCK_133_200:
3252 case GC_CLOCK_100_200:
3254 case GC_CLOCK_166_250:
3256 case GC_CLOCK_100_133:
3260 /* Shouldn't happen */
3264 static int i830_get_display_clock_speed(struct drm_device *dev)
3278 fdi_reduce_ratio(u32 *num, u32 *den)
3280 while (*num > 0xffffff || *den > 0xffffff) {
3287 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3288 int link_clock, struct fdi_m_n *m_n)
3290 m_n->tu = 64; /* default size */
3292 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3293 m_n->gmch_m = bits_per_pixel * pixel_clock;
3294 m_n->gmch_n = link_clock * nlanes * 8;
3295 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3297 m_n->link_m = pixel_clock;
3298 m_n->link_n = link_clock;
3299 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3302 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3304 if (i915_panel_use_ssc >= 0)
3305 return i915_panel_use_ssc != 0;
3306 return dev_priv->lvds_use_ssc
3307 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3311 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3312 * @crtc: CRTC structure
3313 * @mode: requested mode
3315 * A pipe may be connected to one or more outputs. Based on the depth of the
3316 * attached framebuffer, choose a good color depth to use on the pipe.
3318 * If possible, match the pipe depth to the fb depth. In some cases, this
3319 * isn't ideal, because the connected output supports a lesser or restricted
3320 * set of depths. Resolve that here:
3321 * LVDS typically supports only 6bpc, so clamp down in that case
3322 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3323 * Displays may support a restricted set as well, check EDID and clamp as
3325 * DP may want to dither down to 6bpc to fit larger modes
3328 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3329 * true if they don't match).
3331 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3332 unsigned int *pipe_bpp,
3333 struct drm_display_mode *mode)
3335 struct drm_device *dev = crtc->dev;
3336 struct drm_i915_private *dev_priv = dev->dev_private;
3337 struct drm_encoder *encoder;
3338 struct drm_connector *connector;
3339 unsigned int display_bpc = UINT_MAX, bpc;
3341 /* Walk the encoders & connectors on this crtc, get min bpc */
3342 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3343 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3345 if (encoder->crtc != crtc)
3348 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3349 unsigned int lvds_bpc;
3351 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3357 if (lvds_bpc < display_bpc) {
3358 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3359 display_bpc = lvds_bpc;
3364 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3365 /* Use VBT settings if we have an eDP panel */
3366 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3368 if (edp_bpc < display_bpc) {
3369 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3370 display_bpc = edp_bpc;
3375 /* Not one of the known troublemakers, check the EDID */
3376 list_for_each_entry(connector, &dev->mode_config.connector_list,
3378 if (connector->encoder != encoder)
3381 /* Don't use an invalid EDID bpc value */
3382 if (connector->display_info.bpc &&
3383 connector->display_info.bpc < display_bpc) {
3384 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3385 display_bpc = connector->display_info.bpc;
3390 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3391 * through, clamp it down. (Note: >12bpc will be caught below.)
3393 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3394 if (display_bpc > 8 && display_bpc < 12) {
3395 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3398 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3404 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3405 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3410 * We could just drive the pipe at the highest bpc all the time and
3411 * enable dithering as needed, but that costs bandwidth. So choose
3412 * the minimum value that expresses the full color range of the fb but
3413 * also stays within the max display bpc discovered above.
3416 switch (crtc->fb->depth) {
3418 bpc = 8; /* since we go through a colormap */
3422 bpc = 6; /* min is 18bpp */
3434 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3435 bpc = min((unsigned int)8, display_bpc);
3439 display_bpc = min(display_bpc, bpc);
3441 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3444 *pipe_bpp = display_bpc * 3;
3446 return display_bpc != bpc;
3449 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3451 struct drm_device *dev = crtc->dev;
3452 struct drm_i915_private *dev_priv = dev->dev_private;
3455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3456 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3457 refclk = dev_priv->lvds_ssc_freq * 1000;
3458 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3460 } else if (!IS_GEN2(dev)) {
3469 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3470 intel_clock_t *clock)
3472 /* SDVO TV has fixed PLL values depend on its clock range,
3473 this mirrors vbios setting. */
3474 if (adjusted_mode->clock >= 100000
3475 && adjusted_mode->clock < 140500) {
3481 } else if (adjusted_mode->clock >= 140500
3482 && adjusted_mode->clock <= 200000) {
3491 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3492 intel_clock_t *clock,
3493 intel_clock_t *reduced_clock)
3495 struct drm_device *dev = crtc->dev;
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3498 int pipe = intel_crtc->pipe;
3501 if (IS_PINEVIEW(dev)) {
3502 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3504 fp2 = (1 << reduced_clock->n) << 16 |
3505 reduced_clock->m1 << 8 | reduced_clock->m2;
3507 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3509 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3513 I915_WRITE(FP0(pipe), fp);
3515 intel_crtc->lowfreq_avail = false;
3516 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3517 reduced_clock && i915_powersave) {
3518 I915_WRITE(FP1(pipe), fp2);
3519 intel_crtc->lowfreq_avail = true;
3521 I915_WRITE(FP1(pipe), fp);
3525 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3526 struct drm_display_mode *adjusted_mode)
3528 struct drm_device *dev = crtc->dev;
3529 struct drm_i915_private *dev_priv = dev->dev_private;
3530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3531 int pipe = intel_crtc->pipe;
3534 temp = I915_READ(LVDS);
3535 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3537 temp |= LVDS_PIPEB_SELECT;
3539 temp &= ~LVDS_PIPEB_SELECT;
3541 /* set the corresponsding LVDS_BORDER bit */
3542 temp |= dev_priv->lvds_border_bits;
3543 /* Set the B0-B3 data pairs corresponding to whether we're going to
3544 * set the DPLLs for dual-channel mode or not.
3547 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3549 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3551 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3552 * appropriately here, but we need to look more thoroughly into how
3553 * panels behave in the two modes.
3555 /* set the dithering flag on LVDS as needed */
3556 if (INTEL_INFO(dev)->gen >= 4) {
3557 if (dev_priv->lvds_dither)
3558 temp |= LVDS_ENABLE_DITHER;
3560 temp &= ~LVDS_ENABLE_DITHER;
3562 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3563 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3564 temp |= LVDS_HSYNC_POLARITY;
3565 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3566 temp |= LVDS_VSYNC_POLARITY;
3567 I915_WRITE(LVDS, temp);
3570 static void i9xx_update_pll(struct drm_crtc *crtc,
3571 struct drm_display_mode *mode,
3572 struct drm_display_mode *adjusted_mode,
3573 intel_clock_t *clock, intel_clock_t *reduced_clock,
3576 struct drm_device *dev = crtc->dev;
3577 struct drm_i915_private *dev_priv = dev->dev_private;
3578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3579 int pipe = intel_crtc->pipe;
3583 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3584 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3586 dpll = DPLL_VGA_MODE_DIS;
3588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3589 dpll |= DPLLB_MODE_LVDS;
3591 dpll |= DPLLB_MODE_DAC_SERIAL;
3593 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3594 if (pixel_multiplier > 1) {
3595 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3596 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3598 dpll |= DPLL_DVO_HIGH_SPEED;
3600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3601 dpll |= DPLL_DVO_HIGH_SPEED;
3603 /* compute bitmask from p1 value */
3604 if (IS_PINEVIEW(dev))
3605 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3607 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3608 if (IS_G4X(dev) && reduced_clock)
3609 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3611 switch (clock->p2) {
3613 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3616 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3619 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3622 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3625 if (INTEL_INFO(dev)->gen >= 4)
3626 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3628 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3629 dpll |= PLL_REF_INPUT_TVCLKINBC;
3630 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3631 /* XXX: just matching BIOS for now */
3632 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3634 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3635 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3636 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3638 dpll |= PLL_REF_INPUT_DREFCLK;
3640 dpll |= DPLL_VCO_ENABLE;
3641 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3642 POSTING_READ(DPLL(pipe));
3645 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3646 * This is an exception to the general rule that mode_set doesn't turn
3649 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3650 intel_update_lvds(crtc, clock, adjusted_mode);
3652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3653 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3655 I915_WRITE(DPLL(pipe), dpll);
3657 /* Wait for the clocks to stabilize. */
3658 POSTING_READ(DPLL(pipe));
3661 if (INTEL_INFO(dev)->gen >= 4) {
3664 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3666 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3670 I915_WRITE(DPLL_MD(pipe), temp);
3672 /* The pixel multiplier can only be updated once the
3673 * DPLL is enabled and the clocks are stable.
3675 * So write it again.
3677 I915_WRITE(DPLL(pipe), dpll);
3681 static void i8xx_update_pll(struct drm_crtc *crtc,
3682 struct drm_display_mode *adjusted_mode,
3683 intel_clock_t *clock,
3686 struct drm_device *dev = crtc->dev;
3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3689 int pipe = intel_crtc->pipe;
3692 dpll = DPLL_VGA_MODE_DIS;
3694 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3695 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3698 dpll |= PLL_P1_DIVIDE_BY_TWO;
3700 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3702 dpll |= PLL_P2_DIVIDE_BY_4;
3705 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3706 /* XXX: just matching BIOS for now */
3707 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3709 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3710 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3711 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3713 dpll |= PLL_REF_INPUT_DREFCLK;
3715 dpll |= DPLL_VCO_ENABLE;
3716 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3717 POSTING_READ(DPLL(pipe));
3720 I915_WRITE(DPLL(pipe), dpll);
3722 /* Wait for the clocks to stabilize. */
3723 POSTING_READ(DPLL(pipe));
3726 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3727 * This is an exception to the general rule that mode_set doesn't turn
3730 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3731 intel_update_lvds(crtc, clock, adjusted_mode);
3733 /* The pixel multiplier can only be updated once the
3734 * DPLL is enabled and the clocks are stable.
3736 * So write it again.
3738 I915_WRITE(DPLL(pipe), dpll);
3741 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3742 struct drm_display_mode *mode,
3743 struct drm_display_mode *adjusted_mode,
3745 struct drm_framebuffer *old_fb)
3747 struct drm_device *dev = crtc->dev;
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3750 int pipe = intel_crtc->pipe;
3751 int plane = intel_crtc->plane;
3752 int refclk, num_connectors = 0;
3753 intel_clock_t clock, reduced_clock;
3754 u32 dspcntr, pipeconf, vsyncshift;
3755 bool ok, has_reduced_clock = false, is_sdvo = false;
3756 bool is_lvds = false, is_tv = false, is_dp = false;
3757 struct drm_mode_config *mode_config = &dev->mode_config;
3758 struct intel_encoder *encoder;
3759 const intel_limit_t *limit;
3762 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3763 if (encoder->base.crtc != crtc)
3766 switch (encoder->type) {
3767 case INTEL_OUTPUT_LVDS:
3770 case INTEL_OUTPUT_SDVO:
3771 case INTEL_OUTPUT_HDMI:
3773 if (encoder->needs_tv_clock)
3776 case INTEL_OUTPUT_TVOUT:
3779 case INTEL_OUTPUT_DISPLAYPORT:
3787 refclk = i9xx_get_refclk(crtc, num_connectors);
3790 * Returns a set of divisors for the desired target clock with the given
3791 * refclk, or FALSE. The returned values represent the clock equation:
3792 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3794 limit = intel_limit(crtc, refclk);
3795 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3798 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3802 /* Ensure that the cursor is valid for the new mode before changing... */
3803 intel_crtc_update_cursor(crtc, true);
3805 if (is_lvds && dev_priv->lvds_downclock_avail) {
3807 * Ensure we match the reduced clock's P to the target clock.
3808 * If the clocks don't match, we can't switch the display clock
3809 * by using the FP0/FP1. In such case we will disable the LVDS
3810 * downclock feature.
3812 has_reduced_clock = limit->find_pll(limit, crtc,
3813 dev_priv->lvds_downclock,
3819 if (is_sdvo && is_tv)
3820 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
3822 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3823 &reduced_clock : NULL);
3826 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
3828 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3829 has_reduced_clock ? &reduced_clock : NULL,
3832 /* setup pipeconf */
3833 pipeconf = I915_READ(PIPECONF(pipe));
3835 /* Set up the display plane register */
3836 dspcntr = DISPPLANE_GAMMA_ENABLE;
3839 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3841 dspcntr |= DISPPLANE_SEL_PIPE_B;
3843 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3844 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3847 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3851 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3852 pipeconf |= PIPECONF_DOUBLE_WIDE;
3854 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3857 /* default to 8bpc */
3858 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3860 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3861 pipeconf |= PIPECONF_BPP_6 |
3862 PIPECONF_DITHER_EN |
3863 PIPECONF_DITHER_TYPE_SP;
3867 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3868 drm_mode_debug_printmodeline(mode);
3870 if (HAS_PIPE_CXSR(dev)) {
3871 if (intel_crtc->lowfreq_avail) {
3872 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3873 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3875 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3876 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3880 pipeconf &= ~PIPECONF_INTERLACE_MASK;
3881 if (!IS_GEN2(dev) &&
3882 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3883 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3884 /* the chip adds 2 halflines automatically */
3885 adjusted_mode->crtc_vtotal -= 1;
3886 adjusted_mode->crtc_vblank_end -= 1;
3887 vsyncshift = adjusted_mode->crtc_hsync_start
3888 - adjusted_mode->crtc_htotal/2;
3890 pipeconf |= PIPECONF_PROGRESSIVE;
3895 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
3897 I915_WRITE(HTOTAL(pipe),
3898 (adjusted_mode->crtc_hdisplay - 1) |
3899 ((adjusted_mode->crtc_htotal - 1) << 16));
3900 I915_WRITE(HBLANK(pipe),
3901 (adjusted_mode->crtc_hblank_start - 1) |
3902 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3903 I915_WRITE(HSYNC(pipe),
3904 (adjusted_mode->crtc_hsync_start - 1) |
3905 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3907 I915_WRITE(VTOTAL(pipe),
3908 (adjusted_mode->crtc_vdisplay - 1) |
3909 ((adjusted_mode->crtc_vtotal - 1) << 16));
3910 I915_WRITE(VBLANK(pipe),
3911 (adjusted_mode->crtc_vblank_start - 1) |
3912 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3913 I915_WRITE(VSYNC(pipe),
3914 (adjusted_mode->crtc_vsync_start - 1) |
3915 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3917 /* pipesrc and dspsize control the size that is scaled from,
3918 * which should always be the user's requested size.
3920 I915_WRITE(DSPSIZE(plane),
3921 ((mode->vdisplay - 1) << 16) |
3922 (mode->hdisplay - 1));
3923 I915_WRITE(DSPPOS(plane), 0);
3924 I915_WRITE(PIPESRC(pipe),
3925 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3927 I915_WRITE(PIPECONF(pipe), pipeconf);
3928 POSTING_READ(PIPECONF(pipe));
3929 intel_enable_pipe(dev_priv, pipe, false);
3931 intel_wait_for_vblank(dev, pipe);
3933 I915_WRITE(DSPCNTR(plane), dspcntr);
3934 POSTING_READ(DSPCNTR(plane));
3935 intel_enable_plane(dev_priv, plane, pipe);
3937 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3939 intel_update_watermarks(dev);
3945 * Initialize reference clocks when the driver loads
3947 void ironlake_init_pch_refclk(struct drm_device *dev)
3949 struct drm_i915_private *dev_priv = dev->dev_private;
3950 struct drm_mode_config *mode_config = &dev->mode_config;
3951 struct intel_encoder *encoder;
3953 bool has_lvds = false;
3954 bool has_cpu_edp = false;
3955 bool has_pch_edp = false;
3956 bool has_panel = false;
3957 bool has_ck505 = false;
3958 bool can_ssc = false;
3960 /* We need to take the global config into account */
3961 list_for_each_entry(encoder, &mode_config->encoder_list,
3963 switch (encoder->type) {
3964 case INTEL_OUTPUT_LVDS:
3968 case INTEL_OUTPUT_EDP:
3970 if (intel_encoder_is_pch_edp(&encoder->base))
3978 if (HAS_PCH_IBX(dev)) {
3979 has_ck505 = dev_priv->display_clock_mode;
3980 can_ssc = has_ck505;
3986 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
3987 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
3990 /* Ironlake: try to setup display ref clock before DPLL
3991 * enabling. This is only under driver's control after
3992 * PCH B stepping, previous chipset stepping should be
3993 * ignoring this setting.
3995 temp = I915_READ(PCH_DREF_CONTROL);
3996 /* Always enable nonspread source */
3997 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4000 temp |= DREF_NONSPREAD_CK505_ENABLE;
4002 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4005 temp &= ~DREF_SSC_SOURCE_MASK;
4006 temp |= DREF_SSC_SOURCE_ENABLE;
4008 /* SSC must be turned on before enabling the CPU output */
4009 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4010 DRM_DEBUG_KMS("Using SSC on panel\n");
4011 temp |= DREF_SSC1_ENABLE;
4013 temp &= ~DREF_SSC1_ENABLE;
4015 /* Get SSC going before enabling the outputs */
4016 I915_WRITE(PCH_DREF_CONTROL, temp);
4017 POSTING_READ(PCH_DREF_CONTROL);
4020 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4022 /* Enable CPU source on CPU attached eDP */
4024 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4025 DRM_DEBUG_KMS("Using SSC on eDP\n");
4026 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4029 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4031 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4033 I915_WRITE(PCH_DREF_CONTROL, temp);
4034 POSTING_READ(PCH_DREF_CONTROL);
4037 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4039 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4041 /* Turn off CPU output */
4042 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4044 I915_WRITE(PCH_DREF_CONTROL, temp);
4045 POSTING_READ(PCH_DREF_CONTROL);
4048 /* Turn off the SSC source */
4049 temp &= ~DREF_SSC_SOURCE_MASK;
4050 temp |= DREF_SSC_SOURCE_DISABLE;
4053 temp &= ~ DREF_SSC1_ENABLE;
4055 I915_WRITE(PCH_DREF_CONTROL, temp);
4056 POSTING_READ(PCH_DREF_CONTROL);
4061 static int ironlake_get_refclk(struct drm_crtc *crtc)
4063 struct drm_device *dev = crtc->dev;
4064 struct drm_i915_private *dev_priv = dev->dev_private;
4065 struct intel_encoder *encoder;
4066 struct drm_mode_config *mode_config = &dev->mode_config;
4067 struct intel_encoder *edp_encoder = NULL;
4068 int num_connectors = 0;
4069 bool is_lvds = false;
4071 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4072 if (encoder->base.crtc != crtc)
4075 switch (encoder->type) {
4076 case INTEL_OUTPUT_LVDS:
4079 case INTEL_OUTPUT_EDP:
4080 edp_encoder = encoder;
4086 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4087 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4088 dev_priv->lvds_ssc_freq);
4089 return dev_priv->lvds_ssc_freq * 1000;
4095 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4096 struct drm_display_mode *mode,
4097 struct drm_display_mode *adjusted_mode,
4099 struct drm_framebuffer *old_fb)
4101 struct drm_device *dev = crtc->dev;
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104 int pipe = intel_crtc->pipe;
4105 int plane = intel_crtc->plane;
4106 int refclk, num_connectors = 0;
4107 intel_clock_t clock, reduced_clock;
4108 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4109 bool ok, has_reduced_clock = false, is_sdvo = false;
4110 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4111 struct drm_mode_config *mode_config = &dev->mode_config;
4112 struct intel_encoder *encoder, *edp_encoder = NULL;
4113 const intel_limit_t *limit;
4115 struct fdi_m_n m_n = {0};
4117 int target_clock, pixel_multiplier, lane, link_bw, factor;
4118 unsigned int pipe_bpp;
4120 bool is_cpu_edp = false, is_pch_edp = false;
4122 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4123 if (encoder->base.crtc != crtc)
4126 switch (encoder->type) {
4127 case INTEL_OUTPUT_LVDS:
4130 case INTEL_OUTPUT_SDVO:
4131 case INTEL_OUTPUT_HDMI:
4133 if (encoder->needs_tv_clock)
4136 case INTEL_OUTPUT_TVOUT:
4139 case INTEL_OUTPUT_ANALOG:
4142 case INTEL_OUTPUT_DISPLAYPORT:
4145 case INTEL_OUTPUT_EDP:
4147 if (intel_encoder_is_pch_edp(&encoder->base))
4151 edp_encoder = encoder;
4158 refclk = ironlake_get_refclk(crtc);
4161 * Returns a set of divisors for the desired target clock with the given
4162 * refclk, or FALSE. The returned values represent the clock equation:
4163 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4165 limit = intel_limit(crtc, refclk);
4166 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4169 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4173 /* Ensure that the cursor is valid for the new mode before changing... */
4174 intel_crtc_update_cursor(crtc, true);
4176 if (is_lvds && dev_priv->lvds_downclock_avail) {
4178 * Ensure we match the reduced clock's P to the target clock.
4179 * If the clocks don't match, we can't switch the display clock
4180 * by using the FP0/FP1. In such case we will disable the LVDS
4181 * downclock feature.
4183 has_reduced_clock = limit->find_pll(limit, crtc,
4184 dev_priv->lvds_downclock,
4189 /* SDVO TV has fixed PLL values depend on its clock range,
4190 this mirrors vbios setting. */
4191 if (is_sdvo && is_tv) {
4192 if (adjusted_mode->clock >= 100000
4193 && adjusted_mode->clock < 140500) {
4199 } else if (adjusted_mode->clock >= 140500
4200 && adjusted_mode->clock <= 200000) {
4210 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4212 /* CPU eDP doesn't require FDI link, so just set DP M/N
4213 according to current link config */
4215 target_clock = mode->clock;
4216 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4218 /* [e]DP over FDI requires target mode clock
4219 instead of link clock */
4221 target_clock = mode->clock;
4223 target_clock = adjusted_mode->clock;
4225 /* FDI is a binary signal running at ~2.7GHz, encoding
4226 * each output octet as 10 bits. The actual frequency
4227 * is stored as a divider into a 100MHz clock, and the
4228 * mode pixel clock is stored in units of 1KHz.
4229 * Hence the bw of each lane in terms of the mode signal
4232 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4235 /* determine panel color depth */
4236 temp = I915_READ(PIPECONF(pipe));
4237 temp &= ~PIPE_BPC_MASK;
4238 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4253 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4260 intel_crtc->bpp = pipe_bpp;
4261 I915_WRITE(PIPECONF(pipe), temp);
4265 * Account for spread spectrum to avoid
4266 * oversubscribing the link. Max center spread
4267 * is 2.5%; use 5% for safety's sake.
4269 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4270 lane = bps / (link_bw * 8) + 1;
4273 intel_crtc->fdi_lanes = lane;
4275 if (pixel_multiplier > 1)
4276 link_bw *= pixel_multiplier;
4277 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4280 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4281 if (has_reduced_clock)
4282 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4285 /* Enable autotuning of the PLL clock (if permissible) */
4288 if ((intel_panel_use_ssc(dev_priv) &&
4289 dev_priv->lvds_ssc_freq == 100) ||
4290 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4292 } else if (is_sdvo && is_tv)
4295 if (clock.m < factor * clock.n)
4301 dpll |= DPLLB_MODE_LVDS;
4303 dpll |= DPLLB_MODE_DAC_SERIAL;
4305 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4306 if (pixel_multiplier > 1) {
4307 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4309 dpll |= DPLL_DVO_HIGH_SPEED;
4311 if (is_dp && !is_cpu_edp)
4312 dpll |= DPLL_DVO_HIGH_SPEED;
4314 /* compute bitmask from p1 value */
4315 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4317 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4321 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4324 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4327 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4330 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4334 if (is_sdvo && is_tv)
4335 dpll |= PLL_REF_INPUT_TVCLKINBC;
4337 /* XXX: just matching BIOS for now */
4338 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4340 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4341 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4343 dpll |= PLL_REF_INPUT_DREFCLK;
4345 /* setup pipeconf */
4346 pipeconf = I915_READ(PIPECONF(pipe));
4348 /* Set up the display plane register */
4349 dspcntr = DISPPLANE_GAMMA_ENABLE;
4351 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4352 drm_mode_debug_printmodeline(mode);
4354 /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
4356 struct intel_pch_pll *pll;
4358 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4360 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4365 intel_put_pch_pll(intel_crtc);
4367 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4368 * This is an exception to the general rule that mode_set doesn't turn
4372 temp = I915_READ(PCH_LVDS);
4373 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4374 if (HAS_PCH_CPT(dev)) {
4375 temp &= ~PORT_TRANS_SEL_MASK;
4376 temp |= PORT_TRANS_SEL_CPT(pipe);
4379 temp |= LVDS_PIPEB_SELECT;
4381 temp &= ~LVDS_PIPEB_SELECT;
4384 /* set the corresponsding LVDS_BORDER bit */
4385 temp |= dev_priv->lvds_border_bits;
4386 /* Set the B0-B3 data pairs corresponding to whether we're going to
4387 * set the DPLLs for dual-channel mode or not.
4390 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4392 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4394 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4395 * appropriately here, but we need to look more thoroughly into how
4396 * panels behave in the two modes.
4398 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4399 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4400 temp |= LVDS_HSYNC_POLARITY;
4401 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4402 temp |= LVDS_VSYNC_POLARITY;
4403 I915_WRITE(PCH_LVDS, temp);
4406 pipeconf &= ~PIPECONF_DITHER_EN;
4407 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4408 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4409 pipeconf |= PIPECONF_DITHER_EN;
4410 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4412 if (is_dp && !is_cpu_edp) {
4413 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4415 /* For non-DP output, clear any trans DP clock recovery setting.*/
4416 I915_WRITE(TRANSDATA_M1(pipe), 0);
4417 I915_WRITE(TRANSDATA_N1(pipe), 0);
4418 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4419 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4422 if (intel_crtc->pch_pll) {
4423 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4425 /* Wait for the clocks to stabilize. */
4426 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4429 /* The pixel multiplier can only be updated once the
4430 * DPLL is enabled and the clocks are stable.
4432 * So write it again.
4434 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4437 intel_crtc->lowfreq_avail = false;
4438 if (intel_crtc->pch_pll) {
4439 if (is_lvds && has_reduced_clock && i915_powersave) {
4440 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4441 intel_crtc->lowfreq_avail = true;
4442 if (HAS_PIPE_CXSR(dev)) {
4443 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4444 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4447 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4448 if (HAS_PIPE_CXSR(dev)) {
4449 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4450 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4455 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4456 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4457 pipeconf |= PIPECONF_INTERLACED_ILK;
4458 /* the chip adds 2 halflines automatically */
4459 adjusted_mode->crtc_vtotal -= 1;
4460 adjusted_mode->crtc_vblank_end -= 1;
4461 I915_WRITE(VSYNCSHIFT(pipe),
4462 adjusted_mode->crtc_hsync_start
4463 - adjusted_mode->crtc_htotal/2);
4465 pipeconf |= PIPECONF_PROGRESSIVE;
4466 I915_WRITE(VSYNCSHIFT(pipe), 0);
4469 I915_WRITE(HTOTAL(pipe),
4470 (adjusted_mode->crtc_hdisplay - 1) |
4471 ((adjusted_mode->crtc_htotal - 1) << 16));
4472 I915_WRITE(HBLANK(pipe),
4473 (adjusted_mode->crtc_hblank_start - 1) |
4474 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4475 I915_WRITE(HSYNC(pipe),
4476 (adjusted_mode->crtc_hsync_start - 1) |
4477 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4479 I915_WRITE(VTOTAL(pipe),
4480 (adjusted_mode->crtc_vdisplay - 1) |
4481 ((adjusted_mode->crtc_vtotal - 1) << 16));
4482 I915_WRITE(VBLANK(pipe),
4483 (adjusted_mode->crtc_vblank_start - 1) |
4484 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4485 I915_WRITE(VSYNC(pipe),
4486 (adjusted_mode->crtc_vsync_start - 1) |
4487 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4489 /* pipesrc controls the size that is scaled from, which should
4490 * always be the user's requested size.
4492 I915_WRITE(PIPESRC(pipe),
4493 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4495 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4496 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4497 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4498 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4501 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4503 I915_WRITE(PIPECONF(pipe), pipeconf);
4504 POSTING_READ(PIPECONF(pipe));
4506 intel_wait_for_vblank(dev, pipe);
4508 I915_WRITE(DSPCNTR(plane), dspcntr);
4509 POSTING_READ(DSPCNTR(plane));
4511 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4513 intel_update_watermarks(dev);
4518 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4519 struct drm_display_mode *mode,
4520 struct drm_display_mode *adjusted_mode,
4522 struct drm_framebuffer *old_fb)
4524 struct drm_device *dev = crtc->dev;
4525 struct drm_i915_private *dev_priv = dev->dev_private;
4526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4527 int pipe = intel_crtc->pipe;
4530 drm_vblank_pre_modeset(dev, pipe);
4532 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4534 drm_vblank_post_modeset(dev, pipe);
4537 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4539 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4544 static bool intel_eld_uptodate(struct drm_connector *connector,
4545 int reg_eldv, uint32_t bits_eldv,
4546 int reg_elda, uint32_t bits_elda,
4549 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4550 uint8_t *eld = connector->eld;
4553 i = I915_READ(reg_eldv);
4562 i = I915_READ(reg_elda);
4564 I915_WRITE(reg_elda, i);
4566 for (i = 0; i < eld[2]; i++)
4567 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4573 static void g4x_write_eld(struct drm_connector *connector,
4574 struct drm_crtc *crtc)
4576 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4577 uint8_t *eld = connector->eld;
4582 i = I915_READ(G4X_AUD_VID_DID);
4584 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4585 eldv = G4X_ELDV_DEVCL_DEVBLC;
4587 eldv = G4X_ELDV_DEVCTG;
4589 if (intel_eld_uptodate(connector,
4590 G4X_AUD_CNTL_ST, eldv,
4591 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4592 G4X_HDMIW_HDMIEDID))
4595 i = I915_READ(G4X_AUD_CNTL_ST);
4596 i &= ~(eldv | G4X_ELD_ADDR);
4597 len = (i >> 9) & 0x1f; /* ELD buffer size */
4598 I915_WRITE(G4X_AUD_CNTL_ST, i);
4603 len = min_t(uint8_t, eld[2], len);
4604 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4605 for (i = 0; i < len; i++)
4606 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4608 i = I915_READ(G4X_AUD_CNTL_ST);
4610 I915_WRITE(G4X_AUD_CNTL_ST, i);
4613 static void ironlake_write_eld(struct drm_connector *connector,
4614 struct drm_crtc *crtc)
4616 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4617 uint8_t *eld = connector->eld;
4626 if (HAS_PCH_IBX(connector->dev)) {
4627 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4628 aud_config = IBX_AUD_CONFIG_A;
4629 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4630 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4632 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4633 aud_config = CPT_AUD_CONFIG_A;
4634 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4635 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4638 i = to_intel_crtc(crtc)->pipe;
4639 hdmiw_hdmiedid += i * 0x100;
4640 aud_cntl_st += i * 0x100;
4641 aud_config += i * 0x100;
4643 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4645 i = I915_READ(aud_cntl_st);
4646 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4648 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4649 /* operate blindly on all ports */
4650 eldv = IBX_ELD_VALIDB;
4651 eldv |= IBX_ELD_VALIDB << 4;
4652 eldv |= IBX_ELD_VALIDB << 8;
4654 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4655 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4658 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4659 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4660 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
4661 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4663 I915_WRITE(aud_config, 0);
4665 if (intel_eld_uptodate(connector,
4666 aud_cntrl_st2, eldv,
4667 aud_cntl_st, IBX_ELD_ADDRESS,
4671 i = I915_READ(aud_cntrl_st2);
4673 I915_WRITE(aud_cntrl_st2, i);
4678 i = I915_READ(aud_cntl_st);
4679 i &= ~IBX_ELD_ADDRESS;
4680 I915_WRITE(aud_cntl_st, i);
4682 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4683 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4684 for (i = 0; i < len; i++)
4685 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4687 i = I915_READ(aud_cntrl_st2);
4689 I915_WRITE(aud_cntrl_st2, i);
4692 void intel_write_eld(struct drm_encoder *encoder,
4693 struct drm_display_mode *mode)
4695 struct drm_crtc *crtc = encoder->crtc;
4696 struct drm_connector *connector;
4697 struct drm_device *dev = encoder->dev;
4698 struct drm_i915_private *dev_priv = dev->dev_private;
4700 connector = drm_select_eld(encoder, mode);
4704 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4706 drm_get_connector_name(connector),
4707 connector->encoder->base.id,
4708 drm_get_encoder_name(connector->encoder));
4710 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4712 if (dev_priv->display.write_eld)
4713 dev_priv->display.write_eld(connector, crtc);
4716 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4717 void intel_crtc_load_lut(struct drm_crtc *crtc)
4719 struct drm_device *dev = crtc->dev;
4720 struct drm_i915_private *dev_priv = dev->dev_private;
4721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4722 int palreg = PALETTE(intel_crtc->pipe);
4725 /* The clocks have to be on to load the palette. */
4726 if (!crtc->enabled || !intel_crtc->active)
4729 /* use legacy palette for Ironlake */
4730 if (HAS_PCH_SPLIT(dev))
4731 palreg = LGC_PALETTE(intel_crtc->pipe);
4733 for (i = 0; i < 256; i++) {
4734 I915_WRITE(palreg + 4 * i,
4735 (intel_crtc->lut_r[i] << 16) |
4736 (intel_crtc->lut_g[i] << 8) |
4737 intel_crtc->lut_b[i]);
4741 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4743 struct drm_device *dev = crtc->dev;
4744 struct drm_i915_private *dev_priv = dev->dev_private;
4745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4746 bool visible = base != 0;
4749 if (intel_crtc->cursor_visible == visible)
4752 cntl = I915_READ(_CURACNTR);
4754 /* On these chipsets we can only modify the base whilst
4755 * the cursor is disabled.
4757 I915_WRITE(_CURABASE, base);
4759 cntl &= ~(CURSOR_FORMAT_MASK);
4760 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4761 cntl |= CURSOR_ENABLE |
4762 CURSOR_GAMMA_ENABLE |
4765 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4766 I915_WRITE(_CURACNTR, cntl);
4768 intel_crtc->cursor_visible = visible;
4771 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4773 struct drm_device *dev = crtc->dev;
4774 struct drm_i915_private *dev_priv = dev->dev_private;
4775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4776 int pipe = intel_crtc->pipe;
4777 bool visible = base != 0;
4779 if (intel_crtc->cursor_visible != visible) {
4780 uint32_t cntl = I915_READ(CURCNTR(pipe));
4782 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4783 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4784 cntl |= pipe << 28; /* Connect to correct pipe */
4786 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4787 cntl |= CURSOR_MODE_DISABLE;
4789 I915_WRITE(CURCNTR(pipe), cntl);
4791 intel_crtc->cursor_visible = visible;
4793 /* and commit changes on next vblank */
4794 I915_WRITE(CURBASE(pipe), base);
4797 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4799 struct drm_device *dev = crtc->dev;
4800 struct drm_i915_private *dev_priv = dev->dev_private;
4801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4802 int pipe = intel_crtc->pipe;
4803 bool visible = base != 0;
4805 if (intel_crtc->cursor_visible != visible) {
4806 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4808 cntl &= ~CURSOR_MODE;
4809 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4811 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4812 cntl |= CURSOR_MODE_DISABLE;
4814 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4816 intel_crtc->cursor_visible = visible;
4818 /* and commit changes on next vblank */
4819 I915_WRITE(CURBASE_IVB(pipe), base);
4822 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4823 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4826 struct drm_device *dev = crtc->dev;
4827 struct drm_i915_private *dev_priv = dev->dev_private;
4828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4829 int pipe = intel_crtc->pipe;
4830 int x = intel_crtc->cursor_x;
4831 int y = intel_crtc->cursor_y;
4837 if (on && crtc->enabled && crtc->fb) {
4838 base = intel_crtc->cursor_addr;
4839 if (x > (int) crtc->fb->width)
4842 if (y > (int) crtc->fb->height)
4848 if (x + intel_crtc->cursor_width < 0)
4851 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4854 pos |= x << CURSOR_X_SHIFT;
4857 if (y + intel_crtc->cursor_height < 0)
4860 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4863 pos |= y << CURSOR_Y_SHIFT;
4865 visible = base != 0;
4866 if (!visible && !intel_crtc->cursor_visible)
4869 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4870 I915_WRITE(CURPOS_IVB(pipe), pos);
4871 ivb_update_cursor(crtc, base);
4873 I915_WRITE(CURPOS(pipe), pos);
4874 if (IS_845G(dev) || IS_I865G(dev))
4875 i845_update_cursor(crtc, base);
4877 i9xx_update_cursor(crtc, base);
4881 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4884 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4885 struct drm_file *file,
4887 uint32_t width, uint32_t height)
4889 struct drm_device *dev = crtc->dev;
4890 struct drm_i915_private *dev_priv = dev->dev_private;
4891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4892 struct drm_i915_gem_object *obj;
4896 DRM_DEBUG_KMS("\n");
4898 /* if we want to turn off the cursor ignore width and height */
4900 DRM_DEBUG_KMS("cursor off\n");
4903 mutex_lock(&dev->struct_mutex);
4907 /* Currently we only support 64x64 cursors */
4908 if (width != 64 || height != 64) {
4909 DRM_ERROR("we currently only support 64x64 cursors\n");
4913 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4914 if (&obj->base == NULL)
4917 if (obj->base.size < width * height * 4) {
4918 DRM_ERROR("buffer is to small\n");
4923 /* we only need to pin inside GTT if cursor is non-phy */
4924 mutex_lock(&dev->struct_mutex);
4925 if (!dev_priv->info->cursor_needs_physical) {
4926 if (obj->tiling_mode) {
4927 DRM_ERROR("cursor cannot be tiled\n");
4932 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
4934 DRM_ERROR("failed to move cursor bo into the GTT\n");
4938 ret = i915_gem_object_put_fence(obj);
4940 DRM_ERROR("failed to release fence for cursor");
4944 addr = obj->gtt_offset;
4946 int align = IS_I830(dev) ? 16 * 1024 : 256;
4947 ret = i915_gem_attach_phys_object(dev, obj,
4948 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4951 DRM_ERROR("failed to attach phys object\n");
4954 addr = obj->phys_obj->handle->busaddr;
4958 I915_WRITE(CURSIZE, (height << 12) | width);
4961 if (intel_crtc->cursor_bo) {
4962 if (dev_priv->info->cursor_needs_physical) {
4963 if (intel_crtc->cursor_bo != obj)
4964 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4966 i915_gem_object_unpin(intel_crtc->cursor_bo);
4967 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4970 mutex_unlock(&dev->struct_mutex);
4972 intel_crtc->cursor_addr = addr;
4973 intel_crtc->cursor_bo = obj;
4974 intel_crtc->cursor_width = width;
4975 intel_crtc->cursor_height = height;
4977 intel_crtc_update_cursor(crtc, true);
4981 i915_gem_object_unpin(obj);
4983 mutex_unlock(&dev->struct_mutex);
4985 drm_gem_object_unreference_unlocked(&obj->base);
4989 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4993 intel_crtc->cursor_x = x;
4994 intel_crtc->cursor_y = y;
4996 intel_crtc_update_cursor(crtc, true);
5001 /** Sets the color ramps on behalf of RandR */
5002 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5003 u16 blue, int regno)
5005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5007 intel_crtc->lut_r[regno] = red >> 8;
5008 intel_crtc->lut_g[regno] = green >> 8;
5009 intel_crtc->lut_b[regno] = blue >> 8;
5012 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5013 u16 *blue, int regno)
5015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5017 *red = intel_crtc->lut_r[regno] << 8;
5018 *green = intel_crtc->lut_g[regno] << 8;
5019 *blue = intel_crtc->lut_b[regno] << 8;
5022 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5023 u16 *blue, uint32_t start, uint32_t size)
5025 int end = (start + size > 256) ? 256 : start + size, i;
5026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028 for (i = start; i < end; i++) {
5029 intel_crtc->lut_r[i] = red[i] >> 8;
5030 intel_crtc->lut_g[i] = green[i] >> 8;
5031 intel_crtc->lut_b[i] = blue[i] >> 8;
5034 intel_crtc_load_lut(crtc);
5038 * Get a pipe with a simple mode set on it for doing load-based monitor
5041 * It will be up to the load-detect code to adjust the pipe as appropriate for
5042 * its requirements. The pipe will be connected to no other encoders.
5044 * Currently this code will only succeed if there is a pipe with no encoders
5045 * configured for it. In the future, it could choose to temporarily disable
5046 * some outputs to free up a pipe for its use.
5048 * \return crtc, or NULL if no pipes are available.
5051 /* VESA 640x480x72Hz mode to set on the pipe */
5052 static struct drm_display_mode load_detect_mode = {
5053 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5054 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5057 static struct drm_framebuffer *
5058 intel_framebuffer_create(struct drm_device *dev,
5059 struct drm_mode_fb_cmd2 *mode_cmd,
5060 struct drm_i915_gem_object *obj)
5062 struct intel_framebuffer *intel_fb;
5065 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5067 drm_gem_object_unreference_unlocked(&obj->base);
5068 return ERR_PTR(-ENOMEM);
5071 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5073 drm_gem_object_unreference_unlocked(&obj->base);
5075 return ERR_PTR(ret);
5078 return &intel_fb->base;
5082 intel_framebuffer_pitch_for_width(int width, int bpp)
5084 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5085 return ALIGN(pitch, 64);
5089 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5091 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5092 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5095 static struct drm_framebuffer *
5096 intel_framebuffer_create_for_mode(struct drm_device *dev,
5097 struct drm_display_mode *mode,
5100 struct drm_i915_gem_object *obj;
5101 struct drm_mode_fb_cmd2 mode_cmd;
5103 obj = i915_gem_alloc_object(dev,
5104 intel_framebuffer_size_for_mode(mode, bpp));
5106 return ERR_PTR(-ENOMEM);
5108 mode_cmd.width = mode->hdisplay;
5109 mode_cmd.height = mode->vdisplay;
5110 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5112 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5114 return intel_framebuffer_create(dev, &mode_cmd, obj);
5117 static struct drm_framebuffer *
5118 mode_fits_in_fbdev(struct drm_device *dev,
5119 struct drm_display_mode *mode)
5121 struct drm_i915_private *dev_priv = dev->dev_private;
5122 struct drm_i915_gem_object *obj;
5123 struct drm_framebuffer *fb;
5125 if (dev_priv->fbdev == NULL)
5128 obj = dev_priv->fbdev->ifb.obj;
5132 fb = &dev_priv->fbdev->ifb.base;
5133 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5134 fb->bits_per_pixel))
5137 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5143 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5144 struct drm_connector *connector,
5145 struct drm_display_mode *mode,
5146 struct intel_load_detect_pipe *old)
5148 struct intel_crtc *intel_crtc;
5149 struct drm_crtc *possible_crtc;
5150 struct drm_encoder *encoder = &intel_encoder->base;
5151 struct drm_crtc *crtc = NULL;
5152 struct drm_device *dev = encoder->dev;
5153 struct drm_framebuffer *old_fb;
5156 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5157 connector->base.id, drm_get_connector_name(connector),
5158 encoder->base.id, drm_get_encoder_name(encoder));
5161 * Algorithm gets a little messy:
5163 * - if the connector already has an assigned crtc, use it (but make
5164 * sure it's on first)
5166 * - try to find the first unused crtc that can drive this connector,
5167 * and use that if we find one
5170 /* See if we already have a CRTC for this connector */
5171 if (encoder->crtc) {
5172 crtc = encoder->crtc;
5174 intel_crtc = to_intel_crtc(crtc);
5175 old->dpms_mode = intel_crtc->dpms_mode;
5176 old->load_detect_temp = false;
5178 /* Make sure the crtc and connector are running */
5179 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5180 struct drm_encoder_helper_funcs *encoder_funcs;
5181 struct drm_crtc_helper_funcs *crtc_funcs;
5183 crtc_funcs = crtc->helper_private;
5184 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5186 encoder_funcs = encoder->helper_private;
5187 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5193 /* Find an unused one (if possible) */
5194 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5196 if (!(encoder->possible_crtcs & (1 << i)))
5198 if (!possible_crtc->enabled) {
5199 crtc = possible_crtc;
5205 * If we didn't find an unused CRTC, don't use any.
5208 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5212 encoder->crtc = crtc;
5213 connector->encoder = encoder;
5215 intel_crtc = to_intel_crtc(crtc);
5216 old->dpms_mode = intel_crtc->dpms_mode;
5217 old->load_detect_temp = true;
5218 old->release_fb = NULL;
5221 mode = &load_detect_mode;
5225 /* We need a framebuffer large enough to accommodate all accesses
5226 * that the plane may generate whilst we perform load detection.
5227 * We can not rely on the fbcon either being present (we get called
5228 * during its initialisation to detect all boot displays, or it may
5229 * not even exist) or that it is large enough to satisfy the
5232 crtc->fb = mode_fits_in_fbdev(dev, mode);
5233 if (crtc->fb == NULL) {
5234 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5235 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5236 old->release_fb = crtc->fb;
5238 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5239 if (IS_ERR(crtc->fb)) {
5240 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5245 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5246 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5247 if (old->release_fb)
5248 old->release_fb->funcs->destroy(old->release_fb);
5253 /* let the connector get through one full cycle before testing */
5254 intel_wait_for_vblank(dev, intel_crtc->pipe);
5259 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5260 struct drm_connector *connector,
5261 struct intel_load_detect_pipe *old)
5263 struct drm_encoder *encoder = &intel_encoder->base;
5264 struct drm_device *dev = encoder->dev;
5265 struct drm_crtc *crtc = encoder->crtc;
5266 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5267 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5269 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5270 connector->base.id, drm_get_connector_name(connector),
5271 encoder->base.id, drm_get_encoder_name(encoder));
5273 if (old->load_detect_temp) {
5274 connector->encoder = NULL;
5275 drm_helper_disable_unused_functions(dev);
5277 if (old->release_fb)
5278 old->release_fb->funcs->destroy(old->release_fb);
5283 /* Switch crtc and encoder back off if necessary */
5284 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5285 encoder_funcs->dpms(encoder, old->dpms_mode);
5286 crtc_funcs->dpms(crtc, old->dpms_mode);
5290 /* Returns the clock of the currently programmed mode of the given pipe. */
5291 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5293 struct drm_i915_private *dev_priv = dev->dev_private;
5294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5295 int pipe = intel_crtc->pipe;
5296 u32 dpll = I915_READ(DPLL(pipe));
5298 intel_clock_t clock;
5300 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5301 fp = I915_READ(FP0(pipe));
5303 fp = I915_READ(FP1(pipe));
5305 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5306 if (IS_PINEVIEW(dev)) {
5307 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5308 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5310 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5311 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5314 if (!IS_GEN2(dev)) {
5315 if (IS_PINEVIEW(dev))
5316 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5317 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5319 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5320 DPLL_FPA01_P1_POST_DIV_SHIFT);
5322 switch (dpll & DPLL_MODE_MASK) {
5323 case DPLLB_MODE_DAC_SERIAL:
5324 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5327 case DPLLB_MODE_LVDS:
5328 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5332 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5333 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5337 /* XXX: Handle the 100Mhz refclk */
5338 intel_clock(dev, 96000, &clock);
5340 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5343 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5344 DPLL_FPA01_P1_POST_DIV_SHIFT);
5347 if ((dpll & PLL_REF_INPUT_MASK) ==
5348 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5349 /* XXX: might not be 66MHz */
5350 intel_clock(dev, 66000, &clock);
5352 intel_clock(dev, 48000, &clock);
5354 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5357 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5358 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5360 if (dpll & PLL_P2_DIVIDE_BY_4)
5365 intel_clock(dev, 48000, &clock);
5369 /* XXX: It would be nice to validate the clocks, but we can't reuse
5370 * i830PllIsValid() because it relies on the xf86_config connector
5371 * configuration being accurate, which it isn't necessarily.
5377 /** Returns the currently programmed mode of the given pipe. */
5378 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5379 struct drm_crtc *crtc)
5381 struct drm_i915_private *dev_priv = dev->dev_private;
5382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5383 int pipe = intel_crtc->pipe;
5384 struct drm_display_mode *mode;
5385 int htot = I915_READ(HTOTAL(pipe));
5386 int hsync = I915_READ(HSYNC(pipe));
5387 int vtot = I915_READ(VTOTAL(pipe));
5388 int vsync = I915_READ(VSYNC(pipe));
5390 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5394 mode->clock = intel_crtc_clock_get(dev, crtc);
5395 mode->hdisplay = (htot & 0xffff) + 1;
5396 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5397 mode->hsync_start = (hsync & 0xffff) + 1;
5398 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5399 mode->vdisplay = (vtot & 0xffff) + 1;
5400 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5401 mode->vsync_start = (vsync & 0xffff) + 1;
5402 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5404 drm_mode_set_name(mode);
5405 drm_mode_set_crtcinfo(mode, 0);
5410 #define GPU_IDLE_TIMEOUT 500 /* ms */
5412 /* When this timer fires, we've been idle for awhile */
5413 static void intel_gpu_idle_timer(unsigned long arg)
5415 struct drm_device *dev = (struct drm_device *)arg;
5416 drm_i915_private_t *dev_priv = dev->dev_private;
5418 if (!list_empty(&dev_priv->mm.active_list)) {
5419 /* Still processing requests, so just re-arm the timer. */
5420 mod_timer(&dev_priv->idle_timer, jiffies +
5421 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5425 dev_priv->busy = false;
5426 queue_work(dev_priv->wq, &dev_priv->idle_work);
5429 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5431 static void intel_crtc_idle_timer(unsigned long arg)
5433 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5434 struct drm_crtc *crtc = &intel_crtc->base;
5435 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5436 struct intel_framebuffer *intel_fb;
5438 intel_fb = to_intel_framebuffer(crtc->fb);
5439 if (intel_fb && intel_fb->obj->active) {
5440 /* The framebuffer is still being accessed by the GPU. */
5441 mod_timer(&intel_crtc->idle_timer, jiffies +
5442 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5446 intel_crtc->busy = false;
5447 queue_work(dev_priv->wq, &dev_priv->idle_work);
5450 static void intel_increase_pllclock(struct drm_crtc *crtc)
5452 struct drm_device *dev = crtc->dev;
5453 drm_i915_private_t *dev_priv = dev->dev_private;
5454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5455 int pipe = intel_crtc->pipe;
5456 int dpll_reg = DPLL(pipe);
5459 if (HAS_PCH_SPLIT(dev))
5462 if (!dev_priv->lvds_downclock_avail)
5465 dpll = I915_READ(dpll_reg);
5466 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5467 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5469 assert_panel_unlocked(dev_priv, pipe);
5471 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5472 I915_WRITE(dpll_reg, dpll);
5473 intel_wait_for_vblank(dev, pipe);
5475 dpll = I915_READ(dpll_reg);
5476 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5477 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5480 /* Schedule downclock */
5481 mod_timer(&intel_crtc->idle_timer, jiffies +
5482 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5485 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5487 struct drm_device *dev = crtc->dev;
5488 drm_i915_private_t *dev_priv = dev->dev_private;
5489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5490 int pipe = intel_crtc->pipe;
5491 int dpll_reg = DPLL(pipe);
5492 int dpll = I915_READ(dpll_reg);
5494 if (HAS_PCH_SPLIT(dev))
5497 if (!dev_priv->lvds_downclock_avail)
5501 * Since this is called by a timer, we should never get here in
5504 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5505 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5507 assert_panel_unlocked(dev_priv, pipe);
5509 dpll |= DISPLAY_RATE_SELECT_FPA1;
5510 I915_WRITE(dpll_reg, dpll);
5511 intel_wait_for_vblank(dev, pipe);
5512 dpll = I915_READ(dpll_reg);
5513 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5514 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5520 * intel_idle_update - adjust clocks for idleness
5521 * @work: work struct
5523 * Either the GPU or display (or both) went idle. Check the busy status
5524 * here and adjust the CRTC and GPU clocks as necessary.
5526 static void intel_idle_update(struct work_struct *work)
5528 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5530 struct drm_device *dev = dev_priv->dev;
5531 struct drm_crtc *crtc;
5532 struct intel_crtc *intel_crtc;
5534 if (!i915_powersave)
5537 mutex_lock(&dev->struct_mutex);
5539 i915_update_gfx_val(dev_priv);
5541 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5542 /* Skip inactive CRTCs */
5546 intel_crtc = to_intel_crtc(crtc);
5547 if (!intel_crtc->busy)
5548 intel_decrease_pllclock(crtc);
5552 mutex_unlock(&dev->struct_mutex);
5556 * intel_mark_busy - mark the GPU and possibly the display busy
5558 * @obj: object we're operating on
5560 * Callers can use this function to indicate that the GPU is busy processing
5561 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5562 * buffer), we'll also mark the display as busy, so we know to increase its
5565 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5567 drm_i915_private_t *dev_priv = dev->dev_private;
5568 struct drm_crtc *crtc = NULL;
5569 struct intel_framebuffer *intel_fb;
5570 struct intel_crtc *intel_crtc;
5572 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5575 if (!dev_priv->busy)
5576 dev_priv->busy = true;
5578 mod_timer(&dev_priv->idle_timer, jiffies +
5579 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5581 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5585 intel_crtc = to_intel_crtc(crtc);
5586 intel_fb = to_intel_framebuffer(crtc->fb);
5587 if (intel_fb->obj == obj) {
5588 if (!intel_crtc->busy) {
5589 /* Non-busy -> busy, upclock */
5590 intel_increase_pllclock(crtc);
5591 intel_crtc->busy = true;
5593 /* Busy -> busy, put off timer */
5594 mod_timer(&intel_crtc->idle_timer, jiffies +
5595 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5601 static void intel_crtc_destroy(struct drm_crtc *crtc)
5603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5604 struct drm_device *dev = crtc->dev;
5605 struct intel_unpin_work *work;
5606 unsigned long flags;
5608 spin_lock_irqsave(&dev->event_lock, flags);
5609 work = intel_crtc->unpin_work;
5610 intel_crtc->unpin_work = NULL;
5611 spin_unlock_irqrestore(&dev->event_lock, flags);
5614 cancel_work_sync(&work->work);
5618 drm_crtc_cleanup(crtc);
5623 static void intel_unpin_work_fn(struct work_struct *__work)
5625 struct intel_unpin_work *work =
5626 container_of(__work, struct intel_unpin_work, work);
5628 mutex_lock(&work->dev->struct_mutex);
5629 intel_unpin_fb_obj(work->old_fb_obj);
5630 drm_gem_object_unreference(&work->pending_flip_obj->base);
5631 drm_gem_object_unreference(&work->old_fb_obj->base);
5633 intel_update_fbc(work->dev);
5634 mutex_unlock(&work->dev->struct_mutex);
5638 static void do_intel_finish_page_flip(struct drm_device *dev,
5639 struct drm_crtc *crtc)
5641 drm_i915_private_t *dev_priv = dev->dev_private;
5642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5643 struct intel_unpin_work *work;
5644 struct drm_i915_gem_object *obj;
5645 struct drm_pending_vblank_event *e;
5646 struct timeval tnow, tvbl;
5647 unsigned long flags;
5649 /* Ignore early vblank irqs */
5650 if (intel_crtc == NULL)
5653 do_gettimeofday(&tnow);
5655 spin_lock_irqsave(&dev->event_lock, flags);
5656 work = intel_crtc->unpin_work;
5657 if (work == NULL || !work->pending) {
5658 spin_unlock_irqrestore(&dev->event_lock, flags);
5662 intel_crtc->unpin_work = NULL;
5666 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5668 /* Called before vblank count and timestamps have
5669 * been updated for the vblank interval of flip
5670 * completion? Need to increment vblank count and
5671 * add one videorefresh duration to returned timestamp
5672 * to account for this. We assume this happened if we
5673 * get called over 0.9 frame durations after the last
5674 * timestamped vblank.
5676 * This calculation can not be used with vrefresh rates
5677 * below 5Hz (10Hz to be on the safe side) without
5678 * promoting to 64 integers.
5680 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5681 9 * crtc->framedur_ns) {
5682 e->event.sequence++;
5683 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5687 e->event.tv_sec = tvbl.tv_sec;
5688 e->event.tv_usec = tvbl.tv_usec;
5690 list_add_tail(&e->base.link,
5691 &e->base.file_priv->event_list);
5692 wake_up_interruptible(&e->base.file_priv->event_wait);
5695 drm_vblank_put(dev, intel_crtc->pipe);
5697 spin_unlock_irqrestore(&dev->event_lock, flags);
5699 obj = work->old_fb_obj;
5701 atomic_clear_mask(1 << intel_crtc->plane,
5702 &obj->pending_flip.counter);
5703 if (atomic_read(&obj->pending_flip) == 0)
5704 wake_up(&dev_priv->pending_flip_queue);
5706 schedule_work(&work->work);
5708 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5711 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5713 drm_i915_private_t *dev_priv = dev->dev_private;
5714 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5716 do_intel_finish_page_flip(dev, crtc);
5719 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5721 drm_i915_private_t *dev_priv = dev->dev_private;
5722 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5724 do_intel_finish_page_flip(dev, crtc);
5727 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5729 drm_i915_private_t *dev_priv = dev->dev_private;
5730 struct intel_crtc *intel_crtc =
5731 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5732 unsigned long flags;
5734 spin_lock_irqsave(&dev->event_lock, flags);
5735 if (intel_crtc->unpin_work) {
5736 if ((++intel_crtc->unpin_work->pending) > 1)
5737 DRM_ERROR("Prepared flip multiple times\n");
5739 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5741 spin_unlock_irqrestore(&dev->event_lock, flags);
5744 static int intel_gen2_queue_flip(struct drm_device *dev,
5745 struct drm_crtc *crtc,
5746 struct drm_framebuffer *fb,
5747 struct drm_i915_gem_object *obj)
5749 struct drm_i915_private *dev_priv = dev->dev_private;
5750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5751 unsigned long offset;
5755 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5759 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5760 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5762 ret = BEGIN_LP_RING(6);
5766 /* Can't queue multiple flips, so wait for the previous
5767 * one to finish before executing the next.
5769 if (intel_crtc->plane)
5770 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5772 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5773 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5775 OUT_RING(MI_DISPLAY_FLIP |
5776 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5777 OUT_RING(fb->pitches[0]);
5778 OUT_RING(obj->gtt_offset + offset);
5779 OUT_RING(0); /* aux display base address, unused */
5784 intel_unpin_fb_obj(obj);
5789 static int intel_gen3_queue_flip(struct drm_device *dev,
5790 struct drm_crtc *crtc,
5791 struct drm_framebuffer *fb,
5792 struct drm_i915_gem_object *obj)
5794 struct drm_i915_private *dev_priv = dev->dev_private;
5795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5796 unsigned long offset;
5800 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5804 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5805 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5807 ret = BEGIN_LP_RING(6);
5811 if (intel_crtc->plane)
5812 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5814 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5815 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5817 OUT_RING(MI_DISPLAY_FLIP_I915 |
5818 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5819 OUT_RING(fb->pitches[0]);
5820 OUT_RING(obj->gtt_offset + offset);
5827 intel_unpin_fb_obj(obj);
5832 static int intel_gen4_queue_flip(struct drm_device *dev,
5833 struct drm_crtc *crtc,
5834 struct drm_framebuffer *fb,
5835 struct drm_i915_gem_object *obj)
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5839 uint32_t pf, pipesrc;
5842 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5846 ret = BEGIN_LP_RING(4);
5850 /* i965+ uses the linear or tiled offsets from the
5851 * Display Registers (which do not change across a page-flip)
5852 * so we need only reprogram the base address.
5854 OUT_RING(MI_DISPLAY_FLIP |
5855 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5856 OUT_RING(fb->pitches[0]);
5857 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5859 /* XXX Enabling the panel-fitter across page-flip is so far
5860 * untested on non-native modes, so ignore it for now.
5861 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5864 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5865 OUT_RING(pf | pipesrc);
5870 intel_unpin_fb_obj(obj);
5875 static int intel_gen6_queue_flip(struct drm_device *dev,
5876 struct drm_crtc *crtc,
5877 struct drm_framebuffer *fb,
5878 struct drm_i915_gem_object *obj)
5880 struct drm_i915_private *dev_priv = dev->dev_private;
5881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5882 uint32_t pf, pipesrc;
5885 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5889 ret = BEGIN_LP_RING(4);
5893 OUT_RING(MI_DISPLAY_FLIP |
5894 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5895 OUT_RING(fb->pitches[0] | obj->tiling_mode);
5896 OUT_RING(obj->gtt_offset);
5898 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5899 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5900 OUT_RING(pf | pipesrc);
5905 intel_unpin_fb_obj(obj);
5911 * On gen7 we currently use the blit ring because (in early silicon at least)
5912 * the render ring doesn't give us interrpts for page flip completion, which
5913 * means clients will hang after the first flip is queued. Fortunately the
5914 * blit ring generates interrupts properly, so use it instead.
5916 static int intel_gen7_queue_flip(struct drm_device *dev,
5917 struct drm_crtc *crtc,
5918 struct drm_framebuffer *fb,
5919 struct drm_i915_gem_object *obj)
5921 struct drm_i915_private *dev_priv = dev->dev_private;
5922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5923 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5926 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5930 ret = intel_ring_begin(ring, 4);
5934 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
5935 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
5936 intel_ring_emit(ring, (obj->gtt_offset));
5937 intel_ring_emit(ring, (MI_NOOP));
5938 intel_ring_advance(ring);
5942 intel_unpin_fb_obj(obj);
5947 static int intel_default_queue_flip(struct drm_device *dev,
5948 struct drm_crtc *crtc,
5949 struct drm_framebuffer *fb,
5950 struct drm_i915_gem_object *obj)
5955 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5956 struct drm_framebuffer *fb,
5957 struct drm_pending_vblank_event *event)
5959 struct drm_device *dev = crtc->dev;
5960 struct drm_i915_private *dev_priv = dev->dev_private;
5961 struct intel_framebuffer *intel_fb;
5962 struct drm_i915_gem_object *obj;
5963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5964 struct intel_unpin_work *work;
5965 unsigned long flags;
5968 work = kzalloc(sizeof *work, GFP_KERNEL);
5972 work->event = event;
5973 work->dev = crtc->dev;
5974 intel_fb = to_intel_framebuffer(crtc->fb);
5975 work->old_fb_obj = intel_fb->obj;
5976 INIT_WORK(&work->work, intel_unpin_work_fn);
5978 ret = drm_vblank_get(dev, intel_crtc->pipe);
5982 /* We borrow the event spin lock for protecting unpin_work */
5983 spin_lock_irqsave(&dev->event_lock, flags);
5984 if (intel_crtc->unpin_work) {
5985 spin_unlock_irqrestore(&dev->event_lock, flags);
5987 drm_vblank_put(dev, intel_crtc->pipe);
5989 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5992 intel_crtc->unpin_work = work;
5993 spin_unlock_irqrestore(&dev->event_lock, flags);
5995 intel_fb = to_intel_framebuffer(fb);
5996 obj = intel_fb->obj;
5998 mutex_lock(&dev->struct_mutex);
6000 /* Reference the objects for the scheduled work. */
6001 drm_gem_object_reference(&work->old_fb_obj->base);
6002 drm_gem_object_reference(&obj->base);
6006 work->pending_flip_obj = obj;
6008 work->enable_stall_check = true;
6010 /* Block clients from rendering to the new back buffer until
6011 * the flip occurs and the object is no longer visible.
6013 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6015 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6017 goto cleanup_pending;
6019 intel_disable_fbc(dev);
6020 mutex_unlock(&dev->struct_mutex);
6022 trace_i915_flip_request(intel_crtc->plane, obj);
6027 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6028 drm_gem_object_unreference(&work->old_fb_obj->base);
6029 drm_gem_object_unreference(&obj->base);
6030 mutex_unlock(&dev->struct_mutex);
6032 spin_lock_irqsave(&dev->event_lock, flags);
6033 intel_crtc->unpin_work = NULL;
6034 spin_unlock_irqrestore(&dev->event_lock, flags);
6036 drm_vblank_put(dev, intel_crtc->pipe);
6043 static void intel_sanitize_modesetting(struct drm_device *dev,
6044 int pipe, int plane)
6046 struct drm_i915_private *dev_priv = dev->dev_private;
6049 /* Clear any frame start delays used for debugging left by the BIOS */
6050 for_each_pipe(pipe) {
6051 reg = PIPECONF(pipe);
6052 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6055 if (HAS_PCH_SPLIT(dev))
6058 /* Who knows what state these registers were left in by the BIOS or
6061 * If we leave the registers in a conflicting state (e.g. with the
6062 * display plane reading from the other pipe than the one we intend
6063 * to use) then when we attempt to teardown the active mode, we will
6064 * not disable the pipes and planes in the correct order -- leaving
6065 * a plane reading from a disabled pipe and possibly leading to
6066 * undefined behaviour.
6069 reg = DSPCNTR(plane);
6070 val = I915_READ(reg);
6072 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6074 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6077 /* This display plane is active and attached to the other CPU pipe. */
6080 /* Disable the plane and wait for it to stop reading from the pipe. */
6081 intel_disable_plane(dev_priv, plane, pipe);
6082 intel_disable_pipe(dev_priv, pipe);
6085 static void intel_crtc_reset(struct drm_crtc *crtc)
6087 struct drm_device *dev = crtc->dev;
6088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6090 /* Reset flags back to the 'unknown' status so that they
6091 * will be correctly set on the initial modeset.
6093 intel_crtc->dpms_mode = -1;
6095 /* We need to fix up any BIOS configuration that conflicts with
6098 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6101 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6102 .dpms = intel_crtc_dpms,
6103 .mode_fixup = intel_crtc_mode_fixup,
6104 .mode_set = intel_crtc_mode_set,
6105 .mode_set_base = intel_pipe_set_base,
6106 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6107 .load_lut = intel_crtc_load_lut,
6108 .disable = intel_crtc_disable,
6111 static const struct drm_crtc_funcs intel_crtc_funcs = {
6112 .reset = intel_crtc_reset,
6113 .cursor_set = intel_crtc_cursor_set,
6114 .cursor_move = intel_crtc_cursor_move,
6115 .gamma_set = intel_crtc_gamma_set,
6116 .set_config = drm_crtc_helper_set_config,
6117 .destroy = intel_crtc_destroy,
6118 .page_flip = intel_crtc_page_flip,
6121 static void intel_pch_pll_init(struct drm_device *dev)
6123 drm_i915_private_t *dev_priv = dev->dev_private;
6126 if (dev_priv->num_pch_pll == 0) {
6127 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6131 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6132 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6133 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6134 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6138 static void intel_crtc_init(struct drm_device *dev, int pipe)
6140 drm_i915_private_t *dev_priv = dev->dev_private;
6141 struct intel_crtc *intel_crtc;
6144 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6145 if (intel_crtc == NULL)
6148 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6150 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6151 for (i = 0; i < 256; i++) {
6152 intel_crtc->lut_r[i] = i;
6153 intel_crtc->lut_g[i] = i;
6154 intel_crtc->lut_b[i] = i;
6157 /* Swap pipes & planes for FBC on pre-965 */
6158 intel_crtc->pipe = pipe;
6159 intel_crtc->plane = pipe;
6160 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6161 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6162 intel_crtc->plane = !pipe;
6165 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6166 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6167 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6168 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6170 intel_crtc_reset(&intel_crtc->base);
6171 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6172 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6174 if (HAS_PCH_SPLIT(dev)) {
6175 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6176 intel_helper_funcs.commit = ironlake_crtc_commit;
6178 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6179 intel_helper_funcs.commit = i9xx_crtc_commit;
6182 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6184 intel_crtc->busy = false;
6186 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6187 (unsigned long)intel_crtc);
6190 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6191 struct drm_file *file)
6193 drm_i915_private_t *dev_priv = dev->dev_private;
6194 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6195 struct drm_mode_object *drmmode_obj;
6196 struct intel_crtc *crtc;
6199 DRM_ERROR("called with no initialization\n");
6203 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6204 DRM_MODE_OBJECT_CRTC);
6207 DRM_ERROR("no such CRTC id\n");
6211 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6212 pipe_from_crtc_id->pipe = crtc->pipe;
6217 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6219 struct intel_encoder *encoder;
6223 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6224 if (type_mask & encoder->clone_mask)
6225 index_mask |= (1 << entry);
6232 static bool has_edp_a(struct drm_device *dev)
6234 struct drm_i915_private *dev_priv = dev->dev_private;
6236 if (!IS_MOBILE(dev))
6239 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6243 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6249 static void intel_setup_outputs(struct drm_device *dev)
6251 struct drm_i915_private *dev_priv = dev->dev_private;
6252 struct intel_encoder *encoder;
6253 bool dpd_is_edp = false;
6256 has_lvds = intel_lvds_init(dev);
6257 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6258 /* disable the panel fitter on everything but LVDS */
6259 I915_WRITE(PFIT_CONTROL, 0);
6262 if (HAS_PCH_SPLIT(dev)) {
6263 dpd_is_edp = intel_dpd_is_edp(dev);
6266 intel_dp_init(dev, DP_A);
6268 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6269 intel_dp_init(dev, PCH_DP_D);
6272 intel_crt_init(dev);
6274 if (HAS_PCH_SPLIT(dev)) {
6277 if (I915_READ(HDMIB) & PORT_DETECTED) {
6278 /* PCH SDVOB multiplex with HDMIB */
6279 found = intel_sdvo_init(dev, PCH_SDVOB, true);
6281 intel_hdmi_init(dev, HDMIB);
6282 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6283 intel_dp_init(dev, PCH_DP_B);
6286 if (I915_READ(HDMIC) & PORT_DETECTED)
6287 intel_hdmi_init(dev, HDMIC);
6289 if (I915_READ(HDMID) & PORT_DETECTED)
6290 intel_hdmi_init(dev, HDMID);
6292 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6293 intel_dp_init(dev, PCH_DP_C);
6295 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6296 intel_dp_init(dev, PCH_DP_D);
6298 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6301 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6302 DRM_DEBUG_KMS("probing SDVOB\n");
6303 found = intel_sdvo_init(dev, SDVOB, true);
6304 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6305 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6306 intel_hdmi_init(dev, SDVOB);
6309 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6310 DRM_DEBUG_KMS("probing DP_B\n");
6311 intel_dp_init(dev, DP_B);
6315 /* Before G4X SDVOC doesn't have its own detect register */
6317 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6318 DRM_DEBUG_KMS("probing SDVOC\n");
6319 found = intel_sdvo_init(dev, SDVOC, false);
6322 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6324 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6325 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6326 intel_hdmi_init(dev, SDVOC);
6328 if (SUPPORTS_INTEGRATED_DP(dev)) {
6329 DRM_DEBUG_KMS("probing DP_C\n");
6330 intel_dp_init(dev, DP_C);
6334 if (SUPPORTS_INTEGRATED_DP(dev) &&
6335 (I915_READ(DP_D) & DP_DETECTED)) {
6336 DRM_DEBUG_KMS("probing DP_D\n");
6337 intel_dp_init(dev, DP_D);
6339 } else if (IS_GEN2(dev))
6340 intel_dvo_init(dev);
6342 if (SUPPORTS_TV(dev))
6345 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6346 encoder->base.possible_crtcs = encoder->crtc_mask;
6347 encoder->base.possible_clones =
6348 intel_encoder_clones(dev, encoder->clone_mask);
6351 /* disable all the possible outputs/crtcs before entering KMS mode */
6352 drm_helper_disable_unused_functions(dev);
6354 if (HAS_PCH_SPLIT(dev))
6355 ironlake_init_pch_refclk(dev);
6358 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6360 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6362 drm_framebuffer_cleanup(fb);
6363 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6368 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6369 struct drm_file *file,
6370 unsigned int *handle)
6372 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6373 struct drm_i915_gem_object *obj = intel_fb->obj;
6375 return drm_gem_handle_create(file, &obj->base, handle);
6378 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6379 .destroy = intel_user_framebuffer_destroy,
6380 .create_handle = intel_user_framebuffer_create_handle,
6383 int intel_framebuffer_init(struct drm_device *dev,
6384 struct intel_framebuffer *intel_fb,
6385 struct drm_mode_fb_cmd2 *mode_cmd,
6386 struct drm_i915_gem_object *obj)
6390 if (obj->tiling_mode == I915_TILING_Y)
6393 if (mode_cmd->pitches[0] & 63)
6396 switch (mode_cmd->pixel_format) {
6397 case DRM_FORMAT_RGB332:
6398 case DRM_FORMAT_RGB565:
6399 case DRM_FORMAT_XRGB8888:
6400 case DRM_FORMAT_XBGR8888:
6401 case DRM_FORMAT_ARGB8888:
6402 case DRM_FORMAT_XRGB2101010:
6403 case DRM_FORMAT_ARGB2101010:
6404 /* RGB formats are common across chipsets */
6406 case DRM_FORMAT_YUYV:
6407 case DRM_FORMAT_UYVY:
6408 case DRM_FORMAT_YVYU:
6409 case DRM_FORMAT_VYUY:
6412 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6413 mode_cmd->pixel_format);
6417 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6419 DRM_ERROR("framebuffer init failed %d\n", ret);
6423 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6424 intel_fb->obj = obj;
6428 static struct drm_framebuffer *
6429 intel_user_framebuffer_create(struct drm_device *dev,
6430 struct drm_file *filp,
6431 struct drm_mode_fb_cmd2 *mode_cmd)
6433 struct drm_i915_gem_object *obj;
6435 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6436 mode_cmd->handles[0]));
6437 if (&obj->base == NULL)
6438 return ERR_PTR(-ENOENT);
6440 return intel_framebuffer_create(dev, mode_cmd, obj);
6443 static const struct drm_mode_config_funcs intel_mode_funcs = {
6444 .fb_create = intel_user_framebuffer_create,
6445 .output_poll_changed = intel_fb_output_poll_changed,
6448 /* Set up chip specific display functions */
6449 static void intel_init_display(struct drm_device *dev)
6451 struct drm_i915_private *dev_priv = dev->dev_private;
6453 /* We always want a DPMS function */
6454 if (HAS_PCH_SPLIT(dev)) {
6455 dev_priv->display.dpms = ironlake_crtc_dpms;
6456 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6457 dev_priv->display.off = ironlake_crtc_off;
6458 dev_priv->display.update_plane = ironlake_update_plane;
6460 dev_priv->display.dpms = i9xx_crtc_dpms;
6461 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6462 dev_priv->display.off = i9xx_crtc_off;
6463 dev_priv->display.update_plane = i9xx_update_plane;
6466 /* Returns the core display clock speed */
6467 if (IS_VALLEYVIEW(dev))
6468 dev_priv->display.get_display_clock_speed =
6469 valleyview_get_display_clock_speed;
6470 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6471 dev_priv->display.get_display_clock_speed =
6472 i945_get_display_clock_speed;
6473 else if (IS_I915G(dev))
6474 dev_priv->display.get_display_clock_speed =
6475 i915_get_display_clock_speed;
6476 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6477 dev_priv->display.get_display_clock_speed =
6478 i9xx_misc_get_display_clock_speed;
6479 else if (IS_I915GM(dev))
6480 dev_priv->display.get_display_clock_speed =
6481 i915gm_get_display_clock_speed;
6482 else if (IS_I865G(dev))
6483 dev_priv->display.get_display_clock_speed =
6484 i865_get_display_clock_speed;
6485 else if (IS_I85X(dev))
6486 dev_priv->display.get_display_clock_speed =
6487 i855_get_display_clock_speed;
6489 dev_priv->display.get_display_clock_speed =
6490 i830_get_display_clock_speed;
6492 if (HAS_PCH_SPLIT(dev)) {
6494 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6495 dev_priv->display.write_eld = ironlake_write_eld;
6496 } else if (IS_GEN6(dev)) {
6497 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6498 dev_priv->display.write_eld = ironlake_write_eld;
6499 } else if (IS_IVYBRIDGE(dev)) {
6500 /* FIXME: detect B0+ stepping and use auto training */
6501 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6502 dev_priv->display.write_eld = ironlake_write_eld;
6504 dev_priv->display.update_wm = NULL;
6505 } else if (IS_VALLEYVIEW(dev)) {
6506 dev_priv->display.force_wake_get = vlv_force_wake_get;
6507 dev_priv->display.force_wake_put = vlv_force_wake_put;
6508 } else if (IS_G4X(dev)) {
6509 dev_priv->display.write_eld = g4x_write_eld;
6512 /* Default just returns -ENODEV to indicate unsupported */
6513 dev_priv->display.queue_flip = intel_default_queue_flip;
6515 switch (INTEL_INFO(dev)->gen) {
6517 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6521 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6526 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6530 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6533 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6539 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6540 * resume, or other times. This quirk makes sure that's the case for
6543 static void quirk_pipea_force(struct drm_device *dev)
6545 struct drm_i915_private *dev_priv = dev->dev_private;
6547 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6548 DRM_INFO("applying pipe a force quirk\n");
6552 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6554 static void quirk_ssc_force_disable(struct drm_device *dev)
6556 struct drm_i915_private *dev_priv = dev->dev_private;
6557 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6558 DRM_INFO("applying lvds SSC disable quirk\n");
6562 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6565 static void quirk_invert_brightness(struct drm_device *dev)
6567 struct drm_i915_private *dev_priv = dev->dev_private;
6568 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6569 DRM_INFO("applying inverted panel brightness quirk\n");
6572 struct intel_quirk {
6574 int subsystem_vendor;
6575 int subsystem_device;
6576 void (*hook)(struct drm_device *dev);
6579 static struct intel_quirk intel_quirks[] = {
6580 /* HP Mini needs pipe A force quirk (LP: #322104) */
6581 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6583 /* Thinkpad R31 needs pipe A force quirk */
6584 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6585 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6586 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6588 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6589 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6590 /* ThinkPad X40 needs pipe A force quirk */
6592 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6593 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6595 /* 855 & before need to leave pipe A & dpll A up */
6596 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6597 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6599 /* Lenovo U160 cannot use SSC on LVDS */
6600 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6602 /* Sony Vaio Y cannot use SSC on LVDS */
6603 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6605 /* Acer Aspire 5734Z must invert backlight brightness */
6606 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6609 static void intel_init_quirks(struct drm_device *dev)
6611 struct pci_dev *d = dev->pdev;
6614 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6615 struct intel_quirk *q = &intel_quirks[i];
6617 if (d->device == q->device &&
6618 (d->subsystem_vendor == q->subsystem_vendor ||
6619 q->subsystem_vendor == PCI_ANY_ID) &&
6620 (d->subsystem_device == q->subsystem_device ||
6621 q->subsystem_device == PCI_ANY_ID))
6626 /* Disable the VGA plane that we never use */
6627 static void i915_disable_vga(struct drm_device *dev)
6629 struct drm_i915_private *dev_priv = dev->dev_private;
6633 if (HAS_PCH_SPLIT(dev))
6634 vga_reg = CPU_VGACNTRL;
6638 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6639 outb(SR01, VGA_SR_INDEX);
6640 sr1 = inb(VGA_SR_DATA);
6641 outb(sr1 | 1<<5, VGA_SR_DATA);
6642 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6645 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6646 POSTING_READ(vga_reg);
6649 static void ivb_pch_pwm_override(struct drm_device *dev)
6651 struct drm_i915_private *dev_priv = dev->dev_private;
6654 * IVB has CPU eDP backlight regs too, set things up to let the
6655 * PCH regs control the backlight
6657 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6658 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6659 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6662 void intel_modeset_init_hw(struct drm_device *dev)
6664 struct drm_i915_private *dev_priv = dev->dev_private;
6666 intel_init_clock_gating(dev);
6668 if (IS_IRONLAKE_M(dev)) {
6669 ironlake_enable_drps(dev);
6670 intel_init_emon(dev);
6673 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6674 gen6_enable_rps(dev_priv);
6675 gen6_update_ring_freq(dev_priv);
6678 if (IS_IVYBRIDGE(dev))
6679 ivb_pch_pwm_override(dev);
6682 void intel_modeset_init(struct drm_device *dev)
6684 struct drm_i915_private *dev_priv = dev->dev_private;
6687 drm_mode_config_init(dev);
6689 dev->mode_config.min_width = 0;
6690 dev->mode_config.min_height = 0;
6692 dev->mode_config.preferred_depth = 24;
6693 dev->mode_config.prefer_shadow = 1;
6695 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6697 intel_init_quirks(dev);
6701 intel_init_display(dev);
6704 dev->mode_config.max_width = 2048;
6705 dev->mode_config.max_height = 2048;
6706 } else if (IS_GEN3(dev)) {
6707 dev->mode_config.max_width = 4096;
6708 dev->mode_config.max_height = 4096;
6710 dev->mode_config.max_width = 8192;
6711 dev->mode_config.max_height = 8192;
6713 dev->mode_config.fb_base = dev->agp->base;
6715 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6716 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6718 for (i = 0; i < dev_priv->num_pipe; i++) {
6719 intel_crtc_init(dev, i);
6720 ret = intel_plane_init(dev, i);
6722 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6725 intel_pch_pll_init(dev);
6727 /* Just disable it once at startup */
6728 i915_disable_vga(dev);
6729 intel_setup_outputs(dev);
6731 intel_modeset_init_hw(dev);
6733 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6734 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6735 (unsigned long)dev);
6738 void intel_modeset_gem_init(struct drm_device *dev)
6740 if (IS_IRONLAKE_M(dev))
6741 ironlake_enable_rc6(dev);
6743 intel_setup_overlay(dev);
6746 void intel_modeset_cleanup(struct drm_device *dev)
6748 struct drm_i915_private *dev_priv = dev->dev_private;
6749 struct drm_crtc *crtc;
6750 struct intel_crtc *intel_crtc;
6752 drm_kms_helper_poll_fini(dev);
6753 mutex_lock(&dev->struct_mutex);
6755 intel_unregister_dsm_handler();
6758 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6759 /* Skip inactive CRTCs */
6763 intel_crtc = to_intel_crtc(crtc);
6764 intel_increase_pllclock(crtc);
6767 intel_disable_fbc(dev);
6769 if (IS_IRONLAKE_M(dev))
6770 ironlake_disable_drps(dev);
6771 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
6772 gen6_disable_rps(dev);
6774 if (IS_IRONLAKE_M(dev))
6775 ironlake_disable_rc6(dev);
6777 if (IS_VALLEYVIEW(dev))
6780 mutex_unlock(&dev->struct_mutex);
6782 /* Disable the irq before mode object teardown, for the irq might
6783 * enqueue unpin/hotplug work. */
6784 drm_irq_uninstall(dev);
6785 cancel_work_sync(&dev_priv->hotplug_work);
6786 cancel_work_sync(&dev_priv->rps_work);
6788 /* flush any delayed tasks or pending work */
6789 flush_scheduled_work();
6791 /* Shut off idle work before the crtcs get freed. */
6792 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6793 intel_crtc = to_intel_crtc(crtc);
6794 del_timer_sync(&intel_crtc->idle_timer);
6796 del_timer_sync(&dev_priv->idle_timer);
6797 cancel_work_sync(&dev_priv->idle_work);
6799 drm_mode_config_cleanup(dev);
6803 * Return which encoder is currently attached for connector.
6805 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6807 return &intel_attached_encoder(connector)->base;
6810 void intel_connector_attach_encoder(struct intel_connector *connector,
6811 struct intel_encoder *encoder)
6813 connector->encoder = encoder;
6814 drm_mode_connector_attach_encoder(&connector->base,
6819 * set vga decode state - true == enable VGA decode
6821 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6823 struct drm_i915_private *dev_priv = dev->dev_private;
6826 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6828 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6830 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6831 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6835 #ifdef CONFIG_DEBUG_FS
6836 #include <linux/seq_file.h>
6838 struct intel_display_error_state {
6839 struct intel_cursor_error_state {
6846 struct intel_pipe_error_state {
6858 struct intel_plane_error_state {
6869 struct intel_display_error_state *
6870 intel_display_capture_error_state(struct drm_device *dev)
6872 drm_i915_private_t *dev_priv = dev->dev_private;
6873 struct intel_display_error_state *error;
6876 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6880 for (i = 0; i < 2; i++) {
6881 error->cursor[i].control = I915_READ(CURCNTR(i));
6882 error->cursor[i].position = I915_READ(CURPOS(i));
6883 error->cursor[i].base = I915_READ(CURBASE(i));
6885 error->plane[i].control = I915_READ(DSPCNTR(i));
6886 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6887 error->plane[i].size = I915_READ(DSPSIZE(i));
6888 error->plane[i].pos = I915_READ(DSPPOS(i));
6889 error->plane[i].addr = I915_READ(DSPADDR(i));
6890 if (INTEL_INFO(dev)->gen >= 4) {
6891 error->plane[i].surface = I915_READ(DSPSURF(i));
6892 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6895 error->pipe[i].conf = I915_READ(PIPECONF(i));
6896 error->pipe[i].source = I915_READ(PIPESRC(i));
6897 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6898 error->pipe[i].hblank = I915_READ(HBLANK(i));
6899 error->pipe[i].hsync = I915_READ(HSYNC(i));
6900 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6901 error->pipe[i].vblank = I915_READ(VBLANK(i));
6902 error->pipe[i].vsync = I915_READ(VSYNC(i));
6909 intel_display_print_error_state(struct seq_file *m,
6910 struct drm_device *dev,
6911 struct intel_display_error_state *error)
6915 for (i = 0; i < 2; i++) {
6916 seq_printf(m, "Pipe [%d]:\n", i);
6917 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6918 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6919 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6920 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6921 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6922 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6923 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6924 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6926 seq_printf(m, "Plane [%d]:\n", i);
6927 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6928 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6929 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6930 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6931 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6932 if (INTEL_INFO(dev)->gen >= 4) {
6933 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6934 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6937 seq_printf(m, "Cursor [%d]:\n", i);
6938 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6939 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6940 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);