drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 /* FDI */
  80 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  81
  82 static bool
  83 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  84                     int target, int refclk, intel_clock_t *best_clock);
  85 static bool
  86 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  87                         int target, int refclk, intel_clock_t *best_clock);
  88
  89 static bool
  90 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  91                       int target, int refclk, intel_clock_t *best_clock);
  92 static bool
  93 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                            int target, int refclk, intel_clock_t *best_clock);
  95
  96 static inline u32 /* units of 100MHz */
  97 intel_fdi_link_freq(struct drm_device *dev)
  98 {
  99         if (IS_GEN5(dev)) {
 100                 struct drm_i915_private *dev_priv = dev->dev_private;
 101                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 102         } else
 103                 return 27;
 104 }
 105
 106 static const intel_limit_t intel_limits_i8xx_dvo = {
 107         .dot = { .min = 25000, .max = 350000 },
 108         .vco = { .min = 930000, .max = 1400000 },
 109         .n = { .min = 3, .max = 16 },
 110         .m = { .min = 96, .max = 140 },
 111         .m1 = { .min = 18, .max = 26 },
 112         .m2 = { .min = 6, .max = 16 },
 113         .p = { .min = 4, .max = 128 },
 114         .p1 = { .min = 2, .max = 33 },
 115         .p2 = { .dot_limit = 165000,
 116                 .p2_slow = 4, .p2_fast = 2 },
 117         .find_pll = intel_find_best_PLL,
 118 };
 119
 120 static const intel_limit_t intel_limits_i8xx_lvds = {
 121         .dot = { .min = 25000, .max = 350000 },
 122         .vco = { .min = 930000, .max = 1400000 },
 123         .n = { .min = 3, .max = 16 },
 124         .m = { .min = 96, .max = 140 },
 125         .m1 = { .min = 18, .max = 26 },
 126         .m2 = { .min = 6, .max = 16 },
 127         .p = { .min = 4, .max = 128 },
 128         .p1 = { .min = 1, .max = 6 },
 129         .p2 = { .dot_limit = 165000,
 130                 .p2_slow = 14, .p2_fast = 7 },
 131         .find_pll = intel_find_best_PLL,
 132 };
 133
 134 static const intel_limit_t intel_limits_i9xx_sdvo = {
 135         .dot = { .min = 20000, .max = 400000 },
 136         .vco = { .min = 1400000, .max = 2800000 },
 137         .n = { .min = 1, .max = 6 },
 138         .m = { .min = 70, .max = 120 },
 139         .m1 = { .min = 10, .max = 22 },
 140         .m2 = { .min = 5, .max = 9 },
 141         .p = { .min = 5, .max = 80 },
 142         .p1 = { .min = 1, .max = 8 },
 143         .p2 = { .dot_limit = 200000,
 144                 .p2_slow = 10, .p2_fast = 5 },
 145         .find_pll = intel_find_best_PLL,
 146 };
 147
 148 static const intel_limit_t intel_limits_i9xx_lvds = {
 149         .dot = { .min = 20000, .max = 400000 },
 150         .vco = { .min = 1400000, .max = 2800000 },
 151         .n = { .min = 1, .max = 6 },
 152         .m = { .min = 70, .max = 120 },
 153         .m1 = { .min = 10, .max = 22 },
 154         .m2 = { .min = 5, .max = 9 },
 155         .p = { .min = 7, .max = 98 },
 156         .p1 = { .min = 1, .max = 8 },
 157         .p2 = { .dot_limit = 112000,
 158                 .p2_slow = 14, .p2_fast = 7 },
 159         .find_pll = intel_find_best_PLL,
 160 };
 161
 162
 163 static const intel_limit_t intel_limits_g4x_sdvo = {
 164         .dot = { .min = 25000, .max = 270000 },
 165         .vco = { .min = 1750000, .max = 3500000},
 166         .n = { .min = 1, .max = 4 },
 167         .m = { .min = 104, .max = 138 },
 168         .m1 = { .min = 17, .max = 23 },
 169         .m2 = { .min = 5, .max = 11 },
 170         .p = { .min = 10, .max = 30 },
 171         .p1 = { .min = 1, .max = 3},
 172         .p2 = { .dot_limit = 270000,
 173                 .p2_slow = 10,
 174                 .p2_fast = 10
 175         },
 176         .find_pll = intel_g4x_find_best_PLL,
 177 };
 178
 179 static const intel_limit_t intel_limits_g4x_hdmi = {
 180         .dot = { .min = 22000, .max = 400000 },
 181         .vco = { .min = 1750000, .max = 3500000},
 182         .n = { .min = 1, .max = 4 },
 183         .m = { .min = 104, .max = 138 },
 184         .m1 = { .min = 16, .max = 23 },
 185         .m2 = { .min = 5, .max = 11 },
 186         .p = { .min = 5, .max = 80 },
 187         .p1 = { .min = 1, .max = 8},
 188         .p2 = { .dot_limit = 165000,
 189                 .p2_slow = 10, .p2_fast = 5 },
 190         .find_pll = intel_g4x_find_best_PLL,
 191 };
 192
 193 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 194         .dot = { .min = 20000, .max = 115000 },
 195         .vco = { .min = 1750000, .max = 3500000 },
 196         .n = { .min = 1, .max = 3 },
 197         .m = { .min = 104, .max = 138 },
 198         .m1 = { .min = 17, .max = 23 },
 199         .m2 = { .min = 5, .max = 11 },
 200         .p = { .min = 28, .max = 112 },
 201         .p1 = { .min = 2, .max = 8 },
 202         .p2 = { .dot_limit = 0,
 203                 .p2_slow = 14, .p2_fast = 14
 204         },
 205         .find_pll = intel_g4x_find_best_PLL,
 206 };
 207
 208 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 209         .dot = { .min = 80000, .max = 224000 },
 210         .vco = { .min = 1750000, .max = 3500000 },
 211         .n = { .min = 1, .max = 3 },
 212         .m = { .min = 104, .max = 138 },
 213         .m1 = { .min = 17, .max = 23 },
 214         .m2 = { .min = 5, .max = 11 },
 215         .p = { .min = 14, .max = 42 },
 216         .p1 = { .min = 2, .max = 6 },
 217         .p2 = { .dot_limit = 0,
 218                 .p2_slow = 7, .p2_fast = 7
 219         },
 220         .find_pll = intel_g4x_find_best_PLL,
 221 };
 222
 223 static const intel_limit_t intel_limits_g4x_display_port = {
 224         .dot = { .min = 161670, .max = 227000 },
 225         .vco = { .min = 1750000, .max = 3500000},
 226         .n = { .min = 1, .max = 2 },
 227         .m = { .min = 97, .max = 108 },
 228         .m1 = { .min = 0x10, .max = 0x12 },
 229         .m2 = { .min = 0x05, .max = 0x06 },
 230         .p = { .min = 10, .max = 20 },
 231         .p1 = { .min = 1, .max = 2},
 232         .p2 = { .dot_limit = 0,
 233                 .p2_slow = 10, .p2_fast = 10 },
 234         .find_pll = intel_find_pll_g4x_dp,
 235 };
 236
 237 static const intel_limit_t intel_limits_pineview_sdvo = {
 238         .dot = { .min = 20000, .max = 400000},
 239         .vco = { .min = 1700000, .max = 3500000 },
 240         /* Pineview's Ncounter is a ring counter */
 241         .n = { .min = 3, .max = 6 },
 242         .m = { .min = 2, .max = 256 },
 243         /* Pineview only has one combined m divider, which we treat as m2. */
 244         .m1 = { .min = 0, .max = 0 },
 245         .m2 = { .min = 0, .max = 254 },
 246         .p = { .min = 5, .max = 80 },
 247         .p1 = { .min = 1, .max = 8 },
 248         .p2 = { .dot_limit = 200000,
 249                 .p2_slow = 10, .p2_fast = 5 },
 250         .find_pll = intel_find_best_PLL,
 251 };
 252
 253 static const intel_limit_t intel_limits_pineview_lvds = {
 254         .dot = { .min = 20000, .max = 400000 },
 255         .vco = { .min = 1700000, .max = 3500000 },
 256         .n = { .min = 3, .max = 6 },
 257         .m = { .min = 2, .max = 256 },
 258         .m1 = { .min = 0, .max = 0 },
 259         .m2 = { .min = 0, .max = 254 },
 260         .p = { .min = 7, .max = 112 },
 261         .p1 = { .min = 1, .max = 8 },
 262         .p2 = { .dot_limit = 112000,
 263                 .p2_slow = 14, .p2_fast = 14 },
 264         .find_pll = intel_find_best_PLL,
 265 };
 266
 267 /* Ironlake / Sandybridge
 268  *
 269  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 270  * the range value for them is (actual_value - 2).
 271  */
 272 static const intel_limit_t intel_limits_ironlake_dac = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 5 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283         .find_pll = intel_g4x_find_best_PLL,
 284 };
 285
 286 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 3 },
 290         .m = { .min = 79, .max = 118 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297         .find_pll = intel_g4x_find_best_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 3 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 14, .max = 56 },
 308         .p1 = { .min = 2, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 7, .p2_fast = 7 },
 311         .find_pll = intel_g4x_find_best_PLL,
 312 };
 313
 314 /* LVDS 100mhz refclk limits. */
 315 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 316         .dot = { .min = 25000, .max = 350000 },
 317         .vco = { .min = 1760000, .max = 3510000 },
 318         .n = { .min = 1, .max = 2 },
 319         .m = { .min = 79, .max = 126 },
 320         .m1 = { .min = 12, .max = 22 },
 321         .m2 = { .min = 5, .max = 9 },
 322         .p = { .min = 28, .max = 112 },
 323         .p1 = { .min = 2,.max = 8 },
 324         .p2 = { .dot_limit = 225000,
 325                 .p2_slow = 14, .p2_fast = 14 },
 326         .find_pll = intel_g4x_find_best_PLL,
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 126 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 42 },
 337         .p1 = { .min = 2,.max = 6 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340         .find_pll = intel_g4x_find_best_PLL,
 341 };
 342
 343 static const intel_limit_t intel_limits_ironlake_display_port = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000},
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 81, .max = 90 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 10, .max = 20 },
 351         .p1 = { .min = 1, .max = 2},
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 10, .p2_fast = 10 },
 354         .find_pll = intel_find_pll_ironlake_dp,
 355 };
 356
 357 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 358                                                 int refclk)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         struct drm_i915_private *dev_priv = dev->dev_private;
 362         const intel_limit_t *limit;
 363
 364         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 365                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 366                     LVDS_CLKB_POWER_UP) {
 367                         /* LVDS dual channel */
 368                         if (refclk == 100000)
 369                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 370                         else
 371                                 limit = &intel_limits_ironlake_dual_lvds;
 372                 } else {
 373                         if (refclk == 100000)
 374                                 limit = &intel_limits_ironlake_single_lvds_100m;
 375                         else
 376                                 limit = &intel_limits_ironlake_single_lvds;
 377                 }
 378         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 379                         HAS_eDP)
 380                 limit = &intel_limits_ironlake_display_port;
 381         else
 382                 limit = &intel_limits_ironlake_dac;
 383
 384         return limit;
 385 }
 386
 387 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 388 {
 389         struct drm_device *dev = crtc->dev;
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         const intel_limit_t *limit;
 392
 393         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 394                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 395                     LVDS_CLKB_POWER_UP)
 396                         /* LVDS with dual channel */
 397                         limit = &intel_limits_g4x_dual_channel_lvds;
 398                 else
 399                         /* LVDS with dual channel */
 400                         limit = &intel_limits_g4x_single_channel_lvds;
 401         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 402                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 403                 limit = &intel_limits_g4x_hdmi;
 404         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 405                 limit = &intel_limits_g4x_sdvo;
 406         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 407                 limit = &intel_limits_g4x_display_port;
 408         } else /* The option is for other outputs */
 409                 limit = &intel_limits_i9xx_sdvo;
 410
 411         return limit;
 412 }
 413
 414 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 415 {
 416         struct drm_device *dev = crtc->dev;
 417         const intel_limit_t *limit;
 418
 419         if (HAS_PCH_SPLIT(dev))
 420                 limit = intel_ironlake_limit(crtc, refclk);
 421         else if (IS_G4X(dev)) {
 422                 limit = intel_g4x_limit(crtc);
 423         } else if (IS_PINEVIEW(dev)) {
 424                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 425                         limit = &intel_limits_pineview_lvds;
 426                 else
 427                         limit = &intel_limits_pineview_sdvo;
 428         } else if (!IS_GEN2(dev)) {
 429                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 430                         limit = &intel_limits_i9xx_lvds;
 431                 else
 432                         limit = &intel_limits_i9xx_sdvo;
 433         } else {
 434                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 435                         limit = &intel_limits_i8xx_lvds;
 436                 else
 437                         limit = &intel_limits_i8xx_dvo;
 438         }
 439         return limit;
 440 }
 441
 442 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 443 static void pineview_clock(int refclk, intel_clock_t *clock)
 444 {
 445         clock->m = clock->m2 + 2;
 446         clock->p = clock->p1 * clock->p2;
 447         clock->vco = refclk * clock->m / clock->n;
 448         clock->dot = clock->vco / clock->p;
 449 }
 450
 451 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 452 {
 453         if (IS_PINEVIEW(dev)) {
 454                 pineview_clock(refclk, clock);
 455                 return;
 456         }
 457         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 458         clock->p = clock->p1 * clock->p2;
 459         clock->vco = refclk * clock->m / (clock->n + 2);
 460         clock->dot = clock->vco / clock->p;
 461 }
 462
 463 /**
 464  * Returns whether any output on the specified pipe is of the specified type
 465  */
 466 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 467 {
 468         struct drm_device *dev = crtc->dev;
 469         struct drm_mode_config *mode_config = &dev->mode_config;
 470         struct intel_encoder *encoder;
 471
 472         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 473                 if (encoder->base.crtc == crtc && encoder->type == type)
 474                         return true;
 475
 476         return false;
 477 }
 478
 479 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 480 /**
 481  * Returns whether the given set of divisors are valid for a given refclk with
 482  * the given connectors.
 483  */
 484
 485 static bool intel_PLL_is_valid(struct drm_device *dev,
 486                                const intel_limit_t *limit,
 487                                const intel_clock_t *clock)
 488 {
 489         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 490                 INTELPllInvalid ("p1 out of range\n");
 491         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 492                 INTELPllInvalid ("p out of range\n");
 493         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 494                 INTELPllInvalid ("m2 out of range\n");
 495         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 496                 INTELPllInvalid ("m1 out of range\n");
 497         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 498                 INTELPllInvalid ("m1 <= m2\n");
 499         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 500                 INTELPllInvalid ("m out of range\n");
 501         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 502                 INTELPllInvalid ("n out of range\n");
 503         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 504                 INTELPllInvalid ("vco out of range\n");
 505         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 506          * connector, etc., rather than just a single range.
 507          */
 508         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 509                 INTELPllInvalid ("dot out of range\n");
 510
 511         return true;
 512 }
 513
 514 static bool
 515 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 516                     int target, int refclk, intel_clock_t *best_clock)
 517
 518 {
 519         struct drm_device *dev = crtc->dev;
 520         struct drm_i915_private *dev_priv = dev->dev_private;
 521         intel_clock_t clock;
 522         int err = target;
 523
 524         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 525             (I915_READ(LVDS)) != 0) {
 526                 /*
 527                  * For LVDS, if the panel is on, just rely on its current
 528                  * settings for dual-channel.  We haven't figured out how to
 529                  * reliably set up different single/dual channel state, if we
 530                  * even can.
 531                  */
 532                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 533                     LVDS_CLKB_POWER_UP)
 534                         clock.p2 = limit->p2.p2_fast;
 535                 else
 536                         clock.p2 = limit->p2.p2_slow;
 537         } else {
 538                 if (target < limit->p2.dot_limit)
 539                         clock.p2 = limit->p2.p2_slow;
 540                 else
 541                         clock.p2 = limit->p2.p2_fast;
 542         }
 543
 544         memset (best_clock, 0, sizeof (*best_clock));
 545
 546         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 547              clock.m1++) {
 548                 for (clock.m2 = limit->m2.min;
 549                      clock.m2 <= limit->m2.max; clock.m2++) {
 550                         /* m1 is always 0 in Pineview */
 551                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 552                                 break;
 553                         for (clock.n = limit->n.min;
 554                              clock.n <= limit->n.max; clock.n++) {
 555                                 for (clock.p1 = limit->p1.min;
 556                                         clock.p1 <= limit->p1.max; clock.p1++) {
 557                                         int this_err;
 558
 559                                         intel_clock(dev, refclk, &clock);
 560                                         if (!intel_PLL_is_valid(dev, limit,
 561                                                                 &clock))
 562                                                 continue;
 563
 564                                         this_err = abs(clock.dot - target);
 565                                         if (this_err < err) {
 566                                                 *best_clock = clock;
 567                                                 err = this_err;
 568                                         }
 569                                 }
 570                         }
 571                 }
 572         }
 573
 574         return (err != target);
 575 }
 576
 577 static bool
 578 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 579                         int target, int refclk, intel_clock_t *best_clock)
 580 {
 581         struct drm_device *dev = crtc->dev;
 582         struct drm_i915_private *dev_priv = dev->dev_private;
 583         intel_clock_t clock;
 584         int max_n;
 585         bool found;
 586         /* approximately equals target * 0.00585 */
 587         int err_most = (target >> 8) + (target >> 9);
 588         found = false;
 589
 590         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 591                 int lvds_reg;
 592
 593                 if (HAS_PCH_SPLIT(dev))
 594                         lvds_reg = PCH_LVDS;
 595                 else
 596                         lvds_reg = LVDS;
 597                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 598                     LVDS_CLKB_POWER_UP)
 599                         clock.p2 = limit->p2.p2_fast;
 600                 else
 601                         clock.p2 = limit->p2.p2_slow;
 602         } else {
 603                 if (target < limit->p2.dot_limit)
 604                         clock.p2 = limit->p2.p2_slow;
 605                 else
 606                         clock.p2 = limit->p2.p2_fast;
 607         }
 608
 609         memset(best_clock, 0, sizeof(*best_clock));
 610         max_n = limit->n.max;
 611         /* based on hardware requirement, prefer smaller n to precision */
 612         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 613                 /* based on hardware requirement, prefere larger m1,m2 */
 614                 for (clock.m1 = limit->m1.max;
 615                      clock.m1 >= limit->m1.min; clock.m1--) {
 616                         for (clock.m2 = limit->m2.max;
 617                              clock.m2 >= limit->m2.min; clock.m2--) {
 618                                 for (clock.p1 = limit->p1.max;
 619                                      clock.p1 >= limit->p1.min; clock.p1--) {
 620                                         int this_err;
 621
 622                                         intel_clock(dev, refclk, &clock);
 623                                         if (!intel_PLL_is_valid(dev, limit,
 624                                                                 &clock))
 625                                                 continue;
 626
 627                                         this_err = abs(clock.dot - target);
 628                                         if (this_err < err_most) {
 629                                                 *best_clock = clock;
 630                                                 err_most = this_err;
 631                                                 max_n = clock.n;
 632                                                 found = true;
 633                                         }
 634                                 }
 635                         }
 636                 }
 637         }
 638         return found;
 639 }
 640
 641 static bool
 642 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 643                            int target, int refclk, intel_clock_t *best_clock)
 644 {
 645         struct drm_device *dev = crtc->dev;
 646         intel_clock_t clock;
 647
 648         if (target < 200000) {
 649                 clock.n = 1;
 650                 clock.p1 = 2;
 651                 clock.p2 = 10;
 652                 clock.m1 = 12;
 653                 clock.m2 = 9;
 654         } else {
 655                 clock.n = 2;
 656                 clock.p1 = 1;
 657                 clock.p2 = 10;
 658                 clock.m1 = 14;
 659                 clock.m2 = 8;
 660         }
 661         intel_clock(dev, refclk, &clock);
 662         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 663         return true;
 664 }
 665
 666 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 667 static bool
 668 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 669                       int target, int refclk, intel_clock_t *best_clock)
 670 {
 671         intel_clock_t clock;
 672         if (target < 200000) {
 673                 clock.p1 = 2;
 674                 clock.p2 = 10;
 675                 clock.n = 2;
 676                 clock.m1 = 23;
 677                 clock.m2 = 8;
 678         } else {
 679                 clock.p1 = 1;
 680                 clock.p2 = 10;
 681                 clock.n = 1;
 682                 clock.m1 = 14;
 683                 clock.m2 = 2;
 684         }
 685         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 686         clock.p = (clock.p1 * clock.p2);
 687         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 688         clock.vco = 0;
 689         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 690         return true;
 691 }
 692
 693 /**
 694  * intel_wait_for_vblank - wait for vblank on a given pipe
 695  * @dev: drm device
 696  * @pipe: pipe to wait for
 697  *
 698  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 699  * mode setting code.
 700  */
 701 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 702 {
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704         int pipestat_reg = PIPESTAT(pipe);
 705
 706         /* Clear existing vblank status. Note this will clear any other
 707          * sticky status fields as well.
 708          *
 709          * This races with i915_driver_irq_handler() with the result
 710          * that either function could miss a vblank event.  Here it is not
 711          * fatal, as we will either wait upon the next vblank interrupt or
 712          * timeout.  Generally speaking intel_wait_for_vblank() is only
 713          * called during modeset at which time the GPU should be idle and
 714          * should *not* be performing page flips and thus not waiting on
 715          * vblanks...
 716          * Currently, the result of us stealing a vblank from the irq
 717          * handler is that a single frame will be skipped during swapbuffers.
 718          */
 719         I915_WRITE(pipestat_reg,
 720                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 721
 722         /* Wait for vblank interrupt bit to set */
 723         if (wait_for(I915_READ(pipestat_reg) &
 724                      PIPE_VBLANK_INTERRUPT_STATUS,
 725                      50))
 726                 DRM_DEBUG_KMS("vblank wait timed out\n");
 727 }
 728
 729 /*
 730  * intel_wait_for_pipe_off - wait for pipe to turn off
 731  * @dev: drm device
 732  * @pipe: pipe to wait for
 733  *
 734  * After disabling a pipe, we can't wait for vblank in the usual way,
 735  * spinning on the vblank interrupt status bit, since we won't actually
 736  * see an interrupt when the pipe is disabled.
 737  *
 738  * On Gen4 and above:
 739  *   wait for the pipe register state bit to turn off
 740  *
 741  * Otherwise:
 742  *   wait for the display line value to settle (it usually
 743  *   ends up stopping at the start of the next frame).
 744  *
 745  */
 746 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 747 {
 748         struct drm_i915_private *dev_priv = dev->dev_private;
 749
 750         if (INTEL_INFO(dev)->gen >= 4) {
 751                 int reg = PIPECONF(pipe);
 752
 753                 /* Wait for the Pipe State to go off */
 754                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 755                              100))
 756                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 757         } else {
 758                 u32 last_line;
 759                 int reg = PIPEDSL(pipe);
 760                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 761
 762                 /* Wait for the display line to settle */
 763                 do {
 764                         last_line = I915_READ(reg) & DSL_LINEMASK;
 765                         mdelay(5);
 766                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 767                          time_after(timeout, jiffies));
 768                 if (time_after(jiffies, timeout))
 769                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 770         }
 771 }
 772
 773 static const char *state_string(bool enabled)
 774 {
 775         return enabled ? "on" : "off";
 776 }
 777
 778 /* Only for pre-ILK configs */
 779 static void assert_pll(struct drm_i915_private *dev_priv,
 780                        enum pipe pipe, bool state)
 781 {
 782         int reg;
 783         u32 val;
 784         bool cur_state;
 785
 786         reg = DPLL(pipe);
 787         val = I915_READ(reg);
 788         cur_state = !!(val & DPLL_VCO_ENABLE);
 789         WARN(cur_state != state,
 790              "PLL state assertion failure (expected %s, current %s)\n",
 791              state_string(state), state_string(cur_state));
 792 }
 793 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 794 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 795
 796 /* For ILK+ */
 797 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 798                            enum pipe pipe, bool state)
 799 {
 800         int reg;
 801         u32 val;
 802         bool cur_state;
 803
 804         reg = PCH_DPLL(pipe);
 805         val = I915_READ(reg);
 806         cur_state = !!(val & DPLL_VCO_ENABLE);
 807         WARN(cur_state != state,
 808              "PCH PLL state assertion failure (expected %s, current %s)\n",
 809              state_string(state), state_string(cur_state));
 810 }
 811 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 812 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 813
 814 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 815                           enum pipe pipe, bool state)
 816 {
 817         int reg;
 818         u32 val;
 819         bool cur_state;
 820
 821         reg = FDI_TX_CTL(pipe);
 822         val = I915_READ(reg);
 823         cur_state = !!(val & FDI_TX_ENABLE);
 824         WARN(cur_state != state,
 825              "FDI TX state assertion failure (expected %s, current %s)\n",
 826              state_string(state), state_string(cur_state));
 827 }
 828 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 829 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 830
 831 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 832                           enum pipe pipe, bool state)
 833 {
 834         int reg;
 835         u32 val;
 836         bool cur_state;
 837
 838         reg = FDI_RX_CTL(pipe);
 839         val = I915_READ(reg);
 840         cur_state = !!(val & FDI_RX_ENABLE);
 841         WARN(cur_state != state,
 842              "FDI RX state assertion failure (expected %s, current %s)\n",
 843              state_string(state), state_string(cur_state));
 844 }
 845 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 846 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 847
 848 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 849                                       enum pipe pipe)
 850 {
 851         int reg;
 852         u32 val;
 853
 854         /* ILK FDI PLL is always enabled */
 855         if (dev_priv->info->gen == 5)
 856                 return;
 857
 858         reg = FDI_TX_CTL(pipe);
 859         val = I915_READ(reg);
 860         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 861 }
 862
 863 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 864                                       enum pipe pipe)
 865 {
 866         int reg;
 867         u32 val;
 868
 869         reg = FDI_RX_CTL(pipe);
 870         val = I915_READ(reg);
 871         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 872 }
 873
 874 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 875                                   enum pipe pipe)
 876 {
 877         int pp_reg, lvds_reg;
 878         u32 val;
 879         enum pipe panel_pipe = PIPE_A;
 880         bool locked = locked;
 881
 882         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 883                 pp_reg = PCH_PP_CONTROL;
 884                 lvds_reg = PCH_LVDS;
 885         } else {
 886                 pp_reg = PP_CONTROL;
 887                 lvds_reg = LVDS;
 888         }
 889
 890         val = I915_READ(pp_reg);
 891         if (!(val & PANEL_POWER_ON) ||
 892             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 893                 locked = false;
 894
 895         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 896                 panel_pipe = PIPE_B;
 897
 898         WARN(panel_pipe == pipe && locked,
 899              "panel assertion failure, pipe %c regs locked\n",
 900              pipe_name(pipe));
 901 }
 902
 903 static void assert_pipe(struct drm_i915_private *dev_priv,
 904                         enum pipe pipe, bool state)
 905 {
 906         int reg;
 907         u32 val;
 908         bool cur_state;
 909
 910         reg = PIPECONF(pipe);
 911         val = I915_READ(reg);
 912         cur_state = !!(val & PIPECONF_ENABLE);
 913         WARN(cur_state != state,
 914              "pipe %c assertion failure (expected %s, current %s)\n",
 915              pipe_name(pipe), state_string(state), state_string(cur_state));
 916 }
 917 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 918 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 919
 920 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 921                                  enum plane plane)
 922 {
 923         int reg;
 924         u32 val;
 925
 926         reg = DSPCNTR(plane);
 927         val = I915_READ(reg);
 928         WARN(!(val & DISPLAY_PLANE_ENABLE),
 929              "plane %c assertion failure, should be active but is disabled\n",
 930              plane_name(plane));
 931 }
 932
 933 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 934                                    enum pipe pipe)
 935 {
 936         int reg, i;
 937         u32 val;
 938         int cur_pipe;
 939
 940         /* Planes are fixed to pipes on ILK+ */
 941         if (HAS_PCH_SPLIT(dev_priv->dev))
 942                 return;
 943
 944         /* Need to check both planes against the pipe */
 945         for (i = 0; i < 2; i++) {
 946                 reg = DSPCNTR(i);
 947                 val = I915_READ(reg);
 948                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 949                         DISPPLANE_SEL_PIPE_SHIFT;
 950                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 951                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 952                      plane_name(i), pipe_name(pipe));
 953         }
 954 }
 955
 956 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 957 {
 958         u32 val;
 959         bool enabled;
 960
 961         val = I915_READ(PCH_DREF_CONTROL);
 962         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 963                             DREF_SUPERSPREAD_SOURCE_MASK));
 964         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 965 }
 966
 967 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 968                                        enum pipe pipe)
 969 {
 970         int reg;
 971         u32 val;
 972         bool enabled;
 973
 974         reg = TRANSCONF(pipe);
 975         val = I915_READ(reg);
 976         enabled = !!(val & TRANS_ENABLE);
 977         WARN(enabled,
 978              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 979              pipe_name(pipe));
 980 }
 981
 982 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
 983                             int reg, u32 port_sel, u32 val)
 984 {
 985         if ((val & DP_PORT_EN) == 0)
 986                 return false;
 987
 988         if (HAS_PCH_CPT(dev_priv->dev)) {
 989                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
 990                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
 991                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
 992                         return false;
 993         } else {
 994                 if ((val & DP_PIPE_MASK) != (pipe << 30))
 995                         return false;
 996         }
 997         return true;
 998 }
 999
1000 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1001                                    enum pipe pipe, int reg, u32 port_sel)
1002 {
1003         u32 val = I915_READ(reg);
1004         WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
1005              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1006              reg, pipe_name(pipe));
1007 }
1008
1009 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1010                                      enum pipe pipe, int reg)
1011 {
1012         u32 val = I915_READ(reg);
1013         WARN(HDMI_PIPE_ENABLED(val, pipe),
1014              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1015              reg, pipe_name(pipe));
1016 }
1017
1018 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1019                                       enum pipe pipe)
1020 {
1021         int reg;
1022         u32 val;
1023
1024         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1025         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1026         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1027
1028         reg = PCH_ADPA;
1029         val = I915_READ(reg);
1030         WARN(ADPA_PIPE_ENABLED(val, pipe),
1031              "PCH VGA enabled on transcoder %c, should be disabled\n",
1032              pipe_name(pipe));
1033
1034         reg = PCH_LVDS;
1035         val = I915_READ(reg);
1036         WARN(LVDS_PIPE_ENABLED(val, pipe),
1037              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1038              pipe_name(pipe));
1039
1040         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1041         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1042         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1043 }
1044
1045 /**
1046  * intel_enable_pll - enable a PLL
1047  * @dev_priv: i915 private structure
1048  * @pipe: pipe PLL to enable
1049  *
1050  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1051  * make sure the PLL reg is writable first though, since the panel write
1052  * protect mechanism may be enabled.
1053  *
1054  * Note!  This is for pre-ILK only.
1055  */
1056 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1057 {
1058         int reg;
1059         u32 val;
1060
1061         /* No really, not for ILK+ */
1062         BUG_ON(dev_priv->info->gen >= 5);
1063
1064         /* PLL is protected by panel, make sure we can write it */
1065         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1066                 assert_panel_unlocked(dev_priv, pipe);
1067
1068         reg = DPLL(pipe);
1069         val = I915_READ(reg);
1070         val |= DPLL_VCO_ENABLE;
1071
1072         /* We do this three times for luck */
1073         I915_WRITE(reg, val);
1074         POSTING_READ(reg);
1075         udelay(150); /* wait for warmup */
1076         I915_WRITE(reg, val);
1077         POSTING_READ(reg);
1078         udelay(150); /* wait for warmup */
1079         I915_WRITE(reg, val);
1080         POSTING_READ(reg);
1081         udelay(150); /* wait for warmup */
1082 }
1083
1084 /**
1085  * intel_disable_pll - disable a PLL
1086  * @dev_priv: i915 private structure
1087  * @pipe: pipe PLL to disable
1088  *
1089  * Disable the PLL for @pipe, making sure the pipe is off first.
1090  *
1091  * Note!  This is for pre-ILK only.
1092  */
1093 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1094 {
1095         int reg;
1096         u32 val;
1097
1098         /* Don't disable pipe A or pipe A PLLs if needed */
1099         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1100                 return;
1101
1102         /* Make sure the pipe isn't still relying on us */
1103         assert_pipe_disabled(dev_priv, pipe);
1104
1105         reg = DPLL(pipe);
1106         val = I915_READ(reg);
1107         val &= ~DPLL_VCO_ENABLE;
1108         I915_WRITE(reg, val);
1109         POSTING_READ(reg);
1110 }
1111
1112 /**
1113  * intel_enable_pch_pll - enable PCH PLL
1114  * @dev_priv: i915 private structure
1115  * @pipe: pipe PLL to enable
1116  *
1117  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1118  * drives the transcoder clock.
1119  */
1120 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1121                                  enum pipe pipe)
1122 {
1123         int reg;
1124         u32 val;
1125
1126         /* PCH only available on ILK+ */
1127         BUG_ON(dev_priv->info->gen < 5);
1128
1129         /* PCH refclock must be enabled first */
1130         assert_pch_refclk_enabled(dev_priv);
1131
1132         reg = PCH_DPLL(pipe);
1133         val = I915_READ(reg);
1134         val |= DPLL_VCO_ENABLE;
1135         I915_WRITE(reg, val);
1136         POSTING_READ(reg);
1137         udelay(200);
1138 }
1139
1140 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1141                                   enum pipe pipe)
1142 {
1143         int reg;
1144         u32 val;
1145
1146         /* PCH only available on ILK+ */
1147         BUG_ON(dev_priv->info->gen < 5);
1148
1149         /* Make sure transcoder isn't still depending on us */
1150         assert_transcoder_disabled(dev_priv, pipe);
1151
1152         reg = PCH_DPLL(pipe);
1153         val = I915_READ(reg);
1154         val &= ~DPLL_VCO_ENABLE;
1155         I915_WRITE(reg, val);
1156         POSTING_READ(reg);
1157         udelay(200);
1158 }
1159
1160 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1161                                     enum pipe pipe)
1162 {
1163         int reg;
1164         u32 val;
1165
1166         /* PCH only available on ILK+ */
1167         BUG_ON(dev_priv->info->gen < 5);
1168
1169         /* Make sure PCH DPLL is enabled */
1170         assert_pch_pll_enabled(dev_priv, pipe);
1171
1172         /* FDI must be feeding us bits for PCH ports */
1173         assert_fdi_tx_enabled(dev_priv, pipe);
1174         assert_fdi_rx_enabled(dev_priv, pipe);
1175
1176         reg = TRANSCONF(pipe);
1177         val = I915_READ(reg);
1178         /*
1179          * make the BPC in transcoder be consistent with
1180          * that in pipeconf reg.
1181          */
1182         val &= ~PIPE_BPC_MASK;
1183         val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1184         I915_WRITE(reg, val | TRANS_ENABLE);
1185         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1186                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1187 }
1188
1189 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1190                                      enum pipe pipe)
1191 {
1192         int reg;
1193         u32 val;
1194
1195         /* FDI relies on the transcoder */
1196         assert_fdi_tx_disabled(dev_priv, pipe);
1197         assert_fdi_rx_disabled(dev_priv, pipe);
1198
1199         /* Ports must be off as well */
1200         assert_pch_ports_disabled(dev_priv, pipe);
1201
1202         reg = TRANSCONF(pipe);
1203         val = I915_READ(reg);
1204         val &= ~TRANS_ENABLE;
1205         I915_WRITE(reg, val);
1206         /* wait for PCH transcoder off, transcoder state */
1207         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1208                 DRM_ERROR("failed to disable transcoder\n");
1209 }
1210
1211 /**
1212  * intel_enable_pipe - enable a pipe, asserting requirements
1213  * @dev_priv: i915 private structure
1214  * @pipe: pipe to enable
1215  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1216  *
1217  * Enable @pipe, making sure that various hardware specific requirements
1218  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1219  *
1220  * @pipe should be %PIPE_A or %PIPE_B.
1221  *
1222  * Will wait until the pipe is actually running (i.e. first vblank) before
1223  * returning.
1224  */
1225 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1226                               bool pch_port)
1227 {
1228         int reg;
1229         u32 val;
1230
1231         /*
1232          * A pipe without a PLL won't actually be able to drive bits from
1233          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1234          * need the check.
1235          */
1236         if (!HAS_PCH_SPLIT(dev_priv->dev))
1237                 assert_pll_enabled(dev_priv, pipe);
1238         else {
1239                 if (pch_port) {
1240                         /* if driving the PCH, we need FDI enabled */
1241                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1242                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1243                 }
1244                 /* FIXME: assert CPU port conditions for SNB+ */
1245         }
1246
1247         reg = PIPECONF(pipe);
1248         val = I915_READ(reg);
1249         if (val & PIPECONF_ENABLE)
1250                 return;
1251
1252         I915_WRITE(reg, val | PIPECONF_ENABLE);
1253         intel_wait_for_vblank(dev_priv->dev, pipe);
1254 }
1255
1256 /**
1257  * intel_disable_pipe - disable a pipe, asserting requirements
1258  * @dev_priv: i915 private structure
1259  * @pipe: pipe to disable
1260  *
1261  * Disable @pipe, making sure that various hardware specific requirements
1262  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1263  *
1264  * @pipe should be %PIPE_A or %PIPE_B.
1265  *
1266  * Will wait until the pipe has shut down before returning.
1267  */
1268 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1269                                enum pipe pipe)
1270 {
1271         int reg;
1272         u32 val;
1273
1274         /*
1275          * Make sure planes won't keep trying to pump pixels to us,
1276          * or we might hang the display.
1277          */
1278         assert_planes_disabled(dev_priv, pipe);
1279
1280         /* Don't disable pipe A or pipe A PLLs if needed */
1281         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1282                 return;
1283
1284         reg = PIPECONF(pipe);
1285         val = I915_READ(reg);
1286         if ((val & PIPECONF_ENABLE) == 0)
1287                 return;
1288
1289         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1290         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1291 }
1292
1293 /**
1294  * intel_enable_plane - enable a display plane on a given pipe
1295  * @dev_priv: i915 private structure
1296  * @plane: plane to enable
1297  * @pipe: pipe being fed
1298  *
1299  * Enable @plane on @pipe, making sure that @pipe is running first.
1300  */
1301 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1302                                enum plane plane, enum pipe pipe)
1303 {
1304         int reg;
1305         u32 val;
1306
1307         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1308         assert_pipe_enabled(dev_priv, pipe);
1309
1310         reg = DSPCNTR(plane);
1311         val = I915_READ(reg);
1312         if (val & DISPLAY_PLANE_ENABLE)
1313                 return;
1314
1315         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1316         intel_wait_for_vblank(dev_priv->dev, pipe);
1317 }
1318
1319 /*
1320  * Plane regs are double buffered, going from enabled->disabled needs a
1321  * trigger in order to latch.  The display address reg provides this.
1322  */
1323 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1324                                       enum plane plane)
1325 {
1326         u32 reg = DSPADDR(plane);
1327         I915_WRITE(reg, I915_READ(reg));
1328 }
1329
1330 /**
1331  * intel_disable_plane - disable a display plane
1332  * @dev_priv: i915 private structure
1333  * @plane: plane to disable
1334  * @pipe: pipe consuming the data
1335  *
1336  * Disable @plane; should be an independent operation.
1337  */
1338 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1339                                 enum plane plane, enum pipe pipe)
1340 {
1341         int reg;
1342         u32 val;
1343
1344         reg = DSPCNTR(plane);
1345         val = I915_READ(reg);
1346         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1347                 return;
1348
1349         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1350         intel_flush_display_plane(dev_priv, plane);
1351         intel_wait_for_vblank(dev_priv->dev, pipe);
1352 }
1353
1354 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1355                            enum pipe pipe, int reg, u32 port_sel)
1356 {
1357         u32 val = I915_READ(reg);
1358         if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
1359                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1360                 I915_WRITE(reg, val & ~DP_PORT_EN);
1361         }
1362 }
1363
1364 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1365                              enum pipe pipe, int reg)
1366 {
1367         u32 val = I915_READ(reg);
1368         if (HDMI_PIPE_ENABLED(val, pipe)) {
1369                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1370                               reg, pipe);
1371                 I915_WRITE(reg, val & ~PORT_ENABLE);
1372         }
1373 }
1374
1375 /* Disable any ports connected to this transcoder */
1376 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1377                                     enum pipe pipe)
1378 {
1379         u32 reg, val;
1380
1381         val = I915_READ(PCH_PP_CONTROL);
1382         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1383
1384         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1385         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1386         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1387
1388         reg = PCH_ADPA;
1389         val = I915_READ(reg);
1390         if (ADPA_PIPE_ENABLED(val, pipe))
1391                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1392
1393         reg = PCH_LVDS;
1394         val = I915_READ(reg);
1395         if (LVDS_PIPE_ENABLED(val, pipe)) {
1396                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1397                 POSTING_READ(reg);
1398                 udelay(100);
1399         }
1400
1401         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1402         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1403         disable_pch_hdmi(dev_priv, pipe, HDMID);
1404 }
1405
1406 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1407 {
1408         struct drm_device *dev = crtc->dev;
1409         struct drm_i915_private *dev_priv = dev->dev_private;
1410         struct drm_framebuffer *fb = crtc->fb;
1411         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1412         struct drm_i915_gem_object *obj = intel_fb->obj;
1413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1414         int plane, i;
1415         u32 fbc_ctl, fbc_ctl2;
1416
1417         if (fb->pitch == dev_priv->cfb_pitch &&
1418             obj->fence_reg == dev_priv->cfb_fence &&
1419             intel_crtc->plane == dev_priv->cfb_plane &&
1420             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1421                 return;
1422
1423         i8xx_disable_fbc(dev);
1424
1425         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1426
1427         if (fb->pitch < dev_priv->cfb_pitch)
1428                 dev_priv->cfb_pitch = fb->pitch;
1429
1430         /* FBC_CTL wants 64B units */
1431         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1432         dev_priv->cfb_fence = obj->fence_reg;
1433         dev_priv->cfb_plane = intel_crtc->plane;
1434         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1435
1436         /* Clear old tags */
1437         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1438                 I915_WRITE(FBC_TAG + (i * 4), 0);
1439
1440         /* Set it up... */
1441         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1442         if (obj->tiling_mode != I915_TILING_NONE)
1443                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1444         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1445         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1446
1447         /* enable it... */
1448         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1449         if (IS_I945GM(dev))
1450                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1451         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1452         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1453         if (obj->tiling_mode != I915_TILING_NONE)
1454                 fbc_ctl |= dev_priv->cfb_fence;
1455         I915_WRITE(FBC_CONTROL, fbc_ctl);
1456
1457         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1458                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1459 }
1460
1461 void i8xx_disable_fbc(struct drm_device *dev)
1462 {
1463         struct drm_i915_private *dev_priv = dev->dev_private;
1464         u32 fbc_ctl;
1465
1466         /* Disable compression */
1467         fbc_ctl = I915_READ(FBC_CONTROL);
1468         if ((fbc_ctl & FBC_CTL_EN) == 0)
1469                 return;
1470
1471         fbc_ctl &= ~FBC_CTL_EN;
1472         I915_WRITE(FBC_CONTROL, fbc_ctl);
1473
1474         /* Wait for compressing bit to clear */
1475         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1476                 DRM_DEBUG_KMS("FBC idle timed out\n");
1477                 return;
1478         }
1479
1480         DRM_DEBUG_KMS("disabled FBC\n");
1481 }
1482
1483 static bool i8xx_fbc_enabled(struct drm_device *dev)
1484 {
1485         struct drm_i915_private *dev_priv = dev->dev_private;
1486
1487         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1488 }
1489
1490 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1491 {
1492         struct drm_device *dev = crtc->dev;
1493         struct drm_i915_private *dev_priv = dev->dev_private;
1494         struct drm_framebuffer *fb = crtc->fb;
1495         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1496         struct drm_i915_gem_object *obj = intel_fb->obj;
1497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1498         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1499         unsigned long stall_watermark = 200;
1500         u32 dpfc_ctl;
1501
1502         dpfc_ctl = I915_READ(DPFC_CONTROL);
1503         if (dpfc_ctl & DPFC_CTL_EN) {
1504                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1505                     dev_priv->cfb_fence == obj->fence_reg &&
1506                     dev_priv->cfb_plane == intel_crtc->plane &&
1507                     dev_priv->cfb_y == crtc->y)
1508                         return;
1509
1510                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1511                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1512         }
1513
1514         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1515         dev_priv->cfb_fence = obj->fence_reg;
1516         dev_priv->cfb_plane = intel_crtc->plane;
1517         dev_priv->cfb_y = crtc->y;
1518
1519         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1520         if (obj->tiling_mode != I915_TILING_NONE) {
1521                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1522                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1523         } else {
1524                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1525         }
1526
1527         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1528                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1529                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1530         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1531
1532         /* enable it... */
1533         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1534
1535         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1536 }
1537
1538 void g4x_disable_fbc(struct drm_device *dev)
1539 {
1540         struct drm_i915_private *dev_priv = dev->dev_private;
1541         u32 dpfc_ctl;
1542
1543         /* Disable compression */
1544         dpfc_ctl = I915_READ(DPFC_CONTROL);
1545         if (dpfc_ctl & DPFC_CTL_EN) {
1546                 dpfc_ctl &= ~DPFC_CTL_EN;
1547                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1548
1549                 DRM_DEBUG_KMS("disabled FBC\n");
1550         }
1551 }
1552
1553 static bool g4x_fbc_enabled(struct drm_device *dev)
1554 {
1555         struct drm_i915_private *dev_priv = dev->dev_private;
1556
1557         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1558 }
1559
1560 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1561 {
1562         struct drm_i915_private *dev_priv = dev->dev_private;
1563         u32 blt_ecoskpd;
1564
1565         /* Make sure blitter notifies FBC of writes */
1566         gen6_gt_force_wake_get(dev_priv);
1567         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1568         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1569                 GEN6_BLITTER_LOCK_SHIFT;
1570         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1571         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1572         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1573         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1574                          GEN6_BLITTER_LOCK_SHIFT);
1575         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1576         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1577         gen6_gt_force_wake_put(dev_priv);
1578 }
1579
1580 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1581 {
1582         struct drm_device *dev = crtc->dev;
1583         struct drm_i915_private *dev_priv = dev->dev_private;
1584         struct drm_framebuffer *fb = crtc->fb;
1585         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1586         struct drm_i915_gem_object *obj = intel_fb->obj;
1587         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1588         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1589         unsigned long stall_watermark = 200;
1590         u32 dpfc_ctl;
1591
1592         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1593         if (dpfc_ctl & DPFC_CTL_EN) {
1594                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1595                     dev_priv->cfb_fence == obj->fence_reg &&
1596                     dev_priv->cfb_plane == intel_crtc->plane &&
1597                     dev_priv->cfb_offset == obj->gtt_offset &&
1598                     dev_priv->cfb_y == crtc->y)
1599                         return;
1600
1601                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1602                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1603         }
1604
1605         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1606         dev_priv->cfb_fence = obj->fence_reg;
1607         dev_priv->cfb_plane = intel_crtc->plane;
1608         dev_priv->cfb_offset = obj->gtt_offset;
1609         dev_priv->cfb_y = crtc->y;
1610
1611         dpfc_ctl &= DPFC_RESERVED;
1612         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1613         if (obj->tiling_mode != I915_TILING_NONE) {
1614                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1615                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1616         } else {
1617                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1618         }
1619
1620         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1621                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1622                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1623         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1624         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1625         /* enable it... */
1626         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1627
1628         if (IS_GEN6(dev)) {
1629                 I915_WRITE(SNB_DPFC_CTL_SA,
1630                            SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1631                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1632                 sandybridge_blit_fbc_update(dev);
1633         }
1634
1635         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1636 }
1637
1638 void ironlake_disable_fbc(struct drm_device *dev)
1639 {
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         u32 dpfc_ctl;
1642
1643         /* Disable compression */
1644         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1645         if (dpfc_ctl & DPFC_CTL_EN) {
1646                 dpfc_ctl &= ~DPFC_CTL_EN;
1647                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1648
1649                 DRM_DEBUG_KMS("disabled FBC\n");
1650         }
1651 }
1652
1653 static bool ironlake_fbc_enabled(struct drm_device *dev)
1654 {
1655         struct drm_i915_private *dev_priv = dev->dev_private;
1656
1657         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1658 }
1659
1660 bool intel_fbc_enabled(struct drm_device *dev)
1661 {
1662         struct drm_i915_private *dev_priv = dev->dev_private;
1663
1664         if (!dev_priv->display.fbc_enabled)
1665                 return false;
1666
1667         return dev_priv->display.fbc_enabled(dev);
1668 }
1669
1670 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1671 {
1672         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1673
1674         if (!dev_priv->display.enable_fbc)
1675                 return;
1676
1677         dev_priv->display.enable_fbc(crtc, interval);
1678 }
1679
1680 void intel_disable_fbc(struct drm_device *dev)
1681 {
1682         struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684         if (!dev_priv->display.disable_fbc)
1685                 return;
1686
1687         dev_priv->display.disable_fbc(dev);
1688 }
1689
1690 /**
1691  * intel_update_fbc - enable/disable FBC as needed
1692  * @dev: the drm_device
1693  *
1694  * Set up the framebuffer compression hardware at mode set time.  We
1695  * enable it if possible:
1696  *   - plane A only (on pre-965)
1697  *   - no pixel mulitply/line duplication
1698  *   - no alpha buffer discard
1699  *   - no dual wide
1700  *   - framebuffer <= 2048 in width, 1536 in height
1701  *
1702  * We can't assume that any compression will take place (worst case),
1703  * so the compressed buffer has to be the same size as the uncompressed
1704  * one.  It also must reside (along with the line length buffer) in
1705  * stolen memory.
1706  *
1707  * We need to enable/disable FBC on a global basis.
1708  */
1709 static void intel_update_fbc(struct drm_device *dev)
1710 {
1711         struct drm_i915_private *dev_priv = dev->dev_private;
1712         struct drm_crtc *crtc = NULL, *tmp_crtc;
1713         struct intel_crtc *intel_crtc;
1714         struct drm_framebuffer *fb;
1715         struct intel_framebuffer *intel_fb;
1716         struct drm_i915_gem_object *obj;
1717
1718         DRM_DEBUG_KMS("\n");
1719
1720         if (!i915_powersave)
1721                 return;
1722
1723         if (!I915_HAS_FBC(dev))
1724                 return;
1725
1726         /*
1727          * If FBC is already on, we just have to verify that we can
1728          * keep it that way...
1729          * Need to disable if:
1730          *   - more than one pipe is active
1731          *   - changing FBC params (stride, fence, mode)
1732          *   - new fb is too large to fit in compressed buffer
1733          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1734          */
1735         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1736                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1737                         if (crtc) {
1738                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1739                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1740                                 goto out_disable;
1741                         }
1742                         crtc = tmp_crtc;
1743                 }
1744         }
1745
1746         if (!crtc || crtc->fb == NULL) {
1747                 DRM_DEBUG_KMS("no output, disabling\n");
1748                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1749                 goto out_disable;
1750         }
1751
1752         intel_crtc = to_intel_crtc(crtc);
1753         fb = crtc->fb;
1754         intel_fb = to_intel_framebuffer(fb);
1755         obj = intel_fb->obj;
1756
1757         if (!i915_enable_fbc) {
1758                 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1759                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1760                 goto out_disable;
1761         }
1762         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1763                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1764                               "compression\n");
1765                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1766                 goto out_disable;
1767         }
1768         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1769             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1770                 DRM_DEBUG_KMS("mode incompatible with compression, "
1771                               "disabling\n");
1772                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1773                 goto out_disable;
1774         }
1775         if ((crtc->mode.hdisplay > 2048) ||
1776             (crtc->mode.vdisplay > 1536)) {
1777                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1778                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1779                 goto out_disable;
1780         }
1781         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1782                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1783                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1784                 goto out_disable;
1785         }
1786         if (obj->tiling_mode != I915_TILING_X) {
1787                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1788                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1789                 goto out_disable;
1790         }
1791
1792         /* If the kernel debugger is active, always disable compression */
1793         if (in_dbg_master())
1794                 goto out_disable;
1795
1796         intel_enable_fbc(crtc, 500);
1797         return;
1798
1799 out_disable:
1800         /* Multiple disables should be harmless */
1801         if (intel_fbc_enabled(dev)) {
1802                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1803                 intel_disable_fbc(dev);
1804         }
1805 }
1806
1807 int
1808 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1809                            struct drm_i915_gem_object *obj,
1810                            struct intel_ring_buffer *pipelined)
1811 {
1812         struct drm_i915_private *dev_priv = dev->dev_private;
1813         u32 alignment;
1814         int ret;
1815
1816         switch (obj->tiling_mode) {
1817         case I915_TILING_NONE:
1818                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1819                         alignment = 128 * 1024;
1820                 else if (INTEL_INFO(dev)->gen >= 4)
1821                         alignment = 4 * 1024;
1822                 else
1823                         alignment = 64 * 1024;
1824                 break;
1825         case I915_TILING_X:
1826                 /* pin() will align the object as required by fence */
1827                 alignment = 0;
1828                 break;
1829         case I915_TILING_Y:
1830                 /* FIXME: Is this true? */
1831                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1832                 return -EINVAL;
1833         default:
1834                 BUG();
1835         }
1836
1837         dev_priv->mm.interruptible = false;
1838         ret = i915_gem_object_pin(obj, alignment, true);
1839         if (ret)
1840                 goto err_interruptible;
1841
1842         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1843         if (ret)
1844                 goto err_unpin;
1845
1846         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1847          * fence, whereas 965+ only requires a fence if using
1848          * framebuffer compression.  For simplicity, we always install
1849          * a fence as the cost is not that onerous.
1850          */
1851         if (obj->tiling_mode != I915_TILING_NONE) {
1852                 ret = i915_gem_object_get_fence(obj, pipelined);
1853                 if (ret)
1854                         goto err_unpin;
1855         }
1856
1857         dev_priv->mm.interruptible = true;
1858         return 0;
1859
1860 err_unpin:
1861         i915_gem_object_unpin(obj);
1862 err_interruptible:
1863         dev_priv->mm.interruptible = true;
1864         return ret;
1865 }
1866
1867 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1868 static int
1869 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1870                            int x, int y, enum mode_set_atomic state)
1871 {
1872         struct drm_device *dev = crtc->dev;
1873         struct drm_i915_private *dev_priv = dev->dev_private;
1874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1875         struct intel_framebuffer *intel_fb;
1876         struct drm_i915_gem_object *obj;
1877         int plane = intel_crtc->plane;
1878         unsigned long Start, Offset;
1879         u32 dspcntr;
1880         u32 reg;
1881
1882         switch (plane) {
1883         case 0:
1884         case 1:
1885                 break;
1886         default:
1887                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1888                 return -EINVAL;
1889         }
1890
1891         intel_fb = to_intel_framebuffer(fb);
1892         obj = intel_fb->obj;
1893
1894         reg = DSPCNTR(plane);
1895         dspcntr = I915_READ(reg);
1896         /* Mask out pixel format bits in case we change it */
1897         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1898         switch (fb->bits_per_pixel) {
1899         case 8:
1900                 dspcntr |= DISPPLANE_8BPP;
1901                 break;
1902         case 16:
1903                 if (fb->depth == 15)
1904                         dspcntr |= DISPPLANE_15_16BPP;
1905                 else
1906                         dspcntr |= DISPPLANE_16BPP;
1907                 break;
1908         case 24:
1909         case 32:
1910                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1911                 break;
1912         default:
1913                 DRM_ERROR("Unknown color depth\n");
1914                 return -EINVAL;
1915         }
1916         if (INTEL_INFO(dev)->gen >= 4) {
1917                 if (obj->tiling_mode != I915_TILING_NONE)
1918                         dspcntr |= DISPPLANE_TILED;
1919                 else
1920                         dspcntr &= ~DISPPLANE_TILED;
1921         }
1922
1923         if (HAS_PCH_SPLIT(dev))
1924                 /* must disable */
1925                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1926
1927         I915_WRITE(reg, dspcntr);
1928
1929         Start = obj->gtt_offset;
1930         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1931
1932         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1933                       Start, Offset, x, y, fb->pitch);
1934         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1935         if (INTEL_INFO(dev)->gen >= 4) {
1936                 I915_WRITE(DSPSURF(plane), Start);
1937                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1938                 I915_WRITE(DSPADDR(plane), Offset);
1939         } else
1940                 I915_WRITE(DSPADDR(plane), Start + Offset);
1941         POSTING_READ(reg);
1942
1943         intel_update_fbc(dev);
1944         intel_increase_pllclock(crtc);
1945
1946         return 0;
1947 }
1948
1949 static int
1950 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1951                     struct drm_framebuffer *old_fb)
1952 {
1953         struct drm_device *dev = crtc->dev;
1954         struct drm_i915_master_private *master_priv;
1955         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1956         int ret;
1957
1958         /* no fb bound */
1959         if (!crtc->fb) {
1960                 DRM_DEBUG_KMS("No FB bound\n");
1961                 return 0;
1962         }
1963
1964         switch (intel_crtc->plane) {
1965         case 0:
1966         case 1:
1967                 break;
1968         default:
1969                 return -EINVAL;
1970         }
1971
1972         mutex_lock(&dev->struct_mutex);
1973         ret = intel_pin_and_fence_fb_obj(dev,
1974                                          to_intel_framebuffer(crtc->fb)->obj,
1975                                          NULL);
1976         if (ret != 0) {
1977                 mutex_unlock(&dev->struct_mutex);
1978                 return ret;
1979         }
1980
1981         if (old_fb) {
1982                 struct drm_i915_private *dev_priv = dev->dev_private;
1983                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1984
1985                 wait_event(dev_priv->pending_flip_queue,
1986                            atomic_read(&dev_priv->mm.wedged) ||
1987                            atomic_read(&obj->pending_flip) == 0);
1988
1989                 /* Big Hammer, we also need to ensure that any pending
1990                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1991                  * current scanout is retired before unpinning the old
1992                  * framebuffer.
1993                  *
1994                  * This should only fail upon a hung GPU, in which case we
1995                  * can safely continue.
1996                  */
1997                 ret = i915_gem_object_flush_gpu(obj);
1998                 (void) ret;
1999         }
2000
2001         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2002                                          LEAVE_ATOMIC_MODE_SET);
2003         if (ret) {
2004                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2005                 mutex_unlock(&dev->struct_mutex);
2006                 return ret;
2007         }
2008
2009         if (old_fb) {
2010                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2011                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2012         }
2013
2014         mutex_unlock(&dev->struct_mutex);
2015
2016         if (!dev->primary->master)
2017                 return 0;
2018
2019         master_priv = dev->primary->master->driver_priv;
2020         if (!master_priv->sarea_priv)
2021                 return 0;
2022
2023         if (intel_crtc->pipe) {
2024                 master_priv->sarea_priv->pipeB_x = x;
2025                 master_priv->sarea_priv->pipeB_y = y;
2026         } else {
2027                 master_priv->sarea_priv->pipeA_x = x;
2028                 master_priv->sarea_priv->pipeA_y = y;
2029         }
2030
2031         return 0;
2032 }
2033
2034 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2035 {
2036         struct drm_device *dev = crtc->dev;
2037         struct drm_i915_private *dev_priv = dev->dev_private;
2038         u32 dpa_ctl;
2039
2040         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2041         dpa_ctl = I915_READ(DP_A);
2042         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2043
2044         if (clock < 200000) {
2045                 u32 temp;
2046                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2047                 /* workaround for 160Mhz:
2048                    1) program 0x4600c bits 15:0 = 0x8124
2049                    2) program 0x46010 bit 0 = 1
2050                    3) program 0x46034 bit 24 = 1
2051                    4) program 0x64000 bit 14 = 1
2052                    */
2053                 temp = I915_READ(0x4600c);
2054                 temp &= 0xffff0000;
2055                 I915_WRITE(0x4600c, temp | 0x8124);
2056
2057                 temp = I915_READ(0x46010);
2058                 I915_WRITE(0x46010, temp | 1);
2059
2060                 temp = I915_READ(0x46034);
2061                 I915_WRITE(0x46034, temp | (1 << 24));
2062         } else {
2063                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2064         }
2065         I915_WRITE(DP_A, dpa_ctl);
2066
2067         POSTING_READ(DP_A);
2068         udelay(500);
2069 }
2070
2071 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2072 {
2073         struct drm_device *dev = crtc->dev;
2074         struct drm_i915_private *dev_priv = dev->dev_private;
2075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2076         int pipe = intel_crtc->pipe;
2077         u32 reg, temp;
2078
2079         /* enable normal train */
2080         reg = FDI_TX_CTL(pipe);
2081         temp = I915_READ(reg);
2082         if (IS_IVYBRIDGE(dev)) {
2083                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2084                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2085         } else {
2086                 temp &= ~FDI_LINK_TRAIN_NONE;
2087                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2088         }
2089         I915_WRITE(reg, temp);
2090
2091         reg = FDI_RX_CTL(pipe);
2092         temp = I915_READ(reg);
2093         if (HAS_PCH_CPT(dev)) {
2094                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2095                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2096         } else {
2097                 temp &= ~FDI_LINK_TRAIN_NONE;
2098                 temp |= FDI_LINK_TRAIN_NONE;
2099         }
2100         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2101
2102         /* wait one idle pattern time */
2103         POSTING_READ(reg);
2104         udelay(1000);
2105
2106         /* IVB wants error correction enabled */
2107         if (IS_IVYBRIDGE(dev))
2108                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2109                            FDI_FE_ERRC_ENABLE);
2110 }
2111
2112 /* The FDI link training functions for ILK/Ibexpeak. */
2113 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2114 {
2115         struct drm_device *dev = crtc->dev;
2116         struct drm_i915_private *dev_priv = dev->dev_private;
2117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2118         int pipe = intel_crtc->pipe;
2119         int plane = intel_crtc->plane;
2120         u32 reg, temp, tries;
2121
2122         /* FDI needs bits from pipe & plane first */
2123         assert_pipe_enabled(dev_priv, pipe);
2124         assert_plane_enabled(dev_priv, plane);
2125
2126         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2127            for train result */
2128         reg = FDI_RX_IMR(pipe);
2129         temp = I915_READ(reg);
2130         temp &= ~FDI_RX_SYMBOL_LOCK;
2131         temp &= ~FDI_RX_BIT_LOCK;
2132         I915_WRITE(reg, temp);
2133         I915_READ(reg);
2134         udelay(150);
2135
2136         /* enable CPU FDI TX and PCH FDI RX */
2137         reg = FDI_TX_CTL(pipe);
2138         temp = I915_READ(reg);
2139         temp &= ~(7 << 19);
2140         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2141         temp &= ~FDI_LINK_TRAIN_NONE;
2142         temp |= FDI_LINK_TRAIN_PATTERN_1;
2143         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2144
2145         reg = FDI_RX_CTL(pipe);
2146         temp = I915_READ(reg);
2147         temp &= ~FDI_LINK_TRAIN_NONE;
2148         temp |= FDI_LINK_TRAIN_PATTERN_1;
2149         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2150
2151         POSTING_READ(reg);
2152         udelay(150);
2153
2154         /* Ironlake workaround, enable clock pointer after FDI enable*/
2155         if (HAS_PCH_IBX(dev)) {
2156                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2157                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2158                            FDI_RX_PHASE_SYNC_POINTER_EN);
2159         }
2160
2161         reg = FDI_RX_IIR(pipe);
2162         for (tries = 0; tries < 5; tries++) {
2163                 temp = I915_READ(reg);
2164                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2165
2166                 if ((temp & FDI_RX_BIT_LOCK)) {
2167                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2168                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2169                         break;
2170                 }
2171         }
2172         if (tries == 5)
2173                 DRM_ERROR("FDI train 1 fail!\n");
2174
2175         /* Train 2 */
2176         reg = FDI_TX_CTL(pipe);
2177         temp = I915_READ(reg);
2178         temp &= ~FDI_LINK_TRAIN_NONE;
2179         temp |= FDI_LINK_TRAIN_PATTERN_2;
2180         I915_WRITE(reg, temp);
2181
2182         reg = FDI_RX_CTL(pipe);
2183         temp = I915_READ(reg);
2184         temp &= ~FDI_LINK_TRAIN_NONE;
2185         temp |= FDI_LINK_TRAIN_PATTERN_2;
2186         I915_WRITE(reg, temp);
2187
2188         POSTING_READ(reg);
2189         udelay(150);
2190
2191         reg = FDI_RX_IIR(pipe);
2192         for (tries = 0; tries < 5; tries++) {
2193                 temp = I915_READ(reg);
2194                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2195
2196                 if (temp & FDI_RX_SYMBOL_LOCK) {
2197                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2198                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2199                         break;
2200                 }
2201         }
2202         if (tries == 5)
2203                 DRM_ERROR("FDI train 2 fail!\n");
2204
2205         DRM_DEBUG_KMS("FDI train done\n");
2206
2207 }
2208
2209 static const int snb_b_fdi_train_param [] = {
2210         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2211         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2212         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2213         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2214 };
2215
2216 /* The FDI link training functions for SNB/Cougarpoint. */
2217 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2218 {
2219         struct drm_device *dev = crtc->dev;
2220         struct drm_i915_private *dev_priv = dev->dev_private;
2221         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2222         int pipe = intel_crtc->pipe;
2223         u32 reg, temp, i;
2224
2225         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2226            for train result */
2227         reg = FDI_RX_IMR(pipe);
2228         temp = I915_READ(reg);
2229         temp &= ~FDI_RX_SYMBOL_LOCK;
2230         temp &= ~FDI_RX_BIT_LOCK;
2231         I915_WRITE(reg, temp);
2232
2233         POSTING_READ(reg);
2234         udelay(150);
2235
2236         /* enable CPU FDI TX and PCH FDI RX */
2237         reg = FDI_TX_CTL(pipe);
2238         temp = I915_READ(reg);
2239         temp &= ~(7 << 19);
2240         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2241         temp &= ~FDI_LINK_TRAIN_NONE;
2242         temp |= FDI_LINK_TRAIN_PATTERN_1;
2243         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2244         /* SNB-B */
2245         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2246         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2247
2248         reg = FDI_RX_CTL(pipe);
2249         temp = I915_READ(reg);
2250         if (HAS_PCH_CPT(dev)) {
2251                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2252                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2253         } else {
2254                 temp &= ~FDI_LINK_TRAIN_NONE;
2255                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2256         }
2257         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2258
2259         POSTING_READ(reg);
2260         udelay(150);
2261
2262         for (i = 0; i < 4; i++ ) {
2263                 reg = FDI_TX_CTL(pipe);
2264                 temp = I915_READ(reg);
2265                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2266                 temp |= snb_b_fdi_train_param[i];
2267                 I915_WRITE(reg, temp);
2268
2269                 POSTING_READ(reg);
2270                 udelay(500);
2271
2272                 reg = FDI_RX_IIR(pipe);
2273                 temp = I915_READ(reg);
2274                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2275
2276                 if (temp & FDI_RX_BIT_LOCK) {
2277                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2278                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2279                         break;
2280                 }
2281         }
2282         if (i == 4)
2283                 DRM_ERROR("FDI train 1 fail!\n");
2284
2285         /* Train 2 */
2286         reg = FDI_TX_CTL(pipe);
2287         temp = I915_READ(reg);
2288         temp &= ~FDI_LINK_TRAIN_NONE;
2289         temp |= FDI_LINK_TRAIN_PATTERN_2;
2290         if (IS_GEN6(dev)) {
2291                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2292                 /* SNB-B */
2293                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2294         }
2295         I915_WRITE(reg, temp);
2296
2297         reg = FDI_RX_CTL(pipe);
2298         temp = I915_READ(reg);
2299         if (HAS_PCH_CPT(dev)) {
2300                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2301                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2302         } else {
2303                 temp &= ~FDI_LINK_TRAIN_NONE;
2304                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2305         }
2306         I915_WRITE(reg, temp);
2307
2308         POSTING_READ(reg);
2309         udelay(150);
2310
2311         for (i = 0; i < 4; i++ ) {
2312                 reg = FDI_TX_CTL(pipe);
2313                 temp = I915_READ(reg);
2314                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2315                 temp |= snb_b_fdi_train_param[i];
2316                 I915_WRITE(reg, temp);
2317
2318                 POSTING_READ(reg);
2319                 udelay(500);
2320
2321                 reg = FDI_RX_IIR(pipe);
2322                 temp = I915_READ(reg);
2323                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2324
2325                 if (temp & FDI_RX_SYMBOL_LOCK) {
2326                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2327                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2328                         break;
2329                 }
2330         }
2331         if (i == 4)
2332                 DRM_ERROR("FDI train 2 fail!\n");
2333
2334         DRM_DEBUG_KMS("FDI train done.\n");
2335 }
2336
2337 /* Manual link training for Ivy Bridge A0 parts */
2338 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2339 {
2340         struct drm_device *dev = crtc->dev;
2341         struct drm_i915_private *dev_priv = dev->dev_private;
2342         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2343         int pipe = intel_crtc->pipe;
2344         u32 reg, temp, i;
2345
2346         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2347            for train result */
2348         reg = FDI_RX_IMR(pipe);
2349         temp = I915_READ(reg);
2350         temp &= ~FDI_RX_SYMBOL_LOCK;
2351         temp &= ~FDI_RX_BIT_LOCK;
2352         I915_WRITE(reg, temp);
2353
2354         POSTING_READ(reg);
2355         udelay(150);
2356
2357         /* enable CPU FDI TX and PCH FDI RX */
2358         reg = FDI_TX_CTL(pipe);
2359         temp = I915_READ(reg);
2360         temp &= ~(7 << 19);
2361         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2362         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2363         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2364         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2365         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2366         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2367
2368         reg = FDI_RX_CTL(pipe);
2369         temp = I915_READ(reg);
2370         temp &= ~FDI_LINK_TRAIN_AUTO;
2371         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2372         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2373         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2374
2375         POSTING_READ(reg);
2376         udelay(150);
2377
2378         for (i = 0; i < 4; i++ ) {
2379                 reg = FDI_TX_CTL(pipe);
2380                 temp = I915_READ(reg);
2381                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2382                 temp |= snb_b_fdi_train_param[i];
2383                 I915_WRITE(reg, temp);
2384
2385                 POSTING_READ(reg);
2386                 udelay(500);
2387
2388                 reg = FDI_RX_IIR(pipe);
2389                 temp = I915_READ(reg);
2390                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2391
2392                 if (temp & FDI_RX_BIT_LOCK ||
2393                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2394                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2395                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2396                         break;
2397                 }
2398         }
2399         if (i == 4)
2400                 DRM_ERROR("FDI train 1 fail!\n");
2401
2402         /* Train 2 */
2403         reg = FDI_TX_CTL(pipe);
2404         temp = I915_READ(reg);
2405         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2406         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2407         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2408         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2409         I915_WRITE(reg, temp);
2410
2411         reg = FDI_RX_CTL(pipe);
2412         temp = I915_READ(reg);
2413         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2414         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2415         I915_WRITE(reg, temp);
2416
2417         POSTING_READ(reg);
2418         udelay(150);
2419
2420         for (i = 0; i < 4; i++ ) {
2421                 reg = FDI_TX_CTL(pipe);
2422                 temp = I915_READ(reg);
2423                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2424                 temp |= snb_b_fdi_train_param[i];
2425                 I915_WRITE(reg, temp);
2426
2427                 POSTING_READ(reg);
2428                 udelay(500);
2429
2430                 reg = FDI_RX_IIR(pipe);
2431                 temp = I915_READ(reg);
2432                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2433
2434                 if (temp & FDI_RX_SYMBOL_LOCK) {
2435                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2436                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2437                         break;
2438                 }
2439         }
2440         if (i == 4)
2441                 DRM_ERROR("FDI train 2 fail!\n");
2442
2443         DRM_DEBUG_KMS("FDI train done.\n");
2444 }
2445
2446 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2447 {
2448         struct drm_device *dev = crtc->dev;
2449         struct drm_i915_private *dev_priv = dev->dev_private;
2450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2451         int pipe = intel_crtc->pipe;
2452         u32 reg, temp;
2453
2454         /* Write the TU size bits so error detection works */
2455         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2456                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2457
2458         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2459         reg = FDI_RX_CTL(pipe);
2460         temp = I915_READ(reg);
2461         temp &= ~((0x7 << 19) | (0x7 << 16));
2462         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2463         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2464         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2465
2466         POSTING_READ(reg);
2467         udelay(200);
2468
2469         /* Switch from Rawclk to PCDclk */
2470         temp = I915_READ(reg);
2471         I915_WRITE(reg, temp | FDI_PCDCLK);
2472
2473         POSTING_READ(reg);
2474         udelay(200);
2475
2476         /* Enable CPU FDI TX PLL, always on for Ironlake */
2477         reg = FDI_TX_CTL(pipe);
2478         temp = I915_READ(reg);
2479         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2480                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2481
2482                 POSTING_READ(reg);
2483                 udelay(100);
2484         }
2485 }
2486
2487 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2488 {
2489         struct drm_device *dev = crtc->dev;
2490         struct drm_i915_private *dev_priv = dev->dev_private;
2491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2492         int pipe = intel_crtc->pipe;
2493         u32 reg, temp;
2494
2495         /* disable CPU FDI tx and PCH FDI rx */
2496         reg = FDI_TX_CTL(pipe);
2497         temp = I915_READ(reg);
2498         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2499         POSTING_READ(reg);
2500
2501         reg = FDI_RX_CTL(pipe);
2502         temp = I915_READ(reg);
2503         temp &= ~(0x7 << 16);
2504         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2505         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2506
2507         POSTING_READ(reg);
2508         udelay(100);
2509
2510         /* Ironlake workaround, disable clock pointer after downing FDI */
2511         if (HAS_PCH_IBX(dev)) {
2512                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2513                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2514                            I915_READ(FDI_RX_CHICKEN(pipe) &
2515                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2516         }
2517
2518         /* still set train pattern 1 */
2519         reg = FDI_TX_CTL(pipe);
2520         temp = I915_READ(reg);
2521         temp &= ~FDI_LINK_TRAIN_NONE;
2522         temp |= FDI_LINK_TRAIN_PATTERN_1;
2523         I915_WRITE(reg, temp);
2524
2525         reg = FDI_RX_CTL(pipe);
2526         temp = I915_READ(reg);
2527         if (HAS_PCH_CPT(dev)) {
2528                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2529                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2530         } else {
2531                 temp &= ~FDI_LINK_TRAIN_NONE;
2532                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2533         }
2534         /* BPC in FDI rx is consistent with that in PIPECONF */
2535         temp &= ~(0x07 << 16);
2536         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2537         I915_WRITE(reg, temp);
2538
2539         POSTING_READ(reg);
2540         udelay(100);
2541 }
2542
2543 /*
2544  * When we disable a pipe, we need to clear any pending scanline wait events
2545  * to avoid hanging the ring, which we assume we are waiting on.
2546  */
2547 static void intel_clear_scanline_wait(struct drm_device *dev)
2548 {
2549         struct drm_i915_private *dev_priv = dev->dev_private;
2550         struct intel_ring_buffer *ring;
2551         u32 tmp;
2552
2553         if (IS_GEN2(dev))
2554                 /* Can't break the hang on i8xx */
2555                 return;
2556
2557         ring = LP_RING(dev_priv);
2558         tmp = I915_READ_CTL(ring);
2559         if (tmp & RING_WAIT)
2560                 I915_WRITE_CTL(ring, tmp);
2561 }
2562
2563 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2564 {
2565         struct drm_i915_gem_object *obj;
2566         struct drm_i915_private *dev_priv;
2567
2568         if (crtc->fb == NULL)
2569                 return;
2570
2571         obj = to_intel_framebuffer(crtc->fb)->obj;
2572         dev_priv = crtc->dev->dev_private;
2573         wait_event(dev_priv->pending_flip_queue,
2574                    atomic_read(&obj->pending_flip) == 0);
2575 }
2576
2577 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2578 {
2579         struct drm_device *dev = crtc->dev;
2580         struct drm_mode_config *mode_config = &dev->mode_config;
2581         struct intel_encoder *encoder;
2582
2583         /*
2584          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2585          * must be driven by its own crtc; no sharing is possible.
2586          */
2587         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2588                 if (encoder->base.crtc != crtc)
2589                         continue;
2590
2591                 switch (encoder->type) {
2592                 case INTEL_OUTPUT_EDP:
2593                         if (!intel_encoder_is_pch_edp(&encoder->base))
2594                                 return false;
2595                         continue;
2596                 }
2597         }
2598
2599         return true;
2600 }
2601
2602 /*
2603  * Enable PCH resources required for PCH ports:
2604  *   - PCH PLLs
2605  *   - FDI training & RX/TX
2606  *   - update transcoder timings
2607  *   - DP transcoding bits
2608  *   - transcoder
2609  */
2610 static void ironlake_pch_enable(struct drm_crtc *crtc)
2611 {
2612         struct drm_device *dev = crtc->dev;
2613         struct drm_i915_private *dev_priv = dev->dev_private;
2614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2615         int pipe = intel_crtc->pipe;
2616         u32 reg, temp;
2617
2618         /* For PCH output, training FDI link */
2619         dev_priv->display.fdi_link_train(crtc);
2620
2621         intel_enable_pch_pll(dev_priv, pipe);
2622
2623         if (HAS_PCH_CPT(dev)) {
2624                 /* Be sure PCH DPLL SEL is set */
2625                 temp = I915_READ(PCH_DPLL_SEL);
2626                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2627                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2628                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2629                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2630                 I915_WRITE(PCH_DPLL_SEL, temp);
2631         }
2632
2633         /* set transcoder timing, panel must allow it */
2634         assert_panel_unlocked(dev_priv, pipe);
2635         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2636         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2637         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2638
2639         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2640         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2641         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2642
2643         intel_fdi_normal_train(crtc);
2644
2645         /* For PCH DP, enable TRANS_DP_CTL */
2646         if (HAS_PCH_CPT(dev) &&
2647             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2648                 reg = TRANS_DP_CTL(pipe);
2649                 temp = I915_READ(reg);
2650                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2651                           TRANS_DP_SYNC_MASK |
2652                           TRANS_DP_BPC_MASK);
2653                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2654                          TRANS_DP_ENH_FRAMING);
2655                 temp |= TRANS_DP_8BPC;
2656
2657                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2658                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2659                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2660                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2661
2662                 switch (intel_trans_dp_port_sel(crtc)) {
2663                 case PCH_DP_B:
2664                         temp |= TRANS_DP_PORT_SEL_B;
2665                         break;
2666                 case PCH_DP_C:
2667                         temp |= TRANS_DP_PORT_SEL_C;
2668                         break;
2669                 case PCH_DP_D:
2670                         temp |= TRANS_DP_PORT_SEL_D;
2671                         break;
2672                 default:
2673                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2674                         temp |= TRANS_DP_PORT_SEL_B;
2675                         break;
2676                 }
2677
2678                 I915_WRITE(reg, temp);
2679         }
2680
2681         intel_enable_transcoder(dev_priv, pipe);
2682 }
2683
2684 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2685 {
2686         struct drm_device *dev = crtc->dev;
2687         struct drm_i915_private *dev_priv = dev->dev_private;
2688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2689         int pipe = intel_crtc->pipe;
2690         int plane = intel_crtc->plane;
2691         u32 temp;
2692         bool is_pch_port;
2693
2694         if (intel_crtc->active)
2695                 return;
2696
2697         intel_crtc->active = true;
2698         intel_update_watermarks(dev);
2699
2700         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2701                 temp = I915_READ(PCH_LVDS);
2702                 if ((temp & LVDS_PORT_EN) == 0)
2703                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2704         }
2705
2706         is_pch_port = intel_crtc_driving_pch(crtc);
2707
2708         if (is_pch_port)
2709                 ironlake_fdi_pll_enable(crtc);
2710         else
2711                 ironlake_fdi_disable(crtc);
2712
2713         /* Enable panel fitting for LVDS */
2714         if (dev_priv->pch_pf_size &&
2715             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2716                 /* Force use of hard-coded filter coefficients
2717                  * as some pre-programmed values are broken,
2718                  * e.g. x201.
2719                  */
2720                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2721                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2722                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2723         }
2724
2725         /*
2726          * On ILK+ LUT must be loaded before the pipe is running but with
2727          * clocks enabled
2728          */
2729         intel_crtc_load_lut(crtc);
2730
2731         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2732         intel_enable_plane(dev_priv, plane, pipe);
2733
2734         if (is_pch_port)
2735                 ironlake_pch_enable(crtc);
2736
2737         mutex_lock(&dev->struct_mutex);
2738         intel_update_fbc(dev);
2739         mutex_unlock(&dev->struct_mutex);
2740
2741         intel_crtc_update_cursor(crtc, true);
2742 }
2743
2744 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2745 {
2746         struct drm_device *dev = crtc->dev;
2747         struct drm_i915_private *dev_priv = dev->dev_private;
2748         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2749         int pipe = intel_crtc->pipe;
2750         int plane = intel_crtc->plane;
2751         u32 reg, temp;
2752
2753         if (!intel_crtc->active)
2754                 return;
2755
2756         intel_crtc_wait_for_pending_flips(crtc);
2757         drm_vblank_off(dev, pipe);
2758         intel_crtc_update_cursor(crtc, false);
2759
2760         intel_disable_plane(dev_priv, plane, pipe);
2761
2762         if (dev_priv->cfb_plane == plane &&
2763             dev_priv->display.disable_fbc)
2764                 dev_priv->display.disable_fbc(dev);
2765
2766         intel_disable_pipe(dev_priv, pipe);
2767
2768         /* Disable PF */
2769         I915_WRITE(PF_CTL(pipe), 0);
2770         I915_WRITE(PF_WIN_SZ(pipe), 0);
2771
2772         ironlake_fdi_disable(crtc);
2773
2774         /* This is a horrible layering violation; we should be doing this in
2775          * the connector/encoder ->prepare instead, but we don't always have
2776          * enough information there about the config to know whether it will
2777          * actually be necessary or just cause undesired flicker.
2778          */
2779         intel_disable_pch_ports(dev_priv, pipe);
2780
2781         intel_disable_transcoder(dev_priv, pipe);
2782
2783         if (HAS_PCH_CPT(dev)) {
2784                 /* disable TRANS_DP_CTL */
2785                 reg = TRANS_DP_CTL(pipe);
2786                 temp = I915_READ(reg);
2787                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2788                 temp |= TRANS_DP_PORT_SEL_NONE;
2789                 I915_WRITE(reg, temp);
2790
2791                 /* disable DPLL_SEL */
2792                 temp = I915_READ(PCH_DPLL_SEL);
2793                 switch (pipe) {
2794                 case 0:
2795                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2796                         break;
2797                 case 1:
2798                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2799                         break;
2800                 case 2:
2801                         /* FIXME: manage transcoder PLLs? */
2802                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2803                         break;
2804                 default:
2805                         BUG(); /* wtf */
2806                 }
2807                 I915_WRITE(PCH_DPLL_SEL, temp);
2808         }
2809
2810         /* disable PCH DPLL */
2811         intel_disable_pch_pll(dev_priv, pipe);
2812
2813         /* Switch from PCDclk to Rawclk */
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2817
2818         /* Disable CPU FDI TX PLL */
2819         reg = FDI_TX_CTL(pipe);
2820         temp = I915_READ(reg);
2821         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2822
2823         POSTING_READ(reg);
2824         udelay(100);
2825
2826         reg = FDI_RX_CTL(pipe);
2827         temp = I915_READ(reg);
2828         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2829
2830         /* Wait for the clocks to turn off. */
2831         POSTING_READ(reg);
2832         udelay(100);
2833
2834         intel_crtc->active = false;
2835         intel_update_watermarks(dev);
2836
2837         mutex_lock(&dev->struct_mutex);
2838         intel_update_fbc(dev);
2839         intel_clear_scanline_wait(dev);
2840         mutex_unlock(&dev->struct_mutex);
2841 }
2842
2843 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2844 {
2845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2846         int pipe = intel_crtc->pipe;
2847         int plane = intel_crtc->plane;
2848
2849         /* XXX: When our outputs are all unaware of DPMS modes other than off
2850          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2851          */
2852         switch (mode) {
2853         case DRM_MODE_DPMS_ON:
2854         case DRM_MODE_DPMS_STANDBY:
2855         case DRM_MODE_DPMS_SUSPEND:
2856                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2857                 ironlake_crtc_enable(crtc);
2858                 break;
2859
2860         case DRM_MODE_DPMS_OFF:
2861                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2862                 ironlake_crtc_disable(crtc);
2863                 break;
2864         }
2865 }
2866
2867 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2868 {
2869         if (!enable && intel_crtc->overlay) {
2870                 struct drm_device *dev = intel_crtc->base.dev;
2871                 struct drm_i915_private *dev_priv = dev->dev_private;
2872
2873                 mutex_lock(&dev->struct_mutex);
2874                 dev_priv->mm.interruptible = false;
2875                 (void) intel_overlay_switch_off(intel_crtc->overlay);
2876                 dev_priv->mm.interruptible = true;
2877                 mutex_unlock(&dev->struct_mutex);
2878         }
2879
2880         /* Let userspace switch the overlay on again. In most cases userspace
2881          * has to recompute where to put it anyway.
2882          */
2883 }
2884
2885 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2886 {
2887         struct drm_device *dev = crtc->dev;
2888         struct drm_i915_private *dev_priv = dev->dev_private;
2889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2890         int pipe = intel_crtc->pipe;
2891         int plane = intel_crtc->plane;
2892
2893         if (intel_crtc->active)
2894                 return;
2895
2896         intel_crtc->active = true;
2897         intel_update_watermarks(dev);
2898
2899         intel_enable_pll(dev_priv, pipe);
2900         intel_enable_pipe(dev_priv, pipe, false);
2901         intel_enable_plane(dev_priv, plane, pipe);
2902
2903         intel_crtc_load_lut(crtc);
2904         intel_update_fbc(dev);
2905
2906         /* Give the overlay scaler a chance to enable if it's on this pipe */
2907         intel_crtc_dpms_overlay(intel_crtc, true);
2908         intel_crtc_update_cursor(crtc, true);
2909 }
2910
2911 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2912 {
2913         struct drm_device *dev = crtc->dev;
2914         struct drm_i915_private *dev_priv = dev->dev_private;
2915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2916         int pipe = intel_crtc->pipe;
2917         int plane = intel_crtc->plane;
2918
2919         if (!intel_crtc->active)
2920                 return;
2921
2922         /* Give the overlay scaler a chance to disable if it's on this pipe */
2923         intel_crtc_wait_for_pending_flips(crtc);
2924         drm_vblank_off(dev, pipe);
2925         intel_crtc_dpms_overlay(intel_crtc, false);
2926         intel_crtc_update_cursor(crtc, false);
2927
2928         if (dev_priv->cfb_plane == plane &&
2929             dev_priv->display.disable_fbc)
2930                 dev_priv->display.disable_fbc(dev);
2931
2932         intel_disable_plane(dev_priv, plane, pipe);
2933         intel_disable_pipe(dev_priv, pipe);
2934         intel_disable_pll(dev_priv, pipe);
2935
2936         intel_crtc->active = false;
2937         intel_update_fbc(dev);
2938         intel_update_watermarks(dev);
2939         intel_clear_scanline_wait(dev);
2940 }
2941
2942 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2943 {
2944         /* XXX: When our outputs are all unaware of DPMS modes other than off
2945          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2946          */
2947         switch (mode) {
2948         case DRM_MODE_DPMS_ON:
2949         case DRM_MODE_DPMS_STANDBY:
2950         case DRM_MODE_DPMS_SUSPEND:
2951                 i9xx_crtc_enable(crtc);
2952                 break;
2953         case DRM_MODE_DPMS_OFF:
2954                 i9xx_crtc_disable(crtc);
2955                 break;
2956         }
2957 }
2958
2959 /**
2960  * Sets the power management mode of the pipe and plane.
2961  */
2962 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2963 {
2964         struct drm_device *dev = crtc->dev;
2965         struct drm_i915_private *dev_priv = dev->dev_private;
2966         struct drm_i915_master_private *master_priv;
2967         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2968         int pipe = intel_crtc->pipe;
2969         bool enabled;
2970
2971         if (intel_crtc->dpms_mode == mode)
2972                 return;
2973
2974         intel_crtc->dpms_mode = mode;
2975
2976         dev_priv->display.dpms(crtc, mode);
2977
2978         if (!dev->primary->master)
2979                 return;
2980
2981         master_priv = dev->primary->master->driver_priv;
2982         if (!master_priv->sarea_priv)
2983                 return;
2984
2985         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2986
2987         switch (pipe) {
2988         case 0:
2989                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2990                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2991                 break;
2992         case 1:
2993                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2994                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2995                 break;
2996         default:
2997                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
2998                 break;
2999         }
3000 }
3001
3002 static void intel_crtc_disable(struct drm_crtc *crtc)
3003 {
3004         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3005         struct drm_device *dev = crtc->dev;
3006
3007         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3008
3009         if (crtc->fb) {
3010                 mutex_lock(&dev->struct_mutex);
3011                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3012                 mutex_unlock(&dev->struct_mutex);
3013         }
3014 }
3015
3016 /* Prepare for a mode set.
3017  *
3018  * Note we could be a lot smarter here.  We need to figure out which outputs
3019  * will be enabled, which disabled (in short, how the config will changes)
3020  * and perform the minimum necessary steps to accomplish that, e.g. updating
3021  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3022  * panel fitting is in the proper state, etc.
3023  */
3024 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3025 {
3026         i9xx_crtc_disable(crtc);
3027 }
3028
3029 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3030 {
3031         i9xx_crtc_enable(crtc);
3032 }
3033
3034 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3035 {
3036         ironlake_crtc_disable(crtc);
3037 }
3038
3039 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3040 {
3041         ironlake_crtc_enable(crtc);
3042 }
3043
3044 void intel_encoder_prepare (struct drm_encoder *encoder)
3045 {
3046         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3047         /* lvds has its own version of prepare see intel_lvds_prepare */
3048         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3049 }
3050
3051 void intel_encoder_commit (struct drm_encoder *encoder)
3052 {
3053         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3054         /* lvds has its own version of commit see intel_lvds_commit */
3055         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3056 }
3057
3058 void intel_encoder_destroy(struct drm_encoder *encoder)
3059 {
3060         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3061
3062         drm_encoder_cleanup(encoder);
3063         kfree(intel_encoder);
3064 }
3065
3066 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3067                                   struct drm_display_mode *mode,
3068                                   struct drm_display_mode *adjusted_mode)
3069 {
3070         struct drm_device *dev = crtc->dev;
3071
3072         if (HAS_PCH_SPLIT(dev)) {
3073                 /* FDI link clock is fixed at 2.7G */
3074                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3075                         return false;
3076         }
3077
3078         /* XXX some encoders set the crtcinfo, others don't.
3079          * Obviously we need some form of conflict resolution here...
3080          */
3081         if (adjusted_mode->crtc_htotal == 0)
3082                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3083
3084         return true;
3085 }
3086
3087 static int i945_get_display_clock_speed(struct drm_device *dev)
3088 {
3089         return 400000;
3090 }
3091
3092 static int i915_get_display_clock_speed(struct drm_device *dev)
3093 {
3094         return 333000;
3095 }
3096
3097 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3098 {
3099         return 200000;
3100 }
3101
3102 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3103 {
3104         u16 gcfgc = 0;
3105
3106         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3107
3108         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3109                 return 133000;
3110         else {
3111                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3112                 case GC_DISPLAY_CLOCK_333_MHZ:
3113                         return 333000;
3114                 default:
3115                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3116                         return 190000;
3117                 }
3118         }
3119 }
3120
3121 static int i865_get_display_clock_speed(struct drm_device *dev)
3122 {
3123         return 266000;
3124 }
3125
3126 static int i855_get_display_clock_speed(struct drm_device *dev)
3127 {
3128         u16 hpllcc = 0;
3129         /* Assume that the hardware is in the high speed state.  This
3130          * should be the default.
3131          */
3132         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3133         case GC_CLOCK_133_200:
3134         case GC_CLOCK_100_200:
3135                 return 200000;
3136         case GC_CLOCK_166_250:
3137                 return 250000;
3138         case GC_CLOCK_100_133:
3139                 return 133000;
3140         }
3141
3142         /* Shouldn't happen */
3143         return 0;
3144 }
3145
3146 static int i830_get_display_clock_speed(struct drm_device *dev)
3147 {
3148         return 133000;
3149 }
3150
3151 struct fdi_m_n {
3152         u32        tu;
3153         u32        gmch_m;
3154         u32        gmch_n;
3155         u32        link_m;
3156         u32        link_n;
3157 };
3158
3159 static void
3160 fdi_reduce_ratio(u32 *num, u32 *den)
3161 {
3162         while (*num > 0xffffff || *den > 0xffffff) {
3163                 *num >>= 1;
3164                 *den >>= 1;
3165         }
3166 }
3167
3168 static void
3169 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3170                      int link_clock, struct fdi_m_n *m_n)
3171 {
3172         m_n->tu = 64; /* default size */
3173
3174         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3175         m_n->gmch_m = bits_per_pixel * pixel_clock;
3176         m_n->gmch_n = link_clock * nlanes * 8;
3177         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3178
3179         m_n->link_m = pixel_clock;
3180         m_n->link_n = link_clock;
3181         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3182 }
3183
3184
3185 struct intel_watermark_params {
3186         unsigned long fifo_size;
3187         unsigned long max_wm;
3188         unsigned long default_wm;
3189         unsigned long guard_size;
3190         unsigned long cacheline_size;
3191 };
3192
3193 /* Pineview has different values for various configs */
3194 static const struct intel_watermark_params pineview_display_wm = {
3195         PINEVIEW_DISPLAY_FIFO,
3196         PINEVIEW_MAX_WM,
3197         PINEVIEW_DFT_WM,
3198         PINEVIEW_GUARD_WM,
3199         PINEVIEW_FIFO_LINE_SIZE
3200 };
3201 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3202         PINEVIEW_DISPLAY_FIFO,
3203         PINEVIEW_MAX_WM,
3204         PINEVIEW_DFT_HPLLOFF_WM,
3205         PINEVIEW_GUARD_WM,
3206         PINEVIEW_FIFO_LINE_SIZE
3207 };
3208 static const struct intel_watermark_params pineview_cursor_wm = {
3209         PINEVIEW_CURSOR_FIFO,
3210         PINEVIEW_CURSOR_MAX_WM,
3211         PINEVIEW_CURSOR_DFT_WM,
3212         PINEVIEW_CURSOR_GUARD_WM,
3213         PINEVIEW_FIFO_LINE_SIZE,
3214 };
3215 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3216         PINEVIEW_CURSOR_FIFO,
3217         PINEVIEW_CURSOR_MAX_WM,
3218         PINEVIEW_CURSOR_DFT_WM,
3219         PINEVIEW_CURSOR_GUARD_WM,
3220         PINEVIEW_FIFO_LINE_SIZE
3221 };
3222 static const struct intel_watermark_params g4x_wm_info = {
3223         G4X_FIFO_SIZE,
3224         G4X_MAX_WM,
3225         G4X_MAX_WM,
3226         2,
3227         G4X_FIFO_LINE_SIZE,
3228 };
3229 static const struct intel_watermark_params g4x_cursor_wm_info = {
3230         I965_CURSOR_FIFO,
3231         I965_CURSOR_MAX_WM,
3232         I965_CURSOR_DFT_WM,
3233         2,
3234         G4X_FIFO_LINE_SIZE,
3235 };
3236 static const struct intel_watermark_params i965_cursor_wm_info = {
3237         I965_CURSOR_FIFO,
3238         I965_CURSOR_MAX_WM,
3239         I965_CURSOR_DFT_WM,
3240         2,
3241         I915_FIFO_LINE_SIZE,
3242 };
3243 static const struct intel_watermark_params i945_wm_info = {
3244         I945_FIFO_SIZE,
3245         I915_MAX_WM,
3246         1,
3247         2,
3248         I915_FIFO_LINE_SIZE
3249 };
3250 static const struct intel_watermark_params i915_wm_info = {
3251         I915_FIFO_SIZE,
3252         I915_MAX_WM,
3253         1,
3254         2,
3255         I915_FIFO_LINE_SIZE
3256 };
3257 static const struct intel_watermark_params i855_wm_info = {
3258         I855GM_FIFO_SIZE,
3259         I915_MAX_WM,
3260         1,
3261         2,
3262         I830_FIFO_LINE_SIZE
3263 };
3264 static const struct intel_watermark_params i830_wm_info = {
3265         I830_FIFO_SIZE,
3266         I915_MAX_WM,
3267         1,
3268         2,
3269         I830_FIFO_LINE_SIZE
3270 };
3271
3272 static const struct intel_watermark_params ironlake_display_wm_info = {
3273         ILK_DISPLAY_FIFO,
3274         ILK_DISPLAY_MAXWM,
3275         ILK_DISPLAY_DFTWM,
3276         2,
3277         ILK_FIFO_LINE_SIZE
3278 };
3279 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3280         ILK_CURSOR_FIFO,
3281         ILK_CURSOR_MAXWM,
3282         ILK_CURSOR_DFTWM,
3283         2,
3284         ILK_FIFO_LINE_SIZE
3285 };
3286 static const struct intel_watermark_params ironlake_display_srwm_info = {
3287         ILK_DISPLAY_SR_FIFO,
3288         ILK_DISPLAY_MAX_SRWM,
3289         ILK_DISPLAY_DFT_SRWM,
3290         2,
3291         ILK_FIFO_LINE_SIZE
3292 };
3293 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3294         ILK_CURSOR_SR_FIFO,
3295         ILK_CURSOR_MAX_SRWM,
3296         ILK_CURSOR_DFT_SRWM,
3297         2,
3298         ILK_FIFO_LINE_SIZE
3299 };
3300
3301 static const struct intel_watermark_params sandybridge_display_wm_info = {
3302         SNB_DISPLAY_FIFO,
3303         SNB_DISPLAY_MAXWM,
3304         SNB_DISPLAY_DFTWM,
3305         2,
3306         SNB_FIFO_LINE_SIZE
3307 };
3308 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3309         SNB_CURSOR_FIFO,
3310         SNB_CURSOR_MAXWM,
3311         SNB_CURSOR_DFTWM,
3312         2,
3313         SNB_FIFO_LINE_SIZE
3314 };
3315 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3316         SNB_DISPLAY_SR_FIFO,
3317         SNB_DISPLAY_MAX_SRWM,
3318         SNB_DISPLAY_DFT_SRWM,
3319         2,
3320         SNB_FIFO_LINE_SIZE
3321 };
3322 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3323         SNB_CURSOR_SR_FIFO,
3324         SNB_CURSOR_MAX_SRWM,
3325         SNB_CURSOR_DFT_SRWM,
3326         2,
3327         SNB_FIFO_LINE_SIZE
3328 };
3329
3330
3331 /**
3332  * intel_calculate_wm - calculate watermark level
3333  * @clock_in_khz: pixel clock
3334  * @wm: chip FIFO params
3335  * @pixel_size: display pixel size
3336  * @latency_ns: memory latency for the platform
3337  *
3338  * Calculate the watermark level (the level at which the display plane will
3339  * start fetching from memory again).  Each chip has a different display
3340  * FIFO size and allocation, so the caller needs to figure that out and pass
3341  * in the correct intel_watermark_params structure.
3342  *
3343  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3344  * on the pixel size.  When it reaches the watermark level, it'll start
3345  * fetching FIFO line sized based chunks from memory until the FIFO fills
3346  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3347  * will occur, and a display engine hang could result.
3348  */
3349 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3350                                         const struct intel_watermark_params *wm,
3351                                         int fifo_size,
3352                                         int pixel_size,
3353                                         unsigned long latency_ns)
3354 {
3355         long entries_required, wm_size;
3356
3357         /*
3358          * Note: we need to make sure we don't overflow for various clock &
3359          * latency values.
3360          * clocks go from a few thousand to several hundred thousand.
3361          * latency is usually a few thousand
3362          */
3363         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3364                 1000;
3365         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3366
3367         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3368
3369         wm_size = fifo_size - (entries_required + wm->guard_size);
3370
3371         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3372
3373         /* Don't promote wm_size to unsigned... */
3374         if (wm_size > (long)wm->max_wm)
3375                 wm_size = wm->max_wm;
3376         if (wm_size <= 0)
3377                 wm_size = wm->default_wm;
3378         return wm_size;
3379 }
3380
3381 struct cxsr_latency {
3382         int is_desktop;
3383         int is_ddr3;
3384         unsigned long fsb_freq;
3385         unsigned long mem_freq;
3386         unsigned long display_sr;
3387         unsigned long display_hpll_disable;
3388         unsigned long cursor_sr;
3389         unsigned long cursor_hpll_disable;
3390 };
3391
3392 static const struct cxsr_latency cxsr_latency_table[] = {
3393         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3394         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3395         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3396         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3397         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3398
3399         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3400         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3401         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3402         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3403         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3404
3405         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3406         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3407         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3408         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3409         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3410
3411         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3412         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3413         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3414         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3415         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3416
3417         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3418         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3419         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3420         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3421         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3422
3423         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3424         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3425         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3426         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3427         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3428 };
3429
3430 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3431                                                          int is_ddr3,
3432                                                          int fsb,
3433                                                          int mem)
3434 {
3435         const struct cxsr_latency *latency;
3436         int i;
3437
3438         if (fsb == 0 || mem == 0)
3439                 return NULL;
3440
3441         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3442                 latency = &cxsr_latency_table[i];
3443                 if (is_desktop == latency->is_desktop &&
3444                     is_ddr3 == latency->is_ddr3 &&
3445                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3446                         return latency;
3447         }
3448
3449         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3450
3451         return NULL;
3452 }
3453
3454 static void pineview_disable_cxsr(struct drm_device *dev)
3455 {
3456         struct drm_i915_private *dev_priv = dev->dev_private;
3457
3458         /* deactivate cxsr */
3459         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3460 }
3461
3462 /*
3463  * Latency for FIFO fetches is dependent on several factors:
3464  *   - memory configuration (speed, channels)
3465  *   - chipset
3466  *   - current MCH state
3467  * It can be fairly high in some situations, so here we assume a fairly
3468  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3469  * set this value too high, the FIFO will fetch frequently to stay full)
3470  * and power consumption (set it too low to save power and we might see
3471  * FIFO underruns and display "flicker").
3472  *
3473  * A value of 5us seems to be a good balance; safe for very low end
3474  * platforms but not overly aggressive on lower latency configs.
3475  */
3476 static const int latency_ns = 5000;
3477
3478 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3479 {
3480         struct drm_i915_private *dev_priv = dev->dev_private;
3481         uint32_t dsparb = I915_READ(DSPARB);
3482         int size;
3483
3484         size = dsparb & 0x7f;
3485         if (plane)
3486                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3487
3488         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3489                       plane ? "B" : "A", size);
3490
3491         return size;
3492 }
3493
3494 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3495 {
3496         struct drm_i915_private *dev_priv = dev->dev_private;
3497         uint32_t dsparb = I915_READ(DSPARB);
3498         int size;
3499
3500         size = dsparb & 0x1ff;
3501         if (plane)
3502                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3503         size >>= 1; /* Convert to cachelines */
3504
3505         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3506                       plane ? "B" : "A", size);
3507
3508         return size;
3509 }
3510
3511 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3512 {
3513         struct drm_i915_private *dev_priv = dev->dev_private;
3514         uint32_t dsparb = I915_READ(DSPARB);
3515         int size;
3516
3517         size = dsparb & 0x7f;
3518         size >>= 2; /* Convert to cachelines */
3519
3520         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3521                       plane ? "B" : "A",
3522                       size);
3523
3524         return size;
3525 }
3526
3527 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3528 {
3529         struct drm_i915_private *dev_priv = dev->dev_private;
3530         uint32_t dsparb = I915_READ(DSPARB);
3531         int size;
3532
3533         size = dsparb & 0x7f;
3534         size >>= 1; /* Convert to cachelines */
3535
3536         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3537                       plane ? "B" : "A", size);
3538
3539         return size;
3540 }
3541
3542 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3543 {
3544         struct drm_crtc *crtc, *enabled = NULL;
3545
3546         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3547                 if (crtc->enabled && crtc->fb) {
3548                         if (enabled)
3549                                 return NULL;
3550                         enabled = crtc;
3551                 }
3552         }
3553
3554         return enabled;
3555 }
3556
3557 static void pineview_update_wm(struct drm_device *dev)
3558 {
3559         struct drm_i915_private *dev_priv = dev->dev_private;
3560         struct drm_crtc *crtc;
3561         const struct cxsr_latency *latency;
3562         u32 reg;
3563         unsigned long wm;
3564
3565         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3566                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3567         if (!latency) {
3568                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3569                 pineview_disable_cxsr(dev);
3570                 return;
3571         }
3572
3573         crtc = single_enabled_crtc(dev);
3574         if (crtc) {
3575                 int clock = crtc->mode.clock;
3576                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3577
3578                 /* Display SR */
3579                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3580                                         pineview_display_wm.fifo_size,
3581                                         pixel_size, latency->display_sr);
3582                 reg = I915_READ(DSPFW1);
3583                 reg &= ~DSPFW_SR_MASK;
3584                 reg |= wm << DSPFW_SR_SHIFT;
3585                 I915_WRITE(DSPFW1, reg);
3586                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3587
3588                 /* cursor SR */
3589                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3590                                         pineview_display_wm.fifo_size,
3591                                         pixel_size, latency->cursor_sr);
3592                 reg = I915_READ(DSPFW3);
3593                 reg &= ~DSPFW_CURSOR_SR_MASK;
3594                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3595                 I915_WRITE(DSPFW3, reg);
3596
3597                 /* Display HPLL off SR */
3598                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3599                                         pineview_display_hplloff_wm.fifo_size,
3600                                         pixel_size, latency->display_hpll_disable);
3601                 reg = I915_READ(DSPFW3);
3602                 reg &= ~DSPFW_HPLL_SR_MASK;
3603                 reg |= wm & DSPFW_HPLL_SR_MASK;
3604                 I915_WRITE(DSPFW3, reg);
3605
3606                 /* cursor HPLL off SR */
3607                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3608                                         pineview_display_hplloff_wm.fifo_size,
3609                                         pixel_size, latency->cursor_hpll_disable);
3610                 reg = I915_READ(DSPFW3);
3611                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3612                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3613                 I915_WRITE(DSPFW3, reg);
3614                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3615
3616                 /* activate cxsr */
3617                 I915_WRITE(DSPFW3,
3618                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3619                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3620         } else {
3621                 pineview_disable_cxsr(dev);
3622                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3623         }
3624 }
3625
3626 static bool g4x_compute_wm0(struct drm_device *dev,
3627                             int plane,
3628                             const struct intel_watermark_params *display,
3629                             int display_latency_ns,
3630                             const struct intel_watermark_params *cursor,
3631                             int cursor_latency_ns,
3632                             int *plane_wm,
3633                             int *cursor_wm)
3634 {
3635         struct drm_crtc *crtc;
3636         int htotal, hdisplay, clock, pixel_size;
3637         int line_time_us, line_count;
3638         int entries, tlb_miss;
3639
3640         crtc = intel_get_crtc_for_plane(dev, plane);
3641         if (crtc->fb == NULL || !crtc->enabled) {
3642                 *cursor_wm = cursor->guard_size;
3643                 *plane_wm = display->guard_size;
3644                 return false;
3645         }
3646
3647         htotal = crtc->mode.htotal;
3648         hdisplay = crtc->mode.hdisplay;
3649         clock = crtc->mode.clock;
3650         pixel_size = crtc->fb->bits_per_pixel / 8;
3651
3652         /* Use the small buffer method to calculate plane watermark */
3653         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3654         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3655         if (tlb_miss > 0)
3656                 entries += tlb_miss;
3657         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3658         *plane_wm = entries + display->guard_size;
3659         if (*plane_wm > (int)display->max_wm)
3660                 *plane_wm = display->max_wm;
3661
3662         /* Use the large buffer method to calculate cursor watermark */
3663         line_time_us = ((htotal * 1000) / clock);
3664         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3665         entries = line_count * 64 * pixel_size;
3666         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3667         if (tlb_miss > 0)
3668                 entries += tlb_miss;
3669         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3670         *cursor_wm = entries + cursor->guard_size;
3671         if (*cursor_wm > (int)cursor->max_wm)
3672                 *cursor_wm = (int)cursor->max_wm;
3673
3674         return true;
3675 }
3676
3677 /*
3678  * Check the wm result.
3679  *
3680  * If any calculated watermark values is larger than the maximum value that
3681  * can be programmed into the associated watermark register, that watermark
3682  * must be disabled.
3683  */
3684 static bool g4x_check_srwm(struct drm_device *dev,
3685                            int display_wm, int cursor_wm,
3686                            const struct intel_watermark_params *display,
3687                            const struct intel_watermark_params *cursor)
3688 {
3689         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3690                       display_wm, cursor_wm);
3691
3692         if (display_wm > display->max_wm) {
3693                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3694                               display_wm, display->max_wm);
3695                 return false;
3696         }
3697
3698         if (cursor_wm > cursor->max_wm) {
3699                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3700                               cursor_wm, cursor->max_wm);
3701                 return false;
3702         }
3703
3704         if (!(display_wm || cursor_wm)) {
3705                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3706                 return false;
3707         }
3708
3709         return true;
3710 }
3711
3712 static bool g4x_compute_srwm(struct drm_device *dev,
3713                              int plane,
3714                              int latency_ns,
3715                              const struct intel_watermark_params *display,
3716                              const struct intel_watermark_params *cursor,
3717                              int *display_wm, int *cursor_wm)
3718 {
3719         struct drm_crtc *crtc;
3720         int hdisplay, htotal, pixel_size, clock;
3721         unsigned long line_time_us;
3722         int line_count, line_size;
3723         int small, large;
3724         int entries;
3725
3726         if (!latency_ns) {
3727                 *display_wm = *cursor_wm = 0;
3728                 return false;
3729         }
3730
3731         crtc = intel_get_crtc_for_plane(dev, plane);
3732         hdisplay = crtc->mode.hdisplay;
3733         htotal = crtc->mode.htotal;
3734         clock = crtc->mode.clock;
3735         pixel_size = crtc->fb->bits_per_pixel / 8;
3736
3737         line_time_us = (htotal * 1000) / clock;
3738         line_count = (latency_ns / line_time_us + 1000) / 1000;
3739         line_size = hdisplay * pixel_size;
3740
3741         /* Use the minimum of the small and large buffer method for primary */
3742         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3743         large = line_count * line_size;
3744
3745         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3746         *display_wm = entries + display->guard_size;
3747
3748         /* calculate the self-refresh watermark for display cursor */
3749         entries = line_count * pixel_size * 64;
3750         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3751         *cursor_wm = entries + cursor->guard_size;
3752
3753         return g4x_check_srwm(dev,
3754                               *display_wm, *cursor_wm,
3755                               display, cursor);
3756 }
3757
3758 #define single_plane_enabled(mask) is_power_of_2(mask)
3759
3760 static void g4x_update_wm(struct drm_device *dev)
3761 {
3762         static const int sr_latency_ns = 12000;
3763         struct drm_i915_private *dev_priv = dev->dev_private;
3764         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3765         int plane_sr, cursor_sr;
3766         unsigned int enabled = 0;
3767
3768         if (g4x_compute_wm0(dev, 0,
3769                             &g4x_wm_info, latency_ns,
3770                             &g4x_cursor_wm_info, latency_ns,
3771                             &planea_wm, &cursora_wm))
3772                 enabled |= 1;
3773
3774         if (g4x_compute_wm0(dev, 1,
3775                             &g4x_wm_info, latency_ns,
3776                             &g4x_cursor_wm_info, latency_ns,
3777                             &planeb_wm, &cursorb_wm))
3778                 enabled |= 2;
3779
3780         plane_sr = cursor_sr = 0;
3781         if (single_plane_enabled(enabled) &&
3782             g4x_compute_srwm(dev, ffs(enabled) - 1,
3783                              sr_latency_ns,
3784                              &g4x_wm_info,
3785                              &g4x_cursor_wm_info,
3786                              &plane_sr, &cursor_sr))
3787                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3788         else
3789                 I915_WRITE(FW_BLC_SELF,
3790                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3791
3792         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3793                       planea_wm, cursora_wm,
3794                       planeb_wm, cursorb_wm,
3795                       plane_sr, cursor_sr);
3796
3797         I915_WRITE(DSPFW1,
3798                    (plane_sr << DSPFW_SR_SHIFT) |
3799                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3800                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
3801                    planea_wm);
3802         I915_WRITE(DSPFW2,
3803                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3804                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3805         /* HPLL off in SR has some issues on G4x... disable it */
3806         I915_WRITE(DSPFW3,
3807                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3808                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3809 }
3810
3811 static void i965_update_wm(struct drm_device *dev)
3812 {
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814         struct drm_crtc *crtc;
3815         int srwm = 1;
3816         int cursor_sr = 16;
3817
3818         /* Calc sr entries for one plane configs */
3819         crtc = single_enabled_crtc(dev);
3820         if (crtc) {
3821                 /* self-refresh has much higher latency */
3822                 static const int sr_latency_ns = 12000;
3823                 int clock = crtc->mode.clock;
3824                 int htotal = crtc->mode.htotal;
3825                 int hdisplay = crtc->mode.hdisplay;
3826                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3827                 unsigned long line_time_us;
3828                 int entries;
3829
3830                 line_time_us = ((htotal * 1000) / clock);
3831
3832                 /* Use ns/us then divide to preserve precision */
3833                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3834                         pixel_size * hdisplay;
3835                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3836                 srwm = I965_FIFO_SIZE - entries;
3837                 if (srwm < 0)
3838                         srwm = 1;
3839                 srwm &= 0x1ff;
3840                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3841                               entries, srwm);
3842
3843                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3844                         pixel_size * 64;
3845                 entries = DIV_ROUND_UP(entries,
3846                                           i965_cursor_wm_info.cacheline_size);
3847                 cursor_sr = i965_cursor_wm_info.fifo_size -
3848                         (entries + i965_cursor_wm_info.guard_size);
3849
3850                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3851                         cursor_sr = i965_cursor_wm_info.max_wm;
3852
3853                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3854                               "cursor %d\n", srwm, cursor_sr);
3855
3856                 if (IS_CRESTLINE(dev))
3857                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3858         } else {
3859                 /* Turn off self refresh if both pipes are enabled */
3860                 if (IS_CRESTLINE(dev))
3861                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3862                                    & ~FW_BLC_SELF_EN);
3863         }
3864
3865         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3866                       srwm);
3867
3868         /* 965 has limitations... */
3869         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3870                    (8 << 16) | (8 << 8) | (8 << 0));
3871         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3872         /* update cursor SR watermark */
3873         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3874 }
3875
3876 static void i9xx_update_wm(struct drm_device *dev)
3877 {
3878         struct drm_i915_private *dev_priv = dev->dev_private;
3879         const struct intel_watermark_params *wm_info;
3880         uint32_t fwater_lo;
3881         uint32_t fwater_hi;
3882         int cwm, srwm = 1;
3883         int fifo_size;
3884         int planea_wm, planeb_wm;
3885         struct drm_crtc *crtc, *enabled = NULL;
3886
3887         if (IS_I945GM(dev))
3888                 wm_info = &i945_wm_info;
3889         else if (!IS_GEN2(dev))
3890                 wm_info = &i915_wm_info;
3891         else
3892                 wm_info = &i855_wm_info;
3893
3894         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3895         crtc = intel_get_crtc_for_plane(dev, 0);
3896         if (crtc->enabled && crtc->fb) {
3897                 planea_wm = intel_calculate_wm(crtc->mode.clock,
3898                                                wm_info, fifo_size,
3899                                                crtc->fb->bits_per_pixel / 8,
3900                                                latency_ns);
3901                 enabled = crtc;
3902         } else
3903                 planea_wm = fifo_size - wm_info->guard_size;
3904
3905         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3906         crtc = intel_get_crtc_for_plane(dev, 1);
3907         if (crtc->enabled && crtc->fb) {
3908                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3909                                                wm_info, fifo_size,
3910                                                crtc->fb->bits_per_pixel / 8,
3911                                                latency_ns);
3912                 if (enabled == NULL)
3913                         enabled = crtc;
3914                 else
3915                         enabled = NULL;
3916         } else
3917                 planeb_wm = fifo_size - wm_info->guard_size;
3918
3919         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3920
3921         /*
3922          * Overlay gets an aggressive default since video jitter is bad.
3923          */
3924         cwm = 2;
3925
3926         /* Play safe and disable self-refresh before adjusting watermarks. */
3927         if (IS_I945G(dev) || IS_I945GM(dev))
3928                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3929         else if (IS_I915GM(dev))
3930                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3931
3932         /* Calc sr entries for one plane configs */
3933         if (HAS_FW_BLC(dev) && enabled) {
3934                 /* self-refresh has much higher latency */
3935                 static const int sr_latency_ns = 6000;
3936                 int clock = enabled->mode.clock;
3937                 int htotal = enabled->mode.htotal;
3938                 int hdisplay = enabled->mode.hdisplay;
3939                 int pixel_size = enabled->fb->bits_per_pixel / 8;
3940                 unsigned long line_time_us;
3941                 int entries;
3942
3943                 line_time_us = (htotal * 1000) / clock;
3944
3945                 /* Use ns/us then divide to preserve precision */
3946                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3947                         pixel_size * hdisplay;
3948                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3949                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3950                 srwm = wm_info->fifo_size - entries;
3951                 if (srwm < 0)
3952                         srwm = 1;
3953
3954                 if (IS_I945G(dev) || IS_I945GM(dev))
3955                         I915_WRITE(FW_BLC_SELF,
3956                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3957                 else if (IS_I915GM(dev))
3958                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3959         }
3960
3961         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3962                       planea_wm, planeb_wm, cwm, srwm);
3963
3964         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3965         fwater_hi = (cwm & 0x1f);
3966
3967         /* Set request length to 8 cachelines per fetch */
3968         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3969         fwater_hi = fwater_hi | (1 << 8);
3970
3971         I915_WRITE(FW_BLC, fwater_lo);
3972         I915_WRITE(FW_BLC2, fwater_hi);
3973
3974         if (HAS_FW_BLC(dev)) {
3975                 if (enabled) {
3976                         if (IS_I945G(dev) || IS_I945GM(dev))
3977                                 I915_WRITE(FW_BLC_SELF,
3978                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3979                         else if (IS_I915GM(dev))
3980                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3981                         DRM_DEBUG_KMS("memory self refresh enabled\n");
3982                 } else
3983                         DRM_DEBUG_KMS("memory self refresh disabled\n");
3984         }
3985 }
3986
3987 static void i830_update_wm(struct drm_device *dev)
3988 {
3989         struct drm_i915_private *dev_priv = dev->dev_private;
3990         struct drm_crtc *crtc;
3991         uint32_t fwater_lo;
3992         int planea_wm;
3993
3994         crtc = single_enabled_crtc(dev);
3995         if (crtc == NULL)
3996                 return;
3997
3998         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3999                                        dev_priv->display.get_fifo_size(dev, 0),
4000                                        crtc->fb->bits_per_pixel / 8,
4001                                        latency_ns);
4002         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4003         fwater_lo |= (3<<8) | planea_wm;
4004
4005         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4006
4007         I915_WRITE(FW_BLC, fwater_lo);
4008 }
4009
4010 #define ILK_LP0_PLANE_LATENCY           700
4011 #define ILK_LP0_CURSOR_LATENCY          1300
4012
4013 /*
4014  * Check the wm result.
4015  *
4016  * If any calculated watermark values is larger than the maximum value that
4017  * can be programmed into the associated watermark register, that watermark
4018  * must be disabled.
4019  */
4020 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4021                                 int fbc_wm, int display_wm, int cursor_wm,
4022                                 const struct intel_watermark_params *display,
4023                                 const struct intel_watermark_params *cursor)
4024 {
4025         struct drm_i915_private *dev_priv = dev->dev_private;
4026
4027         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4028                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4029
4030         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4031                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4032                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4033
4034                 /* fbc has it's own way to disable FBC WM */
4035                 I915_WRITE(DISP_ARB_CTL,
4036                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4037                 return false;
4038         }
4039
4040         if (display_wm > display->max_wm) {
4041                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4042                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4043                 return false;
4044         }
4045
4046         if (cursor_wm > cursor->max_wm) {
4047                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4048                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4049                 return false;
4050         }
4051
4052         if (!(fbc_wm || display_wm || cursor_wm)) {
4053                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4054                 return false;
4055         }
4056
4057         return true;
4058 }
4059
4060 /*
4061  * Compute watermark values of WM[1-3],
4062  */
4063 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4064                                   int latency_ns,
4065                                   const struct intel_watermark_params *display,
4066                                   const struct intel_watermark_params *cursor,
4067                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4068 {
4069         struct drm_crtc *crtc;
4070         unsigned long line_time_us;
4071         int hdisplay, htotal, pixel_size, clock;
4072         int line_count, line_size;
4073         int small, large;
4074         int entries;
4075
4076         if (!latency_ns) {
4077                 *fbc_wm = *display_wm = *cursor_wm = 0;
4078                 return false;
4079         }
4080
4081         crtc = intel_get_crtc_for_plane(dev, plane);
4082         hdisplay = crtc->mode.hdisplay;
4083         htotal = crtc->mode.htotal;
4084         clock = crtc->mode.clock;
4085         pixel_size = crtc->fb->bits_per_pixel / 8;
4086
4087         line_time_us = (htotal * 1000) / clock;
4088         line_count = (latency_ns / line_time_us + 1000) / 1000;
4089         line_size = hdisplay * pixel_size;
4090
4091         /* Use the minimum of the small and large buffer method for primary */
4092         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4093         large = line_count * line_size;
4094
4095         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4096         *display_wm = entries + display->guard_size;
4097
4098         /*
4099          * Spec says:
4100          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4101          */
4102         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4103
4104         /* calculate the self-refresh watermark for display cursor */
4105         entries = line_count * pixel_size * 64;
4106         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4107         *cursor_wm = entries + cursor->guard_size;
4108
4109         return ironlake_check_srwm(dev, level,
4110                                    *fbc_wm, *display_wm, *cursor_wm,
4111                                    display, cursor);
4112 }
4113
4114 static void ironlake_update_wm(struct drm_device *dev)
4115 {
4116         struct drm_i915_private *dev_priv = dev->dev_private;
4117         int fbc_wm, plane_wm, cursor_wm;
4118         unsigned int enabled;
4119
4120         enabled = 0;
4121         if (g4x_compute_wm0(dev, 0,
4122                             &ironlake_display_wm_info,
4123                             ILK_LP0_PLANE_LATENCY,
4124                             &ironlake_cursor_wm_info,
4125                             ILK_LP0_CURSOR_LATENCY,
4126                             &plane_wm, &cursor_wm)) {
4127                 I915_WRITE(WM0_PIPEA_ILK,
4128                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4129                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4130                               " plane %d, " "cursor: %d\n",
4131                               plane_wm, cursor_wm);
4132                 enabled |= 1;
4133         }
4134
4135         if (g4x_compute_wm0(dev, 1,
4136                             &ironlake_display_wm_info,
4137                             ILK_LP0_PLANE_LATENCY,
4138                             &ironlake_cursor_wm_info,
4139                             ILK_LP0_CURSOR_LATENCY,
4140                             &plane_wm, &cursor_wm)) {
4141                 I915_WRITE(WM0_PIPEB_ILK,
4142                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4143                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4144                               " plane %d, cursor: %d\n",
4145                               plane_wm, cursor_wm);
4146                 enabled |= 2;
4147         }
4148
4149         /*
4150          * Calculate and update the self-refresh watermark only when one
4151          * display plane is used.
4152          */
4153         I915_WRITE(WM3_LP_ILK, 0);
4154         I915_WRITE(WM2_LP_ILK, 0);
4155         I915_WRITE(WM1_LP_ILK, 0);
4156
4157         if (!single_plane_enabled(enabled))
4158                 return;
4159         enabled = ffs(enabled) - 1;
4160
4161         /* WM1 */
4162         if (!ironlake_compute_srwm(dev, 1, enabled,
4163                                    ILK_READ_WM1_LATENCY() * 500,
4164                                    &ironlake_display_srwm_info,
4165                                    &ironlake_cursor_srwm_info,
4166                                    &fbc_wm, &plane_wm, &cursor_wm))
4167                 return;
4168
4169         I915_WRITE(WM1_LP_ILK,
4170                    WM1_LP_SR_EN |
4171                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4172                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4173                    (plane_wm << WM1_LP_SR_SHIFT) |
4174                    cursor_wm);
4175
4176         /* WM2 */
4177         if (!ironlake_compute_srwm(dev, 2, enabled,
4178                                    ILK_READ_WM2_LATENCY() * 500,
4179                                    &ironlake_display_srwm_info,
4180                                    &ironlake_cursor_srwm_info,
4181                                    &fbc_wm, &plane_wm, &cursor_wm))
4182                 return;
4183
4184         I915_WRITE(WM2_LP_ILK,
4185                    WM2_LP_EN |
4186                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4187                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4188                    (plane_wm << WM1_LP_SR_SHIFT) |
4189                    cursor_wm);
4190
4191         /*
4192          * WM3 is unsupported on ILK, probably because we don't have latency
4193          * data for that power state
4194          */
4195 }
4196
4197 static void sandybridge_update_wm(struct drm_device *dev)
4198 {
4199         struct drm_i915_private *dev_priv = dev->dev_private;
4200         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4201         int fbc_wm, plane_wm, cursor_wm;
4202         unsigned int enabled;
4203
4204         enabled = 0;
4205         if (g4x_compute_wm0(dev, 0,
4206                             &sandybridge_display_wm_info, latency,
4207                             &sandybridge_cursor_wm_info, latency,
4208                             &plane_wm, &cursor_wm)) {
4209                 I915_WRITE(WM0_PIPEA_ILK,
4210                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4211                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4212                               " plane %d, " "cursor: %d\n",
4213                               plane_wm, cursor_wm);
4214                 enabled |= 1;
4215         }
4216
4217         if (g4x_compute_wm0(dev, 1,
4218                             &sandybridge_display_wm_info, latency,
4219                             &sandybridge_cursor_wm_info, latency,
4220                             &plane_wm, &cursor_wm)) {
4221                 I915_WRITE(WM0_PIPEB_ILK,
4222                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4223                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4224                               " plane %d, cursor: %d\n",
4225                               plane_wm, cursor_wm);
4226                 enabled |= 2;
4227         }
4228
4229         /*
4230          * Calculate and update the self-refresh watermark only when one
4231          * display plane is used.
4232          *
4233          * SNB support 3 levels of watermark.
4234          *
4235          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4236          * and disabled in the descending order
4237          *
4238          */
4239         I915_WRITE(WM3_LP_ILK, 0);
4240         I915_WRITE(WM2_LP_ILK, 0);
4241         I915_WRITE(WM1_LP_ILK, 0);
4242
4243         if (!single_plane_enabled(enabled))
4244                 return;
4245         enabled = ffs(enabled) - 1;
4246
4247         /* WM1 */
4248         if (!ironlake_compute_srwm(dev, 1, enabled,
4249                                    SNB_READ_WM1_LATENCY() * 500,
4250                                    &sandybridge_display_srwm_info,
4251                                    &sandybridge_cursor_srwm_info,
4252                                    &fbc_wm, &plane_wm, &cursor_wm))
4253                 return;
4254
4255         I915_WRITE(WM1_LP_ILK,
4256                    WM1_LP_SR_EN |
4257                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4258                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4259                    (plane_wm << WM1_LP_SR_SHIFT) |
4260                    cursor_wm);
4261
4262         /* WM2 */
4263         if (!ironlake_compute_srwm(dev, 2, enabled,
4264                                    SNB_READ_WM2_LATENCY() * 500,
4265                                    &sandybridge_display_srwm_info,
4266                                    &sandybridge_cursor_srwm_info,
4267                                    &fbc_wm, &plane_wm, &cursor_wm))
4268                 return;
4269
4270         I915_WRITE(WM2_LP_ILK,
4271                    WM2_LP_EN |
4272                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4273                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4274                    (plane_wm << WM1_LP_SR_SHIFT) |
4275                    cursor_wm);
4276
4277         /* WM3 */
4278         if (!ironlake_compute_srwm(dev, 3, enabled,
4279                                    SNB_READ_WM3_LATENCY() * 500,
4280                                    &sandybridge_display_srwm_info,
4281                                    &sandybridge_cursor_srwm_info,
4282                                    &fbc_wm, &plane_wm, &cursor_wm))
4283                 return;
4284
4285         I915_WRITE(WM3_LP_ILK,
4286                    WM3_LP_EN |
4287                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4288                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4289                    (plane_wm << WM1_LP_SR_SHIFT) |
4290                    cursor_wm);
4291 }
4292
4293 /**
4294  * intel_update_watermarks - update FIFO watermark values based on current modes
4295  *
4296  * Calculate watermark values for the various WM regs based on current mode
4297  * and plane configuration.
4298  *
4299  * There are several cases to deal with here:
4300  *   - normal (i.e. non-self-refresh)
4301  *   - self-refresh (SR) mode
4302  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4303  *   - lines are small relative to FIFO size (buffer can hold more than 2
4304  *     lines), so need to account for TLB latency
4305  *
4306  *   The normal calculation is:
4307  *     watermark = dotclock * bytes per pixel * latency
4308  *   where latency is platform & configuration dependent (we assume pessimal
4309  *   values here).
4310  *
4311  *   The SR calculation is:
4312  *     watermark = (trunc(latency/line time)+1) * surface width *
4313  *       bytes per pixel
4314  *   where
4315  *     line time = htotal / dotclock
4316  *     surface width = hdisplay for normal plane and 64 for cursor
4317  *   and latency is assumed to be high, as above.
4318  *
4319  * The final value programmed to the register should always be rounded up,
4320  * and include an extra 2 entries to account for clock crossings.
4321  *
4322  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4323  * to set the non-SR watermarks to 8.
4324  */
4325 static void intel_update_watermarks(struct drm_device *dev)
4326 {
4327         struct drm_i915_private *dev_priv = dev->dev_private;
4328
4329         if (dev_priv->display.update_wm)
4330                 dev_priv->display.update_wm(dev);
4331 }
4332
4333 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4334 {
4335         return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4336                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4337 }
4338
4339 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4340                               struct drm_display_mode *mode,
4341                               struct drm_display_mode *adjusted_mode,
4342                               int x, int y,
4343                               struct drm_framebuffer *old_fb)
4344 {
4345         struct drm_device *dev = crtc->dev;
4346         struct drm_i915_private *dev_priv = dev->dev_private;
4347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4348         int pipe = intel_crtc->pipe;
4349         int plane = intel_crtc->plane;
4350         int refclk, num_connectors = 0;
4351         intel_clock_t clock, reduced_clock;
4352         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4353         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4354         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4355         struct drm_mode_config *mode_config = &dev->mode_config;
4356         struct intel_encoder *encoder;
4357         const intel_limit_t *limit;
4358         int ret;
4359         u32 temp;
4360         u32 lvds_sync = 0;
4361
4362         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4363                 if (encoder->base.crtc != crtc)
4364                         continue;
4365
4366                 switch (encoder->type) {
4367                 case INTEL_OUTPUT_LVDS:
4368                         is_lvds = true;
4369                         break;
4370                 case INTEL_OUTPUT_SDVO:
4371                 case INTEL_OUTPUT_HDMI:
4372                         is_sdvo = true;
4373                         if (encoder->needs_tv_clock)
4374                                 is_tv = true;
4375                         break;
4376                 case INTEL_OUTPUT_DVO:
4377                         is_dvo = true;
4378                         break;
4379                 case INTEL_OUTPUT_TVOUT:
4380                         is_tv = true;
4381                         break;
4382                 case INTEL_OUTPUT_ANALOG:
4383                         is_crt = true;
4384                         break;
4385                 case INTEL_OUTPUT_DISPLAYPORT:
4386                         is_dp = true;
4387                         break;
4388                 }
4389
4390                 num_connectors++;
4391         }
4392
4393         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4394                 refclk = dev_priv->lvds_ssc_freq * 1000;
4395                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4396                               refclk / 1000);
4397         } else if (!IS_GEN2(dev)) {
4398                 refclk = 96000;
4399         } else {
4400                 refclk = 48000;
4401         }
4402
4403         /*
4404          * Returns a set of divisors for the desired target clock with the given
4405          * refclk, or FALSE.  The returned values represent the clock equation:
4406          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4407          */
4408         limit = intel_limit(crtc, refclk);
4409         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4410         if (!ok) {
4411                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4412                 return -EINVAL;
4413         }
4414
4415         /* Ensure that the cursor is valid for the new mode before changing... */
4416         intel_crtc_update_cursor(crtc, true);
4417
4418         if (is_lvds && dev_priv->lvds_downclock_avail) {
4419                 has_reduced_clock = limit->find_pll(limit, crtc,
4420                                                     dev_priv->lvds_downclock,
4421                                                     refclk,
4422                                                     &reduced_clock);
4423                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4424                         /*
4425                          * If the different P is found, it means that we can't
4426                          * switch the display clock by using the FP0/FP1.
4427                          * In such case we will disable the LVDS downclock
4428                          * feature.
4429                          */
4430                         DRM_DEBUG_KMS("Different P is found for "
4431                                       "LVDS clock/downclock\n");
4432                         has_reduced_clock = 0;
4433                 }
4434         }
4435         /* SDVO TV has fixed PLL values depend on its clock range,
4436            this mirrors vbios setting. */
4437         if (is_sdvo && is_tv) {
4438                 if (adjusted_mode->clock >= 100000
4439                     && adjusted_mode->clock < 140500) {
4440                         clock.p1 = 2;
4441                         clock.p2 = 10;
4442                         clock.n = 3;
4443                         clock.m1 = 16;
4444                         clock.m2 = 8;
4445                 } else if (adjusted_mode->clock >= 140500
4446                            && adjusted_mode->clock <= 200000) {
4447                         clock.p1 = 1;
4448                         clock.p2 = 10;
4449                         clock.n = 6;
4450                         clock.m1 = 12;
4451                         clock.m2 = 8;
4452                 }
4453         }
4454
4455         if (IS_PINEVIEW(dev)) {
4456                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4457                 if (has_reduced_clock)
4458                         fp2 = (1 << reduced_clock.n) << 16 |
4459                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4460         } else {
4461                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4462                 if (has_reduced_clock)
4463                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4464                                 reduced_clock.m2;
4465         }
4466
4467         dpll = DPLL_VGA_MODE_DIS;
4468
4469         if (!IS_GEN2(dev)) {
4470                 if (is_lvds)
4471                         dpll |= DPLLB_MODE_LVDS;
4472                 else
4473                         dpll |= DPLLB_MODE_DAC_SERIAL;
4474                 if (is_sdvo) {
4475                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4476                         if (pixel_multiplier > 1) {
4477                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4478                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4479                         }
4480                         dpll |= DPLL_DVO_HIGH_SPEED;
4481                 }
4482                 if (is_dp)
4483                         dpll |= DPLL_DVO_HIGH_SPEED;
4484
4485                 /* compute bitmask from p1 value */
4486                 if (IS_PINEVIEW(dev))
4487                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4488                 else {
4489                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4490                         if (IS_G4X(dev) && has_reduced_clock)
4491                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4492                 }
4493                 switch (clock.p2) {
4494                 case 5:
4495                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4496                         break;
4497                 case 7:
4498                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4499                         break;
4500                 case 10:
4501                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4502                         break;
4503                 case 14:
4504                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4505                         break;
4506                 }
4507                 if (INTEL_INFO(dev)->gen >= 4)
4508                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4509         } else {
4510                 if (is_lvds) {
4511                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4512                 } else {
4513                         if (clock.p1 == 2)
4514                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4515                         else
4516                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4517                         if (clock.p2 == 4)
4518                                 dpll |= PLL_P2_DIVIDE_BY_4;
4519                 }
4520         }
4521
4522         if (is_sdvo && is_tv)
4523                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4524         else if (is_tv)
4525                 /* XXX: just matching BIOS for now */
4526                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4527                 dpll |= 3;
4528         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4529                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4530         else
4531                 dpll |= PLL_REF_INPUT_DREFCLK;
4532
4533         /* setup pipeconf */
4534         pipeconf = I915_READ(PIPECONF(pipe));
4535
4536         /* Set up the display plane register */
4537         dspcntr = DISPPLANE_GAMMA_ENABLE;
4538
4539         /* Ironlake's plane is forced to pipe, bit 24 is to
4540            enable color space conversion */
4541         if (pipe == 0)
4542                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4543         else
4544                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4545
4546         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4547                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4548                  * core speed.
4549                  *
4550                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4551                  * pipe == 0 check?
4552                  */
4553                 if (mode->clock >
4554                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4555                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4556                 else
4557                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4558         }
4559
4560         dpll |= DPLL_VCO_ENABLE;
4561
4562         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4563         drm_mode_debug_printmodeline(mode);
4564
4565         I915_WRITE(FP0(pipe), fp);
4566         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4567
4568         POSTING_READ(DPLL(pipe));
4569         udelay(150);
4570
4571         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4572          * This is an exception to the general rule that mode_set doesn't turn
4573          * things on.
4574          */
4575         if (is_lvds) {
4576                 temp = I915_READ(LVDS);
4577                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4578                 if (pipe == 1) {
4579                         temp |= LVDS_PIPEB_SELECT;
4580                 } else {
4581                         temp &= ~LVDS_PIPEB_SELECT;
4582                 }
4583                 /* set the corresponsding LVDS_BORDER bit */
4584                 temp |= dev_priv->lvds_border_bits;
4585                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4586                  * set the DPLLs for dual-channel mode or not.
4587                  */
4588                 if (clock.p2 == 7)
4589                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4590                 else
4591                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4592
4593                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4594                  * appropriately here, but we need to look more thoroughly into how
4595                  * panels behave in the two modes.
4596                  */
4597                 /* set the dithering flag on LVDS as needed */
4598                 if (INTEL_INFO(dev)->gen >= 4) {
4599                         if (dev_priv->lvds_dither)
4600                                 temp |= LVDS_ENABLE_DITHER;
4601                         else
4602                                 temp &= ~LVDS_ENABLE_DITHER;
4603                 }
4604                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4605                         lvds_sync |= LVDS_HSYNC_POLARITY;
4606                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4607                         lvds_sync |= LVDS_VSYNC_POLARITY;
4608                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4609                     != lvds_sync) {
4610                         char flags[2] = "-+";
4611                         DRM_INFO("Changing LVDS panel from "
4612                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4613                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
4614                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
4615                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4616                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4617                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4618                         temp |= lvds_sync;
4619                 }
4620                 I915_WRITE(LVDS, temp);
4621         }
4622
4623         if (is_dp) {
4624                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4625         }
4626
4627         I915_WRITE(DPLL(pipe), dpll);
4628
4629         /* Wait for the clocks to stabilize. */
4630         POSTING_READ(DPLL(pipe));
4631         udelay(150);
4632
4633         if (INTEL_INFO(dev)->gen >= 4) {
4634                 temp = 0;
4635                 if (is_sdvo) {
4636                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4637                         if (temp > 1)
4638                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4639                         else
4640                                 temp = 0;
4641                 }
4642                 I915_WRITE(DPLL_MD(pipe), temp);
4643         } else {
4644                 /* The pixel multiplier can only be updated once the
4645                  * DPLL is enabled and the clocks are stable.
4646                  *
4647                  * So write it again.
4648                  */
4649                 I915_WRITE(DPLL(pipe), dpll);
4650         }
4651
4652         intel_crtc->lowfreq_avail = false;
4653         if (is_lvds && has_reduced_clock && i915_powersave) {
4654                 I915_WRITE(FP1(pipe), fp2);
4655                 intel_crtc->lowfreq_avail = true;
4656                 if (HAS_PIPE_CXSR(dev)) {
4657                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4658                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4659                 }
4660         } else {
4661                 I915_WRITE(FP1(pipe), fp);
4662                 if (HAS_PIPE_CXSR(dev)) {
4663                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4664                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4665                 }
4666         }
4667
4668         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4669                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4670                 /* the chip adds 2 halflines automatically */
4671                 adjusted_mode->crtc_vdisplay -= 1;
4672                 adjusted_mode->crtc_vtotal -= 1;
4673                 adjusted_mode->crtc_vblank_start -= 1;
4674                 adjusted_mode->crtc_vblank_end -= 1;
4675                 adjusted_mode->crtc_vsync_end -= 1;
4676                 adjusted_mode->crtc_vsync_start -= 1;
4677         } else
4678                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4679
4680         I915_WRITE(HTOTAL(pipe),
4681                    (adjusted_mode->crtc_hdisplay - 1) |
4682                    ((adjusted_mode->crtc_htotal - 1) << 16));
4683         I915_WRITE(HBLANK(pipe),
4684                    (adjusted_mode->crtc_hblank_start - 1) |
4685                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4686         I915_WRITE(HSYNC(pipe),
4687                    (adjusted_mode->crtc_hsync_start - 1) |
4688                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4689
4690         I915_WRITE(VTOTAL(pipe),
4691                    (adjusted_mode->crtc_vdisplay - 1) |
4692                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4693         I915_WRITE(VBLANK(pipe),
4694                    (adjusted_mode->crtc_vblank_start - 1) |
4695                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4696         I915_WRITE(VSYNC(pipe),
4697                    (adjusted_mode->crtc_vsync_start - 1) |
4698                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4699
4700         /* pipesrc and dspsize control the size that is scaled from,
4701          * which should always be the user's requested size.
4702          */
4703         I915_WRITE(DSPSIZE(plane),
4704                    ((mode->vdisplay - 1) << 16) |
4705                    (mode->hdisplay - 1));
4706         I915_WRITE(DSPPOS(plane), 0);
4707         I915_WRITE(PIPESRC(pipe),
4708                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4709
4710         I915_WRITE(PIPECONF(pipe), pipeconf);
4711         POSTING_READ(PIPECONF(pipe));
4712         intel_enable_pipe(dev_priv, pipe, false);
4713
4714         intel_wait_for_vblank(dev, pipe);
4715
4716         I915_WRITE(DSPCNTR(plane), dspcntr);
4717         POSTING_READ(DSPCNTR(plane));
4718         intel_enable_plane(dev_priv, plane, pipe);
4719
4720         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4721
4722         intel_update_watermarks(dev);
4723
4724         return ret;
4725 }
4726
4727 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4728                                   struct drm_display_mode *mode,
4729                                   struct drm_display_mode *adjusted_mode,
4730                                   int x, int y,
4731                                   struct drm_framebuffer *old_fb)
4732 {
4733         struct drm_device *dev = crtc->dev;
4734         struct drm_i915_private *dev_priv = dev->dev_private;
4735         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4736         int pipe = intel_crtc->pipe;
4737         int plane = intel_crtc->plane;
4738         int refclk, num_connectors = 0;
4739         intel_clock_t clock, reduced_clock;
4740         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4741         bool ok, has_reduced_clock = false, is_sdvo = false;
4742         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4743         struct intel_encoder *has_edp_encoder = NULL;
4744         struct drm_mode_config *mode_config = &dev->mode_config;
4745         struct intel_encoder *encoder;
4746         const intel_limit_t *limit;
4747         int ret;
4748         struct fdi_m_n m_n = {0};
4749         u32 temp;
4750         u32 lvds_sync = 0;
4751         int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
4752
4753         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4754                 if (encoder->base.crtc != crtc)
4755                         continue;
4756
4757                 switch (encoder->type) {
4758                 case INTEL_OUTPUT_LVDS:
4759                         is_lvds = true;
4760                         break;
4761                 case INTEL_OUTPUT_SDVO:
4762                 case INTEL_OUTPUT_HDMI:
4763                         is_sdvo = true;
4764                         if (encoder->needs_tv_clock)
4765                                 is_tv = true;
4766                         break;
4767                 case INTEL_OUTPUT_TVOUT:
4768                         is_tv = true;
4769                         break;
4770                 case INTEL_OUTPUT_ANALOG:
4771                         is_crt = true;
4772                         break;
4773                 case INTEL_OUTPUT_DISPLAYPORT:
4774                         is_dp = true;
4775                         break;
4776                 case INTEL_OUTPUT_EDP:
4777                         has_edp_encoder = encoder;
4778                         break;
4779                 }
4780
4781                 num_connectors++;
4782         }
4783
4784         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4785                 refclk = dev_priv->lvds_ssc_freq * 1000;
4786                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4787                               refclk / 1000);
4788         } else {
4789                 refclk = 96000;
4790                 if (!has_edp_encoder ||
4791                     intel_encoder_is_pch_edp(&has_edp_encoder->base))
4792                         refclk = 120000; /* 120Mhz refclk */
4793         }
4794
4795         /*
4796          * Returns a set of divisors for the desired target clock with the given
4797          * refclk, or FALSE.  The returned values represent the clock equation:
4798          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4799          */
4800         limit = intel_limit(crtc, refclk);
4801         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4802         if (!ok) {
4803                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4804                 return -EINVAL;
4805         }
4806
4807         /* Ensure that the cursor is valid for the new mode before changing... */
4808         intel_crtc_update_cursor(crtc, true);
4809
4810         if (is_lvds && dev_priv->lvds_downclock_avail) {
4811                 has_reduced_clock = limit->find_pll(limit, crtc,
4812                                                     dev_priv->lvds_downclock,
4813                                                     refclk,
4814                                                     &reduced_clock);
4815                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4816                         /*
4817                          * If the different P is found, it means that we can't
4818                          * switch the display clock by using the FP0/FP1.
4819                          * In such case we will disable the LVDS downclock
4820                          * feature.
4821                          */
4822                         DRM_DEBUG_KMS("Different P is found for "
4823                                       "LVDS clock/downclock\n");
4824                         has_reduced_clock = 0;
4825                 }
4826         }
4827         /* SDVO TV has fixed PLL values depend on its clock range,
4828            this mirrors vbios setting. */
4829         if (is_sdvo && is_tv) {
4830                 if (adjusted_mode->clock >= 100000
4831                     && adjusted_mode->clock < 140500) {
4832                         clock.p1 = 2;
4833                         clock.p2 = 10;
4834                         clock.n = 3;
4835                         clock.m1 = 16;
4836                         clock.m2 = 8;
4837                 } else if (adjusted_mode->clock >= 140500
4838                            && adjusted_mode->clock <= 200000) {
4839                         clock.p1 = 1;
4840                         clock.p2 = 10;
4841                         clock.n = 6;
4842                         clock.m1 = 12;
4843                         clock.m2 = 8;
4844                 }
4845         }
4846
4847         /* FDI link */
4848         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4849         lane = 0;
4850         /* CPU eDP doesn't require FDI link, so just set DP M/N
4851            according to current link config */
4852         if (has_edp_encoder &&
4853             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4854                 target_clock = mode->clock;
4855                 intel_edp_link_config(has_edp_encoder,
4856                                       &lane, &link_bw);
4857         } else {
4858                 /* [e]DP over FDI requires target mode clock
4859                    instead of link clock */
4860                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4861                         target_clock = mode->clock;
4862                 else
4863                         target_clock = adjusted_mode->clock;
4864
4865                 /* FDI is a binary signal running at ~2.7GHz, encoding
4866                  * each output octet as 10 bits. The actual frequency
4867                  * is stored as a divider into a 100MHz clock, and the
4868                  * mode pixel clock is stored in units of 1KHz.
4869                  * Hence the bw of each lane in terms of the mode signal
4870                  * is:
4871                  */
4872                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4873         }
4874
4875         /* determine panel color depth */
4876         temp = I915_READ(PIPECONF(pipe));
4877         temp &= ~PIPE_BPC_MASK;
4878         if (is_lvds) {
4879                 /* the BPC will be 6 if it is 18-bit LVDS panel */
4880                 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4881                         temp |= PIPE_8BPC;
4882                 else
4883                         temp |= PIPE_6BPC;
4884         } else if (has_edp_encoder) {
4885                 switch (dev_priv->edp.bpp/3) {
4886                 case 8:
4887                         temp |= PIPE_8BPC;
4888                         break;
4889                 case 10:
4890                         temp |= PIPE_10BPC;
4891                         break;
4892                 case 6:
4893                         temp |= PIPE_6BPC;
4894                         break;
4895                 case 12:
4896                         temp |= PIPE_12BPC;
4897                         break;
4898                 }
4899         } else
4900                 temp |= PIPE_8BPC;
4901         I915_WRITE(PIPECONF(pipe), temp);
4902
4903         switch (temp & PIPE_BPC_MASK) {
4904         case PIPE_8BPC:
4905                 bpp = 24;
4906                 break;
4907         case PIPE_10BPC:
4908                 bpp = 30;
4909                 break;
4910         case PIPE_6BPC:
4911                 bpp = 18;
4912                 break;
4913         case PIPE_12BPC:
4914                 bpp = 36;
4915                 break;
4916         default:
4917                 DRM_ERROR("unknown pipe bpc value\n");
4918                 bpp = 24;
4919         }
4920
4921         if (!lane) {
4922                 /*
4923                  * Account for spread spectrum to avoid
4924                  * oversubscribing the link. Max center spread
4925                  * is 2.5%; use 5% for safety's sake.
4926                  */
4927                 u32 bps = target_clock * bpp * 21 / 20;
4928                 lane = bps / (link_bw * 8) + 1;
4929         }
4930
4931         intel_crtc->fdi_lanes = lane;
4932
4933         if (pixel_multiplier > 1)
4934                 link_bw *= pixel_multiplier;
4935         ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4936
4937         /* Ironlake: try to setup display ref clock before DPLL
4938          * enabling. This is only under driver's control after
4939          * PCH B stepping, previous chipset stepping should be
4940          * ignoring this setting.
4941          */
4942         temp = I915_READ(PCH_DREF_CONTROL);
4943         /* Always enable nonspread source */
4944         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4945         temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4946         temp &= ~DREF_SSC_SOURCE_MASK;
4947         temp |= DREF_SSC_SOURCE_ENABLE;
4948         I915_WRITE(PCH_DREF_CONTROL, temp);
4949
4950         POSTING_READ(PCH_DREF_CONTROL);
4951         udelay(200);
4952
4953         if (has_edp_encoder) {
4954                 if (intel_panel_use_ssc(dev_priv)) {
4955                         temp |= DREF_SSC1_ENABLE;
4956                         I915_WRITE(PCH_DREF_CONTROL, temp);
4957
4958                         POSTING_READ(PCH_DREF_CONTROL);
4959                         udelay(200);
4960                 }
4961                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4962
4963                 /* Enable CPU source on CPU attached eDP */
4964                 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4965                         if (intel_panel_use_ssc(dev_priv))
4966                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4967                         else
4968                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4969                 } else {
4970                         /* Enable SSC on PCH eDP if needed */
4971                         if (intel_panel_use_ssc(dev_priv)) {
4972                                 DRM_ERROR("enabling SSC on PCH\n");
4973                                 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4974                         }
4975                 }
4976                 I915_WRITE(PCH_DREF_CONTROL, temp);
4977                 POSTING_READ(PCH_DREF_CONTROL);
4978                 udelay(200);
4979         }
4980
4981         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4982         if (has_reduced_clock)
4983                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4984                         reduced_clock.m2;
4985
4986         /* Enable autotuning of the PLL clock (if permissible) */
4987         factor = 21;
4988         if (is_lvds) {
4989                 if ((intel_panel_use_ssc(dev_priv) &&
4990                      dev_priv->lvds_ssc_freq == 100) ||
4991                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4992                         factor = 25;
4993         } else if (is_sdvo && is_tv)
4994                 factor = 20;
4995
4996         if (clock.m1 < factor * clock.n)
4997                 fp |= FP_CB_TUNE;
4998
4999         dpll = 0;
5000
5001         if (is_lvds)
5002                 dpll |= DPLLB_MODE_LVDS;
5003         else
5004                 dpll |= DPLLB_MODE_DAC_SERIAL;
5005         if (is_sdvo) {
5006                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5007                 if (pixel_multiplier > 1) {
5008                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5009                 }
5010                 dpll |= DPLL_DVO_HIGH_SPEED;
5011         }
5012         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5013                 dpll |= DPLL_DVO_HIGH_SPEED;
5014
5015         /* compute bitmask from p1 value */
5016         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5017         /* also FPA1 */
5018         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5019
5020         switch (clock.p2) {
5021         case 5:
5022                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5023                 break;
5024         case 7:
5025                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5026                 break;
5027         case 10:
5028                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5029                 break;
5030         case 14:
5031                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5032                 break;
5033         }
5034
5035         if (is_sdvo && is_tv)
5036                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5037         else if (is_tv)
5038                 /* XXX: just matching BIOS for now */
5039                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5040                 dpll |= 3;
5041         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5042                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5043         else
5044                 dpll |= PLL_REF_INPUT_DREFCLK;
5045
5046         /* setup pipeconf */
5047         pipeconf = I915_READ(PIPECONF(pipe));
5048
5049         /* Set up the display plane register */
5050         dspcntr = DISPPLANE_GAMMA_ENABLE;
5051
5052         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5053         drm_mode_debug_printmodeline(mode);
5054
5055         /* PCH eDP needs FDI, but CPU eDP does not */
5056         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5057                 I915_WRITE(PCH_FP0(pipe), fp);
5058                 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5059
5060                 POSTING_READ(PCH_DPLL(pipe));
5061                 udelay(150);
5062         }
5063
5064         /* enable transcoder DPLL */
5065         if (HAS_PCH_CPT(dev)) {
5066                 temp = I915_READ(PCH_DPLL_SEL);
5067                 switch (pipe) {
5068                 case 0:
5069                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5070                         break;
5071                 case 1:
5072                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5073                         break;
5074                 case 2:
5075                         /* FIXME: manage transcoder PLLs? */
5076                         temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5077                         break;
5078                 default:
5079                         BUG();
5080                 }
5081                 I915_WRITE(PCH_DPLL_SEL, temp);
5082
5083                 POSTING_READ(PCH_DPLL_SEL);
5084                 udelay(150);
5085         }
5086
5087         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5088          * This is an exception to the general rule that mode_set doesn't turn
5089          * things on.
5090          */
5091         if (is_lvds) {
5092                 temp = I915_READ(PCH_LVDS);
5093                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5094                 if (pipe == 1) {
5095                         if (HAS_PCH_CPT(dev))
5096                                 temp |= PORT_TRANS_B_SEL_CPT;
5097                         else
5098                                 temp |= LVDS_PIPEB_SELECT;
5099                 } else {
5100                         if (HAS_PCH_CPT(dev))
5101                                 temp &= ~PORT_TRANS_SEL_MASK;
5102                         else
5103                                 temp &= ~LVDS_PIPEB_SELECT;
5104                 }
5105                 /* set the corresponsding LVDS_BORDER bit */
5106                 temp |= dev_priv->lvds_border_bits;
5107                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5108                  * set the DPLLs for dual-channel mode or not.
5109                  */
5110                 if (clock.p2 == 7)
5111                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5112                 else
5113                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5114
5115                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5116                  * appropriately here, but we need to look more thoroughly into how
5117                  * panels behave in the two modes.
5118                  */
5119                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5120                         lvds_sync |= LVDS_HSYNC_POLARITY;
5121                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5122                         lvds_sync |= LVDS_VSYNC_POLARITY;
5123                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5124                     != lvds_sync) {
5125                         char flags[2] = "-+";
5126                         DRM_INFO("Changing LVDS panel from "
5127                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5128                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5129                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5130                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5131                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5132                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5133                         temp |= lvds_sync;
5134                 }
5135                 I915_WRITE(PCH_LVDS, temp);
5136         }
5137
5138         /* set the dithering flag and clear for anything other than a panel. */
5139         pipeconf &= ~PIPECONF_DITHER_EN;
5140         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5141         if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5142                 pipeconf |= PIPECONF_DITHER_EN;
5143                 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5144         }
5145
5146         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5147                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5148         } else {
5149                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5150                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5151                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5152                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5153                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5154         }
5155
5156         if (!has_edp_encoder ||
5157             intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5158                 I915_WRITE(PCH_DPLL(pipe), dpll);
5159
5160                 /* Wait for the clocks to stabilize. */
5161                 POSTING_READ(PCH_DPLL(pipe));
5162                 udelay(150);
5163
5164                 /* The pixel multiplier can only be updated once the
5165                  * DPLL is enabled and the clocks are stable.
5166                  *
5167                  * So write it again.
5168                  */
5169                 I915_WRITE(PCH_DPLL(pipe), dpll);
5170         }
5171
5172         intel_crtc->lowfreq_avail = false;
5173         if (is_lvds && has_reduced_clock && i915_powersave) {
5174                 I915_WRITE(PCH_FP1(pipe), fp2);
5175                 intel_crtc->lowfreq_avail = true;
5176                 if (HAS_PIPE_CXSR(dev)) {
5177                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5178                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5179                 }
5180         } else {
5181                 I915_WRITE(PCH_FP1(pipe), fp);
5182                 if (HAS_PIPE_CXSR(dev)) {
5183                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5184                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5185                 }
5186         }
5187
5188         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5189                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5190                 /* the chip adds 2 halflines automatically */
5191                 adjusted_mode->crtc_vdisplay -= 1;
5192                 adjusted_mode->crtc_vtotal -= 1;
5193                 adjusted_mode->crtc_vblank_start -= 1;
5194                 adjusted_mode->crtc_vblank_end -= 1;
5195                 adjusted_mode->crtc_vsync_end -= 1;
5196                 adjusted_mode->crtc_vsync_start -= 1;
5197         } else
5198                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5199
5200         I915_WRITE(HTOTAL(pipe),
5201                    (adjusted_mode->crtc_hdisplay - 1) |
5202                    ((adjusted_mode->crtc_htotal - 1) << 16));
5203         I915_WRITE(HBLANK(pipe),
5204                    (adjusted_mode->crtc_hblank_start - 1) |
5205                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5206         I915_WRITE(HSYNC(pipe),
5207                    (adjusted_mode->crtc_hsync_start - 1) |
5208                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5209
5210         I915_WRITE(VTOTAL(pipe),
5211                    (adjusted_mode->crtc_vdisplay - 1) |
5212                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5213         I915_WRITE(VBLANK(pipe),
5214                    (adjusted_mode->crtc_vblank_start - 1) |
5215                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5216         I915_WRITE(VSYNC(pipe),
5217                    (adjusted_mode->crtc_vsync_start - 1) |
5218                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5219
5220         /* pipesrc controls the size that is scaled from, which should
5221          * always be the user's requested size.
5222          */
5223         I915_WRITE(PIPESRC(pipe),
5224                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5225
5226         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5227         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5228         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5229         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5230
5231         if (has_edp_encoder &&
5232             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5233                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5234         }
5235
5236         I915_WRITE(PIPECONF(pipe), pipeconf);
5237         POSTING_READ(PIPECONF(pipe));
5238
5239         intel_wait_for_vblank(dev, pipe);
5240
5241         if (IS_GEN5(dev)) {
5242                 /* enable address swizzle for tiling buffer */
5243                 temp = I915_READ(DISP_ARB_CTL);
5244                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5245         }
5246
5247         I915_WRITE(DSPCNTR(plane), dspcntr);
5248         POSTING_READ(DSPCNTR(plane));
5249
5250         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5251
5252         intel_update_watermarks(dev);
5253
5254         return ret;
5255 }
5256
5257 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5258                                struct drm_display_mode *mode,
5259                                struct drm_display_mode *adjusted_mode,
5260                                int x, int y,
5261                                struct drm_framebuffer *old_fb)
5262 {
5263         struct drm_device *dev = crtc->dev;
5264         struct drm_i915_private *dev_priv = dev->dev_private;
5265         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5266         int pipe = intel_crtc->pipe;
5267         int ret;
5268
5269         drm_vblank_pre_modeset(dev, pipe);
5270
5271         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5272                                               x, y, old_fb);
5273
5274         drm_vblank_post_modeset(dev, pipe);
5275
5276         intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5277
5278         return ret;
5279 }
5280
5281 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5282 void intel_crtc_load_lut(struct drm_crtc *crtc)
5283 {
5284         struct drm_device *dev = crtc->dev;
5285         struct drm_i915_private *dev_priv = dev->dev_private;
5286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5287         int palreg = PALETTE(intel_crtc->pipe);
5288         int i;
5289
5290         /* The clocks have to be on to load the palette. */
5291         if (!crtc->enabled)
5292                 return;
5293
5294         /* use legacy palette for Ironlake */
5295         if (HAS_PCH_SPLIT(dev))
5296                 palreg = LGC_PALETTE(intel_crtc->pipe);
5297
5298         for (i = 0; i < 256; i++) {
5299                 I915_WRITE(palreg + 4 * i,
5300                            (intel_crtc->lut_r[i] << 16) |
5301                            (intel_crtc->lut_g[i] << 8) |
5302                            intel_crtc->lut_b[i]);
5303         }
5304 }
5305
5306 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5307 {
5308         struct drm_device *dev = crtc->dev;
5309         struct drm_i915_private *dev_priv = dev->dev_private;
5310         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5311         bool visible = base != 0;
5312         u32 cntl;
5313
5314         if (intel_crtc->cursor_visible == visible)
5315                 return;
5316
5317         cntl = I915_READ(_CURACNTR);
5318         if (visible) {
5319                 /* On these chipsets we can only modify the base whilst
5320                  * the cursor is disabled.
5321                  */
5322                 I915_WRITE(_CURABASE, base);
5323
5324                 cntl &= ~(CURSOR_FORMAT_MASK);
5325                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5326                 cntl |= CURSOR_ENABLE |
5327                         CURSOR_GAMMA_ENABLE |
5328                         CURSOR_FORMAT_ARGB;
5329         } else
5330                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5331         I915_WRITE(_CURACNTR, cntl);
5332
5333         intel_crtc->cursor_visible = visible;
5334 }
5335
5336 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5337 {
5338         struct drm_device *dev = crtc->dev;
5339         struct drm_i915_private *dev_priv = dev->dev_private;
5340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5341         int pipe = intel_crtc->pipe;
5342         bool visible = base != 0;
5343
5344         if (intel_crtc->cursor_visible != visible) {
5345                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5346                 if (base) {
5347                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5348                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5349                         cntl |= pipe << 28; /* Connect to correct pipe */
5350                 } else {
5351                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5352                         cntl |= CURSOR_MODE_DISABLE;
5353                 }
5354                 I915_WRITE(CURCNTR(pipe), cntl);
5355
5356                 intel_crtc->cursor_visible = visible;
5357         }
5358         /* and commit changes on next vblank */
5359         I915_WRITE(CURBASE(pipe), base);
5360 }
5361
5362 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5363 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5364                                      bool on)
5365 {
5366         struct drm_device *dev = crtc->dev;
5367         struct drm_i915_private *dev_priv = dev->dev_private;
5368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5369         int pipe = intel_crtc->pipe;
5370         int x = intel_crtc->cursor_x;
5371         int y = intel_crtc->cursor_y;
5372         u32 base, pos;
5373         bool visible;
5374
5375         pos = 0;
5376
5377         if (on && crtc->enabled && crtc->fb) {
5378                 base = intel_crtc->cursor_addr;
5379                 if (x > (int) crtc->fb->width)
5380                         base = 0;
5381
5382                 if (y > (int) crtc->fb->height)
5383                         base = 0;
5384         } else
5385                 base = 0;
5386
5387         if (x < 0) {
5388                 if (x + intel_crtc->cursor_width < 0)
5389                         base = 0;
5390
5391                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5392                 x = -x;
5393         }
5394         pos |= x << CURSOR_X_SHIFT;
5395
5396         if (y < 0) {
5397                 if (y + intel_crtc->cursor_height < 0)
5398                         base = 0;
5399
5400                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5401                 y = -y;
5402         }
5403         pos |= y << CURSOR_Y_SHIFT;
5404
5405         visible = base != 0;
5406         if (!visible && !intel_crtc->cursor_visible)
5407                 return;
5408
5409         I915_WRITE(CURPOS(pipe), pos);
5410         if (IS_845G(dev) || IS_I865G(dev))
5411                 i845_update_cursor(crtc, base);
5412         else
5413                 i9xx_update_cursor(crtc, base);
5414
5415         if (visible)
5416                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5417 }
5418
5419 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5420                                  struct drm_file *file,
5421                                  uint32_t handle,
5422                                  uint32_t width, uint32_t height)
5423 {
5424         struct drm_device *dev = crtc->dev;
5425         struct drm_i915_private *dev_priv = dev->dev_private;
5426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5427         struct drm_i915_gem_object *obj;
5428         uint32_t addr;
5429         int ret;
5430
5431         DRM_DEBUG_KMS("\n");
5432
5433         /* if we want to turn off the cursor ignore width and height */
5434         if (!handle) {
5435                 DRM_DEBUG_KMS("cursor off\n");
5436                 addr = 0;
5437                 obj = NULL;
5438                 mutex_lock(&dev->struct_mutex);
5439                 goto finish;
5440         }
5441
5442         /* Currently we only support 64x64 cursors */
5443         if (width != 64 || height != 64) {
5444                 DRM_ERROR("we currently only support 64x64 cursors\n");
5445                 return -EINVAL;
5446         }
5447
5448         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5449         if (&obj->base == NULL)
5450                 return -ENOENT;
5451
5452         if (obj->base.size < width * height * 4) {
5453                 DRM_ERROR("buffer is to small\n");
5454                 ret = -ENOMEM;
5455                 goto fail;
5456         }
5457
5458         /* we only need to pin inside GTT if cursor is non-phy */
5459         mutex_lock(&dev->struct_mutex);
5460         if (!dev_priv->info->cursor_needs_physical) {
5461                 if (obj->tiling_mode) {
5462                         DRM_ERROR("cursor cannot be tiled\n");
5463                         ret = -EINVAL;
5464                         goto fail_locked;
5465                 }
5466
5467                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
5468                 if (ret) {
5469                         DRM_ERROR("failed to pin cursor bo\n");
5470                         goto fail_locked;
5471                 }
5472
5473                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
5474                 if (ret) {
5475                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5476                         goto fail_unpin;
5477                 }
5478
5479                 ret = i915_gem_object_put_fence(obj);
5480                 if (ret) {
5481                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5482                         goto fail_unpin;
5483                 }
5484
5485                 addr = obj->gtt_offset;
5486         } else {
5487                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5488                 ret = i915_gem_attach_phys_object(dev, obj,
5489                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5490                                                   align);
5491                 if (ret) {
5492                         DRM_ERROR("failed to attach phys object\n");
5493                         goto fail_locked;
5494                 }
5495                 addr = obj->phys_obj->handle->busaddr;
5496         }
5497
5498         if (IS_GEN2(dev))
5499                 I915_WRITE(CURSIZE, (height << 12) | width);
5500
5501  finish:
5502         if (intel_crtc->cursor_bo) {
5503                 if (dev_priv->info->cursor_needs_physical) {
5504                         if (intel_crtc->cursor_bo != obj)
5505                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5506                 } else
5507                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5508                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5509         }
5510
5511         mutex_unlock(&dev->struct_mutex);
5512
5513         intel_crtc->cursor_addr = addr;
5514         intel_crtc->cursor_bo = obj;
5515         intel_crtc->cursor_width = width;
5516         intel_crtc->cursor_height = height;
5517
5518         intel_crtc_update_cursor(crtc, true);
5519
5520         return 0;
5521 fail_unpin:
5522         i915_gem_object_unpin(obj);
5523 fail_locked:
5524         mutex_unlock(&dev->struct_mutex);
5525 fail:
5526         drm_gem_object_unreference_unlocked(&obj->base);
5527         return ret;
5528 }
5529
5530 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5531 {
5532         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5533
5534         intel_crtc->cursor_x = x;
5535         intel_crtc->cursor_y = y;
5536
5537         intel_crtc_update_cursor(crtc, true);
5538
5539         return 0;
5540 }
5541
5542 /** Sets the color ramps on behalf of RandR */
5543 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5544                                  u16 blue, int regno)
5545 {
5546         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5547
5548         intel_crtc->lut_r[regno] = red >> 8;
5549         intel_crtc->lut_g[regno] = green >> 8;
5550         intel_crtc->lut_b[regno] = blue >> 8;
5551 }
5552
5553 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5554                              u16 *blue, int regno)
5555 {
5556         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5557
5558         *red = intel_crtc->lut_r[regno] << 8;
5559         *green = intel_crtc->lut_g[regno] << 8;
5560         *blue = intel_crtc->lut_b[regno] << 8;
5561 }
5562
5563 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5564                                  u16 *blue, uint32_t start, uint32_t size)
5565 {
5566         int end = (start + size > 256) ? 256 : start + size, i;
5567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5568
5569         for (i = start; i < end; i++) {
5570                 intel_crtc->lut_r[i] = red[i] >> 8;
5571                 intel_crtc->lut_g[i] = green[i] >> 8;
5572                 intel_crtc->lut_b[i] = blue[i] >> 8;
5573         }
5574
5575         intel_crtc_load_lut(crtc);
5576 }
5577
5578 /**
5579  * Get a pipe with a simple mode set on it for doing load-based monitor
5580  * detection.
5581  *
5582  * It will be up to the load-detect code to adjust the pipe as appropriate for
5583  * its requirements.  The pipe will be connected to no other encoders.
5584  *
5585  * Currently this code will only succeed if there is a pipe with no encoders
5586  * configured for it.  In the future, it could choose to temporarily disable
5587  * some outputs to free up a pipe for its use.
5588  *
5589  * \return crtc, or NULL if no pipes are available.
5590  */
5591
5592 /* VESA 640x480x72Hz mode to set on the pipe */
5593 static struct drm_display_mode load_detect_mode = {
5594         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5595                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5596 };
5597
5598 static struct drm_framebuffer *
5599 intel_framebuffer_create(struct drm_device *dev,
5600                          struct drm_mode_fb_cmd *mode_cmd,
5601                          struct drm_i915_gem_object *obj)
5602 {
5603         struct intel_framebuffer *intel_fb;
5604         int ret;
5605
5606         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5607         if (!intel_fb) {
5608                 drm_gem_object_unreference_unlocked(&obj->base);
5609                 return ERR_PTR(-ENOMEM);
5610         }
5611
5612         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5613         if (ret) {
5614                 drm_gem_object_unreference_unlocked(&obj->base);
5615                 kfree(intel_fb);
5616                 return ERR_PTR(ret);
5617         }
5618
5619         return &intel_fb->base;
5620 }
5621
5622 static u32
5623 intel_framebuffer_pitch_for_width(int width, int bpp)
5624 {
5625         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5626         return ALIGN(pitch, 64);
5627 }
5628
5629 static u32
5630 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5631 {
5632         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5633         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5634 }
5635
5636 static struct drm_framebuffer *
5637 intel_framebuffer_create_for_mode(struct drm_device *dev,
5638                                   struct drm_display_mode *mode,
5639                                   int depth, int bpp)
5640 {
5641         struct drm_i915_gem_object *obj;
5642         struct drm_mode_fb_cmd mode_cmd;
5643
5644         obj = i915_gem_alloc_object(dev,
5645                                     intel_framebuffer_size_for_mode(mode, bpp));
5646         if (obj == NULL)
5647                 return ERR_PTR(-ENOMEM);
5648
5649         mode_cmd.width = mode->hdisplay;
5650         mode_cmd.height = mode->vdisplay;
5651         mode_cmd.depth = depth;
5652         mode_cmd.bpp = bpp;
5653         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5654
5655         return intel_framebuffer_create(dev, &mode_cmd, obj);
5656 }
5657
5658 static struct drm_framebuffer *
5659 mode_fits_in_fbdev(struct drm_device *dev,
5660                    struct drm_display_mode *mode)
5661 {
5662         struct drm_i915_private *dev_priv = dev->dev_private;
5663         struct drm_i915_gem_object *obj;
5664         struct drm_framebuffer *fb;
5665
5666         if (dev_priv->fbdev == NULL)
5667                 return NULL;
5668
5669         obj = dev_priv->fbdev->ifb.obj;
5670         if (obj == NULL)
5671                 return NULL;
5672
5673         fb = &dev_priv->fbdev->ifb.base;
5674         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5675                                                           fb->bits_per_pixel))
5676                 return NULL;
5677
5678         if (obj->base.size < mode->vdisplay * fb->pitch)
5679                 return NULL;
5680
5681         return fb;
5682 }
5683
5684 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5685                                 struct drm_connector *connector,
5686                                 struct drm_display_mode *mode,
5687                                 struct intel_load_detect_pipe *old)
5688 {
5689         struct intel_crtc *intel_crtc;
5690         struct drm_crtc *possible_crtc;
5691         struct drm_encoder *encoder = &intel_encoder->base;
5692         struct drm_crtc *crtc = NULL;
5693         struct drm_device *dev = encoder->dev;
5694         struct drm_framebuffer *old_fb;
5695         int i = -1;
5696
5697         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5698                       connector->base.id, drm_get_connector_name(connector),
5699                       encoder->base.id, drm_get_encoder_name(encoder));
5700
5701         /*
5702          * Algorithm gets a little messy:
5703          *
5704          *   - if the connector already has an assigned crtc, use it (but make
5705          *     sure it's on first)
5706          *
5707          *   - try to find the first unused crtc that can drive this connector,
5708          *     and use that if we find one
5709          */
5710
5711         /* See if we already have a CRTC for this connector */
5712         if (encoder->crtc) {
5713                 crtc = encoder->crtc;
5714
5715                 intel_crtc = to_intel_crtc(crtc);
5716                 old->dpms_mode = intel_crtc->dpms_mode;
5717                 old->load_detect_temp = false;
5718
5719                 /* Make sure the crtc and connector are running */
5720                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5721                         struct drm_encoder_helper_funcs *encoder_funcs;
5722                         struct drm_crtc_helper_funcs *crtc_funcs;
5723
5724                         crtc_funcs = crtc->helper_private;
5725                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5726
5727                         encoder_funcs = encoder->helper_private;
5728                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5729                 }
5730
5731                 return true;
5732         }
5733
5734         /* Find an unused one (if possible) */
5735         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5736                 i++;
5737                 if (!(encoder->possible_crtcs & (1 << i)))
5738                         continue;
5739                 if (!possible_crtc->enabled) {
5740                         crtc = possible_crtc;
5741                         break;
5742                 }
5743         }
5744
5745         /*
5746          * If we didn't find an unused CRTC, don't use any.
5747          */
5748         if (!crtc) {
5749                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5750                 return false;
5751         }
5752
5753         encoder->crtc = crtc;
5754         connector->encoder = encoder;
5755
5756         intel_crtc = to_intel_crtc(crtc);
5757         old->dpms_mode = intel_crtc->dpms_mode;
5758         old->load_detect_temp = true;
5759         old->release_fb = NULL;
5760
5761         if (!mode)
5762                 mode = &load_detect_mode;
5763
5764         old_fb = crtc->fb;
5765
5766         /* We need a framebuffer large enough to accommodate all accesses
5767          * that the plane may generate whilst we perform load detection.
5768          * We can not rely on the fbcon either being present (we get called
5769          * during its initialisation to detect all boot displays, or it may
5770          * not even exist) or that it is large enough to satisfy the
5771          * requested mode.
5772          */
5773         crtc->fb = mode_fits_in_fbdev(dev, mode);
5774         if (crtc->fb == NULL) {
5775                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5776                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5777                 old->release_fb = crtc->fb;
5778         } else
5779                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5780         if (IS_ERR(crtc->fb)) {
5781                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5782                 crtc->fb = old_fb;
5783                 return false;
5784         }
5785
5786         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5787                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5788                 if (old->release_fb)
5789                         old->release_fb->funcs->destroy(old->release_fb);
5790                 crtc->fb = old_fb;
5791                 return false;
5792         }
5793
5794         /* let the connector get through one full cycle before testing */
5795         intel_wait_for_vblank(dev, intel_crtc->pipe);
5796
5797         return true;
5798 }
5799
5800 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5801                                     struct drm_connector *connector,
5802                                     struct intel_load_detect_pipe *old)
5803 {
5804         struct drm_encoder *encoder = &intel_encoder->base;
5805         struct drm_device *dev = encoder->dev;
5806         struct drm_crtc *crtc = encoder->crtc;
5807         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5808         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5809
5810         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5811                       connector->base.id, drm_get_connector_name(connector),
5812                       encoder->base.id, drm_get_encoder_name(encoder));
5813
5814         if (old->load_detect_temp) {
5815                 connector->encoder = NULL;
5816                 drm_helper_disable_unused_functions(dev);
5817
5818                 if (old->release_fb)
5819                         old->release_fb->funcs->destroy(old->release_fb);
5820
5821                 return;
5822         }
5823
5824         /* Switch crtc and encoder back off if necessary */
5825         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5826                 encoder_funcs->dpms(encoder, old->dpms_mode);
5827                 crtc_funcs->dpms(crtc, old->dpms_mode);
5828         }
5829 }
5830
5831 /* Returns the clock of the currently programmed mode of the given pipe. */
5832 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5833 {
5834         struct drm_i915_private *dev_priv = dev->dev_private;
5835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5836         int pipe = intel_crtc->pipe;
5837         u32 dpll = I915_READ(DPLL(pipe));
5838         u32 fp;
5839         intel_clock_t clock;
5840
5841         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5842                 fp = I915_READ(FP0(pipe));
5843         else
5844                 fp = I915_READ(FP1(pipe));
5845
5846         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5847         if (IS_PINEVIEW(dev)) {
5848                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5849                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5850         } else {
5851                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5852                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5853         }
5854
5855         if (!IS_GEN2(dev)) {
5856                 if (IS_PINEVIEW(dev))
5857                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5858                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5859                 else
5860                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5861                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5862
5863                 switch (dpll & DPLL_MODE_MASK) {
5864                 case DPLLB_MODE_DAC_SERIAL:
5865                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5866                                 5 : 10;
5867                         break;
5868                 case DPLLB_MODE_LVDS:
5869                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5870                                 7 : 14;
5871                         break;
5872                 default:
5873                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5874                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5875                         return 0;
5876                 }
5877
5878                 /* XXX: Handle the 100Mhz refclk */
5879                 intel_clock(dev, 96000, &clock);
5880         } else {
5881                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5882
5883                 if (is_lvds) {
5884                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5885                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5886                         clock.p2 = 14;
5887
5888                         if ((dpll & PLL_REF_INPUT_MASK) ==
5889                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5890                                 /* XXX: might not be 66MHz */
5891                                 intel_clock(dev, 66000, &clock);
5892                         } else
5893                                 intel_clock(dev, 48000, &clock);
5894                 } else {
5895                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5896                                 clock.p1 = 2;
5897                         else {
5898                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5899                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5900                         }
5901                         if (dpll & PLL_P2_DIVIDE_BY_4)
5902                                 clock.p2 = 4;
5903                         else
5904                                 clock.p2 = 2;
5905
5906                         intel_clock(dev, 48000, &clock);
5907                 }
5908         }
5909
5910         /* XXX: It would be nice to validate the clocks, but we can't reuse
5911          * i830PllIsValid() because it relies on the xf86_config connector
5912          * configuration being accurate, which it isn't necessarily.
5913          */
5914
5915         return clock.dot;
5916 }
5917
5918 /** Returns the currently programmed mode of the given pipe. */
5919 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5920                                              struct drm_crtc *crtc)
5921 {
5922         struct drm_i915_private *dev_priv = dev->dev_private;
5923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5924         int pipe = intel_crtc->pipe;
5925         struct drm_display_mode *mode;
5926         int htot = I915_READ(HTOTAL(pipe));
5927         int hsync = I915_READ(HSYNC(pipe));
5928         int vtot = I915_READ(VTOTAL(pipe));
5929         int vsync = I915_READ(VSYNC(pipe));
5930
5931         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5932         if (!mode)
5933                 return NULL;
5934
5935         mode->clock = intel_crtc_clock_get(dev, crtc);
5936         mode->hdisplay = (htot & 0xffff) + 1;
5937         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5938         mode->hsync_start = (hsync & 0xffff) + 1;
5939         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5940         mode->vdisplay = (vtot & 0xffff) + 1;
5941         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5942         mode->vsync_start = (vsync & 0xffff) + 1;
5943         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5944
5945         drm_mode_set_name(mode);
5946         drm_mode_set_crtcinfo(mode, 0);
5947
5948         return mode;
5949 }
5950
5951 #define GPU_IDLE_TIMEOUT 500 /* ms */
5952
5953 /* When this timer fires, we've been idle for awhile */
5954 static void intel_gpu_idle_timer(unsigned long arg)
5955 {
5956         struct drm_device *dev = (struct drm_device *)arg;
5957         drm_i915_private_t *dev_priv = dev->dev_private;
5958
5959         if (!list_empty(&dev_priv->mm.active_list)) {
5960                 /* Still processing requests, so just re-arm the timer. */
5961                 mod_timer(&dev_priv->idle_timer, jiffies +
5962                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5963                 return;
5964         }
5965
5966         dev_priv->busy = false;
5967         queue_work(dev_priv->wq, &dev_priv->idle_work);
5968 }
5969
5970 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5971
5972 static void intel_crtc_idle_timer(unsigned long arg)
5973 {
5974         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5975         struct drm_crtc *crtc = &intel_crtc->base;
5976         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5977         struct intel_framebuffer *intel_fb;
5978
5979         intel_fb = to_intel_framebuffer(crtc->fb);
5980         if (intel_fb && intel_fb->obj->active) {
5981                 /* The framebuffer is still being accessed by the GPU. */
5982                 mod_timer(&intel_crtc->idle_timer, jiffies +
5983                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5984                 return;
5985         }
5986
5987         intel_crtc->busy = false;
5988         queue_work(dev_priv->wq, &dev_priv->idle_work);
5989 }
5990
5991 static void intel_increase_pllclock(struct drm_crtc *crtc)
5992 {
5993         struct drm_device *dev = crtc->dev;
5994         drm_i915_private_t *dev_priv = dev->dev_private;
5995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5996         int pipe = intel_crtc->pipe;
5997         int dpll_reg = DPLL(pipe);
5998         int dpll;
5999
6000         if (HAS_PCH_SPLIT(dev))
6001                 return;
6002
6003         if (!dev_priv->lvds_downclock_avail)
6004                 return;
6005
6006         dpll = I915_READ(dpll_reg);
6007         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6008                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6009
6010                 /* Unlock panel regs */
6011                 I915_WRITE(PP_CONTROL,
6012                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6013
6014                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6015                 I915_WRITE(dpll_reg, dpll);
6016                 intel_wait_for_vblank(dev, pipe);
6017
6018                 dpll = I915_READ(dpll_reg);
6019                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6020                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6021
6022                 /* ...and lock them again */
6023                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6024         }
6025
6026         /* Schedule downclock */
6027         mod_timer(&intel_crtc->idle_timer, jiffies +
6028                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6029 }
6030
6031 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6032 {
6033         struct drm_device *dev = crtc->dev;
6034         drm_i915_private_t *dev_priv = dev->dev_private;
6035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6036         int pipe = intel_crtc->pipe;
6037         int dpll_reg = DPLL(pipe);
6038         int dpll = I915_READ(dpll_reg);
6039
6040         if (HAS_PCH_SPLIT(dev))
6041                 return;
6042
6043         if (!dev_priv->lvds_downclock_avail)
6044                 return;
6045
6046         /*
6047          * Since this is called by a timer, we should never get here in
6048          * the manual case.
6049          */
6050         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6051                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6052
6053                 /* Unlock panel regs */
6054                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6055                            PANEL_UNLOCK_REGS);
6056
6057                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6058                 I915_WRITE(dpll_reg, dpll);
6059                 intel_wait_for_vblank(dev, pipe);
6060                 dpll = I915_READ(dpll_reg);
6061                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6062                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6063
6064                 /* ...and lock them again */
6065                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6066         }
6067
6068 }
6069
6070 /**
6071  * intel_idle_update - adjust clocks for idleness
6072  * @work: work struct
6073  *
6074  * Either the GPU or display (or both) went idle.  Check the busy status
6075  * here and adjust the CRTC and GPU clocks as necessary.
6076  */
6077 static void intel_idle_update(struct work_struct *work)
6078 {
6079         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6080                                                     idle_work);
6081         struct drm_device *dev = dev_priv->dev;
6082         struct drm_crtc *crtc;
6083         struct intel_crtc *intel_crtc;
6084
6085         if (!i915_powersave)
6086                 return;
6087
6088         mutex_lock(&dev->struct_mutex);
6089
6090         i915_update_gfx_val(dev_priv);
6091
6092         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6093                 /* Skip inactive CRTCs */
6094                 if (!crtc->fb)
6095                         continue;
6096
6097                 intel_crtc = to_intel_crtc(crtc);
6098                 if (!intel_crtc->busy)
6099                         intel_decrease_pllclock(crtc);
6100         }
6101
6102
6103         mutex_unlock(&dev->struct_mutex);
6104 }
6105
6106 /**
6107  * intel_mark_busy - mark the GPU and possibly the display busy
6108  * @dev: drm device
6109  * @obj: object we're operating on
6110  *
6111  * Callers can use this function to indicate that the GPU is busy processing
6112  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6113  * buffer), we'll also mark the display as busy, so we know to increase its
6114  * clock frequency.
6115  */
6116 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6117 {
6118         drm_i915_private_t *dev_priv = dev->dev_private;
6119         struct drm_crtc *crtc = NULL;
6120         struct intel_framebuffer *intel_fb;
6121         struct intel_crtc *intel_crtc;
6122
6123         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6124                 return;
6125
6126         if (!dev_priv->busy)
6127                 dev_priv->busy = true;
6128         else
6129                 mod_timer(&dev_priv->idle_timer, jiffies +
6130                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6131
6132         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6133                 if (!crtc->fb)
6134                         continue;
6135
6136                 intel_crtc = to_intel_crtc(crtc);
6137                 intel_fb = to_intel_framebuffer(crtc->fb);
6138                 if (intel_fb->obj == obj) {
6139                         if (!intel_crtc->busy) {
6140                                 /* Non-busy -> busy, upclock */
6141                                 intel_increase_pllclock(crtc);
6142                                 intel_crtc->busy = true;
6143                         } else {
6144                                 /* Busy -> busy, put off timer */
6145                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6146                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6147                         }
6148                 }
6149         }
6150 }
6151
6152 static void intel_crtc_destroy(struct drm_crtc *crtc)
6153 {
6154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6155         struct drm_device *dev = crtc->dev;
6156         struct intel_unpin_work *work;
6157         unsigned long flags;
6158
6159         spin_lock_irqsave(&dev->event_lock, flags);
6160         work = intel_crtc->unpin_work;
6161         intel_crtc->unpin_work = NULL;
6162         spin_unlock_irqrestore(&dev->event_lock, flags);
6163
6164         if (work) {
6165                 cancel_work_sync(&work->work);
6166                 kfree(work);
6167         }
6168
6169         drm_crtc_cleanup(crtc);
6170
6171         kfree(intel_crtc);
6172 }
6173
6174 static void intel_unpin_work_fn(struct work_struct *__work)
6175 {
6176         struct intel_unpin_work *work =
6177                 container_of(__work, struct intel_unpin_work, work);
6178
6179         mutex_lock(&work->dev->struct_mutex);
6180         i915_gem_object_unpin(work->old_fb_obj);
6181         drm_gem_object_unreference(&work->pending_flip_obj->base);
6182         drm_gem_object_unreference(&work->old_fb_obj->base);
6183
6184         mutex_unlock(&work->dev->struct_mutex);
6185         kfree(work);
6186 }
6187
6188 static void do_intel_finish_page_flip(struct drm_device *dev,
6189                                       struct drm_crtc *crtc)
6190 {
6191         drm_i915_private_t *dev_priv = dev->dev_private;
6192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6193         struct intel_unpin_work *work;
6194         struct drm_i915_gem_object *obj;
6195         struct drm_pending_vblank_event *e;
6196         struct timeval tnow, tvbl;
6197         unsigned long flags;
6198
6199         /* Ignore early vblank irqs */
6200         if (intel_crtc == NULL)
6201                 return;
6202
6203         do_gettimeofday(&tnow);
6204
6205         spin_lock_irqsave(&dev->event_lock, flags);
6206         work = intel_crtc->unpin_work;
6207         if (work == NULL || !work->pending) {
6208                 spin_unlock_irqrestore(&dev->event_lock, flags);
6209                 return;
6210         }
6211
6212         intel_crtc->unpin_work = NULL;
6213
6214         if (work->event) {
6215                 e = work->event;
6216                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6217
6218                 /* Called before vblank count and timestamps have
6219                  * been updated for the vblank interval of flip
6220                  * completion? Need to increment vblank count and
6221                  * add one videorefresh duration to returned timestamp
6222                  * to account for this. We assume this happened if we
6223                  * get called over 0.9 frame durations after the last
6224                  * timestamped vblank.
6225                  *
6226                  * This calculation can not be used with vrefresh rates
6227                  * below 5Hz (10Hz to be on the safe side) without
6228                  * promoting to 64 integers.
6229                  */
6230                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6231                     9 * crtc->framedur_ns) {
6232                         e->event.sequence++;
6233                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6234                                              crtc->framedur_ns);
6235                 }
6236
6237                 e->event.tv_sec = tvbl.tv_sec;
6238                 e->event.tv_usec = tvbl.tv_usec;
6239
6240                 list_add_tail(&e->base.link,
6241                               &e->base.file_priv->event_list);
6242                 wake_up_interruptible(&e->base.file_priv->event_wait);
6243         }
6244
6245         drm_vblank_put(dev, intel_crtc->pipe);
6246
6247         spin_unlock_irqrestore(&dev->event_lock, flags);
6248
6249         obj = work->old_fb_obj;
6250
6251         atomic_clear_mask(1 << intel_crtc->plane,
6252                           &obj->pending_flip.counter);
6253         if (atomic_read(&obj->pending_flip) == 0)
6254                 wake_up(&dev_priv->pending_flip_queue);
6255
6256         schedule_work(&work->work);
6257
6258         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6259 }
6260
6261 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6262 {
6263         drm_i915_private_t *dev_priv = dev->dev_private;
6264         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6265
6266         do_intel_finish_page_flip(dev, crtc);
6267 }
6268
6269 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6270 {
6271         drm_i915_private_t *dev_priv = dev->dev_private;
6272         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6273
6274         do_intel_finish_page_flip(dev, crtc);
6275 }
6276
6277 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6278 {
6279         drm_i915_private_t *dev_priv = dev->dev_private;
6280         struct intel_crtc *intel_crtc =
6281                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6282         unsigned long flags;
6283
6284         spin_lock_irqsave(&dev->event_lock, flags);
6285         if (intel_crtc->unpin_work) {
6286                 if ((++intel_crtc->unpin_work->pending) > 1)
6287                         DRM_ERROR("Prepared flip multiple times\n");
6288         } else {
6289                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6290         }
6291         spin_unlock_irqrestore(&dev->event_lock, flags);
6292 }
6293
6294 static int intel_gen2_queue_flip(struct drm_device *dev,
6295                                  struct drm_crtc *crtc,
6296                                  struct drm_framebuffer *fb,
6297                                  struct drm_i915_gem_object *obj)
6298 {
6299         struct drm_i915_private *dev_priv = dev->dev_private;
6300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6301         unsigned long offset;
6302         u32 flip_mask;
6303         int ret;
6304
6305         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6306         if (ret)
6307                 goto out;
6308
6309         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6310         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6311
6312         ret = BEGIN_LP_RING(6);
6313         if (ret)
6314                 goto out;
6315
6316         /* Can't queue multiple flips, so wait for the previous
6317          * one to finish before executing the next.
6318          */
6319         if (intel_crtc->plane)
6320                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6321         else
6322                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6323         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6324         OUT_RING(MI_NOOP);
6325         OUT_RING(MI_DISPLAY_FLIP |
6326                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6327         OUT_RING(fb->pitch);
6328         OUT_RING(obj->gtt_offset + offset);
6329         OUT_RING(MI_NOOP);
6330         ADVANCE_LP_RING();
6331 out:
6332         return ret;
6333 }
6334
6335 static int intel_gen3_queue_flip(struct drm_device *dev,
6336                                  struct drm_crtc *crtc,
6337                                  struct drm_framebuffer *fb,
6338                                  struct drm_i915_gem_object *obj)
6339 {
6340         struct drm_i915_private *dev_priv = dev->dev_private;
6341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6342         unsigned long offset;
6343         u32 flip_mask;
6344         int ret;
6345
6346         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6347         if (ret)
6348                 goto out;
6349
6350         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6351         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6352
6353         ret = BEGIN_LP_RING(6);
6354         if (ret)
6355                 goto out;
6356
6357         if (intel_crtc->plane)
6358                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6359         else
6360                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6361         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6362         OUT_RING(MI_NOOP);
6363         OUT_RING(MI_DISPLAY_FLIP_I915 |
6364                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6365         OUT_RING(fb->pitch);
6366         OUT_RING(obj->gtt_offset + offset);
6367         OUT_RING(MI_NOOP);
6368
6369         ADVANCE_LP_RING();
6370 out:
6371         return ret;
6372 }
6373
6374 static int intel_gen4_queue_flip(struct drm_device *dev,
6375                                  struct drm_crtc *crtc,
6376                                  struct drm_framebuffer *fb,
6377                                  struct drm_i915_gem_object *obj)
6378 {
6379         struct drm_i915_private *dev_priv = dev->dev_private;
6380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6381         uint32_t pf, pipesrc;
6382         int ret;
6383
6384         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6385         if (ret)
6386                 goto out;
6387
6388         ret = BEGIN_LP_RING(4);
6389         if (ret)
6390                 goto out;
6391
6392         /* i965+ uses the linear or tiled offsets from the
6393          * Display Registers (which do not change across a page-flip)
6394          * so we need only reprogram the base address.
6395          */
6396         OUT_RING(MI_DISPLAY_FLIP |
6397                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6398         OUT_RING(fb->pitch);
6399         OUT_RING(obj->gtt_offset | obj->tiling_mode);
6400
6401         /* XXX Enabling the panel-fitter across page-flip is so far
6402          * untested on non-native modes, so ignore it for now.
6403          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6404          */
6405         pf = 0;
6406         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6407         OUT_RING(pf | pipesrc);
6408         ADVANCE_LP_RING();
6409 out:
6410         return ret;
6411 }
6412
6413 static int intel_gen6_queue_flip(struct drm_device *dev,
6414                                  struct drm_crtc *crtc,
6415                                  struct drm_framebuffer *fb,
6416                                  struct drm_i915_gem_object *obj)
6417 {
6418         struct drm_i915_private *dev_priv = dev->dev_private;
6419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6420         uint32_t pf, pipesrc;
6421         int ret;
6422
6423         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6424         if (ret)
6425                 goto out;
6426
6427         ret = BEGIN_LP_RING(4);
6428         if (ret)
6429                 goto out;
6430
6431         OUT_RING(MI_DISPLAY_FLIP |
6432                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6433         OUT_RING(fb->pitch | obj->tiling_mode);
6434         OUT_RING(obj->gtt_offset);
6435
6436         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6437         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6438         OUT_RING(pf | pipesrc);
6439         ADVANCE_LP_RING();
6440 out:
6441         return ret;
6442 }
6443
6444 /*
6445  * On gen7 we currently use the blit ring because (in early silicon at least)
6446  * the render ring doesn't give us interrpts for page flip completion, which
6447  * means clients will hang after the first flip is queued.  Fortunately the
6448  * blit ring generates interrupts properly, so use it instead.
6449  */
6450 static int intel_gen7_queue_flip(struct drm_device *dev,
6451                                  struct drm_crtc *crtc,
6452                                  struct drm_framebuffer *fb,
6453                                  struct drm_i915_gem_object *obj)
6454 {
6455         struct drm_i915_private *dev_priv = dev->dev_private;
6456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6457         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6458         int ret;
6459
6460         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6461         if (ret)
6462                 goto out;
6463
6464         ret = intel_ring_begin(ring, 4);
6465         if (ret)
6466                 goto out;
6467
6468         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6469         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6470         intel_ring_emit(ring, (obj->gtt_offset));
6471         intel_ring_emit(ring, (MI_NOOP));
6472         intel_ring_advance(ring);
6473 out:
6474         return ret;
6475 }
6476
6477 static int intel_default_queue_flip(struct drm_device *dev,
6478                                     struct drm_crtc *crtc,
6479                                     struct drm_framebuffer *fb,
6480                                     struct drm_i915_gem_object *obj)
6481 {
6482         return -ENODEV;
6483 }
6484
6485 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6486                                 struct drm_framebuffer *fb,
6487                                 struct drm_pending_vblank_event *event)
6488 {
6489         struct drm_device *dev = crtc->dev;
6490         struct drm_i915_private *dev_priv = dev->dev_private;
6491         struct intel_framebuffer *intel_fb;
6492         struct drm_i915_gem_object *obj;
6493         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6494         struct intel_unpin_work *work;
6495         unsigned long flags;
6496         int ret;
6497
6498         work = kzalloc(sizeof *work, GFP_KERNEL);
6499         if (work == NULL)
6500                 return -ENOMEM;
6501
6502         work->event = event;
6503         work->dev = crtc->dev;
6504         intel_fb = to_intel_framebuffer(crtc->fb);
6505         work->old_fb_obj = intel_fb->obj;
6506         INIT_WORK(&work->work, intel_unpin_work_fn);
6507
6508         /* We borrow the event spin lock for protecting unpin_work */
6509         spin_lock_irqsave(&dev->event_lock, flags);
6510         if (intel_crtc->unpin_work) {
6511                 spin_unlock_irqrestore(&dev->event_lock, flags);
6512                 kfree(work);
6513
6514                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6515                 return -EBUSY;
6516         }
6517         intel_crtc->unpin_work = work;
6518         spin_unlock_irqrestore(&dev->event_lock, flags);
6519
6520         intel_fb = to_intel_framebuffer(fb);
6521         obj = intel_fb->obj;
6522
6523         mutex_lock(&dev->struct_mutex);
6524
6525         /* Reference the objects for the scheduled work. */
6526         drm_gem_object_reference(&work->old_fb_obj->base);
6527         drm_gem_object_reference(&obj->base);
6528
6529         crtc->fb = fb;
6530
6531         ret = drm_vblank_get(dev, intel_crtc->pipe);
6532         if (ret)
6533                 goto cleanup_objs;
6534
6535         work->pending_flip_obj = obj;
6536
6537         work->enable_stall_check = true;
6538
6539         /* Block clients from rendering to the new back buffer until
6540          * the flip occurs and the object is no longer visible.
6541          */
6542         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6543
6544         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6545         if (ret)
6546                 goto cleanup_pending;
6547
6548         mutex_unlock(&dev->struct_mutex);
6549
6550         trace_i915_flip_request(intel_crtc->plane, obj);
6551
6552         return 0;
6553
6554 cleanup_pending:
6555         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6556 cleanup_objs:
6557         drm_gem_object_unreference(&work->old_fb_obj->base);
6558         drm_gem_object_unreference(&obj->base);
6559         mutex_unlock(&dev->struct_mutex);
6560
6561         spin_lock_irqsave(&dev->event_lock, flags);
6562         intel_crtc->unpin_work = NULL;
6563         spin_unlock_irqrestore(&dev->event_lock, flags);
6564
6565         kfree(work);
6566
6567         return ret;
6568 }
6569
6570 static void intel_sanitize_modesetting(struct drm_device *dev,
6571                                        int pipe, int plane)
6572 {
6573         struct drm_i915_private *dev_priv = dev->dev_private;
6574         u32 reg, val;
6575
6576         if (HAS_PCH_SPLIT(dev))
6577                 return;
6578
6579         /* Who knows what state these registers were left in by the BIOS or
6580          * grub?
6581          *
6582          * If we leave the registers in a conflicting state (e.g. with the
6583          * display plane reading from the other pipe than the one we intend
6584          * to use) then when we attempt to teardown the active mode, we will
6585          * not disable the pipes and planes in the correct order -- leaving
6586          * a plane reading from a disabled pipe and possibly leading to
6587          * undefined behaviour.
6588          */
6589
6590         reg = DSPCNTR(plane);
6591         val = I915_READ(reg);
6592
6593         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6594                 return;
6595         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6596                 return;
6597
6598         /* This display plane is active and attached to the other CPU pipe. */
6599         pipe = !pipe;
6600
6601         /* Disable the plane and wait for it to stop reading from the pipe. */
6602         intel_disable_plane(dev_priv, plane, pipe);
6603         intel_disable_pipe(dev_priv, pipe);
6604 }
6605
6606 static void intel_crtc_reset(struct drm_crtc *crtc)
6607 {
6608         struct drm_device *dev = crtc->dev;
6609         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6610
6611         /* Reset flags back to the 'unknown' status so that they
6612          * will be correctly set on the initial modeset.
6613          */
6614         intel_crtc->dpms_mode = -1;
6615
6616         /* We need to fix up any BIOS configuration that conflicts with
6617          * our expectations.
6618          */
6619         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6620 }
6621
6622 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6623         .dpms = intel_crtc_dpms,
6624         .mode_fixup = intel_crtc_mode_fixup,
6625         .mode_set = intel_crtc_mode_set,
6626         .mode_set_base = intel_pipe_set_base,
6627         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6628         .load_lut = intel_crtc_load_lut,
6629         .disable = intel_crtc_disable,
6630 };
6631
6632 static const struct drm_crtc_funcs intel_crtc_funcs = {
6633         .reset = intel_crtc_reset,
6634         .cursor_set = intel_crtc_cursor_set,
6635         .cursor_move = intel_crtc_cursor_move,
6636         .gamma_set = intel_crtc_gamma_set,
6637         .set_config = drm_crtc_helper_set_config,
6638         .destroy = intel_crtc_destroy,
6639         .page_flip = intel_crtc_page_flip,
6640 };
6641
6642 static void intel_crtc_init(struct drm_device *dev, int pipe)
6643 {
6644         drm_i915_private_t *dev_priv = dev->dev_private;
6645         struct intel_crtc *intel_crtc;
6646         int i;
6647
6648         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6649         if (intel_crtc == NULL)
6650                 return;
6651
6652         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6653
6654         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6655         for (i = 0; i < 256; i++) {
6656                 intel_crtc->lut_r[i] = i;
6657                 intel_crtc->lut_g[i] = i;
6658                 intel_crtc->lut_b[i] = i;
6659         }
6660
6661         /* Swap pipes & planes for FBC on pre-965 */
6662         intel_crtc->pipe = pipe;
6663         intel_crtc->plane = pipe;
6664         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6665                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6666                 intel_crtc->plane = !pipe;
6667         }
6668
6669         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6670                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6671         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6672         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6673
6674         intel_crtc_reset(&intel_crtc->base);
6675         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6676
6677         if (HAS_PCH_SPLIT(dev)) {
6678                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6679                 intel_helper_funcs.commit = ironlake_crtc_commit;
6680         } else {
6681                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6682                 intel_helper_funcs.commit = i9xx_crtc_commit;
6683         }
6684
6685         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6686
6687         intel_crtc->busy = false;
6688
6689         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6690                     (unsigned long)intel_crtc);
6691 }
6692
6693 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6694                                 struct drm_file *file)
6695 {
6696         drm_i915_private_t *dev_priv = dev->dev_private;
6697         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6698         struct drm_mode_object *drmmode_obj;
6699         struct intel_crtc *crtc;
6700
6701         if (!dev_priv) {
6702                 DRM_ERROR("called with no initialization\n");
6703                 return -EINVAL;
6704         }
6705
6706         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6707                         DRM_MODE_OBJECT_CRTC);
6708
6709         if (!drmmode_obj) {
6710                 DRM_ERROR("no such CRTC id\n");
6711                 return -EINVAL;
6712         }
6713
6714         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6715         pipe_from_crtc_id->pipe = crtc->pipe;
6716
6717         return 0;
6718 }
6719
6720 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6721 {
6722         struct intel_encoder *encoder;
6723         int index_mask = 0;
6724         int entry = 0;
6725
6726         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6727                 if (type_mask & encoder->clone_mask)
6728                         index_mask |= (1 << entry);
6729                 entry++;
6730         }
6731
6732         return index_mask;
6733 }
6734
6735 static bool has_edp_a(struct drm_device *dev)
6736 {
6737         struct drm_i915_private *dev_priv = dev->dev_private;
6738
6739         if (!IS_MOBILE(dev))
6740                 return false;
6741
6742         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6743                 return false;
6744
6745         if (IS_GEN5(dev) &&
6746             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6747                 return false;
6748
6749         return true;
6750 }
6751
6752 static void intel_setup_outputs(struct drm_device *dev)
6753 {
6754         struct drm_i915_private *dev_priv = dev->dev_private;
6755         struct intel_encoder *encoder;
6756         bool dpd_is_edp = false;
6757         bool has_lvds = false;
6758
6759         if (IS_MOBILE(dev) && !IS_I830(dev))
6760                 has_lvds = intel_lvds_init(dev);
6761         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6762                 /* disable the panel fitter on everything but LVDS */
6763                 I915_WRITE(PFIT_CONTROL, 0);
6764         }
6765
6766         if (HAS_PCH_SPLIT(dev)) {
6767                 dpd_is_edp = intel_dpd_is_edp(dev);
6768
6769                 if (has_edp_a(dev))
6770                         intel_dp_init(dev, DP_A);
6771
6772                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6773                         intel_dp_init(dev, PCH_DP_D);
6774         }
6775
6776         intel_crt_init(dev);
6777
6778         if (HAS_PCH_SPLIT(dev)) {
6779                 int found;
6780
6781                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6782                         /* PCH SDVOB multiplex with HDMIB */
6783                         found = intel_sdvo_init(dev, PCH_SDVOB);
6784                         if (!found)
6785                                 intel_hdmi_init(dev, HDMIB);
6786                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6787                                 intel_dp_init(dev, PCH_DP_B);
6788                 }
6789
6790                 if (I915_READ(HDMIC) & PORT_DETECTED)
6791                         intel_hdmi_init(dev, HDMIC);
6792
6793                 if (I915_READ(HDMID) & PORT_DETECTED)
6794                         intel_hdmi_init(dev, HDMID);
6795
6796                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6797                         intel_dp_init(dev, PCH_DP_C);
6798
6799                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6800                         intel_dp_init(dev, PCH_DP_D);
6801
6802         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6803                 bool found = false;
6804
6805                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6806                         DRM_DEBUG_KMS("probing SDVOB\n");
6807                         found = intel_sdvo_init(dev, SDVOB);
6808                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6809                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6810                                 intel_hdmi_init(dev, SDVOB);
6811                         }
6812
6813                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6814                                 DRM_DEBUG_KMS("probing DP_B\n");
6815                                 intel_dp_init(dev, DP_B);
6816                         }
6817                 }
6818
6819                 /* Before G4X SDVOC doesn't have its own detect register */
6820
6821                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6822                         DRM_DEBUG_KMS("probing SDVOC\n");
6823                         found = intel_sdvo_init(dev, SDVOC);
6824                 }
6825
6826                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6827
6828                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6829                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6830                                 intel_hdmi_init(dev, SDVOC);
6831                         }
6832                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6833                                 DRM_DEBUG_KMS("probing DP_C\n");
6834                                 intel_dp_init(dev, DP_C);
6835                         }
6836                 }
6837
6838                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6839                     (I915_READ(DP_D) & DP_DETECTED)) {
6840                         DRM_DEBUG_KMS("probing DP_D\n");
6841                         intel_dp_init(dev, DP_D);
6842                 }
6843         } else if (IS_GEN2(dev))
6844                 intel_dvo_init(dev);
6845
6846         if (SUPPORTS_TV(dev))
6847                 intel_tv_init(dev);
6848
6849         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6850                 encoder->base.possible_crtcs = encoder->crtc_mask;
6851                 encoder->base.possible_clones =
6852                         intel_encoder_clones(dev, encoder->clone_mask);
6853         }
6854
6855         intel_panel_setup_backlight(dev);
6856
6857         /* disable all the possible outputs/crtcs before entering KMS mode */
6858         drm_helper_disable_unused_functions(dev);
6859 }
6860
6861 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6862 {
6863         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6864
6865         drm_framebuffer_cleanup(fb);
6866         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6867
6868         kfree(intel_fb);
6869 }
6870
6871 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6872                                                 struct drm_file *file,
6873                                                 unsigned int *handle)
6874 {
6875         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6876         struct drm_i915_gem_object *obj = intel_fb->obj;
6877
6878         return drm_gem_handle_create(file, &obj->base, handle);
6879 }
6880
6881 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6882         .destroy = intel_user_framebuffer_destroy,
6883         .create_handle = intel_user_framebuffer_create_handle,
6884 };
6885
6886 int intel_framebuffer_init(struct drm_device *dev,
6887                            struct intel_framebuffer *intel_fb,
6888                            struct drm_mode_fb_cmd *mode_cmd,
6889                            struct drm_i915_gem_object *obj)
6890 {
6891         int ret;
6892
6893         if (obj->tiling_mode == I915_TILING_Y)
6894                 return -EINVAL;
6895
6896         if (mode_cmd->pitch & 63)
6897                 return -EINVAL;
6898
6899         switch (mode_cmd->bpp) {
6900         case 8:
6901         case 16:
6902         case 24:
6903         case 32:
6904                 break;
6905         default:
6906                 return -EINVAL;
6907         }
6908
6909         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6910         if (ret) {
6911                 DRM_ERROR("framebuffer init failed %d\n", ret);
6912                 return ret;
6913         }
6914
6915         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6916         intel_fb->obj = obj;
6917         return 0;
6918 }
6919
6920 static struct drm_framebuffer *
6921 intel_user_framebuffer_create(struct drm_device *dev,
6922                               struct drm_file *filp,
6923                               struct drm_mode_fb_cmd *mode_cmd)
6924 {
6925         struct drm_i915_gem_object *obj;
6926
6927         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6928         if (&obj->base == NULL)
6929                 return ERR_PTR(-ENOENT);
6930
6931         return intel_framebuffer_create(dev, mode_cmd, obj);
6932 }
6933
6934 static const struct drm_mode_config_funcs intel_mode_funcs = {
6935         .fb_create = intel_user_framebuffer_create,
6936         .output_poll_changed = intel_fb_output_poll_changed,
6937 };
6938
6939 static struct drm_i915_gem_object *
6940 intel_alloc_context_page(struct drm_device *dev)
6941 {
6942         struct drm_i915_gem_object *ctx;
6943         int ret;
6944
6945         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6946
6947         ctx = i915_gem_alloc_object(dev, 4096);
6948         if (!ctx) {
6949                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6950                 return NULL;
6951         }
6952
6953         ret = i915_gem_object_pin(ctx, 4096, true);
6954         if (ret) {
6955                 DRM_ERROR("failed to pin power context: %d\n", ret);
6956                 goto err_unref;
6957         }
6958
6959         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6960         if (ret) {
6961                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6962                 goto err_unpin;
6963         }
6964
6965         return ctx;
6966
6967 err_unpin:
6968         i915_gem_object_unpin(ctx);
6969 err_unref:
6970         drm_gem_object_unreference(&ctx->base);
6971         mutex_unlock(&dev->struct_mutex);
6972         return NULL;
6973 }
6974
6975 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6976 {
6977         struct drm_i915_private *dev_priv = dev->dev_private;
6978         u16 rgvswctl;
6979
6980         rgvswctl = I915_READ16(MEMSWCTL);
6981         if (rgvswctl & MEMCTL_CMD_STS) {
6982                 DRM_DEBUG("gpu busy, RCS change rejected\n");
6983                 return false; /* still busy with another command */
6984         }
6985
6986         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6987                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6988         I915_WRITE16(MEMSWCTL, rgvswctl);
6989         POSTING_READ16(MEMSWCTL);
6990
6991         rgvswctl |= MEMCTL_CMD_STS;
6992         I915_WRITE16(MEMSWCTL, rgvswctl);
6993
6994         return true;
6995 }
6996
6997 void ironlake_enable_drps(struct drm_device *dev)
6998 {
6999         struct drm_i915_private *dev_priv = dev->dev_private;
7000         u32 rgvmodectl = I915_READ(MEMMODECTL);
7001         u8 fmax, fmin, fstart, vstart;
7002
7003         /* Enable temp reporting */
7004         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7005         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7006
7007         /* 100ms RC evaluation intervals */
7008         I915_WRITE(RCUPEI, 100000);
7009         I915_WRITE(RCDNEI, 100000);
7010
7011         /* Set max/min thresholds to 90ms and 80ms respectively */
7012         I915_WRITE(RCBMAXAVG, 90000);
7013         I915_WRITE(RCBMINAVG, 80000);
7014
7015         I915_WRITE(MEMIHYST, 1);
7016
7017         /* Set up min, max, and cur for interrupt handling */
7018         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7019         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7020         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7021                 MEMMODE_FSTART_SHIFT;
7022
7023         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7024                 PXVFREQ_PX_SHIFT;
7025
7026         dev_priv->fmax = fmax; /* IPS callback will increase this */
7027         dev_priv->fstart = fstart;
7028
7029         dev_priv->max_delay = fstart;
7030         dev_priv->min_delay = fmin;
7031         dev_priv->cur_delay = fstart;
7032
7033         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7034                          fmax, fmin, fstart);
7035
7036         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7037
7038         /*
7039          * Interrupts will be enabled in ironlake_irq_postinstall
7040          */
7041
7042         I915_WRITE(VIDSTART, vstart);
7043         POSTING_READ(VIDSTART);
7044
7045         rgvmodectl |= MEMMODE_SWMODE_EN;
7046         I915_WRITE(MEMMODECTL, rgvmodectl);
7047
7048         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7049                 DRM_ERROR("stuck trying to change perf mode\n");
7050         msleep(1);
7051
7052         ironlake_set_drps(dev, fstart);
7053
7054         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7055                 I915_READ(0x112e0);
7056         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7057         dev_priv->last_count2 = I915_READ(0x112f4);
7058         getrawmonotonic(&dev_priv->last_time2);
7059 }
7060
7061 void ironlake_disable_drps(struct drm_device *dev)
7062 {
7063         struct drm_i915_private *dev_priv = dev->dev_private;
7064         u16 rgvswctl = I915_READ16(MEMSWCTL);
7065
7066         /* Ack interrupts, disable EFC interrupt */
7067         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7068         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7069         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7070         I915_WRITE(DEIIR, DE_PCU_EVENT);
7071         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7072
7073         /* Go back to the starting frequency */
7074         ironlake_set_drps(dev, dev_priv->fstart);
7075         msleep(1);
7076         rgvswctl |= MEMCTL_CMD_STS;
7077         I915_WRITE(MEMSWCTL, rgvswctl);
7078         msleep(1);
7079
7080 }
7081
7082 void gen6_set_rps(struct drm_device *dev, u8 val)
7083 {
7084         struct drm_i915_private *dev_priv = dev->dev_private;
7085         u32 swreq;
7086
7087         swreq = (val & 0x3ff) << 25;
7088         I915_WRITE(GEN6_RPNSWREQ, swreq);
7089 }
7090
7091 void gen6_disable_rps(struct drm_device *dev)
7092 {
7093         struct drm_i915_private *dev_priv = dev->dev_private;
7094
7095         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7096         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7097         I915_WRITE(GEN6_PMIER, 0);
7098
7099         spin_lock_irq(&dev_priv->rps_lock);
7100         dev_priv->pm_iir = 0;
7101         spin_unlock_irq(&dev_priv->rps_lock);
7102
7103         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7104 }
7105
7106 static unsigned long intel_pxfreq(u32 vidfreq)
7107 {
7108         unsigned long freq;
7109         int div = (vidfreq & 0x3f0000) >> 16;
7110         int post = (vidfreq & 0x3000) >> 12;
7111         int pre = (vidfreq & 0x7);
7112
7113         if (!pre)
7114                 return 0;
7115
7116         freq = ((div * 133333) / ((1<<post) * pre));
7117
7118         return freq;
7119 }
7120
7121 void intel_init_emon(struct drm_device *dev)
7122 {
7123         struct drm_i915_private *dev_priv = dev->dev_private;
7124         u32 lcfuse;
7125         u8 pxw[16];
7126         int i;
7127
7128         /* Disable to program */
7129         I915_WRITE(ECR, 0);
7130         POSTING_READ(ECR);
7131
7132         /* Program energy weights for various events */
7133         I915_WRITE(SDEW, 0x15040d00);
7134         I915_WRITE(CSIEW0, 0x007f0000);
7135         I915_WRITE(CSIEW1, 0x1e220004);
7136         I915_WRITE(CSIEW2, 0x04000004);
7137
7138         for (i = 0; i < 5; i++)
7139                 I915_WRITE(PEW + (i * 4), 0);
7140         for (i = 0; i < 3; i++)
7141                 I915_WRITE(DEW + (i * 4), 0);
7142
7143         /* Program P-state weights to account for frequency power adjustment */
7144         for (i = 0; i < 16; i++) {
7145                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7146                 unsigned long freq = intel_pxfreq(pxvidfreq);
7147                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7148                         PXVFREQ_PX_SHIFT;
7149                 unsigned long val;
7150
7151                 val = vid * vid;
7152                 val *= (freq / 1000);
7153                 val *= 255;
7154                 val /= (127*127*900);
7155                 if (val > 0xff)
7156                         DRM_ERROR("bad pxval: %ld\n", val);
7157                 pxw[i] = val;
7158         }
7159         /* Render standby states get 0 weight */
7160         pxw[14] = 0;
7161         pxw[15] = 0;
7162
7163         for (i = 0; i < 4; i++) {
7164                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7165                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7166                 I915_WRITE(PXW + (i * 4), val);
7167         }
7168
7169         /* Adjust magic regs to magic values (more experimental results) */
7170         I915_WRITE(OGW0, 0);
7171         I915_WRITE(OGW1, 0);
7172         I915_WRITE(EG0, 0x00007f00);
7173         I915_WRITE(EG1, 0x0000000e);
7174         I915_WRITE(EG2, 0x000e0000);
7175         I915_WRITE(EG3, 0x68000300);
7176         I915_WRITE(EG4, 0x42000000);
7177         I915_WRITE(EG5, 0x00140031);
7178         I915_WRITE(EG6, 0);
7179         I915_WRITE(EG7, 0);
7180
7181         for (i = 0; i < 8; i++)
7182                 I915_WRITE(PXWL + (i * 4), 0);
7183
7184         /* Enable PMON + select events */
7185         I915_WRITE(ECR, 0x80000019);
7186
7187         lcfuse = I915_READ(LCFUSE02);
7188
7189         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7190 }
7191
7192 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7193 {
7194         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7195         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7196         u32 pcu_mbox, rc6_mask = 0;
7197         int cur_freq, min_freq, max_freq;
7198         int i;
7199
7200         /* Here begins a magic sequence of register writes to enable
7201          * auto-downclocking.
7202          *
7203          * Perhaps there might be some value in exposing these to
7204          * userspace...
7205          */
7206         I915_WRITE(GEN6_RC_STATE, 0);
7207         mutex_lock(&dev_priv->dev->struct_mutex);
7208         gen6_gt_force_wake_get(dev_priv);
7209
7210         /* disable the counters and set deterministic thresholds */
7211         I915_WRITE(GEN6_RC_CONTROL, 0);
7212
7213         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7214         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7215         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7216         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7217         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7218
7219         for (i = 0; i < I915_NUM_RINGS; i++)
7220                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7221
7222         I915_WRITE(GEN6_RC_SLEEP, 0);
7223         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7224         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7225         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7226         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7227
7228         if (i915_enable_rc6)
7229                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7230                         GEN6_RC_CTL_RC6_ENABLE;
7231
7232         I915_WRITE(GEN6_RC_CONTROL,
7233                    rc6_mask |
7234                    GEN6_RC_CTL_EI_MODE(1) |
7235                    GEN6_RC_CTL_HW_ENABLE);
7236
7237         I915_WRITE(GEN6_RPNSWREQ,
7238                    GEN6_FREQUENCY(10) |
7239                    GEN6_OFFSET(0) |
7240                    GEN6_AGGRESSIVE_TURBO);
7241         I915_WRITE(GEN6_RC_VIDEO_FREQ,
7242                    GEN6_FREQUENCY(12));
7243
7244         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7245         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7246                    18 << 24 |
7247                    6 << 16);
7248         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7249         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7250         I915_WRITE(GEN6_RP_UP_EI, 100000);
7251         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7252         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7253         I915_WRITE(GEN6_RP_CONTROL,
7254                    GEN6_RP_MEDIA_TURBO |
7255                    GEN6_RP_USE_NORMAL_FREQ |
7256                    GEN6_RP_MEDIA_IS_GFX |
7257                    GEN6_RP_ENABLE |
7258                    GEN6_RP_UP_BUSY_AVG |
7259                    GEN6_RP_DOWN_IDLE_CONT);
7260
7261         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7262                      500))
7263                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7264
7265         I915_WRITE(GEN6_PCODE_DATA, 0);
7266         I915_WRITE(GEN6_PCODE_MAILBOX,
7267                    GEN6_PCODE_READY |
7268                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7269         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7270                      500))
7271                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7272
7273         min_freq = (rp_state_cap & 0xff0000) >> 16;
7274         max_freq = rp_state_cap & 0xff;
7275         cur_freq = (gt_perf_status & 0xff00) >> 8;
7276
7277         /* Check for overclock support */
7278         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7279                      500))
7280                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7281         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7282         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7283         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7284                      500))
7285                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7286         if (pcu_mbox & (1<<31)) { /* OC supported */
7287                 max_freq = pcu_mbox & 0xff;
7288                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7289         }
7290
7291         /* In units of 100MHz */
7292         dev_priv->max_delay = max_freq;
7293         dev_priv->min_delay = min_freq;
7294         dev_priv->cur_delay = cur_freq;
7295
7296         /* requires MSI enabled */
7297         I915_WRITE(GEN6_PMIER,
7298                    GEN6_PM_MBOX_EVENT |
7299                    GEN6_PM_THERMAL_EVENT |
7300                    GEN6_PM_RP_DOWN_TIMEOUT |
7301                    GEN6_PM_RP_UP_THRESHOLD |
7302                    GEN6_PM_RP_DOWN_THRESHOLD |
7303                    GEN6_PM_RP_UP_EI_EXPIRED |
7304                    GEN6_PM_RP_DOWN_EI_EXPIRED);
7305         spin_lock_irq(&dev_priv->rps_lock);
7306         WARN_ON(dev_priv->pm_iir != 0);
7307         I915_WRITE(GEN6_PMIMR, 0);
7308         spin_unlock_irq(&dev_priv->rps_lock);
7309         /* enable all PM interrupts */
7310         I915_WRITE(GEN6_PMINTRMSK, 0);
7311
7312         gen6_gt_force_wake_put(dev_priv);
7313         mutex_unlock(&dev_priv->dev->struct_mutex);
7314 }
7315
7316 static void ironlake_init_clock_gating(struct drm_device *dev)
7317 {
7318         struct drm_i915_private *dev_priv = dev->dev_private;
7319         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7320
7321         /* Required for FBC */
7322         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7323                 DPFCRUNIT_CLOCK_GATE_DISABLE |
7324                 DPFDUNIT_CLOCK_GATE_DISABLE;
7325         /* Required for CxSR */
7326         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7327
7328         I915_WRITE(PCH_3DCGDIS0,
7329                    MARIUNIT_CLOCK_GATE_DISABLE |
7330                    SVSMUNIT_CLOCK_GATE_DISABLE);
7331         I915_WRITE(PCH_3DCGDIS1,
7332                    VFMUNIT_CLOCK_GATE_DISABLE);
7333
7334         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7335
7336         /*
7337          * According to the spec the following bits should be set in
7338          * order to enable memory self-refresh
7339          * The bit 22/21 of 0x42004
7340          * The bit 5 of 0x42020
7341          * The bit 15 of 0x45000
7342          */
7343         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7344                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
7345                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7346         I915_WRITE(ILK_DSPCLK_GATE,
7347                    (I915_READ(ILK_DSPCLK_GATE) |
7348                     ILK_DPARB_CLK_GATE));
7349         I915_WRITE(DISP_ARB_CTL,
7350                    (I915_READ(DISP_ARB_CTL) |
7351                     DISP_FBC_WM_DIS));
7352         I915_WRITE(WM3_LP_ILK, 0);
7353         I915_WRITE(WM2_LP_ILK, 0);
7354         I915_WRITE(WM1_LP_ILK, 0);
7355
7356         /*
7357          * Based on the document from hardware guys the following bits
7358          * should be set unconditionally in order to enable FBC.
7359          * The bit 22 of 0x42000
7360          * The bit 22 of 0x42004
7361          * The bit 7,8,9 of 0x42020.
7362          */
7363         if (IS_IRONLAKE_M(dev)) {
7364                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7365                            I915_READ(ILK_DISPLAY_CHICKEN1) |
7366                            ILK_FBCQ_DIS);
7367                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7368                            I915_READ(ILK_DISPLAY_CHICKEN2) |
7369                            ILK_DPARB_GATE);
7370                 I915_WRITE(ILK_DSPCLK_GATE,
7371                            I915_READ(ILK_DSPCLK_GATE) |
7372                            ILK_DPFC_DIS1 |
7373                            ILK_DPFC_DIS2 |
7374                            ILK_CLK_FBC);
7375         }
7376
7377         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7378                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7379                    ILK_ELPIN_409_SELECT);
7380         I915_WRITE(_3D_CHICKEN2,
7381                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7382                    _3D_CHICKEN2_WM_READ_PIPELINED);
7383 }
7384
7385 static void gen6_init_clock_gating(struct drm_device *dev)
7386 {
7387         struct drm_i915_private *dev_priv = dev->dev_private;
7388         int pipe;
7389         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7390
7391         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7392
7393         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7394                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7395                    ILK_ELPIN_409_SELECT);
7396
7397         I915_WRITE(WM3_LP_ILK, 0);
7398         I915_WRITE(WM2_LP_ILK, 0);
7399         I915_WRITE(WM1_LP_ILK, 0);
7400
7401         /*
7402          * According to the spec the following bits should be
7403          * set in order to enable memory self-refresh and fbc:
7404          * The bit21 and bit22 of 0x42000
7405          * The bit21 and bit22 of 0x42004
7406          * The bit5 and bit7 of 0x42020
7407          * The bit14 of 0x70180
7408          * The bit14 of 0x71180
7409          */
7410         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7411                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7412                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7413         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7414                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7415                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7416         I915_WRITE(ILK_DSPCLK_GATE,
7417                    I915_READ(ILK_DSPCLK_GATE) |
7418                    ILK_DPARB_CLK_GATE  |
7419                    ILK_DPFD_CLK_GATE);
7420
7421         for_each_pipe(pipe)
7422                 I915_WRITE(DSPCNTR(pipe),
7423                            I915_READ(DSPCNTR(pipe)) |
7424                            DISPPLANE_TRICKLE_FEED_DISABLE);
7425 }
7426
7427 static void ivybridge_init_clock_gating(struct drm_device *dev)
7428 {
7429         struct drm_i915_private *dev_priv = dev->dev_private;
7430         int pipe;
7431         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7432
7433         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7434
7435         I915_WRITE(WM3_LP_ILK, 0);
7436         I915_WRITE(WM2_LP_ILK, 0);
7437         I915_WRITE(WM1_LP_ILK, 0);
7438
7439         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7440
7441         for_each_pipe(pipe)
7442                 I915_WRITE(DSPCNTR(pipe),
7443                            I915_READ(DSPCNTR(pipe)) |
7444                            DISPPLANE_TRICKLE_FEED_DISABLE);
7445 }
7446
7447 static void g4x_init_clock_gating(struct drm_device *dev)
7448 {
7449         struct drm_i915_private *dev_priv = dev->dev_private;
7450         uint32_t dspclk_gate;
7451
7452         I915_WRITE(RENCLK_GATE_D1, 0);
7453         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7454                    GS_UNIT_CLOCK_GATE_DISABLE |
7455                    CL_UNIT_CLOCK_GATE_DISABLE);
7456         I915_WRITE(RAMCLK_GATE_D, 0);
7457         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7458                 OVRUNIT_CLOCK_GATE_DISABLE |
7459                 OVCUNIT_CLOCK_GATE_DISABLE;
7460         if (IS_GM45(dev))
7461                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7462         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7463 }
7464
7465 static void crestline_init_clock_gating(struct drm_device *dev)
7466 {
7467         struct drm_i915_private *dev_priv = dev->dev_private;
7468
7469         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7470         I915_WRITE(RENCLK_GATE_D2, 0);
7471         I915_WRITE(DSPCLK_GATE_D, 0);
7472         I915_WRITE(RAMCLK_GATE_D, 0);
7473         I915_WRITE16(DEUC, 0);
7474 }
7475
7476 static void broadwater_init_clock_gating(struct drm_device *dev)
7477 {
7478         struct drm_i915_private *dev_priv = dev->dev_private;
7479
7480         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7481                    I965_RCC_CLOCK_GATE_DISABLE |
7482                    I965_RCPB_CLOCK_GATE_DISABLE |
7483                    I965_ISC_CLOCK_GATE_DISABLE |
7484                    I965_FBC_CLOCK_GATE_DISABLE);
7485         I915_WRITE(RENCLK_GATE_D2, 0);
7486 }
7487
7488 static void gen3_init_clock_gating(struct drm_device *dev)
7489 {
7490         struct drm_i915_private *dev_priv = dev->dev_private;
7491         u32 dstate = I915_READ(D_STATE);
7492
7493         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7494                 DSTATE_DOT_CLOCK_GATING;
7495         I915_WRITE(D_STATE, dstate);
7496 }
7497
7498 static void i85x_init_clock_gating(struct drm_device *dev)
7499 {
7500         struct drm_i915_private *dev_priv = dev->dev_private;
7501
7502         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7503 }
7504
7505 static void i830_init_clock_gating(struct drm_device *dev)
7506 {
7507         struct drm_i915_private *dev_priv = dev->dev_private;
7508
7509         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7510 }
7511
7512 static void ibx_init_clock_gating(struct drm_device *dev)
7513 {
7514         struct drm_i915_private *dev_priv = dev->dev_private;
7515
7516         /*
7517          * On Ibex Peak and Cougar Point, we need to disable clock
7518          * gating for the panel power sequencer or it will fail to
7519          * start up when no ports are active.
7520          */
7521         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7522 }
7523
7524 static void cpt_init_clock_gating(struct drm_device *dev)
7525 {
7526         struct drm_i915_private *dev_priv = dev->dev_private;
7527
7528         /*
7529          * On Ibex Peak and Cougar Point, we need to disable clock
7530          * gating for the panel power sequencer or it will fail to
7531          * start up when no ports are active.
7532          */
7533         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7534         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7535                    DPLS_EDP_PPS_FIX_DIS);
7536 }
7537
7538 static void ironlake_teardown_rc6(struct drm_device *dev)
7539 {
7540         struct drm_i915_private *dev_priv = dev->dev_private;
7541
7542         if (dev_priv->renderctx) {
7543                 i915_gem_object_unpin(dev_priv->renderctx);
7544                 drm_gem_object_unreference(&dev_priv->renderctx->base);
7545                 dev_priv->renderctx = NULL;
7546         }
7547
7548         if (dev_priv->pwrctx) {
7549                 i915_gem_object_unpin(dev_priv->pwrctx);
7550                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7551                 dev_priv->pwrctx = NULL;
7552         }
7553 }
7554
7555 static void ironlake_disable_rc6(struct drm_device *dev)
7556 {
7557         struct drm_i915_private *dev_priv = dev->dev_private;
7558
7559         if (I915_READ(PWRCTXA)) {
7560                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7561                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7562                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7563                          50);
7564
7565                 I915_WRITE(PWRCTXA, 0);
7566                 POSTING_READ(PWRCTXA);
7567
7568                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7569                 POSTING_READ(RSTDBYCTL);
7570         }
7571
7572         ironlake_teardown_rc6(dev);
7573 }
7574
7575 static int ironlake_setup_rc6(struct drm_device *dev)
7576 {
7577         struct drm_i915_private *dev_priv = dev->dev_private;
7578
7579         if (dev_priv->renderctx == NULL)
7580                 dev_priv->renderctx = intel_alloc_context_page(dev);
7581         if (!dev_priv->renderctx)
7582                 return -ENOMEM;
7583
7584         if (dev_priv->pwrctx == NULL)
7585                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7586         if (!dev_priv->pwrctx) {
7587                 ironlake_teardown_rc6(dev);
7588                 return -ENOMEM;
7589         }
7590
7591         return 0;
7592 }
7593
7594 void ironlake_enable_rc6(struct drm_device *dev)
7595 {
7596         struct drm_i915_private *dev_priv = dev->dev_private;
7597         int ret;
7598
7599         /* rc6 disabled by default due to repeated reports of hanging during
7600          * boot and resume.
7601          */
7602         if (!i915_enable_rc6)
7603                 return;
7604
7605         mutex_lock(&dev->struct_mutex);
7606         ret = ironlake_setup_rc6(dev);
7607         if (ret) {
7608                 mutex_unlock(&dev->struct_mutex);
7609                 return;
7610         }
7611
7612         /*
7613          * GPU can automatically power down the render unit if given a page
7614          * to save state.
7615          */
7616         ret = BEGIN_LP_RING(6);
7617         if (ret) {
7618                 ironlake_teardown_rc6(dev);
7619                 mutex_unlock(&dev->struct_mutex);
7620                 return;
7621         }
7622
7623         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7624         OUT_RING(MI_SET_CONTEXT);
7625         OUT_RING(dev_priv->renderctx->gtt_offset |
7626                  MI_MM_SPACE_GTT |
7627                  MI_SAVE_EXT_STATE_EN |
7628                  MI_RESTORE_EXT_STATE_EN |
7629                  MI_RESTORE_INHIBIT);
7630         OUT_RING(MI_SUSPEND_FLUSH);
7631         OUT_RING(MI_NOOP);
7632         OUT_RING(MI_FLUSH);
7633         ADVANCE_LP_RING();
7634
7635         /*
7636          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7637          * does an implicit flush, combined with MI_FLUSH above, it should be
7638          * safe to assume that renderctx is valid
7639          */
7640         ret = intel_wait_ring_idle(LP_RING(dev_priv));
7641         if (ret) {
7642                 DRM_ERROR("failed to enable ironlake power power savings\n");
7643                 ironlake_teardown_rc6(dev);
7644                 mutex_unlock(&dev->struct_mutex);
7645                 return;
7646         }
7647
7648         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7649         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7650         mutex_unlock(&dev->struct_mutex);
7651 }
7652
7653 void intel_init_clock_gating(struct drm_device *dev)
7654 {
7655         struct drm_i915_private *dev_priv = dev->dev_private;
7656
7657         dev_priv->display.init_clock_gating(dev);
7658
7659         if (dev_priv->display.init_pch_clock_gating)
7660                 dev_priv->display.init_pch_clock_gating(dev);
7661 }
7662
7663 /* Set up chip specific display functions */
7664 static void intel_init_display(struct drm_device *dev)
7665 {
7666         struct drm_i915_private *dev_priv = dev->dev_private;
7667
7668         /* We always want a DPMS function */
7669         if (HAS_PCH_SPLIT(dev)) {
7670                 dev_priv->display.dpms = ironlake_crtc_dpms;
7671                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7672         } else {
7673                 dev_priv->display.dpms = i9xx_crtc_dpms;
7674                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7675         }
7676
7677         if (I915_HAS_FBC(dev)) {
7678                 if (HAS_PCH_SPLIT(dev)) {
7679                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7680                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
7681                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
7682                 } else if (IS_GM45(dev)) {
7683                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7684                         dev_priv->display.enable_fbc = g4x_enable_fbc;
7685                         dev_priv->display.disable_fbc = g4x_disable_fbc;
7686                 } else if (IS_CRESTLINE(dev)) {
7687                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7688                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
7689                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
7690                 }
7691                 /* 855GM needs testing */
7692         }
7693
7694         /* Returns the core display clock speed */
7695         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7696                 dev_priv->display.get_display_clock_speed =
7697                         i945_get_display_clock_speed;
7698         else if (IS_I915G(dev))
7699                 dev_priv->display.get_display_clock_speed =
7700                         i915_get_display_clock_speed;
7701         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7702                 dev_priv->display.get_display_clock_speed =
7703                         i9xx_misc_get_display_clock_speed;
7704         else if (IS_I915GM(dev))
7705                 dev_priv->display.get_display_clock_speed =
7706                         i915gm_get_display_clock_speed;
7707         else if (IS_I865G(dev))
7708                 dev_priv->display.get_display_clock_speed =
7709                         i865_get_display_clock_speed;
7710         else if (IS_I85X(dev))
7711                 dev_priv->display.get_display_clock_speed =
7712                         i855_get_display_clock_speed;
7713         else /* 852, 830 */
7714                 dev_priv->display.get_display_clock_speed =
7715                         i830_get_display_clock_speed;
7716
7717         /* For FIFO watermark updates */
7718         if (HAS_PCH_SPLIT(dev)) {
7719                 if (HAS_PCH_IBX(dev))
7720                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7721                 else if (HAS_PCH_CPT(dev))
7722                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7723
7724                 if (IS_GEN5(dev)) {
7725                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7726                                 dev_priv->display.update_wm = ironlake_update_wm;
7727                         else {
7728                                 DRM_DEBUG_KMS("Failed to get proper latency. "
7729                                               "Disable CxSR\n");
7730                                 dev_priv->display.update_wm = NULL;
7731                         }
7732                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7733                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7734                 } else if (IS_GEN6(dev)) {
7735                         if (SNB_READ_WM0_LATENCY()) {
7736                                 dev_priv->display.update_wm = sandybridge_update_wm;
7737                         } else {
7738                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7739                                               "Disable CxSR\n");
7740                                 dev_priv->display.update_wm = NULL;
7741                         }
7742                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7743                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7744                 } else if (IS_IVYBRIDGE(dev)) {
7745                         /* FIXME: detect B0+ stepping and use auto training */
7746                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7747                         if (SNB_READ_WM0_LATENCY()) {
7748                                 dev_priv->display.update_wm = sandybridge_update_wm;
7749                         } else {
7750                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7751                                               "Disable CxSR\n");
7752                                 dev_priv->display.update_wm = NULL;
7753                         }
7754                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7755
7756                 } else
7757                         dev_priv->display.update_wm = NULL;
7758         } else if (IS_PINEVIEW(dev)) {
7759                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7760                                             dev_priv->is_ddr3,
7761                                             dev_priv->fsb_freq,
7762                                             dev_priv->mem_freq)) {
7763                         DRM_INFO("failed to find known CxSR latency "
7764                                  "(found ddr%s fsb freq %d, mem freq %d), "
7765                                  "disabling CxSR\n",
7766                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
7767                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7768                         /* Disable CxSR and never update its watermark again */
7769                         pineview_disable_cxsr(dev);
7770                         dev_priv->display.update_wm = NULL;
7771                 } else
7772                         dev_priv->display.update_wm = pineview_update_wm;
7773                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7774         } else if (IS_G4X(dev)) {
7775                 dev_priv->display.update_wm = g4x_update_wm;
7776                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7777         } else if (IS_GEN4(dev)) {
7778                 dev_priv->display.update_wm = i965_update_wm;
7779                 if (IS_CRESTLINE(dev))
7780                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7781                 else if (IS_BROADWATER(dev))
7782                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7783         } else if (IS_GEN3(dev)) {
7784                 dev_priv->display.update_wm = i9xx_update_wm;
7785                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7786                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7787         } else if (IS_I865G(dev)) {
7788                 dev_priv->display.update_wm = i830_update_wm;
7789                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7790                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7791         } else if (IS_I85X(dev)) {
7792                 dev_priv->display.update_wm = i9xx_update_wm;
7793                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7794                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7795         } else {
7796                 dev_priv->display.update_wm = i830_update_wm;
7797                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7798                 if (IS_845G(dev))
7799                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7800                 else
7801                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7802         }
7803
7804         /* Default just returns -ENODEV to indicate unsupported */
7805         dev_priv->display.queue_flip = intel_default_queue_flip;
7806
7807         switch (INTEL_INFO(dev)->gen) {
7808         case 2:
7809                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7810                 break;
7811
7812         case 3:
7813                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7814                 break;
7815
7816         case 4:
7817         case 5:
7818                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7819                 break;
7820
7821         case 6:
7822                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7823                 break;
7824         case 7:
7825                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7826                 break;
7827         }
7828 }
7829
7830 /*
7831  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7832  * resume, or other times.  This quirk makes sure that's the case for
7833  * affected systems.
7834  */
7835 static void quirk_pipea_force (struct drm_device *dev)
7836 {
7837         struct drm_i915_private *dev_priv = dev->dev_private;
7838
7839         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7840         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7841 }
7842
7843 /*
7844  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7845  */
7846 static void quirk_ssc_force_disable(struct drm_device *dev)
7847 {
7848         struct drm_i915_private *dev_priv = dev->dev_private;
7849         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7850 }
7851
7852 struct intel_quirk {
7853         int device;
7854         int subsystem_vendor;
7855         int subsystem_device;
7856         void (*hook)(struct drm_device *dev);
7857 };
7858
7859 struct intel_quirk intel_quirks[] = {
7860         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7861         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7862         /* HP Mini needs pipe A force quirk (LP: #322104) */
7863         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7864
7865         /* Thinkpad R31 needs pipe A force quirk */
7866         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7867         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7868         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7869
7870         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7871         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
7872         /* ThinkPad X40 needs pipe A force quirk */
7873
7874         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7875         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7876
7877         /* 855 & before need to leave pipe A & dpll A up */
7878         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7879         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7880
7881         /* Lenovo U160 cannot use SSC on LVDS */
7882         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7883 };
7884
7885 static void intel_init_quirks(struct drm_device *dev)
7886 {
7887         struct pci_dev *d = dev->pdev;
7888         int i;
7889
7890         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7891                 struct intel_quirk *q = &intel_quirks[i];
7892
7893                 if (d->device == q->device &&
7894                     (d->subsystem_vendor == q->subsystem_vendor ||
7895                      q->subsystem_vendor == PCI_ANY_ID) &&
7896                     (d->subsystem_device == q->subsystem_device ||
7897                      q->subsystem_device == PCI_ANY_ID))
7898                         q->hook(dev);
7899         }
7900 }
7901
7902 /* Disable the VGA plane that we never use */
7903 static void i915_disable_vga(struct drm_device *dev)
7904 {
7905         struct drm_i915_private *dev_priv = dev->dev_private;
7906         u8 sr1;
7907         u32 vga_reg;
7908
7909         if (HAS_PCH_SPLIT(dev))
7910                 vga_reg = CPU_VGACNTRL;
7911         else
7912                 vga_reg = VGACNTRL;
7913
7914         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7915         outb(1, VGA_SR_INDEX);
7916         sr1 = inb(VGA_SR_DATA);
7917         outb(sr1 | 1<<5, VGA_SR_DATA);
7918         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7919         udelay(300);
7920
7921         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7922         POSTING_READ(vga_reg);
7923 }
7924
7925 void intel_modeset_init(struct drm_device *dev)
7926 {
7927         struct drm_i915_private *dev_priv = dev->dev_private;
7928         int i;
7929
7930         drm_mode_config_init(dev);
7931
7932         dev->mode_config.min_width = 0;
7933         dev->mode_config.min_height = 0;
7934
7935         dev->mode_config.funcs = (void *)&intel_mode_funcs;
7936
7937         intel_init_quirks(dev);
7938
7939         intel_init_display(dev);
7940
7941         if (IS_GEN2(dev)) {
7942                 dev->mode_config.max_width = 2048;
7943                 dev->mode_config.max_height = 2048;
7944         } else if (IS_GEN3(dev)) {
7945                 dev->mode_config.max_width = 4096;
7946                 dev->mode_config.max_height = 4096;
7947         } else {
7948                 dev->mode_config.max_width = 8192;
7949                 dev->mode_config.max_height = 8192;
7950         }
7951         dev->mode_config.fb_base = dev->agp->base;
7952
7953         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7954                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7955
7956         for (i = 0; i < dev_priv->num_pipe; i++) {
7957                 intel_crtc_init(dev, i);
7958         }
7959
7960         /* Just disable it once at startup */
7961         i915_disable_vga(dev);
7962         intel_setup_outputs(dev);
7963
7964         intel_init_clock_gating(dev);
7965
7966         if (IS_IRONLAKE_M(dev)) {
7967                 ironlake_enable_drps(dev);
7968                 intel_init_emon(dev);
7969         }
7970
7971         if (IS_GEN6(dev))
7972                 gen6_enable_rps(dev_priv);
7973
7974         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7975         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7976                     (unsigned long)dev);
7977 }
7978
7979 void intel_modeset_gem_init(struct drm_device *dev)
7980 {
7981         if (IS_IRONLAKE_M(dev))
7982                 ironlake_enable_rc6(dev);
7983
7984         intel_setup_overlay(dev);
7985 }
7986
7987 void intel_modeset_cleanup(struct drm_device *dev)
7988 {
7989         struct drm_i915_private *dev_priv = dev->dev_private;
7990         struct drm_crtc *crtc;
7991         struct intel_crtc *intel_crtc;
7992
7993         drm_kms_helper_poll_fini(dev);
7994         mutex_lock(&dev->struct_mutex);
7995
7996         intel_unregister_dsm_handler();
7997
7998
7999         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8000                 /* Skip inactive CRTCs */
8001                 if (!crtc->fb)
8002                         continue;
8003
8004                 intel_crtc = to_intel_crtc(crtc);
8005                 intel_increase_pllclock(crtc);
8006         }
8007
8008         if (dev_priv->display.disable_fbc)
8009                 dev_priv->display.disable_fbc(dev);
8010
8011         if (IS_IRONLAKE_M(dev))
8012                 ironlake_disable_drps(dev);
8013         if (IS_GEN6(dev))
8014                 gen6_disable_rps(dev);
8015
8016         if (IS_IRONLAKE_M(dev))
8017                 ironlake_disable_rc6(dev);
8018
8019         mutex_unlock(&dev->struct_mutex);
8020
8021         /* Disable the irq before mode object teardown, for the irq might
8022          * enqueue unpin/hotplug work. */
8023         drm_irq_uninstall(dev);
8024         cancel_work_sync(&dev_priv->hotplug_work);
8025
8026         /* Shut off idle work before the crtcs get freed. */
8027         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8028                 intel_crtc = to_intel_crtc(crtc);
8029                 del_timer_sync(&intel_crtc->idle_timer);
8030         }
8031         del_timer_sync(&dev_priv->idle_timer);
8032         cancel_work_sync(&dev_priv->idle_work);
8033
8034         drm_mode_config_cleanup(dev);
8035 }
8036
8037 /*
8038  * Return which encoder is currently attached for connector.
8039  */
8040 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8041 {
8042         return &intel_attached_encoder(connector)->base;
8043 }
8044
8045 void intel_connector_attach_encoder(struct intel_connector *connector,
8046                                     struct intel_encoder *encoder)
8047 {
8048         connector->encoder = encoder;
8049         drm_mode_connector_attach_encoder(&connector->base,
8050                                           &encoder->base);
8051 }
8052
8053 /*
8054  * set vga decode state - true == enable VGA decode
8055  */
8056 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8057 {
8058         struct drm_i915_private *dev_priv = dev->dev_private;
8059         u16 gmch_ctrl;
8060
8061         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8062         if (state)
8063                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8064         else
8065                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8066         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8067         return 0;
8068 }
8069
8070 #ifdef CONFIG_DEBUG_FS
8071 #include <linux/seq_file.h>
8072
8073 struct intel_display_error_state {
8074         struct intel_cursor_error_state {
8075                 u32 control;
8076                 u32 position;
8077                 u32 base;
8078                 u32 size;
8079         } cursor[2];
8080
8081         struct intel_pipe_error_state {
8082                 u32 conf;
8083                 u32 source;
8084
8085                 u32 htotal;
8086                 u32 hblank;
8087                 u32 hsync;
8088                 u32 vtotal;
8089                 u32 vblank;
8090                 u32 vsync;
8091         } pipe[2];
8092
8093         struct intel_plane_error_state {
8094                 u32 control;
8095                 u32 stride;
8096                 u32 size;
8097                 u32 pos;
8098                 u32 addr;
8099                 u32 surface;
8100                 u32 tile_offset;
8101         } plane[2];
8102 };
8103
8104 struct intel_display_error_state *
8105 intel_display_capture_error_state(struct drm_device *dev)
8106 {
8107         drm_i915_private_t *dev_priv = dev->dev_private;
8108         struct intel_display_error_state *error;
8109         int i;
8110
8111         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8112         if (error == NULL)
8113                 return NULL;
8114
8115         for (i = 0; i < 2; i++) {
8116                 error->cursor[i].control = I915_READ(CURCNTR(i));
8117                 error->cursor[i].position = I915_READ(CURPOS(i));
8118                 error->cursor[i].base = I915_READ(CURBASE(i));
8119
8120                 error->plane[i].control = I915_READ(DSPCNTR(i));
8121                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8122                 error->plane[i].size = I915_READ(DSPSIZE(i));
8123                 error->plane[i].pos= I915_READ(DSPPOS(i));
8124                 error->plane[i].addr = I915_READ(DSPADDR(i));
8125                 if (INTEL_INFO(dev)->gen >= 4) {
8126                         error->plane[i].surface = I915_READ(DSPSURF(i));
8127                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8128                 }
8129
8130                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8131                 error->pipe[i].source = I915_READ(PIPESRC(i));
8132                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8133                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8134                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8135                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8136                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8137                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8138         }
8139
8140         return error;
8141 }
8142
8143 void
8144 intel_display_print_error_state(struct seq_file *m,
8145                                 struct drm_device *dev,
8146                                 struct intel_display_error_state *error)
8147 {
8148         int i;
8149
8150         for (i = 0; i < 2; i++) {
8151                 seq_printf(m, "Pipe [%d]:\n", i);
8152                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8153                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8154                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8155                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8156                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8157                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8158                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8159                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8160
8161                 seq_printf(m, "Plane [%d]:\n", i);
8162                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8163                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8164                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8165                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8166                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8167                 if (INTEL_INFO(dev)->gen >= 4) {
8168                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8169                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8170                 }
8171
8172                 seq_printf(m, "Cursor [%d]:\n", i);
8173                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8174                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8175                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8176         }
8177 }
8178 #endif